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SMCS332-SpW User Manual - SpaceWire

1. 110 LDL DDOSCHUPUON i035 E 110 L22 E EE 113 13 Simple Interprocessor Communication Protocol Specification e eese eee eres eene eene ene en ne tnue 114 E GE 114 13 2 Assumptions about the Environment eee esses eene eee enne entente nennen tren EKE NEEE ekai enne rennen 115 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 6 of 131 13 3 Service Specific liOni c eee b tremere ing eee eR HEY S ER eR eC EYRE UAE HERE EE CER CE ER RB eene ENE Prades 115 13 3 1 Transport of data between two nodes nennen enne nennen enne nennen 115 13 3 2 Execution of control commande 116 13 3 2 1 Simple Control Commandes 116 13 3 2 2 Complex Control Commandes 117 134 EP IUUD 118 134 1 Acknowledgements ceo ec P Dee iH eU REL EHE ER Fe EET REA EH ER FEE EY 118 13 4 2 Access to Command Signal Output Port 119 134 3 Safety Critical Commands ERENNERT 119 BAA Eeer 120 13 4 5 Shutdown Link Channel Operation Restart Link Channel Operation eee 121 13 4 6 Read of Link Interface Status Register 121 43 3 Encoding Format of Transactions E 122 I3 5 1 Headerand EOP Coding Leere cet eh peser i ter rco eO EDO ED EI epa rede 122 13 5
2. All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 85 of 131 10 2 Pin Assignment The table below lists the pins of the SMCS332SpW Pi Name Pin Number Name Pin Number Name Number PLLOUT CMDATAS VCC GND CMDATA9 CMDATA10 CMDATAII CMDATAI2 CMDATA13 CMDATA14 VCC GND 67 70 71 72 73 74 75 76 TT S 82 83 84 85 87 88 91 92 93 94 95 7 a ow f e we 9 a 70 Rese In OP WC OM oa M D SCH E Ls a ups Le mares f mm euparas pos L8 Lod WE 5 NE XE 2 9 1 Le E 164 GND VC CLK RESET DO VC GN 1 7 D 1 1 CDe Dew 1 1 1 1 D 1 HDATA30 GND CMDATA2I CMDATA22 CMDATA23 VCC GND CMDATA24 CMDATA25 VCC GND C C CC C N 2 2 2 2 2 2 2 2 2 3 CC CC D D M C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LA n 0 1 2 3 4 5 6 7 8 9 0 2 3 4 5 6 7 8 9 0 2 3 All Rights Reserved Copyright per DIN 34 ASTRIUM EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 86 of 131 SMCS332SpW User Manual Pin Name SMCSADRO 34 SMCSADRI SMCSADR2 S MCSADR3 SMCSIDO SMCSIDI SMCSID2 SMCSID3 V HD
3. B pes SpaceWire links E After a write access to this register the new value will be send as a time code character over the active All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW DocNo SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 44 of 131 5 SMCS332SpW Modes This section describes the organization of data passing through the HOCI and COMI ports on the SMCS332SpW the procedure used to arbitrate between two SMCS332SpW on the COMI port control by link the SMCS332SpW routing capability the time code interface and the version control register 5 1 HOCI Data Transfer Big Little endian selection of the HOCI is done using a special pin HOSTBIGE of the SMCS332SpW By connecting this pin to either Vcc or GND the HOCI is configured to be in little or big endian mode as follows When Signal HOSTBIGE 0 GND the HOCI data port is in little endian mode When Signal HOSTBIGE 1 Vcc the HOCI data port is in big endian mode Little endian mode selected 8 bit data port default after reset register byte 0 is connected with pin HDATA7 HDATAO 16 bit data port register byte 0 is connected with pin HDATA7 HDATAO register byte 1 is connected with pin HDATA15 HDATA8 32 bit data port register byte 0 is connected with pin HDATA7 HDATAO register byte 1 is connected with pin HDATAI5 HDATA8 register byt
4. EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 67 of 131 8 Electrical Specifications 8 1 Absolute Maximum Ratings Parameter Symbol Unit Supply Voltage Vcc 0 5 to 5 5 V 0 5 to 43 6 TO Voltage ese vec sos Operating Temperature Range Ambient 55 to 4125 Junction Temperature T TA 20 Storage Temperature Range 65 to 150 Thermal Resistance junction to ambient RThy 38 C W still air Stresses above those listed may cause permanent damage to the device 8 2 DC Electrical Characteristics SMCS332SpW can work with Vcc 5 V 0 5V and Vcc 3 3 V 0 3V Vout VCC Vout GND D see also the signal description in chapter 7 Although specified for TTL outputs all SMCS332SpW outputs are CMOS compatible and will drive to VCC and GND assuming no dc loads All Rights Reserved Copyright per DIN 34 ASTRIUM SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 68 of 131 8 3 Power consumption Max power consumption figures at Vcc 5 5V 55 C CLK 25MHz are Operation Mode Power consumption mA 115 not clocked SMCS in RESET SMCS in IDLE Maximum Max power consumption figures at Voc 3 6V 55 C CLK 15 MHz are Operation Mode Power consumption mA not clocked SMCS in R
5. EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 EADS Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 100 of 131 111 CMADR8 OUTZ 112 CMADR9 OUTZ 113 CMADR10 OUTZ 114 CMADR11 OUTZ 117 CMADR12 OUTZ 118 CMADR13 OUTZ 119 CMADR14 OUTZ 120 CMADR15 OUTZ 95 CMCSO OUT ger CMCS1 OUT 99 CMRD OUT 100 CMWR OUT gq Coco OUT nay CPUR OUT 18 HACK OUTZ WON HINTR OUT 178 LDO1L OUT 186 I DO2 OUT 190 T DO3 OUT 179 LSOL OUT 187 LSO2 OUT 191 LSO3 OUT 182 TEST OUT eg SESO OUT ao SES1 OUT 9o SES2 OUT 9 SES3 OUT 121 CMDATAO IO 122 CMDATA1 IO 123 CMDATA2 IO 126 CMDATA3 IO 127 CMDATA4 IO 128 CMDATA5 IO 131 CMDATA6 IO 132 CMDATA7 IO 133 CMDATA8 IO 136 CMDATA9 IO 137 CMDATA10 IO 138 CMDATA11 IO 139 CMDATA12 IO 140 CMDATA13 IO 141 CMDATA14 IO 144 CMDATAI5 IO 145 CMDATA16 IO 146 CMDATA17 IO 147 CMDATA18 IO 148 CMDATA19 IO 149 CMDATA20 IO 152 CMDATA21 IO All Rights Reserved Copyright per DIN 34 A EADS ASTRIUM EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 User Manual Updated 9 Sep 2006 Page 101 of 131 153 CMDATA22 154 C
6. esses eene enne nnne enne en tentent en ten terret nene entente 13 nnnL 14 3 1 Data Strobe SpaceWire signals ertt tdeo tes ide itae eee eet Peste tuit EENS UR Ud S 14 3 2 Character level flow control iiis oed er dees fer e UE I e e rS Pep etia 15 3 3 IPSI X 16 3 4 Errors on T m E 16 3 5 SPACE WIPE STALE ON start UD sssi inor i no e aS AE EEE EN AE E EEEE O EE EEEE REES 17 3 6 DANK CONNECTIONS sineresia e ES EES eae aE aE S 17 d Register AA 18 4 1 Register address mp iiis rtr PROHIBERI EG RO PR S MEER SEE EE PER CERN 18 4 1 1 SMCS332SpW status and control registers sess enne nnne enne 18 4 1 2 SMCS332SpW channel 1 status and control registers essssssesseseeeeeeeee eene 19 4 1 3 SMCS332SpW channel 2 status and control registers ssssesssseseeeeeeeeneneee eene 20 4 1 4 SMCS332SpW channel 3 status and control registers sese 21 4 1 5 SMCS332SpW GPIO control registers ssessseseseccsseceseneconssntsecnenoncesnesonsssanasenenesensenesssenseneronenenses 22 4 1 6 Time code control Tegisters eieiei Nee ENEE ebore REENEN 22 4 2 Register DeSCHIPEHON iiie rei E Ree cite rt dese aeu oae ists edes abe Lied eee sab eie be tee Mee eee redde SEEN Pape iN o 23 4 2 1 General SMCS Registers i ire cere teh a ih d P
7. 4 EADS ASTRIUM SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS_ASTD_UM_100 Issue 1 4 Updated 9 Sep 2006 Page 107 of 131 104 BC 1 INPUT 103 BC 1 INPUT 102 BC 1 INPUT 101 BC 1 INPUT 100 BC 1 INPUT 99 BC 1 INPUT 98 BC 1 INPUT 97 BC 1 INPUT 96 BC 1 INPUT 95 BC 1 INPUT 94 BC 1 INPUT 93 BC 1 INPUT 92 BC 1 INPUT 91 BC 1 INPUT 90 BC 1 INPUT 89 BC 1 INPUT 88 BC 1 INPUT 87 BC 1 INPUT 86 BC 1 INPUT 85 BC 1 INPUT 84 BC 1 INPUT 83 BC 1 INPUT 82 BC 1 INPUT 81 BC 1 INPUT 80 BC 1 INPUT 79 BC 1 INPUT 78 BC 1 INPUT 77 BC 1 INPUT 76 BC 1 INPUT 75 BC 1 INPUT 74 BC 1 INPUT 73 BC 1 INPUT 72 BC 1 INPUT 71 BC 1 INPUT 70 BC 1 INPUT 69 BC 1 INPUT 68 BC 1 INPUT 67 BC 1 INPUT 66 BC 1 INPUT 65 BC 1 INPUT 64 BC 1 INPUT 63 BC 1 INPUT 62 BC 1 INPUT 61 BC 1 INPUT 60 BC 1 INPUT 59 BC 1 INPUT 58 BC 1 INPUT 57 BC 1 INPUT 56 BC 1 INPUT H H DATA2 7 H H 8 0 H mom HDATA26 H H DATA2 6 H H 7 Ki H om HDATA25 HDATA25 76 omn HDATA24 HDATA24 75 Win HDATA23 H H DATA2 3 H H 72 H mom HDATA22 HDATA22 71 mom HDATA21 HDATA21 70 om HDATA20 HDATA20 69 mom HDATA19 HDATA19 68 mom HDATA18 HDATA18 67 omn HDATA17 HDATA17 64 om HDATA16 HDATA16 63 mom HDATA15 HDATA15 62 om HDATA14 HDATA14 ein mom HDATA13 HDATA13 en
8. Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 26 of 131 address 8 bit mode 0x06 16 bit mode 0x06 32 bit mode 0x04 ISR Byte 2 Em meri T REES einen channel 3 SpaceWire parity disconnect ESC or credit error For more information refer to register CH3 DSM STAR channel 3 SpaceWire status register channel 3 error For more information over this error flag refer to register CH3_ ESRI and CH3 EXR2 channel 3 data from the communication memory are read That means channel3 transmit COMI address generator reach the value of the end address register CH3 TX EAR channel3 the received data from channel 3 is transmitted in the communication memory That means channel3 receive COMI address generator reach the value of the end address register CH3 RX EAR The following interrupts are stored in byte 2 of the ISR address 8 bit mode 0x07 16 bit mode 0x06 32 bit mode 0x04 ISR Byte 3 channel 3 the EOP EEP character was received For more information refer to register CH3 STAR bit 4 and 5 channel 3 reset channel 3 command received only if protocol mode enabled channel 3 transmit fifo is empty set after reset ES EN To read the ISR when the HOCI is in 8 16 mode the following steps are required All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH
9. ni Decne lower byte of the end address Byte 1 at address 0x23 only in 8 bit mode of the HOCI data port l upper byte of the end address 4 2 2 17 Channel 1 Transmit Current Address Register CH1 TX CAR address 0x24 0x25 data width 16 bit D15 0 access mode read only reset value 0x0000 The CH1 TX CAR register shows the current address of the address generator Byte 0 at address 0x24 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 39 of 131 m pS lower byte of the current address Byte 1 at address 0x25 only in 8 bit mode of the HOCI data port E upper byte of the current address 4 2 2 18 Channel 1 Transmit FIFO CH1 TX FIFO address 0x26 data width 8 16 32 bit D31 0 access mode write only reset value n a Beside the communication memory the host processor can send data over the transmit FIFO interface The FIFO data width is equal to the HOCI data port width The FIFO has a size of 32 bytes The host processor can control the data transmission with bits 6 and 7 of the interrupt status register ISR or with the status bits 0 and 1 of the channel 1 status register CH1 STAR At the end of the packet the host processor has to send an EOP character with register CHI TX EOPB 4 2 2 19 Channel 1 Tran
10. SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 10 of 131 2 Interfaces The SMCS332SpW consists of the following blocks See block diagram of the SMCS332SpW in Figure 1 3 bidirectional SpaceWire AD1 channels all comprising the DS link SpaceWire cell receive and transmit sections each including FIFOs and a protocol processing unit PPU Each channel allows full duplex communication up to 200 Mbit s in each direction With protocol command execution a higher level of communication is supported Link disconnect detection and parity check at character level are performed A checksum generation for a check at packet level can be enabled The transmit rate is selectable between 1 25 and 200 Mbit s The start up transmit rate is 10 Mbit s For special applications the data transmit rate can be programmed to values even below 10 Mbit s the lowest possible SpaceWire transmit rate is 1 25 Mbit s the next values are 2 5 and 5 Mbit s Communication Memory Interface COMI performs autonomous accesses to the communication memory of the module to store data received via the links or to read data to be transmitted via the links The COMI consists of individual memory address generators for the receive and transmit direction of every SpaceWire link channel The access to the memory is controlled via an arbitration unit providing a fair arbitration scheme Two SMCS332SpW can share one DPRAM
11. 9p sPACEWIRE LINK 2 CPUR e SES ch sPACEWIRE LINK 5 TIME CODE SYNC ae CNICSI Li OE A cMWR Lech WEA WEB CMDATA 4 DATA A DATAB CMADR t ADDR A ADDR B vec D ual Port cam LA Communication BANK 0 coco Lk 3p rac Memory BANK 1 gt 7 coc Wi GND PLLOUT ___y This section describes the pins of the SMCS Groups of pins represent busses where the highest number is the MSB O Output I Input Z High Impedance O Z if using a configuration with two SMCS332SpWs these signals can directly be connected together WIROR Type Function max output load pF current mA HSEL Select host interface host interface read strobe active low signal SMCS register address lines This address lines will be used to access address the SMCS registers HDATA 31 0 I O Z SMCS data HACK O Z host acknowledge SMCS deasserts this output to add wait 3 states to a SMCS access After SMCS is ready this output will be asserted 50 50 HINTR o host interrupt request line SMCSADR 3 0 I SMCS Address The binary value of this lines will be compared with the value of the SMCS ID lines SMCSID 3 0 I SMCS ID lines offers possibility to use sixteen SMCS within one HSEL HOSTBIGE I O host I F Little Endian All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM
12. HDATA inout bit vector 0 to 31 GND linkage bit vector 0 to 28 VDD linkage bit vector 0 to 25 NC linkage bit vector 0 to 1 use STD 1149 1 1990 all attribute PIN MAP of SMCS entity is PHYSICAL PIN MAP constant PGA PACKAGE PIN MAP STRING OPP Package BOOTLINK 32 amp BYPPLL 168 amp CAM 92 amp CLK 4 amp CLK10 6 amp COCI 93 amp HADR 22 23 24 25 26 27 28 29 amp HOSTBIGE 7 amp HRD 16 amp HSEL 15 amp HWR 17 amp LDI1 176 LDI2 180 LDI3 188 f m m m LSI1 177 All Rights Reserved Copyright per DIN 34 A EADS ASTRIUM SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 92 of 131 LSI2 181 amp LSI3 189 amp RESET 5 amp SMCSADRO 33 SMCSADR1 34 SMCSADR2 35 f m m m SMCSADR3 36 SMCSIDO 37 amp SMCSID1 38 amp amp SMCSID2 39 SMCSID3 40 amp TIME CODE SYNC 192 amp VCC 3VOLT 169 amp TCK 8 amp TDI 10 amp TDO 12 amp TMS 9 amp TRST 11 amp CMADR 101 102 103 104 105 108 109 110 111 112 113 114 117 118 119 120 amp CMCS0 95 E CMCS1 96 amp CMRD 99 amp CMWR 100 amp COCO 94 amp CPUR 87 amp HACK 18 amp HINTR 19 EDODL 3178 LDO2 186 LDO3 190 LnS01 179 LSO2 187 f
13. 0x3FFF gt CMCSO is active Address 0x4000 OxFFFF gt CMCSI is active 4 2 1 7 COMI Arbitration Control Register COMI ACR address OxOE data width 4 bit D3 0 access mode read write reset value 0x08 Signal COCI is an input pin that requests access from the other SMCS332SpW to the communication memory bus When COCI is asserted the SMCS332SpW COMI interface completes the current access places the interface in a high impedance state and then deasserts the output signal COCO to indicate to the requesting SMCS332SpW that it is no longer driving the COMI bus After COMI ACR 1 CLK cycles and when the SMCS332SpW COMI needs the bus for further access to the communication memory the SMCS332SpW asserts the COCO pin connected with the COCI pin of the other SMCS332SpW COMI ACR wait time between two accesses All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 28 of 131 COMI ACR values from 0x00 disable communication memory interface 0x01 is not allowed to OxOF max CLK cycles between two accesses See also the description for pins CAM COCI COCO and chapter 5 3 COMI arbitration 4 2 1 8 PRCI Register PRCIR address OxOF data width 5 bit D4 0 access mode read write reset value 0x00 Gives the status of the protocol command interface
14. ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 27 of 131 1 read always all bytes 2 read first byte 0 last byte 3 3 when Byte 3 is read the signal HINTR will be deactivated for a minimum of two CLK cycles and all bits in the ISR will be cleared Note that the ISR will be latched when reading Byte 0 Only the interrupts flagged at that time will be reset when reading Byte 3 This makes sure that no interrupts will be lost that happen to be raised in the time between reading Byte 0 and Byte 3 4 2 1 5 Interrupt Mask Register IMR address 0x08 0x0B data width 32 bit D31 0 access mode read write reset value 0x00000000 All interrupts are masked after reset A 1 written to the IMR enables the corresponding interrupt source in register ISR to activate the interrupt signal HINTR 4 2 1 6 COMI Chip Select0 Boundary Register COMI CSOR address 0x0C data width 8 bit D7 0 access mode read write reset value OxFF The communication memory address space is divided into two banks Each bank has a separate memory select pin CMCSO0 and CMCS1 The upper COMI address signals CMADRIS 8 are compared with the value of COMI CSOR Bank 0 starts at address 0x0000 until COMI CSOR 256 255 IF 0x0000 lt CMADR lt COMI CSOR 0x100 OXFF THEN CMCSO is active ELSE CMCS1 is active Example COMI CSOR 0x3F Address 0x0000
15. If set automatically restart of the link after an error disconnect parity ESC or credit error 7 3 always 0 reserved 4 2 2 3 Channel 1 Link SpaceWire Status Register CH1_DSM_STAR address 0x12 data width 8 bit D6 0 access mode read only reset value 0x00 The status register is readable and bits D1 D2 D4 D5 and D6 are reset by reading the register m pe o m o s redi eror tne tate received vo muci nommat characters or FCT comot ciance Differences between the SMCS332 and the SMCS332SpW for the bits D0 D3 and D4 When D0 D3 and D4 are set the SpaceWire link is was in the Run state See ADI On an Space Wire link error 1 e disconnect parity these bits will be cleared However if the running link is stopped the bits DO D3 and D4 are not reset Therefore on a new start of the link these bits do not reflect the current situation of the link For this reason it 1s necessary to read the register before the start of the link Then only bit 4 shall be checked whether the link is in the Run state or not All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 31 of 131 4 2 2 4 Channel 1 SpaceWire Test Register CHL DSM TSTR address 0x13 data width 4 bit D3 0 access mode read write reset value 0x0 The test register
16. X amp 106 BC 1 5 control 0 E HOCI Data Output Enable 105 BC 1 HDATA 27 output3 X 106 0 Z amp 104 BC 1 HDATA 27 input X amp 103 BC 1 S control 0 E HOCI Data Output Enable 102 BC 1 HDATA 26 output3 X 103 0 Z amp 101 BC 1 HDATA 26 input X amp 100 BC 1 S control 0 E HOCI Data Output Enable 99 BC 1 HDATA 25 output3 X 100 0 Z amp 98 BC 1 HDATA 25 input X amp 97 BC 1 e control 0 E HOCI Data Output Enable 96 BC 1 HDATA 24 output3 X 97 0 Z E 95 BC 1 HDATA 24 input X amp 94 BC 1 P control 0 amp HOCI Data Output Enable 93 BC 1 HDATA 23 output3 X 94 0 Z E 92 BC 1 HDATA 23 input X amp w 91 BC 1 j control 0 amp HOCI Data Output Enable 90 BC 1 HDATA 22 output3 X 91 0 A amp 89 BC 1 HDATA 22 input X amp 88 BC 1 e control 0 E HOCI Data Output Enable 87 BC 1 HDATA 21 output3 X 88 0 Z amp 86 BC 1 HDATA 21 input X amp 85 BC 1 i control 0 amp HOCI Data Output Enable 84 BC 1 HDATA 20 output3 X 85 0 Z amp 83 BC 1 HDATA 20 input X amp 82 BC 1 i control 0 amp HOCI Data Output Enable 81 BC 1 HDATA 19 output3 X 82 0 Z E All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW DocNo SMCS ASTD
17. low and HSEL low and SMCSADR SMCSID Signal HACK disable when HRD high or HSEL high or SMCSADR SMCSID All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW DocNo SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 77 of 131 9 5 COMI Read ie ae EE ee E terca CRCH terew CMCSO CMCS1 t t CRCA CRCH lonew CMRD MWR terca torca Lann CMADR Addr Valid Adar Valid Addr Valid terns tenon Data Valid omoara Hl Vcc7 5V 0 5V CMCS0 CMCS1 and CMRD low and CMADR valid after CLK high CMCS0 CMCS1 or CMRD high after CLK high CMCS0 CMCS1 CMRD CMADR pulse width ae CMDATA setup before CMCS0 or CMCS1 or CMRD high or new tcrps 4 address on CMADR CMDATA hold after CMCS0 or CMCS1 or CMRD high or new tcron address on CMADR Vec 3 3 V 0 3V CMCS0 CMCS1 and CMRD low and CMADR valid after CLK high CMCS0 CMCS1 or CMRD high after CLK high CMCS0 CMCS1 CMRD CMADR pulse width ia cd CMDATA setup before CMCS0 or CMCS1 or CMRD high ornew address on CMADR CMDATA hold after CMCS0 or CMCSI or CMRD high or new tcron address on CMADR All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated
18. m m m m m m LSO3 191 SESO 88 SES1 89 SES2 90 P m m m SES3 91 TEST 182 amp CMDATA 121 122 123 126 127 128 131 132 133 136 137 138 139 140 141 amp 144 145 146 147 148 149 152 153 154 157 158 159 162 163 164 amp 165 166 amp HDATA 43 44 45 46 47 48 49 52 53 54 55 56 59 60 61 62 63 64 67 68 69 amp 70 71 72 75 76 77 80 81 82 85 86 amp GND 2 14 21 31 42 51 58 66 74 79 84 98 107 116 125 130 135 143 151 156 amp 161 167 170 171 173 174 193 194 196 amp VDD 3 13 20 30 41 50 57 65 73 78 83 97 106 115 124 129 134 142 150 amp 155 160 172 183 184 185 195 amp INC LITS y All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 EAD el SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 93 of 131 attribute TAP SCAN IN of TDI signal is true attribute TAP SCAN MODE of TMS attribute TAP SCAN OUT of TDO attribute TAP SCAN RESET of TRST unconfirmed TCK Fmax attribute TAP SCAN CLOCK of TCK attribute INSTRUCTION LENGTH of SMCS attribute INSTRUCTION OPCODE of SMCS Signal is signal is true signal is true signal is true 10 0e6 BOTH entity is 3 entity is BYPASS 111 110 101 100 amp EXTEST 000 amp SAMPLE 001 amp IDCODE 010 amp HIGHZ 011 attribute INSTRUCTION CAPTURE of SMCS 101 attri
19. 1 1990 kkkkkxkxkkxkkkkkkkkkkkkkkkkkkkkkkkkkkx k PIN NR PIN NAME PIN TYPE PIN FAMILY All Rights Reserved Copyright per DIN 34 4 EADS ASTR IUM SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 99 of 131 kkkkkxkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkx k 32 BOOTLINK 168 BYPPLL 92 CAM 4 CLK 6 CLK10 93 COCI 22 HADRO 23 HADR1 24 HADR2 25 HADR3 26 HADR4 27 HADR5 28 HADR6 29 HADR7 7 HOSTBIGE 16 HRD 15 HSEL 17 HWR 176 LDII 180 IDI2 188 IDI3 177 STi 181 ILSI2 189 ILSI3 b RESET 33 SMCSA 34 SMCSA 35 SMCSA 36 SMCSA 37 SMCSI 38 SMCSI 39 SMCSI 40 SMCSI 169 VCC _3VOLT n DRO DR1 DR2 DR3 DO D1 D2 D3 192 TIME C S B TCK 10 TDI 12 TDO 9 TMS 11 TRST 101 CMADR o 102 CMADR1 103 CMADR2 104 CMADR3 105 CMADR4 108 CMADR5 109 CMADR6 110 CMADR7 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN TCK DI DO I4 We RST O OO oO Oo Oo O00 dH Hd d All Rights Reserved Copyright per DIN 34
20. 2 Control Word Coding Specification tesa er oce ier dcr Ese vere ree Tae 122 13 5 3 Link Interface Status Register Encodmg enne ener 124 13 5 4 Data Transfer Type Transactions eut 125 13 5 5 Read Link Interface Status Register Transaction ssesssssssesseeeeeneeenenerenn ener 126 13 5 6 Enable Command Execution Transaction esee enne eene nennen trennen enne nennnn 127 13 5 7 Critical Simple Command Execution Transaction sees 128 ER E 129 14 Differences between the SMCS332SpW and the old SMCS332 eee eee esee eese entes etat n ense tn tuse ta tu nenn 130 14 1 Summary of changed modified added registers or register btte eere 130 BE E EE 131 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 DS um User Manual Updated 9 Sep 2006 Page 7 of 131 1 Scope and Objectives This document describes in detail the new SMCS332SpW The SMCS332SpW provides an interface between three SpaceWire links according to the SpaceWire Standard ECSS E 50 12A and a data processing node like a CPU 11 List of applicable documents Number Document SpaceWire Links nodes ADI ECSS E 50 12A routers and network 24 January 2003 SMCS332SpW Requirements Specification AD2 SMCS332SpW_RS 01 1 2 Reference Documents The documents below have been used as support for establishin
21. 4 1 Selecting remote mode The external signal BOOTLINK pin 32 must be tied to 1 This will set the SMCS332SpW to remote mode It is not possible to switch the SMCS332SpW into remote mode by software 5 4 2 Determination of the control link After the reset signal is released the SMCS332SpW will wait for NULL characters on the three links It will not start a link until it has received NULL characters on this link Only then the SMCS332SpW will send NULL characters itself After the links are active the SMCS332SpW scans these links for data characters The link on which the SMCS332SpW receives data first is then identified and determined as control link This means that each ofthe 3 SMCS332SpW links can function as control link Which ofthe links is used as control link is only determined by the first appearance of data on a link directly after it is started That link then operates as control link until the SMCS332SpW is reset by the reset signal RESET 5 4 3 Protocol and Commands The protocol ofthe SMCS332SpW in remote mode provides two commands Read and Write A read command requires at least one byte and a write command requires at least two bytes Each command packet must be terminated by an EOP character Data received on the control link is interpreted according to this simple protocol Bit 7 the MSB ofthe first byte received on the control link determines whether the command is a Read bit 7 1 or a Write bit 7 0 command Al
22. 9 Sep 2006 Page 78 of 131 9 6 COMI Write ax J LI LY UJ LI CJ towca Lach Lage CMCSO CMCS1 CMRD CWCA CWCH towew MWR Leien o d 4 c Lac WK CMADR Addr Valid Adar Valid _ Towne Las La CMDATA ipaa vai L Data Valid I Vcc 7 5V 0 5V Description Symbol CMCS0 CMCS1 and CMWR low and CMADR valid after CLK MCS0 CMCS1 or CMWR high after CLK high e E MCS0 CMCS1 CMWR pulse width tic 1 MDATA valid after CLK high enn J CMDATA valid before CMCS0 or CMCS1 or CMWR high Hom 27 CMDATA hold after CMCS0 or CMCS1 or CMWR high Vec 73 3 V 0 3V Description Symbol CMCS0 CMCS1 and CMWR low and CMADR valid after CLK TII high CMCS0 CMCS1 or CMWR high after CLK high CMCS0 CMCS1 CMWR pulse width CMDATA valid after CLK high PR NEN ET CMDATA valid before CMCS0 or CMCS1 or CMWR high towns 54 CMDATA hold after CMCS0 or CMCS1 or CMWR high All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 79 of 131 9 7 COMI Arbitration Cap La e gt eg gt CMCSO f tean tone WK Wi t Lag CAD ui ten D tow E KS d ke g
23. BC 1 INPUT 201 BC 1 INPUT 200 BC 1 INPUT 199 BC 1 INPUT 198 BC 1 INPUT 197 BC 1 INPUT 196 BC 1 INPUT 195 BC 1 INPUT 194 BC 1 INPUT 193 BC 1 INPUT 192 BC 1 INPUT 191 BC 1 INPUT 190 BC 1 INPUT 189 BC 1 INPUT 188 BC 1 INPUT 187 BC 1 INPUT 186 BC 1 INPUT 185 BC 1 INPUT 184 BC 1 INPUT 183 BC 1 INPUT 182 BC 1 INPUT 181 BC 1 INPUT 180 BC 1 INPUT 179 BC 1 INPUT 178 BC 1 INPUT 177 BC 1 INPUT 176 BC 1 INPUT 175 BC 1 INPUT 174 BC 1 INPUT 173 BC 1 INPUT 172 BC 1 INPUT 171 BC 1 INPUT 170 BC 1 INPUT 169 BC 1 INPUT 168 BC 1 INPUT 167 BC 1 INPUT 166 BC 1 INPUT 165 BC 1 INPUT 164 BC 1 INPUT 163 BC 1 INPUT 162 BC 1 INPUT 161 BC 1 INPUT 160 BC 1 INPUT 159 BC 1 INPUT 158 BC 1 INPUT 157 BC 1 INPUT 156 BC 1 INPUT 155 BC 1 INPUT 154 BC 1 INPUT CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM CM DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT l A27 l A26 l A26 l A25 l A25 l A24 l A24 l A23 l A23 l A22 l A22 l A21 l A
24. D4 shall be checked whether the link is in the Run state or not 0x13 CHx DSM TSTR D4 always 0 reserved D4 link output mute 0x33 D5 always 0 reserved D5 send EEP instead of EOP 0x53 0x18 CHx CNTRL1 D5 always 0 reserved D5 header field control bit 0x38 0x58 Ox1F CHx_COMICFG D2 0 send EOPI token at D2 0 send EOP token at 0x3F the end of the packet the end of the packet send EOP2 token at if D3 0 Ox5F the end of the packet T send EOP token at D3 always 0 reserved the end of the packet if D3 0 D3 0 send EOP token at All Rights Reserved Copyright per DIN 34 SMCS ASTD UM 100 EADS Astrium GmbH ASE2 E SMCS332SpW ae SMCS_ASTD_UM_1 00 ASTRIUM User Manual Updated 9 Sep 2006 Page 131 of 131 Address Register Description SMCS332 Description SMCS332SpW the end of the packet send NO EOP token at the end of the packet 0x27 CHx TX EOPB DO send an EOP token DO send an EOP token 0x47 D1 send an EOP2 token D1 send an EOP token 0x67 0x2F CHx STAR D4 EOP received D4 EOP received Ox4F D5 EOP2 received D5 EEP received Ox6F 0x78 TIME CNTRL reserved time code control register 0x79 TIME CODE reserved time code value register 14 2 Pin Modifications Pin number Description SMCS332 Description SMCS332SpW 1 VCC PLLOUT 3 GND VCC 167 NC GND 168 NC GND 169 N
25. EOP control character at the end of the packet when bit 3 is not set see RD1 send EOP control character at the end of the packet send NO EOP control character at the end of the packet the COMI data port operates in receive direction with 8 bit after reset each access writes 8 bit to the memory bit 31 8 set to 0 see also bit 7 the COMI data port works with 16 bit bit 31 16 set to 0 the COMI data port works with 32 bit for little big endian access of the COMI data port see bit 2 of register SICR no stop because of a received EOP EEP if channel 1 receive the EOP EEP the COMI receive address generator stops no further data will be written in the communication memory Only one packet will be received If channel 1 receive the EOP EEP the COMI receive address generator works until CHI RS EAR current COMI address More than one packet will be received expand sign bit only in 8 16 bit mode of the receive channel 1 bit 5 4 0X Little endian 0 in 8 bit mode set data bits 31 8 of the COMI to 0 in 16 bit mode set data bits 31 16 to 0 1 in 8 bit mode if MSB of the received data 1 set data bits 31 8 of the COMI to 1 if MSB of the received data 0 set data bits 31 8 of the COMI to 0 in 16 bit mode if MSB of the received data 1 set data bits 31 16 of the COMI to 1 if MSB of the received data 0 set data bits 31 16 of the COMI to 0 Big endian 0 in 8 bit mode se
26. Ox1C data width 6 bit D5 0 access mode read write reset value 0x00 The CH1 ESRI and CH1 ESR2 registers give detailed information about the source of the channel 1 error interrupt bit 1 byte 0 of the interrupt status register ISR The channel 1 error source register 1 is readable and the bits are reset only by writing 1 thus ensuring status never gets missed by software in protocol mode received acknowledge packet has a wrong control byte in protocol mode received acknowledge packet has a wrong destination byte not equal with register CHI ADDR in protocol mode received acknowledge packet has a wrong transaction ID All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 36 of 131 Bp received acknowledge packet has a wrong checksum only when generate checksum enabled bit 4 of register CHI CNTRL 1 in transparent mode checksum error if checksum enabled in transparent mode wrong route destination byte if routing enabled destination byte not equal with CH1 ADDR or CH2 RT ADDR or CH3 RT ADDR always 0 reserved 4 2 2 13 Channel 1 Error Source Register 2 CH1_ESR2 address 0x1D data width 7 bit D6 0 access mode read write reset value 0x00 Only in protocol mode The CH1_ESR2 register give detailed information about t
27. RX EAR last address defines an area in the communication memory The receive address generator stops when bit 6 0 in register CHI COMICFG EOP EEP was recevied or bit 6 1 in register CHI COMICFG current address CHI RX EAR and the last data was written Byte 0 at address 0x2A Bit Description lower byte of the end address Byte 1 at address 0x2B only in 8 bit mode of the HOCI data port B Dein 0 upper byte of the end address 4 2 2 22 Channel 1 Receive Current Address Register CH1 RX CAR address 0x2C 0x2D data width 16 bit D15 0 access mode read only reset value 0x0000 The CH1 RX CAR register shows the current address of the receive address generator The current address is the next free address Byte 0 at address 0x2C i pea lower byte of the current address All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 41 of 131 Byte 1 at address 0x2D only in 8 bit mode of the HOCI data port Bit Description upper byte of the current address 4 2 2 3 Channel 1 Receive FIFO CH1 RX FIFO address Ox2E data width 8 16 32 bit D31 0 access mode read only reset value OxXXXXXXXX Beside the communication memory interface the host processor can read data from the receive FIFO interface The FIFO data wi
28. UM 100 EADS Issue 14 ASTRIUM User Manual Updated 9 Sep 2006 Page 97 of 131 80 BC 1 HDATA 19 input X amp 79 BC 1 5 control 0 amp HOCI Data Output Enable 78 BC 1 HDATA 18 output3 X 79 0 Z amp 77 BC 1 HDATA 18 input X amp 76 BC 1 i control 0 amp HOCI Data Output Enable 75 BC_1 HDATA 17 output3 X 76 0 Z E 74 BC 1 HDATA 17 input X amp 73 BC 1 i control 0 amp HOCI Data Output Enable 72 BC 1 HDATA 16 output3 X 73 0 Z amp 71 BC 1 HDATA 16 input X E 70 BC 1 S control 0 amp HOCI Data Output Enable 69 BC 1 HDATA 15 output3 X 70 0 Z E 68 BC 1 HDATA 15 input X amp 67 BC 1 e control 0 amp HOCI Data Output Enable 66 BC 1 HDATA 14 output3 X 67 0 Z amp 65 BC 1 HDATA 14 input X amp 64 BC 1 control 0 amp HOCI Data Output Enable 63 BC 1 HDATA 13 output3 X 64 0 Z amp 62 BC 1 HDATA 13 input X amp H et BC ip r control 0 amp HOCI Data Output Enable 60 BC_1 HDATA 12 output3 X 61 0 Z amp 59 BC 1 HDATA 12 input X amp 58 BC 1 control 0 amp HOCI Data Output Enable 57 BC 1 HDATA 11 output3 X 58 0 Z E 56 BC 1 HDATA 11 input X amp 55 BC 1 n control 0 amp HOCI Data Output Enable 54 BC 1 HDATA 10 outp
29. User Manual Updated 9 Sep 2006 Page 65 of 131 Signal Name Type Function max output load pF current mA host I F Big Endian BOOTLINK I control by host control by link CMCS 1 0 O Z Communication memory select lines These pins are 25 asserted as chip selects for the corresponding banks of the communication memory CMRD O Z Communication memory read strobe This pin is asserted 25 when the SMCS reads data from memory CMWR O Z Communication memory write strobe This pin 1s asserted 25 when the SMCS writes to data memory CMADR 15 0 O Z Communication memory address The SMCS outputs an 6 address on these pins CMDATA 3 1 0 Communication memory data The SMCS inputs and 3 outputs data from and to com memory on these pins COCI Communication interface occupied input signal COCO Ex Communication interface occupied output signal p Communication interface arbitration master input signal see section 4 3 1 master 0 slave CPUR EX CPU Reset Signal can be used as user defined flag SES 3 0 au Specific External Signals can be used as user defined flags LD ID I Link Data Input channel 1 LSI EN Link Strobe Input channel 1 bo LDOI o Link Data Output channel 1 LSO1 o Link Strobe Output channel 1 LDI2 Link Data Input channel 2 EEN ae LSI2 Link Strobe Input channel 2 WEED J LDO2 o Link Data Output channel 2 LSO2 ES Link Strobe Output channel 2 LDI3 Link Dat
30. amp 133 BC 1 CMADR 2 output3 X 147 0 Z amp 132 BC 1 CMADR 1 output3 X 147 0 Z amp 131 BC 1 CMADR 0 output3 X 147 0 Z amp 130 BC 1 CMWR output2 X amp All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW DocNo SMCS ASTD UM 100 EADS Issue 14 ASTRIUM User Manual Updated 9 Sep 2006 Page 96 of 131 129 BC 1 CMRD output2 X amp 128 BC 1 CMCS1 output2 X amp 127 BC 1 CMCSO output2 X amp 126 BC 1 COCO output2 X amp internal tristate t 125 BC 1 COCI input X amp 124 BC 1 CAM input X amp 123 BC 1 SES3 output2 X amp 122 BC 1 SES2 output2 X amp 121 BC 1 SES1 output2 X amp 120 BC 1 SESO output2 X amp 119 BC 1 CPUR output2 X amp 118 BC 1 P control 0 E HOCI Data Output Enable 117 BC 1 HDATA 31 output3 X 118 0 Z amp 116 BC 1 HDATA 31 input X amp 115 BC d control 0 amp HOCI Data Output Enable 114 BC 1 HDATA 30 output3 X 115 0 Z E 113 BC 1 HDATA 30 input X amp 112 BC 1 S control 0 E HOCI Data Output Enable 111 BC 1 HDATA 29 output3 X 112 0 Z E 110 BC 1 HDATA 29 input X amp H 109 BC 1 control 0 E HOCI Data Output Enable 108 BC 1 HDATA 28 output3 X 109 0 Z amp 107 BC 1 HDATA 28 input
31. ene Ep ERR rape cnini ElNegEE gea 67 6 2 DC Electricat CharacteristiCS RRRRRTm 67 8 3 ae me ii eie EE E EEA EER E ESE N 68 6 4 PEE FULD CE lavender 69 6 5 Power and Ground Guidelines uicti eet t re siae EEN pe ER eo EE EE Cea Ee ave e eI eek EE 69 9 Timing Parameter 70 9 1 Clock Signals ir itte ote te beer esed evt dete ree teet tero debe erteilen 70 9 2 Didi V 72 9 3 HOS REOL uo EE ONERE IRURE cane EID EE ced eene 73 9 4 LAU rem OA 75 95 3COMEPROUd rea E E e nihi E E A E aedes 77 KENE e EE 78 9 7 GE B 1271171710 PRICE Ee Eeer ee ENNEN Nee 79 9 6 CPUR EE 80 9 9 ER eege EE H 61 9 10 Lest Port STAG i ro ERE eege deed 62 HB CTDUcBIrir 84 Z IT HEN Te er PB TARDE ZECH 64 HUP MEE VU quud 65 11 Additional Informations 87 ILI Frequently Asked Ouestions 5c creen e RR ER Ee Pe EN NR le ERN ee e ARN e Ee teats PARAR e Ree EN Ee e ERR MEE EARS EN 67 11 2 BSDL File for the SMCS332SpW enne ener nnne trennen tenere enne nren nr en eren erret eene 90 12 Handling RO AA I
32. field control bit For more flexibility for packets routed via a SpaceWire Router the SMCS332SpW has a header field control bit D5 in the register CHx CNTRLI Description If bit 5 in the register CHx CNTRL I is set the SMCS332SpW will use the first byte of an incoming data to be transmitted from COMI or HOCI as number of bytes which are excluded from checksum if checksum is enabled The allowed range is from 1 to 15 The number byte and the associated header byte s defined as header field The header field size is minimum 2 and maximum 16 bytes It is always accessed in blocks of 4 bytes the first 4 8 12 or 16 incoming bytes All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 52 of 131 This means that data has to start at the next modulo 4 bytes The rest of a 4 byte block which is not covered by the number of header bytes will not be transmitted Examplel CHx CNTRLI 0x20 The header field consist of a first byte which contains the number of header bytes value 4 and 4 header bytes give in total 5 bytes The first 8 bytes comprise the header field However the number byte and the last 3 bytes ofthe 8 byte in total will be NOT transmitted byte0 4 number of following header bytes NOT transmitted byte 1 first header byte byte 2 second header byte byte 3 third header
33. four links 32 nodes each with 8 links etc the interconnect network between the nodes is a flat network no hierarchical addressing is required and supported Especially header deletion is not supported since it is not required in such relatively small networks multicast and broadcast messages are not supported only simple destination fields in ECSS E 50 12A terminology are provided the three previous addressing characteristics allow to reduce the size of the destination field of the packet header to one byte the target system is physically small enough to fit into one box the interconnect capabilities covers connections between elements on a PC board and between boards in a box via a backplane or equivalent interconnect system Interconnect between boxes is not covered This has one major implication it is assumed that the electrical environment within boxes is clean and no error is introduced on the links e g by spikes noise or HF interference Experience with bus systems has shown that indeed data transfer can be regarded as reliable and parity checking is sufficient to detect possible very rare transmission failures In this case error recovery must be handled by some kind of control program It is assumed that a SW kernel is running on the nodes of the system providing resources for the execution for the major part of the transaction level protocol functions From the transaction level protocol function
34. if CHx COMICFG bit 7 1 and Byte3 Bit 7 0 COMI data port is set to 8 Bit width datalines 31 24 23 16 15 8 7 0 00 00 00 ByteO if CHx COMICFG bit 7 0 00 00 00 Bytel 00 00 00 Byte2 00 00 00 Byte3 FF FF FF ByteO if CHx COMICFG bit 7 1 and ByteO Bit 7 1 00 00 00 Bytel if CHx COMICFG bit 7 1 and Bytel Bit 7 0 BIG endian COMI data port is set to 32 Bit width datalines 31 24 23 16 15 8 7 0 ByteO Bytel Byte2 Byte3 COMI data port is set to 16 Bit width datalines 31 24 23 16 15 8 7 0 ByteO Bytel 00 00 if CHx COMICFG bit 7 0 Byte2 Byte3 00 00 ByteO Bytel FF FF if CHx COMICFG bit 7 1 and Bytel Bit 7 1 Byte2 Byte3 00 00 if CHx COMICFG bit 7 1 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 EAD T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 Doux User Manual Updated 9 Sep 2006 Page 89 of 131 and Byte3 Bit 7 0 COMI data port is set to 8 Bit width datalines 31 24 23 16 15 8 7 0 ByteO 00 00 00 if CHx COMICFG bit 7 0 Bytel 00 00 00 Byte2 00 00 00 Byte3 00 00 00 ByteO 00 00 00 if CHx COMICFG bit 7 and ByteO Bit 7 0 Bytel FF FF FF if CHx COMICFG bit 7 and Bytel Bit 7 1 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 EADS User Manual Updated 9 Sep 2006 Page 90 of 131 11 2 BSDL File for the SMCS332SpW Below is the BSDL file required for u
35. is writeable only when bit 7 of register CHI DS5M MODR is set Once this bit has been set it remains so even when test mode is exited enables internal feedback of transmit link to receive link data will also be transmitted externally disable disconnect detection link input mute insert wrong parity If set inverts the transmitted parity The wrong parity bit is used to invert the parity generation bit and so invoke a parity error at the other end of the link The other end of the link detects an error and stops the transmission disconnect link output mute 5 send EEP character instead of an EOP character always 0 reserved The input mute bit holds the D and S inputs on the reset value 0 The output mute bit holds the D and S outputs on the reset value 0 4 2 2 5 X Channel 1 Address Register CH1 ADDR address 0x14 data width 8 bit D7 0 access mode read write reset value 0x00 In protocol mode with enabled check destination bit The SpaceWire cell compares the first byte destination address byte of the received data packet with the value of register CHI ADDR If it does not match an error condition occurs see CH1_ESR1 In wormhole routing mode The SpaceWire cell compares the first byte destination address byte of the received data packet with the value of register CHI ADDR or with the value of register CHx RT ADDR from the other two SpaceWire channels If it does not match an error conditio
36. on the link The link interface which sends a response packet on the link The response packet may be a simple acknowledge or a data packet Data storage part of a node s memory All Rights Reserved Copyright per DIN 34 ASTRIUM SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No Issue 1 4 Updated 9 Sep 2006 Page 130 of 131 14 Differences between the SMCS332SpW and the old SMCS332 14 1 Summary of changed modified added registers or register bits Address Register Description SMCS332 Description SMCS332Spw 0x04 Interrupt status ISR Byte0 DO ISR Bvte DO register ISR channel 1 IEEE1355 parity or channel 1 SpaceWire parity 0x05 f 3 disconnect error disconnect ESC or credit error NS ISR Bytel D2 ISR Bytel D2 0x07 channel 2 IEEE1355 parity or channel 2 SpaceWire parity disconnect error disconnect ESC or credit error ISR Byte2 D4 ISR Byte2 D4 channel 3 IEEE1355 parity or channel 3 SpaceWire parity disconnect error disconnect ESC or credit error ISR Byte3 D6 ISR Byte3 D6 always 0 reserved TICK IN received interrupt 0x08 Interrupt mask register IMR Byte3 D6 IMR Byte3 D6 0x09 always 0 reserved mask bit for TICK IN received interrupt 0x0A 0x0B 0x10 CHx DSM MODR D5 power save mode bit D5 always 0 reserved 0x30 0x50 0x12 CHx DSM STAR D5 always 0 reserved D5 ESC error 0x32 D6 always 0 reserved D6 FCT error 0x52 Attention Only
37. output3 X 212 0 Z amp 162 BC 1 CMDATA 7 input X amp 161 BC 1 CMDATA 6 output3 X 212 0 Z amp 160 BC 1 CMDATA 6 input X amp 159 BC 1 CMDATA 5 output3 X 212 0 Z amp 158 BC 1 CMDATA 5 input X amp 157 BC 1 CMDATA 4 output3 X 212 0 Z amp 156 BC 1 CMDATA 4 input X amp 155 BC 1 CMDATA 3 output3 X 212 0 Z amp 154 BC 1 CMDATA 3 input X amp 153 BC 1 CMDATA 2 output3 X 212 0 Z amp 152 BC 1 CMDATA 2 input X 151 BC 1 CMDATA 1 output3 X 212 0 Z amp 150 BC 1 CMDATA 1 input X amp 149 BC 1 CMDATA 0 output3 X 212 0 Z amp 148 BC 1 CMDATA 0 input X amp 147 BC 1 control 0 amp COMI Adr Output Enable 146 BC 1 CMADR 15 output3 X 147 0 Z amp 145 BC 1 CMADR 14 output3 X 147 0 Z amp 144 BC 1 CMADR 13 output3 X 147 0 Z amp 143 BC 1 CMADR 12 output3 X 147 0 Z amp 142 BC 1 CMADR 11 output3 X 147 0 Z amp 141 BC 1 CMADR 10 output3 X 147 0 Z amp 140 BC 1 CMADR 9 output3 X 147 0 Z amp 139 BC 1 CMADR 8 output3 X 147 0 Z amp 138 BC 1 CMADR 7 output3 X 147 0 Z amp 137 BC 1 CMADR 6 output3 X 147 0 Z amp 136 BC 1 CMADR 5 output3 X 147 0 Z amp 135 BC 1 CMADR 4 output3 X 147 0 Z amp 134 BC 1 CMADR 3 output3 X 147 0 Z
38. packet delimiters and generates autonomously EOP or no EOP as configured marker after each end of a transmission packet This mode also includes as a special sub mode e Wormbole routing This mode allows hardware routing of packets by the SMCS332SpW Simple Interprocessor Communication SIC Protocol Mode This mode executes the simple interprocessor communication protocol as described in chapter 13 The following capabilities ofthe protocol are implemented into the SMCS332SpW interpretation of the first 4 data characters as the header bytes of the protocol autonomous execution of the simple control commands as described in the protocol specification autonomous acknowledgement of received packets if configured In transmit direction no interpretation ofthe data is performed This means that for transmit packets the four header bytes must be generated by the host CPU and must be available as the first data read from the communication memory EOP control characters are automatically inserted by the SMCS332SpW if one configured transfer from the communication memory has finished 2 3 SMCS332SpW Control by SpaceWire link A feature of the SMCS332SpW is the possibility to control the SMCS332SpW not only via HOCI but via one of the three links This allows to use the SMCS332SpW in systems without a local controller uController FPGA etc Since the HOCI is no longer used in this operation mode it is instead available as a set of general p
39. signals CPUR and SESO 3 Status of signal CPUR 0 Signal CPUR is inactive high 1 Signal CPUR is active low status of signal SESO 0 Signal SESO is inactive high 1 Signal SESO is active low status of signal SES1 0 Signal SES 1 is inactive high 1 Signal SESI is active low status of signal SES2 0 Signal SES2 is inactive high 1 Signal SES2 is active low status of signal SES3 0 Signal SES3 is inactive high 1 Signal SES3 is active low always 0 reserved See also the Simple Interprocessor Communication Protocol Specification chapter 13 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 29 of 131 4 2 2 Channel 1 Registers 4 2 2 1 Channel 1 SpaceWire Mode Register CH1_DSM_MODR address 0x10 data width 8 bit D7 0 access mode read write reset value 0x00 iess Transmit bitrate selection only if bit 3 set 000 transmit bitrate max transmit bitrate 1 1 001 transmit bitrate max transmit bitrate 1 2 010 transmit bitrate max transmit bitrate 1 4 011 transmit bitrate max transmit bitrate 1 8 100 transmit bitrate max transmit bitrate 1 16 101 transmit bitrate max transmit bitrate 1 32 110 transmit bitrate max transmit bitrate 1 64 111 reserved see also bit 3 and register TRS CTRL Addr
40. to transfer data between the two SMCS and the RAM connected to the COMI port of the remote controlled SMCS or to use the SIC protocol mode DI ty BOOTLINK BOOTLINK Link 1 4 PiLink 1 HOCI TL GPIO lt 4 naa CPU a Link 2 control link PiLink 2 Link 3 amp Fum 3 Cl COM AAA 22 SS DPRAM amp Z curo SMCS ns CMADR ICMDATA j up to 64132 n addressable sy remote Lon controlled 4 coco S M CS coer 5 5 Wormhole Routing 5 5 1 Overview To enable packets to be routed each packet has a header at the front which contains routing information The SMCS332SpW uses the header of each incoming packet to determine the link to be used to output the packet Anything after the header is treated as the packet body until the packet terminator is received This enables the SMCS332SpW to transmit packets of arbitrary length In most packet switching networks complete packets are stored internally decoded and then routed to the destination node This causes relatively long delays due to the high latency at each node To overcome this limitation the SMCS332SpW uses wormhole routing in which the routing decision is taken as soon as the routing information which is contained in the packet header has been input Therefore the packet header can be received and the routing decision taken before the whole packet has been transmitted by the source A pack
41. two consequences packets with address headers allow to use this link standard in networks using routers e since the standard does not define the data payload within the packets an efficient transaction layer definition is missing To compensate for these deficiencies of the SpaceWire specification the SMCS332SpW implementations the SMCS332SpW and the SMCS116SpW introduce an optional transaction layer extension to the SpaceWire protocol standard This high level protocol extension supports applications in fault tolerant systems heterogeneous architectures feature power saving modes and remote configuration of the communication controller and autonomous command execution With this flexible and powerful protocol the SpaceWire link has many advantages over commonly used interface solutions such as RS 485 etc 3 Data Strobe SpaceWire signals The SpaceWire links use a protocol with two wires in each direction one for data and one to carry a strobe signal and are also referred to as data strobe DS Links Each DS pair carries characters and an encoded clock The characters can be data or control characters The figure below shows the format of data and control characters on the data and strobe wires Data characters are 10 bits long and consist of a parity bit a control flag which is set to 0 to indicate a data character and 8 bits of data Control characters are 4 bits long and consist of a parity bit a control flag which is set to 1 to i
42. without external arbitration logic The data bus width is scalable 8 16 32 bit to allow flexible integration with any CPU type Operation in little or big endian mode is configurable through internal registers The COMI address bus is 16 bit wide allowing direct access of up to 64K words 32 bit ofthe DPRAM Two chip select signals are provided to allow splitting of the 64k address space in two memory banks Host Control Interface HOCI gives read and write access to the SMCS332SpW configuration registers and to the SpaceWire channels for the controlling CPU Viewed from the CPU the interface behaves like a peripheral that generates acknowledges to synchronize the data transfers and which is located somewhere in the CPU s address space Packets can be transmitted or received directly via the HOCI In this case the Communication Memory DPRAM is not strictly needed However in this case the packet size should be limited to avoid frequent CPU interaction The data bus width is scalable 8 16 32 bit to allow flexible integration with any CPU type The byte alignment can be configured for little or big endian mode through an external pin Additionally the HOCI contains the interrupt signalling capability of the SMCS by providing an interrupt output the interrupt status register and interrupt mask register to the local CPU A special pin is provided to select between control of the SMCS332SpW by HOCI or by link If control by link is enabl
43. 0 millimeters For longer distances a matched 100 ohm transmission line should be used together with differential link transceivers LVDS The inputs and outputs have been designed to have minimum skew at the 1 5 V TTL threshold Buffers may be used for very long transmissions If so their overall propagation delay should be stable within the skew tolerance of the link although the absolute value of the delay is immaterial For more information see ADI All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 18 of 131 4 Register Set This chapter describes the SMCS332SpW registers which can be read or written by the HOCI or via the link in case the control by link is enabled to control SMCS332SpW operations All SMCS332SpW control operations are performed by writes or reads of the respective registers Most of the control operations are obvious from the content of the registers General Conventions bit 0 DO least significant bit bit 7 D7 most significant bit or bit 15 or bit 31 Dx 0 means data bit x until bit 0 4 Register address map The addresses of the SMCS332SpW registers are directly mapped with pins HADR7 0 The tables below shows the addresses of all the SMCS332SpW registers depending on the HOCI port width 4 1 1 SMCS332SpW status and control registers Port Wid
44. 130 BC 1 INPUT 129 BC 1 Rp 128 BC 1 INPUT 127 BC 1 INPUJ 126 BC 1 INPUT 125 BC 1 INPUT 124 BC 1 INPUT 123 BC 1 INPUT 122 BC 1 INPUT 121 BC 1 INPUJ 120 BC 1 INPUT 119 BC 1 INPUT 118 BC 1 INPUT 117 BC 1 Rp 116 BC 1 INPUT 115 BC 1 INPUT 114 BC 1 Rp 113 BC 1 INPUJ 112 BC 1 Rp 111 BC_1_INPUT 110 BC 1 pm 109 BC 1 Rp 108 BC 1 INPUT 107 BC 1 INPUT 106 BC 1 INPUT 105 BC 1 INPUT CMDATA2 CMDATA2 CMDATA1 CMDATA1 CMDATAO CMDATAO CMADR15 CMADR14 CMADR13 CMADR12 OQ UU UU UO CMADR11 CMADR10 CMADR9 CMADR8 OU UU UU UO CMADR7 CMADR6 CMADR5 CMADR4 CMADR3 CMADR2 CMADR1 CMADRO CMWR CMRD CMCS1 CMCSO COCO COCI CAM SES3 SES2 SES1 SESO CPUR won HDATA31 HDATA31 HDATA30 HDATA30 HDATA29 HDATA29 HDATA28 HDATA28 HDATA27 123 122 121 o3 oan gg g5 ga 81 123 122 121 120 119 118 117 114 113 112 111 110 109 108 105 104 103 102 101 100 DEER 9g 95 ogg 91 ngo ngg nga 87 ngg g5 ga 81 go 212 212 212 147 147 147 147 147 147 147 147 147 147 147 147 147 147 147 147 106 Ga uc uc oO C C Sa oO oO vo o e All Rights Reserved Copyright per DIN 34
45. 2 COMICFG channel 2 COMI configuration register foo LA J r w O m w LA HE AR AR CH2_TX_SAR channel 2 transmit Start Address Register r w A CH2 TX EAR channel 2 transmit End Address Register A AR CH2 TX CAR channel 2 transmit Current Address Register 0 45 6 CH2_TX_FIFO channel 2 transmit FIFO 7 CH2 TX EOPB channel 2 transmit EOP Bit Register 48 CH2 RX SAR channel 2 receive Start Address Register 46 BR E A AJA Bj fF 4A A 4A Wlwowlwl wl t w w wo 2 2 w wf wf wl wl w e Aim al gt oo A AB N oimimiocloi iui i iiejoj xjoj jovo n2je vte j C io o o w o o w w T T Q H2_RX EAR channel 2 receive End Address Register H2 RX CAR channel 2 receive Current Address Register 0 CH2_RX_FIFO channel 2 receive FIFO XXXXXXXX ro CH2 STAR channel 2 Status Register ro r r T D Ww WwW T SIEEIEEI E Q ES EN ES 95 ES Se 4A ri All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 21 of 131 4 1 8 SMCS332SpW channel 3 status and control registers Port Width Register Function Access Address hex m De a EREECHEN ow Es s s cre psm cvor casi Dov commana resse on w _ E s s un osm star emnes psv sas resse or hw _ s s s om psv rsm cis smiesne m rw s s se emos T ernas aioe
46. 2 Transmit bitrate base Register TRS_CTRL address 0x01 data width 5 bit D4 0 access mode read write reset value 0x0A w pem Multiplier value 0x0A after reset LSB setting will be ignored Value hex max bitrate 0x08 80 Mbit s 0x0A 100 Mbit s 0x0C 120 Mbit s not possible if VCC 3 3 Volt OxOE 140 Mbit s not possible if VCC 3 3 Volt 0x10 160 Mbit s not possible if VCC 3 3 Volt 0x12 180 Mbit s not possible if VCC 3 3 Volt 0x14 200 Mbit s not possible if VCC 3 3 Volt 0x00 0x07 not possible always 0 reserved The max transmit bitrate in Mbit s of all 3 channels is the result of the multiplication between the input frequency at the CLK10 pin and the multiplier value MUL Select the MUL value only to one of the above values A write of a new value in the transmit bitrate base register should only be taken when all links are running with 10 MBit s After the write of the new value the PLL needs 10 us to run on the new frequency After this time the links can run with the new transmit bit rate All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 D e SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 24 of 131 Example CLK10 Frequency 10 MHz max transmit bitrate CLK 10 MUL 160 MBit s 10 0x10 4 2 1 3 Route Control Status Register RT CTRL address 0x02 data width 8 bi
47. 21 l A20 l A20 l A19 l A19 l A18 l A18 l A17 l A17 rA16 rA16 rA15 l A15 rA14 DATA l A13 l A13 l A12 l A12 l A11 l A11 rA10 rA10 rAg rAg DAG rAs TA7 TA7 l A6 l A6 DAG DAS DAAT rA4 l A3 DAT l A3 162 159 15g 157 154 153 152 149 74g 147 146 145 144 141 140 139 138 137 136 133 132 131 128 127 126 159 158 157 154 153 152 149 148 147 146 145 144 141 140 139 138 137 136 133 132 131 128 127 126 212 212 212 212 212 212 212 212 212 212 212 212 212 212 212 212 212 212 212 212 212 212 212 212 All Rights Reserved Copyright per DIN 34 4 EADS ASTRIUM SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS_ASTD_UM_100 Issue 1 4 Updated 9 Sep 2006 Page 106 of 131 153 BC 1 INPUT 152 BC 1 INPUT 151 BC 1 Rp 150 BC 1 INPUT 149 BC 1 INPUT 148 BC 1 INPUT 147 BC 1 INPUT 146 BC 1 INPUT 145 BC 1 INPUT 144 BC 1 INPUT 143 BC 1 INPUT 142 BC 1 INPUT 141 BC 1 Rp 140 BC 1 INPUT 139 BC 1 INPUT 138 BC 1 INPUT 137 BC 1 INPUT 136 BC 1 INPUT 135 BC 1 INPUT 134 BC 1 INPUT 133 BC 1 INPUT 132 BC 1 INPUT 131 BC 1 INPUT
48. 32SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 74 of 131 Vec 73 3 V 0 3V Etat AER AN RN uy meaa e S HACK low after HRD HSEL active and SMCSADR valid turacen Im HACK disable after HRD HSEL inactive or SMCSADR invalid turacka Im EE HDATA enable after HRD HSEL active and SMCSADR valid tue Jul Notes D Signal HACK active when HRD low and HSEL low and SMCSADR SMCSID Signal HACK disable when HRD high or HSEL high or SMCSADR SMCSID tursu 7 HRDW 7 th 23 turpv HRDH HRDE All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 75 of 131 9 4 Host Write ax L Lj LJ L esc t e HWSU HSEL HRD Lamm t HADR Address valid Addr valid SMCSADR SMCSID smcsiD 4 kal t t Lee thiwacka HACK i Lage HDATA Data valid HWR pulse width high 5 HACK low after HWR HSEL active and SMCSADR valid waca 14 HACK disable after HWR or HSEL inactive or SMCSADR invalid 3 le HDATA setup before HSEL or HWR high or SMCSADR tuwpsu 5 SMCSID HDATA hold after HWR or HSEL inactive or SMCSADR invalid HACK high after HSEL and HWR and SMCSADR SMCSID tuwa
49. ATAO HDATAI CC C GND HDATA12 Low qwe n ew CMRD CMWR 165 166 CMDATA30 CMDATA31 D CMADR2 169 VCC_3VOLT CMADR3 170 CMADR4 171 Ne CMADR8 CMADR9 CMADRIO CMADRII CMADR14 185 CMADRI5 CMDATAO CMDATAI CMDATA3 CMDATA4 CMDATAS 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 132 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 87 of 131 11 Additional Informations 11 1 Frequently Asked Questions T Pe gt Q zO gt Q zO T Pe Is the SMCS332SpW compatible with the old SMCS332 Yes the link standard IEEE 1355 1995 and ECSS E 50 12A are compatible however the old SMCS332 has a slightly different startup behavior the SMCS332 must be started first on a link connecting with the SMCS332SpW The nominal frequency for CLK10 is 10 MHz Can it be different What is the effect on the transmission rate It can be different the transmission rate changes in direct proportion to the change of the CLK10 frequency However it is recommended to keep CLK10 at 10 MHz to be conforming to ECSS What is the best way for adding a transfer rate of 5Mbps and still be able to select 10 12 5 25 50 100 Mbps With these setting
50. C VCC_3VOLT 170 NC GND 171 NC GND 175 LEN1 NC 182 LEN2 NC 192 LEN3 TIME CODE SYNC 196 PLLOUT GND All Rights Reserved Copyright per DIN 34
51. DATA 2 output3 X 31 0 Z amp 29 BC 1 HDATA 2 input X amp 28 BC 1 S control 0 amp HOCI Data Output Enable 27 BC 1 HDATA 1 output3 X 28 0 Z amp 26 BC 1 HDATA 1 input X amp 25 BC 1 P control 0 amp HOCI Data Output Enable 24 BC 1 HDATA 0 output3 X 25 0 Z amp 23 BC 1 HDATA 0 input X amp 22 BC 1 SMCSID3 input X amp 21 BC 1 SMCSID2 input X amp 20 BC 1 SMCSID1 input X amp 19 BC 1 SMCSIDO input X amp 18 BC 1 SMCSADR3 input X amp 17 BC 1 SMCSADR2 input X amp 16 BC 1 SMCSADR1 input X amp 15 BC 1 SMCSADRO input X amp 14 BC 1 BOOTLINK input X amp 13 BC 1 HADR 7 input X amp 12 BC 1 HADR 6 input X amp 11 BC 1 HADR 5 input X amp 10 BC 1 HADR 4 input X amp 9 BC 1 HADR 3 input X amp 8 BC 1 HADR 2 input X amp 7 BC 1 HADR 1 input X amp 6 BC 1 HADR O input X amp 5 BC 1 HINTR output2 X amp 4 BC 1 E control 0 amp HACK Enable 3 BC 1 HACK output3 X 4 0 Z amp 2 BC 1 HWR input X amp 1 BC 1 HRD input X amp 0 BC 1 HSEL input X end SMCS JTAG Technologies B V smcs dsh created by BSDL90 version 2 2 date 07 05 1998 time 08 52 23 EBST COMPONENT STANDARD PIN LIST SMCS IEEE 1149
52. EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 EA D v User Manual Updated 9 Sep 2006 Page 1 of 131 SMCS332SpW User Manual Prepared by SE SE Date 14 046 4 Checked by perd e i Date 74 04 06 Checked by bum T Date A 49 06 ae Dir amm me geog All Rights Reserved Copyright per DIN 34 ASTRIUM SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 2 of 131 Document Revision History Revision Date Responsible Modifications Reasons for Change 1 0 June 05 Uwe Liebst ckel First release 1 1 Nov 05 Uwe Liebst ckel Section 11 3 Special Behaviour added Section 4 2 2 8 Checksum generation figure added 1 2 Nov 05 Uwe Liebst ckel Section 11 3 Special Behaviour deleted Section 12 Handling Empty Packets added 1 3 Jul 06 Uwe Liebst ckel Section 12 Handling Empty Packets changed Section 4 2 2 3 Updated 1 4 Sep 06 Stephan Fischer Section 12 editorial modifications ESA comments All Rights Reserved Copyright per DIN 34 Copying of this document and giving it to others and the use or communication ofthe contents thereof are forbidden without express authority Offenders are liable to the payment of damages All rights are reserved in the event of the grant of a patent or the registration of a utility model or design Proprietary N
53. ESET SMCS in IDLE 100 Maximum All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 69 of 131 8 4 PLL Filter The pin PLLOUT should be connected as shown below SMCS PLLOUT R1 C1 C2 Values for Vcc 5 V x 0 5V R1 1 8kQ 596 LAM C1 33pF 5 200V C2 820pF 5 200V Values for Vcc 3 3 V 0 3V R1 2 0kQ 596 LAM C1 33pF 5 200V C2 760pF 5 200V 8 5 Power and Ground Guidelines To achieve its fast cycle time the SMCS332SpW is designed with high speed drivers on output pins Large peak currents may pass through a circuit board s ground and power lines especially when many output drivers are simultaneously charging or discharging their load capacitances These transient currents can cause disturbances on the power and ground lines To minimize these effects the SMCS332SpW provides separate supply pins for its internal logic and for its external drivers All GND pins should have a low impedance path to ground A ground plane is required in SMCS332SpW systems to reduce this impedance minimizing noise The VCC pins should be bypassed to the ground plane using approximately 10 high frequency capacitors 0 1 uF ceramic Keep each capacitor s lead and trace length to the pins as short as possible Thi
54. EST output2 X amp 219 BC 1 LSI2 input X amp 218 BC 1 LDI2 input X amp 217 BC 1 LSO1 output2 X amp 216 BC 1 LDO 1 output2 X amp 215 BC 1 LSI 1 input X amp 214 BC 1 LDI 1 input X amp 213 BC 1 VCC 3VOLT input X amp 212 BC 1 control 0 amp COMI Data Output Enable 211 BC 1 CMDATA 31 output3 X 212 0 Z amp 210 BC 1 CMDATA 31 input X amp 209 BC 1 CMDATA 30 output3 X 212 O Z amp 208 BC 1 CMDATA 30 input X amp 207 BC 1 CMDATA 29 output3 X 212 O Z E 206 BC 1 CMDATA 29 input X amp 205 BC 1 CMDATA 28 output3 X 212 O Z E 204 BC 1 CMDATA 28 input X amp 203 BC 1 CMDATA 27 output3 X 212 0 Z amp 202 BC 1 CMDATA 27 input X amp 201 BC 1 CMDATA 26 output3 X 212 O Z amp 200 BC 1 CMDATA 26 input X amp 199 BC 1 CMDATA 25 output3 X 212 O Z amp 198 BC 1 CMDATA 25 input X amp 197 BC 1 CMDATA 24 output3 X 212 O Z amp 196 BC 1 CMDATA 24 input X amp 195 BC 1 CMDATA 23 output3 X 212 O Z amp 194 BC 1 CMDATA 23 input X amp 193 BC 1 CMDATA 22 output3 X 212 0 Z amp 192 BC 1 CMDATA 22 input X amp 191 BC 1 CMDATA 21 output3 X 212 O Z amp 190 BC 1 CMDATA 21 input X amp 189 BC 1 CMDATA 20 ou
55. HOCI ER 44 5 2 COMI Data Transfer n GS RR ERU MEN Eg HE Lg ee EES 45 5 3 E EE 45 5 4 Control DY c ries 46 5 4 1 Selecting remote mode eere ete aree EI EXER eR ne LEUR HE PRU ea EE HEURE Ee EES 48 5 4 2 Determination of the control link onion Rr ei ee teehee DE Ple ee eee 48 5 4 3 Protocol and Commands aee epe HA a Lae 48 5 4 4 Host Data Bus GPIO Port eas RI ee ee ee 49 5 4 5 Restrictions mirni a ERRAT ces onl RETIRER ERNEUT E URINE eR eae 49 5 5 Wormhole ROUTING iscsi s ssscene itio teen tit beer tienne R a aged etes Cono robo ges es v bees bene ees eteg 49 5 5 1 i cag Soeneeae et 49 5 532 Wormhole routing on SMCH332nMW ener ener eene nnne entren nennen enn ennt 50 5 5 3 Routing Implementation on SMCS332SpW ccccesccssecsececeeseceneceeecseecseeeseeeeeeeeeeseeneenseceaeenaeenseceeeaeeenes 50 5 5 4 SMCS332332SpW Routing Examples essen enne enne enne enne nnne nennen 51 X6 Hedder bytes generation cite eo e et tbe eR e eC ordre tod te deed deen 51 5 6 1 Header feld controlibit enne em eror e eere HEU b EES 51 5 62 Routing and Checksum Generation niente one decsdtesdaveacealeschevadscveveccstensnien codes 53 3 7 Time Code EERSTEN poy 54 5 7 1 SMCS33SpW transmit time code sss ener ener ener enne nennt nnne nnns 54 5 7 2 SMCS332SpW receive time Code 55 5 8 SMCSISZSPW Version Contr
56. Hx ESRI 0x1C bit D4 checksum error 4 2 2 9 Channel 1 Control Register 2 CH1 CNTRL2 address 0x19 data width 3 bit D2 0 access mode read write reset value 0x00 maim E reset delete channel transmit and acknowledge section reset delete channell receive section reset protocol unit always 0 reserved Note The above bits must be specifically set cleared as required There is no automatic reset See also the procedure following disconnect described in chapter 3 4 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 35 of 131 4 2 2 10 Channel 1 Header Transaction ID CH1 HTID address Ox1A data width 8 bit D7 0 access mode read only reset value 0x00 When protocol mode enabled If an error occurs this register shows the third byte transaction ID of the received acknowledge packet Wl T transaction ID of the received packet 42 241 Channel 1 Header Control Byte CH1 HCNTRL address Ox1B data width 8 bit D7 0 access mode read only reset value 0x00 When protocol mode is enabled If an error occurs this register shows the second byte header control byte of the received acknowledge packet LX CNN header control byte of the received packet 4 2 2 12 Channel 1 Error Source Register 1 CH1 ESRI1 address
57. IFO is empty set after reset 3 only when bit 3 of register CH1_CNTRLI is enabled protocol unit acknowledge FIFO is full always 0 reserved All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 33 of 131 4 2 2 8 Channel 1 Control Register 1 CH1_CNTRL1 address 0x18 data width 6 bit D5 0 access mode read write reset value 0x00 Wlan OOS data transfer mode of channel 1 transparent mode reset this mode allows complete transparent data transfer between two nodes reserved simple interprocessor communication protocol mode known as protocol mode this mode executes the simple interprocessor communication protocol as described in the protocol specification reserved only when protocol mode enabled check destination byte enabled compare first byte header destination address byte of the received data packet with register CHI ADDR only when protocol mode enabled send acknowledge packet enabled when set the protocol unit sends acknowledge packets see also bit 2 and 3 of register CHI PR STAR checksum enabled when set the channel sends two checksum bytes at the end of the transmitted packet and checks the last two bytes See Note header field control bit when set the SMCS332SpW use the first byte of a packet as number of bytes which are transmit
58. IUM User Manual Updated 9 Sep 2006 Page 118 of 131 This command is required since the link end which intents to stop link operation must inform the other end of the link Otherwise the link shutdown might be interpreted as a link failure Ifa link has been shut down previously it can be requested to start up again by a restart link operation complex command This command has to be issued via an already operating link to the CPU of a node which then initiates the actual restart operation for the link requested to start up Details of the link shutdown operation are given in para 4 Note that the simple procedures work only for direct connected systems but that systems incorporating a router require more complicated procedures e g by involving the system controller All complex control commands should be addressed This means that a complex control command received via one link interface can control every other link interface on the same node 13 4 Procedure Rules 13 4 1 Acknowledgements Data Transmission and Simple Commands With the exception of the reset command the reception of each packet is acknowledged by an acknowledge packet The acknowledge packet informs the requester node on the successful reception of the packet but does not contain information about a completed execution of a command The acknowledgement covers in case of data transfer commands including encapsulated complex commands the correct recept
59. LSB Link Interface Operation Mode Bit 7 Bit4 Link Interface Operation Status Bit 15 Bit 8 Link Interface Error Status Bit 23 Bit 16 Link Interface Command Execution Status Bit 31 Bit 24 Reserved for Future Implementation 2 0 LSB Link Speed Oxx minimum speed 100 maximum speed Restart from Commanded Reset 0 no restart 1 restart Link Interface Received Packet with Wrong Address 0 no wrong addressed packet received 1 wrong addressed packet received Received Command Field not Specified 0 Command fields specified 1 not specified checksum error in Request Packet 0 no checksum error occurred 1 checksum error occurred currently not used Execution of Critical Simple Control Commands Enable 0 not enabled 1 enabled 17 CPU Reset Signal Status 0 not active 1 active en fem Specific External Signal 0 3 Status 0 not active 1 active All Rights Reserved Copyright per DIN 34 D e SMCS332SpW ASTRIUM User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 125 of 131 13 5 4 Data Transfer Type Transactions Requester Packet DEST CNTRL DATA EOP CNTRL Transfer Data Complex Command Request or Complex Command Acknowledge DATA n 8 bit data Actions Transfer data to host working memory DEST SRC SRC DEST CNTRL Transaction OK or in case of errors CNTRL Transaction Error Resp
60. M SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 113 of 131 12 2 Workaround A stop at either end of the link causes a disconnect and hence clears this problem Note that there is NO need to reset the entire device Please do make sure that this situation be treated properly if consecutive empty packets are expected All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 114 of 131 13 Simple Interprocessor Communication Protocol Specification 13 1 Application Scenario The purpose of this protocol specification is to provide a framework which allows the exchange of data and simple system control commands between single nodes of a multiprocessor system Nodes in this context are understood as computing nodes and controlling nodes a physical node may be a mix of both The exchange of data and commands is structured into packets A target multiprocessor system for this protocol is understood as a small to medium size system the multiprocessor system is based on a message passing architecture with only local memory the protocol supports 256 different link addresses this means the protocol is applicable to multiprocessor systems consisting of e g 256 nodes each with one link not very likely 64 nodes each with
61. MDATA23 157 CMDATA24 158 CMDATA25 159 CMDATA26 162 CMDATA27 163 CMDATA28 164 CMDATA29 165 CMDATA30 166 CMDATA31 43 HDATAO 44 HDATA1 45 HDATA2 46 HDATA3 47 HDATAA4 48 HDATA5 49 HDATA6 52 HDATA7 53 HDATAS8 54 HDATA9 55 HDATA10 56 HDATA11 59 HDATA12 60 HDATA13 61 HDATA14 62 HDATA15 63 HDATA16 64 HDATA17 67 HDATA18 68 HDATA19 69 HDATA20 70 HDATA21 71 HDATA22 72 HDATA23 75 HDATA24 76 HDATA25 77 HDATA26 80 HDATA27 81 HDATA28 82 HDATA29 85 HDATA30 86 HDATA31 n2 GNDO 14 GND1 21 GND2 31 GND3 42 GNDA4 51 GND5 58 GND6 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GN GN GN GN GN GN GN iw 1 iw H Ae s kb ME UO i All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 EADS om User Manual Updated 9 Sep 2006 Page 102 of 131 66 GND7 GND 74 GND8 GND 79 GND9 GND B 84 GND10 GND 98 GND11 GND 107 GND12 G
62. MDATAO 16 bit data port byte 0 is transferred via CMDATA7 CMDATAO byte is transferred via CMDATA15 CMDATA8 32 bit data port byte 0 is transferred via CMDATA7 CMDATAO byte is transferred via CMDATA15 CMDATA8 byte 2 is transferred via CMDATA23 CMDATAI6 byte 3 is transferred via CMDATA31 CMDATA24 Big endian mode selected 8 bit data port default after reset byte 0 is transferred via CMDATA31 CMDATA24 16 bit data port byte 0 is transferred via CMDATA31 CMDATA24 byte 1 is transferred via CMDATA23 CMDATAI6 32 bit data port byte 0 is transferred via CMDATA31 CMDATA24 byte 1 is transferred via CMDATA23 CMDATAI6 byte 2 is transferred via CMDATA15 CMDATA8 byte 3 is transferred via CMDATA7 CMDATAO 5 3 COMI Arbitration The operation of two SMCS332SpW in master slave mode is shown below All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW DocNo SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 46 of 131 DPRAM COMI SMCS Master Two SMCS332SpW can work on a common memory without any external arbitration logic However if more than two SMCS332SpWs share a common communication memory an external arbiter is required The following describes the arbitration between two SMCS332SpWs The rising edge of the RESET signal loads the level ofthe CAM signal into t
63. Manual Updated 9 Sep 2006 Page 17 of 131 The following procedure can be used to restart a link following an error routing is assumed disabled 1 Disconnect is detected cause error 2 SMCS332SpW enters exchange of silence if the corresponding interrupt mask bit is enabled the SMCS332SpW HINTR signal will be asserted 3 The transmit section 1s reset by the SMCS332SpW after an error has occurred Any currently on going transmit transfer via COMI is stopped The user can decide to read the receive FIFO if not empty and then to reset the receive section or to reset the receive section immediately without reading the receive FIFO Resetting the receive section is done by setting and clearing bitl in register CHx_CNTRL2 If the protocol mode is used the protocol unit should be reset by setting and clearing bit2 in register CHx CNTRL2 4 If the auto start bit bit2 CHx_ DSM CMDR is set the link will start automatically after the protocol of silence otherwise the user has to start the link by setting bit in CHx_ DSM CMDR The configuration registers are not affected by the disconnect error 5 New transmit and receive transfers can be started 3 5 SpaceWire state on start up After power on all LinkData and LinkStrobe signals are low without clocks Following power on reset an initialization sequence sets the speed of the link clock The DS Links are initially inactive They are configured and started by configu
64. ND 116 GND13 GND 125 GND14 GND 130 GND15 GND 135 GND16 GND 2 143 GND17 GND 151 GND18 GND 156 GND19 GND 161 GND20 GND 167 GND21 GND 170 GND22 GND 171 GND23 GND 173 GND24 GND 174 GND25 GND et 193 GND26 GND 194 GND27 GND 196 GND28 GND nga VDDO PWR l3 VDDI PWR 20 VDD PWR z 30 VDD3 PWR B 41 vDD4 PWR 50 VDD5 PWR 57 VDDpe PWR 65 VDD7 PWR 73 VDD8 PWR TO T VDDS9T PWR 83 VDD10O PWR 97 VDD11 PWR 106 VDD12 PWR 115 VDD13 PWR 124 VDD14 PWR 129 VDD15 PWR i 134 VDD16 PWR 142 VDD17 PWR 150 VDD18 PWR 155 VDD19 PWR 160 VDD20 PWR 172 VDD21 PWR ei 183 VDD22 PWR 184 VDD23 PWR 185 VDD24 PWR 195 VDD25 PWR wa NCO PWR All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 e SMCS332SpW DocNo SMCS ASTD UM 100 EAD Issue 14 ASTRIUM User Manual Updated 9 Sep 2006 Page 103 of 131 DI 175 DI NCI DI PWR DI 182 DI NC2 DI PWR kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxkxk END PIN LIST INSTRUCTION REGISTER instr PURPOSE select register and BST mode LENGTH 3 CAPTURE 101 INSTRUCTION LIST ek ck K K k K k ke ke ke ke kk che e ke ck k ek ke che ke ke TEE k k k k k k k k k k k sk k k k k k k k k k k k k INSTR INSTR SELECTED BST ACTIVE NAME VAL
65. RX End Address Reg check sum error if enabled With setting a bit in the Interrupt Mask Register the respective event is enabled The interrupt capability can be switched off by masking all interrupt sources through setting the complete interrupt mask register to 0 when the system is not able to service it In this case SMCS332SpW ISR can be polled to wait for the event The structure of storage of data words can be configured for each channel independently The following list shows the switches that are possible storage of one versus more packets per segment If more than one packet is allowed to be stored in one segment the user must take care about the separation of the different packets data word width to 8 versus 16 versus 32 sign bit expand versus no expand in 8 16 bit mode Furthermore the SMCS332SpW supports both little and big endian mode on its COMI as well as for the HOCI to be compliant to the most processors Program Sequence All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW DocNo SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 59 of 131 Before starting with transmission the channel must be configured for proper operation Besides general SMCS332SpW configuration see chapter SMCS332SpW initialization at least the following channel specific registers must be set CHx DSM MODR Channel Mode Register CHx DSM CMDR Chann
66. Register For transmitting data the CPU writes the words directly to the channel transmit FIFO address The end of a transmit packet is indicated by writing on the EOP Bit register The EOP termination is appended to the last word as a control character on the link To recognize the end of an incoming receiving packet the CPU reads the channel status or the interrupt status register Note Reading the interrupt status register will clear its contents Thus relevant information concerning other link channels must be saved for further evaluation if so required Before accessing the FIFOs the CPU must evaluate the status of the FIFO flags For each channel FIFO status flags are provided transmit FIFO empty transmit FIFO full receive FIFO not empty receive FIFO full With the first write access on the transmit FIFO the transmit FIFO empty flag becomes inactive The transmit FIFO full flag must be examined carefully to assure that no data words will be overwritten The first two data words once written in the transmit FIFO are not immediately sent towards the listening node but remain in the queue Either with adding the next word to the packet or writing the EOP bit on the Transmit EOP Bit Register the SMCS332SpW begins transmission of one word or the whole packet respectively All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 EADS m Use
67. SMCSID1 38 19 BC_1_INP SMCSIDO Su 18 BC 1 INP SMCSADR3 36 i i 17 BC 1 INP SMCSADR2 35 16 BC 1 INP SMCSADR1 34 15 BC 1 INP SMCSADRO 33 14 BC_1_INP BOOTLINK 32 13 BC_1_INP HADR7 29 12 BC_1 INP HADR6 28 Tr BC 1 INP HADR5 A 10 BC 1 INP HADR4 26 9 BC 1 INP HADR3 257 8 BC 1 INP HADR2 24 7 BC 1 INP HADRI 23 All Rights Reserved Copyright per DIN 34 4 EADS SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM Updated 9 Sep 2006 Page 109 of 131 6 BC 1 INPUT HADRO 22 z 2 5 BC 1 INPUT HINTR 19 a 7 4 BC 1 INPUT mon a z 3 BC 1 INPUT HACK 1g z 4 0 2 BC 1 INPUT HWR 17 E E 1 BC 1 INPUT HRD 16 z 0 BC 1 INPUT HSEL 15 S kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxk END CHAIN LIST END BOUNDARY SCAN REGISTER IDENTIFICATION REGISTER IDENT PURPOSE LENGTH CAPTURE MANUFACTURER IDCODE PARTNUMBER IDCODE VERSION IDCODE device identification 32 00010100010001010011000010110001 00001011000 0100010001010011 0010 END IDENTIFICATION REGISTER GLOBAL FAMILY SMCS TCK STOP AT ONE TEST FREQUENCY TEMPERATURE RANGE END GLOBAL FAMILY END COMPONENT END EBST YES 0 10 0E6 10 0E6 All Rights Reserved Co
68. The allowed range is from 1 up to 15 The number byte and the associated address byte s defined as header field The header field size is minimum 2 and maximum 16 bytes It is always accessed in blocks of 4 bytes the first 4 8 12 or 16 incoming bytes This means that data which should be included in the checksum has to start at the next modulo 4 bytes The rest of a 4 byte block which is not covered by the number of address bytes is not transmitted Example Bit 4 is set in register CHx_CNTRL1 AND Bit 7 in register RT_CTRL is set The first byte contains the number of header bytes excluded from checksum generation value 1 The second byte is a header byte In total 2 bytes The first 4 bytes built the header field but the last 2 bytes will be NOT transmitted byte 0 1 number of following header bytes excluded from checksum NOT transmitted byte 1 header byte byte 2 ignored NOT transmitted byte 3 ignored NOT transmitted byte 4 first data byte included in checksum byte n last data byte included in checksum transmitted packet via SpaceWire byte 1 header byte byte 4 byten data bytes byte cl byte c2 2 checksum bytes EOP All Rights Reserved Copyright per DIN 34 ASTRIUM EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 User Manual Updated 9 Sep 2006 Page 54 of 131 5 7 Time Code Interface Both time code interface registers TIME CNTRL an
69. These additional FIFOs are large enough to decouple at least to a certain extent the transmission speed on the SpaceWire links from the transfer speed between the node s communication memory and the link interface If the receive FIFO is full reception of further tokens is stalled utilizing the SpaceWire link low level flow control mechanism If more than one link interface HW is integrated on one chip the different link channels can share the interfaces for the protocol s control commands for the data transferred between the node s communication memory and the links and the control interface provided to enable control by the CPU The transmission of data and command is structured into packets Although this protocol does not limit the maximum packet length it is recommended that the packet length 1s kept short to decrease latency and to avoid blocking of links due to long packets Since the protocol is intended to be used in HW implementations housed in shielded boxes with a clean electrical environment inside no additional error protection checking is performed on top ofthe parity checking already provided by the SpaceWire links However it is expected that the SW kernel running on the nodes ofthe system provides a certain set of control functions The protocol supports routing and assumes Inmos C104 like routing networks with one byte header and without header deletion The protocol provides a structure to enable routing but does not define
70. U RESET kl HACK ST HDATA d HINTR Naas CAM 1 CMRD if a CMT CMWR A oO Z 3 CMADR A o Z l CMDATA E 4j a CAN lt CAM 0 HOSTBIGE BOOTLINK U n n SS om Disch ls Unit Em Em E Symbol Max Unit ns hum e is he prem s All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 73 of 131 9 3 Host Read lusu HSEL l turonw HRD m NN oe Lea y HADR Address valid Addr valid SMCSADR SMCSID GoD tude y lick e d Tack HACK M t Lem throe HDATA Data valid Vcc7 5V 0 5V Description WADRSMCSADRIoHaRerISEL MRD High ue 9 HACK low after HRD HSEL active and SMCSADR valid ben wes Tan t m EE m Kc HACK disable after HRD HSEL inactive or SMCSADR invalid nen 16 EE HDATA enable after HRD HSEL active and SMCSADR valid tu a Ir Notes D Signal HACK active when HRD low and HSEL low and SMCSADR SMCSID Signal HACK disable when HRD high or HSEL high or SMCSADR SMCSID All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS3
71. UE REGISTER MODE REGISTER ck ck ck ck ck ck ck ck kk kk kk kk kk kk kk kk kk ck Sk Sk kc kc kc kc kc kc kc kc kc ko kc ck ckc ko ko koc k kc k k k k kk BYPASS 111 BYPASS SAMPLE BYPASS BYPASS 110 BYPASS SAMPLE BYPASS BYPASS 101 BYPASS SAMPLE BYPASS BYPASS 100 BYPASS SAMPLE BYPASS EXTEST 000 BOUNSCAN EXTERNAL BOUNSCAN SAMPLE PRELOAD 001 BOUNSCAN SAMPLE BOUNSCAN IDCODE 010 IDENT SAMPLE IDENT HIGHZ 011 BYPASS BYPASS ck ck ck ck ck ck ck ck kk ck kk kk kk kk kk kk kk Sk kk Sk kk kc kc kc kc kc kc kc kc kc kcko ko koc ko kc k kc k k kk END INSTRUCTION LIST END INSTRUCTION REGISTER CELL BC 1 INPUT DATA INPUTS PIL DATA OUTPUTS z POL MODE_LIST kkkkkxkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkx k MODE SELECT CAPTURE PO1 kkkkkxkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxk EXTERNAL PTL UPD SAMPLE PIL PIL INTERNAL PIL UPD ck ck ck ck ck ck ck ck kk ck kk kk kk kk kk Sk kk kk kk kc kc kc kc kc kc kc kc kk ko ko koc k kc kc k k k kk END MODE LIST END CELL All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 el SMCS332SpW Doc No SMCS ASTD UM 100 E AD Issue 14 ASTRIUM User Manual Updated 9 Sep 2006 Page 104 of 131 BYPASS REGISTER BYPASS PURPOSE Short cut LENGTH S1 CAPTURE o END BYPASS REGISTER BOUNDARY SCAN REGISTER BOUNSCAN PURPOSE scan line along boundary LENGTH 233 CHAIN LIST kkkkkxkxkkxkkkkkkkkkkkkkkkkk
72. W This command performs a hard reset interrupting all currently running transmissions of the link channel receiving this command This command must be enabled All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 EADS H Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 117 of 131 Reset Link Interface Unit HW This command performs a hard reset interrupting all currently running transmissions of all link interfaces integrated within one link interface unit This command must be enabled Read Link Interface Status Register This commands reads the status register of the link interface and sends the content to the requester within the response packet of this command This command can be executed without being previously enabled It depends on the implementation whether the CPU reset and the activate deactivate signal commands are supported or not It is only possible to support all of these commands or none of them Subsets are not allowed 13 3 2 Complex Control Commands Currently the following complex commands are foreseen enable complex command read status of complex command enable switch set link speed to minimum set link speed to maximum shut down link operation restart link operation Enable Complex Command Read Status of Complex Command Enable Switch To enhance security all safety relevant complex comma
73. a Input channel 3 L0 LSI3 Link Strobe Input channel 3 a LDO3 o Link Data Output channel 3 LSO3 O Link Strobe Output channel 3 TRST I Test Reset Resets the test state machine All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 66 of 131 Signal Name Type Function max output load pF current mA TCK I Test Clock Provides an asynchronous clock for JTAG boundary scan ee Test Mode Select Used to control the test state machine ess 3d Test Data Input Provides serial data for the boundary scan logic a LA Test Data Output Serial scan output of the boundary scan path RESET SMCS Reset Sets the SMCS to a known state This input must be asserted low at power up The minimum width of RESET low is 5 cycles of CLK10 in parallel with CLK running External clock input to SMCS max 25 MHz Must be derived from RAM access time A falling edge on this signal sends if enabled the internal SpaceWire time code value over the links Output of internal PLL Used to connect a network of external RC devices No PLL clock output Power Supply TIME CODE SYNC CLK10 I External clock input to SMCS DS links application specific nominal 10 MHz Used to generate to transmission speed and link disconnect timeout All Rights Reserved Copyright per DIN 34
74. aken FIFO buffering with minimal latency Note that if a packet 1s transmitted from a link running at a higher speed than the link on which it is received there will be a loss of efficiency because the higher speed link will have to wait for data from the slower link In most cases all the links in a network should be run at the same speed 5 5 2 Wormhole routing on SMCS332SpW The SMCS332SpW supports wormhole routing if in ROUTE CTRL register D7 is set bit7 1 and when operating in transparent mode Wormhole routing could only be enabled for the whole SMCS332SpW not for dedicated channels only The figure below shows the routing possibilities inside the SMCS332SpW An incoming packet can be routed to the channelx receive fifo or to one ofthe two other links The routing connection is terminated by the EOP or EEP ofthe routed packet channel 1 channel 1 cm 9 receive fifo COMI channel 2 channel 2 receive fifo HOCI channel 3 channel 3 mm receive fifo 5 5 3 Routing Implementation on SMCS332SpW When routing is enabled the first byte of a received packet will be interpreted as the address destination byte or routing header The address byte will be removed from the packet header deletion The remaining packet is unchanged The address byte is compared with the contents ofthe CHx ADDR and th
75. and to interpret the data The SpaceWire links which are used for the implementation of the low levels of the protocol transports data in pieces of data characters consisting of 8 bits It is also the smallest entity of data which is covered by the data transport service of this protocol It is up to an implementation into which higher datastructures the 8 bit entity is organized Data transfer between two nodes is basically acknowledged by this protocol ona packet by packet basis This acknowledge covers the correct reception of data up to the EOP end of packet marker and the storage of the data into the link interface s receive FIFO The acknowledge provided here does not cover the correct transfer of data from the link interface HW to the All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 116 of 131 node CPU s working memory If required it is up to higher levels of a communication protocol to provide this acknowledge Refer to para 4 1 for details 13 3 2 Execution of control commands The protocol supports two kinds of commands Simple control commands which may be executed directly by a link interface HW without intervention of the node s CPU The coding and function of the simple commands are specified in this document Complex control commands coded into the data transported betwee
76. another FCT before transmitting any more tokens The provision of more than 8 normal characters of buffering on each link input ensures that in practice the next FCT is received before the previous block of 8 normal characters has been fully transmitted so the character level flow control does not restrict the maximum bandwidth of the link For further information see AD1 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 16 of 131 3 3 Link speeds The SpaceWire links can support a range of communication speeds which are programmed by writing to registers At reset all links are configured to run at the base speed of 10 Mbits sec Only the transmission speed of a link is programmed as reception is asynchronous This means that links running at different speeds can be connected provided that each device is capable of receiving at the speed of the connected transmitter The transmission speeds of all of the links on a given device are related to the maximum transmission rate programmed for the complete device This maximum transmission rate is programmed through the transmit bitrate base register TRS_CTRL described in section 4 2 1 2 This max transmission bitrate is divided down to obtain the transmission frequency for each link The division factor can be programmed separately for each link via the Cha
77. anual Updated 9 Sep 2006 Page 9 of 131 2 Introduction The SMCS332SpW provides an interface between 3 SpaceWire links according to the SpaceWire Standard ECSS E 50 12A specification and a data processing node consisting of a CPU and a communication data memory The SMCS332SpW provides HW supported execution of the major parts of the simple interprocessor communication protocol particularly transfer of data between two nodes of a multi processor system with minimal host CPU intervention execution of simple commands to provide basic features for system control functions provision of fault tolerant features However with disabling of features such as the protocol handling or with reduction of the transmit rate also low power usage is supported CMADR CM CONTROL gt le CMDATA COMI HADR H_CONTROL HOCI HDATA e SC HINTR PRCI JTAG p Figure 1 SMCS332SpW Block Diagram Target applications are heterogeneous multi processor systems supported by scalable interfaces including the little big endian byte swapping The SMCS332SpW connects modules with different processors e g ADSP21020 SHARC ERC32 TMS320C40 Any kind of network topology could be realized through the high speed point to point SpaceWire links see chapter Applications in sectioon 2 8 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2
78. bits 5 0 will be incremented by 1 All Rights Reserved Copyright per DIN 34 ASTRIUM SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 55 of 131 5 7 2 SMCS332SpW receive time code Status bits 5 6 or 7 in register TIME CNTRL will be set when the SMCS332SpW receives a time code character over link1 2 or 3 If bit 2 ofthe TIME CNTRL register is set the received time code will be written in the TIME CODE register Interrupt generation See also interrupt bit in ISR Byte 3 bit 6 TIME CNTRL TIME CNTRL Description Bitl Bu 0 0 No interrupt signal to the interrupt controller 0 1 Generates an interrupt signal to the interrupt controller for a valid TIME CODE register bit5 0 1 received TIME CODE character received from the SpaceWire links 1 0 Generates an interrupt signal to the interrupt controller for all received TIME CODE characters 1 1 Generates an interrupt signal to the interrupt controller for a invalid TIME CODE characters received from the SpaceWire links 5 8 SMCS332SpW Version Control The Software needs often the capability to check which version of the SMCS332 is used the new SMCS332SpW or the older SMCS332 The solution for this problem is the SW can use the new TIME CNTRL register In the old version ofthe SMCS332 there is no register on this address therefore when the software wr
79. bute INSTRUCTION DISABLE of SMCS HIGHZ attribute IDCODE REGISTER of SMCS entity is entity is entity is 0010 amp Version 0100010001010011 amp Part number 00001011000 amp ID of manufacturer nius required by IEEE Std 1149 1 1990 attribute REGISTER ACCESS of SMCS BSREG EXTEST SAMPLE amp BOUNDARY EXTEST SAMPLE amp IDREG IDCODE amp BYPASS BYPASS HIGHZ BPREG BYPASS HIGHZ attribute BOUNDARY CELLS of SMCS BC dss BC 1 output control BC 1 attribute BOUNDARY LENGTH of SMCS attribute BOUNDARY REGISTER of SMCS num cell port func safe 232 BC 1 HOSTBIGE input X 231 BC 1 CLK10 input X 230 BC 1 RESET input X 229 BC 1 CLK input X 228 BC 1 BYPPLL input X input entity is entity is entity is 233 entity is ccell disval rslt OR n n n n f m m m All Rights Reserved Copyright per DIN 34 A EADS SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM Updated 9 Sep 2006 Page 94 of 131 227 BC 1 TIME C SY input X amp 226 BC 1 LSO3 output2 X amp output2 for internal tristate 225 BC 1 LDO3 output2 X amp 224 BC 1 LSI3 input X E 223 BC 1 LDI3 input X amp 222 BC 1 LSO2 output2 X amp 221 BC 1 LDO2 output2 X amp 220 BC 1 T
80. byte byte 4 forth header byte byte 5 ignored NOT transmitted byte 6 ignored NOT transmitted byte 7 ignored NOT transmitted byte 8 first data byte byte n last data byte transmitted packet via SpaceWire byte 1 byte4 4 header bytes byte 8 byten data bytes EOP Example2 No data bytes short packets CHx CNTRLI 0x20 The header field consist of a first byte which contains the number of header bytes value 2 and 2 header bytes give in total 3 bytes The first 4 bytes comprise the header field However the number byte and the last byte of the 4 byte in total will be NOT transmitted byte 0 2 number of following header bytes NOT transmitted byte 1 first header byte byte 2 second header byte byte 3 ignored NOT transmitted NO data byte transmitted packet via SpaceWire byte 1 byte 2 like data bytes EOP Example3 with checksum generation CHx CNTRLI 0x30 The header field consist ofa first byte which contains the number of header bytes excluded from checksum generation value 3 and 3 header bytes give in total 4 bytes byte 0 2 3 number of following header bytes excluded from checksum NOT transmitted byte 1 header byte byte 2 header byte All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 53 of 131 byte 3 header byte byte 4
81. cku 1 tax 2 5 tax ns 5 24 Notes D To achieve the above timing tywwx without hardware it may be necessary to avoid two subsequent write accesses to the HOCI port e g by a NOP or any other instruction between two HOCI writes depending on the type and clock frequency of the CPU Signal HACK active when HRD low and HSEL low and SMCSADR SMCSID Signal HACK disable when HRD high or HSEL high or SMCSADR z SMCSID Veco 7 3 3 V 0 3V All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 76 of 131 Description Symb HSEL HWR and SMCSADR and HADR setup before CLK high HADR SMCSADR hold after HSEL or HWR high HWR pulse width high 6 HACK low after HWR HSEL active and SMCSADR valid 2 Iwan 000 Im o 41 HACK disable after HWR or HSEL inactive or SMCSADR invalid 3 Le HDATA setup before HSEL or HWR high or SMCSADR tuwpsu 7 SMCSID HDATA hold after HWR or HSEL inactive or SMCSADR invalid HACK high after HSEL and HWR and SMCSADR SMCSID 5 Notes D To achieve the above timing tywwx without hardware it may be necessary to avoid two subsequent write write accesses to the HOCI port e g by a NOP or any other instruction between two HOCI writes depending on the type and clock frequency of the CPU Signal HACK active when HRD
82. configuration of the maximum transmit bit rates between 80 and 200MBit s see also Channel specific mode register The reset value of the register 0x0A results in a transmit bitrate of 100 MBit s The Transmit bitrate register can be configured between 80 and 200 MBit s in 20 MBit steps as follows ww 6 1 3 SMCS332SpW Interrupt Status Register ISR This register contains all interrupt status information It should be read out initially after reset to clear all illegal latched interrupts All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 57 of 131 6 1 4 SMCS332SpW Interrupt Mask Register All interrupts are masked after reset The interrupt mask bits are located according to their pendants in the ISR A 1 written to the IMR enables the corresponding interrupt in ISR to be activated towards the CPU via the signal HINTR 6 1 5 Channel specific configuration registers The channel specific registers are configurable independently This allows flexible communications with different nodes at the same time The following registers are the most important to be set x stands for Channel no 1 2 or 3 6 1 5 1 SpaceWire Mode Register CHx DSM MODR The basic function of this register is to select the transmit speed Bit 3 enables the divider bit 2 to 0 for transmit bit
83. cured 0 usage smcs reg write SMCS base address register address value configure COMI Channel 1 32 bit words transmit port followed by EOP 16 bit receive port stop RX generator after EOP reception no sign expand smcs reg write SMCS CH1 COMICFG 0x13 Channel 2 32 bit word receive port no RX generator stop after EOP reception no Sign expand smcs reg write SMCS CH2 COMICFG 0x70 set interrupt mask only access on SMCS IMRO with 32 bit HOCI disable CH1 TX generator finished CH1 RX EOP EEP received All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 Kos SMCS332SpW Doc No SMCS_ASTD_UM_100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 60 of 131 lt CH2 RX generator finished gt SI smcs reg write SMCS SMCS IMRO 0x2014 select transmit rate to max Transmit bitrate smcs reg write SMCS CH1 DSM MODR 0x08 smcs reg write SMCS CH2 DSM MODR 0x08 start the links smcs reg write SMCS CH1 DSM CMDR 0x02 smcs reg write SMCS CH2 DSM CMDR 0x02 start transfers wait for interrupts smcs reg write SMCS CH1 TX SAR 0x00 smcs reg write SMCS CH1 TX EAR OxO0F smcs reg write SMCS CH1 RX SAR 0x100 smcs reg write SMCS CH1 RX EAR Ox13F smcs reg write SMCS CH2 RX SAR 0x200 smcs reg write SMCS CH2 RX EAR Ox2FF while 1 static int Cl coun
84. d SMCS332 The new ECSS E 50 12A SpaceWire standard used by the SMCS332SpW and the IEEE 1355 standard used by the old SMCS332 are compatible however the old SMCS332 has a slightly different startup behavior the SMCS332 must be started first on a link connecting with the SMCS332SpW All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 14 of 131 3 TheSpaceWire link The SpaceWire standard AD1 defines a full duplex bit serial point to point link with a raw transmit rate of up to 400 Mbit sec The link consists of 2 signals in each direction one for strobe and one for data By coding the strobe that it only changes level when the data does not clock recovery and data synchronization can be achieved by XOR ing of data and strobe signals without having the need to run the strobe at very high frequencies The Character level defines the data and control characters used to manage the flow of data across a link The exchange level of the protocol is used to implement flow control which avoids overflow ofthe front end buffers Also error detection is provided by implemented parity checks during transmission and by timeout supervision in case of inter connect failures The SpaceWire standard aims only to define a transport medium between two nodes and covers the protocol layers only up to the packet level This has
85. d TIME CODE controls the receiving and transmitting of time code characters A time code on the SpaceWire links consists of an ESC control character and a data character the time code value The time code consists of the 6 bit time field bitO0 bit5 and two bits control flags 5 7 SMCS33SpW transmit time code After writing of a new value to the TIME CODE register the time code interface will send this new value to the 3 SpaceWire interfaces The SpaceWire interface will send the time code only when it is in the RUN state A second way to send the time code is the TIME CODE SYNC signal If bit 3 ofthe TIME CNTRL register is set a falling edge ofthe TIME CODE SYNC input signal sends the content of the TIME CODE register over the active SpaceWire links If bit 4 ofthe TIME CNTRL register is set the value ofthe TIME CODE register will be incremented by 1 after the transmitting of the TIME CODE value TIME CNTRL TIME CNTRL Description Bit3 Bit4 0 0 No time code will be send after the falling edge of the TIME CODE SYNC signal 0 1 No time code will be send after the falling edge of the TIME CODE SYNC signal and the value of the TIME CODE will not be incremented 1 0 A falling edge of the TIME CODE SYNC input signal sends the time code register value over the active SpaceWire links 1 1 A falling edge of the TIME CODE SYNC input signal sends the time code register value over the active SpaceWire links and the TIME CODE register
86. d interprets in protocol mode the four header data characters received after an EOP control character If the address field matches the link channel address and the command field contains a valid command then forwarding of data into the receive FIFO is enabled If the command field contains a simple control command then the execution request is forwarded to the command execution unit The protocol execution unit also enables forwarding of header data characters to the acknowledge generator and provides an error signal in case of address mismatch wrong commands or disabled safety critical simple control commands The protocol execution unit is disabled in transparent or wormhole routing operation mode Receive Transmit Acknowledge the transmit and receive FIFOs decouple the SpaceWire link related operations from the SMCS332SpW related operations in all modes and such allows to keep the speed of the different units even when the source or sink of data is temporarily blocked In the protocol mode a further FIFO acknowledge FIFO is used to decouple sending of acknowledges from receiving new data when the transmit path is currently occupied by a running packet transmission Command Execution Unit This unit performs activating resp deactivating of the CPU reset and the specific external signals and provides the capability to reset one or all links inside the SMCS332SpW all actions requested by the decoded commands from the protocol ex
87. dth is equal to the HOCI data port width The FIFO has a size of 32 bytes The host processor can control the data transfer with byte 1 bits 0 and 1 of the interrupt status register ISR or with the status bits 2 and 3 of the channel 1 status register CH1 STAR Bit 4 or 5 of the channel 1 status register CH1 STAR signals whether a EOP or EEP character was received 4 2 2 24 Channel 1 Status Register CH1 STAR address Ox2F data width 6 bit D5 0 access mode read only reset value 0x01 SE ene FO a oterassa gt mete FO is uts or eetebe SSCS rsoreswremesema O s eeen 1 4 2 3 Channel 2 Registers see 4 2 2 Channel 1 Register 4 2 4 Channel 3 Registers see 4 2 2 Channel 1 Register All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 42 of 131 4 25 Time Code Registers 4 2 5 1 Time Code Control Register TIME CNTRL address 0x78 data width 8 bit D7 0 access mode D4 0 read write D7 5 read only reset value 0x00 mem OSC SOU Interrupt control bits 00 No interrupt signal to the interrupt controller 01 enable the internal interrupt signal generation to the interrupt controller only for a correct received TIME CODE character received from the SpaceWire links enable the internal interrupt signal generation to the interrupt con
88. e 2 is connected with pin HDATA23 HDATAI6 register byte 3 is connected with pin HDATA31 HDATA24 Big endian mode selected 8 bit data port default after reset register byte 0 is connected with pin HDATA31 HDATA24 16 bit data port register byte 0 is connected with pin HDATA31 HDATA24 register byte 1 is connected with pin HDATA23 HDATA16 32 bit data port register byte 0 is connected with pin HDATA31 HDATA24 register byte 1 is connected with pin HDATA23 HDATA16 register byte 2 is connected with pin HDATAI15 HDATA8 register byte 3 is connected with pin HDATA7 HDATAO The registers of the SMCS332SpW are 1 2 or 4 Bytes wide That means if the HOCI data port is in 8 bit mode 4 read or write accesses are necessary to access a 4 Byte register e g the interrupt mask register In 16 32 bit mode the data bits 31 8 are 0 if an 8 bit register is read All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW DocNo SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 45 of 131 5 2 COMI Data Transfer Big Little endian selection of the COMI is done using bit 2 of SICR When SICR 0x00 Bit 2 0 the COMI data port is in little endian mode When SICR 0x00 Bit 2 1 the COMI data port is in big endian mode Little endian mode selected 8 bit data port default after reset byte 0 is transferred via CMDATA7 C
89. e contents of the register CHx RT ADDR ofthe two other channels If the address byte matches with one of the three register contents the packet will automatically forwarded to this link or the internal receive FIFO If the address byte does not match with the contents of one of the three registers the packet is forwarded to the internal receive FIFO and an error interrupt 1f enabled will be raised The figure below shows the address comparator In the figure a packet comes in on channel 2 The leading byte address byte is compared with the contents of register CH2 ADDR CHI RT ADDR CH3 RT ADDR and removed from the packet If the address byte matches with the contents of one of the register the packet is routed along this channel If the address byte does not match at all the packet 1s routed to channel receive fifo and an interrupt is raised All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 51 of 131 channel 1 transmit section CHANNEL 2 channel 2 m gt receive fifo address comperator select channel 3 R transmit OP nDNA JROUEE ADDR xczmg gt CHI RLADD ROUTE ADDR CH2 ADDR section CHA RT ADDR 5 5 4 SMCS332332SpW Routing Examples When routing it is recommended that each of the following registe
90. ead address 0x04 to 0x07 16 bit mode Read address 0x04 and 0x06 32 bit mode Read address 0x04 What is the use of SMCS332SpW signals CPUR and SES 3 0 These signals could be used as user defined flags Examples of possible uses are contained in the All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 EAD el SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 88 of 131 SMCS332SpW protocol specification see Appendix B When using the SMCS332SpW internal link loopback test mechanism do the link signals propagate outside the SMCS332SpW A Yes but you can avoid this by using the CHx DSM TSTR register bit 4 link output mute On which datalines are bytes received on SMCS332SpW serial link transferred into the DPRAM through the COMI A Suppose receiving 4 bytes ByteO to Byte3 on serial link Byte0 being the first one Note that the order of the data within one byte is the same in both little and big endian mode The most right line carries the least significant and the most left line carries the most significant bit Little endian COMI data port is set to 32 Bit width datalines 31 24 23 16 15 8 7 0 Byte3 Byte2 Bytel ByteO COMI data port is set to 16 Bit width datalines 31 24 23 16 15 8 7 0 00 00 Bytel ByteO if CHx COMICFG bit 7 0 00 00 Byte3 Byte2 FF FF Bytel ByteO if CHx COMICFG bit 7 1 and Bytel Bit 7 1 00 00 Byte3 Byte2
91. eception of the end of packet marker of the received packet and forwarded to the transmission segment of the link channel If data and acknowledge packets compete on access to the transmission segment acknowledge packets have precedence but can occupy the transmission segment only after the previous transmission has been finished Since a currently running transmission cannot be interrupted a significant delay between end of the received packet and transmission of the acknowledgement can occur All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 119 of 131 Complex Commands Issuing complex commands results in two acknowledges the low level acknowledge of the successful reception of the data packet containing the complex command and a high level acknowledge contained in a response data packet with information on e g the execution of the command Note that this high level acknowledge also releases a low level acknowledge indicating that the high level acknowledge data packet has been received The content and coverage of the high level acknowledge can be defined by a specific implementation but regarding sending complex commands the same policy holds as for simple commands a complex command can only be issued if the last acknowledge of a previous data transmission or the acknowledge of a pr
92. ectly for all speeds from 1 25 Mbps 100 Mbps All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 82 of 131 9 10 Test Port JTAG trok TCK t t TCKH TCKL t t TIS TIH gt TMS TDI tmo mo t TRST TRST t YSS lover INPUTS OUTPUTS Vec 5 V 0 5V TCK period trc Resa ws 8 s Trex viantoy ee 9 e TMS TDI hold after TCK high tri TDO delay after TCK low trpo Vec 73 3 V 0 3V TCK period TCK width high Uwsopmeaeran m 8 1 Dmosaaw ge m 19 1 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 83 of 131 TRST pulse width TETEN SEENEN SMCs musos ater roemen Sid tw m SMCs Oupas dey aterro iw wo id Note The BSDL file is printed in the Annex of this document All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 84 of 131 10 Mechanical Data 10 1 Package Dimensions SYMBOL INCHES EOM MM MM EN
93. ecution unit The unit contains a register controlling the enable disable state of safety critical commands which is set into the enable state upon command request and which is reset after a safety critical command has been executed The CPU reset and the specific external signals are forwarded to the Protocol Command Interface PRCI 2 6 Fault Tolerance The SpaceWire standard specifies low level checks as link disconnect credit value sequence and parity at token level The SMCS332SpW provides through the Protocol Processing Unit features to reset a link or all links inside the SMCS332SpW to reset the local CPU or to send special signals to the CPU commanded via the links Additionally it is possible to enable a checksum coder decoder to have fault detection capabilities at packet level 2 7 Software Support The SMCS332SpW is supported by VSPWorks from Wind River a commercially available distributed real time kernel It is a multi tasking as well as a multi processor Operating System The main goals are to enable programming at a higher level to configure and to perform communication and to administer the tasks on a board with multiple processes running in parallel The VSPWorks kernel supports multiple processors and application specific chips e g the SHARC ADSP21020 TMS320C40 SPARC ERC32 etc Thus it is possible to run a heterogeneous multiprocessor system with a single Operating System without consideration of the hardware platf
94. ed the host data bus functions as a 32 bit general purpose interface GPIO Protocol Command Interface PRCI that collects the decoded commands from all PPUs and forwards them to external circuitry via 5 special pins JTAG Test Interface that represents the boundary scan testing provisions specified by IEEE Standard 1149 1 ofthe Joint Testing Action Group JTAG The SMCS test access port and on chip circuitry is fully compliant with the IEEE 1149 1 specification The test access port enables boundary scan testing of circuitry connected to the SMCS I O pins All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 11 of 131 2 2 Operation Modes According to the different protocol formats expected for the operation of the SMCS332SpW two major operation modes are implemented into the SMCS332SpW The operation modes are chosen individually for each link channel by setting the respective configuration registers via the HOCI or via the link Transparent Mode default after reset This mode allows complete transparent data transfer between two nodes without performing any interpretation of the data bytes and without generating any acknowledges It is completely up to the host CPU to interpret the received data and to generate acknowledges if required The SMCS332SpW accepts EOP and EEP control tokens as
95. ee i HR re Ter i eos 23 4 2 1 SMCS332SpW Interface Control Register SICR eese nre 23 4 2 1 2 Transmit bitrate base Register TRS CIR 23 4 2 1 3 Route Control Status Register RT CIR 24 4 2 1 4 Interrupt Status Register USR 24 4 2 1 5 Interrupt Mask Register IMR sesssssessesseeseeeereneren enn enne eren rnnt 27 4 2 1 0 COMI Chip SelectO Boundary Register COMI CSO 27 4 2 1 7 COMI Arbitration Control Register COMI ACHT 27 4218 PRCIRegiter PRCIR isei iinei oeaiei epa eiaa ae ea ed Aien Lie EEs Dese 28 4 2 2 Channel T Registers EP 29 4 2 2 1 Channel 1 SpaceWire Mode Register CH1 DS8M MODR seen 29 4 2 2 2 Channel 1 SpaceWire Command Register CHI DSM CMDR eene 29 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 4 of 131 4 2 2 3 Channel 1 Link SpaceWire Status Register CH1 DSM STAR eene 30 4 2 2 4 Channel 1 SpaceWire Test Register CHI DSM TSIR nennen 31 4 2 2 5 Channel 1 Address Register CH1 AIDDR 31 4 2 2 6 Channel 1 Route Address Register CH1 RT ADDR seen 32 4 2 2 7 Channel 1 Protocol Status Register CH1 PR STAR sse nennen 32 4 2 2 8 Channel 1 Control Register 1 CH1 CNTRLI eene nre nenne 33 4 2 2 9 Channel 1 Control Register 2 CH1 CNTRLI A 34 4 2 2 10 Channe
96. el Command Register CHx COMICFG Channel COMI Configuration Register The Channel Mode Register is basically used to select the transmit bitrate of the link Then the link can be started by setting up the Channel Command Register No data is transmitted yet but the link sends NULL s and exchanges Flow Control Tokens with the opposite node if started as well The Channel COMI Configuration Register determines the word width of the COMI data bus basically Furthermore it configures whether one or more packets fit into one Communication Memory segment In the first case the SMCS stops the RX address generation after receiving an EOP EEP and for the reception of another packet the receive channel must be set up again In the second case the packets are appended and the SMCS332SpW only signals that the end of the segment is reached RX generator finished The CPU User must have the knowledge to separate the packets itself Example 1 Link no 1 shall transmit two packets of 16 words a 32 bit with the maximum bit rate The same link shall be configured to receive one packet of up to 64 words a 16 bit Link no 2 shall collect 32 bit word packets in the COMI segment without signaling reception of every packet The transfers run via the COMI in little endian mode default The Communication Memory is segmented in three parts The excerpt of a Pseudo C code looks like this init chi rx int occured 0 chi tx int occured 0 ch2 rx int oc
97. equester Packet DEST CNTRL TID SRC EOP CNTRL Simple Command Request refer to para 5 2 Actions Execute the requested simple command DEST SRC SRC DEST CNTRL Transaction OK or in case of errors CNTRL Transaction Error Response Acknowledge Packet All Rights Reserved Copyright per DIN 34 ASTRIUM EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 User Manual Updated 9 Sep 2006 Page 129 of 131 13 6 Glossary Communication Memory Part of a node s working memory reserved for communication Computing Node Controlling Node Level 0 Level 1 Level 2 Level 3 Level 4 Link Interface Unit Link Interface Node Requester Responder Working Memory A node which performs only computing tasks A node which is allowed to perform system control tasks A controlling node may also perform computing tasks Signal Level Character Level Exchange Level Packet Level Transaction Level Integrated Unit single chip MCM consisting of multiple link interfaces Circuitry to connect a node to one physical DS SE link channel consists generally of a SpaceWire link frontend a protocol controller and interfaces to the node CPU Entity of a multiprocessor system consists of a CPU memory and multiple link interfaces The term is used in the communication related view of a multiprocessor system The link interface which sends a request packet
98. ess 0x01 base frequency selection 0 transmit bitrate 10 Mbit s frequency of signal CLK10 after reset 1 for transmit bitrate see bits 2 0 always 0 reserved E always 0 reserved always 0 reserved 7 test mode if set enables access to test register CHI DSM_TSTR Note When reprogramming the link speed it is recommended to wait at least 800 ns between two subsequent changes of link speed It is also recommended to program only single steps 1 e when switching from 1 1 to 1 32 link speed it should be done in steps from 1 1 to 1 2 1 4 1 8 1 16 and then 1 32 each with a 800 ns pause between two steps This register will keep its contents also when TRS_CTRL is modified 4 2 2 2 Channel 1 SpaceWire Command Register CH1 DSM CMDR address 0x11 data width 4 bit D3 0 access mode read write reset value 0x00 las Stop SpaceWire link if set the SpaceWire cell goes in the Error Reset state See ADI This bit is autoreset by itself 1 Start Space Wire link Starts the transmission of NULL s All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 30 of 131 pS This bit is autoreset by itself This bit have to be set after an error disconnect to restart the SpaceWire link or set also Bit 2 to automatically restart the link after an error
99. et may be passing through several nodes at one time thereby pipelining the transmission of the packet The term wormhole routing comes from the analogy of a worm crawling through soil creating a All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 50 of 131 hole that closes again behind its tail Wormhole routing is invisible as far as the senders and receivers of packets are concerned its only effect is to minimize the latency in message transmission The SMCS332SpW interprets the signals on its inputs as sequences of packets It takes the first byte of data as the header of the packet which determines what it will do with the whole packet The length and contents of the remainder of the packet are arbitrary The end of the packet is indicated by one of two distinguished termination characters called EOP and EEP route address packet body 0 or more byte EOP 1 byte 2 n byte The routing decision is taken as soon as the header of the packet has been input If the output link is free the packet without header is sent directly from input to output without being stored Ifthe output link is not free then the packet is buffered To exploit the full bandwidth ofthe internal pathways on the SMCS332SpW there is buffering on each path through the device The buffering is fully hand sh
100. evious simple command or the high level acknowledge of a previous complex command has been received No split transactions are allowed Control Word Content not Specified Ifthe content ofa control word in a requester packet is not specified according to the control word specification in para 5 then the rest of the packet up to the next EOP is ignored After reception of the EOP of the requester packet an acknowledge is sent back indicating an error The requesting node can interpret the mirrored content of the control word to recognize the unspecified control word 13 4 2 Access to Command Signal Output Ports Basically every link channel has its own set of command signal output ports The reset CPU and activate deactivate specific external signal commands of each link channel are forwarded to their command signal ports without any prioritization or other coordination In order to save pins when multiple link interfaces are integrated on one link interface unit chip the SESO SES3 signals of the different link channels can be combined in such a way that a logical or function is realized if one of the link interfaces activates one of the specific external signals then the respective signal at the output pin will be activated e g if one link interface activates SESO then the respective output pin 1s activated independent from the state of the other SESO signals from the other link interfaces In this case it is a task of the
101. first data byte included in checksum byte n last data byte included in checksum transmitted packet via SpaceWire byte 1 header byte byte2 header byte byte3 header byte byte 4 byten data bytes byte cl byte c2 2 checksum bytes EOP 5 6 2 Routing and Checksum Generation Assuming wormhole routing and checksum generation check is enabled The first header byte will be removed from the packet on each SpaceWire Router where the packet is routed through if header deletion is enabled If the header byte s is included in the checksum the two checksums will never be equal Therefore it is mandatory to exclude the header byte s from checksum if routing over Space Wire Router is combined with checksum generation The number of header bytes deleted during routing can range from one byte to several bytes This depends on the number of routers a packet is routed through In this case the SMCS332SpW generates two checksum bytes from the data bytes and appends these bytes at the end of the data bytes The SMCS332SpW at the other end of the virtual link generates again a checksum from the received bytes without the last 2 bytes and compares these with the received checksum last 2 bytes If routing is combined with checksum generation set bit 4 in the register CHx_CNTRL1 The SMCS332SpW will use the first byte of the incoming data to be transmitted from HOCI or COMI as number of bytes which should be excluded from checksum
102. g this document and contain background information relating to the subjects addressed Number Document RD1 Issue 2 21 04 1999 SMCS332 User Manual All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 8 of 131 1 3 List of Abbreviations AD Applicable Document API Application Programming Interface ASIC Application Specific Integrated Circuit CODEC COder DECoder COMI Communication Memory Interface DPU Data Processing Unit DSP Digital Signal Processor EOP End Of Packet EEP Error End Of Packet ESC Escape FCT Flow Control Token FIFO First In First Out FPGA Field Programmable Gate Array GPIO General Purpose Input Output JTAG Joint Testing Action Group HOCI Host Control Interface LVDS Low Voltage Differential Signalling LSB Least Significant Bit MSB Most Significant Bit PCB Printed Circuit Board PE Processing Element PPU Protocol Processing Unit PRCI Protocol Command Interface SIC Simple Interprocessor Communication SRAM Static Random Access Memory SSRAM Synchronous Static Random Access Memory SMCS Scalable Multichannel Communication Subsystem TBC to be confirmed TBD to be defined All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User M
103. he SMCS332SpW The level ofthe CAM signal determines which SMCS332SpW owns the COMI BUS is master and the other is slave The arbitration between the two SMCS332SpW follows a fair toggle and parking scheme This means if SMCS332SpW A got the communication memory bus after arbitration or after reset it parks on it until SMCS332SpW B sends a request over his COCO output active high to the COCI input of SMCS332SpW A SMCS332SpW B however sends only a request signal to SMCS332SpW A if it needs the COMI bus for memory transfers After completion of the current memory transfer from SMCS332SpW A the SMCS332SpW A COM interface becomes tristate and the SMCS332SpW A COCO signal goes inactive low After SMCS332SpW B receives the low level on its COCI it occupies the COMI bus and enables its COM interface drives the signals Now SMCS332SpW B parks on the bus until there is a request from SMCS332SpW A If a bus owner releases the bus after a request from the other SMCS332SpW it has to wait for N 1 Cycles N value from Register COMI ACR before it can request the bus again With the according values in the COMI ACR register the bandwidth of the communication memory data bus can be split between the two SMCS332SpWs Example COMI ACR SMCS332SpW A 4 COMI ACR SMCS332SpW B 8 both SMCS332SpW read data from the communication memory datawidth 32 bit CLK 25 MHz gt cycletime 40ns overall bandwidth 4 1 1 arbi
104. he source of the channel lerror interrupt bit 1 byte 0 of the interrupt status register ISR The channel 1 error source register 2 is readable and the bits are reset only by writing 1 thus ensuring status never gets missed by software E Simple Interprocessor Command SIC sequence error That means the SMCS332SpW received an unexpected acknowledge packet Received SIC packet with a wrong checksum only when generate checksum enabled bit 4 of register CHI CNTRL 1 received SIC packet has a wrong control byte eee dera packet wg ess ere hess enable bist fester H_CNTRLD always 0 reserved 4 2 2 14 Channel 1 COMI Configuration Register CH1 COMICFG address Ox1F data width 8 bit D7 0 access mode read write reset value 0x00 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 37 of 131 B pe transmit data port width 00 the COMI data port operates in transmit direction with 8 bit after reset each access of the COMI data port reads 8 bit from the communication memory the COMI data port works with 16 bit the COMI data port works with 32 bit for little big endian access of the COMI data port see bit 2 of register SICR send EOP control character at the end of the packet when bit 3 is not set which was read from the communication memory send also
105. how the routing is actually performed and how certain network events e g transmission errors or change of transmission speed are propagated via the router 13 3 Service Specification Based on this protocol data characters and simple system control commands are transported between nodes of a multiprocessor system The protocol does interpret control commands if they are coded as specified for simple control commands in para 5 Data transferred via the link is not interpreted by the protocol but exchanged transparently with the CPU ofa node This implies that every acknowledgement required by the content of the data must be performed by SW a higher level communication protocol running on the CPU Since this protocol does not interpret the data transferred between nodes specific functions and commands in addition to the ones specified in the description below can be freely embedded within the data The protocol is based on a packet communication structure it allows a full duplex transfer of data and commands 13 3 1 Transport of data between two nodes The transaction level protocol described here provides transport of data structured into packets between the endpoints of a communication link It does not interpret the data It is up to other here not specified parts of a higher transaction level protocol e g running on the CPU of the node to control the transfer data from the link interface to buffers in the working memory of a node
106. into the respective bits of an acknowledge control word Request Type and Command Specification Table All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 123 of 131 Req Command Specification Remarks Spec TEL reserved for future use Bit 3 0 are not interpreted Complex Command Request coded within the datafield Bit 2 0 are not interpreted Complex Command Acknowledge details coded in the datafield Bit 2 0 are not interpreted poo p De EELER pop p KREE hope pe pepesesesee 70000 5 p pp e e metet 5 pop po emen Ip pep pee Deactivate CPU Reset cep Reset Link Interface HW a f fo f fi fi ResetAl neger HW Activate Specific External Signal 0 Activate Specific External Signal 1 Activate Specific External Signal 2 1 Activate Specific External Signal 3 Deactivate Specific External Signal 1 EJ Deactivate Specific External Signal 0 o Deactivate Specific External Signal 2 Deactivate Specific External Signal 3 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 124 of 131 13 5 3 Link Interface Status Register Encoding General Layout of the Link Interface Status Register Bit 3 Bit 0
107. ion of the packet including the associated EOP marker and the forwarding of the data to the receive FIFO in the link interface It does not cover any operation related to memory access of the node CPU s working communication memory in case of simple commands the correct reception of the packet including the associated EOP marker the successful decoding of the command and the forwarding of the command to the command execution unit The acknowledgement covers additionally the cases whether or not the command execution unit has been enabled previously for safety critical commands or not In case of data transmission or transmission of simple commands the requesting node has to wait for the last acknowledge of a previous data transmission or the acknowledge of a previous simple command execution request or the high level acknowledge of a previous complex command before a new simple command execution request packet can be send In other words split transactions are NOT allowed Within this protocol only two forms of acknowledgement are required reception successful reception with errors or problems with the execution of the requested command If the second form of the acknowledgement is received it is up to the requester node to read the status register of the responder node in order get more information about the malfunction The acknowledge packet structure is defined in para 5 The acknowledge packet is generated immediately after the r
108. ites the value 0x01 to this address they will read the value 0x00 from the old SMCS332 and 0x01 from the new SMCS332SpW All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 56 of 131 6 Programming and Operation Modes This section contains the descriptions how to operate the SMCS332SpW from the programmers point of view together with some code examples 6 1 SMCS332SpW Initialization After power up or any other reset the configuration registers of the SMCS332SpW are set to their default values see chapter register description For proper operation each application has to adapt them according to their specific needs The following list shows registers that are important for the SMCS332SpW initialization It represents a configuration guideline for the configuration subsystem Each register description is accompanied by an exemplary value 6 1 1 SMCS332SpW Interface Control Register This register determines the HOCI data bus width and the COMI data bus endian mode This register should be the first to be configured to ensure proper SMCS332SpW operation Setting the HOCI port to 32 bit all internal registers are accessible with one read or write operation in 8 bit mode each byte of a 16 or 32 bit register must be accessed separately 6 4 2 Transmit Bitrate Register TRS CTRL This allows
109. kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxkk CHAIN CELL PIN DATA DATA SELECT CONTROL DISABLE POS NAME NAME INPUT OUTPUT POS POS VALUE kk 232 BC 1 INPUT HOSTBIGE 7 231 BC 1 INPUT CLK10 Eh 230 BC 1 INPUT RESET p 229 BC 1 INPUT CLK nau 228 BC 1 INPUT BYPPLL 168 227 BC 1 INPUT TIME C S 192 226 BC_1 INPUT LSO3 191 gt 225 BC_1_INPUT LDO3 190 224 BC_1_INPUT LSI3 189 223 BC_1 INPUT LDI3 188 x 222 BC 1 INPUT LSO2 TOY 221 BC 1 INPUT LDO2 186 220 BC 1 INPUT TEST 182 219 BC 1 INPUT LSI2 181 218 BC 1 INPUT LDI2 180 217 BC_1 INPUT LSO1 KS EC S 216 BC 1 INPUT LDO1 178 215 BC_1 INPUT LST1 ny 214 BC 1 INPUT LDI1 176 213 BC 1 INPUT NCC 3VOLT 169 212 BC 1 INPUT Nun 211 BC 1 INPUT CMDATA31 166 210 BC_1_INPUT CMDATA31 166 gt 209 BC_1_INPUT CMDATA30 365 208 BC_1 INPUT CMDATA30 165 207 BC 1 INPUT CMDATA29 164 206 BC 1 INPUT CMDATA29 164 205 BC 1 INPUT CMDATA28 163 i 204 BC 1 INPUT CMDATA28 163 203 BC 1 INPUT CMDATA27 162 212 212 212 212 212 All Rights Reserved Copyright per DIN 34 A EADS ASTRIUM SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 105 of 131 202
110. l internal registers of the SMCS332SpW can be written Read Command 7 6 0 1 register address ignored EOP 1 byte 2 n byte Read Response Packet 7 6 0 register address register value EOP 1 byte 2 byte Write Command 7 6 0 oS register address write data ignored EOP 1 byte 2 byte 3 n byte All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW DocNo SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 49 of 131 5 4 4 Host Data Bus GPIO Port If the SMCS332SpW is in remote mode the HOCI cannot be used to control the SMCS332SpW locally Instead the 32 bit wide data bus of the HOCI can be used as GPIO port Four registers are provided to control the direction of each line of the 32 bit wide GPIO port This means that each line of the GPIO port can be configured as input or as output After a reset the GPIO port is configured that all lines are input lines In addition four extra registers are provided to write data to the GPIO port outputs and to read data from the GPIO port inputs The GPIO port outputs are latched so that the value written to a specific bit will not change unless programmed accordingly As an example a single shot pulse on one of the GPIO output lines 0 1 0 needs to be programmed remotely by writing a 0 a l and another 0 to the appropriate GPIO register The pul
111. l 1 Header Transaction ID CH1_ HTID enne nnns 35 4 2 2 11 Channel 1 Header Control Byte CH1 HCONTRL esee eene eene 35 4 2 2 12 Channel 1 Error Source Register 1 CH1 ESRI ene 35 4 2 2 13 Channel 1 Error Source Register 2 CH1_ESR2 ssesssessesseeeeenenn enne 36 4 2 2 14 Channel 1 COMI Configuration Register CH1 COMICEG sse 36 4 2 2 15 Channel 1 Transmit Start Address Register CH1 TX BAR 37 4 2 2 16 Channel 1 Transmit End Address Register CH1 TX EAR eene 38 4 2 2 17 Channel 1 Transmit Current Address Register CH1 TX CAR eene 38 4 2 2 18 Channel 1 Transmit FIFO CH1 TX FIFO sseseseesseeeeeeneeneenen nennen nnne nnn 39 4 2 2 19 Channel 1 Transmit EOP Bit Register CH1 TX EOP I eene 39 4 2 2 20 Channel 1 Receive Start Address Register CH1 RX SAR sse 39 4 2 2 21 Channel 1 Receive End Address Register CH1 RX EAR esee 40 4 2 2 22 Channel 1 Receive Current Address Register CH1 RX CAR 40 4 2 2 23 Channel 1 Receive FIFO CH1 RX FIFO sees nennen enne nre nre nenne 41 4 2 2 24 Channel 1 Status Register CH1 STAR sese eene enne nennen 41 4 2 3 Channel 2 Reglsters uude errore pene eeh 41 4 2 4 Channel E RIEN Em 41 4 2 5 Time Code Registers eet eidele 42 4 2 5 1 Time Code Control Register TIME CNTRL seseeseeee eere 42 4 2 5 2 Time Code Value Register TIME CODE 42 SMUSS332S DW MD M 44 5 1
112. l status register is read via the link the content of the register must be kept constant during the read operation Change of the link channel status register during a read operation is not allowed Some entries in the status register are transient in the sense that they are reset after a read This holds especially for some error information which is regarded as invalid when it has been read Details are given in para 5 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 122 of 131 13 5 Encoding Format of Transactions 13 5 1 Header and EOP Coding DEST Destination address of the packet 8 bit field CNTRL 8 bit control word for commands and acknowledges according to para 5 2 TID Transaction identifier of the packet Unique number generated by the requester to identify acknowledges 8 bit field SRC Source address of the packet 8 bit field EOP End of Packet marker 13 5 2 Control Word Coding Specification 7 MSB Request Acknowledge Packet 0 Acknowledge 1 Request Acknowledge OK or Error 0 Transaction Error Acknowledge 1 OK Acknowledge This bit is not interpreted if the packet is a request packet Request Type Packet Specification see table below Command Specification see table below Detailed Command Specification see table below Bits 5 0 are simply mirrored
113. n mom HDATA12 HDATA12 59 omn HDATA11 HDATA11 56 77 76 75 72 71 70 g9 ngg 67 nga 63 g2 61 60 59 56 58 All Rights Reserved Copyright per DIN 34 A EADS SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM Updated 9 Sep 2006 Page 108 of 131 55 BC 1 INP ln 54 BC_1_INP HDATA10 55 55 53 BC_1_INP HDATA10 55 B 52 BC 1 INP ln 54 BC_1_INP HDATA9 54 52 50 BC 1 INP HDATA9 54 49 BC 1 INP ln 48 BC 1 INP HDATA8 53 49 47 BC 1 INP HDATA8 53 46 BC 1 INP ln x 7 z 45 BC_1_INP HDATA7 52 46 44 BC_1 INP HDATA7 52 43 BC 1 INP ln 42 BC 1 INP HDATA6 ag 43 41 BC_1 INP HDATA6 ag 40 BC 1 INP ln 5 z 39 BC_1_INP HDATA5 48 40 38 BC_1_INP HDATA5 48 37 BC 1 INP ln 7 7 36 BC_1 INP HDATA4 a7 37 35 BC_1 INP HDATA4 a7 34 BC 1 INP ln 33 BC_1_INP HDATA3 46 34 32 BC 1 INP HDATA3 46 8 31 BC 1 INP ln 7 7 30 BC_1 INP HDATA2 Si a5 31 29 BC_1 INP HDATA2 a5 28 BC 1 INP ln 7 z 27 BC 1 INP HDATA1 44 28 26 BC 1 INP HDATA1 44 25 BC 1 INP ln 24 BC 1 INP HDATAO a3 25 23 BC_1 INP HDATAO a3 22 BC_1 INP SMCSID3 40 21 BC_1 INP SMCSID2 39 20 BC 1 INP
114. n occurs see CH1 ESRI For more information see chapter 5 5 7 0 Address of channel 1 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 32 of 131 4 2 2 0 Channel 1 Route Address Register CH1 RT ADDR address 0x15 data width 8 bit D7 0 access mode read write reset value 0x00 In wormhole routing mode The content of the channel 1 route address register builds the routing address of channel 1 and will be compared with the first byte of an incoming packet in the two other SpaceWire cells The result of the comparison is used to determine the destination of the packet It can be delivered to the internal channel FIFO or to one of the two other SpaceWire channels inside the SMCS332SpW For more information see chapter 5 5 Wl T register content will be compared with first byte of an incoming packet if routing 1s enabled 4 2 2 7 Channel 1 Protocol Status Register CH1 PR STAR address 0x16 data width 4 bit D3 0 access mode read only reset value 0x00 Shows status of internal protocol unit signals EE only when protocol mode enabled when set execution of critical commands is enabled 1 only when protocol mode enabled when set acknowledge packet is received 2 only when bit 3 of register CH1_CNTRLI is enabled protocol unit acknowledge F
115. n two nodes This protocol defines only the basic functionality of some complex commands the coding ofthese commands and execution details are up to a specific implementation It is likely that the complex control commands are executed by the SW kernel running on the node This document gives only a few constraints for complex command implementation Implementations of this protocol can define their own complex commands 13 3 2 1 Simple Control Commands Enable command execution For security reasons the execution of a set of safety critical simple commands must be enabled before a command can be executed A safety critical simple command is executed only after an enable command execution command has been received Activate CPU Reset This command activates an external static signal CPUR which brings the CPU of the node into its reset state This command must be enabled Deactivate CPU Reset This command deactivates an external signal CPUR which is set by the Reset CPU command and such enables restart of the CPU s command execution This command must be enabled Activate External Signal 0 3 This command activates one of four specific external signals SESO SES3 The interpretation of these signals is application dependent This command must be enabled Deactivate External Signal 0 3 This command deactivates one of four specific external signals SESO SES3 This command must be enabled Reset Link Interface H
116. ndicate a control character and 2 bits to indicate the type of control character One of the four possible control characters is the escape code ESC The ESC code is used to form control codes Two control codes are specified the NULL code and the time code The NULL code is transmitted whenever a link is not sending data or control characters The time code is used to distribute system time over a SpaceWire network which comprises a ESC control character followed by a single data character The DS Link protocol ensures that only one of the two wires ofthe data strobe pair has an edge in each bit time The levels on the data wire give the data bits transmitted The strobe signal changes whenever the data signal does not These two signals encode a clock together with the data bits permitting asynchronous detection of the data at the receiving end The data and control characters are of different lengths for this reason the parity bit in any characters covers the parity ofthe data or control bits in the previous characters and the control flag in the same character as shown in the above figure This allows single bit errors in the character type flag to be detected Odd parity checking is used Thus the parity bit is set unset to ensure that the bits covered inclusive of the parity bit see below figure always contain an odd number of 1 s The coding of the characters is shown in the table below To ensure the immediate detection of parity errors and t
117. nds must be enabled by a specific command This command activates a SW switch which allows the execution of one complex command If the switch is set or not can be read back by the respective read status command Set Link Speed to Maximum Set Link Speed to Minimum These two commands are required since it is assumed that the link interfaces accept in their receiver part transmission speeds between the minimum and maximum range specified in para 2 but that their transmission speed do not automatically follow the speed of the data received from the other node This has following effect in case of speed increase although one node is transmitting at full speed the link bandwidth is near its minimum value since the FCTs and acknowledgements from the other node are sent with minimum speed The node intending to change its transmission speed has to inform the other node so that their transmission speed can be adapted e g by CPU commands forwarded to the link I F HW The actual link speed is indicated in the status register This command must be enabled Note that the described simple procedure works only for direct connected systems but that systems incorporating a router require more complicated procedures e g by involving the system controller Shut Down Link Operation Restart Link Operation All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 EADS H Issue 1 4 ASTR
118. nel 1 detailed error source register 2 o Ire e hw e fea m le ig iF ar CH1_COMICFG channel 1 COMI configuration register Im Ire 20 1F ME CHI TX SAR channel 1 transmit Start Address Register CHI TX EAR channel 1 transmit End Address Register CHI TX CAR channel 1 transmit Current Address Register 2 5 26 26 26 CH1_TX_FIFO channel 1 transmit FIFO CH1_TX_EOPB channel 1 transmit EOP Bit Register CH1_RX SAR channel 1 receive Start Address Register 28 2B 2D i CHI RX FIFO channel 1 receive FIFO XXXXXXXX TO F CH1_STAR channel 1 Status Register All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 20 of 131 4 1 5 SMCS332SpW channel 2 status and control registers Port Width Register Function Address hex Lu r w r w N LAT wi C2 Lu N r w LA LA Lu AR LA AR LA CA LA Nn r w LA CH LA nN r w CH2 PR STAR channel 2 Protocol Status Register 04 Lu T r w CH2 CNTRLI channel 2 control Register 1 No oo N E CH2_CNTRL2 channel 2 control Register 2 LA A CH2 HTID channel 2 Header Transaction ID byte TO o LA B CH2 HCNTRL channel 2 Header control byte LA A r w CH2 ESRI channel 2 detailed error source register 1 CH2 ESR2 channel 2 detailed error source register 2 reserved JN CH
119. nell the received data from channel 1 is transmitted in the communication memory That means channell receive COMI address generator reach the value of the end address register CHI RX EAR channel 1 the EOP EEP character was received For more information refer to register CHI STAR bit 4 and 5 channel 1 reset channel 1 command received only if protocol mode enabled lex channel 1 transmit fifo is empty set after reset channel 1 transmit fifo is full The following interrupts are stored in byte of the ISR address 8 bit mode 0x05 16 bit mode 0x04 32 bit mode 0x04 ISR Byte 1 channel 1 receive fifo is not empty channel 1 receive fifo is full channel 2 SpaceWire parity disconnect ESC or credit error For more information refer to register CH2 DS8M STAR channel 2 SpaceWire status register channel 2 data from the communication memory are read That means channel2 transmit COMI address generator reach the value of the end address register CH2 TX EAR channel2 the received data from channel 2 is transmitted in the communication memory That means channel2 receive COMI address generator reach the value of the end address register CH2 RX EAR channel 2 the EOP EEP character was received For more information refer to register CH2_ STAR bit 4 and 5 channel 2 reset channel 2 command received only if protocol mode enabled The following interrupts are stored in byte 2 of the ISR All Rights Reserved
120. nnel Link SpaceWire Mode Register CH x DSM MODR register described in section 4 2 2 1 This arrangement allows each link to be run at different transmission speeds as shown in the table below shown for minimum and maximum link speeds Max Transmit Speed Link Speed Divider Link Speed Mbit s 3 4 Errors on links Link inputs can detect parity and disconnection conditions as errors A single bit odd parity system will detect single bit errors at the character level The protocol to transmit NULL s in the absence of other characters enables disconnection of a link to be detected A disconnection error indicates that the link has been physically disconnected an error has occurred on the link or at the other end of the link which may have then stopped transmitting The status bits in the CH x DSM STAR registers flags that a parity credit sequence ESC and or disconnect error has occurred on the link The errors can be detected independently When a SpaceWire channel detects a parity credit or sequence error it halts its output This is detected as a disconnect error at the other end of the link causing this to halt its output also Detection of an error causes the link to be stopped Thus the disconnect behavior ensures that both ends are stopped Each end can then be restarted All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User
121. o enable link disconnection to be detected NULL code are sent in the absence of other tokens All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 15 of 131 Data token Control token M D LI Parity bit Parity bit Control flag Data flag H Token type Data e g FCT h 1 Te H 0 0 1 1 1 0 1 0 l 0 Dr D i Data Strobe control characters control codes Null NULL ESC FCT P1110100 Time code ESC DATA P11110DDDDDDDD P Parity bit D Data bit 3 2 Character level flow control Character level flow control is performed in each Space Wire module and the additional flow control characters used are not visible to the higher level packet protocol The character level flow control mechanism prevents a sender from overrunning the input buffer of a receiving link Each receiving link input contains a buffer for at least 8 normal characters 16 normal characters of buffering is in fact provided Normal characters are data character and EOP EEP Whenever the link input has sufficient buffering available to consume a further 8 normal characters a FCT is transmitted on the associated link output and this FCT gives the sender permission to transmit of further 8 normal characters Once the sender has transmitted 8 normal characters it waits until it receives
122. ol E 55 Programming and Operation Modes scsscssssssssscsssssssscssnsssssssssssssssessssesessssnsecesssssessssssessssesssesssssessessessosees 56 6 1 KEE ET 56 6 1 1 SMCS332SpW Interface Control Register 56 6 12 Transmit Bitrate Register TRS CTRL secessit teen reta Evae IP RES Ee EEN deen 56 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW DocNo SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 5 of 131 6 1 3 SMCS332SpW Interrupt Status Register USR 56 6 1 4 SMCS332SpW Interrupt Mask Register 57 6 1 5 Channel specific configuration registerg rennen ener nneneen rennen enne 57 6 1 5 1 SpaceWire Mode Register CHx DSM MODR enne nnne nennen nnns 57 6 1 5 2 COMI Configuration Register CHx COMICFG sese nne 57 6 1 5 3 Control Register 1 CHX ENER eite enint aterert NEESS Sea rue Een HESE 57 6 1 5 4 SpaceWire Command Register CHx DSM CMDR eese nre 57 6 2 Data transfer via e EE 58 6 3 Data Transfer via HOCGLT ie ier n Ee REESE P Rte HER ERR EH EP E EE E PESE EP ERR EISE ERE ERREUR Ee 61 6 3 1 Special behaviour in case of SpaceWire link error sesessssssssesseeee eene eene 62 T Signal Descrip ptioi P 64 Electrical ju vii Dci T 67 6 1 Absolute Maximum Ratings e eee eei Wits Ee
123. onse Acknowledge Packet All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 126 of 131 13 5 5 ReadLink Interface Status Register Transaction Requester Packet CNTRL Read Link Interface Status Register Actions Reads the Link Interface Status Register DEST SRC SRC DEST CNTRL Transaction OK 4 BYTES DATA Content of Link Channel Status Register or in case of errors CNTRL Transaction Error Response Acknowledge Packet Normal Acknowledge DEST CNTRL 4 BYTES DATA EOP Error Acknowledge All Rights Reserved Copyright per DIN 34 D e SMCS332SpW ASTRIUM User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 127 of 131 13 5 6 Enable Command Execution Transaction Requester Packet CNTRL Enable Safety Critical Command Actions Enable the execution of a following safety critical command DEST SRC SRC DEST CNTRL Transaction OK or in case of errors CNTRL Transaction Error Response Acknowledge Packet All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 128 of 131 13 5 7 Critical Simple Command Execution Transaction R
124. orm All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW DocNo SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 13 of 131 2 8 Application The SMCS332SpW can be used for single board systems where standardised high speed interfaces are needed Even non intelligent modules such as A D converter or sensor interfaces can be assembled with the SMCS332SpW because of the control by link feature The complete control of the SMCS332SpW can be done via link from a central controller node The SMCS332SpW is a very high speed scalable link interface chip with fault tolerance features The initial exploitation is for use in multi processor systems where the standardization or the high speed of the links is an important issue and where reliability is a requirement Further application examples are heterogeneous systems as shown in Figure 2 or modules without any communication features as special image compression chips certain signal processors ADSP21020 MC56000 application specific programmable logic or mass memory Heterogeneous Systems These systems are often used for applications where different kind of tasks are to be processed Figure 2 below shows an application with multiple processing modules using the SMCS332SpW for interprocessor communication Figure 2 Multiprocessor System with SMCS332SpW link connections 2 9 SMCS332SpW connected with the ol
125. otice This document is the property of EADS Astrium GmbH and contains material proprietary to EADS Astrium GmbH The contents are for confidential use only and are not to be disclosed to any others in any manner in whole or in part except with the express written approval of EADS Astrium GmbH or to the provision of the relevant contract All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW DocNo SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 3 of 131 Table of Contents 1 Scope and Objectives Leere creer eee ee eene eee eese tn seta seta stets sns ssassn tasso setas etos tas e tas e ta seta stesse estne sns so seta se sss 7 1 1 Listof applicable documents ui RR HR aaah EdeEd E 7 1 2 Reference Documents ea tp pc e a a bea E E E ER E E a eo ea E 7 1 3 EE 6 2 Introducti n iioii iei ope ceb cete qued cesa p Top iQUCRD EUNT ene ab IND d ab AEE Rd DR ERREUR e Re Uen 9 2 4 D TA PU CA MD Ee ee tege eegene ee Eesen Ee ec 10 2 2 Operation Mod s UT 11 2 3 8MCS3325pW Control TE 11 2 4 Wo ormhol Trai rp X 11 2 3 PPU Functional Description teen ette Ite MEUSE Ve EEGENEN 12 2 6 Fault Tolerate srren 12 2 7 e EE 12 2 8 rni mm 13 2 9 SMCS332SpW connected with the old SMCS332
126. pyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 110 of 131 12 Handling Empty Packets 12 1 Description Due to an anomaly in the SpaceWire CODEC Coder Decoder version 1 4 which is used in the SMCS332SpW the SMCS332SpW behavior is affected when more than one empty packet is received in a row In this case the credit count is not updated correctly Please note that empty packets are normally not expected The SMCS332SpW never transmits empty packets however the problem may occur when the SMCS332SpW receives empty packets For example if lt data gt lt EOP gt lt EOP gt lt EOP gt is received then the receive credit counter is incremented only for one EOP However the transmit credit counter at the other end ofthe link would have been incremented once for each EOP This gives rise to a discrepancy between the two FCT counters The handling of empty packets 1s specifically mentioned in the SpaceWire standard sub clause 8 9 3 EOPs and EEPs should always be counted in the credit counter sub clause 8 3 1 EOPs and EEPs are NChars This means that the SpaceWire CODEC version 1 4 and therefore the SMCS332SpW are NOT fully compliant with the SpaceWire standard Detailed Description The SMCS332Spw has space for 16 characters in the receive buffer After reading 8 characters data or EOP EEP from the receive buffer a FCT
127. r Manual Updated 9 Sep 2006 Page 62 of 131 Example 2 The following two C code routines show a handling of transferring small packets m SMCS number n channel number define TXfull 0x02 define RXnotEmpty 0x04 define RXrecvEOP 0x60 int smcs fifo read int SMCSm SMCS to use int Chn STAR int Chn RX FIFO int amount number of words to read int rxdpram pointer on receive buffer int num for num 0 num lt amount num while smcs reg read SMCSm CHn STAR amp RxnotEmpty wait for data rxdpram smcs reg read SMCSm CHn RX FIFO if smcs reg read SMCSm CHn STAR amp RXrecvEOP break return num return number of words read void smcs fifo write int SMCSm SMCS to use int Chn STAR int Chn TX FIFO int Chn TX EOPB int amount number of words to transmit int txdpram pointer on transmit buffer int num for num 0 num amount num while smcs reg read SMCSm CHn STAR amp TXfull wait for space in fifo smcs reg write SMCSm CHn TX FIFO txdpram send EOP smcs reg write SMCSy CHx TX EOPB EOD 6 3 1 Special behaviour in case of SpaceWire link error Data written to the HOCI transmit FIFO are not transmitted immediately as already described in the previous section This All Rights Reserved Copyright per DIN 34 ASTRIUM SMCS332SpW User Manual EADS Ast
128. rate selection value effect 0x00 10 MBit s OxOE lowest transmission bitrate 0x08 highest transmission bitrate 6 1 5 2 COMI Configuration Register CHx COMICFG This register must be set up if data transfer via COMI is desired It determines the COMI data bus width for receive and transmit separately transmit EOP character or not at the end of a packet and the structure of data storage in the Communication Memory refer to chapter Data Transfer via COMI 6 1 5 3 Control Register 1 CHx_CNTRL1 No configuration has to be made if transmission in transparent mode is desired For operation with the SMCS332SpW in protocol mode the respective bits are to set see chapter 13 6 1 5 4 SpaceWire Command Register CHx DSM CMDR The link can be started by writing a 1 to bit 1 of this register The corresponding link begins to send NULLs the first flow control characters FCT will be exchanged after a NULL has been received Each link can be started or stopped independently but it should be considered that stopping a link will result in a link disconnect error at the receiving end All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 58 of 131 6 2 Data transfer via COMI The transmission via the Communication Memory Interface COMI is a very efficient way to transfer data packets over the SpaceWi
129. ration writes Their status can be determined by configuration reads Each link must be explicitly started by writing to the Start Transmit Node bit in its CHx_DSM_ CMDR register When a Space Wire link is started up it transmits NULL s Data may not be transferred over the link until the receiving link has sent a FCT which it will do as soon as it has been started In remote mode control by link however the SMCS332SpW will send characters as soon as it receives a NULL on one of the three links the control link The receiving link receives and correctly decodes the characters However only when the receiving link has been explicitly started by writing across the internal configuration bus can it send characters back NULL s are then sent until data 1s required A start up sequence between SpaceWire devices cannot be defined in general The start up depends heavily on the system user requirements and consequently on the procedure defined at system level to initialize the system or to recover from an error No master slave arrangement is necessary The SpaceWire links are hot plug able which means SpaceWire links can be connected together at any time 3 6 Link connections SpaceWire links are TTL compatible and intended to be used in electrically quiet environments between devices on a single printed circuit board or between two boards via a backplane Direct connection may be made between devices separated by a distance of less than 20
130. re links The CPU only fills the Communication Memory DPRAM with the relevant data words and sets the registers in the SMCS332SpW that point on these words Further transfer activities are applied by the SMCS332SpW without any CPU intervention For each link channel 6 registers are provided 4 registers to assign an area in the Communication Memory and 2 registers which carry the current address value CHx TX SAR Channel x Transmission Start Address Register CHx TX EAR Channel x Transmission End Address Register TX and RX registers are programmable independently thus there is no interference between TX and RX activities With writing on the End Address Register the transmit receive activity of the respective channel is initiated With reading the Current Address Register the status of data transfer of this activity can be observed A successful packet transmission reception or the occurrences of an error is indicated through an interrupt by the SMCS332SpW The cause of an interrupt can be read from the Interrupt Status Register ISR via the Host Control Interface HOCI The following events cause an interrupt and are important for the transmission via COMI in transparent mode SpaceWire link error disconnect parity credit and ESC error packet transmission completed TX Current Address Reg TX End Address Reg reception segment in Communication Memory full packet reception completed EOP or EEP received RX Current Address Reg
131. resse fw fow 55 55 55 CH3 RT ADDR channel 3 Route address Register 00 r w s Bs e hea O o o e e REES EE 5A 5B E r CH3_HTID channel 3 Header Transaction ID byte CH3 HCNTRL channel 3 Header control byte C D Lem F channel 3 COMI configuration register 0 CH3 TX SAR channel 3 transmit Start Address Register Gi CH3 TX EAR channel 3 transmit End Address Register uu CH3 TX CAR channel 3 transmit Current Address Register iu N LA CH3 TX FIFO channel 3 transmit FIFO CH3 TX EOPB channel 3 transmit EOP Bit Register CH3 RX SAR channel 3 receive Start Address Register CH3 RX EAR channel 3 receive End Address Register CH3 RX CAR channel 3 receive Current Address Register E CH3 RS FIFO channel 3 receive FIFO XXXXXXXX F CH3 STAR channel 3 Status Register r ON Ur 67 68 69 ion DD Dv 59 CH3_CNTRL2 channel 3 control Register 2 Im Ire e T anm 5B 5C 5D SE SF 62 64 67 6A 6C 6E 6F ESES EXEN EE EXEN ENEE ENEE lul ri CECE CECE ist ud CICE Cara a All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW DocNo SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 22 of 131 4 1 5 SMCS332SpW GPIO control registers These registers are only enabled when the SMCS332SpW is configured for control by link using the BOOTLINK pin see sections 2 3 5 4 and 9 2 Port Width Register Function Acces
132. rium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 63 of 131 causes a special behaviour if a link error occurs The remainder ofthe last written packet remains in the internal pipe which is not cleared in case of a SpaceWire link error After the link reconnects this remainder will be transmitted immediately after a new data character or an EOP is written to the HOCI FIFO To prevent a transmission of the remaining bytes in front of a new packet after link reconnects following sequence is proposed 1 After the link disconnects reset the transmit section of the channel by setting of bit DO in register CHx CNTRL2 2 If the packet isn t finished with an EOP then close the packet by writing to the EOP register 0x27 transmit EOP 3 Clear the bit DO in register CHx_CNTRL2 4 restart the link All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 64 of 131 7 Signal Description The Figure below shows the SMCS332SpW embedded in a typical module environment SMCS332SpW Processor p HOSTBIGE HINTR p INTERRUPTIN _ p BOOTLNK HSEL le e CHIP SELECTS AN RESET HRD lq READ p CLK HWR e WRITE p CLK10 HACK p WAIT ACK HDATA DATA HADR ADDRESS 45 SPACEWIRE LINK 1 SMOSADR SMCSID 4
133. rs contains a different value CHI RT ADDR CH2 RT ADDR CH3 RT ADDR and CHx ADDR Initialization of SMCS332SpW for routing register value CHI ADDR 0xF1 CH2 ADDR OxF2 CH3 ADDR OxF3 CHI RT ADDR 0x21 CH2 RT ADDR 0x22 CH3 RT ADDR 0x23 RT CTRL 0x80 routing enabled Assume that data is incoming on channel 1 The first byte will be compared with CHI ADDR CH2 RT ADRR and CH3 RT ADDR and depending on its value one of the following actions will be taken Case 1 the first byte address byte of the received packet is OxF1 gt the packet excluding address byte F1 will be routed to the internal receive FIFO of channell Case 2 the first byte address byte of the received packet is 0x22 gt the packet will be routed to the transmit section of channel2 Case 3 the first byte address byte of the received packet is 0x23 the packet will be routed to the transmit section of channel3 Case 4 the first byte address byte of the received packet 1s neither OxF1 0x22 nor 0x23 the packet will be routed to the internal receive FIFO of channel and error bit5 in CHx_ESR1 will be set In parallel an interrupt will be raised if respective bit is set in IMR 5 6 Header bytes generation There are two modes to insert header bytes at the beginning of a packet A new mode controlled by the header field control bit and the well known SMCS332 mode with routing and checksum generation 5 6 1 Header
134. s Address hex GPIO DIRO GPIO direction register 0 GPIO_DIR1 GPIO direction register 1 GPIO_DIR2 GPIO direction register 2 GPIO_DIR3 GPIO direction register 3 GPIO_DATAO GPIO data register 0 GPIO DATAI GPIO data register 1 GPIO DATA2 GPIO data register 2 GPIO DATA3 GPIO data register 3 4 1 6 Time code control registers These registers controls the transmit and receive of the time code Port Width Register Function Access Address hex ps f TIME CNTRL time code control register r w TIME CODE time code value register r w All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 23 of 131 4 20 Register Description 4 2 1 General SMCS Registers 4 2 1 1 SMCS332SpW Interface Control Register SICR address 0x00 data width 3 bit D2 0 access mode read write reset value 0x00 i basis OOS 00 Host Control Interface Data Port operates as 8 bit port RESET 01 HOCI data port operates as 16 bit port 1X HOCI data port operates as 32 bit port refer also to little big endian mode of HOCI data port which is hardware controlled by input level at the HOSTBIGE pin Signal level of HOSTBIGE pin 0 little endian 1 big endian 2 0 COMI operates in little endian mode RESET 1 COMI operates in big endian mode 7 3 always 0 reserved 4 2 1
135. s the specification scope of this document covers the frame of the data transfers between two nodes and the coding and execution of a range of required control commands It is explicitly intended to specify only a minimum of transaction level functions and formats in order to keep flexibility and broaden the application range In general the basic design approach can be described as trading off functionality for conceptual and implementation simplicity and speed All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 115 of 131 13 2 Assumptions about the Environment The protocol specified here is intended to work on top ofthe SpaceWire link protocol This covers e g link startup low level error handling low level flow control timeouts routing provisions and the like This protocol assumes a link interface HW implementation based on a front end which handles all SpaceWire related issues and a backend providing resources to interpret this protocol and perform the required actions e g in case of commands or acknowledges The link interface is controlled at least for configuration purposes by the CPU of a node Itis further assumed that within the protocol specific HW circuitry buffer storage FIFOs exist in addition to the receive and transmit FIFOs provided by the SpaceWire link frontend circuitry
136. s transfers at rates down to 6 25 and 3 125 Mbps can be achieved If the max speed to 80Mbps then the transmission speed can be selected to 5 10 20 40 and 80 Mbps What is the minimum transmission rate on an SpaceWire link SpaceWire defines the max time between two bits with 850ns which corresponds to 1 18 Mbit s Are the outputs of the SMCS332SpW TTL compatible Yes the SMCS332SpW features CMOS outputs and TTL inputs When the SMCS332SpW is connected to a dual port memory can it monitor the busy wire of the DPRAM No External logic is required for that Due to the mechanism applied in the SMCS it is not necessary to monitor busy wire when data is flowing via COMI How does the COMI COmmunication Memory Interface works in big endian mode The COMI works in big endian mode in the same manner as it is described for the HOCI HOst Control Interface When in control by link mode can the link used as control link be used to send data to the RAM connected to the SMCS332SpW No another link must be used for this purpose See section 4 4 5 In control by link mode can I access the link control registers also from the links not working as control link Yes all SMCS332SpW registers can be accessed via the control link See section 4 4 When are the ISR bits reset This depends on the width of the host interface After reset or in control by link mode it is in 8 bit mode To reset the ISR bits do the following 8 bit mode R
137. s low inductive path provides the SMCS332SpW with the peak currents required when its output drivers switch The capacitors ground leads should also be short and connect directly to the ground plane This provides a low impedance return path for the load capacitance of the SMCS332SpW output drivers The following pins must have a capacitor 20 78 129 and 155 The remaining capacitors should be distributed equally around the SMCS332SpW All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 70 of 131 9 Timing Parameters 9 1 Clock Signals CLK Fox 666 hau ms Symbol Max D Max 15 MHz All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 71 of 131 CLK10 locos loco Vcc 7 5V 0 5V CLK10 period CLK10 width high CLK 10 with low Pax JL Typically 10 MHz Vec 7 3 3 V E 0 3V CLK10 period P 100 CLK10 width high 40 CLK10 width low 40 D Typically 10 MHz All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 72 of 131 9 2 Reset a AU VI V
138. se width of such a pulse depends on the selected link speed and the operating frequency of the SMCS332SpW as well as the remote Space Wire controller 5 4 5 Restrictions The SpaceWire link which controls the SMCS332SpW must be a direct link point to point connection Using the control link all internal registers of the SMCS332SpW can be addressed In addition the GPIO port can be accessed via the control link The only exception is that the receive part of the COMI associated with the control link cannot be used This limitation is imposed since every byte received on the control link is interpreted as a command and therefore no data can be written into the communication memory via the control link However the transmit part of the COMI associated with the control link can be used to transfer data from the SMCS332SpW under remote control to another SpaceWire controller If data needs to be transferred via the COMI to an external device of the remotely controlled SMCS332SpW e g memory an additional link must be used for that purpose The registers for that link can then be set via the control link The block diagram below shows a typical constellation of a remotely controlled SMCS332SpW controlled via link 2 from another Space Wire device in this case an SMCS332SpW Note that if data is to be written to the RAM of the remote controlled SMCS332SpW an extra link in the figure below this is link 1 needs to be used This link can be used
139. set command is still forwarded to the node s working memory Utilizing the interrupt signal indicating to the node CPU that an externally commanded link reset has occurred the CPU can then decide on invalidating data already received via this channel Reset Link Interface Unit HW Provided that safety critical command execution has been enabled the execution of this command is performed immediately after correct reception ofthe command and the EOP marker Due to the immediate execution no acknowledge packet is sent The command has the same results on ALL link channels integrated on one chip as the reset link interface HW command described above with the exception of the reception path of the memory interface The reception path of all link channel interfaces are reset in the same way as it is the case for the transmission path clearing of all configuration registers clearing of all intermediated storage marking FIFOs as empty 13 4 5 Shutdown Link Channel Operation Restart Link Channel Operation During link shutdown basically the same actions are performed as for the reset link interface unit HW command It is up to the implementation to assure that no currently running traffic is disturbed by a link shutdown The restart link channel operation complex command initiates a link frontend restart just like a restart from a simple reset link interface command 13 4 6 Read of Link Interface Status Register If the link channe
140. sing the JTAG port of the SMCS332SpW BSDL for SMCS332SpW Uses HP s BSDL format and compiles correctly using HP s parser or compiler of JTAG Technologies Author date entity SMCS is generic PHYSICAL PIN MAP string UNDEFINED port BOOTLINK in bit BYPPLL in bit CAM in bit CLK in bit CLK10 in bit COCI in bit HADR in bit vector 0 to 7 HOSTBIGE in bit HRD in bit HSEL in bit HWR in bit LDI1 in bit LDI2 in bit LDI3 in bit LSI1 in bit LSI2 in bit LSI3 in bit RESET in bit SMCSADRO in bit SMCSADR1 in bit SMCSADR2 in bit SMCSADR3 in bit SMCSIDO in bit SMCSID1 in bit SMCSID2 in bit SMCSID3 in bit TIME C SY in bit VCC 3VOLT in bit TCK in bit TDI in bit All Rights Reserved Copyright per DIN 34 T SMCS332SpW EADS m User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 91 of 131 TDO out bit TMS in bit TRST in bit CMADR out bit vector 0 to 15 CMCSO out bit CMCS1 out bit CMRD out bit CMWR out bit COCO out bit CPUR out bit HACK out bit HINTR out bit LDO1 out bit LDO2 out bit LDO3 out bit LSO1 out bit LSO2 out bit LSO3 out bit SESO out bit SESI out bit SES2 out bit SES3 out bit TEST out bit CMDATA inout bit vector 0 to 31
141. smit EOP Bit Register CH1 TX EOPB address 0x27 data width 2 bit D1 0 access mode write only reset value n a For data transfer over the transmit FIFO the host processor has to send the EOP character at the end of the packet If the host processor sets bit 0 or 1 or both the SMCS332SpW sends an EOP character at the end of the packet mede T SI send an EOP character send an EOP character always 0 reserved 4 2 2 20 Channel 1 Receive Start Address Register CH1 RX SAR address 0x28 0x29 data width 16 bit D15 0 access mode read write reset value 0x0000 The value of CH1 RX SAR shows the start address of an area in the communication memory where the received data shall be written Byte 0 at address 0x28 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 40 of 131 B pe lower byte of the start address Byte 1 at address 0x29 only in 8 bit mode of the HOCI data port Bit Description upper byte of the start address 4 2 2 21 Channel 1 Receive End Address Register CH1_RX_EAR address 0x2A 0x2B data width 16 bit D15 0 access mode read write reset value 0x0000 As soon as the upper byte is written the address generator starts with the address in CH1 RX SAR The register CHI RX SAR start address and CHI
142. system implementation to control via the enable command execution command the access to the specific external signal output pins It is up to the implementation to chose a physical signal level for the active and passive states of the CPUR and SESO SES3 signals 13 4 3 Safety Critical Commands Simple Control Commands The execution of safety critical simple commands consists of a sequence of two steps enabling the execution of simple commands execution of the simple command For each of these step a separate simple command request packet from the requester node is required The status register of the link channel includes one bit indicating 1f safety critical simple command execution is enabled or not All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 EADS H Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 120 of 131 After a critical simple command has been executed the simple command execution state is immediately changed from enable to disable This assures that every critical simple command execution must be preceded by a enable command Complex Control Commands The same two step procedure as for simple control commands is applied to complex control commands with the difference that the status of enabling a complex command is not stored in the link status register Since it is assumed that the complex commands are e
143. t MWR 4 tow D tow E CMADR E Lan tone CMDATA HHI f lods pe CO em ao KE toocow Coco N content of COMI ACR Veo 73 3 V 0 3V cociente us s I e fe mo fe d N content of COMI ACR All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 80 of 131 9 8 CPUR SES Interrupt ok Lh LI touro CPUR SESx HINTR Vcc 5 V 0 5V CPUR SESx HINTR delay after CLK high Fon II m Vec 7 3 3 V 0 3V CPUR SESx HINTR delay after CLK high Fon m All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 81 of 131 9 9 Links tne LSOx LDOx tours E tours LDIx Leet los LSIx Vcc 7 5V 0 5V Note tips is the minimum separation time between consecutive edges on the data and strobe inputs that the SMCS332SpW can discriminate correctly for all speeds from 1 25 Mbps 200 Mbps Veco 7 3 3 V 0 3V Description Symbol Unit Bit Period LDOx LSOx output skew Note tips is the minimum separation time between consecutive edges on the data and strobe inputs that the SMCS332SpW can discriminate corr
144. t 0 wait for int if chl tx int occured amp amp txl count 0 chl tx int occured 0 tx1_count start transfer of second packet over Link 1 smcs reg write SMCS CH1 TX SAR 0x10 smcs reg write SMCS CH1 TX EAR 0x1F if chl tx int occured amp amp chl rx int occured amp amp ch2 rx int occured break All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 61 of 131 6 3 Data Transfer via HOCI The Host Control Interface is mainly designed for the access to internal SMCS332SpW registers But for small packets data transfer can be performed via this interface for the purpose of saving board space and power through the absence of the Communication Memory Also applications with sample oriented processing can take advantage of this feature The CPU user makes usage of its direct access on the SMCS332SpW internal FIFOs to read write the single data words to be transferred With checking the FIFO flags the CPU must assure to handle the process of communication properly This action results in a programming overhead of course but saves board space and power Program Sequence The transfer is controlled by 4 registers CHx TX FIFO channel x Transmit FIFO CHx TX EOPB channel x Transmit EOP Bit Register CHx RX FIFO channel x Receive FIFO CHx STAR channel x Status
145. t D7 0 access mode D6 0 read only D7 read write reset value 0x00 E Status channel 1 no connection connection to local fifo connection to channel 2 connection to channel 3 Status channel 2 no connection connection to channel 1 connection to local fifo connection to channel 3 Status channel 3 no connection connection to channel 1 connection to channel 2 connection to local fifo SMCS332SpW Wormhole Route Enable Bit 0 Wormhole Routing disabled Reset 1 Wormhole Routing enabled 4 2 1 4 Interrupt Status Register ISR address 0x04 0x07 data width 32 bit D31 0 access mode read only reset value 0x04010040 The following interrupts are stored in byte 0 of the ISR address 8 bit mode 0x04 16 bit mode 0x04 32 bit mode 0x04 ISR Byte 0 All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 25 of 131 SE channel 1 SpaceWire parity disconnect ESC or credit error For more information refer to register CHI DS8M STAR channel SpaceWire status register 1 channel 1 error For more information over this error flag refer to register CHI ESRI and CH1 EXR2 channel 1 data from the communication memory are read That means channell transmit COMI address generator reach the value of the end address register CHI TX EAR chan
146. t data bits 24 0 of the COMI to 0 in 16 bit mode set data bits 15 0 to 0 1 in 8 bit mode if MSB of the received data 1 set data bits 24 0 of the COMI to 1 if MSB of the received data O set data bits 24 0 of the COMI to 0 in 16 bit mode if MSB of the received data 1 set data bits 15 0 of the COMI to 1 if MSB of the received data 0 set data bits 15 0 of the COMI to 0 4 2 2 15 Channel 1 Transmit Start Address Register CH1_TX_SAR address 0x20 0x21 data width 16 bit D15 0 access mode read write All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 38 of 131 reset value 0x0000 The value of CH1 TX SAR shows the start address the value of CHI TX EAR shows the end address of a packet in the communication memory which should be transmitted over channel 1 Byte 0 at address 0x20 Description lower byte of the start address Byte 1 at address 0x21 only in 8 bit mode of the HOCI data port Pi Duets upper byte of the start address 4 2 2 16 Channel 1 Transmit End Address Register CH1_TX_EAR address 0x22 0x23 data width 16 bit D15 0 access mode read write reset value 0x0000 As soon as the upper byte is written the address generator starts with the address in CHI TX SAR Byte 0 at address 0x22
147. ted as header bytes If checksum enabled this bytes are excluded from the checksum The range for the header field is from minimum 2bytes number byte header byte to maximuml6 bytes The size of the header field is 4 8 12 and 16 bytes This means that the data field starts at the next modulo 4 bytes The rest of a 4 byte block which is not covered by the number of header bytes will not be transmitted See for additional information chapter 5 6 always 0 reserved Note The Checksum generation and check module adds all bytes in the packet checksum 16 0 checksum 16 0 data 7 0 checksum 16 The checksum is generated in the SMCS332SpW as shown in the following figure All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 34 of 131 DATA GE Sege 1 CS 17 Figure Checksum generation Example the packet consists of 259 OxFF 1 checksum 0x00000 OxFF 0 0x000FF 2 checksum 0x000FF OxFF 0 0x001FE 256 checksum OxOFEO01 OxFF 0 OxOFF00 257 checksum OxOFFO00 OxFF 0 OxOFFFF 258 checksum OxOFFFF OxFF 0 0x100FE 259 checksum 0x100FE OxFF 1 0x101FE 1 checksum byte send over SpaceWire checksum 7 0 2 checksum byte send over SpaceWire checksum 15 8 See also register C
148. terface MUST be left operational but a signal is generated indicating to the CPU that an externally commanded reset has occurred This may be implemented as a specific signal or as an interrupt read status register sequence Memory Interface Transmission Path Any currently running transmission at the link to be reset is interrupted immediately by the reset command Since the state of transmission cannot be restored the transmission path is completely reset including clearing of any transmission related configuration register of the memory interface and clearing of intermediate storage containing data already read for transmission from communication memory but not yet forwarded to the link frontend The transmission path must be completely reconfigured by the CPU after this kind of reset Memory Interface Reception Path The reception path is left unchanged especially all intermediate storage containing data received previously but not yet forwarded to the working memory of the node The reception path can be left unchanged since it can be assumed that the last data packet previous to this reset command was received correctly otherwise this reset command would have not been All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 EADS m User Manual Updated 9 Sep 2006 Page 121 of 131 received and decoded correctly Data received previous to the re
149. th Register Function Address hex 32 Jis je Ew o e sin smcssszspw merte conarnesser m fow o fo o mscmt EES fe o o o rrem rouine nbe soten m fo wfe je bee e L 04 04 04 ISR Interrupt Status Register 04010040 ro 05 06 06 07 08 08 IMR Interrupt Mask Register 00000000 r w 09 0A 0A COMI CSOR COMI Chip Select 0 upper address boundary Register Low Jee COMI ACR COMI Arbitration Control Register ti All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 19 of 131 4 1 2 SMCS332SpW channel 1 status and control registers Port Width Register Function Access Address hex w js 10 CH DSM MOBDR channel 1 DSM mode Register o few e CHI DSM CMDR channel 1 DSM command Register o Ire e 12 CH DSM STAR channel 1 DSM status Register Im Ire O 13 CH1 DSM TSTR channel 1 DSM test Register o iw 14 CHI ADDR channel 1 address Register o Ire e CHI RT ADDR channel 1 Route Address Register o Iris O CHI PR STAR channel 1 Protocol Status Register wqw m e e s CH1 CNTRLI channel 1 control Register 1 o Ire e CH1 CNTRLI2 channel 1 control Register 2 o Ire O CH1 HTID channel 1 Header Transaction ID byte Im fro 1B CH1 HCNTRL channel 1 Header control byte ro CH1 ESRI channel 1 detailed error source register 1 o Ire CH1 ESR2 chan
150. tput3 X 212 O Z amp 188 BC 1 CMDATA 20 input X amp 187 BC 1 CMDATA 19 output3 X 212 O Z E 186 BC 1 CMDATA 19 input X amp 185 BC 1 CMDATA 18 output3 X 212 0 Z amp 184 BC 1 CMDATA 18 input X amp 183 BC 1 CMDATA 17 output3 X 212 O Z amp 182 BC 1 CMDATA 17 input X amp 181 BC 1 CMDATA 16 output3 X 212 O Z amp 180 BC 1 CMDATA 16 input X amp 179 BC 1 CMDATA 15 output3 X 212 O Z E All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 EADS H Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 95 of 131 178 BC 1 CMDATA 15 input X amp 177 BC 1 CMDATA 14 output3 X 212 O Z amp 176 BC 1 CMDATA 14 input X amp 175 BC 1 CMDATA 13 output3 X 212 O Z amp 174 BC 1 CMDATA 13 input X amp 173 BC 1 CMDATA 12 output3 X 212 0 Z amp 172 BC 1 CMDATA 12 input X amp 171 BC 1 CMDATA 11 output3 X 212 0 Z amp 170 BC 1 CMDATA 11 input X amp 169 BC 1 CMDATA 10 output3 X 212 0 Z amp 168 BC 1 CMDATA 10 input X amp 167 BC 1 CMDATA 9 output3 X 212 0 Z amp 166 BC 1 CMDATA 9 input X amp 165 BC 1 CMDATA 8 output3 X 212 0 Z amp 164 BC 1 CMDATA 8 input X amp 163 BC 1 CMDATA 7
151. trationcycle 8 1 1 arbitrationcycle 12 cycles readcycles 4 1 8 1 10 cycles bandwidth 25 MHz 10 12 4 Byte cycle gt 83 3 Mbyte s bandwidth SMCS332SpW A 8 1 7 readcycles 25 MHz 7 12 4 Bytes cycle 58 33 Mbyte s bandwidth SMCS332SpW B All Rights Reserved Copyright per DIN 34 ASTRIUM SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 47 of 131 4 1 3 readcycles 25 MHz 3 12 4 Bytes cycle 25 Mbyte s Note COMI ACR value 0x01 is not allowed COMI ACR value 0x00 means disable communication memory interface All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 48 of 131 5 4 Control by Link The SMCS332SpW offers the possibility to be used in a so called remote mode which means that for controlling the SMCS332SpW read write registers no local controller u Controller CPU FPGA etc is required Instead the SMCS332SpW is being configured and controlled using one ofthe three links as a dedicated control link Since the HOCI is no longer used to access the SMCS332SpW registers locally it is instead available as a 32 bit bidirectional general purpose I O GPIO port The direction in out of each bit of this port can be programmed individually 5
152. troller for all received TIME CODE characters enable the internal interrupt signal generation to the interrupt controller for a false TIME CODE character received from the SpaceWire links see also interrupt bit in ISR Byte 3 bit 6 Time code value register control bit 0 overwrite of the time code value register with a received time code is enabled l No overwrite of the time code value register with a received time code TIME CODE SYNC signal control bit0 0 The TIME CODE SYNC signal is disabled 1 A falling edge of the TIME CODE SYNC input signal sends the time code register value over the SpaceWire links TIME CODE SYNC signal control bt 0 No increment of the time code value register 1 A falling edge ofthe TIME CODE SYNC input signal increments the time code register value by 1 Status time code character received on SpaceWire link 1 Only read reset after read Status time code character received on SpaceWire link 2 Only read reset after read Status time code character received on SpaceWire link 3 Only read reset after read 4 2 5 0 Time Code Value Register TIME CODE address 0x79 data width 8 bit D7 0 access mode read write reset value 0x00 mem OSS Time code value register All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 T SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 43 of 131
153. urpose I O GPIO lines The detailed description of this operation mode is given in section 5 4 2 4 Wormhole Routing The SMCS332SpW introduces a wormhole routing function similar to the routing implemented in the Space Wire Router Each of the three links and the SMCS332SpW itself can be assigned an eight bit address When routing is enabled in the SMCS332SpW the first byte ofa packet will be interpreted as the address destination byte analyzed and removed from the packet header deletion If this address matches one of the two other link addresses or the SMCS332SpW address assigned previously the packet will be automatically forwarded to this link or the FIFO of the SMCS332SpW If the header byte does not match a link address the packet will be written to the internal FIFO as well and an error interrupt maskable will be raised All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW DocNo SMCS ASTD UM 100 Issue 1 4 ASTRIUM User Manual Updated 9 Sep 2006 Page 12 of 131 2 5 PPU Functional Description Since the Protocol Processing Unit PPU determines a major part ofthe SMCS332SpW functionality the principal blocks of the PPU and their function are described here This functionality is provided for every SpaceWire channel of the SMCS332SpW Protocol Execution Unit This unit serves as the main controller of the PPU block It receives the character from the SpaceWire cell an
154. ut3 X 55 0 Z amp 53 BC 1 HDATA 10 input X amp 52 BC 1 e control 0 amp HOCI Data Output Enable 51 BC 1 HDATA 9 output3 X 52 0 Z E 50 BC 1 HDATA 9 input X amp 49 BC 1 j control 0 amp HOCI Data Output Enable 48 BC 1 HDATA 8 output3 X 49 0 Z amp 47 BC 1 HDATA 8 input X amp 46 BC 1 s control 0 amp HOCI Data Output Enable 45 BC 1 HDATA 7 output3 X 46 0 Z amp 44 BC 1 HDATA 7 input X amp 43 BC 1 i control 0 amp HOCI Data Output Enable 42 BC 1 HDATA 6 output3 X 43 0 Z amp 41 BC 1 HDATA 6 input X amp 40 BC 1 y control 0 amp HOCI Data Output Enable 39 BC 1 HDATA 5 output3 X 40 0 Z E 38 BC 1 HDATA 5 input X amp 37 BC 1 e control 0 amp HOCI Data Output Enable 36 BC 1 HDATA 4 output3 X 37 0 Z amp 35 BC 1 HDATA 4 input X amp 34 BC 1 i control 0 amp HOCI Data Output Enable 33 BC 1 HDATA 3 output3 X 34 0 Z amp 32 BC 1 HDATA 3 input X E All Rights Reserved Copyright per DIN 34 4 EADS EADS Astrium GmbH ASE2 SMCS332SpW Doc No SMCS ASTD UM 100 Issue 1 4 User Manual ASTRIUM Updated 9 Sep 2006 Page 98 of 131 31 BC 1 A control 0 amp HOCI Data Output Enable 30 BC 1 H
155. ween the two credit counters of more than 8 causes a deadlock situation Scenario 2 Credit Tx Discr Credit SMCS332 Rx Buffer Remark 16 SE 0 16 Link Initialisation 9 7 Data Bytes 0 9 7 Byte 8 a 8 1 EOP 16 1 FCT 0 16 15 OE l 16 Empty packet g 7 Data Bytes 1 9 7 Byte 7 Tor l 8 1 EOP 15 1 FCT 1 16 14 EE 2 16 Empty packet 7 7 Data Byte 2 9 7 Byte 6 EIE 2 8 1 EOP 14 1 FCT Z 16 13 EO 3 16 Empty packet 6 7 Data Byte 3 9 7 Byte 5 LE 8 1 EOP 13 1 FCT 2 16 12 EO Y 16 Empty packet 5 7 Data Bytes 9 7 Byte All Rights Reserved Copyright per DIN 34 EADS Astrium GmbH ASE2 SMCS332SpW De Ne SMOS ASTD_UM 1 00 ASTRIUM User Manual Updated 9 Sep 2006 Page 112 of 131 4 LE0P 8 1 EOP 12 PEL 16 11 LI FOF 5 16 Empty packet 4 7 Data Bytes 5 9 7 Byte 3 LE0P 5 8 1 EOP T 1 FCT 5 16 Ww 10 i S 16 Empty packet 3 7 Data Bytes 6 9 7 Byte 2 LEoP 8 EOP 10 1 FCT 6 16 9 li 16 Empty packet 2 7 Data Bytes 7 9 7 Byte 1 LEOP H 8 EOP 9 1 FCT 7 16 lt lt 8 EO 16 Empty packet 1 7 Data Bytes 8 9 7 Byte 0 LEoP y j 8 1 EOP g 1 FCT 8 16 7 ____1 EOP EOP 9 16 Empty packet 0 7 Data Bytes 9 9 7 Byte DEADLOCK All Rights Reserved Copyright per DIN 34 ASTRIU
156. will be sent to the transmitting link node Empty packets except for the first empty packet after a link initialization are deleted before writing to the receive buffer therefore these packets EOP s do not increment the receive credit counter This causes a discrepancy between the receiver and the transmitter credit counter A discrepancy of 8 eight empty packets causes a slow down of the link If the discrepancy is greater than 8 the link runs into a deadlock situation because the SMCS332Spw will not send a FCT and the credit counter of the transmitter is expired Scenario 1 Credit Tx Discr Credit SMCS332 Rx Buffer Remark 16 one y 16 Link Initialisation 8 8 BUE y 15 1 EOP 7 empty packets 7 EOP gt 8 15 1 empty packet 0 JL Data Bytes p 8 8 7 Byte 8 1 FCT 8 16 7 LEGE y d 15 1 EOP 6 LE r 15 1 empty packet 0 B Data Bytes p 9 9 6 Byte DEADLOCK Discrepancy 9 All Rights Reserved Copyright per DIN 34 ASTRIUM SMCS332SpW User Manual EADS Astrium GmbH ASE2 Doc No SMCS ASTD UM 100 Issue 1 4 Updated 9 Sep 2006 Page 111 of 131 after Link Initialisation Disconnect the RCVEOP received EOP flag is cleared therefore an EOP EEP transmitted directly after link connects is counted properly and can be read from Rx Buffer 1 S e ES A discrepancy between the two credit counters of 8 causes a reduced transmission rate A discrepancy bet
157. xecuted by SW running on the CPU of a node the status of complex commands is kept in a SW register and can be read by the read status of complex command enable switch complex command 13 4 4 Reset Commands Reset Link Interface HW Provided that safety critical command execution has been enabled the execution of this command is performed immediately after correct reception of the command and the EOP marker Due to the immediate execution no acknowledge packet is sent The command has the following results Link Frontend After receiving a reset link channel command the frontend performs the following actions analog to the SpaceWire DS SE link procedures A auto restart procedure is required so that the node requesting a reset link channel command can assume that the other node is again operating after a certain amount of time after the reset link channel command This requires that the link frontend which has executed the reset command either automatically starts to transmit FCTs and NULL characters after having received tokens from the other node or that the node CPU observes reception of tokens after link interface reset and then enables the link interface to restart with transmission Channel Status Register The status register is cleared reset but one bit is set indicating that the link channel has started up from an externally commanded reset Node CPU Interface The interface configurations are not modified and the in

SMCS332-SpW User Manual - SpaceWire

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