NetFusion Libero Starter Project Helper
Contents
1. 22 4 6 COREGPIO sete estis asia 23 47 COREUARTAPB 24 4 48 CORESPIO 1 25 4 9 TEMPERATURE SENSOR GLUE LOGIG rss serre 26 4 10 COORDINATED RESET i 27 4 11 BIBUF TETTE 28 4 12 GORESF2C ONFIG EE 29 4 13 CORE AX nano 30 4 14 CORE AHB LITE te ali 31 4 15 CORE cue ein E lea 32 4 16 AXI AHB LITE amp APB3 DEFAULT MEMORY MAPPED SETTINGS ERE 33 4 17 UNUSEDLOGIGIBLOCK ci ERI RN aliena ina lan 36 4 18 SMARTFUSION2 MESS 37 5 NETFUSION ARM CORTEX MSS DEFAULT CONFIGURATION 38 51 ee EE 39 52 USB A 40 5 3 ETHERNET 41 5 4 MSS EE 42 5 5 RESET CONTROLLER i 42 56 TEE 43 S7 Ela 44 5 8 FIC_2 PERIPHERAL INITIALIZATION PRIA TRE m 45 6 ADDING IP CORES FROM VERILOG VHDL 1100s0ss KREE iii 46 iol Q9 0 research 9 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 IMPORTING SOURCE FILES2. 4 Advanced options have been modified The information displayed in this tab might be inaccurate please use the advanced tab for the actual figuration Figure 12 PLL Clock Macro Settings Output signal GLO is distributed to the memory bus and the MSS ARM block The main base clock frequency for the 166MHz ARM processor is scaled up inside the MSS block 9 and development 9 NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 5 Counter GPIO NetFusion PCB has an on board temperature sensor The output of which is a square wave signal that has a frequency is equivalent to degrees Kelvin down to absolute zero This signal is routed into the SmartFusion2 FPGA fabric and clocks the 16 bit counter counter 6_0 The counter s 16 bit output value is wired into GPIO input CoreGPIO 1 which is memory addressable from the ARM uClinux applications This serves as a simple 32 bit memory location to read and makes the software algorithm for determining the temperature incredibly simple Note the memory interface from the ARM MSS is an APB interface counter16 0 clkout reset counter 15 0 Pa Figure 13 Temperature Sensor Logic 22 research and development e NINE WAYS NetFusion Libero Starter Project Helper 4 6 CoreGPIO V1 1 January 2015 The vast majority of the hardware on the NetFusion PCB is connected through this
3. Enable FPGA Fabric to M3 Reset M3 RESET N Enable MSS to FPGA Fabric Reset MSS_RESET_N_M2F 2 ran Figure 35 Reset 55 Module NetFusion by default enables the MSS_RESET_N_F2M M3_RESET_N and the MSS_RESET_N_M2F negative reset signals to come in from the SmartFusion2 FPGA fabric This gives more functionality to the user However if it is not a required functionality when the design is customized then they can be de selected iol 42 research 0000 and development NetFusion Libero Starter Project Helper V1 1 January 2015 5 6 0 Mss Fabric Interface Controller 0 Configurator E MSS To FPGA Fabric Interface Interface Type Use Master Interface Use Slave Interface Advanced AHBLite Options Use Bypass Mode AHBLite only IT Expose Master Identity Port FPGA Fabric Address Regions MSS Master View FIC32 0 FIC32 1 Fabric Region 0 0x30000000 Ox3FFFFFFF Fabric Region 1 0x50000000 OxSFFFFFFF Fabric Region 2 0x70000000 Ox7FFFFFFF c c r Figure 36 AHB APB Fabric Interface 1 The NetFusion FIC_0 has been chosen to be assigned for the AHB Lite fabric interface It is a MASTER which connects to the SLAVES in the fabric as the ARM processor has complete control By default the AHB Lite only interfaces to the AMBA DMA Controller used for 3rd party Ethernet IP cores Although the DMA Con
4. cotto Pe tete Lettera pet cut ii 46 6 2 INSTANTIATING INTO THE F ABRIC cte Cetera tette laxe ud dL ara aa Cere V ea d npa Do e uu ead 47 6 2 1 Building and Synthesizing the NetFusion Design sene 48 USING FLASHPRO4 IDE TO PROGRAM NETFUSION rennen 50 HEFERENGCES inen eege eebe 52 eege ee E EE 53 10 DOCUMENT HISTORY rie 54 research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 List of Figures Figure 1 Libero 11 X IDE Boot Up 8 Figure 2 Libero Updating IP Core in the Vault ener enne 12 Figure Example of Top List I O Ball Aesionments eene 13 Figure 4 Example of Bottom List I O Ball Aesionments nene 14 Figure 5 Selecting the I O Constraints sse enne eene 14 Figure 6 NetFusion Top Level Sheet ertet nennen 15 Figure 7 Lower Level SOM sheet MSS block 16 Figure 7 Screenshot of Lower Level SOM sheet of the StartPack Libero Project 17 Figure 9 ULPI UTMI USB Converter IP Core 18 Figure 10 SmartFusion2 Reset Controller IP Core 19 Figure 11 Glock PEE Macro Cote e dederit Gea Date reddo rite dO bete e qe ede 20 Figure 12 PLE Clock Macro Settings
5. wm FS TRISTATE 1 0525 Y9 66 TRISTATE 525 ws wr F6 LVCMOS25 10 67 1 0525 w10 GMIT ITEN E PEER ERE EERE EE GM ER LVCMOS25 vii Ports A Package Pins JV Package Viewer J Ready Fam SmartFusion2 De 25050 Pkg 484 FEGA Figure 3 Example of Top List I O Ball Assignments research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 Se HH 2m ees WOtdtr Port A Direction Standard Pin Number Locked BankName 1 OstateinFlash Freeze mode Resistor Pull I O available Flash Freeze mode Schmitt Trigger Odt static Odtimp ohm Low Power Exit InputDelay Slew TRISTATE None No Off Off Off CLKOUT Input OTG DATAO Inout DATA1 Inout pense Jore OTG DATA4 oe DATAS a TRISTATE None Off TRISTATE None Off Off TRISTATE None off off TRISTATE None off off TRISTATE None off off TRISTATE None off off Off Off Off Off Off OTG_DATAG TRISTATE None TRISTATE None OTG orepR NXT TRISTATE None 3199199 399 998 TRISTAT
6. Programming Connectivity and Interface amp Programmer Settings Device UO States During Programming 5 Desgnr DesignHierar StimulusHierar Catalog Fies E Messages Errors Warnings Info The 1 0 modules located in these banks cannot be assigned any I O macro arning IOPRL2 1 1 0 Bank s have been assigned a Vccr voltage but no Vref pin The 1 0 modules located in these banks cannot be assigned any voltage Lc 1 0 macro The set device command succeeded The set input cfg command succeeded The set output cfg command succeeded The gen envm command succeeded The Execute Script command succeeded Fam SmartFusion2 De 250507 Pkg 484FBGA Verilog Figure 6 NetFusion Top Level Sheet When lower level SOM sheets are built and prepared they propagate information up automatically to this higher sheet New ports suddenly appear and you must then compile this sheet before the main synthesis Note you can instantiate normal IP cores into this top sheet if you wish and it makes sense according to your design requirements This is just the starter project so everything by default is kept in the lower SOM module But this can change rapidly as your customization starts to take effect The lower SOM sheet of the NetFusion starter Libero project contains all of the default designs and linkage i 9 research and development NINE WAYS N
7. s Guide Describes how to create designs in ViewDraw using menu commands toolbar buttons and by selecting and entering information on dialog boxes ViewDraw for Microsemi is not available on UNIX ModelSim ME Book Case Contains a User s Manual Command Reference and Tutorial These guides contain details about using ModelSim ME Libero s integrated simulation tool Refer to the documentation included with ModelSim ME for more information ModelSim ME documentation is also available at http www microsemi com products fpga soc design resources design software liberosoc Documents Synopsys Synplify Pro ME Documents include release notes user s guide tutorial reference manual and license configuration and set up Refer to the documentation included with Synopsys Synplify Pro for more information Synopsys Synplify Pro ME documentation is also available at http www microsemi com products fpga soc design resources design software libero soc documents research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 2 Downloading New IP Core s into the Libero IDE Installation Project File Edit View Design k SmartDesign 2 2 Catalog d C Smuiation Mode DI Name e Version Size MB us ic DE m Li eD 42 amp EN Reports amp x Bus som x E M2s050_SOM_FG484 T0P 8 X gt Arit
8. EIMDOR PADS EMDDR_PADS Figure 28 Unused Block in NetFusion SOM 36 research 9 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 Libero 11 X and SynplifyPro do not like un terminated signals and it will remove them from the I O assignments if they were not routed by default to this block As you require a signal terminated at this block simply un route it from the unused block and then re assign to your new IP core using the quick connect option However make sure that if it was an output of the unused block to assign the pin left vacant as unused or if an input then set the attribute to tie LOW The output signal REGSPR is just a necessary signal that is not assigned any I O ball of the FPGA is used internally with in the core to stop Libero 11 X optimization occurring and removing the inputs of this block from the I O assignments Do not remove this output 4 18 SmartFusion2 MSS In the SOM layer sheet of the NetFusion starter project the MSS ARM processor main core is situated in the middle and is shown below If you double click on the MSS block it will expanded and create another window in Libero 11 X on screen Note Refer to the next section for the MSS documentation FCCC_0 i Ag 1 M2S_SOM_MSS_0 COTTO CLK FIC 2 APB Ge NI T L i SEU PADS MODR_DDR_AXI SLAVE FIC_2_APB_MASTER MD
9. On the FlashPro IDE screen click on New Project Enter any project name and make sure you have write permissions to the selected directory you choose file Edit View Tools Programmers Configuration Customize Help Dell sb bbb Configure Device gt RUN Open Project EN View Programmers Programmer Port Programmer Programmer Name Te Status Enabled 1 80945 FashProd 18080945 USB 2 0 Eg Programmer List Window _ P TL an Eos X Warnings Les Figure 44 FlashPro Programming Screen In the drop down menus choose Configuration then select Load Programming File Chose your STP file to program NetFusion Click on the main PROGRAM button center right of the above screen Wait for the programming to complete typically after several minutes If you cannot select the USB programmer correctly check it is plugged in and also click on Refresh Rescan for Programmers button towards the bottom of the screen above Important once the operation to program NetFusion is complete the SmartFusion2 FPGA will re power and start automatically 10 51 research 000 and 5 development e NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 8 References Please refer to online documented support at the Microsemi reference center For M2S SOM F484 hardware documents ple
10. corespi v EN M2S_SOM_CoreUARTapb_0_CoreUAR Set As Root Instantiate in M2S_SOM Open HDL File Check HDL File Create 1 0 Constraint from Module COREAHBLITE 9K Remove Core Definition COREAPB3_LIE COREAXI_OBF Delete from Project corEsPI LB Delete from Disk and Project Properties Figure 40 Instantiating an Imported IP Core in your Fabric Design Whether you wish to instantiate into the SmartFusion2 fabric an imported 3rd party source code core from VHDL Verilog or it is from the vault downloaded from ACTEL the process to get the core into the design sheets is the same and relatively simple Even if the core is a macro as part of the ASIC area of the FPGA the process is the same no matter what area of the design it involves Simply move the left panel to select Design Hierarchy and then right click on the listed core of your choice Select nstantiate in M2S SOM or whichever sheet is displayed on the right pane of Libero IDE The core will appear in the design for you to move and anchor ready for connection routing 47 research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 Note f the core has errors the error report page will appear and the instantiation will not occur 6 2 1 Building and Synthesizing the NetFusion Design Open the Top Level SOM and the MSS sheets Start with the MSS and right click Generate Com
11. Interface MII Fabric Line Speed 100 Management Interface Main Package MII_TXD 3 0 MII TX E MII_TX_ER MII_RXD 3 0 MII_RX_ER MII_RX_DV Click on a signal row to see the preview 4 MII_CRS 4 MII COL MI RX OK ema Fa 4 MII_TX_CLK Figure 33 MSS MAC for 10 100 Ethernet Using SOM PHY This is a very strategic and important module in the MSS of the SmartFusion2 of NetFusion The 4th RJ45 Ethernet connector on the NetFusion PCB is routed directly to the PHY on the M2S SOM F484 which in turn connects into the SmartFusion2 FPGA and directly into the ARM MSS Special Note on the SFP SERDES variant of NetFusion PCB the dedicated SOM RJ45 is the 2 port on the dual HALO Once in the MSS the Ethernet MAC receives the connections which then provide a memory interface internally for the ARM uClinux device drivers for the network interfaces Note The connections route to the fabric before going up through to the I O assignments It is important to emphasize that with NetFusion three of the RU45 10 100 1000 ports use a separate Marvell PHY that routes into the SOM sheet of the starter project and terminates at unused_block_0 Special Note on the SFP SERDES variant two of the 1Gb s ports are 1 25Gb s SERDES However the dedicated 4th port always allows MSS and ARM gateway access to the network Benefits of this architecture can provide IP routing function
12. WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 NetFusion Libero 11 X IDE SoC Top Level Within the NetFusion starter Libero project the 25 SOM Top Level sheet illustrates the lower modules to the design just before the I O ports go out to the real world PCB The ports labeled in this sheet correspond to the I O assignments shown in the previous section This sheet is effectively the linkage from the inner SOM design see next section up to the I O balls of the SmartFusion2 FPGA Libero C Morethanip SmartFusion_SOM Project Project File Edit View Design Tools SmartDesign Help A Design Flow 8 El masoso som 84 8 X Emas soM Mss 8 X Mas som cas 255 ow AA Tool constraint io M2S_SOM_FG484_TOP_synth 4 Timing Constraints amp synthesis M25_SOM_sdc sdc constraint M2S_SOM_FG484_TOP_designet constraint M2S_SOM_FG484_TOP_synthesis H Floorplan Constraints 4 gt Implement Design lt gt Synthesize v 4 gt Verify Post Synthesis Implementation Bl simulate Bi Compile Configure Flash Freeze A Place and Route 4 Edit Constraints VO Constraints Timing Constraints B Floorplan Constraints 4 gt Verify Post Layout Implementation Generate Back Annotated Files Bl Simulate Verify Timing Verify Power 4 gt Edit Design Hardware Configuration
13. directory on your development PC provides an immediate project for your needs Instead of having to start and debug creating an ARM sub system with all of the supporting IP cores required to have a functioning NetFusion PCB just use the provided project From installation you can program the IDE project once synthesized into your NetFusion product using the FlashPro4 USB device This will provide the standard functionality in the Smartfusion2 FPGA fabric on the M2S SOM F484 SOM System On Module to see a working project In the software bundle to this product the uClinux device drivers will drive and control the hardware on the NetFusion PCB through the IP cores in this project for the FPGA fabric Users can contact Nine Ways R amp D for special functionality to be developed and deployed but this serves as an addition to this starter Libero 11 X IDE project Moreover in conjunction with MorethaniP GmbH customized and locked down projects can be tailored for customer requests but that also is separate to this project 1 5 Product Development At the point where the Libero IDE SoC has been installed the NetFusion starter project has been downloaded and exploded into a target directory on your PC the project has been loaded synthesized programmed and shown to be running on the NetFusion PCB product you are ready to begin your development As standard the main fast Ethernet pathways into the SmartFusion2 FPGA fabric are wired in throu
14. the PCB using the open source IP project as a start point will aid and help the user s intended functional product and allow for a start point in their design customization process Intended Audience This document is fully intended to be viewed and reference by Nine Ways customers using the technology for larger designs and projects research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 1 Introduction Microsemi design and manufactured the SmartFusion2 FPGA Libero is the IDE software for programming and synthesizing IP cores Along with the bundle of uClinux firmware compilation tools this is the heart of the NetFusion design process for Users Microsemi 1 1 Libero SoC IDE Version 11 x Derivatives Microsemi s Libero IDE software release for designing with Microsemi Rad Tolerant FPGAs Antifuse FPGAs and Legacy amp Discontinued Flash FPGAs and managing the entire design flow from design entry synthesis and simulation through place and route timing and power analysis PCN 1108 Silicon Family Support in Libero IDE Libero IDE Software Features Powerful project and design flow management e Full suite of integrated design entry tools and methodologies e SmartDesign graphical SoC design creation with automatic abstraction to HDL e Core Catalog and configuration e User defined block creation flow for design re use Synplify Pro ME syn
15. 4 Slot 5 sote Slot 7 Slot8 Slot 9 Slot 10 Slot 11 n Slot 12 Slot 13 Slot 14 Slot 15 Enabled Slave Slots Slot 0 Sot2 Slot 3 Slot 4 Slot 6 Slot 7 Slot 8 Slot 10 Slot 11 Slot 12 Slot 14 I Slot 15 Figure 27 Default APB Configuration Important Note as a Libero 11 X designer and developer the user may change these defaults and added or remove memory accessible IP cores to from the fabric research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 17 Unused Logic Block Specifically to the NetFusion starter project is the instantiated dummy block that allows all of the wires and signals coming into the SmartFusion2 FPGA fabric from the outside PCB that are not connected to IP cores to terminate here Most of these are the Ethernet signals and pathways of the GMII In order to make it easier for a user to instantiate their own IP cores and then connect the unused signals this starter project has had to include the unused signals at the I O level of the FPGA bring them down through the Top Level then into the SOM sheet They then terminate at the unsused_block_0 unused_block_0 i 4 Li 1 1 2 in nudi AT NA A RRMSEEa SEM 1 4 4 lt 4
16. 7 7 M3 can access slot 7 L oe Joe roc J Figure 24 Editing the APB3 core settings Please Note the previous AXI and AHB Lite cores can be edited and changed with exactly the same method by double clicking on the cores themselves research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 16 AXI AHB Lite amp APB3 default Memory Mapped Settings E Configuring COREAXI 0 COREAXI 2 1 101 ioj x Configuration r Memory space Memory space elei 8181818 AXI data width r Enable master access MO can access slave slot 0 MO can access slave slot 1 MO can access slave slot 2 MO can access slave slot 3 MO can access slave slot 4 MO can access slave slot 5 0 can access slave dote MO can access slave slot 7 MO can access slave slot8 0 can access slave slot9 can access slave slot 10 can access slave slot 11 T MO can access slave slot 12 T MO can access slave slot 13 T 0 can access slave slot 14 0 can access slave slot 15 Select AXI channel ID width Testbench License Help z Figure 25 Default AXI Configuration research 9 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 Configuration Memory space Memory sp
17. DR APB SLAVE BASE AI T T Lock o I MOOR_AFB_S_FRESET_N den Ip MDDR S FCLK Mss RESET F2M MSS RESET M3 RESET N E e el A EA EA 55 MDDR DDR CORE RESET MSS_INT_M2F15 0 1 8 vDDR DDR AXI 5 RMW EMSS_INT_F2M 15 0 MMUART 1 MSS_INT_F2M 15 MMUART 1 TXD A Mss NT F2W14 MMUART 1 RXD reset 1 Ip MSS_INT_F2M 13 MMUART 0 PADS IH pk resetn A Mss NT FMZ MAC FABRE E LB MSS_INT_F2M 11 TXD 3 0 LB wee Wr F2Nw10 MAC M L MSS_INT_F2M9 MAC M L MSS_INT_F2MB MAC MI RXD 3 L MSS_INT_F2M7 MAC MI RX A MSS_INT_F2M6 MAC A MSS_INT_F2M5 MSS rage LP MSS_INT_F2MR MAC_MLRX MSS_INT_F2M2 MAC MI TX TP vr 2 1 MSS_INT_F2M0 MAC Figure 29 SOM Module of the ARM MSS 37 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 5 NetFusion ARM Cortex MSS Default Configuration Figure 30 Exploded View of the Modules in the NetFusion ARM MSS The MSS in the heart of the SmartFusion2 NetFusion design is defaulted and set to the exact current needs of the PCB product Modules 2C1 2C2 CAN GPIO RTC and PDMA are disabled currently but there is nothing stopping the user from enabling and wiring out the modules to the SOM sheet The blue modules are currently enabled f
18. E None off SIS TRISTATE None TRISTATE TRISTATE off 8 3 3 3 3 3 3 3 3 3 Off Off Off Off Off Off Sj IS Off Bl V Ports X Package Pins Package Viewer J Ready SmartFusion2 De 250507 Pkg 484 FBGA Figure 4 Example of Bottom List I O Ball Assignments The I O assignment dialog is selected from the I O Constraints anchor in Place and Route section below ynthesize synplify log 25 SOM srr run options txt e Compile t Synthesize M2S SOM rwnetlist log Verify Post Synthesis Implementation M2S SOM compil Bl Simulate 25 SOM compilexml Sp Compile 25 SOM combinatio g Configure Flash Freeze Place and Route DE Place and Route M2S_SOM_gp_report 4 gt Edit Constraints A Generate Programmin BE VO Constraints i M2S_SOM_generatePr Timing Constraints Run PROGRAM Action Bi Floorplan Constraints M25 SOM PROGR 4 b Verify Post Layout Implementation 21 Generate Back Annotated Files SS Simulate Verify Timing Verify Power 4 Edit Design Hardware Configuration constraint M2S_SOM_FG484_TOP_designer constraint M2S_SOM_FG484_TOP_synthesis 9 Floorplan Constraints Implement Design 14 research and development NINE
19. HB matrix memory map and therefore attached IP cores can then have hardware address visibility from the ARM processor software environment REES EEN ___ _ _ oO e 5 5555 88 0 ao Qo Ill ID IQ g Sur Or 2580 59 3 i PEs P Core AHBLite_0 lt 2 2 55 2 aS FE 33 amp z o II TT Figure 22 AMBA Memory Interfaces from ARM for an AHB Lite bus 31 research and Q development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 15 Core APB3 The SOM sheet design has a useful APB3 core instantiated as 0 which is by default used to collate and connect various important cores to the ARM MSS memory map Currently the temperature sensor counter GPIO CoreGPIO 1 the main GPIO core CoreGPIO 0 the UART core CoreUARTapb 0 the two audio SPI cores CORESPI 0 COHESPI 1 and finally the SPI baseboard device IC chip select logic CoreGPIO_2 HRES REMAP HRBADY OUT HRDHTA 50 RESP EN Figure 23 AMBA Memory Interfaces from ARM for the APB3 fixed bus used for the UART GPIO and Counter Peripherals Although the APB3 core is used extensively this can be extended to allow any user instantiated core to be connected by adding anoth
20. ace Address range seen by slave connected to huge 2GB slot interface 0 00000000 Ox7FFFFFFF 0x30000000 OxFFFFFFFF r Allocate memory space to combined region slave Soto Slot 2 Slot 3 Slot 4 Slot6 9 7 Slot 8 Slot 10 Slot 11 Slot 12 Slot 14 Slot 15 Enable Master access MO can access slot 0 1 can access slot 0 M2 can access slot 0 M3 can access slot 0 MO can access slot 1 can access slot 1 M2 can access slot 1 can access slot 1 MO can access slot 2 can access slot 2 M2 can access slot 2 can access slot 2 MO can access slot 3 1 can access slot 3 M2 can access slot 3 M3 can access slot 3 MO can access slot 4 1 can access slot 4 M2 can access slot 4 can access slot 4 Hep Figure 26 Default AHB Lite Configuration research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 Configuration Data Width Configuration Master Data Bus Width 6 32bit 16 bit C Address Configuration Number of address bits driven by master 28 Position in slave address of upper 4 bits of master address 27 24 Ignored if master address width gt 32 bits Indirect Addressing Not in use M r Allecate memory space to combined region slave Slot 0 Slot 1 Sot2 Slot 3 Slot
21. add significant time especially if the design has strict time constraints 49 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 7 Using FlashPro4 IDE to Program NetFusion Install and make use of FlashPro IDE on Windows XP 7 8 OS to allow for the stand alone programming of the baseboard without the need for launching installing or using the full Libero 11 X SoC IDE FlashPro Eege File Edit View Tools Programmers Configuration Customize Help Dell EE TO Microsemi A Version 11 4 1 17 Release 11 4 5 1 Errors Warnings Info esch SE No project loaded Figure 42 Opening screen of FlashPro IDE Launch the IDE so that you see the above screen Also if you have just installed the IDE ensure that you have also installed the FlashPro4 USB device driver in the Windows Device Manager Note the device driver should be automatically installed with the FlashPro installation which is downloadable from the Microsemi website iol 50 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 Ensure that the NetFusion PCB has the ribbon cable attached from the FlashPro4 USB programmer below iv TS Figure 43 Microsemi FlashPro4 ribbon connection
22. ality for the user This is due to the link between the MSS MAC and the fabric MACs only being visible to each other in the uClinux IP stack of the kernel iol 41 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 5 4 MSS CCC Clock Source BASE 83 000 MHz IV Monitor FPGA Fabric PLL Lock CLK_BASE_PLL_LOCK r Cortex M3 and MSS Main Clock CLK 166 MHz 166 000 MHz MSS CCC MDDR Clocks MDDR CLK M3_CLK 1 zl 166 000 MHz Uso DDR SMC FIC 2 83 000 MESS 0 1 Sub busses Clocks 0 2 7 83 000 MHz amiak 2 x 83 000 MHz FPGA Fabric Interface Clocks v FICO CK 2 83 000 MHz FIC 1 CK M3_CLK 2 83 000 MHz Figure 34 MSS CCC Divider from the CLK_BASE with in ARM Sub System The main 166 2 clock into the MSS from the fabric is configured to be split up and if necessary divided down to the different areas of the sub system It is derived from the Div 2 83MHz from the PLL in the fabric In the case of NetFusion and the StarterPack Libero 11 X IDE project all peripherals memory controllers and fabric interfaces run at half the base clock frequency at 83MHz 5 5 RESET Controller Gi Configuring RESET MSS RESET 1 0 100 Configuration Enable FPGA Fabric to MSS Reset MSS RESET F2M
23. ary 2015 4 11 BIBUF Throughout the NetFusion starter project s fabric logic design is scattered around Bi Directional macros These convert conveniently any IN OUT data flow when the RX and TX are kept separate in the IP cores The output side always routes up out of the SmartFusion2 FPGA to the NetFusion PCB hardware where the signals are capable of input output operation using pull up resistors combining tri state operation The instantiated BIBUFs are illustrated in the Figure below They are controlled by an output enable signal that drives the state of the output pin An example of the need for bi directional signal operation is MDIO for the Marvell PHY and the SDA data line for ALL 12C buses on the NetFusion PCB TMT ake US WI BB Edd did Scalar BIBUF 18 Y A t PAD D E BIBUF 16 li PAD D E BIBUF 19 Ni PAD __ E i BIBUF_20 eR D E EE E E E EE E D E oo y T c Figure 19 Bi Directional Fabric Macros for input output signals 28 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 12 CoreSF2Config The SmartFusion2 MSS processor sub system always as standard has a default CoreSF2Config block which loops back an APB bus out and then back into the MSS block This seems at first strange and can be very confusing However i
24. ase visit the Emcraft hardware for the SOM F484 If you need Libero 11 X references from Emcraft this will illustrate the default designs that NetFusion was built from in order to achieve the baseboard functionality iol 52 research 9 and development e NINE WAYS NetFusion Libero Starter Project Helper Contact Nine Ways Research amp Development Ltd V1 1 January 2015 E Mail pbates nineways co uk Internet www nineways co uk UK Unit iDCentre Lathkill House Business Park London Road Derby DE24 8UP United Kingdom Tel 44 0 1332 258847 FAX 44 0 1332 258823 iol 53 research 9 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 10 Document History Document Change Notices DCO Version Description Created Changed By Date Version 1 0 Initial Release according to Paul Bates Nine Ways 17th July 2014 Version 1 0 Version 1 1 Updated the pictures ofthe Bates Nine Ways 23rd January 2015 cores tidied up and added new sections on new cores that have been included in the latest StartPack Libero Project for NetFusion Copyright O Nine Ways R amp D Ltd 2014 All Rights Reserved 54
25. baseboard PCB Various IP cores were added to accommodate the need to support and facilitate the vast multitude of NetFusion s PCB hardware available to the ARM MSS sub system in the SmartFusion2 FPGA on the Emcraft M2S SOM F484 housed on NetFusion as one product As the MSS can only drive and support some of the pins on the SOM unit there was a requirement therefore to add more IP cores in the fabric to interface through the I O assignments to the PCB hardware not connected directly to the MSS These additional cores and the default statutory parts of the SOM design in the Fabric are described in the sub sections below 4 2 ULPI UTMI OTG USB On the SmartFusion2 F484 package that is used with Emcraft s M2S SOM F484 System On Module the ULPI MSS interface is not supported However the UTMI OTG USB signals are supported As the track routing and the IC USB device on the NetFusion PCB support ULPI an IP core in the fabric is require to convert between the two different USB On The Go protocols and signals This has been instantiated as ulpi port 0 This core was used from OpenCores at http www opencores com and resides in the NetFusion starter project s hdl sub directory Figure 9 ULPI UTMI USB Converter IP Core 18 E research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 3 CoreSF2Reset This core is used to co ordinate the reset acro
26. ces and Obfuscated IP Bundle View the complete descriptions of the above Libero installations at http www microsemi com products fpga soc design resources design software libero soc licensing View the IP Bundle contents at http www microsemi com products fpga soc design resources ip cores Libero installation is covered in Installing Libero Software on page 16 Note You must have Admin rights on the installation machine to install Libero SoC research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 1 3 Starting a Project and Basic Understanding Before attempting to modify or implement any project in Libero it is advised that you download and read the following PDF references System on Chip installation Libero SoC v11 X User s Guide Libero SoC Quick Start Guide for Software v10 0 Integrated Development Environment installation Libero IDE and Software Installation and Licensing Guide Libero IDE License Troubleshooting Guide Note Press CNTL and click to download the links 1 3 1 Libero 11 X IDE First Launch Project File Edit View Design Tools Help n WC fui Oa LAO StartPage 4 3 De Libefo System on Chip C Morethanip Smart 3PSWITCH F484 Welcome To Microsemi s Libero SoC v11 4 Software F484 Libero SoC is a comprehensive software suite for designing wi
27. core The obvious exceptions are the Ethernet pathways RS485 UART and the SP audio input output However all of the 2 Relays VO expanders Real Time clock IC voltage monitor expansion I O and all other slow speed communications are handled through this CoreGP O 0 instantiated block It is visible to the ARM MSS processor via an APB interface memory bus Lines can be configured as inputs or outputs and are all individually controlled and observed by the uClinux UIO device driver E GC SIIT Figure 14 Main GPIO Interface with bus from the ARM Processor MSS block 23 iol research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 7 CoreUARTapb As there is no way in the SmartFusion2 ARM MSS block for standard UART connections dev ttyS0 and dev ttyS1 already used the RS484 PCB hardware has to be controlled and handled from a fabric UART core This was instantiated as CoreUARTabp 0 and has an APB connection to the MSS block The uClinux device driver for this hardware access the core as a block of memory and the FIFO RX and TX data is stored in the fabric core The RX ad TX signals to the NetFusion PCB hardware are TTL levels and then get converted to RS485 voltage signals in the electronics Figure 15 RS485 UART IP core research and d
28. cture of the SOM F484 so this is primarily based upon the Emcraft starter project for this block 39 SES research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 5 2 USB DN MSS USB Configurator r Configuration Interface Selection 71 options IO Group Selection v UTMI_LINE_STATE UTMI RX DATA g ali UTMI_TX_READY UTMI_RX_VALID UTMI_RX_ACTIVE H Click on a signal row to see the preview UTMI RX ERROR g ml UTMI_VBUS_VALID UTMI_AVALID UTMI_SESSION_END g 3 UTMI_HOST_DISCONNECT JE JE 525 325 8 2 E 4 UTMI_ID_DIG Figure 32 USB OTG UTMI Host Controller NetFusion does utilize on the PCB hardware an OTG USB interface In the fabric the ULP is converted to UTMI and then connected to this MSS internal block The ARM uClinux application code will be able to access this USB block as a block of memory registers and device drivers will be able to control the USB OTG as a USB stack Note the UTMI signals do not get routed to the I O pins directly but the fabric for the use of the ULPI UTMI converter IP core 4o c research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 5 3 Ethernet MSS Ethernet MAC Configurator p Connectivity Preview
29. development NetFusion Libero Starter Project Helper V1 1 January 2015 NetFusion Libero Starter Project Helper User Guide iol LO research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 Table of Contents 1 INTRODUGTIONI lt i eee EE 6 1 1 LIBERO SOC IDE VERSION 11 X DERIVATIVES 6 BEE RE e EE 7 1 3 STARTING A PROJECT AND BASIC 1 2 sies seriis snnt rris nan 8 1 3 1 Libero 11 X IDE First 8 eeh ee 9 1 5 PRODUCT DEVELOPMENT 9 1 6 DOCUMENTATION CHECKLIST 10 2 DOWNLOADING NEW IP CORE S INTO THE LIBERO IDE INSTALLATION 12 NETFUSION LIBERO I O ASSIGNMENTS ssaa ei nana eee iii 13 4 NETFUSION LIBERO 11 X IDE SOC 15 4 1 EMCRAFT 5 5 0 1 1 18 4 2 ULPUUTMIOTGUSGR EAEE EEEE nnan nann nanena 18 4 3 ere e TT KEE 19 SEGG EE 20 4 5 COUNTER GPIO
30. e Beer Qe Te esti deor e QOO foe Qa De ee he 21 Figure 13 Temperature Sensor LOgiC 22 Figure 14 Main PCB GPIO Interface with bus from the ARM Processor MSS block 23 Figure 15 R9485 UART P core nia e i Mee ee ein ee ee 24 Figure 16 Stereo Audio Line IN amp Line OUT 25 Figure 16 Temp Sensor Counter Logic i 26 Figure 16 Customized RESET logiC Lie aio es d ln 27 Figure 17 Bi Directional Fabric Macros for input output signals sse 28 Figure 18 APB feedback Bus for Peripheral Configuration by Software 29 Figure 19 AMBA Memory Interfaces from ARM for an AXI bus i 30 Figure 19 AMBA Memory Interfaces from ARM for an AHB Lite 31 Figure 19 AMBA Memory Interfaces from ARM for the APB8 fixed bus used for the UART GPIO and Gounter Peripherals audere EORR ERE A ees Gas IRINA 32 Figure 19 Editing the APBS core settings A 32 Figure 20 Default AXI Configuration iii 33 Figure 21 Default AHB Lite Configuration esses 34 Figure 22 Default APB Configuration i 35 Figure 23 Unused Block in NetFusion GON 36 Figure 24 SOM Module of the ARM MSS eene nennen nnne nnne nennen 37 Figure 25 Explod
31. ecklist Libero SoC User s Guide Explains how to use the Libero SoC Project Manager including Designer and SmartDesign SmartFusion2 and IGLOO2 SmartTime I O Editor and ChipPlanner User s Guide Provides details about using SmartTime for timing analysis placing macros floor planning and viewing chip resources for SmartFusion2 MultiView Navigator User s Guide includes documentation for ChipPlanner PinEditor UO Attribute Editor and NetlistViewer in MVN Provides details about placing macros floor planning and viewing chip resources contains information about using NetlistViewer in the MultiView Navigator to view your netlist describes how to use the PinEditor MVN describes how to use the I O Attribute Editor tool Design Constraints User s Guide Provides a complete reference for creating and modifying timing physical and netlist optimization constraints in Libero SoC including families and file formats supported for each constraint It also describes how to create and modify I O constraints with the I O Attribute Editor before compiling your design SmartPower User s Guide Describes how to use SmartPower for power analysis SmartTime User s Guide Describes how to use SmartTime for timing analysis and how to set clock constraints Tcl Command Reference Lists all the Tcl commands and parameters for the Microsemi software tools Analog System Builder FlashROM and Flash Memory System Builder User s Guide De
32. ed View of the Modules in the NetFusion ARM ME 38 Figure 26 MDDR MSS Controlling LPDDR Memory with AXI from Fabric 39 Figure 27 USB OTG UTMI Host Controller nnne 40 Figure 28 MSS MAC for 10 100 Ethernet Using SOM PHY iii 41 Figure 29 MSS CCC Divider from the CLK BASE with in ARM Sub System 42 Figure 30 Reset MSS Module sse eene teen ettet tenerent nennen 42 Figure 31 AHB APB Fabric Interface Il 43 Figure 32 APB3 AHB Lite Fabric Interface ID 44 Figure 33 APB Peripheral Hardware Configuration eene 45 Figure 34 Importing a single Verilog VHDL file into the NetFusion Libero 46 Figure 35 Instantiating an Imported IP Core in your Fabric Design sss 47 Figure 36 Selecting Full NetFusion Synthesis and FPGA Programming sss 49 Figure 36 Opening screen of FlashPro IDE enne nnne 50 Figure 36 Microsemi FlashPro4 ribbon connection nnne emnes 51 Figure 36 FlashPro Programming Screen eee 51 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 About This Document This specification introduces the NetFusion baseboard s Libero IDE starter project Whilst the project ZIP binary is provided as a downloadable target to
33. er slave line to the core This can be obtained by double clicking on the core and editing the settings fa Configuring CoreAHBLite_0 CoreAHBLite 5 0 100 da c Configuration Memory space Memory space 256MB addressable space apportioned into 16 slave slots each of size 16MB n Address range seen by slave connected to huge 2GB slot interface 00000000 7FFFFFFI 80000000 OXFFFFFFFI Allocate memory space to combined region slave Slot 0 Slot 1 Slot 2 Slot 3 E Setz E Sots Slot6 E Set EI Slots 5 5 9 E Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 Enable Master access can access slot 0 can access slot 0 2 can access slot 0 EI M3 can access slot 0 MO can access slot 1 1 can access slot 1 M2 can access slot 1 M3 can access slot 1 can access slot 2 O 1 can access slot 2 2 can access slot 2 can access slot 2 can access slot 3 1 can access slot 3 li M2 can access slot 3 M3 can access slot 3 MO can access slot 4 7 1 access slot 4 M2 can access slot 4 3 can access slot 4 access slot 5 1 can access slot 5 2 can access slot 5 EI can access slot 5 MO can access slot 6 1 can access slot 6 M2 can access slot 6 M3 can access slot 6 MO can access slot 7 Mi access slot 7 7 M2 can access slot
34. etFusion Libero Starter Project Helper V1 1 January 2015 This SOM sheet lower layer contains the ARM Cortex M3 MSS block and then all of the necessary associated IP core blocks to allow the processor the Emcraft SOM and the wider surrounding NetFusion baseboard hardware to and be accessed en eu d D 25 SOM LEE KEE e LE MOOR ARE FOLK MOR CORE RESELN MOD IR ARE RUN wi A MDDR DDR Ax SLOANE nt osco i AS SOE OF 7 Lower Level SOM sheet MSS block The next screenshot shows a rats nest but the following sub sections illustrates the different parts in more detail Note ncidentally the largest module center left is the MSS ARM cortex processor zoomed above 16 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 PH CE TE Figure 8 Screenshot of Lower Level SOM sheet of the StartPack Libero Project 10 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 1 Emcraft Systems The above figure overview encapsulates the whole of the NetFusion SOM sheet However it was built on the basic project supplied currently by Emcraft They designed and developed the M2S SOM F484 that is housed on the NetFusion
35. etFusion PCB product This means that you will not have to consider any of these assignments unless you are planning any major changes to the inherent default design This is very unlikely as you would need then to request changes to the PCB design However this section highlights the assignments in case you also want to make minor changes to the direction of the port default output values and or change internal SmartFusion2 FPGA pull up values File Edit View Tools Help 2 ess PortName A Direction 1 0 Standard Pin Number Locked Bank Name 1 0 state in Flash Freeze mode Resistor Pull 1 0 available Fiash Freeze mode Schmitt Trigger Odt Static Odtimp Ohm LowPowerExit InputDelay Sew DEVRST_N Input RIS EXT_RESET_OUT_N Output wm 05 TRISTATE REC GMII1GTCK Output 1 0525 GM ORO Input K18 IRCK Input K6 TRISTATE TRISTATE off off TRISTATE off off GMII 1RDO Input B1 TRISTATE off off GMILIRD1 Input 82 TRISTATE Off off GMIIHRD2 Input c3 TRISTATE off off 03 Input 2 GMII 1804 Input 4 GMILIRDS Input 83 TRISTATE off off TRISTATE off off TRISTATE off off GMIIIRD6 Input E4 TRISTATE off off Input D4 GMII 1REN H7 TRISTATE off off TRISTATE off off 1 0525 wil off off K7 TRISTATE
36. evelopment NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 8 CoreSPIO 1 Running as separated IP cores instantiated in the fabric to achieve higher speed sampling by SPI software are SPI blocks These are CORESPI_0 and CORESPI_1 and use an APB interface to the ARM MSS sub system Each core has a 4 wire SPI bus routed out of the FPGA to the wider NetFusion PCB hardware These SPI interfaces connect to DAC and ADC stereo IC devices This allows for audio to be sent and received from the PCB and the digital samples can be processed by the ARM processor from network traffic if necessary SPI is used as it is full duplex and runs at over 1MHz during operation However bottlenecks in the processor application code and also human audible hearing limitations keep realistic sampling operations around lt 10KHz Figure 16 Stereo Audio Line IN amp Line OUT 25 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 9 Temperature Sensor Glue Logic The baseboard temperature sensor IC is mounted under the Emcraft SOM daughter card and monitors the temperature of the FPGA that can often be demanded to perform high switching tasks in the fabric of the device The sensor produces an output square wave in which the frequency in Hz is equal to the degrees Kelvin on the baseboard This is routed into the FPGA and the fabric and is repre
37. gh the FPGA ball I O assigned in the I O editor brought down through the Top Level and then into the SOM level of the design in the project They then terminate at a dummy IP core for all un assigned wires this makes life a lot easier for the developer knowing that all the NetFusion traces coming into the M2S SOM F484 are wired into the SOM level of the fabric design Changes are therefore quick and easy to then re assign in that lower level sheet to new instantiated IP cores of the user s choice The category of wires left terminated and not used are the GMII Ethernet pathways Users can download and use Vendor specific MAC SWITCH cores or chose to privately purchase cores from reputable design houses such as All other used hardware on the NetFusion PCB is wired and connected in the SOM sheet layer to GPIO SPI UART USB I2C etc as standard in the starter project If you decide to write and author your own IP cores in Verilog or VHDL you can drop and place the code into the Project Dir hdl directory Note Once you have started to customize and tailor the project to your own needs and functionality obviously renaming the project is easy just rename the project directory and inside that directory just rename the prj file Close and re open the Libero IDE research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 1 6 Documentation Ch
38. heet design and currently has no intended functionality other than providing the user with a hook access point to the AXI ARM MSS system The AXI core has an associated location in the overall ARM AHB matrix memory map and therefore attached IP cores can then have hardware address visibility from the ARM processor software environment o oa e 2 ge o o PDT b 2 SR SE 58 28 959 So Sao Es I 59 ARVALID MO AWBURST M WID M AWADDR MO AWSIZE M Figure 21 AMBA Memory Interfaces from ARM for an AXI bus 30 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 14 Core AHB Lite In the SOM sheet of the design there exists an IP core used for AHB lite memory bus accessing It does not have any memory core attached as default when you open and view the project initially However this stub is the user to use to attach to any AHB lite memory bus interface IP core that they wish to use All of the signals not used are either tied LOW or HIGH if required for input signals and marked as unused if output signals The AHB core is instantiated as CoreAHBLite 0 in the SOM sheet design and currently has no intended functionality other than providing the user with a hook access point to the AHB ARM MSS system The AHB core has an associated location in the overall ARM A
39. hmetic nets Bus Interfaces D Clock amp Managem DSP Vo Macro Library Memory amp Contro Peripherals Processors Tamper mp amba contoler Jownloading core 10 of 67 6 Design F Design Hierar Stimulus Hierar Catalog og ERE ues Aere Downloading Actel DirectCore COREDES 3 0 106 Downloading Actel DirectCore CORESDR 4 0 115 Downloading Actel DirectCore corepwm 4 1 106 Downloading Actel DirectCore COREQEI 2 0 111 Fam SmartFusion2 Die M2S050T Pkg 484FBGA Verilog Figure 2 Libero Updating IP Core in the Vault When you first load the NetFusion starter project into the IDE the most likely occurrence to happen is a system message warning you to update New IP Cores This is because the design includes cores that you possibly do not have on your vault on your local hard drive Click YES to proceed and let the download process complete Note this may take several minutes and you MUST have a network connection and gateway to the internet 12 doy 9 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 3 NetFusion Libero I O Assignments The NetFusion Libero starter project is delivered already with the I O balls of the FPGA assigned ready for the user These all correspond with the pin out tracking assignments on the N
40. ilog VHDL file into the NetFusion Libero Project From time to time you may want to deviate from the default NetFusion Libero 11 X Starter Project If you need to add catalogue cores especially for the fabric macros then download using the vault Also as illustrated above you also may wish to import 3rd party source IP cores To do this on the panel on the left of the Libero IDE right click on Create HDL and then select mport Files This will bring the Verilog VHDL into the main system You can check if the source code has syntax errors and is valid for the synthesizer Libero 11 XSynplify Pro that Libero 11 X uses This mechanism enables the NetFusion project to be customized and built on for a users system requirements iol 46 000 research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 6 2 Instantiating into the Fabric Libero C NetFusion M25 SOM F484 CAT5 NetFusion F484 prjx Project File Edit View Design Tools SmartDesign Help 0 Design Hierarchy 8 zo 8 x E 25050 50 rese rop x ire EMITE TE EET x 00 6 Od work melt lM A XTLOSC_FAB osc_comps v B RCOSC_1MHZ_FAB osc_comps v 5 1 2 osc_comps v Bg 25050 SOM FG484 TOP E 25 FA M2S_SOM_COREAXI_0_COREAXI cor B CoreGPIO coregpio v CoreSF2Config coresf2config v A CoreSF2Reset coresf2reset v E CORESPI
41. or the NetFusion design as they have functional requirements and the signals are wired out to the SOM sheet then if necessary up to the I O assignments then out of the FPGA device itself 38 dol research and development e NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 5 1 MDDR e Mss External Memory Configurator E Import Configuration Export Configuration Restore Defaults General Memory Initialization Memory Timing Memory Settings Memory Type por sl Data Width 16 SECDED Enabled ECC Arbitration Scheme 3 HghstPioty 2 Address Mapping ROW BANK COLUMN 7 IV Fabric Interface Settings Use an AXI interface Use an AHBLite Interface Use two AHBLite Interfaces Figure 31 MDDR MSS Controlling LPDDR Memory with AXI from Fabric The MDDR has been configured to use a single data rate LPDDR SDRAM device the M2S SOM F484 using 16 bit data width Priority has been given to the AXI master interface from the fabric where the default connection is to the AMBA DMA Controller for 3rd party MACs and Ethernet SWITCH If you do not wish to keep the DMA Controller or any AXI interface for that matter then you can de select the Fabric Interface and the SOM sheet will adjust accordingly Important You will have to remove and delete the instantiated DMA Controller however Note NetFusion has to follow the archite
42. ponent If errors eliminate then perform previous instruction over again Once successful move to the SOM sheet Right click Generate Component If errors eliminate then perform previous instruction over again Once successful move to the Top Level sheet Right click Generate Component If errors eliminate then perform previous instruction over again iol 48 _ NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 Libero C NetFusion M2S SOM F484 CAT5 NetFusion F484 prjx B 0 i 798 Floorplan Constraints E b Verify Post Layout Implementation L Generate Back Annotated Files B simulate Ch Verify Timing P Edit Design Hardware Configuration Jl Programming Connectivity and Interface amp Programmer Settings i Device I O States During Programming Configure Security and Programming Security Policy Manager Bitstream Configuration E Update eNVM Memory Content Program Design Generate Programming Data Debug De Update and Run HQ Identify Run SmartDe Clean and Run All Clean View Report E Messages E Reading file mr Figure 41 Selecting Full NetFusion Synthesis and FPGA Programming Once you are ready to synthesize and program the SmartFusion2 FPGA on the M2S SOM F484 housed on NetFusion select the option shown above Note This should take around 20 minutes on a standard Windows XP 7 8 PC However larger customized design will
43. rocessor This can be bare metal code or early boot code from uClinux called u boot This MSS module block enables the signals to connect a feedback APB interface from the ARM processor to the other peripherals in the MSS itself It seems an overkill but that is the architecture we are ruled by it seems In the case of NetFusion we configure the FIC 0 and FIC 1 fabric interface controllers and also select the AXI Slave interface for the MDDR block Important Note do not ever remove this feature from the design of NetFusion The system will not operate if deleted io 45 9 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 6 Adding IP Cores from Verilog VHDL 6 1 Importing Source Files Libero C NetFusion M25 SOM F484 CAT5 NetFusion F484 prjx n Edit View ue Tools ie cx I E 25 50 amp x 25050_5 _ 484_ x Create Design amp System Builder amp Configure MSS Create Constraints 1 0 Constraints constraint jo M2S050_SOM_FG484_ constraint jo M2S_SOM io pdc constraint io M2S_SOM_FG484_TO Timing Constraints synthesis M2S_SOM_sdc sdc constraint M2S_SOM_FG484_TOP_ Sj constraint M2S_SOM_FG484_TOP_ Qi Floorplan Constraints Design gt Synthesize Verify Post Synthesis Implement Figure 39 Importing a single Ver
44. scribes how to use the FlashROM generator the Analog System Builder and the Flash Memory System Builder SmartGen Cores Reference Guide Provides descriptions of cores that can be generated from the Catalog using the SmartGen Core Builder research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 FlashPro User s Guide Contains information about how to program your devices using the FlashPro software and device programmer FlashPro is not available on UNIX SmartFusion2 and IGLOO2 Macro Library Guide Provides descriptions of Microsemi library elements for the Microsemi SmartFusion2 and IGLOO2 device families Symbols truth tables and module counts if appropriate are included for all macros IGLOO ProASIC3 SmartFusion and Fusion Macro Library Guide Provides descriptions of Microsemi library elements for Microsemi SmartFusion Fusion ProASIC3 and ProASICSE device families Symbols truth tables and module counts if appropriate are included for all macros SmartFusion2 and 2 Block Flow User s Guide Describes how to create and integrate Blocks in Libero SoC for SmartFusion2 and IGLOO2 VHDL Vital Simulation Guide Contains information about using the ModelSim to simulate designs for Microsemi SoC devices Verilog Simulation Guide Contains information about interfacing the FPGA development software with Verilog simulation tools ViewDraw User
45. sented on the SOM design sheet as TEMP SENSOR This in turn clocks the counter16 0 which has a 16 bit register output and can be read into the ARM software environment via the CoreGP O 1 core Although this read value wraps around 16 bit values the software can use a one second timer to run comparisons and then calculate the temperature in Kelvin Figure 17 Temp Sensor Counter Logic 000 Q9 O0 research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 10 Coordinated RESET The customized IP core instantiated as mtip_reset_1 coordinates a longer reset pulse than the power on reset core often provides The source SYSRESET_0 feeds into the mtip reset 1 which then provides an output to the whole SOM sheet design This includes the ARM MSS block memory cores GPIO and all peripherals p i 74 a z d MS RESET N BR cR CORE NOOR DORAN S EMSS 2 152 2 vwssONDEM S i eseu Zb SSN EM ISSN aen I veswCrowg I 5 7 MS L esu MSS INT MSS INT MSS INT 2 5 MSS INT EM LB mM MSS INT 2 21 L NSSINT AMI MSS_INT_F2MO H i Figure 18 Customized RESET logic 27 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 Janu
46. ss all of the FPGA in strict timed sequence It is important for the peripheral logic to be released after the MSS ARM processor and then the fabric logic following the MSS This is a standard Libero ACTEL core from the vault The EXT_RESET_OUT signal is routed out of the FPGA device to the NetFusion PCB The input to this core is the POWER ON RESET This core was instantiated as CoreSF2Reset_0 Figure 10 SmartFusion2 Reset Controller IP Core research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 4 FCCC The entire FPGA sub system comprising of the MSS ARM processor and the main fabric run on clocks all generated from this core It is the main coordination of the clock lines that are distributed The input is 12MHz from an off chip crystal IC The CCC PLL divides down the 12MHz source by 12 to 1 2 Then this is multiplied up by differing amounts for GLO You can add more clock PLL lines as you wish when you are modifying the design FCCC_0 XTLOSC_CCC_IN Figure 11 Clock PLL Macro Core The core as been instantiated as FCCC_0 There is also a LOCK output signal that is used by the MSS to determine when the PLL has settled and locked onto the desired output frequencies All clock outputs are digital square waves iol 20 SC NetFusion Libero Starter Project Helper V1 1 January 2015
47. t is the inherent architecture of the FPGA ASIC area that most of the peripheral devices inside the MSS ARM processor core are not actually controlled by the selections made in the Libero 11 X IDE It is the software in U boot during boot up that configures If say for instance an AHB Lite interface is selected in Libero then this does not configure the SmartFusion2 FPGA itself It saves a configuration file that can be included by software in either bare metal programming or the u boot from Emcraft uClinux environment Only when the boot up code access the APB feedback bus via CoreSF2Config_0 and manipulates hardware peripheral memory address does the peripherals in the MSS get the correct mode of operation intended for them Figure 20 APB feedback Bus for Peripheral Configuration by Software iol 29 research and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 4 13 Core AXI In the SOM sheet of the design there exists an IP core used for AXI memory bus accessing It does not have any memory core attached as default when you open and view the project initially However this stub is the user to use to attach to any AXI memory bus interface IP core that they wish to use All of the signals not used are either tied LOW or HIGH if required for input signals and marked as unused if output signals The AXI core is instantiated as COHEAXI 0 in the SOM s
48. th Microsemi s SmartFusion2 and SmartFusion SoC FPGAs and IGLOO2 IGLOO ProASIC3 and Fusion FPGA families Visit the Documents tab on your device page at www microsemi com to obtain silicon Datasheets Silicon User s Guides Tutorials and Application Notes Development Kits and Starter Kits are available from the Microsemi website to Libero SOC What s New in Libero SoC Libero SoC Quickstart Libero SoC Interface Description Libero SoC Release Notes on the Web Libero Ul Enhancements New Tool flow for Simulation Support for VHDL Constructs like Records Array of Arrays Libero Tutorials Non IDE Flow New HDL Text Editor Product Tutorials New Reporting Structure Training Webcasts Dynamic On Die Termination ODT added in DDR Mode Microsemi SoC Website Design Entry and Implementation Learn more System Builder Update o Added Independent PCle resets for M2S090 GL090 Ontinn far humancina ALDI ita Be Log Szen Warnings Fam Die Pkg Figure 1 Libero 11 X IDE Boot Up Screen research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 1 4 NetFusion When purchasing any NetFusion variant an important component of the overall product is the Libero starter project that is provided by Nine Ways Research amp Development Ltd This is downloadable from Nine Ways R amp D Ltd and when expanded into a target
49. thesis fully optimizes Microsemi FPGA device performance and area utilization e Synphony Model Compiler ME performs high level synthesis optimizations within a Simulink amp environment research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 Modelsim ME VHDL Verilog behavioral post synthesis and post layout simulation capability Physical design implementation floor planning physical constraints and layout Timing driven and power driven place and route e SmartTime environment for timing constraint management and analysis SmartPower provides comprehensive power analysis for actual and what if power scenarios Interface to FlashPro programmers Post route On Chip Debug Tools and Identify ME debugging software for Microsemi flash designs Silicon Explorer Il debugging software for Microsemi antifuse designs 1 2 Installation Libero software is downloadable for free from http www microsemi com products fpga soc designresources design software libero soc downloads Some Libero features are optional during installation You can minimize the disk space required by only installing tools you use You must have a license to run Libero the license type that you obtain determines what devices you can use and what IP is included The following license types exist for Libero Libero Platinum All devices and RTL IP Bundle Libero Gold Limited devi
50. troller uses AX for the main data throughput the AHB Lite is used to access the configuration registers Note you will observe that Fabric Region 2 0x7000000 0x7FFFFFF has been allocated to the next FIC_1 block next sub section The configuration on the left panel above selects mapping for both FIC_0 and FIC_1 NetFusion assigns Fabric Region 2 to the APB memory interface so that the UART SPI and GPIO can be accessed in the fabric otherwise only this AHB Lite interface would be mapped which would severely limit the NetFusion functionality and capability 43 E J m J NetFusion Libero Starter Project Helper V1 1 January 2015 5 7 FIC 1 Mss Fabric Interface Controller FIC 1 Configurator Figure 37 APB3 AHB Lite Fabric Interface 2 Using the configuration from the previous FIC 0 block previous this MSS module enables the APB interface to access the GP O SPI and UART in the NetFusion SmartFusion2 fabric Note this is also an APB Master as the ARM processor has complete control jo 44 NINE WAYS NetFusion Libero Starter Project Helper V1 1 January 2015 5 8 FIC 2 Peripheral Initialization cortex zl Fabric DDR and or SERDES Blocks Iv li ONFIG PRESET Figure 38 APB Peripheral Hardware Configuration As described earlier in this document the SmartFusion2 FPGA is setup and primarily configured by boot up software executed by the ARM p
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