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VS1005g Datasheet

1. Digital DAOSET_CF Sampl DAOSET_LEFT paren DAOSET_RIGHT 24 upconverter 74 DAC_SRC DAC_VOL DAC Sample rate output ae LERT upconverter drivers DAC_RIGHT 24 with filters 24 24 24 12S_CF I2S_BCK I2S_FRM_ I2S_LEFT 32 16 12S_D I2S_RIGHT 24 SRC_CF 7 Filterless RED Pin sample rate SRC_LEFT e a p BLUE Register down 24 SRC_RIGHT converter SP_LDATA S PDIF SPDIF_OUT SP_RDATA 24 encoder 24 16 Figure 17 VS1005g playback DA audio paths The VS1005g playback audio paths are shown in Figure 17 The nominal high quality audio path egins from registers DAC_LEFT and DAC_RIGHT then goes through the Sample Rate Upconverter with Filters and the Volume Control to the DAC and finally to the LEFT and RIGHT output pins CBUF is used as a ground reference For lower quality sound effects secondary audio with a potentially different sample rate can be independently added to the signal through the DAOSET_LEFT and DAOSET_RIGHT registers The upconverter for this path contains only sample and hold filtering so using low sample rates may result in audible aliasing The combined main and secondary audio path signal can optionally also be copied to the 12S output Alternatively the 12S output can be controlled directly using registers 12S_LEFT and I2S_RIGHT The main audio path may be intercepted and downsampled with the Filterless Sample Rate Downconverter Because the downco
2. ANA_CFO_ Input Input Set Check Also M1FM M1LIN M1MIC Pin s Pin Name s 0 1 0 73 LINE1_1 1 1 0 68 LINE2_1 0 0 0 71 LINES 1 1 0 1 72 73 MIC1P ANA_CF2_AMP1_ENA MIC1N ANA_CF3_GAIN1 2 0 1 0 0 75 76 RF_N amp RF_P ANA CF2_AMP1_ENA I signal ANA_CF2_LNA ENA ANA_CF2 2G ENA ANA_CF3_FMDIV 1 0 ANA_CF3_DIV 1 0 ANA_CF3_GAIN1 2 0 ANA_CF3_2GCNTA 3 0 AD_CF_DEC6ENA AD_CF_DEC6SEL 1 0 Version 0 63 2014 12 19 59 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS ADC2 Signal Path Configuration Note Always set ANA_CF2 bits ANA_CF2_REF_ENA and ANA_CF2_M2_ENA ANA_CFO_ AD_CF_ Input Input Set Check Also M2FM M2LIN M2MIC AD23_FLP Pin s Pin Name s 0 1 0 0 72 LINE1_2 1 1 0 67 LINE2 2 0 0 0 0 70 LINE3 2 1 0 1 0 70 71 MIC2P amp ANA_CF2_AMP2_ENA MIC2N ANA_CF3_GAIN2 2 0 1 0 0 0 75 76 RF_N amp RF_P ANA_CF2_AMP2_ENA Q signal ANA_CF2_LNA_ENA ANA_CF2 2G ENA ANA_CF3_FMDIV 1 0 ANA_CF3_DIV 1 0 ANA_CF3_GAIN2 2 0 ANA_CF3_2GCNTA 3 0 AD_CF_DEC6ENA AD_CF_DEC6SEL 1 0 x x x 1 69 LINE1_3 ADC3 Signal Path Configuration Note Always set ANA_CF2 bits ANA_CF2_REF_ENA and ANA_CF2_M2_ENA ANA_CFO_ AD_CF_ Input Input Set Check Also M2FM M2LIN M2MIC AD23_FLP Pin s Pin Name s x x x 0 69 LINE1_3 0 1 0 1 72 LINE1_2 0 0 0 1 67 LIN
3. RTC Interface Registers Reg Type Reset Abbrev Description OxFEAO r w 0 RTC_LOW RTC data register bits 15 0 OxFEA1 r w 0 RTC_HIGH RTC data register bits 31 16 OxFEA2 r w 0 RTC_CF 4 0 RTC if control and status register RTC_CF Bits Name Bits Description RTC_CF_GSCK 4 Generate serial clock for RTC RTC_CF_EXEC 3 RTC execute instruction RTC_CF_RDBUSY 2 Read cycle init and busy flag RTC_CF_DBUSY 1 Data cycle init and busy flag RTC_CF_IBUSY 0 Instruction cycle init and busy flag RTC_LOW and RTC_HIGH are the rtc_if data registers Write to RTC_CF registers busy bits start a data transfer to from RTC When the operation has finished the status bit is reset and result can be read from RTC_HIGH and RTC_LOW registers or RTC_HIGH and RTC_LOW registers were transferred to RTC RTC_IBUSY is the instruction cycle initialization register When RTC_IBUSY is set the cur rent content of RTC_HIGH and RTC_LOW registers is transferred to RTC and latched to its instruction register When rtc_if is ready it resets the RTC_IBUSY RTC_DBUSY is the data cycle initialization register When RTC_DBUSY is set the current content of RTC_HIGH and RTC_LOW registers is transferred to RTC data buffer When rtc_if is ready it resets the RTC_DBUSY RTC_RDBUSY is the data read cycle initialization register Before reading rtc a valid in struction must be in RTC instruction register RTC_ READRTC R
4. USB_CF_MASTER 9 Set for master host mode USB_CF_RSTUSB 8 Reset receiver set to 0 USB_CF_USBENA 7 Enable USB USB_CF_USBADDR 6 0 Current USB address USB_CTRL Bits Name Bits Description USB_CTRL_BUS_ RESET 15 Interrupt mask for bus reset USB_CTRL_SOF 14 Interrupt mask for start of frame USB_CTRL_RX 13 Interrupt mask for receive data USB_CTRL_TX 11 Interrupt mask for transmitter empty idle USB_CTRL_NAK 10 Interrupt mask for NAK packet sent to host USB_CTRL_TIME 9 Interrupt mask for bus timeout USB_CTRL_SUSP 8 Interrupt mask for suspend request USB_CTRL_RESM 7 Interrupt mask for resume request USB_CTRL_BR_START 6 Interrupt mask for start of bus reset USB_CTRL_DCON 5 Interrupt mask for usb disconnected USB_CTRL_CF 0 USB Configured 0 1 transition loads dtogg host and dtogg device USB ST Bits Name Bits Description USB_ST_BRST 15 Bus reset occurred USB_ST_SOF 14 Start of frame USB_ST_RX 13 Receive data USB_ST_TX_HLD 12 Transmitter holding register empty USB_ST_TX_EMPTY 11 Transmitter empty idle USB_ST_NAK 10 NAK packet sent to host USB_ST_TIME 9 Bus time out USB_ST_SUSPI 8 Device suspended USB_ST_RES 7 Device resumed USB_ST_MTERR 6 Bus reset start USB master toggle error USB_ST_STAT 5 Device disconnected Status setup USB_ST_SPD 4 USB speed USB_ST_PI
5. Version 0 63 2014 12 19 108 NLS VS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 20 10 Bit Successive Approximation Register Analog to Digital Converter SAR VS1005g has a 10 bit ADC with following features e Successive Approximation Register conversion SAR Before SAR can be used the following analog control registers must be configured Up to 5 analog input channels Up to 0 1Msps conversion speed AVDD voltage as reference input range from OV to AVDD Continuous or software enabled once only operation modes Analog configuration for SAR Register Name Address Value Description ANA_CF2 OxFED2 0x0008 Analog reference ANA_CF1 OxFECB 0x0100 SAR power down SAR operation is controlled with configuration register and the 10 bit data is stored in the data register SAR generates an interrupt as the data register is updated SAR Data Register Reg Type Reset Abbrev Description OxFECD r 0 SAR_DAT 9 0 10 bit SAR data register SAR Control Configuration Register Reg Type Reset Abbrev Description OxFED6 r w 0x003F SAR_CF 11 0 SAR control register SAR_CF Bits Name Bits Description SAR_CF_SEL 11 8 SAR input selection SAR_CF_ENA 7 SAR initialize read cycle SAR_CF_MODE 6 SAR operation mode SAR_CF_CK 5 0 5 0 SAR Clock divider register
6. Version 0 63 2014 12 19 65 ONY vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS The VCO frequency is 24 20 or 16 times the FM tuning frequency i e for 95 0 MHz FM channel the VCO frequency must be set to 1 900 GHz The target VCO frequency can be calculated from equation Foco 4 x VCOdin CCF x Frta where CCF is defined as CCF SEs 16 and the FM channel frequency can be given as Fry 4 x VCOgiy CCF x Fietat F Mai For Hi Speed USB FMCCF registers must be reset when XTALI 12 000 MHz is used When XTALI 12 288 MHz is used the registers are initialized to OxFF87 OxFFFF 7864321 FM_CF register is initialized to value 0x0041 This makes VCO frequency of 1 92GHz which results to 480 MHz USB clock FM_PHSCL Bits Name Bits Description FM_PHSCL_I 7 0 15 8 scaling factor FM_PHSCL_Q 7 0 7 0 Q scaling factor FM_PHSCL register is used to compensate and Q signal s phase and amplitude error This error depends from several factors and values should be calculated for each FM band The compensation logic is enabled when FM_CF_PHCOMP register is set Typical values are 111 for I scaling and 137 for Q scaling DEC6_LEFT DEC6_LEFT_LSB DEC6_RIGHT and DEC6_RIGHT_LSB are the FM demodu lator output data registers Sample rate 12 288 MHz is 32 kHz XTALI 384 11 9 3 Radio Data System RDS FM demodulator includes an RDS module This module decodes the RDS b
7. lt I lt lt lt lt lt 8000 i ee S T Version 0 63 2014 12 19 39 ENbe vS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 VS1005g Peripherals and Registers 11 1 The Processor Core VS_DSP is a 16 32 bit DSP processor core that also has extensive all purpose processor fea tures VLSI Solution s free VSIDE Software Package contains all the tools and documentation needed to write simulate and debug Assembly Language or Extended ANSI C programs for the VS_DSP processor core VLSI Solution also offers a full Integrated Development Environment VSIDE for full debug capabilities 11 2 VS1005g Memory Map VS1005g s Memory Map is shown in Figure 16 Note that when loaded the VLSI Solution Operating System VSOS allocates some User Instruction RAM User X Data RAM and User Y Data RAM 0x0000 0x0000 0x0010 0x0010 0x0080 0x0400 0x0080 0x0400 0x0500 0x0870 0x0500 0x0870 0x7000 0x7000 0x7B00 0x7B00 0x7FC0 0x7FC0 0x8000 0x8000 Instruction ROM OxF400 i OxF400 OxF800 OxF800 OxFC00 OxFC00 OxFFFF oo l OxFFFF Figure 16 VS1005g s memory map Version 0 63 2014 12 19 40 NLS 11 3 VS1005g Peripherals VS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS System peripherals are located in Y address space The peripherals that use PLL clock are in addresses 0xFC
8. SAR_CF_ENA is used to start SAR cycle When this register is set the SAR measures voltage from a given channel and stores the 10 bit value to SAR_DAT register SAR_CF_ENA is reset when the result is ready and can be read from data register SAR_CF_CkK 5 0 is used to select the interface clock speed divider The SAR clock runs at XTALI 32x SAR_CF_CK 1 SAR_CF_MODE selects between continuous mode 1 and run once 0 modes SAR input channel is selected with SAR_CF_SEL 3 0 register This register is double buffered against possible conversion time changes The register is sampled as the SAR is enabled or it is in idle state In continuous mode the register is sampled at the end of each conversion Version 0 63 2014 12 19 109 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS SAR input channel selection Decimal Hex Package Pin Max Voltage Description 12 OxC 67 3 6 V aux0 10 OxA Internal 3 6 V Divided VHIGH 8 0x8 Internal 78 3 6 V RCAP 1 2 or 1 6 V reference voltage 7 Ox7 68 3 6 V aux1 6 0x6 Internal 64 1 95V RTC voltage 5 0x5 Internal 1513 1 95V Core voltage CVDD 4 0x4 71 3 6 V aux4 2 0x2 70 3 6 V aux3 0 0x0 69 3 6 V aux2 1 Although connected to a pin this voltage is normally generated by VS1005g In a typical case this pin should not be driven externally 2 Maximum allowed external vo
9. j Figure 18 VS1005g recording AD and FM signal paths VS1005g has three 24 bit AD input channels and an FM receiver The signal paths for them are shown in Figure 18 ADs 1 and 2 can be configured for mic or line input mode stereo AD AD 3 can be used as a line input mono AD However if AD_CF_AD23_FLP is set then analog channels 2 and 3 are crossed before the analog to digital converters This makes it possible to use AD3 as a mono microphone input e g pins MIC2N and MIC2P potentially at a different sample rate from a stereo line input to AD1 and AD2 e g to pins LINE1_1 and LINE1_3 When the FM receiver is used only AD 3 is available for other uses because the FM demodulator reserves the signal paths of ADs 1 and 2 All of the logic is clocked directly with the XTALI 11 13 MHz FM and AD digital peripheral clocks can be switched off to save power In order to use FM or and AD channels the master clock enable registers REGU_CF_ADOFF and REGU_CF_FMOFF must be reset Analog and RF logic clocking is automatically switched on when blocks are enabled The front end of the ADs analog section i e ADC always operates at XTALI 2 The digital logic has a programmable sample rate Sample rates are between 24kHz and 192kHz It should be noted that the exact sample rates are XTALI dependent and here it is assumed that XTALI 12 288 MHz Version 0 63 2014 12 19 58 NLS 11 VS1005g Datasheet VS1005G PERIPHERALS A
10. SAR Characteristics Parameter Symbol Min Typ Max Unit SAR resolution 10 bits Input amplitude range 0 AVDD V SAR sample rate 100 kHz Integral Nonlinearity INL 2 LSB Differential Nonlinearity DNL 0 5 LSB 1 XTALI dependent 5 6 FM Characteristics FM Characteristics Parameter Symbol Min Typ Max Unit Channel frequency range 10 kHz steps 76 108 MHz FM mono S N Ratio deviation 22kHz Input level 50dBm LSNR 72 dB FM stereo S N Ratio deviation 45kHz Input level 50dBm LSNR 47 dB FM mono S N Ratio deviation 22kHz Input level 90dBm LSNR 45 dB FM stereo S N Ratio deviation 45kHz Input level 90dBm LSNR 27 dB Total harmonic distortion deviation 75 kHz THD 0 1 0 3 Stereo separation 40 dB 1 Measured over whole FM band Version 0 63 2014 12 19 12 ENO vst 005g Datasheet 5 CHARACTERISTICS amp SPECIFICATIONS 5 7 Analog Characteristics of Regulators Parameter Symbol Min Typ Max Unit IOVDD Recommended voltage setting range 1 7 3 6 V Voltage setting step size 55 60 65 mV Default setting reset mode 1 1 8 V Default setting active mode 1 8 3 6 V Load regulation 4 0 mV mA Line regulation from VHIGH 2 0 mV V Continuous current 304 60 mA IOVDD2 Recommended voltage setti
11. Version 0 63 2014 12 19 67 NLS 11 10 SPI Peripherals VS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS VS1005g has two SPI serial to paralle peripherals which can be configured as a master or a slave Before SPls can be used the VS1005g I Os must be configured to peripheral mode e set I O pins to peripheral mode GPIO1_MODE register selects between spi mode or gpio mode e Embedded Serial Flash disabled SYSTEMPD_SFENA bit reset when using SPIO also boot device e Buffered SPI slave disabled ETH_RXLEN_PMODE bit reset when using SPI1 SPIO and SPI1 pins are mapped to GPIO1 port To select peripheral mode the bits in GPIOx_MODE register must be set HIGH SPI pins and their GPIOx_MODE register SPI id VS1005g pin Type SPI pin GPIO_MODE register Description SPIO XCSO GPIO1 0 i o XCS GPIO1_MODE 0 Master slave chip select SPIO SCLKO GPIO1 1 i o sclk GPIO1_MODE 1 Master slave clock SPIO MISOO GPIO1 2 i o miso GPIO1_MODE 2 Master input slave output SPIO MOSIO GPIO1 3 i o mosi GPIO1_MODE 3 Master output slave input SPI1 XCS1 GPIO1 4 i o XCS GPIO1_MODE 4 Master slave chip select SPI1 SCLK1 GPIO1 5 i o sclk GPIO1_MODE 5 Master slave clock SPI1 MISO1 GPIO1 6 i o miso GPIO1_MODE 6 Master input slave output SPI1 MOSI1 GPIO1 7 i o mosi GPIO1_MODE 7 Master output slave input The SPls are ma
12. A USB 2xSPI 3xGPIO SPDIF NF SD ETHERNET Peripheral Bridge v vvv Digital Filters FM Demodulati UART TIMERS WATCHDOG BACKUP RAM Figure 15 VS1005g block diagram 8 1 1 Regulator Section UART BUS 12S BUS RTCVDD CLK32K The VHIGH pin in the regulator section is used as a common main power supply for voltage regulation This input is connected to three internal regulators which are activated when the PWRBITN pin voltage is kept above 0 9 V for about one millisecond so that AVDD starts to rise and reaches about 1 5 V After the PWRBTN has given this initial start current the regulators reach their default voltages even if the PWRBTN is released VHIGH must be sufficiently about 0 3 V above the highest regulated power normally AVDD so that regulation can be properly performed The PWRBTN state can also be read by software so it can be used as one of the user interface Version 0 63 2014 12 19 29 ENO vst 005g Datasheet 8 VS1005G GENERAL DESCRIPTION buttons A power on reset monitors the core voltage and asserts reset if CVDD drops below the CMON level It is also possible to force a reset b
13. o O t Optional boot ident 18 EWRD 511 code NandFlash Type Configuration Low byte Description byte 0x4 0 512 16B small page flash with 2 byte block address lt 32 MiB 1 2048 64 B large page flash with 2 byte block address lt 128 MiB 2 512 16 B small page flash with 3 byte block addr gt 32 MiB lt 8 GiB 3 2048 64 B large page flash with 3 byte bl addr gt 128 MiB lt 32 GiB 4 512 16B small page flash with 4 byte block address gt 8 GiB 5 2048 64 B large page flash with 4 byte block address gt 32 GiB Version 0 63 2014 12 19 35 ENO vst 005g Datasheet 10 FIRMWARE OPERATION If bytes 14 16 EWRD contain BoOt the value in bytes 10 and 11 determines how many sectors are read from NAND flash Note that 0 is interpreted as 1 After the data is read into memory the boot records in this data are processed transferring code and data sections into the right places in memory and possibly executed If an unknown boot record is encountered booting is stopped and control returns to the firmware code NandFlash Record Configuration Code byte Description 17 16 type 0x8000 I mem 0x8001 X mem 0x8002 Y mem 0x8003 execute 19 18 data length in words 1 0 1 word 1 2 words etc 21 20 address record address 22 data 10 3 UART Boot Monitor When byte Oxef is sent to RX at 115200 bps the firmware en
14. 5 CHARACTERISTICS amp SPECIFICATIONS 5 2 Recommended Operating Conditions Voltage Specification Parameter Symbol Min Typ Max Unit Operating temperature 40 85 C Analog and digital ground AGND DGND 0 0 V Regulator input voltage VHIGH AVDD 0 3 4 0 5 25 V Analog positive supply AVDD 2 75 28 36 v Digital positive supply CVDD 1 65 1 8 11 95 V Digital RTC supply RTCVDD 1 2 1 5 1 95 V I O positive supply IOVDD 1 8 2 8 3 6 V 1 Must be connected together as close the device as possible for latch up immunity At least 4 0 V is required for compliant USB level 3 Regulator output of the device Oscillator Specification Parameter Symbol Min Typ Max Unit Input clock frequency XTALI 11 12 2887 13 MHz Input clock duty cycle 40 50 60 Oscillator frequency tolerance 10 ppm Startup time 1 ms Internal clock frequency USB connected CLKU 60 60 MHz Internal clock frequency USB disconnected CLKI 98 MHz RTC clock frequency XTALI_RTC 32768 Hz RTC frequency tolerance 100 ppm RTC oscillator startup time 1000 ms 1 The maximum sample rate that can be played with correct speed is XTALI 128 With 11 MHz XTALI sample rates over 85937 Hz are played at 85937 Hz 2 When full speed FS or Hi Speed HS USB is used it is recommended that XTALI of 12 288 MHz or 12 0 MHz is used The ROM
15. a 29 8 1 2 WVOSection m Wm cores 30 8 1 3 DigitalSection gg Be 2 ee 30 8 2 Analog Section 3 Sam Wh es 32 9 Oscillator and Reset Configuration 33 10 Firmware Operation 34 10 1 SPIBoot gt 25 2 s a Wo AEG RE ee RES 34 10 2 NAND FLASH Probe Wr 624 6 2 SG4 4456444 54554 295 35 10 3 UART Boot Monitor gee ee ce es 36 10 4 Default Firmware Features 2 2 000 eee ee eee 37 10 4 1 SD Card Test A es 37 10 4 2 USB Mass Storage and Audio Device 37 10 5 Supported Audio Decoders 000 ee ee 38 10 5 1 Supported MP3 MPEG layer III Decoder Formats 38 10 6 Supported Audio Encoders 0 00 ee es 39 10 6 1 Supported MP3 MPEG layer Ill Encoder Formats 39 11 VS1005g Peripherals and Registers 40 11 1 The Processor Core anaana aaa ee 40 Version 0 63 2014 12 19 3 ENO vst 005g Datasheet CONTENTS 11 2 VS1005g Memory Map 02 0 5 00 8 4 40 11 3 VS1005g Peripherals 2 2222 eee ee eee ge 41 11 4 Interrupt Controller 2 20225 2 eee ee ee SY Big 43 11 4 1 Interrupt Controller Registers 2 0 44 11 4 2 Interrupt Enable INT ENABLE 0 1 _ H LJP 44 11 4 3 Interrupt Origin INT_ORIGIN 0 1 00 0 45 11 4 4 Interrupt Vector INT VECTOR 0 45 11 4 5 Interrupt Enable Counter INT ENCOUNT 45 11 4
16. SPI O OxFC50 OxFC5F SPI 1 OxFC60 OxFC65 10base t ethernet controller OxFC66 OxFC6C DSP interface for peripheral data buffer OxFC70 OxFC76 Reed Solomon codes OxFC77 OxFC7A Nand flash interface OxFC7B OxFC7F SD card interface OxFC80 OxFC9F Hi Speed USB OxFCAO OxFCBF 16 bit GPIO port 0 OxFCCO OxFCDF 16 bit GPIO port 1 OxFCEO OxFCFF 14 bit GPIO port 2 OxFDOO OxFD1F S PDIF XTALI clocked peripherals OxFEOO OxFE1F UART OxFE20 OxFESF Watchdog OxFE40 OxFE5F FM and A D interface OxFE60 OxFE7F 12S OxFE80 OxFE9F Timers OxFEAO OxFEBF RTC interface OxFECO OxFEDF Control and configuration registers for 12 MHz clock Version 0 63 2014 12 19 42 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 4 Interrupt Controller VS1005g has 28 maskable interrupt vectors and 33 interrupt sources The interrupt controller is external to DSP and it prioritizes the requests before forwarding them to the DSP Interrupt controller has three levels of priority for simultaneous requests and a global dis able enable for all of the sources Interrupt sources are divided so that interrupt sources 15 0 are mapped to low registers and 27 16 to high registers For an interrupt handler written in C an assembly language stub that re enables interrupts be fore RETI should b
17. 5 1 Absolute Maximum Ratings 00000 eee ee 9 5 2 Recommended Operating Conditions 2 20 005 10 5 3 Analog Characteristics of Audio Outputs 2 0000 11 5 4 Analog Characteristics of Audio Inputs 00000 ee 12 5 5 SAR Characteristics Wa MR es 12 5 6 FM Characteristics SHB a ee ee ee 12 5 7 Analog Characteristics of Regulators 00002 eee 13 5 8 Analog Characteristics of VHIGH voltage monitor 14 5 9 Analog Characteristics of CVDD voltage monitor 14 5 10 Power Button Characteristics 0 00 eee ee 14 5 11 Digital Characteristics ooo a 14 5 12 Power Consumption oa aa a a 15 5 12 1 Digital Power Consumption a oaoa a 15 5 12 2 Analog Power Consumption aoso a 15 5 12 3 I O Power Consumption n sosa eoa a 16 5 12 4 Example Power Consumption soa oaoa a 16 Version 0 63 2014 12 19 2 ENO vst 005g Datasheet CONTENTS 6 Package and Pin Descriptions 17 6 1 LFGA 88 Package Current VS1005g from Datecode 1407 17 6 2 LFGA 88 Package Old VS1005g upto Datecode 1406 20 6 3 Pin Assignments 2 ee ee ee ee ee fe SF 23 6 4 VS1005g Pin Descriptions 2 2 ee a 24 6 4 1 PCB Layout Recommendations 22004 26 7 Example Schematic 27 8 VS1005g General Description 28 8 1 VS1005g Internal Architecture a 29 8 1 1 ReguiatorSection Si
18. DAC_VOL DAC volume control register DAC_VOL Bits Name Bits Description DAC_VOL_LADDJ3 0 15 12 Left channel 0 5dB steps DAC_VOL_LSFT 3 0 11 8 Left channel 6dB steps DAC VOL RADD 3 0 7 4 Right channel 0 5dB steps DAC_VOL_RSF1 3 0 3 0 Right channel 6dB steps DAC_VOL_LSFT and DAC_VOL_RSFT are the coarse volume control registers They suppress channel volume by 6dB steps DAC_VOL_LADD and DAC_VOL_RADD are the fine volume control registers They add chan nel volume level by 0 5dB steps Allowed values are from 0 to 11 i e maximum is 5 5d0B Values between 12 15 equal to OB Version 0 63 2014 12 19 55 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 7 3 Secondary Audio Path DAOSET Registers In VS1005g a secondary audio source can be mixed to the main audio path output This is done with DAC offset registers The sample rate is programmable DAC Offset Registers Reg Type Reset Abbrev Description OxFEC1 r w 0 DAOSET_CF DAC offset configuration register OxFEC2 r w 0 DAOSET_LEFT_LSB 15 12 DAC left offset bits 3 0 OxFEC3 r w 0 DAOSET_LEFT DAC left offset bits 19 4 OxFEC4 r w 0 DAOSET_RIGHT_LSB 15 12 DAC right offset bits 3 0 OxFEC5 r w 0 DAOSET_RIGHT DAC right offset bits 19 4 DAOSET_CF Bits Name Bits Description DAOSET_CF_URUN 14 Data register underrun flag DA
19. Firmware default setup after startup CLKI 60 000 MHz ID60MP3 24 4 mA Using PLL clock instead of RF clock CLKI 61 440 MHz 16 5 mA After powering down unused peripherals CLKI 61 440 MHz ID61MP3 13 4 mA Setting CLKI 36 684 MHz ID36MP3 12 0 mA Setting CLKI 24 576 MHz ID24MP3 11 1 mA Decode 96 kbit s 16 kHz stereo MP3 CLKI 12 288 MHz ID12MP3 7 4 mA Decode 56 kbit s 16 kHz mono MP3 CLKI 6 144MHz_ IDO6MP3 3 8 mA Check for Key push using GPIO CLKI 12 000 kHz ID12KHZ 0 1 mA 1 This clock is enough to decode all MP3 streams with some to spare The following table shows the digital power consumption when the processor is running but sitting idle gt 95 of the time Digital Current Consumption from CVDD Processor Idle Parameter Symbol Min Typ Max Unit CLKI 61 440 MHz ID61IDLE 7 1 mA CLKI 24 576 MHz ID24IDLE 4 6 mA CLKI 12 288 MHz ID12IDLE 3 0 mA CLKI 6 144 MHz IDO6IDLE 1 6 mA 5 12 2 Analog Power Consumption The following power consumptions are unless otherwise noted obtained with the following parameters decoding 128 kbit s 44 1 kHz stereo MP3 from RAM memory to analog output CVDD 1 67 V AVDD 2 75 V 3 60 V for V 1 2 V 1 6 V respectively IOVDD 3 3 V XTALI 12 288 MHz CLKI 24 576 MHz Typical Analog Current Consumption from AVDD Vref 1 2V Vref 1 6V 302 10k 302 10k Parameter
20. Real time clock power pin can be connected to CVDD net or it can have its own power supply which enables its use during chip power down The inputs and outputs of the RTC logic have level shifters but the RTCVDD voltage should not exceed the CVDD voltage range Clock The crystal amplifier uses a crystal connected to XTALI and XTALO An external logic level input clock can also be used When VS1005g is used with FS USB 12 MHz crystal allows lower power consumption With FS HS USB the input clock of 12 MHz or 12 288 MHZ is rec ommended An internal phase locked loop PLL generates the internal clock by multiplying the input clock by 1 0x 1 5x 8 0x When USB is connected the clock is 5 0x 12 MHz 60 MHz When the player is active the clock will be automatically changed according to the requirements of the song being played XRESET disables the clock buffer and puts the digital section into powerdown mode Version 0 63 2014 12 19 30 ENO vst 005g Datasheet 8 VS1005G GENERAL DESCRIPTION In usb suspend state the core clock is switced to RTC clock and the clock oscillator is powered down VSDSP VSDSP is VLSI Solution s proprietary digital signal processor with a 32 bit instruction word two 16 bit data buses and both 16 bit and 32 40 bit arithmetic IROM XROM and YROM contain the firmware including the default player application Most of the instruction RAM and some of the X and Y data RAM s can be used to custom
21. connected to the pwm pin PWM start up oscillator Item Min Typical Max Description Pull up resistor 100 kQ Value of external pull up resistor Start up frequency 370 kHz Start up oscillation frequency Version 0 63 2014 12 19 111 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 22 Special Features 11 22 1 Software Protection VS1005g hardware supports software protection Two registers control the hardware debug ging and serial flash access To use on circuit debugging it must first be enabled by a software register After power up the debugger is disabled The register can be set and reset by soft ware The access to serial flash can be disabled with a software register after boot up When serial flash is disabled it can not be enabled by software To re enable it requires system reset SYSRST Version 0 63 2014 12 19 112 ENO vst 005g Datasheet 12 VS1005G DEBUGGER 12 VS1005g Debugger VS1005g has a hardware debugger which uses common Joint Test Action Group JTAG inter face The JTAG pins are in hardware debug mode when the dbgmode pin is pulled high This enables the JTAG pins to access Test Acess Port TAP controller and swithes clocks to debug mode VS1005g Hardware Debuger Pins Name Package pin Description tms 31 Test mode select tdi 32 Test data in tdo 33 Test data out tck 34 Test clock dbgreq 35 Debug interrup
22. r w 0 SD_CF SD card configuration register OxFC7F r w 0 SD_ST SD card status register SD_PTR is the 11 bit memory pointer register SD_LEN defines the number of bytes that are read from or written to SD card The length is given in bytes SD_CF Bits Name Bits Description SD_CF_NOCRCTX 12 Do not send crc continued operation SD_CF_NOCRCRST 11 Do not reset crc register continued operation SD_CF_4BIT 10 Use 4 bit data bus mode SD_CF_ENA 7 Start SD card transfer SD_CF_READSEL 6 Read 1 or write 0 select SD_CF_CMDSEL 5 Command or data transfer select SD_CF_NOSTARTB 4 Skip data start bit continued operation SD_CF_NOSTOPB 3 Do not add data stop bit continued operation SD_CF_CRC16 2 Enable crc16 calculation during write SD_CF_CRC7 1 Enable crc7 calculation during write SD_CF_POLL O Poll for start bit when read SD_CF_NOCRCTX makes the interface to skip crc transfer SD_CF_NOCRCRST makes the interface to continues crc calculation from previous transfer SD_CF_4BIT forces the interface to use 4 bit data transfer instead of 1 bit if set SD_CF_ENA start SD card read or write transfer when set SD_CF_READSEL register selects a read transfer For code clarity SD_CF_WRITESEL has also been defined as zero SD_CF_CMDSEL register selects between command and data transfers For code clarity SD_CF_DATASEL has also been defined as zero S
23. 11 11 1 Ethernet Controller e 75 11 11 2 Reed Solomon Codec naoa 78 11 11 38 Nand Flash Interface 22200505 5 MMR eee 82 11 11 4 SD Card Interface 5 ge ss 84 11 12 USB Peripheral 2222052222 5 5 2 86 11 12 1 USB Peripheral Registers 2 2 02 00 87 11 12 2 USB Clocking Modes Sm WR se 90 11 12 3 USB Host 4 owadak ene 6 eee ie a RS OO PRS 90 11 13 Interruptable General Purpose IO Ports 0 2 20004 91 11 14 S PDIF Peripheral Mm Wm 2222 2 93 11 14 1 S PDIF Receiver gs Rm 7 ee ee es 93 11 14 2 S PDIF Receiver Registers 2 2 02 0000 94 11 14 3 S PDIF Transmitter Wy SHR ee ee eee 96 11 14 4 S PDIF Transmitter Registers 02 0000 97 11 15 UART Peripheral La anona a a ee 100 11 15 1 UART Peripheral Registers a a oaaae a 100 11 16 Watchdog Peripheral SAB a 102 11 16 1 Watchdog Registers 2 2 02 2 a 102 11 17 12S Peripheral Wm My eee 103 11 17 1 12S Peripheral Registers 2 02 2 2 0000 103 11 18 Timer Peripheral A aaa a 105 11 18 1 Timer Peripheral Registers 2022 0 005 105 11 19 Real Time Clock MC 107 11 19 1 RTC Peripheral Registers noaoae 107 11 20 10 Bit Successive Approximation Register Analog to Digital Converter SAR 109 11 21 Pulse Width Modulation Unit a aoa oaoa 11
24. 12S Peripheral VS1005g has a bi directional 12S digital interface 12S is a serial audio interface which uses serial bit clock i2s_bck frame sync i2s_frm and serial data line i2s_dout i2s_din to transfer data 12S frame consists of left and right data which is transmitted left word first and MSB bit first Data is latched out at falling edge of bit clock and latched in at rising edge of bit clock 12S data format is shown in Figure 27 i2s bck ae ir i2s frm i2s dout __ tsByMsBy LSB MSBY WORD n 1 WORD n WORD n RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL Figure 27 12S frame format 11 17 1 12S Peripheral Registers 12S Registers Reg Type Reset Abbrev Description OxFE60 r w 0 1l2S_CF 13 0 Configuration and status register OxFE61 r w O l2S_LEFT_LSB Left data bits 15 0 OxFE62 r w 0 12S_LEFT Left data bits 31 16 OxFE63 r w O 12S _RIGHT_LSB Right data bits 15 0 OxFE64 r w 0 12S_RIGHT Right data bits 31 16 I2S_CF Bits Name Bits Description I2S_CF_32B 13 32 bit mode 1 16 bit mode 0 select I2S_CF_INTENA 12 12S peripheral interrupt enable I2S_CF_RXRFULL 11 Receiver right data register full 12S CF _RXLFULL 10 Receiver left data register full 1l2S_CF_RXORUN 9 Receiver over run flag I2S_CF_TXRFULL 8 Transmitter right data register full 12S
25. 5 6448 MHz 48 kHz 3 072 MHz 6 144 MHz 96 kHz 6 144 MHz 12 288 MHz 192 kHz 12 288 MHz 24 576 MHz Divider Master clock Targer frequency Divider Master clock Fs 64 2 SP_TX_CF_IE when 1 enables processor interrupt request when new values must be written for the sample word registers SP_LDATA and SP_RDATA Default is 0 SP_TX_CF_SND when 1 S PDIF Transmitter sends the data in the sample word registers Otherwise only empty subframes with zero payload will be sent This is because the receiver may use S PDIF signal as a clock source and hence the S PDIF signal must not stop even though no data is sent The S PDIF Transmitter has one interrupt Interrupt request is issued when SP_ST_NWRQ is set i e when new sample words must be written to the sample word registers Version 0 63 2014 12 19 99 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 15 UART Peripheral RS232 UART implements a serial interface using rs232 standard Start bit DO bt D2 o3 D4 os pe D7 ptr Figure 26 RS232 serial interface protocol When the line is idling it stays in logic high state When a byte is transmitted the transmission begins with a start bit logic zero and continues with data bits LSB first and ends up with a stop bit logic high 10 bits are sent for each 8 bit byte frame 11 15 1 UART Peripheral Registers UA
26. 75ys North America or 50s Europe Australia de emphasis filters When set the de emphasis is 75s FM_CF_RDSENA register enables the rds calculation logic when set FM_CF_CCFLCK register enables automatic FM fine tuning when set When reset the FM band frequency is always at fixed value as defined in FMCCF register FM_CF_FM_ENA is the FM demodulator enable The register must be set when FM is used To receive in stereo mode the FM_PLL registers must be initialized correctly These regis ters FMPLL_HI and FMPLL_LO set the FM stereo carrier PLL frequency This factor is xtal dependent and is defined as _ 64x 278 x 38000Hz pll_factor TarfreqHz PLL value examples for most typical xtals XTALI frequency FMPLL register 12 0 MHz 54402918 0x033E 1F66 12 288 MHz 53127850 0x032A AAAA 13 0 MHz 50218079 0x02FE 445F FMCCF_HI and FMCCF_LO are used to set FM tuning frequency FM Carrier Center Fre quency These registers hold a 27 bit signed value which controls the frequency inside the selected VCO center frequency range This VCO center frequency is set with divider registers ANA_CF3_DIV 1 0 and ANA_CF3_FMDIV 1 0 VCO Divider Register ANA_CF3_DIV 1 0 VCO Divider 00 36 01 10 30 11 25 FM divider ANA_CF3_FMDIV 1 0 FM divider 00 16 10 20 11 01 24
27. Device Which device is activated depends on the state of GPIOO_6 when the USB connection is detected If GPIOO_6 has a pull up resistor VS1005g appears as an USB Audio Device If GPIOO_6 has a pull down resistor VS1005g appears as an USB Mass Storage Device 8 2 Analog Section The third regulator provides power for the analog section The analog section consists of digital to analog converters an earphone driver and FM receiver This includes a buffered common voltage generator CBUF around 1 2 V that can be used as a virtual ground for headphones The regulator AVDD output pin must be connected to AVDD1 and AVDD2 pins with proper bypass capacitors because they are not connected internally The AVDDRF pin is connected to regulator CVDD pin with proper bypass capacitors or with external regulator from VHIGH The USB pins use the internal AVDD voltage and the firmware configures AVDD to 3 6 V when USB is attached AVDD voltage level can be monitored by software Currently the firmware does not take advan tage of this feature CBUF contains a short circuit protection It disconnects the CBUF driver if pin is shorted to ground In practise this only happens with external power regulation because there is a limit to how much power the internal regulators can provide Version 0 63 2014 12 19 32 GAN LSI VS1 005g Datasheet OSCILLATOR AND RESET CONFIGURATION 9 Oscillator and Reset Configuration The reset module gathers reset so
28. FM tuning frequency multiplied by 16 20 or 24 FM Divider Bits FMDIV 1 FMDIV 0 Divider Description 1 1 24 FM frequency is VCO frequency divided by 24 1 0 20 FM frequency is VCO frequency divided by 20 0 1 24 Don t Use reserved 0 0 16 FM frequency is VCO frequency divided by 16 ANA_CF3_2GCNTR register is used to match VCO s center frequency to programmed value CCF ANA_CF3_DIV 1 0 controls the VCO s dividers These dividers are used to set VCO s output frequency range ANA_CF3_480ENA is the 480 MHz clock driver enable for UTM When set the clock driver is enabled ANA_CF3_GAIN1 and ANA_CF3_GAIN2 set the ADC 1 and 2 gains ADC gain can be ad justed to four values ADC Gain Register value Gain 001 20dB max 010 17dB 100 14dB 000 11 dB min default after reset Version 0 63 2014 12 19 51 NLS VS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 6 2 Regulator and Peripheral Clock Control Registers VS1005g has four internal regulators one regulator for each power domain The voltage can be adjusted in about 50mV step size To save power some of the peripheral clocks can be switched off Regulator and Clock Control Reg Type Reset Abbrev Description OxFECE r w 0 REGU_CF Regulator control register OxFEDO r w 0 REGU_VOLT Regulator voltage register REG
29. I02VDD IOVDD XRESET NFDIOO NFDIO1 NFDIO2 NFDIO3 NFDIO4 NFDIO5 NFDIO6 NFDIO7 NFRDY NFRD XCS1 SCLK1 CVDD1 MISO1 e 1 2 3 4 5 6 7 8 9 GPIOO_0 GPIOO_1 GPIOO_2 GPIOO 3 GPIOO 4 GPIOO_5 GPIOO 6 GPIOO_7 GPIOO 8 GPIOO_9 GPIO1 4 GPIO1_5 m e e GPIO1_6 84l AVDD1 LEFT GPIO1_2 ata 397 ag 68 885 ae EAM oS BUG as a ce SI A AaHo m DESEE 3292 0 Figure 12 Version 0 63 2014 12 19 CBUF NC MISOO MOSIO GPIO1 3 VS1005g Datasheet 6 PACKAGE AND PIN DESCRIPTIONS S o o inal Z Z any aa S S ae m ao SZAN Soe242Z yw St SHG gt S Den Ss EA A AZAZ A A N ERRER E kx Pantene easssSSuz on 4 NNa ono or nnRoRR RO Oo C Stereo line in C Alternate stereo line in Alternate stereo line in VS1005 LFGA 88 Digital AD2 input Digital AD1 input External AD DA clk Digital AD3 input a a8 Ss 8 68 9 oo ZS ER 55 A A no om A N x a lt gt a we s 44 N 299909 885555 ALAARA Manana Jaooo GORRRA of wsa ZA BEBER enoxo Roads gt lt PEFERSREASSAAN S AUX0 LINE2 2 67 L I2S_12M GPIO1_ 14 XTALL RTC XTALO_RTC RTCVDD PWRBIN TEST DBG CVDD3 US_OUT GPIO0_15 US_IN GPIO0_14 SPDIF_OUT GPIOO 13 SPDIF IN GPIOO 12 ETH TXN GPIO2_13 DIA2 IOVDD3 ETH TXP GPIO2_12 DIA1 N A GPIO1_15 ETH_RXP GPIO2_11 DIA3 SD_CMD GPIO2_10 SD_DAT3 GPIO2_9 SD_DAT2 GPIO2_8 SD_DAT1 G
30. INT_ORIGINO or INT_ORIGIN1 will be set to 1 If an interrupt source is enabled using INT_ENABLE 0 1 _ H L P registers the interrupt controller generates an interrupt request sig nal for VSDSP with the corresponding vector value The bit in the origin registers is reset automatically after the interrupt is requested If the source is not enabled the processor can read the origin register state and perform any necessary actions without using interrupt generation i e polling of the interrupt sources is also possible The bits in the interrupt origin registers can be cleared by writing 1 to them A read from the interrupt origin register returns the register state A write to the interrupt origin register clears the bits in the origin register that are set by the write In other words writing b to INT_ORIGINx performs the logical operation INT_ORIGINx INT_ORIGINx and not b Example If value for INT_ORIGINO is OxOOFF writing OxFOOF to it will end up with INT_ORIGINO OxOOFF and not OxFOOF OxOOFF and OxOFFO OxOOFO 11 4 4 Interrupt Vector INT_VECTOR The last generated vector value 0 27 can be read from the vector register 11 4 5 Interrupt Enable Counter INT_ENCOUNT The global interrupt enable disable register INT _ENCOUNT is used to control whether an in terrupt request is sent to the processor or not If the 3 bit counter is zero interrupt signal generation is enabled While it is non zero interrupt requests
31. SP EEPROM boot is skipped Boot records are read from EEPROM until an execute record is reached Unknown records are skipped using the data length field Byte Description 0 type 0 l mem 1 X mem 2 Y mem 3 execute 1 2 data len lo hi data length in bytes 3 4 address lo hi record address 5 data 10 2 NAND FLASH Probe If NAND FLASH chip select NFCE is high a NAND FLASH is assumed to be present and the first sector is read The access methods nandTypes 0 5 are tried in order to find the VLN5 identification If the first bytes are VLN5 a valid boot sector is assumed This sector gives the necessary information about the NAND FLASH so that it can be accessed in the right way NandFlash Header Byte Value Description 0 1 2 3 0x56 0x4c 0x4E 0x35 V L N 5 Identification 4 5 0x00 0x03 NandType 0x0003 large page with 3 byte block address See table 6 0x08 BlockSizeBits 2 x 512 128 KiB per block 7 0x13 FlashSizeBits 21 x 512 256 MIB flash 8 9 0x00 0x46 NandWaitNs NAND FLASH access time in ns e g 0x46 10 11 0x00 0x01 Number of 512 byte blocks for boot e g 0x0001 12 13 0x00 0x00 EWRD How many words to skip before B o O t string 14 14 EWRD 1 Extra words this field exists only if EWRD 0 14 15 16 17 EWRD 0x42 Ox6f Ox4f 0x74 B
32. Symbol Typ Typ Typ Typ Unit Full scale 1 kHz sine wave full volume IAFSxxVyy 42 0 5 4 57 4 8 7 mA Loud music full volume IAODBxxVyy 11 2 5 3 15 6 8 1 mA Loud music 20 dB volume IA20DBxxVyy 5 6 5 3 8 3 8 0 mA Silence IASILxxVyy 5 4 5 3 8 1 8 0 mA Mute analog drivers off IAMxxVyy 1 8 1 81 25 2 5 mA 1 Output signal approximately 660 mVrms for V s 1 2 V and 900 mVrms for V 1 6 V 2 Replace xx with 12 for Vref 1 2 V and 16 for V e 1 6 V Replace yy with 30 for 30 Q load and with HI for 10 kQ load Version 0 63 2014 12 19 15 NLS 5 12 3 I O Power Consumption VS1005g Datasheet 5 CHARACTERISTICS amp SPECIFICATIONS The following power consumptions are unless otherwise noted obtained with the following parameters decoding 128kbit s 44 1 kHz stereo MP3 from RAM memory to analog output CVDD 1 67 V AVDD 3 6 V XTALI 12 288 MHz no specific I O activity Digital Current Consumption from CVDD MP3 decode Parameter Symbol Min Typ Max Unit IOVDD 3 6 V IIO36 1 51 mA IOVDD 3 3 V O33 1 20 mA IOVDD 2 7V O27 0 85 mA lIOVDD 1 8V O18 0 46 mA 5 12 4 Example Power Consumption Let s assume a system with an earphone output and audio playback capability Lets fur ther assume that the system could be run at CVDD 1 67V AVDD 2 70V V f 1 2V IOVDD 3 3 V The VS1005g typical power consumption decoding a 128
33. _ CF_TXLFULL 7 Transmitter left data register full 12S _CF_TXURUN 6 Transmitter under run flag I2S_CF_MODE 5 12S output mode DSP 1 or SRC 0 out 12S CF_FS 1 0 4 3 12S sample rate selection I2S CF_ENA 2 12S peripheral enable 12S _CF_ENAMCK 1 12S master clock 12 MHz pad driver enable I2S_CF_MASTER 0 12S master 1 slave 0 mode select Value can only be changed if 12S_CF_ENA has previously been cleared to 0 Version 0 63 2014 12 19 103 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS I2S_CF_MASTER bit is used to select between master 1 and slave 0 modes In master mode the VS1005g generates bit clock and frame sync signals In slave mode the external 12S master generates the clock and sync signals I2S_CF_ENAMCK is the 12MHz output clock enable signal It can be used to clock external I2S circuitry This clock is the same clock as the XTALI oscillator clock of VS1005g I2S_CF_ENA is the transmitter and receiver enable signal When set the receiver and trans mitter enter the active state Other fields of the same register I2S_CF_32B l2S_CF_INTENA I2S_CF_MODE I2S_CF_FS l2S_CF_ENAMCK and l2S_CF_MASTER can only be changed if 12S CF_ENA is 0 I2S_CF_FS register is used to set the 12S peripheral sample rate This register can be modified only when 12S is in idle state i e 12S CF_ENA is reset Next table lists the sample rates when XTALI 12 288 MHz is used 12S Sampl
34. abled When transmitter is enabled this register is decremented after a byte has been sent When the length register reached zero the transmitter returns to idle state In SPI slave mode this register is zero ETH_TXPTR Bits Name Bits Description ETH _TXPTR_SPI_TX_ENA 15 SPI slave transmitter enable ETH_TXPTR_SPI_RX_ENA 14 SPI slave receiver enable ETH_TXPTR_BUSY 13 Ethernet transmitter busy ETH_TXPTR_START 12 Ethernet transmitter start to send packet ETH_TXPTR_PTR 10 0 10 0 Ethernet transmitter memory address pointer ETH_TXPTR_SPI_TX_ENA and ETH_TXPTR_SPI_RX_ENA are the SPI slave mode enables for transmitter and receiver SPI start and stop interrupts are generated even though these reg Version 0 63 2014 12 19 Ethernet Controller Registers Reg Type Reset Abbrev Description OxFC60 r w 0 ETH_TXLEN Ethernet transmitter packet length OxFC61 r w 0 ETH_TXPTR Ethernet transmitter memory address pointer OxFC62 r w 0 ETH_RXLEN Ethernet receiver packet length OxFC63 r w 0 ETH_RXPTR Ethernet receiver memory address pointer OxFC64 r w 0 ETH_RBUF Ethernet transmitter receiver ring buffer configuration OxFC65 r 0 ETH_RXADDR Ethernet receiver memory address 11 bits ETH_TXLEN Bits Name Bits Description ETH_TXLEN META 15 SPI slave synhronization configuration ETH_TXLEN_RX_BE 14 Set big endian SPI slave receiver bit order ETH_TXLEN_TX_BE 13 Set big endian SPI slave
35. are not forwarded to VSDSP The counter is increased by one whenever the interrupt controller generates an interrupt request for VSDSP or when the register INT_GLOB_DIS is written to It is decresed by one if it is non zero and the register INT _GLOB_ENA is written to When read the enable counter register returns the counter value Don t write directly to INT_ENCOUNT Manipulate its value by writing to INT_GLOB_DIS and INT_GLOB_ENA instead 11 4 6 Interrupt Global Disable INT_GLOB_DIS A write of any value to the global disable register increases the global interrupt enable disable counter INT_ENCOUNT by one thus disabling interrupts Note If an interrupt is generated during the same clock cycle as a write to the global disable register the interrupt enable counter is increased by two Version 0 63 2014 12 19 45 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 4 7 Interrupt Global Enable INT_GLOB_ENA If the global interrupt enable disable counter INT_ENCOUNT is not zero a write of any value to INT_GLOB_ENA the counter by one The user must write to this register once at the end of interrupt handlers to re enable interrupts Version 0 63 2014 12 19 46 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 5 DSP Clock Domain Registers 11 5 1 General Purpose Software Registers SW_REGO SW_REG1 SW_REG2 and SW_REG are software registers for user purposes They are zeroed in reset and
36. convey the same bits Again for full description of channel status bits refer to IEC 60958 3 SP_RX_BLFRCNT Bits Name Bits Type Description SP_RX_BLCNT 15 8 r Frame block count SP_RX_FRCNT 7 0 r Frame count SP_RX_BLCNT is a freame block counter This counter increment each time a new frame is received Itis zeroed after the 191th frame is received SP_RX_FRCNT is zeroed with every Z preamble and incremented with every X preamble S PDIF Receiver uses two interrupts a frame received interrupt and a channel status chance interrupt Device issues an interrupt when it has received a frame The interrupt is cleared when SP_RX_LDATA is read Channel status change interrupt is set when at least one of the following conditions is satisfied e Channel status bit 0 selection between professional and consumer mode is changed e Channel status bit 1 which indicates whether the sample word is linear PCM or not is changed e Validity bit for either channel left or right is changed This interrupt is enabled by setting SP_RX_CF_INT_ENA bit 11 14 3 S PDIF Transmitter S PDIF is a serial digital audio transfer standard Sampling frequencies up to 192 kHz and sample word width of 16 24 bits are supported for two channels S PDIF transmitter peripheral has a processor interface and one external output signal for digital audio S PDIF is described in IEC 60958 1 and IEC 60958 3 Standard connectors are
37. decoder syndrome index 10 bits 0000 R S encoder parity word as selected with RS_CF 7 4 16 bits Version 0 63 2014 12 19 81 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 11 3 Nand Flash Interface Nand Flash Controller Registers Reg Type Reset Abbrev Description OxFC77 r w 0 NF_CF Nand flash configuration register OxFC78 r w 0 NF_CTRL Nand flash control register OxFC79 r w 0 NF_PTR_ Nand flash memory pointer OxFC7A r w 0 NF_LEN Nand flash data length register bytes NF_CF Bits Name Bits Description NF_CF_SCLK_INV 9 Slave mode clock active edge select NF_CF_SLAVE 8 Slave mode enable NF_CF_FLT_BUS 7 Nand flash output bus float enable NF_CF_INT_ENA 6 Nand flash interface interrupt enable NF_CF_WAITSTATES 5 0 Nand flash interface clock configuration NF_CF_SCLK_INV selects slave mode active clock edge If set the data bus is read at rising edge of ready busy line when reset at falling edge NF_CF_SLAVE configures the nand flash interface to slave input mode In slave mode the nand flash interface reads data from 8 bit bus and stores it to memory The clock is the ready bysy input NF_CF_FLT_BUS leaves the data output bus flash input bus floating when set When reset the bus is driven to low or high state NF_CF_INT_ENA enables the nand flash interrupt re
38. external 1 MQ pull up 1 Smaller pull down resistors may be needed for keys if the capacitance on the GPIO pins is high Boot order Stage Description Power on Power button PWRBTN pressed when VHIGH has enough volt age Reset Power on reset XRESET or watchdog reset causes software restart UART Boot Almost immediately after power on UART can be used to enter emulator mode UART boot remains possible after the following steps too SPI EEPROM boot If XCS is high SPI Boot is tried NAND FLASH probed If NFCE is high NAND FLASH is checked SD boot If VS1005G SYS exists it is used as a boot file Default firmware The firmware in ROM takes control 10 1 SPI Boot The first boot method is SPI EEPROM If GPIO1_0 is low after reset SPI boot is skipped If GPIO1_0 is high it is assumed to have a pull up resistor and SPI boot is tried First the first four bytes of the SP EEPROM are read using 16 bit address If the bytes are VLS5 for protected host or WLS5 for unprotected host a 16 bit EEPROM is assumed and the boot continues If the last 3 bytes are read as VLS a 24 bit EEPROM is assumed and boot continues in 24 bit mode Both 16 bit and 24 bit EEPROM should have the VLS5 or WLS5 string starting at address 0 and the rest of the boot data starting at address 4 If no Version 0 63 2014 12 19 34 NLS VS1005g Datasheet 10 FIRMWARE OPERATION identifier is found
39. from Datecode 1407 and Chap ter 6 2 LFGA 88 Package Old VS1005g upto Datecode 1406 For the same reason Figures 9 10 and 11 have been updated Version 0 61 2014 10 30 e Added a new Chapter 6 1 LFGA 88 Package Current VS1005g from Datecode 1407 Renamed Chapter 6 2 LFGA 88 Package Old VS1005g upto Datecode 1406 Updated first and last page VS1005 images to current LFGA 88 package e Updated memory map in Chapter 11 2 VS1005g Memory Map and added reference to VSOS e Corrected XP_IDATA XP_ODATA mix up in explanation for bits XP_CF_WRBUF_ENA and XP_XF_RDBUF_ENA in Chapter 11 11 Common Data Interfaces e Registers PWM_FRAME and PWM_PULSE were switched in Chapter 11 21 Pulse Width Modulation Unit They have been replaced with PCM_PULSE_LEN and PWM_FRAME_LEN respectively Version 0 60 2014 07 23 e Added new Chapter 5 12 Power Consumption e Switched ANA_CFO_xxx values between LINE2_1 and LINE3 1 and between LINE2 2 and LINE3_2 in Chapter 11 8 1 Configuring Signal Paths for ADC 1 ADC2 and ADC3 Version 0 53 2013 10 04 Updated first and last page VS1005 images from VS1005f to VS1005g Added Figure 8 VS1005g LFGA 88 top and bottom view photo Slightly changed the way frequency formula for DAC_SRC Chapter 11 7 1 Primary Audio Path 24 bit Sample Rate Upconverter with Filters DAC Registers is written e Added some symbolic names for Ethernet configuration bits in Chapter 11 11 1 Ethernet Controller Clarif
40. kbit s MP3 stream to 30 2 earphones would be approximately lot IDSEMP3 IAZ0DB12V30 11033 12 0 mA 5 6 mA 1 20 mA 18 8 mA This figure needs to be rounded slightly up because the digital current figures don t include reading the file from external memory or a user interface Note that the figures assume that all VS1005g peripherals that are not being used have been powered down or their clock gates have been closed see registers CLK_CF and REGU_CF Note also that the external memory used for playback e g an SD card can often consume significant amounts of current Version 0 63 2014 12 19 16 ENO vst 005g Datasheet 6 PACKAGE AND PIN DESCRIPTIONS 6 Package and Pin Descriptions 6 1 LFGA 88 Package Current VS1005g from Datecode 1407 LFGA 88 is a 10x10x0 8mm lead Pb free and RoHS compliant package RoHS is a short name of Directive 2002 95 EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment Package and pin dimensions are shown in Figures 4 5 6 and 7 For more information about the LFGA 88 package and its dimensions visit http www visi fi en support download htm Note that in this package pins extend to the sides of the IC see Figures 1 2 3 5 6 and 7 This revision of the package has been used in all VS1005gs from and including datecode 1407 It is recommended to use this package revision as the basis for VS1005g PCB designs even if us
41. should be reset The SD_ST_WS and SD_CF_4BIT have their usual meaning SD_ST_CMDBRkK is set if a cmd start bit is found during data transfer This register is reset at the start of each SD card op SD_ST_DATO register samples the SD cards data 0 line SD_ST_NOSTOPB_ERR is set if stop bit was not found when reading data from SD card SD_ST_CRC16_ERR is set if crc16 error was detected when reading data from SD card SD_ST_CRC7_ERR is set if command response had a crc7 error SD_ST_NOSTARTB_ERR is set if start bit was not found during 256 SD clocks For code clarity also SD_ST_ANY_ERR has been defined as SD_ST_NOSTOPB_ERR SD_ST_CRC16_ERR SD_ST_CRC7_ERR SD_ST_NOSTARTB_ERR Version 0 63 2014 12 19 85 ENO vst 005g Datasheet 11 12 USB Peripheral 11 VS1005G PERIPHERALS AND REGISTERS VS1005g has a Full Speed Hi Speed Universal Serial Bus The Universal Serial Bus Controller handles USB 2 0 data traffic at 12 Mbit s signalling speed and high speed USB data at 480 Mbit s The devices support a maximum of four endpoints The USB implementation is based on transceiver macromodel interface UTMI Block diagram of usb modules is shown in Figure 22 Simplified UTM module diagram is shown in Figure 23 VS_DSP USB Peripheral Logic Serial Interface Engine USB 2 0 USB 2 0 lt a Transceiver Macromodel SIE Control Logic VCO 480MHz Figure 22 VS1005g USB block diagram The USB device can handle traffic
42. transmitter bit order ETH_TXLEN_LEN 11 0 11 0 Ethernet transmitter packet size in bytes 75 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS isters would be reset It should be noted that when ETH_TXPTR_SPIRE is set the transmitter address pointer must be initialized to data start address In ethernet mode these registers are don t care ETH_TXPTR_BUSY is the ethernet transmitter busy flag In SPI slave mode this flag is set if transmitter is enabled and chip select line is in its active state low ETH_TXPTR_START enables the ethernet transmitter When this register is set the transmitter changes from idle to busy state and sends ETH_TXLEN 11 0 number of bytes Before this register is set the packet data must be stored in peripheral memory and tx address pointer and tx packet length registers must be configured In SPI slave mode this register is zero ETH_TXPTR 10 0 is the ethernet SPI transmitter memory address pointer This pointer is loaded with packet start address before transmitter is enabled ETH_RXLEN Bits Name Bits Description ETH _RXLEN_SPIMODE 15 Peripheral mode select Ethernet 0 SPI slave mode 1 ETH _RXLEN_SPIINVCLK 14 SPI slave transmitter clock configuration ETH _RXLEN_LEN 11 0 11 0 Ethernet receiver packet size in bytes ETH_RXLEN_SPIMODE register configures the peripheral to ethernet mode or to SPI slave mode When register is reset default
43. v t t 44100 v v v v v v 32000 v V V V V lt MPEG 2 0 amp 2 5 layer III MP3 low rates stereo Samplerate Hz Bitrate kbit s stereo 8 16 24 32 40 48 56 64 80 96 112 128 144 160 24000 x V V V V V V lt 22050 x v v jv Iiv jv f lt lt 16000 x iv jv v t f lt lt 12000 v vV vV Z x 11025 v v v lt lt 8000 lt lt lt MPEG 1 0 layer III MP3 full rates mono Samplerate Hz Bitrate kbit s mono 32 40 48 56 64 80 96 112 128 160 192 224 256 320 48000 v v v tt t te f t t lt 44100 v V V 32000 J f lt lt lt A MPEG 2 0 amp 2 5 layer III MP3 low rates mono Samplerate Hz Bitrate kbit s mono 8 16 24 32 40 48 56 64 80 96 112 128 144 160 24000 v V lt lt lt 22050 v V lt lt lt 16000 v V lt lt lt p lt lt P lt 12000 v V lt lt lt lt T 11025 v V
44. when xcs is asserted and data is sampled at first clock edge rise edge when SPI_CC_INV_CLKPOL 0 and fall edge if SPI_CC_INV_CLKPOL 1 If SPl_CC_INV_CLKPHASE is set the first data is written a the first data clock edge and sampled at second Version 0 63 2014 12 19 69 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS Status SPlx_STATUS Bits Name Bits Description SPI ST_RXFIFOFULL Receiver FIFO register full SPL ST_TXFIFOFULL Transmitter FIFO register full SPI_ST_BREAK Chip select deasserted mid transfer SPILST_RXORUN Receiver overrun SPI ST_RXFULL Receiver data register full SPI_ST_TXFULL Transmitter data register full SPL ST_TXRUNNING Transmitter running SPIST_TXURUN Transmitter underrun NI O BY OIO N SPI_ST_BREAK is set in slave mode if chip select was deasserted in interrupted xCS mode or a starting edge is encountered in xCS edge modes while a data transfer was in progress This bit has to be cleared manually SPI_ST_RXORUN is set if a received byte overwrites unread data when it is transferred from the receiver shift register to the data register This bit has to be cleared manually SPI_ST_RXFULL is set if there is unread data in the data register SPI_ST_TXFULL is set if the transmit data register is full SPI_ST_TXRUNNING is set if the transmitter shift register is in operation SPI_ST_TXURUN is set if an external data transfer has been initia
45. 00 OxFD3F and peripherals that use XTALI clock are in addresses OxFEOO OxFEDF Peripheral address spaces are summarized in the following table VS1005g peripheral address ranges Address Device PLL clocked peripherals OxFCOO OxFC1F Interrupt controller OxFC20 OxFC3F DSP interface registers OxFC40 OxFC4F SPI O OxFC50 OxFC5F SPI 1 OxFC60 OxFC65 10base t ethernet controller OxFC66 OxFC6C DSP interface for peripheral data buffer OxFC70 OxFC76 Reed Solomon codes OxFC77 OxFC7A Nand flash interface OxFC7B OxFC7F SD card interface OxFC80 OxFC9F Hi Speed USB OxFCAO OxFCBF 16 bit GPIO port 0 OxFCCO OxFCDF 16 bit GPIO port 1 OxFCEO OxFCFF 14 bit GPIO port 2 OxFDOO OxFD1F S PDIF XTALI clocked peripherals OxFEOO OxFE1F UART OxFE20 OxFESF Watchdog OxFE40 OxFE5F FM and A D interface OxFE60 OxFE7F 12S OxFE80 OxFE9F Timers OxFEAO OxFEBF RTC interface OxFECO OxFEDF Control and configuration registers for 12 MHz clock Version 0 63 2014 12 19 41 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS VS1005g Peripheral Addresses Address Device PLL clocked peripherals OxFCOO OxFC1F Interrupt controller OxFC20 OxFC3F DSP interface registers OxFC40 OxFC4F
46. 1 11 22 Special Features 2 ee ee 112 11 22 1 Software Protection o oo e a a e a 112 Version 0 63 2014 12 19 5 ENO vst 005g Datasheet CONTENTS 12 VS1005g Debugger 113 13 Document Version Changes 116 14 Contact Information 118 Version 0 63 2014 12 19 6 ENS vst 005g Datasheet LIST OF FIGURES List of Figures 1 VS1005g LFGA 88 VS1205G F product variant top and bottom view photo 17 2 VS1005g LFGA 88 VS1205G F product variant side view photo 17 3 VS1005g LFGA 88 VS1205G F product variant bottom corner view photo 17 4 VS1005g top view LFGA 88 naaa eee ee ee 18 5 VS1005g corner view LFGA 88 aoaaa Se ss 18 6 VS1005g bottom view LFGA 88 aoaaa 0 0000 ee 19 7 VS1005g side view LFGA 88 aaao a 19 8 VS1005g old LFGA 88 VS1205G F product variant top and bottom view photo 20 9 VS1005g top view old LFGA 88 4 2 ee 21 10 VS1005g bottom view old LFGA 88 0 000005 ee eee 22 11 VS1005g side view old LFGA 88 2 00000 eee eee 22 12 VS1005g 88 pin LFGA pinassignment 0 0 0000022 e 23 13 VS1005g default pin usage Ny Wm 2 ee 27 14 VS1005g external interfaces 2 2 0 ee 28 15 VS1005g block diagram WB MM ee 29 16 VS10059 s memory mapa WER ee 40 17 VS1005g playback DA audio paths 0 2 ee 53 18 VS1005g recording AD and FM signalpaths 58 19 Block diagram of FM receiver RF
47. 12 3 word 2 15 8 amp word 1 7 6 4 word 3 9 8 amp word 2 7 0 5 word 3 3 0 amp word 3 15 10 6 word 4 13 8 amp word 3 7 4 7 word 4 7 0 amp word 4 15 14 RF Reed Solomon encoder outputs the 8 bit check symbols as 16 16 bit words Here the 32 8 bit symbols are organized in big endian format This codec provides a means to detect 32 symbo errors and to fix 16 symbols The NF Reed Solomon decoder makes it possible to detect 8 symbol errors and to fix a maxi mum of 4 symbols The decoder first reads the data symbols and then the parity check words Version 0 63 2014 12 19 78 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS As the check symbols are 10 bits they must be organized into memory in this format before check symbol decoding is started The encoder expects them to be in LSB bits 9 0 in con secutive memory locations The decoder returns the number of total errors and the number of errors in data symbols Only the data symbol errors are returned as location magnitude pairs when Reed Solomon decoder has finished the calculation These errors must be fixed by software to the code word by XORing magnitude to the error location data The location magnitude pairs are stored in memory Reed Solomon codecs use a shared interrupt source INT_XPERIP The source of interrupt is stored in register XP_ST where the decoder has one bit for Reed Solomon encoder and two bits for Reed S
48. 12S RIGHT and I2S_RIGHT_LSB are the left and right data reg isters for receiver and transmitter Each write to 12S LEFT and I2S_RIGHT registers sets the I2S_CF_TXLFULL and l2S_CF_TXRFULL flags Each read from l2S_ LEFT and l2S_ RIGHT registers resets the 12S CF_RXLFULL and Il2S_CF_RXRFULL flags In 16 bit mode the reg isters 12S LEFT LSB and I2S_RIGHT_LSB are not used In 32 bit mode they are used to transfer 16 LSBs of data Version 0 63 2014 12 19 104 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 18 Timer Peripheral VS1005g has three 32 bit timers that can be initialized and enabled independently of each other If enabled a timer initializes to its user initialized start value and starts decrementing every clock cycle When the value goes past zero an interrupt request is generated and the timer initializes to the value in its start value register and continues downcounting A timer stays in that loop as long as it is enabled Each timer has its own interrupt request A timer has a 32 bit timer register for down counting and a 32 bit TIMER1_LH register for holding the timer start value written by the processor Timers have also a 3 bit TIMER_ENA register Each timer is enabled 1 or disabled 0 by a corresponding bit of the enable register 11 18 1 Timer Peripheral Registers Timer Registers Reg Type Reset Abbrev Descripti
49. 6 Interrupt Global Disable INT GLOB DIS 45 11 4 7 Interrupt Global Enable INT GLOB_ENA 46 11 5 DSP Clock Domain Registers 00 0002 e ee eee eee 47 11 5 1 General Purpose Software Registers 0 47 11 5 2 Peripheral I O Control Mm 2 7 es 47 11 5 3 PLL Clock Control w a NR ww es 47 11 6 XTALI Clock Domain Registers aooaa a 49 11 6 1 Analog Control Registers Wh ee 49 11 6 2 Regulator and Peripheral Clock Control Registers 52 11 7 Audio Playback Interfaces 2 2 2 ee 53 11 7 1 Primary Audio Path 24 bit Sample Rate Upconverter with Filters DAC Registers oaoa aaa ee eee ee 54 11 7 2 Primary Audio Path Volume Control 55 11 7 3 Secondary Audio Path DAOSET Registers 56 11 7 4 Filterless Sample Rate Converter SRC Registers 57 11 8 24 bit Analog to Digital Converters ADC naaa aa 58 11 8 1 Configuring Signal Paths for ADC1 ADC2 andADC3 59 11 8 2 Digital Filter Operation Modes 00 61 11 9 FM Receiver we 63 11 9 1 Configuring RF and Analog Modules for FM Receiver Mode 63 11 9 2 Configuring the FM Demodulator noaoae 64 11 9 3 Radio Data System RDS anaa 66 Version 0 63 2014 12 19 4 ENS vst 005g Datasheet CONTENTS 11 10 SPI Peripherals 0 2 2 2 cee ee AE 68 11 11 Common Data Interfaces 255 20082 545 me 72
50. 96 0 kHz and 192 0 kHz S PDIF Receiver peripheral device supports linear PCM sample recovery up to 24 bits S PDIF subframe parity check biphase channel coding check subframe frame and block integrity checks and read miss notification This version does not perform cyclic redundancy check CRC for channel status bits in hardware CRC check can be implemented by software if needed Frame format is depicted in Figure 24 X Y and Z are the allowed preambles of a subframe An X subframe and an Y subframe constitute a frame X preamble is replaced by Z preamble every 192 frames to indicate block limit Channel 1 Channel 2 Channel 1 Channel 2 Channel 1 Channel 2 Sub frame 1 Sub frame 2 Frame 191 Frame 0 Frame 1 Start of block Figure 24 S PDIF frame format Subframe format is depicted in Figure 25 A Preamble is a signal pattern lasting 4 time slots S PDIF Receiver decodes it and keeps track of frame and block integrity A payload is max 24 bit sample word Validity bit indicates whether the payload is valid audio sample User data bit allows simultaneous data send Channel information is conveyed in channel status bits as specified in IEC 60958 1 and IEC 60958 3 S PDIF Receiver peripheral device uses the parity bit to calculate parity check The result is shown in SP_CTL register bits LPerr and RPerr Each bit occupies one time slot of the subframe a 0 3 4 27 28 29 30 31 Parity Preamble LSB 24 bit audio sample w
51. A_CF1 Bits Name Bits Description 15 Reserved use 0 ANA_CF1_VHMON 14 Regulator input voltage monitor VHIGH ANA_CF1_PWRBTN 13 Power button pin state ANA_CF1_BTNDIS 12 Power button reset disable 11 Reserved use 1 ANA_CF1_DBG 10 Debug mode pin state ANA_CF1_XTDIV 9 Input clock divider for 24 576 MHz XTALI oscillator ANA_CF1_SAR_ENA 8 SAR power and enable 7 Reserved Use 0 ANA_CF1_DA_ENA 6 DAC power and enable 5 4 Reserved use 00 ANA_CF1_DRV_ENA 3 DAC driver power enable 2 Reserved use 0 ANA_CF1_DAGAIN 1 0 DAC gain control DAC Gain ANA_CF1_DAGAIN Values Name Value Gain Description ANA_CF1_DAGAIN_M6DB 3 6dB 2 2dB Causes distortion in sound do not use ANA_CF1_DAGAIN_M12DB 1 12dB ANA_CF1_DAGAIN_ODB 0 0dB ANA_CF1_XTDIV is the input clock prescaler control register When register is set the input clock is divided by 2 ANA_CF1_SAR_ENA ANA_CF1_DA_ENA and ANA_CF1_DRV_ENA are analog module s enable signals When register is set the module is enabled ANA_CF2 Bits Name Bits Description 15 14 Reserved use 0 ANA_CF2_TSTE 13 Hardware debug test enable read only ANA_CF2_VCMST 12 Ground buffer short circuit monitor ANA_CF2_VCMDIS 11 Ground buffer driver short circuit protection disable ANA_CF2_UTM_ENA 10 Hi Speed USB U
52. Be D3 3 R ded 10 Pin U i 2 13 ETH_TXN is gt D4 ecommende In Usage IOVDD3 re gt i v ag A ETH_TXP bihir Yoga D5 2 12 E au lt 2 pg 1 15 TFT_CS aF W D7 2 11 ETH_RXP NF_RDY 2 10 SD_CMD RD 2 9 SD_DAT3 XCS1 A 2 8 SD_DAT2 amp SCLK1 f i 2 7 SD_DATI Y CVDD1 2 6 SD_DATO MISO1 2 5 SD_CLK co aN MM t Oo aN MJO N oa eso ei re St tat HH NAAN N ao dod a mon eone rd Mm wn N oO Oo a N mM T N N NN NMM Mm Mm mA A t rT 7 7 are tA MN DSC DONnZTOYONX xX ZTO N BEeanu tOGFsFRGuareaAAoZaA Of Sem xo oF FF ele Vw a 2 e Oo a 0 TIRES O ONLUS EXTRA SPI PORT BOOT JTAG ICE x S INPUT OR FAST LINK EEPROM DEBUGGER 5 OR OUTPUT OR SPI FLASH Figure 13 VS1005g default pin usage Version 0 63 2014 12 19 27 NLS 8 VS1005g General Description VS1005g Datasheet 8 VS1005G GENERAL DESCRIPTION VS1005g architecture is based on VS_DSP core VS_DSP core architecture is described in VS_DSP User s Manual Chip is powered with internal regulator which provides voltages for three separate power domains The core and periphery I O power domains can be driven off separately allowing simple I O interfacing and minimizing power consumption RTC has its own power supply which enables the RTC usage when the rest of the chip is powered down RTC also includes a small backup ram VS1005g has two clock domains which are clocked by PLL Analog interfaces are clocked with a XTALI clock but the dsp digital intarf
53. CF_FS is used to set src sample rate This register defines the interval in clock cycles when the samples are generated When new samples are stored to data registers also an interrupt request is generated Output sample rate can be calculated from equation fs XTALI 2 x src_cf_fs 1 where src_cf_fs can be between 0 and 4095 OxFFF Example With src_cf_fs 0x7FF the sample rate fs 12 288 MHz 2 Ox7FF 1 3000 Hz Version 0 63 2014 12 19 57 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 8 24 bit Analog to Digital Converters ADC DIAL Digital Analog and RF ANa cfo RED Pin FM_CF_UAD1 BLUE Register or register bit s F roe NA AD_CF_ADFS ANA SEO GAIN AD_LEFT gt t gt 94 24 m ANA_CF0 ANA CF3 A ae Gee a eas _GAIN2 ANA_CFO ADENA AD_CF_ADFS ko AD_CF_ ADR e AD_RIGHT m AD23_FLP 24 24 iced SI gt AD A AD_CF_AD3FS AD_MONO AD3 i 24 24 gt AD_CF_DEC6SEL I FML LGELUADS on ie AD_CF_DEC6ENA 2 demod i DEC6_LEFT 18 18 J Let JRS V6 DEC6_ RIGHT i Right Tg DIA2 Mono gt DIA3 SP_LDA A S PDIF 24 i decoder SP_RDATA 24
54. CHSTO_PCM is 0 SP_TX_CHSTO_PCMM selects linear PCM mode The default value is 000 which corresponds to 2 audio channels without pre emphasis SP_TX_CHSTO_CP is a copyright bit When 0 copyright for current stream is asserted SP_TX_CHSTO_PCM is 0 when the audio sample word is linear PCM SP_TX_CHSTO_PROCON is 0 in S PDIF defining consumer usage If this bit is 1 channel is for professional use and the interface would be called AES EBU However the channel status bits would be different in this case Channel Status SP_TX_CHST1 Name Bits of data Bits of Chan Description word nel status 15 14 31 30 Not specified 00 SP_TX_CHST1_CLKA 13 12 29 28 Clock Accuracy SP_TX_CHST1_FS 11 8 27 24 Sampling Frequency SP_TX_CHST1_CH 7 4 23 20 Channel Number SP_TX_CHST1_SRC 3 0 19 16 Source Number SP_TX_CHST1_CLKA indicates the level of clock accuracy the S PDIF transmitter is capable of providing to its output The sampling frequency of the audio sample stream is defined in SP_TX_CHST1_FS SP_TX_CHST1_CH is the number of channels in the transmission 0011 indicates two chan nel stereo format SP_TX_CHST1_SRC is the number of sources 0000 is defined as do not take into account Channel Status SP_TX_CHST2 Name Bits of Bits of Chan Description data word nel status SP_TX_CHST2_ST_
55. D 3 0 Packet id Endpoint number of last rx tx trans action The USB_ST_PID can be used mainly for debugging purposes Version 0 63 2014 12 19 88 VS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS GAN LSI USB_RDPTR Bits Name Bits Description USB _RDPTR 9 0 Packet Read Pointer This buffer marks the index position of the last word that the DSP has successfully read from the receive packet buffer DSP should control this register and update the position after each packet it has read from the receive buffer After reset this register is zero USB_WRPTR Bits Name Bits Description USB_WRPTR 9 0 Packet Write Pointer After a packet has been received from the PC the USB hardware updates this pointer to the receive buffer memory USB_WRPTR is index location of the next free word location in the USB receive buffer When USB_RDPTR equals to USB_WRPTR the packet input buffer is empty After reset this register is zero USB_UTMIR Bits Name Bits Description USB_UTMIR_LSTATE 15 14 USB bus line state USB_UTMIR_CNT 13 0 USB frame counter master mode USB_UTMIW Bits Name Bits Description USB_UTMIW_ORIDE 15 Bus override 14 Reserved use 0 USB_UTMIW_J 6 Drive chirp J USB_UTMIW_HSHK 5 Reset handshake USB_UTMIW_K 4 Drive chirp K USB_UTMIW_RCVSEL 3 Receiver selec
56. DE ote All VSOS features not available yet Version 0 63 2014 12 19 Applications Portable recorders Digital docking stations MP3 players Internet radio Wireless headphones Audio co processor Overview VS1005g is a flexible audio platform device It is built around VS_DSP which is a power ful DSP Digital Signal Processor core and runs VLSI Solution s proprietary DSP oriented multitasking VSOS operating system VS1005g s digital interfaces provide flexible access to external devices in standalone ap plications and flexible digital audio data in puts and outputs when the device is used as an audio signal processor in complex sys tems The analog interfaces provide high quality audio inputs and outputs and the con trol ADC can be used for example for interfac ing a resistive touch panel VS1005g has an embedded FLASH mem ory of 8Mi bits 1 MiByte for customization by VLSI customers or third parties The firm ware and hardware are designed to prevent access to the embedded FLASH in protected mode After FLASH memory programming VS1005g can be booted from it as a fully cus tomized stand alone audio processor VS1005g is offered in six different variants see Chapter 4 for details ENO vst 005g Datasheet CONTENTS Contents VS1005g Front Page 1 Table of Contents 2 List of Figures 7 1 Disclaimer 8 2 Licenses 8 3 Definitions 8 4 Product Variants 8 5 Characteristics amp Specifications 9
57. DEND register is automatically reset after one clock cycle RS_CF_DSTR initializes the R S decoder i e starts a new decoding sequence This register is reset automatically when first symbol is decoded RS_CF_DENA enables the R S decoder When RS_CF_DNF is set the decoder is decoding symbols as they are read from nand flash If RS_CF_DNF is reset the decoder starts reading Version 0 63 2014 12 19 80 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS symbols from peripheral memory from address RS_DPTR onwards The symbols are fetched from memory as 8 bit or 10 bit symbols but are always forwarded to decoder as 10 bit symbols where bits 9 8 are zero if RS_CF_D10B is reset The decoder decodes RS_DLEN number of symbols and then reset RS_CF_DENA Also an XP_ST_RSDEC_RDY interrupt request is generated RS_CF_DMODE register should be set when decoding nand flash data 10 bit NF When reset the 8 bit code is used RF RS_CF_SEL is used to select encoded parity symbols The selected parity symbol can be read from RS_DATA register RS_CF_ENF selects between two data input modes When set the encoder uses nand flash output data register as input When reset the data is fetched from peripheral memory RS_CF_ESTR initializes the R S encoder i e starts a new encoding sequence This register is reset automatically when first symbol is encoded The encoder does not need encode end register as the check symbols are updated on the
58. DIF receiver interrupt SP_RX_CLKDIV Bits Name Bits Description SP_RX_CLKDIV 7 0 Receiver clock divider SP_RX_CLKDIV is an 8 bit clock divider value that is used to adjust the S PDIF Receiver peripheral to proper Fs according to master clock frequency Default value is 8 resulting to Fs 48 kHz with master clock 24 576 MHz Values smaller than 4 are not allowed since at least 4 samples per audio sample are needed 2 samples per biphase mark S PDIF Receiver peripheral supports audio sampling frequencies up to 192 kHz The supported frequencies and corresponding bit rates are summarized in the following table Bit rate is sampling frequency multiplied by 64 which is channel number 2 times subframe time slot count 32 While the divider value should be targeted to bit rate of the table below the peripheral actually operates with quadruple clock rate This must be accounted for in the system clocking design The system clock must be at least four 4 times the bit rate if S PDIF peripheral is to be used In other words SP_CF_DIV values less than four lt 4 are forbidden Divider must be even number Version 0 63 2014 12 19 94 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS S PDIF Frequencies Fs bit rate Fs x 64 Minimum system clock rate 4 x bit rate 22 05 kHz 1 4112 MHz 5 6448 MHz 24 kHz 1 5386 MHz 6 144 MHz 32 kHz 2 048 MHz 8 192 MH
59. D_CF_NOSTARTB register forces the interface to skip start bit when set SD_CF_NOSTOPEB register forces the interface to skip stop bit when set SD_CF_CRC16 and SD_CF_CRC7 enable the crc calculation Crc is send automatically if SD_CF_NOCRCYTX is reset SD_CF_POLL forces the SD card interface to search for start bit when reading command re sponse or data If start bit is not found during 256 SD clock cycles the operation is cancelled Version 0 63 2014 12 19 84 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS and SD_ST_NOSTR error flag is set SD_ST Bits Name Bits Description SD_ST_WAITSTATES 12 8 SD card clock configuration SD_ST_REPEAT 7 Repeat mode enable Reserved 6 Use 0 SD_ST_CMDBRK 5 cmd response during data transfer SD_ST_DATO 4 SD card dat0 bus state SD_ST_NOSTOPB_ERR 3 data stop bit missing error SD_ST_CRC16_ERR 2 crc16 error when reading data SD_ST_CRC7_ERR 1 crc7 error when reading command response SD_ST_NOSTARTB_ERR 0 timeout error when reading no start bit SD_ST_WAITSTATES configures the length of SD card clock cycle The cycle time is 2 x SD_ST_WAITSTATES 1 dsp clock cycles SD_ST_REPEAT sets the interface into a pattern generation mode In this mode the SD data lines repeat a 512 byte buffer continuously The buffer s location in memory can be set with registers SD_PTR 10 8 In this mode all other SD_ST and SD_CF registers
60. E2 2 1 1 0 1 70 LINES 2 1 0 1 1 70 71 MIC2P amp ANA_CF2_AMP2_ENA MIC2N ANA_CF3_GAIN2 2 0 1 0 0 1 75 76 RF_N amp RF_P ANA_CF2_AMP2_ENA Q signal ANA_CF2_LNA_ENA NOTE There ANA_CF2_2G_ENA is no hardware ANA_CF3_FMDIV 1 0 to decode ANA_CF3_DIV 1 0 signals from ANA_CF3_GAIN2 2 0 this path ANA_CF3_2GCNTR 3 0 Note Decoding FM transmissions is only possible if both ADC1 and ADC2 are configured for FM reception RF pins and if ANA_CF3_GAIN1 ANA_CF3_GAIN2 Version 0 63 2014 12 19 60 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 8 2 Digital Filter Operation Modes The FM_CF register has four bits that have effect on AD functionality FM_CF_ENABLE acti vates digital filters When the register is set the digital filters are operable This register bit can also be used to synchronize the stereo and mono AD filters when three channels are used with same sample rate no phase error To do this clear FM_CF_ENABLE if not already cleared then set it again The input to digital filters can also be selected from external ADCs With FM_CF_UAD1 FM_CF_UAD2 and FM_CF_UADS registers the filters input can be taken from an external source pins DIA1 DIA2 and DIAS respectively In this mode the AD input sample rate must be XTALI 2 or XTALI 4 and the input must be synchronized to VS1005g the XTALI oscillator clock VS1005g can provide both the XTAL XTAL 2 and XTAL 4 clocks
61. I 1 Chapter 11 10 INT_SPIO 3 0x23 SPIO Chapter 11 10 INT_XPERIP 2 0x22 Common Data Interfaces Chapter 11 11 Ethernet SPI SD Nand flash Reed Solomon Ethernet INT_USB 1 0x21 Full Hi Speed USB Chapter 11 12 INT_DAC 0 0x20 DAC Chapter 11 7 1 Version 0 63 2014 12 19 43 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 4 1 Interrupt Controller Registers The interrupt controller has three type of registers e Enable registers which contain enable disable bits for each interrupt source Bit pairs configure the interrupt priority and disable e Origin registers which contain the source flags for each interrupt A request from an interrupt source sets the corresponding bit A bit is automatically reset when a request for the source is generated e Enable counter register which contains the value of the General Interrupt Enable counter and two registers for increasing and decreasing the value Interrupt Controller Registers Address Type Reset Abbrev Description OxFCO2 r w O INT_ENABLEO_HP Interrupt enable high priority for ints 0 15 OxFCOO r w O INT_ENABLEO LP Interrupt enable low priority for ints 0 15 OxFCO3 r w O INT_ENABLE1_HP_ Interrupt enable high priority for ints 16 27 OxFCO1 r w O INT_ENABLE1_LP_ Interrupt enable low priority for ints 16 27 OxFC04 r w O INT_ORIGINO Interrupt origin for interrupts 0 15 OxFC
62. I O bit and a data output input register bit for each of the bit engine registers GPIOx_BIT_CONF Bits Name Bits Description GPIO_BE_DAT1 15 12 Data bit selection 0 15 for bit engine 1 GPIO_BE_101 11 8 I O bit selection 0 15 for bit engine 1 GPIO_BE_DATO 7 4 Data bit selection 0 15 for bit engine 0 GPIO_BE_lO0 3 0 I O bit selection 0 15 for bit engine 0 GPIOx_BIT_ENGO is a register used to read write a GPIO pin specified in GPIOx_BIT_CONF register When writing a value to the bit engine O register the data bit specified in the configuration register is copied to the data output register bit specified in the same register When reading a value from the bit engine 0 register the data input register bit specified in the configuration register is copied to the data bit specified in the same register other bits read out as 0 GPIOx_BIT_ENG1 works just like GPIOx_BIT_ENGO Version 0 63 2014 12 19 92 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 14 S PDIF Peripheral 11 14 1 S PDIF Receiver S PDIF receiver interface offers a receiver function for serial digital audio S PDIF supports two channels which are multiplexed in one signal line Synchronizing to S PDIF input data bit frequency is done by the digital frequency divider the clock of which is generated by the low jitter programmable PLL Supported sampling frequencies are 32 0 kHz 44 1 kHz 48 0 kHz
63. IPHERALS AND REGISTERS 11 9 2 Configuring the FM Demodulator The FM demodulator has several configuration registers that must be initialized in order to receive an FM channel FM demodulator s control and data registers are listed in next table FM Control and Data Registers Reg Type Reset Abbrev Description OxFE40 r w 0 FM_CF FM demodulator control OxFE41 r w 0 AD_CF AD filter configuration OxFE42 r w 0 FMPLL_LO FM PLL carrier frequency bits 15 0 OxFE43 r w 0 FMPLL_HI FM PLL carrier frequency bits 28 16 OxFE44 r w 0 FMCCF_LO Carrier center frequency bits 15 0 OxFE45 r w 0 FMCCF_HI 10 0 Carrier center frequency bits 26 16 OxFE4E r 0 DEC6_LEFT_LSB 15 14 FM filter left channel bits 1 0 OxFE4F r 0 DEC6_LEFT FM filter left channel bits 17 2 OxFE50 r 0 DEC6_RIGHT_LSB 15 14 FM filter right channel bits 1 0 OxFE51 r 0 DEC6_RIGHT FM filter right channel bits 17 2 OxFE52 r 0 RDS_DATA FM RDS data OxFE53 r 0 RDS_CHK 12 0 FM RDS checkwork and block status OxFE5B r 0 FM_PHSCL FM I Q phase error scaling factor FM_CF register is a configuration register which is used to select demodulator operation modes The FMCCF_HI and FMCCF_LO are used to tune FM receiver to a certain channel The FM PLL_HI and FMPLL_LO registers are used to match xtal frequency to the stereo subcarrier frequency 38 kHz FM
64. L USB_EP_ST_ISTL_SENT At least 1 STALL sent USB_EP_ST_INAKSENT At least 1 NAK sent USB_EP_ST_IXMIT_EMP Transmitter empty O NIO A reserved Use 0 11 12 2 USB Clocking Modes USB usage requires a special clock setup The core clock must be set to 60 MHz If only Full Speed USB is used the 60 MHz clock can be achieved byt placing the PLL to 5x clocking mode and using 12 000 MHz XTAL When Hi Speed USB is used the core clock must also be 60 MHz but this clock is generated with a PLL which can be programmed with fractional multiplier fac tors The xtal oscillator frequencies of 12 000 MHz or 12 288 MHz are recommended in this mode 11 12 3 USB Host USB module can be configured as an USB host In USB host mode the 1 5kOhm pull up resistor in D pin is replaced with 15kOhm pull down resistors in in both the D and D pins USB host is capable of Send Start of Frame SOF packets Send SETUP IN and OUT packets Schedule transfers within 1ms frames Signal USB bus reset Provide USB power management Version 0 63 2014 12 19 90 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 13 Interruptable General Purpose IO Ports 0 2 VS1005g has 3 general purpose IO ports that can operate either in GP mode or in perip mode In order to use pins as gpio the GPIOx_MODE registers must be reset default value GPIO port 0 1 and register offsets are OxFCAO OxFCCO and
65. ND REGISTERS Note that the S PDIF interface does not interact with any other audio paths It is only included to show all available audio input paths digital or analog AD filter s control and data registers are listed in following table A D Control and Data Registers Reg Type Reset Abbrev Description OxFE40 r w 0 FM_CF FM demodulator and AD filter configura tion register OxFE41 r w 0 AD_CF AD filter configuration register OxFE46 r 0 AD_LEFT_LSB 15 8 AD1 filter left channel bits 7 0 OxFE47 r 0 AD_LEFT AD1 filter left channel bits 23 8 OxFE48 r 0 AD_RIGHT_LSB 15 8 AD2 filter right channel bits 7 0 OxFE49 r 0 AD_RIGHT AD2 filter right channel bits 23 8 OxFE4A r 0 AD_MONO_LSB 15 8 AD3 filter mono channel bits 7 0 OxFE4B r 0 AD_MONO AD3 filter mono channel bits 23 8 OxFE4E r 0 DEC6_LEFT_LSB 15 14 FM filter left channel bits 1 0 OxFE4F r 0 DEC6_LEFT FM filter left channel bits 17 2 OxFE50 r 0 DEC6_RIGHT_LSB 15 14 FM filter right channel bits 1 0 OxFE51 r 0 DEC6_RIGHT FM filter right channel bits 17 2 11 8 1 Configuring Signal Paths for ADC1 ADC2 and ADC3 Analog signal paths for ADCs are configured using registers ANA_CFO see Chapter 11 6 1 on Page 49 and AD_CF see Chapter 11 8 2 Page 61 ADC1 Signal Path Configuration Note Always set ANA_CF2 bits ANA_CF2_REF_ENA and ANA_CF2_M1_ENA
66. NLS VS1005g Datasheet VS1005g Audio Processing Platform IC Analog Hardware Features Three channels of 24 bit audio ADC Two 24 bit audio DACs Stereo earphone driver for 30 Q load Internal microphone amplifiers Stereo FM radio receiver with RDS 10 bit ADC 3 5 external inputs Operation from single power supply four programmable internal regulators Digital Hardware Features 100 MIPS VS_DSP processor core 128 KiB program RAM 32 KiWord 128 KiB data RAM 2x32 KiWord Protected 8 Mi bit FLASH Optional USB 2 0 Hi Speed 480 Mbit s Device Host 12S and SPDIF digital audio interfaces NAND FLASH interface with EEC SD Card interface 2 SPI bus interfaces 10BaseT Ethernet controller UART interface All digital pins are user configurable for general purpose IO e Flexible clock selection default opera tion from 12 288 MHz e Internal PLL clock multiplier for digital logic e RTC with battery backed memory e Reed Solomon error correction e HW debug support with VSIDE via JTAG Firmware and VSOS Features e Decoders MP3 WMA Ogg Vorbis AAC AAC FLAC WAV PCM Encoders MP3 Ogg Vorbis WAV PCM File I O for SD cards and NAND flash FM tuner and RDS decoder USB host and slave libraries Graphical display with resistive touch panel e e e e e e Extensive audio DSP library e IP stack of Ethernet e Flexible boot options e Pre emptive multitasking e N Easy to write software interface with VSI
67. NWRQ 13 New Word Request read only bit SP_TX_CHST2_TX_ENA 12 Transmitter enable SP_TX_CHST2_RS1_RU 11 User Data bit right channel SP_TX_CHST2_RS1_RV 10 Validity bit right channel SP_TX_CHST2_LS1_RU 9 User Data bit left channel SP_TX_CHST2_LS1_RV 8 Validity bit left channel SP_TX_CHST2_CH2_FSO 7 4 39 36 Original Sampling Frequency SP_TX_CHST2_CH2_WRDL 3 1 35 33 Sample Word Length SP_TX_CHST2_CH2_WRDLM 0 32 Maximum Sample Word Length SP_TX_CHST2_ST_NWRQ bit is set when new sample words must be written to sample word registers Itis cleared when SP_TX_CHST2_TX_LDATA is written Hence SP_TX_CHST2_ST_NWRQ has the same function as S PDIF Interrupt but this bit is not controlled by SP_TX_CHST2_CF_IE SP_TX_CHST2_TX_ENA is the S PDIF transmit enable Transmitter is enabled when this reg ister is set SP_TX_CHST2_RS1_RU is a user data bit for the right channel Default value is 0 User data bits can be used to convey an application specific message to the receiver Some equipment Version 0 63 2014 12 19 98 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS categories dictate the message see IEC 60958 3 SP_TX_CHST2_RS1_ RV is the validity bit of the right channel sample word If the audio sam ple word is not a linear PCM this bit must be set SP_TX_CHST2_LS1_LU is a user data bit for the left channel Default value is 0 User data bits can be used to convey an application specific message to th
68. O5 r w O INT_ORIGIN1 Interrupt origin for interrupts 16 27 OxFC06 r 0 INT_VECTOR 4 0 Interrupt vector OxFCO7 r w 0 INT_ENCOUNT 2 0 Interrupt enable counter OxFC08 w 0 INT_GLOB_DIS Interrupt global disable OxFCO9 w 0 INT_GLOB_ENAJ Interrupt global enable 11 4 2 Interrupt Enable INT_ENABLE 0 1 H L P Interrupt enable registers selectively masks interrupt sources Enable registers 0 contain sources 0 15 and enable registers 1 contain sources 16 27 Each source has two enable bits one in the enable high priority _HP and one in the enable low priority _LP register If both bits are zero the corresponding interrupt source is not enabled otherwise the bits select the interrupt priority HP _LP Priority 0 0 Source disabled 0 1 Priority 1 low 1 0 Priority 2 medium C a1 1 Priority 3 high Priorities only matter when the interrupt controller decides which interrupt to generate for the core next This happens whenever two interrupt sources request interrupts at the same time or when interrupts become enabled after an interrupt handler routine or a part of code where the interrupts have been disabled Version 0 63 2014 12 19 44 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 4 3 Interrupt Origin INT_ORIGIN 0 1 If an interrupt source requests an interrupt the corresponding bit in the interrupt origin regis ter
69. OPD Nand flash IO7 General purpose IO Port 0 bit 7 NFRDY GPIOO_8 17 DIO Nand flash READY General purpose IO Port 0 bit 8 NFRD GPIOO_9 18 DIO Nand flash RD General purpose IO Port 0 bit 9 XCS1 GPIO1_4 19 DIOPD SPI1 XCS General Purpose I O Port 1 bit 4 SCLK1 GPIO1_5 20 DIOPD SPI1 CLK General Purpose I O Port 1 bit 5 CVDD1 21 CPWR Core power supply connect to regulator CPWR MISO1 GPIO1_6 22 DIOPD SPI1 MISO General Purpose I O Port 1 bit 6 Pin Name LFGA Pin Type Function Pin MOSI1 GPIO1_7 23 DIOPD SPI1 MOSI General Purpose I O Port 1 bit 7 NFWR GPIOO_10 24 DIO Nand flash WR General purpose IO Port 0 bit 10 IOVDD1 25 IOPWR I O power supply connect to regulator IOPWR NFCE GPIOO_11 26 DIOPD Nand flash CE General purpose IO Port 0 bit 11 XCSO GPIO1_0 27 DIOPD SPIO XCS General Purpose I O Port 1 bit 0 SCLKO GPIO1_1 28 DIOPD SPIO CLK General Purpose I O Port 1 bit 1 MISOO GPIO1_2 29 DIOPD SPIO MISO General Purpose I O Port 1 bit 2 MOSIO GPIO1_3 30 DIOPD SPIO MOSI General Purpose I O Port 1 bit 3 TMS GPIO2_0 31 DIOPD JTAG TMS General Purpose I O Port 2 bit 0 TDI GPIO2_1 32 DIOPD JTAG TDI General Purpose I O Port 2 bit 1 TDO GPIO2_2 33 DIOPD JTAG TDO General Purpose I O Port 2 bit 2 TCK GPIO2_3 34 DIOPD JTAG TCK General Purpose I O Port 2 bit 3 DBGREQ GPIO2_4 35 DIOPD Debug interrupt General Purpose I O Port 2 bit 4 CVDD2 36 CPWR Core power supply connect to regulator CPWR
70. OSET_CF_FULL 13 Data register full flag DAOSET_CF_ENA 12 Enable for DAC offset DAOSET_CF_FS 11 0 DAC offset sample rate DAOSET_CF_URUN is an underrun flag register The register is set if data register was read when the full flag was not set DAOSET_CF_FULL is a data status register Flag is set when data is written to DAOSET_LEFT and DAOSET_RIGHT registers and reset when DAC reads the register DAOSET_CF_ENA enables DAC offset module DAOSET_CF_FS is used to set DAC offset sample rate This register defines the interval in clock cycles where the samples are added to DAC output When new samples are read from data registers also an interrupt request is generated Sample rate can be calculated from equation fs Fur dacof fset_cf_fs 1 where dacoffset_cf_fs can have values from 0 to 4095 OxFFF and Fa is the XTALI clock frequency E g value OxFFF gives sample rate of 12 288 MHz OxFFF 1 3 0 kHz DAC and DAC offset mixing logic uses saturation to limit samples to 20 bit signed values The mixed values should not exceed 75 of the full scale values or the signal to noise ratio may be degraded Version 0 63 2014 12 19 56 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 7 4 Filterless Sample Rate Converter SRC Registers VS1005g has a programmable sample rate converter which can be used to convert DAC s input sample rate to an other sample rate which is higher than t
71. OxFCEO accordingly GPIO port 0 and 1 are 16 bits wide and GPIO port 2 is 14 bits wide Interruptable General I O Registers Prefix GPIOx_ Reg Type Reset Abbrev Description Ol rw 0 DDR Data direction 1 rw 0 ODATA Data output 2 r 0 IDATA Data input I O pin state 3l rw 0 INT_FALL Falling edge interrupt enable 4 rw O INT_RISE Rising edge interrupt enable 5f rw I0 INT_PEND Interrupt pending source 6 w 0 SET_MASK Data set 1 mask 7 Ww 0 CLEAR_MASK Data clear 0 mask 8 rw 0 BIT_CONF Bit engine config 0 and 1 9 rw 0 BIT_ENGO Bit engine 0 read write 10 rw 0 BIT_ENG1 Bit engine 1 read write GPIOx_DDR register configure the directions of each of the 16 I O pins A bit set to 1 in the DDR turns the corresponding I O pin to output mode while a bit set to 0 sets the pin to input mode The register is set to all zeros in reset i e all pins are inputs by default The current state of the DDR can also be read GPIOx_ODATA register sets the GPIO pin high or low Only pins that are configured as outputs are affected GPIOx_IDATA monitiors the current state of a pin The actual logical levels of the I O pins are seen in the input data register Note The pin state can be read even if the pin is in peripheral mode i e GPIOx_MODE y is set GPIOx_INT_RISE and GPIOx_INT_FALL configures an interrupt trigger edge If a bit of the falling edge interru
72. PIO2_7 SD DATO GPOI2 6 SD_CLK GPIO2_5 VS1005g 88 pin LFGA pin assignment 23 NLS VS1005g Datasheet 6 PACKAGE AND PIN DESCRIPTIONS 6 4 VS1005g Pin Descriptions Pin Name LFGA Pin Type Function Pin GPLATE 0 PWR Center ground plate use multiple vias to create low impedance connection to ground network on PCB Pin Name LFGA Pin Type Function Pin XTALO 1 AO Crystal output XTALI 2 Al Crystal input AVDD 3 APWR Analog power supply Regulator output VHIGH 4 PWR Power supply Regulator input CVDD 5 CPWR Core power supply Regulator output IO2VDD 6 IO2PWR Serial Flash power supply Regulator output IOVDD 7 IOPWR I O power supply Regulator output XRESET 8 DI Active low asynchronous reset schmitt trigger input NFDIOO GPIO0_0 9 DIOPD Nand flash lOO General purpose IO Port 0 bit 0 NFDIO1 GPIOO_1 10 DIOPD Nand flash 1O01 General purpose IO Port 0 bit 1 NFDIO2 GPIOO_2 11 DIOPD Nand flash IO2 General purpose IO Port 0 bit 2 NFDIO3 GPIOO_3 12 DIOPD Nand flash lO3 General purpose IO Port 0 bit 3 NFDIO4 GPIOO_4 13 DIOPD Nand flash 104 General purpose IO Port 0 bit 4 NFDIO5 GPIOO_5 14 DIOPD Nand flash IO5 General purpose IO Port 0 bit 5 NFDIO6 GPIOO_6 15 DIOPD Nand flash lO6 General purpose IO Port 0 bit 6 NFDIO7 GPIOO_7 16 DI
73. RT Registers Reg Type Reset Abbrev Description OxFE0O r 0 UART_STATUS 4 0 Status OxFEO1 r w 0 UART_DATA 7 0 Data OxFEO2 r w 0 UART_DATAH 15 8 Data High OxFEO3 r w 0 UART_DIV Divider UART_STATUS register monitors the UART status UART_STATUS Bits Name Bits Description UART_ST_FRAMERR 4 Framing Error stop bit was 0 UART_ST_RXORUN 3 Receiver overrun UART_ST_RXFULL 2 Receiver data register full 1 0 UART_ST_TXFULL Transmitter data register full UART_ST_TXRUNNING Transmitter running UART_ST_FRAMERR is set at the time of stop bit reception When reception is functioning normally stop bit is always 1 If however O is detected at the line input at the stop bit time UART_ST_FRAMERR is set to 1 This can be used to detect break condition in some protocols UART_ST_RXORUN is set if a received byte overwrites unread data when it is transferred from the receiver shift register to the data register otherwise it is cleared UART_ST_RXFULL is set if there is unread data in the data register UART_ST_TXFULL is set if a write to the data register is not allowed data register full UART_ST_TXRUNNING is set if the transmitter shift register is in operation UART_DATA is the uart data register A read from UART_DATA returns the received byte in bits 7 0 bits 15 8 are returned as 0 If there is no more data to be read the receiv
74. RX GPIO1_8 37 DIO UART RX General Purpose I O Port 1 bit 8 connect with 100 kQ to IOVDD if not used for UART TX GPIO1_9 38 DIO UART TX General Purpose I O Port 1 bit 9 I2S_DI GPIO1_10 39 DIOPD 12S data in General Purpose I O Port 1 bit 10 I2S DO GPIO1_11 40 DIOPD 12S data out General Purpose I O Port 1 bit 11 12S BCK GPIO1_12 41 DIOPD 12S bit clock General Purpose I O Port 1 bit 12 I2S_ FRM GPIO1_13 42 DIOPD 12S frame sync General Purpose I O Port 1 bit 13 lIOVDD2 43 IOPWR I O power supply connect to regulator IOPWR I2S_12M GPIO1_14 44 DIOPD 12S XTALI clock output General Purpose I O Port 1 bit 14 Version 0 63 2014 12 19 24 NLS VS1005g Datasheet 6 PACKAGE AND PIN DESCRIPTIONS Pin Name LFGA Pin Type Function Pin SD_CLK GPIO2_5 45 DIOPD SD card clock General Purpose I O Port 2 bit 5 SD_DAT0O GPIO2_6 46 DIO SD card data line 0 General Purpose I O Port 2 bit 6 SD_DAT1 GPIO2_7 47 DIO SD card data line 1 General Purpose I O Port 2 bit 7 SD_DAT2 GPIO2_8 48 DIO SD card data line 2 General Purpose I O Port 2 bit 8 SD_DAT3 GPIO2_9 49 DIO SD card data line 3 General Purpose I O Port 2 bit 9 SD_CMD GPIO2_10 50 DIO SD card cmd line General Purpose I O Port 2 bit 10 ETH_RXP GPIO2_11 DIA3 51 DIOPD Ethernet RXP General Purpose I O Port 2
75. S 11 9 FM Receiver The FM receiver in VS1005g is capable of receiving frequency modulated FM signals from 76 MHz to 108 MHz The operation of FM receiver requires several modules e RF modules VCO LNA and Mixer e Analog modules Muxes amplifiers and ADCs e Digital modules Digital filters and FM demodulator As was shown in Figure 18 the FM receiver uses partially the same signal paths as the ADCs When FM demodulator is used the stereo AD filter must be configured to 192 kHz sample rate and the decimation filter enabled with input selection from FM demodulator Other modules must be powered up and FM path is selected to analog output 11 9 1 Configuring RF and Analog Modules for FM Receiver Mode The front end configuration of the FM receiver is shown in Figure 19 The VCO is digitally controlled and set to an FM band as is explained in section Configuring FM Demodulator RF_p RF_n FM enable gt fi FM VCO A Front End 4 enable clk_12M gt gt sel_rf1 2 vv 3 0 p gt gt gt oo pod e EE g i t enablel 2 95 80 AMP1 AMP2 gt amp gt O 4 gain1 2 vy ADC1 ADC2 4 enable1 2 al Je Figure 19 Block diagram of FM receiver RF and analog section To see how to configure the A D converters for FM reception usage see Chapter 11 8 1 on Page 59 Version 0 63 2014 12 19 63 ENS vst 005g Datasheet 11 VS1005G PER
76. TC_I_RDDIV128 When RTC_RDBUSY is set the rtc_if first samples the selected rtc register to RTC data buffer When the data is read to RTC_HIGH and RTC_LOW registers When rtc_if is ready it resets the RTC_RDBUSY RTC_EXEC is used to execute current RTC instruction Before executing an instruction a valid instruction must be in RTC instruction register RTC_ _ RESET RTC_I _ LOADRTC For Version 0 63 2014 12 19 107 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS RTC_ _RESET RTC_I _ LOADRTC instructions the RTC_EXEC register must be set for 1 sec ond before the instruction is ececuted The user must reset the RTC_EXEC register after this time has elapsed RTC_GSCK is used to generate RTC memory clock When RTC_GSCK is set the rtc_if gen erates one clock pulse for memory store RTC_EXEC must be set during this operation Rtc_if resets this register automatically RTC instructions are 8 bit codes which are written to RTC_HIGH 15 8 before setting RTC_IBUSY RTC Instruction Codes Instruction Hex code Delay Description RTC_ _ RESET EB 1 128s Reset control registers RTC_ _ LOADRTC 59 1s Initialize time counter register RTC_l _ READRTC 56 1 12MHz Read time counter register RTC_ _ RDDIV128 C7 1 12MHz Read 8 bit divider register 1 128s RTC_ _ ALARM AC 1 128s Set RTC alarm time RTC_ MEM_WR 35 1 12MHz Write to rtc memory RTC_ _ MEM_RD 3A 1 12MHz Read from RTC memory
77. TM enable ANA_CF2_LNA_ ENA 9 Low Noise Amplifier enable ANA_CF2_2G_ENA 8 2GHz VCO enable ANA_CF2_AMP1_ENA 7 Microphone amplifier 1 enable ANA_CF2_AMP2_ENA 6 Microphone amplifier 2 enable 5 Reserved use 0 ANA_CF2_HIGH_REF 4 Analog reference voltage V 1 2 V 0 or 1 6 V 1 ANA_CF2_REF_ENA 3 Analog reference power enable ANA_CF2_M3_ENA 2 ADC 3 power enable ANA_CF2_M2_ENA 1 ADC 2 power enable ANA_CF2_M1_ENA 0 ADC 1 power enable ANA_CF2 register controls several analog module power enables Each module is enabled when the power enable register bit is set Version 0 63 2014 12 19 50 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS ANA_CF3 Bits Name Bits Description ANA_CF3_480 ENA 15 480 MHz clock enable ANA_CF3_UTMBIAS 14 USB pad bias enable ANA_CF3_FMDIV 1 0 13 12 FM divider selection 16 20 or 24 ANA_CF3_DIV 1 0 11 10 VCO divider select register ANA_CF3_GAIN2 2 0 9 7 ADC 2 gain register ANA_CF3_GAIN1 2 0 6 4 ADC 1 gain register ANA_CF3_2GCNTR 3 0 3 0 VCO center frequency register ANA_CF3_FMDIV is the VCO divider selection register for FM receiver When the register is set the VCO clock is divided by 20 FM mode When the register is reset the divider value is 16 HS USB mode ANA_CF3_FMDIV2 register selects the divider 24 In this divider mode the ANA_CF3_FMDIV should be set The VCO frequency is therefore
78. USB firmware assumes XTALI 12 288 MHz 3 The 32 kHz crystal is optional but required for RTC time counter Version 0 63 2014 12 19 10 ENS vst 005g Datasheet 5 CHARACTERISTICS amp SPECIFICATIONS 5 3 Analog Characteristics of Audio Outputs Unless otherwise noted AVDD 3 6 V CVDD 1 8 V IOVDD 2 8 V V ef 1 6 V TA 25 C XTALI 12 MHz Internal Clock Multiplier 3 0x DAC tested with full scale output sinewave mea surement bandwidth 20 20000 Hz analog output load LEFT to CBUF 302 RIGHT to CBUF 30 Microphone test amplitude 50 mVpp f 1 kHz Line input test amplitude 2 2 Vpp f 1 kHz FM test signal input level 70 dBm deviation 75 kHz pre emphasis 50 ps f 1 kHz DAC Characteristics Parameter Symbol Min Typ Max Unit DAC Resolution 24 bits Dynamic range DAC unmuted A weighted min gain IDR 100 dB S N ratio full scale signal no load SNR 92 dB S N ratio full scale signal 30 ohm load SNRL 90 dB Total harmonic distortion 3dB level no load THD 0 01 Total harmonic distortion 3dB level 30 ohm load THDL 0 05 Crosstalk L R to R L 30 ohm load without CBUF XTALK1 75 dB Crosstalk L R to R L 30 ohm load with CBUF XTALK2 54 dB Gain mismatch L R to R L GERR 0 5 0 5 dB Frequency response AERR 0 05 0 05 dB Full scale output voltage LEVEL 1 0 Vrms Deviation from linear phase PH 0 5 Analog output load resistance AOLR 30 Q Analog
79. U_VOLT Bits Name Bits Description REGU_VOLT_AVDD 4 0 14 10 Analog voltage configuration 2 7V 3 6V REGU_VOLT_IOVDD 4 0 9 5 IO voltage configuration 1 8V 3 6V REGU_VOLT_CVDD 4 0 4 0 Core voltage configuration 1 65V 1 9V REGU_CF Bits Name Bits Description REGU_CF_SNFVOLT 11 7 Serial Flash voltage configuration REGU_CF_SNFOFF 6 Serial Flash voltage regulator shutdown REGU_CF_ADOFF AD filter clock gate control REGU_CF_FMOFF FM demodulator clock gate control REGU_CF_REGCK Regulator latch enable REGU_CF_AOFF Analog voltage regulator shutdown REGU_CF_IOOFF IO voltage regulator shutdown REGU_CF_COFF Oo N ow A oO Core voltage regulator shut down 1 User should not modify this register if embedded serial flash is used REGU_CF_ADOFF and REGU_CF_FMOFF control the AD and FM peripheral clocks When these registers are set the clocks are cut off REGU_CF_REGCK is used to latch in the regulator voltage and shutdown bits Typical values for voltages are calculated from equations e CVDD 1 24V 30mV x voltage register e IOVDD 1 80V 60mV x voltage register e AVDD 2 48V 40mV x voltage register Version 0 63 2014 12 19 52 GIN LSI VS1 005g Datasheet VS1005G PERIPHERALS AND REGISTERS 11 7 Audio Playback Interfaces
80. VDD voltage monitor Parameter Symbol Min Typ Max Unit Trigger voltage CMON 1 40 1 45 V Hysteresis 2 mV 5 10 Power Button Characteristics Unless otherwise noted VHIGH 4 0 5 3 V Parameter Symbol Min Typ Max Unit Power button activation threshold PBTHR 1 0 V 5 11 Digital Characteristics Parameter Symbol Min Typ Max Unit High Level Input Voltage 0 7xIOVDD IOVDD 0 3 V Low Level Input Voltage 0 2 0 3xIOVDD V High Level Output Voltage 1 0 mA load 0 7xIOVDD V Low Level Output Voltage 1 0 mA load 0 3xIOVDD V XTALO high level output voltage 0 1 mA load 0 7xIOVDD V XTALO low level output voltage 0 1 mA load 0 3xIOVDD V Input leakage current 1 0 1 0 uA Rise time of all output pins load 30 pF 50 ns 1 Pins GPIOO_ 15 0 GPIO1_ 15 0 GPIO2_ 13 0 Version 0 63 2014 12 19 14 ENO vst 005g Datasheet 5 CHARACTERISTICS amp SPECIFICATIONS 5 12 Power Consumption 5 12 1 Digital Power Consumption The following power consumptions are unless otherwise noted obtained with the following parameters decoding 128 kbit s 44 1 kHz stereo MP3 from RAM memory to analog output CVDD 1 67 V AVDD 3 6 V IOVDD 3 3 V V7 1 6 V XTALI 12 288 MHz Digital Current Consumption from CVDD MP3 decode Parameter Symbol Min Typ Max Unit
81. YNC pin If SPIx_DATA is written to without priorly writing to SPIX_FSYNC the last value written to SPIx_FSYNC is sent Version 0 63 2014 12 19 70 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS SPIx_FSYNC is double buffered like SPIx_DATA The SPI block has one interrupt Interrupt 0 request is sent when SPI_ST_BREAK is asserted or when SPI_ST_TXFULL or SPI_ST_TXRUNNING is cleared This allows for sending data in an interrupt based routine and turning chip select off when the device becomes idle Version 0 63 2014 12 19 71 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 11 Common Data Interfaces VS1005g has a 3 KiB data buffer which is a dedicated peripheral memory The memory can be configured to be used with e Ethernet interface e Nand Flash Interface e SD Card Interface e Reed Solomon Codecs Block diagram of the data interfaces is shown in Figure 21 Ethernet 10Base t SPI slave lt gt SPI bus Nand Flash gt Nand Flash 3kB data Reed Solomon encode Reed Solomon decode Figure 21 Block diagram of data interfaces Each peripheral can be configured to use its own address space The DSP interface has a read and write port with auto incrementing address register The read operation is pipelined and requires two reads to fill the pipeline After that the memory can be read on each instruction cycle It should be noted that the memory is time multiplexed be
82. _CF Bits Name Bits Description 15 Reserved use 0 FM_CF_UAD2 14 Enable AD2 digital input FM_CF_UAD1 13 Enable AD1 digital input FM_CF_UAD3 12 Enable AD3 digital input 11 8 Reserved Use 000 FM_CF_PHCOMP 7 Enable for FM I and Q signal scaling FM_CF_ENABLE Enable amp synchronize AD filters and FM demodulator FM_CF_RDSSYNC FM RDS forced to keep synchronization FM_CF_MONO FM receiver mono 1 stereo 0 selection FM_CF_DEEMP FM de emphasis filter configuration 75s or 50us FM CF RDSENA FM_CF_CCFLCK FM CF FM ENA FM RDS enable FM carrier lock enable FM demodulator enable N A O O In FM mode the registers FM_CF_UAD2 and FM_CF_UAD1 must be reset FM_CF_PHCOMP is the enable signal for FM input scaling FM_CF_ENABLE is the global enable for FM demodulator and AD filters When zero demod ulators and mono stereo AD filters are reset To synchronize and use the demodulators first Version 0 63 2014 12 19 64 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS clear this bit then set it FM_CF_RDSSYNC forces the RDS decoder to keep current symbol synchronization When sync search is enabled i e FM_CF_RDSSYNC is reset the RDS decoder tries to find best symbol synchronization at all times even when the FM signal is lost FM_CF_MONO register selects between mono and stereo receive modes When set the mode is mono FM_CF_DEEMP register selects between
83. aces and memories are clocked with a multiplied clock VS1005g external interfaces are shown in Figure 14 Display vs1005 NF DIO NF WE RE CE Nand flash 2 NF BUSY XRESET lt amp SPDIF OUT TEST _ a XI SPDIF IN SPDIF F 12 288MHz E Battery SPIO SI SO RTCXI SPIO CLK XCS cs 32kHz SPI eprom SPIL SI SO SPrdevige E SPI1 CLK XCS a LEFT RIGHT gt 5 CBUF Uart UART TX RX AD1 AD2 AD3 4 D 0 4 f le Ps 28 CLKIBCK FRM SARADO 12S DI DO FM ANTENNA _ USB DP F sp cf SD CLK E wn yeu SD CMD DAT USB DN lt gt ETH RX Ethernet JTAGEN _ ETH TX TCK TMS S JTAG TDLTDO debugger DBGREQ a oO Figure 14 VS1005g external interfaces Version 0 63 2014 12 19 28 VLSI GAN LSI 8 1 VS1005g Internal Architecture VS1005g Datasheet 8 VS1005G GENERAL DESCRIPTION VS1005g block diagram is shown in Figure 15 PWRBTN AVDD IOVDD CVDD XRESET CLK12M SPI BUS GP BUS SPDIF BUS NF SD ETH BUS JTAG BUS USB BUS CBUFRCAP LEFT RIGHT FM_P FM_N LINE1 2 MIC1 2 LINE3 AUX BUS Reference Regulator Regulator Regulator voy v Common Voltage Driver Stereo Earphone Driver Stereo ADC A vy ID Flash Voltage Monitor Stereo DAC al gt
84. ad enable XP_CF_ODAT is a control register for RS_ODATA register XP_CF_ECCRST and XP_CF_ECCENA control the ECC unit XP_CF_ECCRST reset the unit when set THe register is reset automatically after one clock cycle XP_CF_ECCENA register enables the ECC calculation column parity CP and line parity LP registers are modified when data is read from XP_ODATA or written to XP_IDATA register and XP_CF_ECCENA is set XP_CF_WRBUF_ENA and XP_CF_RDBUF_ENA enable the DSP access to the peripheral data buffer When either register is set the XP_ADDR is incremented on each memory access and data is read XP_IDATA or written XP_ODATA to memory Version 0 63 2014 12 19 73 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS Data interfaces can generate only one interrupt request for the DSP INT_XPERIP see Chap ter 11 4 Interrupt Controller The interrupt source is stored in the interrupt status register XP_ST XP_ST is used to track the interrupt source of the peripherals using data buffer memory With the exception of bit XP_ST_INT_ENA and XP_ST_SPIERR_INT a write to XP_ST bits clears the bits in the origin register that are set by the write In other words writing b to XP_ST performs the logical operation XP_ST 13 10 8 0 XP_ST 13 10 8 0 and not b XP_ST 14 b 14 XP_ST 9 XP_ST 9 Example If value for XP_SP is 0x47FF writing 0x440F to it will end up with XP_ST 0x440F and 0x4000 or O
85. and analog section 63 20 Structure of the RDS baseband coding group 4 66 21 Block diagram of data interfaces 2 0005022 eee 72 22 VS1005g USB block diagram 2 ee ee 86 23 VS1005g UTM functional block diagram 22 0054 ee 87 24 S PDIF frame format ee a 93 25 S PDIF sub frame format 2 eee a 93 26 RS232 serial interface protocol o oaoa a 100 27 l2S frame format 3 a6 ee dee do aR Oe Ke He Beh OSE ee 103 28 JTAG state machine 2 222 eee ee ee ee 113 Version 0 63 2014 12 19 7 ENO vst 005g Datasheet 4 PRODUCT VARIANTS 1 Disclaimer This is a preliminary datasheet All properties and figures are subject to change 2 Licenses MPEG Layer 3 audio coding VS1205 decoding VS1005 technology licensed from Fraun hofer IIS and Thomson Supply of this product does not convey a license nor imply any right to distribute MPEG Layer 3 compliant content created with this product in revenue generating broadcast systems terres trial satellite cable and or other distribution channels streaming applications via Internet intranets and or other networks other content distribution systems pay audio of audio on demand applications and the like or on physical media compact discs digital versatile discs semiconductior chips hard drives memory cards and the like An independent license for such use is required For details please visit http mp3licensing co
86. bit 11 Digital ADC 1 input GPIO1_15 52 DIOPD General Purpose I O Port 1 bit 15 ETH_TXP GPIO2_12 DIA1 53 DIOPD Ethernet TXP General Purpose I O Port 2 bit 12 Dig ital ADC 1 input IOVDD3 54 IOPWR I O power supply connect to regulator IOPWR ETH_TXN GPIO2_13 DIA2 55 DIOPD Ethernet TXN General Purpose I O Port 2 bit 13 Digital ADC 1 input SPDIF_IN GPIOO_12 56 DIOPD S PDIF data in General Purpose I O Port 0 bit 12 SPDIF_OUT GPIOO_13 57 DIOPD S PDIF data out General Purpose I O Port 0 bit 13 GPIOO_14 58 DIOPD General Purpose I O Port 0 bit 14 GPIOO_15 59 DIOPD General Purpose I O Port 0 bit 15 CVDD3 60 CPWR Core power supply connect to regulator CPWR DBG 61 DI Debug mode enable active high connect to ground TEST 62 DI Test mode input active high connect to ground PWRBTN 63 AIO Power button for Regulator startup and Power Key RTCVDD 64 RTCPWR Real time clock power supply XTALO_RTC 65 AO Real time clock crystal output XTALI_RTC 66 Al Real time clock crystal input Pin Name LFGA Pin Type Function Pin AUX0 LINE2_2 67 Al SAR AD input 0 Line 2 input 2 AUX1 LINE2_1 68 Al SAR AD input 1 Line 2 input 1 AUX2 LINE1_3 69 Al SAR AD input 2 Line 1 input 3 MIC2P AUX3 LINE3 2 70 Al Microphone 2 pos differential input self biasing SAR AD input 3 Line 3 input 2 MIC2N AUX4 LINE3_1 71 Al Microphone 2 neg differential input self biasing SAR AD input 4 Line 3 input 1 MIC1P LINE1 2 72 Al Microphone 1 pos
87. ch combined form the 20 bit register DAC_SRC Output sample rate is derived from the rollover frequency of a 20 bit interpolator accumulator Its accumulation rate is specified by ifreq Input sample rate f can be calculated from the equation fs XTALI 2 x DAC _SRC where DAC_SRC can have values from 1 to 1048575 OxFFFFF Value zero of ifreq places the DAC in idle mode In idle mode all logic is halted Also the analog clock is halted Note that the DAC clock is not controlled by the PLL The exact sample rate is xtal dependent and a sample rate of e g exactly 48 kHz requires that XTALI 12 288 MHz 24 bit samples are written to registers DAC_LEFT DAC_LEFT_LSB DAC_RIGHT and DAC_RIGHT_LSB after each DAC interrupt Configuring Analog DAC Modules Example values of analog configuration registers with 1 6 V reference are given in next table Analog Control Register example for DAC Operation Address Register Value Description OxFECB ANA_CF1 0x0048 DAC and output driver power down OxFED2 ANA_CF2 0x0018 Reference voltage select and reference power down Version 0 63 2014 12 19 54 ENO vst 005g Datasheet 11 7 2 Primary Audio Path Volume Control 11 VS1005G PERIPHERALS AND REGISTERS In VS1005g the DAC s volume level can be adjusted in 0 5dB steps DAC Volume Registers Reg Type Reset Abbrev Description OxFECO r w 0
88. commendations The following recommendations should be followed to ensure reliable operation e Analog power nets that are connected to regulator APWR CPWR output should have bypass capacitors e USBP and USBN traces should be kept within 2mm of each other and with preferred length of 20 30mm max 75mm A solid ground plane is preferred under USBP and USB N traces e USBP and USBN traces should be very close to same length drawn together and their characteristic differential impedance 90 Ohms e No vias are allowed in USBP or USBN traces only 45 degree angles should be used e USBP and USBN traces should be isolated from all other signal traces e RF_P and RF_N traces should be isolated from all other signal traces Version 0 63 2014 12 19 26 ENO vst 005g Datasheet 7 EXAMPLE SCHEMATIC 7 Example Schematic Default pin usage is shown in Figure 13 a z0 wg H STEREO D ZO zWwd lt LINE IN oa I ore Zz E Bu a2 zi DE aE s E Z nid ua L lt uz MiG x a TS 2 Ezg TOUCHPAD 2 gt 2a0 i Qa a zoa SAnm ais T az2 74a F E G A SZunnr gt ruMmMvVv gt U UZu ul gt lt Z nna UDD I UZEI oer C r a a XTALO f1 XTALI_RTC RTE XTALI f2 XTALO_RTC NVRAM AVDD 3 RTCVpp BATTERY VHIGH f4 PWRBTN CVDD 45 GND 1IOVDD 46 DBG IOVDD 47 CVDD3 XRESET 8 GPIO0 15 NFALE TP_XYS 3 0 0 ia lt lt a os 0 14 NFCLE TFT_RS TP_ENA D1 0 13 S PDIF_OUT DIGITAL ix 0 12 S PDIF_IN IN OUT as D2 a ro VS1005
89. count register When R S decoder fix algorithm has completed the number of location magnitude pairs is stored to this register RS_ST_DFFAIL register is set when the decoder algorithm could not fix all the errors in code word RS_ST_DFRDY2 RS_ST_DFBUSY and RS_ST_DFRDY1 are monitoring the status of R S Version 0 63 2014 12 19 79 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS decoder When both ready register are set the error correcting agorithm has completed and an interrupt request is generated RS_ST_DFAIL is set when a fatal error was encountered It is not possible to restore code word RS_ST_DFAIL is modified after code end was given RS_CF_DEND set by user RS_ST_DERR flag is set if code word has errors RS_ST_DERR is modified after code end was given RS_CF_DEND was set by user If this flag was set the error correcting algorithm is started automatically RS_ST_DOK flag is set if code word does not has errors RS_ST_DOK is modified after code end was given RS_CF_DEND was set by user RS_CF Bits Name Bits Description RS_CF_DNF 13 R S decoder nand flash mode select RS_CF_D10B 12 R S decoder 10 bit input data RS_CF_DEND 11 R S decoder code end RS_CF_DSTR 10 R S decoder code start RS_CF_DENA 9 R S decoder enable RS_CF_DMODE 8 R S decoder mode control RS_CF_SEL 3 0 7 4 R S encoder parity select for RS_OPORT RS_CF_ENF 3 R S encoder nand flash mo
90. de reserved 11 Set to 0 NF_PTR_PTR 10 0 10 0 Nand flash memory pointer NF_PTR 10 0 is the memory pointer register NF_PTR_RENA and NF_PTR_RCEF configure a ring buffer for slave mode In ring buffer mode only the lower address bits are modified and higher bits are locked E g when 512 word buffer size is used the ring buffer uses memory addresses 0 511 when NF_PTR 10 9 bits are 0b00 addresses 512 1023 when bits are 0b10 and so on Ring buffer configuration bits CF register Ring buffer size Locked bits Incremented bits 111 100 1024 words 10 9 0 011 512 words 10 9 8 0 010 256 words 10 8 7 0 001 128 words 10 7 6 0 000 64 words 10 6 5 0 Ring buffer mode generates interrupt in the mid and end addresses of the buffer NF_LEN defines the number of bytes that are read from or written to nand flash The length is given in bytes In read and write operations the data uses big endian format i e the MSB part is transmitted first Version 0 63 2014 12 19 83 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 11 4 SD Card Interface VS1005g has a SD card interface which supports 1 bit and 4 bit data bus SD Card Interface Registers Reg Type Reset Abbrev Description OxFC7C r w 0 SD_PTR SD card memory address pointer OxFC7D r w 0 SD_LEN SD card data length in bytes OxFC7E
91. de select RS_CF_ESTR 2 R S encoder code start RS_CF_EENA 1 R S encoder enable RS _CF_EMODE 0 R S encoder mode control RS_CF_DNF selects between two data input modes When set the decoder uses nand flash input data register as input When reset the data is fetched from peripheral memory RS_CF_D10B selects between 10 bit and 8 bit input modes Normally the symbols are 8 bit and two MSB zero bits are added When RS_CF_D10B is set the symbols are fetched from peripheral memory as 10 bit and the two MSB bits are not zeroed In 10 bit mode the data is in bits 9 0 and it is fetched from memory in word format This bit is set when NF parity check symbols are decoded When decoding the 10 bit check symbols the decoder does not generate RS decoder interrupt XP_ST_RSDEC_RDY RS_CF_DEND is a code end register for decoder When this register is set the decoder stops decoding current code word and the status can be read from RS_ST register If code word contained symbol errors the symbol error correction algorithm is started automatically The location and magnitude pairs needed to fix corrupted symbols are placed in memory from RS_DPTR address onwards The RS_DPTR value is not incremented during calculation and it holds the start address of the location magnitude pairs in memory The progress of the calculation is visible in RS_ST register When the location magnitude pairs are calculated an XP_ST_RSEC_RDY interrupt is generated RS_CF_
92. dec in VS1005g supports two different code lengths e NF n 1023 symbols and t 4 This makes 2 t 8 10 bit parity check symbols The data symbols are interpreted as 8 bit symbols where the two msb bits are always zero e RF n 255 symbols and t 16 This makes 2 t 32 8 bit parity check symbols Also the data symbols are 8 bits wide VS1005g Reed Solomon Codecs Codec Data Symbols k Symbol Width Check Symbols 2 t Typical Code Width n NF lt 1015 8 10 bits 8 10 bits 518 8 RF lt 223 8 bits 32 8 bits 223 32 The NF codec is used for multi level cell MLC flash error detection and correction Therefore the symbol width is limited to 8 bits for data symbols The R S encoder generates eight 10 bit parity check symbols 80 bits which are stored with 518 byte user data These check symbols are organized as 10 8 bit symbols which are stored to memory chip The code word would therefore be a total of 528 bytes long NF Reed Solomon encoder check symbols are outputed as five 16 bit words 80 bits total These check symbol words can be read from RS_DATA port when the RS encoder has finished calculation The check symbol organization is as listed in the table NF Reed Solomon Encoder Check Symbol Organization Check Symbol RS Encoder output word bits 0 word 0 1 0 amp word 0 15 8 1 word 1 11 8 amp word 0 7 2 2 word 1 5 0 amp word 1 15
93. defined in IEC 60268 11 1987 although commercial products feature a variety of connectors both electrical and optical Version 0 63 2014 12 19 96 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS The speed of the S PDIF transmitter depends on the sampling frequency of the audio signal Since S PDIF signal is often used to retrieve a clock signal at the receiving end S PDIF trans mitter must produce an exact frequency with a very low jitter Supported sampling frequencies are 32 kHz 48 kHz 96 kHz and 192kHz when master clock frequency is n x 12 288 MHz 44 1 kHz sampling frequency is supported 11 14 4 S PDIF Transmitter Registers S PDIF supports audio sample width of 16 to 24 bits The exact figure is conveyed to the receiver by channel status bits If the the transmitted sample word is less than 24 bits wide the remaining LSB s must be zero Channel status registers provide interface to the S PDIF standard implementation channel sta tus bits The S PDIF Transmitter inserts the corresponding bits to their proper places in the transfer frame Channel status data byte 23 for cyclic redundancy check character CRCC is not tested yet This document offers a terse description of the channel status bits Full coverage in IEC 60958 3 is mandatory Current implementation shares Channel Status Data bits registers CHSO and CHS1 for both channels S PDIF Transmitter Regist
94. differential input self biasing Line 1 input 2 MIC1N LINE1_1 73 Al Microphone 1 neg differential input self biasing Line 1 input 1 AVDDRF 74 APWR1V8 1 8V RF power supply connect to regulator CPWR RF_N 75 Al RF FM antenna negative differential input RF_P 76 Al RF FM antenna positive differential input AGND 77 APWR Analog reference ground connect to both GPLATE and RCAP capacitor without vias in PCB RCAP 78 AIO Filtering capacitance for reference AVDDO 79 APWR Analog power supply connect to regulator APWR RIGHT 80 AO Right channel output N A 81 N A Not connected pin CBUF 82 AO Common voltage buffer for headphones LEFT 83 AO Left channel output AVDD1 84 APWR Analog power supply connect to regulator APWR USBP 85 AlO USB differential in out controllable 1 5kQ pull up USBN 86 AIO USB differential in out GNDUSB 87 APWR USB ground connect to ground network in PCB and GPLATE PWM 88 DO PWM output Version 0 63 2014 12 19 25 NLS Pin type descriptions VS1005g Datasheet 6 PACKAGE AND PIN DESCRIPTIONS Type Description Type Description DI Digital input CMOS input pad Al Analog input DIPD Digital input with weak pull down re AO Analog output sistor approx 1 MQ AIO Analog input output DO Digital output CMOS output pad APWR Analog power supply pin or ground DIO Digital input output APWR1V8 Analog power supply pin 1 8V DIOPD Digital input output with w
95. do not control any logic Software Registers Address Type Reset Abbrev Description OxFC20 r w 0 SW_REGO 16 bit general purpose sw register OxFC21 r w O SW_REG1 16 bit general purpose sw register OxFC22 r w 0 SW_REG2 16 bit general purpose sw register OxFC23 r w 0 SW_REG83 16 bit general purpose sw register 11 5 2 Peripheral I O Control VS1005g has three general purpose I O ports Ports 0 and 1 are 16 bits and port 2 is 14 bits GPIO pins can be used either in GP mode or they can have also a special peripheral function GPIO or peripheral function can be defined for each pin separately GPIO Mode Registers Address Type Reset Abbrev Description OxFC30 rw 0 GPIOO_MODE Mode control for gpio port 0 OxFC31 rw 0 GPIO1_MODE Mode control for gpio port 1 OxFC32 rw 0 GPIO2_MODE Mode control for gpio port 2 GPIOO_MODE GPIO1_MODE and GPIO2_MODE registers are used to select current GPIO mode By default all VS1005g pins are at GPIO mode and all GPIOx_MODE register are reset If a peripheral mode is reguired the pin s GPIOx_MODE bit must be set 1 11 5 3 PLL Clock Control VS1005g has two clock domains the PLL clock domain and 12 MHz clock domain The PLL is controlled with one register Clock Control Register Address Type Reset Abbrev Description OxFC33 r w 0 CLK_CF PLL clock c
96. e Rates I2S CF_FS 1 0 16 bit mode 32 bit mode 11 48 kHz 24 kHz 10 192 kHz 96 kHz 01 96 kHz 48 kHz 00 48 kHz 24 kHz 12S _CF_MODE register selects between DSP mode 1 and SRC mode 0 In DSP mode the data is transferred from registers l2S_ LEFT l2S_ LEFT LSB 12S RIGHT and l2S_ RIGHT LSB In SRC mode which is the default data is sampled from DAC s SRC filter and 12S is operating in master mode only I2S_CF_TXURUN is the transmitter under run flag register It is set if left or right data buffer register was empty as it was copied to shifter register I2S_CF_TXLFULL and l2S_CF_TXRFULL registers are the transmitter data buffer full flags for left and right channel Flags are set when transmitter data buffer registers are modified The flags are reset as the left and right data buffer is copied to shifter register I2S_CF_RXORUN is the receiver over run flag It is set when receiver data buffers were full and new frame was received The flag is reset by writing it to 0 12S _CF_RXLFULL and 12S _CF_RXRFULL are the receiver data buffer full flags for left and right channel Flags are set when receiver data buffer registers are full The flags are reset as the left and right data buffer is read I2S_CF_INTENA enables the 12S interrupt when set l2S_CF_32B register selects between 32 bit 1 and 16 bit 0 data format This register can be modified only in idle state I2S_LEFT 12S LEFT LSB
97. e output clock is PLL s vco clock When reset the output clock is XTALI oscillator clock It should be noted that the vco must be locked when CLK_CF_CKSW is modified CLK_CF_USBCLK selects Hi Speed USB clock UTM insted of PLL vco clock This clock must be selected before CLK_CF_FORCEPLL is modified CLK_CF_MULT must have some value other than 0 when this clock mode is used Also the Hi Speed USB must be configured properly to output 60 MHz clock for core CLK_CF_VCOOUT enables the vco clock s output pad driver The pad must be in peripheral mode in order to output clock The output driver has glitch removal CLK_CF_LCKCHK and CLK_CF_LCKST are used to poll vco lock status When CLK_CF_LCKCHK is first set and reset the lock status can be read from CLK_CF_LCKST If CLK_CF_LCKST re mains set the PLL vco is locked CLK_CF_GDIV256 and CLK_CF_GDIV2 are the global clock dividers These divider divide also the 12 MHz clock domain clock PLL must be disabled when these dividers are used CLK_CF_RTCSLP enables RTC clocking mode CLK_CF_EXTOFF CLK_CF_NFOFF and CLK_CF_USBOFF control peripheral clock gates CLK_CF_NFOFF controls Nand flash SD card ethernet Reed Solomon codecs and peripeheral data buffer clocks CLK_CF_EXTOFF controls S PDIF peripheral clock CLK_CF_USBOFF controls USB peripheral clock Version 0 63 2014 12 19 48 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 6 XTALI Clock Domain Registers Peripheral c
98. e receiver Some equipment categories dictate the message see IEC 60958 3 SP_TX_CHST2_LS1_LV is the validity bit of the left channel sample word If the audio sample word is not a linear PCM this bit must be set SP_TX_CHST2_CH2_FSO defines the original sampling frequency of the audio stream 0000 means the original sampling frequency is not indicated default In SP_TX_CHST2_CH2_WRDL the sample word length is coded with respect to SP_TX_CHST2_CH2_WRDI 000 means the word length is not indicated SP_TX_CHST2_CH2_WRDLM indicates whether the maximum word length is 24 bits 1 or 20 bits 0 S PDIF TX Configuration SP_TX_CF Name Bits Description SP TX CF CLKDIV 15 2 Clock divider SP_TX_CF_IE 1 Interrupt enable SP_TX_CF_SND 0 Send words SP_TX_CF_CLKDIV contains a clock divider value that is used to generate S PDIF Transmit ter operating frequency The target is twice the bit rate Bit rate is sampling frequency of the transmitted signal multiplied by 64 For example 48 kHz audio signal requires bit rate of 3 072 MHz and consequent clock frequency for the peripheral is 6 144 MHz Default value for SP_TX_CF_CLKDIV is 4 resulting to Fs 48 kHz when master clock frequency is 24 576 MHz Zero is forbidden value S PDIF Transmitter frequencies Fs bit rate Fs x 64 Target frequency for clock divider 32 kHz 2 048 MHz 4 096 MHz 44 1 kHz 2 8224 MHz
99. e written The assembly language stub should call the C language handler routine VS1005g interrupt vectors continued Source Vector Address Device Read also INT_SAR 27 Ox3b 10 bit ADC SAR Chapter 11 20 INT_PWM 26 Ox8a Pulse width modulator Chapter 11 21 INT_REGU 25 0x39 Power button Chapter 11 6 1 INT_STX 23 0x37 S PDIF transmitter Chapter 11 14 3 INT_SRX 22 0x36 S PDIF receiver Chapter 11 14 14 INT_RDS 21 0x35 FM RDS Chapter 11 9 3 INT_RTC 20 0x34 RTC time alarm Chapter 11 19 INT_DAOSET 19 0x33 DAC offset Chapter 11 7 3 INT_SRC 18 0x32 DAC sample rate converter Chapter 11 7 4 INT_FM 17 0x31 FM interrupt 192 kHz Chapter 11 9 INT_TIMER2 16 0x30 Timer 2 Chapter 11 18 VS1005g interrupt vectors continued Source Vector Address Device Read also INT_TIMER1 15 Ox2f Timer 1 Chapter 11 18 INT_TIMERO 14 Ox2e Timer 0 Chapter 11 18 INT_UART_RX 13 Ox2d UART receive Chapter 11 15 INT_UART_TX 12 Ox2c UART transmit Chapter 11 15 INT_l2S 11 Ox2b 12S transmitter receiver Chapter 11 17 INT_MAC2 10 Ox2a A D 3 mono AD Chapter 11 8 INT_GPIO2 9 0x29 Gpio port 2 Chapter 11 13 INT_GPIO1 8 0x28 Gpio port 1 Chapter 11 13 INT_GPIOO 7 0x27 Gpio port 0 Chapter 11 13 INT_MACO 6 0x26 A D 1 2 stereo AD Chapter 11 8 INT_MAC1 5 0x25 FM decimation by 6 filter Chapter 11 8 INT_SPI1 4 0x24 SP
100. eak pull RTCPWR_ Real time clock power supply pin 1 8V down resistor in input approx 1 MQ CPWR Core power supply pin IOPWR I O power supply pin Package bottom plate is a ground net and it is connected to ground network in PCB NOTE Unused inputs should not be left floating Tie either HIGH or LOW as appropriate At power up all GPIO is three stated and current leakage from IOVDD is cut Outputs that are three statable should only be pulled high or low to ensure signals at power up and in standby Alternate pin functions in VS1005g package Pin Name LFGA Pin Type Function Pin Analog Line input 1 71 Al Alternate analog input pin for Line input 1 Analog Line input 2 70 Al Alternate analog input pin for Line input 2 Analog Line input 1 68 Al Alternate analog input pin for Line input 1 Analog Line input 2 67 Al Alternate analog input pin for Line input 2 Digital DA AD Clock 52 DO Digital DA AD clock output XTALI 2 4 Digital DAC Right 32 DO DAC right channel digital output XTALI 2 Digital DAC Left 33 DO DAC left channel digital output XTALI 2 DIA1 53 DIPD Digital ADC 1 input XTALI 2 DIA2 55 DIPD Digital ADC 2 input XTALI 2 DIA3 51 DIPD Digital ADC 3 input XTALI 2 TMS 31 DIPD Jtag Test Mode Select TDI 32 DIPD Jtag Test Data In TDO 33 DO Jtag Test Data Out TCK 34 DIPD Jtag Test Clock DBGREQ 35 DO Hardware debug state pin 6 4 1 PCB Layout Re
101. ed figures in Chapter 6 2 Packages Package thickness has changed from 0 9mm to 0 8mm Changed function descriptions for pins 67 68 and 70 73 in Chapter 6 4 VS1005g Pin Descriptions Version 0 63 2014 12 19 117 ENO vst 005g Datasheet 14 CONTACT INFORMATION 14 Contact Information VLSI Solution Oy Entrance G 2nd floor Hermiankatu 8 FI 33720 Tampere FINLAND URL http www visi fi Phone 358 50 462 3200 Commercial e mail sales visi fi For technical support or suggestions regarding this document please participate at http www vsdsp forum com For confidential technical discussions contact support vlsi fi Version 0 63 2014 12 19 118
102. er data register Version 0 63 2014 12 19 100 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS full indicator will be cleared A receive interrupt will be generated when a byte is moved from the receiver shift register to the receiver data register A write to UART_DATA sets a byte for transmission The data is taken from bits 7 0 other bits in the written value are ignored If the transmitter is idle the byte is immediately moved to the transmitter shift register a transmit interrupt request is generated and transmission is started If the transmitter is busy the UART_ST_TXFULL will be set and the byte remains in the transmitter data register until the previous byte has been sent and transmission can proceed UART_DATAH is the same register as the UART_DATA except that bits 15 8 are used UART_DIV register configures uart tansmission speed UART_DIV Bits Name Bits Description UART_DIV_D1 15 8 Divider 1 0 255 UART_DIV_D2 7 0 Divider 2 6 255 The divider is set to Ox0000 in reset The ROM boot code must initialize it correctly depending on the master clock frequency to get the correct bit speed The second divider D2 must be from 6 to 255 The communication speed f ESEIA where fm is XTALI and f is the TX RX speed in bps Version 0 63 2014 12 19 101 NLS VS1005g Datasheet 11 16 Watchdog Peripheral The watchdog consist of a watchdog counter and some l
103. ernet SPI slave receiver This receiver sets the flag when changes its state from idle to busy state Version 0 63 2014 12 19 76 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS ETH_RXPTR_ENA register places the ethernet receiver on hold for incoming packet when set When packet start is detected the receiver switches from idle to busy state Receiver address pointer must be configured before this register is set In SPI slave mode this register controls the SPI receiver enable When register is set the SPI transmit end automatically enables the SPI receiver ETH _RXPTR 10 0 is the ethernet SPI receiver memory pointer This pointer is loaded with packet start address before receiver is enabled When receiver changes it state from idle to busy this register is loaded to memory write address pointer register ETH_RBUF Bits Name Bits Description ETH RBUF_CLKCF 9 8 Reserved use 00 ETH _RBUF_TXENA 7 Ethernet transmitter ring buffer enable ETH _RBUF_TXCF 6 4 Ethernet transmitter ring buffer configuration ETH _RBUF_RXENA 3 Ethernet receiver ring buffer enable ETH _RBUF_RXCF 2 0 Ethernet receiver ring buffer configuration ETH_RBUF_TXENA and ETH_RBUF_RXENA are ring buffer enable registers for transmitters and receiver respectively Ring buffer size is defined with ETH_RBUF_TXCF and ETH_RBUF_RXCF registers as explained in table below Ring buffer co
104. ers Reg Type Reset Abbrev Description OxFDO02 Ww 0 SP_LDATA_LSB Left channel Audio sample bits 7 0 OxFDO3 w 0 SP_LDATA Left channel Audio sample bits 23 8 OxFD04 w 0 SP_RDATA_LSB Right channel Audio bits sample 7 0 OxFDO5 w 0 SP_RDATA Right channel Audio sample bits 23 8 OxFDO8 r w 0 SP_TX_CHSTO Channel Status 0 OxFDO9 r w 0 SP_TX_CHST1 Channel Status 1 OxFDOA r w 0 SP_TX_CHST2_ Channel Status 1 OxFDOB r w 0x40 SP_TX_CF Transmitter configuration SP_TX_LDATA SP_TX_LDATA_LSB SP_TX_RDATA and SP_TX_RDATA_LSB registers are transmitter data registers S PDIF data is 24 bits and it is divided in two registers 16 MSB bits are in registers SP_TX_LDATA and SP_TX_RDATA The remaining 8 LSB bits are in registers SP_TX_LDATA_LSB and SP_TX_RDATA_LSB Channel Status SP_TX_CHSTO Name Bits of data Bits of Chan Description word nel status SP_TX_CHSTO_CAT 15 8 15 8 Category Code SP_TX_CHSTO _MDO 7 6 7 6 PCM Mode 0 SP_TX_CHSTO_PCMM 5 3 5 3 Linear PCM Mode SP_TX_CHSTO_CP 2 2 Copyright SP_TX_CHSTO_PCM 1 1 Linear PCM SP_TX_CHSTO_PROCON 0 0 Professional Consumer mode SP_TX_CHSTO_CAT indicates to which category the device belongs Default value is 00000000 Version 0 63 2014 12 19 97 NLS 11 VS1005g Datasheet VS1005G PERIPHERALS AND REGISTERS The default value of SP_TX_CHSTO_MDO0 is 00 No other states are defined yet When SP_TX_
105. fly and are readable from the RS_DATA port after the current operation has finished RS_CF_EENA enables the R S encoder When RS_CF_ENF is set the encoder is encoding symbols as they are written to nand flash If RS_CF_ENF is reset the encoder starts reading symbols from peripheral memory from address RS_EPTR onwards The symbols are fetched from memory as 8 bit data but are forwarded to encoder as 10 bit symbols where bits 9 8 are always zero The big endian byte order is expected The encoder encodes RS_ELEN number of symbols and then reset RS_CF_EENA Also an XP_ST_RSENC_RDY interrupt request is generated RS_CF_EMODE register should be set when encoding nand flash data 10 bit When reset the 8 bit code is used RF RS_EPTR and RS_DPTR are the 11 bit address registers for Reed Solomon encoder and decoder The start address of data is written to these registers prior the encode or decode is enabled The big endian byte order is expected RS_ELEN and RS_DLEN are the code length registers for the encoder and decoder The length is given as the number of 8 bit symbols For decoder the symbols can also be 10 bit parity check symbols RS_DATA is a data read port for several data registers RS_OPORT Mux Control Bits XP_CF 15 12 register Mux input 1111 1100 Reserved 1011 R S decoder total errors data check symbols 5 bits 1010 0100 Reserved 0011 R S decoder CSF index 10 bits 0010 R S decoder BM index 9 bits 0001 R S
106. for the control endpoint 0 plus three input and output endpoints Bulk Isochronous and Interrupt transfer modes are supported at Full Speed 12 Mbit s The maximum packet size is 1023 bytes 4 kilobytes of Y data memory is used as the USB packet buffer 2 KiB for incoming packets X 0xF400 OxF7FF and 2 KiB for outgoing packets X 0xF800 OxFBFF The input buffer is a ring buffer with incoming packets consisting of a status word and n data words The output buffer has 16 possible start locations for outgoing packets at 128 byte 64 address intervals note that all data addressing in VS1005g is based on 16 bit words Version 0 63 2014 12 19 86 NLS VS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS gm A USB HS FS pair usbout HS_trev A Xe vad usb a hs rx ena FS pull up gt 15k usbin lt 1 gue m hs_rx bit I 2 ie iy hs tx ena gt opmode hs tx bit 2 p He a lt lt gt usbp linestate e hs tx bitx E lt __ tx valid p fs tx_ena HS TERM l gt usbn tx_ready lt _ lt _ _ FS trev fs_tx_bit fee rx valid lt lt 60MHz a eli rx active lt Hee rx_error lt _ lt Sa Eo a an a gt suspend gt na FS_ gt E Hebe bit xcvrselect gt usbn pit
107. gister defines the Timer X Startvalue The 32 bit start value TIMER_Tx L H sets the initial counter value when the timer is reset The timer interrupt frequency fi A where f is the master clock obtained with the clock divider and c is TIMER_Tx L H TIMER_TXCNT L H contains the current counter values By reading this register pair the user may get knowledge of how long it will take before the next timer interrupt Also by writing to this register a one shot different length timer interrupt delay may be realized Each timer has its own interrupt which is asserted when the timer counter underflows Version 0 63 2014 12 19 106 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 19 Real Time Clock RTC RTC is used for accurate time measurements and storing data when CPU is powered down The oscillator input clock frequency is 32768 Hz Real time clock is a 32 bit time keeping up counter which has a resolution of 1 second Additionally the 8 bit clock divider register value is accessible giving 1 128 seconds resolution Other functions of VS1005g RTC are time alarm and 32 word register memory for battery backup The RTC consists of two parts the Real Time Clock module and its dsp interfacing peripheral The RTC has its own power network which enables its use when the rest of the system is powered off The interface between these two is bit serial 11 19 1 RTC Peripheral Registers
108. he original sample rate SRC Characteristics Item Value Description XTALI Clock 11 0 MHz 13 0MHz_ Clock frequency DAC bit width 24 Input data width SRC bit width 24 Output data width DAC sample rate 0 Hz 96 kHz Input sample rate Output sample rate 1 0 97 xF Sin 192kHz Output sample rate Filter delay 7 19 input samples Gain 0 78 1 Assuming 12 288 MHz XTALI clock 2 In start up the SRC output is valid after 19 DAC interrupts SRC Registers Reg Type Reset Abbrev Description OxFEC6 r w 0 SRC_CF SRC sampler configuration register OxFEC7 r w 0 SRC_LEFT_LSB 15 12 SRC left sample bits 7 0 OxFED8 r w 0 SRC_LEFT SRC left sample bits 23 8 OxFED9 r w 0 SRC_RIGHT_LSB 15 12 SRC right sample bits 7 0 OxFEDA r w 0 SRC_RIGHT SRC right sample bits 23 8 SRC_CF Bits Name Bits Description SRC_CF_ORUN 15 SRC overrun flag SRC_CF_RFULL 14 Right data register full flag SRC_CF_LFULL 13 Left data register full flag SRC_CF_ENA 12 Enable for sample rate convertter SRC_CF_FS 11 0 SRC sample rate SRC_CF_ORUN is set if data register was full when data registers were modified SRC_CF_RFULL and SRC_CF_LFULL status registers for new samples Flags are set as SRC_LEFT and SRC_RIGHT are modified and reset as they are read SRC_CF_ENA enables sample rate converter when set SRC_
109. ied 12S CF_MODE in Chapter 11 17 1 2S Peripheral Registers Version 0 63 2014 12 19 116 ENO vst 005g Datasheet 13 DOCUMENT VERSION CHANGES Version 0 52 2012 11 07 Added new pin types DIPD and DIOPD replacing a part of DI and DIO pins in Chap ter 6 4 VS1005g Pin Descriptions Clarified documentation in Chapter 11 4 nterrupt Controller Renamed INT_ENABLEHO INT_ENABLELO INT_ENABLEH1 and INT_ENABLEL1 to INT_ENABLEO_HP INT_ENABLEO LP INT_ENABLE1_HP and INT_ENABLE1_LP in Chapter 11 4 1 Some register XP_ST bit names changed in Chapter 11 11 Common Data Interfaces Some ANA_CF1 register bits changed in Chapter 11 6 1 Analog Control Registers Version 0 51 2012 10 16 Added better instructions on how to connect the center ground plate GPLATE in Chap ter 6 4 VS1005g Pin Descriptions Corrected name for bit RS_DN_DNERR in Chapter 11 11 2 Reed Solomon Codec Version 0 50 2012 10 01 Added documentation regarding how to use ADC3 to Chapter 11 8 24 bit Analog to Digi tal Converters ADC including adding configuration bit AD_CF_AD23_FLP to Figure 18 Description for FM_CF register bit FM_CF_ENABLE changed in Chapter 11 8 2 Digital Filter Operation Modes Added new USB CF bits in Chapter 11 12 1 USB Peripheral Registers Added Chapter 2 Licenses Corrected descriptions for Nand flash register bits Chapter 11 11 3 Nand Flash Interface Typo corrections Versions 0 42 amp 0 41 2012 05 31 Updat
110. imensions are shown in Figures 9 10 and 11 For more information about the LFGA 88 package and its dimensions visit http www visi fi en support download htm Note that the pins do not extend to the sides of the IC see Figures 8 10 and 11 This revision of the package has been used in all VS1005gs with an older datecode than 1406 Do not use this package revision as a basis for PCB design For new designs use the current LFGA 88 package presented in Chapter 6 1 as a basis for PCB design It will be compatible with this package and it will work better with the current package Figure 8 VS1005g old LFGA 88 VS1205G F product variant top and bottom view photo Version 0 63 2014 12 19 20 ENS vst 005g Datasheet 6 PACKAGE AND PIN DESCRIPTIONS TOP VIEW 10 000 0 075 E B OLD FOOTPRINT DO NOT USE FOR NEW DESIGNS 10 000 0 075 D l a eae een ees ae l l l PIN 1 LASER ma Figure 9 VS1005g top view old LFGA 88 Version 0 63 2014 12 19 21 BOTTOM VIEW 45 46 47 48 49 50 51 52 53 54 a 56 57 58 59 60 61 62 64 D 7 L 2 OLD FOOTPRINT a 3 DO NOT USE FOR re NEW DESIGNS P S G AM ZA Z Y Ges T A s o A e Ws Z A mS GZ Y Y WI MMV MVVLVYVVYVYY 1 20 19 18 17 16 15 12 11 C 14 13 12 200 0 050 NLS 6 3 Pin Assignments 86 USBN 87 GND_USB 85l USBP A FA XTALO XTALI AVDD VHIGH CVDD
111. ing ICs with the older LFGA 88 package Chapter 6 2 For an example of PCB design see http www visi fi en support evaluationboards vs 1005developerboard htm PELE e e a GEGGEGHGGRERRREREHHEES Figure 1 VS1005g LFGA 88 VS1205G F product variant top and bottom view photo Figure 3 VS1005g LFGA 88 VS1205G F product variant bottom corner view photo Version 0 63 2014 12 19 17 ENO vst 005g Datasheet 6 PACKAGE AND PIN DESCRIPTIONS TOP VIEW paemani 10 000 0 075 E gt al i S O 5 t 4 8 oO O Q i 1 1 i _PIN 1 LASER oe en Figure 4 VS1005g top view LFGA 88 __ _ 0 700 TYP l MOLD CAP Land Detail Figure 5 VS1005g corner view LFGA 88 Version 0 63 2014 12 19 18 OVRI VS1005g Datasheet B BOTTOM_VIEW oO H 1 8 as S a Z _ NVVE wy wy 400 WY PALA QAR Q LOR LL LO Of A A P A AA YY A A A A vA A A A A HATCH AREA a e SOLDER MASK od g 2 150 cIAlB 18 m THIC ane daug l _ 1 0 10 iC MIN 40 u INCH THICKNESS ENO vst 005g Datasheet 6 PACKAGE AND PIN DESCRIPTIONS 6 2 LFGA 88 Package Old VS1005g upto Datecode 1406 LFGA 88 is a 10x10x0 8mm lead Pb free and RoHS compliant package RoHS is a short name of Directive 2002 95 EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment Package and pin d
112. is a poll bit for channel status change interrupt SP_RX_STAT_FRCV is set by the peripheral when a frame is received and cleared when SP_RX_LDATA is read SP_RX_STAT_MISS bit is set if SP_RX_STAT_FRCV is set and new samples are written to SP_RX_LDATA and SP_RX_RDATA The time to read the samples is a few clock cycles less than the sampling period SP_RX_STAT_BERR is set if the period between Z preambles is not equal to 192 frames SP_RX_STAT_FERR is set if Y preamble does not follow X preamble or Z preamble SP_RX_STAT_SFERR is set if the previous subframe has not been equal to 32 time slots Version 0 63 2014 12 19 95 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS SP_BIPHERR is set if biphase coding of the S PDIF channel is compromised SP_RX_STAT_RPERR and SP_RX_STAT_LPERR are set if the parity count is failed in the respective subframe SP_RX_STAT_MISS SP_RX_STAT_BERR SP_RX_STAT_FERR SP_RX_STAT_SFERR SP_BIPHERR SP_RX_STAT_RPERR and SP_RX_STAT_LPERR are sticky bits i e if set they keep their state until cleared by sw SP_RX_STAT_RV and SP_RX_STAT_LV are validity bits for right channel and left channel restectively When validity bit is 0 sample word is a valid PCM sample SP_RX_STAT_RU and SP_RX_STAT_LU are user data bits User data bits should be used as specified in IEC 60958 3 SP_RX_STAT_RC and SP_RX_STAT_LC are channel status bits According to the S PDIF standard both channels should
113. isn t disturbed when keys are pressed SD Card Interface The SD card interface automates some of the communication with an SD card Peripheral supports 1 bit and 4 bit data transfers The SD card interface pins can also be used as general purpose 1 O Version 0 63 2014 12 19 31 ENO vst 005g Datasheet 8 VS1005G GENERAL DESCRIPTION Ethernet Controller Ethernet Controller is an interface to 10base t network The interface uses digital signal levels and external components are required to connect to ethernet The core clock must be switched to 60 MHz when ethernet peripheral is used The ethernet interface pins can also be used as general purpose O USB The USB peripheral handles USB 2 0 Full Speed and Hi Speed harware protocols Low speed communication is not supported but is correctly ignored The USBP pin has a software controllable 1 5kQ pull up A control endpoint 1 IN and 1 OUT and upto 6 other endpoints 3 IN and 3 OUT can be used simultaneously Bulk interrupt and isochronous transfer modes are selectable for each endpoint USB receive from USB host to device OUT uses a 2 KiB buffer thus allowing very high transfer speeds USB transmit from device to USB host IN also uses a 2 KiB buffer and allows all IN endpoints to be ready to transmit simultaneously Double buffering is also possible but not usually required The firmware uses the USB peripheral to implement both USB Mass Storage Device and USB Audio
114. its from baseband signal to form bit groups When a full block is decoded the 16 bit data and 10 bit checkword are stored to registers and an RDS interrupt is generated RDS data structure is shown in Figure 20 RDS data rate is 1187 5 bits per second 104 bits Block1 Checkword a 16 bits gt lt 10 bits Figure 20 Structure of the RDS baseband coding group Version 0 63 2014 12 19 66 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS RDS module s control bits are in register FM_CF RDS Control Bits in Register FM_CF address 0xFE40 Name Bit Index Description FM_CF_RDSSYNC 5 FM RDS forced to keep current bit synchronization FM_CF_RDSENA 2 FMRDS enable FM Control and Data Registers Reg Type Reset Abbrev Description OxFE52 r 0 RDS_DATA 15 0 FM RDS data register OxFE53 r 0 RDS_CHK 12 0 FM RDS checkwork and block status RDS_DATA and RDS_CHK registers store the last decoded RDS block RDS module finds automatically bit and block synhronization but it does not do any data correction if crc errors exist This must be done by software RDS_CHK Register Bits Reg Bit index Name Description RDS_CHK_CHKW 12 3 CHECKWORD Checkword of the last received block data RDS_CHK_ST 2 STATUS Validity of the last received block RDS_CHK_BLK 1 0 BLOCK Index of the last received block 0 3
115. ize and extend the functionality of the player For software customization the firmware supports nand flash and SD card boot The VS1005gxF version can use also the internal serial flash as a boot device UART An asynchronous serial port is used for debugging and special applications The default speed is 115200 bps RX and TX pins can also be used for general purpose I O when the UART is not required SPls A synchronous serial port peripheral is used for SPIEEPROM boot and can be used to access other SPI peripherals for example LCD or SED by using another chip select The SPIO is only used for boot if the XCSO pin has a high level after reset pull up resistor attached These pins can also be used for general purpose I O when the SPI is not required The default player uses MISOO and MOSIO for LED outputs NAND FLASH Interface The NAND FLASH peripheral calculates a simple error correcting code ECC and automates some of the communication with a NAND FLASH chip The firmware uses the peripheral to access both small page 512 16B pages and large page 2048 64B pages NAND FLASH chips The first sector in the FLASH tells the firmware how it should be accessed The NAND FLASH interface pins can also be used as general purpose I O The default firmware uses GPIOO_ 4 0 for keys and GPIOO_ 7 6 for other purposes Pull up and pull down resis tors must be used for these connections so that the data transfer to and from the NAND FLASH
116. l and status registers are e Enable register SENA e 16 bit event count register ECNT e 16 bit instruction address register BADDR SENA register enables the snooper module when set The register is reset when breakpoint interrupt is triggered and all snooper logic is halted ECNT register is a decrementing counter which is decremented by one at each breakpoint event When register is zero and a break point event occurs a breakpoint interrupt is generated BADDR register stores the instruction address when the breakpoint interrupt is generated Each breakpoint has three configuration registers e Configuration register e Address register e Data register Breakpoint configuration register is used to set up a breakpoint Breakpoint Configuration Register Bits Name Register Bit Description Status 7 Breakpoint triggered flag Bus Type 6 5 X Y I bus selection Access Type 4 3 Fetch Read Write access type selection Condition Type 2 0 Breakpoint condition selection Breakpoint status bit is set when the breakpoint triggeres an interrupt Breakpoint Bus Type Bit Configuration Value Bus Description 00 Breakpoint at l bus oT X Breakpoint at X bus 10 Y Breakpoint at Y bus a Illegal Don t use Version 0 63 2014 12 19 114 ENS vst 005g Datasheet 12 VS1005G DEBUGGER Breakp
117. ller Interrupt requests in XP_ST are modified regardless of the value of XP_ST_INT_ENA The SPI slave error register XP_ST_SPIERR_INT is a read only register which is reset when SPI start is detected in the SPI bus and set if data transfer was interrupted in the middle of a byte Version 0 63 2014 12 19 74 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 11 1 Ethernet Controller VS1005g has a controller for interfacing 10base t ethernet bus Additionally this peripheral can be configured to SPI slave mode to be used with VLSI Solution s RF link In this mode the SPI1 pins are used and they must be configured to peripheral mode with GPIO1_ MODE 7 4 registers ETH_TXLEN_META register enables the use of higher bit rate If the SPI slave and master are using same clock source this register can be set The SPI slave synchronization is then made simpler It is recommended to keep this register in reset In ethernet mode this register is don t care ETH_TXLEN_RX_BE and ETH_TXLEN_TX_BE are used to reverse bit order in SPI mode When registers are reset the bits are sent received Isb bit first i e from 0 to 7 When registers are set the bits are sent received msb bit first i e from 7 to 0 In ethernet mode these registers are don t care ETH_TXLEN 11 0 register is loaded with packet length in bytes before the transmitter is en
118. ltage to this pin is RTCVDD 1 95 V Failing to follow this limita tion may break VS1005Q s internal digital circuitry 3 Maximum allowed external voltage to this pin is CVDD 1 95 V Failing to follow this limitation may break VS1005q s internal digital circuitry Other pin values than mentioned in the table are not allowed Version 0 63 2014 12 19 110 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 21 Pulse Width Modulation Unit VS1005g has a PWM output which can be programmed to generate any pulse width within 256 XTALI clock periods PWM Registers Reg Type Reset Abbrev Description OxFED4 r w 0 PWM_FRAME_LEN 7 0 PWM frame length 2 255 clock cycles OxFED5 r w 0 PWM_PULSE_LEN 7 0 PWM pulse width 0 255 clock cycles PWM_FRAME_LEN 7 0 defines the pwm frame length Values 0 and 1 are not allowed and they place the unit in powerdown output is zero With frame values gt 1 the pwm output is enabled with rising edge at start of frame and falling edge at PWM_PULSE_LEN 7 0 If PWM_PULSE_LEN is zero the output is always zero If PWM_PULSE_LEN gt PWM_FRAME_LEN the output is always at logic high state PWM unit generates interrupt request at the start of each frame In VS1005g power up as the PWRBRTN pin is high the pwm output generates an oscillation for external powering circuitry The oscillation reguires that there is an external pull up resistor
119. m 3 Definitions B Byte 8 bits b Bit Ki Kibi 2 17024 IEC 60027 2 Mi Mebi 2 1 048 576 IEC 60027 2 Gi Gibi 230 1 073 741 824 IEC 60027 2 VS _ DSP VLSI Solution s DSP core VSOS VLSI Solution s Operating System W Word In VS_DSFP instruction words are 32 bit and data words are 16 bit wide 4 Product Variants Device ID Order Code MP3 Encoder MP3 Decoder Embedded 8 Mi bit Flash VS1005G Q X VS1005G F Q X X VS1205G Q X X VS1205G F Q X X X VS8005G Q VS8005G F Q X Version 0 63 2014 12 19 8 ENO vst 005g Datasheet 5 CHARACTERISTICS amp SPECIFICATIONS 5 Characteristics amp Specifications 5 1 Absolute Maximum Ratings Parameter Symbol Min Max Unit Regulator input voltage VHIGH 0 3 5 25 V Analog Positive Supply AVDD 0 3 3 6 V Digital Positive Supply CVDD 0 3 1 95 V Digital RTC Supply RTCVDD 0 3 1 95 V I O Positive Supply IOVDD 0 3 3 6 V Voltage at Any Digital Input 0 3 IOVDD 0 3 V Voltage at power Button PWRBTN 0 3 3 6 V Voltage at RTC Pins XTALI_RTC XTALO_RTC 0 3 CVDD 0 34 V Total Injected Current on Pins 200 mA Operating Temperature 40 85 C Storage Temperature 65 150 C 1 Must not exceed 3 6 V 2 Latch up limit 3 Except RTC and PWRBTN pin 4 Must not exceed 1 95 V Version 0 63 2014 12 19 9 ENS vst 005g Datasheet
120. nfiguration bits Name CF register Ring buf size Locked bits Incremented bits ETH RBUF_TXCF_1024W 111 100 1024 words 10 9 0 ETH RBUF_TXCF_512W 011 512 words 10 9 8 0 ETH RBUF_ TXCF_256W 010 256 words 10 8 7 0 ETH RBUF_TXCF_128W 001 128 words 10 7 6 0 ETH RBUF_TXCF 64W 000 64 words 10 6 5 0 1 For the corresponding RX configuration register use name ETH _RBUF_RXCF_xxxW in stead where xxx is the ring buffer size ETH_RXADDR register is the current memory address were receiver stores data This register is loaded with ETH_RXPTR 10 0 when new packet start is detected in bus Ethernet controller generates an interrupt each time a new packet is received or transmitter has finished sending a packet When ring buffers are used the interrupt is given also when ring buffer address pointer has reached middle or end of the configured buffer size Version 0 63 2014 12 19 77 NLS 11 11 2 Reed Solomon Codec VS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS VS1005g has a Reed Solomon encoder and decoder for error correction e g from nand flash data Reed Solomon is a forward error correction code which adds redundancy at the end of the message The code word length n is defined as k 2 t where k is the maximum number of data symbols pay load and 2 t is the number of parity check symbols The algorithm can fix up to t symbols from code word and detect 2 t errors The Reed Solomon co
121. ng range 1 7 3 6 IV Voltage setting step size 55 60 65 mV Default setting reset mode 1 1 8 V Default setting active mode 1 8 3 6 V Load regulation 4 0 mV mA Line regulation from VHIGH 2 0 mvV V Continuous current 304 60 mA CVDD Recommended voltage setting range 1 65 1 95 V Voltage setting step size 25 30 35 mV Default setting reset mode 1 1 8 V Default setting active mode 1 8 V Continuous current 254 70 mA Load regulation 2 0 mV mA Line regulation from VHIGH 2 0 mV V AVDD Recommended voltage setting range 2 6 3 6 IV Voltage setting step size 35 40 45 mV Default setting reset mode 1 2 5 V Default setting active mode 2 7 V Continuous current 307 70 mA Load regulation 1 5 mV mA Line regulation from VHIGH 2 0 mvV V PWRBTN Minimum startup voltage 0 9 V Minimum startup pulse 100 ms 1 Device enters reset mode when XRESET pin is pulled low 2 Device enters active mode when XRESET pin is pulled high after reset mode Regulator settings can be modified when booted from external memory see Section 10 3 Depends on GPIOO_7 pin status in boot see Section 10 4 Device is tested with a 30 mA load Version 0 63 2014 12 19 13 ENO vst 005g Datasheet 5 CHARACTERISTICS amp SPECIFICATIONS 5 8 Analog Characteristics of VHIGH voltage monitor Parameter Symbol Min Typ Max Unit Trigger voltage AMON 1 07xAVDD V Hysteresis 50 mV 5 9 Analog Characteristics of C
122. nverter is filterless the user has to take care to select sample rates in such a way that doesn t introduce audible aliasing Aliasing does not occur if the sample rate for the output GRC_LEFT and SRC_RIGHT is never lower than the sample rate for the input DAC_LEFT and DAC_RIGHT but in special cases even lower Downconverter sample rates may result in audio that is good enough for the application Not directly connected to any other part of the playback audio path is the S PDIF signal path This signal path does not interact with the other ones and it is only included in the figure to show all available playback audio paths Version 0 63 2014 12 19 53 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 7 1 Primary Audio Path 24 bit Sample Rate Upconverter with Filters DAC Registers VS1005g has a 24 bit DAC with a programmable sample rate Sample rates up to 96 KHz are supported DAC Interface Registers Address Type Reset Abbrev Description OxFC34 r w 0 DAC_SRCL DAC sample rate bits 15 0 OxFC35 r w 0 DAC_SRCH 3 0 DAC sample rate bits 19 16 OxFC36 r w 0 DAC_LEFT_LSB 15 8 DAC left sample bits 7 0 OxFC37 r w 0 DAC_LEFT DAC left sample bits 23 8 OxFC38 r w 0 DAC_RIGHT_LSB 15 8 DAC right sample bits 7 0 OxFC39 r w 0 DAC_RIGHT DAC right sample bits 23 8 The DAC interpolator frequency is defined with registers DAC_SRCH and DAC_SRCL whi
123. ogic After reset the watchdog is inac tive The counter reload value can be set by writing to WODOG_CF The watchdog is activated by writing 0x4ea9 to register WODOG_KEY Every time this is done the watchdog counter is reset Every 65536 th clock cycle the counter is decremented by one If the counter underflows it will 11 VS1005G PERIPHERALS AND REGISTERS activate vsdsp s internal reset sequence Thus after the first Ox4ea9 write to WOOG_KEY subsequent writes to the same register with the same value must be made no less than every 65536x WDOG_CF clock cycles Once started the watchdog cannot be turned off Also a write to WDOG_CF doesn t change the counter reload value After watchdog has been activated any read write operation from to WDOG_CF or WDOOG_DUMMY will invalidate the next write operation to WDOG_KEY This will prevent runaway loops from re setting the counter even if they do happen to write the correct number Writing an incorrect value to WDOG_KEY will also invalidate the next write to WDOG_KEY Reads from watchdog registers return undefined values 11 16 1 Watchdog Registers Watchdog Registers Reg Type Reset Abbrev Description OxFE20 w 0 WDOG_CF Configuration OxFE21 Ww 0 WDOG_KEY Clock configuration OxFE22 w 0 WDOG_DUMMY Dummy register Version 0 63 2014 12 19 102 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 17
124. oint Access Type Bit Configuration Value Register Bit Description 00 Disabled Breakpoint is disabled 01 Fetch Read Breakpoint set to snoop read accesses 10 Write Breakpoint set to snoop write accesses 41 Read or Write Breakpoint set to snoop both the read and write accesses Breakpoint Condition Type Bit Configuration Value Bus Description 000 Disabled Breakpoint disabled 001 Any Match only address 010 X Y bus data EQUAL to snoop breakpoint data 011 X Y bus data NOT EQUAL to snoop breakpoint data 100 lt signed Signed comparison of X Y bus data LESS THAN snoop breakpoint data 101 gt signed Signed comparison of X Y bus data GREATER THAN OR EQUAL to snoop breakpoint data 110 Illegal Don t use 11t Illegal Don t use The hardware debugger requires the VLSI JTAG connector and Integrated Development Envi ronment VSIDE for full debug capabilities For further information about the hardware debugger connect VLSI technical support Version 0 63 2014 12 19 115 ENO vst 005g Datasheet 13 DOCUMENT VERSION CHANGES 13 Document Version Changes This chapter describes the latest and most important changes to this document Version 0 63 2014 12 19 e Updated telephone number in Chapter 14 Contact Information Version 0 62 2014 11 04 e Further cleared up that the current VS1005g package should be used for all new designs in Chapter 6 1 LFGA 88 Package Current VS1005g
125. olomon decoder To enable the interrupts the XP_ST_INT_ENA must be set Reed Solomon interrupts in XP_ST Register Name Bits Description XP_ST_INT_ENA 14 Interrupt enable active high XP_ST_RSEC_RDY 8 Reed Solomon decode error correction ready XP_ST_RSDEC_RDY 7 Reed Solomon decode ready XP_ST_RSENC_RDY 6 Reed Solomon encode ready Reed Solomon Registers Reg Type Reset Abbrev Description OxFC70 r 0 RS_ST Reed Solomon status for encoder and decoder OxFC71 r w 0 RS_CF Reed Solomon control and configuration register OxFC72_ r w 0 RS_EPTR Reed Solomon encoder memory pointer OxFC73 r w 0 RS_ELEN Reed Solomon encoder data length in bytes OxFC74 r w 0 RS_DPTR Reed Solomon decoder memory pointer OxFC75 r w 0 RS_DLEN Reed Solomon decoder data length OxFC76 r 0 RS_DATA Data read port RS_ST Bits Name Bits Description RS_ST_DNERR 12 8 Number of errors in decoded code word RS_ST_DFFAIL 6 Decoder fix algorithm found too many errors RS_ST_DFRDY2 5 Decoder fix algorithm completed RS_ST_DFBUSY 4 Decoder fix algorithm is calculating magni tude and location pairs RS_ST_DFRDY1 3 Decoder fix algorithm part 1 completed RS_ST_DFAIL 2 Code word errors can not be fixed RS_ST_DERR 1 Code word has errors RS_ST_DOK 0 Code word does not contain errors RS_ST_DNERR is the error
126. on OxFE80 r w 0 TIMER_CF 7 0 Timer configuration OxFE81 r w 0 TIMER_ENA 2 0 Timer enable OxFE84 r w 0 TIMER_TOL TimerO startvalue LSBs OxFE85 r w 0 TIMER_TOH TimerO startvalue MSBs OxFE86 r w 0 TIMER_TOCNTL TimerO counter LSBs OxFE87 r w 0 TIMER_TOCNTH TimerO counter MSBs OxFE88 r w 0 TIMER_TiL Timer1 startvalue LSBs OxFE89 r w 0 TIMER_T1H Timer1 startvalue MSBs OxFE8A r w 0 TIMER_T1CNTL Timer1 counter LSBs OxFE8B r w 0 TIMER_T1CNTH Timer1 counter MSBs OxFE8C r w 0 TIMER_T2L Timer2 startvalue LSBs OxFE8D r w 0 TIMER_T2H Timer2 startvalue MSBs OxFE8E r w 0 TIMER_T2CNTL Timer2 counter LSBs OxFE8F r w 0 TIMER_T2CNTH Timer2 counter MSBs TIMER_CF Bits Name Bits Description TIMER_CF_CLKDIV 7 0 Master clock divider TIMER_CF_CLKDIV is the master clock divider for all timer clocks The generated internal clock frequency fi in where fm is the master clock frequency and cis TIMER_CF_CLKDIV Example With a 12 MHz master clock TIMER _CF_DIV 3 divides the master clock by 4 and h 12MHz y the output sampling clock would thus be f lt 47 3M Hz TIMER_ENA Bits Name Bits Description TIMER_ENA_T2 2 Enable timer 2 TIMER_ENA_T1 1 Enable timer 1 TIMER_ENA_TO 0 Enable timer 0 Version 0 63 2014 12 19 105 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS TIMER_Tx L H re
127. ontrol register Version 0 63 2014 12 19 47 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS CLK_CF Bits Name Bits type Description CLK_CF_EXTOFF 15 r w S PDIF peripheral clock gate control CLK_CF_NFOFF 14 r w NF SD and R S peripherals clock gate control CLK_CF_USBOFF 13 r w USB peripheral clock gate control CLK_CF_RTCSLP 12 r w _ RTC power down mode enable CLK_CF_LCKST 11 r w PLL vco lock status CLK_CF_GDIV256 10 r w Global Clock 256 divider enable CLK_CF_GDIV2 9 r w Global clock 2 divider enable CLK_CF_LCKCHK r w_ PLL vco lock check initialization CLK_CF_VCOOUT r w_ Enable PLL clock output pad driver CLK_CF_USBCLK r w_ Hi Speed usb clock mode control 8 7 6 CLK_CF_FORCEPLL 5 r w PLL clock switch control 4 0 CLK_CF_DIVI r w_ PLL input clock divider control CLK_CF_MULT 3 r w_ PLL clock multiplier factor CLK_CF_MULT determines the clock multiplier for input clock Multiplier is value 1 i e value 1 means clock is multiplied by 2 Value 0 disables the PLL CLK_CF_DIVI controls the input divider of PLLs vco If CLK_CF_DIVI is set the vco input clock is divided by two If CLK_CF_DIVI is reset the vco input clock is the XTALI oscillator clock When divider is used the CLK_CF_MULT can be programmed with values 1 15 CLK_CF_FORCEPLL register controls the output clock switch When set th
128. ontrol registers control the logic that is clocked with the XTALI clock 12 288 MHz 11 6 1 Analog Control Registers Analog Control Registers Reg Type Reset Abbrev Description OxFECC r w 0 ANA_CFO Analog Control register 0 OxFECB r w 0 ANA_CF1 Analog Control register 1 OxFED2 r w 0 ANA_CF2 Analog Control register 2 OxFED3 r w 0 ANA_CF8 Analog Control register 3 ANA_CF0O Bits Name Bits Description 15 11 Reserved use 00000 ANA_CFO_M1LIN 10 Line input mode select for ADC 1 ANA_CFO_M2LIN 9 Line input mode select for ADC 2 8 6 Reserved use 000 ANA_CFO_M2MIC 5 Mic input mode select for ADC 2 ANA_CFO_LCKST 4 2 GHz vco lock status ANA_CFO_LCKCHK 3 2 GHz vco lock check init ANA_CFO_M1MIC 2 Mic input mode select for ADC 1 1 0 ANA_CFO_M2FM FM input mode select for ADC 2 ANA_CFO_M1FM FM input mode select for ADC 1 ANA_CFO_LCKCHK and ANA_CFO_LCKST are used to poll 2 GHz vco lock status When ANA_CFO_LCKCHK is first set and reset the lock status can be read from ANA_CFO_LCKST If ANA_CFO_LCKST remains set the 2 GHz VCO is locked For details on how to program register bits ANA_CFO_M 1 2 LIN ANA_CFO_M 1 2 MIC and ANA_CFO_M 1 2 FM see Chapter 11 8 1 on Page 59 Version 0 63 2014 12 19 49 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS AN
129. ord MSB Validity bit User Channel data bit status bit bit b ie 3 4 7 8 27 28 29 30 31 Preamble Auxiliary 20 bit audio sample word MSB Validity Channel sample bits bit data bit status bit Figure 25 S PDIF sub frame format Version 0 63 2014 12 19 93 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS 11 14 2 S PDIF Receiver Registers The base address for S PDIF Receiver interface registers is Y 0xFDOO S PDIF Receiver Registers Address Type Reset Abbrev Description OxFDOO r w Ox1FFO SP_RX_CF S PDif control and status register OxFDO1 r w 0 SP_RX_CLKDIV S PDif receiver clock divider register OxFD02 r 0 SP_LDATA_LSB S PDif input left input channel bits 8 0 OxFDO3 r 0 SP_LDATA S PDif left input channel bits 23 8 OxFD04 r 0 SP_RDATA_LSB S PDif left input channel bits 8 0 OxFDO5 r 0 SP_RDATA S PDif right input channel bits 23 8 OxFDO6 r w 0 SP_RX_STAT S PDif status register OxFDO7 r 0 SP_RX_BLFRCNT S PDif frame status register SP_RX_CF Bits Name Bits Description SP_RX_CF_EN 3 S PDIF enable SP_RX_CF_INT_ENA 1 Interrupt enable SP_RX_CF_EN Enables S PDIF Receiver peripheral If disabled i e 0 most of the peripheral is resetted and synchronisation to S PDIF stream is lost and must be re acquired after enabling SP_RX_CF_INT_ENA when set enables S P
130. output load capacitance AOLC 100 pF DC level V 1 2 V CBUF LEFT RIGHT 1 1 1 3 V DC level V 1 6 V CBUF LEFT RIGHT 1 5 17 V CBUF disconnect current short circuit protection 130 200 mA 1 Loaded from Left Right pin to analog ground via 100 F capacitors 2 AOLR may be lower than Typical but distortion performance may be compromised Also there is a maximum current that the internal regulators can provide 3 CBUF must have external 109 47nF load LEFT and RIGHT must have external 20 10 nF load for optimum stability and ESD tolerance Version 0 63 2014 12 19 11 ENO vst 005g Datasheet 5 CHARACTERISTICS amp SPECIFICATIONS 5 4 Analog Characteristics of Audio Inputs ADC Characteristics Parameter Symbol Min Typ Max Unit ADC Resolution 24 bits Microphone input amplifier gain MICG 20 dB Microphone input amplitude 50 1401 mVpp AC Microphone Total Harmonic Distortion MTHD 0 02 0 10 Microphone S N Ratio A weighted MSNR 50 75 dB Line input amplitude 2200 2800 mVpp AC Line input Total Harmonic Distortion LTHD 0 015 0 10 Line input S N Ratio LSNR_ 80 90 100 dB Sample rate 24 192 kHz Line and Microphone input impedances 100 kQ 1 Above typical amplitude the Harmonic Distortion increases 2 Limit Min due to noise level of production tester 5 5 SAR Characteristics
131. pped in Y addresses 0xFC40 SPIO and OxFC50 SP11 SPI Registers Prefix SPIx_ SPIO address SPI1 address Type Reset Abbrev Description OxFC40 OxFC50 r w O CF 11 0 Configuration OxFC41 OxFC51 r w 0 CLKCF 9 0 Clock configuration OxFC42 OxFC52 r w 0 STATUS 7 0 Status OxFC43 OxFC53 r w 0 DATA Sent received data OxFC44 OxFC54 r w 0 FSYNC SSI Sync data in master mode OxFC45 OxFC55 r w 0 DEFAULT Data to send slave if SPIx_ST_TXFULL 0 Version 0 63 2014 12 19 68 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS Main Configuration SPIx_CF Bits Name Bits Description SPI_CF_EARLYINT 12 T interrupt when SPI_ST_TXFULL clear TX mode 0 interrupt when no transfer ready RX mode SPI _CF_SRESET 11 SPI software reset SPI_CF_RXFIFOMODE 10 1 interrupt only when FIFO register full or CS deasserted with receive register full 0 interrupt always when a word is received SPI_CF_RXFIFO_ENA 9 Receive FIFO enable SPI_CF_TXFIFO_ENA 8 Transmit FIFO enable SPI_CF_XCSMODE 7 6 xCS mode in slave mode SPI _CF_MASTER 5 Master mode SPI_CF_DLEN 4 1 Data length in bits SPI_CF_FSIDLE 0 Frame sync idle state SPI_CF_EARLYINT selects whether the SPI interrupt happens immediately when the SPI de vice is capable of taking new data 1 useful for when transmi
132. pt enable register GPIOx_INT_FALL is set to 1 a falling edge in the cor responding pin even when configured as output will set the corresponding bit in the interrupt pending source register GPIOx_INT_PEND If a bit of the rising edge interrupt enable register GPIOx_INT_RISE is set to 1 a rising edge in the corresponding pin even when configured as output will set the corresponding bit in the interrupt pending source register GPIOx_INT_PEND GPIOx_INT_PEND defines the source of a pending interrupt If any of the bits in the interrupt pending source register GPIOx_INT_PEND are set an interrupt request is generated Bits in GPIOx_INT_PEND can be cleared by writing a 1 bit to the bit that is to be cleared Note the interrupt request will remain asserted until all GPIOx_INT_PEND bits are cleared GPIOx_SET_MASK register can be used to mask GPIO pins high when GPIOx_ODATA register is written All bits that are set in the mask register also set the corresponding bit in the data output register Other bits retain their old values Version 0 63 2014 12 19 91 ENS vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS GPIOx_CLEAR_MASK register can be used to mask GPIO pins low when GPIOx_ODATA reg ister is written All bits that are set in the mask clear the corresponding bit in the data output register Other bits retain their old values GPIOx_BIT_CONMF is a bit engine configuration register and selects a mapping between an
133. quest when set NF_CF_WAITSTATES configures the length of nand flash read enable and write enable pulses The cycle time is 2 x NF_CONF_WS 1 dsp clock cycles NF_CTRL Bits Name Bits Description NF_CTRL_RDY 4 Status of nand flash ready line reserved 3 Set to 0 NF_CTRL_READSEL 2 Read 1 or write 0 select NF_CTRL_ENA 1 Start nand flash read or write NF_CTRL_USEPERIP 0 Use peripheral memory NF_CTRL_RDY register is monitoring the current state of nand flash ready busy line The line has pull up and when it is in its low state the flash chip is busy NF_CTRL_READSEL is a read or write select When this register is set the operation is a nand flash read When reset the nand flash interface writes to flash NF_CTRL_ENA starts nand flash read or write when set When all bytes are transfered this register is reset and an interrupt request is generated NF_CTRL_USEPERIP configures nand flash interface to use peripheral memory when set If NF_CTRL_USEPERIP is reset when nand flash interface is enabled the data is read from Version 0 63 2014 12 19 82 NLS VS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS XP_IDATA register or written to XP_ODATA register This is a one byte transaction and big endian format is used NF_PTR Bits Name Bits Description NF_PTR_RENA 15 Ring buffer enable for slave mode NF_PTR_RCF 14 12 Ring buffer configuration for slave mo
134. state the peripheral is in ethernet mode ETH _RXLEN_SPIINVCLK selects SPI slave transmitter clock edge When register is reset the SPI out data is written after falling SPI clock edge When register is set the data is written after rise edge With high SPI bit rates SPI clock gt core clock 6 the rise edge should be used It should be noted that the SPI slave clock can not exceed core clock 4 at any time In ethernet mode this register is don t care ETH_RXLEN_LEN 11 0 register is loaded with ethernet SPI receiver packet length counter when receiver returns from busy state to idle packet end Packet length is given in bytes ETH_RXPTR Bits Name Bits Description ETH _RXPTR_CRCOK 15 Ethernet receiver crc status flag ETH_RXPTR_NEWPKT 14 Ethernet receiver packet received flag ETH _RXPTR_BUSY 13 Ethernet receiver busy ETH _RXPTR_ENA 12 Ethernet receiver enable ETH_RXPTR_PTR 10 0 10 0 Ethernet receiver memory address pointer ETH_RXPTR_CRCOK is the received packet crc status flag Receiver sets the flag if the received packet crc was correct Flag must be reset by user write 1 In SPI slave mode the crc flag is set if last four bytes were OxFF ETH_RXPTR_NEWPKT is the flag for incoming packet The receiver sets the flag when it changes its state from busy to idle Flag must be reset by user write 1 In spi mode this register is zero ETH_RXPTR_BUSY is a busy flag for eth
135. t USB_UTMIW_TERMSEL 2 Termination select USB_UTMIW_OPMOD 1 0 Operation mode USB_HOST Bits Name Bits Description USB _HOST_PID 15 12 USB host packet id USB _HOST_ISOC 11 Disable NAK packet send USB_HOST_TX 9 USB host send packet USB_EP_SENDn Bits Name Bits Description USB_EP_SEND_TXR 15 Packet ready for transmission USB_EP_SEND ADDR 13 10 Starting location of packet USB_EP_SEND_LEN 9 0 Length of packet in bytes 0 1023 Version 0 63 2014 12 19 89 NLS When the DSP has written a packet into the transmit buffer that is ready to be transmitted to the PC by an endpoint the DSP signals the USB firmware by setting the value of the USB_EP_SENDn register of the endpoint that should transmit the packet USB_EP_SENDO VS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS for endpoint 0 USB_EP_SEND1 for endpoint 1 etc USB_EP_StTn Bits Name Bits Description EPnOUT PC Device endpoint 0 3 flags USB_EP_ST_OTYP 15 14 00 bulk 01 interrupt 11 isochronous USB_EP_ST_OENA 13 1 enabled O disabled USB_EP_ST_OSTL 12 Force STALL USB_EP_ST_OSTL_SENT 11 Atleast 1 STALL sent reserved 10 8 Use 0 EPnIN Device PC endpoint 0 3 flags USB_EP_ST_ITYP 7 6 00 bulk 01 interrupt 11 isochronous USB_EP_ST_INT_ENA 5 1 enabled 0 disabled USB_EP_ST_ISTL Force STAL
136. t dbgmode 61 JTAG debug mode enable Debug functions are controlled with JTAG DR data and IR instruction registers which can be written and read in predefined JTAG states JTAG state machine is shown in Figure 28 1 Test Logic Reset 4 0 d 1 1 1 0 Run test Idle gt Select DR Scan _ Select IR Scan A 0 0 1 1 Capture DR Capture IR 0 0 v v gt Shift DR 0 gt Shift IR 0 1 1 Vv p Exit1 DR 1 L p Exit1 IR 1 0 0 v v Pause DR 0 Pause IR 0 1 1 0 T 0 A Exit2 DR Exit2 IR 1 1 Vv v Update DR lt Update IR 0 0 _y y v v Figure 28 JTAG state machine TAP function is selected by writing a special 4 bit instruction to IR register Additionally to debug functions some common JTAG functions are supported Version 0 63 2014 12 19 113 ENS vst 005g Datasheet 12 VS1005G DEBUGGER VS1005g JTAG instruction codes Instruction IR register Description BYPASS 0000 Places jtag to bypass mode In bypass mode there is one clock cycle delay between tdi and tdo IDCODE 1111 Places jtag s 32 bit ID code register between tdi and tdo The snooper module supports up to 8 breakpoints which can be programmed to trigger at data address events Snooper s contro
137. te kbit s 8 16 24 32 40 48 56 64 80 96 112 128 144 160 12000 t f Jr ft ft f 11025 ft l f fe ft ft f 8000 1 All variable bitrate VBR formats are also supported Version 0 63 2014 12 19 38 ENO vst 005g Datasheet 10 FIRMWARE OPERATION 10 6 Supported Audio Encoders VS1005g ROM firmware supports encoding MP3 files only VS1205 Support for other file formats is implemented as link libraries 10 6 1 Supported MP3 MPEG layer Ill Encoder Formats VS1005g supports all MP3 samplerates and bitrates in stereo and mono both with constant bitrate CBR or variable bitrate VBR The following tables apply to constant bitrate Conventions Symbol Description Format is supported and recommended for this channel configuration and bitrate Format is supported Format is supported but use is strongly discouraged for quality reasons Format is supported but for best quality lower samplerate with same bitrate is recommended Format is supported but lower bitrate will give same quality Format exists but isn t supported Format doesn t exist tL Al lt x MPEG 1 0 layer III MP3 full rates stereo Samplerate Hz Bitrate kbit s stereo 32 40 48 56 64 80 96 112 128 160 192 224 256 320 48000 v v v v v v
138. ted in slave mode and the transmit data register has not been loaded with new data to shift out This bit has to be cleared manually Note Because TX and RX status bits are implemented as separate entities it is relatively easy to make asynchronous software implementations which do not have to wait for an SPI cycle to finish SPIx_DATA SPI_CF_DLEN 0 may be written to whenever SPI_ST_TXFULL is clear In master mode writing will initiate an SPI transaction cycle of SPI_CF_DLEN 1 bits In slave mode data is output as soon as suitable external clocks are offered Writing to SPI_DATA sets SPI_ST_TXFULL which will again be cleared when the data word was put to the shift reg ister If SPILST_TXRUNNING was clear when SPI_DATA was written to data can immediately be transferred to the shift register and SPI_ST_TXFULL won t be set at all When SPI_ST_RXFULL is set SPI_DATA may be read Bits SPI_CF_DLEN 0 contain the received data The rest of the 16 register bits are set to 0 SPIx_FSYNC is meant for generation of potentially complex synchronization signals including several SSI variants as well as a simple enough automatic chip select signal SPIx_FSYNC is only valid in master mode If a write to SPIx_DATA is preceded by a write to SPIx_FSYNC the data written to SPIx_FSYNC is sent to FSYNC pin with the same synchronization as the data written to SPIx_DATA is written to MOSI When SPL_ST_TXRUNNING is clear the value of SPI_CF_FSIDLE is set to FS
139. termselect gt bo 3 515k T host_rpd_ena gt 480MHz 60MHz Figure 23 VS1005g UTM functional block diagram 11 12 1 USB Peripheral Registers Universal Serial Bus Controller Registers Address Register Function OxFC80 USB_CF USB Device Config OxFC81 USB_CTRL USB Device Control OxFC82 USB_ST USB Device Status OxFC83 USB_RDPTR 9 0 Receive buffer read pointer OxFC84 USB_WRPTR 9 0 Receive buffer write pointer OxFC85 USB _UTMIR UTM read control OxFC86 USB_UTMIW UTM write control OxFC87 USB_ HOST Host control OxFC88 USB_EP_SENDO EPOIN Transmittable Packet Info OxFC89 USB_EP_SEND1 EP1IN Transmittable Packet Info OxFC8A USB_EP_SEND2 EP2IN Transmittable Packet Info OxFC8B USB _EP_SEND3 EP3IN Transmittable Packet Info OxFC90 USB _EP_STO Flags for endpoints EPOIN and EROOUT OxFC91 USB_EP_ST1 Flags for endpoints EP1IN and EP1OUT OxFC92 USB_EP_ST2 Flags for endpoints EP2IN and EP2OUT OxFC93 USB _EP_ST3 Flags for endpoints EP3IN and EP30UT Version 0 63 2014 12 19 87 NLS VS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS USB_CF Bits Name Bits Description USB_CF_RST 15 Reset Active USB_CF_HDTOG 14 Reset value of host data toggle set to 0 USB_CF_DDTOG 13 Reset value of device data toggle set to 0 12 Reserved use 0 USB_CF_NOHIGHSPEED 11 Set to disable high speed functionality USB_CF_DTOGERR 10 Data Toggle error control set to 0
140. ters monitor mode and communi cates with vs3emu Memory contents can be displayed executables can be loaded and run or the firmware code can be restarted or continued The UART is also a convenient way to program the NAND FLASH boot sector s or the SPI EEPROM Version 0 63 2014 12 19 36 ENO vst 005g Datasheet 10 FIRMWARE OPERATION 10 4 Default Firmware Features 10 4 1 SD Card Test If an SD card is connected to VS1005g the firmware searches for a boot file file called VS1005G SYS If found VS1005g executes the code in that file If VS1005G SYS is not found the firmware tries to open the file TEST MP3 If successful that file is played back Note Playback is provided only as a functional test Playback quality is not indicative of VS1005g default playback quality Note MP3 playback is not supported by VS8005g 10 4 2 USB Mass Storage and Audio Device If no SD card boot or test file was found the firmware goes into USB detection mode When USB cable insertion is detected by the firmware USB handling code is started The internal clock is configured to 48 MHz assuming XTALI 12 288 MHz the analog power is configured to 3 6 V the USB peripheral is initialized and the USB pull up resistor is enabled If GPIOO_6 has a pull up resistor VS1005g appears as an USB Audio Device The audio device contains a HID interface which allows for code to be loaded to VS1005g with a custom program If GPIOO_6 has a pull down resis
141. to external circuits FM_CF Bits for Digital Filters see Chapter 11 9 2 for other bits Name Bits Description FM_CF_UAD2 14 External input enable for stereo AD right channel FM_CF_UAD1 13 External input enable for stereo AD left channel FM_CF_UAD3 12 External input enable for mono AD FM_CF_ENABLE 6 Software reset for AD and FM demodulator The AD configuration register has bits to enable filters and to select sample rates When the filter is enabled also the interrupt request is generated and forwarded to the interrupt controller The decimation filter is included to decimate the demodulated FM signals downto 32 kHz sam ple rate but its input can be selected from other sources also The filter s input bit width is 18 bits AD_CF Bits Name Bits Description AD_CF_AD23_FLP 9 Flip AD2 and ADS inputs AD_CF_DEC6SEL 1 0 8 7 Input selection for FM filter decimation by 6 AD_CF_AD3FS 1 0 6 5 Sample rate selection for AD filter 3 mono AD AD_CF_ADFS 1 0 4 3 Sample rate selection for AD filters 1 and 2 stereo AD AD_CF_DEC6ENA 2 FM decimation by 6 filter enable AD_CF_AD3ENA 1 AD filter 3 enable mono AD line input 3 AD_CF_ADENA 0 AD filter 1 and 2 enable stereo AD line input 1 and 2 AD_CF_AD23_FLP register flips the input of filters 2 and 3 The FM decimation filter is used when FM is enabled and it decimates the FM signals to 32 kH
142. tor VS1005g appears as an USB Mass Storage Device If during power on the NAND FLASH contained a valid boot sector the NAND FLASH disk will be used with the mass storage device The NAND FLASH disk requires a filesystem level formatting before it can be used Version 0 63 2014 12 19 37 ENO vst 005g Datasheet 10 FIRMWARE OPERATION 10 5 Supported Audio Decoders VS1005g ROM firmware supports decoding MP3 files only VS1005 and VS1205 Support for other file formats is implemented as link libraries Conventions Mark Description Format is supported Format exists but is not supported Format doesn t exist 10 5 1 Supported MP3 MPEG layer III Decoder Formats The decoder supports all MP3 samplerates and bitrates MPEG 1 0 Samplerate Hz Bitrate kbit s 32 40 48 56 64 80 96 112 128 160 192 224 256 320 48000 I t t ft ft 44100 t f 32000 Jt s MPEG 2 0 Samplerate Hz Bitrate kbit s 8 16 24 32 40 48 56 64 80 96 112 128 144 160 24000 I J Jt fe ft 22050 16000 MPEG 2 5 Samplerate Hz Bitra
143. tting data or only when the SPI transfer has been fully completed 0 useful when mostly receiving data SPI_CF_XCSMODE selects xCS mode for slave operation 00 is interrupted xCS mode 10 is falling edge xCS mode and 11 is rising edge xCS mode SPI_CF_MASTER sets master mode If not set slave mode is used SPI_CF_DLEN 1 is the length of SPI data in bits Example For 8 bit data transfers set SPI_CF_DLEN to 7 SPI_CF_FSIDLE contains the state of FSYNC when SPI_ST_TXRUNNING is clear This bit is only valid in master mode Clock Configuration SPIx_CLKCF Bits Name Bits Description SPIL_CC_CLKDIV 9 2 Clock divider SPIL_CC_INV_CLKPOL 1 Inverse clock polarity selection SPI_CC_INV_CLKPHASE 0 Inverse clock phase selection In master mode SPI_CC_CLKDIV is the clock divider for the SPI block The generated SCLK frequency f Peery where fm is the master clock frequency and c is SPI_CC_CLKDIV Example With a 12 MHz master clock SPI_CC_CLKDIV 3 divides the master clock by 4 and the output sampling clock would thus be f aera 1 5 MHz SPI_CC_INV_CLKPOL reverses the clock polarity If SPI_CC_INV_CLKPOL is clear the data is read at rise edge and written at fall edge if SPI_CC_INV_CLKPHASE is clear When SPI_CC_INV_CLKPHASE is set the data is written at rise edge and read at fall edge SPI_CC_INV_CLKPHASE defines the data clock phase If clear the first data is written
144. tween the peripherals with the DSP having absolute highest priority Because of this some idle cycles are required during long DSP read write operations As a guideline at least every 16th read cycle should be left idle by the DSP The DSP interface has Error Correction Code ECC registers for nand flash It uses 2D xor to protect and correct data Version 0 63 2014 12 19 72 NLS VS1005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS DSP Interface Registers for Peripheral Memory Reg Type Reset Abbrev Description OxFC66 r 0 ECC_LP_LOW ECC line parity register bits 15 0 OxFC67 r 0 ECC_CP_LP_HIGH ECC column parity bits 5 0 and line parity bits 17 16 OxFC68 r w 0 XP_CF Dsp interface control OxFC69 r w 0 XP_ADDR Memory address register for dsp interface 11 bits OxFC6A r w 0 XP_ODATA Memory write port for dsp OxFC6B r 0 XP_IDATA Memory read port for dsp OxFC6C r w 0 XP_ST Interrupt status register for data buffer peripherals ECC_LP_LOW and ECC_CP_LP_HIGH are the error correction code data registers They are modified when DSPI_ODATA or DSPI_IDATA ports are accessed The DSPI_CF_ECCENA must be set in order to use ECC XP_CF Bits Name Bits Description XP_CF_ODAT 15 12 RS_ODATA mux control XP_CF_ECC_RST 9 ECC reset XP_CF_ECC_ENA 8 ECC enable XP_CF_WRBUF_ENA 1 Data buffer write enable XP_CF_RDBUF_ENA 0 Data buffer re
145. urces and controls the system s internal reset signals Reset Sources are e POR Power On reset and CVDD voltage monitor e XRESET External active low reset pin wdog_rst Watchdog timer reset dbg_rst Debugger reset e PWRBTN Power Button reset after 5 seconds Two clock sources can be used e 11 MHz 13 MHz oscillator recommended 12 288 MHz e 32kHz RTC oscillator Version 0 63 2014 12 19 33 ENO vst 005g Datasheet 10 FIRMWARE OPERATION 10 Firmware Operation The firmware uses the following pins see the example schematics in Section 7 Pin Description PWRBTN High level starts regulator is also read as the Power button Key GPIOO_0 external 1 MQ pull down resistor Key 1 connects a 100 kQ pull up resistor GPIO0_1 external 1 MQ pull down resistor Key 2 connects a 100 kQ pull up resistor GPIOO_2 external 1 MQ pull down resistor Key 3 connects a 100 kQ pull up resistor GPIOO_3 external 1 MQ pull down resistor Key 4 connects a 100 kQ pull up resistor GPIOO_4 external 1 MQ pull down resistor Key 5 connects a 100 kQ pull up resistor GPIO0_6 external pull down resistor for USB Mass Storage Device pull up for USB Audio Device GPIO0_7 external pull down resistor for 1 8 V I O voltage pull up resistor for 3 3 V I O voltage NFCE external pull up resistor for normal operation XCS external pull up to enable SP EEPROM boot USBN external 1 MQ pull up USBP
146. x47FF and 0x0200 or 0x47FF and not 0x440F and 0x3DFF 0x4000 or 0x0200 or 0x01F0 0x43F0 Interrupt sources are listed in the table below XP_ST Bits Name Bits Description XP_ST_INT_ENA 14 Interrupt enable for data buffer peripherals XP_ST_ETXRB_HALF2_INT 13 Ethernet transmit ring buffer second half empty XP_ST_ETXRB_HALF1_INTf 12 Ethernet transmit ring buffer first half empty XP_ST_ERXRB_HALF2_INTf 11 Ethernet receive ring buffer second half full XP_ST_ERXRB_HALF1_INT 10 Ethernet receive ring buffer first half full H XP_ST_SPIERR_INT 9 SPI slave error transfer was interrupted mid dle of byte XP_ST_RSEC_RDY_INT 8 Reed Solomon decode error correction data ready XP_ST_RSDEC_RDY_INT 7 Reed Solomon decode ready XP_ST_RSENC_RDY_INT 6 Reed Solomon encode ready XP_ST_SD_INT 5 SD card interface ready interrupt XP_ST_NF_INT 4 Nand flash interface ready interrupt XP_ST_SPI_STOP_INT 3 SPI slave stop interrupt chip select to inactive state XP_ST_SPI_START_INT 2 SPI slave start interrupt chip select to active state XP_ST_ETHRX_INT 1 Ethernet receiver new packet interrupt XP_ST_ETHTX_INT 0 Ethernet transmitter ready interrupt 1 A write with the bit set will clear the bit 2 Read only bit XP_ST_INT_ENA is the peripheral interrupt enable When set the interrupt requests are for warded to the interrupt contro
147. y keeping PWRBTN pressed for longer than approx imately 5 6 seconds This feature can be disabled by software A watchdog counter and the XRESET pin can also generate a reset for the device Resets do not cause the regulators to shut down but they restore the default regulator voltages After boot the firmware and user software can change the voltages Return to power off is possible only with active software control VSDSP writes the regulator shutdown bits or when VHIGH voltage is removed for a sufficiently long time In the default firmware player the power button has to be pressed for 2 seconds to make the software power down the system and turn the regulators off 8 1 2 I O Section IOVDD is used for the level shifters of the digital I O and crystal oscillator The regulated IO voltage is internally connected The IOVDD regulator output must be connected to IOVDD1 IOVDD2 and IOVDD3 input pins Proper bypass capacitors should also be used The firmware uses GPIOO_7 to select I O voltage level After reset the I O voltage is 1 8 V If GPIOO_7 has a pull down resistor 1 8 V I O voltage is used If GPIOO_7 has a pull up resistor 3 3 V I O voltage is used 8 1 3 Digital Section All digital logic except the real time clock is powered from core voltage CVDD The regulated core voltage is internally connected The CVDD regulator output must be connected to CVDD1 CVDD2 and CVDD3 input pins CVDD pins should have proper bypass capacitors
148. z However the filter can also be used with other inputs Register AD_CF_DEC6SEL is used to select the filter input Decimation filter input selection Name AD_CF_DEC6SEL Filter input AD_CF_DEC6SEL_MONO 11 or 10 mono AD left right AD_CF_DEC6SEL_STEREO 01 stereo ADs AD_CF_DEC6SEL_FM 00 FM demodulator Version 0 63 2014 12 19 61 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTERS Sample rate selection for AD filters 1 and 2 stereo AD Name AD_CF_ADFS Decimation factor Sample rate AD_CF_ADFS_24K 11 256 24 kHz AD_CF_ADFS_48K 10 128 48 kHz AD_CF_ADFS_96K 01 64 96 kHz AD_CF_ADFS_192K 00 32 192 kHz 1 The filter input is XTALI 2 or nominally 6 144 MHz 2 Sample rate when XTALI 12 288 MHz Sample rate selection for AD filters 3 mono AD Name AD_CF_AD3FS Decimation factor Sample rate AD_CF_AD3FS_24K 11 256 24 kHz AD_CF_AD3FS_48K 10 128 48 kHz AD_CF_AD3FS_96K 01 64 96 kHz AD_CF_AD3FS_192K 00 32 192 kHz 1 The filter input is XTALI 2 or nominally 6 144 MHz 2 Sample rate when XTALI 12 288 MHz AD_LEFT AD_LEFT_LSB AD_RIGHT AD_RIGHT_LSB AD_ MONO and AD_MONO LSB are the output data registers of the three AD filters As a new data sample is calculated also an interrupt request is generated Version 0 63 2014 12 19 62 ENO vst 005g Datasheet 11 VS1005G PERIPHERALS AND REGISTER
149. z 44 1 kHz 2 8224 MHz 11 2896 MHz 48 kHz 3 072 MHz 12 288 MHz 96 kHz 6 144 MHz 24 576 MHz 192 kHz 12 288 MHz 49 152 MHz Divider Master clock bit rate Divider gt 3 even number SP_RX_LDATA SP_RX_LDATA_LSB SP_RX_RDATA and SP_RX_RDATA_LSB registers are received data registers S PDIF data is 24 bits and it is divided in two registers 16 MSB bits are in registers SP_RX_LDATA and SP_RX_RDATA The remaining 8 LSB bits are in registers SP_RX_LDATA_LSB and SP_RX_RDATA_LSB SP_RX_STAT Bits Name Bits type Description SP_RX_STAT_CHSCH 15 r w Channel Status Change SP_RX_STAT_FRCV 14 r Frame receive N A 13 always zero SP_RX_STAT_MISS 12 r w Missed reading previous frame SP_RX_STAT_ BERR 11 r w Block error Z preamble every 192 frames failure SP_RX_STAT_FERR 10 r w Frame error Y preamble after X or Z failure SP_RX_STAT_SFERR 9 rw Subframe error subframe 28 bits SP_RX_STAT_BIPHERR 8 r w Biphase coding error SP_RX_STAT_RPERR 7 r w Parity error right channel SP_RX_STAT_LPERR 6 r w Parity error left channel SP_RX_STAT_RV 5 r Validity bit right channel SP_RX_STAT_RU 4 r User data bit right channel SP_RX_STAT_RC 3 r Channel status bit right channel SP_RX_STAT_LV 2 r Validity bit left channel SP_RX_STAT_LU 1 r User data bit left channel SP_RX_STAT_LC 0 r Channel status bit left channel SP_RX_STAT_CHSCH

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