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Datasheet - Renesas Electronics

1. Data Port latch Data bus gt _ Port latch Key on wakeup CCE Key input control interrupt input 3 Port P40 4 Port P41 Pull up control P41 TxD P channel output disable bit 2 Serial l O1 enable bit Transmit enable bit Direction Direction Hj gister Y register Y Data bus Port latch gt Databus 4 Port latch Serial I O enable bit _ Pull up control 1 Receive enable bit D 4 21 T Serial input Serial output 5 Port P42 6 Port P43 Serial 1 01 synchronous clock Serial 1 01 mode selection bit Pull up control selection bit E Pulkup control Serial 1 01 enable bit Ly Serial 1 enable bit SRDY1 output enable bit Serial 1 01 mode selection bit Serial 1 01 enable bit Direction register Direction register Data bus 1 Port latch Databus Port latch
2. Serial 1 01 ready output gt Serial 1 01 clock output EI Serial 1 01 clock Fig 14 Port block diagram 1 Rev 3 04 20 2008 22 01134 stENESAS REJ03B0158 0304 3805 7 44 8 Port P45 Pull up control F P45 SOUT2 P channel output disable bit up control Serial 2 transmit end signal Serial 1 02 synchronous clock selection bit Serial 1 02 port selection bit 4 Direction register gt Direction Lt register D4 Data bus gt _ Port latch Data Port latch 91 lt Serial 1 02 input 1 Serial 1 02 input Key on wakeup interrupt input x Key input control Key on wakeup interrupt input 4 Key input control 9 Port 4 10 Port P47 up contro Serial 1 02 synchronous clock selection bit 1 up control Serial 1 02 port selection output selection bit Direction Direction r register register Data bus Port latch Data bus T
3. 0 5 mm pitch plastic molded LQFP Memory Size lt QzROM version gt ROM iin 32 K to 60 K bytes RAM 1536 to 2048 bytes lt Flash memory version gt 60 bytes 2048 bytes Memory Expansion Plan ROM size 60K bytes 1 1 1 1 1 1 1 1 zl 56K 48K 4 MS38D59GC M38D58G8 P ede eo ie i ed ee de dh E eS 192 256 384 640 768 896 RAM size bytes Fig 5 Memory expansion plan Currently supported products are listed below Table 5 Support products As of Apr 2008 ROM size bytes RAM size ROM size for User in bytes M38D58G8 XXXFP 32768 32638 1536 PRQPO080GB A QzROM version M38D58G8 XXXHP PLQPO080KB A M38D58G8FP 32768 32638 1536 PRQPO080GB A QzROM version blank M38D58G8HP PLQPOO080KB A M38D59GC XXXFP 49152 49022 2048 PRQPO080GB A QzROM version M38D59GC XXXHP PLQPOO080KB A M38D59GCFP 49152 49022 2048 PRQPOO080GB A QzROM version blank M38D59GCHP PLQPOO80KB A M38D59GF XXXFP 61440 61310 2048 PRQPO080GB A QzROM version M38D59GF XXXHP PLQPOO80KB A M38D59GFFP 61440 61310 2048 PRQPO080GB A QzROM version blank M38D59GFHP PLQPOO080KB A M38D59FFFP 61440 61310
4. Serial 1 02 register write signal Serial 2 output SOUT2 Serial 1 02 input SIN2 Reception enable signal SRDY2 When the internal clock is selected 1 1 1 1 1 7 I T 1 Serial 2 interrupt request bit set Notes 1 When the internal clock is selected as the transfer the dividing frequency of internal clock for transfer clock can be selected by bits 0 to 2 of serial 1 2 control register 2 When the internal clock is selected as the synchronous clock the SOUT2 pin is placed in the high impedance state after transfer is completed 3 When the external clock is selected as the synchronous clock the SOUT2 pin retains the D7 output level after transfer is completed However if the synchronous clock is continuously input the serial 2 register continues shifting and the SOUT2 pin keeps outputting transmit data Fig 40 Serial 2 timing Rev 3 04 REJ03B0158 0304 20 2008 Page 490f 134 FLRENESAS 3805 A D CONVERTER The 3805 Group has a 10 bit A D converter The A D converter performs successive approximation conversion The 38D5 Group has the ADKEY function which perform A D conversion of the L level analog input from the ADKEY pin automatically AD Conversion Register ADL ADH One of these registers is a high order register and the other is a low order register
5. VPP RESET Connect oscillation circuit indicates flash memory Package type 0080 80P6N A Fig 80 Connection for standard serial I O mode 1 Rev 3 04 20 2008 88 01134 RENESAS REJ03B0158 0304 3805 Flash memory version P22 SEG2 KWe KW7 0 1 2 3 59 4 P23 SEG3 58 574 poossEGs 56 P26 SEG6 5514 gt P27 SEG7 544 gt poosEGs 531 P01 SEG9 52 4 po2 SEG 5114 gt pos SEG 50 lt gt 04 4914 pos SEG 4814 posisEG 60 lt gt 44 42 lt p 41 p P21 SEG1 KWs gt P20 SEGo KW4 P47 SRDY2 KW3 P46 SCLK2 KW2 P45 SouT2 KW1 DES ye P44 SIN2 KWO BUSY P43 SRDY1 lt gt L INPUT P42 Sciki gt P41 TXD RXBL PayRxp M38D59FFHP AVss VREF P57 AN7 ADKEYo 51 1 14 gt P5o ANo RTPo gt e 4 1 lt gt 2 lt gt 3 lt gt 4 lt gt 5 LEDs P60 XCIN lt gt 10 P61 Xcour
6. P50 ANoO P51 AN1O P52 AN2O P53 AN3O P54 AN4O 55 5 P56 AN6O P57 AN7 ADKEYo O Comparator Channel selector A D control circuit Channel Selector The channel selector selects one of the input ports P57 AN7 5 and inputs it to the comparator Comparator and Control Circuit The comparator and control circuit compare an analog input voltage with the comparison voltage and store the result in the AD conversion register When an A D conversion is completed the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to 1 The comparator is constructed linked to a capacitor The conversion accuracy may be low because the change is lost if the conversion speed is not enough Accordingly set f XIN to at least 500 kHz during A D conversion in the XIN mode Also do not execute the STP and WIT instructions during the A D conversion In the low speed mode and on chip oscillator mode there is no limit on the oscillation frequency because the on chip oscillator is used as the A D conversion clock In the low speed mode on chip oscillator starts oscillation automatically at the A D conversion is executed and stops oscillation automatically at the A D conversion is finished even though it is not oscillating 50 A D interrupt request N AD conversion register AD conversion register L Address 001716 Resistor ladder Address 001
7. Edge Compare register 1 low order 8 Compare register 2 low order Compare register 2 high order 8 Edge Ly gt selection gt Compare register 3 low order 8 Y Compare register high order 8 ulse output mode P6s Txouri LEDs g N Timer X output 1 active edge switch P65 direction register _ P65 latch IGBT output mode PWM mode Timer X output 1 selection bit P63 TxouT2 LED1 Timer X output 2 active edge switch bit P63 direction register P63 latch Timer X output 2 selection bit Note1 SOURCE indicates the followings XiN input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode Fig 28 Timer X block diagram Rev 3 04 20 2008 38 01134 RENESAS REJ03B0158 0304 3805 e Frequency Divider For Timer Each timer X and timer Y have the frequency dividers for the count source The count source of the frequency divider is switched to XIN XCIN or the on chip oscillator OCO divided by 4 in the on chip oscillator mode by the CPU mode register The division ratio of each timer can be cont
8. 1 Unused common pin outputs the unselected waveform Segment Signal Output Pin The segment signal output pins SEGo SEG31 are shared with ports When these pins are used as the segment signal output pins set the direction registers of the corresponding pins to 1 and set the segment output disable register to 0 Also these pins are set to the input port after reset the Vcc voltage is output by the pull up resistor Contrast adjust gt P7V INT P7o INTO Vu 1 2 bias 1 1 bias static When the voltage multiplier is not used the C and Ce pins function as input ports P7o INTo1 P71 INT11 Fig 45 Example of circuit at each bias at external power supply input Rev 3 04 REJ03B0158 0304 20 2008 Page 54 0 134 sENESAS 3805 LCD Display RAM The 36 byte area of address 084016 to 086316 is the designated RAM for the LCD display When 1 is written to these addresses the corresponding segments of the LCD display panel are turned on The LCDCK timing frequency LCD drive timing is generated internally and the frame frequency can be determined with the following equation frequency of count source for LCDCK LE divider division ratio for LCD Frame frequency f LCDCK duty ratio at 4COM x 36SEG M 7 6 5 4 3 2 1 0 Address 084016 SEGo 084116 SEGi lt Notes gt 1 Executing STP Instruction Executing the STP instr
9. Block erasing connect to external ceramic resonator or on chip oscillator Program Erase control by software command e Sub clock generating circuit eee 1 connect to external quartz crystal oscillator APPLICATION Household products Consumer electronics etc Rev 3 04 20 2008 1 0134 stENESAS REJ03B0158 0304 3805 PIN CONFIGURATION TOP VIEW 4 9 17 29165 914 gt 2 2035 9114 gt 77 2915 14 gt BLDAS ELd 97 5 214 lt 2 gt 87 53S 0d 6 7193 904 gt 05 5193 304 gt 15 2 93S r0d 4 25 935 504 gt ES 0193 204 75 995 0 ss 8935 00 55 1018 4 E 953S 92d gt 85 9015 gt 55 O3S ed 4 M EDAS EZd 4 99 5 24 4 SM O3S Zd 4 MM 0O3S 02d 79 4 gt P30 SEG24 lt gt P31 SEG25 4 gt P32 SEG26 lt gt P33 SEG27 P34 SEG s lt gt P35 SEG 9 lt gt 36 5 P37 SEG31 P47 SRDY2 KW3 P46 ScLK2 45 800 2 44 P43 SRDY1 4 gt 69 42 5 lt gt P41 TxD 4 P40 RxD 4 gt lt gt lt LO Q Co gt COM7 SEG32 M38D59FFFP 6 5 gt COMs SE
10. 2 2 2 In frequency 4 mode 2 gt In frequency 8 mode IA IAT IAF IA gt NOTE 1 12 5 MHz lt f XIN lt 16 MHz is not available in the frequency 2 mode Rev 3 04 20 2008 Page4of134 amp 4 NC S AS REJ03B0158 0304 3805 Table 2 Performance overview 2 Parameter Function Power dissipation QzROM version In frequency 2 mode Std 32 mW Vcc 5 V f XIN 12 5 MHz Ta 25 C In low speed mode Std 18 uW Vcc 2 5 V f XIN stop 32 kHz Ta 25 C Power dissipation Flash memory version In frequency 2 mode Std 20 mW Vcc 5 V 12 5 MHz 25 C In low speed mode Std 1 1 mW Vcc 2 7 V f XiN stop 32 kHz 25 C Input Output characteristics Input Output withstand voltage Output current 10 mA Operating temperature range 20 to 85 C Device structure CMOS silicon gate Package Rev 3 04 20 2008 Page 5 134 REJ03B0158 0304 80 pin plastic molded LQFP QFP 5 5 3805 92 001 10 1 920 uren LNOX NIX uoneJjeuo x420Jo 15 uod 8
11. 2 Read Order to Timer X In all modes read the following registers in the order as shown below the timer X register extension the timer X register high order the timer X register low order When reading the timer X register extension is not required read the timer X register high order first and the timer X register low order Read order to the compare registers 1 2 3 is not specified Read from the timer X register by the 16 bit unit Do not write to the timer X register while read operation is performed If the read operation is not completed normal operation will not be performed 3 Write to Timer X Which write control can be selected by the timer X write control bit b3 of the timer X mode register address 2D16 writing data to both the latch and the timer at the same time or writing data only to the latch When writing a value to the timer X address to write to the latch only the value is set into the reload latch and the timer is updated at the next underflow After reset release when writing a value to the timer X address the value is set into the timer and the timer latch at the same time because they are written at the same time When writing to the latch only if the write timing to the high order reload latch and the underflow timing are almost the same the value is set into the timer and the timer latch at the same time In this time counting is stopped during writing to the
12. total peak output current 1 110 mA P62 P67 XoH avg total average output current 1 20 mA 0 0 P1o P17 20 27 P3o P37 P72 P74 XoH av total average output current 1 20 mA P4o P47 P5o P57 P6o P67 XoL avg L total average output current 1 20 mA 07 P1o P17 20 27 P3o P37 P72 P74 L total average output current 1 20 mA P4o P47 P5o P57 P60 P61 L total average output current 1 90 mA P62 P67 loH peak peak output current 2 2 mA 0 0 P1o P17 20 27 P3o P37 peak output current 2 5 mA P4o P47 P5o P57 P6o P67 P72 P74 L peak output current 2 5 mA 0 0 P1o P17 20 27 P3o P37 loLpea L peak output current 2 10 mA P4o P47 P5o P57 P6o P61 P72 P74 L peak output current 2 30 mA P62 P67 loH avg H average output current 3 1 0 mA 0 0 P1o P17 20 27 P3o P37 loH avg average output current 3 2 5 mA P4o P47 P5o P57 P6o P67 P72 P74 loL avg L average output current 3 2 5 mA 0 0 P1o P17 20 27 P3o P37 loL avg L average output current 3 5 0 mA P4o P47 P5o P57 P6o P67 P72 P74 loL avg L average output current 3 15 mA P62 P67 NOTES 1 The total output current is the sum of all the currents flowing through
13. 21 1 ADKEY selection bit ADKEY enable bit Sub clock oscillation circuit input 4 Analog input pin selection bit _ A D conversion input 4 9 9 O 15 Port P61 16 Port P62 Pull up control Port Xc switch bit D Pull up control Port X itch bit ort Xc switch bi P Direction Direction register register gt Data bus T Port latch Data bus gt _ Port latch Sub clock oscillation circuit Port P60 INTO interrupt input Xc oscillation enable INTO input port switch bit 17 Ports P64 P67 18 Ports P63 P65 Pull up contro Pull up control 71 r Direction Direction register Da register gt Data bus Port latch gt Data bus 5 Port latch gt 4 1 interrupt input Pulse output mode INT2 interrupt input Timer X output 1 21 Timer output 2 Fig 16 Port block diagram 3 Rev 3 04 20 2008 Page 240 134 stENESAS REJ03B0158 0304 3805 19 Port P66 20 Ports P70 P71 l up contr
14. COMo SEGo 1 2 duty COMo SEGo ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF 4 gt gt gt gt gt gt 4 gt gt gt gt gt gt gt COM COMo COM COM COMo COM COM COMo COMo Fig 48 LCD drive waveform 1 3 bias Rev 3 04 20 2008 57 0 134 RENESAS REJ03B0158 0304 3805 ROM CORRECTION FUNCTION A part of program in ROM can be corrected Set the start address of the corrected ROM data i e an Op code address of the beginning instruction to the ROM correction ROM correction address 1 low order register RCA1L OFF916 address high order and low order registers When the program is being executed and the value of the ROM correction address 1 high order register RCA1H OFF816 ROM correction address 2 high order register RCA2H 16 program counter matches with the set address value the 3 correction address registers the program is branched to the ROM ROM correction address 2 low order register RCA2L OFFB16 correction vectors and then the correction program can
15. Mask file For the writing confirmation form and the mark specification form refer to the Technology Corp Homepage http www renesas com homepage jsp Note that we cannot deal with special font marking customer s trademark etc in QZROM microcomputer QzROM Receive Flow When writing to QzROM is performed by user side the receiving inspection by the following flow is necessary QzROM product shipped after writing protect disabled protect enabled to the protect area 1 QzROM product shipped in blank Renesas Renesas Programming V Shipping Verify test Shipping Receiving inspection of gt unprotected area Verify test Programming User Receiving inspection Blank check Programming to unprotected areal Verify test for all area Verify test for unprotected area 7v Fig 89 QzROM receive flow 20 2008 940f134 RENESAS 3805 NOTES FLASH MEMORY VERSION CPU Rewrite Mode 1 Operation speed During CPU rewrite mode set the system clock 4 0 MHz or less using the main clock division ratio selection bits bits 6 and 7 of address 0038 16 2 Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during the CPU re
16. Timer 4 count stop bit PWM1 circuit Timer 4 output selection bit P74 PWM1 o 74 2 latch el T4OUT output edge switch bit P74 direction register Timer 4 output selection bit PWM01 register 2 Note1 SOURCE indicates the followings Timer 4 write control bit Timer 4 interrupt request Fig 25 Timer 1 4 block diagram XIN input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode Rev 3 04 REJ03B0158 0304 20 2008 Page 35 01134 sRENESAS 3805 e Frequency Divider For Timer Timer 1 timer 2 timer 3 and timer 4 have the frequency divider for the count source The count source of the frequency divider is switched to XIN XCIN or the on chip oscillator OCO divided by 4 in the on chip oscillator mode by the CPU mode register The frequency divider is controlled by each timer division ratio selection bit The division ratio can be selected from as follows 1 1 1 2 1 16 1 256 of f XIN f XcIN or f DCO 4 Switch the frequency division or count source while the timer count is stopped This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes on chip oscillator mode XIN mode or low speed mode Be careful when changing settings in the CPU
17. 32 tCONV Conversion time 1 10bitAD mode tc AD x61 tc 9AD x62 8bitAD mode 49 50 RLADDER Ladder resistor 12 100 IVREF Reference input VREF 5 0V 50 200 current Analog input current 5 0 NOTES 1 tc AD one cycle of AD conversion clock AD conversion clock can be selected from SOURCE 2 or SOURCE 8 SOURCE represents the input in the frequency 2 4 or 8 mode and internal on chip oscillator divided by 4 in the on chip oscillator mode or the low speed mode When the A D conversion is executed in the frequency 2 mode frequency 4 mode or frequency 8 mode set f XiN 2 500 kHz Relationship among AD conversion clock frequency power source voltage AD conversion mode and absolute accuracy AD conversion clock 10bitAD 4LS Low speed mode and 8bitAD 2LSB on chip oscillator mode or f OCO 32 MHz 6 257 AD conversion clock XIN 8 frequency 2 mode i 8bitAD 2LSB frequency 4 and frequency 8 mode f XiN 2 or f XIN 8 AD conversion clock frequency f XIN 2 or 8 10bitAD 4LSB H f XiN 2 or 8 8bitAD 2LSB NENNEN i i i 0 18 2 02 2 4 0 4 5 5 5 V Power source voltage Vcc Note gt 500kHz Rev 3 04 20 2008 104 of 134 42 N S AS REJ03B0158 0304 3
18. Port PO direction register POD Port P1 P1 Port P1 direction register P1D Port P2 P2 Port P2 direction register P2D Port P3 P3 Port P3 direction register P3D Port P4 P4 Port direction register Port P5 P5 Port P5 direction register P5D Port P6 P6 Port P6 direction register P6D Port P7 P7 Port P7 direction register P7D CPU mode register 2 CPUM2 RRF register RRFR LCD mode register1 LM1 LCD mode register2 LM2 AD control register ADCON AD conversion register low order ADL AD conversion register high order ADH Transmit receive buffer register 1 TB1 RB1 Serial 1 01 status register SIO1STS Serial 1 01 control register SIO1CON UART control register UARTCON Baud rate generator BRG Serial 1 02 control register SIO2CON Reserved 1 Serial 1 02 register 5102 Flash memory control register 0 FMCRO Flash memory control register 1 FMCR1 Flash memory control register 2 FMCR2 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 002016 002116 002216 002316 002416 0025
19. 20 2008 840f 134 stENESAS REJ03B0158 0304 3805 Parallel I O Mode The parallel I O mode is used to input output software commands address and data in parallel for operation read program and erase to internal flash memory User ROM and Boot ROM Areas In parallel I O mode the User ROM and Boot ROM areas shown in Figure 70 can be rewritten Both areas of flash memory can be operated on in the same way The Boot ROM area is 4 Kbytes in size and located at addresses F00016 through FFFF16 Make sure program and block erase operations are always performed within this address range Access to any location outside this address range is prohibited In the Boot ROM area an erase block operation is applied to only one 4 K byte block The boot ROM area has had a standard serial I O mode control program stored in it when shipped from the factory Therefore using the MCU in standard serial I O mode do not rewrite to the Boot ROM area Rev 3 04 20 2008 85 01134 RENESAS REJ03B0158 0304 3805 Standard serial I O Mode The standard serial I O mode inputs and outputs the software commands addresses and data needed to operate read program erase etc the internal flash memory This I O is clock synchronized serial This mode requires a purpose specific peripheral unit The standard serial I O mode is different from the parallel I O mode in that the CPU controls flash memo
20. and then 1 in succession Set user block 1 E W enable bit At E W disabled writing 0 at E W enabled writing 0 and then 1 in succession Using software command executes erase program or other operation v Execute read array command v Set user block 0 E W enable bit to 0 Set user block 1 E W enable bit to 0 v Write 0 to CPU rewrite mode select bit End Notes 1 Set the main clock as follows depending on the clock division ratio selection bits of CPU mode register bits 6 7 of address 003Bt6 2 Before exiting the CPU rewrite mode after completing erase or program operation always be sure to execute the read array command Fig 74 CPU rewrite mode set release flowchart be sure to execute Rev 3 04 20 2008 77 0 134 stENESAS REJ03B0158 0304 3805 lt Notes on CPU Rewrite Mode gt Take the notes described below when rewriting the flash memory in CPU rewrite mode 1 Operation speed During CPU rewrite mode set the system clock to 4 0 MHz or less using the main clock division ratio selection bits bits 6 and 7 of address 0038 16 2 Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode 3 Interrupts The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of
21. control register is written to Internal reset circuit STP instruction function selection bit 1 STP instruction Reset Wait until reset release Note1 SOURCE indicates the followings input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode Fig 52 Block diagram of Watchdog timer Watchdog timer control register WDTCON address 002916 1111 _ Watchdog timer for read out of high order 5 bit FF 16 is set to watchdog timer by writing to these bits Watchdog timer count source selection bit 2 0 souRcE 0 1 On chip oscillator 4 STP instruction function selection bit 0 Entering stop mode by execution of STP instruction 1 Internal reset by execution of STP instruction Watchdog timer count source selection bit 0 Count source 1024 1 Count source 4 Fig 53 Structure of Watchdog timer control register Rev 3 04 REJ03B0158 0304 Notes 1 SOURCE indicates the followings input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode When the on chip oscillator is selected by the watchdog timer count source selection bit 2 set the STP instruction function selection bit to 1 Select SOURCE as the count source at the system which on chip oscillato
22. 1 PWM mode Timer 4 operating mode selection bit 0 Timer mode 1 PWM mode Not used returns 0 when read bo Timer 1234 mode register T1234M address 002716 Tsour output edge switch bit 0 Start at L output 1 Start at H output Taour output edge switch bit 0 Start at L output 1 Start at H output Timer 3 output selection bit P73 0 port 1 Timer 3 output Timer 4 output selection bit P74 0 port 1 Timer 4 output Timer 2 write control bit 0 Write data to both timer latch and timer 1 Write data to timer latch only Timer 3 write control bit 0 Write data to both timer latch and timer 1 Write data to timer latch only Timer 4 write control bit 0 Write data to both timer latch and timer 1 Write data to timer latch only Not used returns 0 when read Fig 27 Structure of timer 1 to timer 4 related registers 60 PWM01 register address 002416 PWMO set bits b1b0 0 0 extended 0 1 Extended once in four periods 1 0 Extended twice in four periods 1 1 Extended three times in four periods PWM1 set bits b3b2 0 0 extended 0 1 Extended once in four periods 1 0 Extended twice in four periods 1 1 Extended three times in four periods Not used returns 0 when read Timer 1234 frequency division selection register PRE1234 address 002816 Timer 1 frequency division selection bit
23. Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring Use lines with a larger diameter than other signal lines for Vss line and Vcc line Connect the power source wiring via a bypass capacitor to the Vss pin and the pin Reset _ circuit Vss Fig 91 Wiring for the RESET pin 2 Wiring for clock input output pins Make the length of wiring which is connected to clock I O pins as short as possible Make the length of wiring within 20 mm across the grounding lead of a capacitor which is connected to an oscillator and the Vss pin of a microcomputer as short as possible Separate the Vss pattern only for oscillation from other Vss Fig 93 Bypass capacitor across the Vss line and the Vcc patterns line Reason If noise enters clock I O pins clock waveforms may be deformed This may cause a program failure or program runaway Also if a potential difference is caused by the noise between the Vss level of a microcomputer and the Vss level of an oscillator the correct clock will not be input in the microcomputer Rev 3 04 20 2008 Page960f134 RENESAS REJ03B0158 0304 3805 3 Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition contact the oscillator manufacturer and select the oscillator and oscillation circuit constants Be careful especially when range of voltage and temperature is
24. INTo gt interrupt request External trigger delay time selection bits Data for control of event counter window Timer 1 interrupt L O us 00 Trigger for IGBT input control bit Edge selec INToo tNTo gt Noise filter 4 times same tion Clock for Timer X 0 levels judgment Timer X count source selection bit Timer X operating mode bits 000 4001 Timer X count stop bit SOP 4 Delay circuit AM XIN B XIN to Delay circuit 1 2 Timer X operating 010 bits 16 XIN 11 o Timer X write control bit 000 001 011 100 101 9 00 101 Timer X low order latch 8 Timer X high order latch 8 Extend latch 2 gt Both edges detection a us Soi Lo 10 11 100 Timer X low order 8 Timer X high order 8 Extend counter 2 ii Pulse width measurement CNTRo active mode Timer X interrupt request CNTRo interrupt request edge switch bits Timer X output Timer X operating control bit 1 mode bits 010 gt Edge 9 gt v INT10 INT11 selection Timer X output reg 8 control bit 2
25. P42 SCLk P43 BUSY RESET circuit Set the same termination as the single chip mode 1 Open collector buffer Note 1 For the programmer circuit the wiring capacity of each signal pin must not exceed 47pF Fig 83 When using E8 programmer in standard serial I O mode 1 connection example Rev 3 04 20 2008 Page 91 01134 stENESAS REJ03B0158 0304 3805 Flash memory version td CNVss RESET td P41 RESET 1 Power source 5 Note In the standard serial I O mode 1 input to the P42 pin Be sure to set the CNVss pin to before rising RESET td CNVss RESET Be sure to set the P41 pin to before rising RESET td P41 RESET Symbol Fig 84 Operating waveform for standard serial I O mode 1 Flash memory version td CNVss RESET td P41 RESET Power source RESET P40 RxD NTT TNT 0 00M 4 LII LI s Limits Note In the standard serial I O mode 2 input H to the P42 pin Typ Be sure to the CNVss to H before rising RESET td CNVss RESET 2 Be sure to set the P41 pin to before rising RESET td P41 RESET Symbol Fig 85 Operating waveform for standard serial I O mode 2 Rev 3 04 20 2008 92 01134 stENESAS
26. ROM code protection NOTE Available in parallel mode and standard serial I O mode 1 The Boot ROM area has had a standard serial I O mode control program stored in it when shipped from the factory This Boot ROM area can be erased and written in only parallel I O mode Rev 3 04 REJ03B0158 0304 20 2008 Page 74 01134 sRENESAS 3805 Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I O mode beforehand If the control program is written into the Boot ROM area the standard serial I O mode becomes unusable See Figure 70 for details about the Boot ROM area Normal microcomputer mode is entered when the microcomputer is reset with pulling pin low In this case the CPU starts operating using the control program in the User ROM area When the microcomputer is reset and the CNVSss pin high after pulling the P41 TxD pin and CNVss pin high the CPU starts operating start address of program is stored into addresses FFFC16 and FFFD16 using the control program in the Boot ROM area This mode is called the Boot mode Also User ROM area can be rewritten using the control program in the Boot ROM area Block Address Block addresses refer to the maximum address of each block These addresses are used in the block erase command 000016 SFR area 100016 004016 Internal RAM area 2K bytes 083F
27. Timing controller Common driver Segment driver Bias control circuit A maximum of 36 segment output pins and 8 common output pins can be used Up to 256 pixels can be controlled for an LCD display When the LCD enable bit is set to 1 after data is set in the LCD mode register the segment output disable register and the LCD display RAM the LCD drive control circuit starts reading the display data automatically performs the bias control and the duty ratio control and displays the data on the LCD panel LCD mode register 1 LM 1 address 001316 Duty ratio selection bits 26160 1 Static 2 use 1 3 use 4 use COMo COM3 to 1 10 Not available 11 8 ias control bit 0 1 3 bias 1 2 bias LCD enable bit 0 LCD OFF LCD ON 01 10 11 00 b6b5 00 Clock input 0 1 2 division of clock input 0 4 division of clock input 1 8 division of clock input LCDCK count source selection bit 2 0 f Xcin 32 9SOURCE 8192 Segment output disable register 0 SEGO address OF F416 3 Segment output disable bit 0 0 Segment output SEGs Output port POo Segment output disable bit 1 0 Segment output SEGs 1 Output port PO Segment output disable bit 2 0 Segment output Output port Segment output disable bit 3
28. y Aq 1050 diuo uo 8 p 2 y NIX 5 ay sejeorpur 007 eui 10 9012 S 0007 1 SJON 9935 7935 SWOOD 28035 to3S ted 29145 22 95 24 093S 0Zd 1 1 i 14 ys Je e1 k 1 1 1 10 0819 10 9 10198195 1019985 2019195 2012195 915980 1 912980 1 1 915780 912780 911780 1 910780 ssaippy 1 1 SseJppy Sseippy ssaippy 1 f LCD controller driver 44 Block diagram o ig F 20 2008 53 01134 RENESAS REJ03B0158 0304 Rev 3 04 3805 Voltage Multiplier The voltage multiplier performs threefold boosting This circuit inputs a reference voltage for boosting from LCD power input pin VL1 Set each bit of the segment output disable registers and the LCD mode registers in the following order for operating the voltage multiplier 1 Set the segment output disable bits bits 0 to 19 of the segment output disable registers SEGO 1 2 to 0 or 1 2 Set the duty ratio selection bits bits
29. 0 Segment output SEG11 1 Output port Segment output disable bit 4 0 Segment output SEGi2 Output port POs Segment output disable bit 5 0 Segment output SEGi3 1 Output port POs Segment output disable bit 6 0 Segment output SEG14 Output port POs Segment output disable bit 7 0 Segment output SEGis 1 Output port 07 Segment output disable register 2 SEG address OFF6 6 9 Notes 1 2 Segment output disable bit 16 0 Segment output SEGie SEGi9 1 Output port P1o P13 Segment output disable bit 17 0 Segment output SEG20 SEG s 1 Output port P14 P17 Segment output disable bit 18 0 Segment output SEG24 SEG27 1 Output port P3o P33 Segment output disable bit 19 0 Segment output SEG2s SEGst 1 Output port P34 P37 Not used do not write 1 Fig 43 Structure of LCD related registers Rev 3 04 20 2008 52 134 QEN REJ03B0158 0304 Table 12 Maximum number of display pixels at each duty ratio Duty ratio Maximum number of display pixels 36 dots 1 or 8 segment LCD 4 digits 72 dots or 8 segment LCD 9 digits 108 dots or 8 segment LCD 13 digits 144 dots or 8 segment LCD 18 digits 256 dots or 8 segment LCD 32 digits LCD mode register 2 LM2 address 001416 Voltage multiplier ci
30. 1 8 When start oscillating 3 0 05 1 9 Power source voltage input voltage Voltage multiplier is used 1 3 A D converter reference voltage 2 0 Analog power source voltage Analog input voltage ANo AN7 AVss H input voltage 00 07 10 17 P24 P27 P30 P37 P41 P43 5 57 6 0 P61 P65 72 74 0 7Vcc lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Vcc H input voltage 20 23 P40 P42 P44 47 P62 P64 P66 P67 P70 P71 0 8Vcc Vcc input voltage RESET 2 2 lt Voc lt 5 5V 0 8Vcc Vcc Vcc x 2 2V 65 x Vcc 99 100 Vcc H input voltage XIN 0 8Vcc Vcc L input voltage P0o PO7 10 17 P24 P27 7 P41 P43 5 57 P60 P61 P65 P72 P74 0 0 3Vcc L input voltage 20 2 P40 P42 P44 P47 P62 P64 P66 P67 0 2Vcc 7 P71 OSCSEL L input voltage RESET 2 2 lt Vcc lt 5 5V Vcc lt 2 2V 0 2Vcc 65 x Vcc 99 o 0 2Vcc L input voltage XIN NOTES 1 When the A D converter is used refer to the recommended operating conditions of the A D converter 2 12 5 MHz f XiN x 16 MHz is not available in the frequency 2 mode 3 The oscillation start voltage and the oscillation start time differ dependi
31. 14 4 em o DN XIN stop XIN stop XIN stop XCIN stop XCIN oscillation XCIN oscillation oscillation OCO oscillation OCO stop f OCO 32 f OCO 32 f XciN 2 CM7 1 CM7 1 CM7 1 invalid 6 CM6 1 CM6 1 CM6 1 invalid CM5 1 5 1 CM5 1 CM4 0 CM4 1 CM4 1 CM3 0 8 0 CM3 0 CM8 0 CM3 1 CM8 1 XIN oscillation XIN oscillation XIN oscillation QzROM version XCIN stop XCIN oscillation XCIN oscillation Flash memory version OCO oscillation OCO oscillation CM3 CM7 OCO stop OSCSEL L 32 32 2 CM7 1 CM7 1 Ii 7 0 invalid CMe 1 CMe 1 6 CMe 1 invalid 5 0 5 0 5 0 CM4 0 CM4 1 CM4 1 CM3 0 8 0 CM3 0 8 0 CM3 1 1 A CM6 CM6 CM7 6 CM7 6 Y Reset release XIN oscillation XIN oscillation XCIN oscillation XCIN oscillation NS stop stop y equency 8 mode 2 2 QzROM version mas T 7 0 invalid CM7 1 invalid OSCSEL H XIN oscillation frequency 8 XIN oscillation frequency 8 CM6 0 invalid 6 0 invalid XCIN stop XCIN oscillation 5 0 5 0 oscillation stop c OCO oscillation or stop CM4 1 CM4 1 9 8 4 f XiN 8 E 7 0 CM7 0 CM3 1 CM8 1 CM3 1 CM8 1 CMe 1 1 5 0 5 0 CM4 0 CM4 1 CM3 0 CM8 CM3 0 CM8 CM6 Frequency 2 mode Frequency 4 mod
32. 3 When bit 6 of address 001 16 is 1 clock synchronous Divide this value by four when bit 6 of address 001 16 is 0 UART Rev 3 04 20 2008 105 of 134 42 N S AS REJ03B0158 0304 3805 QzROM VERSION Table 31 Timing requirements 2 Vcc 1 8 to 4 0 V Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter tw RESET Reset input L pulse width tc XIN Main clock input cycle time 2 0V lt VCC lt 4 0V XIN input Vcc lt 2 0V twH XIN Main clock input H pulse width 2 0V lt Vcc lt 4 0V 50 Vcc 2 0V 70 tWL XIN Main clock input L pulse width 2 0V lt Vcc lt 4 0V 50 Vcc 2 0V 70 CNTRo CNTRt input cycle time 2 0V lt Vcc lt 4 0V 1000 Vcc lt 2 0V 1000 5 x VCC 8 CNTRo CNTR input pulse width tc CNTR 2 20 CNTRo input L pulse width tc CNTR 2 20 INToo INTo1 INT10 INT11 INT2 input pulse width 230 twL INT INTo1 INT10 INT2 input L pulse width 230 tc ScLk1 Serial 1 01 clock input cycle time 1 2000 twH SCLK1 Serial 1 01 clock input pulse width 1 950 tWL SCLK1 Serial 1 01 clock input L pulse width 1 950 tsu RXD ScLk1 Serial 1 input setup time 400 th ScLk1 RxD Serial 1 01 input hold time 200 tc ScLk2 Serial 1 02 clock input cycle time 2000
33. CNTR1 KWo KW7 Hysteresis SiN2 SCLK1 SCLK2 RxD Hysteresis RESET H input current P0o PO7 P10 P17 P20 P27 7 input current 40 47 P5o P57 P60 P67 P70 P74 input current RESET CNVss input current XIN Vi Vcc Vi Vcc input current Vi Vss POo P07 10 17 P20 P27 Pull up OFF 7 5 Vi Vss Pull up ON 3 Vi Vss Pull up ON input current Vi Vss P40 P47 5 5 67 Pull up OFF P72 P74 Vcc 5V 55 Pull up Vec 3V Vi Vss Pull up ON Vi Vss L input current RESET CNVss L input current Vi Vss On chip oscillator frequency Vcc 5V Ta 25 C NOTE 1 When the port Xc switch bit bit 4 of address 003 16 of CPU mode register is 1 the drivability of P61 is different from the above Rev 3 04 20 2008 Page 113 01134 stENESAS REJ03B0158 0304 3805 FLASH MEMORY VERSION Table 39 Electrical characteristics 2 Vcc 2 7 to 5 5 V Vss 0 V 20 to 85 C f XCIN 32 768 kHz output transistors in the cut off state A D converter stopped unless otherwise noted Parameter Test conditions RAM hold voltage When clock is stopped Power source current Frequency 2 mode Vcc 5 0V 12 5 2 f XIN 12 5MHz WIT state
34. COMO Fig 46 LCD display RAM map Rev 3 04 REJ03B0158 0304 20 2008 55 01134 sRENESAS 3805 Internal signal LCDCK timing 1 8 duty COMo COM1 COM COMs SEGo 1 4 duty COM SEGo 1 3 duty COMo SEGo 1 2 duty COMo SEGo Voltage level Vis 2 Vss OFF ON OFF ON OFF ON OFF ON 4 gt 4 gt gt gt gt gt gt gt gt 4 gt gt gt 5 COM COM COMe COMs COM OFF ON OFF ON 4 gt 4 gt gt gt 4 gt gt gt gt gt gt 4 gt COM COM COMo COM COM COMo 2 COM ON OFF OFF ON OFF ON OFF ON gt gt gt gt gt gt gt gt gt
35. P33 SEG27 P34 SEG 8 P35 SEG 9 P36 SEG30 P37 SEG31 P21 SEG1 KW5s P20 SEGo KWa P47 SRDY2 KWs3 46 5 KW1 lt gt lt gt O P45 Sout2 KW1 P44 SiN2 K Wo P4s SRDYi lt gt 42 5 9 68 ESDA P41 TxD lt 69 M38D5XGXHP AVss VREF P57 AN7 ADKEYo lt gt P5e ANe lt gt 55 5 lt gt P54 AN4 lt gt P53 AN3 lt gt P52 AN2 lt gt P51 AN1 RTP1 lt gt P5o ANo RTPo 4 gt 80 4 P70 C1 INTo WAT 20 Vss Q P64 INT2 P61 Xcour lt 9 lt P73 PWMo TsourT lt gt P72 T20UT CKOUT lt gt P71 C2 NT11 gt P67 CNTR1 P65 TxouT1 P63 T xouT2 P66 INT10 CNTRo Connect to oscillation circuit QzROM pin Vcc PLQP0080KB A 80P6Q A Fig 65 Pin connection diagram M38D5XGXHP Rev 3 04 20 2008 69 01134 RENESAS REJ03B0158 0304 3805 QzROM version 38D5 Group RESET circuit Vcc OSCSEL P41 ESDA P42 ESCLK P43 ESPGMB Set the same termination as the 1 Open collector buffer single chip mode Note For the programming circuit the wiring capacity of each signal pin must not exceed 47 pF Fig 66 When
36. P67 P70 P71 H input voltage RESET input voltage XIN L input voltage POo P07 10 17 P24 P27 P30 P37 P41 P43 5 57 P60 CM4 0 P61 P65 P72 P74 L input voltage 20 2 P40 P42 P44 P47 P62 P64 P66 P67 P70 P71 L input voltage RESET L input voltage XIN L lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 1 When the A D converter is used refer to the recommended operating conditions of the A D converter 2 12 5 MHz lt f XiN x 16 MHz is not available in the frequency 2 mode Rev 3 04 20 2008 110 of 134 42 N S AS REJ03B0158 0304 3805 FLASH MEMORY VERSION Table 36 Recommended operating conditions 2 Vcc 2 7 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limits Symbol Parameter Min Typ Max XoH pea total peak output current 1 40 mA P0Oo P07 P1o P17 20 27 P3o P37 P72 P74 total peak output current 1 40 mA P4o P47 P5o P57 P6o P67 total peak output current 1 40 mA 07 P1o P17 20 27 P3o P37 P72 P74 4 total peak output current 1 40 mA P4o P47 P5o P57 P6o P61
37. Rev 3 04 REJ03B0158 0304 Product shipped in blank As for the product shipped in blank Renesas does not perform the writing test to user ROM area after the assembly process though the QZROM writing test is performed enough before the assembly process Therefore a writing error of approximate 0 1 may occur Moreover please note the contact of cables and foreign bodies on a socket etc because a writing environment may cause some writing errors Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing submit the mask file extension msk which is made by the mask file converter MM Be sure to set the ROM option data setup when making the mask file by using the mask file converter MM The ROM code protect is specified according to the ROM option data in the mask file which is submitted at ordering Note that the mask file which has nothing at the ROM option data or has the data other than 0016 16 and 16 can not be accepted Set FF16 to the ROM code protect address in ROM data regardless of the presence or absence of a protect When data other than FF16 is set we may ask that the ROM data be submitted again ROM option data mask option noted in MM Data Required For QZROM Writing Orders The following are necessary when ordering a QZROM product shipped after writing 1 Writing Confirmation Form 2 Mark Specification Form 3 ROM data
38. SOURCE 9 00 1 Frequency divider 5 75 Timer 2 for Timer 00 10 o 0 XCOUT Port Xc switch bit 0 Main clock division ratio selection bit 0 Gc WI nternal system clock selection bit 1 p System clock WIT_ STP instruction instruction R STP instruction Reset Interrupt disable flag Interrupt request 4 Notes 1 When the XcIN XCOUT oscillation is selected as the system clock set the port Xc switch bit to 1 2 Although a feed back resistor exists on chip an external feed back resistor may be needed depending on conditions 3 SOURCE indicates the followings XIN input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode However when used as the A D conversion clock by the A D converter SOURCE indicates the followings XIN input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the low speed or the on chip oscillator mode Fig 62 Clock generating circuit block diagram Rev 3 04 20 2008 65 01134 RENESAS REJ03B0158 0304 3805 7 On chip oscillator mode _ Low speed mode
39. Static added Notes added Fig 11 OFFE16 OFFF16 Reserved added Direction Registers Ports PO P6 P72 P74 Depending on the pin may be read is deleted 6 7 REVISION HISTORY 38D5 Group Data Sheet Date Description Summary May 20 2008 Table 9 P45 Sin2 KW1 P45 SouT2 KW1 P42 SCLK2 KWe P46 ScLK2 KW2 P43 SRDY2 KW3 P47 SRDY2 KW3 Fig 14 is revised Table 10 P20 SEGo P27 SEG7 P20 SEGo KWa4 P27 SEG7 Fig 64 P20 SEGo KW4 P20 SEGo KWa4 P21 SEG1 KW5 gt P21 SEG1 KW5 P22 SEG2 KWe P22 SEG2 KWe P23 SEG3 KW7 gt P23 SEG3 KW7 Fig 65 P22 SEG2 KWe P22 SEG2 KWe P23 SEG3 KW7 gt P23 SEG3 KW7 P56 AN10 P56 ANe Fig 73 is revised Fig 81 56 10 P56 ANe Notes On QzROM Writing Orders is revised All trademarks and registered trademarks are the property of their respective owners 7 7 Renesas Tech nology Corp Sales Strategic Planning Div Nippon Bldg 2 6 2 Ohte machi Chiyoda ku Tokyo 100 0004 Japan Notes 1 This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes 10 warranties or representations with respect to the accuracy or completeness of the information contained in th
40. The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data of the flash memory 4 Watchdog Timer In case of the watchdog timer has been running already the internal reset generated by watchdog timer underflow does not happen because of watchdog timer is always clearing during program or erase operation 5 Reset Reset is always valid In case of CNVss when reset is released boot mode is active So the program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area CNVss Pin The CNVss pin determines the flash memory mode Connect the CNVss pin the shortest possible to the GND pattern which is supplied to the Vss pin of the microcomputer In addition connecting an approximately 5 resistor in series to the GND could improve noise immunity In this case as well as the above mention connect the pin the shortest possible to the GND pattern which is supplied to the Vss pin of the microcomputer Note When the boot mode or the standard serial I O mode is used a switch of the input level to the CNVss pin is required shortest Approx 5kQ van shortest Note 1 Shows the microcomputer s pin Fig 110 Wiring for CNVss pin Rev 3 04 20 2008 134 of 134 42 N S AS REJ03B0158 0304 REVISION HISTORY 38D5 Group Data Sheet Description Summary Aug 12 2005 First edition issued Jan 23 2006 Pin name revis
41. Vector fetch Interrupt handling Main routine alnirout routine Oto 16 cycles 7 cycles 7 to 23 cycles When executing DIV instruction Fig 20 Time up to execution in interrupt routine Push onto stack Vector fetch Execute interrupt routine gt gt RD WR Address bus PC XS SPSX8 1 SPSXE 2 5PSX BL X BH X PCH X PS X AL X AL AH Data bus _ Not used SYNC CPU operation code fetch cycle This is an internal signal that cannot be observed from the external unit BL BH Vector address of each interrupt AL AH Jump destination address of each interrupt SPS 0016 or 0116 SPS is a page selected by the stack page selection bit of CPU mode register Fig 21 Interrupt sequence 20 2008 31 of 134 q N S AS 3805 lt Notes gt If it is not necessary to generate an interrupt synchronized with The interrupt request bit may be set to 1 in the following cases these settings take the following sequence When setting the external interrupt active edge 1 Set the corresponding enable bit to 0 disabled Related bits INTo interrupt edge selection bit 2 Set the interrupt edge selection bit the active edge switch bit O of interrupt edge selection register bit or the interrupt source bit address 003
42. do not write 1 Before executing the STP instruction set the values to generate the wait time required for oscillation stabilization to timer 1 and timer 2 CPU mode register and set to 0 interrupts disabled to the interrupt enable bits of CPUM timer 1 and timer 2 address 003816 QzZROM version OSCSEL L initial value E016 Execute the transition after the oscillation used in the destination QzROM version OSCSEL H initial value 4016 mode is stabilized Flash memory version initial value E016 When system goes to on chip oscillator mode the oscillation Processor mode bits stabilizing wait time is not needed b1 b0 The on chip oscillator can be stopped in all kinds of state of 0 0 Single chip mode frequency 2 4 mode 01 In all XIN mode stop of on chip oscillator is enabled 10 Not available The example assumes that 8 MHz is being applied to the pin and 11 32 kHz to the XCIN pin f OCO indicates the oscillation frequency of Stack page selection bit on chip oscillator 0 0 page When selecting the on chip oscillator for the WDT clock the on chip 1 1 page oscillator does not stop Internal system clock selection bit Also in low speed mode the on chip oscillator stops in the 0 Main clock selected version regardless of the on chip oscillator stop bit value The on includes OCO XIN chip oscillator does not stop in the flash memory version so set
43. of UART control register is 0 Table 46 Switching characteristics 2 Vcc 2 7 to 4 0 V Vss 0 V Ta 20 to 85 unless otherwise noted Symbol Parameter Limits Min Typ twH SCLK1 Serial 1 clock output pulse width 2 80 SCLK1 Serial 1 clock output L pulse width 2 80 ta SCLK1 TXD Serial 1 01 output delay time 1 tv ScLK1 TxD Serial 1 01 output valid time 1 30 tr SCLK1 Serial 1 clock output rising time tt SCLK1 Serial 1 clock output falling time SCLKk2 Serial 2 clock output H pulse width tc ScLk2 2 80 twL ScLK2 Serial 2 clock output L pulse width tc ScLk2 2 80 tt SCLK2 Serial 2 clock output falling time td SCLK2 SouT2 Serial 2 output delay time tv ScLk2 SouT2 NOTE Serial 2 output valid time 1 The P41 TxD P channel output disable bit bit 4 of address 001B16 of UART control register is O Measurement output O e J Fig 97 Circuit for measuring output switching characteristics Rev 3 04 20 2008 11801134 42 N S AS REJ03B0158 0304 T 100pF 777 CMOS output 1k 100 N channel open drain output Note Measurement output pin 3805 FLASH MEMORY VERSION tc CNTR tWH CNTR
44. voltage from 1 3 V or more to 2 1 V or less to the VL1 pin When the multiplier circuit is not used set the VL3 connection bit to 1 open and apply an appropriate voltage to the LCD power source input pins VL to VL3 When the VL3 connection bit is set open the VL3 pin is placed in the high impedance state When the multiplier circuit is used set the LCDCK frequency to 100 Hz or more The on chip oscillator cannot be used as LCDCK In a system where the multiplier circuit is used a multiplier capacitor is externally connected between the C1 and C2 pins set the multiplier circuit control bit to 1 multiplier circuit enabled before executing the STP or WIT instruction 1 Correct processing 2 Setting Data to LCD Display RAM To write data to the LCD display RAM when the LCD enable bit is set to 1 and while LCD is turned on set fixed data Rewriting with temporary data may cause LCD to flicker The following shows a processing example to write data to the LCD display RAM while LCD is turned on Content at address 084016 FF1e LCD on or off On Set LCD display RAM data LRAMO address 084016 lt FF16 Set LCD display RAM data LRAMO address 084016 lt 0016 Set fixed data to LCD display RAM 1 2 Incorrect processing Content at address 084016 FFie Set LCD display RAM data LRAMO address 084016 lt 0016 LCD on off On Set LCD display RAM
45. 15mA loL 3 0mA Vcc 2 5V Hysteresis INToo INTo1 INT10 INT11 INT2 CNTRo CNTR1 KWo KW7 Hysteresis SCLK2 RxD Hysteresis RESET Vcc 2 0 V to 5 5 V on RESET input current 00 07 P10 P17 P20 P27 P30 P37 input current P40o P47 P5o P57 7 70 74 input current RESET OSCSEL input current XIN p input current 00 07 P10 P17 P20 P27 P30 P37 Vi Vss Pull up OFF Vcc 5V Vi Vss Pull up ON Vcc 3V Vi Vss Pull up ON input current 40 47 P5o P57 P60 P67 P72 P74 Vi Vss Pull up OFF Vcc 5V Vi Vss Pull up ON Vcc 3V Vi Vss Pull up ON p input current RESET OSCSEL Vi Vss p input current XIN Vi Vss NOTE On chip oscillator frequency Vcc 5V 25 C 1 When the port Xc switch bit bit 4 of address 003 16 of CPU mode register is 1 the drivability of P61 is different from the above Rev 3 04 20 2008 102 of 134 42 N S AS REJ03B0158 0304 3805 QzROM VERSION Table 27 Electrical characteristics 2 Vcc 1 8 to 5 5 V 20 to 85 C 32 768 kHz output transistors in the cut off state A D converter stopped unless otherwise noted Parame
46. 2048 PRQP0080GB A Flash memory version M38D59FFHP PLQPOO80KB A Part No Package Remarks Rev 3 04 20 2008 10 01134 stENESAS REJ03B0158 0304 3805 Table 6 Differences between QzROM and flash memory versions QzROM version Flash memory version Main clock XIN or on chip oscillator selectable by OSCSEL pin OSCSEL H OSCSEL L CNVss L Oscillation circuit at reset and at returning from stop mode On chip oscillator Termination of OSCEL CNVss pin 7 Main clock oscillation at reset and at returning from Stop mode i On chip oscillator oscillation at reset and at returning from stop mode System clock oscillation at reset and at returning 1 from stop mode Oscillation on Stop Stop Stop Oscillation on Oscillation on f XIN 8 f OCO 32 f OCO 32 Mounting of main clock oscillation circuit Required Optional Optional Stop by setting the on chip On chip oscillator oscillation in low speed mode Stop oscillator stop bit because it is not stopped Writing 1 to on chip oscillator stop bit in on chip On chip oscillator is not oscillator mode stopped Reset input L pulse width 2 us or more 2 ms or more Absolute maximum rating OSCSEL CNVss pin 0 3 to 8 0 0 3 to Vcc 0 3 Minimum operating power source voltage 1 8V 2 7V A D converter minimum operating power
47. 52 51 50 49 47 45 42 41 P20 SEGo KW4 P47 SRDY2 KW3 P46 ScLK2 KW2 P45 S0uT2 KW1 P44 SiN2 KWo P43 SRDY1 P21 SEG1 KWs M38D5XGXHP M38D59FFHP VREF P57 AN7 ADKEYo P5e ANe lt gt P55 AN5 lt gt P54 AN4 lt gt P53 AN3 lt P52 AN2 4 P51 AN1 RTP1 lt P5o ANo RTPo 80 20 4 P71 C2 INT11 P64 INT2 P63 TxouT2 P74 PWM1 T40uT lt gt P73 PWMo TsoUT gt P72 T20UT CKOUT 4 P67 CNTR1 P66 INT10 CNTRo P65 Txour1 Package type PLQPOO80KB A 80P6Q A Fig 2 Pin configuration LQFP package Rev 3 04 20 2008 Page30f134 RENESAS REJ03B0158 0304 P16 SEG22 P17 SEG23 P30 SEG24 P31 SEG25 P32 SEG26 P33 SEG27 P34 SEG28 P35 SEGa29 P36 SEG30 P37 SEG31 COM7 SEG32 COMe SEG33 P70 Ci INTo1 Note 1 CNVss in flash memory version 3805 Table 1 Performance overview 1 Parameter Function Number of basic instructions 71 Instruction execution time 0 32 us Minimum instruction Oscillation frequency 12 5 MHz Oscillation frequency 16 MHz 1 Memory sizes ROM 32 K to 60 K bytes QzROM version RAM 1536 to 2048 bytes Memory sizes ROM 60 K bytes Flash memory version RAM 2048 bytes Input port 7 P71 2 bit x 1 port PO P6 P72 P74 8 bit x 7 3 bit x 1 36 pins sharing SEG Interrupt 17 sources 16 vectors
48. 7 Output voltage 0 3 to 0 3 P4o P47 P5o P57 7 72 74 Output voltage 0 3 to 6 5 Output voltage Vi2 SEG32 SEG35 COMo COM3 0 3 to VL3 0 3 Output voltage 0 3 to 0 3 Power dissipation 25 300 Operating temperature 20 to 85 Storage temperature 40 to 125 At segment output 0 3 to VL3 0 3 lt lt lt lt lt lt lt lt lt lt lt lt Rev 3 04 20 2008 109 of 134 42 N S AS REJ03B0158 0304 3805 FLASH MEMORY VERSION Recommended Operating Conditions Table 35 Recommended operating conditions 1 Vcc 2 7 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter 2 lt 2 23 IAT IAT IA LIA IA IA Power source Frequency 2 mode 2 voltage 1 2 2 Frequency 4 mode 2 2 Frequency 8 mode 2 Low speed mode On chip oscillator mode Power source voltage VL1 input voltage Voltage multiplier is used A D converter reference voltage Analog power source voltage Analog input voltage ANo AN7 H input voltage 0 07 10 17 P24 P27 P30 P37 P41 P43 5 57 P60 CM4 0 P61 P65 P72 P74 H input voltage P20 P23 P40 P42 P44 P47 P62 P64 P66
49. 8 Hp 22 5 22 8 23 1 He 16 5 16 8 17 1 3 05 0 0 1 0 2 bp 0 3 0 35 0 45 0 13 0 15 02 e 0 10 0 65 0 8 0 95 y 0 10 20 0 8 Ze 1 0 L 0 4 0 6 0 8 3805 JEITA Package Code RENESAS Code Previous Code MASS Typ P LQFP80 12x12 0 50 PLQPO080KB A 80P6Q A 0 5g Index mark Terminal cross section NOTI o L pest 8 Li Detail F 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET Reference Dimension in Millimeters Symbol Min Nom D 119 12 0 12 1 11 9 12 0 12 1 14 Hp 13 8 14 0 14 2 13 8 14 0 14 2 17 01 0 2 bp 0 15 0 20 0 25 b 0 18 0 09 0 145 0 20 1 0 125 9 0 eA 10 05 x 0 08 y 0 08 Zp 1 25 Ze 125 L 03 0 5 07 Ly 10 Rev 3 04 20 2008 Page 121 of 134 13 NE SAS REJ03B0158 0304 3805 APPENDIX Note on Programming 1 Processor Status Register 1 Initializ
50. 9 9 P64 INT2 LED2 P63 TXOUT2 P74 PWM 1 T40UT gt 5 P73 PWMo T30uT 4 gt 16 P72 T20UT CKOUT lt gt 17 67 1 P65 TXOUT1 Package type 80P6Q A Fig 81 Connection for standard serial I O mode 2 Rev 3 04 20 2008 89 01134 RENESAS REJ03B0158 0304 P71 C2 INT11 20 Connect oscillation circuit lindicates flash memory pin lt gt P16 SEG22 lt gt P17 SEG23 lt gt P3ysEG24 lt gt P31 SEG25 P32 SEG26 P33 SEG27 lt gt P34 SEG28 P35 SEG29 P36 SEG30 P37 SEG31 COM7 SEG32 gt COM6 SEG33 k COM5 SEG34 COM4 SEG35 COM3 come lt P70 C1 INT01 3805 Flash memory version 38D5 Group TVDD 1 gt Vcc 4 7 T RXD P41 TxD Po RxD C T SCLK gt P42 SCLK T PGM OE MD CNVss P43 BUSY RESET circuit RESET Vss AVss XOUT 53 Set the same termination as the single chip mode Note 1 For the programmer circuit the wiring capacity of each signal pin must not exceed 47pF Fig 82 When using programmer in standard serial I O mode 1 of Suisei Electronics System Co LTD connection example Rev 3 04 20 2008 900f 134 RENESAS REJ03B0158 0304 3805 Flash memory version 38D5 Group P41 TxD 4 RxD
51. ADKEY selection bit to SE When the ADKEY enable bit of the AD control register is 1 the analog input pin selection bits become invalid Please do not write 0 in the AD conversion completion bit by the program during ADKEY enabled state ADKEY Control Circuit In order to obtain a more exact conversion result by the A D conversion with ADKEY execute the following set the input to the ADKEY pin into a steep falling waveform stabilize the input voltage within 8 clock cycles 1 at f XIN 8 MHz after the input voltage is under VIL The threshold voltage with an actual ADKEY pin is the voltage between VIH VIL In order not to make ADKEY operation perform superfluously in a noise etc in the state of the waiting for an input set the voltage of an ADKEY pin to 0 9 VCC or more When the following operations are performed the A D conversion operation cannot be guaranteed When the CPU mode register is operated during A D conversion operation When the AD conversion control register is operated during A D conversion operation When the STP or WIT instruction is executed during A D conversion operation 20 2008 51 of 134 q N S AS 3805 LCD DRIVE CONTROL CIRCUIT The 38D5 Group has the built in Liquid Crystal Display LCD drive control circuit consisting of the following LCD display RAM Segment output disable register LCD mode register Selector
52. P42 ESCLK input Serial clock input pin P43 Rev 3 04 ESPGMB input REJ03B0158 0304 Read program pulse input pin May 20 2008 67 of 134 RENESAS 3805 QzROM version 53S 4Ld gt F 20 95 9 1 gt 27 1253S9 S5 Ld 77 02503S Ld gt 153S Ld gt 57 8153S 2Ld 97 1938 14 27 9153S 0 Ld 87 153S 0d 4 gt 53S 90d gt 153S s0d gt 253S r0d 4 1193 50 gt 0193 204 gt 6935 1404 gt 993S 00d gt 4935 64 903S 2d 4 993S SZd gt 935 764 LMY EDAS EZd 4 2935 229 4 935 4 rMM oO3S 02d P47 SRbY2 KWs 40 4 P3o SEG24 lt gt P31 SEG25 lt gt P32 SEG 6 lt gt P33 SEGz7 lt gt 34 5 lt gt P35 SEG29 gt P36 SEG30 lt gt P37 SEG31 COM7 SEG32 gt COMe SEGs3 M38D5XGXFP COMS SEG34 4 5 lt gt lt gt 66 We lt gt Wi lt gt 68 Wo SRDY1 4 gt 69 K K P46 ScLK2 1 45 2 44 5 ESPGMB P43 P42 ScLk1 70 ESDA P41 TxD 4 gt 71 P40 RxD 72 P57 AN7 ADKEYo lt 75 5 4 gt 76 55 5 4 77 P54 AN4 78 P53 AN3 lt 79 P52 A
53. ROMCP1 b7b6 0 0 Protect enabled 0 1 Protect enabled 1 0 Protect enabled 1 1 Protect disabled Notes 1 When ROM code protect is turned on the internal flash memory is protected against readout or modification in parallel mode 2 When ROM code protect level 2 is turned on ROM code readout by a shipment inspection LSI tester etc also is inhibited 3 The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2 However no change can be made in parallel I O mode Use serial I O mode or other modes to change settings Fig 78 Structure of ROM code protect control address Rev 3 04 REJ03B0158 0304 20 2008 Page 83 01134 sENESAS 3805 ID Code Check Function Use this function in standard serial I O mode When the contents of the flash memory are not blank the ID code sent from the programmer is compared with the ID code written in the flash memory to see if they match If the ID codes do not match the commands sent from the programmer are not accepted The ID code consists of 8 bit data and its areas are FFD416 to FFDA16 Write a program which has had the ID code preset at these addresses to the flash memory Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 gt FFDBt16 ROM code protect control Interrupt vector area Fig 79 ID code store addresses Rev 3 04
54. Serial I O1 8 bit x 1 UART or Clock synchronized In frequency 2 mode Typ 32 mW Serial VOZ eene 8 bit x 1 Clock synchronized Vcc 5 V Xm 12 5 MHz 25 PWM 10 bit x 2 16 bit x 1 common to IGBT output 5 V f XIN 5 e i A D 10 bit x 8 channels Vcc 2 5 V stop 32 kHz Ta 25 C A D converter can be operated in low speed mode Power dissipation Flash memory version UMP VISUM VER AM M Bored In frequency 2 mode sss Typ 20 mW ROM correction function 32 bytes x 2 vectors Vcc 5 V 12 5 MHz Ta 25 LED direct drive port eem oce ais 6 mode uenia dm Typ 1 1 mW average current 15 mA peak current 30 mA total current 90 mA Vcc 2 7 V stop f XcIN 32 kHz Ta 25 i ren drive control circuit Operating temperature 20 to 85 INC M 1 2 1 3 Duty Static 2 3 4 8 Flash Memory Mode Common output iie Bea ei 4 8 Program Erase voltage Vcc 2 7 to 5 5 V Segment output 32 36 Program method Programming in unit of byte e Main clock generating circuit 1 Erase
55. Start at L output 1 Start at output 0 Count operation 1 Count stop Timer X output 1 selection bit P65 0 port 1 Timer X output 1 Timer X control register 2 TXCON2 address 002F 16 Timer X output 2 control bit P63 0 port 1 Timer X output 2 Timer X output 2 active edge switch bit 0 Start at L output 1 Start at H output Timer X dividing frequency selection bits b3b2 0 0 1 16 x p SOURCE 0 1 1 1 SOURCE 1 0 1 2 x p SOURCE 1 1 1 256 x p SOURCE Trigger for IGBT input control bit 0 Noise filter sampling clock x 1 External trigger delay time x 1 1 Noise filter sampling clock x 2 External trigger delay time x 1 2 Not used returns 0 when read Fig 30 Structure of Timer X related registers Rev 3 04 REJ03B0158 0304 CNTRo active edge switch bits b7b6 0 0 Count at rising edge in event counter mode Falling edge active for CNTRo interrupt Measure pulse width in pulse width measurement mode 0 1 Count at falling edge in event counter mode Rising edge active for CNTRo interrupt Measure L pulse width in pulse width measurement mode 1 0 Count at both edges in event counter mode 1 1 Both edges active for CNTRo interrupt SOURCE indicates the followings XIN input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mo
56. activated When the frequency divider is selected as the count source a one cycle delay of the maximum count source will result between when the timer is activated and when it starts counting or outputs the waveform The count source cannot be observed externally 2 Division Ratio for Timer 1 to 4 The division ratio is 1 1 when the value 0 to 255 is written to the timer latch 3 Switching Frequency and Count Source for Timer 1 to 4 X and Y Switch the frequency division or count source while the timer count is stopped This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes on chip oscillator mode XIN mode or low speed mode Be careful when changing settings in the CPU mode register 4 Setting Timer 1 and 2 When STP Instruction Executed Before executing the STP instruction first set the wait time at return 5 Setting Order to Timer 1 to 4 When switching the count source of timer 1 to timer 4 a narrow pulse may be generated at the count input which causes the timer count value to be undefined Also if the timers are used in cascade connection a narrow pulse may be generated at the output when writing to the pervious timer which causes the next timer count value to be undefined Thus set the value from timer 1 in order after setting the count source of timer 1 to timer 4 6 W
57. be executed by setting it to the ROM correction vectors Note Do not set address other than ROM area Use the JMP instruction 3 byte instruction to return the main program from the correction program Fig 49 ROM correction address register The correctable area is up to two There are two vectors for ROM correction Also ROM correction vector can be selected from the RAM area 000016 SFR area or ROM area by the ROM correction memory selection bit 004016 RAM area ROM area RC2 0 RC2 1 010016 ROM correction vector 1 Vector 1 address 010016 address F10016 Vector 2 address 012016 address F12016 012016 ROM correction vector 2 L 063 16 The ROM correction function is controlled by the ROM correction address 1 enable bit and ROM correction address 2 enable bit E If the ROM correction function is not used the ROM correction 800016 vector may be used as normal RAM ROM When using the 808016 ROM correction vector as normal RAM ROM make sure to set Reserved ROM area bits 1 and 0 in the ROM correction enable register to 0 Disable lt Notes gt 1 When using the ROM correction function set the 1001 correction vector 1 rection address registers and then enable the ROM correc tion with the ROM correction enable register 12016 ROM correction vector 2 2 Do not set addresses other than the RO
58. bits 0 to 5 of the timer 12 mode register are cleared to 0 XCIN XCOUT XOUT pow p mem The values of the timer 12 frequency divider selection register Note Insert a damping resistorit reguired M The resistance will vary depending on the oscillator and the oscillation drive are not changed capacity setting 5 1 n Use the value recommended by the maker of the oscillator Set the interrupt enable bits of the timer 1 timer 2 to be Also if the oscillator manufacturer s data sheet specifies that a feedback disabled 0 before executing the STP instruction resistor be added external to the chip though a feedback resistor exists on chip insert a feedback resistor between XIN and XOUT following the instruction Reference Set values according to your oscillator and system OSCSEL L of the QzROM version and flash memory version 000516 or more Fig 60 Ceramic resonator circuit example O1FF16 or more When an external interrupt is received the clock set according to the OSCSEL pin state starts oscillating in the QZROM version The operation mode at returning is decided by the clock that set according to the OSCSEL pin state Rf Open Bits 3 5 6 and 7 of CPUM and bit 0 of CPUM2 are forcibly External oscillation circuit changed by the OSCSEL pin
59. certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Elect
60. correction enable register 16 0016 Processor status register PS 1 FFFD16 contents 16 contents x Not fixed Depends on OSCSEL setting at the QZROM version In the flash memory version the CPU mode register 2 address 001116 is set to 0016 and the CPU mode register address 003 16 is set to E016 Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset they must be set Fig 59 Internal status at reset Rev 3 04 20 2008 62 01134 RENESAS REJ03B0158 0304 3805 CLOCK GENERATING CIRCUIT The oscillation circuit of 38D5 Group can be formed by connecting an oscillator capacitor and resistor between XIN and XOUT XCIN and XCOUT To supply a clock signal externally input it to the XIN pin and make the XOUT pin open The clocks that are externally generated cannot be directly input to XCIN Use the circuit constants in accordanc
61. data LRAMO address 084016 lt FF16 Set off data to LCD display RAM Set fixed data to LCD display RAM Fig 105 Processing example when writing data to LCD display RAM While LCD Turned On Rev 3 04 REJ03B0158 0304 20 2008 Page 130 01134 pLRENESAS 3805 3 Executing STP Instruction Executing the STP instruction sets the LCD enable bit bit 4 of LCD mode register address 001316 to 0 and the LCD panel turns off To turn the LCD panel on after returning from stop mode set the LCD enable bit to 1 4 VL3 Pin To use the LCD drive control circuit while VL3 is set to the voltage equal to Vcc apply the Vcc voltage to the VL3 pin and write 1 to the VL3 connection bit bit 1 of LCD mode register 2 address 001416 5 LCD Drive Power Supply Power supply capacitor may be insufficient with the division resistance for LCD power supply and the characteristic of the LCD panel In this case there is the method of connecting the bypass capacitor about 0 1 0 33 to VL1 VL3 pins The example of a strengthening measure of the LCD drive power supply is shown below Connect by the shortest possible wiring Connect the bypass capacitor to the VL1 pins as short as possible Referential value 0 1 0 33 uF Fig 106 Strengthening measure example of LCD drive power supply Notes on ROM Correction Function 1 Returning to Main Progr
62. disabled pins P4o to P43 operate as ordinary pins 1 Serial l O1 enabled pins P40 to P43 operate as serial I O pins SOURCE indicates the followings XIN input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode 1 N channel open drain output in output mode Rev 3 04 20 2008 47 0 134 stENESAS 158 0304 3805 Serial 1 02 The serial I O2 function be used only for clock synchronous serial IO For serial I O2 the transmitter and the receiver must use the Serial 1 02 control register same clock SIO2CON address 001D16 When the internal clock is selected as the operating clock a write s signal to the serial I O2 register initializes serial I O2 and Clock sesetan pite transmission reception starts 00 49SOURCE 8 0 SOURCE 16 SOURCE 32 SOURCE 64 Not available Not available SOURCE 128 9SOURCE 256 When the external clock is selected as the operating clock a write signal to the serial I O2 register initializes the serial I O2 counter and transmission reception is enabled Inputting the external clock starts transmission reception To write to the serial 1 02 register when the external clock is selected as the operating clock perform writing while SCLK2 is set to Serial 1 02 port selecti
63. e Frequency Divided For Timer revised Notes on Timer 1 to Timer 4 gt 2 Writing to Timer 2 Timer Timer 4 2 Write Timer 2 Timer 3 Timer4 Fig 28 Figure title is revised Timer X output 1 edge switch bit Timer X output 1 active edge switch bit 4 7 REVISION HISTORY 38D5 Group Data Sheet Date Description 3 01 Aug 08 2007 Fig 28 Timer X output 2 edge switch bit gt Timer X output 2 active edge switch bit e Frequency Divided For Timer revised timer X1 output edge switch bit timer X output 1 active edge switch bit timer X2 output edge switch bit timer X output 2 active edge switch bit 6 Pulse Width Measurement Mode revised 1 Write Order to Timer X description added 2 Read Order to Timer X revised 8 Write to Timer X revised 7 When Timer X Pulse Width Measurement Mode Used added Fig 30 Timer X output 1 edge switch bit gt Timer X output 1 active edge switch bit e Timer Y revised 5 Real Time Port Control moved from Notes on Timer Y gt e Real Time Port Control moved to e Timer Y e Serial 1 02 revised Fig 39 Serial I O counter 2 Serial 1 02 counter Serial I O shift register 2 Serial l O2 register Serial 2 Operation added Fig 40 revised Comparator and Control Circuit revised ADKEY function moved from the next page Fig 43 Added the note number to each register Do not write 1 Not used do not write 1 Voltage Multiplier revised e Bias Cont
64. f XiN 24MHz Vec 2 7V f XiN 4MHz f XiN 24MHz in WIT state f XIN 2MHz Frequency 4 mode Vcc 5 0V f XIN 12 5MHz f XIN 12 5MHz WIT state f XiN 24MHz Vec 2 7V 8 2 f XiN 28MHz WIT state f XIN 4MHz Frequency 8 mode Vcc 5 0V f XIN 12 5MHz f XiN 212 5MHz in WIT state f XIN 4MHz Vec 2 7V f XIN 8MHz f XiN 28MHz in WIT state f XiN 4MHz Low speed mode Vcc 5 0V f XiN stop in WIT state 25 85 2 7 f XIN stop in WIT state Ta 25 C Ta 85 C On chip oscillator mode Vcc 5 0V f XiN stop Vcc 2 7V Vcc 2 7V in WIT state All oscillations stopped 25 in STP state Ta 85 C Current increased f XiN 212 5MHz Vcc 5V at A D converter operating in frequency 2 4 or 8 mode f XIN stop Vcc 5V in on chip oscillator operating f XIN stop Vcc 5V in low speed mode A D Converter Characteristics Table 40 A D converter recommended operating condition Vcc 2 7 to 5 5 V Ta 20 to 85 output transistors in cut off state unless otherwise noted Limits Parameter Test conditions Max Power source voltage 5 5 H input voltage ADKEYo Voc L input voltage ADKEYo 0 7 x Vcc 0 5 AD converter clock frequ
65. gt gt gt gt gt gt COMo COM COMo COM COM COMo 2 COM COMo 2 COM COMo 2 ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF 94 gt 4 gt gt gt gt gt gt gt gt gt gt 4 gt COM COMo COM COMo COM COMo COM COM COMo COMo COMo Fig 47 LCD drive waveform 1 2 bias Rev 3 04 20 2008 Page560f134 RENESAS REJ03B0158 0304 3805 Internal signal LCDCK timing 1 8 duty Voltage level COMo COM4 COMs COMs COM7 SEGo OFF ON OFF ON OFF ON OFF ON lt _ gt gt gt gt gt gt 4 gt gt gt gt gt gt gt 5 4 2 COM COMo COMe COMs 2 COM 1 4 COMo SEGo 1 3 duty
66. high order reload latch Switch the frequency division or count source while the timer count is stopped This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes on chip oscillator mode XIN mode or low speed mode Be careful when changing settings in the CPU mode register 20 2008 Page400f134 qQ N S AS 3805 4 Set of Timer X Mode Register Set the write control bit of the timer X mode register to 1 write to the latch only when setting the IGBT output and PWM modes Output waveform simultaneously reflects the contents of both registers at the next underflow after writing to the timer X register high order 5 Output Control Function of Timer X When using the output control function and INT2 in the IGBT output mode set the levels of INT1 and INT2 to H in the falling edge active or to L in the rising edge active before switching to the IGBT output mode 6 Switch of CNTRo Active Edge When the CNTRo active edge switch bits are set at the same time the interrupt active edge is also affected When the pulse width is measured set the bit 7 of the active edge switch bits to 0 bo 7 When Timer X Pulse Width Measurement Mode Used When timer X pulse width measurement mode is used enable the event counter w
67. in the frequency 2 mode 2 32 ns the frequency 2 mode 3 When bit 6 of address 001A16 is 1 clock synchronous Divide this value by four when bit 6 of address 001A16 is 0 UART Rev 3 04 20 2008 116 of 134 42 N S AS REJ03B0158 0304 3805 Table 44 Timing requirements 2 Vcc 2 7 to 4 0 V Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter FLASH MEMORY VERSION iw RESET Reset input L pulse width tc XIN Main clock input cycle time XIN input tWH XIN Main clock input pulse width 50 Main clock input L pulse width 50 CNTRo CNTR input cycle time 1000 Vcc CNTRo CNTR input H pulse width tc CNTR 2 20 CNTRo CNTR input L pulse width tc CNTR 2 20 1 INT10 INT11 INT2 input pulse width 230 INToo 1 INT10 INT11 INT2 input L pulse width 230 tc SCLk1 Serial 1 01 clock input cycle time 2000 tWH SCLK1 Serial 1 01 clock input pulse width 950 Serial 1 01 clock input L pulse width 950 tsu RXD ScLk1 Serial 1 01 input setup time 400 th ScLk1 RxD Serial 1 01 input hold time 200 tc ScLk2 Serial 1 02 clock input cycle time 2000 tWH SCLK2 Serial 1 02 clock input H pul
68. includes key input interrupt Timer 8 bit x 4 16 bit x 2 Serial 1 1 8 bit x 1 UART or Clock synchronized Serial 1 02 8 bit x 1 Clock synchronized PWM 10 bit x 2 16 bit x 1 common to IGBT output A D converter 10 bit x 8 operated in low speed mode Watchdog timer 8 bit x 1 ROM correction function 32 bytes x 2 vectors LED direct drive port 6 average current 15 mA peak current 30 mA total current 90 mA LCD drive control Bias 1 2 1 3 circuit Duty Static 2 3 4 8 Common output 4 8 Segment output 32 36 Main clock generating circuits Built in connect to external ceramic resonator or on chip oscillator Sub clock generating circuits Built in connect to external quartz crystal oscillator Power source voltage In frequency 2 mode 4 5t0 5 5 V QzROM version 1 4 0 to 5 5 V 2 0 to 5 5 V 1 8t0 5 5 V 4 5 to 5 5 V 2 0 to 5 5 V 1 8 10 5 5 V 4 5 to 5 5 V 2 0 to 5 5 V 1 8 10 5 5 V In low speed mode 1 8t0 5 5 V Power source voltage In frequency 2 mode 4 5 to 5 5 V Flash memory version 1 4 0 to 5 5 V 2 7 to 5 5 V 4 5t0 5 5 V 2 7 to 5 5 V 4 5 to 5 5 V 2 7 t0 5 5 V In low speed mode 2 7 to 5 5 V x 2 2 2 fH 2 2 In frequency 4 mode 2 2 2 In frequency 8 mode 2 IAT IAF IAT IAT IAP IAT IAP IAT IAT IA 2
69. input level CMOS 3 state output structure O direction register allows each pin to be individually programmed as either input or output Pull up control is enabled in a bit unit P62 to P67 6 bits are enabled to output large current for LED drive Sub clock generating I O pins oscillator connected External interrupt pin Timer X output pin External interrupt pin Timer X output pin Timer X Timer Y output pins External interrupt pins P70 C1 INTo1 P71 C2 INT11 Input port P7 2 bit input port CMOS input level External interrupt pins External capacitor connect pins for a voltage multiplier of LCD P72 T20uT CKOUT P73 PWMo TsouT P74 PWM1 T40UT port P7 3 bit I O port CMOS compatible input level CMOS 3 state output structure O direction register allows each pin to be individually programmed as either input or output Pull up control is enabled in 3 bit unit Clock output pin Timer 2 output pin PWM output pins Timer 3 output pin Timer 4 output pin OSCSEL Only 7 version Oscillation start selection pin Whether oscillation starts by an oscillator between the XiN and Xour pins or an on chip oscillator is selected e VPP power source input in the QZROM writing mode CNVss Only flash memory version CNVss Pin for controlling the oper
70. instructions can be used The central processing unit CPU has six registers Figure 6 shows the 740 Family CPU register structure Accumulator A The accumulator is an 8 bit register Data operations such as arithmetic data transfer etc are executed mainly through the accumulator Index Register X X The index register X is an 8 bit register In the index addressing modes the value of the OPERAND is added to the contents of register X and specifies the real address Index Register Y Y The index register Y is an 8 bit register In partial instruction the value of the OPERAND is added to the contents of register Y and specifies the real address Fig 6 740 Family CPU register structure Rev 3 04 REJ03B0158 0304 Stack Pointer S The stack pointer is an 8 bit register used during subroutine calls and interrupts This register indicates start address of stored area stack for storing registers during subroutine calls and interrupts The low order 8 bits of the stack address are determined by the contents of the stack pointer The high order 8 bits of the stack address are determined by the stack page selection bit If the stack page selection bit is 0 the high order 8 bits becomes 00167 If the stack page selection bit is 1 the high order 8 bits becomes 0116 The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 7 Table 7 sh
71. lt M S Note1 Condition for acceptance of an interrupt request here Interrupt disable flag is 0 and Interrupt enable bit corresponding to each interrupt source is 1 Fig 7 Register push and pop at interrupt generation and subroutine call Table 7 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP Rev 3 04 20 2008 130 134 RENESAS REJ03B0158 0304 3805 Processor Status Register PS The processor status register is an 8 bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation Branch operations can be performed by testing the Carry C flag Zero Z flag Overflow V flag or the Negative N flag In decimal mode the Z V N flags are not valid Table 8 Bit 0 Carry flag C The C flag contains a carry or borrow generated by the arithmetic logic unit ALU immediately after an arithmetic operation It can also be changed by a shift or rotate instruction Bit 1 Zero flag Z The Z flag is set to 1 if the result of an immediate arithmetic operation or a data transfer is 0 and set to 0 if the result is anything other than 0 Bit 2 Interrupt disable flag The I flag disables all interrupts except for the
72. mode register e Timer 1 Timer 2 The count source for timer 1 and timer 2 can be set using the timer 12 mode register XCIN may be selected as the count source If XCIN is selected count operation is possible regardless of whether or not the XIN input oscillator or the on chip oscillator is operating In addition the timer 12 mode register can be used to output from the P72 T20UT pin a signal to invert the polarity every time timer 2 underflows At reset all bits of the timer 12 mode register are set to 0 timer 1 is set to 16 and timer 2 is set to 0116 When executing the STP instruction previously set the wait time at return e Timer 3 Timer 4 The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register Also by the timer 34 mode register each time timer 3 or timer 4 underflows the signal of which polarity is inverted can be output from P73 T30UT pin or P74 T40UT pin Timer 3 PWMo Mode Timer 4 PWM1 Mode A PWM rectangular waveform corresponding to the 10 bit accuracy can be output from the P73 PWMo pin and P74 PWM1 by setting the timer 34 mode register and PWMOI register refer to Figure 26 One output pulse is the short interval Four output pulses are the long interval The is the value set in the timer 3 address 002216 or the timer 4 address 002316 The ts is one period of timer 3 or timer 4 count source width of the short i
73. must be stabilized Be especially careful when turning the power on and returning from stop mode Refer to the clock state transition diagram for a transition between each mode Also set the frequency in the condition that f XIN gt 3 When XIN mode is not used the XIN XOUT oscillation or external clock input to XIN is not performed connect XIN to Vcc through a resistor 3 Oscillation Stabilization Before executing the STP instruction set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch low order 8 bits of timer 1 and high order 8 bits of timer 2 Referential values Set values according to your oscillator and system e OSCSEL L in the flash memory versions its ves in aos teste 000516 or more O1FF16 or more 4 Low Speed Mode Xin Mode To use low speed mode or XIN mode wait until oscillation stabilizes after enabling the XIN XOUT and XCIN XCOUT oscillation then switch to the mode 20 2008 131 01134 pLRENESAS 3805 Notes on Flash Memory Mode CPU Rewrite Mode 1 Operating Speed During CPU rewrite mode set the system clock to 4 0 MHz or less using the main clock division ratio selection bits bits 6 and 7 of address 0038 16 2 Prohibited Instructions During CPU rewrite mode the instructions which reference dat
74. not valid and the above values are set Bits 7 to 5 can be rewritten only once after releasing reset After rewriting it is disable to write any data to this bit This bit becomes 0 after reset Standard Operation of Watchdog Timer The watchdog timer is in the stop state at reset and the watchdog timer starts to count down by writing an optional value in the watchdog timer control register An internal reset occurs at an underflow of the watchdog timer Then reset is released after the reset release time is elapsed the program starts from the reset vector address Normally writing to the watchdog timer control register before an underflow of the watchdog timer is programmed If writing to the watchdog timer control register is not executed the watchdog timer does not operate When reading the watchdog timer control register is executed the contents of the high order 5 bit counter the count source selection bit 2 bit 5 the STP instruction function selection bit bit 6 and the count source selection bit bit 7 are read out Watchdog timer count source selection bit Watchdog timer count Source selection bit 2 0 Bit 6 of Watchdog Timer Control Register 1 When bit 6 of the watchdog timer control register is 0 the MCU enters the stop mode by execution of STP instruction Just after releasing the stop mode the watchdog timer restarts counting Note 1 When executing the WIT instruction t
75. of each bit in status register Each bit of SRD bits Status name Erase status SR5 The erase status indicates the operating status of erase operation If an erase error occurs it is set to 1 When the erase status is cleared it is reset to 0 Program status SR4 The program status indicates the operating status of write operation When a write error occurs it is set to 1 The program status is reset to 0 when it is cleared If 1 is written for any of the SR5 and SR4 bits the read array program and block erase commands are not accepted Before executing these commands execute the clear status register command 5016 and clear the status register Also if any commands are not correct both SR5 and SR4 are set to 1 Definition 1 0 Sequencer status Ready Busy Reserved Erase status Terminated in error Terminated normally Program status Terminated in error Terminated normally Reserved Reserved Reserved Reserved Rev 3 04 REJ03B0158 0304 20 2008 Page 810f134 RENESAS 3805 Full Status Check By performing full status check it is possible to know the execution results of erase and program operations Figure 77 shows a full status check flowchart and the action to be taken when each error occurs Read status register Execute the clear status register command 5016 c
76. or 8 mode Internal on chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode 20 2008 43 01134 RENESAS 3805 SERIAL INTERFACE 1 Clock Synchronous Serial I O Mode SERIAL 1 01 Clock synchronous serial I O1 mode can be selected by setting Serial I O1 can be used as either clock synchronous the serial I O mode selection bit of the serial I O1 control register asynchronous UART serial I O A dedicated timer is also 19 p provided for baud rate generation For clock synchronous serial I O1 the transmitter and the receiver must use the same clock If an internal clock is used transfer is started by a write signal to the TB RB Data bus Address 001816 Serial 1 01 control register Address 001A16 Receive buffer register Receive buffer full flag RBF P40 RxD 3 Receive shift register Receive interrupt request RI A Shift clock Clock control circuit P42 ScLk1 4 Serial 1 01 ew x clock selection bit BRG count source selection bit Frequency division ratio 1 1 Baud rate generator 1 4 gt t Address 001C16 8 1 4 4 1 Falling edge detector Clock control circuit Shift clock gt Transmit shift completion flag TSC _ _ Transmit inter
77. output control with pins INT1 and INT2 are not used Except for those this mode operates just as in the IGBT output mode The period of PWM waveform is specified by the timer X set value In the case that the timer X output 1 active edge switch bit is 0 the interval is specified by the compare register 1 set value In the case that the timer X output 2 active edge switch bit is 0 the interval is specified by the compare registers 2 and 3 set values When using this mode set the port sharing the pin used as TXOUT1 TXOUT2 function to output mode Do not write 1 to the timer X register extension when using the PWM mode 5 Event Counter Mode The timer counts signals input through the CNTRo pin In this mode timer X operates as the 18 bit counter by setting the timer X register extension When using this mode set the port sharing the CNTRo pin to input mode In this mode the window control can be performed by the timer underflow When the bit 5 data for control of event counter window of the timer X mode register is set to 1 counting is stopped at the next timer 1 underflow When the bit is set to 0 counting is restarted at the next timer 1 underflow 6 Pulse Width Measurement Mode In this mode the count source is the output of frequency divider for timer In this mode timer X operates as the 18 bit counter by setting the timer X register extension When the bit 6 of t
78. register 2 Interrupt edge selection register Timer X mode register Timer X control registers 1 2 Timer Y function input PULL register 2 Timer Y mode register P70 C1 INTO1 P71 C2 INT11 Port P7 P72 T20UT CKOUT P73 PWMo T30UT P74 PWM1 T40UT Input individual bits CMOS compatible input level External interrupt input LCD voltage multiplier input Interrupt edge selection register LCD mode registers 1 2 Input Output individual bits CMOS compatible input level CMOS 3 state output clock output Timer 2 output Timer 3 output Timer 4 output PWM output PULL register 3 Timer 1234 mode register Timer 1234 frequency division register Clock output control register Common COM4 SEG35 COM7 SEG32 Common Segment Rev 3 04 REJ03B0158 0304 LCD common output LCD common Segment output LCD common output LCD Segment output 20 2008 Page 210f 134 sLRENESAS LCD mode register 1 2 3805 1 Ports P1 P24 P27 2 Ports P20 P23 VL3 VL2 34 VL3 VL2 3 Segment data Segment data Segment output disable bit 4 o 4 Segment output disable bit 4 4 Direction Direction register register
79. registers cannot be read This means it is impossible to use the LDA instruction memory operation instruction when the T flag is 1 addressing mode using direction register values as qualifiers and bit test instructions such as BBC and BBS It is also impossible to use bit operation instructions such as CLB and SEB and read modify write instructions to direction registers including calculations such as ROR To set the direction registers use instructions such as LDM or STA Serial Interface In clock synchronous serial I O if the receive side is using an external clock and it is to output the SRDY signal set the transmit enable bit the receive enable bit and the SRDY output enable bit to 1 Serial I O continues to output the final bit from the TxD pin after transmission is completed Rev 3 04 REJ03B0158 0304 A D Converter The comparator is constructed linked to a capacitor The conversion accuracy may be low because the charge is lost if the conversion speed is not enough Accordingly set f XIN to at least 500kHz during A D conversion in the XIN mode Also do not execute the STP or WIT instruction during an A D conversion In the low speed mode since the A D conversion is executed by the on chip oscillator the minimum value of f XIN frequency is not limited LCD Drive Control Circuit Execution of the STP instruction sets the LCD enable bit bit 4 of the LCD mode register to 0 and the L
80. request bit for an interrupt request generated during period 2 is set to 1 at timing point IR1 or IR2 The timing point at which the bit is set to 1 varies depending on conditions When two or more interrupt requests are generated during the period 2 each request bit may be set to 1 at timing point IR1 or IR2 separately Fig 22 Timing of interrupt request generation interrupt request bit and interrupt acceptance Rev 3 04 20 2008 Page320f134 stENESAS REJ03B0158 0304 3805 Key Input Interrupt Key on Wake Up interrupt is shown in Figure 23 where an interrupt request is A key input interrupt request is generated by detecting the falling generated by pressing one of the keys consisted as an active low edge from any pin of ports P20 P23 P44 P47 that have been set key matrix which inputs to ports P44 P47 to input mode In other words it is generated when AND of input level goes from 1 to 0 An example of using a key input Port PXx L level output Segment output Port P2 direction disable register 1 egister bit 3 1 Bit 3 1 Key input control Key input interrupt request register bit 7 1 x Port P23 T latch D P23 output L T 4 i gt Segment output Port P22 direction disable register 1 register bit 2 1 Bit 2 1 Key input control Poit Pos register bit 6 1 TE i3 Segment ou
81. speed on chip oscillator mode excluded 4 0V lt Voc lt 4 5V 4 0 2 0 lt Vcc lt 4 0V Vcc Parameter Test conditions NOTE 1 Confirm the recommended operating condition for main clock input frequency Rev 3 04 20 2008 Page 103 of 134 42 N S AS REJ03B0158 0304 3805 QzROM VERSION Table 29 A D converter characteristics Vcc 2 0 to 5 5 V 20 to 85 C output transistors in cut off state low speed on chip oscillator mode included unless otherwise noted Limits Typ Parameter Test conditions Resolution Absolute accuracy 10bitAD 4 5 lt Vcc x 5 5V quantification error mode AD conversion 2 f XiN 8 lt 6 25MHz excluded 4 0V lt Vcc lt 4 5V AD conversion clock f XIN 2 f XiN 8 lt 4MHz 2 2 lt Voc lt 4 0V AD conversion clock f XIN 2 f XiN 8 lt VccMHz 2 0 lt Voc lt 5 5V AD conversion clock f OCO 8 f OCO 32 8bitAD 4 5 lt Vcc lt 5 5V mode conversion clock f XIN 2 f XiN 8 lt 6 25MHz 4 0V lt Voc x 4 5V AD conversion clock f XIN 2 f XiN 8 lt 4MHz 2 2 lt Voc lt 4 0V AD conversion clock f XIN 2 f XiN 8 lt VccMHz 2 0V lt Vcc lt 2 2V AD conversion 2 f XiN 8 x 6 11 2 2 0V lt Vcc lt 2 2V AD conversion 8 x VccMHz 2 0V lt Vcc lt 5 5V AD conversion clock f OCO 8
82. the CNTR1 active edge switch bits 16 Read from Write to Timer Y 1 When reading from writing to timer Y read from write to both the high order and low order bytes of timer Y To read the value read the high order bytes first and the low order bytes next To write the value write the low order bytes first and the high order bytes next Writing reading should be preformed in 16 bit units If write read operation is changed in progress normal operation will not be performed 2 Timer Y can select either writing data to both the latch and the timer at the same time or writing data only by the timer Y write control bit b0 in the timer Y control register address 003916 When writing to the latch only if a value is written to the timer Y address the value is set into the reload latch and the timer is updated at the next underflow After a reset release if a value is written to the timer Y address the value is set into the timer and the timer latch at the same time because they are written simultaneously When writing to the latch only if the write timing to the high order reload latch and the underflow timing are almost the same the value is set into the timer and the timer latch at the same time At this time count is stopped during write operation to the high order reload latch 3 Switch the frequency division or count source while the timer count is stopped This also applies when the frequency divider output is selecte
83. the flash memory 4 Watchdog timer If the watchdog timer has been already activated internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase 5 Reset Reset is always valid The MCU is activated using the boot mode at release of reset in the condition of CNVss so that the program will begin at the address which is stored in addresses FFFC16 and 16 of the boot ROM area Rev 3 04 20 2008 78 01134 RENESAS REJ03B0158 0304 3805 Software Commands Table 18 lists the software commands After setting the CPU rewrite mode select bit to 1 execute a software command to specify an erase or program operation Each software command is explained below Read Array Command FF16 The read array mode is entered by writing the command code FF16 in the first bus cycle When an address to be read is input in one of the bus cycles that follow the contents of the specified address are read out at the data bus Do to D7 The read array mode is retained until another command is written Read Status Register Command 7016 When the command code 7016 is written in the first bus cycle the contents of the status register are read out at the data bus Do to D7 by a read in the second bus cycle The status register is explained in the next section Clear Status Register Command 5016 This command is
84. the serial transmit interrupt request bit is automatically set to 1 When not requiring the interrupt occurrence synchronous with the transmission enabled take the following sequence 1 Set the serial I O1 transmit interrupt enable bit to 0 disabled 2 Set the transmit enable bit to 1 3 Set the serial I O1 transmit interrupt request bit to 0 after or more instructions have been executed 4 Set the serial I O1 transmit interrupt enable bit to 1 enabled 20 2008 Page460f134 RENESAS 3805 Serial 1 status register SIO1STS address 001916 Transmit buffer empty flag TBE 0 Buffer full 1 Buffer empty Receive buffer full flag RBF 0 Buffer empty 1 Buffer full Transmit shift completion flag TSC 0 Transmit shift in progress 1 Transmit shift completed Overrun error flag OE 0 No error 1 Overrun error Parity error flag PE 0 No error 1 Parity error Framing error flag FE 0 No error 1 Framing error Summing error flag SE 0 U FE 1 U U FE 0 1 Not used returns 1 when read UART control register 50 address 001816 Character length selection bit CHAS 0 8 bits 1 7 bits Parity enable bit PARE 0 Parity checking disabled 1 Pa
85. this 1 XCIN XCOUT selected bit to 1 to stop the oscillation Port Xc switch bit 11 27 In on chip oscillator mode even if this bit is set to 1 the on chip 0 I O port function Oscillation stop oscillator oscillation does not stop in the flash memory version but 1 0 oscillating function stops in the QzROM version XIN XOUT oscillation stop bit 12 m 0 Oscillatin In low speed mode the XCIN XCOUT oscillation stops if the port Xc 1 Stopped 9 switch bit is set to 0 Main clock division ratio selection bit In XIN mode the XIN XOUT oscillation does not stop even if the XIN Valid only when CM3 0 13 Xour oscillation stop bit is set to 1 b7 b8 12 5 MHz lt lt 16 MHz is not available in the frequency 2 0 0 f XIN 2 frequency 2 mode mode 0 1 f XIN 8 frequency 8 mode In the flash memory version set the on chip oscillator stop bit to 1 1 0 f XIN 4 frequency 4 mode oscillation stops because OCO is in the state set by the setting 1 1 On chip oscillator value of the on chip oscillator stop bit Fig 63 State transitions of system clock Rev 3 04 20 2008 Page660f134 RENESAS REJ03B0158 0304 3805 QzROM Writing Mode In the QzROM writing mode the user ROM area can be rewritten while the microcomputer
86. used to clear the bits 4 and SR5 of the status register after they have been set These bits indicate that operation has ended in an error To use this command write the command code 5016 in the first bus cycle Program Command 4016 Program operation starts when the command code 4016 is written in the first bus cycle Then if the address and data to program are written in the 2nd bus cycle program operation data programming and verification will start Whether the write operation is completed can be confirmed by read status register or the RY BY status flag To read the status register write the read status register command 7016 The status register bit 7 SR7 is set to 0 at the same time the program starts and returned to 1 upon completion of the program The read status mode remains active until the read array command 16 is written Table 18 List of software commands CPU rewrite mode The RY BY status flag is set to 0 during program operation and 1 when the program operation is completed as is the status register bit 7 SR7 At program end program results can be checked by reading the status register Write 4016 44 Write address Write Write data Read status register YES Program completed Fig 75 Program flowchart cycle First bus cycle Second bus cycle command number Mode Address B br Mode Address Bu b R
87. 0 E W enable bit 9 0 E W disabled 800016 16 1 enabled 800016 16 Not used return 0 when read Not used return 1 when read Not used return 0 when read Notes 1 For this bit to be set to 1 the user needs to write a 0 and then a 1 to it in succession For this bit to be set to 0 write 0 only to this bit 2 Effective only when the CPU rewrite mode select bit 1 Fig 73 Structure of flash memory control register 2 Table 17 State of E W inhibition function User block 0 User block 1 User block 0 User block 1 Data block E W enable bit E W enable bit Addresses 800016 to FFFF16 Addresses 180016 to 7FFF16 Addresses 100016 to 17FF16 0 0 E W disabled E W disabled E W enabled 0 1 E W disabled E W enabled E W enabled 1 0 E W enabled E W disabled E W enabled 1 1 E W enabled E W enabled E W enabled Figure 74 shows a flowchart for setting releasing CPU rewrite mode Start Single chip mode Boot mode Set CPU mode register v Transfer CPU rewrite mode control program to internal RAM Jump to control program transferred to internal Subsequent operations are executed by control program in this RAM v Set CPU rewrite mode select bit to 1 by writing 0 and then 1 in succession v Set user block 0 E W enable bit to 1 by writing 0
88. 0 to 2 the bias control bit bit 3 the LCD circuit divider division ratio selection bits bits 5 and 6 and the LCDCK count source selection bit bit 7 of the LCD mode register 1 to 0 or 1 3 Set the VL3 connection bit bit 1 of the LCD mode register 2 LM2 to 1 4 Set the voltage multiplier control bit 10 of the LCD mode register 2 to 1 When voltage is input to the VL1 pin during operating the voltage multiplier voltage that is twice as large as VL1 occurs at the VL2 pin and voltage that is three times as large as VL1 occurs at the VL3 pin The voltage multiplier is controlled by the voltage multiplier control bit bit 0 of the LCD mode register 2 In addition when the voltage multiplier is used set the voltage multiplier control bit to 1 voltage multiplier enabled after the voltage 1 3 V or more and 2 1 V or less When the voltage multiplier is not used set the VL3 connection bit to 1 open and apply the suitable voltage for the power supply input pins for LCD VL1 VL3 When VL3 connection bit is set to be open VL3 pin is in a high impedance state When the voltage multiplier is used set the LCDCK frequency to 100 Hz or more The on chip oscillator cannot be used for LCDCK In a system where the multiplier circuit is used a multiplier capacitor is externally connected between the C1 and C2 pins set the voltage multiplier circuit control bit to 1 voltage multiplier
89. 01 synchronous clock selection bit d gt Clock control circuit 1 BRG count source selection bit SOURCE 4 1 4 P41 TxD Frequency division ratio 1 n 1 Baud rate generator Address 001 16 ST SP PA generator Character length selection bit 4 1 Transmit shift register Mu a ransmit bu Transmit buffer register Address 001B16 Transmit shift completion flag TSC Transmit interrupt source selection bit Address 001816 Serial 1 01 status register Transmit interrupt request TI fer empty flag TBE Address 001916 Data bus Note1 SOURCE indicates the followings input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode Fig 35 Block diagram of UART serial l O1 Transmit or receive clock Transmit buffer register write signal Serial output TxD Receive buffer register read signal Serial input RxD Notes 1 Error flag detection occurs at the same time that the RBF flag becomes 1 at 1st stop bit during reception 2 As the transmit interrupt TI when either the TBE or TSC flag becomes 1 can be selected to occur depending on the setting of the transmit interrupt source selection bit TIC of the serial I O control register 3 T
90. 1 Pin name Signal name Function Vcc Vss Power supply Apply 2 7 to 5 5 V to the Vcc pin and 0 V to the Vss pin CNVss CNVss After input of port is set input H level RESET Reset input Reset input pin To reset the microcomputer RESET pin should be held at an L level for 16 cycles or more of XIN XIN Clock input XouT Clock output Connect an oscillation circuit between the XiN and Xour pins As for the connection method refer to the clock generating circuit AVss Analog power supply input Connect AVss to Vss VREF Reference voltage input Apply reference voltage of A D convertor to this pin 00 07 P10 P17 P20 P27 P30 P37 40 47 50 57 7 P72 P74 port Input L or level or keep open P40 RxD input Serial data input pin P41 TxD output Serial data output pin P42 input Serial clock input pin P43 BUSY output BUSY signal output pin Table 21 Description of pin function Flash Memory Standard Serial I O Mode 2 Pin name Signal name Function Vcc Vss Power supply Apply 2 7 to 5 5 V to the Vcc pin and 0 V to the Vss pin CNVss CNVss After input of port is set input H level RESET Reset input Reset input pin To reset the microcomputer RESET pin should be held at an L level for 16 cycles or more of X
91. 112 gt 1 1 Interrupt request ts One period of Timer 3 count source or Timer 4 count source PWM01 register address 002416 2 bit value corresponding to PWMO bits 0 1 bits 2 3 Fig 26 Waveform of PWMO PWM1 Rev 3 04 REJ03B0158 0304 20 2008 36 01134 sRENESAS 3805 bo Timer 12 mode register T12M address 002516 Timer 1 count stop bit 0 Count operation 1 Count stop Timer 2 count stop bit 0 Count operation 1 Count stop Timer 1 count source selection bits b3b2 0 0 Frequency divider for Timer 1 0 1 f XoiN 1 0 Underflow of Timer Y 1 1 Notavailable Timer 2 count source selection bits b5b4 0 0 Underflow of Timer 1 0 1 f Xcin 1 0 Frequency divider for Timer 2 1 1 Not available Timer 2 output selection bit P72 0 I O port 1 Timer 2 output output edge switch bit 0 Start at L output 1 Start at H output 50 Timer 34 mode register T34M address 002616 L Timer 3 count stop bit 0 Count operation 1 Count stop Timer 4 count stop bit 0 Count operation 1 Count stop Timer 3 count source selection bit 0 Frequency divider for Timer 3 1 Underflow of Timer 2 Timer 4 count source selection bits b4b3 0 0 Frequency divider for Timer 4 0 1 Underflow of Timer 3 1 0 Underflow of Timer 2 11 Timer 3 operating mode selection bit 0 Timer mode
92. 12 Structure of ports PO to Not used do not write 1 Note1 The PULL register and segment output disable register affect only ports programmed as the input ports Fig 13 Structure of PULL register and segment output disable register Rev 3 04 20 2008 20 0134 stENESAS REJ03B0158 0304 3805 Table 9 Pin Name List of I O port function Input Output format Non port function Related SFRs 00 5 PO7 SEG15 Port PO Input Output individual bits CMOS compatible input level CMOS 3 state output P10 SEG16 P17 SEG23 Port P1 Input Output individual bits CMOS compatible input level CMOS 3 state output P20 SEGo KWa P23 SEG3 KW7 Port P2 P24 SEG4 P27 SEG7 Input Output individual bits CMOS compatible input level CMOS 3 state output P30 SEG24 P37 SEG31 Port Input Output individual bits CMOS compatible input level CMOS 3 state output LCD segment output Segment output disable register 0 Segment output disable register 2 Key input key on wakeup interrupt input Segment output disable register 1 Key input control register Segment output disable register 1 Segment output disable register 2 P40 RxD P41 TxD P42 SCLK1 P43 SRDY1 P44 SiN2 KWo P45 SoUT2 KW1 P46 SCLK2 KW2 P47 SRDY2 KW3 Port P4 Input Output individual bits CMOS compatible input l
93. 16 57344 200016 208016 61440 100016 108016 XXXX16 084016 086316 OFEO016 OFEF 6 OFFO16 100016 YYYY 6 ZZZZ16 EFFF16 FF0016 FFD416 FFDBte FFDCt6 FFFE16 FFFFi6 Reserved area LCD display RAM area Not used SFR area SFR area Reserved ROM area 128 bytes Reserved ROM ID code Reserved ROM area ROM code protect Interrupt vector area Reserved ROM area Note 1 This area is available in the flash memory version only 2 ROM correction vectors are assigned As for the details refer to the HOM CORRECTION FUNCTION 3 In the flash memory version programming and erase operations can be performed to reserved ROM areas Note that their areas are different from those in the QZROM version Fig 10 Memory map diagram Rev 3 04 REJ03B0158 0304 20 2008 Page 18 01134 sENESAS Zero page 2 Protect area 1 Special page 3805 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000816 000 16 000016 000 16 000 16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001816 00116 001016 001E16 001F 16 0 016 0 116 0 216 0 16 OFE416 0 516 0 16 OFE716 OFE816 0 916 16 0 16 0 16 OFED16 OFEE16 16 Port
94. 16 OFE016 OFFF16 100016 Internal flash memory area 60K bytes FFFF16 Fig 70 Block diagram of built in flash memory Rev 3 04 REJ03B0158 0304 140016 180016 800016 FFFF16 CPU Rewrite Mode In CPU rewrite mode the internal flash memory can be operated on read program or erase under control of the Central Processing Unit CPU In CPU rewrite mode only the User ROM area shown in Figure 70 can be rewritten the Boot ROM area cannot be rewritten Make sure the program and block erase commands are issued for only the User ROM area and each block area The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area In the CPU rewrite mode because the flash memory cannot be read from the CPU the rewrite control program must be transferred to internal RAM area before it can be executed User ROM area Data block B 1K bytes Data block A 1K bytes Block 1 26K bytes Notes1 The boot ROM area can be rewritten in a parallel 1 mode Access to except boot ROM area is disabled To specify a block use the maximum address in the block The QzROM version has the reserved ROM area Note the difference of the area Block 0 32 K bytes F00016 Boot ROM area 4K bytes FFFF16 20 2008 75 01134 sENESAS 3805 Outline Performance CPU rewrite mode is usable in the single chip or Boot mode The only User ROM area can
95. 16 002616 002716 002816 002916 002A16 002 16 002 16 002016 002E16 002F 16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003816 003 16 003016 003E16 003F 16 OFFO16 OFF 116 OFF216 OFF316 OFF416 OFF516 OFF616 OFF716 OFF816 OFF916 1 1 1 OFFD16 OFFE16 OFFF16 Note 1 The blanks are reserved Do not write data to these areas 2 No memory access is allowed to the blank areas within the SFRs 3 Addresses OFE016 to OFEF16 are available in the flash memory version only Fig 11 Memory map of special function register SFR Rev 3 04 Timer 1 T1 Timer 2 T2 Timer 3 T3 Timer 4 T4 PWM01 register PWMO 1 Timer 12 mode register T12M Timer 34 mode register T34M Timer 1234 mode register T1234M Timer 1234 frequency division selection register PRE1234 Watchdog timer control register WDTCON Timer X low order TXL Timer X high order TXH Timer X extension TXEX Timer X mode register TXM Timer X control register 1 1 Timer X control register 2 2 Compare register 1 low order COMP1L Compare register 1 high order COMP1H Compare register 2 low order COMP2L Compare register 2 high order COMP2H Compare register 3 high order Compare register 3 low or
96. 2Vcc or less Wee min 2 In the flash memory version input to the RESET pin in the following procedure When power source is stabilized 1 Input L level for 2us or more to RESET pin 2 Input level to RESET pin At power on 1 Input L level to RESET pin 2 Increase the power source voltage to 2 7 V 3 Wait for td P R until internal power source has stabilized 4 Input level to RESET pin In the version the input level applied to the OSCSEL Un pin is determined when the RESET pin changes from L to td P R or more voltage detection circuit Note 1 QzROM version 2 us or more Flash memory version td P R or more Fig 57 Reset circuit example OSCSEL L OCO OSCSEL H XIN 2 System clock RESET 4 Internal reset vector table Address X X X X FFFD iex aD X gt Data 1 1 1 Reset address from 1 1 L 1 1 T 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 gt OSCSEL L OCO about 32768 cycles OSCSEL H Xin about 8192 cycles Notes 1 The frequency of system clock is 32 or f XIN 8 2 The qu
97. 3 04 REJ03B0158 0304 6 Serial l O1 Enable Bit during Transmit Operation During transmission if the serial I O1 enable bit bit 7 of serial control register address 001A16 is set to 0 the pin function is set to an I O port and the internal transmit operation continues even though transmit data is not output externally Also if the transmit buffer register is written in this state transmit operation starts internally If the serial I O1 enable bit is set to 1 at this time transmit data is output to the TxD pin from that point 7T Transmission Control When External Clock Selected During data transmission if the external clock is selected as the synchronous clock set the transmit enable bit to 1 while SCLK1 is set to Also write to the transmit buffer register while SCLK1 is set to H 8 Receive Operation in Clock Synchronous Serial I O Mode During reception in clock synchronous serial I O mode set both the transmit enable bit and the receive enable bit to 1 Then write dummy data to the transmit buffer register When the internal clock is selected as the synchronous clock the synchronous clock is output at this point and receive operation starts When the external clock is selected reception is enabled at this point and inputting the external clock starts transmit operation The P41 TxD pin outputs dummy data written in the transmit buffer register 9 Transmit Receive Opera
98. 3o P37 P72 P74 L total average output current 1 20 mA P4o P47 P5o P57 P6o P6 4 total average output current 1 90 mA P62 P67 loH peak peak output current 2 2 mA P0o PO7 P1o P17 20 27 P3o P37 lOH peak peak output current 2 5 mA P4o P47 P5o P57 P6o P67 P72 P74 4 peak output current 2 5 mA P0o PO7 P1o P17 P2o P27 P3o P37 loL peak L peak output current 2 10 mA P4o P47 P5o P57 P61 7 gt 74 4 peak output current 2 30 mA P62 P67 loH avg H average output current 3 1 0 mA POo P07 P1o P17 20 27 P3o P37 loH avg average output current 3 2 5 mA P4o P47 P5o P57 P6o P67 P72 P74 lOL avg 4 average output current 3 2 5 mA 0 0 P1o P17 20 27 P3o P37 loL avg L average output current 3 5 0 mA P4o P47 P5o P57 P60 P61 P72 P74 loL avg 4 average output current 3 15 mA P62 P67 NOTES 1 The total output current is the sum of all the currents flowing through all the applicable ports The total average current is an average value measured over 100 ms The total peak current is the peak value of all the currents 2 The peak output current is the peak current flowing in each port 3 The average output current is average value measured over 100 ms Rev 3 04 20 2008 100 of 134 42 N S AS REJ03B0158 030
99. 4 3805 QzROM VERSION Table 25 Recommended operating conditions 3 Vcc 1 8 to 5 5 V 55 20 to 85 C unless otherwise noted Symbol Parameter Conditions Max f CNTRo f CNTR1 Timer X and Timer Y Input frequency duty cycle 50 4 5 lt Vcc x 5 5V 6 25 4 0 lt lt 4 5V 2 Vcc 4 2 0 lt Vcc lt 4 0V Vcc lt 2 0V 5 x Vcc 8 Timer X Timer Y Timer 1 Timer 2 Timer 3 Timer 4 clock input frequency Count source frequency of each timer 4 5 lt lt 5 5V 16 4 0 lt Vcc lt 4 5V 4 x Vcc 8 2 0 lt Vcc lt 4 0V 2 x Vcc Vcc 2 0V 10 x Vcc 16 System clock frequency 1 4 5 lt Vcc lt 5 5V 6 25 4 0 lt Vcc lt 4 5V 4 2 0 lt Vcc lt 4 0V Vcc Vcc lt 2 0V 5 x Vcc 8 Main clock input frequency duty cycle 50 2 3 4 5 lt Vcc x 5 5V 16 2 0 lt Vcc lt 4 5V 8 0 Vcc lt 2 0V 20 x Vcc 32 NOTES Sub clock oscillation frequency duty cycle 50 4 5 80 1 Relationship between system clock frequency and power source voltage is shown in the graph below 2 When the A D converter is used refer to the recommended operating conditions of the A D converter 3 12 5 MHz f XiN x 16 MHz is not available in the frequency 2 mode 4 The oscillation start voltage and the oscillati
100. 5 QzROM version 38D5 Group gt 1 Jumper OSCSEL switch O TVPP 4 7kQ C C T TXD 27 4 7kQ T_RXD gt P41 ESDA TSCLK P42 ESCLK T BUSY NC T PGM OE MD P43 ESPGMB RESET circuit RESET RESET C GND P vss Ly AVSS XOUT Set the same termination as the single chip mode 1 When programming QzROM is performed disconnect Vcc from OSCSEL by a jumper switch Note For the programming circuit the wiring capacity of each signal pin must not exceed 47 pF Fig 69 When using programmer of Suisei Electronics System Co LTD connection example 2 OSCSEL Rev 3 04 20 2008 73 0 134 RENESAS REJ03B0158 0304 3805 FLASH MEMORY MODE The 38D5 Group flash memory version has the flash memory that can be rewritten with a single power source For this flash memory three flash memory modes are available in which to read program and erase the parallel I O and standard serial I O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit CPU For details of each mode refer to the next and after pages Contact the manufacturer of your programmer for the programmer Refer to
101. 50 200 current Analog input 5 0 current NOTE 1 tc AD one cycle of AD conversion clock AD conversion clock can be selected from 6SOURCE 2 or SOURCE 8 SOURCE represents the XIN input in the frequency 2 4 or 8 mode and internal on chip oscillator divided by 4 in the on chip oscillator mode or the low speed mode When the A D conversion is executed in the frequency 2 mode frequency 4 mode or frequency 8 mode set f XiN 2 500 kHz Relationship among AD conversion clock frequency power source voltage AD conversion mode and absolute accuracy AD conversion clock Low speed mode and on chip oscillator mode f OCO 8 or f OCO 32 10bitAD 4LSB 8bitAD 2LSB 4 ee AD conversion clock frequency 2 mode frequency 4 and frequency 8 mode f XIN 2 or f XIN 8 27 AD conversion clock frequency XIN 2 or f XIN 8 10bitAD 4LSB 8bitAD 2LSB 0 27 4 0 4 5 55 Power source voltage VCC Note f XIN gt 500kHz Rev 3 04 20 2008 1150f 134 42 NE S AS REJ03B0158 0304 3805 Timing Requirements And Switching Characteristics Table 42 Power supply circuit characteristics Vcc 2 7 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter Test conditions FLASH MEMORY VERSION Internal power source voltage 2 7 lt Vcc lt 5 5V sta
102. 6 0 0 f XIN 2 frequency 2 mode 0 1 f XIN 8 frequency 8 mode 1 0 f XIN 4 frequency 4 mode 1 1 On chip oscillator Notes 1 When the on chip oscillator is selected by the watchdog timer count source selection bit 2 bit 5 of watchdog timer control register address 002916 the on chip oscillator does not stop even when the on chip oscillator stop bit is set to 1 Also when the low speed mode is set the on chip oscillator stops regardless of the value of this bit in the QZROM version The on chip oscillator does not stop in the flash memory version so set this bit to 1 to stop the oscillation In on chip oscillator mode even if this bit is set to 1 the on chip oscillator does not stop in the flash memory version but stops in the QZROM version 2 In low speed mode the XCIN XCOUT oscillation stops if the port XC switch bit is set to 0 3 In XIN mode the XIN XOUT oscillation does not stop even if the XIN XOUT oscillation stop bit is set to 1 4 12 5 MHz lt f XIN lt 16 MHz is not available in the frequency 2 mode Fig 8 Structure of CPU mode register Rev 3 04 20 2008 15 134 RENESAS REJ03B0158 0304 3805 After releasing reset Low speed Xin mode Y Start the bits 4 and oscillation 5 of CPUM Wait by on chip oscillator operation until establishment of o
103. 616 AVss VREF Note 1 9SOURCE indicates the followings XIN input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the low speed and the on chip oscillator mode Fig 41 Block diagram of A D converter Rev 3 04 REJ03B0158 0304 20 2008 50 01134 sRENESAS 3805 bo AD control register ADCON address 001516 Analog input pin selection bits b2 b1 50 P50 ANo P51 AN1 P52 AN2 P53 AN3 P54 AN4 55 5 P56 AN6 57 7 AD conversion completion bit 0 Conversion in progress 1 Conversion completed AD conversion clock selection bit 0 SOURCE 2 i 1 SOURCE 8 ADKEY enable bit 0 Disabled 1 Enabled 10 bit or 8 bit conversion switch bit 0 10 bit AD 1 8 bit AD ADKEY selection bit 0 Invalid 1 Valid At 10bitAD Read address 001716 before 001616 AD conversion register high order Address 001716 AD conversion register low order Address 001616 VREF input switch bit 0 ON only during A D conversion 1 ON Note The bit 5 to bit 1 of address 001616 become 0 at reading Also bit 0 is undefined at reading At 8bitAD Read only address 001716 b7 b9 b8 57 b6 5 b4 b2 high order b7 low order b7 50 PEEEEEE Notes 1 SOURCE indicates the followings XIN input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the low speed and the on chip osc
104. 8 Gd uod 8 uod Jeu BopuoieM 9109 095 98 x v 10 DAS cE WOO 8 GOT suq 01 LWMd suq 8 jeu 01 ONMd suq 8 e jeu 8 z 19W11 sug 8 sug 91 A 19W11 indino 1991 91 107811280 91 x diuo uo 01994109 4 2010 leues 2019 10 u vf leues leues Sjeuueuo g x 819 01 JeueAuoo uonounj eJeudued jeuje1u 8 uod 8 Ld uod 8 Od uod INVHOVIG MOO 18 IWNOILONNA Fig 3 Functional block diagram 131 NE SAS May 20 2008 Page 6 of 134 REJ03B0158 0304 Rev 3 04 3805 PIN DESCRIPTION Table 3 Pin Pin description 1 Name Function Function except a port function Vcc Vss Power source Apply power source voltage to Vcc and 0 V to Vss RESET Reset input Reset input pin for active L XIN Clock input XOUT Clock output Input and output pins for the main clock generating circuit Connect a ceramic resonator or a quartz crystal oscillator between the XiN and Xour pins to set the oscillation frequency When an external cloc XIN and leave Xour pin open k is used connect the clock source to Feedback res
105. 805 T QzROM VERSION Timing Requirements And Switching Characteristics Table 30 Timing requirements 1 Vcc 4 0 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter tw RESET Reset input L pulse width Main clock input cycle time 4 5V lt lt 5 5V 1 4 0 lt Vcc lt 4 5V tWH XIN Main clock input pulse 4 5V x Vcc lt 5 5V 2 width 4 0V lt Vcc lt 4 5V tWL XIN Main clock input L pulse 4 5V lt Vcc lt 5 5 2 width 4 0V lt lt 4 5V tc CNTR CNTRo CNTR input cycle time twH CNTR CNTRo CNTR input pulse width CNTRo input L pulse width twH INT 1 INT10 INT2 input pulse width twL INT INTo1 INT10 INT2 input L pulse width Serial 1 clock input cycle time 3 twH ScLk1 Serial 1 01 clock input pulse width 3 twL ScLk1 Serial 1 01 clock input L pulse width 3 tsu RxD ScLk1 Serial 1 01 input setup time th ScLk1 RxD Serial 1 01 input hold time tc ScLk2 Serial 1 2 clock input cycle time tWH SCLK2 Serial 1 2 clock input pulse width twL ScLk2 Serial 2 clock input L pulse width tsu SIN2 SCLK2 Serial 1 2 input setup time th ScLk2 Sin2 Serial 1 2 input hold time NOTES 1 80 ns in the frequency 2 mode 2 32 ns in the frequency 2 mode
106. A16 3 Set the corresponding interrupt request bit to 0 after one INT interrupt edge selection bit or more instructions have been executed bit 1 of interrupt edge selection register 4 Setthe corresponding interrupt enable bit to 1 enabled INT2 interrupt edge selection bit bit 2 of interrupt edge selection register CNTRo activate edge switch bit bits 6 and 7 of timer X control register 1 address 002E16 CNTR activate edge switch bit bits 6 of timer Y mode register address 003816 When switching the interrupt sources of an interrupt vector address where two or more interrupt sources are assigned Related bit Timer Y CNTRi interrupt switch bit bit 3 of interrupt edge selection register When switching the INT pins Related bits INTO input port switch bit bit 4 of interrupt edge selection register INT input port switch bit bit 5 of interrupt edge selection register Push onto stack Vector fetch Instruction cycle 1 1 1 Instruction cycle 1 1 f 1 1 1 Internal clock E os sc LE 1 H H IR1T2 T1 T2 T3 Interrupt acceptance timing points IR1 IR2 Timings points at which the interrupt request bit is set to 1 Note Period 2 indicates the last cycle during one instruction cycle 1 The interrupt request bit for an interrupt request generated during period 1 is set to 1 at timing point IR1 2 The interrupt
107. CD panel turns off To make the LCD panel turn on after returning from the stop mode set the LCD enable bit to 1 Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction The number of cycles required to execute an instruction is shown in the list of machine instructions Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions the microcomputer does not operate normally and may perform unstable operation In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation Handling of Power Source Pin In order to avoid a latch up occurrence connect a capacitor suitable for high frequencies as bypass capacitor between power source pin Vcc pin and GND pin Vss pin and between power source pin VCC pin and analog power source pin AVCC Besides connect the capacitor to as close as possible For bypass capacitor which should not be located too far from the pins to be connected a ceramic capacitor of 0 1 uF is recommended LCD drive power supply Power supply
108. ESET Xin Input voltage OSCSEL Output voltage C2 All voltages are based on Vss When an input voltage is measured output transistors are cut off 0 3 to 6 5 0 3 to 0 3 0 3 to 2 to Vis 2 to 6 5 0 3 to 6 5 0 3 to Vcc 0 3 0 3 to 8 0 0 3 to 6 5 Output voltage P0o P07 P1o P17 20 27 P3o P37 At output port 0 3 to Vcc 0 3 At segment output 0 3 to Vi3 0 3 Output voltage P4o P47 P5o P57 P6o P67 P72 P74 Output voltage Vis Output voltage 2 SEGs2 SEGiss COMo COMs Output voltage Xour All voltages are based on Vss 0 3 to Vcc 0 3 0 3 to 6 5 0 3 to Vi3 0 3 0 3 to Vcc 0 3 Power dissipation Ta 25 C 300 Operating temperature 20 to 85 Rev 3 04 Storage temperature 20 2008 Page 98 0 134 RENESAS REJ03B0158 0304 40 to 125 3805 Recommended Operating Conditions Table 23 Recommended operating conditions 1 Vcc 1 8 to 5 5 V Vss 0 V 20 to 85 C unless otherwise noted Parameter QzROM VERSION Min Power source voltage 1 Frequency 2 mode 2 4 5 lt 4 0 2 0 1 8 Frequency 4 mode 4 5 2 0 1 8 Frequency 8 mode 4 5 2 0 1 8 Low speed mode 1 8 On chip oscillator mode
109. Fig 94 Wiring for a large current signal line Wiring of signal lines where potential levels change frequently Rev 3 04 REJ03B0158 0304 4 Analog input The analog input pin is connected to the capacitor of a voltage comparator Accordingly sufficient accuracy may not be obtained by the charge discharge current at the time of A D conversion when the analog signal source of high impedance is connected to an analog input pin In order to obtain the A D conversion result stabilized more please lower the impedance of an analog signal source or add the smoothing capacitor to an analog input pin 5 Difference of memory size When memory size differ in one group actual values such as an electrical characteristics A D conversion accuracy and the amount of proof of noise incorrect operation may differ from the ideal values When these products are used switching perform system evaluation for each product of every after confirming product specification 20 2008 97 of 134 RENESAS 3805 QzROM VERSION ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Table 22 Absolute maximum ratings Parameter Conditions QzROM VERSION Ratings Power source voltage Input voltage 0 7 1 17 20 27 P3o P37 P4o P47 5 5 P6o P67 70 74 Input voltage Input voltage Input voltage C1 C2 Input voltage Input voltage R
110. G34 P57 AN7 ADKEYo lt gt gt COM4 SEG35 56 lt gt P55 AN5 lt gt P54 AN4 lt gt P53 AN3 lt gt P52 AN2 80 4 lt Note 1 CNVss in flash gt 1 1039 1n0e lt gt 17102 0INMd Zd gt 1 07 L IWMd Zd LNOX NX SSA gt NI9X 99d gt 1009X 9d _ 13538 L 30N 115050 0031 001NI 29d 037 21 0 1 94 9 4 2031 21 1 9 gt ca31 100x L s9d ra31 0H1N9 0 LNI 99d lt gt sa31 H1NO 9d 2 lt gt od1u oNv oSd lt gt bd LY INW Sd memory version Package type PRQPO080GB A 80P6N A QFP Package Fig 1 Pin configuration 131 NE SAS 20 2008 Page 2 of 134 REJ03B0158 0304 Rev 3 04 3805 PIN CONFIGURATION TOP VIEW 0 1 2 3 4 5 6 7 8 9 lt gt P11 SEG lt gt P13 SEG gt P14 SEG20 lt gt P15 SEGe 44 P12 SEG lt gt P07 SEG 46 P10 SEG lt gt P05 SEG 48 gt POe SEG lt gt P23 SEG3 KW7 60 4 9 P22 SEG2 KWe lt gt P24 SEG4 lt gt P25 SEG5 lt gt P26 SEGe lt gt P27 SEG7 lt gt POo SEGs gt P01 SEG9 gt P02 SEG lt gt P03 SEG lt gt PO4 SEG 59 58 57 56 55 54 _53
111. IN XIN Clock input XouT Clock output Connect an oscillation circuit between the XiN and Xour pins As for the connection method refer to the clock generating circuit AVss Analog power supply input Connect AVss to Vss VREF Reference voltage input Apply reference voltage of A D convertor to this pin P0o PO7 P10 P17 P20 P27 P30 P37 40 47 P5o P57 P60 P67 72 74 I O port Input L or H level or keep open 4 RxD input Serial data input pin P41 TxD output Serial data output pin P42 input Input L level P43 BUSY output BUSY signal output pin Rev 3 04 20 2008 Page 870f 134 RENESAS REJ03B0158 0304 3805 P47 SRbY2 KWs gt P4e Sc k2 KW2 lt gt P4s Sour2 KW1 lt P44 SiN2 KWo lt gt P43 SRDY1 lt P42 Scik1 lt gt P41 TXD gt P40 RXD lt gt AVss VREF P57 AN7 ADKEYo0 lt gt lt gt P20 SEGo lt gt 1 gt 22 5 2 gt P23 SEG3 lt gt P24 SEG4 lt gt P25 SEG5 lt gt 26 5 6 lt gt P27 SEG7 lt gt P00 SEGs lt gt 1 5 lt gt P02 SEGi10 lt gt P03 SEG11 lt gt PO4 SEG12 lt gt P05 SEGi3 gt P06 SEG14 lt gt 07 15 lt gt P1o SEGi6 lt gt 11 3 17 gt P12 SEG18 gt P13 SEGi9 gt P14 SEG20 lt gt 15 21 lt
112. Initial value of 2 is 0016 As for the details of condition for transition among each mode refer to the state transition of system clock Oscillator starts oscillation Do not change bit 3 bit 6 and bit 7 of CPUM until oscillation stabilizes System can operate in on chip oscillator mode until oscillation stabilize Select internal system clock Do not change bit 3 bit 6 and bit 7 of CPUM at the same time Select main clock division ratio Switch to frequency 2 or 4 mode here if necessary Fig 9 Switch procedure of CPU mode register Rev 3 04 REJ03B0158 0304 20 2008 Page 16 01134 q N S AS The CPU starts its operation in the built in XIN mode Initial value of CPUM is 4016 Initial value of CPUM2 is 0116 lt Flash memory version gt 3805 MEMORY Special Function Register SFR Area The Special Function Register area in the zero page contains control registers such as I O ports and timers RAM RAM is used for data storage and for stack area of subroutine calls and interrupts ROM In the QzROM version the first 128 Kbytes and the last 2 bytes are reserved for device testing and the rest is the user area Also 1 byte of address FFDB 16 is reserved In the flash memory version programming and erase operations can be performed to reserved ROM areas Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors Zero Pag
113. M area in the ROM FF0016 correction address registers Do not set the same ROM correction addresses in both the Special ROM correction address registers 1 and ROM correction FFDBis Reserved ROM area address registers 2 3 It is necessary to contain the process for ROM correction in the program Fig 50 Memory map of M38D58G8 Interrupt vector area 00 ROM correction enable register Address 16 RCR ROM correction address 1 enable bit RCO 0 Disable 1 Enable ROM correction address 2 enable bit RC1 0 Disable 1 Enable ROM correction memory selection bit RC2 0 Branch to the RAM area 1 Branch to the ROM area Not used returns 0 when read Note After ROM correction address register is set set the ROM correction address enable bit to be enabled Fig 51 Structure of ROM correction enable register Rev 3 04 20 2008 58 01134 RENESAS REJ03B0158 0304 3805 WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop for example because of a software run away The watchdog timer consists of an 8 bit counter Initial Value of Watchdog Timer At reset or writing to the watchdog timer control register each watchdog timer is set to FF16 Instructions such as STA LDM and CLB to generate the write signals can be used The written data in bits 7 6 or 5 are
114. N2 4 gt 80 lt OLNI O 02d 4 lt 81 lt gt 1009 1002 lt gt 1not lt gt 1nov Connect to oscillation circuit QzROM pin nx SSA lt gt 9 gt lt 13539 185050 lt gt 1 1 1 94 5 lt gt 2031 21 9 lt gt 1 1 9 4 raa1 u1N9 0 LNI 99d 5 lt gt 1 494 lt gt od LHONW 0Sd lt gt a1u Nv Sd PRQPO0080GB A 80P6N A M38D5XGXFP Fig 64 Pin connection diagram 20 2008 Page 680f134 RENESAS REJ03B0158 0304 Rev 3 04 3805 QzROM version 0 1 2 3 4 5 6 7 8 9 lt gt P23 SEG3 KW7 60 lt P22 SEG2 KWe lt gt P24 SEG4 lt gt P25 SEGs5 lt gt P26 SEGe P27 SEG7 lt gt P00 SEGs lt gt P01 SEG9 PO2 SEG lt 4 gt POs SEG gt PO4 SEG lt gt P05 SEG lt gt POe SEG lt 4 gt PO7 SEG P10 SEG gt P11 SEG 44 4 P12 SEG lt gt P13 SEG P14 SEG20 lt gt P15 SEG 1 EI EI 57 756 755 54 53 52 51 56 49 48 47 46 45 43 22 41 P1e SEG22 P17 SEGes P3o SEG24 P31 SEG 5 P32 SEG 6
115. Portlatch lt Serial 1 02 clock output Serial 1 02 ready output E Serial 1 02 input 1 Key on wakeup interrupt input Key input control Key on wakeup interrupt input lt Key input control 11 Ports P50 P51 12 Ports P52 P56 up contro Pull up control 771 r Direction Direction register register Data bus gt Port latch Data bus gt latch Real time port control bit Data for real time port Analog input pin selection bit Analog input pin selection bit A D conversion input o ve A D conversion input o ADKEY enable gt ADKEY enable bt Fig 15 Port block diagram 2 Rev 3 04 20 2008 Page 23 0 134 stENESAS REJ03B0158 0304 3805 13 Port P57 14 Port P60 Pull up control Port Xc switch bit up control gt register Direction Direction Port Xc switch bit il 3 4 eed register Data bus 1 Port latch Data bus 1 Port latch
116. REJ03B0158 0304 3805 NOTES ON USE Processor Status Register The contents of the processor status register PS after a reset are undefined except for the interrupt disable flag I which is 1 After a reset initialize flags which affect program execution In particular it is essential to initialize the index X mode T and the decimal mode D flags because of their effect on calculations Initialize these flags at beginning of the program Interrupt The contents of the interrupt request bits do not change immediately after they have been written After writing to an interrupt request register execute at least one instruction before performing a BBC or BBS instruction Decimal Calculations To calculate in decimal notation set the decimal mode flag D to 1 then execute an ADC or SBC instruction After executing an ADC or SBC instruction execute at least one instruction before executing a SEC CLC or CLD instruction In decimal mode the values of the negative N overflow V and zero Z flags are invalid Timers The division ratio is 1 1 when the value 0 to 255 is written to the timer latch Multiplication and Division Instructions The index mode T and the decimal mode D flags do not affect the MUL and DIV instruction The execution of these instructions does not change the contents of the processor status register Direction Registers The values of the port direction
117. The high order 8 bits of a conversion result is stored in the AD conversion register high order address 001716 and the low order 2 bits of the same result are stored in bit 7 and bit 6 of the AD conversion register low order address 001616 During A D conversion do not read these registers Also the connection between the resistor ladder and reference voltage input pin VREF can be controlled by the VREF input switch bit bit 0 of address 001616 When 1 is written to this bit the resistor ladder is always connected to VREF When 0 is written to this bit the resistor ladder is disconnected from except during the A D conversion AD Control Register ADCON This register controls A D converter Bits 2 to 0 are analog input pin selection bits Bit 3 is an AD conversion completion bit and 0 during A D conversion This bit is set to 1 upon completion of A D conversion A D conversion is started by setting 0 in this bit Bit 5 is the ADKEY enable bit The ADKEY function is enabled by setting 1 to this bit When this function is valid the analog input pin selection bits are ignored Also when bit 5 is 1 do not set 0 to bit 3 by program Comparison Voltage Generator The comparison voltage generator divides the voltage between 55 and VREF and outputs the divided voltages Data bus b7 AD control register _ ADKEY control circuit
118. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 17 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 2 NE S AS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is gr
119. V gt 2 0V lt Vcc lt 2 2V 1 8V lt Vcc lt 5 5V gt 2 0V lt Vcc lt 5 5V 104 115 Table 31 and 45 Each main clock input condition Vcc are revised 105 Table 32 2 0V lt Vcc lt 4 0V gt 2 0V lt Vcc lt 4 0V Vcc lt 2 0V gt Vcc lt 2 0V Note 1 is added 108 Table 35 CNVss is added Storage temperature is revised 112 Table 40 Limits value of liL are revised 113 Table 41 All limits value are revised 113 114 Table 41 42 and 43 55 is added to test conditions 114 Table 43 2 7V lt Vcc lt 4 0V gt 2 7V lt Vcc lt 4 0V 2 7 lt Vcc lt 5 5V and test conditions of and f OCO 32 are added Table 44 are added Table 45 Main clock input L pulse width is added Note 1 is revised 120 133 Appendix added Sep 11 2007 Table 5 Latest revised date of products list Fig 10 Brancket indicates the ROM area is modified Fig 45 VL1 external capacitor external power supply Marge the Recommended operating conditions 1 table and Recommended operating conditions 2 Marge the Recommended operating conditions 1 table and Recommended operating conditions 2 2nd item of 8 Write Order to Timer X is added 2nd item of 10 Write to Timer X is deleted Oct 02 2007 40 7 When Timer X Pulse Width Measurement Mode Used is revised 64 Fig 62 is revised 65 Fig 63 is revised 76 Fig 73 is revised Table 17 is revised May 20 2008 4 17 19 20 Table 1 LCD drive control circuit Duty
120. Value of Watchdog Timer Some description added Standard Operation of Watchdog Timer Some description eliminated Bit 6 of Watchdog Timer Control Register added Note 2 revised Fig 50 Structure of Watchdog timer control register Name of bit 6 and description of its function revised Fig 55 Reset sequence revised Fig 56 Internal state at reset ROM correction address 1 low order ROM correction address 2 high order and ROM correction address 2 low order revised Oscillation Control 1 Stop Mode Some description revised Fig 58 Clock generating circuit block diagram or ROSC clock division ratio selection bit eliminated Fig 60 State transitions of system clock on chip oscillator mode f OCO 32 Note 8 to Note 10 revised and Note 12 added QzROM programming mode Overview Pin description Pin connection diagram Connection example added 6 Wiring to OSCSEL pin revised QzROM Receive Flow added 1 7 REVISION HISTORY 38D5 Group Data Sheet Description Summary Jan 23 2006 Table 14 Recommended operating conditions Vcc Power source voltage and Note revised Vit RESET revised Table 16 Recommended operating conditions all revised Power source voltage graph added Table 17 Electrical characteristics ROSC f OCO Table 18 Electrical characteristics revised Table 19 A D converter recommended operating condition revised Table 20 A D converter chara
121. a in the flash memory cannot be used 3 Interrupts During CPU rewrite mode interrupts cannot be used because they reference data in the flash memory 4 Watchdog Timer If the watchdog timer has been running already the internal reset by underflow will not occur because the watchdog timer is continuously cleared during program or erase operation 5 Reset Reset is always valid If CNVss H when a reset is released boot mode is active The program starts from the address stored in addresses FFFC16 and FFFD16 in boot ROM area Notes on Watchdog Timer 1 Watchdog Timer Underflow The watchdog timer does not operate in stop mode but it continues counting during the wait time to release the stop state and in wait mode Write to the watchdog timer control register so that the watchdog timer will not underflow during these periods 2 Stopping On Chip Oscillator Oscillation When the on chip oscillator is selected by the watchdog timer count source selection bit 2 the on chip oscillator forcibly oscillates and it cannot be stopped Also in this time set the STP instruction function selection bit to 1 at this time Select 0 for the watchdog timer count source selection bit 2 at the system which on chip oscillator is stopped 3 Watchdog Timer Control Register Bits 7 to 5 can be rewritten only once after a reset After writing rewriting is disabled because they are locked These bits are
122. al I O1 control register and the serial I O1 transmit interrupt request bit is set to 1 3 Data Transmission Control Using Transmit Shift Completion Flag After transmit data is written to the transmit buffer register the transmit shift completion flag bit 2 of serial I O1 status register address 001916 changes from 1 to 0 after a delay of 0 5 to 1 5 cycles of the system clock Thus after transmit data is written to the transmit buffer register note this delay when controlling data transmission by referencing the transmit shift completion flag 4 Setting Serial l O1 Control Register Before setting the serial I O1 control register again first set both the transmit enable bit and the receive enable bit to 0 and initialize the transmission and reception circuits Set both the transmit enable bit TE and the receive enable bit RE to 0 Y Set bits 0 to 3 and 6 of the serial 1 01 control register Settings can be made with Y the LDM instruction at the same time Set both the transmit enable bit TE and the receive enable bit RE or one of them to 1 Fig 104 Sequence of setting serial 1 01 control register 5 Pin Status After Transmission Completed After transmission is completed the TxD pin retains the level when transmission is completed When the internal clock is selected in clock synchronous serial T O mode the SCLK1 pin is set to Rev
123. all the applicable ports The total average current is an average value measured over 100 ms The total peak current is the peak value of all the currents 2 The peak output current is the peak current flowing in each port 3 The average output current is average value measured over 100 ms Rev 3 04 20 2008 Page 11101134 42 N S AS REJ03B0158 0304 3805 Table 37 Recommended operating conditions 3 Vcc 2 7 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted pd add f CNTRo f CNTR1 Timer X and Timer Y Input frequency duty cycle 50 4 5V lt Voc lt 5 5V FLASH MEMORY VERSION Limits ww T 4 0V lt Vcc lt 4 5V 2 7 Voc lt 4 0V Timer X Timer Y Timer 1 Timer 2 4 5 lt Voc lt 5 5V 4 0V lt Vcc lt 4 5V Timer 3 Timer 4 clock input frequency Count source frequency of each timer 2 7 lt lt 4 0V 4 5V lt Vcc lt 5 5V 4 0V lt Vcc lt 4 5V 2 7V lt Vcc lt 4 0V 4 5V lt Vcc lt 5 5V 2 7N lt Ncc lt 4 5V System clock frequency 1 Main clock input frequency duty cycle 50 2 3 Sub clock oscillation frequency duty cycle 5096 4 5 6 25 2xVcc 4 Vcc 16 4xVcc 8 2 6 25 4 Vcc 1 0 16 1 0 8 0 32 768 80 NOTES 1 Relationship between system clock frequency and power source voltage is shown in the graph below 2 When the A D converter is used ref
124. am To return to the main program from the correction program use the JMP instruction 3 byte instruction 2 Using ROM Correction Function If the ROM correction function is used be sure to enable the ROM correction enable bit after setting the ROM correction register 3 Address Do not set addresses other than the ROM area in the ROM correction address registers Also do not set the same address in the ROM correction address 1 register and the ROM correction address 2 register 4 ROM Correction Process Include the ROM correction process in the program beforehand Rev 3 04 REJ03B0158 0304 5 Using No ROM Correction Function If the ROM correction function is not used the ROM correction vector can be used as normal RAM ROM When using as normal RAM ROM be sure to set bits 1 and 0 of the ROM correction enable register to 0 disabled Notes on Clock Generating Circuit 1 Oscillation Circuit Constants The oscillation circuit constants vary depending on the resonator Use values recommended by the oscillator manufacturer A feed back resistor is implemented between the XIN and XOUT pins an external feed back resistor may be required depending on conditions As no feed back resistor is implemented between XCIN and XCOUT add a feedback resistor of about 10 MQ 2 Transition between Modes When the MCU transits between on chip oscillator mode XIN mode or low speed mode both the XIN and XCIN oscillations
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126. ason The OSCSEL pin is the power source input pin for the built in QzROM When programming in the QzROM the impedance of the OSCSEL pin is low to allow the electric current for writing to flow into the built in QzZROM Because of this noise can enter easily If noise enters the OSCSEL pin abnormal instruction codes or data are read from the which may cause program runaway Termination of OSCSEL pin 1 OSCSEL L 2 OSCSEL H oscseL he shortest about 5 about 5 p OSCSEL dj The shortest i The shortest Note 1 It shows the microcomputer s pin Fig 87 Wiring for the OSCSEL pin Precautions Regarding Overvoltage in QZROM Version Make sure that voltage exceeding the pin voltage is not applied to other pins In particular ensure that the state indicated by bold lines in figure below does not occur for OSCSEL pin VPP power source pin for QZROM during power on or power off Otherwise the contents of QZROM could be rewritten Vcc pin voltage OSCSEL pin voltage H input 1 OSCSEL pin ve 2 1 L input u 1 Input voltage to other MCU pins rises before Vcc pin voltage 2 Input voltage to other MCU pins falls after Vcc pin voltage Note The internal circuitry is unstable when Vcc is below the minimum voltage specification of 1 8 V shaded portion so particular care should be exercised regarding overvoltage Fig 88 Example of Overvoltage
127. ating mode of the chip Connect to Vss VREF Analog reference voltage Reference voltage input pin for A D converter AVss Rev 3 04 Analog power source May 20 2008 Page 8 of 134 REJ03B0158 0304 Analog power source input pin for A D converter Connect to Vss 13 NE SAS 3805 PART NUMBERING Product M38D5 8 8 XXX Package type FP PRQPO080GB A package HP PLQPO080KB A package ROM number Omitted in the shipped in blank version ROM memory size 4096 bytes 8192 bytes 12288 bytes 16384 bytes 20480 bytes 24576 bytes 36864 bytes 40960 bytes 45056 bytes 49152 bytes 53248 bytes 57344 bytes 9 A B D E F 28672 bytes 92768 bytes 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas they cannot be used Memory type version F Flash memory version RAM size 0 192 bytes 256 bytes 384 bytes 512 bytes 640 bytes 768 bytes 896 bytes 1024 bytes 1536 bytes 2048 bytes Fig 4 Part numbering Rev 3 04 20 2008 Page 9 of 134 REJ03B0158 0304 5 5 3805 GROUP EXPANSION Packages Renesas plans to expand the 38D5 Group as follows e 8 0 8 mm pitch plastic molded e
128. ation of the processor status register It is required to initialize the processor status register PS flags which affect program execution It is particularly essential to initialize the T and D flags because of their effect on calculations Initialize these flags at the beginning of the program lt Reason gt At a reset the contents of the processor status register PS are undefined except for the I flag which is 1 Initialize the flags Main program Fig 99 Initialization of processor status register flags 2 How to refer the processor status register To refer the contents of the processor status register PS execute the PHP instruction once and then read the contents of S 1 If necessary execute the PLP instruction to return the stored PS to its original status Fig 100 Stack memory contents after PHP instruction execution Rev 3 04 REJ03B0158 0304 2 Decimal Calculations 1 Instructions for decimal calculations To perform decimal calculations set the decimal mode D flag to 1 with the SED instruction and execute the ADC or SBC instruction In that case after the ADC or SBC instruction execute another instruction before the SEC CLC or CLD instruction Set the decimal mode D flag to 1 Execute the ADC or SBC instruction Execute the SEC CLC or CLD instruction Fig 101 Instructions for decimal calculations 2 Status flag at decimal cal
129. b4 0 0 Timer mode 0 1 Period measurement mode 1 0 Event counter mode CNTRt active edge switch bit 0 Count at rising edge in event counter mode Falling edge active for CNTR1 interrupt Count at falling edge in event counter mode Rising edge active for CNTR interrupt Timer Y count stop bit 0 Count operation 1 Count stop Fig 32 Structure of Timer Y related registers Rev 3 04 REJ03B0158 0304 Measure rising period in period measurement mode Switch the frequency division or count source while the timer count is stopped This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes on chip oscillator mode XIN mode or low speed mode Be careful when changing settings in the CPU mode register Timer Y control register TYCON address 003916 Timer Y write control bit 0 Write data to both timer latch and timer 1 Write data to timer latch only Timer Y count source selection bit 0 Frequency divider output 1 Timer frequency division selection bits b3 62 0 0 1 16 x SOURCE 0 1 1 1 x SOURCE 1 0 1 2 x SOURCE 1 1 1 256 x SOURCE Not used returns 0 when read 1 1 Pulse width HL continuous measurement mode Measure falling period in period measurement mode Note1 SOURCE indicates the followings XIN input in the frequency 2 4
130. be rewritten In CPU rewrite mode the CPU erases programs and reads the internal flash memory as instructed by software commands This rewrite control program must be transferred to internal RAM area before it can be executed The MCU enters CPU rewrite mode by setting 1 to the CPU rewrite mode select bit bit 1 of address 0 016 Then software commands can be accepted Use software commands to control program and erase operations Whether a program or erase operation has terminated normally or in error can be verified by reading the status register Figure 71 shows the flash memory control register 0 Bit 0 of the flash memory control register 0 is the RY BY status flag used exclusively to read the operating status of the flash memory During programming and erase operations it is 0 busy Otherwise it is 1 ready Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit When this bit is set to 1 the MCU enters CPU rewrite mode And then software commands can be accepted In CPU rewrite mode the CPU becomes unable to access the internal flash memory directly Therefore use the control program in the internal RAM for write to bit 1 To set this bit 1 to 1 it is necessary to write 0 and then write 1 in succession to bit 1 The bit can be set to 0 by only writing 0 Bit 2 of the flash memory control register 0 is the user block 1 Flash memory co
131. bilizes time at power on Table 43 Timing requirements 1 Vcc 4 0 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter iw RESET Reset input L pulse width tc XIN Main clock input cycle time 4 5V lt Vcc lt 5 5 1 4 0V lt Vcc lt 4 5V tWH XIN Main clock input pulse width 4 5V lt Vcc lt 5 5V 2 4 0V lt Vcc lt 4 5V twL XIN Main clock input L pulse width 4 5V lt Vcc lt 5 5V 2 4 0V lt Vcc lt 4 5V CNTRo CNTR input cycle time twH CNTR CNTRo 1 input H pulse width tWL CNTR CNTRo 1 input L pulse width twH INT INToo INTo1 INT10 INT11 INT2 input pulse width tWL INT INToo INTo1 INT10 INT11 INT2 input L pulse width tc SCLk1 Serial 1 01 clock input cycle time 3 tWH SCLK1 Serial 1 01 clock input pulse width 3 twL ScLk1 Serial 1 01 clock input L pulse width 3 tsu RxD SCLk1 Serial 1 01 input setup time th SCLK1 RxD Serial 1 01 input hold time tc ScLk2 Serial 1 02 clock input cycle time tWH SCLK2 Serial 1 02 clock input pulse width twL ScLk2 Serial 1 02 clock input L pulse width tsu SIN2 SCLKk2 Serial 2 input setup time th SCLK2 SIN2 NOTES Serial 1 02 input hold time 1 80 ns
132. capacitor may be insufficient with the division resistance for LCD power supply and the characteristic of the LCD panel In this case there is the method of connecting the bypass capacitor about 0 1 0 33uF to VL1 VL3 pins The example of a strengthening measure of the LCD drive power supply is shown below Connect by the shortest possible wiring Connect the bypass capacitor to the VL1 pins as short as possible Referential value 0 1 0 33 uF Fig 86 Strengthening measure example of LCD drive power supply 20 2008 93 01134 sENESAS 3805 NOTES QzROM VERSION Wiring to OSCSEL pin 1 OSCSEL L Connect the OSCSEL pin the shortest possible to the GND pattern which is supplied to the Vss pin of the microcomputer In addition connecting an approximately 5 resistor in series to the GND could improve noise immunity In this case as well as the above mention connect the pin the shortest possible to the GND pattern which is supplied to the Vss pin of the microcomputer 2 OSCSEL H Connect the OSCSEL pin the shortest possible to the Vcc pattern which is supplied to the Vcc pin of the microcomputer In addition connecting an approximately 5 resistor in series to the Vcc could improve noise immunity In this case as well as the above mention connect the pin the shortest possible to the Vcc pattern which is supplied to the Vcc pin of the microcomputer Re
133. ce equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under
134. ceptance Interrupt Handling Execution When interrupt handling is executed the following operations are performed automatically 1 Once the currently executing instruction is completed an interrupt request is accepted 2 The contents of the program counters and the processor status register at this point are pushed onto the stack area in order from 1 to 3 1 High order bits of program counter PCH 2 Low order bits of program counter PCL 3 Processor status register PS 3 Concurrently with the push operation the jump address of the corresponding interrupt the start address of the interrupt processing routine is transferred from the interrupt vector to the program counter 4 The interrupt request bit for the corresponding interrupt is set to 0 Also the interrupt disable flag is set to 1 and multiple interrupts are disabled 5 The interrupt routine is executed 6 When the RTI instruction is executed the contents of the registers pushed onto the stack area are popped off in the order from 3 to 1 Then the routine that was before running interrupt processing resumes As described above it is necessary to set the stack pointer and the jump address in the vector area corresponding to each interrupt to execute the interrupt processing routine Rev 3 04 REJ03B0158 0304 Interrupt request generated Interrupt request Interrupt routine acceptance starts Interrupt sequence Stack push and
135. chronous serial 1 01 function Rev 3 04 20 2008 Page 440f 134 RENESAS REJ03B0158 0304 3805 2 Asynchronous Serial I O UART Mode Clock asynchronous serial I O mode UART can be selected by setting the serial I O mode selection bit of the serial I O1 control register to 0 Eight serial data transfer formats can be selected and the transfer formats used by a transmitter and receiver must be identical register cannot be written to or read from directly transmit data is written to the transmit buffer register and receive data is read from the receive buffer register The transmit buffer register can also hold the next data to be The transmit and receive shift registers each have a buffer but the two buffers have the same address in memory Since the shift transmitted and the receive buffer register can hold a character while the next character is being received Data bus Character length se Address 001816 Serial 1 01 control register 4 Receive buffer register P40 RxD ST detector ection bit ES Receive buffer full flag RBF Receive interrupt request RI Receive shift register 7 bits _ ion m PE FE 5 detector 1 16 Address 001A16 UART control register 42 5 1
136. circuit enabled before executing the STP or WIT instruction Bias Control and Applied Voltage to LCD Power Input Pins Apply the voltage value shown in Table 13 according to the bias value to the LCD power input pins Apply the voltage value shown in Table 13 according to the bias value by setting to VL3 connection bit bit 1 of LCD mode register 1 to 1 when the voltage multiplier is not used Select a bias value by the bias control bit bit 3 of the LCD mode register 1 Contrast adjust P7V INT P7o INTO Vu 1 3 bias R1 2 1 3 bias Voltage multiplier is not used 1 3 bias Voltage multiplier is used Table 13 Bias control and applied voltage to VL1 VL3 Bias value Voltage value VL3 VLCD 1 3 bias VL2 2 3 VLCD 1 3 VLCD 1 2 bias VL2 1 2 VLCD NOTE 1 25 the maximum value of supplied voltage for the LCD Common Pin and Duty Ratio Control The common pins 7 to be used are determined by duty ratio Select duty ratio by the duty ratio selection bits bits 0 1 and 2 of the LCD mode register1 When reset is released voltage is output from the common pin Table 14 Duty ratio control and common pins used Duty ratio selection bits Bit 2 Bit 1 Bit 0 0 0 0 Common pins used COMO 0 1 1 2 1 1
137. commended that related registers be overwritten periodically to prevent malfunctions etc Open If the input level become unstable through current flow to an input circuit and the power supply current may increase 20 2008 Page260f134 RENESAS REJ03B0158 0304 Especially when expecting low consumption current at STP or WIT instruction execution etc pull up or pull down input ports to prevent through current built in resistor can be used We recommend processing unused pins through a resistor which can secure IOH avg or IOL avg Because when an I O port or a pin which have an output function is selected as an input port it may operate as an output port by incorrect operation etc 3805 Table 10 Termination of unused pins Pin Termination 1 Termination 2 Termination 3 00 5 07 5 5 I O port When selecting SEG output open P10 SEG16 P17 SEG23 P20 SEGo KWa4 P27 SEG7 P30 SEG24 P37 SEGs1 P40 RxD When selecting RxD function perform termination of input port P41 TxD When selecting TxD function perform termination of output port 42 5 When selecting external clock input When selecting internal clock output perform termination of input port perform termination of output port P43 SRDY1 When selecting SRDY1 function perform termination of output port P44 SiN2 KWo When selecting SiN2 function perform termina
138. compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products With the exception of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above Notwithstanding the preceding paragraph y
139. confirmation form and the mark specification form refer to the Technology Corp Homepage http www renesas com homepage jsp Note that we cannot deal with special font marking customer s trademark etc in 7 microcomputer 3 QzROM Product Receiving Procedure When writing to QzROM is performed by user side the receiving inspection by the following flow is necessary QzROM product shipped in blank QzROM product shipped after writing protect disabled protect enabled to the protect area 1 Renesas Renesas Programming Shipping b d 4 User Verify test lt Shipping User pa Receiving inspection of 4 unprotected area Verify test Programming Receiving inspection Blank check Programming to unprotected areal Verify test for all area Verify test for unprotected area Fig 109 QzROM receiving procedure 20 2008 Page 133 01134 42 NE S AS 3805 Notes on Flash Memory Version CPU Rewrite Mode 1 Operating Speed During CPU rewrite mode set the system clock 4 0 MHz less using the main clock division ratio selection bits bits 6 and 7 of address 003B 16 2 Prohibited Instructions The instructions which refer to the internal data of the flash memory cannot be used during the CPU rewrite mode 3 Interrupts
140. crocomputers include variations of memory size f XIN lt 16 MHz 4 5 to 5 5 V and packaging For details refer to ihe SecHint diu 2 E vu A a M 38 MHZ i EXIN lt 4 1 8 to 5 5 V In low speed 0 1 8 to 5 5 V FEATURES Note 12 5 MHz lt f XiN lt 16 MHz is not available in the fre quency 2 mode e Basic machine language instructions 71 Power source voltage Flash memory version The minimum instruction execution time 0 32 us In frequency 2 mode at 12 5 MHz oscillation frequency PEKIN S 12 5 MEZ ritiene 4 5to 5 5 V Memory size QzROM version f XiN lt 8 MHz 4 0 to 5 5 V ROM 32 K to 60 K bytes XN S 2 7 to 5 5 V RAM 1536 to 2048 bytes In frequency 4 mode Memory size Flash memory version TOXIN SS 16 aet rtr 4 5to 5 5 V 60 bytes FOXIN lt 8 MHz eese 27 05 5 V 2048 bytes In frequency 8 mode Programmable input output ports 59 common to SEG 36 16 4 5 10 5 5 V Interrupts bem 17 sources 16 vectors KXIN lt 8 MHz e 2 7 to 5 5 V Key input interrupt included In low speed mode sss 2 7t05 5 V 8 bit x 4 16 bit x 2 Note n aes Serial interface Power dissipation QZROM version
141. cteristics test conditions revised AD Power source voltage graph added Table 21 Timing requirements 1 tc XIN twH XIN twL XIN revised and Note added PACKAGE OUTLINE revised Mar 24 2006 FEATURES Power source voltage revised Performance overview Oscillation frequency and Power source voltage revised Table 7 Related SFRs of port P7 revised Fig 46 Address revised Fig 50 Note 1 revised 1 Stop mode Description revised Fig 59 souRcE added Fig 60 State transitions of system clock Note 3 revised Table 14 Vcc Power source voltage and Note 3 revised Table 16 Power source voltage Main clock XiN frequency graph added Table 20 Description of and Note revised Jul 10 2006 Fig 11 Register names of ROM correction addresses 1 and 2 revised Termination of unused pins ports Description added Table 8 Termination 1 recommended Delete recommended Termination 1 to of P70 C1 INTo1 and P71 C2 INT11 revised XCIN is selected as Timer 1 2 count source sentence is revised 32 XCIN is selected as Timer X count source sentence is revised 33 Fig 26 TXCON1 bit 5 1 23 TXCON 1 bit 5 0 35 XCIN is selected as Timer Y count source sentence is revised 43 Fig 38 eSoURCE clock added 52 Fig 47 Border line in ROM area revised 53 Fig 49 chip oscillator On chip oscillator 4 Fig 50 b5 and b7 revised 58 Frequency Control Description added 61 Table 12 Func
142. ction register corresponds to one each pin be P50 pull up set to be input port or output port P51 pull up When 0 is written to the bit of the direction register the P52 pull up corresponding pin becomes an input pin As for ports PO P3 Ree pulF p when 1 is written to the bit of the direction register and the in n segment output disable register the corresponding pin becomes 5 pull up an output pin As for ports P4 P6 P72 P74 when 1 is written to P57 pull up Pulup the bit of the direction register the corresponding pin becomes M an output pin PULL register 2 If data is read from a pin set to output the value of the port latch PULL2 address OFF116 is read not the value of the pin itself However when peripheral PED pu up output RTP1 RTPo TxouT1 TxouT2 T30UT and ien T20UT CKOUT is selected the output value is read Pins set to s p lbup input are floating If a pin set to input is written to only the port P64 pull up output latch is written to and the pin remains floating ______________ 5 pull up P86 pull up 0 No pull up Ports 7 71 c P7 pull up 1 Pull up These are input ports which are shared with the voltage E PULL register 3 multiplier When these are read out at using the voltage PULL3 address OFF216 multiplier the contents are 1 P4o P43 pull up 44 47 pull up 0 No pull up 1 Pull
143. culations When the ADC or SBC instruction is executed in decimal mode D flag 1 three of the status flags V and Z are disabled The carry C flag is set to 1 if a carry is generated and is cleared to 0 if a borrow is generated as a result of a calculation so it can be used to determine whether the calculation has generated a carry or borrow Initialize the C flag before each calculation 20 2008 Page 122 of 134 4 NE S AS 3805 3 JMP Instruction When using the JMP instruction indirect addressing mode do not specify the address where FF16 is allocated to the low order 8 bits as the operand 4 Multiplication and Division Instructions 1 The MUL and DIV instructions are not affected by the T and D flags 2 Executing these instructions does not change the contents of the processor status register 5 Read Modify Write Instruction Do not execute any read modify write instruction to the read invalid address SFR The read modify write instruction reads 1 byte of data from memory modifies the data and writes 1 byte the data to the original memory In the 740 Family the read modify write instructions are the following 1 Bit handling instructions CLB SEB 2 Shift and rotate instructions ASL LSR ROL ROR RRF 3 Add and subtract instructions DEC INC 4 Logical operation instructions 1 s complement COM Although not the read modify write in
144. d Buckinghamshire SL8 5FH U K lt 44 gt 1628 585 100 Fax 44 1628 585 900 Renesas Technology Shanghai Co Ltd Un Te it 204 205 AZIACenter No 1233 Lujiazui Ring Rd Pudong District Shanghai China 200120 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2377 3473 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 3518 3399 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel 65 6213 0200 Fax 65 6278 8001 Renesas Technology Korea Co Ltd Ku Tel kje Center Bldg 18th Fl 191 2 ka Hangang ro Yongsan ku Seoul 140 702 Korea 82 2 796 3115 Fax 82 2 796 2145 Renesas Technology Malaysia Sdn Bhd Un Te it 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia 603 7955 9390 Fax 603 7955 9510 2008 Renesas Technology All rights reserved Printed in Japan Colophon 7 2
145. d as the timer count source and the count source is switched in conjunction with a transition between operating modes on chip oscillator mode XIN mode or low speed mode Be careful when changing settings in the CPU mode register 20 2008 127 of 134 4 NE S AS 3805 Notes on Serial 1 1 Write to Baud Rate Generator Write to the baud rate generator while transmission reception is stopped 2 Setting Sequence When Serial l O1 Transmit Interrupt Used To use the serial I O1 transmit interrupt if the interrupt occurrence synchronized with settings is not required take the following sequence 1 Set the serial I O1 transmit interrupt enable bit bit 2 of interrupt control register 2 address 003F16 to 0 disabled 2 Set the transmit enable bit to 1 3 After one or more instructions have been executed set the serial I O1 transmit interrupt request bit bit 2 of interrupt request register 2 address 003D16 to 0 no interrupt 4 Set the serial I O1 transmit interrupt enable bit to 1 enabled lt Reason gt When the transmit enable bit is set to 1 the transmit buffer empty flag bit 0 of serial I O1 status register and the transmit shift completion flag are set to 1 This allows an interrupt request to be generated regardless of which interrupt occurrence source has been selected by the transmit interrupt source selection bit bit 3 of seri
146. d thoroughly on the user side lt Reason gt An analog input pin has a built in capacitor for analog voltage comparison Thus if a signal from the high impedance signal source is input to the analog input pin charge and discharge noise will be generated This may cause the A D conversion comparison accuracy to drop 2 Clock Frequency during A D Conversion The comparator input consists of a capacity coupling If the conversion rate is too low the A D conversion accuracy may deteriorate due to a charge lost so set f XIN 500 kHz or more for A D conversion in XIN mode Also do not execute the STP or WIT instruction during A D conversion In low speed mode when on chip oscillator is selected as A D conversion is performed using the internal on chip oscillator there is no limit on the minimum frequency for f XIN 3 ADKEY Function When the ADKEY enable bit is set to 1 the analog input pin selection bits are disabled Do not execute the A D conversion by a program while ADKEY is enabled Enabling ADKEY does not change bits 0 to 2 of ADCON 4 A D Conversion Immediately After ADKEY Function Started In the ADKEY function A D conversion is not performed to the analog input voltage immediately after starting the function This causes the A D conversion result immediately after starting the function to be undefined If the A D conversion result of the analog input voltage applied to the ADKEY pin is required select the anal
147. d layout patterns Because of these differences characteristic values operation margins noise immunity and noise radiation and oscillation circuit constants may vary within the specified range of electrical characteristics When switching to the QzROM version implement system evaluations equivalent to those performed in the flash memory version Confirm page 11 about the differences of functions May 20 2008 95 01134 RENESAS 3805 Countermeasures against noise 1 Shortest wiring length 1 Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible Especially connect a capacitor across the RESET pin and the Vss pin with the shortest possible wiring within 20 mm Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions If noise having a shorter pulse width than the standard is input to the RESET pin the reset is released before the internal state of the microcomputer is completely initialized This may cause a program runaway Fig 92 Wiring for clock pins 2 Connection of bypass capacitor across Vss line and line In order to stabilize the system operation and avoid the latch up Reset connect an approximately 0 1 uF bypass capacitor across the Vss circuit line and the Vcc line as follows e Connect a bypass capacitor across the Vss pin and the Vcc pin at equal length
148. dded and separates to Table 2 Next page Memory size QZROM version 640 bytes 1536 bytes port 32 pins gt 36 pins Table 3 port I O port revised Table 4 OSCSEL gt CNVss function revised Fig 4 Memory type Flash memory version added Memory Type deleted Memory size QZROM version 640 bytes 1536 bytes Fig 5 Under development products mass produced Table 5 Flash memory version products added Table 6 Notes on Differences between QzROM and Flash Memory Versions added Central Processing Unit revised Fig 8 Flash memory version contents added Notes revised Fig 9 Flash memory version contents added Low XiN mode Low speed XIN mode Memory Flash memory version contents added ROM is revised ROM code Protect Address in QZROM version is revised Fig 10 revised Fig 11 revised Fig 13 Do not write 1 Not used do not write 1 Fig 16 14 Port P60 Revised port Xc switch bit input to low active INTERRUPTS revised Interrupt Source Selection interrupt source selection register interrupt edge selection register e External Interrupt Pin Selection INTo INT1 interrupt switch bit INTo INT1 input port switch bit Fig 19 Do not write 1 Not used do not write 1 Notes Related registers Related bits and its explain is revised Fig 25 Figure title is revised P72 clock output control bit block is revised
149. de 20 2008 Page410f134 RENESAS 3805 Data bus 2 SOURCE l Frequency divider Timer Y dividing frequency selection bit Timer Y operating mode bits 00 01 10 CNTRi interrupt request 0 Pulse width HL continuous o measurement mode o Count source selection bit Rising edge detection Period measurement Falling edge detection mode Timer Y write control bit Timer Y count y stop bit Timer Y low order latch rime Y high order latch 8 CNTR1 active edge switch bit 0 Timer Y interrupt request Timer Y low order 8 Timer Y high order 8 Timer Y operating mode bits Real time port 2 control bit Real time 2 control bit RTP1 data for real time port o Timer Y mode register lt 077 write signal o 51 direction E register P51 latch P51 RTP1 AN1 Real time port 1 control bit 4 Real time port 1 control bit 0 Timer Y mode register i 077 write signal 5 direction g Latch 1 register P50 latch RTPo data for real time port P5o RTPo ANo Note1 SOURCE indicates the followings input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode Fig 31 Bl
150. der COMP3L Timer Y low order TYL Timer Y high order TYH Timer Y mode register TYM Timer Y control register TYCON Interrupt edge selection register INTEDGE CPU mode register CPUM Interrupt request register 1 IREQ1 Interrupt request register 2 IREQ2 Interrupt control register 1 ICON1 Interrupt control register 2 ICON2 PULL register 1 PULL1 PULL register 2 PULL2 PULL register 3 PULL3 Clock output control register CKOUT Segment output disable register 0 SEGO Segment output disable register 1 SEG1 Segment output disable register 2 SEG2 Key input control register KIC ROM correction address 1 high order register RCA1H ROM correction address 2 high order register RCA2H ROM correction address 2 low order register RCA2L ROM correction enable register RCR ROM correction address 1 low order register RCA1L Reserved 1 Reserved 1 Reserved 1 20 2008 19 0 134 sENESAS REJ03B0158 0304 3805 PORTS Direction Registers Ports PO P6 P72 P74 The I O ports 0 6 P72 P74 have direction registers which determine the input output direction of each individual pin Each PULL1 address 0 016 bit in a dire
151. e XIN oscillation frequency 2 XIN oscillation frequency 2 XIN oscillation frequency 4 XIN oscillation frequency 4 XCIN stop XCIN oscillation XCIN stop XCIN oscillation OCO oscillation or stop OCO oscillation or stop OCO oscillation or stop OCO oscillation or stop f XiN 2 f XiN 2 4 f XIN 4 CM7 0 CM7 0 CM7 1 CM7 1 CM6 0 CM6 0 CM6 0 CM6 0 5 0 5 0 5 0 5 0 CM4 0 CM4 1 CM4 0 CM4 1 CM3 0 8 CM3 0 8 CM3 0 CM8 CM3 0 CM8 The oscillating at 0 the stopped at 1 CPU mode register 2 b7 bO CPUM2 Notes 1 Switch the mode by the arrows shown between the mode blocks cmg address 001116 version OSCSEL L initial value 0016 The all modes can be switched to the stop mode or the wait mode QzROM version OSCSEL Hiinitial value 0116 2 Timer and LCD operate in the wait mode System is returned to the Flash memory version initial value 0016 Source mode when the wait mode is ended L On chip oscillator stop bit 3 The CM4 value is retained in the stop mode When the stop mode is 0 Oscillating ended the operation mode varies as follows 1 Stopped In the 2 version Mode set by the OSCSEL pin state Not used do not write 1 In the flash memory version On chip oscillator mode Not used The input level applied to the OSCSEL pin is determined when returns 0 when read executing the STP instruction Not used
152. e Access to this area with only 2 bytes is possible in the zero page addressing mode Special Page Access to this area with only 2 bytes is possible in the special page addressing mode ROM Code Protect Address in QZROM Version Address FFDBt6 Address FFDB16 as reserved ROM area in the QZROM version is ROM code protect address 0016 or 16 is written into this address when selecting the protect bit write by using a serial programmer and selecting protect enabled for writing shipment by Renesas Technology Corp When 0016 or FE16 is set to the ROM code protect address the protect function is enabled so that reading or writing from to the corresponding area is disabled by a serial programmer As for the QzROM product in blank the ROM code is protected by selecting the protect bit write at ROM writing with a serial programmer The protect can be performed dividing twice The protect area 1 is from the beginning address of ROM to address 16 As for the QzROM product shipped after writing 0016 protect enabled to all area 16 protect enabled to the protect area 1 or 16 protect disabled is written into the ROM code protect address when Renesas Technology Corp performs writing The writing of 0016 16 or FF16 can be selected as ROM option setup option written in the mask file converter when ordering For the ROM code protect in the fla
153. e bit Serial 2 receive transmit interrupt enable bit CNTRo interrupt enable bit m Y interrupt enable bit CNTR interrupt enable bit AD conversion interrupt enable bit Not used do not write to 1 0 Interrupts disabled 1 Interrupts enabled 3805 Interrupt Request Generation Acceptance Handling Interrupts have the following three phases i Interrupt Request Generation An interrupt request is generated by an interrupt source external interrupt signal input timer underflow etc and the corresponding request bit is set to 1 ii Interrupt Request Acceptance Based on the interrupt acceptance timing in each instruction cycle the interrupt control circuit determines acceptance conditions interrupt request bit interrupt enable bit and interrupt disable flag and interrupt priority levels for accepting interrupt requests When two or more interrupt requests are generated simultaneously the highest priority interrupt is accepted The value of interrupt request bit for an unaccepted interrupt remains the same and acceptance is determined at the next interrupt acceptance timing point iii Handling of Accepted Interrupt Request The accepted interrupt request is processed Figure 20 shows the time up to execution in the interrupt routine and Figure 21 shows the interrupt sequence Figure 22 shows the timing of interrupt request generation interrupt request bit and interrupt request ac
154. e control circuit of internal flash memory 5 Write to this bit in program on RAM This bit is used when flash memory access has failed When the CPU rewrite mode select bit is 1 setting 1 for this bit resets the control circuit To release the reset it is necessary to set this bit to 0 Bit 5 of the flash memory control register 0 is the User ROM area select bit and is valid only in the boot mode Setting this bit to 1 in the boot mode switches an accessible area from the boot Fig 71 Structure of flash memory control register 0 ROM area to the user ROM area To use the CPU rewrite mode in the boot mode set this bit to 1 To rewrite bit 5 execute the user original reprogramming control software transferred to the internal RAM in advance Bit 6 of the flash memory control register O is the program status flag This bit is set to 1 when writing to flash memory is failed When program error occurs the block cannot be used Bit 7 of the flash memory control register O is the erase status flag Flash memory control register 1 FMCR1 address 0 116 initial value 4016 Erase Suspend enable bit 0 Suspend invalid 1 Suspend valid Erase Suspend request bit 0 Erase restart 1 Suspend request Not used do not write 1 to this bit This bit is set to 1 when erasing flash memory is failed When Erase Suspend flag erase error occurs the block cannot be us
155. e to only one of them When the above mode is set and timer X operates as the 16 bit counter if the timer X register extension is never set after reset is released setting the timer X register extension is not required In this case write the timer X register low order first and the timer X register high order However once writing to the timer X register extension is executed note that the value is retained to the reload latch Write to the timer X register by the 16 bit unit Do not read the timer X register while write operation is performed If the write operation is not completed normal operation will not be performed In the IGBT output and PWM modes do not write 1 to the timer X register extension Also when 1 is already written to the timer X register be sure to write 0 to the register before using Write to the following registers in the order as shown below the compare registers 1 2 3 high and low order the timer X register extension the timer X register low order the timer X register high order It is possible to use whichever order to write to the compare registers 1 2 3 high and low order However write both the compare registers 1 2 3 and the timer X register at the same time For the compare registers set a value less than the setting value in the timer X register Also do not set 0016 Rev 3 04 REJ03B0158 0304 ts One period of timer X count source
156. e with the oscillator manufacturer s recommended values No external resistor is needed between XIN and XOUT since a feed back resistor exists on chip An external feed back resistor may be needed depending on conditions However an about 10 external feedback resistor is needed between XCIN and XCOUT The 38D5 Group operation mode immediately after reset depends on the OSCSEL pin state in the QZROM version When the OSCSEL pin state is GND level the only on chip oscillator starts oscillating The XIN XOUT oscillation stops oscillating and XCIN and XCOUT pins function as I O ports Flash memory version as same When the OSCSEL pin state is Vcc level the XIN XOUT oscillation divided by 8 starts oscillating The on chip oscillator stops oscillating and the XCIN and XCOUT pins function as I O ports Note the following in each mode Mode The XIN XOUT oscillation does not stop even if the XIN XOUT oscillation stop bit is set to 1 Low Speed Mode The XCIN XCOUT oscillation stops if the port XC switch bit is set to 0 On Chip Oscillator Mode Even if the on chip oscillator stop bit is set to 1 the on chip oscillator oscillation does not stop in the flash memory version but stops in the version Rev 3 04 REJ03B0158 0304 Frequency Control 1 On chip oscillation mode The system clock 6 is the on chip oscillator oscillation divided by 32 2 mode Frequency 2 mode freque
157. ead array 1 Write X4 FF16 Read status register 2 Write X 7016 Read X 5 Clear status register 1 Write X 5016 Program 2 Write X 4016 Write WD 2 Block erase 2 Write X 2016 Write BAG D016 NOTES 1 SRD Status Register Data 2 WA Write Address WD Write Data 3 BA Block Address to be erased Input the maximum address of each block 4 X denotes a given address the User ROM area Rev 3 04 REJ03B0158 0304 20 2008 Page 79 01134 RENESAS 3805 Block Erase Command 2016 0016 By writing the command code 2016 in the first bus cycle and the confirmation command code D016 and the block address in the second bus cycle that follows the block erase erase and erase verify operation starts for the block address of the flash memory to be specified Whether the block erase operation is completed can be confirmed Write 2016 by read status register or the RY BY status flag of flash memory control register To read the status register write the status register command 7016 The status register bit 7 SR7 is set to 0 at the same time the block erase operation starts and returned Block address to 1 upon completion of the block erase operation The read status mode at this time remains active until the read array command FF16 is written Read status register The RY BY status flag register is set to 0 during block erase operation and 1
158. ed 0 Erase active Figure 72 shows the flash memory control register 1 1 Erase inactive Erase Suspend mode Bit 0 of the flash memory control register 1 is the Erase suspend enable bit By setting this bit to 1 the erase suspend mode to suspend erase processing temporary when block erase command Notes 1 For this bit to be set to 1 the user needs to write 0 and then is executed can be used In order to set this bit O to 1 writing ce GAYO 0 and 1 in succession to bit 0 In order to set this bit to 0 2 Effective only when the suspend enable bit 1 write 0 only to bit 0 Bit 1 of the flash memory control register 1 is the erase suspend request bit By setting this bit to 1 when erase suspend enable bit is 1 the erase processing is suspended Bit 6 of the flash memory control register 1 is the erase suspend flag This bit is cleared to 0 at the flash erasing Not used do not write 1 to this bit Fig 72 Structure of flash memory control register 1 Rev 3 04 20 2008 76 0 134 stENESAS REJ03B0158 0304 3805 50 Flash memory control register 2 FMCR2 address 0 216 initial value 4516 Not used return 1 when read Not used do not write 1 to this bit Not used return 1 when read Not used return 0 when read User block
159. ed CNVss gt OSCSEL Frequency name revised ROSC Mode name revised Middle High speed mode 2 4 8 mode Bit names of some registers 1 ROSC stop bit gt On chip oscillator stop bit 2 STP instruction disable bit STP instruction function selection bit 3 Vector 1 enable bit RCO ROM correction address 1 enable bit RCO 4 Vector 2 enable bit RC1 ROM correction address 2 enable bit RC1 5 Vector control bit RC2 ROM correction memory selection bit RC2 Description Power source voltage and Power dissipation revised Table 2 Pin description 1 Some description of Port P1 Function revised Table 3 Pin description 2 Description of OSCSEL added Fig 5 Memory expansion plan Table 4 Support products M38D59GFFP HP M38D59GCFP HP added Some description revised Fig 8 Structure of CPU mode register Note on on chip oscillator added Fig 9 Switch procedure of CPU mode register Initial values of CPUM2 added and initial value of CPUM revised Fig 10 Memory map diagram Reserved ROM area FFD416 to FFDC16 gt FFDO16 to FFDC16 Note on ROM correction vector added Fig 11 Memory map of special function register SFR Reserved area is added to address OFFD16 and Note added Table 8 Termination of unused pins XIN and Xour pin termination added ROM CORRECTION FUNCTION Description and some bit names revised and Fig 47 Memory map of M38D58 added Initial
160. ed bit is set to output mode the port latch is normally read but the peripheral function output is read in some ports and the value is written to the port latch At this time if the original content of the port latch and the peripheral function output do not match the content of the port latch changes Bit handling instructions CLB SEB 2 Read modify write instruction Reads 1 byte of data from memory modifies the data and writes 1 byte of the data to the original memory 20 2008 Page 123 of 134 4 NE S AS 3805 3 Direction Registers The values of the port direction registers cannot be read This means it is impossible to use the LDA instruction memory operation instruction when the T flag is 1 addressing mode using direction register values as qualifiers and bit test instructions such as BBC and BBS It is also impossible to use bit operation instructions such as CLB and SEB and read modify write instructions to direction registers including calculations such as ROR To set the direction registers use instructions such as LDM or STA 4 Pull Up Conirol Only for the pin set to input mode pull up is controlled by the PULL register and the segment output disable register Rev 3 04 REJ03B0158 0304 Notes on Termination of Unused Pins 1 Termination of Unused Pins Perform the following at the shortest possible distance 20 mm or less from the MCU pins 1 I O ports Set the
161. ed to output mode due to a program runaway or noise a short circuit may occur between the ports 20 2008 Page 124 of 134 4 N S AS 3805 Notes on Interrupts 1 Changing Related Register Settings If the interrupt occurrence synchronized with the following settings is not required take the sequence shown below When selecting the external interrupt active edge When selecting the interrupt source of the interrupt vector address where two or more interrupt sources are allocated Set the corresponding interrupt enable bit to 0 disabled Set the interrupt edge selection bit active edge Switch bit or interrupt source selection bit NOP one or more instructions Set the corresponding interrupt request bit to 0 no interrupt request Set the corresponding interrupt enable bit to 1 enabled Fig 102 Sequence for setting related register lt Reason gt In the following cases the interrupt request bit of the corresponding interrupt may be set to 1 lt When switching the external interrupt active edge gt INTo interrupt edge selection bit bit 0 of interrupt edge selection register address 003A16 INT interrupt edge selection bit bit 1 of interrupt edge selection register INT interrupt edge selection bit bit 2 of interrupt edge selection register CNTRo active edge switch bits bits 6 and 7 of timer X control
162. egister 003816 0016 Port P7 direction register 000 1 0016 Timer Y control register 003916 0016 CPU mode register 2 001116 010 Interrupt edge selection register 003A16 0016 register 001216 0016 CPU mode register 003 16 010 LCD mode register 1 001316 0016 Interrupt request register 1 003Ci6 0016 LCD mode register 2 001416 0016 Interrupt request register 2 003016 0016 AD control register 001516 0816 Interrupt control register 1 003 16 0016 Serial 1 status register 001916 010 Interrupt control register 2 003F 16 0016 Serial 1 01 control register 001A16 0016 PULL register 1 OFF0t6 0016 UART control register 001 16 010 PULL register 2 OFF 116 0016 Serial 1 02 control register 001016 0016 PULL register 3 OFF 216 0016 Timer 1 002016 16 Clock output control register OFF316 0016 Timer 2 002116 0116 Segment output disable register 0 OFF 416 FF16 Timer 3 002216 FFie Segment output disable register 1 OFF 516 FFie Timer 4 002316 16 Segment output disable register 2 OFF616 OF 16 PWM01 register 002416 0016 Key input control register OFF716 0016 Timer 12 mode register 002516 0016 ROM correction address 1 high order OFF816 0016 Timer 34 mode register 002616 0016 ROM correction address 1 low order OFF916 0016 Timer 1234 mode register 002716 0016 ROM correction address 2 high order 16 0016 division 002816 0016 ROM correction address 2 low order OFFBi6 0016 Watchdog timer control register 002916 0 0 1 1 1 1 1 ROM
163. ency 1 4 5V lt Vcc lt 5 5V 6 25 on chip oscillator 4 0V lt Vcc lt 4 5V 4 0 mode excluded 2 7 Ncc lt 4 0V Vcc NOTE 1 Confirm the recommended operating condition for main clock input frequency Rev 3 04 20 2008 11401134 42 N S AS REJ03B0158 0304 3805 FLASH MEMORY VERSION Table 41 A D converter characteristics Vcc 2 7 to 5 5 V Ta 20 to 85 C output transistors in cut off state low speed on chip oscillator mode included unless otherwise noted Limits Typ Parameter Test conditions Resolution Absolute accuracy 10bitAD 4 5V lt Vcc lt 5 5V quantification error mode AD conversion clock f XIN 2 f XIN 8 lt 6 25MHz excluded 4 0V lt Voc lt 4 5V AD conversion clock f XIN 2 f XIN 8 lt 4MHz 2 7 lt Voc lt 4 0V AD conversion clock f XiN 2 f XIN 8 lt VccMHz 2 7V lt Vcc lt 5 5 f OCO 8 f OCO 32 8bitAD 4 5 lt Vcc lt 5 5V mode AD conversion clock f XIN 2 f XiN 8x6 25MHz 4 0V lt Voc lt 4 5V AD conversion clock f XIN 2 8 lt 4 2 2 7N lt Voc lt 4 0V AD conversion clock f XIN 2 f XIN 8 lt VccMHz 2 7 lt Vcc lt 5 5 f OCO 8 f OCO 32 tCONV Conversion 10bitAD mode x 61 x 62 8bitAD mode tc pAD x 49 x 50 RLADDER Ladder resistor 12 100 IVREF Reference input VREF 5V
164. enough time for oscillation to stabilize by programming to restart the stopped oscillation and switch the operation mode Also set enough time for oscillation to stabilize by programming to switch the timer count source lt Notes on Clock Generating Circuit gt If you switch the mode between on chip oscillator mode XIN mode and low speed mode stabilize both XIN and XCIN oscillations Especially be careful immediately after power on and at returning from stop mode Refer to the clock state transition diagram for the setting of transition to each mode Set the frequency in the condition that f XIN gt 3 f XCIN When the XIN mode is not used XIN XOUT oscillation and external clock input are not performed connect XIN to Vcc through a resistor 20 2008 Page630f134 sENESAS 3805 Oscillation Control 1 Stop Mode If the STP instruction is executed the system clock stops at an level and main clock and sub clock oscillators stop Tn this time values set previously to timer 1 latch and timer 2 latch are loaded automatically to timer 1 and timer 2 Set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch low order 8 bits of timer 1 and high order 8 bits of timer 2 before the STP instruction The frequency divider for timer 1 is used for the timer 1 count source and the output of timer 1 is forcibly connected to timer 2 In this time
165. er Y underflow At detection of either rising or falling edge of 1 input At completion of A D conversion At BRK instruction execution Valid when INT2 interrupt is selected External interrupt active edge selectable Valid when Key input interrupt is selected External interrupt falling valid Key input FFF516 FFF416 wakeup Timer X Timer 1 Timer 2 Timer 3 Timer 4 Serial 1 01 receive Serial 1 transmit FFF316 FFF 116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFF216 FFF016 FFEE16 FFECi6 FFEA16 FFE816 FFE616 Serial 2 516 416 16 FFE216 External interrupt active edge selectable Timer Y FFE116 FFEO16 External interrupt active edge selectable FFDF16 FFDD16 FFDE16 FFDC16 A D conversion BRK instruction NOTES 1 Vector addresses contain interrupt jump destination addresses 2 Reset function in the same way as an interrupt with the highest priority 3 INTo and INT1 input pins are selected by the interrupt edge selection register INTEDGE Non maskable software interrupt Rev 3 04 20 2008 Page 28 01134 stENESAS REJ03B0158 0304 3805 Interrupt request bit Interrupt enable bit Interrupt disable flag 1 BRK instruction Fig 18 Interrupt control Interrupt Disable Flag The interrupt disable flag is assigned to bit 2 of the processor status re
166. er to the recommended operating conditions of the A D converter 3 12 5 MHz f XiN x 16 MHz is not available in the frequency 2 mode 4 The oscillation start voltage and the oscillation start time differ depending on factors such as the oscillator circuit constants and operaning temperature range Note that oscillation start may be particularly difficult at low voltage when using a high frequency oscillator 5 When using the microcomputer in low speed mode set the clock input oscillation frequency on condition that f XcIN lt 3 System clock frequency Main clock XIN frequency System clock frequency Main clock XIN frequency 0 2 7 4 0 4 5 5 5 V 0 2 7 45 Power source voltage 5 5 V Power source voltage Rev 3 04 20 2008 Page 112 01134 stENESAS REJ03B0158 0304 3805 FLASH MEMORY VERSION Electrical Characteristics Table 38 Electrical characteristics 1 Vcc 2 7 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter Test conditions output voltage lOH 2 5 00 07 10 17 20 27 P30 P37 output voltage loH 5mA 40 47 50 57 P60 P67 1 25 72 74 1 output voltage L 5mA P0o PO7 P10 P17 P20 P27 L 1 25mA P30 P37 output voltage L 10mA 40 47 P5o P57 P60 P67 L 2 5mA P72 P74 1 L output voltage L 15mA P62 P67 Hysteresis INToo INTo1 INT10 INT11 INT2 CNTRo
167. estion marks indicate an undefined state 3 In the QZROM version the input level applied to the OSCSEL pin is determined when the RESET pin changes from L to H Fig 58 Reset sequence Rev 3 04 20 2008 Page610f134 stENESAS REJ03B0158 0304 3805 Address Register contents Address Register contents Port PO 000016 0016 Timer X low order 002 16 16 Port direction register 000116 0016 Timer X high order 002816 16 Port P1 000216 0016 Timer X extension 002 16 0016 Port P1 direction register 000316 0016 Timer X mode register 002016 0016 Port P2 000416 0016 Timer X control register 1 002 16 0016 Port P2 direction register 000516 0016 Timer control register 2 002Fi6 0016 Port P3 000616 0016 Compare register 1 low order 003016 0016 Port direction register 000716 0016 Compare register 1 high order 003116 0016 Port P4 000816 0016 Compare register 2 low order 003216 0016 Port P4 direction register 000916 0016 Compare register 2 high order 003316 0016 Port P5 000 1 0016 Compare register 3 low order 003416 0016 Port P5 direction register 000 1 0016 Compare register 3 high order 003516 0016 Port P6 000Ci6 0016 Timer Y low order 003616 FF16 Port P6 direction register 000016 0016 Timer high order 003716 FFie Port P7 000 16 0016 Timer Y mode r
168. evel CMOS 3 state output Serial 1 function I O PULL register 3 Serial 1 01 control register Serial 1 status register UART control register A Serial 1 02 function Key input key on wakeup interrupt input PULL register 3 Serial 1 02 control register Serial 2 register Key input control register e P50 ANo RTPo P51 AN1 RTP1 Port P5 P52 AN2 P56 AN6 P57 AN7 ADKEYo Input Output individual bits CMOS compatible input level CMOS 3 state output A D conversion input Real time port function output PULL register 1 AD control register Timer Y mode register k ADKEY input PULL register 1 AD control register P60 XCIN P61 XCOUT P62 INToo LEDo Port P6 P63 TXOUT2 LED1 P64 INT2 LED2 P65 Txour1 LED3 P66 INT10 CNTRo LED4 P67z CNTR1 LED5 Input Output individual bits CMOS compatible input level CMOS 3 state output Sub clock oscillation circuit PULL register 2 CPU mode register External interrupt input PULL register 2 Interrupt edge selection register Timer X output 2 PULL register 2 Timer X mode register Timer X control registers 1 2 External interrupt input PULL register 2 Interrupt edge selection register Timer X output 1 PULL register 2 Timer X mode register Timer X control register 1 Timer X function input External interrupt input PULL
169. ey input interrupt is controlled by the key input control register and port direction registers When the key input interrupt is enabled set 1 to the key input control register A key input of any pin of ports P20 P23 P44 P47 that have been set to input mode is accepted Key input control register address OF F716 P44 key input control bit P45 key input control bit P46 key input control bit P47 key input control bit 20 key input control bit P21 key input control bit P22 key input control bit P23 key input control bit 0 Key input interrupt disabled 1 Key input interrupt enabled Fig 24 Structure of key input control register Rev 3 04 20 2008 Page340f134 stENESAS REJ03B0158 0304 3805 TIMERS 8 Bit Timer The 3805 Group has four built in 8 bit timers Timer 1 Timer 2 Timer 3 and Timer 4 1 SOURCE 8 Clock for Timer 1 Timer Y output The following values can be selected the clock for Timer 1 1 1 2 1 16 1 256 Q 5 3 2 JOU 10 0012 if 10 32010 it 10 19019 P72 clock output control bit Clock for System clock P72 T20uT CKOUT 00 Timer Frequency divider Lag 4 Timer 2 Timer 3 Timer Timer 2 5 Timer 2 output selection b
170. falling edges of CNTR pin input signal Except for that this mode operates just as in the period measurement mode When using this mode set the port sharing the CNTR pin to input mode 5 Real Time Port Control When the real time port function is valid data for the real time port is output from ports P50 and P51 each time the timer Y underflows However if the real time port control bit is changed from 0 to 1 after the data for real time port is set data is output independent of the timer Y operation When the data for the real time port is changed while the real time port function is valid the changed data is output at the next underflow of timer Y Before using this function set the P50 and P51 port direction registers to output 20 2008 Page 420f134 RENESAS 3805 lt Notes Timer Y gt CNTR Interrupt Active Edge Selection CNTR1 interrupt active edge depends on the CNTR active edge switch bit However in pulse width HL continuously measurement mode 1 interrupt request is generated at both rising and falling edges of pin input signal regardless of the setting of CNTR1 active edge switch bit Timer Y Read Write Control When reading from writing to timer Y read from write to both the high order and low order bytes of timer Y When the value is read read the high order bytes first and the low order bytes next When the value is written write the low order b
171. for writing to flow into the built in QzZROM Because of this noise can enter easily If noise enters the OSCSEL pin abnormal instruction codes data are read from the which may cause program runaway Termination of OSCSEL pin 2 OSCSEL H The shortest Of The shortest 12 1 OSCSEL L OSCSEL about 5 about 5 OSCSEL lt 1 he shortest a The shortest 77 Note 1 It shows the pin Fig 107 Wiring for OSCSEL pin Overvoltage in QZROM Version Make sure that voltage exceeding the VCC pin voltage is not applied to other pins In particular ensure that the state indicated by bold lines in figure below does not occur for pin OSCSEL pin VPP power source pin for QZROM during power on or power off Otherwise the contents of QZROM could be rewritten 22 1 1 2 1 8V 1 e 1 8V Vcc pin voltage i 1 u i 1 OSCSEL pin voltage 1 H input OSCSEL pin voltage 1 L input 22 1 Input voltage to other MCU pins rises before Vcc pin voltage 2 Input voltage to other MCU pins falls after Vcc pin voltage Note The internal circuitry is unstable when Vcc is below the minimum voltage specification of 1 8 V shaded portion so particular care should be exercised regarding overvoltage Fig 108 Timing Diagram Bold lined periods are applicable Rev 3 04 REJ03B0158 0304 QzROM Version Product Shipped
172. gister This flag controls the acceptance of all interrupt requests except for the BRK instruction When this flag is set to 1 the acceptance of interrupt requests is disabled When it is set to 0 acceptance of interrupt requests is enabled This flag is set to 1 with the SEI instruction and set to 0 with the CLI instruction When an interrupt request is accepted the contents of the processor status register are pushed onto the stack while the interrupt disable flag remains set to 0 Subsequently this flag is automatically set to 1 and multiple interrupts are disabled To use multiple interrupts set this flag to 0 with the CLI instruction within the interrupt processing routine The contents of the processor status register are popped off the stack with the RTI instruction Interrupt Request Bits Once an interrupt request is generated the corresponding interrupt request bit is set to 1 and remains 1 until the request is accepted When the request is accepted this bit is automatically set to 0 Each interrupt request bit can be set to 0 but cannot be set to 1 by software Interrupt Enable Bits The interrupt enable bits control the acceptance of the corresponding interrupt requests When an interrupt enable bit is set to 0 the acceptance of the corresponding interrupt request is disabled If an interrupt request occurs in this condition the correspondi
173. gister to 1 writing to latch only After writing to the timer X register high order the contents of both registers are simultaneously reflected in the output waveform at the next underflow 12 Timer X Output Control Functions To use the output control functions INT1 and INT2 set the levels of INT1 and INT2 to H for the falling edge active or to L for the rising edge active before switching to IGBT output mode 13 CNTRo Active Edge Selection 1 Setting the active edge switch bits also affects the interrupt active edge at the same time 2 When the pulse width is measured set bit 7 of the CNTRo active edge switch bits to 0 14 When Timer X Pulse Width Measurement Mode Used When timer X pulse mode measurement mode is used enable the event counter wind control data bit 5 of timer X mode register address 002D16 by setting to 0 Reason If the event counter window control data bit 5 of timer X mode register address 002D16 is set to 1 disabled to enable disable the CNTRo input the input is not accepted after the timer 1 underflow Rev 3 04 REJ03B0158 0304 15 CNTR1 Active Edge Selection Setting the CNTR active edge switch bits also affects the interrupt active edge at the same time However in pulse width HL continuous HL measurement mode the CNTR interrupt request is generated at both rising and falling edges of the pin regardless of the settings of
174. gt Pi6 SEG22 lt gt P17 SEG23 a B D gt 54 lo loo Io lo lo lon I gt ln lov F 45 M38D59FFFP Flash memory version lt gt P3o SEG24 lt gt P31 SEG25 gt P32 SEG26 lt gt P33 SEG27 lt gt P34 SEG28 lt gt P3s SEG29 gt P3e SEGs0 lt gt P37 SEG31 COM7 SEG32 6 5 COMS SEGa4 4 5 5 COM gt COMO P56e ANe lt gt P55 ANs lt P54 AN4 gt 5 lt gt P52 AN2 lt gt ERIS A Eri lt P o 4 4 8 VLi 9 VL2 P71 C2 INT11 IB P61 Xcour gt 4 Vss Vcc P70 C1 INTo i 3 51 1 1 gt P50 ANo RTPo 4 P67 CNTR1 P66 INT10 CNTRo 65 P74 PWM1 T40oUT lt gt P73 PWMo Tsour lt gt P72 T20ut CKOUT gt
175. h pin to be individually programmed as either input or output Pull up control is enabled in 4 bit unit Key input interrupt input pins P40 RxD P41 TxD P42 ScLk1 P43 SRDY1 P44 SiN2 KWo P45 Sout2 KW1 P46 Scik2 KW2 47 5 Rev 3 04 port P4 May 20 2008 Page 7 of 134 REJ03B0158 0304 8 bit I O port CMOS compatible input level CMOS 3 state output structure O direction register allows each pin to be Serial 1 01 function pins individually programmed as either input or output Pull up control is enabled in 4 bit unit 131 NE SAS Serial 1 02 function pins Key input interrupt input pins 3805 Table 4 Pin Pin description 2 Name Function Function except a port function P50 ANo RTPo P51 AN1 RTP1 P52 AN2 56 P57 AN7 ADKEYo port P5 8 bit I O port CMOS compatible input level CMOS 3 state output structure O direction register allows each pin to be individually programmed as either input or output Pull up control is enabled in a bit unit AD converter input pins Real time port function pins ADKEY input pin P60 XCIN P61 XcouT P62 INToo LEDo Pes Txour2 LED1 P64 INT2 LED2 P65 TxouT1 LED3 P66 INT10 CNTRo LED P67 CNTR1 LEDs port P6 8 bit I O port CMOS compatible
176. hat the contents of internal flash memory are protected against readout and modification The ROM code protect is implemented in two levels If level 2 is selected the flash memory is protected even against readout by a shipment inspection LSI tester etc When an attempt is made to select both level 1 and level 2 level 2 is selected by default If both of the two ROM code protect reset bits are set to 00 the ROM code protect is turned off so that the contents of internal flash memory can be readout or modified Once the ROM code protect is turned on the contents of the ROM code protect reset bits cannot be modified in parallel I O mode Use standard serial mode or other modes to rewrite the contents of the ROM code protect disable bits Rewriting of only the ROM code protect control address address FFDB i16 cannot be performed When rewriting the ROM code protect reset bit rewrite the whole user ROM area block 0 containing the ROM code protect control address ROM code protect control address address FFDBt6 ROMCP when shipped Reserved bits 1 at read write ROM code protect level 2 set bits ROMCP2 2 b3b2 0 0 Protect enabled 0 1 Protect enabled 1 0 Protect enabled 1 1 Protect disabled ROM code protect reset bits b5b4 0 0 Protect removed 0 1 Protect set bits effective 1 0 Protect set bits effective 1 1 Protect set bits effective ROM code protect level 1 set bits
177. he CNTRo active edge switch bits is 0 counting is executed during the interval of CNTRo pin input When the bit is 1 counting is executed during the L interval of CNTRo pin input When using this mode set the port sharing the pin to input mode Also set to enable 0 the data for control of event counter window bit 5 of timer X mode register address 002D16 20 2008 39 01134 RENESAS 3805 Timer count source Timer X PWM mode IGBT output mode output mode TXOUT1 output bit 5 0 External trigger INTo source is generated Level is H only IGBT INT or INT2 source is generated TXOUT2 output TXCON bit 1 0 Level is forcibly L only IGBT output mode LEG n Timer X setting value m Compare register 1 setting value n 1 x ts p Compare register 2 setting value q Compare register 3 setting value The following PWM waveform is output Duty of TXOUT1 output n 1 m n 1 Duty of TXOUT2 output p q n 1 Period n 1 x ts Fig 29 Waveform of PWM IGBT lt Notes on Timer X gt 1 Write Order to Timer X In the timer mode pulse output mode event counter mode and pulse width measurement mode write to the following registers in the order as shown below the timer X register extension the timer X register low order the timer X register high order Do not writ
178. he P41 TxD P channel output disable bit bit 4 of address 001B16 of UART control register is 0 Table 33 Switching characteristics 2 Vcc 1 8 to 4 0 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limits NOTE 1 The P41 TxD P channel output disable bit bit 4 of address 001B16 of UART control register is O Fig 95 Circuit for measuring output switching characteristics Rev 3 04 Measurement output pin REJ03B0158 0304 m A CMOS output Measurement output pin 100 N channel open drain output Note address 001 16 is 1 N channel open drain output mode 20 2008 107 of 134 pRENESAS Note When bit 4 of the UART control register Symbol Parameter Min Max Unit twH ScLk1 Serial 1 01 clock output pulse width tc Scuk1 2 80 ns twL ScLk1 Serial l O1 clock output L pulse width tc Scuk1 2 80 ns td ScLk1 TxD Serial 1 01 output delay time 1 350 ns tv ScLk1 TxD Serial l O1 output valid time 1 30 ns tr SCLK1 Serial 1 01 clock output rising time 80 ns tf ScLK1 Serial 1 01 clock output falling time 80 ns twH ScLk2 Serial 1 02 clock output H pulse width tc ScLk2 2 80 ns twL ScLk2 Serial 1 2 clock output L pulse width tc ScLk2 2 80 ns tf ScLk2 Serial 1 02 clock output falling time 80 ns td ScLk2 SouTz Serial 1 O2 output delay ti
179. he receive interrupt RI is set when the RBF flag becomes 1 4 After data is written to the transmit buffer when TSC flag 1 0 5 to 1 5 cycles of the data shift cycle is necessary until changing to TSC flag 0 TBE 1 4 _ _ _ 70 8 data bit 1 start bit 1 or 0 parity bit 1 or 2 stop bit s TSC 1 s Generated at 2nd bit in 2 stop bit mode RBF 1 RBF 1 4 _ o ALS XY Fig 36 Operation of UART serial 1 function Rev 3 04 REJ03B0158 0304 20 2008 45 01134 5 5 3805 Transmit Buffer Register Receive Buffer Register TB1 RB1 The transmit buffer register and the receive buffer register are located at the same address The transmit buffer is write only and the receive buffer is read only If a character bit length is 7 bits the MSB of data stored in the receive buffer is 0 Serial 1 01 Status Register SIO1STS The read only serial I O1 status register consists of seven flags bits O to 6 which indicate the operating status of the serial I O function and various errors Three of the flags bits 4 to 6 are valid only in UART mode The receive buffer full flag bit 1 is set to 0 when the receive buffer register is read If there is an error it is detected at the same time that data is transferred from
180. he watchdog timer does not stop 2 When bit 6 is 1 execution of STP instruction causes an internal reset When this bit is set to 1 once it cannot be rewritten to 0 by program Bit 6 is 0 at reset 3 The time until the underflow of the watchdog timer register after writing to the watchdog timer control register is exe cuted is as follows when the bit 7 of the watchdog timer control register is 0 4 at XIN mode f XIN 8 MHz 32 768 ms 5 at low speed mode f XCIN 32 KHz 8 195 lt Notes gt 1 The watchdog timer continues to count even during the wait time set by timer 1 and timer 2 to release the stop state and in the wait mode Accordingly write to the watchdog timer control register to not underflow the watchdog timer in this time 2 When the on chip oscillator is selected by the watchdog timer count source selection bit 2 the on chip oscillator forcibly oscillates and it cannot be stopped Also in this time set the STP instruction function selection bit to 1 at this time Select 0 QSOURCE the watchdog timer count source selection bit 2 at the system which on chip oscillator is stopped Data bus 1 1024 H 1 qr SOURCE a On chip oscillator 1 4 Watchdog timer L 3 Watchdog timer H 5 1 gt 1 4 Undefined instruction Reset 16 is set when watchdog timer
181. illator mode 2 When the ADKEY enable bit is 1 the analog input pin selection bits are invalid Do not execute the A D conversion by program while the ADKEY is enabled Bit 0 to bit 2 of ADCON are not changed even when ADKEY is enabled Address 001716 Fig 42 Structure of AD control register Rev 3 04 REJ03B0158 0304 ADKEY function The ADKEY function is used to judge the analog input voltage input from the ADKEY pin When the A D converter starts operating after VIL 0 7 x 0 5 or less is input the event of analog voltage input can be judged with the A D conversion interrupt This function can be used with the STP and WIT state As for the ADKEY function in 38D5 Group the A D conversion of analog input voltage immediately after starting ADKEY function is not performed Therefore the A D conversion result immediately after an ADKEY function is undefined Accordingly when the A D conversion result of the analog input voltage input from the ADKEY pin is required start the A D conversion by program after the analog input pin corresponding to ADKEY is selected ADKEY Selection When the ADKEY pin is used set the ADKEY selection bit to 1 The ADKEY selection bit is 0 just after the A D conversion is started ADKEY Enable The ADKEY function is enabled by writing 1 to the ADKEY enable bit Surely in order to enable ADKEY function set 1 to the ADKEY enable bit after setting the
182. in Blank As for the product shipped in blank Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process Therefore a writing error of approximate 0 1 may occur Moreover please note the contact of cables and foreign bodies on a socket etc because a writing environment may cause some writing errors Ordering Writing 1 Notes On QzROM Writing Orders When ordering the 2 product shipped after writing submit the mask file extension msk which is made by the mask file converter MM Be sure to set the ROM option data setup when making the mask file by using the mask file converter MM The ROM code protect is specified according to the ROM option data in the mask file which is submitted at ordering Note that the mask file which has nothing at the ROM option data or has the data other than 0016 FE16 and FF16 can not be accepted Set FF16 to the ROM code protect address in ROM data regardless of the presence or absence of a protect When data other than FF16 is set we may ask that the ROM data be submitted again ROM option data mask option noted in MM 2 Data Required for QZROM Ordering The following are necessary when ordering a QZROM product shipped after writing OzROM Writing Confirmation Form Mark Specification Form ROM data Mask file For the QzROM writing
183. ind control data bit 5 of timer X mode register address 002D16 by setting to 0 lt Reason gt If the event counter window control data bit 5 of timer X mode register address 002D16 is set to 1 disabled to enable disable the CNTRo input the input is not accepted after the timer 1 underflow Timer X mode register TXM address 002D16 bo Timer X control register 1 TXCON1 address 002 16 Timer operating mode bits b2b1b0 0 0 0 Timer mode 0 1 Pulse output mode 0 IGBT output mode 1 PWM mode 0 Event counter mode 0 0 0 Pulse width measurement mode Not available 1 Not available Timer X write control bit 0 Write data to both timer latch and timer 1 Write data to timer latch only Timer X count source selection bit 0 Frequency divider output 1 f XCIN Data for control of event counter window 0 Event count enabled 1 Event count disabled Timer X count stop bit L Noise filter sampling clock selection bit 0 f XiN 2 1 f XiN 4 External trigger delay time selection bits b2b1 0 0 Not delayed 0 1 4 f XIN us 1 0 8 f XIN us 1 1 16 f XIN us Timer X output control bit 1 P66 or P71 0 Not used interrupt signal 1 INT1 interrupt signal used Timer X output control bit 2 P64 0 Not used INT2 interrupt signal 1 INT2 interrupt signal used Timer X output 1 active edge switch bit 0
184. interrupt generated by the BRK instruction Interrupts are disabled when the I flag is 1 Bit 3 Decimal mode flag D The D flag determines whether additions and subtractions are executed in binary or decimal Binary arithmetic is executed when this flag is 0 decimal arithmetic is executed when it is 1 Decimal correction is automatic in decimal mode Only the ADC and SBC instructions can be used for decimal arithmetic Bit 4 Break flag B The B flag is used to indicate that the current interrupt was generated by the BRK instruction When the BRK instruction is generated the B flag is set to 1 automatically When the other interrupts are generated the B flag is set to 0 and the processor status register is pushed onto the stack Bit 5 Index X mode flag T When the T flag is 0 arithmetic operations are performed between accumulator and memory When the T flag is 1 direct arithmetic operations and direct data transfers are enabled between memory locations Bit 6 Overflow flag V The V flag is used during the addition or subtraction of one byte of signed data It is set if the result exceeds 127 to 128 When the BIT instruction is executed bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag Bit 7 Negative flag N The flag is set to 1 if the result of an arithmetic operation or data transfer is negative When the BIT instruc
185. is document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology described herein you should follow the applicable export control laws and regulations and procedures required by such laws and regulations All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com Renesas has used reasonable care in
186. is inverted each time the timer underflows are output from the pin Except for that this mode operates just as in the timer mode When using this mode set the port sharing the TXOUT pin to output mode 3 IGBT Output Mode After dummy output from the TXOUT pin count starts with the INTO pin input as a trigger In the case that the timer X output 1 active edge switch bit is 0 when the trigger is detected or the timer X underflows H is output from the TXOUTI pin And then when the count value corresponds with the compare register 1 value the TXOUT1 output becomes L After noise is cleared by noise filters judging continuous 4 time same levels with sampling clocks to be signals the INTO signal can use 4 types of delay time by a delay circuit When using this mode set the port sharing the INTO pin to input mode and set the port sharing the pin used as TXOUTI or TXOUT2 function to output mode When the timer X output control bit 1 or 2 of the timer X control register is set to 1 the timer X count stop bit is fixed to 1 forcibly by the interrupt signal of or INT2 And then the output and TXOUT2 output can be set to L forcibly at the same time that the timer X stops counting Do not write 1 to the timer X register extension when using the IGBT output mode Rev 3 04 REJ03B0158 0304 4 PWM Mode IGBT dummy output an external trigger with the INTo pin and
187. is mounted on board by using a serial programmer which is applicable for this microcomputer Table 15 lists the pin description writing mode and Figure 64 and Figure 65 show the pin connections Refer to Figure 66 to Figure 69 for examples of a connection with a serial programmer Contact the manufacturer of your serial programmer for serial programmer Refer to the user s manual of your serial programmer for details on how to use it Table 15 Pin description QZROM writing mode Pin Name Function Vcc Vss Power source Input Apply 2 7 to 5 5 V to Vcc and 0 V to Vss RESET Reset input Input Reset input pin for active L Reset occurs when RESET is held at an L level for 16 cycles or more of XIN XIN Clock input Input XOUT Clock output Output Set the same termination as the single chip mode VREF Analog reference voltage Input Input the reference voltage of A D converter to VREF AVss Analog power source Input Connect AVss to Vss 00 07 10 17 20 27 P33 P37 P40 P44 P47 5 57 P60 P67 P72 P74 port Input L level signal leave the pin open P70 P71 Input port Input or L level signal or leave the pin open OSCSEL input QzROM programmable power source pin P41 ESDA input output Serial data I O pin
188. istor is built in between pin and Xour pin VL2 LCD power source Input 0 lt x 2 lt voltage Input 0 Vi3 voltage to LCD COMo Common output LCD common output pins and are not used at 1 2 duty ratio COMs is not used at 1 3 duty ratio 4 5 5 COM7 SEG32 Common output Segment output LCD common segment output pins POo SEGsa 07 5 15 port PO 8 bit I O port CMOS compatible input level CMOS 3 state output structure e direction register allows each pin to be individually programmed as either input or output Pull up control is enabled in a bit unit 10 5 16 P17 SEG23 port P1 8 bit I O port CMOS compatible input level CMOS 3 state output structure O direction register allows each pin to be programmed as either input or output Pull up control is enabled in 4 bit unit P20 SEGo KWa4 P23 SEG3 KW7 P24 SEG4 P27 SEG7 port P2 8 bit port CMOS compatible input level CMOS 3 state output structure I O direction register allows each to be individually programmed as either input or output Pull up control is enabled in a bit unit P3o SEG24 P37 SEGs1 port 8 bit port CMOS compatible input level CMOS 3 state output structure I O direction register allows eac
189. it Each timer has the 8 bit timer latch All timers are down counters When the timer reaches 0016 the contents of the timer latch is reloaded into the timer with the next count pulse In this mode the interrupt request bit corresponding to that timer is set to 1 The count can be stopped by setting the stop bit of each timer to gt 1 Frequency division selection bits 4 2 bits for each Timer Timer 1 count source selection 00 bits Timer 1 latch 8 Timer 1 8 Timer 1 count stop bit Timer 2 count source selection bits Timer 2 latch 8 Timer 2 8 o 0 Timer 2 count stop bit 2 oH T2OUT output P72 direction edge switch bit register Timer 2 output selection bit Clock for Timer 3 Timer 3 operating mode selection bit 10 bit Timer 3 count source selection bit PWMO circuit Timer 3 output selection bit pS P73 L v 1 latch 0 T3OUT output edge switch bit P73 PWMo EE T30UT 7 direction register 1 2 Timer 3 output selection bit Clock for Timer 4 Timer 4 operating mode selection bit 10 bit Data bus Timer 1 interrupt request Timer 2 write control bit Timer 2 interrupt request Timer 3 write control bit Timer interrupt request Timer 4 latch 8 Timer 4 count source selection bits Timer 4 8
190. lear the status register Try performing the Sequence error operation one more time after confirming that the command is entered correctly Block erase error Should an erase error occur the block in error cannot be used Program error Should a program error occur the block in error cannot be used End block erase program Note When one of 585 and SR4 is set to 1 none of the read array program and block erase commands is accepted Execute the clear status register command 5016 before executing these commands Fig 77 Full status check flowchart and remedial procedure for errors Rev 3 04 20 2008 82 01134 RENESAS REJ03B0158 0304 3805 Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily this MCU incorporates a ROM code protect function for use in parallel I O mode and an ID code check function for use in standard serial I O mode ROM Code Protect Function The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control address address FFDB16 in parallel I O mode Figure 78 shows the ROM code protect control address address FFDB16 This address exists in the User ROM area If one or both of the pair of ROM code protect bits is set to 0 the ROM code protect is turned on so t
191. lection bits 51 Fig 45 1 3 duty revised 52 ROM CORRECTION FUNCTION Description added Fig 47 FFD016 FFDBte 53 Fig 49 Note added and revised 54 Fig 40 LM2 bits 1 to 7 revised Fig 51 CKOUT bits 2 to 7 revised 59 Fig 59 Note 3 added and circuit expression is revised 61 Table 12 ESDA input ESDA input output 64 to 66 Fig 63 to Fig 66 Revised 71 Precautions Regarding Overvoltage Description revised and Fig 73 added 72 Table 13 e Vcc Oscillation start voltage When start oscillating Vi OSCSEL added Vo Conditions added Table 14 OSCSEL added Note 3 revised Table 16 Note 4 revised Table 20 TCONV Limits Note Notes 1 2 Note 2 revised Note set lt 500 kHz 2 500 kHz Table 22 tsu RXD ScLk2 SIN2 SCLK2 3 7 REVISION HISTORY 38D5 Group Data Sheet Description Summary th SCLK2 RxD th SCLK2 SIN2 Table 23 Limits of twH SCLK2 twL SCLK2 te SCLK1 2 30 te ScLK2 2 30 38D5 Group Flash Memory Version For Development Datasheet No REJ03B0197 is merged Flash memory version contents added DESCRIPTION Description added Memory size QZROM version 640 bytes 1536 bytes Power dissipation Flash memory version revised Fig 1 Flash memory version M38D59FFFP added Notes added Fig 2 Flash memory version M38D59FFHP added Notes added Table 1 Flash memory version contents a
192. ltiplier and connect to Vss through a resistor P72 Tzout CKOUT port When selecting T2our function or CKOUT function perform termination of output port P73 PWMo TsouT When selecting PWM or P74 PWM1 T40uT function perform termination of output port Set the VL3 connect bit to 1 and Set the Vi3 connect bit to 0 and leave the apply a Vcc level voltage to VL3 pin Via pin open VL2 VL3 gt VL2 gt VL1 Connect to Vss COM4 SEG35 Open COM7 SEG32 VREF Connect to Vcc XIN When only on chip oscillator is used connect to Vcc through a resistor XOUT When external clock is input or when only on chip oscillator is used open Rev 3 04 20 2008 Page 27 0 134 RENESAS REJ03B0158 0304 3805 INTERRUPTS The 38D5 Group interrupts are vector interrupts with a fixed priority scheme and generated by 16 sources among 17 sources 6 external 10 internal and 1 software The interrupt sources vector addresses and interrupt priority are shown in Table 11 Each interrupt except the BRK instruction interrupt has the An interrupt requests is accepted when all of the following conditions are satisfied Interrupt disable flag 0 Interrupt request i Cd Interrupt enable bit sess TA Though
193. me 350 ns tv ScLk2 Sout2 Serial 1 02 output valid time 30 ns 3805 QzROM VERSION twH CNTR tWL CNTR CNTRo 1 0 2Vcc INToo INTO1 INT10 INT11 INT2 tW RESET tWH XIN tWL XIN tc ScLK2 tt twL SCLK1 twL SCLk2 d 0 2Vcc tsu RXD SCLK1 tsu SIN2 SCLK2 SRI OVE LXKKKKKKKKK KK 0 2VEC td SCLK1 TxD ta SCLK2 SOUT2 tr twH SCLK1 tWH SCLK2 0 8 th SCLK1 RxD th SCLK2 SIN2 55555550505505050505050505 tv SCLK1 TXxD tv SCLK2 SOUT2 Fig 96 Timing diagram Rev 3 04 REJ03B0158 0304 20 2008 Page 108 of 134 pRENESAS 3805 FLASH MEMORY VERSION FLASH MEMORY VERSION ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Table 34 Absolute maximum ratings Parameter Conditions Ratings Power source voltage 0 3 to 6 5 Input voltage 0 3 to 0 3 P0o PO7 10 17 27 P30 P37 40 4 5 5 P6o P67 70 74 All voltages are based on Vss Input voltage 0 3 to VL2 P 9 When an input voltage is Input voltage 2 measured output Input voltage transistors are cut off 2 to 6 5 Input voltage C1 C2 0 3 to 6 5 Input voltage RESET CNVss 0 3 to Vcc 0 3 Output voltage C2 0 3 to 6 5 Output voltage At output port 0 3 to Vcc 0 3 P00 P07 10 17 20 27
194. mer X register extension is written note that the value is retained in the reload latch 2 Write to the timer X register by the 16 bit unit Do not read the timer X register while write operation is performed If the write operation is not completed normal operation will not be performed 3 When IGBT output mode or PWM mode is set do not write 1 to the timer X register extension If 1 has been already written to the timer X register be sure to write 0 to the register before use Write to the following registers in the order below The compare registers 1 2 3 high and low order The timer X register extension The timer X register low order The timer X register high order The compare registers high and low order can be written in either order However be sure to write both the compare registers 1 2 3 and the timer X register at the same time 9 Read Order to Timer X 1 In all modes read the following registers in the order below The timer X register extension The timer X register high order The timer X register low order When reading the timer X register extension is not required read the timer X register high order first and the timer X register low order next The read order to the compare registers 1 2 3 is not specified 2 Read the timer X register in 16 bit units Do not write to it during read operation If read operation is terminated in progress normal operatio
195. n bit and serial 1 02 port selection bit 2 SOURCE indicates the followings XIN input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode Fig 39 Block diagram of serial 1 2 Rev 3 04 20 2008 48 01134 stENESAS REJ03B0158 0304 3805 Serial 1 02 Operation Writing to the serial I O2 register initializes the serial I O2 counter to 7 After writing the SOUT2 pin outputs data each time the synchronous clock changes from to L The SIN2 pin captures data each time the synchronous clock changes from L to and the serial I O2 register shifts 1 bit simultaneously When the external clock is selected as the synchronous clock counting the synchronous clock eight times results the following Serial I O2 counter 0 Synchronous clock is stopped at Serial I O2 interrupt request bit 1 After transfer is completed the SOUT2 pin is placed in the high impedance state 1 Transfer clock When the external clock is selected as the synchronous clock counting the synchronous clock eight times sets the serial I O2 bit to 1 and the 50072 pin retains the D7 output level However if the synchronous clock is continuously input the serial I O2 register continues shifting and the SOUT2 pin keeps outputting transmit data
196. n divided by 8 starts oscillation The on chip oscillator through a resistor and leave XOUT open stops oscillating and the XCIN and XCOUT pins function as I O ports The operating mode is frequency 8 mode CPU Mode Register 2 CPUM2 001116 The CPU mode register 2 contains the control bits for the on chip oscillator The CPU mode register 2 is allocated at address 001116 CPU mode register 2 50 CPUM2 address 001116 QzROM version OSCSEL L initial value 0016 QzROM version OSCSEL H initial value 0116 Flash memory version initial value 0016 On chip oscillator stop bit 0 Oscillating 1 Stopped Not used do not write 1 Not used returns 0 when read Not used do not write 1 CPU mode register b7 50 CPUM CM7 ome cvs 4 address 003B16 QZROM version OSCSEL L initial value E016 QzROM version OSCSEL H initial value 4016 Flash memory version initial value E016 Processor mode bits b1 bO 0 0 Single chip mode 01 1 0 Not available 11 Stack page selection bit 0 0 page 1 1 page Internal system clock selection bit 0 Main clock selected includes OCO XIN 1 XCIN XCOUT selected Port Xc switch bit 2 0 I O port function Oscillation stop 1 XCIN XCOUT oscillating function XIN XOUT oscillation stop bit 3 0 Oscillating 1 Stopped Main clock division ratio selection bit Valid only when CM3 0 4 b7 6
197. n for hardware and software including but not limited to redundancy fire control an malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachment This document may not be eproduced or duplicated in any form in whole or in part without prior written approval from Renesas Please contact a Renesas sa office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries RENESAS SALES OFFICES 44 NE SAS http www renesas com Refer to http www renesas com en network for the latest and detailed information Renesas Technology America Inc 450 Holger Way San Jose CA 95134 1368 U S A Tel 1 408 382 7500 Fax 1 408 382 7501 Renesas Technology Europe Limited Du Tel kes Meadow Millboard Road Bourne En
198. n will not be performed 20 2008 126 of 134 RENESAS 3805 10 Write to Timer X 1 Timer X can select either writing data to both the latch and the timer at the same time or writing data only by the timer X write control bit b3 in the timer X mode register address 002D16 When writing to the latch only if a value is written to the timer X address the value is set into the reload latch and the timer is updated at the next underflow After a reset release if a value is written to the timer X address the value is set into the timer and the timer latch at the same time because they are written simultaneously When writing to the latch only if the write timing to the high order reload latch and the underflow timing are almost the same the value is set into the timer and the timer latch at the same time At this time count is stopped during write operation to the high order reload latch 2 Switch the frequency division or count source while the timer count is stopped This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes on chip oscillator mode XIN mode or low speed mode Be careful when changing settings in the CPU mode register 11 Setting Timer X Mode Register When PWM mode or IGBT output mode is set be sure to set the write control bit in the timer X mode re
199. ncy 4 mode and frequency 8 mode collectively referred as XIN mode Frequency 8 Mode The system clock is the frequency of XIN divided by 8 Frequency 4 Mode The system clock is the frequency of XIN divided by 4 Frequency 2 Mode The system clock is half the frequency of XIN 3 Low speed Mode The system clock is half the frequency of sub clock After reset and when system returns from the stop mode the operation mode depends on the OSCSEL pin state in the QzROM version and the flash memory version operation mode is the on chip oscillator mode When the RESET pin changes from L to H and when the STP instruction is executed determine the input level applied to the OSCSEL pin Refer to the clock state transition diagram for the setting of transition to each mode The XIN OUT oscillation is controlled by the bit 5 of CPUM and the sub clock oscillation is controlled by the bit 4 of CPUM and the on chip oscillator oscillation is controlled by the bit 0 of CPUM2 In the on chip oscillator mode the oscillation by the oscillator can be stopped In the low speed mode the power consumption can be reduced by stopping the XIN XOUT oscillation In low speed mode the on chip oscillator stops in the version regardless of the on chip oscillator stop bit value The on chip oscillator does not stop in the flash memory version so set the on chip oscillator stop bit to 1 to stop the oscillation Set
200. ng interrupt request bit is set to 1 but the interrupt request is not accepted When an interrupt enable bit is set to 1 acceptance of the corresponding interrupt request is enabled Each interrupt enable bit can be set to 0 or 1 by software The interrupt enable bit for an unused interrupt should be set to 0 Rev 3 04 REJ03B0158 0304 Interrupt Reset acceptance Interrupt Source Selection Any of the following combinations can be selected by the interrupt edge selection register 003A 16 Timer or CNTR1 External Interrupt Pin Selection For external interrupts INTo and INT1 the INTo input port switch bit in the interrupt edge selection register bits 4 and 5 of address 003A 16 can be used to select INToo INTo1 pin input or INT10 and INT11 pin input 20 2008 Page 290f 134 RENESAS 3805 67 Interrupt edge selection register INTEDGE address 003A16 m INTo interrupt edge selection bit INT interrupt edge selection bit INT2 interrupt edge selection bit Timer Y CNTR interrupt switch bit 0 Timer Y interrupt 1 CNTR1 interrupt INTo input port switch bit 0 input from Port P62 INToo 1 input from Port P70 1 input port switch bit 0 input from Port 66 INT10 1 input from Port P71 INT11 Not used do not write to 1 Not used return 0 when read 0 Falling edge ac
201. ng on factors such as the oscillator circuit constants and operating temperature range Note that oscillation start may be particularly difficult at low voltage when using a high frequency oscillator f Oscillation frequency 1 MHz x f XiN lt 8 MHz of oscillator When the 8 MHz oscillation is used assign 8 to f Rev 3 04 20 2008 Page990f134 RENESAS REJ03B0158 0304 3805 QzROM VERSION Table 24 Recommended operating conditions 2 Vcc 1 8 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limit Symbol Parameter S Unit Min Typ Max XioH pea total peak output current 1 40 mA P0o PO7 P1o P17 20 27 P3o P37 P72 P74 total peak output current 1 40 mA 4 4 P5o P57 P6o P67 41 total peak output current 1 40 mA POo P07 P1o P17 20 27 P3o P37 P72 P74 total peak output current 1 40 mA P4o P47 P5o P57 P6o P6 41 total peak output current 1 110 mA P62 P67 total average output current 1 20 mA P0o PO7 P1o P17 20 27 7 P72 P74 total average output current 1 20 mA P4o P47 P5o P57 P6o P67 L total average output current 1 20 mA POo P07 P1o P17 20 27 P
202. nterval is obtained by n x ts However in the long interval width of output pulse is extended for ts which is set by the PWMOI register address 002416 Notes on Timer 1 to Timer 4 gt 1 Timer 3 PWMo Mode Timer 4 PWM1 Mode When PWM output is suspended after starting PWM output depending on the level of the output pulse at that time to resume an output the delay of the one section of the short interval may be needed Stop at No output delay Stop at L Output is delayed time of 256 x ts n the PWM mode the follows are performed every cycle of the long interval 4 x 256 x ts Generation of timer 3 timer 4 interrupt requests Update of timer 3 timer 4 2 Write to Timer 2 Timer 3 Timer 4 When writing to the latch only if the write timing to the reload latch and the underflow timing are almost the same the value is set into the timer and the timer latch at the same time In this time counting is stopped during writing to the reload latch Output waveform of Timer PWMO or Timer 4 PWM1 Long interval 4 x 256 x ts 1 Short interval 1 Short interval Short interval 256 x ts Short interval 256 15 1 n 1 x ts PWMO01 register 012 PWMO 1 register 102 1 1 1 Interrupt request n Setting value of Timer 3 or Timer 4 256 x ts gt lt Ne 256 x ts PWMO1 register
203. ntrol register 0 FMCRO address OFE0ie initial value 0116 RY BY status flag 0 Busy being written or erased 1 Ready CPU rewrite mode select bit 0 CPU rewrite mode invalid 1 CPU rewrite mode valid User block 1 enable bit 2 0 disabled 1800 6 7FFF16 1 enabled 180016 7FFF16 Flash memory reset bit 0 Normal operation 1 reset Not used do not write 1 to this bit User ROM area select bit 0 Boot ROM area is accessed 1 User ROM area is accessed Program status flag 0 Pass 1 Error Erase status flag 0 Pass 1 Error Notes 1 For this bit to be set to 1 the user needs to write 0 and then a E W enable bit By setting combination of bit 4 user block 0 4 to it in succession For this bit to be set to 0 write 0 only to i i this bit E W enable bit of the flash control d tee 2 address 2 This bit can be written only when CPU rewrite mode select bit is 1 OFE216 and this bit as shown in Table 17 E W is disabled to 3 Effective only when the CPU rewrite mode select bit 1 Fix this user block in the CPU rewriting mode bit to 0 when the CPU rewrite mode select bit is 0 Bit 3 of the flash trol ister 0 is the flash 4 When setting this bit to 1 when the control circuit of flash memory 9 CONTO Iegis 44 is reset the flash memory cannot be accessed for 10 ms reset bit used to reset th
204. ock diagram of Timer Y e Timer Y Timer Y is a 16 bit timer The timer Y count source can be 3 Event Counter Mode The timer counts signals input through the CNTR1 pin selected by setting the timer Y mode register XCIN can be selected as the count source When XCIN is selected as the count source counting can be performed regardless of XIN oscillation or on chip oscillator oscillation Four operating modes can be selected for timer Y by the timer Y mode register Also the real time port can be controlled 1 Timer Mode The timer Y count source can be selected by setting the timer Y mode register 2 Period Measurement Mode The interrupt request is generated at rising or falling edge of CNTR pin input signal Simultaneously the value in timer Y latch is reloaded in timer Y and timer Y continues counting Except for that this mode operates just as in the timer mode The timer value just before the reloading at rising or falling of pin input is retained until the timer Y is read once after the reload The rising or falling timing of CNTR pin input is found by CNTR1 interrupt When using this mode set the port sharing the CNTR pin to input mode Rev 3 04 REJ03B0158 0304 Except for that this mode operates just as in the timer mode When using this mode set the port sharing the CNTR pin to input mode 4 Pulse Width HL Continuously Measurement Mode The interrupt request is generated at both rising and
205. og input pin corresponding to ADKEY before performing A D conversion 5 Input Voltage Applied to ADKEY Pin Set the input to the ADKEY pin into a steep falling waveform and stabilize the input voltage within eight cycles 1 us when 8 MHz from the moment the input voltage reaches VIL or lower The actual threshold voltage for the ADKEY pin is between VIH and VIL To prevent unnecessary ADKEY operation due to noise or other factors set the ADKEY pin voltage to VIH 0 9 or more while the input is waited Rev 3 04 REJ03B0158 0304 6 Register Operation during A D Conversion The A D conversion operation is not guaranteed if the following are preformed The CPU mode register is operated during A D conversion operation The AD control register is operated during A D conversion operation STP or WIT instruction is executed during A D conversion operation 7 A D Converter Power Source Pin Connect to the A D converter power source pin to 55 or whether the A D conversion function is used or not Reason If the AVSs pin is left open the MCU may operate incorrectly because the pin will be affected by noise or other factors 20 2008 129 of 134 4 N S AS 3805 Notes LCD Drive Control Circuit 1 Multiplier Circuit When the multiplier circuit is used set the multiplier circuit control bit to 1 multiplier circuit enabled after applying a
206. ol 71 Voltage multiplier Cic control bit recti 1 02 Direction register T YH Y Data bus f o v Data 3 latch INTo interrupt INT1 interrupt 9 INTO input port switch bit 4 INT1 input port switch bit CNTRo norimu a interrupt input input port switch bit 21 Ports P72 P73 P74 22 COMo to l up contro Direction The gate input signal of each register transistor is controlled by the LCD duty ratio and the bias value Data bus pl Port latch J Port Timer output selected 1 Timer output PWM output Timer output system clock output XCIN output 23 COM4 SEGs35 to COM7 SEG32 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value Duty ratio selection bits Segment data 5 gt L Vi1 Vss Fig 17 Port block diagram 4 Rev 3 04 20 2008 25 0 134 RENESAS REJ03B0158 0304 3805 Termination of unused pins Termination of common pins I O ports Output ports Input ports Rev 3 04 Select an input port or an output port and follow each processing method In addition it is re
207. on bit 0 I O port 1 SOUT2 SCLK2 signal pin 1 1 1 1 Serial 1 02 control register SIO2CON P45 SOUT2 P channel output disable bit The serial I O2 control register contains 8bits which control 0 CMOS output at output mode various serial I O functions 1 N channel open drain output at output mode Transfer direction selection bit 0 LSB first 1 MSB first Serial 1 02 synchronous clock selection bit 0 External clock 1 Internal clock SRDY2 output selection bit 0 I O port P47 1 SRDY2 signal output Note1 jSOURCE indicates the followings input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode Fig 38 Structure of serial 1 02 control registers Internal synchronous clock selection bits 1 8 Data bus Frequency divider P47 latch Serial l O2 synchronous 1 clock selection bit 1 P47 SRDY2 Synchronous circuit 9 P46 latch 0 P46 ScLk2 2 Externa Serial 1 02 interrupt request D P45 latch 0 0 49 Y Serial 1 02 counter 3 P45 SouT2 20 Serial 2 port selection bit i P44 SIN2 gt Serial 2 register 8 001 16 Notes 1 It is selected by the serial 1 02 synchronous clock selection bit SRDY2 output selectio
208. on start time differ depending on factors such as the oscillator circuit constants and operating temperature range Note that oscillation start may be particularly difficult at low voltage when using a high frequency oscillator 5 When using the microcomputer in low speed mode set the clock input oscillation frequency on condition that f XCIN lt 3 System clock frequency System clock frequency Rev 3 04 4 0 4 5 Power source voltage 1 8 2 0 Main clock XIN frequency MHz 164 8 07 Main clock XIN frequency 4 07 0 20 2008 Page 101 01134 pLRENESAS REJ03B0158 0304 1 8 2 0 45 Power source voltage 5 5 3805 Electrical Characteristics Table 26 Electrical characteristics 1 Vcc 1 8 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter Test conditions QzROM VERSION output voltage P0o PO7 P10 P17 P20 P27 P30 P37 2 5 0 Voc 2 5V output voltage 40 47 50 57 P60 P67 72 74 1 loH 5mA 1 25 loH2 1 25 Voc 2 5V output voltage POo P07 P10 P17 P20 P27 P30 P37 loL 5mA loL21 25mA loL21 25mA 2 5 output voltage 40 47 50 57 P60 P61 72 74 1 loL 10mA loL 2 5mA loL 2 5mA Vcc 2 5V output voltage P62 P67 loL
209. ou should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applications You should use the products described herein within the range specified by Renesas especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety desig
210. ows the push and pop instructions of accumulator or processor status register Store registers other than those described in Figure 7 with program when the user needs them during interrupts or subroutine calls Program Counter PC The program counter is a 16 bit counter consisting of two 8 bit registers PCH and PCL It is used to indicate the address of the next instruction to be executed Accumulator Index register X Index register Y Stack pointer Program counter Processor status register PS Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag 20 2008 Page 12 01134 sENESAS 3805 On going Routine Interrupt request 1 gt M S lt PCH Push return address on stack T Execute JSR Push return address on stack G ra 2 T D T 1 1 d Push contents of processor status register on stack n n Interrupt Service Routine Flag is set from 0 to 1 Fetch the jump vector Subroutine Execute RTI Execute RTS 5 5 1 POP contents of processor status POP return address register from stack from stack n T ER PS M 7 7 T POP return address 1 from stack T 9 PCH
211. ports to input mode and connect each pin to Vcc or Vss through a resistor of 1 k to 10 An internal pull up resistor can also be used for the port where the internal pull up resister is selectable To set the ports to output mode leave open at or output When setting the ports to output mode and leave open input mode in the initial state remains until the mode of the ports are switched to output mode by a program after a reset This may cause the voltage level of the pins to be undefined and the power source current to increase while the ports remains in input mode For any effects on the system careful system evaluations should be implemented on the user side The direction registers may be changed due to a program runaway or noise so reset the registers periodically by a program to increase the program reliability 2 Termination Concerns 1 When setting I O ports to input mode 1 Do not leave open Reason The power source current may increase depending on the first stage circuit The ports are more likely affected by noise when compared with the termination shown on the above 1 1 I O ports 2 Do not connect to VCC or Vss directly Reason If the direction registers are changed to output mode due to a program runaway or noise a short circuit may occur 3 Do not connect multiple ports in a lump to VCC or Vss through a resistor Reason If the direction registers are chang
212. put edge itch bit Timer 2 latch 8 T dn P72 T20UT CKOUT Timer 2 8 P72 latch P72 direction register System clock Timer 2 output selection bit bO Timer 12 mode register address 002516 10 T12M P72 clock output Timer 2 output selection bit control bits 0 port 1 Timer 2 output Fig 55 Block diagram of Clock output function Other function registers RRF register RRFR RRF register The RRF register address 001216 is the 8 bit register and does RRFR address 001216 not have the control function As for the value written in this register high order 4 bits and DBa data storage low order 4 bits interchange DBs data storage It is initialized after reset DBe data storage DB7 data storage DBo data storage DBt data storage DBe data storage DB3 data storage Fig 56 Structure of RRF register Rev 3 04 20 2008 Page600f134 RENESAS REJ03B0158 0304 3805 RESET CIRCUIT To reset the microcomputer RESET pin should be held at an L level for 2 us or more Then the RESET pin is returned to an level the power source voltage should be between Vcc min and 5 5 V reset is released After the reset is completed the program starts from the address contained in address FFFD16 high order byte and address FFFC16 low order byte Make sure that the reset input voltage meets VIL spec When power source voltage passes VCC min 0
213. r is stopped Bits 7 to 5 can be rewritten only once after reset After rewriting it is disable to write any data to this bit 20 2008 Page 59 01134 sRENESAS 3805 CLOCK OUTPUT FUNCTION A system clock can be output from I O port P72 The triple 60 function of I O port timer 2 output function and system clock Clock output control register output function are controlled by the clock output control register CKOUT address OFF31s address OFF316 and the timer 2 output selection bit of the timer 12 mode register address 002516 P72 clock output control bits In order to output a system clock from I O port P72 set the 6160 timer 2 output selection bit to 1 and P72 clock output control 0 0 Timer 2 output bits of the clock output control register to 01 In order to output 0 1 frequency signal output the same signal as oscillation frequency of sub clock XCIN set 1 0 XCIN frequency signal output the P72 clock output control bits to 10 When the clock output 1 1 Not available function is selected a clock is output while the direction register Not used returns 0 when read of port P72 is set to the output mode P72 is switched to the port output or the output timer 2 output or Fig 54 Structure of clock output control register the clock output except port at the cycle after the timer 2 output selection bit is switched Timer 2 output selection bit T20OUT out
214. rcuit control bit 0 Voltage multiplier circuit disabled Input ports P7o INTot P71 INT11 1 Voltage multiplier circuit enabled C2 pins connection bit 0 Connect LCD internal Vis to 1 Connect LCD internal Vis to Vis Not used returns 0 when read LCD circuit divider division ratio selection bits Segment output disable register 1 SEG1 address OFF516 9 Segment output disable bit 8 0 Segment output SEGo Output port P20 Segment output disable bit 9 0 Segment output SEG Output port P21 Segment output disable bit 0 Segment output SEG2 Output port P22 Segment output disable bit 0 Segment output SEG3 Output port P23 Segment output disable bit 0 Segment output SEG4 Output port P24 Segment output disable bit 0 Segment output SEGs Output port P25 Segment output disable bit 0 Segment output SEGe Output port P26 Segment output disable bit 0 Segment output SEG7 Output port P27 When 1 is selected as duty ratio by the duty ratio selection bits set 1 to the bias control bit LCDCK is a clock for the LCD timing controller SOURCE indicates the followings input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode Only pins set to output ports by the direction
215. register 1 address 002E16 e CNTR active edge switch bit bits 6 of timer Y mode register address 003816 When switching the interrupt source of the interrupt vector address where two or more interrupt sources are allocated Timer Y CNTR1 interrupt switch bit bit 3 of interrupt edge selection register When switching the INT pin INTO input port switch bit bit 4 of interrupt edge selection register INT input port switch bit bit 5 of interrupt edge select register Rev 3 04 REJ03B0158 0304 2 Checking Interrupt Request Bit To check the interrupt request bit with the BBC or BBS instruction immediately after this bit is set to 0 take the following sequence lt Reason gt If the BBC or BBS instruction is executed immediately after the interrupt request bit is set to 0 the bit value before being set to 0 is read Set the interrupt request bit to 0 no interrupt NOP one or more instructions Execute the BBC or BBS instruction Fig 103 Sequence for setting interrupt request bit 3 Setting Unused Interrupts Set the interrupt enable bit of the unused interrupt to 0 disabled 20 2008 Page 125 of 134 pRENESAS 3805 Notes Timers 1 Frequency Divider All timers shares one circuit for the frequency divider to generate the count source Thus the frequency divider is not initialized when each individual timer is
216. register can be controlled to switch to output ports or segment outputs by the segment output disable register When disabling the voltage multiplier circuit the Ct and C2 pins function as input ports P7o INTo P71 INT11 ESAS 3805 2680156 035 OAS 9035 WOO O 0 ENOO WOO WOO O T uoWWOD I uowwog 1 1 T 1 JOAUP JOAUP 2 I luowwooluowwogluowwog 1 1 uonoeuuoo 70 O SSA OOOOOO wys unus 19087 1 uus e 91 1 uus uius 9497 1 1 abn 26 8 30unose o 5 JOPIAIp 0 eo1nos 42021 z uoioejes 1 007 uonoejes oes Ang ejgeue 057 1 seig 4q seig feidsip 001 LLLNI HZd HOLNI OZd 5109 se uorounj pue 9 eui z 19151691 09110 0 pesn jou 1 eBeyoA eui ueuM z peeds o y YOO O qns 101811060
217. rite to Timer 2 3 and 4 When writing to the latch only if the write timing to the reload latch and the underflow timing are almost the same the value is set into the timer and the timer latch at the same time At this time count is stopped during write operation to the reload latch 7 Timer 3 PWMo Mode Timer 4 PWM1 Mode 1 When PWM output is suspended once it starts the time to resume outputting may be delayed one section 256 x ts of the short interval depending on the level of the output pulse at that time Stop at No output delay Stop at L Output is delayed time of 256 x ts 2 When PWM mode is used the interrupt requests and values of timer 3 and timer 4 are updated every cycle of the long interval 4 x 256 x ts Rev 3 04 REJ03B0158 0304 8 Write Order to Timer X 1 When timer mode pulse output mode event counter mode or pulse width measurement mode is set write to the following registers in the order below The timer X register extension The timer X register low order The timer X register high order Writing to only one of these registers cannot be performed When either of the above modes is set and timer X operates as a 16 bit counter if the timer X register extension is never set after a reset release setting the timer X register extension is not required In that case write the timer X register low order first and the timer X register high order next However once the ti
218. rity checking enabled selection bit PARS 0 Even parity 1 Odd parity Stop bit length selection bit STPS 0 1 stop bit 1 2 stop bits 0 CMOS output in output mode Not used return 1 when read Fig 37 Structure of serial l O1 related registers Serial 1 01 control register SIO1CON address 001 16 P41 TXD P channel output disable bit POFF BRG count source selection bit CSS 0 9SOURCE 1 SOURCE 4 Serial 1 01 synchronous clock selection bit SCS 0 BRG output divided by 4 when clock synchronous serial I O is selected BRG output divided by 16 when UART is selected 1 External clock input when clock synchronous serial is selected External clock input divided by 16 when UART is selected SRDY1 output enable bit SRDY 0 P43 pin operates as ordinary pin 1 P43 pin operates as 1 output pin Transmit interrupt source selection bit TIC 0 Interrupt when transmit buffer has emptied 1 Interrupt when transmit shift operation is completed Transmit enable bit TE 0 Transmit disabled 1 Transmit enabled Receive enable bit RE 0 Receive disabled 1 Receive enabled l O1 mode selection bit SIOM 0 Clock asynchronous UART serial I O 1 Clock synchronous serial I O Serial I O1 enable bit SIOE 0 Serial 1 01
219. rol and Applied Voltage to LCD Power Input Pins evised Fig 45 revised title is revised Notes added Fig 50 revised e Initial Value of Watchdog Timer revised lt Notes gt revised Fig 52 Watchdog timer selection bit 2 Watchdog timer count source selection bit 2 Fig 53 revised 59 Title RRF register RRFR added 60 RESET CIRCUIT description added Fig 57 Fig 58 revised 61 Fig 59 18 RRF register RRFR 18 RRF register Notes revised 62 CLOCK GENERATING CIRCUIT and Frequency Control Description added 64 e Oscillation Control Description added 65 Fig 63 revised 66 Table 15 Function of Vcc Vss pins 1 8 to 5 5 2 7 to 5 5 69 70 Fig 66 and 67 revised 731091 FLASH MEMORY MODE added 92 NOTES ON PROGRAMMINGi is merged to NOTES ON USE 93 NOTES ON QzROM VERSION is separated 94 NOTES ON FLASH MEMORY VERSION and NOTES ON DEFFAERENCES BETWEEN QzROM VERSION AND FLASH MEMORY VERSION are added 5 7 REVISION HISTORY 38D5 Group Data Sheet Date Description Summary 3 01 Aug 08 2007 97 108 Table 22 and 35 Vi of OCESEL are added of are added Vo of ports and SEG32 SEG35 are revised Table 23 to 34 55 is added to test conditions Table 24 of RESET is revised Table 27 Vcc test conditions are revised Table 30 At 10bitAD 2 2V lt Vcc lt 4 0V gt 2 2V lt Vcc lt 4 0V 1 8V lt Vcc lt 5 5V gt 2 0V lt Vcc lt 5 5V At 8bitAD 2 0V lt Vcc lt 2 2
220. rolled by each timer division ratio selection bit The division ratio can be selected from as follows 1 1 1 2 1 16 1 256 of f XcIN or 4 Switch the frequency division or count source while the timer count is stopped This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes on chip oscillator mode XIN mode or low speed mode Be careful when changing settings in the CPU mode register e Timer X The count source for timer X can be set using the timer X mode register XCIN may be selected as the count source If XCIN is selected count operation is possible regardless of whether or not the XIN input oscillator or the on chip oscillator is operating The timer X operates as down count When the timer contents reach 000016 an underflow occurs at the next count pulse and the timer latch contents are reloaded After that the timer continues countdown When the timer underflows the interrupt request bit corresponding to the timer X is set to 1 Six operating modes can be selected for timer X by the timer X mode register and timer X control register 1 Timer Mode The count source can be selected by setting the timer X mode register In this mode timer X operates as the 18 bit counter by setting the timer X register extension 2 Pulse Output Mode Pulses of which polarity
221. ronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 2 NEC S AS 38D5 Group REJ03B0158 0304 SINGLE CHIP 8 BIT CMOS MICROCOMPUTER Rev 3 04 May 20 2008 DESCRIPTION Power source voltage QZROM version In fi 2 mod The 38D5 Group is the 8 bit microcomputer based on the 740 in frequency 2 mode Family core technology 125 MHZ tte 4 5 to 5 5 V The 3805 Group is pin compatible with the 38C5 Group AXN S8 MHZ 4 0 to 5 5 V The 3805 Group has an LCD drive control circuit an A D f XIN S2 MEZ irren ether reet 2 0to 5 5 V converter a serial interface and a ROM correction function as TOXIN S2 1 8 to 5 5 V additional functions In frequency 4 mode The QzROM version and the flash memory version are available f XIN lt 16 MHz 4 5 to 5 5 V The flash memory version does not have a selection function for f XiN lt 8 2 2 0 to 5 5 V the oscillation start mode Only the on chip oscillator starts S 1 8 to 5 5 V In frequency 8 mode The various mi
222. rupt source selection bit P41 TxD O Transmit shift register TN interrupt request TI Transmit buffer register Transmit buffer empty flag TBE Address 001816 Serial 1 01 status register Address 001916 Data bus Note1 6SOURCE indicates the followings XiN input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode Fig 33 Block diagram of clock synchronous serial 1 01 Transfer shift clock 1 2 to 1 2048 of the internal clock or an external clock Serial output TxD Serial input RxD Receive enable signal SRDY Write pulse to receive transmit buffer register 1 1 Overrun error OE detection C aw Notes 1 As the transmit interrupt Tl source which can be selected either when the transmit buffer has emptied TBE 1 or after the transmit shift operation has ended TSC 1 by setting the transmit interrupt source selection bit TIC of the serial 1 control register 2 If data is written to the transmit buffer register when TSC 0 the transmit clock is generated continuously and serial data is output continuously from the TxD pin 3 The receive interrupt RI is set when the receive buffer full flag RBF becomes 1 Fig 34 Operation of clock syn
223. ry rewrite uses the CPU rewrite mode rewrite data input and so forth The standard serial I O mode is started by connecting to the CNVSs pin and H to the P41 BOOTENT pin and releasing the reset operation In the ordinary microcomputer mode set CNVss pin to L level This control program is written in the Boot ROM area when the product is shipped from Renesas Accordingly make note of the fact that the standard serial I O mode cannot be used if the Boot ROM area is rewritten in parallel I O mode The standard serial I mode has standard serial I O mode 1 of the clock synchronous serial and standard serial I O mode 2 of the clock asynchronous serial Tables 20 and 21 show description of pin function standard serial I O mode Figure 80 to 83 show the pin connections for the standard serial I O mode In standard serial I O mode only the User ROM area shown in Figure 70 can be rewritten The Boot ROM area cannot be written In standard serial I O mode a 7 byte ID code is used When there is data in the flash memory this function determines whether the ID code sent from the peripheral unit programmer and those written in the flash memory match The commands sent from the peripheral unit programmer are not accepted unless the ID code matches Rev 3 04 20 2008 86 0 134 stENESAS REJ03B0158 0304 3805 Table 20 Description of pin function Flash Memory Standard Serial I O Mode
224. s b1b0 1 0 0 1 16 x p SOURCE 0 1 1 1 SOURCE 1 0 1 2 SOURCE 1 1 1 256 x SOURCE Timer 2 frequency division selection bits b3b2 0 0 1 16 x 9 SOURCE 0 1 1 1 SOURCE 10 1 2 SOURCE 1 1 1 256 SOURCE Timer 3 frequency division selection bits 6564 0 0 1 16 x SOURCE 0 1 1 1 x 9 SOURCE 1 2 SOURCE 1 1 1 256 x 9 SOURCE Timer 4 frequency division selection bits b7b6 0 0 1 16 x 9 SOURCE 0 1 1 1 x p SOURCE 10 1 2 SOURCE 1 1 1 256 x p SOURCE SOURCE indicates the followings input in the frequency 2 4 or 8 mode On chip oscillator divided by 4 in the on chip oscillator mode Sub clock in the low speed mode Rev 3 04 20 2008 37 0 134 stENESAS 158 0304 3805 16 bit Timer Read and write operation on 16 bit timer must be performed for both high and low order bytes When reading a 16 bit timer read the high order byte first When writing to a 16 bit timer write the low order byte first The 16 bit timer cannot perform the correct operation when reading during the write operation or when writing during the read operation Noise filter sampling clock selection bit 14 Frequency o 04 x2 divider OO Et 12 qe Trigger for IGBT input control bit Data bus 2 6 Timer X frequency division selection bits SOURCE Frequency divider
225. s capacitor a ceramic capacitor of 0 01 uF to 0 1 uF is recommended Also use the shortest possible wiring to connect a bypass capacitor between the power source pin and the GND pin and between the power source pin and the analog power source pin Notes on Memory 1 RAM The RAM content is undefined at a reset Be sure to set the initial value before use 20 2008 Page 132 of 134 4 N S AS 3805 Notes QzROM Version Wiring to OSCSEL pin 1 OSCSEL L Connect the OSCSEL pin the shortest possible to the GND pattern which is supplied to the Vss pin of the microcomputer In addition connecting an approximately 5 kQ resistor in series to the GND could improve noise immunity In this case as well as the above mention connect the pin the shortest possible to the GND pattern which is supplied to the Vss pin of the microcomputer 2 OSCSEL H Connect the OSCSEL pin the shortest possible to the pattern which is supplied to the Vcc pin of the microcomputer In addition connecting an approximately 5 KQ resistor in series to the Vcc could improve noise immunity In this case as well as the above mention connect the pin the shortest possible to the Vcc pattern which is supplied to the pin of the microcomputer lt Reason gt The OSCSEL pin is the power source input pin for the built in QzROM When programming in the QzROM the impedance of the OSCSEL pin is low to allow the electric current
226. scillator clock v Select internal system clock bit 3 of CPUM or bit 7 6 01 QzROM version Wait by operation until establishment Start with an on chip oscillator Initial value of CPUM is E016 C After releasing reset Initial value of CPUM2 is 0016 As for the details of condition for transition among each mode refer to the state transition of system clock Oscillator starts oscillation Do not change bit 3 bit 6 and bit 7 of CPUM until oscillation stabilizes System can operate in on chip oscillator mode until oscillation stabilize Select internal system clock Do not change bit 3 bit 6 and bit 7 of CPUM at the same time Switch the main clock division ratio selection bit bit 7 6 00 or 10 Main routine After releasing reset Low speed Xin mode Y v Start the bits 4 and oscillation 5 of CPUM v Wait by on chip oscillator operation until establishment of oscillator clock Select system clock bit 3 of CPUM or bit 7 6 01 Switch the main clock division ratio selection bit bit 7 6 00 or 10 gt Y Main routine Select main clock division ratio Switch to frequency 2 or frequency 4 mode here if necessary Start with an on chip oscillator Initial value of CPUM is E016
227. se width 950 twL ScLk2 Serial 1 02 clock input L pulse width 950 tsu SIN2 SCLK2 Serial 2 input setup time 400 th SCLK2 SIN2 NOTE Serial 1 02 input hold time 1 When bit 6 of address 001 1 is 1 clock synchronous Divide this value by four when bit 6 of address 001 1 is 0 UART Rev 3 04 20 2008 Page 117 of 134 42 N S AS REJ03B0158 0304 200 3805 Table 45 Switching characteristics 1 Vcc 4 0 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter FLASH MEMORY VERSION Min SCLK1 Serial 1 01 clock output H pulse width tc Scuk1 2 30 twL SCLK1 Serial 1 clock output L pulse width tc Scuk1 2 30 ta SCLK1 TxD Serial 1 01 output delay time 1 tv ScLK1 TxD Serial 1 output valid time 1 30 tr SCLK1 Serial 1 1 clock output rising time tt SCLK1 Serial 1 clock output falling time twH SCLKk2 Serial 2 clock output pulse width tc ScLk2 2 30 twL ScLK2 Serial 2 clock output L pulse width tc ScLk2 2 30 tt SCLK2 Serial 2 clock output falling time td SCLK2 SouT2 Serial 02 output delay time tv ScLk2 SouT2 NOTE Serial 2 output valid time 1 The P41 TxD P channel output disable bit bit 4 of address 001B16
228. set to 0 after a reset Rev 3 04 REJ03B0158 0304 Notes on Differences between Flash Memory Version and QzROM Version The flash memory and QzROM versions differ in their manufacturing processes built in ROM memory size and layout patterns Because of these differences characteristic values operation margins noise immunity and noise radiation and oscillation circuit constants may vary within the specified range of electrical characteristics When switching to the QzROM version implement system evaluations equivalent to those performed in the flash memory version Confirm page 11 about the differences of functions Notes on Power Source Voltage When the power supply voltage value of the MCU is less than the value indicated in the recommended operating conditions the MCU may not operate normally and perform unstable operation In a system where the power source voltage drops slowly when the power source voltage drops or the power is turned off reset the MCU when the power source voltage is less than the recommended operating conditions and design the system so that this unstable operation does not cause errors to it Notes on Handling Power Source Pins Before using the MCU connect a capacitor suitable for high frequencies as a bypass capacitor between the following The power source pin VCC pin and the GND pin Vss pin The power source pin VCC pin and the analog power source input pin AVSS pin As a bypas
229. sh memory version refer to the FLASH MEMORY MODE lt Notes gt After a reset the contents of RAM are undefined Make sure to set the initial value before use When Renesas ships write products we write ROM option data specified by the mask file converter MM to the ROM code protect address Therefore set FF16 to the ROM code protect address in ROM data regardless of the presence or absence of a protect When data other than FF 16 is set we may ask that the ROM data be submitted again ROM option data mask option noted in MM Rev 3 04 20 2008 17 0 134 stENESAS REJ03B0158 0304 3805 size bytes Address XXXX16 192 00 16 256 013 16 384 01 1 512 02316 640 02 1 768 033 16 896 O3BFi6 1024 043 16 1536 063 16 2048 083 16 ROM area 000016 SFR area 004016 010016 ROM size bytes Address YYYY16 Address ZZZZ16 4096 00016 F08016 8192 E00016 E08016 12288 000016 008016 16384 00016 08016 20480 00016 08016 24576 00016 08016 28672 900016 908016 32768 800016 808016 36864 700016 708016 40960 600016 608016 45056 500016 508016 49152 400016 408016 53248 300016 3080
230. source voltage 2 0 V 2 7V NOTE 1 For detailed specifications confirm the descriptions in the Datasheet On chip oscillator is stopped Notes on Differences between QZROM and Flash Mem ory Versions 1 The memory map the writing modes and programming circuits vary because of the differences in their internal memories 2 The oscillation parameters of XIN XOUT and XCIN XCOUT may vary 3 The QzROM version and the flash memory version MCUs differ in their manufacturing processes built in ROM and layout patterns Because of these differences characteristic values operation margins A D conversion accuracy noise immunity and noise radiation may vary within the specified range of electrical characteristics 4 When switching from the flash memory version to the QzROM version implement system evaluations equivalent to those implemented in the flash memory version 5 The both operations except the electrical characteristics are same at the emulator emulator MCU board M38D59T RLFS Rev 3 04 20 2008 11 01134 q NC S AS REJ03B0158 0304 3805 FUNCTIONAL DESCRIPTION Central Processing Unit CPU The 38D5 Group uses the standard 740 Family instruction set Refer to the 740 Family Software Manual for details on the instruction set Machine resident 740 Family instructions are as follows The FST and SLW instructions cannot be used The STP WIT MUL and DIV
231. state In the flash memory version T CcouT the on chip oscillator starts oscillating and the operation mode at zr J returning is set to on chip oscillator mode The bit 3 of CPUM is Vss changed to 0 bits 5 6 and 7 of CPUM are changed to 1 and the bit 0 of CPUM2 is changed to 0 forcibly Oscillator restarts when reset occurs or an interrupt request is received but the system clock is not supplied to the CPU until timer 2 underflows This allows time for the clock circuit oscillation to stabilize 2 Wait Mode If the WIT instruction is executed only the system clock stops at an state The states of main clock on chip oscillator and sub clock are the same as the state before executing the WIT instruction and oscillation does not stop Since supply of system clock is started immediately after the interrupt is received the instruction can be executed immediately Fig 61 External clock input circuit Rev 3 04 20 2008 Page 640f 134 stENESAS REJ03B0158 0304 3805 CPUN2 BITO On chip oscillator stop bit On chip oscillator 1 4 Main clock division ratio selection bit CPUM BIT7 6 11 XIN XOUT oscillation stop bit Internal system clock CPUM BIT5 p Selection bit Timer 1 count source 1 CPUM selection bits Timer 2 count source 01 selection bits
232. structions add and subtract logical operation instructions ADC SBC AND EOR and ORA when T flag 1 operate in the way as the read modify write instruction Do not execute them to the read invalid SFR lt Reason gt When the read modify write instruction is executed to the read invalid SFR the following may result As reading is invalid the read value is undefined The instruction modifies this undefined value and writes it back so the written value will be indeterminate Rev 3 04 REJ03B0158 0304 Notes on Peripheral Functions Notes I O Ports 1 Use in Stand By State When using the MCU in stand by state for low power consumption do not leave the input level of an I O port undefined Be especially careful to the I O ports for the N channel open drain In this case pull up connect to Vcc or pull down connect to Vss these ports through a resistor When determining a resistance value note the following External circuit Variation in the output level during ordinary operation When using a built in pull up resistor note variations in current values When setting as an input port Fix the input level When setting as an output port Prevent current from flowing out externally Reason Even if a port is set to output by the direction register when the content of the port latch is 1 the transistor becomes the OFF state which allows the port to be in the high impedance state This may ca
233. tWH SCLK2 Serial 2 clock input pulse width 950 twL ScLk2 Serial 1 2 clock input L pulse width 950 tsu SIN2 SCLk2 Serial 2 input setup time 400 Serial 1 2 input hold time 200 NOTE 1 When bit 6 of address 001 16 is 1 clock synchronous Divide this value by four when bit 6 of address 00116 is 0 UART Rev 3 04 20 2008 106 of 134 42 N S AS REJ03B0158 0304 3805 Table 32 Switching characteristics 1 Vcc 4 0 to 5 5 V Vss 0 V 20 to 85 C unless otherwise noted Symbol Parameter QzROM VERSION Min twH SCLk1 Serial 1 clock output H pulse width tc Scuk1 2 30 twL ScLk1 Serial 1 01 clock output L pulse width tc Scuk1 2 30 td ScLk1 TxD Serial l O1 output delay time 1 tv ScLk1 TxD Serial l O1 output valid time 1 30 tr SCLk1 Serial 1 01 clock output rising time tf SCLK1 Serial 1 01 clock output falling time twH SCLk2 Serial 1 02 clock output H pulse width tc ScLk2 2 30 twL ScLk2 Serial 1 02 clock output L pulse width tc ScLk2 2 30 tf SCLk2 Serial 1 02 clock output falling time td ScLk2 SouT2 Serial 02 output delay time tv SCLK2 SOUT2 NOTE Serial 1 02 output valid time 1 T
234. ter Test conditions RAM hold voltage When clock is stopped Power source current Frequency 2 mode Vcc 5V XIN 212 5MHz XIN 212 5MHz WIT state f XiN 4MHz f XiN 4MHz f XiN 24MHz in WIT state 2 2 XIN XIN f f Frequency 4 mode f XiN 212 5MHz f XIN 12 5MHz WIT state 2 f XiN 28MHz f XiN 28MHz in WIT state f XiN 4MHz XIN Frequency 8 mode f XiN 212 5MHz f XIN 12 5MHz WIT state Vcc 2 5V Low speed mode 5 0 f XIN stop in WIT state 2 5 WIT state On chip oscillator mode Vcc 5V stop Vcc 2 5V Vcc 2 5V WIT state oscillations stopped 25 STP state Ta 85 C Current increased f XiN 212 5 MHz Vcc 5 V at A D converter operating in frequency 2 4 or 8 mode f XiN 2 stop Vcc 5 V in on chip oscillator operating f XiN stop Vcc 5 V in low speed mode A D Converter Characteristics Table 28 A D converter recommended operating condition Vcc 2 0 to 5 5 V Ta 20 to 85 output transistors in cut off state unless otherwise noted Limits Typ Max Power source voltage d 5 0 5 5 H input voltage ADKEYo Vcc L input voltage ADKEYo 0 7 x Vcc 0 5 AD converter clock frequency 1 4 5 lt Vcc lt 5 5V 6 25 Low
235. the interrupt priority is determined by hardware priority processing can be performed by software using the above bits and flag interrupt request bit and the interrupt enable bit These bits and the interrupt disable flag I flag control the acceptance of interrupt requests Figure 18 shows an interrupt control diagram Table 11 Interrupt vector addresses and priority Vector Addresses 1 High Low FFFD1e 16 FFFBt16 1 Interrupt Request Generating Conditions Interrupt Source Priority Remarks Reset 2 At reset Non maskable INTo INToo or INTo1 INT10 or INT11 INT2 At detection of either rising or falling edge of INTo input External interrupt active edge selectable 91 FFF816 At detection of either rising or falling edge of INT1 input External interrupt active edge selectable FFF71e FFF616 At detection of either rising or falling edge of INT2 input At falling of ports 20 23 P44 P47 input logical level AND At timer X underflow At timer 1 underflow At timer 2 underflow At timer 3 underflow At timer 4 underflow At completion of serial 1 data receive Valid only when serial 1 1 is selected At completion of serial l O1 transmit Valid only when serial 1 1 is selected shift or transmit buffer is empty At completion of serial 1 02 data transmit receive At detection of either rising or falling edge of CNTRo input At tim
236. the receive shift register to the receive buffer register and the receive buffer full flag is set A write to the serial I O1 status register sets all the error flags OE PE FE and SE bit 3 to bit 6 respectively to 0 Writing 0 to the serial enable bit SIOE bit 7 of the serial I O1 control register also sets all the status flags to 0 including the error flags All bits of the serial I O1 status register are set to 0 at reset but if the transmit enable bit bit 4 of the serial I O1 control register has been set to 1 the transmit shift completion flag bit 2 and the transmit buffer empty flag bit 0 become 1 Serial 1 Control Register SIO1CON The serial I O1 control register consists of eight control bits for the serial I O1 function UART Control Register UARTCON The UART control register consists of four control bits bits 0 to 3 which are valid when asynchronous serial I O is selected and set the data format of the data transfer and one bit bit 4 which is always valid and sets the output structure of the P41 TxD pin Baud Rate Generator BRG The baud rate generator determines the baud rate for serial transfer The baud rate generator divides the frequency of the count source by 1 n 1 where n is the value written to the baud rate generator Rev 3 04 REJ03B0158 0304 lt Notes on serial 1 gt When setting transmit enable bit of serial I O1 to 1
237. the user s manual of your programmer for details on how to use it Performance overview Table 16 lists the performance overview of the 3805 Group flash memory version This flash memory version has some blocks on the flash memory as shown in Figure 70 and each block can be erased In addition to the ordinary User ROM area to store the MCU operation control program the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I O modes This Boot ROM area has had a standard serial I O mode control program stored in it when shipped from the factory However the user can write a rewrite control program in this area that suits the user s application system This Boot ROM area can be rewritten in only parallel I O mode Table 16 Performance overview of 38D5 Group flash memory version Parameter Function Power source voltage Vcc Vcc 2 7 to 5 5 V Program Erase VPP voltage VPP Vcc 2 7 to 5 5 V Flash memory mode 3 modes Parallel mode Standard serial I O mode CPU rewrite mode Erase block division User ROM area Data ROM area Refer to Figure 70 Boot ROM area 1 Not divided 4K bytes Program method In units of bytes Erase method Block erase Program Erase control method Program Erase control by software command Number of commands 5 commands Number of program Erase times 100
238. tion in Clock Synchronous Serial I O Mode In clock synchronous serial I O mode set the transmit enable bit and the receive enable bit to 0 simultaneously to stop transmit receive operations If only one of the operations is stopped transmission and reception cannot be synchronized which will cause a bit error Notes on Serial 02 1 Switching Synchronous Clock If the synchronous clock is switched by the serial I O2 synchronous clock selection bit bit 6 of serial I O2 control register address 001D16 initialize the serial I O2 counter writing to serial I O2 register address 001F16 2 Notes When External Clock Selected When the external clock is selected as the synchronous clock the SOUT pin retains the D7 level after transfer is completed However if the synchronous clock is continuously input the serial I O2 register continues shifting and the SOUT2 pin keeps outputting transmit data Also write to the serial I O2 register while SCLK2 is set to When the internal clock is selected as the synchronous clock the SoUT pin is placed in the high impedance state after transfer is completed 20 2008 128 of 134 4 NE S AS 3805 Notes A D Conversion 1 Analog Input Pin Set the signal source impedance for analog input low or equip an analog input pin with an external capacitor of 0 01 uF to 1 In addition operations of application products should be verifie
239. tion is executed bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag Set and clear instructions of each bit of processor status register Set instruction Rev 3 04 Clear instruction REJ03B0158 0304 20 2008 Page 14 0 134 sENESAS 3805 CPU Mode Register CPUM 003 16 In the flash memory version only the on chip oscillator starts The CPU mode register contains the stack page selection bit etc Oscillating The XIN XOUT oscillation stops oscillating and the This register is allocated at address 003 16 XCIN and XCOUT pins function as I O ports The operating mode After the system is released from reset the mode depends on the 18 the on chip oscillator mode OSCSEL pin state in the QzZROM version When the main clock or sub clock is used after the XIN XOUT When the OSCSEL pin state is GND level only the on chip Oscillation and the XciN XcovT oscillation are enabled wait in oscillator starts oscillation The XIN XOUT oscillation stops the on chip oscillator mode etc until the oscillation stabilizes oscillating and XCIN and XCOUT pins function as I O ports The and then switch the operation mode E operating mode is the on chip oscillator mode When the main clock is not used XIN XOUT oscillation and an When the OSCSEL pin state is level the XiN Xour external clock input are not used connect the XIN pin to Vcc oscillatio
240. tion of VREF and AVss revised 64 to 67 Fig 63 to Fig 66 Revised and added Table 17 Parameter of and lic added Aug 31 2006 Table 1 Main clock and Sub clock generating circuit feedback resistor eliminated Table 3 AVss GND Analog power source Table 8 P41 TxD input port gt output port P42 ScLK1 output port gt input port 2 7 REVISION HISTORY 38D5 Group Data Sheet Rev Date Description Summary 2 03 5 Aug 31 2006 Table 16 Max of f 2 x Vcc 45 4 Table 17 Test condition of VT VT Vcc 2 0 V on RESET gt Vcc 2 0 V to 5 5 V on RESET Table 24 Limits of twH SCLK2 tw ScLk2 tc ScLK1 2 80 tc ScLK2 2 80 MEMORY ROM Description revised ROM Code Protect Address Description revised and added Fig 10 Reserved ROM area FFD016 16 Fig 8 and Fig 60 CPUM2 bits 2 to 7 revised Direction Resisters Description revised Fig 11 ROM correction enable register gt ROM correction enable register RCR 2 04 Feb 02 2007 Table 8 Terminations 1 and 2 of VL3 revised Fig 13 PULL3 bits 4 to 7 SEG2 bits 4 to 7 revised Fig 19 INTEDGE bit 6 ICON2 bit 7 revised Fig 25 revised Fig 28 Note added and revised Fig 27 TXCON BITS 3 4 revised Fig 36 Note added Fig 29 TYM bits 2 3 revised AD control Register Fig 39 Fig 38 Note added 46 analog input selection bit analog input pin se
241. tion of input port P45 Sour2 KWt1 When selecting Sour function perform termination of output port P4e ScLk2 KWo When selecting external clock input When selecting internal clock output perform termination of output port perform termination of output port P47 SRbv2 KWs3 When selecting SRpv2 function perform termination of output port P50 ANo RT Po When selecting AN function these pins When selecting RTP function P51 AN1 RTP1 can be opened A D conversion result perform termination of output port P52 AN2 P56 AN6 cannot be guaranteed _ P57 AN7 ADKEYo When selecting ADKEY function pull up this pin through a resistor P60 XCIN Do not select XciN Xcour oscillation P61 XcouT function by program P62 INToo LEDo When selecting INT function perform termination of input port P6es Txour2 LED1 When selecting Txour function perform termination of output port P64 INT2 LED2 When selecting INT function perform termination of input port P65 TxouT1 LED3 When selecting Txour function perform termination of output port P66 INT10 CNTRo When selecting CNTR input function or INT LEDa4 function perform termination of input port P67 CNTR1 LEDs When selecting CNTR input function perform termination of input port P70 C1 INTo1 Disable the voltage multiplier and When selecting INT function disable the voltage P71 C2 INT11 connect to Vss through a resistor mu
242. tive 1 Rising edge active nterrupt request register 1 b7 50 IREQ1 address 003 1 Interrupt request register 2 REQ2 address 003D16 INTo interrupt request bit INT1 interrupt request bit INT interrupt request bit Key input interrupt request bit Timer X interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit 50 Timer 4 interrupt request bit Serial 1 receive interrupt request bit Serial 1 transmit interrupt request bit Serial 2 receive transmit interrupt request bit CNTRo interrupt request bit Timer Y interrupt request bit CNTA1 interrupt request bit AD conversion interrupt request bit Not used returns 0 when read 0 No interrupt request issued 1 Interrupt request issued ds nterrupt control register 1 60 control register 2 ICON2 address 003F 16 ICON1 address 003 16 INTo interrupt enable bit interrupt enable bit INT2 interrupt enable bit Key input interrupt enable bit Timer X interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Fig 19 Structure of interrupt related registers Rev 3 04 20 2008 30 01134 RENESAS REJ03B0158 0304 L Timer 4 interrupt enable bit Serial 1 receive interrupt enable bit Serial 1 transmit interrupt enabl
243. tput Port P2 direction disable register 1 register bit 1 1 Bit 1 1 Key input control register bit 5 2 1 Port P2 x Port P21 Tt Ben Input reading circuit gt DD Segment output Port P2 direction disable register 1 register bit 0 1 Bit 0 1 Key input control register bit 4 1 Port P20 oe P20 output n i gt 22 output P21 output Port P4 direction register bit 7 0 Key input control register bit 3 1 Port P47 latch P47 D gt Port P4 direction register bit 6 0 Key input control x Port 4 register bit 2 1 latch L P4 input LI Port P4 direction register bit 5 0 Key input control Port P4 Riu Ponpa EE EET Input reading circuit latch y e input gt gt Port P4 direction register bit 4 0 Key input control register bit 0 1 Port P44 latch 1 P44 inpu i i gt gt PULL register 3 lt Bit 1 f P channel transistor for pull up CMOS output buffer Fig 23 Connection example when using key input interrupt Rev 3 04 20 2008 33 01134 RENESAS REJ03B0158 0304 3805 A k
244. twL CNTR CNTRo CNTR1 twH INT tWL INT INToo INTO1 0 8VCC INT10 INT11 0 2VcC INT2 tw RESET 0 2Vcc 0 8VcC tWH XIN tWL XIN 0 2Vcc tC SCLK1 5 tWL SCLK1 tWL SCLK2 tr tWH SCLK1 tWH SCLK2 0 2Vcc tsu RXD SCLK1 th SCLK1 RXD tsu SIN2 SCLK2 th SCLK2 SIN2 XXX XXX XXX XXX XA SR 0 2voc 1200000606000 0000 Nw CN NL 2 CN CNN tv SCLK1 TXD td SCLK1 TXD td SCLK2 SOUT2 tV SCLK2 SOUT2 Fig 98 Timing diagram in single chip mode Rev 3 04 20 2008 11901134 42 N S AS REJ03B0158 0304 3805 PACKAGE OUTLINE Diagrams showing the latest package dimensions and mounting information are available in the Packages section of the Renesas Technology website JEITA Package Code RENESAS Code Previous Code MASS Typ P QFP80 14x20 0 80 PRQPO0080GB A 80P6N A 1 6g Index mark Rev 3 04 20 2008 120 of 134 42 N S AS REJ03B0158 0304 A1 Detail F NOTE 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET Reference Dimension in Millimeters Symbol Min Nom D 19 8 20 0 20 2 13 8 14 0 14 2 A2 2
245. uction sets the LCD enable bit bit 4 of LCD mode register address 001316 to 0 and the LCD panel turns off To turn the LCD panel on after returning from stop mode set the LCD enable bit to 1 2 Pin To use the LCD drive control circuit while VL3 is set to the voltage equal to Vcc apply the Vcc voltage to the VL3 pin and write 1 to the VL3 connection bit bit 1 of LCD mode register 2 address 001416 at 8COM x 32SEG 084216 2 084316 SEG3 084416 SEG4 084516 SEGs 084616 SEGe 084716 SEG7 084816 SEGs 084816 084916 SEGo 084916 084A16 SEGio 084A16 084 16 SEGi11 084 16 084 16 SEG12 084016 SEG13 084C16 084016 084 16 SEG14 084E16 Not used This area can be used as normal RAM 084F16 SEG15 085016 SEG16 084F16 085016 085116 SEG17 085116 085216 SEG18 085316 SEG19 085216 085316 085416 SEG20 085416 085516 SEGa1 085616 SEG22 085516 085616 085716 SEGes 085816 SEG24 085916 SEGe5 085716 085A16 SEG26 085 16 SEG27 085 16 SEG28 085B16 085C16 085016 SEG29 085016 085 16 085 16 1 085E16 086016 SEGs 086116 SEG33 086216 SEG34 Not used 086216 This area can be used as normal RAM 086316 SEG35 086316 COM2 COM1 COM6 COM5 COM4 COM3 COM1
246. up P72 P74 pull up Not used do not write 1 Not used return 0 when read Pull up Control Each individual bit of ports PO P3 can be pulled up with a program by setting direction registers and segment output disable registers to 2 addresses OFF416 to OFF616 Sediment ufu disable The pin is pulled up by setting 0 to the direction register and SEGO address 416 to the segment output disable register P00 pull By setting the PULL registers addresses OFF016 to OFF216 pull ports P4 P7 can control pull up with a program pull However the contents of PULL register do not affect ports P03 pull programmed as the output ports FOU POs pull pull 0 No pull up P0O7 pull 1 Pull up alle Segment output disable register 1 1 address OFF516 P20 pull P21 pull P22 pull P23 pull P24 pull P25 pull P26 pull 0 No pull up P27 pull 1 Pull up Segment output disable register Direction register Initial state Input port Input port No pull up Pull up b0 Segment output disable register 2 Segment 2 address OFF616 come Port output 10 1 pull up output P14 P17 pull up 0 N No pull up P3o P33 pull up 1 Pull up P34 P37 pull up Fig
247. use the level to be undefined depending on external circuits As described above if the input level of an I O port is left undefined the power source current may flow because the potential applied to the input buffer in the MCU will be unstable 1 Stand by state Stop mode by executing the STP instruction Wait mode by executing the WIT instruction 2 Modifying Output Data with Bit Handling Instruction When the port latch of an I O port is modified with the bit handling instruction the value of an unspecified bit may change Reason I O ports can be set to input mode or output mode in byte units When the port register is read or written the following will be operated Port as input mode Read Read the pin level Write Write to the port latch Port as output mode Read Read the port latch or peripheral function output specifications vary depending on the port Write Write to the port latch output the content of the port latch from the pin Meanwhile the bit handling instructions are the read modify write instructions 2 Executing the bit handling instruction to the port register allows reading and writing a bit unspecified with the instruction at the same time If an unspecified bit is set to input mode the pin level is read and the value is written to the port latch At this time if the original content of the port latch and the pin level do not match the content of the port latch changes If an unspecifi
248. using E8 programmer connection example 1 OSCSEL L Rev 3 04 20 2008 700f 134 stENESAS REJ03B0158 0304 3805 QzROM version 38D5 Group OSCSEL P41 ESDA P42 ESCLK P43 ESPGMB circuit Set the same termination as the single chip mode 1 Open ocollector buffer 2 When programming 38D5 Group is performed disconnect Vcc from OSCSEL by a jumper switch Note For the programming circuit the wiring capacity of each signal pin must not exceed 47 pF Fig 67 When using E8 programmer connection example 2 OSCSEL Rev 3 04 20 2008 71 01134 stENESAS REJ03B0158 0304 3805 QzROM version 38D5 Group T_VDD gt T VPP gt OSCSEL 4 7kQ T TXD 27 7 T RXD gt P41 ESDA T SCLK P42 ESCLK T BUSY NC T_PGM OE MD 4 ESPGMB RESET circuit RESET RESET 4 GND Vss AVss XIN XOUT at Set the same termination as the single chip mode Note For the programming circuit the wiring capacity of each signal pin must not exceed 47 pF Fig 68 When using programmer of Suisei Electronics System Co LTD connection example 1 OSCSEL L Rev 3 04 20 2008 72 01134 stENESAS REJ03B0158 0304 380
249. ut Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers offi
250. when the block erase operation is completed as is the status register bit 7 SR7 After the block erase ends erase results can be checked by reading the status register For details refer to the section where the status register is detailed Erase error Erase completed write read command FF 16 Fig 76 Erase flowchart Rev 3 04 20 2008 800f134 RENESAS REJ03B0158 0304 3805 Status Register The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error It can be read in the following ways 1 By reading an arbitrary address from the User ROM area after writing the read status register command 7016 2 By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command 16 is input Also the status register can be cleared by writing the clear status register command 5016 After reset the status register is set to 8016 Table 19 shows the status register Each bit in this register is explained below Sequencer status SR7 The sequencer status indicates the operating status of the flash memory This bit is set to 0 busy during write or erase operation and is set to 1 when these operations ends After power on the sequencer status is set to 1 ready Table 19 Definition
251. wide Also take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals Keeping oscillator away from large current signal lines Install a microcomputer and especially an oscillator as far as possible from signal lines where a current larger than the tolerance of current value flows Reason In the system using a microcomputer there are signal lines for controlling motors LEDs and thermal heads or others When a large current flows through those signal lines strong noise occurs because of mutual inductance 2 Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently Also do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise Reason Signal lines where potential levels change frequently such as the CNTR pin signal line may affect other lines at signal rising edge or falling edge If such lines cross over a clock line clock waveforms may be deformed which causes a microcomputer failure or a program runaway 1 Keeping oscillator away from large current signal lines Microcomputer Mutual inductance GND Large current 2 Installing oscillator away from signal lines where potential levels change frequently Do not cross
252. write mode 3 Interrupts inhibited against use The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data of the flash memory 4 Watchdog timer In case of the watchdog timer has been running already the internal reset generated by watchdog timer underflow does not happen because of watchdog timer is always clearing during program or erase operation 5 Reset Reset is always valid In case of CNVss when reset is released boot mode is active So the program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area CNVss Pin The CNVss pin determines the flash memory mode Connect the CNVss VPP pin the shortest possible to the GND pattern which is supplied to the Vss pin of the microcomputer In addition connecting an approximately 5 resistor in series to the GND could improve noise immunity In this case as well as the above mention connect the pin the shortest possible to the GND pattern which is supplied to the Vss pin of the microcomputer Note When the boot mode or the standard serial I O mode is used a switch of the input level to the CNVss pin is required T shortest Note 1 Shows the microcomputer s pin Fig 90 Wiring for the CNVss Rev 3 04 REJ03B0158 0304 NOTES ON DIFFERENCES BETWEEN QzROM VERSION AND FLASH MEMORY VERSION The QzROM and flash memory versions differ in their manufacturing processes built in ROM an
253. ytes first and the high order bytes next Write to or read from the timer Y register by the 16 bit unit If reading from the timer Y register during write operation or writing to it during read operation is performed normal operation will not be performed Which write control can be selected by the timer Y write control bit b0 of the timer Y control register address 003916 writing data to both the latch and the timer at the same time or writing data only to the latch When writing a value to the timer Y address to write to the latch only the value is set into the reload latch and the timer is updated at the next underflow After reset release when writing a value to the timer Y address the value is set into the timer and the timer latch at the same time because they are set to write at the same time When writing to the latch only if the write timing to the high order reload latch and the underflow timing are almost the same the value is set into the timer and the timer latch at the same time In this time counting is stopped during writing to the high order reload latch 60 Timer mode register TYM address 003816 L Real time port 1 control bit P50 0 Real time port function invalid 1 Real time port function valid Real time port 2 control bit P51 0 Real time port function invalid 1 Real time port function valid RTPo data for real time port 1 data for real time port Timer Y operating mode bits b5

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