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User interface processor for computer network with maintenance

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1. 4 bee SI Sheet 11 of 16 4 701 845 U S Patent Oct 20 1987 224 583008 994 SW3G0W 335 QUNM AME sng 90 33 9 9914 DY TNU3INT M 0 1804 01 91907 let 3VHSONVH 1081807 1904 SYJLYJANT 11934 04 VIV 119110 NANI 01 o asta siod hd 91901 s NOI LINO SLOW 1311931 WIJANG TETUR vivi INANI viva ind ind V F a ___ KINO 8 1404 2 ONY LT SH3WI M31N009 OL _ WNN3INI LUV 2078 8 ONY v 5150400 9 DIA U S Patent Oct 20 1987 Sheet 12 of 16 4 701 845 FIG 6 PRIOR ART PORT C 409 CIO PORT C BLOCK DIAGRAM INTERNAL SEE FIG 4 TO COUNTER TIMER 3 i PORT POR 403 FIG 4 Cee an ME COUNTER TIMER 3 TO PORT A PORT 0 8 fp HANDSHAKE AND 630 REQUEST WAIT LOGIC 212 610 QUTPUT DATA REGISTER BUFFER 1 618 INVERTERS L 620 622 618 INTERNAL PORT CONTROL LINES Sheet 13 of 16 4 701 845 U S Patent Oct 20 1987 0b 20 Lev goa 10 5 850 83151934 5 851 83151938 02 INNO 1N3HMf INNOD INIHYND a A 1081502 8313102 1909 OL SASW 3151939 INVISNOO WIL 5 851 93151939 INVLSNOD 91901 HINO 8 102 010 508 INU3LNT 2018 7 331N0O 2911 U S Patent
2. lt 001 STRETCH CLK INTERRUPTS PIC DIAGNOSTIC CONTROL SHIFT CHAINS 1001 LEGEND UIP PIC ODT DLI BUS 100 UIP DLP E 1004 REMOTE D SUPPORT LINK 11 USER INTERFACE PROCESSOR PROCESSOR INTERFACE CARD OPERATOR DISPLAY TERMINAL DATA LINK INTERFACE DLI MLI DATA LINK INTERFACE and or MESSAGE LEVEL INTERFACE MCU MEMORY CONTROL UNIT HDP HOST DEPENDENT PORT U S Patent Oct 20 1987 FIG 1D UIP I O INTERFACE PCT PCC UIP DLI BDI ODT MDT DLP LOCAL TERMINA ODT or M REMOTE SUPPORT LINK PROCESSOR INTERFACE CARD POWER CONTROL CARD USER INTERFACE PROCESSOR DATA LINK INTERFACE BURROUGHS DIRECT INTERFACE OPERATOR DISPLAY TERMINAL MAINTENANCE DISPLAY TERMINAL DATA LINK PROCESSOR Sheet 6 of 16 4 701 845 _ 4 701 845 Sheet 7 of 16 U S Patent 20 1987 1530038 LIYA JN 99019 13NNVH VIVO 141935 Sa 51041809 43H10 HO N300N 00 51041800 Y3HL0 80 W3QOW 1530038 LIYA JNAS 93901 TINNYHI C VIVO 141935 Wd OND AA SINIT 1081800 dft LNL 006 0 1 518 fld CS y a W 47 ISSN 91901 TOULNOD bel 011 Sd WVYOVId 2018 H3T1OHINO2 SNOTLVSINAWWOD 191935 LUV Hong 7514 DGI 0010 SAILS ONY ONY V 8 T3NNWHO U S Patent Oct 20 1987
3. FIG 1A shows the User Interface Processor 100 as part of a network configuration The output bus 100 of microprocessor 110 connects to the processor interface card 40 and to the memory bus 30 which connects the main processor 30 FIG 1B to the memory control unit 32 and main memory 34 In FIG 1A the DRAM 150 provides output to the power control card 50 and the erasable PROMs 150 connect to the operator display terminal 100 The power control card 50 FIG 1A functions to provide power up down sequencing to monitor for power failure to initiate automatic restart after power failure to provide warning of over temperature to 20 25 30 40 45 50 55 60 65 4 provide automatic power ON OFF operation to pro vide remote power control of external cabinets to maintain an internal time of day clock and to provide a communication path data link for a remote support and diagnostic service The processor interface card 40 FIG 1A functions to provide control and data acquisition for diagnostic testing of memory 34 FIG 1B memory control unit 32 host dependent port 500 and the main processor 30 the PIC 40 provides initialization functions such as microcode load initialization state and clock control and distribution The PIC 40 provides a history file FIG 1A for real time tracing of microcode addresses break points it provides 16 general purpose links for tracing of intermittent failures a
4. a5 programmable priority interrupt controller means connected to said microprocessor means for receiving and prioritizing interrupt signals from said serial communications controllers from said L O port means and from a plurality of programmable interval timers and including a5a means to output a vector data signal to said microprocessor means for selecting a service routine dependent on the source of said inter rupt signal 5 10 15 20 25 30 35 45 50 55 60 65 30 a6 said plurality of programmable interval timers for receiving instruction data from said micro processor means and for providing programmed time interval signals to said priority interrupt controller means b a dual function controller means connected to said microprocessor means to said serial communica tions controllers to said I O port means and to said priority interrupt controller means said dual function controller providing an interface for data transfers via said data link transfer interface and including 1 means to execute transfer operations as a mas ter via said data link transfer interface to said data link processors said user interface proces sor operating to send commands to initiate a data link processor self test routine and b2 means to execute data transfer operations to said host computer as a slave of said data link transfer interface said data transfer being exe cuted as a specifically ori
5. 1 Programmable Array Logic are as follows LCLCLR Local clear MSTRCLR Master clear SELCLR Select clear PUPCLR Power Up clear PSSCLG Path selection module generated clear These signals are received and latched by the Clear self test PAL 112 and a non maskable interrupt is gen erated by the self test PAL 112 thus informing the microprocessor 110 that a clear condition has occurred The microprocessor 110 can then read this PAL 112 and determine which condition occurred and what action to take as a result The Clear self test PAL 112 also performs the func tion of controlling the microprocessor 110 reset Signal The UIP 100 resets and clears for the following listed conditions i PUPCLR power up clear ii A foreplane paddle card mounted push button clear iii Jumper selectable option of selective clear SELCLR iv All other clear signals generate the 8086 micro processor s 110 FIG 1 non maskable interrupt Incorporated into the clear self test PAL 112 is the dynamic RAM parity error signal This term also gener ates a non maskable interrupt and can be read by the microprocessor 110 to determine which clear signal or parity error caused the NMI interrupt DLI Send Receive Registers In FIG 9 the DLI send receive registers 912 and 922 are implemented in two 2917A bidirectional register latches The 2917A is a register latch manufactured by Advanced Micro Devices Inc whose a
6. FIG 1B The User Interface Processor 100 can communicate via the controller 180 and through the UIO universal input output backplane to a host computer using a standard UIO DLI backplane protocol which conforms to the Burroughs Message Level Interface as described in U S Pat No 4 074 352 at FIG 5E this patent being entitled Modular Block Unit for Input Output Subsys tem The User Interface Processor is capable of simulating a DLI host dependent port thus enabling it to commu nicate with data link processors in a common base that does not have a distribution card It emulates the priorly used Distribution Card The description of data link processors and use of the distribution card have been described in U S Pat Nos 4 313 162 entitled I O Subsystem Using Data Link Processors and 4 390 964 entitled Input Output Subsystem Using Card Reader Peripheral Controller The User Interface Processor includes backplane interface to a bus known as the backplane maintenance These backplane lines can be used to initiate a data 10 20 25 link processor self test routine and to read a result of 30 that self test as it is driven on to the backplane from a given data link processor In this disclosure the two above mentioned user interface processor ports will be referred to as the DLP and the HDP respectively The User Interface Processor 100 FIG 1 is a micro processor controlled system that contain
7. PIT As seen in FIG 1 1 the User Interface Processor includes a PIT 700 or programmable interval timers These incorporate three counter timers which are used as interval timers Each device is an eight megahertz programmable interval timer that consists of an I O accessible set of three 16 bit counter timers These timers operate functionally similar to the three counters in the CIO 400 Two outputs of the PIT 700 timers are ORed together and drive an interrupt level to the priority interrupt controller PRITC 800 of FIG 1 1 The individual outputs of these two timers are also routed to the CIO 400 FIG 4 so that the microproces sor 110 of FIG 1 1 can determine via a read from the CIO port which timer caused the interrupt The other timer also directly drives the programmable priority interrupt controller PRITC 800 via a different inter rupt level The PIT 700 FIG 1 1 programmable interval timer has six different modes of operation which may be described as follows Output on terminal count A hardware retriggerable one shot A rate generator A squarewave generator A software triggerable strobe A hardware triggered strobe Programmable Priority Interrupt Controller 800 In FIGS 1 and 8 there is seen the PRITC 800 which is designated as the Programmable Priority Interrupt Controller In order to accommodate the multiple inter rupts provided on the User Interface Processor this interrupt controller de
8. STARTING SYSTEM INITIALIZATION In the described computer network this initialization will take an approximate time of three minutes If the reading does not appear on the console display 100 within a few seconds then it indicates that the mainte nance subsystem is not operable and the following prob lems are likely to be encountered a There is no external power being supplied to the console cabinet It is necessary to restore power and then to press the power on button again 5 20 25 30 35 40 45 50 55 60 65 20 b The self test procedures have encountered a fail ure It is necessary again to push the button for pow er off power on another time Here a repeated fail ure to display the greeting on the ODT screen 100 indicates that there are problems in the system hard ware or the firmware c There is some problem that exists in the connec tion from the maintenance subsystem over to the operator s console 100 Here it is necessary to make sure that the operator s terminal 100 15 properly pow ered and turned on and also to check that the cable from the computer cabinet to the terminal 100 is securely plugged into the terminal After this check is made it is necessary to press the button for power off power on again LOADING MAINTENANCE SUBSYSTEM SOFTWARE It is now necessary that the maintenance subsystem load its own software from a file designated BOOT CODE whi
9. Ue sss J 6 1911335 ee ne sas d oll 86 9I4 4 701 845 1 USER INTERFACE PROCESSOR FOR COMPUTER NETWORK WITH MAINTENANCE AND PROGRAMMABLE INTERRUPT CAPABILITY FIELD OF THE INVENTION This disclosure relates to the area of computer net works and to specialized processors which operate a maintenance subsystem for the network CROSS REFERENCES TO RELATED APPLICATIONS This application is related to a copending application entitled Maintenance Subsystem For Computer Net work U S Ser No 664 670 filed Oct 25 1984 by inventor David Andrew Andreasen et al BACKGROUND OF THE INVENTION In the design and development of computer system networks there are many considerations and trade offs which must be balanced in order to provide an optimum system and to decide what limits must be drawn in terms of economic factors size and space factors and versatility of control of the system The presently described computer network system is designed not only to be used with a variety of periph eral type devices but also with data comm and tele phone lines to remote terminals to provide rapid trans ference of data between the units and rapid data pro cessing by a central processing unit in a fashion whereby reliability is maintained to a very high degree The system is organized so that each of the various elements and units will when initiated provide its own self test routines and report the results
10. e Waa BUS aim mef MPU L gt 50 SCC I MODEMS J 2 dy 200b S 3 CALL ra C10 e UIS 7 lt 2 I E ipai DLI HDP CONTROLLER f 180 PERIPHERAL INTERFACE U S Patent Oct 20 1987 Sheet 2 of 16 4 701 845 FIG 1 2 MAIN HOST COMPUTER ADDR BUS i nee FPI2 rig OO DI DO DT DO CAS 150a i 50 DRAM 0 BACKPLANE 500 4 701 845 Sheet 3 of 16 U S Patent 20 1987 uc 105 a nen Ime SOOW 100 77 W300 1404415 100 dog JLOWIH 05 UVI 1081809 83004 1041302 TNH 0b MV 1419 805530084 IQ AMOLSIH 518084 LNdNI 91 4001 sng 001 snd W u 25018 WSLSASENS 3oNVN3INIVN V I SL 4 701 845 Sheet 4 of 16 U S Patent Oct 20 1987 S 34 2005 358 0 1 NOISNVdX 3 5008 WAISASENS 0 1 S DE sawa 3915015 TIW UG 110 004 SNE 0 805532084 001 41 905539044 WISA Hg 10 1 04405 1001 083 018 431545 OIA U S Patent Oct 20 1987 Sheet5of16 4 701 845 IG 1C UIP AND SYSTEM MAINTENANCE INTERFACE 32 DIAGNOSTIC CONTROLS M BUS SHIFT CHAIN 30m ac c lt lt gt c CI
11. ii a dynamic RAM of 512K bytes 150 iii a PROM of 192K bytes EPROM 170 iv four serial data communication ports 200 5 202 5 six parallel I O ports two units of 407 408 409 vi programmable interval timers PIT 700 vii a programmable interrupt controller PRITC 800 These elements are shown in FIG 1 of the drawings MICROPROCESSOR 110 The microprocessor 110 is used to drive the User Interface Processor 100 and may constitute an eight megahertz chip designated as the INTEL 8086 2 iAPX 86 10 This microprocessor chip is described at pages 3 1 through 3 24 in an INTEL publication enti tled Microprocessor and Peripheral Handbook 1983 Order No 210844 001 and published by INTEL Lit erature Dept 3065 Bowers Avenue Santa Clara Ca 95051 This processor is a high performance 16 bit CPU which is implemented in HMOS technology and pack aged in a 40 pin dual in line package This processor is capable of addressing up to one megabyte of memory as well as 64k of I O addresses The 8086 microproces sor is operated in a minimum mode since it is used only in a single processor environment and as such it gener ates its own bus control signals DYNAMIC RAM 150 The microprocessor 110 is provided with access to a dynamic RAM array of 128 bytes The array 150 of FIG 1 2 is organized as 64 18 bits and it is byte addressable by the microprocessor 110 The RAM array 150 is controlled by a dynamic
12. 1C in the maintenance subsystem is used to provide the basic system clocks and in addition it provides data link inter face input output clocks of 8 megahertz It provides an interface to the processor backplane and also provides a unit called the system event analyzer 40e Further the PIC provides 4 000 16 bit words of history trace 40 in order to maintain a history of any selected input signal Additionally it provides a 16 K byte memory which holds the error correction bits for the control store in the User Interface Processor The Power Control Card PCC The power control card 50 FIG 1A will control the power on off sequencing and detect any DC failures for all power supply modules which are connected directly to the PCC The PCC also monitors any air loss and cabinet over temperature in order to provide sensing signals to this effect The power control card communicates with the User Interface Processor via an 8 bit parallel bus It further communicates with any remote device using the RS 232C remote link interface It can communicate with other power control cards on external basis by using two wire RS 422 direct connect data communication protocol The power control card 50 also maintains a battery backup with the time of day function in addition to providing 256 bytes of non volatile storage memory It also provides an automatic restart option after failure of the AC power lines DESCRIPTION OF PREFERRED EMBODIMENT
13. 30 45 55 60 65 18 The burst end logic 926 uses the signal TERM termi nate the signal BUFFUL carry out of the burst counter and the signal STIOL strobe 1 level These signals are used to provide a condition input to the DLI state machine 925 910 to halt the burst mode as well as to reset the burst flip flop 926 Longitudinal Parity Generation Checking The parity check circuit 918 provides a longitudinal parity generator which is implemented in two PALs 923 which are programmed to perform the longitudi nal parity word LPW accumulation A data pipelining latch means consists of two latches 914 and 923 which are used to meet the timing requirements on the internal DLI data bus FIG 9B The microprocessor 110 of FIG 1 controls the clear ing and also examines the NEQZERO status from the LPW generator 923 The DLI state machine 910 925 controls the accumulation and the reading of the longitudinal parity word LPW generator 923 The pipelining latch enable 923 is also controlled by the DLI state machine 910 925 Vertical Parity Generation Checking Vertical parity generation and routing are performed by two nine bit parity generators with a quad 2x1 tristate multiplexor 922 A bidirectional register latch 2917A is used to send and receive the parity bit on the DLI data bus FIG 1 Vertical parity is generated and written into the par ity RAM 920 when writing into the dual port RAM 920 from th
14. 85 Family User s Manual Oct 1979 by Intel Corp pp 6 68 73 6 132 7 6 140 9 6 158 67 6 17 8 85 Primary Examiner Gary V Harkcom Assistant Examiner Lawrence E Anderson Attorney Agent or Firm Alfred W Kozak Nathan Cass L Joseph Marhoefer 57 ABSTRACT A processor forms part of a computer network wherein the processor designated as the User Interface Proces Sor operates to initialize and maintain and communicate to remote diagnostic terminals for purposes of confirm ing integrity of the system and also for finding the loca tion of any faults or problems in the system The User Interface Processor involves a microprocessor unit working in conjunction with a serial communications controller random access memory and read only mem ory memories a communications input output 1 O system a multiple set of timer units and a priority inter rupt controller The User Interface Processor provides interfaces to a power control card unit an I O subsys tem of data link processors and a remote terminal for diagnostic intercommunication 11 Claims 19 Drawing Figures USER INTERFACE PROCESSOR BLOCK DIAGRAM J 2 52 7 WTS 7 gt PERIPHERAL INTERFACE U S Patent Oct 20 1987 Sheet 1 of 16 4 701 845 FIG 1 1 USER INTERFACE PROCESSOR BLOCK DIAGRAM 5 ADDRESS LATCH CLEAR 2 ary DT 2 2 11 HLDA CTL als
15. In synchronous modes the data path is determined by the phase of the receive process currently in oper ation synchronous receive operation begins with a hunt phase in which a bit pattern that matches the programmed sync characters 6 8 or 16 bits is searched The incoming data then passes through the receive sync register 282 and is compared to a sync character stored in register WR6 238 or register WR7 236 depending upon the mode being used The monosync mode matches the sync characters programmed in register WR7 236 and the character assembled in the receive sync register 282 in order to establish synchronization 0 20 25 30 35 40 45 50 55 65 10 Synchronization is achieved differently in the bi sync mode Incoming data is shifted into the receive shift register 232 234 while the next eight bits of the message are assembled in the receive sync register 282 If these two characters match the programmed charac ters in WR6 238 and in register WR7 236 the syn chronization is established Incoming data can then bypass the receive sync register 282 and enter the three byte delay 280 directly The SDLC mode of operation uses the receive sync register 282 to monitor the receive data stream and to perform zero deletion 278 when necessary for exam ple when five continuous ones are received the sixth bit is inspected and deleted from the data stream if it is a zero The se
16. Oct 20 1987 Sheet 14 of 16 4 701 845 Se a 56 881 83151939 1530038 LANYY SINT pt INT PRIOR ART 83 10538 ALIYOIYd 820 212 INTERNAL BUS Y Hm INTA INTERRUPT MASK REGISTER IMR YSI 83151938 391 935 NI 834304 01901 sng JIWA 431108 b VIVO 10252 1 cic gt lt lt gt 810 I CAS 0 CAS CAS 2 SP CC al 5 C10 400 195 uS J 10 20 I8 H3 T IO8LINOO 1d08334NI ALTMOTSd AVSSVIO o0 9 2 553400 lt isma KY Qoi wo 110 er MM 845 Sheet 15 of 16 4 701 AT 913 11001 83151938 5115 009911 110 I 410 26 T 96 88151938 d0H d1 T9 dd oe e SINIOd 109109 dri 2 6 1041802 1 1 15818 5534800 7 91901 NOLLIONO 3NIH39VN 111 26 2018 dGH T DIA 6904 U S Patent Oct 20 1987 Sheet 16 of 16 4 701 845 U S Patent Oct 20 1987 wi i fs 46 5 aCe 616 Cig 96 v 26 ye NO 110 ese 83151934 1 3938 1835 110 616 431108 553400 sna 553800 0011 I u 6 0 uoSS390Hd OYIN
17. Sheet 8 of 16 4 701 845 FIG 3A PRIOR ART SCC DATA PATHS CPU MO 230 kan CORT INTERNAL DATA BUS 210 260 UPPER BYTE TIME CONSTANT LOWER BITE TIME CONSTANT te Lem 16817 DOWN T COUNTER DR GENERATOR OUTPUT 232 lt P HUNT MODE SISYNC 280 28 SYNC REGISTER AND a DELETE 246 RESULT INTERNAL TXD CRC CHECKER MUX 270 27 S NRZIDECODEP FIG FIC 38 8BITS SDLC CRC 216 U S Patent Oct 20 1987 Sheet9 of 16 4 701 845 FIG 3B PRIOR ART 212 OTHER 736 CHANNEL NTERNAL TxD 246 z BIT i EV REGISTER 2 START RENE um 256 LOGIC FINAL Tx MUX 288 ENCODE ZERO INSERT 5 BITS CRC GENERATOR TRANSMIT CLOCK 290 ia GENERATOR OUTPUT LL OUTPUT RECEIVE CLOCK TRANSMIT CLOCK DPLL CLOCK DR GENERATOR CLOCK 200 c CLOCK MUX Sheet 10 of 16 4 701 845 VIVO 4 0 431515 VLVO AVG 30 VIVO 39NVN31NIVW 310438 00d SW300N U S Patent Oct 20 1987 c c 2 0 1 9 1804 r 0 1 V 1909 2o vue hain JIN 60b LUV OMA 01901 1081502 WNHUJ3INI 006 SINANI 10818409 JOWUJINI fld JOWUJINI Sf shg 553400 1081402 JdNYYJINI WVYOVIG 42018 a
18. can also be modified to indicate various status conditions Thus up to eight possible interrupt routines can be refer enced Transmit receive and external status interrupts are the sources of these interrupts Each interrupt source is enabled under program control with channel A of FIG 2 having a higher priority than channel B and with the receive transmit and external status interrupts being prioritized within each of the channels SCC Baud Rate Generator The baud rate generator for each channel A and B is shown in FIG 2 as 210 for channel and as 2105 for channel B Thus each channel contains its own pro grammable baud rate generator Each generator con sists of two eight bit time constant registers forming a 16 bit time constant a 16 bit down counter and a flip flop on the output that ensures a squarewave output This baud generator uses a four megahertz clock de rived from the eight megahertz processor clock in order to drive the baud rate generator Loading the time con stant register causes the counter to toggle at the speci fied X1 X16 X32 or X64 baud rates Digital Phase Lock and Loop DPLL Referring to FIGS 3A 3B the serial communication controller 200 is shown to have a DPLL unit 271 which can be used to receive clock information from a data stream with NRZI FM encoding NRZI is return to zero inverted while is frequency mod ulation The DPLL 271 of FIG 3A is driven b
19. here is composed of the following items The main central processor which includes data cards and control cards The memory control unit MCU The host dependent port HDP The data link processors DLPs The maintenance subsystem which is basically the maintenance and initialization subsystem of this dis closed computer network is comprised of the following items The User Interface Processor 100 The processor interface card PIC The power control card PCC DIAGNOSTIC REQUIREMENTS In order for diagnostic routines to occur in the de scribed computer system network there are certain parameters and requirements which are involved These are 4 701 845 23 a All diagnostic tests must run both locally and re motely and they must appear in the same format and accept the same commands b The diagnostic testing must isolate any system fail ures down to or at the level c The diagnostic testing must be usable both to sup port engineering debug to support the customer s sites and for test engineering INITIALIZATION REQUIREMENTS The following elements are required for initialization of the disclosed computer network a The initialization of the system can be accomplished either from the local site and or the remote site b Initialization of a system can be possible without operator intervention of any sort that is to say the operator at the local site c Structural failures in
20. number to be used The maintenance I O configuration will be displayed on the console to show the operator the set of units found on the last attempt to find or to access the BOOT CODE file If the correct unit does not appear in the table then it is likely that there are problems in the I O subsystem 500 of FIG 1B If the unit is in the table but the BOOT CODE file is not found on the specifying unit it is then likely that a BOOT CODE file was never created on that particular unit Another possibility is that the disk in question has been damaged or corrupted and the operator should then specify a backup unit if one exists or else he should 4 701 845 21 load the software from the BOOT CODE tape which is also supplied in the described computer network Sys tem If the backup BOOT unit exists it may be specified as the next unit to try However if no BOOT unit has been found it is then not useful to attempt one of the units already displayed in the I O configuration table since that list would have already been searched It is necessary to make sure that the expected BOOT unit is operable and if not to take action to bring the BOOT unit to an operable state after which the Operator should retry the operation by specifying the unit num ber It is possible that a BOOT CODE unit may be located but that parity errors are encountered while loading the software When that situation occurs the operator will be instructed to s
21. provide a unified approach an interface to the diagnostics an executive program called the TEST RUNNER will control the execution the interface and error logging of all of the off line diagnos tics The TEST RUNNER is a simple menu driven program which gives unambiguous details of failures at the board level and is designed to complement the over all maintenance philosophy of resolving problems to units which can be replaced There are two modes of operation for the TEST RUNNER First there is the automatic mode which is involved during the system initialization sequence and which runs a subset of the diagnostics Any critical failure detected during this mode will take the system out of automatic and put into manual initialization mode where diagnostics can be run to verify or further isolate the problem Any non critical failure detected example memory module other than a module or data link processor which is not required for initializa tion will be flagged to the operator but will now allow initialization to be continued 4 701 845 27 Secondly there is the MANUAL or INTERAC TIVE MODE This mode can be entered during system initialization or it will be entered as a result of a critical failure during the automatic mode This mode allows the specification of which diagnostics are to be run and it also allows the use of hardware software screens and event history logic in order to trap and or examine the s
22. these drawings the User Interface Proces sor is connected to all the various elements of the com puter system network that is to say it connects to the processor interface card and the main host processor on the one hand and on the other hand it connects to the power control card the maintenance card III the oper ator display terminals and the various data link proqes sors 4 701 845 3 Thus these combinations of elements connected to the User Interface Processor 100 provide the basic op erational and maintenance functions for the computer network For example the User Interface Processor 100 will initialize and power up the entire computer net work system It will initiate self testing procedures whereby each of the interconnected data link proces sors will do their own self test do a check out routine and send the results back to the User Interface Proces sor Additionally the User Interface Processor will connect to the power control card in order to provide maintenance and diagnostic information and data to a remote unit which can then provide further diagnostics which will determine the location of any faulty areas in the system Further the User Interface Processor will initiate its own self testing routines to make sure that it itself is in proper operating condition and it will display the results on the operator display terminal Processor Interface Card PIC The processor interface card 40 FIGS 1A
23. RAM controller chip of which the preferred element is the National DP 8409 This chip is described at pages 350 391 in a publi cation entitled NS 16000 Data Book 1983 and pub lished by the National Semiconductor Corp 2900 Semiconductor Drive Santa Clara Ca 95051 This chip provides all the necessary multiplexing of the row and column addresses drivers and the refresh logic Since this chip is operated in its fastest mode there is no wait state required A refresh request is requested every 1 6 microseconds by a refresh counter which in turn requests a 8086 hold sequence in micro processor 110 to occur Once the sequence is granted the RAM controller chip DP 8409 accesses one row of RAM 150 thus refreshing it The duration of this access equals that of a micro processor memory access cycle thereby reducing the refresh overhead time to a minimum With this type of configuration the memory band width is 3 83 mega bytes per second The memory is refreshed also during a reset of the microprocessor 110 thus preventing destruction of the memory contents Error detection in the RAM array 150 is accom plished by vertical byte parity via circuit 160 FIG 1 2 Thus each 16 bit word of RAM 150 has two parity bits one for each byte Whenever a word or a byte of a dynamic RAM is accessed the parity is checked for each byte regardless of whether the operation is a word cycle or a byte memory cycle When such an error Occ
24. United States Patent ro Andreasen et al 54 USER INTERFACE PROCESSOR FOR COMPUTER NETWORK WITH MAINTENANCE AND PROGRAMMABLE INTERRUPT CAPABILITY David Andreasen Newtown Square Pa Jerrold E Buggert San Juan Capistrano Calif Harshad Desai Mission Viejo Calif Zubair Hussain Sunnyvale Calif 75 Inventors 73 Assignee Unisys Corporation Detroit Mich 21 Appl No 664 896 22 Filed Oct 25 1984 51 Int G06F 11 22 GO6F 13 34 521 iim 364 200 371 18 58 Field of Search 364 200 MS File 900 MS File 371 16 18 56 References Cited U S PATENT DOCUMENTS 3 838 260 9 1974 Nelson 371 16 4 030 075 6 1977 Barlow 364 200 4 091 455 5 1978 Woods 364 200 4 275 440 6 1981 Adams 364 200 4 334 307 6 1982 Bourgeois 364 200 4 630 224 12 1986 Sollman pur 364 550 OTHER PUBLICATIONS Intel Microprocessor and Peripherals Handbook 1983 pp 3 1 to 3 11 3 22 3 24 1984 Series 32000 Databook National Semiconductor 4 701 845 Oct 20 1987 1 Patent Number 45 Date of Patent Corp pp 338 353 Published by National Semicon ductor Corp Santa Clara CA Counter Firmware Technical Manual Published by Zilog Campbell CA 95008 Mar 1982 pp 259 273 281 298 Microprocessors and Microcomputer Development Systems by Mohamed Rafiquzzaman pp 388 395 MCS 80
25. ance subsystem which includes the User Interface Processor 100 the processor interface card 40 and the power control card 50 E MODE STAND ALONE DIAGNOSTICS LEVEL 3 The E mode stand alone diagnostics are NEWP New Programming Language compiled E mode pro grams that run on top of the normal system microcode The E mode involves Burroughs stack architecture and is described in a paper entitled E Machine Workbench by G Wagnor and J W Maine published by ACM Association for Computing Machinery in the proceedings of the 16th annual workshop on Micropro gramming Oct 11 14 1983 They are used to obtain a higher level of confidence in the main frame hardware by arranging for the testing of the following a the interaction between sub modules in a controlled E mode environment b the interaction between microcode and hardware c the system and I O interfaces not covered in the lower level tests These level 3 tests fall into two groups the proces sor group and the I O group The processor group tests are designed to test E mode OPs in an environment where the complexities of the master control program are not involved Standard test cases are provided that run OPs in singles pairs and triples There is also the option to generate test cases using a patched NEWP compiler in order to enable a few engineers to take a failing code from the master control processor environment and run it in a diagnostic e
26. and information to a maintenance processor called the User Interface Processor 100 This processor works in conjunction with the various remote terminals and the various types of peripheral devices through an I O subsystem which is uniquely designed to handle units called data link processors These types of data link processing units were described in their earlier versions in U S Pat Nos 4 415 986 4 392 207 4 313 162 4 390 964 and 4 386 415 The maintenance subsystem involved herein is so interconnected to the various elements of the system that self test data may be collected and transported to a remote diagnostic unit which may be a central diagnos tic unit for many many computer networks in many different locations The remote terminal will perform the basic diagnostic routines to any of the computer networks which have problems and will send messages which pinpoint the specific cause or location of the trouble so that a local operator may correct the fault by changing a card replacing a module or fixing any other designated fault or outness SUMMARY OF THE INVENTION The User Interface Processor of the present disclo sure is a specialized processor known as a maintenance processor which supports a computer system network which involves a central processing unit connected to many remote peripherals through data link processors and other remote terminals via telephone lines The User Interface Processor or maintenance p
27. and to the interrupt request register 828 to provide outputs to the internal bus 212 and also to the control logic 820 The control logic 820 provides out puts to the read write logic 812 and to the cascade buffer comparator 814 The counter timer input output unit CIO 400 and the serial communication controller SCC 200 require a separate interrupt acknowledge term for each of the units Since the microprocessor 110 8086 drives a common interrupt acknowledge INTA there was provided means to implement a method of decoding separate acknowledge signals The PRITC 800 interrupt controller is programmed to see the CIO 400 and the SCC 200 interrupts as though they were interrupts from another interrupt controller device called mode This causes the PRITC 800 interrupt controller to output a three bit field CASO CAS2 FIG 8 which is unique for each interrupt level programmed as a slave interrupt These three outputs are decoded and are used as the separate interrupt acknowledge required by the SCC 200 and the CIO 400 units This permits full utilization of the interrupt vectoring capabilities of the SCC and the CIO chips The three mentioned cascade outputs CASO CASI CASA which exit from the cascade buffer 814 of FIG 8 are also driven to the foreplane FP to allow for another external interrupt control chip to be used which can thus increase the amount of interrupts to fifteen types of interrup
28. ation table can be built The computer system network disclosed herein may have several UIO universal input output bases One base includes all of the data link processors and the peripherals on the data link interface A separate base may also be configured on the message level interface MLI port on the HDP 500 as seen in FIGS 1B and 1C The UIP 100 cannot communicate directly with the peripherals on the message level interface Thus the software programs and the files that are used by the UIP 100 to perform diagnostics and other maintenance func tions must reside on peripherals whose data link proces sors are on the data link interface The power up of the described computer system network is an automatic sequence of events that does not generally require operator intervention except in certain specific cases If the default path is not func tional for example a system disk is not operational then other means if bringing up the system are pro vided Several options that require operator interven tion here are as follows a operator intervention as required to perform a cold start or a cool start which requires loading an E mode program called Loader b operator intervention is required to determine the configuration of the I O system on the message link interface this also requires loading an E mode pro gram called Utiloader c using a Halt Load unit that is not the default halt load unit this requires interve
29. cess memory means for tempo rary storage of code for effecting initialization and maintenance routines a3 said plurality of serial communications con trollers providing serial data channels for data communication lines to a first set of external units said serial communications controllers operable for driving programmable interrupt vectors a4 said plurality of 1 O port means for bidirec tional parallel data transfer connections to sec ond set of external units at least one of said I O port means capable of pattern recognition and generation of an interrupt upon recognition of a specific pattern a5 programmable priority interrupt controller means connected to said microprocessor means for receiving and prioritizing interrupt signals from said serial comunications controllers and from said I O port means and from a plurality of programmable interval timers and including a5a means to output a vector data signal to said microprocessor means for selecting a service routine dependent on the source of said inter rupt signal a6 said plurality of programmable interval timers for receiving instruction data from said micro processor means and for providing programmed time interval signals to said priority interrupt controller means b a dual function controller means connected to said microprocessor means to said serial communica tions controllers to said I O port means and to said priority interrupt controller m
30. ch as failure to pow er up no response on the console unit operator display terminal or failure to resolve an operational problem which arises Here there is no diagnostic program which is readily available or there is more than one failure present The probability is high that the fault is in the core logic circuitry This type of failure cannot be verified from a remot service center Fault Type II These types of faults are detected at the time of sys tem initialization when a console message is displayed which specifies the logic card and fault Type II faults 20 25 30 45 55 60 65 24 are also detected when running diagnostic programs where the same console message is displayed The characteristics of this type of fault are structural failures stuck at 1 stuck at 0 or short circuits Correc tion of this type of problem merely requires replacing the card or cards called out on the Maintenance Dis play Console Fault Type III Type failures are detected by a high number of device failures reported in the maintenance log the failure of the master control program MCP to initial ize continuous dumps which are not cleared by a halt load and or an error message displayed by running internal diagnostic E mode diagnostics programs The characteristics of this fault type III are periph eral device failure or a memory unit failure and a failure which can be verified from a remote service c
31. ch code is located on the in built disk which connects to the User Interface Processor 100 by means of the data link interface line at 5d of FIG 1B If there is no BOOT CODE file which is available then one must be created for use Normally this file would be available and required software loaded in a few seconds after which the operator can recognize that the BOOT CODE file has been found by observing the messages that will appear briefly on the console display These messages will appear as follows BOOT DLP xx BOOT UNIT xxx Sector Address xxxxx When numbers appear for the BOOT DLP BOOT unit and sector address the unit containing the BOOT CODE file has thus then been selected In addition the status line at the bottom of the screen will indicate loading maintenance software FAILURE TO LOAD BOOT CODE Any failure to load the maintenance software will be displayed on the operator s display screen The status line at the bottom of the screen will indicate the cause of the failure and will make a request that the operator take some action Thus the possible causes of failure will may be displayed are a BOOT unit was not found b No BOOT CODE file was found on the input unit XXX c Input unit xxx was not ready As a result of this the operator will be instructed to specify a valid unit number The operator must then make sure that the appropriate unit is powered up and ready to go after which he can type in the unit
32. ch for and detect incoming bit or byte patterns which match a programmed bit or byte pattern and to establish a synchronization signal 7 The User Interface Processor of claim 1 wherein said microprocessor means can set each of said serial communication controllers to operate in a polling mode or an interrupt mode said microprocessor means in cluding a polling means to determine if said serial communi cation controller requires a receive data or trans 4 701 845 31 mit data operation and to execute said data transfer operation with no interrupts and b means to determine when receive or transmit operations are required in a serial communications controller by means of said interrupt signals 8 The User Interface Processor of claim 1 wherein each of said I O port means includes a two 8 bit parallel general purpose ports providing handshake data transfer operations to said second set of external units b one 4 bit parallel special purpose port for provid ing handshake lines for each of said two 8 bit gen eral purpose ports 9 The User Interface Processor of claim 8 wherein each of said I O port means includes a means to detect when an incoming data pattern matches a pre programmed pattern b means to signal an interrupt to said microproces sor means when said match occurs c polling means to determine if said serial communi cation controller requires a receive data or a trans mit data operatio
33. ddress is 901 Thompson Place P O Box 453 Sunnyvale Ca 94086 and the 2917A unit is described in Bipolar Microproces sor Logic and Interface Data Book which was pub lished by Advanced Micro Devices Inc in 1981 The output enable on to the DLI status bus FIG 9 is generated by the signal called CONNECT and the signal IOSND This control signal CONNECT and IOSND is gen erated in the request logic 913 The combination of CONNECT and a DLP request generates an output enable for the DLI buffers 922 thus allowing data to be driven on to the DLI data bus FIGS 1C and 9 from a connected data link processor DLP The micro processor 110 is also capable of sending DLP request as true as well as resetting it to false The latch enable to receive data from the DLI into the receive register 922 is controlled by the signal AF synchronized STIOL The clocking of data into the DLI send register is controlled by the DLI state ma chine 925 and 910 The use of the term PAL will be meant to indicate Programmable Array Logic DLI Burst Counter 916 The burst counter 916 of FIG 9B is implemented as a PAL programmed as an eight bit up counter It can be read and also loaded by the microprocessor 110 with the count enable generated by the DLI state machine 910 925 An overflow term designated BUFFUL is also generated by the burst counter 916 that causes a burst exit when the counter overflows 20 25
34. direct memory access to the UIP RAM array 150 Further the buffers which drive some signals on the foreplane are always enabled and they cannot be disabled by either the UIP microproces sor 110 or by the application dependent logic wwhich may be attached to the foreplane FP 2 FIG 1 2 There are a group of signals brought out to the fore plane connectors FP 2 of the User Interface Processor board In the signals the direction is indicated by B for bidirectional by I for input and by O for output The list of signals on the foreplane connectors is as follows Microprocessor Address Bus 20 bits Microprocessor Data Bus 16 bits B Interrupt Controller Cascade Bus 3 bits Microprocessor Control Signals BHE Byte High Enable RD Read Strobe WR Write Strobe M IO Memory IO DT R Data Transmit Receive ALE Address Latch Enable DEN Data Enable HLDA Hold Acknowledge INT Interrupt input to interrupt controller 1 INTA Interrupt Acknowledge RDY Ready wait enable I In FIG 9 as shown on two sheets as FIGS 9A and 9B a block diagram is shown of the DLI HDP control ler The term DLI represents Data Link Interface while the term represents Host Dependent Port The Data Link Interface DLI HDP Controller The DLI HDP controller 180 of FIG 1 is shown in more detail by the block structure indicated in FIG 9 The DLI controller provides an inter
35. e microprocessor system of 110 Vertical parity is checked when writing into the dual port RAM 920 from the DLI interface 922 and the actual DLI parity is written into the parity RAM 920 Vertical parity is read from the parity RAM when reading into the DLI send receive registers 922 A flip flop is used to store the parity checking result and used to produce the vertical parity error status signal VPERR to the microprocessor 110 VPERR is a sta tus input which may be read by microprocessor 110 Request Logic for DLP Request and emergency request logic is handled in the request PAL 913 The microprocessor 110 controls the sending and removing of the DLP request signal The request monitors the emergency request input from DLI FIG 1C to remove the UIP request when an emergency request is present from another data link processor on the DLI backplane FIG 1C The signal IOSND input output send is also gener ated by the request PAL 913 The signal IOSND is set automatically when the UIP 100 is requesting service and the signal CONNECT is true This situation occurs when the UIP 100 is returning a descriptor link to the host computer 30 FIG 1B The signal IOSND is also settable by the microprocessor 110 SYSTEM INITIALIZATION Reference to FIGS 1A 1B 1C and 1D will indicate the system network connections of the User Interface Processor UIP 100 and its relationship to the other units in the system network such as the process
36. eans said dual function controller providing an interface for data transfers via said data link transfer interface and including 1 means to execute data transfer operations as a master via said data link transfer interface to said data link processor said user interface processor operating to send commands to initiate a data link processor self test routine and b2 means to execute data transfer operations to said host computer as a slave of said data link interface said means to execute providing a spe cifically oriented message level interface proto col to continuously provide maintenance and or information data transfers between the user in terface processor and host computer
37. ented message level interface protocol to continuously provide main tenance and or information data transfers be tween the user interface processor and host com puter 2 The User Interface Processor of claim 1 wherein each of said serial communications controllers provides two independent serial full duplex data comm chan nels operable with both synchronous and asynchronous protocols 3 The User Interface Processor of claim 1 wherein each of said serial communications controller operates as a slave interrupt controlled device dependent on priority signals from said priority interrupt controller means 4 The User Interface Processor of claim 1 wherein each serial communication controller includes a transmitter section means including al means to program sync characters in a byte oriented mode a2 means to program a 6 bit or 8 bit sync charac ter for mono sync mode a3 means to program a 15 bit sync character in a bi sync mode a4 means to program for asynchronous data transmission 5 The User Interface Processor of claim 4 wherein each serial communications controller includes a receiver section means including al register means for buffering at least 3 bytes of incoming data in asynchronous synchronous mode a2 means for delaying at least 3 bits of serial data in a synchronous mode 6 The User Interface Processor of claim 5 wherein said receiver section means includes a means to sear
38. enter The corrective factors in this type of problem may involve the adjustment of peripheral devices or replace ment of logic cards or both Fault Type IV The examples of this type of fault are a system dump caused by a machine check or an event trap for captur ing data about a particular event The characteristics of this type of fault are a data dependent failure an intermittent hardware failure or software failure However these failures must be such that they can be verified from a remote support center This type of problem requires high skill for correction The problem can only be identified in a running system environment or by analysis of dumps TESTING LEVELS The diagnostic tests involved are divided into four levels where each is intended to deal with a particular fault type Generally the execution of a test case de pends on the successful execution of the preceding test case unless the tests are used to handle or cover com pletely independent logic Each test case is so arranged as to avoid the use of previously untested hardware BASIC BOARD TESTS AND SELF TESTS LEVEL 1 This type of test is used to gain a minimal level of structural and functional confidence in the hardware involved Its purpose is to verify the initialization path during system power up to serve as a confidence test during debug and later as a manufacturing test These tests use diagnostic codes running either on the UIP basic board tes
39. er Interface Processor 100 can use the serial communication controller 200 in two different ways These are i polled and ii interrupt Both of these require register manipulation during initialization and data transfer However when used in the interrupt mode the SCC 200 can be programmed to use its vec tored interrupt protocol for faster and more efficient data transfers SCC POLLING During a polling sequence the status of the Read register 211 or 2115 FIG 2 is examined in each chan nel This register indicates whether or not a receive or a transmit data transfer is needed and whether or not any special conditions exist This method of I O transfer avoids interrupts All interrupt functions must be disabled in order for a de vice to operate correctly With no interrupts enabled this mode of operation must initiate a Read cycle of the Read register 0 to detect an incoming character be fore jumping to a data handler routine 4 701 845 11 SCC Interrupts The serial communication controller 200 provides an interrupt capability similar to that of the PIC priority interrupt controller 800 of FIG 1 1 Through the use of this method an increase in throughput is realized Whenever the SCC interrupt is active then the SCC 200 is ready to transfer data The Read and Write registers of FIG 2 211 2115 are programmed so that an interrupt vector points to an interrupt service routine The interrupt vector
40. ers Automatic sync character insertion and deletion Cyclic redundancy check CRC generation detection 6 or 8 bit sync character 3 SDLC HDLC Capabilities of the SCC Abort sequence generation and checking Automatic zero insertion and deletion Automatic flag insertion between messages Address field recognition I field residue handling CRC generation detection SDL loop mode with EDP recognition loop entry and exit 4 Further SCC Capabilities NRZ NRZI also FM encoding Baud rate generator for each channel Digital phase locked loop for synchronous clock recov ery period SCC Register Functions All the modes of communication used are established by the bit values of the Write registers 236 238 FIG 3B As data is received or transmitted the Read register 2114 4 values change The values of these Read status registers can promote software action for further regis ter changes Referring to FIG 2 of the serial communication con troller 200 block diagram the register set 211 and 2115 for each channel B includes 14 Write registers and seven Read registers Ten of the Write registers are used for control two are used for sync character generation and two are used for Baud rate generation The remaining two Write registers are shared by both channels one is used as the interrupt vector and one is used as the master interrupt con trol Five Read registers indicate the status func tions and t
41. f and said host computer and between itself and said data link processors via a host dependent port HDP data link transfer interface said User Inter face Processor operating to initialize and power up said network and operating to initiate self testing procedures for purposes of confirming system integrity and locat ing any faults said user interface processor comprising a a microprocessor subsystem including al microprocessor means for executing instruc tions and maintenance data transfer operations said microprocessor means connected to mem ory means to a plurality of serial communication controllers to a plurality of I O port means and to a programmable priority interrupt controller a2 said memory means including a2a programmable read only memory means for storing firmware instruction data a2b random access memory means for tempo rary storage of code for effecting initialization and maintenance routines a3 said plurality of serial communications con trollers providing serial data channels for data communication lines to a first set of external units said serial communications controllers operable for driving programmable interrupt vectors a4 said plurality of I O port means for bidirec tional parallel data transfer connections to a sec ond set of external units at least one of said I O port means capable of pattern recognition and generation of an interrupt upon recognition of a specific pattern
42. face which consists of the clear and self test initiation logic the DLI send receive registers 922 a burst counter 916 a burst end logic 926 a longitudinal parity word LPW generator 923 vertical parity generation and routing request and emergency request logic and DLI micro processor communication logic A 24 bit state machine 925 and 910 with parity accepts the conditions from and controls these data elements The microprocessor 110 also accepts status from and provides control of portions of these ele ments FIG 9 also shows a block diagram of the DLI HDP interface A data bus 909 connects control store 910 HDP register 911 a DLP status send receive register 912 a DLP request address logic 913 data latches 914 host pointer 915 and burst counter 916 The control store 910 has outputs which provide signals to a condi tion selector 917 and to a parity check circuit 918 The data latches 914 have a data bus connection to the DLI send receive register 922 The host pointer 915 provides addresses to RAM 920 which is connected to a vertical parity generator checker 923 The microprocessor address bus 110a connects to an address buffer 919 and a device decoder 921 Clear Self Test Initiation The clear and self test initialization logic 112 FIG 1 detects when various types of clear signals and 4 701 845 17 self test signals are required Clear signals detected by the clear self test PAL 112 FIG 1
43. gnated as SYSTEM UTILOADER into the computer system This pro gram is loaded from the BOOT CODE file and this takes approximately 30 seconds Any failure to load the SYSTEM UITLOADER program may be due to I O problems with the BOOT unit or certain system problems In the event of a fail ure the cause of the problem will be displayed on the operator s console 100 Then the operator must take appropriate action by either restarting the power on sequence on a backup BOOT unit or by servicing the failing elements MAINTENANCE PHILOSOPHY Since the requirements for initialization and mainte nance in a computer system network are similar this similarity has been made use of in order to yield a par ticularly significant cost reduction by sharing the access interface hardware The sharing of the hardware for initialization and for maintenance allows the reporting of failures either locally or remotely and also permits initialization to occur with only a small functional set of circuitry A further advantage of this shared hardware is the high degree of visibility to all of the subsystems within the overall system network This direct visibility per mits excellent analysis for faults and for fault resolution The access and viability of the initialization and main tenance functions for the computer network system is provided through the use of the User Interface Proces sor 100 The particular computer network system disclosed
44. k diagram of the User Interface Pro cessor used in the maintenance system network FIG 1 is made up of two sheets labeled FIG 1 1 and FIG 1 2 FIGS 1A 1B 1 and 1D are system and network drawings showing how the User Interface Processor module connects to other elements of the system net work to provide a maintenance subsystem FIG 2 is a block diagram of the serial communica tions controller elements of the User Interface Proces sor FIG 3 is a block diagram showing the data paths involved in the serial communications controller FIG 3 is made up of two sheets designated as FIG 3A and FIG 3B FIG 4 is a block diagram of the communications input output unit elements of the User Interface Pro cessor FIG 5 is a block diagram showing the ports of the communication input output unit FIG 6 is a block diagram of the communications input output port designated as port C FIG 7 is a block diagram of the counter timers of the communications input output unit of FIG 4 FIG 8 is a block diagram of the priority interrupt controller PRITC of the User Interface Processor FIG 9 is a block diagram of the unit designated as the data link interface host dependent port FIG 9 is made up of two sheet labeled 9A and 9B GENERAL OVERVIEW The Maintenance Subsystem The maintenance subsystem of the computer network is organized around the User Interface Processor 100 which is shown in FIGS 1A 1B 1C and 1D As seen in
45. l data link processor for the system Up to two operator display terminals may be configured in any one computer system network THE DATE LINK INTERFACE The UIP 100 can communicate with data link proces sors via the data link interface shown in FIGS 1B 1C and 1D To the data link processor the UIP 100 com mands will look like commands sent by the host depen dent port 500 FIGS 1C and 1B that is to say the User Interface Processor 100 has the ability to control de vices connected on to the data link interface There are eight available addresses 0 7 for data link processors on the data link interface The UIP 100 occu pies the first address 0 on a data link interface A printer tape data link processor occupies one slot since it is a one card data link processor and because it is logically considered as two data link processors com municating with two types of peripheral devices A SMD DLP storage module disk data link proces sor occupies a fourth address on the data link interface This leaves four addresses available for expansion The User Interface Processor 100 can communicate with peripheral devices by sending 1 O descriptors to the data link processors and receiving back I O result descriptors from the data link processors In order to determine the system configuration the UIP 100 sends a Test I O operation to the peripheral devices on the data link interface From this information a data link interface configur
46. n and to execute said data transfer operation with no interrupts 4 means to determine when receive or transmit operations are required in said communication controllers by means of interrupt signals 10 The User Interface Processor of claim 1 wherein said programmable priority interrupt controller means includes d means to receive interrupt signals from said dual function controller 11 In a computer network having a host computer and plurality of input output 1 O subsystem con nected to periperal units via data link processors 1 O controllers a User Interface Processor for interfacing both said 1 O subsystem and said host computer via a data link transfer interface HDP said User Interface Processor operating to initialize and power up said network and operating to initiate self testing procedures for purposes of confirming system integrity and locat ing any faults said user interface processor comprising a a microprocessor subsystem including al microprocessor means for executing instruc tions and data transfer operations said micro processor means connected to memory means to a plurality of serial communication controllers to a plurality of I O port means and to a pro grammable priority interrupt controller a2 said memory means including 10 15 20 25 30 35 45 50 55 65 32 a2a programmable read only memory means for storing firmware instruction data a2b random ac
47. n the disk and thus the BOOT CODE tape may then be dismounted LOADING SYSTEM MICROCODE The next step is done automatically in the power on sequence This step is the loading of the computer sys tem microcode from the BOOT CODE file or from the tape depending on whether or not the system is being tape loaded The status line at the bottom of the operator s screen will indicate that state This loading will take approximately 30 seconds If the loading fails the reason will then be shown on the console of the display unit 100 If the failure is due to I O problems on the BOOT unit then the Operator should restart the system by specifying a backup BOOT unit if possible If the loading fails because of errors in the control store of the processor 30 memory into which the Sys wa 5 20 25 30 35 40 45 50 55 65 22 tem microcode is stored then the failing elements must be serviced SYSTEM CONFIDENCE TEST After the system microcode is loaded then confi dence test will be run on the computer network The tests take about 30 seconds each and indicate that the control store in the processor 30 is properly loaded and that the system processing elements are Operable The system is now ready to BOOT the master control pro gram INITIALIZING THE OPERATING SYSTEM At this point the maintenance subsystem has one more task left to perform in the power up sequence Here it must load a program desi
48. n in FIG 7 each counter timer connects to the internal data bus 212 and has two time constant regis ters 710 and 711 which connect a 16 bit down counter 715 having outputs to the current count registers 720 and 721 In addition there is a counter timer control logic unit 712 which has input lines from a port and which connects to the internal bus 212 Interrupt Control Logic For CIO Counter Timer Input Output Unit The microprocessor 110 of FIG 1 1 can receive interrupt signals from the CIO 400 FIG 4 interrupt control logic 222 The interrupt control logic of the CIO 400 provides for five registers not shown which are 20 25 30 35 40 45 50 55 65 14 i the master interrupt control register ii the current vector register iii iv and v the three interrupt vector registers associated with the interrupt logic In addition each port and counter timer command and status register includes three bits associated with the interrupt logic these are the interrupt pending the interrupt under service and the interrupt en able One interrupt per counter timer input output unit drives a priority interrupt controller 800 FIG 1 input with the interrupt controller programmed to rec ognize the CIO 400 as a slave interrupt controller Simi lar to operation of the SCC 200 this implementation allows the full use of the CIO 400 interrupt vector capa bilities Programmable Interval Timers
49. nd it permits perfor mance monitoring so that a trap can be set to count the number of failure occurrences The PIC 40 supplies a communication path AULF register CSCP operator so that the main system processor 30 can communicate to the UIP 100 for maintenance information on power off time of day reload etc In FIG the memory bus 30 connects the main processor 30 to the memory control unit MCU 32 and to the UIP 100 Also attached to memory bus 30 is the host depen dent port 500 HDP which provides a DLI data link interface bus 5 to the I O subsystem 500 and mes sage level interface MLI bus 5 to the I O expansion module 500 which connects to peripheral devices FIG 1C shows in greater detail the UIP 100 con nections to the HDP 500 and to the processor interface card PIC 40 which interconnect the main processor 30 and the HDP 500 FIG 1D shows how the UIP 100 connects to the processor interface card 40 and main processor 30 on one side and to the I O data link processor 1002 to maintenance card 100 and to ODT 100 and remote link 50 The acronym ODT refers to operator dis play terminal The User Interface Processor 100 FIG 1 is desig nated with the acronym UIP The User Interface Processor consists of one logic board which can inter face to a data link interface DLI backplane and also to four independent serial data communications interfaces Under certain software instructi
50. nterface Processor 100 also provides the link to the local terminals for maintenance and for oper ative display terminal 100 functions Additionally the User Interface Processor 100 provides the Test Bus function via the Burroughs direct interface BDI shown in FIG 1B and FIG 1D The UIP 100 has the ability to communicate with peripherals in order to provide system maintenance to load the operator microcode into RAM to perform diagnostics to enable remote maintenance and to pro vide for Halt Load The software programs which do this reside on peripheral devices whose data link proces sors are connected on the data link interface that is system maintenance programs that are used by the User Interface Processor 100 MAINTENANCE TERMINAL AND OPERATOR DISPLAY TERMINAL FUNCTIONS The UIP communicates with terminals via a TDI link Terminal Direct Interface These terminals provide the separate windows to the computer system network One window occurs when the system is in the mainte nance mode and the terminal is a maintenance display terminal MDT In this mode the user may access state may perform system diagnostics and perform other low level functions The other window occurs 5 20 25 30 40 45 50 65 28 when the system is under master control program MCP control The terminal then is 2 ODT or operator display terminal The UIP 100 provides the function of the operator display termina
51. nterrupt acknowledge signal The use in FIG 1 1 of the priority interrupt PRITC 800 controller s cascade output allows the SCC 200 to be operable as a slave interrupt controller This usage allows implementation of the SCC 200 vec tored interrupt capability While the serial communica tion controller chip has an interrupt priority option it is not used in the User Interface Processor since this function is allowed for in the interrupt control logic device 222 of FIG 2 By using two of the serial communication controller chips this results in a total of four serial data communi 0 _ 5 25 30 35 45 50 35 60 65 8 cation lines shown in FIG 1 1 as lines 1 and 2 and lines 3 and 4 These four lines are interfaced over to two external four plane connectors which allow the use of existing data communication paddle cards in order to provide the electrical interfaces for use with interfaces such as the RS 232C or the TDI and so on The serial communication controller 200 has certain capabilities which will be described hereinbelow 1 Asynchronous Capabilities of SCC 5 6 7 or 8 bits per character 1 1 3 or 2 stop bits Odd or even parity Times 1 16 32 or 64 clock modes Break generation and detection Parity overrun and framing error detection 2 Byte Oriented Synchronous Capabilities of the SCC Internal or external character synchronization 1 or 2 sync characters in separate regist
52. ntion on part of the operator as does the loading of alternate operator microcode It may be noted that both the Utiloader and the Loader must reside on the peripheral devices which are connected to the data link interface 4 701 845 29 USER INTERFACE PROCESSOR DIAGNOSTIC CAPABILITY The UIP 100 has provision for some diagnostic capa bilities for the I O subsystem The UIP 100 can deter mine the configuration on the data link interface thus to provide a basic interface test In addition the UIP 100 can initiate self test on the storage module disk and the printer tape data link processors Finally the UIP performs tests on other data link processors that are part of the system configuration via the Burroughs direct interface BDI that is the test bus function The UIP 100 via the PCC 40 also provides the link to the remote support center 50 for remote diagnostics While a preferred embodiment of the User Interface Processor and its maintenance subsystem has been de scribed other equivalent embodiments may be devel oped within the concepts of this disclosure which are hereinafter defined by the following claims What is claimed is 1 Ina computer network having a host computer and input output I O subsystem connected to peripheral units via data link processors 1 0 controllers a User Interface Processor for support and maintenance opera tions and for dual functional operations in data trans fers between itsel
53. nvironment using the computer network features of event and history logic in order to aid the diagnosis as well as using the extensive debug features which are brought into this particular program The 1 0 group are diagnostic which are designed to test the complete path from the E mode through the processor 30 and the host dependent port 500 mi crocode hardware the message level interface data link interface MLI DLI and the data link processors to the peripheral itself This is in a relatively simple controlled environment which can use the event and history logic and the extensive debug features of these programs INTERACTIVE TESTS LEVEL 4 The level 4 tests are used to find failures which only occur in a system environment After the computer main frame 30 is verified to be functioning properly the master control program can drive the interactive tests PTD and SYSTESTS in order to further diagnose the 20 25 30 35 40 45 50 55 60 65 26 problem in a master control program environment Further the event and history logic can also be used to trap failures that only occur while running the system or while running the application software DIAGNOSTIC RESOLUTION AND ERROR HANDLING When there is an occurrence of an error the diagnos tic system will provide error messages indicating which boards have malfunctioned At the basic board or at the interactive level the hardware is tes
54. of port 409 which are not used as hand shake lines can be used as input output lines or as external access lines to the counter timer 3 403 of FIG 4 Since the port C s function is defined primarily by ports A and B in addition to the internal input data and output data registers which are similarly accessed as in ports A and B here only the three bit path registers are needed that is the data path polarity register the data direction register and the special I O control register not shown Counter Timers Input Output Unit In FIG 4 the three counter timers 401 402 403 in the CIO 400 are all identical type units Each is made of a 16 bit down counter a 16 bit time constant register which holds the value loaded into the down counter a 16 bit current count register which is used to read the contents of the down counter and two eight bit regis ters for control and status that is the mode specifica tion and the counter timer command and status regis ters Up to four port pins counter input gate input trigger input and counter timer output can be used as dedicated external access lines for each counter timer FIG 4 There are three different counter timer out put duty cycles which are available These are i pulse duty cycle ii one shot duty cycle and iii a square wave duty cycle The operation of the counter timers can be programmed as either retriggerable or as non retriggerable As see
55. ond with FM frequency modulation encoding and they can provide up to 125k bits per second with NRZI non return to zero inverted encoding The SCC chip includes two receiver sections 232 234 FIGS 3A and 3B having a three byte FIFO first in first out register that allows buffering of four bytes including the receive data register of data in the re ceive mode The transmitter section incorporates a single holding register as well as a transmitter data register FIG 2 shows the typical internal features of the Zilog Z8530 SCC serial communication controller 200 There are two channels channel A 215 and channel B 215 which connect to remote terminals on serial data lines The control signals for these channels are designated as discrete control and status for channel 2174 and for channel B 217 An internal bus 212 connects these channels and control units to the Baud rate generator A 210 and also to the Baud rate generator B 2105 The internal bus 212 also connects the channel A registers 211 and the channel B registers 211 together with further connections to internal control logic 220 and interrupt control logic 222 which then connect to the CPU bus input output unit 224 The serial communication controller 200 is an opera ble part of the User Interface Processor 100 for use as an interrupt control device It is capable of driving a programmable interrupt vector in response to a micro processor i
56. ons the User Inter face Processor 100 can operate as a data link processor DLP and in so doing will support a burst rate of up to eight megabytes per second It can also be used as a host dependent port HDP where it will support a burst rate of 50 kilobytes per second Thus the same card of hard ware can be made to assume different personalities and functions as required The User Interface Processor 100 operates on a main tenance philosophy whereby cards in a computer sys tem as FIG 1A can be isolated and replaced A combi nation of self test and peripheral test driver tests PTD are used to isolate any failure to a replaceable module This is done by indicating to the operator via operator display terminal ODT 100 the identity of a failing board after the completion of the self test Thus the User Interface Processor 100 is basically a microcomputer system which is placed on a single printed circuit board It includes a number of key com ponents as follows a a 16 bit central processing unit 110 FIG 1 b 192 kilobytes of PROM 170 FIG 1 c up to one half megabytes of RAM 1504 of FIG 1 4 701 845 5 d programmable input output ports 2022 2025 e serial data communication ports 200 2005 f a priority interrupt controller PRITC 800 g programmable timers PIT 700 h DLI HDP controller 180 DLI Data Link Interface i a DLI host dependent port HDP 500 of
57. or inter face card 40 the operator display terminal 100 the power control card 50 and power modules 50 the modem 50 and the remote support center 50 all of which are indicated in FIG 1A 4 701 845 19 In FIG 1B there is seen further relationships of the User Interface Processor 100 to the host dependent port 500 and the I O subsystem 500 and the expansion 1 0 base 500 and additionally the connections to the main processor 30 the memory bus 30 and the mem ory control unit 32 and memory storage cards 34 FIG 1C shows further interconnective relationships of the User Interface Processor 100 to the processor interface card 40 the main host processor 30 the mem ory control unit 32 and the host dependent port 500 FIG 1D shows the interface relationships of the User Interface Processor 100 in relationship to the processor interface card 40 and the main host processor 30 and additionally the relationship to the group of data link processors 1002 to the maintenance card 100m to the local terminals 100 and to the power control card 50 and remote support link 50 The User Interface Processor 100 plays a significant part in the operation and especially the initialization of the system network The computer network system shown in FIGS 1A 1B 1C 1D will power on and initialize in approxi mately three minutes When the hardware and software are properly installed in the system then no operator intervention i
58. output buffer inverters 418 The output buffer inverters 418 can provide an output to the input buffer inverters 422 which can provide their outputs to the data multiplexor 420 or to the counter timers 1 and 2 of port B 408 FIG 4 The port control logic 413 of FIG 5 can provide internal port control or 4 701 845 13 hand shake control while communicating with the in ternal data bus 212 For each port the primary control and status bits are grouped in a single register called the command and Status register Once the port has been programmed this is the only register that is accessed for the most part To facilitate initialization the port control logic 413 is designed so that registers associated with a non needed or unrequired capability are ignored and do not have to be programmed The block diagram of FIG 5 is illus trative of the port configuration which is used and it applies both to port A and port B 407 and 408 FIG 4 Port C 409 of FIG 6 In FIG 6 there is included a special purpose four bit register residing in port C 409 FIG 4 The function of this register depends upon the functions of ports A 407 and B 408 Port C 409 provides the hand shake lines when required by the other two ports A request wait line can also be provided by port C 409 so that transfers by ports A 407 and B 408 can be synchronized with direct memory access units or cen tral processing units CPU 30 FIG 1B Any bits
59. pecify another BOOT unit Thus a backup unit should be specified if there is one in exis tence and available If the software loading consistently fails due to errors in the maintenance subsystem memory the system must be serviced to replace the failing elements before the power on sequence can be successfully completed TAPE LOADING MAINTENANCE SUBSYSTEM SOFTWARE This procedure for tape loading the maintenance software is necessary only in the event of a catastrophic loss of the BOOT unit for example a head crash or if the computer system has never had its BOOT unit ini tialized If no BOOT code file is available the maintenance subsystem must be tape loaded This procedure is done by first mounting the BOOT CODE tape ona tape unit visible to the maintenance subsystem and then to specify this unit as the BOOT unit the screen on the operator s console 100 should then be waiting on the operator to specify it The maintenance subsystem will then operate off of the tape unit rather than the disk unit The tape unit must remain mounted throughout the initialization se quence in order to allow subsequent files to be read When the MCP master control program operating system is finally up and running the operator must create a BOOT CODE file on an in built disk and again he must initiate the switch for power off power on for the system The next and all subsequent uses of power on will find and use the BOOT CODE file o
60. re i the input data register 411 ii the output data regis ter 410 iii and the buffer register 415 The output data register 410 is accessed by writing to the port data register while the input data register is accessed by reading the port data register Two regis ters the mode specification register and the hand shake specification register are used to define the mode of the port and to specify which type of hand shake if any is to be used In ports A and B the reference pattern for the pat tern recognition logic is specified by the contents of three registers not shown which are designated as i the pattern polarity register ii the pattern transition register and iii the pattern mask register The detailed characteristics of each bit path for example the direc tion of data flow or whether a path is inverting or is non inverting are progr mmed using the data path polarity register the data direction register and a spe cial I O control register Referring to FIG 5 there is seen a block diagram of certain details of each of the counter timer input output CIO ports A and B In FIG 5 there is seen an output data register 410 and an input data register 411 con nected to the internal data bus 212 The output data register 410 connects to a data multiplexor 420 which feeds a buffer register 415 having an output which can be conveyed to pattern recognition logic 412 or to input data register 411 or to the
61. ro cessor provides an interface to the central host pro cessing unit and to various elements of the network such as the data link processors which connect to re mote peripherals to the operator display terminal which provides visual information and diagnostic infor 15 25 30 35 40 45 50 55 65 2 mation to external cabinets and to power control card which enables connection to a remote support center for comprehensive diagnostic and fault location ser vices The User Interface Processor connects to the central host processing unit through a processor interface card and to various peripherals and terminals through a data link interface host dependent port controller A set of serial communication controllers and com munication input output units work together with a set of timers and a priority interrupt controller in order to communicate with the main host processor both for normal operational purposes and also for maintenance and diagnostic services Each one of a series of local computer networks may be locally checked on self testing procedures and then connected to a remote support center for comprehen sive diagnostics in order to locate specific problems within any given computer network system Many dif ferently located computer system networks may be connected to one remote support center which can service them all on a time shared basis BRIEF DESCRIPTION OF THE DRAWINGS FIG 1 is a bloc
62. s i a microcomputer subsystem 110 ii a data link interface controller 180 iii a host dependent port controller 180 These three units allow the User Interface Processor to communicate with the host computer 30 32 34 FIG 1B via the DLI controller 180 FIG 1 and also with other data link processors 1004 FIG 1D that are connected to the I O backplane via the host dependent port 500 of FIG 1B The UIP 100 has certain communication restrictions in this regard The host dependent port 500 is a DLI Data Link Interface controller 180 and as such does not provide a MLI Message Level Interface but merely provides a backplane DLI interface In this regard it cannot be used with a distribution card path selection module or base control card as was done in the organization of data link processors which were described in the cited U S Pat Nos 4 313 162 and 4 390 964 since it provides these functions for itself in firmware This particular host dependent port 180 FIG 1 must be used in a base that provides an eight megahertz clock such as that provided from the main tenance card 100 of FIG 1D MICROPROCESSOR SUBSYSTEM The microcomputer subsystem includes both serial and parallel interfaces that are used to perform data communication operations The microprocessor subsystem consists of certain elements as follows 1 a microprocessor 110 such as Intel 8086 35 40 45 50 55 65 6
63. s required during the power on se quence The operational functioning of this sequence and ways for handling exception conditions that may occur are discussed hereinbelow POWER ON There is a power button located in the upper left hand corner of the computer cabinet whereby pressing of this button will initiate either the power on or the pow er off sequence depending on the current state of the system The power on button will connect power to the system s main processor 30 and also to disk system units which are built into the cabinet It is required that there be at least one operable in built disk for the pow er on sequence to be completed successfully After power is successfully established the UIP maintenance subsystem will be in control of the system network in order to handle the next phase of the pow er up sequence COMPUTER MAINTENANCE SUBSYSTEM SELF TEST The computer maintenance subsystem will first per form a self test in order to verify that its own process ing elements and memory are operable Thus in FIG 1A a self test procedure will be generated to verify the microprocessor 110 the timers 700 the memories EPROM 170 and the DRAM 150 and also the DLI HDP controller 180 This self test will take only a few seconds and if the self test routine successfully passes all of the participating units then there will be displayed a greeting at the operator s display terminal console 100 FIG 1A
64. ted in separate building blocks with the testing of one block depending on the successful test completion of a preceding block Thus the diagnostic test will terminate upon the occurrence of an error within the module under test but it will continue to run tests on other modules providing that they are not de pendent on the previous test in order to further diag nose failures in areas such as the M bus or the control bus that can potentially affect more than one module Upon the occurrence of a recoverable error for ex ample data miscompares in a pattern sensitivity test the diagnostic tests will log all information relating to an error when it occurs and will continue until completion DIAGNOSTIC GRADING The diagnostics are graded by running against a list of faults which can be generated by DDRIVE program for generating test cases The number of faults detected by the diagnostic tests can be used to determine the percentage of testing necessary MAINTENANCE INTERFACES There are six maintenance interfaces which will be discussed as follows TEST RUNNER interfaced to maintenance soft ware b Computer system main frame diagnostic interface Computer system 1 diagnostic interface d Maintenance terminal and operator display terminal functions e The data link interface DLI interface d User Interface Processor diagnostic capabilities TEST RUNNER INTERFACE TO MAINTENANCE SOFTWARE In order to
65. terconnections and line faults during initialization can be detected before detection can be made of the violation of machine integrity DIAGNOSTIC TEST OPERATIONS The diagnostic program involved in this system has two main functions first to serve as a confidence test on any well defined subsystem and second to resolve any failures detected by the confidence routine to the loca tion of a specific card unit SELF TEST All subsystems which have a microprocessor must be able to perform self test For those units which do not have a microprocessor the diagnostic access hardware for the self test is provided on each printed circuit board Self test is accomplished by connecting with the User Interface Processor 100 which provides the intelli gence to drive the test via the processor interface card 40 SYSTEM TEST These tests are developed as diagnostic tests which provide means for dynamic testing at the system level This dynamic testing incorporates the event analyzer of the processor interface card 40 and the history file of the processor interface card 40 FAULT TYPES The fault types to be detected in this system are cate gorized by the level of the test required to detect the fault the level of skill required to correct the fault and the time at which the fault is detected There are four fault types which are considered for detection in the computer system network Fault Type I These types of faults are faults su
66. tes an interrupt upon recognition of a specific pattern at a port As seen in FIG 4 there are three I O ports provided by the counter input output device Port A 407 and port B 408 are eight bit general purpose ports while port C 409 is a four bit special purpose port Two port configurations are available and are designated as i bit port and ii port with hand shake All three of these ports can be programmed as bit ports however only ports A and B are capable of operation as hand shake ports Ports A 407 and B 408 These are the two general purpose eight bit ports which are identical except that port B 408 can be pro grammed to provide external access to the counter timers 1 401 and 2 402 of FIG 4 Either port can be programmed to be hand shake driven as a single double buffered port input output or bidirectional or as a control port with the direction of each bit indi vidually programmable Both ports A and B FIG 5 include pattern recogni tion logic 412 which allows interrupt generation when a specific pattern is detected The pattern recognition logic 412 can be programmed to make the port function like a priority interrupt controller The ports A and B can also be linked to a 16 bit input output port with hand shake capability Each of these ports has 12 control and status regis ters which control these capabilities The data path of each port is made of three internal registers which a
67. to the CRC cyclic redundancy checker generator 250 as well as to the transmit multiplexor 252 at the X1 clock rate It should be understood that SDLC means synchro nous data link control while HDLC is the European version The SDLC HDLC data is shifted out through the zero insertion logic 248 which is disabled while the flags are being sent The address bit AO is inserted in all address control information and frame clock fields following the five contiguous 1 s in the data stream The resultant of the CRC generator 250 for the SDLC data is also routed through the zero insertion logic 248 SCC Receiver Referring to FIGS 3A 3B receivers 232 234 have three eight bit FIFO buffer registers and an eight bit Shift register This arrangement creates a three byte delay time which allows the central processing unit 30 FIG 1B time to service an interrupt at the beginning of a block of high speed data With each receipt of data in FIFO at 232 234 FIGS 3A 3B an error FIFO 234 is provided to store parity and framing errors and other types of status informa tion In FIG 3 the incoming data is routed through one of several paths depending on the mode and the character length In asynchronous mode the serial data enters the three bit delay at element 280 if a character length of seven or eight bits is selected If a character length of five or six bits is selected then data enters the receive register 232 234 directly
68. ts Foreplane Interface for Microprocessor 110 FP 2 in FIG 1 As seen in FIG 1 2 the User Interface Processor 100 provides a buffered microprocessor interface that is brought to the foreplane connectors FP 2 This inter face allows the UIP 100 to be connected to application dependent logic via this interface All necessary mem ory control signals are provided so that logic providing expanded memory can also be implemented Input out put devices external to the UIP 100 can also be con nected These can be input output units or units memo ry mapped to the UIP 100 Each interrupt is received by the UIP s programma ble priority interrupt controller PRITC 800 More in terrupts can be provided by the addition of another controller that uses the UIP interrupt controller cas cade outputs CASO 1 2 of 814 of FIG 8 This can result in the expansion of up to eight interrupt signals For devices with very slow access times a ready in put derived from the microprocessor 110 is brought to the foreplane FP 2 so that these slower components can meet the microprocessor timing constraints The microprocessor 110 has an output signal HLDA which is present on the CTL bus of the fore plane FP 2 of FIG 1 2 however the input signal 5 20 25 30 35 40 45 55 60 65 16 HOLD is not present This means that the application dependent logic connected to the foreplane FP 2 can not for example perform
69. ts or the on board microprocessor state machine self tests The level 1 tests cover tests involving the main cen tral processor 30 the memory control unit 32 the host dependent port 500 and the processor interface card 40 whereby each of these four units are given a basic board test which is driven by the User Interface Processor 100 The level 1 tests also cover certain other units which are defined as a self test which is driven by on board microprocessor unit These units which are given the self test via the microprocessor are the User Inter face Processor 100 the power control card 50 the stor age module disk data link processor the printer tape data link processor and the data comm data link proces sor 4 701 845 25 MICRO CODED DIAGNOSTICS LEVEL 2 These tests are used to obtain a higher level of confi dence in main frame hardware by testing the interac tions between sub modules in a controlled environment and are also used as memory sub unit exercises These tests are written in OHNE microcode and are run on the central processor 30 at normal clock speed 4 mega hertz with a driver running on the User Interface Pro cessor 100 that controls the execution of test cases and monitors the results These level 2 tests cover the fol lowing items a the central processor 30 b the memory control unit 32 and the memory storage boards 34 c the host dependent port 500 FIG 1B d the mainten
70. urs the microprocessor 110 has its non maskable interrupt set to true and the error logging can then be implemented to record the bad address when such an implementation has been provided in the UIP 100 firm ware 4 701 845 7 PROM STORAGE MEMORY 170 The storage of firmware for the User Interface Pro cessor 100 is provided by an array of six 8K x8 PROMs which are arranged in a matrix of 24K x 16 Thus this results in a 48K byte storage capacity These PROMs which are used are 8K X 8 erasable and oper ate on a single cycle no wait The PROM memory 170 FIG 1 2 is mapped into the highest point of the micro processor memory map This is because of the fact that the microprocessor 110 resets to this point which is the hex addresss 0 SERIAL PORTS As will be seen in FIG 1 1 the User Interface Pro cessor 100 uses two chips 200 and 200 which are called serial communication controller chips SCC In the preferred embodiment these chips are those manufac tured by the Zilog Corporation whose address is 1315 Dell Avenue Campbell Ca 95008 and described in the publication entitled Counter Firmware Technical Manual as Zilog part 28530 and published in March 1982 by Zilog Corporation The SCC chips 200 and 200 each provide two inde pendent serial full duplex data communication channels with synchronous asynchronous data rates of up to one megabit per second They can provide up to 250k bits per sec
71. venth bit is inspected only if the sixth bit equals If the seventh bit is a zero a flag sequence has been received and the receiver is synchronized to that partic ular flag If the seventh bit is a one then an abort or an EOP end of poll is recognized depending on the selection of either the normal SDLC mode or the SDLC loop mode Thus for both SDLC modes the same path is taken by the incoming data The reformatted data enters the 3 bit delay and is transferred to the receive shift register 232 234 The SDLC receive operation begins in the hunt phase by attempting to match the assembled char acter in the receive shift register 232 232 with the flag pattern in register WR7 236 When the flag character is recognized subsequent data is routed through the same path regardless of the character length Either the CRC 16 or the CRC SDLC cyclic redundancy check polynomial can be used for both monosync and the bisync modes but only the CRC SDLC polynomial is used for the SDLC oper ation The data path taken for each mode is also different Bisync protocol is a byte oriented operation that re quires the central processing system host 30 FIG 1B to decide whether or not a data character is to be in cluded in the CRC calculation An eight bit delay in all synchronous modes except SDLC is allowed for this process In the SDLC mode all bytes are included in the cyclic redundancy checker calculation The Us
72. vice 800 is incorporated The Programmable Priority Interrupt Controller is capable of handling eight possible interrupts and for generating a priority for each interrupt as well as an individual vector for each interrupt Various components of the User Interface Processor 100 can provide an interrupt signal to the microproces sor 110 These various types of interrupts are as follows a SCC 1 interrupt b SCC 2 interrupt c CIO 1 interrupt d CIO 2 interrupt e Interval timer interrupt 8254 2 ORed together 9 Interval timer interrupt 8254 g Foreplane receive interrupt h DLI controller interrupt These interrupts are given a priority rating and the interrupt controller device 800 will output a vector pointing to a service routine in microprocessor 110 in 4 701 845 15 response to its corresponding interrupt input The prior ity is under programmed control and can be used to assign a level of priority to each input The programma ble priority interrupt controller PRITC 800 is shown in block diagram form in FIG 8 The block diagram of FIG 8 shows the basic ele ments of the PRITC 800 that is to say the priority interrupt controller of the User Interface Processor 100 Here a data bus buffer 810 connects to the internal bus 212 which has a bidirectional connection to the inter rupt mask register 822 The mask register 822 communi cates to the in service register 824 to the priority re solver 826
73. wo are used by the Baud rate generator 210 210 one is used for the interrupt vector one is used for the receiver buffer and one is used for reading the interrupt pending bits SCC Transmitter The transmitter section 240 of the serial communica tion controller 200 is shown in FIG 3B The transmitter section of the SCC has an eight bit transmit data register 240 which is loaded from the 4 701 845 9 internal data bus 212 FIGS 2 3 and also has a trans mit shift register 244 which is loaded from either the sync character or the address register 238 WR6 the sync character or the SDLC flag register 236 WR7 of FIG 3B or the transmit data register 240 In the byte oriented modes the registers WR6 238 and WR7 236 of FIG be programmed with sync characters In the monosync mode an eight bit or a six bit sync character is used in WR6 whereas a 15 bit sync charac ter is used in the mode in registers WR and WRT In the bit oriented modes the flag contained in regis ter WR7 236 is loaded into the transmit shift register 244 FIG 3B at the beginning and at the end of a mes sage If asynchronous data is being processed then regis ters WR6 and WR7 of FIG are not used and the transmit shift register 244 is formatted with start and stop bits shifted out to the transmit multiplexor 252 at the selected clock rate Synchronous data except SDLC HDLC is shifted
74. y a clock which is normally 32 times NRZI or which is 16 times FM the data rate The DPLL uses this clock along with the data stream to construct a receive clock from the data This clock can then be used as the SCC receive or the SCC transmit clock or both Input Output Ports In order to provide access to external interfaces there are provided as seen in FIG 4 a pair of counter timer parallel input output ports CIO These counter timer ports are provided through the use of a Zilog chip Z8536 which is described in a Zilog publication enti tled Zilog Tech Manual and which is manufactured by Zilog Corporation of 7315 Dell Ave Campbell Ca 95008 and which was published in March 1982 This CIO or counter input output port 202 202 of FIG 1 1 is a general purpose I O port that provides two independent eight bit double buffered bidirec tional input output ports plus an extra four bit I O port These types of ports feature a programmable polarity and a programmable direction in the bit mode they provide 1 s catchers and programmable open drain outputs This CIO device also includes three 16 bit counter timers each having three output duty cycles and up to 20 25 30 35 40 45 55 60 65 12 four external access lines These timers are programma ble as being retriggerable or as being non retriggera ble The CIO 400 of FIG 4 is capable of pattern recog nition and genera
75. ystem s state COMPUTER SYSTEM MAIN FRAME DIAGNOSTIC INTERFACE The diagnostic tests for the main processor 30 the memory control unit 32 and the host dependent port 500 are initiated from the User Interface Processor 100 Here the User Interface Processor functions as follows a it initializes the computer system network b it provides for on site and remote service access to the computer system network This includes the in terface to the main central processor 30 and the ma nipulation of shift chains into the computer network system and control of the system clocks and event analysis in order to halt the computer system net work c it responds to real time interrupts such as control store parity and super halt interrupts from the com puter system d it provides the software soft front panel for the computer system network The User Interface Processor hardware and its func tionality are discussed in conjunction with FIGS 1 through 9 of the specification COMPUTER SYSTEM INPUT OUTPUT DIAGNOSTIC INTERFACE The User Interface Processor 100 is a processor that has a limited input output capability The UIP 100 can communicate with peripheral devices that are config ured into the system via the data link interface The User Interface Processor 100 through the power con trol card 40 provides the link to the remote support center shown as 50 FIG 1A This is to permit remote diagnostic functions The User I

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