S-band Transmitter (STX) Interface Control Document
Contents
1. 43 45 47 49 51 H1 STX enable Hi SPI signals mo PE Ground H1 El Ready signal H1 41 43 Pc H1 MB FPGA Reset H2 Power Battery H1 21 23 Alternate I2C Figure 3 CSK header connections French South African 7 of 9 www cput ac za fsati Institute of Technology Software interfaces CPUT ICD STX 01 gt i SAT I Rev 1 1 French South African Institute of Technology 4 Software interfaces 4 1 SPI The high speed SPI interface is utilised to transfer user data payload data to the STX The serial data MOSI is sampled on the rising edge of the SPI clock SCK e Mode 0 e CPOL 0 polarity e CPHA 0 phase 4 2 2C operation All telecommands and telemetry are communicated via 12C The default 12C address is 0x26 but may be configured according to user specifications at time of production Issuing a telecommand writing data has the following procedure The first byte written to the I C points to the address of the register and the following byte writes the value to the register Reading telemetry follows a similar approach firstly a byte is written to point to the correct register followed by a read transaction to return the value Consecutive read transactions automatically increment the read pointer 4 3 Operation On power up the STX is ready to transmit data It will boot up with default set2. GA Supervisor Dual DAC PEL Telemetry ADC gt 2400MHz 2450MHz y of sy DD Modulator lt gt Pre amplifier gt Power Amplifier Figure 1 Block diagram of the STX with its CSK header connections Small form factor CubeSat Kit PC 104 compatible QPSK OQPSK modulation schemes e 2 Mbps data rate e IntelSAT 308 based encoding e Operation in Earth Exploration Satellite Services or amateur bands built to order French South African 1 of 9 www cput ac za fsati Institute of Technology Top Level Description CPUT ICD STX 01 gt SATI Detailed Characteristics Rev 1 1 French South African Institute of Technology e Adjustable RF output power e Adjustable data rate e Simple digital interfaces I C interface for Control Telemetry SPI interface for user data 2 2 Detailed Characteristics 2 2 1 Power e Transmit RF output power maximum 30 dBm e DC power consumption less than 6 W e Compatible with Clyde Space EPS Battery bus 6V 12V 2 2 2 RF e Amateur band transmit frequency range 2400 MHz 2450 MHz e Carrier frequency adjustable in 500 kHz steps via 12C telecommand e Transmit RF output power adjustable to 21 24 27 30 dBm 2 2 3 Encoding and modulation e QPSK and OQPSK modulation schemes e Open Network Encoding scheme based on IntelSAT IESS 308 specifications e V 35 IntelSAT scrambler e Differential encoding e Half rate convolutional encod
3. Ges 3 5 CSK header connections 2 ee 4 Software interfaces A A ocke ha hoe G 4 3 Operations out shea hee oe Oa eae AG a Aa a oe lt AA PPGA reset 2 4 ica fb thle a eee BNE Bod Ss A day Be bok Gee a ie ees List of Figures 1 Block diagram of the STX with its CSK header connections 2 Mechanical diagram shown in mm ESQ 126 13 G D header shown 3 CSK header connections ee iii List of Tables 1 Mechanical specifications oaoa ee 2 Materials list 2 Lats ld wwe es ee a ee ya SG he BE eS 3 OSK connector pinouts Sor si ic a at ied iv Nomenclature Abbreviations CSk FPGA OBC PA STX TBC TR CubeSat Kit Field Programmable Gate Array On board computer Power Amplifier S band Transmitter To be confirmed Transmit ready Top Level Description CPUT ICD STX 01 gt SATI Rev 1 1 French South African Institute of Technology 1 Introduction 2 Top Level Description 2 1 Overview The STX is an integrated RF data transmitter module operating in the S band and supporting data rates of up to 2 Mbps This document describes the interfaces between the transmitter and an OBC via the PC 104 header stack connector A general overview of the intended operation for the transmitter is provided Operation is subject to change without notice PC 104 header E E E gt 2 7 3 2 E PSU Reset FP
4. Sa Mor Peninsula D F i SATI University of Technology French South African Institute of Technology S band Transmitter STX Interface Control Document Document no CPUT ICD STX 01 Revision 1 1 Date 5 February 2014 Name Date Signed Author Jason Quibell 5 February 2014 Approved Charl Jooste 5 February 2014 Approved Francois Visser 5 February 2014 Document Control Description of Rev Date Section Reason for Change Change 1 0 6 Dec 2013 All First Release 1 1 5 Feb 2014 All Second Release eS da diagram Revision Control Revisions Product Part Number Notes Covered This documentation relates to STX CPUT STX 01 1 7 the STX Related Documents No Document Name Document Reference CPUT UM STX User Manual S band 01 Transmitter STX Revision 1 6 Contents Document Control Revision Control Related Documents Nomenclature 1 Introduction 2 Top Level Description Ql HOWOPVICW a a ct Ate Rs Meech ot Y 2 2 Detailed Characteristics Be Zo OWEN a a tias 22 2 RE E RN 2 2 3 Encoding and modulation i 22A Plivsical ia a a bee Be cd e 2 3 Detailed Description e PASS E A O A RRA 2 3 2 FPGA Support Circuitry 0 0 0 2002000002 ee ee 23I A o A 3 Mechanical interfaces Sit Specifications E its eda ds Boe Gy ee de ee ea ee ae Gea ghee o 3 2 Mechanical configuration s oaoa ee 3 3 Materials we Ds ea ao a A a A a ag 3A Connectors 25 4 a es o dan A e a ta thal
5. are provided as telemetry and are accessible via 12C 3 Mechanical interfaces 3 1 Specifications Table 1 Mechanical specifications Value Units Dimensions 96 x 90 2 x 17 mm Mass lt 95 g 3 2 Mechanical configuration French South African 4 of 9 www cput ac za fsati Institute of Technology ASO OUUYIA JO se3n31I3SUT 90 79 tr 4 o 5 a 5 81 03 tn en 9 381 77 47 E i S 55 22 gt _ 24 79 Ph a I J Q 00 HERRERA AA RRE AR ARRE ERRE O E E EE E EE OO OO l 5 ono E E EE BB S PU EEES EE Be Be Be Be Ee E A 8 o Oo _ Woo 3 Ol 1000 Sp a Sp a oooool mn 0 o0 7 NA i 1 21 0 00 g eo ST 5 85 oO 222 20d 000 Bd a FS 3 06 o 20050 e PUB iF 19 A ne 0 T in 00 MQ ooo DD 5 E o e pa o OM lo ON h Ri NNA Co ao Q bal NY 6 LO N CO CD g ry lon Sy LO LO N LO o o 2 64 N Y 521 72 14 a 80 01 84 10 ooo 85 22 ryesy ezoe yndo MMM Figure 2 Mechanical diagram shown in mm ESQ 126 13 G D header s
6. hown 3 39 Too UOYeINSYUO TEIUEBUIOWN S90BJI9 UTI JETUE YOY TI Ay 10 X LS GOl Lndo NGojouysay Jo aynyiysuy eaudy unos youayy ILVS 3 Mechanical interfaces CPUT ICD STX 01 4 K SN gt F SATI Materials Rev 1 1 French South African Institute of Technology 3 3 Materials Table 2 Materials list Material Manufacturer TML CVCM AWVR Application Note Scotch Weld 3M 0 97 0 02 0 32 Adhesive 2216 Epoxy B A Fixing Conformal PCB Material FR4 0 62 0 0 1 PCB Board NASA Worst Case Solder Resist CARAPACE 0 95 0 02 0 31 Solder EMP110 Mask Solder Sn63 3 4 Connectors The STX utilises a 50 Q SMA as the RF transmit connector The STX header is a SAMTEC connector from the ESQ 1 range 3 5 CSK header connections Figure 3 illustrates the connections that are made available at the CSK header Optional con nections that are provided on the header include an FPGA reset STX enable SPI transmitter buffer ready and alternative 12C The optional connections may be selected at the time of pro duction and should be selected according to application and performance requirements Either the primary 12C or alternate 12C must be chosen not both Should the optional functionality not be required it will not be made available at the header there will be no physica
7. ing K 7 e Pulse shaping filter 0 35 roll off factor e 2 Mbps data rate with full 1 2 1 4 and 1 s data rate modes French South African 2 of 9 www cput ac za fsati Institute of Technology Top Level Description CPUT ICD STX 01 i SAT I Detailed Characteristics Rev 1 1 French South African Institute of Technology 2 2 4 Physical e Mass lt 95g e Form factor 96x90 2x17 mm PC 104 CubeSat Kit compatible PCB e Operating temperature range 25 C to 61 C French South African 3of9 www cput ac za fsati Institute of Technology Mechanical interfaces CPUT ICD STX 01 gt i SAT I Detailed Description Rev 1 1 French South African Institute of Technology 2 3 Detailed Description 2 3 1 FPGA The STX utilises an Actel Igloo Nano FPGA for all data processing encoding and control The FPGA s tolerance to single event upsets and radiation in low Earth orbit have made it a suitable candidate for this purpose All the code modules were implemented in VHDL 2 3 2 FPGA Support Circuitry The FPGA is supported by a reset supervisor IC The device monitors the supply voltage of the FPGA and will hold the FPGA in reset if there is an undervoltage condition The reset supervisor will hold the FPGA in reset for 200 ms upon startup An oscillator to provide a clock signal to the FPGA is also included 2 3 3 Sensors The STX includes on board temperature current and voltage sensors All the sensor readings
8. ker ASM for non turbo coded data 0x1ACFFCID Precautions When not transmitting into an antenna ensure that an appropriate RF load is connected to prevent damaging the transmitter 4 4 FPGA reset A reset signal is provided to the header that will allow an external subsystem such as an OBC to reset the FPGA to a known good state This is an optional signal Alternatively cycling the power of the radio will also reset the FPGA to a known good state French South African 9 of 9 www cput ac za fsati Institute of Technology
9. l connection All signal voltage levels are 3 0 V LVCMOS yet are 3 3 V compatible French South African 6 of 9 www cput ac za fsati Institute of Technology Mechanical interfaces CPUT ICD STX 01 D y S AT CSK header connections Rev 1 1 French South African Institute of Technology Pin Pin name I O type Description Optional H1 41 SDA Bidirectional PC serial data Yes H1 43 SCL Input I2C serial clock Yes H1 23 SDA_ALT Bidirectional Alternate 12C data Yes H1 21 SCL ALT Input Alternate 12C clock Yes H1 13 TR Output Transmitter ready for data Yes H1 09 COMM_SCLK Input SPI clock Yes H1 11 COMM_MOSI Input SPI data Yes H1 12 COMM_CS Input SPI chip select Yes H1 15 nFPGA_RESET Input FPGA reset active low Yes H1 10 STX_EN Input Board power enable Yes H2 45 VBATT_BUS Power Battery bus supply No H2 46 VBATT_BUS Power Battery bus supply No H2 29 GND Power Power ground No H2 30 GND Power Power ground No H2 32 GND Power Power ground No Table 3 CSK connector pinouts 2 4 6 8 10 12 14 16 18 20 22 24 26 28 34 36 38 40 42 44 48 50 52 He 1 3 5 7 9 11 13 15 17 19 21 23 25 ye 35 37 39 41 E 49 51 2 4 6 8 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 HA 113 5 7 17 19 21 23 25 27 29 31 33 35 37 39 41
10. tings for the data rate RF power setting etc Transmit Data to be transmitted is sent via SPI Each byte of data sent to the STX will be placed into the 4096 byte buffer A transmit ready TR flag is provided to the PC 104 header as a hard signal optional as well as via an I C telemetry channel as a soft signal The hard TR signal should provide a performance advantage as opposed to polling the PC telemetry channel since it can be used to interrupt an OBC The TR flag will become active once the number of bytes in the buffer drops below a predefined threshold indicating more data can be added to the buffer The threshold trigger for the TR flag has been configured to 513 bytes French South African 8 of 9 www cput ac za fsati Institute of Technology Software interfaces CPUT ICD STX 01 gt i SAT I FPGA reset Rev 1 1 French South African Institute of Technology Sync bytes The OBC may send a telecommand to put the STX into Synchronisation Mode In this mode when the PA is activated synchronisation bytes will be sent from the transmitter no real data is read from the SPI input data FIFO This allows the ground station receiver to achieve lock synchronisation before actual payload data is transmitted over the link In this mode the data buffer will accept data via the SPI interface only until the internal FIFO is full indicated via the transmit ready line going low The synchronisation word is a CCSDS 32bit Attached Sync Mar
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