ScanPCI User`s Manual (70351)
Contents
1. Figure 5 4 Assembly Details Window for the UUT Assembly Click on the first row Netlist File This will select the Netlist File row as shown in Figure 5 5 Assembly Details YOUR_CPCI_TARGET Netlist File Topology File Constraint File Netlist Edit File Merge Pin Library SDF File MDF File Figure 5 5 Assembly Details Window with Netlist File Row Selected Testing CompactPCI Cards 5 5 Click on the Add command button A new Add Files to Assembly file browser window will be displayed Select the netlist for the UUT and click on the Add command button The Assembly Details screen will be displayed again and will include the netlist file Resize the window so that the entire pathname is visible and your screen should look like Figure 5 6 Assembly Details YOUR_CPCI_TARGET AE m Assembly Input Files Netlist File C Targets Compact PCI Board Compact PCI Board net Topology File Constraint File Netlist Edit File Merge Pin Library SDF File MDF File Add Remove Edit Jv Add Assembly Name as a prefix to all file contents OK Cancel Figure 5 6 UUT Netlist File Selected Click on the second row labeled Topology File This will select the Topology File row Click on the Add command button and a new Add Files to Assembly file browser window is displayed Select the topology file for the UUT and click on the Add command button The Assembly Details screen will be2. JTAG TAP Connector 10 pin IDC 3M part no 3793 6302 or equivalent JTAG Interface IEEE 1149 1 compliant interface Power Internal ATX style power supply sy Contin mn wax Unt KITTS EIER ozsa pa me IA Vi Vec G GND Vo Ve loz or GND Table 3 3 Signal Level Characteristics ScanPCI Hardware Reference ScanPCI Operating Characteristics The following operating characteristics are not specifications but are typical operating characteristics for the ScanPCI TEMPERATURE Operating 0 C to 55 32 PF to 131 F Non operating 40 C to 75 C 40 F to 167 F ALTITUDE Operating up to 4600 meters 15 000 feet Nonoperating up to 15 300 meters 50 000 feet Humidity 90 non condensing Avoid sudden extreme temperature changes that could cause condensation within the instrument Table 3 4 ScanPCI Operating Characteristics ScanPCI Hardware Reference Chapter 4 Preparation of Test Input Files How to use the ScanPCI with the ScanPlus boundary scan tools Introduction The ScanPCI integrates easily with a boundary scan test plan When a PCI card is installed in the PCI slot socket of the ScanPCI the socket behaves like a boundary scan component Therefore it is not normally necessary to make any changes to the netlist to include the ScanPCI in a test plan Once the PCI card is plugged into the socket of the ScanPCI the boundary scan test
3. ScanPlus Merge Untitled fl File Help m Assembly Configuration Assembly Name Assembly 1 Assembly 2 Assembly 3 Assembly 4 Assembly 5 Assembly 6 Add System Connection File Browse Figure 5 1 ScanPlus Merge Main Window 5 2 Testing CompactPCI Cards Step 2 Add the Unit Under Test UUT Assembly Since the UUT is the first target in the scan chain it will be added first Click on the Add button to add a new assembly to the current Merge Plan A new assembly will be added and the default name of ASSEMBLY1 will appear in the first assembly entry as shown in Figure 5 2 ScanPlus Merge Untitled Figure 5 2 ScanPlus Merge Main Window with aNew Assembly Testing CompactPCI Cards 5 3 Give the new assembly entry for the UUT a meaningful name by typing it into the Assembly 1 name field Your screen should now look similar to Figure 5 3 ScanPlus Merge Untitled Figure 5 3 ScanPlus Merge Main Window Showing Renamed UUT Assembly 5 4 Testing CompactPCI Cards Double click on the UUT assembly name or click on the Details button to bring up the Assembly Details screen for the UUT assembly This screen shown in Figure 5 4 is where the Test Step files are entered for the UUT assembly Assembly Details YOUR_CPCI_TARGET Netlist File Topology File Constraint File Netlist Edit File Merge Pin Library SDF File
4. vq44 NO CROCHE C TENZ xc2s200_fg456 bsd FG456 NO cPCI Target U3 xc2s200_fg456 bsd FG456 NO CPCI_ADAPTER_ Pl ScanPCI_3V bsd PCI_CONN NO D_CHAI END N DEVI CES Figure 5 19 Example Topology top file After the ScanPCI is Added Testing CompactPCI Cards Chapter 6 Executing Selftest with ScanPlus Runner How to run a basic sanity check on the ScanPCI unit ScanPlus Runner sold separately can load and run the compact vector file ScanPCI_Selftest_inf cvf and quickly verify that the ScanPCI is functional Both the ScanPlus Runner software and a Corelis Boundary Scan controller such as the PCI 1149 1 Turbo are required to execute this file Infrastructure Test The infrastructure test verifies the TAP connection between the controller and the ScanPCI The infrastructure test requires a Corelis boundary scan controller a 10 pin TAP cable from the controller and a ScanPCI unit The following steps execute an infrastructure test Step 1 Remove any PCI cards from the ScanPCI s PCI test sockets Step 2 Verify that JP1 and JP2 are installed Step 3 Connect the 10 pin TAP cable from the external controller to the TAP connector of the ScanPCI Step 4 Apply power to the ScanPCI Step 5 Make sure that both LEDs on the ScanPCI illuminate Step 6 Double click on the ScanPlus Runner Icon on the Host PC Step 7 Select New Test Plan from the File menu and click on the Add button Step 8 With the file b
5. displayed again and will include the topology file as shown in Figure 5 7 Add the constraint netlist edit merge pin library SDF and MDF files if any to the assembly in the same way The configuration of the UUT assembly is now complete Click on the OK button to return to the main screen Assembly Details YOUR_CPCI_TARGET olx m Assembly Input Files Netlist File C Targets Compact PCI Board Compact PCI Board net Topology File C Targets Compact PCI Board Compact PCI Board top Constraint File Netlist Edit File Merge Pin Library SDF File MDF File remove _ Jv Add Assembly Name as a prefix to all file contents OK Cancel Figure 5 7 UUT Topology File Selected 5 6 Testing CompactPCl Cards Step 3 Add the CompactPCI Adapter Assembly Click on the Add button to add a new assembly to the current configuration A new assembly will be added and the default name of ASSEMBLY2 will appear in the second assembly entry as shown in Figure 5 8 4 ScanPlus Merge Untitled OUR_CPCI_LTARGET Figure 5 8 ScanPlus Merge Main Window with a Second Assembly Added Testing CompactPCI Cards 5 7 Give the new assembly entry for the CompactPCI Adapter a meaningful name by typing CPCI_ADAPTER into the Assembly 2 name field Your screen should now look similar to Figure 5 9 ScanPlus Merge Untitled al OUR_CPCILTARGET CPCILADAPTER Figure 5
6. 9 ScanPlus Merge Main Window Showing Renamed Assembly 5 8 Testing CompactPCI Cards Double click on the CPCI_LADAPTER assembly name or click on the Details button to bring up the Assembly Details screen for the new assembly This screen as shown in Figure 5 10 is where the Test Step files are added to the assembly Assembly Details CPCI_ADAPTER Netlist File Topology File Constraint File Netlist Edit File Merge Pin Library SDF File MDF File Figure 5 10 Assembly Details Window Since there are no boundary scan components on the CompactPCI to PCI adapter only a netlist is required Add the adapter netlist to the assembly as shown previously your screen should look similar to Figure 5 11 The configuration of the second assembly is now complete Click on the OK button to return to the main window Assembly Details CPCI_ADAPTER Netlist File C Targets Compact PCI Board CPCI Adapter NET Topology File Constraint File Netlist Edit File Merge Pin Library SDF File MDF File Figure 5 11 Assembly Details after Test Step files added Testing CompactPCI Cards 5 9 Step 4 Add the System Connection File The System Connection file shown in Figure 5 12 describes the interconnections between the defined assemblies System Connection File for merging the Compact PCI Adapter with your Compact PCI target CONNECTIONS YOUR_CPCI_TARGET J1 CPCI_ADAPTER Pe YOUR_CPCI_TAR
7. ATION OF TEST INPUT FILES 4 1 TAthO GUC OL is 4 1 How to Generate Vectors using the ScanPCI ueeeesssssesssssenssssnnnsssnsnnnsnnsnnnsnnsnnsnnnsnnnsnnnsnnnnnsnsnnnsnnnnnnn 4 1 CHAPTER 5 TESTING COMPACTPCI CARDS 5 1 TtithO Gu Gti Otis ii A aa 5 1 Merging the CompactPCI Adapter and the UUT zueesseessnessnessnesenssnsssnnnsnensnensnensnensnonsnnssenssensnensnnnann Step 1 Starting ScanPlus Merge Step 2 Add the Unit Under Test UUT Assembly Step 3 Add the CompactPCI Adapter Assemblly Step 4 Add the System Connection Pile ccoo essen aa Step o Merse the Assemblies ninni n i at lidad Modifying the Topology File to Include the ScanPCI zuusssuesssnnssssnssssensnnnnensnnnnsnnnsnnnsnnnnssnnensnnnsnnnn 5 14 CHAPTER 6 EXECUTING SELFTEST WITH SCANPLUS RUNNER 6 1 Infrastructure Testoni aca annie 6 1 Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 24 Figure 4 1 Figure 4 2 Figure 5 1 Figure 5 2 Figure 5 3 Figure 54 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 5 10 Figure 5 11 Figure 5 12 Figure 5 13 Figure 5 14 Figure 5 15 Figure 5 16 Figure 5 17 Figure 5 18 Figure 5 19 Figure 6 1 Table of Figures SOUP CL Boundary Stan Teer ee ae 1 1 Connection of the ScanPCI and the Target using Separate TAPS nnnnnnneneneneneneenenenenene 2 2 UUT Connection Example using Separate TAPS a a as 2 3 Block Diagram of the Connection to a ScanPCI
8. CORELIS ScanPCI ScanPCI PCI and CompactPCI Boundary Scan Tester User s Manual CORELIS ScanPCI ScanPCI PCI and CompactPCI Boundary Scan Tester User s Manual Document Part Number 70351 Revision A Copyright 2003 Corelis Inc Corelis Inc 12607 Hiddencreek Way Cerritos CA 90703 Telephone 562 926 6727 Fax 562 404 6196 Preface PRINTING HISTORY New editions are complete revisions of the manual Update packages which are issued between editions contain additional and replacement pages to be merged into the manual by the customer The dates on the title page change only when a new edition is published A software code may be printed before the date this indicates the version of the software product at the time the manual or update was issued Many product updates and fixes do not require manual changes and conversely manual corrections may be done without accompanying product changes Therefore do not expect a one to one correspondence between product updates and manual updates Revision A September 2003 GENERAL NOTICE Information contained in this document is subject to change without notice CORELIS shall not be liable for errors contained herein for incidental or consequential damages in connection with the furnishing performance or use of material contained in this manual This document contains proprietary information which is protected by copyright All rights reserved No part of this do
9. GET Jz CPCI_ADAPTER P3 END CONNECTIONS Replace the string YOUR_CPCI_ TARGET with the assembly name used for your target in ScanPlus Merge Replace the reference designators Jl and J2 with the reference designators of the compact PCI connectors in your target Figure 5 12 System Connection File To add the System Connection file to the Merge Plan click on the Browse button in the System Connection File area near the bottom of the main window and a file browsing window will appear Select the file CompactPCI Board sco and click on the Open button Select a System Connection File 2 x Lookin Compact PCI Board e ex Ey File name Compact PCI Board sco Files oftype System Connection File sco v Cancel 77 Figure 5 13 System Connection File Browsing Window 5 10 Testing CompactPCI Cards The ScanPlus Merge main window will now be displayed as shown in Figure 5 14 The Merge Plan is now complete ScanPlus Merge Untitled OUR_CPCITARGET CPCILADAPTER CA Targets Compact PCI Board Compact PCI Board s Figure 5 14 ScanPlus Merge Main Window with System Connection File Testing CompactPCI Cards 5 11 Step 5 Merge the Assemblies Click on the Generate button to begin the merging process Because this is a new unsaved Merge Plan the Save Merge Plan File window will be displayed Move to the directory where you would like the merged test plan fil
10. adapter is available from Twin Industries www twinhunter com The following table lists the part number for the adapter at the time that this manual was printed Note that there may be other manufacturers that offer similar parts as well Twin Industries Part Number Description 2000 64PCI cPCI to PCI Passive Adapter Once the cPCI card is plugged into the socket of the ScanPCI via the cPCI to PCI adapter the boundary scan test system will automatically test the cPCI card edge connector However regeneration of the interconnect tests using ScanPlusTPG with the relevant ScanPCI input files supplied on the floppy disk is required Regeneration of the files consists of three main steps 1 Use ScanPlus Merge to combine the netlist of the CompactPCI to PCI Adapter with the UUT 2 Modify the topology file to add the ScanPCI module 3 Regenerate the test vector files using ScanPlusTPG Testing CompactPCl Cards 5 1 Merging the CompactPCI Adapter and the UUT ScanPlus Merge is required to combine the netlists of the UUT and the CompactPCI Adapter Follow the instructions in the ScanPlus Merge User s Manual to install ScanPlus Merge if it has not already been installed To merge the two assemblies follow the steps below Step 1 Starting ScanPlus Merge ScanPlus Merge can be started by selecting the ScanPlus Merge entry from the Windows Start menu When ScanPlus Merge starts the main window is displayed as shown in Figure 5 1
11. aracteristics 34 Table 5 1 Files Created by the Merge Posen AAA AAN 5 14 vi Chapter 1 Product Overview Introduction The ScanPCI is a boundary scan based PCI card tester that provides a convenient way to test the PCI card unit under test UUT using boundary scan An optional adapter is available for testing CompactPCI cPCI cards as well The ScanPCI provides power to the UUT and contains special boundary scan circuitry to permit interconnect testing of the UUT s PCI cPCI card edge connector It is designed to add boundary scan control and visibility to PCI connectors that would otherwise be impossible to test or would require expensive wiring adapter harnesses The ScanPCI is designed to be used with the Corelis ScanPlus family of tools which are sold separately Figure 1 1 ScanPCI Boundary Scan Tester Product Overview 1 1 The ScanPCI provides the following advantages for testing and programming PCI and CompactPCI cPCI cards Enables boundaty scan JTAG testing of PCI cPCI cards Extends boundary scan test coverage and provides easy access to PCI cPCI edge connectors Provides test coverage for the hard to test traces between the PCI cPCI edge connectors and devices connected to them Allows easy access to the PCI cPCI bus via the connectots Maintains a clean integration environment Supports a JTAG TAP connection through the PCI cPCI bus interface or directly to the UUT Supports 3 3V 5V and universal I O PCI
12. arget UUT TAP Connections on the PCI Card edge Connector The ScanPCI also supports the connection of the TAP signals from the ScanPCI to the target UUT over the PCI card edge connector Connect the 10 pin cable from the boundary scan controller ScanTAP 4 Buffer 1149 1 Gang etc to the ScanPCI TAP connector The connection list for the TAP signals on the card edge connector defined in the PCI specification must be followed Figure 2 3 shows a block diagram for the TAP connection from the ScanPCI module to the target UUT over the PCI card edge connector HOST COMPUTER SCANPCI SCANTAP 4 PCI 1149 1 TURBO INTELLIGENT POD CONTROLLER Figure 2 3 Block Diagram of the Connection to a ScanPCI with a Single TAP For this mode jumpers JP1 and JP2 need to be configured to jumper TDI to TDO across the ScanPCI connector that is not being used For example if a universal or 3 3V PCI card is being tested in the 3 3V PCI slot then JP2 should be installed and JP1 should be open If a 5V PCI card is being tested in the 5V PCI slot then JP1 should be installed and JP2 should be open 2 3 An example of a UUT connected to the ScanPCI using a single TAP configuration is shown in Figure 2 4 Test System Figure 2 4 UUT Connection Example Using a Single TAP 2 4 ScanPCI Installation Chapter 3 ScanPCI Hardware Reference Connector Pinout LEDs and Product Specification Jumper Configuration Four jumpers on the ScanPCI are used to conf
13. cPCI cards Internal power supply included for powering up the Unit Under Test UUT Power indicator LEDs Selectable PCI bus clock speed Reset switch for generating reset to the UUT Software supplied contains BSDL and other files for automatic test pattern generation with the ScanPCI Compatible with the ScanPlus family of products for testing and in system programming of Flash memories and CPLDs Product Overview Required hardware and software The ScanPCI requires the following additional equipment that is sold separately and is not part of this product e Any of the Corelis Boundary Scan Controllers We recommend the high performance PCI 1149 1 Turbo with the ScanTAP 4 Intelligent Pod please call Corelis for a list of other available controllers e ScanPlusTPG Software e ScanPlus Runner Software e Host PC computer with the above products installed as per the specific instructions found in these product s users manuals e ScanPlus Merge Software only required if testing CompactPCI cards e CompactPCI to PCI adapter only required if testing CompactPCI cards 1 Contact information for purchasing the CompactPCI to PCI adapter can be found in Chapter 5 Product Overview 1 3 Chapter 2 ScanPCI Installation Installing and setting up the ScanPCI hardware Connecting the UUT Product Components The ScanPCI product package consists of the following components e ScanPCI Hardware e ScanPCI User s Manual e ScanPCI Sof
14. cument may be reproduced or translated to other languages without the prior written consent of CORELIS CORELIS assumes no responsibility for the use of or reliability of its software on equipment that is not furnished by CORELIS PRODUCT WARRANTY This CORELIS product has a warranty against defects in material and workmanship for a period of 90 days from date of shipment During the warranty period CORELIS will at its option either repair or replace products that prove to be defective For warranty service or repair this product must be returned to a service facility designated by CORELIS Outside CORELIS service travel areas warranty service will be performed at the Buyer s facility only upon CORELIS prior agreement and Buyer shall pay CORELIS round trip travel expenses For products returned to CORELIS for warranty service the Buyer shall prepay shipping charges to CORELIS and CORELIS shall pay shipping charges to return the product to the Buyer However the Buyer shall pay all shipping charges duties and taxes for products returned to CORELIS from another country CORELIS warrants that its software and firmware designated by CORELIS for use with an instrument will execute its programming instructions when properly installed on that instrument CORELIS does not warrant that the operation of the instrument software or firmware will be uninterrupted or error free The foregoing warranty shall not apply to defects resulting from i
15. es to be stored and type in a meaningful Merge Plan filename like Y our_Target_with_ScanPCI Your window should now look similar to Figure 5 15 Click on the Save button and the Merge Plan settings will be saved to the file that you specified and the merge process will begin All files generated by the merge process will be stored in the same directory as the mpf Merge Plan file Save As 2x Save in Compact PCI Board vl Behr File name Your_Target_with_ScanPC Save as type Merge Plan Files mpf v Cancel 4 Figure 5 15 Saving the Merge Plan file The Merge Status window will appear and provide ongoing status of the assembly merging process Part of the merge process involves copying the BSDL files cluster Signal Level SLF files and memory cluster Memory Information MIF files for each assembly to the merged target directory When ScanPlus Merge detects duplicate files a Confirm File Replace window will appear as shown in Figure 5 16 For this tutorial click on the Yes to All button which will cause ScanPlus Merge to automatically overwrite all duplicate files without asking Confirm File Replace x El This folder already contains a file named 4SIC280LW BSD F Would you like to replace the existing file i 26608 bytes A modified on Thursday August 08 1999 11 05 46 AM with this one 26608 bytes A modified on Thursday August 08 1999 11 05 46 AM Yes to All No No
16. gy file If the ScanPCI unit is connected to TAP2 as recommended then it is placed at the end of the topology file If the ScanPCI unit is connected to TAP1 then it is placed at the beginning of the topology file On the next page is an example of a topology file that describes a target system with a PCI card installed in the 3 3V PCI slot of a ScanPCI The two TAPs are chained together with a ScanTAP 4 Figure 4 1 shows the UUT s topology file before the ScanPCI module is added The modified topology file with the ScanPCI module connected to TAP 2 added is shown in Figure 4 2 Note how the reference designators in the topology file are prefixed by the assembly name from ScanPlus Merge The merged test generation files may then be compiled into test vectors with ScanPlus TPG as usual 5 14 Testing CompactPCI Cards Boundary Scan Chain Topology File Example for the ScanPCI CHAIN chainl DEVICES DEVICE ESE a PACKAGE gt BYPASS l EIG ES xc18v04_vq44 bsd vq4 4 NO CRECIERON xc2s200_fg456 bsd FG456 NO CPCI larget xc2s200_fg456 bsd FG456 NO END_DEVICES END_CHAIN Figure 5 18 Example Topology top File Before the ScanPCI is Added Boundary Scan Chain Topology File Example for the ScanPCI CH ENI AIN chain1 DEVICES DEVICE BSD Inge EA ie gt PACKAGE gt BYPASS CI teveciene 104 xc18v04_vq44 bsd
17. he target UUT can be connected to the boundary scan controller The method of connection depends on whether the TAP signals are brought to an external header or to the PCI card edge connector Target UUT TAP Connections on an External Header If the TAP signals from the target UUT are brought to a header the recommended and most common approach to use an external ScanTAP 4 Intelligent Pod to chain the Target UUT with the ScanPCI module Simply connect TAP1 from the pod to the TAP connector on the target UUT and connect TAP2 from the pod to the ScanPCI connector labeled TAP Figure 2 1 shows the TAP connections for the Target UUT on TAP1 and the ScanPCI module on TAP2 HOST COMPUTER SCANPCI SCANTAP 4 CONTROLLER POD Figure 2 1 Connection of the ScanPCI and the Target using Separate TAPs It is best to use a PCI 1149 1 Turbo equipped with a ScanTAP 4 Intelligent Pod with one TAP connected to the ScanPCI and with additional TAP s connected to the UUT However any Corelis controller with an appropriate version of the Buffer 1149 1 can also be used to connect to the UUT and the ScanPCI on separate TAPs For this mode both jumpers JP1 and JP2 should be installed 2 2 ScanPCI Installation An example of a UUT connected to the ScanPCI using a 2 TAP configuration is shown in Figure 2 2 Boundary Scan Test System Scan Chain 1 Chain 2 ScanPCI Figure 2 2 UUT Connection Example using Separate TAPs T
18. his file contains the merged netlists of the UUT and the Yout_Target_with_ScanPCI net CompactPCI Adapter It will be named after the Merge Plan file This file contains the merged topology files of the UUT Your_Target_with_ScanPCl top and the CompactPCI Adapter It will be named after the Merge Plan file This file contains the merged constraint files of the UUT Your_Target_with_ScanPCI con and the CompactPCI Adapter It will be named after the Merge Plan file This file contains the merged netlist edit files of the UUT Your_Target_with_ScanPCl edt and the CompactPCI Adapter It will be named after the Merge Plan file bsd Table 5 1 Files Created by the Merge Process Modifying the Topology File to Include the ScanPCl The assembly merging process is now complete but the topology file needs to be modified to include the ScanPCI in the scan chain Copy ScanPCI_3V bsd or ScanPCI_5V bsd from the supplied disk to your design directory Use ScanPCI_3V bsd when testing universal or 3 3V cPCI cards Use ScanPCI_5V bsd when testing 5V cPCI cards The next step is to add the ScanPCI module to the topology file and regenerate your test vectors In the topology file the ScanPCI module takes the reference designator of the cPCI to PCI adapter card edge connector J1 Note that how the ScanPCI and target UUT are connected to the boundary scan controller will determine the order that the components will appear in the topolo
19. igure the scan chain and the PCI clock See Table 3 1 When the TAP signals on the target UUT are present on the PCI card edge connector it is necessary to configure some jumpers to modify the ScanPCI scan chain JP1 should be installed when testing 5V cards and removed when testing 3 3V cards JP2 should be installed when testing 3 3V cards and removed when testing 5V cards When the UUT TAP signals are brought to an external connector both JP1 and JP2 should be installed If the target UUT requires a free running PCI clock for testing a clock can be generated by placing a shunt across JP3 JP4 is used to configure the built in oscillator that is used to provide the free running PCI clock If the UUT requires a 33MHz clock signal a shunt can be placed across pins 1 and 2 of JP4 If the UUT requires a 66MHz clock signal a shunt can be placed across pins 2 and 3 of JP4 JP3 must be installed to enable the clock setting chosen by JP4 Jumper Signal Description Default 1 2 Jumpers TDI to TDO actoss the 3 3V PCI connector jp 3 3V Slot This jumper should be removed when testing a 3 3V PCI card with the Jumper TAP signals on the PCI card edge connector and installed when testing a installed 5V PCI card JP1 should be installed when the TAP signals on the UUT are on an external header no matter which voltage the card is 1 2 Jumpers TDI to TDO across the 5V PCI connector jp2 5V Slot This jumper should be removed when testi
20. ly or through its authorized sales representative TABLE OF CONTENTS CHAPTER 1 PRODUCT OVERVIEW 1 1 Introduction eseesesenssssnsensensnonsnnsnnnnsennsnnssonnnssnnsnsnssnonsnssnnsnsnsnssnnsnsnnenssnssnnnsssnnesssnsssnssssessssssesssnnssssnnessonn 1 1 Required hardware and software zsressesssnensnsnnenssnsnsnnssnnnsnnsnnnsnnnssonsnssnnnnsenssnnsnnsnnnssenssnnsssonsnssnnssssnnensenenn 1 3 CHAPTER 2 SCANPCI INSTALLATION 2 1 Product ESmponentsi nen inneren lea ih Sn senlelesnerenepe SESER EOT EE a Ee 2 1 Whars onithe SRA 2 1 Connecting the Unit Under Test UUT to the ScanPCl zueessesssssssssensnennensnensnonsenssenssenssnnsnensnnnann 2 2 Connecting to the Boundary Scan Conttroller eseesssssssssssssssssnsnnssnnnnnnnsnnnnsnssnnnnssnsnnnnnnsnnnnssnsnnnnnsssnnnnnnn 2 2 Target UUT TAP Connections on an External Header ueneneeensesenssenensenensnnenennenennnnenennenennenenennenenn 2 2 Target UUT TAP Connections on the PCI Card edge Connector usenesennenensenensnenennenennnenenenen 2 3 CHAPTER 3 SCANPCI HARDWARE REFERENCE 3 1 Jumper Configuration ccsssessccersecssssessecessecesesenscecessecesesensesecsseeeesseessesenseeceseeessesenseecessaeeesseeenseeeesees 3 1 TAP Connector Pinout saneren aer A E a aE 3 2 Power Indicator LEDS 3 2 Specifications s ceccesierscesectestecesssai ciedssestes ci ici circa diciendo nie 3 3 ScanPCI Operating Characteristiecss2202 02 2222220222 2202 2 2222202 8 3 4 CHAPTER 4 PREPAR
21. mproper or inadequate maintenance by the Buyer Buyer supplied software or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the product or improper site preparation or maintenance NO OTHER WARRANTY IS EXPRESSED OR IMPLIED CORELIS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE EXCLUSIVE REMEDIES THE REMEDIES CONTAINED HEREIN ARE THE CUSTOMER S SOLE AND EXCLUSIVE REMEDIES CORELIS SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY Product maintenance agreements and other customer assistance agreements are available for Corelis products For assistance contact your nearest Corelis Sales and Service Office RETURN POLICY No items returned to CORELIS for watranty service or any other reason shall be accepted unless first authorized by CORELIS either direct or through its authorized sales representatives All returned items must be shipped pre paid and clearly display a Return Merchandise Authorization RMA number on the shipping carton Freight collect items will NOT be accepted Customers or authorized sales representatives must first contact CORELIS with notice of request for return of merchandise RMA s can only originate from CORELIS If authorization is granted an RMA number will be forwarded to the customer either direct
22. ng a 5V PCI card with the installed Jumper TAP signals on the PCI card edge connector and installed when testing a 3 3V PCI card JP2 should be installed when the TAP signals on the UUT are on an external header no matter which voltage the card is PCI 1 2 Enables a free running PCI clock JP3 Clock open Enable open Free running PCI clock is disabled PCI 1 2 Selects 33 MHz free running PCI Clock JP4 Clock 2 3 Selects 66 MHz free running PCI Clock open Select open Built in oscillators are disabled Table 3 1 Jumper Configuration ScanPCl Hardware Reference 3 1 TAP Connector Pinout The TAP connector on the ScanPCI conforms to the popular Corelis 10 pin dual row 5x2 connector pinout The pin assignment is standard allowing any Corelis boundary scan controller to connect to the ScanPCI using the appropriate 10 pin TAP cable Table 3 2 shows the pin assignments for the TAP connector Description O ea Test Data In E Ground Test Mode Select MON Ground zZ Ground Table 3 2 TAP Connector Connection List Power Indicator LEDs Two LEDs on the top of the ScanPCI unit labeled 3 3V and 5V illuminate when power is turned on 3 2 ScanPCI Hardware Reference Specifications Size 10 5 x 9 0 x 4 5 Status Indicators Power ON OFF indicator Output Logic Levels 3 3V CMOS 5V tolerant see Table 3 3 Input Logic Levels TTL see Table 3 3 Maximum TCK clock frequency 10 MHz
23. rowser find and select the ScanPCI_Selftest_inf cvf file Click OK Step 9 Select Controller from the Setup menu then choose the appropriate Boundary Scan controller and set the frequency to 1 MHz and the TAP voltage to 3 3V Make sure that the controller is configured to use TAP 1 Step 10 Select Run Test The test should run and pass Figure 6 1 shows a passing infrastructure test Executing Selftest with ScanPlus Runner 6 1 ScanPlus Runner Untitled File Setup Diagnostics View Help Test Steps AE 1 ScanPCI_Selftest_inf cvf Test Status Status M EE Total Runs 1 Passed Runs 1 Test Statistics Bun Test Close Figure 6 1 ScanPlus Runner Infrastructure Test Executing Selftest with ScanPlus Runner
24. system will automatically test the PCI card edge connector However regeneration of the interconnect tests using ScanPlusTPG with the relevant ScanPCI input files supplied on the floppy disk is required How to Generate Vectors using the ScanPCI Copy ScanPCI_3V bsd or ScanPCI_5V bsd from the supplied disk to your design directory Use ScanPCI_3V bsd when testing universal or 3 3V PCI cards Use ScanPCI_5V bsd when testing 5V PCI cards The next step is to add the ScanPCI module to the topology file and regenerate your test vectors In the topology file the ScanPCI module takes the reference designator of the PCI card edge connector from the schematic Note that how the ScanPCI and target UUT are connected to the boundary scan controller will determine the order that the components will appear in the topology file If the ScanPCI unit is connected to TAP2 as recommended then it is placed at the end of the topology file If the ScanPCI unit is connected to TAP1 then it is placed at the beginning of the topology file The next page shows an example topology file that describes a target system with a PCI card installed in the 3 3V PCI slot of a ScanPCI The two TAPs are chained together with a Scan TAP 4 Figure 4 1 shows the UUT s topology file before the ScanPCI module is added The modified topology file with the ScanPCI module connected to TAP 2 added is shown in Figure 4 2 Note In certain cases it may be required to modify the ne
25. tlist because some schematic capture programs use a separate reference designator for the front and back of the PCI card edge connector example PICS1 and P1SS1 If this is the case the easiest solution is to search for one reference designator and replace all cases of it with the other Preparation of Test Input Files 4 1 l Boundary Scan Chain Topology File l CHAIN chainl DEMIEGES DEMIE BSDL FILE gt PACKAGE gt BYPASS l U1 xc18v04_vq44 bsd vq44 NO U2 xc2s200_fg456 bsd FG456 NO U3 xc2s200_fg456 bsd FG456 NO l END_DEVICES END_CHAIN Figure 4 1 Example Topology top File Before the ScanPCI is Added Boundary Scan Chain Topology File Example for the ScanPCI CHAIN chainl DEVICES DEVICE BSDL IIb gt PACKAGE gt BYPASS l U1 xc18v04_vq44 bsd vq44 NO U2 xc2s200_fg456 bsd FG456 NO U3 xc2s200_fg456 bsd FG456 NO PICS1 ScanPCI_3V bsd PCI_CONN NO END_DEVICES END_CHAIN Figure 4 2 Example Topology top File After the ScanPCI is Added Preparation of Test Input Files Chapter 5 Testing CompactPCl Cards How to use the ScanPC1 with the ScanPlus boundary scan tools to test CompactPCI Cards Introduction With the use of a CompactPCI to PCI adapter the ScanPCI can easily be used to test CompactPCI cPCI cards A cPCI to PCI
26. to All Cancel Figure 5 16 Confirm File Replace Window 5 12 Testing CompactPCI Cards When the merge process is complete as shown in Figure 5 17 click on the OK command button to close the Merge Status window The main ScanPlus Merge window will then be displayed again Merge Status iof xi Status Messages STARTING THE MERGE PROCESS Destination directory is C Targets Compact PCI Board Loading Netlist C Targets Compact PCI Board Compact PCI Board net Loading Netlist C Targets Compact PCI Board CPCI Adapter NET Merging Netlists Creating Merged Netlist C Targets Compact PCI Board Your_Target_with_ScanPCl net Creating Merged Topology file C Targets Compact PCI Board Your_Target_with_ScanPCI top Loading Topology file C Targets Compact PCI Boardi Compact PCI Board top Copying BSDL file C Targets Compact PCI Board xcs30_PQ208 bsd Processing System Connection File C Targets Compact PCI Board Compact PCI Board sco Creating Master Netlist Edit file CTargets Compact PCI Board Your_Target_with_ScanPCl edt Merge complete Figure 5 17 Merge Status Window Indicating Completion Testing CompactPCl Cards 5 13 When the merge process is complete all of the resulting files are placed in the directory where the Merge Plan file mpf was saved Table 5 1 shows a list of all files created by the merge process Required Files Description BSDL file s which describe the boundary scan components T
27. tware Disk Please ensure that all materials listed are present and free from visible damage or defects before proceeding If anything appears to be missing or damaged contact Corelis at the number listed in the front of the manual immediately What s on the Disk The disk contains the following test vector generation files Filename Description ScanPCI_3V bsd BSDL file for the 3 3V ScanPCI connector ScanPCI_5V bsd BSDL file for the 5V ScanPCI connector ScanPCI top An example topology file for the ScanPCI cPCI_adapter net Netlist for the CompactPCI to PCI adapter System Connection file for the CompactPCI to PCI Compact_PCI_Board sco adapter Used by ScanPlus Merge to combine the netlists from the UUT and cPCI to PCI adapter An infrastructure test for a ScanPCI with nothing connected to its PCI connectors and JP1 and JP2 installed It is used with ScanPlus Runner as a basic self test of the ScanPCI ScanPCI_Selftest_inf cvf Table 2 1 Files on the Provided Software Disk ScanPCI Installation 2 1 Connecting the Unit Under Test UUT to the ScanPCI If the target UUT is designed to be a universal PCI card or to use 3 3 volts install the card in the ScanPCI socket connector labeled 3 3V PCT If the UUT is designed to use 5 volts install the card in the ScanPCI socket connector labeled SV PCT Connecting to the Boundary Scan Controller There are two ways that the TAP from t
28. with a Single IP 2 3 UUT Connection Example Using a Single TAP nenn ah ee 24 Example Topology tob File Before the ScanPCI is Added 4 2 Example Topology top File After the ScanPCI is Added 4 2 BOGE IS Meroe Maim ADD A iaa 5 2 ScanPlus Merge Mam Window with a New Assemhh aa asi 5 3 ScanPlus Merge Main Window Showing Renamed UUT Assembly neeeenesenesenenenenenenen 5 4 Assembly Details Window for the UUT Assembly sun 5 5 Assembly Details Window with Netlist File Row Selected u a lan 5 5 UUT Netlist File Seleited a en innana RR 5 6 UUT Topology LED ebenen NE AAA a 5 6 ScanPlus Merge Main Window with a Second Assembly Added 5 7 ScanPlus Merge Main Window Showing Renamed Assembly ossessi 5 8 ARI WE alada sde NONATO a 5 9 Assembly Details after Test Step files added ados 5 9 Sjem Conneton A 5 10 System Connection File Browsing Window a 5 10 ScanPlus Merge Main Window with System Connection File sussies 5 11 Saving the Merge INTA A A 5 12 CONTI File Replace Window season 5 12 Merge Status Window Indicating COMPOTION sso ski 5 13 Example Topology tab File Before the ScanPCI is Adnan 5 15 Example Topology top file After the ScanPCI is Add io ai 5 15 CAE TUS AS RACE IRSA Tofo tain ahnen 6 2 Table of Tables Table 3 2 Files on the Provided So tware Dig 2 1 Table 3 4 Jumper CON TOUFANON dos 3 1 Table 3 2 TAP E Lee se aaa 3 2 Fable 3 3 PROS Tevel C WGP Achera stits AS ee 3 3 Table 3 4 ScanPCI Operating Ch
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