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User Manual - MediaLB Interface Test Bench

1. Cn em mitb 19330 1024fs m syscmd setup txt Manual setup of test via Files mitb 19330 1024fs m syscmd start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pan Speed Data Type Channel Address CI SAU PCO 0x01FE PC1 0x0000 Device 3 Pin 1024xFs none PC2 0x0000 PC31 0x0000 DUT DUT MediaLB DUTMOST RS232 Port Target Interface Clock cece Mode Speed Sai 3 Pin 1024xFs 0101h System Command Test Tab System No System e Command Commands Commands MOSTLock 5 100 MOSTUnLock 10 10 MLBReset 1916 200 Table 8 107 mitb t9330 3pin 1024fs m syscmd User Manual Copyright O 2011 SMSC Page 196 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cSnmnsc V2 2 X 8 7 2 mitb t9640 6pin 2048fs m syscmd 1024xFs test with generation of system commands MediaLB Port open without any Channel Addresses Description No data transfer MOSTLock MOSTUnLock and MLBReset commands generated one after the other with a 2 second gap in between mitb 19640 204815 syscmd setup txt Manual setup of test via E mitb 19640 2048fs m syscmd start txt GUI possible ediaL B atio Interface Clock Transferred Physical Channel Pari Mace Mode Speed Data Type Ch
2. 32 Trigger cei 33 Trigger Evelib EIE IE er 33 LOOPBACK 34 Ethernet Connection MITB Platform and Host 36 IP Address Configuration on Host 37 Verify Connection to MITB 38 Load FPGA Image File to MITB Platform 39 Flash FPGA Image to MITB Platform 39 Verify Connection to MITB 40 Load Pattern Generator amp Analyzer Firmware to MITB Platform 41 Flash Pattern Generator amp Analyzer to MITB 41 SEI 43 Configuration Tab EE 44 Control aes ein is dein 46 Asynchronous Tab wad eee eee euet 50 Synchronous Ez lo pee E 54 isochronous Tab 57 System Commands 61 Control Message Format 2 2 65 Data Packet Format reete lite eed 67 Ethernet Packet Format 69 Synchronous Byte Counter 71 Synchronous Random 71 Isochronous Packet Format 72 User Manual
3. 17 D MediaLB 3 Pin port testing Phy Board Variant 13 27 Differential MediaLB 6 Pin interface 17 MediaLB 6 Pin clock 17 MediaLB 6 Pin interface 11 F MediaLB 6 Pin port testing Phy Board Variant 1 13 27 11 MediaLB Analyzer CP 11 28 FPGA Configuration DONE LED 26 MediaLB device 12 26 MediaLB Device Setup EE 11 12 22 VG GIS AY cs utei EE 13 G MediaLB 3 6 12 Phy Board Variant 1 13 Graphical User 10 Phy Board Variant 3 13 em 10 RS232 interface 12 Asynchronous 42 Status 13 Configuration tab 42 User hardware requirements 13 2 42 XILINX Virtex4 FX60 FPGA 13 ISOCHFONOUS 42 MEP TOF Mal eren th 67 Syn
4. 13 15 Walking Byte 69 70 X XILINX Virtex4 FX60 FPGA 13 15 Copyright O 2011 SMSC Document Version V2 2 X Date 2011 12 0902 User Manual Page 209
5. Table 8 11 mitb_t1336_3pin_1024fs_c_1q User Manual Copyright 2011 SMSC Page 86 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 8 2 9 11337 1024145 14 The purpose this test is to verify the correct behavior of the MediaLB DUT in case it is transmitting control data and the receiving device 0581110 connected to the MDUT is responding with ReceiverProtocolError responses After the data transfer is started the MITB will generate 20 ReceiverProtocolError responses the Control Rx Channel ChannelAddress 0x0002 of the 0581110 ReceiverProtocolError responses are generated with a delay of 100 ms between consecutive ReceiverProtocolError The MDUT transmitting control messages needs to detect the ReceiverProtocolError responses Following the detection of the ReceiverProtocolError the MDUT must stop message transmission following the MediaLB protocol defined in the MediaLB spec The user needs to verify manually that the MDUT is properly terminating the message transmission Additionally it may be verified if MDUT internally a status indicating the detection of the ReceiverProtocolError response is signalled properly The MITB does not provide an indication if the MDUT is handling the HeceiverProtocolError as expected To verify the MDUT behavior and capture the generated HeceiverProtocolError responses generated by the MITB it
6. 22 2 5 2 MOST150 Device Setup 23 26 Funber Roading TERRE 24 3 COMPONENT 25 3 1 MediaLB Interface Test Bench Platform 25 3 2 Physical Interface Board 0581110 Phy 27 3 3 INIC Explorer Interface BOX 27 3 4 MediabB Analy Zen vic rte des ted eee 28 252 acude 28 3 6 28 3 6 1 Configuration Debug 29 3 6 2 Board 30 3 6 3 MediaLB 3 6 Pin High Speed Debug 32 3 6 4 Trigger Connector irae trie biete 33 3 7 MediaLB Device Under Test rasieren 34 374 Loop Back Functionality 34 4 SET UP THE TEST 35 4 1 Connect MITB Platform to Host 35 4 2 Connect MITB Platform to User Hardware 35 4 3 Connect INIC Explorer Interface 35 4 4 Connect MediaLB Analyzer 35 5 FLASHING THE MITB
7. 3 Phys Board Variant 1 Status Ed LEDs lt MediaLB 3 6 pin High Speed Debug Header MediaLB Interface Test Bench MITB User Hardware Figure 2 2 MOST150 Device Setup The MOST150 Device Setup is applicable in case the user hardware is realizing a MOST150 device This requires that on the user hardware the MDUT is integrated as well as an OS81110 MOST150 transceiver chip and an optical MOST150 network interface The MITB and the user hardware are connected via an optical MOST150 network A MediaLB 3 Pin and or a 6 Pin interface is used to connect the MDUT and the OS81110 INIC MediaLB controller on the user hardware Configured as a MOST150 Device Setup the MITB provides two main interfaces RS232 interface o Main interface to the GUI running on the host PC o Enables configuration of PGA software and definition of generated test patterns o Used to pass test results to host PC e Optical MOST150 interface o Realized by a Phy Board o Used to connect customer MOST150 device which incorporates MDUT User Manual Copyright 2011 SMSC Page 14 Document Version 2 2 Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X Additionally the MITB provides the following main components e XILINX Virtex4 FX60 FPGA including o PowerPC used to run the PGA o MediaLB Device Interface Macro featuring a differential MediaLB 6 Pin port o RS232 interface for conne
8. 36 5 1 SetuplP Address on Host PG ttn ehe Da 37 5 2 Flash FPGA Imagerie dete inpr nnde 38 5 3 Flash Pattern Generator amp 40 6 CONFIGURE THE TEST BENCH 43 6 1 Execute the Graphical User 43 6 2 Description of the Graphical User 43 6 2 1 44 6 2 2 Control 46 623 50 6 2 4 Synchronous 54 5 2 5 isochronous A 57 Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 5 MediaLB Interface Test Bench e smsc V2 2 X 6 2 6 System Commands 61 6 3 QGonfiguration 62 631 62 6 3 2 Load Configuration Files erret trente irte e 63 6 45 LOG 64 7 TEST PATTERN FORMATS 2c ren cucina ce pae 65 7 1 Control Message Form
9. Messages RS232 to Host PC Baudra TET FPGA Configuration Done Dota 8 b 2 FPGA PowerPC Parity None PGA Pattern Generator PGA Active LED 0 0 PHY2 Active LED 2 Power Supply 12 3 On Off Switch 5 V Power LED PHY2 Phy Board Co PHY2 3 3 V Power LEC PHY2 MOST Lock LED PHY2 MediaLB Lock LED LCD Display 4 X 16 Characters Trigger Connector Figure 6 1 GUI Main Window The GUI features several tabs including e Configuration tab Defines general configuration parameters Control tab Defines parameters for control message tests e Asynchronous tab Defines parameters for asynchronous packet tests Synchronous tab Defines parameters for synchronous streaming data tests e sochronous tab Defines parameters for isochronous data tests System Commands tab Defines parameters to generate system commands Copyright O 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 43 MediaLB Interface Test Bench e lt lt V2 2 X 6 2 1 Configuration Tab The following figure shows the configuration tab of the GUI 1 i GUI V220 MTR MediaLB Interface Test Bench Pattern Generator and Analyzer GUI V2 2 0 Configuration Control Asynchronous Synchronous Isochronous System Commands Status Initialization Configuration General
10. 74 Table 8 2 Control Test Overview Part 2 75 Table 8 3 Control Test Overview Part 3 76 Table 8 4 11310 256fs 14 77 Table 8 5 11320 51216 18 78 Table 8 6 11330 102446 14 79 Table 8 7 11331 102415 14 80 Table 8 8 11332 3pin 102446 114 81 Table 8 9 11333 102448 82 Table 8 10 mitb 11335 10246 1 84 Table 8 11 mitb 11336 102415 10 86 Table 8 12 mitb 11337 10246 1 88 Table 8 13 mitb 11338 102416 14 90 Table 8 14 mitb 11640 2048fs 1484 91 Table 8 15 11641 2048fs 10 93 Table 8 16 mitb 11642 2048fs 10 95 Table 8 17 mitb 11643 204815 1484 97 Table 8 18 mitb 11644 204815 10 99 8 19 11650 307215 eee 100 8 20 mitb 11651 6pin 307215 18 ttt reete ence 101 8 21 11660 409615 18 102
11. 148 8 4 6 mitb t3333 1024s 5 iiic iere deett der eret dete Pe de E ree di 149 8 47 mitb 13334 102415 5 YQ ciento eee tee tre 150 8 4 8 mitb t3335 3pin 1024fs s 151 8 4 9 mitb 13640 2048fs s 152 8 4 10 13641 6pin 2048fs s 150 153 8 4 11 mitb 13642 2048fs s 44 154 8 4 12 mitb 13650 3072fs s 14 155 8 4 13 mitb 13651 3072fs s 15 156 8 4 14 mitb 13660 4096fs s 14 157 8 4 15 mitb 13661 6pin 4096fs s 154 158 8 5 ISOCHFONOUS Tesis PO 159 8 5 1 14310 256fs i 1 161 8 5 2 mitb 14320 51216 176022000050 00 162 8 5 3 mitb 14330 3pin 10241S 1 16 2 Co bs ie eee 163 8 5 4 14331 3 102416 1 76 164 8 5 5 143392 102416 1 76 torno E dae es heeds 165 8 5 6 mitb 14333 10241512154 E 166 8 5 7 mith 14394 Spin 102416 12156250005 167 8 5 8 mith 14337 Spin 102418 12150 e 168 8 5 9 mitb 14640 204818 18 169 8 5 10 14641 6pin 2048fs
12. Frame 3 0x00 0x00 0x00 0x02 0x06 0x07 0x08 0 09 0x00 1 1 1 1 P 1 Y 3 Frame Counter Data Bytes Figure 7 4 Synchronous Byte Counter Format Quadlet 1 Quadlet 2 Quadlet 3 5 Quadlet 1 Keil ot 1 E Frame 0x00 0x00 0x00 0x00 0 56 OxFF 0x00 0 08 OE XFF OX0B 1 Frame 2 0x00 0x00 0x00 OxES 7 0x44 0x67 OB OE Frame 3 0x00 0x00 0x00 0x02 0x06 0x08 0x22 0 0 0 88 Ox4C Ox8B 1 Frame Counter Data Bytes Figure 7 5 Synchronous Random Format Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 71 MediaLB Interface Test Bench e smsc V2 2 X 7 4 Isochronous Packet Format Isochronous data is transferred in packets The MITB supports the generation of isochronous packets with the fixed length of 188 bytes or 196 bytes To identify transferred packets every packet incorporates a 32 bit packet index The data bytes support the pattern types Walking Byte and Random 4 bytes 188 or 184 196 at bytes 192 data bytes Packet Index Data Bytes Figure 7 6 Isochronous Packet Format Packet Index 32
13. Figure 6 7 System Commands Tab 6 2 6 1 System Commands Tab Parameters Parameters and buttons of the system commands tab are described in the table below Description System Command MediaLB System Command to be generated No of System Number of system commands to be generated Commands Delay System Approximate delay between the generation of consecutive system Commands commands in ms Generate Cmd Button to manually start the generation of the MediaLB System Commands Table 6 14 System Commands Tab Parameters Hint Once the Generate button is clicked the generation of System Commands is stopped after the number of adjusted commands is generated or the Initialize MITB button on the configuration tab has been clicked Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 61 MediaLB Interface Test Bench e smsc V2 2 X 6 3 Configuration Sequence To configure the MITB and execute a test two approaches are possible e Manual configuration e Load configuration files Both approaches are described in detail in the following sections 6 3 1 Manual Configuration At manual configuration the user needs to enter the test parameters on the GUI Tests are started and terminated by clicking the respective Start Stop button For manual configuration the following sequence is recommended Step 1 Configure MITB Step 1 1 Select configuration tab se
14. SUCCESS BY DESIGN Copyright 2011 SMSC Multimedia and Control Networking Technology MediaLB Interface Test Bench V2 2 X User Manual Document Information Version V2 2 X 1d0 Date 2011 12 09 MOST Media Oriented Systems Transport MediaLB Interface Test Bench er smsc V2 2 X Further Information For more information on SMSC s automotive products including integrated circuits software and MOST development tools and modules visit our web site http www smsc ais com Direct contact information is available at http www smsc ais com offices SMSC Europe GmbH Bannwaldallee 48 76185 Karlsruhe GERMANY SMSC 80 Arkay Drive Hauppauge New York 11788 USA Technical Support Contact information for technical support is available at http Awww smsc ais com contact Legend Copyright O 2011 SMSC All rights reserved Please make sure that all information within a document marked as Confidential or Restricted Access is handled solely in accordance with the agreement pursuant to which it is provided and is not reproduced or disclosed to others without the prior written consent of SMSC The confidential ranking of a document can be found in the footer of every page This document supersedes and replaces all information previously supplied The technical information in this document loses its validity with the next edition Although the information is believed to be accurate no responsibility is a
15. 2048fs a 44 134 mit 12645 6pin 204815 a 18 tete nte eb erret 136 mitb 12646 204815 a 44 138 12650 3072fs a 14 139 MUL 126 51 6 307 215 84 24 i eria sp tenta side da 140 mitb 12660 2048fs 14 141 Synchronous Test Overview Part 1 142 Synchronous Test Overview 2 143 mitb 3310 3pin 25619 S 144 mitb 13820 3 512158 S ana rre 145 _13330_3 _102415_5 14 146 mitb 13331 102416 S 30 147 mitb 13332 3pin 102415 S 30 ette tte fee 148 3883 301 1028415 5 702 toic ote Pug eb be iets 149 19934 10245 S 74 150 19935 1024156 S 1505 151 mitb 19640 204815 5 14 152 3641 6 204815 5 158 pete rata ce 153 19642 204815 25 442 154 mitb 13650 307215 S 1 155 3651 6pin 307218 S
16. Length Length Length oss Length bytes bytes bytes 9 Disable 45 Continuous Test Duration Throughput Message Delay RxResp Test msgs msgs s Counter Peni ine Nip ms Disable 5000 500 Enable Byte Counter ReceiverBreak 5 100 Table 8 16 mitb_t1642_6pin_2048fs_c_1q Copyright 2011 SMSC User Manual Page 95 MediaLB Interface Test Bench e smsc V2 2 X 8 2 14 11643 2048fs 14 The purpose of this test is to verify the correct behavior of the MediaLB DUT case it is transmitting control data and the receiving device 0581110 connected to the MDUT is responding with ReceiverProtocolError responses After the data transfer is started the MITB will generate 20 ReceiverProtocolError responses the Control Rx Channel ChannelAddress 0x0002 of the 0581110 ReceiverProtocolError responses are generated with a delay of 100 ms between consecutive ReceiverProtocolError The MDUT transmitting control messages needs to detect the ReceiverProtocolError responses Following the detection of the ReceiverProtocolError the MDUT must stop message transmission following the MediaLB protocol defined in the MediaLB spec The user needs to verify manually that the MDUT is properly terminating the message transmission Additionally it may be verified if MDUT internally a status indicating the detection of the ReceiverProtocolError response is signalled properly The MITB does not provide an indi
17. pesos ll Blockwidth 2 x 3 quadlet per frame CA 0x003C 8 e 278 mitb 13331 102415 s 3 setup txt Manual setup of test via E oS mitb 13331 1024fs s start txt GUI possible D ediaL B atio Interface Clock Transferred Physical Channel Boote Mode Speed Data Types Channel Address 27 PCO 0x01FE PC1 0x003C Syne Rx 2 0x003E Sync Tx PC3 0x003C Sync Rx Device 3 Pin 1024xFs Sync PC4 0x003C Sync Rx 5 0x003E Sync Tx PC6 0x003E Sync Tx PC31 0x0000 PGA GUI Configuration Configuration Tab DUT ee 5232 MediaLB Clock Target Pin Mode Speed Address 3 Pin 1024xFs 0101h Tx Rx Blockwidth Channel Channel quadlets uud Address Address frame yp Byte 0x003C 0x003E 3 Counter Table 8 58 13331 1024fs s 34 Copyright 2011 SMSC Document Version V2 2 X Date 2011 12 0902 User Manual Page 147 MediaLB Interface Test Bench e smsc V2 2 X 8 4 5 mitb t3332 3pin 1024fs s 34 1024xFs test with alternating ChannelAddresses mS Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x quadlet per frame CA 0x003C amp CA 0x003E mitb_t3332_3pin_1024fs_s 3q setup txt Manual setup of test via es mitb_t333
18. PCO 0x01FE PC1 0x0004 Control Tx PC2 0x0002 Control Rx PC3 0x0006 Rx Device 6 Pin 2048xFs Control Async Sync PC4 0x0008 Async Tx PC5 0 000 Sync Rx PC6 0x000C Sync Tx PC57 0x0000 DUT DUT DUT MOST RS232 Port MediaLB MediaLB Target Interface Clock Address Mode Speed 6 2048 0101h Control Data Test Tab Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum 5 Message Length Length Length E Length bytes bytes bytes 9 Disable 8 Continuous mom Throughput Message Pattern Test msgs msgs s Counter Type Disable 10000 450 Enable Counter Table 8 99 mitb_t5640_6pin_2048fs_cas Part 1 User Manual Copyright 2011 SMSC Page 188 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X Basic 2048xFs test Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous data hes E Blockwidth 2 x 1 quadlet per frame per loopback Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s TM LE mitb 15640 6pin 2048fs cas cfg setup txt Manual setup of test via e mitb 15640 6pin 2048fs cas cfg start txt GUI possible ono Vata D Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimu
19. Speed 6 4096xFs 0101h Asynchronous Data Test Tab Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum Packet Length Length Length dion i Length bytes bytes bytes Disable 32 Test Packet E Duration Delay dus 27 5 us yte Enable 5000 2000 Enable Counter Table 8 52 mitb_t2660_6pin_2048fs_a_1q Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 141 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 4 Synchronous Tests The following table provides an overview of available synchronous data tests Test Test Characteristics MediaLB 3 pin Tests mitb_t3310_3pin_256fs_s_1q Basic 256xFs test Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame mitb_t3320_3pin_512fs_s_1q Basic 512xFs test Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame mitb_t3330_3pin_1024fs_s_1q Basic 1024xFs test Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame mitb_t3331_3pin_1024fs_s_3q 1024xFs test with alternating Tx Rx ChannelAddresses Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 3 quadlet per frame 0 003 amp CA 0x003E mitb_t3332_3pin_1024fs_s_3q 1024xFs
20. M T MediaLB Interface Test Bench Pattern Generator and Analyzer GUI V2 2 0 Configuration Control Asynchronous Synchrono s isochronous System Comman Synchronous Data Test Tx ChannelAddress Dooa Rx ChannelAddress loooc hex Start Test Blockwidth h quadlets frame PGA Statistics n a Pattern Generator and Analyzer Results Pattern Generator and Analyzer Statistics Pattern Type Byte Counter Clear Logs Configuration and Debug Messages Clear Log PGA s Synchronous Results Log PGA s Synchronous Statistics Log Figure 6 5 Synchronous Tab User Manual Copyright 2011 SMSC Page 54 Document Version 2 2 Date 2011 12 09 MediaLB Interface Test Bench e lt lt V2 2 X 6 2 4 1 Synchronous Tab Parameters Parameters and buttons of the synchronous tab are described in the table below Description Tx ChannelAddress MediaLB ChannelAddress which the synchronous test pattern is transmitted by the 0581110 connected to the MDUT Rx ChannelAddress MediaLB ChannelAddress on which the synchronous test pattern is received by the 0581110 connected to the MDUT Blockwidth Number of quadlets allocated per MediaLB frame for the transmission and reception of the synchronous test pattern Depending on the MediaLB speed the bandwidth ranges from 1 to 15 quadlets per frame For details about pattern formats refer to chapter 7 Te
21. MediaLB Interface Test Bench e cnmnsc V2 2 X 8 2 3 11330 1024fs 14 Basic 1024xFs test Concurrent Rx and Tx transfer of MediaLB control data Description Blockwidth 2 x 1 quadlet per frame Fixed Message Length 28 Bytes Throughput 450 msgs s AE e mitb t1330 3pin 1024fs c 1q cfg setup txt Manual setup of test via E mitb t1330 1024fs 1q start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pan ede Mode Speed Data Type Channel Address sen 0x01FE PC1 0x0004 Control Tx Device 3 Pin 1024xFs Control PC2 0x0002 Control Rx PC31 0x003E DUT DUT Oat oe Interface Clock Ad des Mode Speed mom 3 Pin 1024xFs 0101h O ol Da D Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum Repetitions Message Length Length Length bytes x 5 Length bytes bytes bytes 9 Disable 28 Continuous Throughput Message Pattern Test msgs msgs s Counter Type Disable 5000 450 Enable Counter Table 8 6 mitb_t1330_3pin_1024fs_c_1q Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 79 MediaLB Interface Test Bench V2 2 X 8 2 4 mitb t1331 3pin 1024fs c 1q 1024xFs test with min and max Message Length Concurrent Rx and Tx transfer of
22. Table 8 77 mitb 14333 3pin 1024fs i 159 User Manual Copyright O 2011 SMSC Page 166 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X 8 5 7 mitb t4334 3pin 1024fs 154 1024xFs test with Packet Size 196 Bytes smsc Description Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 15 quadlet per frame EU m mitb 14334 1024fs 154 setup txt Manual setup of test via s mitb 14334 1024fs i 154 start txt GUI possible D ediaL B atio Interface Clock Transferred Physical Channel Par Meze Mode Speed Data Types Channel Address 0x01FE PC1 0x000E Isoc Rx PC15 0x000E Isoc Rx Device 3 Pin 1024xFs Isoc PC16 0x0010 Isoc Tx PC30 0x0010 Isoc Tx 1 0x0000 DUT DUT MOST RS232 Port MediaLB Clock Target Pin Mode Speed Address pee 3 Pin 1024xFs 0101h configurable Isochronous Data Test Tab Tx Rx Blockwidth Channel Channel quadlets Flow Control Pada Throughput bytes 5 Address Address frame kbit s 0 000 0 0010 15 Disable 196 1000 Continuous SET Packet Pattern Test okts Counter Type 2 Disable 5000 Enable Counter Table 8 78 mitb 14334 3pin 1024fs i 159 Copyright O 2011 SMSC Document Version V2 2 X Date 2011 12 0902 User Manual Page 167 MediaLB Interface
23. 1024fs a 14 indicates in most cases a TEST PASS the MITB GUI This behavior relates to the length of the ReceiverBusy periods as well as to the MDUT packet buffer size In some cases the MITB test case mitb 12338 1024fs a 1q might indicate a TEST FAILED with missing messages in the MITB GUI This behavior is expected and is related to the nature of the MOST network and the OS81110 as well as to the packet buffer size on the MDUT During the ReceiverBusy periods the OS81110 will not receive data from the MDUT via MediaLB Since loop back application of the MDUT cannot transmit any data it also will only be able to receive a certain amount of new packets from the OS81110 via MediaLB and the MITB respectively Large packet buffers allow the MDUT to keep receiving more packets where as with small packet buffers the MDUT will stop receiving data quite fast This again results in the OS81110 holding of messages received via MOST from the MITB platform Depending on how long the ReceiverBusy period lasts and how deep the MDUT packet buffers are the OS81110 buffers will run full and packets transmitted from MITB platform to OS81110 via MOST will get lost on the MOST network There is no such thing as a ReceiverBusy response on MOST Because of this no feedback from the OS81110 connected to the DUT is passed to the OS81110 on the MITB platform indicating the buffer full condition of the DUT OS81110 and the MITB keeps transmitting pac
24. 4096xF s test with maximum bandwidth Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 15 quadlet per frame Description Test Configuration mitb 13661 6pin 4096fs 5 154 setup txt Manual setup of test via Files mitb 13661 6pin 409615 s 154 start txt GUI possible ediaLb Interface Clock Transferred Physical Channel PON Mede Mode Speed Data Types Channel Address Allocated een 0x01FE PC1 0x000A Sync Rx PC15 0x000A Sync Rx Device 6 Pin 4096xFs Sync PC16 0x000C Sync Tx PC30 0x000C Sync Tx PC116 0x0000 DUT eee RS232 Port MediaLB Clock Target Pin Mode Speed Address User configurable 6 Pin 4096xFs 0101h Synchronous Data Test Tab Tx Rx Blockwidth Channel Channel quadlets uns dd Address Address frame 0x000A 0x000C 15 Enable Gaunt Table 8 69 mitb_t3661_6pin_4096fs_s_15q User Manual Copyright O 2011 SMSC Page 158 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 5 Isochronous Tests The following table provides an overview of available isochronous data tests Test Name Test Characteristics MediaLB 3 pin Tests 14310_3pin_256fs_i_1q Basic 256xFs test Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 1 quadlet per frame mitb 14320 51216 14 Basic 512xFs test Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x
25. 8 22 mitb 11661 4096fs 18 tme dn 103 Table 8 23 Asynchronous Test Overview Part 1 104 Table 8 24 Asynchronous Test Overview Part 2 105 Table 8 25 Asynchronous Test Overview Part 3 106 Table 8 26 Asynchronous Test Overview Part 4 22 4 1 2 12010 0 00 0000 0 107 Table 8 27 mitb 12310 256 a 14 108 Table 8 28 mitb 12320 512fs 14 109 Table 8 29 mitb 12321 512fs 7Q essere a 110 Table 8 30 mitb 12330 102416 14 111 Table 8 31 mitb 12331 102416 a 154 112 Table 8 32 mitb 12332 102416 5 113 Table 8 33 mitb 12333 102416 15 1 114 Table 8 34 mitb 12333 1024156 15 115 Table 8 35 mitb 12334 102416 15 116 Table 8 36 mitb 12334 102415 1548 117 Table 8 37 mitb 12335 102446 a 10 118 Copyright 2011 SMSC Document Version 2 2 Date 2011 12 0902 User Manual Page 205 MediaLB Interface Test Bench e smsc V2 2 X Table 8 38
26. Mediol B sob Pin13 No Connect 14 11 MLBSP 12 9 MLBSN zi Pin10 MLBD Pin7 No Connect Pin8 No Connect 5 MLBS _ Pin3 MLBCKP Pin4 No Connect Pint MLBCKN 2 MLBCLK N GND Figure 3 4 MediaLB 3 6 Pin High Speed Debug Header At a MOST150 Device Setup the MediaLB debug header needs to be available on the user hardware to enable the connection of a MediaLB Analyzer If the MITB is used in MediaLB Device Setup the MediaLB debug header does not need to be available on the user hardware because a MediaLB Analyzer can be directly connected to the Phy Board plugged on the user hardware User Manual Copyright 2011 SMSC Page 32 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e smscC V2 2 X 3 6 4 Trigger Connector The trigger connector is available on the MITB platform It features four trigger output signals For every MediaLB data type the PGA is asserting one of the trigger signals in case an error is detected in the received data stream Connected to either an oscilloscope or the high speed trigger input of a MediaLB Analyzer the trigger signals can be used to capture error conditions V Pint No connect Pin2 No connect HE Trigger Output Signals Pin3 Pin4 Pin7 No connect Pin8 No connect No connect P
27. Packet 16 bit field indicating the total number of bytes which follow in the Port Message Length Body PMB including the two bytes of Packet Length itself Packet Length can be adjusted in the MITB GUI Minimum value 6 bytes Maximum value 1506 bytes Packet Index 32 bit field representing a packet counter which is incremented for each transmitted packet Data Data bytes with pattern type Byte Counter or Random Number of data bytes can vary from 0 to 1504 bytes Pattern Type Byte Counter Packet Index 00 00 00 00 00 00 00 01 00 00 00 02 Packet 1 Packet 2 Packet 3 Pattern Type Random Packet Index Packet 1 00 00 00 00 Packet 2 00 00 00 01 00 00 00 02 Table 7 3 MEP Format Description User Manual Copyright 2011 SMSC Page 70 Document Version 2 2 Date 2011 12 09 MediaLB Interface Test Bench e V2 2 X 7 3 Synchronous Pattern Format Synchronous data is transferred in frames To identify transferred frames every frame incorporates a 32 bit frame counter in the first quadlet of a frame The following data bytes support the pattern types Walking Byte and Random Quadlet 1 Quadlet 2 Quadlet ae Quadlet n l 1 l 1 E Frame 0x00 0x00 0x00 0 00 0x04 0x05 0x06 0507 0 08 Oxo XOA 908 1 22 Frame 2 0x00 0 00 0x00 0x05 0 06 0x07 0x08 009 000
28. Since the OS81110 is generating ReceiverBreak responses randomly it cannot be guaranteed that the ReceiverBreak responses always happen at times when the MDUT is transmitting control messages By that means it is not guaranteed that MediaLB commands 0x30 0x32 and 0x34 transmitted by the MDUT are acknowledged by HeceiverBreak responses It might happen that the ReceiverBreak responses are present on the bus when NoData commands are transmitted by the MDUT In that case the HeceiverBreak responses have no effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverBreak response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case 11336 1024fs 14 indicates a TEST FAILED with missing messages in the MITB GUI for most cases This behavior is expected and entirely depends on the customer specific DUT system re transmission mechanisms If the OS81110 generates ReceiverBreak response message reception is terminated and the broken message will be lost In case the MDUT does not re transmit the broken message the MITB will indicate a missing message and TEST FAILED If the broken message is re transmitted by the MDUT after receiving the ReceiverBreak response the MITB will not detect any errors Copyright O 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 85 MediaLB Interface
29. To verify the MDUT behavior and capture the generated HeceiverBreak responses generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the OS81110 is generating ReceiverBreak responses randomly it cannot be guaranteed that the ReceiverBreak responses always happen at times when the MDUT is transmitting control messages By that means it is not guaranteed that MediaLB commands 0x30 0x32 and 0x34 transmitted by the MDUT are acknowledged by HeceiverBreak responses It might happen that the ReceiverBreak responses are present on the bus when NoData commands are transmitted by the MDUT In that case the HeceiverBreak responses have no effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverBreak response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb t1642 6pin 2048fs c 1q indicates a TEST FAILED with missing messages in the MITB GUI for most cases This behavior is expected and entirely depends on the customer specific DUT system re transmission mechanisms If the OS81110 generates ReceiverBreak response message reception is terminated and the broken message will be lost In case the MDUT does not re transmit the broken message the MITB will indicate a missing message and TEST FAILED If the broken message is re transmitted by the MDUT after receiving th
30. 2048xFs test with 2 x 27q blockwidth Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 27 quadlet per frame Variable Packet Length Packet Delay 2000 us mitb 12642 6pin 2048fs 54 2048xFs test with 2 x 5q blockwidth and ChannelAddresses in the upper address range Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 5 quadlet per frame Variable Packet Length Packet Delay 2000 us CA 0x007E amp CA 0x7C mitb 12643 6pin 2048fs a 14 2048xFs test with RxBusy Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 16 Bytes Packet Delay 2000 us mitb 12644 6pin 2048fs 44 2048xFs test with RxBreak Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 4 quadlet per frame Fixed Packet Length 500 Bytes Packet Delay 1500 us mitb 12645 6pin 2048fs a 1q 2048xFs test with RxProtocollError Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 16 Bytes Packet Delay 2000 us mitb 12646 6pin 2048fs a 4q 2048xFs test with TxBreak Command generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 4 quadlet per frame Fixed Packet Length 500 Bytes Packet Delay 2000 u
31. Concurrent Rx and Tx transfer of MediaLB control data Description Blockwidth 2 x 1 quadlet per frame Variable Message Length Throughput 500 msgs s 11332 1024fs_c_1q_cfg_setup txt Manual setup of test via mitb_t1332_3pin_1024fs_c_1q_cfg_start txt GUI possible Files DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pan Mede Mode Speed Data Type Channel Address sen 0x01FE PC1 0x0004 Control Tx Device 3 Pin 1024xFs Control PC2 0x0002 Control Rx PC31 0x003E DUT DUT MediaLB PUT MOST RS232 Port Target Interface Clock Address Mode Speed User configurable 3 Pin 1024xFs 0101h O ol D Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum Repetition Message Length Length Length bytes s 2 Length bytes bytes bytes 9 Enable 6 45 1 1 Test Continuous Duration Throughput Message Pattern Test msgs msgs s Counter Type Disable 5000 475 Enable Counter Table 8 8 mitb 11332 1024fs 14 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 81 MediaLB Interface Test Bench V2 2 X 8 2 6 mitb t1333 3pin 1024fs 14 1024xFs test with none default ChannelAddresses Concurrent Rx and Tx transfer of MediaLB control data smsc Description Blockwidth 2 x 1 quadlet per frame Variable Message Length Throughput 500 msgs s AE e mitb 113
32. Intended to be flashed on OS81110 connected to PGA on MITB e 02 XX YYWITB 0581110 00 90 XX Intended to be flashed on OS81110 connected to MDUT in case of MediaLB 3 pin testing e FirmwareiDUTIWVO2 XX YYWITB OS81110 00 90 XX 6pin ipf Intended to be flashed on OS81110 connected to MDUT in case of MediaLB 6 pin testing The MITB delivery incorporates three Phy Boards The OS81110 devices assembled on these boards are by default flashed with the proper firmware Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 199 MediaLB Interface Test Bench e smsc V2 2 X 9 6 Test Configuration Files The test cases defined in chapter 7 are grouped in categories The following categories and folders are available on the installation CD Firmware Testbench V02_XX_YYlasync Firmware Testbench V02_XX_YY combined Firmware Testbench V02_XX_Y Y control Firmware Testbench V02_XX_Y Y isoc Firmware Testbench V02_XX_YY misc Firmware Testbench V02_XX_YY syne For every test case an additional sub folder is available which incorporates configuration files defining test specific parameters These configuration files can be loaded on the MITB GUI by clicking Load Config File button to execute a test case Two types of test configuration files are available Configuration setup files and Configuration start files The prefix mitb_txxxx_ _
33. SmS V2 2 X 2048xFs test all data types varied transfer parameter Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data E Blockwidth 2 x 1 quadlet per frame per loopback Varied msg packet length control async packet size Isochronous 196 bytes Packet delay 12 000 us message throughput 50mgs s packet throughput 1000 kbit s TM LE mitb 15463 6pin 2048fs casi setup txt Manual setup of test via e mitb 15463 6pin 2048fs casi cfg start txt GUI possible ono 2 Blockwidth MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum Length Length Length ay En Length bytes bytes bytes Enable 22 502 1 1 Continuous Pee Packet Pattern Test pkts us yte Disable 5000 12 000 Enable Counter Synchronous Data Test Tab Rx Blockwidth Channel Channel quadlets ae p Address Address frame yp Byte 0x000A 0x000C 1 Enable Counter ono Vata Rx Blockwidth Packet Size Packet Channel Channel quadlets Flow Control bytes Throughput Address Address frame kbit s 0 000 0 0010 1 Disable 196 1000 Continuous Test Packet Pattern Test Counter Type pkts Dis
34. The MITB does not support the data transfer of multiple logical MediaLB channels with the same data type and direction e g the transfer of two or more logical synchronous channels with the same direction is not supported The MOST150 Device Setup of the MITB described in section 2 1 2 is only possible if the MDUT is part of a MOST150 device incorporating an OS81110 MOST150 transceiver and optical MOST150 interface User Manual Copyright O 2011 SMSC Page 20 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 2 4 System and Tool Requirements To setup a complete MITB several components are required Some of them are compulsory others are optional 2 4 1 Compulsory Components For utilizing the MITB a host PC or laptop is needed The following PC environment is recommended e Pentium Class PC 2GBRAM 1 GB free disk space e Three Free USB 2 0 ports Two free RS232 ports e Windows XP or 2000 Additionally the following SMSC components are required to setup a complete MITB e NIC Explorer Interface Box 1 e OSS Flasher free of charge 2 The INIC Explorer Interface Box and the OSS Flasher are required to flash the MITB OS81110 test firmware to the OS81110 connected to the MDUT By default the Phy Boards part of the MITB delivery are flashed with the MITB OS81110 test firmware If a firmware update is necessary or the Phy Boards are used on different app
35. Updated test descriptions V2 1 X 1 2010 11 23 Expression replaced by Logs Packet Format 8 testcases 9 Summary of provided files modified V2 0 X 1 2010 09 01 Initial version of User Manual for 20 User Manual Copyright 2011 SMSC Page 4 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc 2 2 Table of Contents 1 PREFACE UII 9 1 1 nie 9 1 2 SCOPE of 9 2 10 Ee Ie 10 21 15 MediaLB Device Setup 12 2 1 2 MOST150 Device Setup 14 220 16 2 24 General Features anda dees 16 222 Hardware Features wv 17 2 2 3 Software GUI amp PGA Features 18 2 9 Functional Restrictions ii jacinta cinere tits eee db 20 2 4 System and Tool 21 241 Compulsory Components 21 24 2 Optional 5 22 2 5 User Hardware Requirements 444 22 2 5 4 Medial B Device Setup
36. ether ert Poe re re exe ie 128 8 3 16 12641 6pin 204815 2 0 p La er e ed 129 8 317 12642 6pin 204818 a 54 ioco tirer eder etes exte ux ed Eno Rx 130 8 3 18 12643 2048Is ANG ioco tete tee Pent rg xxt re Eu e dn 131 8 3 19 mitb 12644 204815 4 xt reu d e ex 133 8 3 20 12645 6pin 2048fs a 14 135 8 3 21 mitb 12646 6pin 2048fs a 44 7 137 8 3 22 mitb 12650 3072fs a 1 139 User Manual Copyright O 2011 SMSC Page 6 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 8 3 23 12651_6pin 30 215 A 2 0 tege t d rp 140 8 3 24 12660 4096S a 10 ioco Foxit rne ex ee 141 8 4 SynchronoUs eet eee tente 142 8 4 1 13310 25618 8 TQ ee e ex re 144 8 4 2 mith 13320 5121535 TQ aic ite Pte eta ere rg 145 84 3 mitb 13330 1024188 1Q eee lene 146 8 44 mitb 13331 102415 5 EE dn 147 8 4 5 13332 102415 5 er er ex de
37. 15Q 156 mito 13660 6pin 409615 5 14 157 mith 13661 6pin 409615 5 1958 eure E ORE 158 Isochronous Test Overview Part 1 159 Isochronous Test Overview Part 2 160 mitb t4310 25618 1 44 helene cic 161 mith t4320 51215 t eke 162 mitb 14330 102416 i 14 163 mitb 14331 1024146 1 74 4 164 mitb 4332 102415 1 78 a 165 mitb 4333 1024146 1 159 166 mith 4334 1024146 1 150 vies eaten 167 mith 14337 Spin 102416 1 158 168 mith 14640 204816 1 1 eros kk xen 169 mitb 14641 2048fs i 274 170 mitb 14642 204816 1 dq cie 171 14650 6 307216 ey Doa 172 mitb 14651 307216 2784 173 Combined Test Overview nnne enne enne 174 Combined Test Overview Part 2 enne enne entren nens 175 mitb 15310 25618 cas Part 1 tette ce 176 15310 256fs cas Part 2 esee endete enata neben 177 111615320 3pin 51218 cas Part 1 ettet 178 mitb 15320 21215 Cas Part 2 iei 179
38. Board connector is outlined below For more detailed information please refer to the Physical Interface Board 0581110 Data Sheet 3 Pin37 Pin38 Pin35 SDA Pin36 reserved 12 Interface Pin33 SCL Pin34 INT Pin31 TDO DINT B Pin32 TDI DSDA Debug amp JTAG Interface Pin29 TCK DSCL Pin30 TMS Pin27 ERR BOOT_B Pin28 MCK Misc Signals Pin25 RST_B Pin26 RSOUT_B Pin23 STATUS STATUS NOACT SCBUS Pin24 PWROFF Physical Interface Board IDs Pin21 50 22 51 19 MLBCP TSYN1 CSB B EI Pin20 SRX3 SDINB Network Interface 17 MLBCN TCLK1 SCLKB 18 TDATO SRXO SDOUTA 15 Reserved MOST_RXP 16 ISRX2 SDINA za Shared Serial IOs Pin13 Reserved MOST RXN 14 TVALO SRX1 SINTA_B MLB6 Pini MLBDP FSYB 12 PhylntfBrd 102 5 9 MLBDN SCKB SDINB Pinto RMCKO MLBDAT Pin7 PhyintfBrd_ID3 Pin8 hylntfBrd 101 125 5 104 Pine TSYNO MLBSIG FSYA CSA B I2SA Pin3 TVAL1 SINTB PhylntfBrd IDO Pini MLBSN TDAT1 SDOUTB Pin2 TCLKO MLBCLK SCKA SCLKA E GND Figure 3 3 Phy Board Connector The Phy Board connector needs to be available on the user hardware if the MITB is configured as MediaLB Device Setu
39. Mode Clock Speed Address 3 Pin 1024xFs 0101h configurable ono Vata 2 D Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 4 Disable Varied Fixed Minimum Maximum s Packet Length Length Length E Length bytes bytes bytes Disable 500 gt 2 Continuous Test Duration Packet Delay Packet Pattern Type RxRes Nr RxRes pkts us Counter yp ms p Enable 5000 1500 Enable Byte Counter ReceiverBreak 32 5 Table 8 40 mitb 12339 102415 44 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 123 MediaLB Interface Test Bench e smsc V2 2 X 8 3 13 mitb 123310 3pin 1024fs 14 The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is transmitting async data and the receiving device OS81110 connected to the MDUT is responding with ReceiverProtocolError responses After the data transfer is started the MITB will generate 32 ReceiverProtocolError responses on the Async Rx Channel ChannelAddress 0x0002 of the OS81110 ReceiverProtocolError responses are generated with a delay of 100 ms between consecutive HeceiverProtocolError The MDUT transmitting async packets needs to detect the ReceiverProtocolError responses Following the detection of the ReceiverProtocolError the MDUT must stop packet transmission following the MediaLB protocol
40. Pattern Type Byte Counter Throughput 450 msps s Continuous Test Test Duration 5000 msgs Clear Logs Configuration and Debug Messages Clear Log PGA s Control Results Log PGA s Control Statistics Log Figure 6 3 Control Tab User Manual Copyright O 2011 SMSC Page 46 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e smsc V2 2 X 6 2 2 1 Control Tab Parameters Parameters and buttons of the control tab are described in the table below Description transmitted by the 0581110 connected to the MDUT by the 0581110 connected to the MDUT RxResponse Defines special RxResponse to be generated by the MITB The following RxResponses are defined None RxBusy RxBreak and RxProtErr RxResponse Number Indicates number of special RxResponses to be generated RxResponses in ms following TxCommands are defined None TxCommand Number TxComand Delay Indicates approximate delay between consecutive generated TxCommands in ms Varied Message Length Check box to enable disable messages with fixed or varied length Fixed Length Length of control messages in case Varied Packet Length is disabled Value Range 6 45 Bytes Minimum Minimum length of control messages in case Varied Packet Length is enabled Value Range 6 45 Bytes with Minimum lt Maximum Maximum Maximum length of control messages in case Varied Packet Length is enabled
41. Table 8 39 Table 8 40 Table 8 41 Table 8 42 Table 8 43 Table 8 44 Table 8 45 Table 8 46 Table 8 47 Table 8 48 Table 8 49 Table 8 50 Table 8 51 Table 8 52 Table 8 53 Table 8 54 Table 8 55 Table 8 56 Table 8 57 Table 8 58 Table 8 59 Table 8 60 Table 8 61 Table 8 62 Table 8 63 Table 8 64 Table 8 65 Table 8 66 Table 8 67 Table 8 68 Table 8 69 Table 8 70 Table 8 71 Table 8 72 Table 8 73 Table 8 74 Table 8 75 Table 8 76 Table 8 77 Table 8 78 Table 8 79 Table 8 80 Table 8 81 Table 8 82 Table 8 83 Table 8 84 Table 8 85 Table 8 86 Table 8 87 Table 8 88 Table 8 89 Table 8 90 Table 8 91 Table 8 92 Table 8 93 Table 8 94 Table 8 95 Table 8 96 mitb 12336 3pin 1024s rnm 119 mitb 12338 102416 Qi 121 mitb 12339 Spin 102415 123 mitb 123310 102476 125 mitb t29311 Spin 102415 A Mq ive 127 mitb 12640 6pin 204816 Qe 128 mitb 126411 2048 s 27Q irte ttr arret 129 mitb 12642 204815 54 rre 130 12643 6pin 2048 sS ud 132 mitb 12644
42. V2 2 X smsc 8 3 Asynchronous Tests The following table provides an overview of available asynchronous data tests Test Name 12310_3pin_256fs_a_1q Test Characteristics MediaLB 3 pin Tests Basic 256xFs test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 14 Bytes Packet Delay 2000 us mitb 12320 512fs a 14 Basic 512xFs test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 14 Bytes Packet Delay 2000 us mitb 12321 512fs 74 512xFs test with 2 x 7q blockwidth Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 7 quadlet per frame Variable Packet Length Packet Delay 5200 us mitb 12330 Spin 1024fs a 14 Basic 1024xFs test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 14 Bytes Packet Delay 2000 us mitb 12331 1024fs 154 1024xFs test with maximum blockwidth Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 15 quadlet per frame Variable Packet Length Packet Delay 1000 us mitb 12332 1024fs 54 1024xFs test with intermediate Blockwidth and min and max packet length Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth
43. are not assembled by default but there are place holders prepared to assemble the required pull up and pull down resistors on the MLBSP N and signals For details about calculation of required pull up and pull down resistors refer to MediaLB Specification V4 2 4 section A 3 2 Please note that the resistors and capacitors values shown in the MediaLB spec are recommendations only Values chosen in actual systems are based on the MediaLB clock speed impedance of the PCB traces and the load capacitance on the line e PWROFF signal is an output from INIC and may be connected to input of EHC e Apart from the MLB signals the following signals are recommended to be connected on the user board RST_B power on reset through a Oohm resistor to the reset of user board SCL SDA to GPIOs on EHC PWROFF to GPIO on EHC RMCK1 optionally to an external reference clock through 0 ohm e Except of the MediaLB 6 pin signals on the user board no termination circuit is required e The MediaLB 3 pin signal levels are dependant of the INIC on the Phy Boards For detailed information refer to the INIC data sheets 0581110 the MediaLB 3 pin signal levels are of type 3 3V 0581050 the levels are of type 2 5V Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 31 MediaLB Interface Test Bench e smsc V2 2 X 3 6 3 MediaLB 3 6 Pin High Speed Debug Heade
44. e g provided power supply Do not interfere in the product s original state Otherwise user safety faultless operation and electromagnetic compatibility are not guaranteed To avoid electric shocks and short circuits use this device only in an appropriate environment This open device may exceed the limits of electromagnetic interference Electromagnetic compatibility can be only achieved if the equipment is built into an appropriate housing 1 2 Scope of Delivery The delivery of the MediaLB Interface Test Bench MITB consists of e 1 x MITB Platform e 2x Physical Interface Board 0581110 Variant 1 e 1 x Physical Interface Board 0581110 Variant 3 e 1x RS232 cable e 1x USB RS232 Adapter e 1 x Ethernet crossover cable e 1x Optical cable set e Power supply e 1 Installation CD including o MITB Graphical User Interface GUI o PCFlasher application o MITB FPGA image o PowerPC Pattern Generator amp Analyzer firmware o OS81110 test firmware o MITB user manual o Physical Interface Board OS81110 data sheet o MediaLB Analyzer product flyer and user manual o INIC Explorer product flyer and user manual Check your shipment for completeness If you have any complaints direct them to sales ais europoe smsc com Europe and Asia or to sales ais usa smsc com America Providing the delivery note number eases the handling Optional tools such as INIC Explorer MediaLB Analyzer are not part of
45. indicated by ReceiverReady responses the next ReceiverBusy period starts The ReceiverBusy responses indicate that the OS81110 connected to the MDUT is not able to receive data The ReceiverBusy responses need to be detected by the MDUT and transmitted data quadlets acknowledged by a ReceiverBusy response must be repeatedly transmitted until a ReceiverReady response is detected The user must verify this behavior manually The MITB does not provide an indication if the ReceiverBusy is handled properly by the MDUT To verify the MDUT behavior and capture the generated ReceiverBusy responses generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the OS81110 is generating ReceiverBusy responses randomly it cannot be guaranteed that the ReceiverBusy responses always happen at times when the MDUT is transmitting Async messages By that means it is not guaranteed that MediaLB commands 0x20 0x22 and 0x24 transmitted by the MDUT are acknowledged by ReceiverBusy responses It might happen that the ReceiverBusy responses are present on the bus when NoData commands are transmitted by the MDUT In that case the ReceiverBusy responses have no effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverBusy response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb 12338
46. is available in a data sheet and includes reference schematics required to realize an optical MOST150 interface as well as connector definitions Detailed information about the physical layer and link layer of a MediaLB 3 Pin as well as 6 Pin interface can be found in the MediaLB Specification V4 1 4 Information on the MOST150 OS81110 transceiver is stated in the OS81110 data sheet 5 and the OS81110 INIC API User s Manual 6 User Manual Copyright O 2011 SMSC Page 24 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e SmS V2 2 X 3 Component Description 3 1 MediaLB Interface Test Bench Platform The MITB platform represents the main hardware component of the MediaLB Interface Test Bench The MITB platform comes with all components properly configured and is ready to use The following figure depicts the MITB platform and its main components which are described below RS232 to Host PC FPGA Configuration Done LED Baudrate 115200 Data 8 bit 2 n FPGA PowerPC Parity None 5 Be walt an PGA Pattern Generator amp Analyzer Stop 1 bit 6 L M PGA Active LED LED 0 Flow Control None PHY2 Active LED LED 2 Power Supply 12 V 3 A On Off Switch PHY2 Phy Board Connector PHY2 3 3 V Power LED PHY2 MOST Lock LED PHY2 MediaLB Lock LED 5 V Power LED EH e LCD Display 4 x 16 Characters User Buttons Trigger Connector RJ 45 Connector Figu
47. part of a test definition The configuration files need to be loaded with the MITB GUI as described in section 6 3 2 The following sections define test cases and test specific parameters 8 1 Test Name Convention The naming convention for the defined test cases is as follows mitb 555515 T Extension Ixxxx Unique Test Number MediaLB Interface Mode 3 Pin Mode 6 6 Pin Mode SSSS MediaLB Clock Speed 256 256xFs 512 512xFs 1024 1024xFs 2048 2048xFs 3072 3072xFs 4096 4096xFs 6144 6144xFs 8192 8192xFs Data Transfer c Control Data a Asynchronous Data s Synchronous Data i Isochronous Data m Miscellaneous Combination of c a s and i in case of combined test cases Extension Verbal description optional Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 73 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 2 Control Tests The following table provides an overview of available control data tests Test Name Test Characteristics MediaLB 3 pin Tests t1310_3pin_256fs_c_1q Basic 256xFs test Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 8 Bytes Throughput 450 msgs s mitb_t1320_3pin_512fs_c_1q Basic 512xFs test Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length
48. yt g Disable 8 2 Test Continuous Throughput Message Pattern Test msgs s Counter Type msgs Disable 5000 50 Enable Byte Counter Table 8 93 mitb 15331 102415 casi Part 1 User Manual Copyright 2011 SMSC Page 182 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 1024xFs test 4 data types Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data hes E Blockwidth 2 x 1 quadlet per frame per loopback Fixed packet msg length control 8 bytes asynchronous 14 bytes isochronous 188 bytes Packet Delay 12 000 us Message Throughput 50mgs s 1000 kbit s TM LE mitb 15331 Spin 1024fs casi setup txt Manual setup of test via e 15331 Spin 1024fs casi start txt GUI possible ono 2 D Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum Packet Length Length Length ay Length bytes bytes bytes Disable 14 Continuous Test Packet Packet Pattern Test 9047 pkts us yte Disable 5000 12 000 Enable Counter Synchronous Data Test Tab Rx Blockwidth Channel Channel quadlets ae p Address Address frame yp Byte 0x000A 0x000C 1 Enable Counter ono Vata Rx Block
49. 1 quadlet per frame mitb 14330 Spin 1024fs i 19 Basic 1024xFs test Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 1 quadlet per frame 7q 1024xFs test with alternating Tx Rx ChannelAddresses Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 7 quadlet per frame CA 0x003C amp CA 0x003E 7q 1024xFs test with alternating Tx Rx ChannelAddresses Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 7 quadlet per frame CA 0x003C CA 0x003E 15q 1024xFs test with maximum blockwidth Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 15 quadlet per frame 154 1024xFs test with Packet Size 196 Bytes Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 15 quadlet per frame 154 1024xFs test with Flow Control enabled packet size 188 bytes Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth Tx channel 15 quadlet per frame Rx channel 1 quadlet per frame mitb_t4331_3pin_1024fs mitb 14332 Spin 102416 mitb 14333 Spin 102415 mitb 14334 Spin 102416 mitb_t4337_3pin_1024fs Table 8 70 Isochronous Test Overview Part 1 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 159 MediaLB Interface Test Bench e cnmnsc V2 2 X Test Test Character
50. 2 X Date 2011 12 09 MediaLB Interface Test Bench e smsc V2 2 X Test Name Test Characteristics MediaLB 6 pin Tests mitb_t5640_6pin_2048fs_cas Basic 2048xFs test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous data Blockwidth 2 x 1 quadlet per frame per loopback Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s mitb_t5641_6pin_2048fs_si 2048xFs test 2 streaming loopbacks Concurrent Rx and Tx transfer of MediaLB synchronous and isochronous data Blockwidth 2 x 1 quadlet per frame per loopback packet size 188 bytes packet throughput 1000 kbit s mitb 15642 2048fs casi 2048xFs test all data types Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data Blockwidth 2 x 1 quadlet per frame per loopback Fixed packet msg length control 8 bytes asynchronous 14 bytes isochronous 188 bytes Packet Delay 12 000 us message Throughput 50mgs s packet throughput 1000 kbit s mitb t5643 6pin 2048fs casi 2048xFs test all data types varied transfer parameter Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data Blockwidth 2 x 1 quadlet per frame per loopback Varied msg packet length control async packet size Isochronous 196 bytes Packet delay 12 000 us message throughput 50mgs s packet throughput 1
51. 2 X Date 2011 12 0902 Page 65 MediaLB Interface Test Bench e SmS V2 2 X PML 16 bit field indicating the total number of bytes that follow in the Port Message Header PMH and the Port Message Body PMB PMHL Single byte field indicating the byte length of the FIFO Protocol Header FPH and FIFO Data Header FDH Value is always set to 0x06 FPH Defines the Port Message Type and the FIFO to be targeted Value is always set to 0x04 Length 12 bit field indicating the total number of data bytes following in the Port Message Body PMB Message 16 bit field indicating the total number of bytes which follow in the Port Message Length Body PMB including the two bytes of Message Length itself Message Length can be adjusted in the MITB GUI Minimum value 6 bytes Maximum value 45 bytes Message 32 bit field representing a message counter which is incremented for each Index transmitted message Data Data bytes with pattern type Byte Counter or Random Number of data bytes can vary from 0 to 39 bytes Pattern Type Byte Counter Message Index Message 1 00 00 00 00 Message 2 0000 00 01 Message 3 0000 00 02 Pattern Type Random Message Index Message 1 00 00 00 00 Message 2 0000 00 01 Message 3 0000 00 02 Table 7 1 Control Message Format Description User Manual Copyright O 2011 SMSC Page 66 Document Version V2 2 X Date 2011 1
52. 3 Pin 1024xFs 0101h configurable ono Vata ab Tx Rx Blockwidth Channel Channel quadlets dus r E Address Address frame 0 000 0 000 15 Enable Counter Table 8 62 mitb 13335 3pin 1024fs s 15q Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 151 MediaLB Interface Test Bench e smnsc V2 2 X 8 4 9 mitb t3640 6pin 2048fs s 1q Basic 2048xFs test Description Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame mitb 13640 6pin 2048fs s 19 cfg setup txt Manual setup of test via Ie mitb 13640 204815 s 1q start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel pendere Mode Speed Data Types Channel Address 0x01FE PC1 0 000 Sync Rx Device 6 Pin 2048xFs Sync PC2 0x000C Sync Tx PC57 0x0000 DUT RS232 Port MediaLB Clock Target Pin Mode Speed Address de 6 Pin 2048xFs 0101h Synchronous Data Test Tab Blockwidth Fram Pattern Channel Channel quadlets CR Address Address frame yp Byte 0x000A 0x000C 1 Enable Counter Table 8 63 mitb_t3640_6pin_2048fs_s_1q User Manual Copyright 2011 SMSC Page 152 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cSnmnsc V2 2 X 8 4 10
53. 450 Enable Byte Counter Table 8 91 mitb_t5330_3pin_1024fs_cas Part 1 User Manual Copyright 2011 SMSC Page 180 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X smsc Basic 1024xFs test Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous data Charactenstic Blockwidth 2 x 1 quadlet per frame per loopback Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s mitb 15330 102415 cas setup txt Manual setup of test via EIER mitb 15330 1024fs cas start txt GUI possible GUI Configuration Asynchronous Data Test Tab Tx Rx Blockwidth MEP MEP Channel Channel quadlets Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum T Packet Length Length Length EO E Length bytes bytes bytes Disable 14 Continuous vesi Parei Packet Pattern Test pkts us Disable 10000 2000 Enable Counter Tx Rx Blockwidth Frame Pattern Channel Channel quadlets Address Address frame counei 0x000A 0x000C 1 Enable Counter Table 8 92 mitb_t5330_3pin_1024fs_cas Part 2 Copyright 2011 SMSC Document Version V2 2 X Date 2011 12 0902 User Manual Page
54. 7 170 8 5 11 mitb 14642 204816 1 4q iei aaa 171 8 5 12 14650 307218 1 172 8 5 13 14651 307218 1 7 terere 173 8 6 Gombinied Testseite eig arx tie ace tease 174 8 6 1 mitb 15310 256fs 8 176 8 6 2 15320 51215 esee ener enn 178 8 6 3 mitb 15330 1024fs 180 8 6 4 mitb 15331 102416 182 8 6 5 mitb 15332 102416 184 8 6 6 mitb 15333 102416 186 8 6 7 mitb 15640 6pin 204815 188 8 6 8 15641 204816 2200 190 8 6 9 mitb 15642 6pin 2048fs 191 8 6 10 15643 6pin 2048fs 193 8 7 Miscellaneous 5 5 195 8 7 1 19330 102415 m syscmd 196 8 7 2 19640 6pin 2048fs 197 9 SUMMARY OF PROVIDED 198 9 1 Graphical User I
55. 8 88 mitb_t5310_3pin_256fs_cas Part 2 Copyright 2011 SMSC Document Version V2 2 X Date 2011 12 0902 User Manual Page 177 MediaLB Interface Test Bench e SmS V2 2 X 8 6 2 mitb 15320 3pin 512fs cas Basic 512xFs test Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous data Characteristic Blockwidth 2 x 1 quadlet per frame per loopback Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s mitb 15320 512fs cas setup txt Manual setup of test via E mitb 15320 512fs cas start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Par Mede Mode Speed Data Types Channel Address Allocated PCO 0x01FE PC1 0x0004 Control Tx PC2 0x0002 Control Rx Control 0 0006 ontrol Device 3 Pin 512xFs Async Sync PC4 0x0008 Async Tx PC5 0x000A Sync Rx PC6 0x000C Sync Tx PC15 0x003E DUT DUT MS Interface Clock Ad eee Mode Speed ate 3 Pin 512xFs 0101h ol D Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum t Repetiti Message Length Length Length Pos S Ee en Length bytes bytes bytes 9 Disable 8 Continuous Throughput Message
56. Clock Address Mode Speed 6 Pin 2048xFs 0101h configurable ono 0 2 Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 27 Disable Varied Fixed Minimum Maximum T Packet Length Length Length pos btw Length bytes bytes bytes Enable 6 1014 1 1 Test Packet Duration Delay nu pkts us Disable 5000 2000 Enable Random Table 8 44 mitb_t2641_6pin_2048fs_a_27q Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 129 MediaLB Interface Test Bench e smnsc V2 2 X 8 3 17 mitb 12642 6pin 2048fs 54 2048xFs test with 2 x 5q blockwidth and ChannelAddresses the upper address range Concurrent Rx and Tx transfer of MediaLB asynchronous data Test Blockwidth 2 x 5 quadlet per frame Characteristic Variable Packet Length Packet Delay 2000 us CA 0x007E amp CA 0x7C Test 5 mitb 12642 2048fs 5 setup txt Manual setup of test via Configuration Files mitb_t2642_6pin_2048fs_a_5q_cfg_start txt GUI possible D ediaL B atio Interface Clock Transferred Physical Channel Par Mede Mode Speed Data Type Channel Address tensia PCO 0x01FE PC1 0x007C Async Rx 5 0 007 Device 6 Pin 2048xFs Async PC6 0x007E Async Tx PC11 0x0008 A
57. D Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 4 Disable Fixed Minimum Maximum Length Length Length aN Length bytes bytes bytes Disable 500 5 x s Continuous Test Duration Packet Delay Packet Delay TES okts us Cds Pattern Type Nr TxCmd ms Enable 5000 2000 Enable Byte Counter AsyncBreak 32 4 Table 8 49 mitb_t2646_6pin_2048fs_a_4q User Manual Copyright 2011 SMSC Page 138 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e V2 2 X 8 3 22 mitb 12650 3072fs 1q Basic 3072xFs test Test Concurrent Rx and Tx transfer of MediaLB asynchronous data Characteristic Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 32 Bytes Packet Delay 2000 us COM DEN mitb 12650 6pin 307215 a 1q cfg setup txt Manual setup of test via E mitb 12650 6pin 307215 14 start txt GUI possible ediaLB Interface Clock Transferred Physical Channel PUE Mode Speed Data Type Channel Address Mesue PCO 0x01FE PC1 0x0006 Async Rx Device 6 Pin 3072xFs Async PC2 0x0008 Tx PC86 0x0000 DUT DUT MediaLB MOST RS232 Port Target Interface Clock Speed 6 3072xFs 0101h Asynchronous D
58. DESIGN Flash Memory Usage Delete Flash File Send Figure 5 5 Flash FPGA Image to MITB Platform 6 Load FPGA image Power up MITB platform Do not press any button New image will be loaded to FPGA For a few seconds the version of the FPGA image is indicated on the LCD display next to the user buttons Copyright O 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 39 MediaLB Interface Test Bench e smsc V2 2 X 5 3 Flash Pattern Generator amp Analyzer To flash Pattern Generator amp Analyzer firmware to the MITB platform the following steps are required 1 Power up MITB platform Power up the MITB platform while user button WEST is pressed Button needs to be pressed for several seconds until Flashloader application will be executed on the MITB platform The version of the Flashloader is indicated on the LCD display next to the user buttons 2 Run PCFlasher exe Start PCFlasher exe application on host PC the PCFlasher exe file is provided on the CD delivered with the MITB platform 3 Verify connection to MITB platform The IP address of MITB platforms is defined as 192 168 0 100 Enter IP address of MITB platform in the GUI of the PCFlasher application Click the Ping button In the log window connection success should be reported Ext ClearLog Device IP Address 192 168 0 100 Ping Re connect Flashing Hos
59. Device Setup o MOST150 Device Setup Optical physical layer for MOST150 supported e MITB operates as MediaLB controller and MOST150 network master e GUI for test pattern configuration e GUI for remote configuration of MediaLB controller INIC connected to MDUT e GUI for test status visualization User Manual Copyright O 2011 SMSC Page 16 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 2 2 2 Hardware Features e Supported physical MediaLB interfaces o Single ended MediaLB 3 Pin interface o Differential MediaLB 6 Pin interface Supported MediaLB debug headers o MediaLB 3 6 Pin high speed debug header SAMTEC 0 5 mm 20 pair high speed differential pair socket QSH 020 01 L D DP A Supported MOST Phy Boards o Phy Board Variant 3 optimized for single ended MediaLB 3 Pin interface Phy Board Variant 1 optimized for differential MediaLB 6 Pin interface Supported MediaLB clock rates on 3 Pin interface o 256xFs e g 256 x 48 kHz 12 288 MHz 512xFs e g 512 x 48 kHz 24 576 MHz o 1024xFs e g 1024 x 48 kHz 49 152 MHz Supported MediaLB clock rates on 6 Pin interface o 2048xFs e g 2048 x 48 kHz 98 304 MHz o 3072xFs e g 3072 x 48 kHz 147 446 MHz o 4096xFs e g 4096 x 48 kHz 196 608 MHz Status LEDs for o MediaLB Lock detection o MOST Lock detection o Power indication 5232 interface to host PC e 10 100 Ether
60. Enable Byte Counter ControlBreak 240 20 Table 8 18 mitb_t1644_6pin_2048fs_c_1q Copyright 2011 SMSC User Manual Page 99 MediaLB Interface Test Bench V2 2 X 8 2 16 mitb t1650 6pin 307215 14 Basic 3072xFs test Concurrent Rx and Tx transfer of MediaLB control data smsc Description Blockwidth 2 x 1 quadlet per frame Fixed Message Length 14 Bytes Throughput 250 msgs s Test Contiguration mith 11650 3072fs_c_1q_cfg_setup txt Manual setup of test via Files mitb_t1650_6pin_3072fs_c_1q_cfg_start txt GUI possible ediaLb Interface Clock Transferred Physical Channel PON Mede Mode Speed Data Type Channel Address sse BT TE e PCO 0x01FE PC1 0x0004 Control Tx PC2 0x0002 Control Rx Device 6 Pin 3072xFs Control m 57 0 00 Unused PC86 0x0000 GUI Configuration Configuration Tab DUT DUT MESES Interface Clock Ad dies Mode Speed User configurable 6 Pin 3072xFs 0101h O oi D D Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum t Repetiti Message Length Length Length 3 dard Length bytes bytes bytes Disable 14 Continuous TR Throughput Message Pattern Test msgs msgs s Counter Type z Byte Disable 5000 250 Enable Table 8 19 11650 3072fs 14
61. Isoc Rx Device 6 Pin 3072xFs Isoc PC28 0x0010 Isoc Tx PC54 0x0010 Isoc Tx PC86 0x0000 DUT emus Eunos RS232 Port MediaLB Clock Target Pin Mode Speed Address User configurable 6 Pin 3072xFs 0101h isochronous Data Test Tab Tx Rx Blockwidth Packet Channel Channel quadlets Flow Control Throughput Address Address frame y kbit s 0x000E 0x0010 27 Disable 196 1000 Continuous Tue Packet Pattern Test okts Counter Type 2 Disable 5000 Enable Co nt i Table 8 84 mitb_t4651_6pin_3072fs_i_27q Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 173 MediaLB Interface Test Bench e cSnmnsc V2 2 X 8 6 Combined Tests The following table provides an overview of available combined data tests Test Name Test Characteristics MediaLB 3 pin Tests mitb_t5310_3pin_256fs_cas Basic 256xFs test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous data Blockwidth 2 x 1 quadlet per frame per data type Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s mitb_t5320_3pin_512fs_cas Basic 512xFs test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous data Blockwidth 2 x 1 quadlet per frame per loopback Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s mitb 15330 1024fs cas Basic 1024xFs test Con
62. MediaLB control data smsc DUT MediaLB Configuration Description Blockwidth 2 x 1 quadlet per frame Variable Message Length Throughput 450 msgs s M mitb t1331 1024fs 14 setup txt Manual setup of test via Em mitb 11331 Spin 1024fs 19 start txt GUI possible Interface Clock Transferred Physical Channel Pan Mede Mode Speed Data Type Channel Address PCO 0x01FE PC1 0x0004 Control Tx Device 3 Pin 1024xFs Control PC2 0x0002 Control Rx PC31 0x003E DUT DUT MediaLB PUT MOST RS232 Port Target Interface Clock Address Mode Speed User configurable 3 Pin 1024xFs 0101h O ol D 0 Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum Repetitions Message Length Length Length bytes msgs Length bytes bytes bytes Enable 6 45 1 1 Test Continuous Throughput Message Pattern Test Durian msgs s Counter Type msgs Disable 5000 450 Enable Counter Table 8 7 11331 Spin 1024fs 14 User Manual Copyright O 2011 SMSC Page 80 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X 8 2 5 11332 1024145 14 smsc 1024xFs test with maximum Message Throughput
63. Page 204 Copyright 2011 SMSC Document Version 2 2 Date 2011 12 09 MediaLB Interface Test Bench V2 2 X Appendix E List of Tables Table 6 1 Configuration Tab Parameters 44 Table 6 2 Configuration Tab Parameters Part 2 45 Table 6 3 Control Tab 48 Table 6 4 Control Results 1 09 48 Table 6 5 Control Statistics Log 49 Table 6 6 Asynchronous Tab 52 Table 6 7 Asynchronous Results Log 52 Table 6 8 Asynchronous Statistics 53 Table 6 9 Synchronous Tab Parameters 55 Table 6 10 Synchronous Results Log 56 Table 6 11 Isochronous Tab Parameters sss 58 Table 6 12 Isochronous Results 59 Table 6 13 Isochronous Statistics Log 60 Table 6 14 System Commands Tab 61 Table 7 1 Control Message Format 66 Table 7 2 MDP Format 68 Table 7 3 MEP Format Description 70 Table 7 4 Isochronous Packet Format Description 72 Table 8 1 Control Test Overview Part 1
64. Pattern Test msgs msgs s Counter Type Byte Disable 10000 450 Enable C unt r Table 8 89 mitb_t5320_3pin_512fs_cas Part 1 User Manual Copyright 2011 SMSC Page 178 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X smsc Basic 512xFs test Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous data Charactenstic Blockwidth 2 x 1 quadlet per frame per loopback Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s mitb 15320 Spin 51215 cas setup txt Manual setup of test via EIER mitb 15320 512fs cas start txt GUI possible GUI Configuration Asynchronous Data Test Tab Tx Rx Blockwidth MEP MEP Channel Channel quadlets Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum T Packet Length Length Length EO E Length bytes bytes bytes Disable 14 Continuous vesi Parei Packet Pattern Test pkts us Disable 10000 2000 Enable Counter Tx Rx Blockwidth Frame Pattern Channel Channel quadlets Address Address frame Counisr 0x000A 0x000C 1 Enable Counts Table 8 90 mitb_t5320_3pin_512fs_cas Part 2 Copyright 2011 SMSC Document Vers
65. Rx PC6 0x000A Sync Rx PC7 0x000C Sync Tx Device 3 Pin 1024xFs Sync PC8 0x000C Sync Tx 9 0 000 Sync Tx PC10 0 000 Sync Rx 11 0 000 Sync Rx PC12 0x000A Sync Rx PC13 0x000C Sync Tx PC14 0x000A Sync Rx PC31 0x0000 DUT RS232 Port MediaLB Clock Target Pin Mode 5 Address peed 3 Pin 1024xFs 0101h configurable ono BEIE 2 Rx Blockwidth Channel Channel quadlets E Address Address frame yp Byte 0x000A 0x000C 7 Enable Counter Table 8 61 13334 1024fs s 74 User Manual Copyright O 2011 SMSC Page 150 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 4 8 mitb t3335 3pin 1024fs s 15q 1024xFs test with high blockwidth Description Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 15 quadlet per frame mitb_t3335_3pin_1024fs_s_15q_cfg_setup txt Manual setup of test via Configuration Files mitb_t3335_3pin_1024fs_s_15q_cfg_start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pan Meze Mode Speed Data Types Channel Address Allocated nene PCO 0x01FE 1 0x000A Sync Rx Device 3 Pin 1024xFs Sync BETS Ox000A Syne Ax PC16 0x000C Sync Tx PC30 0x000C Sync Tx PC31 0x0000 DUT any 5232 MediaLB Clock Target Pin Mode 5 Address peed
66. Rx Blockwidth Channel Channel quadlets Flow Control E Throughput Address Address frame kbit s 0x003C 0x003E 7 Disable 188 1000 Continuous acces Packet Pattern Test okts Counter Type Byte Disable 5000 Enable Counter Table 8 75 mitb_t4331_3pin_1024fs_i_7q User Manual Copyright 2011 SMSC Page 164 Document Version 2 2 Date 2011 12 09 MediaLB Interface Test Bench V2 2 X 8 5 5 mitb t4332 3pin 1024fs 74 smsc 1024xFs test with alternating Tx Rx ChannelAddresses Description 7 Rx Tx transfer of MediaLB isochronous data Blockwidth 2 x 7 quadlet per frame CA 0x003C 8 mitb t4332 Spin 1024fs 7q_cfg_setup txt Manual setup of test via Files mitb 14332 1024fs i 7q start txt GUI possible D ediaL B Allocated Transfer PCO 0x01FE PC1 0x003E Isoc Tx PC2 0x003C Isoc Rx PC3 0x003E Isoc Tx PC4 0x003E Isoc Tx PC5 0 003 Isoc Rx 6 0 003 Isoc Rx 0x003E Isoc Tx Device 3 Pin 1024xFs Isoc PC8 0x003E Isoc Tx PC9 0 00 Isoc Tx PC10 0x003C Isoc Rx 11 0 003 Isoc Rx 12 0 003 5 Rx PC13 0x003E Isoc Tx PC14 0x003C Isoc Rx 1 0 0000 DUTMOST RS232 Port MediaLB Clock Target Pin Mode Speed Address ue 3 Pin 1024xFs 0101h RT Flow Contro
67. Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 4 Disable Varied Fixed Minimum Maximum T Packet Length Length Length ee ae Length bytes bytes bytes Disable 500 Continuous Test Duration Packet Delay Packet RxRes Nr RxRes Test pkts us Counter yp B ms P Enable 5000 1500 Enable Byte Counter ReceiverBreak 32 5 Table 8 47 mitb_t2644_6pin_2048fs_a_4q User Manual Copyright 2011 SMSC Page 134 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 8 3 20 mitb_t2645 2048fs 14 The purpose of this test is to verify the correct behavior of the MediaLB DUT case it is transmitting async data and the receiving device 0581110 connected to the MDUT is responding with ReceiverProtocolError responses After the data transfer is started the MITB will generate 32 ReceiverProtocolError responses the Async Rx Channel ChannelAddress 0x0002 of the 0581110 ReceiverProtocolError responses are generated with a delay of 100 ms between consecutive ReceiverProtocolError The MDUT transmitting async packets needs to detect the ReceiverProtocolError responses Following the detection of the ReceiverProtocolError the MDUT must stop packet transmission following the MediaLB protocol defined in the MediaLB spec The user needs to verify manually that the MDUT
68. Test Bench e cnmnsc V2 2 X 1024xFs test with ReceiverBreak responses generated by MITB Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes Description Throughput 500 msgs s generates 48 ReceiverBreak responses on the Control Rx Channel ChannelAddress 0x0002 of the MDUT 0581110 ReceiverBreak responses generated with a delay of 200 ms between consecutive ReceiverBreaks mith 11336 1024fs_c_1q_cfg_setup txt Manual setup of test via Files mitb_t1336_3pin_1024fs_c_1q_cfg_start txt GUI possible DUT MediaLB Configuration Transferred Physical Channel Port Mode Interface Mode Clock Speed Data Type Channel Kadas Allocated Transfer PCO 0x01FE PC1 0x0004 Control Tx Device 3 Pin 1024xFs Control PC2 0x0002 Control Rx PC31 0x003E GUI Configuration Configuration Tab DUT MediaLB DUT MediaLB DUT MOST REZ Pori Interface Mode Clock Speed Target Address E 3 Pin 1024xFs 0101h configurable Control Data Test Tab Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum increments Renetitions Message Length Length Length bytes Be 5 Length bytes bytes bytes 9 Disable 45 Continuous Test Duration Throughput Message Delay RxResp Test msgs msgs s Counter S Ni ms Disable 5000 500 Enable Byte Counter ReceiverBreak 48 200
69. Test Bench e smsc V2 2 X 8 5 8 mitb t4337 3pin 1024fs i 15q 1024xFs test with Flow Control enabled packet size 188 bytes Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth Tx channel 15 quadlet per frame Blockwidth Rx channel 1 quadlet per frame Description Test fails with missed packets due to INIC overflow on Rx channel to force RxBusy responses on both channels missed packets due discarded isoc data on MOST because of INIC overflow mitb 14337 102415 159 setup txt Manual setup of test via ee mitb_t4337_3pin_1024fs_i_15q_cfg_start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Par Maze Mode Speed Data Types Channel Address 0x01FE PC1 0x000E Isoc Rx Device 3 Pin 1024xFs Isoc PC15 Ox000E Isoc Rx PC16 0x0010 5 Tx PC31 0x0000 PGA GUI Configuration Configuration Tab DUT DUTMOST RS232 Port MediaLB Clock Target Pin Mode Speed Address User 3 Pin 1024xFs 0101h configurable Isochronous Data Test Tab Blockwidth Blockwidth 13 Rx Tx Rx Flow Packet Size Channel Channel Throughput quadlets quadlets Control bytes gt Address Address frame frame kbit s 0 000 0 0010 15 1 Disable 188 3000 Test capu esee ae pkts Disable 10 000 Enable Counter Table 8 79 mit
70. The test result is indicated on the test status field next to the Start Stop Button as soon as a test is stopped 6 2 4 3 Synchronous Statistics Log For synchronous data no statistics are available User Manual Copyright 2011 SMSC Page 56 Document Version 2 2 Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 6 2 5 Isochronous Tab The following figure shows the isochronous tab of the GUI In this tab parameters can be entered which define the characteristics of the generated isochronous test patterns A button is available to manually start and stop the pattern processing Log windows display the PGA results and statistics Dedicated test status fields indicate the test status Isochronous PGA Statistics Status Field Isochronous PGA Result Status Field Isochronous Tab Parameters Isochronous Start Stop Button Isochronous Test Status Field GUI V2 20 M TR MediaLB Interface Test Bench Pattern Generator and Analyzer GUI V2 2 0 Configuration Control Asynchronous Synchronods Isochronous System Commands Isochronous Data Test Tx ChannelAddress Rx ChannelAddress 0010 hex Start Test Blockwidth 17 quadlets frame Pattern Generator and Analyzer Results Flow Control Packet Length 196 bytes b Pattern Generator and Analyzer Statistics kbity s Pattern Type Byte Counter Throughput 1000 Continuous Test Clear L
71. Value Range 6 45 Bytes with Maximum gt Minimum Increments Number of bytes the length of consecutive messages are incremented in case Varied Packet Length is enabled Repetitions Number of consecutive messages generated with the same length in case Varied Packet Length is enabled Pattern Type Two types of patterns are supported Byte Counter and Random For details about pattern formats refer to chapter 7 Throughput Number of messages transmitted per second Value Range 15 450 msgs s Continuous Test Check box to enable disable the successive transmission of control messages Test Duration If Continuous Test is disabled the Test Duration defines how many messages are transmitted Clear Logs Button to clear the PGA Results and Statistics windows Start Stop Test Button to manually start and stop the test Test Status Field The Control Test Status Field provides an indication of the overall state of a test The state is indicated by four colors Grey Test Default state no active test Yellow Test Running Test active and running Red TEST FAILED Test is stopped and failed with errors detected in either the PGA Results or Statistics Green TEST PASSED Test is stopped and passed PGA Results Status The Control Results Status Field provides an indication of the PGA test Field results of actually received test patterns The state is indicated by four Copyright O 2011 SMSC User Manual Document Versio
72. X Date 2011 12 0902 User Manual Page 101 MediaLB Interface Test Bench V2 2 X 8 2 18 mitb t1660 4096fs 14 Basic 4096xFs test Concurrent Rx and Tx transfer of MediaLB control data smsc Description Blockwidth 2 x 1 quadlet per frame Fixed Message Length 14 Bytes Throughput 250 msgs s Test Contiquration mitb t1660 6pin 4096fs c 1q cfg setup txt Manual setup of test via E mitb t1660 6pin 4096fs 1q start txt GUI possible Interface Clock Transferred Physical Channel PON Mede Mode Speed Data Type Channel Address sse BT TE e PCO 0x01FE PC1 0x0004 Control Tx PC2 0x0002 Control Rx Device 6 Pin 4096xFs Control m PC57 0 00 Unused PC116 0x0000 GUI Configuration Configuration Tab DUT DUT a MESES Interface Clock Ad dies Mode Speed User configurable 6 Pin 4096xFs 0101h O oi D D Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum t Repetiti Message Length Length Length 3 dard Length bytes bytes bytes Disable 14 Continuous TR Throughput Message Pattern Test msgs msgs s Counter Type z Byte Disable 5000 250 Enable Table 8 21 mitb 11660 4096fs 14 User Manual Copyright 2011 SMSC Page 102 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Ben
73. a TEST PASS in the MITB GUI This behavior relates to the length of the ReceiverBusy periods as well as to the MDUT packet buffer size In some cases the MITB test case mitb t2643 6pin 2048fs a 1q might indicate a TEST FAILED with missing messages in the MITB GUI This behavior is expected and is related to the nature of the MOST network and the OS81110 as well as to the packet buffer size on the MDUT During the ReceiverBusy periods the OS81110 will not receive data from the MDUT via MediaLB Since loop back application of the MDUT cannot transmit any data it also will only be able to receive a certain amount of new packets from the OS81110 via MediaLB and the MITB respectively Large packet buffers allow the MDUT to keep receiving more packets where as with small packet buffers the MDUT will stop receiving data quite fast This again results in the OS81110 holding of messages received via MOST from the MITB platform Depending on how long the ReceiverBusy period lasts and how deep the MDUT packet buffers are the OS81110 buffers will run full and packets transmitted from MITB platform to OS81110 via MOST will get lost on the MOST network There is no such thing as a ReceiverBusy response on MOST Because of this no feedback from the OS81110 connected to the DUT is passed to the OS81110 on the MITB platform indicating the buffer full condition of the DUT OS81110 and the MITB keeps transmitting packets which may get lost Copyright O 2
74. as the INIC Explorer Interface Box by an RS232 connection If RS232 to USB converters are used the INIC Explorer Interface Box and the MITB platform may be connected via USB to the host PC 3 6 Connectors Four kinds of connectors are available on a MITB setup e Configuration debug header e Phy Board connector e MediaLB 3 6 Pin high speed debug header e Trigger connector User Manual Copyright 2011 SMSC Page 28 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X The configuration debug header is required to flash the firmware or to modify the configuration string of an OS81110 MOST transceiver The Phy Board connector is used to connect a Phy Board to a main board e g MITB platform or to user hardware The MediaLB 3 6 high speed debug header is suitable to connect a MediaL Analyzer for observation and debugging the data flow on a MediaLB interface The Phy Board connector and the MediaLB 3 6 Pin high speed debug header are physically identical Both headers are high speed differential connectors with 40 pins or 20 differential pairs The difference between both connectors is the signal layout The Phy Board connector incorporates all interface signals of the 0581110 INIC including MediaLB 3 6 Pin 125 SPI TSI C JTAG MediaLB debug connector comprises the MediaLB 3 Pin and 6 Pin signals only For every MediaLB data type the trigger connect
75. behavior and capture the generated HeceiverBreak responses generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the 0581110 is generating ReceiverBreak responses randomly it cannot be guaranteed that the ReceiverBreak responses always happen at times when the MDUT is transmitting async packets By that means it is not guaranteed that MediaLB commands 0x20 0x22 and 0x24 transmitted by the MDUT are acknowledged by HeceiverBreak responses It might happen that the ReceiverBreak responses are present on the bus when NoData commands are transmitted by the MDUT In that case the ReceiverBreak responses have no effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverBreak response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb t2644 6pin 2048fs c 4q indicates a TEST FAILED with missing packets in the MITB GUI for most cases This behavior is expected and entirely depends on the customer specific DUT system re transmission mechanisms If the OS81110 generates a ReceiverBreak response packet reception is terminated and the broken packet will be lost In case the MDUT does not re transmit the broken packet the MITB will indicate a missing packet and TEST FAILED If the broken packet is re transmitted by the MDUT after receiving the ReceiverBreak response the MI
76. capture the generated ControlBreak command generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the OS81110 is generating ControlBreak commands randomly it cannot be guaranteed that the ControlBreak command always happen at times when the OS81110 is transmitting control messages By that means it is not guaranteed that the MDUT is receiving a message when the Contro Break command is transmitted by the OS81110 Since the MDUT may not receive a message when the ControlBreak is present on the MediaLB bus the ControlBreak command may not be detected by the MDUT In that case the ControlBreak commands have no effect on the behavior of the MDUT To still be able to test the proper handling of the ControlBreak command by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb t1338 3pin 1024fs c 1q is expected to indicate a TEST PASS This is the case because the messages terminated by a ControlBreak command are re transmitted entirely by the OS81110 Copyright O 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 89 MediaLB Interface Test Bench V2 2 X 1024xFs test with ControlBreak commands generated by MITB Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes Configuration File
77. defined in the MediaLB spec The user needs to verify manually that the MDUT is properly terminating the packet transmission Additionally it may be verified if MDUT internally a status indicating the detection of the HeceiverProtocolError response is signalled properly The MITB does not provide an indication if the MDUT is handling the ReceiverProtocolError as expected To verify the MDUT behavior and capture the generated HeceiverProtocolError responses generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the OS81110 is generating HeceiverProtocolError responses randomly it cannot be guaranteed that the ReceiverProtocolError responses always happen at times when the MDUT is transmitting async packets By that means it is not guaranteed that MediaLB commands 0x30 0x32 and 0x34 transmitted by the MDUT are acknowledged by HeceiverProtocolError responses It might happen that the ReceiverProtocolError responses are present on the bus when NoData commands are transmitted by the MDUT In that case the HeceiverProtocolError responses have no effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverProtocolError response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb t23310 1024fs 1q indicates a TEST FAILED with missing packets in the MITB GUI for m
78. frame CA 0x007E amp CA 0x7C e 078 mitb 14642 204815 i 4 setup txt Manual setup of test via E oS mitb 4642 6pin 2048fs i 4q cfg start txt GUI possible D ediaL B atio Interface Clock Transferred Physical Channel Por Meee Mode Speed Data Types Channel Address Urine PCO 0x01FE PC1 0x007E Isoc Rx PC4 0x007E Isoc Rx Device 6 Pin 2048xFs Isoc PC5 0x007C Tx PC10 0x007C Isoc Tx PC57 0x0000 PGA GUI Co Configuration Tab DUT ee RS232 Port MediaLB Clock Target Pin Mode Speed Address User configurable 6 Pin 2048xFs 0101h O ono BELE e Rx Blockwidth Packet Size Packet Channel Channel quadlets Flow Control bytes Throughput Address Address frame kbit s 0x007E 0x007C 4 Disable 188 1000 Continuous Shoe Packet Pattern Test okts Counter Type Disable 1000 Enable Byte Counter Table 8 82 mitb 14642 6pin 2048fs 44 Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 171 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 5 12 mitb 14650 307215 14 Basic 3072xFs test Concurrent Rx and Tx transfer of MediaLB isochronous data ET Blockwidth 2 x 1 quadlet per frame Description E mitb_t4650_6pin_3072fs_i_1q_cfg_setup txt Manual setup of test via E mitb 14650 6pin 3072fs i 1q
79. isochronous data The MediaLB device interface realizes the hardware port required to transmit and receive the data patterns on MediaLB The PowerPC is linked to a host PC via an RS232 interface A GUI running on the host PC allows the configuration of the generated test patterns as well as the configuration of the MediaLB controller INIC connected to the MDUT and enables the visualization of pattern verification results and error reporting In addition to the GUI the MITB Platform features a LCD display and LEDs to provide status information like MOST and MediaLB Lock conditions User Manual Copyright O 2011 SMSC Page 10 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X An optical MOST150 network is used as connection between the user hardware and the MITB Platform On the MITB Platform the MOST150 interface is realized by a special add on card also referred to as Physical Interface Board 0581110 which features 0581110 MOST150 transceiver as well as a MOST150 2 0 Fiber Optic Transceiver FOT unit The FPGA on the MITB Platform and the 0581110 the Phy Board are connected via a MediaLB 6 Pin interface The user hardware also needs to have a MOST150 interface Dependent on the available user hardware this can be done by the Phy Board by integrating 0581110 MOST150 transceiver and the FOT unit on the user hardware Based on different types of user hardware the M
80. length control async packet size Isochronous 196 bytes Packet delay 12 000 us message throughput 50mgs s packet throughput 1000 kbit s Test 7 Configuration mitb 15463 6pin 2048fs casi cfg setup txt Manual setup of test via Files mitb 15463 2048fs casi start txt GUI possible ediaLb O atio Interface Clock Transferred Physical Channel PON ses Mode Speed Data Types Channel Address eder tarsier PCO 0x01FE PC1 0x0004 Control Tx PC2 0x0002 Control Rx PC3 0x0006 Rx Control 4 0 0008 Device 6 Pin 2048xFs ae 5 0x000A Sync Rx nc Isoc d PC6 0x000C Sync Tx PC7 0 000 Isoc Rx 0x0010 Isoc Tx PC57 0x003E GUI Configuration Configuration Tab DUT DUT DUT MOST MediaLB MediaLB Trigger on Reese Pon Interface Clock Error Mode Speed User configurable 6 Pin 2048xFs 0101h Disable O ol Da D Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum x Message Length Length Length pe Length bytes bytes bytes jn 9 Enable 6 45 1 1 Test Continuous Throughput Message Pattern Test 1505 5 msgs Disable 5000 50 Enable Byte Counter Table 8 104 mitb_t5643_6pin_2048fs_casi Part 1 Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 193 MediaLB Interface Test Bench e
81. ls el Interface Clock Ad idee Mode Speed User 6 2048xFs 0101h configurable ono Br e Rx Blockwidth Frame Pattern Channel Channel quadlets Address Address frame 0x000A 0x000C 1 Enable Counter ono Vata Rx Blockwidth Packet Siz Packet Channel Channel quadlets Flow Control Throughput Address Address frame y kbit s 0 000 0 0010 1 Disable 188 1000 Continuous Pattern Test pkts Disable 10 000 Enable ounter Table 8 101 mitb_t5641_6pin_2048fs_si User Manual Copyright 2011 SMSC Page 190 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cSnmnsc V2 2 X 8 6 9 mitb t5642 6pin 2048fs casi 1024xFs test 4 data types Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data Characteristic Blockwidth 2 x 1 quadlet per frame per loopback Fixed Packet Length Control 8 bytes Asynchronous 14 bytes 188 bytes Isoc Blocksize Packet Delay 2000 us message Throughput 450mgs s 1000 kbit s COM DEN mitb 15462 2048fs casi cfg setup txt Manual setup of test via ec mitb 15462 6pin 2048fs casi cfg start txt GUI possible ediaLb O Interface Clock Transferred Physical Channel PON ses Mode Speed Data Types Channel Address Allocated Transfer PCO 0x01FE PC1 0x0004 Control Tx PC2 0x
82. m 6 Pin 2048 0101h ono BEIE Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum 2 Packet Length Length Length boa br Length bytes bytes bytes p Disable 16 Test Packet Duration Delay m pkts us yte Enable 5000 2000 Enable Counter Table 8 43 mitb_t2640_6pin_2048fs_a_1q User Manual Copyright 2011 SMSC Page 128 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 3 16 12641 6pin 2048fs a 274 2048xFs test with 2 x 274 blockwidth Test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 27 quadlet per frame Characteristic _ Variable Packet Length Packet Delay 2000 us oT mitb 12641 204815 279 setup txt Manual setup of test via Em mitb 12641 2048fs a 27q start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Por Moce Mode Speed Data Type Channel Address PCO 0x01FE PC1 0x0006 Async Rx Device 6 Pin 2048xFs Async 2 00006 Async Rx PC28 0x0008 Async Tx PC54 0x0008 Async Tx 57 0 0000 GUI Configuration Configuration Tab DUT DUT MediaLB PUT MOST RS232 Port Target Interface
83. may support only a sub set of the possible MediaLB functionality The MITB provides test cases for a wide variety of MediaLB parameters Dependent on the functionality supported by the MDUT the user can decide which of the provided test cases are useful to be tested at its MediaLB device The test cases defined by the MITB are described in chapter 7 3 7 1 Loop Back Functionality The loop back functionality on the MediaLB Device Under Test is a precondition for correct operation of test cases and required to perform the test scenarios provided by the MITB The loop back functionality includes the capability to receive data patterns on a MediaLB Rx channel and re transmit the patterns on a Tx channel without modifying the patterns The transferred test patterns are generated by the PGA part of the MITB and are transmitted on a Tx channel of the MediaLB Controller connected to the MDUT The patterns re transmitted by the MDUT are received by the MediaLB controller and analyzed by the PGA Errors in the received pattern are reported on the GUI of the MITB The test patterns can be of any data type such as control asynchronous synchronous or isochronous data The MITB comprises test cases transferring single data types as well as combined test cases with the concurrent transfer of several data types The test definitions include ChannelAddresses used to transmit and receive test patterns To successfully run a selected test the MDUT must be confi
84. mitb t5330 1024fs cas Part T esiisaks enn 180 mitb 15330 1024fs cas Part 2 181 15331 1024fs casi Part 1 182 mitb t5331 1024fs casi 2 183 mitb_t5332_3pin_1024fs_casi Part 1 184 mitb_t5332_3pin_1024fs_casi 2 185 User Manual Page 206 Copyright 2011 SMSC Document Version 2 2 Date 2011 12 09 MediaLB Interface Test Bench V2 2 X Table 8 97 mitb 15333 102415 csi Part 1 Table 8 98 mitb 15333 1024fs csi Part 2 Table 8 99 mitb 15640 6pin 204815 cas Part 1 mitb 15640 2048fs cas Part 2 mitb t5641 204815 5 mitb 15642 2048fs casi Part 1 Table 8 100 Table 8 101 Table 8 102 Table 8 103 Table 8 104 Table 8 105 Table 8 106 Table 8 107 Table 8 108 mitb t5642 6pin 2048fs casi mitb 15643 204815 casi Part 1 mitb 15643 204815 casi Part 2 mitb 19330 102415 mitb 19640 204
85. of test via e mitb 15462 6pin 2048fs casi cfg start txt GUI possible ono 2 Blockwidth MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum Packet Length Length Length ay Length bytes bytes bytes Disable 14 Continuous Vesi here Packet Pattern Test 9047 pkts us yte Disable 5000 12 000 Enable Counter Synchronous Data Test Tab Rx Blockwidth Channel Channel quadlets ae p Address Address frame yp Byte 0x000A 0x000C 1 Enable Counter ono Vata Rx Blockwidth Packet Size Packet Channel Channel quadlets Flow Control bytes Throughput Address Address frame kbit s 0 000 0 0010 1 Disable 188 1000 Continuous Test Packet Pattern Test Counter Type pkts Disable 5000 Enable Table 8 103 mitb_t5642_6pin_2048fs_casi Part 2 User Manual Copyright 2011 SMSC Page 192 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cSnmnsc V2 2 X 8 6 10 mitb t5643 6pin 2048fs casi 2048xFs test all data types varied transfer parameter Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data Characteristic Blockwidth 2 x 1 quadlet per frame per loopback Varied msg packet
86. stop the test The Async Test Status Field provides an indication of the overall state of a test The state is indicated by four colors User Manual Page 51 Copyright O 2011 SMSC Document Version V2 2 X Date 2011 12 0902 MediaLB Interface Test Bench e SmS V2 2 X No Test Default state no active test Test Running Test active and running TEST FAILED Test is stopped and failed with errors detected in either the PGA Results or Statistics TEST PASSED Test is stopped and passed PGA Results Status Field The Async Results Status Field provides an indication of the PGA test results of actually received test patterns The state is indicated by four colors Grey No PGA Results Default state no active test Yellow Test Running Test active and running Red Results NOT OK Test is stopped Test failed with Pattern Errors as indicated in the PGA Results window Green PGA Results Test is stopped No pattern errors in received packets detected PGA Statistics Status The Async Statistics Status Field provides an indication of the PGA Field test statistics The state is indicated by four colors Grey No PGA Statistics Default state no active test Yellow Test Running Test active and running Red PGA Statistics NOT Test is stopped Test failed with uneven number of transmitted and received packets Green PGA Statistics OK Test i
87. test patterns The MITB configuration includes the setup of the PGA as well as the configuration of the OS81110 devices part of the MITB setup The configuration of the MITB can be done by means of a GUI which is running on the host PC 6 1 Execute the Graphical User Interface The MITB GUI runs on a host PC or laptop with a Windows OS XP or 2000 and supports communication with the MITB via an RS232 interface The GUI is part of the MITB delivery and can be found on the installation CD For details about the files provided on the installation CD refer to chapter 9 Summary of Provided Files To start the GUI double click the provided MITB GUI V02 02 XX exe file Parameters entered by the user on the GUI are saved to the file MITB GUI Parameters ini when the GUI is closed and re loaded when the GUI is started again 6 2 Description of the Graphical User Interface The following figure depicts the main window of the GUI MITB GUI V220 1 mx MediaLB Interface Test Bench and Analyze ie oa rator anc nalyzer M A Configuration Contro Asynchronous Synchronous Isochronous System Commands Status Initialization Configuration General W 5232 RS232 Port COM3 MDUT MediaLB Interface Mode 6 Pin Trigger on Error MOST MediaLB Clock Speed 2048xFs v Load Config File MediaLB Initialize MDUT MOST Target Address 0101 hex
88. test via E mitb 12320 512fs a 1q start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Data Address edis tensio PCO 0x01FE PC1 0x0006 Async Rx Device 3 Pin 512xFs Async PC2 0x0008 Async Tx PC15 0x0000 DUT DUT exce MESES Interface Clock Ad ae Mode Speed 3 Pin 512xFs 0101h ono BEIE Blockwidth Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Fixed Minimum Maximum 1 Packet Length Length Length ee D Length bytes bytes bytes Disable 14 Test Packet pue Duration Delay ad E pkts us yte Disable 5000 2000 Enable Counter Table 8 28 mitb 12320 3pin 512fs a 1q Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 109 MediaLB Interface Test Bench e smnsc V2 2 X 8 3 3 12321 3pin 51215 74 512xFs test with 2 x 7 blockwidth Test Concurrent Rx and Tx transfer of MediaLB asynchronous data Characteristic Blockwidth 2 x 7 quadlet per frame Variable Packet Length Packet Delay 2000 us cim on mitb_t2321_3pin_512fs_a_7q_cfg_setup txt Manual set
89. the receiving device 0581110 connected to the MDUT is responding with ReceiverBusy responses After the data transfer is started the MITB will generate a series of 32 consecutive ReceiverBusy response periods on the Control Rx Channel ChannelAddress 0x0002 of the 0581110 During each period the OS81110 generates ReceiverBusy responses in every frame on the Control Rx Channel for approximately ms After a delay of 500 ms at which the 0581110 is able to receive data indicated by ReceiverReady responses the next ReceiverBusy period starts The ReceiverBusy responses indicate that the 0581110 connected to the MDUT is not able to receive data The ReceiverBusy responses need to be detected by the MDUT and transmitted data quadlets acknowledged by ReceiverBusy response must be repeatedly transmitted until ReceiverReady response is detected The user must verify this behaviour manually The MITB does not provide an indication if the ReceiverBusy is handled properly by the MDUT To verify the MDUT behavior and capture the generated ReceiverBusy responses generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the 0581110 is generating ReceiverBusy responses randomly it cannot be guaranteed that the ReceiverBusy responses always happen at times when the MDUT is transmitting control messages By that means it is not guaranteed that MediaLB commands 0x30 0x32 and 0x34 transmitted by th
90. the result report is 1 s xs If test is started by loading a configuration file the period used to generate the result report is defined in the loaded file LockState Pattern Unlock Pattern Analyzer receives invalid messages Pattern Search Pattern Analyzer received a valid message and waits to receive the next message in the correct sequence Pattern Locked Pattern Analyzer receives valid messages ErrorType No Error No error detected Corrupted Msg Message incorporates error in payload Missed Msg Error in received message sequence detected Table 6 4 Control Results Log A successful control data test indicates e No Locks 1 e No Errors 0 Missed 0 msgs User Manual Copyright 2011 SMSC Page 48 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e smscC V2 2 X The test result is indicated on the test status field next to the Start Stop Button as soon as a test is stopped 6 2 2 3 Control Statistics Log The PGA s Control Statistics Log displays information about transmitted received and missed packets The values displayed in the Control Statistic Log are described in the following table Name Description MCM Tx Number of messages transmitted in TimeWindow MCM Tx Total Total number of messages transmitted from beginning of test MCM Rx Number of messages received in TimeWindow MCM Rx Total Total number of messages received from beginning of test MCM Mis
91. to transfer synchronous streaming data MediaLB Port used to transfer synchronous streaming data ReportType Once Result report is generated once Forever Result report is generated successive result report is defined in the loaded file LockState Pattern Unlock Pattern Analyzer receives invalid synchronous streaming data Pattern Search Pattern Analyzer received valid synchronous streaming data and TimeWindow 1s If testis started manually the period used to generate the result report is 15 XS If test is started by loading a configuration file the period used to generate the Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 55 MediaLB Interface Test Bench e smsc V2 2 X waits to receive the next synchronous data in the correct sequence Pattern Locked Pattern Analyzer receives valid synchronous streaming data ErrorType No Error No error detected Corrupted Msg Synchronous streaming data incorporates errors Missed Msg Error in received synchronous streaming data sequence detected Number of transitions from unlock to lock state Number of detected errors Frame counter value on which an error was detected Byte number pointing to start of quadlet on which an error was detected Received frame counter value Expected frame counter value Table 6 10 Synchronous Results Log A successful synchronous data test indicates e Locks 11 Errors
92. without limitation any and all implied warranties of merchantability fitness for a particular purpose title and against infringement and the like and any and all warranties arising from any course of dealing or usage of trade In no event shall SMSC be liable for any direct incidental indirect special punitive or consequential damages or for lost data profits savings or revenues of kind regardless of the form of action whether based on contract tort negligence of SMSC or others strict liability breach of warranty or otherwise whether or not any remedy of buyer is held to have failed of its essential purpose and whether or not SMSC has been advised of the possibility of such damages User Manual Copyright O 2011 SMSC Page 2 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X MediaLB Interface Test Bench Copyright 2011 SMSC All rights reserved Copyright 2011 SMSC User Manual Document Version 2 2 Date 201 1 12 0902 Page 3 MediaLB Interface Test Bench e 5 V2 2 X Document History Version Date Section Comment on Changes V2 2 X 1 2011 12 09 2 3 Functional Restrictions Max Synchronous Bandwidth is 15 quadlets 6 2 Split Test Status Fields for all data types Updated screen shots Added value range for parameters 3 6 2 1 Added paragraph with detailed description wiring of Phy Board on DUT V2 1 X 2 2011 02 10 8 7
93. 000 kbit s Table 8 86 Combined Test Overview Part 2 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 175 MediaLB Interface Test Bench e lt 5 71 lt V2 2 X 8 6 1 mitb t5310 3pin 256fs cas Basic 256xFs test Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous data Blockwidth 2 x 1 quadlet per frame per data type Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s Characteristic mitb_t5310_3pin_256fs_cas_cfg_setup txt Manual setup of test via mitb_t5310_3pin_256fs_cas_cfg_start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pot Moce Mode Speed Data Types Channel Address Allocated PCO 0x01FE PC1 0x0004 Control Tx PC2 0x0002 Control Rx Device 3 Pin 256xFs n Tr 0 0006 Async Rx syne gt y PC4 0x0008 Async Tx PC5 0 000 Sync Rx PC6 0x000C Sync Tx PC7 0x003E GUI Configuration Configuration Tab DUT DUT MediaLB DUT MOST RS232 Port Target Interface Clock Address Mode Speed User 3 Pin 256xFs 0101h configurable ol D D Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum 1 Message Length Length Length y ibas n Length bytes b
94. 0002 Control Rx PC3 0x0006 Rx Control 4 0 0008 Device 6 Pin 2048xFs ae 5 0x000A Sync Rx 6 0x000C Sync Tx PC7 0 000 Isoc Rx 0 0010 Isoc Tx PC57 0x003E GUI Configuration Configuration Tab DUT DUT DUT MOST MediaLB MediaLB Trigger on PEDIS Fari Interface Clock Error Mode Speed Gest 6 Pin 2048xFs 0101h Disable configurable O ol Da D Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum m Message Length Length Length Els Length bytes bytes bytes yt 9 Disable 8 Conti Test ontinuous Duration Throughput Message Pattern Test msgs msgs s Counter Type Disable 5000 50 Enable E ounter Table 8 102 mitb 15642 204815 casi Part 1 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 191 MediaLB Interface Test Bench e SmS V2 2 X 1024xFs test 4 data types Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data E Blockwidth 2 x 1 quadlet per frame per loopback Fixed Packet Length Control 8 bytes Asynchronous 14 bytes 188 bytes Isoc Blocksize Packet Delay 2000 us message Throughput 450mgs s 1000 kbit s T eee mitb_t5462_6pin_2048fs_casi_cfg_setup txt Manual setup
95. 010 1 Disable 188 1000 Continuous Pattern Test okts Counter Type Disable 5000 Enable Counter Table 8 74 mitb 14330 3pin 1024fs i 1q Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 163 MediaLB Interface Test Bench V2 2 X smsc 8 5 4 mitb t4331 3pin 1024fs 74 1024xFs test with alternating Tx Rx ChannelAddresses _ Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 7 quadlet per frame CA 0x003C amp CA 0x003E mitb_t4331_3pin_1024fs_i_7q_cfg_setup txt Manual setup of test via es mitb_t4331_3pin_1024fs_i_7q_cfg_start txt GUI possible ediaLb Interface Clock Transferred Physical Channel Mode Speed Data Types Channel Address Alesit Tensiar PCO 0x01FE PC1 0x003C Isoc Rx PC2 0x003E Isoc Tx PC3 0x003C 5 Rx PC4 0x003C 5 Rx PC5 0x003E 5 Tx PC6 0x003E 5 Tx PC7 0x003C 5 Rx Device 3 Pin 1024xFs Isoc PC8 0x003C Isoc Rx PC9 0x003C Isoc Rx PC10 0x003E 5 Tx 11 0x003E 5 Tx PC12 0x003E Isoc Tx PC13 0x003C Isoc Rx PC14 0x003E Isoc Tx PC31 0x0000 DUT DUT MOST RS232 Port MediaLB Clock Target Pin Mode Speed Address User configurable 3 Pin 1024xFs 0101h isochronous Data Test Tab Tx
96. 011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 131 MediaLB Interface Test Bench V2 2 X SMSE 2048xFs test with ReceiverBusy Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Test Fixed Packet Length 14 Bytes Characteristic Packet Delay 2000 us MITB generates series of 20 consecutive ReceiverBusy response periods on Async Rx Channel ChannelAddress 0x0008 of the MDUT 581110 During each period ReceiverBusy responses generated in every frame for approximately 2 ms After delay of 110 ms next ReceiverBusy period starts Bees tas mitb_t2643_6pin_2048fs_a_1q_cfg_setup txt Manual setup of test via En mitb 12643 2048fs a 1q start txt GUI possible ediaLb atio Interface Transferred Physical Channel Port Mode Clock Speed Data Type Channel adress Allocated Transfer PCO 0x01FE PC1 0x0006 Async Rx Device 6 Pin 2048xFs Async PC2 0x0008 Async Tx PC57 0x0000 MEUS DUT DUT MOST RS232 Port MediaLB Target Clock Speed Address ass 6 Pin 2048xFs 0101h configurable Asynchronous Data Test Tab Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum T Packet Length Length Len
97. 02 Packet 1 Packet 2 Packet 3 Pattern Type Random Packet Index Packet 1 00 00 00 00 Packet 2 00 00 00 O1 00 00 00 02 Table 7 2 MDP Format Description User Manual Copyright 2011 SMSC Page 68 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench er smsc V2 2 X 7 2 2 MOST Ethernet Packets MEPs MEPs support a maximum packet length of 1526 bytes The MEP format is depicted below 26 bytes 26 1526 bytes 0 1500 data bytes Port Message Length PML Port Message Header PMH O Port Message Body PMB Figure 7 3 Ethernet Packet Format Copyright 2011 SMSC User Manual Page 69 Document Version V2 2 X Date 2011 12 0902 MediaLB Interface Test Bench e SmS V2 2 X Description 16 bit field indicating the total number of bytes that follow in the Port Message Header PMH and the Port Message Body PMB Single byte field indicating the byte length of the FIFO Protocol Header FPH and FIFO Data Header FDH Value is always set to 0x05 FPH Defines the Port Message Type and the FIFO to be targeted Value is always set to 0x24 For MEPs all bytes of the FDH are 0x00 Destination 48 bit field indicating the destination address of the Ethernet device of the MOST Address network being targeted Source 48 bit field indicating the source address of the Ethernet device of the MOST Address network sourcing the packet data
98. 04 Async Rx PC5 0x0004 Async Rx Device 3 Pin 1024xFs Async PC6 0x0002 Async Tx PC10 0x0002 Async Tx PC31 0x0000 DUT DUT edite Med td Interface Clock Ad dud Mode Speed oU 3 Pin 1024xFs 0101h ono Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x111111 0x333333 0x0004 0x0002 5 Enable 222222 444444 Varied Fixed Minimum Maximum Packet Length Length Length pos Be Length bytes bytes bytes Enable 6 1506 1 1 5 Test Packet Duration Delay Saas E pkts us yte Disable 5000 2000 Enable Counter Table 8 38 mitb_t2336_3pin_1024fs_a_5q Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 119 MediaLB Interface Test Bench e smsc V2 2 X 8 3 11 mitb 12338 3pin 1024fs 14 The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is transmitting Async data and the receiving device OS81110 connected to the MDUT is responding with ReceiverBusy responses After the data transfer is started the MITB will generate a series of 20 consecutive ReceiverBusy response periods on the Async Rx Channel ChannelAddress 0x0008 of the OS81110 During each period the OS81110 generates ReceiverBusy responses in every frame on the Async Rx Channel for approximately 2 ms After a delay of 110 ms at which the OS81110 is able to receive data
99. 0x0002 0x0004 Varied Fixed Minimum Maximum Length Length Length pu pog Length bytes bytes bytes 9 Disable 45 Continuous Test Duration Throughput Message Delay RxResp Test msgs msgs s Counter Type 88 Nir ms Disable 5000 500 Enable Byte Counter ReceiverBusy 20 100 Table 8 15 mitb_t1641_6pin_2048fs_c_1q Copyright 2011 SMSC User Manual Page 93 MediaLB Interface Test Bench e smsc V2 2 X 8 2 13 mitb t1642 6pin 2048fs 14 The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is transmitting control data and the receiving device OS81110 connected to the MDUT is responding with ReceiverBreak responses After the data transfer is started the MITB will generate 48 HeceiverBreak responses on the Control Rx Channel ChannelAddress 0x0002 of the OS81110 ReceiverBreak responses are generated with a delay of 200 ms between consecutive ReceiverBreaks The MDUT transmitting control messages needs to detect the ReceiverBreak responses Following the detection of the ReceiverBreak the MDUT must stop message transmission The user needs to verify manually that the MDUT is properly terminating the message transmission Additionally it may be verified if MDUT internally a status indicating the detection of the HeceiverBreak response is signalled The MITB does not provide an indication if the is handling the ReceiverBreaks as expected
100. 0x0006 Async Rx Device 6 Pin 2048xFs Async PC2 0x0008 Async Tx PC57 0x0000 DUT DUT DUT MOST RS232 Port MediaLB MediaLB Target Interface Clock Speed 6 Pin 2048 0101h Asynchronous Data Test Tab Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Address Address frame Address Source Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum im Packet Length Length Length d EM Length bytes bytes bytes Disable 16 Test Packet Delay P Duration Delay id Pur RxResp Nr RxResp RxResp pkts us ms Byte Enable 5000 2000 Enable amat ReceiverProtocolError 32 100 Table 8 48 mitb 12645 6pin 2048fs a 14 User Manual Copyright O 2011 SMSC Page 136 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 8 3 21 mitb t2646 6pin 2048fs a 4q The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is receiving async data and the transmitting device OS81110 connected to the MDUT is sending AsyncBreak commands After the data transfer is started the MITB will transmit 16 AsyncBreak command on the Async Tx Channel ChannelAddress 0x0004 of the OS81110 AsyncBreak commands are generated with a delay of 5 ms between consecutive AsyncBreaks The MDUT receiving async packets needs to detect the AsyncBreak commands Following the detection of the AsyncBreak the MDUT must stop an ongoing pack
101. 1 11640 2048fs 14 Basic 2048xFs test Concurrent Rx and Tx transfer of MediaLB control data Description Blockwidth 2 x 1 quadlet per frame Fixed 33 Bytes Throughput 450 msgs s ee mitb_t1640_6pin_2048fs_c_1q_cfg_setup txt Manual setup of test via Em mitb 11640 204815 14 start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Por Moce Mode Speed Data Type Channel Address PCO 0x01FE PC1 0x0004 Control Tx Device 6 Pin 2048xFs Control Pez Control Rx 57 0x003E Unused DUT DUT Rs2so Pon MedialB MOST Interface Clock Ad fee Mode Speed 6 Pin 2048xFs 0101h Control Data Test Tab Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum Message Length Length Length ids bcn Length bytes bytes bytes 9 Disable 32 Continuous Pom Throughput Message Pattern Test msgs msgs s Counter Type Disable 5000 450 Enable cunta Table 8 14 mitb_t1640_6pin_2048fs_c_1q Copyright 2011 SMSC Document Version V2 2 X Date 2011 12 0902 User Manual Page 91 MediaLB Interface Test Bench e smsc V2 2 X 8 2 12 mitb 11641 2048fs 14 The purpose of this test is to verify the correct behavior of the MediaLB DUT case it is transmitting control data and
102. 1 0x003E GUI Configuration Configuration Tab DUT DUT DUT MOST RS232 Port MediaLB MediaLB Target Trigger on Interface Clock Address Error Mode Speed User configurable 3 Pin 1024xFs 0101h Disable O ol Da D Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum m Message Length Length Length pe Length bytes bytes bytes jn 9 Enable 6 45 1 1 Test Continuous Duration Throughput Message Pattern Test msgs msgs s Counter Type Disable 5000 50 Enable Byte Counter Table 8 95 mitb 15332 102415 casi Part 1 User Manual Copyright 2011 SMSC Page 184 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 1024xFs test 4 data types Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data hes E Blockwidth 2 x 1 quadlet per frame per loopback Fixed packet msg length control 8 bytes asynchronous 14 bytes isochronous 188 bytes Packet Delay 12 000 us Message Throughput 50mgs s 1000 kbit s TM LE mitb 15332 Spin 1024fs casi setup txt Manual setup of test via e mitb 15332 Spin 1024fs casi cfg start txt GUI possible ono 2 D Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disa
103. 14 Bytes Throughput 550 msgs s mitb_t1330_3pin_1024fs_c_1q Basic 1024xFs test Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 28 Bytes Throughput 450 msgs s mitb_t1331_3pin_1024fs_c_1q 1024xFs test with min and max Message Length Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Variable Message Length Throughput 450 msgs s mitb_t1332_3pin_1024fs_c_1q 1024xFs test with maximum Message Throughput Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Variable Message Length Throughput 475 msgs s mitb_t1333_3pin_1024fs_c_1q 1024 5 test with none default ChannelAddresses Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Variable Message Length Throughput 475 msgs s CA 0x0012 CA 0x0026 mitb t1335 Spin 102415 c 19 1024xFs test with RxBusy Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes Throughput 500 msgs s Table 8 1 Control Test Overview Part 1 User Manual Copyright O 2011 SMSC Page 74 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e smsc V2 2 X Test Test Characteristics MediaLB 3 pin Tes
104. 181 MediaLB Interface Test Bench e SmS V2 2 X 8 6 4 mitb_t5331_3pin_1024fs_casi 1024xFs test 4 data types Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data Characteristic Blockwidth 2 x 1 quadlet per frame per loopback Fixed packet msg length control 8 bytes asynchronous 14 bytes isochronous 188 bytes Packet Delay 12 000 us Message Throughput 50mgs s 1000 kbit s Test 7 Configuration mitb 15331 3pin 1024fs casi cfg setup txt Manual setup of test via Files mitb 15331 Spin 1024fs casi cfg start txt GUI possible ediaLb O Interface Clock Transferred Physical Channel PON ses Mode Speed Data Types Channel Address eder tarsier PCO 0x01FE PC1 0x0004 Control Tx PC2 0x0002 Control Rx PC3 0x0006 Rx Control 4 0 0008 Device 3 Pin 1024xFs ae 5 0x000A Sync Rx nc Isoc d PC6 0x000C Sync Tx PC7 0x000E Isoc Rx PC8 0x0010 Isoc Tx PC31 0x003E GUI Configuration Configuration Tab DUT DUT DUT MOST MediaLB MediaLB Trigger on Reese Pon Interface Clock Error Mode Speed User configurable 3 Pin 1024xFs 0101h Disable O ol Da D Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum x Message Length Length Length Els Length bytes bytes bytes
105. 2 09 MediaLB Interface Test Bench ee smsg V2 2 X 7 2 Asynchronous Packet Format Asynchronous data is transferred in packets The MITB supports the generation of MOST Data Packets MDPs and MOST Ethernet Packets MEPs The format of MDPs and MEPs is described in the following sections 7 2 1 MOST Data Packets MDPs MDPs support a maximum packet length of 1534 bytes The MDP format is depicted below 7 16 bytes gt 16 1534 bytes gt 0 1518 data bytes Port Message Length PML Port Message Header PMH L Port Message Body PMB Figure 7 2 Data Packet Format Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 67 MediaLB Interface Test Bench e SmS V2 2 X Description 16 bit field indicating the total number of bytes that follow in the Port Message Header PMH and the Port Message Body PMB 16 bit field indicating the total number of bytes which follow in the Port Message Body PMB including the two bytes of Packet Length itself Packet Length can be adjusted in the MITB GUI Minimum value 6 bytes Maximum value 1534 bytes Note Typically Length and Packet Length are identical Only in error case it may happen that length fields don t match Data Data bytes with pattern type Byte Counter or Random Number of data bytes can vary from 0 to 1518 bytes Pattern Type Byte Counter Packet Index 00 00 00 00 00 00 00 01 00 00 00
106. 2 14 mitb 11643 204815 6 14 iiie 96 8 2 15 mitb 11644 204818 6 14 98 82 16 11650 307218 0 100 8 2 17 11651 Spin 307218 26 101 8 2 18 mitb 11660 4096fs 14 102 8 2 19 mitb 11661 409616 Tornis 103 83 Asynchronous 104 8 3 1 12310 Spin 2565 108 8 3 2 12320 5121s 148 detener 109 8 3 3 mitb 12321 5121s a 79 110 8 3 4 mith 12330 10246 18 111 8 3 5 mitb 12331 102416 154 112 8 3 6 12332 102418 54 113 8 3 7 mitb 12333 102415 154 114 8 3 8 mitb 12334 102415 154 116 8 3 8 mitb 12335 102446 14 dede de d 118 8 3 10 12336 102415 tee 119 8 91 Mib 12338 1024 5 4 18 120 8 3 12 12339 102418 AAO ceto tertie tee ee ree 122 8 3 13 123310 102415 Qin eerte 124 8 3 14 123311 102415 40 eer ig etn e o 126 8 3 15 mith 12640 6pin 204818 14
107. 2 X 1024xFs test with ReceiverBusy responses generated by Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes mitb 11335 1024fs c 14 setup txt Description Throughput 500 msgs s MITB generates series of 20 consecutive ReceiverBusy response periods on Control Rx Channel ChannelAddress 0x0002 of the MDUT 0581110 During each period ReceiverBusy responses generated in every frame for approximately 3 ms after delay of 500 ms next ReceiverBusy period starts Test Manual setup of test via configurable mitb_t1335_3pin_1024fs_c_1q_cfg_start txt GUI possible ediaLb O atio Transferred Physical Channel Port Mode Interface Mode Clock Speed Data Type Channel Address Allocated Transfer PCO 0x01FE PC1 0x0004 Control Tx Device 3 Pin 1024xFs Control PC2 0x0002 Control Rx PC31 0x003E GUI Configuration Configuration Tab DUT MediaLB DUT MediaLB DUT MOST puse Po Interface Mode Clock Speed Target Address DERE 3 Pin 1024xFs 0101h Control Data Test Tab Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum Message Length Length Length joa DD Length bytes bytes bytes 9 Disable 45 Continuous Test Duration Throughput Message Delay RxResp Test msgs msgs s
108. 2 x 5 quadlet per frame Variable Packet Length Packet Delay 1100 us 12333 102415 a 154 1024xFs test with alternating physical positions for Rx and Tx channels Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 15 quadlet per frame Variable Packet Length Packet Delay 2000 us Table 8 23 Asynchronous Test Overview Part 1 User Manual Page 104 Copyright O 2011 SMSC Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e smsc V2 2 X Test Name Test Characteristics 22222 Tests mitb 12334 Spin 102415 154 1024xFs test with alternating physical positions for Rx Tx channels Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 15 quadlet per frame Variable Packet Length Packet Delay 2000 us mitb_t2335_3pin_1024fs_a_1q 1024xFs test with minimum Packet Delay and ChannelAddresses in the upper address range Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Variable Packet Length Packet Delay 5200 us CA 0x003A CA 0x003E mitb_t2336_3pin_1024fs_a_5q 1024xFs test with MEP transfer min and max MEP packet length Concurrent Rx and Tx transfer of MediaLB asynchronous MEP data packets Blockwidth 2 x 5 quadlet per frame Variable Packet Length Packet Delay 2000 us mitb_t23
109. 2_3pin_1024fs_s_3q_cfg_start txt GUI possible B Clock Transferred Physical Channel Pori Moce Mode Speed Data Types Channel Address 0 PCO 0x01FE PC1 0x003E Sync Tx 2 0x003C Sync Rx PC3 0x003E Sync Tx Device 3 Pin 1024xFs Sync PC4 0x003E Sync Tx 5 0x003C Sync Rx PC6 0x003C Sync Rx PC31 0x0000 PGA GUI Configuration Configuration Tab DUT Vets Bun Most RS232 Port MediaLB Clock Target Pin Mode Speed Address mE 3 Pin 1024xFs 0101h ono Vata Blockwidth Channel Channel quadlets ui Buen Address Address frame 0x003C 0x003E 3 Enable Counter Table 8 59 13332 1024fs s 34 User Manual Copyright 2011 SMSC Page 148 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X 8 4 6 mitb t3333 3pin 1024fs s 74 smsc Document Version V2 2 X Date 2011 12 0902 1024xFs test with alternating Tx Rx ChannelAddresses Description Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 7 quadlet per frame TM EAE mitb 13333 3pin 1024fs s 7q cfg setup txt Manual setup of test via Files mitb 13333 1024fs 5 79 start txt GUI possible D ediaL B atio Interface Clock Transferred Physical Channel Par Meze Mode Speed D
110. 3 6 Pin Device Under Test MDUT o Connected to the OS81110 via 3 Pin single ended and or 6 Pin differential MediaLB interface o Must provide loop back functionality to allow reception and re transmission of test patterns e 0581110 MOST150 INIC transceiver o Connected to MDUT via single ended 3 Pin and or differential 6 Pin MediaLB interface o Functions as MediaLB controller o Flashed with special 0581110 test firmware o Functions as gateway between MOST network and MediaLB Port of MDUT Optical MOST150 interface o MOST150 2 0 Header e 3 6 high speed debug header o Required to connect MediaLB Analyzer for analysis of MediaLB data flow e Configuration debug header o Required to flash OS81110 MOST150 transceiver with dedicated MITB OS81110 test firmware or standard INIC firmware For layout information on the MediaLB 3 6 Pin high speed debug header and the configuration debug header refer to section 3 6 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 23 MediaLB Interface Test Bench e smsc V2 2 X 2 6 Further Reading This user manual describes the setup and usage of the MITB and its components For detailed information about the INIC Explorer Interface Box refer to the INIC Explorer User Manual 1 For further information about the MediaLB Analyzer refer to the MediaLB Analyzer User Manual 2 Information on the Physical Board OS81110 3
111. 32 Port MediaLB Clock Target Pin Mode Speed Address User 3 Pin 512xFs 0101h configurable Data Test Tab Tx Rx Blockwidth Packet Size Packet Channel Channel quadlets Flow Control bytes Throughput Address Address frame kbit s 0 000 0 0010 1 Disable 188 1000 Test ee pkts Byte Disable 5000 Enable Counter Table 8 73 mitb 14320 512fs 14 User Manual Copyright O 2011 SMSC Page 162 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cSnmnsc V2 2 X 8 5 3 mitb t4330 3pin 1024fs i 1q Basic 1024xFs test Description Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 1 quadlet per frame mitb 14330 3pin 1024fs i 19 setup txt Manual setup of test via Configuration Files 14330 1024fs 19 start txt GUI possible D ediaL B atio Interface Clock Transferred Physical Channel Pan Meze Mode Speed Data Types Channel Address 0x01FE PC1 0x000E Isoc Rx Device 3 Pin 1024xFs Isoc PC2 0x0010 Isoc Tx PC31 0x0000 DUT eens EU tuer RS232 Port MediaLB Clock Target Pin Mode Speed Address User 3 Pin 1024xFs 0101h configurable isochronous Data Test Tab Tx Rx Blockwidth Packet Size Packet Channel Channel quadlets Flow Control bytes Throughput Address Address frame kbit s 0x000E 0x0
112. 33 1024fs c 14 setup txt Manual setup of test via E mitb 11333 1024fs c 14 start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pan vecs Mode Speed Data Type Channel Address Allocated Transfer PCO 0x01FE Device 3 Pin 1024xFs Control 15 00026 Gomme Ds PC28 0x0012 Control Rx PC31 0x003E DUT DUT MediaLB PUT MOST RS232 Port Target Interface Clock User configurable 3 Pin 1024xFs 0101h O oi D D Tx Rx Channel Channel Address Address 0x0012 0x0026 Varied Fixed Minimum Maximum increments Repetition Message Length Length Length bytes 5 5 5 Length bytes bytes bytes 9 Enable 6 45 1 1 Test Continuous Throughput Message Pattern Test msgs s Counter Type msgs Disable 5000 475 Enable Counter Table 8 9 mitb_t1333_3pin_1024fs_c_1q User Manual Copyright 2011 SMSC Page 82 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 8 2 7 mitb 11335 3pin 1024145 14 The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is transmitting control data and the receiving device OS81110 connected to the MDUT is responding with ReceiverBusy responses After the data transfer is started the MITB will generate a series of 20 cons
113. 330 1024fs a 14 start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Por Mace Mode Speed Data Type Channel Address Allocated Wem PCO 0x01FE PC1 0x0006 Async Rx Device 3 Pin 1024xFs Async PC2 0x0008 Async Tx PC31 0x0000 DUT DUT MediaLB MOST Interface Clock Ad Phan Mode Speed o 3 Pin 1024xFs 0101h ono BEIE e Blockwidth Channel Channel quadlets Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable 2 Varied Fixed Minimum Maximum e Packet Length Length Length x n E Length bytes bytes bytes Disable 14 7 Test Packet Duration Delay ae Em pkts us Byte Enable 5000 2000 Enable Counter Table 8 30 mitb_t2330_3pin_1024fs_a_1q Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 111 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 3 5 mitb 12331 3pin 1024fs a 15q 1024xFs test with 2 154 blockwidth Test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 15 quadlet per frame Characteristic _ Variable Packet Length Packet Delay 2000 us ee mitb_t2331_3pin_1024fs_a_15q_cfg_setup txt Manual setup of test via E mitb 12331 1024fs 154 start txt GUI possible DUT MediaLB Configuration Inte
114. 38_3pin_1024fs_a_1q 1024xFs test with RxBusy Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 14 Bytes Packet Delay 2000 us mitb_t2339_3pin_1024fs_a_4q 1024xFs test with RxBreak Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 4 quadlet per frame Fixed Packet Length 500 Bytes Packet Delay 1500 us mitb 123310 3pin 1024fs a 1q 1024xFs test with RxProtErr Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 14 Bytes Packet Delay 2000 us mitb 123311 1024fs 44 1024xFs test with Tx Break Command generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 4 quadlet per frame Fixed Packet Length 500 Bytes Packet Delay 2000 us Table 8 24 Asynchronous Test Overview Part 2 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 105 MediaLB Interface Test Bench e cnmnsc V2 2 X Test Name Test Characteristics MediaLB 6 pin Tests mitb_t2640_6pin_2048fs_a_1q Basic 2048xFs test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 16 Bytes Packet Delay 2000 us mitb 12641 6pin 2048fs 279
115. 4 start txt GUI possible GUI Configuration Configuration Tab DUT DUT RS232 Port MediaLB MediaLB Interface Clock Ad Speed 3 Pin 1024xFs 0101h ono Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0002 0x0004 15 Disable Fixed Minimum Maximum 2 Length Length Length noremens Repetitions Length bytes bytes bytes Enable 7 1014 1 1 Test Packet Duration Delay Packet Pattern est okts us Counter Type Disable 5000 2000 Enable Random Table 8 36 mitb_t2334_3pin_1024fs_a_15q Part 2 Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 117 MediaLB Interface Test Bench e smnsc V2 2 X 8 3 9 12335 3pin 1024fs 14 1024xFs test with minimum Packet Delay and ChannelAddresses in the upper address range Concurrent Rx and Tx transfer of MediaLB asynchronous data Test Blockwidth 2 x 1 quadlet per frame Characteristic Variable Packet Length Packet Delay 1000 us CA 0x003A CA 0x0038 Test mitb 12335 1024fs 14 setup txt Manual setup of test via mitb_t2335_3pin_1024fs_a_1q_cfg_start txt GUI possible D ediaL B Interface Clock Transferred Physical Channel Pan Mede Mode Speed Data Type
116. 5 14 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 145 MediaLB Interface Test Bench e smsc V2 2 X 8 4 3 13330 3pin 1024fs s 14 Basic 1024xFs test Description Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame mitb_t3330_3pin_1024fs_s_1q_cfg_setup txt Manual setup of test via Files mitb_t3330_3pin_1024fs_s_1q_cfg_start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel pendere Mode Speed Data Types Channel Address 0x01FE PC1 0x0016 Sync Rx Device 3 Pin 1024xFs Sync PC2 0x0018 Sync Tx PC31 0x0000 DUT RS232 Port MediaLB Clock Target Pin Mode Speed Address User configurable 3 Pin 1024xFs 0101h Synchronous Data Test Tab Blockwidth Fram Pattern Channel Channel quadlets CR e ah Address Address frame yp 0x0016 0x0018 1 Enable Byte Counter Table 8 57 mitb 13330 1024fs s 14 User Manual Copyright 2011 SMSC Page 146 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X 8 4 4 mitb t3331 3pin 1024fs s 34 1024xFs test with alternating Tx Rx ChannelAddresses Concurrent Rx and Tx transfer of MediaLB synchronous data smsc
117. 50 Enable Counter Table 8 4 mitb_t1310_3pin_256fs_c_1q Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 77 MediaLB Interface Test Bench V2 2 X 8 2 2 11320 3pin 51215 14 Basic 512xFs test Concurrent Rx and Tx transfer of MediaLB control data Description Blockwidth 2 x 1 quadlet per frame Fixed Message Length 14 Bytes Throughput 550 msgs s M mitb 11320 512fs 14 setup txt Manual setup of test via E mitb t1320 512fs c 1q cfg start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pen Mocs Mode Speed Data Type Channel Address sen 0x01FE PC1 0x0004 Control Tx Device 3 Pin 512xFs Control PC2 0x0002 Control Rx PC15 0x003E DUT DUT E Interface Clock Ad Speed User configurable 3 Pin 512xFs 0101h O ol D Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum 5 Message Length Length Length boa d Length bytes bytes bytes 9 Disable 14 Test Continuous Duration Throughput Message Pattern Test msgs msgs s Counter Type Disable 5000 450 Enable Counter Table 8 5 mitb 11320 512fs c 14 User Manual Copyright O 2011 SMSC Page 78 Document Version V2 2 X Date 2011 12 09
118. 6 Pin 3072xFs Sync PC2 0x000C Sync Tx PC86 0x0000 DUT ues RS232 Port MediaLB Clock Target Pin Mode Speed Address 6 3072xFs 0101h Synchronous Data Test Tab Rx Blockwidth Channel Channel quadlets uus ud Address Address frame yp Byte 0x000A 0x000C 1 Enable Go nter Table 8 66 mitb 13650 307215 s 14 Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 155 MediaLB Interface Test Bench e smsc V2 2 X 8 4 13 mitb t3651 307215 s 154 3072xFs test with maximum bandwidth Concurrent Rx and Tx transfer of MediaLB synchronous data Y Blockwidth 2 x 15 quadlet per frame Description T mitb 13651 307216 s 154 setup txt Manual setup of test via Configuration Files mitb_t3651_6pin_3072fs_s_15q_cfg_start txt GUI possible ediaLb Interface Clock Transferred Physical Channel PON Mede Mode Speed Data Types Channel Address Allocated een 0x01FE PC1 0x000A Sync Rx PC15 0x000A Sync Rx Device 6 Pin 3072xFs Sync PC16 0x000C Sync Tx PC30 0x000C Sync Tx PC86 0x0000 DUT emus RS232 Port MediaLB Clock Target Pin Mode Speed Address 6 3072xFs 0101h configurable Synchronous Data Test Tab Tx Rx Blockwidth Channel Channel quadlets uns pa Address Address frame yp Byte 0x000A 0x000C 15 Enable cu
119. 8fs syscmd Copyright 2011 SMSC Document Version 2 2 Date 2011 12 0902 User Manual Page 207 MediaLB Interface Test Bench e smsc V2 2 X Appendix F Index M L 5 V power LED 25 LCD display 10 13 15 26 EE ee EL REX Rede e 2 A Limitations Asynchronous 10 0 2 Asynchronous 44244 0 40 1 48 Isochronous packets 20 ite en 20 C MOST150 Device 20 PLE 20 5 Loop back 10 33 Compolsory 7 21 Optio mall 22 Configuration setup 61 M Configuration tab 49 MDP format ettet ees 65 Configuration debug header 10 33 Control dala 10 MediaLB 3 6 Pin high speed debug 11 Control message 63 31 Control tab 45 Medial 3 6 Pin 12 MediaLB 3 Pin clock
120. 9 MediaLB Interface Test Bench e smsc V2 2 X Test Name Test Characteristics MediaLB 6 pin Tests mitb t3650 6pin 3072fs s 1q Basic 3072xFs test Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame mitb 13651 6pin 307215 5 154 3072xFs test with maximum bandwidth Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 15 quadlet per frame 13660 4096fs s 14 Basic 4096xFs test Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame mitb 13661 6pin 4096 5 5 154 4096xFs test with maximum bandwidth Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 15 quadlet per frame Table 8 54 Synchronous Test Overview Part 2 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 143 MediaLB Interface Test Bench V2 2 X 8 4 1 13310 3pin 256fs s 14 Basic 256xFs test Description Concurrent Rx Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame mitb_t3310_3pin_256fs_s_1q_cfg_setup txt Manual setup of test via mitb_t3310_3pin_256fs_s_1q_cfg_start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel pendere Mode Speed Data Types Channel Add
121. Bytes Packet Delay 2000 us mitb_t2310_3pin_256fs_a_1q_cfg_setup txt Manual setup of test via Em 12310 256fs 19 start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Por Mace Mode Speed Data Type Channel Address Allocated eneit PCO 0x01FE PC1 0x0006 Async Rx Device 3 Pin 256xFs Async PC2 0x0008 Async Tx PC7 0x0000 DUT DUT MediaLB MOST Interface Clock Ad vhs Mode Speed o 3 Pin 256xFs 0101h D ono Vata Blockwidth Channel Channel quadlets Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable 2 Varied Fixed Minimum Maximum Repetition Packet Length Length Length done i Length bytes bytes bytes Disable 14 7 Test Packet Duration Delay ae m pkts us Byte Disable 5000 2000 Enable Counter Table 8 27 mitb_t2310_3pin_256fs_a_1q User Manual Copyright 2011 SMSC Page 108 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 3 2 mitb 12320 3pin 512fs a 1q Basic 512xFs test Concurrent Rx and Tx transfer of MediaLB asynchronous data T Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 14 Bytes Packet Delay 2000 us m m 12320 512fs a 19 setup txt Manual setup of
122. Channel Address RIBERA PCO 0x01FE 1 0x003A Async Rx Device 3 Pin 1024xFs Async PC2 0x0038 Async Tx PC31 0x0000 DUT DUT MediaLB PUT MOST RS232 Port Target Interface Clock Speed 3 Pin 1024xFs 0101h Asynchronous Data Test Tab Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x003A 0x0038 1 Disable Varied Fixed Minimum Maximum Packet Length Length Length Bale ae Length bytes bytes bytes Enable 6 1014 1 1 Test Packet Duration Delay E pkts us yte Disable 5000 5200 Enable Gente Table 8 37 12335 1024fs 14 User Manual Copyright O 2011 SMSC Page 118 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 3 10 mitb 12336 3pin 1024fs 54 1024xFs test with MEP transfer Concurrent Rx and Tx transfer of MediaLB asynchronous MEP data packets PU NE Blockwidth 2 x 5 quadlet per frame Variable Packet Length Packet Delay 2000 us oT mitb 12336 102415 5 setup txt Manual setup of test via Em mitb 12336 1024fs a 5q start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pan Mede Mode Speed Data Type Channel Address PCO 0x01FE PC1 0x00
123. Counter Paien Type 88 Nir ms Disable 5000 500 Enable Byte Counter ReceiverBusy 20 500 Table 8 10 mitb_t1335_3pin_1024fs_c_1q User Manual Copyright 2011 SMSC Page 84 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 8 2 8 mitb t1336 3pin 1024fs c 1q The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is transmitting control data and the receiving device OS81110 connected to the MDUT is responding with ReceiverBreak responses After the data transfer is started the MITB will generate 48 HeceiverBreak responses on the Control Rx Channel ChannelAddress 0x0002 of the OS81110 ReceiverBreak responses are generated with a delay of 200 ms between consecutive ReceiverBreaks The MDUT transmitting control messages needs to detect the ReceiverBreak responses Following the detection of the ReceiverBreak the MDUT must stop message transmission The user needs to verify manually that the MDUT is properly terminating the message transmission Additionally it may be verified if MDUT internally a status indicating the detection of the HeceiverBreak response is signalled The MITB does not provide an indication if the is handling the ReceiverBreaks as expected To verify the MDUT behavior and capture the generated HeceiverBreak responses generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer
124. DUT In that case the ReceiverBusy responses have no effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverBusy response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case 11335 1024fs 14 indicates a TEST FAILED with missing messages in the MITB GUI for most cases This behavior is expected and is related to the nature of the MOST network and the OS81110 During the HeceiverBusy periods the OS81110 will not receive data from the MDUT via MediaLB Since loop back application of the MDUT cannot transmit any data it also will not be able to receive new messages from the OS81110 via MediaLB and the MITB respectively This again results in the OS81110 holding of messages received via MOST from the MITB platform Depending on how long the HeceiverBusy period lasts the OS81110 buffers will run full and messages transmitted from MITB platform to OS81110 via MOST will get lost on the MOST network There is no such thing as a ReceiverBusy response on MOST Because of this no feedback from the OS81110 connected to the DUT is passed to the OS81110 on the MITB platform indicating the buffer full condition of the DUT OS81110 and the MITB keeps transmitting messages which may get lost Copyright O 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 83 MediaLB Interface Test Bench V2
125. INX Virtex4 oe Test Firmware Character lt FX60 FPGA LCD 5 MediaLB PowerPC cassie Devi l 3 6 Pin Pattern ediaLB Device lt pry 38 Generator amp Host Bus Interface Macro DE 1 OS81110 PHY 0881110 gt Analyzer 3 i E Phys Board Variant 1 Phy Board Variant 1 or 3 L Status LEDs lt MediaLB 3 6 pin High Speed Debug Header MediaLB Interface Test Bench MITB User Hardware Figure 2 1 MediaLB Device Setup At this setup the user hardware is realized by a MediaLB device which needs to integrate the MDUT as well as MediaLB 3 6 Pin high speed debug header used to connect a Phy Board The Phy Board connected to the user hardware is required to realize the above outlined setup Given that the Phy Board connected to the user s MediaLB device is part of the MITB two interfaces are provided by the MITB configured as MediaLB Device Setup RS232 interface o Main interface to the GUI running on the host PC o Enables configuration of PGA software and definition of generated test patterns o Used to pass test results to the host PC 3 6 interface on high speed debug header of Phy Board connected to the user s MediaLB device o Supports single ended MediaLB 3 Pin interface o Supports differential MediaLB 6 Pin interface o Used to connect MDUT o Optionally used to conn
126. ITB can be arranged as MediaLB Device Setup see section 2 1 1 or MOST150 Device Setup see section 2 1 2 The MediaLB Device Setup is applicable when the user provides a MediaLB device without a MOST interface If the user owns a MOST150 device with an integrated MDUT as well as an MOST150 transceiver and an optical MOST150 interface it is recommended to use the MOST150 Device Setup Both setups are described in detail in the following sections Regardless which setup is used in both cases the 0581110 transceiver connected to the MDUT is configured remotely by the GUI running on the host PC via the MOST network This is required to configure the complete setup for a dedicated test case and to relief the user from configuring the 581110 0581110 connected the MDUT needs to be flashed with dedicated 0581110 test firmware which allows remote configuration and the generation of specific test scenarios By default the Phy Boards delivered with the MITB are flashed with this firmware An INIC Explorer 1 is required in case these Phy Boards need to be flashed with a firmware different than the MITB 581110 test firmware This may be required when the Phy Boards are re used for other applications than the or the MOST150 Device Setup is used and the 0581110 on the user hardware needs to be flashed with the 0581110 test firmware To complete the entire setup a MediaLB Analyzer 2 can be connect
127. ITB platform Refer to section 5 for details on how to flash the MITB platform Trigger Connector For debugging purposes the MITB platform features an error trigger connector See section 3 6 4 for details RJ 45 Connector For flashing FPGA images and Pattern Generator amp Analyzer software the MITB platform features an RJ 45 connector used to establish a 10 100 Ethernet connection to a host PC or laptop Refer to chapter 5 for details about flashing the MITB platform FPGA Configuration DONE LED This LED illuminates when the FPGA on the MITB platform has been properly configured FPGA PowerPC The MITB Platform features a XILINX Virtex4 FPGA with integrated PowerPC The PowerPC is used to run the Pattern Generator amp Analyzer firmware Additionally the FPGA integrates a MediaLB 6 Pin interface PGA Active LED This LED blinks periodically when the PGA is up and running PHY2 Active LED This LED illuminates when the MediaLB 6 Pin interface of the FPGA is enabled and configured to communicate with an INIC connected to the PHY2 Phy Board connector PHY2 Phy Board Connector This connector is used to mount a Phy Board Variant 1 optimized for MediaLB 6 communication to the MITB platform By default a Phy Board is pre installed on the MITB platform and the OS81110 on the Phy Board has been flashed with the proper firmware PHY2 3 3 V Power LED This LED illuminates when the 3 3 V power supply on the PHY2 Phy Board conne
128. LB Target Interface Clock Address Mode Speed 6 3072xFs 0101h Asynchronous Data Test Tab Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 27 Disable Varied Fixed Minimum Maximum T Packet Length Length Length Length bytes bytes bytes vies gg Enable 6 1014 1 1 Continuous Em E Packet Pattern Test pkts us Counter Type Disable 5000 6000 Enable Random Table 8 51 mitb 12651 307215 a 274 User Manual Copyright O 2011 SMSC Page 140 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 3 24 mitb 12660 4096fs 1q Basic 4096xFs test Test Concurrent Rx and Tx transfer of MediaLB asynchronous data Characteristic Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 32 Bytes Packet Delay 2000 us COM DEN mitb 12660 4096fs 1q setup txt Manual setup of test via E mitb 12660 4096fs a 14 start txt GUI possible ediaLB Interface Clock Transferred Physical Channel PUE Mode Speed Data Type Channel Address Mesue PCO 0x01FE PC1 0x0006 Async Rx Device 6 Pin 4096xFs Async PC2 0x0008 Async Tx PC116 0x0000 DUT DUT MediaLB PUT MOST RS232 Port Target Interface Clock
129. RS232 85232 Port MDUT MediaLB Interface Mode e Pin MOST MDUT MediaLB Clock Speed 2048 5 Load Config File Trigger on Error W MediaLB Initialize MITB MOUT MOST Target Address 0101 hex Configuration Debug Messages RS232 to Host PC Baudrate 115200 FPGA Configuration Done FPGA PowerPC PGA Pattern PGA Active LED 120 0 PHY2 Active LED uto 2 Parity None Stop 1 bit Flow Control None Power Supply 12 V 27234 On Off Switch ed PHY2 Phy Board Coni 5 V Power LED PHY2 3 3 V Power LED PHY2 MOST Lock LED PHY2 MediaLB Lock LED LCD Display 4 16 Characters Trigger Connector Configuration and Debug Messages Clear Log Configuration and Debug Message Log Figure 6 2 Configuration Tab 6 2 1 1 Configuration Tab Parameters Indicators buttons and parameters of the configuration tab are described in the table below Description Red RS232 connection to MITB not available Yellow RS232 connection to MITB in progress Green RS232 connection to MITB established Red MOST Unlock Network connection between MITB and MDUT not available Yellow MOST Network configuration in progress Green MOST Lock Network connection between MITB and MDUT established MediaLB Red MediaLB Unlock PGA not locked to MediaLB Yellow MediaLB configuration in progress Green MediaLB Lock PGA locked to MediaLB Table 6 1 Configura
130. T must stop an ongoing packet reception Already received data quadlets are considered to be invalid and should be rejected The user needs to verify manually that the MDUT is properly terminating the packet reception Additionally it may be verified if MDUT internally a status indicating the detection of the AsyncBreak command is signalled properly The MITB does not provide an indication if the MDUT is handling the AsyncBreak as expected To verify the MDUT behavior and capture the generated AsyncBreak command generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the 0581110 is generating AsyncBreak commands randomly it cannot be guaranteed that the AsyncBreak command always happen at times when the 0581110 is transmitting async packets that means it is not guaranteed that the MDUT is receiving a packet when the AsyncBreak command is transmitted by the 0581110 Since the MDUT may not receive a packet when the AsyncBreak is present on the MediaLB bus the AsyncBreak command may not be detected by the MDUT In that case the AsyncBreak commands have no effect on the behavior of the MDUT To still be able to test the proper handling of the AsyncBreak command by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb t23311 3pin 1024fs c 4g is expected to indicate TEST PASS This is the case because the pa
131. TB will not detect any errors Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 133 MediaLB Interface Test Bench e smnsc V2 2 X 2048xFs test with ReceiverBreak responses generated by Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 4 quadlet per frame Test Fixed Packet Length 500 Bytes Characteristic Packet Delay 1500 us MITB generates 32 ReceiverBreak responses on the Async Rx Channel ChannelAddress 0x0008 of the MDUT 0581110 ReceiverBreak responses generated with a delay of 5 ms between consecutive ReceiverBreaks mitb 12644 2048fs 49 setup txt Manual setup of test via ee mitb_t2644_6pin_2048fs_a_4q_cfg_start txt GUI possible ediaL atio Interface Transferred Physical Channel Port Mode Mode Clock Speed Data Type Channel Address Allocated Transfer PCO 0x01FE PC1 0x0006 Async Rx 2 0x0006 Rx PC3 0x0006 Rx PC4 0x0006 Async Rx Device 6 Pin 2048xFs 5 0x0008 Async Tx PC6 0x0008 Async Tx PC7 0x0008 Async Tx PC8 0x0008 Async Tx PC57 0x0000 GUI Configuration Configuration Tab DUT Medial B DUT DUT MOST RS232 Port interface MediaLB Target Clock Speed Address 6 2048 0101h configurable ono D Tx
132. UT system re transmission mechanisms If the OS81110 generates a HeceiverProtocolError response packet reception is terminated and the broken packet will be lost In case the MDUT does not re transmit the broken packet the MITB will indicate a missing packet and a TEST FAILED If the broken packet is re transmitted by the MDUT after receiving the HeceiverProtocolError response the MITB will not detect any errors Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 135 MediaLB Interface Test Bench e smsc V2 2 X 2048xFs test with ReceiverProtocolError responses generated by Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Test Fixed Packet Length 14 Bytes Packet Delay 2000 us MITB generates 32 ReceiverProtocolError responses on the Async Rx Channel ChannelAddress 0x0008 of the DUT 0581110 ReceiverProtocolError responses generated with a delay of 100 ms between consecutive ReceiverProtocolError ME mitb 12645 2048fs 14 setup txt Manual setup of test via ES mitb 12645 2048fs a 14 start txt GUI possible atio Interface Clock Transferred Physical Channel Par Mete Mode Speed Data Type Channel Address 0x01FE PC1
133. User Manual Copyright 2011 SMSC Page 100 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X 8 2 17 mitb_t1651_6pin_3072fs_c_1q 3072xFs test with min max msg length max throughput Concurrent Rx and Tx transfer of MediaLB control data smsc Description Blockwidth 2 x 1 quadlet per frame Variable Message Length Throughput 475 msgs s E e mitb_t1651_6pin_3072fs_c_1q_cfg_setup txt Manual setup of test via E mitb t1651 307215 1q start txt GUI possible Interface Clock Transferred Physical Channel PON Mede Mode Speed Data Type Channel Address sse BT TE e PCO 0x01FE PC1 0x0004 Control Tx PC2 0x0002 Control Rx Device 6 Pin 3072xFs Control PC57 0x003E Unused PC86 0x0000 GUI Configuration Configuration Tab DUT DUT Interface Clock Ad dies Mode Speed pee 6 Pin 3072xFs 010th configurable O oi D D Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum t Repetiti Message Length Length Length noremens bytes msgs Length bytes bytes bytes Enable 6 45 1 1 Continuous Throughput Message Pattern Test msgs msgs s Counter Type z Byte Disable 5000 475 Enable Table 8 20 mitb 1651 3072fs 14 Copyright 2011 SMSC Document Version V2 2
134. able 10 000 Enable Counter Table 8 105 mitb_t5643_6pin_2048fs_casi Part 2 User Manual Copyright 2011 SMSC Page 194 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test V2 2 X Bench smsc 8 7 Miscellaneous Tests The following table provides an overview of available miscellaneous tests Test Name MediaLB 3 pin Tests mitb_t9330_3pin_1024fs_m_syscmd mitb_t9640_6pin_2048fs_m_syscmd Test Characteristics 1024xFs test with generation of system commands MediaLB Port open without any Channel Addresses No data transfer MOSTLock MOSTUnLock and MLBReset commands generated one after the other with a 2 second gap in between MediaLB 6 Tests 2048xFs test with generation of system commands MediaLB Port open without any Channel Addresses No data transfer MOSTLock MOSTUnLock and MLBReset commands generated one after the other with a 2 second gap in between Table 8 106 Miscellaneous Test Overview Copyright 2011 SMSC Document Version V2 2 X Date 2011 12 0902 User Manual Page 195 MediaLB Interface Test Bench e smnsc V2 2 X 8 7 1 mitb t9330 3pin 1024fs m syscmd 1024xFs test with generation of system commands MediaLB Port open without any Channel Addresses Description No data transfer MOSTLock MOSTUnLock and MLBReset commands generated one after the other with a 2 second gap in between
135. annel Address Alocarea tensia PCO 0x01FE PC1 0x0000 Device 6 Pin 2048xFs none PC2 0x0000 PC63 0x0000 DUT DUT MedialB MOST Interface Clock Ad Speed 6 Pin 2048xFs 0101h System Command Test Tab Delay MOSTLock No System System MOSTUnLock Commands MOSTLock 5 100 MOSTUnLock 10 10 MLBReset 1916 200 Table 8 108 mitb_t9640_6pin_2048fs_m_syscmd Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 197 MediaLB Interface Test Bench e smsc V2 2 X 9 Summary of Provided Files A description and the location of the files required to use the MITB and to verify a MediaLB device implementation can be found in the following sections 9 1 Graphical User Interface Executable The MITB GUI can be found on the provided installation CD in the following folder e SoftwareMITB GUhVO2 XX This folder incorporates the following installation file e MITB GUI 02 02 00 Installer exe To install the GUI double click on the file and follow the instructions When the GUI is executed the file MITB GUI Parameters ini is generated Parameters entered on the GUI are stored in this file when the GUI is closed and re loaded when the GUI is started again 9 2 PCFlasher Executable The PCFlasher application used to flash FPGA images and Pattern Generation amp Analyzer firmware to the MITB platform can be
136. at edt EHE OUR EINER 65 7 2 Asynchronous Packet 67 7 2 1 MOST Data Packets MDPS 67 7 2 2 MOST Ethernet Packets MEPSs sess nnns 69 7 3 Synchronous Pattern 71 7 4 Isochronous Packet 72 8 TEST DEFINITION E 73 81 Test Name Convention 73 9 2 Gohttol Tests ete ep erede Ld ug ao 74 8 2 1 11310 256fs 14 77 8 2 2 t1320 512fs 1 78 8 2 3 11330 Spin 1024fs 79 8 2 4 mith 11331 1024fs C 80 8 2 5 mitb 11332 10246 nri e e dert 81 8 2 6 t1333 1024fs 14 82 B 2 mitb t1335 102418 iot bro ee ege dre 83 58 2 8 11396 1024160 1Q oor 85 82 9 mitb it1337 Spin TO24TS 96 gt 87 8 2 10 1338 102480 14 iret a 89 8 2 11 11640 20488360 14 91 8 2 12 11641 204815 6 14 ERR es 92 8 2 19 11642 20481896 14 94 8
137. ata Test Tab Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum Packet Length Length Length dion ipd Length bytes bytes bytes Disable 32 Continuous Test Packet Packet Pattern Test 5 us yte Enable 5000 2000 Enable Counter Table 8 50 mitb_t2650_6pin_3072fs_a_1q Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 139 MediaLB Interface Test Bench e smnsc V2 2 X 8 3 23 12651 3072fs 274 2048xFs test with 2 x 27q blockwidth Test Concurrent Rx and Tx transfer of MediaLB asynchronous data Characteristic Blockwidth 2 x 27 quadlet per frame Variable Packet Length Packet Delay 6000 us COM DEN mitb 12651 307215 274 setup txt Manual setup of test via E mitb 12651 6pin 307215 27q start txt GUI possible ediaLb O Interface Clock Transferred Physical Channel PUE Mode Speed Data Type Channel Address eMe PCO 0x01FE PC1 0x0006 Async Rx PC27 0x0006 Rx Device 6 Pin 3072xFs Async PC28 0x0008 Async Tx PC54 0x0008 Async Tx PC86 0x0000 DUT DUT DUT MOST RS232 Port MediaLB Media
138. ata Types Channel Address 0x01FE PC1 0x000A Sync Rx 2 0 000 Sync Tx PC3 0x000A Sync Rx 4 0x000A Sync Rx PC5 0x000C Sync Tx PC6 0x000C Sync Tx PC7 0x000A Sync Rx Device 3 Pin 1024xFs Sync PC8 0x000A Sync Rx PC9 0x000A Sync Rx PC10 0x000C Sync Tx PC11 0x000C Sync Tx PC12 0x000C Sync Tx PC13 0x000A Sync Rx PC14 0x000C Sync Tx PC31 0x0000 DUT ou most RS232 Port MediaLB Clock Target Pin Mode 5 Address peed User configurable 3 Pin 1024xFs 0101h ono Vata D Tx Rx Blockwidth Channel Channel quadlets EM Address Address frame yp Byte 0x000A 0x000C 7 Enable Counter Table 8 60 mitb 13333 1024fs s 74 Copyright 2011 SMSC User Manual Page 149 MediaLB Interface Test Bench e smnsc V2 2 X 8 4 7 mitb t3334 3pin 1024fs s 74 1024xFs test with alternating Tx Rx ChannelAddresses Description Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 7 quadlet per frame mitb_t3334_3pin_1024fs_s_7q_cfg_setup txt Manual setup of test via Configuration Files mitb_t3334_3pin_1024fs_s_7q_cfg_start txt GUI possible D ediaL B Interface Clock Transferred Physical Channel Benoe Mode Speed Data Types Channel Address 0x01FE PC1 0x000C Sync Tx 2 0 000 Sync Rx PC3 0x000C Sync Tx PC4 0x000C Sync Tx PC5 0 000 Sync
139. b_t4337_3pin_1024fs_i_15q User Manual Copyright 2011 SMSC Page 168 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cSnmnsc V2 2 X 8 5 9 mitb t4640 6pin 2048fs i 1q Basic 2048xFs test Description Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 1 quadlet per frame 14640 6pin 2048fs i 19 setup txt Manual setup of test via Configuration Files mitb 14640 6pin 2048fs i 1 start txt GUI possible D ediaL B atio Interface Clock Transferred Physical Channel Pan Meze Mode Speed Data Types Channel Address 0x01FE PC1 0x000E Isoc Rx Device 6 Pin 2048xFs Isoc PC2 0x0010 Tx PC57 0x0000 DUT RS232 Port MediaLB Clock Target Pin Mode Speed Address User 6 Pin 2048xFs 0101h configurable isochronous Data Test Tab Tx Rx Blockwidth Packet Size Packet Channel Channel quadlets Flow Control bytes Throughput Address Address frame kbit s 0x000E 0x0010 1 Disable 188 1000 Continuous Pattern Test okts Counter Type Disable 5000 Enable Counter Table 8 80 mitb_t4640_6pin_2048fs_i_1q Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 169 MediaLB Interface Test Bench er smnsc V2 2 X 8 5 10 mitb 14641 6pin 204815 274 2048xFs test with maximum blockwidth Descriptio
140. bit field representing packet counter which is incremented for each transmitted packet Data Data bytes with pattern type Byte Counter or Random Number of data bytes can be adjusted in the GUI to 184 or 192 bytes Pattern Type Byte Counter Packet Index Packet 1 00 00 00 00 Packet 2 00 00 00 01 Packet 3 00 00 00 02 Pattern Type Random Packet Index Packet 1 00 00 00 00 Packet 2 00 00 00 O1 Packet 3 00 00 00 02 Table 7 4 Isochronous Packet Format Description User Manual Copyright 2011 SMSC Page 72 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 8 Test Definition The MITB includes a set of defined test cases The test cases are split in the following categories Control data tests Asynchronous data tests Synchronous data tests Isochronous data test Combined tests Miscellaneous tests For every category several test cases are defined A test case is used to verify the proper transfer of test patterns with a selected data type Combined test cases support the concurrent transfer of test patterns with multiple data types In addition to the data type every test is defined by a set of parameters Miscellaneous tests cover the generation of system commands To run a selected test the user s Device Under Test needs to be programmed to support loop back of the test specific test patterns For the test specific configuration of the MITB configuration files are
141. ble Varied Fixed Minimum Maximum Length Length Length ay En Length bytes bytes bytes Enable 6 1014 1 1 Continuous Pattern Test PRY Counter Type pkts us yte Disable 5000 12 000 Enable Counter Synchronous Data Test Tab Rx Blockwidth Channel Channel quadlets ae p Address Address frame yp Byte 0x000A 0x000C 1 Enable Counter ono Vata Rx Blockwidth Packet Size Packet Channel Channel quadlets Flow Control bytes Throughput Address Address frame kbit s 0 000 0 0010 1 Disable 196 1000 Continuous Test Packet Pattern Test Counter Type pkts Disable 10 000 Enable Caunter Table 8 96 mitb 15332 1024fs casi Part 2 Copyright 2011 SMSC Document Version V2 2 X Date 2011 12 0902 User Manual Page 185 MediaLB Interface Test Bench e SmS V2 2 X 8 6 6 mitb_t5333_3pin_1024fs_csi 1024xFs test data types Test Concurrent Rx and Tx transfer of MediaLB control synchronous and isochronous data Characteristic Blockwidth 2 x 4 quadlet per frame per loopback Control Fixed Packet Length 8 bytes 188 bytes Isoc Blocksize Message Throughput 50mgs s 1000 kbit s COM DEN mitb 15333 Spin 1024fs csi setup txt Manual setup
142. bug messages of MITB initialization e mitb t log cfg txt Includes configuration and debug messages mitb t log Includes PGA results and statistics of control data test e mitb log async txt Includes PGA results and statistics of asynchronous data test e mitb L log sync txt Includes PGA results and statistics of synchronous data test mitb t log isoc txt Includes PGA results and statistics of isochronous data test User Manual Copyright O 2011 SMSC Page 64 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench er cnmsc V2 2 X 7 Test Pattern Formats The MITB transfers MediaLB test pattern which are received and re transmitted by the MDUT Test patterns of the following data type are supported by the MITB Control messages Asynchronous packets Synchronous streaming data e packets The format of the pattern for the various supported data types are described the following sections 7 1 Control Message Format Control data is transferred in messages The MITB supports the generation of control messages with maximum length of 58 bytes The control message format is defined below 19 bytes 19 58 bytes 0 39 data bytes Port Message Length PML L Port Message Header PMH L Port Message Body PMB Figure 7 1 Control Message Format Copyright O 2011 SMSC User Manual Document Version V2
143. cation if the MDUT is handling the HeceiverProtocolError as expected To verify the MDUT behavior and capture the generated HeceiverProtocolError responses generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the 0581110 is generating HeceiverProtocolError responses randomly it cannot be guaranteed that the ReceiverProtocolError responses always happen at times when the MDUT is transmitting control messages By that means it is not guaranteed that MediaLB commands 0x30 0x32 and 0x34 transmitted by the MDUT are acknowledged by ReceiverProtocolError responses It might happen that the ReceiverProtocolError responses are present on the bus when NoData commands are transmitted by the MDUT In that case the ReceiverProtocolError responses have effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverProtocolError response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb t1643 6pin 2048fs c 1q indicates a TEST FAILED with missing messages in the MITB GUI for most cases This behavior is expected and entirely depends on the customer specific MDUT system re transmission mechanisms If the OS81110 generates a HeceiverProtocolError response message reception is terminated and the broken message will be lost In case the MDUT does not re transmit the broken me
144. cation if the MDUT is handling the ReceiverBreaks as expected To verify the MDUT behavior and capture the generated HeceiverBreak responses generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the 0581110 is generating ReceiverBreak responses randomly it cannot be guaranteed that the ReceiverBreak responses always happen at times when the MDUT is transmitting async packets By that means it is not guaranteed that MediaLB commands 0x20 0x22 and 0x24 transmitted by the MDUT are acknowledged by HeceiverBreak responses It might happen that the ReceiverBreak responses are present on the bus when NoData commands are transmitted by the MDUT In that case the ReceiverBreak responses have no effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverBreak response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case 12339 1024fs c 44 indicates a TEST FAILED with missing packets in the MITB GUI for most cases This behavior is expected and entirely depends on the customer specific DUT system re transmission mechanisms If the OS81110 generates a ReceiverBreak response packet reception is terminated and the broken packet will be lost In case the MDUT does not re transmit the broken packet the MITB will indicate a missing packet and TEST FAILED If the bro
145. ce 17 SMSC Status LEDS ish ctn rt er 10 13 15 Synchronous data 10 Synchronous pattern format 69 Synchronous tab 52 System commands 1 58 T Test configuration files Configuration setup 182 Configuration start 182 Test Pattern Formats Asynchronous packets 63 Control messages 63 Isochronous packets 63 Synchronous streaming 63 Test pattern parameters Asynchronous 18 Control data 18 Isochronous 18 Synchronous data 18 System 18 Test result reporting 19 Trigger connector 32 Trigger event 32 U User hardware 10 MediaL 12 MOST150 14
146. ch V2 2 X 8 2 19 mitb 11661 4096fs 14 4096xFs test with min max msg length max throughput Concurrent Rx and Tx transfer of MediaLB control data smsc Description Blockwidth 2 x 1 quadlet per frame Variable Message Length Throughput 475 msgs s Test Configuration mitb 11661 4096fs 19 setup txt Manual setup of test via Files mitb_t1661_6pin_4096fs_c_1q_cfg_start txt GUI possible ediaLb Interface Clock Transferred Physical Channel PON Mede Mode Speed Data Type Channel Address sse BT TE e PCO 0x01FE PC1 0x0004 Control Tx PC2 0x0002 Control Rx Device 6 Pin 4096xFs Control m PC57 0x003E PC116 0x0000 GUI Configuration Configuration Tab DUT DUT Interface Clock Ad dies Mode Speed User configurable 6 Pin 4096xFs 0101h O oi D D Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum t Repetiti Message Length Length Length noremens bytes msgs Length bytes bytes bytes Enable 6 45 1 1 Continuous Throughput Message Pattern Test msgs msgs s Counter Type z Byte Disable 5000 475 Enable Table 8 22 11661 4096fs 14 Copyright 2011 SMSC Document Version V2 2 X Date 2011 12 0902 User Manual Page 103 MediaLB Interface Test Bench
147. chronous 40 10 25 System commands tab 42 MITB 42 MITB connectors H Configuration debug 28 Phy Board 28 Hardware setup 10 Trigger connector ucc 28 lade 10 OS81110 test firmware 11 MITB Platform 10 MOST150 2 0 Fiber Optic Transceiver 11 MOST150 14 terre tn 11 MOST150 Device Setup 11 14 23 INIC Explorer Interface 21 27 LCD display NR 15 Intended USC te det exe s 9 Optical MOST150 interface 14 Isochronous data 10 Phy Board Variant 1 15 Isochronous packet format 70 RS232 Interface iei tiec 14 Isochronous tab TERR AE E REUS 55 Status LEDS 15 User hardware requirements 15 User Manual Copyright O 2011 SMSC Page 208 Document Ver
148. cket Delay 2000 us ee mitb 12333 1024fs 15q setup txt Manual setup of test via Em mitb 12333 1024fs a 154 start txt GUI possible GUI Configuration Configuration Tab DUT DUT RS232 Port MediaLB MediaLB Interface Clock Ad Speed 3 Pin 1024xFs 0101h ono Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0002 0x0004 15 Disable Fixed Minimum Maximum 2 Length Length Length noremens Repetitions Length bytes bytes bytes Enable 7 1014 1 1 Test Packet Duration Delay Packet Pattern est okts us Counter Type Disable 5000 2000 Enable Random Table 8 34 mitb_t2333_3pin_1024fs_a_15q Part 2 Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 115 MediaLB Interface Test Bench e SmS V2 2 X 8 3 8 mitb_t2334_3pin_1024fs_a_15q 1024xFs test with alternating physical positions for Rx and Tx channels Test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 15 quadlet per frame Variable Packet Length Packet Delay 2000 us C d en mitb 12334 1024fs a 15q cfg setup txt Manual setup of test via Fil
149. ckets terminated by an AsyncBreak command are re transmitted entirely by the OS81110 User Manual Copyright O 2011 SMSC Page 126 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e lt 5 7 lt V2 2 X GUI Configuration Configuration Tab DUT 1024xFs test with AsyncBreak commands generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 4 quadlet per frame Test Fixed Packet Length 500 Bytes Characteristic Packet Delay 2000 us MITB transmits 32 AsyncBreak commands on the Async Tx Channel ChannelAddress 0x0006 of the MDUT 0581110 AsyncBreak commands generated with a delay of 4 ms between consecutive AsyncBreaks M mitb 123311 1024fs a 4q setup txt Manual setup of test via SE mitb 123311 1024fs a 4q start txt GUI possible Interface Transferred Physical Channel Port Mode Modo Clock Speed Data Type Channel Address Allocated Transfer PCO 0x01FE PC1 0x0006 Async Rx PC2 0x0006 Async Rx 0 0006 4 0 0006 Device 3 Pin 1024xFs 5 0x0008 Async Tx PC6 0x0008 Async Tx PC7 0x0008 Async Tx PC8 0x0008 Async Tx PC31 0x0000 MedialB DUT DUT MOST RS232 Port a nee MediaLB Target Clock Speed Address Mode User 3 Pi
150. cribed in the following table Description DataType IsocPacket PGA configured to transfer isochronous packets MediaLB Port used to transfer isochronous packets ReportType Once Result report is generated once Forever Result report is generated successive TimeWindow 1s If test is started manually the period used to generate the result report is 1s XS If test is started by loading a configuration file the period used to generate the result report is defined in the loaded file LockState Pattern Unlock Pattern Analyzer receives invalid packets Pattern Search Pattern Analyzer received a valid packet and waits to receive the next packet in the correctsequence Pattern Locked Pattern Analyzer receives valid packets ErrorType No Error No error detected Corrupted Msg Packet incorporates error in payload Missed Msg Error in received packet sequence detected Table 6 12 Isochronous Results Log A successful isochronous data test indicates e No Locks 11 Errors The test result is indicated on the test status field next to the Start Stop Button as soon as a test is stopped Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 59 MediaLB Interface Test Bench e smsc V2 2 X 6 2 5 3 Isochronous Statistics Log The PGA s Isochronous Statistics Log displays information about transmitted received and missed packets The values displayed in
151. ction to host PC Phy Board Variant 1 o Connected to MITB Platform o Incorporates an OS81110 MOST150 transceiver o Connected via MediaLB 6 Pin interface operated at 2048xFs to FPGA o Serves as gateway between the MediaLB 6 Pin port of the FPGA and the MOST150 network e LCD Display o Provides information on the PGA version running on the MITB Platform e Status LEDs for o MOST Lock detection o MediaLB Lock detection o Power indication The requirements for the user hardware realizing a MOST150 device are described in section 2 5 2 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 15 MediaLB Interface Test Bench e smsc V2 2 X 2 2 Features 2 2 1 General Features Hardware setup to verify link layer implementation of MediaLB device Test pattern generation and verification of the following data types o Control messages o Asynchronous packets o Synchronous streaming data Isochronous packets o Combination of the above listed data types Generation of the following MediaLB commands o NoData o SyncData o AsyncStart AsyncContinue AsyncEnd AsyncBreak o ControlStart ControlContinue ControlEnd ControlBreak IsoNoData Iso4Bytes IsoSync4Bytes o MOSTLock MOSTUnlock MLBReset e Generation of the following MediaLB RxStatus responses o ReceiverReady o ReceiverBusy o HeceiverBreak o HeceiverProtocolError Supported Setups o MediaLB
152. ctor has been enabled PHY2 MOST Lock LED This LED illuminates when the OS81110 on the Board which is mounted to the MITB platform detects MOST Lock PHY2 MediaLB Lock LED This LED illuminates when the OS81110 on the Phy Board which is mounted on the MITB platform has opened the MediaLB 6 Pin port and the FPGA is locked to the FRAMESYNC signal transmitted by the OS81110 User Manual Copyright O 2011 SMSC Page 26 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 3 2 Physical Interface Board OS81110 Phy Board The Phy Board is an add on board which can be plugged via a Phy Board connector to a main board It incorporates an OS81110 MOST150 INIC and a Fiber Optic Transceiver FOT Connected to the MITB Platform and the user hardware in case of the MediaLB Device Setup it is realizing the interface to a MOST150 network The delivery of the MITB includes the following Phy Boards 1x Physical Interface Board 0581110 Variant 3 o Optimized for MediaLB 3 Pin 47 pull down resistors for MediaLB 3 pin signals are assembled 2 x Physical Interface Board 0581110 Variant 1 o Optimized for MediaLB 6 Pin o 100 Q termination resistors for differential MediaLB 6 pin signal are assembled o Pull down and pull up resistors required for differential voltage offset on the MediaLB 6 Pin interface are not assembled by default They need to be available on the ma
153. current Rx and Tx transfer of MediaLB control asynchronous synchronous data Blockwidth 2 x 1 quadlet per frame per loopback Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s mitb 15331 Spin 102415 casi 1024xFs test 4 data types Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data Blockwidth 2 x 1 quadlet per frame per loopback Fixed packet msg length control 8 bytes asynchronous 14 bytes isochronous 188 bytes Packet Delay 12 000 us Message Throughput 50mgs s 1000 kbit s mitb 15332 Spin 1024fs casi 1024xFs test all data types varied transfer parameter Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data Blockwidth 2 x 1 quadlet per frame per loopback Varied msg packet length control async packet size Isochronous 196 bytes Packet delay 12 000 us message throughput 50mgs s packet throughput 1000 kbit s mitb 15333 Spin 102415 csi 1024xFs test 3 data types Concurrent Rx and Tx transfer of MediaLB control synchronous and isochronous data Blockwidth 2 x 4 quadlet per frame per loopback Control Fixed Packet Length 8 bytes 188 bytes Isoc Blocksize Message Throughput 50mgs s 1000 kbit s Table 8 85 Combined Test Overview Part 1 User Manual Copyright O 2011 SMSC Page 174 Document Version V2
154. cuted on the host PC to enable flashing The PCFlasher is available on the Installation CD of the MITB package To initiate a flash process the user buttons described in section 3 1 need to be pressed The following figure shows the connection of the MITB platform and a host PC MITB Platform User Hardware MediaLB Device FPGA E 3 6 Pin PowerPC 5 4 Pattern MediaLB Device P MediaLB lt 85 Generator amp Interface Macro gt 0881110 gt PHY MOST150 PHY gt 0581110 8 gt Analyzer MDIM 5 2 Phy Board Variant 1 Phy Board Variant 1 3 0 RJ 45 Connector Ja PCHasher 5 Ethernet Crossover Cable Gearlog Mode Device IF Address 0 D Host Fach Fie on MITB ISP MLA05 9 Upload Rash INIC 1 Flash INIC 2 Upload Upload Progress Commands G DORRAM Usage Rest FPGA Fash Usage Delete Fish Fle PCFlasher Figure 5 1 Ethernet Connection MITB Platform and Host PC User Manual Copyright 2011 SMSC Page 36 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e smscC V2 2 X 5 1 Setup IP Address on Host PC The MITB platform is configured fo
155. e Figure 6 2 Step 1 2 Define RS232 Port Step 1 3 Select MDUT MediaLB Interface Mode 3 Pin or 6 Pin Step 1 4 Select MDUT MediaLB Clock Speed 256xFs 512xFs Step 1 5 Select MDUT MOST Target Address typically 0101hex Step 1 6 Enable or disable Trigger on Error events Step 1 7 Enable or disable visibility of Configuration Debug Messages Step 1 8 Click Initialize MITB button to configure MITB with the provided parameters Step 2 Configure Test Pattern Step 2 1 Select tab for required data type see Figure 6 6 Step 2 2 Select and enter data type specific parameters Step 3 Start Loop Back Application on Device Under Test To successfully run a test make sure that the MDUT is configured for the same parameters as adjusted on the GUI and the loop back function has been enabled Step 4 Execute Test Step 4 1 Click Start Test button to activate pattern generation Step 4 2 Wait until number of expected test patterns are generated Step 4 3 Click Stop Test button to hold pattern generation Step 5 Verify Test Results Step 5 1 Check error log of result log and or test status field Step 6 Re run Test If MediaLB specific parameters such as interface mode or clock speed need to be modified go to Step 1 If modifications of data pattern specific parameters or no modifications at all are required go to Step 2 Note Manual configuration does not support concurrent pattern generation of different data ty
156. e MDUT are acknowledged by responses It might happen that the ReceiverBusy responses are present on the bus when NoData commands are transmitted by the MDUT In that case the ReceiverBusy responses have no effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverBusy response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb t1641 6pin 2048fs c 1q indicates a TEST FAILED with missing messages in the MITB GUI for most cases This behavior is expected and is related to the nature of the MOST network and the OS81110 During the HeceiverBusy periods the OS81110 will not receive data from the MDUT via MediaLB Since loop back application of the MDUT cannot transmit any data it also will not be able to receive new messages from the OS81110 via MediaLB and the MITB respectively This again results in the OS81110 holding of messages received via MOST from the MITB platform Depending on how long the HeceiverBusy period lasts the OS81110 buffers will run full and messages transmitted from MITB platform to OS81110 via MOST will get lost on the MOST network There is no such thing as a ReceiverBusy response on MOST Because of this no feedback from the OS81110 connected to the DUT is passed to the OS81110 on the MITB platform indicating the buffer full condition of the DUT OS81110 and the MITB keeps tra
157. e ReceiverBreak response the MITB will not detect any errors User Manual Copyright O 2011 SMSC Page 94 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X smsc 2048xFs test with ReceiverBreak responses generated by Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes 11642 2048fs c 14 setup txt Throughput 500 msgs s generates 48 ReceiverBreak responses on the Control Rx Channel ChannelAddress 0x0002 of the DUT 0581110 ReceiverBreak responses generated with a delay of 200 ms between consecutive ReceiverBreaks Test configurable GS DENIS Manual setup of test via Se mitb 11642 204815 14 start txt GUI possible ediaLb atio Transferred Physical Channel Port Mode Interface Mode Clock Speed Data Type Address Allocated Transfer PCO 0x01FE PC1 0x0004 Control Tx Device 6 Pin 2048xFs Control 2 0x0002 Control Rx 57 0 00 Unused DUT MediaLB DUT MediaLB DUT MOST Reze Por Interface Mode Clock Speed Target Address 6 2048xFs 0101h Control Data Test Tab Document Version V2 2 X Date 2011 12 0902 Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum
158. eak command are re transmitted entirely by the OS81110 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 137 MediaLB Interface Test Bench e cnmnsc V2 2 X 2048xFs test with AsyncBreak commands generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 4 quadlet per frame Test Fixed Packet Length 500 Bytes Characteristic Packet Delay 2000 us MITB transmits 32 AsyncBreak commands on the Async Tx Channel ChannelAddress 0x0006 of the MDUT OS81110 AsyncBreak commands generated with a delay of 4 ms between consecutive AsyncBreaks M mitb 12646 204815 4q setup txt Manual setup of test via SE mitb 12646 2048fs a 44 start txt GUI possible ediaLb O atio Interface Transferred Physical Channel Port Mode Modo Clock Speed Data Type Channel Address Allocated Transfer PCO 0x01FE PC1 0x0006 Async Rx PC2 0x0006 Async Rx 0 0006 4 0 0006 Device 6 Pin 2048xFs 5 0x0008 Async Tx PC6 0x0008 Async Tx PC7 0x0008 Async Tx PC8 0x0008 Async Tx PC57 0x0000 GUI Configuration Configuration Tab DUT Medial DUT DUT MOST RS232 Port nee MediaLB Target Clock Speed Address Mode User 6 Pin 2048xFs 0101h configurable ono Vata
159. ect MediaLB Monitor for MediaLB interface analysis User Manual Copyright 2011 SMSC Page 12 Document Version 2 2 Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X Additionally the MITB provides the following main components XILINX Virtex4 FX60 FPGA including o PowerPC used to run the PGA o MediaLB Device Interface Macro featuring a differential MediaLB 6 Pin o RS232 interface for connection to host PC 17 Phy Board Variant 1 o Connected to MITB Platform Incorporates 0581110 MOST150 transceiver o Connected via MediaLB 6 Pin interface operated at 2048xFs to FPGA o Serves as gateway between the MediaLB 6 Pin port of the FPGA on the MITB Platform and the MOST150 network 2 Phy Board Variant 3 o Connected to user hardware o Optimized for a single ended MediaLB 3 Pin interface o Used for testing of MediaLB 3 Pin port of MDUT o Connected via MediaLB 3 6 Pin high speed debug header to MDUT o Serves as gateway between the MOST150 network and the MDUT o Optically connected to 1st Phy Board 3 Phy Board Variant 1 o Connected to user hardware o Optimized for a differential MediaLB 6 Pin interface o Used for testing of MediaLB 6 Pin port of MDUT o Connected via MediaLB 3 6 Pin high speed debug header to MDUT o Serves as gateway between the MOST150 network and the MDUT o Optically connected to 1st Phy Board LCD Display o Provides information on the PGA version r
160. ecutive ReceiverBusy response periods on the Control Rx Channel ChannelAddress 0x0002 of the OS81110 During each period the OS81110 generates ReceiverBusy responses in every frame on the Control Rx Channel for approximately 3 ms After a delay of 500 ms at which the OS81110 is able to receive data indicated by ReceiverReady responses the next ReceiverBusy period starts The ReceiverBusy responses indicate that the 0581110 connected to the MDUT is not able to receive data The ReceiverBusy responses need to be detected by the MDUT and transmitted data quadlets acknowledged by ReceiverBusy response must be repeatedly transmitted until a HeceiverHeady response is detected The user must verify this behaviour manually The MITB does not provide an indication if the ReceiverBusy is handled properly by the MDUT To verify the MDUT behavior and capture the generated HeceiverBusy responses generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the OS81110 is generating HeceiverBusy responses randomly it cannot be guaranteed that the ReceiverBusy responses always happen at times when the MDUT is transmitting control messages By that means it is not guaranteed that MediaLB commands 0x30 0x32 and 0x34 transmitted by the MDUT are acknowledged by responses It might happen that the ReceiverBusy responses are present on the bus when NoData commands are transmitted by the M
161. ed between the GUI and the INIC connected to the MDUT Additionally status information is provided about the state of the MITB initialization and the pattern generation The Configuration and Debug Messages Log can be cleared by clicking the Clear Log button located next to the log window Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 45 MediaLB Interface Test Bench e smsc V2 2 X 6 2 2 Control Tab The following figure shows the control tab of the GUI In this tab parameters can be entered which define the characteristics of the generated control test patterns A button is available to manually start and stop the pattern processing Log windows display the PGA results and statistics Dedicated test status fields indicate the test status Control PGA Statistics Status Field Control PGA Result Status Field Control Tab Parameters Control Start Stop Button Control Test Status Field 2 MITE 5419220 M TR MediaLB Interface Test Bench Pattern Generator and Analyzer GUI V2 2 0 Configuration Control Asynchronous Synchronous Control Data Test Tx ChannelAddress 0002 hex Rx ChannelAddress 10004 hex RxResponse None Number 5 dec Delay lioo ms Pattern Generator and Analyzer Results TxCommand None Number 5 Delay 100 ms Varied Message Length Fixed Length 32 bytes Incr nt Pattern Generator and Analyzer Statistics
162. ed to the MediaLB interface of the MDUT This is highly recommended and required for observing the data transfer on the MediaLB interface between the MDUT and the connected INIC and to debug error cases To be able to connect the MediaLB Analyzer a MediaLB 3 6 Pin high speed debug header is required Using the MOST150 Device Setup this connector needs to be implemented on the user hardware If a Phy Board is used as required for the MediaLB Device Setup the MediaLB debug connector is available on the Phy Board Hint INIC Explorer 1 as well as MediaLB Analyzer 2 are not part of the MITB delivery and need to be purchased separately Hereafter abbr as Phy Board Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 11 MediaLB Interface Test Bench e smsc V2 2 X 2 1 1 MediaLB Device Setup The following figure outlines the block diagram of the MediaLB Device Setup MediaLB Analyzer Host PC Host A RS232 Explorer MITB GUI Interface MediaLB Configuration Box Monitor Debug RS232 Header No 14ePin Ribbon Cable Platform MediaLB Device Dedicated MITB 0581110 MediaLB 6 4x16 RS232 XIL
163. eds to be linked to a free RS232 port on the host PC 4 2 Connect MITB Platform to User Hardware The MITB platform and the user hardware have to be connected via an optical MOST150 network using the two optical fiber cables with Yazaki 2 0 connectors The two boards have to be connected in a way that the fibers form an optical loop 4 3 Connect INIC Explorer Interface Box The INIC Explorer Interface Box needs to be connected to the configuration debug header on the Boards or the user hardware via a 14 pin ribbon cable delivered with the INIC Explorer Interface Box In addition the box has to be linked via an RS232 cable to a free port of the host PC For detailed information on the INIC Explorer refer to the INIC Explorer User Manual 1 4 4 Connect MediaLB Analyzer For connecting the MediaLB Analyzer refer to the MediaLB Analyzer User Manual 2 Copyright O 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 35 MediaLB Interface Test Bench e smsc V2 2 X 5 Flashing the MITB Platform FPGA images as well as Pattern Generator amp Analyzer firmware can be flashed to the MITB platform To perform the flashing the MITB platform needs to be connected to a host PC or laptop via Ethernet An Ethernet crossover cable is part of the MITB delivery and used to link a host PC to the RJ 45 Ethernet connector of the MITB platform see section 3 1 for details A PCFlasher application needs to be exe
164. elay 1000 us Continuous Test Clear Logs Configuration and Debug Messages Clear Log PGA s Asynchronous Results Log PGA s Asynchronous Statistics Log Figure 6 4 Asynchronous Tab User Manual Copyright 2011 SMSC Page 50 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X smsc 6 2 3 1 Asynchronous Tab Parameters Parameters and buttons of the asynchronous tab are described in the table below Tx ChannelAddress Rx ChannelAddress Blockwidth RxResponse RxResponse Number RxResponse Delay TxCommand TxCommand Number TxComand Delay MEP MEP Destination Address MEP Source Address Varied Packet Length Fixed Length Minimum Maximum Increments Repetitions Pattern Type Packet Delay Continuous Test Test Duration Clear Logs Start Stop Test Test Status Field Description transmitted by the OS81110 connected to the MDUT received by the OS81110 connected to the MDUT Number of quadlets allocated per MediaLB frame for the transmission and reception of the asynchronous test pattern Depending on the MediaLB speed the bandwidth ranges from 1 to 27 quadlets per frame Defines special RxResponse to be generated by the MITB The following RxResponses are defined None RxBusy RxBreak and RxProtErr Indicates number of special RxResponses to be generated Indicates approximate delay between consecutive generated RxRespon
165. erated by MITB Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes 11644 2048fs 14 setup txt Throughput 500 msgs s MITB transmits 240 ControlBreak commands on the Control Tx Channel ChannelAddress 0x0004 of the DUT 0S81110 ControlBreak commands generated with a delay of 20 ms between consecutive ControlBreaks Test configurable Control Data Test Tab Manual setup of test via Se mitb 11644 204815 1q start txt GUI possible ediaLb atio Transferred Physical Channel Port Mode Interface Mode Clock Speed Data Type Address Allocated Transfer PCO 0x01FE PC1 0x0004 Control Tx Device 6 Pin 2048xFs Control 2 0x0002 Control Rx 57 0 00 Unused DUT MediaLB DUT MediaLB DUT MOST Reze Por Interface Mode Clock Speed Target Address 6 2048xFs 0101h Document Version V2 2 X Date 2011 12 0902 Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum Length Length Length oss Qon Length bytes bytes bytes 9 Disable 45 Continuous Test Duration Throughput Message Delay Test msgs msgs s Nr TxCmd ms Disable 5000 500
166. es mitb 12334 1024fs a 154 start txt GUI possible DUT MediaLB Configuration hook Pec located Trans PCO 0x01FE PC1 0x0004 Async Tx PC2 0x0002 Async Rx PC3 0x0004 Async Tx PC4 0x0004 Async Tx PC5 0x0002 Async Rx PC6 0x0002 Async Rx PC7 0x0004 Async Tx PC8 0x0004 Async Tx 9 0 0004 10 0x0002 Async Rx PC11 0x0002 Async Rx PC12 0x0002 Rx PC13 0x0004 Async Tx PC14 0x0004 Async Tx PC15 0x0004 Async Tx Device 3 Pin 1024xFs Async PC16 0x0004 Async Tx PC17 0x0002 Async Rx PC18 0x0002 Async Rx PC19 0x0002 Async Rx PC20 0x0002 Async Rx 21 0 0004 22 0 0004 Async Tx PC23 0x0004 Async Tx PC24 0x0004 Async Tx PC25 0x0004 Async Tx PC26 0x0002 Async Rx PC27 0x0002 Async Rx PC28 0x0002 Async Rx PC29 0x0002 Async Rx PC30 0x0002 Async Rx PC31 0x0000 Table 8 35 mitb 12334 1024fs 154 Part 1 User Manual Copyright O 2011 SMSC Page 116 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 1024xFs test with alternating physical positions for Rx and Tx channels Test 2 2 MediaLB asynchronous data Blockwidth 2 x 15 quadlet per frame Chee M Variable Packet Length Packet Delay 2000 us ee mitb 12334 102415 159 setup txt Manual setup of test via Em mitb 12334 1024fs a 15
167. est Bench e smsc V2 2 X 5 2 Flash FPGA Image To flash an FPGA image to the MITB platform the following steps are required 1 Power up MITB platform Power up MITB platform while user button WEST is pressed Button needs to be pressed for several seconds until Flashloader application will be executed on the MITB platform The version of the Flashloader is indicated on the LCD display next to the user buttons 2 Run PCFlasher exe Start PCFlasher exe application on host PC the PCFlasher exe file is provided on the CD delivered with the MITB platform 3 Verify connection to MITB platform The IP address of MITB platforms is defined as 192 168 0 100 Enter IP address of MITB platform in the GUI of the PCFlasher application Click the Ping button Connection success is reported by the log window Ext ClearLog Device IP Address Flashing Host PC File a Biewee j Flash File on MITB ISP ML405 v Upload Flash Upload Flash Flash INIC 1 Flash INIC 2 Upload File Upload Progress Commands DDR RAM Memory Usage Reset FPGA SUCCESS BY DESIGN 1 Flash Memory Usage Delete Flash File Figure 5 3 Verify Connection to MITB Platform 4 Load FPGA image file to MITB platform Open the Browse dialog and select the FPGA image to be flashed e g SP89420 vhdl v02 02 13 01 bootloader v00 05 08 01 xsvf The FPGA image needs to be available in xsvf format The se
168. et reception Already received data quadlets are considered to be invalid and should be rejected The user needs to verify manually that the MDUT is properly terminating the packet reception Additionally it may be verified if MDUT internally a status indicating the detection of the AsyncBreak command is signalled properly The MITB does not provide an indication if the MDUT is handling the AsyncBreak as expected To verify the MDUT behavior and capture the generated AsyncBreak command generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the OS81110 is generating AsyncBreak commands randomly it cannot be guaranteed that the AsyncBreak command always happen at times when the OS81110 is transmitting async packets By that means it is not guaranteed that the MDUT is receiving a packet when the AsyncBreak command is transmitted by the OS81110 Since the MDUT may not receive a packet when the AsyncBreak is present on the MediaLB bus the AsyncBreak command may not be detected by the MDUT In that case the AsyncBreak commands have no effect on the behavior of the MDUT To still be able to test the proper handling of the AsyncBreak command by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb t23311 3pin 1024fs c 4g is expected to indicate a TEST PASS This is the case because the packets terminated by an AsyncBr
169. found on the provided installation CD in the following folder SoftwarelPCFlashenV01 XX This folder incorporates the following installation file e PCFlasher 01 01 01 Installer exe To install the PCFlasher double click on the file and follow the instructions 9 3 FPGA Image The following FPGA image is provided on the installation CD and can be flashed to the XILINX Virtex 4 FPGA on the MITB platform e FirmwareMITBWVO2 XX SP89420 02 02 13 01 bootloader 00 05 08 01 xsvf Hint The delivered MITB platform is by default flashed with the proper FPGA image The FPGA needs to be flashed only in case a version update is required User Manual Copyright O 2011 SMSC Page 198 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 9 4 Pattern Generator amp Analyzer Firmware The following Pattern Generator amp Analyzer firmware is provided on the installation CD and can be flashed to the MITB platform e Firmware MITB V02_XX_YY MITB_PGA_V02_02_00 01 srec The delivered MITB platform is by default flashed with the proper Pattern Generator amp Analyzer firmware The PGA needs to be flashed only in case a version update is required 9 5 OS81110 INIC Firmware The following OS81110 INIC firmware files are provided on the installation CD and can be flashed to the OS81110 devices part of the MITB e FirmwareMITBWO2 XX 0581110 01 02 03
170. gth DS puc Length bytes bytes bytes Disable 16 Continuous Test Duration Packet Delay Packet RxRes Nr Test pkts us Counter p ms P Enable 5000 2000 Enable Byte Counter ReceiverBusy 20 110 Table 8 46 mitb_t2643_6pin_2048fs_a_1q User Manual Copyright 2011 SMSC Page 132 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 8 3 19 mitb 12644 2048fs 44 The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is transmitting async data and the receiving device OS81110 connected to the MDUT is responding with ReceiverBreak responses After the data transfer is started the MITB will generate 32 ReceiverBreak responses on the Async Rx Channel ChannelAddress 0x0002 of the OS81110 ReceiverBreak responses are generated with a delay of 5 ms between consecutive HeceiverBreaks The MDUT transmitting async packets needs to detect the ReceiverBreak responses Following the detection of the ReceiverBreak the MDUT must stop packet transmission The user needs to verify manually that the MDUT is properly terminating the packet transmission Additionally it may be verified if MDUT internally a status indicating the detection of the ReceiverBreak response is signalled The MITB does not provide an indication if the MDUT is handling the ReceiverBreaks as expected To verify the MDUT
171. gured to receive and re transmit the patterns generated by the MITB on the defined MediaLB ChannelAddresses Additionally the MDUT must be configured for the correct interface mode 3 Pin or 6 Pin clock speed 256xFs 512xFs and data type control asynchronous synchronous or isochronous data The following figure shows an example how the loop back functionality works The MDUT receives data from MediaLB on ChannelAddress 0 0002 and re transmits the received pattern on ChannelAddress 0x0004 MediaLB Controller 0581110 E g _ ChannelAddress Rx MediaLB 0x0004 3 6 Pin i E g ChannelAddress 0x0002 Figure 3 7 Loop Back User Manual Copyright 2011 SMSC Page 34 Document Version 2 2 Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 4 Set Up the Test Bench In sections 2 1 1 and 2 1 2 of this user manual the MediaLB Device Setup and the MOST150 Device Setup of the MITB are described It is up to the user to establish the mandatory connections displayed in Figure 2 1 MediaLB Device Setup and Figure 2 2 MOST150 Device Setup to realize the most suitable setup for MediaLB device testing 4 1 Connect MITB Platform to Host PC The MITB platform has to be connected to a host PC or laptop via an RS232 cable The RS232 cable is provided with the package of the MITB To establish the connection the lower RS232 port of the MITB platform see section 3 1 for details ne
172. icated on the test status field next to the Start Stop Button as soon as a test is stopped 6 2 3 3 Asynchronous Statistics Log The PGA s Asynchronous Statistics Log displays information about transmitted received and missed packets The values displayed in the statistic log are described in the following table Name Number of packets transmitted in TimeWindow MDP MEP Tx Total Total number of packets transmitted from start of test MDP MEP Rx Number of packets received in TimeWindow MDP MEP Rx Total Total number of packets received from start of test MDP MEP Missed Total number of missed packets MDP MEP Tx Total MDP MEP Rx Total Table 6 8 Asynchronous Statistics Log Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 53 MediaLB Interface Test Bench er smsc V2 2 X 6 2 4 Synchronous Tab The following figure shows the synchronous tab of the GUI In this tab parameters can be entered which define the characteristics of the generated synchronous test patterns A button is available to manually start and stop the pattern processing Log windows display the PGA results and statistics Dedicated test status fields indicate the test status Synchronous PGA Statistics Status Field Synchronous Tab Parameters Synchronous PGA Result Status Field Synchronous Test Status Field Synchronous Start Stop Button MITB GUIV2 2 0 m
173. in board A Phy Board Variant 1 is mounted on the MITB platform at delivery The remaining Phy Boards Variant 1 and Variant 3 may be used to realize a MediaLB Device Setup of the MITB as outlined in Figure 2 1 MediaLB Device Setup For testing the MediaLB 3 Pin or 6 Pin port of a MDUT different Phy Boards need to be connected to the user hardware e 3 Pin port testing requires Phy Board Variant 3 e MediaLB 6 Pin port testing requires Phy Board Variant 1 The layout of the Phy Board connector is described in section 3 6 2 For further information on the Physical Interface Board including reference schematics refer to the Physical Interface Board 0581110 2 0 Data Sheet 3 3 3 INIC Explorer Interface Box The INIC Explorer Interface Box represents the interface between an INIC MOST transceiver and a connected host PC In combination with the OSS Flasher Software 7 the INIC Explorer Interface Box may be used to flash the 0581110 on the MITB Platform or the user hardware The Interface Box has to be connected to the Customer Configuration Interface of the 0581110 via a 14 bit ribbon cable An RS232 connection is used to link the Interface Box to the host PC For detailed information about the INIC Explorer Interface Box refer to the INIC Explorer User Manual 1 Hint The Explorer Interface Box is not delivered with the MITB It has to be purchases separately 1 Copyright O 2011 SMSC User Manua
174. in9 No connect Pin10 No connect 11 12 13 14 15 16 17 18 19 20 21 22 Pin23 No connect Pin24 No connect Pin25 No connect Pin26 No connect Pin27 No connect Pin28 No connect Pin29 No connect Pin30 No connect Pin31 No connect Pin32 No connect Pin33 No connect Pin34 No connect Pin35 No connect Pin36 No connect EE EE Power Supply There is no need to use these signals Figure 3 5 Trigger Connector The shape of the generated trigger events are shown in the following figure V t Vhigh 3 3 V 0V Thigh 2 12 us Figure 3 6 Trigger Event Copyright O 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 33 MediaLB Interface Test Bench e SmS V2 2 X 3 7 MediaLB Device Under Test The MDUT represents a MediaLB device implemented by the user The functional capabilities of the MDUT depend on the user specific device implementation While some devices may support all kind of MediaLB parameters such as different clock speeds 256xFs 512xFs interface modes 3 Pin and 6 Pin or data transfer types control asynchronous synchronous and isochronous other devices
175. ion V2 2 X Date 2011 12 0902 User Manual Page 179 MediaLB Interface Test Bench e SmS V2 2 X 8 6 3 15330 3pin 102445 cas Basic 1024xFs test Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous data Characteristic Blockwidth 2 x 1 quadlet per frame per loopback Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s mitb 15330 1024fs cas setup txt Manual setup of test via E mitb 15330 1024fs cas start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Par Mede Mode Speed Data Types Channel Address Allocated PCO 0x01FE PC1 0x0004 Control Tx PC2 0x0002 Control Rx Control 0 0006 ontrol Device 3 Pin 1024xFs Sync PC4 0x0008 Async Tx PC5 0x000A Sync Rx PC6 0x000C Sync Tx PC31 0x003E DUT DUT MedialB NS Interface Clock Ad eee Mode Speed ate 3 Pin 1024xFs 0101h ol D Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum increment Repetition Message Length Length Length b he S tes B Length bytes bytes bytes 9 Disable 8 Continuous Throughput Message Pattern Test msgs msgs s Counter Type Disable 10000
176. is properly terminating the packet transmission Additionally it may be verified if MDUT internally a status indicating the detection of the HeceiverProtocolError response is signalled properly The MITB does not provide an indication if the MDUT is handling the ReceiverProtocolError as expected To verify the MDUT behavior and capture the generated HeceiverProtocolError responses generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the OS81110 is generating HeceiverProtocolError responses randomly it cannot be guaranteed that the ReceiverProtocolError responses always happen at times when the MDUT is transmitting async packets By that means it is not guaranteed that MediaLB commands 0x30 0x32 and 0x34 transmitted by the MDUT are acknowledged by HeceiverProtocolError responses It might happen that the ReceiverProtocolError responses are present on the bus when NoData commands are transmitted by the MDUT In that case the HeceiverProtocolError responses have no effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverProtoco Error response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb 12645 6pin 2048fs c 1q indicates a TEST FAILED with missing packets in the MITB GUI for most cases This behavior is expected and entirely depends on the customer specific MD
177. is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the 0581110 is generating HeceiverProtocolError responses randomly it cannot be guaranteed that the ReceiverProtocolError responses always happen at times when the MDUT is transmitting control messages By that means it is not guaranteed that MediaLB commands 0x30 0x32 and 0x34 transmitted by the MDUT are acknowledged by ReceiverProtocolError responses It might happen that the ReceiverProtocolError responses are present on the bus when NoData commands are transmitted by the MDUT In that case the ReceiverProtocolError responses have effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverProtocolError response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case 11337 1024fs 14 indicates a TEST FAILED with missing messages in the MITB GUI for most cases This behavior is expected and entirely depends on the customer specific MDUT system re transmission mechanisms If the OS81110 generates a HeceiverProtocolError response message reception is terminated and the broken message will be lost In case the MDUT does not re transmit the broken message the MITB will indicate a missing message and a TEST FAILED If the broken message is re transmitted by the MDUT after receiving the ReceiverProtocolError response the MITB
178. istics MediaLB 6 pin Tests mitb_t4640_6pin_2048fs_i_1q Basic 2048xFs test Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 1 quadlet per frame mitb_t4641_6pin_2048fs_i_27q 2048xFs test with maximum blockwidth Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 27 quadlet per frame 4q 2048xFs test with ChannelAddresses in the upper address range Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 4 quadlet per frame CA 0x007E amp CA 0x7C 1q Basic 3072xFs test Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 1 quadlet per frame mitb_t4651_6pin_3072fs_i_27q 3072xFs test with maximum blockwidth Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 27 quadlet per frame Packet size 196 bytes mitb_t4642_6pin_2048fs mitb_t4650_6pin_3072fs Table 8 71 Isochronous Test Overview Part 2 User Manual Copyright O 2011 SMSC Page 160 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cSnmnsc V2 2 X 8 5 1 mitb t4310 3pin 256fs i 1q Basic 256xFs test Description Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 1 quadlet per frame c m mitb 14310 256fs i 14 setup txt Manual setup of test via s 14310 256fs 14
179. ken packet is re transmitted by the MDUT after receiving the ReceiverBreak response the MITB will not detect any errors User Manual Copyright O 2011 SMSC Page 122 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 1024xFs test with ReceiverBreak responses generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 4 quadlet per frame Test Fixed Packet Length 500 Bytes Characteristic Packet Delay 1500 us MITB generates 32 ReceiverBreak responses on the Async Rx Channel ChannelAddress 0x0008 of the MDUT OS81110 ReceiverBreak responses generated with a delay of 5 ms between consecutive ReceiverBreaks C DAT mitb 12339 1024fs a 4q setup txt Manual setup of test via SES mitb 12339 1024fs a 44 start txt GUI possible atio Interface Transferred Physical Channel Port Mode Mode Clock Speed Data Type Channel Address Allocated Transfer PCO 0x01FE PC1 0x0006 Async Rx PC2 0x0006 Rx PC3 0x0006 Async Rx PC4 0x0006 Async Rx Device 3 Pin 1024xFs 5 0x0008 Tx PC6 0x0008 Async Tx PC7 0x0008 Async Tx PC8 0x0008 Async Tx 1 0 0000 GUI Configuration Configuration Tab DUT Medial DUT DUT MOST RS232 Port pene MediaLB Target
180. kets which may get lost User Manual Copyright O 2011 SMSC Page 120 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X SMST Document Version V2 2 X Date 2011 12 0902 1024xFs test with ReceiverBusy responses generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Test Fixed Packet Length 14 Bytes 2000 5 MITB generates series of 20 consecutive ReceiverBusy response periods on Async Rx Channel ChannelAddress 0x0008 of the MDUT 581110 During each period ReceiverBusy responses generated in every frame for approximately 2 ms After delay of 110 ms next ReceiverBusy period starts te mitb 12338 102415 14 setup txt Manual setup of test via Ee mitb 12338 1024fs a 1q start txt GUI possible ediaL B atio Interface Transferred Physical Channel Port Mode Mode Clock Speed Data Type Channel Address Allocated Transfer PCO 0x01FE PC1 0x0006 Rx Device 3 Pin 1024xFs Async PC2 0x0008 Tx PC31 0x0000 GUI Configuration Configuration Tab DUT DUT MOST RS232 Port mieie MediaLB Target Mode Clock Speed Address User 3 Pin 1024xFs 0101h configurable 5 ono Vata 2 D Rx Blockwidth MEP MEP Channel Channel quadlet
181. l Document Version V2 2 X Date 2011 12 0902 Page 27 MediaLB Interface Test Bench e smsc V2 2 X 3 4 MediaLB Analyzer The MediaLB Analyzer is a tool designed to observe and visualize MediaLB data in a comfortable Way It consists of the following hardware and software modules Hardware Modules e MediaLB Monitor USB converter box transferring MediaLB data received from Active Pods via USB 2 0 to a host PC Active Pods functioning as interface to the MediaLB port of the Device Under Test Software Module OptoLyzer Suite software which supports analysis and visualization of MediaLB data Hint The components of the MediaLB Analyzer need to be purchased separately to complete a MediaLB Analyzer setup Active Pods have to be purchased dependent on the MediaLB interface 3 Pin or 6 Pin to be analyzed and the used MediaLB debug header low speed or high speed A typical MITB setup comprises only MediaLB 3 6 Pin high speed debug headers Therefore it is recommended to purchase 3 Pin and or 6 Pin high speed Active Pods for usage on the MITB For further information on the MediaLB Analyzer refer to the MediaLB Analyzer User Manual 2 3 5 Host PC The host PC should be a standard Pentium class PC or laptop on which the GUI of the MITB and the OSS Flasher Software 7 need to be installed The minimum requirements for the host PC are outlined in section 2 4 The host PC has to be connected to the MITB Platform as well
182. l Packet Size Trin Address Address frame nce kbit s 0x003C 0x003E 7 Disable 188 1000 Continuous Pattern Test okts Counter Type Disable 5000 Enable Table 8 76 mitb 14332 1024fs 74 User Manual Page 165 Copyright 2011 SMSC Document Version V2 2 X Date 2011 12 0902 MediaLB Interface Test Bench e smsc V2 2 X 8 5 6 mitb t4333 3pin 1024fs 154 1024xFs test with maximum blockwidth Description Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 15 quadlet per frame P mitb 14333 1024fs i 15q setup txt Manual setup of test via Ie mitb t4333 Spin 1024fs i 15q cfg start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Mode Speed Data Types Channel Address PCO 0x01FE PC1 0 000 Isoc Rx PC15 0x000E Isoc Rx Device 3 Pin 1024xFs Isoc PC16 0x0010 Isoc Tx PC30 0x0010 Tx 1 0 0000 DUT DUT MOST RS232 Port MediaLB Clock Target Pin Mode Speed Address User 3 Pin 1024xFs 0101h configurable Isochronous Data Test Tab Tx Rx Blockwidth Packet Channel Channel quadlets Flow Control Ew Throughput Address Address frame kbit s 0 000 0 0010 15 Disable 188 1000 mus pkts Byte Disable 5000 Enable Counter
183. lay 1000 us oT mitb 12332 102415 5 setup txt Manual setup of test via Em mitb 12332 1024fs a 54 start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pan Mede Mode Speed Data Type Channel Address tust 0x01FE PC1 0x0002 Async Rx PC5 0x0002 Async Rx Device 3 Pin 1024xFs Async PC6 0x0004 Async Tx PC10 0x0004 Async Tx PC31 0x0000 DUT DUT edite Med td Interface Clock Ad dud Mode Speed oU 3 Pin 1024xFs 0101h ono Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0002 0x0004 5 Disable Varied Fixed Minimum Maximum increment Repetition Packet Length Length Length o engt es es es Length bytes bytes bytes 2 Enable 118 1014 1 1 Test Packet Duration Delay um pkts us Disable 5000 1100 Enable Counter Table 8 32 mitb_t2332_3pin_1024fs_a_5q Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 113 MediaLB Interface Test Bench e SmS V2 2 X 8 3 7 12333 1024fs 154 1024xFs test with alternating physical positions for Rx and Tx channels Test Concurrent Rx and Tx transfer of MediaLB asynchronous data Gharactersti
184. lected file name must have less than 63 characters Configure PCFlasher to PowerPC Application via the Mode menu Select the Upload check box and click Upload File button The log window indicates if the selected file has been properly loaded to the MITB platform User Manual Copyright O 2011 SMSC Page 38 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X _ ie Exit Clear Log Mode Device IP Address 192 168 0 100 Reconnect Flashing Host PC File Flash File on MITB ISP ML405 5 89420 02 02 09 00 bootloader 00 05 08 Upload Flash Upload Flash Upload File Upload Progress Commands DDR RAM Memory Usage Reset FPGA SUCCESS BY DESIGN Flash Memory Usage Delete Flash File Figure 5 4 Load FPGA Image File to MITB Platform 5 Flash FPGA image to MITB platform Select the Flash check box and click the Flash Board button Do not interrupt the flash process Flashing of FPGA image can take up to five minutes The log window indicates if the selected file has been properly flashed n Ext ClearLog Device IP Address 192 188 0 100 Re connect Flashing Host PC File Browse Flash File on MITB ISP ML405 P89420_vhdl_v02_02_09 00_bootloader_vO0_05_08 Upload Flash Upload Flash Flash Board Flash Progress Commands DDR RAM Memory Usage Reset FPGA SUCCESS BY
185. lications than the MITB it may be required to flash the OS81110 chips assembled on the Phy Boards Flashing of the OS81110 connected to the MDUT is also necessary when using the MOST150 Device Setup with the OS81110 assembled on the user hardware Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 21 MediaLB Interface Test Bench e smsc V2 2 X 2 4 2 Optional Components For debugging the MediaLB interface between the MITB and the MDUT the following tools are recommended e MediaLB Analyzer 2 e Oscilloscope As outlined in Figure 2 1 MediaLB Device Setup and Figure 2 2 MOST150 Device Setup the MediaLB Analyzer may be connected to the MediaLB 3 6 Pin high speed debug header to visualize data transfer on the MediaLB interface between the MDUT and the connected OS81110 MediaLB controller Additionally the MediaLB Analyzer can also be connected to the MediaLB 3 6 Pin high speed debug header on the MITB Platform to observe MediaLB data transfer between the FPGA and the connected 0581110 The MediaLB Analyzer allows for seamless observation of transferred MediaLB data in raw data format on MediaLB protocol level and additionally it enables visualization of combined and disassembled control messages as well as asynchronous packet data It is highly recommended to use a MediaLB Analyzer to observe and debug data transfer occurring on the MediaLB interface of the MDUT To verify the signal in
186. m Maximum m Packet Length Length Length bc Eo Length bytes bytes bytes Disable 14 Continuous bey Packet Pattern Test okts us Counter yte Disable 10000 2000 Enable Count f Synchronous Data Test Tab Tx Rx Blockwidth Channel Channel quadlets Ed Address Address frame yp Byte 0x000A 0x000C 1 Enable Counter Table 8 100 mitb_t5640_6pin_2048fs_cas Part 2 Copyright 2011 SMSC Document Version V2 2 X Date 2011 12 0902 User Manual Page 189 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 6 8 mitb t5641 6pin 2048fs si 2048xFs test 2 streaming loopbacks Test Concurrent Rx and Tx transfer of MediaLB synchronous and isochronous data Characteristic Blockwidth 2 x 1 quadlet per frame per loopback packet size 188 bytes packet throughput 1000 kbit s 15641 2048fs si cfg setup txt Manual setup of test via Files mitb 15641 2048fs start txt GUI possible ediaL B Interface Clock Transferred Physical Channel PUE Mode Speed Data Types Channel Address Allocate 0x01FE PC1 0 000 Sync Rx PC2 0x000C Sync Tx Device 6 Pin 2048xFs Sync PC3 0x000E Isoc Rx PC4 0x0010 Isocc Tx PC57 0x0000 GUI Configuration Configuration Tab DUT DUT verser
187. mitb t3641 6pin 2048fs s 15q 2048xFs test with 2 x 15 quadlets blockwidth Description Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 15 quadlet per frame c um mitb t3641 6pin 2048fs s 15q cfg setup txt Manual setup of test via s mitb t3641 6pin 2048fs s 15q cfg start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pan Manes Mode Speed Data Types Channel Address nene PCO 0x01FE PC1 0x000A Sync Rx PC15 0x000A Sync Rx Device 6 Pin 2048xFs Sync PC16 0x000C Sync Tx PC30 0x000C Sync Tx PC57 0x0000 DUT DUT MOST RS232 Port MediaLB Clock Target Pin Mode Speed Address ue 6 Pin 2048xFs 0101h Synchronous Data Test Tab Tx Rx Blockwidth Channel Channel quadlets iba Pa Address Address frame yp Byte 0x000A 0x000C 15 Enable Counter Table 8 64 mitb_t3641_6pin_2048fs_s_15q Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 153 MediaLB Interface Test Bench V2 2 X 8 4 11 13642 204815 s 44 smsc DUT 2048xFs test with ChannelAddresses in the upper address range Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 4 quadlet per frame CA 0x0042 amp CA 0x007E mitb 13642 6pin 2048fs s 4q cfg set
188. n 2 2 Date 2011 12 0902 Page 47 MediaLB Interface Test Bench e SmS V2 2 X No PGA Results Default state no active test Test Running Test active and running PGA Results NOT OK Test is stopped Test failed with Pattern Errors as indicated in the PGA Results window PGA Results OK Test is stopped No pattern errors in received messages detected PGA Statistics Status The Control Statistics Status Field provides an indication of the PGA test Field statistics The state is indicated by four colors Grey No PGA Statistics Default state no active test Yellow Test Running Test active and running Red Statistics NOT Test is stopped Test failed with uneven number of transmitted and received messages Green PGA Statistics OK Test is stopped Number of transmitted and received messages equal Table 6 3 Control Tab Parameters 6 2 2 2 Control Results Log The PGA s Control Results Log displays information about the pattern analyzer s state and provides error indications The information displayed in the Control Results Log is described in the following table Description DataType ControlMsg PGA configured for transfer of MediaLB Port used to transfer messages ReportType Once Result report is generated once Forever Result report is generated successive TimeWindow 15 If testis started manually the period used to generate
189. n Concurrent Rx and Tx transfer MediaLB isochronous data Blockwidth 2 x 27 quadlet per frame mitb 14641 204815 279 setup txt Manual setup of test via mitb_t4641_6pin_2048fs_i_27q_cfg_start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Mode Speed Data Types Channel Address PCO 0x01FE PC1 0 000 Isoc Rx PC27 0x000E Isoc Rx Device 6 Pin 2048xFs Isoc PC28 0x0010 Isoc Tx PC54 0x0010 Isoc Tx PC57 0x0000 DUT MODI DUT MOST RS232 Port MediaLB Clock Target Pin Mode Speed Address aoe 6 Pin 2048xFs 0101h configurable Data Test Tab Tx Rx Blockwidth Packet Channel Channel quadlets Flow Control Ew Throughput Address Address frame kbit s 0 000 0 0010 27 Disable 188 1000 e pkts Byte Disable 5000 Enable Counter Table 8 81 mitb_t4641_6pin_2048fs_i_27q User Manual Copyright 2011 SMSC Page 170 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e smnsc V2 2 X 8 5 11 mitb t4642 6pin 2048fs i 4q 2048xFs test with ChannelAddresses in the upper address range Concurrent Rx and Tx transfer of MediaLB isochronous data Blockwidth 2 x 4 quadlet per
190. n 1024xFs 0101h configurable ono Vata D Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 4 Disable Fixed Minimum Maximum Length Length Length aN Length bytes bytes bytes Disable 500 5 x Continuous Test Duration Packet Delay Packet Delay TES okts us Cds Pattern Type Nr TxCmd ms Enable 5000 2000 Enable Byte Counter AsyncBreak 32 4 Table 8 42 mitb_t23311_3pin_1024fs_a_4q Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 127 MediaLB Interface Test Bench e V2 2 X 8 3 15 mitb 12640 204815 14 Basic 2048xFs test Test Concurrent Rx and Tx transfer of MediaLB asynchronous data Gharacteristion Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 14 Bytes Packet Delay 2000 us A mitb_t2640_6pin_2048fs_a_1q_cfg_setup txt Manual setup of test via E mitb 12640 2048fs a 14 start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pan Mede Mode Speed Data Type Channel Address tst PCO 0x01FE PC1 0x0006 Async Rx Device 6 Pin 2048xFs Async PC2 0x0008 Async Tx PC57 0x0000 DUT DUT seamen 2 Interface Clock Ad des Mode Speed a
191. net interface to host PC for flashing the MITB platform e Trigger connector for generation of error events Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 17 MediaLB Interface Test Bench e smsc V2 2 X 2 2 3 Software GUI amp PGA Features e GUL is split in specific functional sections including o Configuration tab 6 2 1 o Control tab 6 2 2 o Asynchronous tab 6 2 3 o Synchronous tab 6 2 4 Isochronous tab 6 2 5 o System Commands tab 6 2 6 e Configuration o Manual as well as script based configuration of test cases o Optional configuration and debug message log windows o Optional generation of error trigger events o DUT MOST Target Address RS232 port Supported test pattern parameters o Control data test Tx Rx ChannelAddress Message length Test duration Pattern type Throughput o Asynchronous data test Tx Rx ChannelAddress Blockwidth in quadlets per frame Packet length Test duration Pattern type Packet delay Asynchronous packet type MDP MEP destination and source address o Synchronous data test Tx Rx ChannelAddress Blockwidth in quadlets per frame Pattern type o Isochronous data test Tx Rx ChannelAddress Blockwidth in quadlets per frame Packet length Test duration Pattern type Throughput o System command test Generation of MOSTLock MOSTUnlock and MLBReset commands Use
192. nnel Address PCO 0x01FE PC1 0x0006 Async Rx Device 3 Pin 1024xFs Async PC2 0x0008 Async Tx PC31 0x0000 DUT DUT MediaLB MOST RS232 Port Target Interface Clock Address Mode Speed Num 3 Pin 1024xFs 0101h 2 ono Vata D Tx Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Address Address frame Address Saute Acties 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum T Packet Length Length Length pode boe Length bytes bytes bytes Disable 14 Test Packet Delay ME Duration Delay e du E RxResp Nr RxResp RxResp pkts us ms Byte Enable 5000 2000 Enable Counter ReceiverProtocolError 32 100 Table 8 41 mitb_t23310_3pin_1024fs_a_1q Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 125 MediaLB Interface Test Bench e smsc V2 2 X 8 3 14 mitb_t23311_3pin_1024fs 44 The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is receiving async data and the transmitting device 0S81110 connected to the MDUT is sending AsyncBreak commands After the data transfer is started the MITB will transmit 16 AsyncBreak command on the Async Tx Channel ChannelAddress 0x0004 of the 0581110 AsyncBreak commands are generated with a delay of 5 ms between consecutive AsyncBreaks The MDUT receiving async packets needs to detect the AsyncBreak commands Following the detection of the AsyncBreak the MDU
193. not planned to be used like 2 above serial 125 and Transport stream interfaces do not require termination and may be unconnected User Manual Copyright O 2011 SMSC Page 30 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X For testing the MediaLB 3 pin interface of the DUT 0581110 Phy Boards Variant 3 need to be used On these Phy Boards 47 KOhm pull down resistors as well as 47 Ohm series resistors close to the INIC are present on all MediaLB 3 pin signals see the schematic in the Phy Board data sheet for details It is recommended to implement series termination resistors as close as possible to the DUT MediaLB Device as outlined in the MediaLB Specification 4 Figure 2 1 And optionally also a RC termination on the MLBCLK line may be implemented to provide the possibility to improve signal integrity if required Please note that the resistors and capacitors values shown in the MediaLB Specification are recommendations only Values chosen in actual systems are based on the MediaLB clock speed impedance of the PCB traces and the load capacitance on the line e For testing the MediaLB 6 pin interface of the DUT 0581110 Phy Boards Variant 1 need to be used On these Phy Boards 100 Ohm termination resistors are present on all differential MediaLB 6 pin signals close to the INIC Pull up and pull down resistors as defined in the MediaLB Specification see 4 Figure 2 6 for details
194. nses the next ReceiverBusy period starts The ReceiverBusy responses indicate that the OS81110 connected to the MDUT is not able to receive data The ReceiverBusy responses need to be detected by the MDUT and transmitted data quadlets acknowledged by a ReceiverBusy response must be repeatedly transmitted until a ReceiverReady response is detected The user must verify this behavior manually The MITB does not provide an indication if the ReceiverBusy is handled properly by the MDUT To verify the MDUT behavior and capture the generated ReceiverBusy responses generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the OS81110 is generating ReceiverBusy responses randomly it cannot be guaranteed that the ReceiverBusy responses always happen at times when the MDUT is transmitting Async messages By that means it is not guaranteed that MediaLB commands 0x20 0x22 and 0x24 transmitted by the MDUT are acknowledged by ReceiverBusy responses It might happen that the ReceiverBusy responses are present on the bus when NoData commands are transmitted by the MDUT In that case the ReceiverBusy responses have no effect on the behavior of the MDUT To still be able to test the proper handling of the ReceiverBusy response by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb t2643 6pin 2048fs a 1q indicates in most cases
195. nsmitting messages which may get lost User Manual Copyright O 2011 SMSC Page 92 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X smsc 2048xF s test with ReceiverBusy responses generated by Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes configurable Description Throughput 500 msgs s MITB generates series of 20 consecutive ReceiverBusy response periods on Control Rx Channel ChannelAddress 0x0002 of the DUT 0581110 During each period ReceiverBusy responses generated in every frame for approximately ms after delay of 500 ms next ReceiverBusy period starts ee mitb t1641 6pin 2048fs c 1q cfg setup txt Manual setup of test via El 11641 6 204816 19 start txt GUI possible atio Transferred Physical Channel Port Mode Interface Mode Clock Speed Data Type Channel Address Allocated Transfer PCO 0x01FE PC1 0x0004 Control Tx Device 6 Pin 2048xFs Control Ete 0 0002 Control Ax 57 0 00 Unused GUI Configuration Configuration Tab DUT MediaLB DUT MediaLB DUT MOST Interface Mode Clock Speed Target Address User 6 Pin 2048 0101h Control Data Test Tab Document Version V2 2 X Date 2011 12 0902 Tx Rx Channel Channel Address Address
196. nt Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes Throughput 500 msgs s mitb 11644 6pin 2048fs c 14 2048xFs test with TxBreak Commands generated by MITB Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes Throughput 500 msgs s mitb t1336 Spin 102415 c 19 Table 8 2 Control Test Overview Part 2 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 75 MediaLB Interface Test Bench e cnmnsc V2 2 X Test Test Characteristics MediaLB 6 pin Tests mitb_t1650_6pin_3072fs_c_1q Basic 3072xFs test Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 14 Bytes Throughput 250 msgs s mitb 11651 6pin 307215 c 14 3072xFs test with min max msg length max throughput Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Variable Message Length Throughput 475 msgs s mitb 11660 6pin 4096fs 14 Basic 4096xFs test Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 14 Bytes Throughput 250 msgs s 11661 6pin 4096fs c 14 4096xFs test with min max msg length max throughput Concurrent Rx and Tx t
197. nter Table 8 67 mitb 13651 307215 s 154 User Manual Copyright 2011 SMSC Page 156 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X smsc 8 4 14 13660 6pin 409615 s 14 Basic 4096xFs test Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame Description E mitb_t3660_6pin_4096fs_s_1q_cfg_setup txt Manual setup of test via E mitb t3660 6pin 409615 s 1q start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Par Mede Mode Speed Data Types Channel Address Allocated Een PCO 0x01FE 1 0x000A Sync Rx Device 6 Pin 4096xFs Sync PC2 0x000C Sync Tx PC116 0x0000 DUT fontes RS232 Port MediaLB Clock Target Pin Mode Speed Address 6 4096xFs 0101h Synchronous Data Test Tab Rx Blockwidth quadlets C S en Address Address frame ogne ype 0x000A 0x000C 1 Enable Eu ounter Table 8 68 mitb 13660 6pin 4096fs s 1q User Manual Page 157 Copyright O 2011 SMSC Document Version V2 2 X Date 2011 12 0902 MediaLB Interface Test Bench e lt 5 7 lt V2 2 X 8 4 15 mitb_t3661 409615 s 154
198. nterface Executable 198 9 2 PCElash r rrr ettet Per Un resp 198 9 3 FPGA WMA 6 198 9 4 Pattern Generator amp Analyzer 199 9 5 581110 INIC Firmware 199 9 6 Test Configuration Files 200 APPENDIX A REFERENCES nene hea deg 201 APPENDIX LIST OF 202 APPENDIX C SPARE PART LIST 203 Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 7 MediaLB Interface Test Bench e smsc 2 2 APPENDIX D LIST OF FIGURES 1 11 11 11 204 APPENDIX E LIST OF TABLES 11rii tuneruensveervvesveceudscduecevetvasseentventveesneeds 205 APPENDIX eum 208 Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 09 Page 8 MediaLB Interface Test Bench smsc V2 2 X 1 Preface 1 1 Intended Use This SMSC product is intended to be used for developing testing or analyzing MOST and MediaLB based multimedia products and systems by persons with experience in developing multimedia devices Wotice Use this SMSC product only with original SMSC devices
199. o a host PC A Graphical User Interface GUI runs on the PC and is able to configure the generated test patterns and to display the test results of the pattern verification 2 1 Overview A complete hardware setup used to verify if a MediaLB device has been implemented properly typically includes user hardware and a MITB both parts connected The MediaLB device to be tested is part of the user hardware see for example Figure 2 1 and Figure 2 2 To simplify the verification of proper MDUT functionality the MITB features a PGA The patterns generated by the PGA are transmitted by the MITB The MDUT receives these patterns on its MediaLB Port and re transmits the same patterns which in turn are received by the MITB and verified by the PGA If the data patterns transmitted and received by the MITB are identical it can be ensured that the MDUT is able to properly receive and transmit data on the MediaLB interface Since the test pattern generation and analysis is done by the MITB the implementer of the MDUT can focus on programming the MDUT rather than spend time and resources to configure the MediaLB Controller In addition the user is exempt from coding a pattern generator and analyzer To be able to implement a sophisticated PGA the MITB Platform features an FPGA incorporating a PowerPC and a MediaLB device interface The PowerPC generates and analyzes the test patterns for all MediaLB data types including control asynchronous synchronous and
200. of a configuration file represents the test name Configuration setup files define general test parameters and have the following format mitb_txxxx_ _cfg_setup txt Configuration start files are used to start the pattern generation and the format looks as follows mitb_txxxx_ _cfg_start txt User Manual Copyright 2011 SMSC Page 200 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X Appendix A References 1 INIC Explorer User Manual SMSC http www smsc ais com INIC Explorer Download 2 MediaLB Analyzer User Manual SMSC http www smsc ais com MediaLB Analyzer Download 3 Physical Interface Board 0581110 2 0 Data Sheet SMSC Contact support ais de smsc com 4 MediaLB Specification V4 2 SMSC http www smsc ais com MediaLB Download 5 0581110 Hardware Data Sheet SMSC Contact support ais de smsc com 6 OS81110 INIC API User s Manual SMSC Contact support ais de smsc com 7 OSS Flasher SMSC http www smsc ais com OSS Flasher Download 8 www smsc com Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 201 MediaLB Interface Test Bench e cnmnsc V2 2 X Appendix B List of Abbreviations The table below gives an overview of abbreviations mentioned in this user manual listed in alphabetical order Abbreviation Definition FOT GUI MedialB Device Interface Macro MDP MOST Data Packet
201. of test via ec mitb 15333 Spin 1024fs csi start txt GUI possible Interface Clock Transferred Physical Channel Pon Moce Mode Speed Data Types Channel Address eder tarsier PCO 0x01FE 1 0 0004 2 0 0002 Control Rx PCS 0x000A Sync Rx Device 3 Pin 1024xFs Control Sync Isoc PC6 0x000C Sync Tx PC7 0 000 Isoc Rx PC8 0x0010 5 Tx PC31 0x003E DUT DUT DUT MOST RS232 Port MediaLB MediaLB Target Trigger on Interface Clock Address Error Mode Speed 3 Pin 1024xFs 0101h Disable Control Data Test Tab Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum increments Repetitions Message Length Length Length bytes 5 Length bytes bytes bytes 9 Disable 8 Continuous mm Throughput Message Pattern Test msgs msgs s Counter Type Disable 5000 50 Enable en ounter ono Vata 2 Rx Blockwidth Frame Pattern Channel Channel quadlets Counter s A Address Address frame yp 0 000 0x000C 1 Enable B ounter Table 8 97 15333 Spin 1024fs csi Part 1 User Manual Copyright O 2011 SMSC Page 186 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e lt 5 7 lt V2 2 X 1024xFs test 3 data types Test Concurrent Rx and Tx transfer of MediaLB control synchronous and isochronous data hec E Blockwidth 2 x 4 quadlet per frame per loopback Cont
202. of the ControlBreak command is signalled properly The MITB does not provide an indication if the MDUT is handling the ControlBreak as expected To verify the MDUT behavior and capture the generated ControlBreak command generated by the MITB it is required to trace the MediaLB data transfer e g with a MediaLB Analyzer Since the OS81110 is generating ControlBreak commands randomly it cannot be guaranteed that the ControlBreak command always happen at times when the OS81110 is transmitting control messages By that means it is not guaranteed that the MDUT is receiving a message when the Contro Break command is transmitted by the OS81110 Since the MDUT may not receive a message when the ControlBreak is present on the MediaLB bus the ControlBreak command may not be detected by the MDUT In that case the ControlBreak commands have no effect on the behavior of the MDUT To still be able to test the proper handling of the ControlBreak command by the MDUT the test could be executed by configuring the MITB GUI manually with e g user specific delay parameters The MITB test case mitb t1644 6pin 2048fs c 1q is expected to indicate a TEST PASS This is the case because the messages terminated by a ControlBreak command are re transmitted entirely by the OS81110 User Manual Copyright O 2011 SMSC Page 98 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X smsc 2048xFs test with ControlBreak commands gen
203. ogs Configuration and Debug Messages Clear Log PGA s Isochronous Results Log PGA s Isochronous Statistics Log Figure 6 6 Isochronous Tab Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 57 MediaLB Interface Test Bench e SmS V2 2 X 6 2 5 1 Isochronous Tab Parameters Parameters and buttons of the isochronous tab are described in the table below Name Description transmitted by the 0581110 connected to the MDUT by the OS81110 connected to the MDUT Number of quadlets allocated per MediaLB frame for the transmission and reception of the isochronous test pattern Depending on the MediaLB speed the bandwidth ranges from 1 to 27 quadlets per frame isochronous receive channel of the OS81110 connected to the MDUT 196 Length of isochronous packet set to 196 bytes For details about pattern formats refer to chapter 7 Isochronous data in kbit transmitted per second Minimum throughput 1000 kbit s maximum up to 65535 kbit s packets packets are transmitted Button to clear the PGA Results and Statistics windows Test Status Field The Isoc Test Status Field provides an indication of the overall state of a test The state is indicated by four colors Grey Test Default state no active test Yellow Test Running Test active and running Red TEST FAILED Test is stopped and failed with errors detected in either the PGA Results or Statis
204. on Blockwidth 2 x 15 quadlet per frame Variable Packet Length Packet Delay 2000 us C d en mitb 12333 1024fs a 15q cfg setup txt Manual setup of test via Files mitb 12333 1024fs a 154 start txt GUI possible DUT MediaLB Configuration ronwede a PCO 0x01FE PC1 0x0002 Async Rx PC2 0x0004 Async Tx 0x0002 Async Rx PC4 0x0002 Async Rx PC5 0x0004 Async Tx PC6 0x0004 Async Tx PC7 0x0002 Async Rx PC8 0x0002 Async Rx 9 0x0002 Async Rx PC10 0x0004 Async Tx PC11 0x0004 Async Tx PC12 0x0004 Async Tx PC13 0x0002 Rx PC14 0x0002 Async Rx PC15 0x0002 Async Rx Device 3 Pin 1024xFs Async PC16 0x0002 Async Rx PC17 0x0004 Async Tx PC18 0x0004 Async Tx PC19 0x0004 Async Tx PC20 0x0004 Async Tx 21 0 0002 22 0 0002 PC23 0x0002 Async Rx PC24 0x0002 Async Rx PC25 0x0002 Async Rx PC26 0x0004 Async Tx PC27 0x0004 Async Tx PC28 0x0004 Async Tx PC29 0x0004 Async Tx PC30 0x0004 Async Tx PC31 0x0000 Table 8 33 mitb 12333 1024fs 154 Part 1 User Manual Copyright O 2011 SMSC Page 114 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 1024xFs test with alternating physical positions for Rx and Tx channels Test 2 2 MediaLB asynchronous data Blockwidth 2 x 15 quadlet per frame Chee M Variable Packet Length Pa
205. or features a pin used to generate events in case the PGA detects error conditions A detailed layout of the connectors is shown in the following sections 3 6 1 Configuration Debug Header For proper operation of the MITB a dedicated test firmware needs to be flashed to the OS81110 connected to the MDUT The configuration debug header is defined to flash the OS81110 via its JTAG Port With SMSC s INIC Explorer tool which can be directly connected to the configuration debug header the OS81110 on a Board or on the user hardware can be flashed The configuration debug header is defined as a standard 14 Pin 2 x 7 2 mm header such as Molex 87332 1420 or equivalent The following figure outlines the configuration debug header including the connection to the 0581110 INIC For further details please refer to the 0581110 Data Sheet 5 0581110 RST 3 3 Vs 2938100 1H 2 ERR BOOT Tae o sf eA TDI DSDA TCK DSCL TDO DINT 131 TS Figure 3 2 Configuration Debug Header Copyright 2011 SMSC User Manual Document Version V2 2 X Date 201 1 12 0902 Page 29 MediaLB Interface Test Bench er smsc V2 2 X 3 6 2 Phy Board Connector To connect a Phy Board to a main board a Phy Board connector is used An example Phy Board connector is SAMTEC 0 5 mm 20 pair high speed differential pair socket QSH 020 01 L D DP A The layout of the Phy
206. ost cases This behavior is expected and entirely depends on the customer specific MDUT system re transmission mechanisms If the OS81110 generates a HeceiverProtocolError response packet reception is terminated and the broken packet will be lost In case the MDUT does not re transmit the broken packet the MITB will indicate a missing packet and a TEST FAILED If the broken packet is re transmitted by the MDUT after receiving the HeceiverProtocolError response the MITB will not detect any errors User Manual Copyright O 2011 SMSC Page 124 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e smsc V2 2 X 1024xFs test with ReceoverProtocolError responses generated by MITB Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 14 Bytes 2000 MITB generates 32 ReceiverProtocolError responses the Async Rx Channel ChannelAddress 0x0008 of the DUT 0581110 ReceiverProtocolError responses generated with a delay of 100 ms between consecutive ReceiverProtocolError eae mitb_t23310_3pin_1024fs_a_1q_cfg_setup txt Manual setup of test via mitb_t23310_3pin_1024fs_a_1q_cfg_start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Puno Mode Speed Data Type Cha
207. p In this case Phy Board must be connected to the user hardware to complete the setup see paragraph 3 6 2 1 for detailed description For a MOST150 Device Setup no Phy Board connector is required on the user hardware because the functionality of the Phy Board is an integral part of the user hardware 3 6 2 1 Wiring of Phy Board Connector for MediaLB Device Setup To connect the Phy Board to the user hardware in the MediaLB Device Setup the following general information and instructions on wiring and termination need to be followed case of OS81050 and OS81110 Phy Board 12 V supply is not required In case of 0581082 92 PhyBoard 12 V is required e f no power management is required the 3 3 V switched and 3 3 V continuous supply can be tied together from a single supply e f l2C is not used no termination is required on I2C signals But if possible it is recommended to connect the 2 interface Possible use cases are flashing of INIC firmware via EHC or initial communication with INIC for debug purposes e The ID pins are configured on the PHY Boards They may be used on the user boards to identify the PHY Boards connected The definition of the ID signals can be found in the datasheets of the PHY Boards If the ID pins are evaluated on the user board pull ups are required If the ID pins are unused no termination is required e MISC signals not require termination be unconnected Signals that
208. pes User Manual Copyright O 2011 SMSC Page 62 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 6 3 2 Load Configuration Files The MITB includes a set of predefined test cases For every test case a configuration setup file is provided which is used to initialize the MITB Additionally for every test case a configuration file is available to start the generation of test patterns The provided configuration files include parameters required to execute a defined test The configuration files for the predefined test cases are part of the MITB delivery and can be found on the installation CD For details about the files provided on the installation CD refer to chapter 9 Summary of Provided Files For loading the configuration files the following sequence is recommended Step 1 Configure MITB Step 1 1 Select configuration tab see Figure 6 2 Step 1 2 Define RS232 Port Step 1 3 Enable or disable Trigger on Error events Step 1 4 Enable or disable visibility of Configuration Debug Messages Step 1 5 Click Initialize MITB button to configure MITB with the provided parameters Step 1 6 Select predefined test case to be executed Step 1 7 Click Load Config File button and load setup file for selected test case Step 2 Start Loop Back Application on Device Under Test To successfully run a test make sure that the MDUT is configured for the same parameters as adju
209. r The MediaLB 3 6 Pin high speed debug header represents a differential high speed connector used to connect a MediaLB Analyzer for observation of data transfer on a MediaLB interface Especially for MediaLB 6 Pin debugging it is essential that this 40 pin header can support high speed data rates An example header is SAMTEC 0 5 mm 20 pair high speed differential pair socket QSH 020 01 L D DP A For more details including schematic and PCB layout recommendations refer to the MediaLB Specification 4 The MediaLB debug header is physically identical to the Phy Board connector but as outlined in Figure 3 4 MediaLB 3 6 Pin High Speed Debug Header the MediaLB debug header incorporates only the MediaLB 3 Pin and 6 Pin signals as a subset of the available signal on the Phy Board connector Pin39 Pin40 No Connect Dur Detection Pin37 Pin38 No Connect Pin35 No Connect Pin36 No Connect No Connect Pin33 No Connect Pin34 No Connect Pin31 No Connect Pin32 No Connect Pin29 No Connect Pin30 No Connect Pin27 No Connect Pin28 No Connect Pin25 No Connect Pin26 No Connect Pin23 No Connect Pin24 No Connect Pin21 No Connect Pin22 No Connect Pint9 MLBDP Pin20 No Connect MediaLB Pint7 MLBDN 18 MediaLB 6 pin differential 15 16
210. r IP address 192 168 0 100 To enable proper communication between the MITB platform and the connected host PC the IP address on the PC needs to be set to 192 168 0 1 as shown in the following figure 4 Local Area Connection 2 Properties 4 Internet Protocol Properties General Advanced General Connect using You can get IP settings assigned automatically if your network supports this capability Otherwise you need to ask your network administrator for D Link DUB E100 USB 2 0 Fast Ethe the appropriate settings This connection uses the following items Obtain an IP address automatically Client for Microsoft Networks File and Printer Sharing for Microsoft Networks IP address 492 168 0 1 15 QoS Packet Scheduler Protocol TCP IP Subnet mask 255 255 255 0 Default gateway 192 1 68 0 st Description Transmission Control Protocol Internet Protocol The default 9 Use the following DNS server addresses wide area network protocol that provides communication 3 2 across diverse interconnected networks Preferred DNS server Alternate DNS server Show icon in notification area when connected Notify me when this connection has limited or no connectivity Figure 5 2 IP Address Configuration on Host PC Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 37 MediaLB Interface T
211. r Manual Copyright O 2011 SMSC Page 18 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc 2 2 e Test result reporting o Number of transmitted messages packets o Number of received messages packets o Number of errors o Number of locks o Throughput o Result reporting done by visualization in GUI as well as test protocol file Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 19 MediaLB Interface Test Bench e smsc V2 2 X 2 3 Functional Restrictions The following limitations apply to the MITB e The PGA supports generation and analysis of control messages asynchronous packets and isochronous packets with the following lengths total packet length including 2 bytes of PML o Control messages MCM Min message length of 19 bytes max message length of 58 bytes o Asynchronous packets Min packet length of 16 bytes max packet length of 1534 bytes Min packet length of 26 bytes max packet length of 1526 bytes Isochronous packets Packet length of 188 bytes and 196 bytes e The PGA is able to generate and verify test patterns up to the following data quadlets per MOST MediaLB frame one direction o Control messages Max 1 quadlet frame o Asynchronous packets Max 27 quadlet frame o Synchronous streaming data Max 15 quadlet frame Isochronous packets Max 27 quadlet frame
212. ransfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Variable Message Length Throughput 475 msgs s Table 8 3 Control Test Overview Part 3 User Manual Copyright O 2011 SMSC Page 76 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X smsc 8 2 1 mitb t1310 3pin 256fs 14 Basic 256xFs test Concurrent Rx and Tx transfer of MediaLB control data Description Blockwidth 2 x 1 quadlet per frame Fixed Message Length 8 Bytes Throughput 450 msgs s AE e 11310 256fs c 14 setup txt Manual setup of test via E mitb t1310 3pin 256fs c 1q cfg start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pan ede Mode Speed Data Type Channel Address cuisse 0x01FE PC1 0x0004 Control Tx Device 3 Pin 256xFs Control PC2 0x0002 Control Rx PC7 0x003E DUT DUT Clock Ad Speed 3 Pin 256xFs 0101h ol D D Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum Repotitions Message Length Length Length bytes x 5 Length bytes bytes bytes 9 Disable 8 5 Continuous Throughput Message Pattern Test msgs msgs s Counter Type Disable 5000 4
213. re 3 1 MediaLB Interface Test Bench Platform RS232 to Host PC The MITB platform features two 9 pin female D SUB RS232 connectors The lower one is used to establish an RS232 connection to a host PC Via this connection the GUI running on the host PC communicates with the Pattern Generator amp Analyzer on the MITB platform The RS232 interface is configured for the following parameters Baudrate 115200 Data 8 bit Parity None Stop 1 bit Flow Control None To enable communication with the MITB platform the GUI running on the host PC automatically configures the RS232 port of the PC with the proper parameters Power Supply The MITB platform is designed for a typical power supply of 12 V DC voltage and a power consumption of 3 A A proper power supply is part of the MITB delivery On Off Switch The on off switch is used to turn on and off the power supply of the MITB platform 5 V Power LED The 5 V Power LED indicates if the platform is properly powered Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 25 MediaLB Interface Test Bench e smsc V2 2 X LCD Display Status information such as version of the Pattern Generator amp Analyzer firmware running on the platform is provided on the 4 x 16 character LCD display User Buttons There are five active high pushbutton switches available for general purpose usage The WEST button is used to initiate the flash process of the M
214. ress viensis 0x01FE PC1 0x000A Sync Rx Device 3 Pin 256xFs Sync PC2 0x000C Sync Tx PC7 0x0000 DUT DUT MOST RS232 Port MediaLB Clock Target Pin Mode Speed Address User 3 Pin 256xFs 0101h configurable Synchronous Data Test Tab Tx Rx Blockwidth AS Pattern Channel Channel quadlets Address Address frame Counter 0x000A 0x000C 1 Enable Counter Table 8 55 mitb 13310 256fs s 14 User Manual Copyright 2011 SMSC Page 144 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cSnmnsc V2 2 X 8 4 2 mitb t3320 3pin 512fs s 1q Basic 512xFs test Description Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame c um mitb 13320 5125 5 14 setup txt Manual setup of test via s mitb 13320 51215 s 19 start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Fw Meet Mode Speed Data Types Channel Address nene PCO 0x01FE PC1 0x0012 Sync Rx Device 3 Pin 512xFs Sync PC2 0x0014 Sync Tx PC15 0x0000 DUT RS232 Port MediaLB Target Pin Mode EE Address Speed 3 Pin 512xFs 0101h Synchronous Data Test Tab Tx Rx Blockwidth Frame Pattern Channel Channel quadlets Address Address frame yp Byte 0x0012 0x0014 1 Enable Counter Table 8 56 mitb 13320 512fs
215. rface Clock Transferred Physical Channel Por Moce Mode Speed Data Type Channel Address PCO 0x01FE PC1 0x0002 Async Rx Device 3 Pin 1024xFs Async PCAS Async Rx PC16 0x0004 Async Tx 0 0004 1 0 0000 GUI Configuration Configuration Tab DUT DUT MediaLB Media g PUT MOST RS232 Port Target Interface Clock Address Mode Speed oo 3 Pin 1024xFs 0101h configurable ono 0 2 Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0002 0x0004 15 Disable Varied Fixed Minimum Maximum Meremere Repotitions Packet Length Length Length bytes pkts Length bytes bytes bytes Enable 54 1014 1 1 4 Duration Delay obl En pkts us Disable 5000 1000 Enable Random Table 8 31 mitb 12931 3pin 102415 154 User Manual Copyright O 2011 SMSC Page 112 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X 8 3 6 mitb 12332 102416 5q smsc 1024xFs test with intermediate Blockwidth and min and max packet length Test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 5 quadlet per frame Variable Packet Length 6 1014 byte Packet De
216. rol Fixed Packet Length 8 bytes 188 bytes Isoc Blocksize Message Throughput 50mgs s 1000 kbit s Test Configuration mith 15333 102415 csi cfg_setup txt Manual setup of test via Files mitb_t5333_3pin_1024fs_csi_cfg_start txt GUI possible ono Vata C Rx Blockwidth Packet Siz Packet Channel Channel quadlets Flow Control gies e Throughput Address Address frame kbit s 0x000E 0x0010 1 Disable 188 1000 Continuous Pattern Test okts Counter Type Disable 20 000 Enable Byte Counter Table 8 98 15333 Spin 102415 csi Part 2 Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 187 MediaLB Interface Test Bench e SmS V2 2 X 8 6 7 mitb t5640 6pin 2048fs cas Basic 2048xFs test Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous data Blockwidth 2 x 1 quadlet per frame per loopback Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s COM DEN mitb 15640 2048fs cas setup txt Manual setup of test via ec mitb 15640 6pin 2048fs cas cfg start txt GUI possible Interface Clock Transferred Physical Channel PUE Mode Speed Data Types Channel Address eder
217. s mitb 11338 102415 14 setup txt mitb 11338 102415 19 start txt DUT MediaLB Configuration Manual setup of test via GUI possible Description Throughput 500 msgs s MITB transmits 240 ControlBreak commands on the Control Tx Channel ChannelAddress 0x0004 of the DUT OS81110 ControlBreak commands generated with a delay of 20 ms between consecutive ControlBreaks Test Transferred Physical Channel Port Mode Interface Mode Clock Speed Data Type Channel Address Allocated Transfer PCO 0x01FE PC1 0x0004 Control Tx Device 3 Pin 1024xFs Control PC2 0x0002 Control Rx PC31 0x003E GUI Configuration Configuration Tab configurable DUT MediaLB DUT MediaLB DUT MOST PEACE Pon Interface Mode Clock Speed Target Address User 3 Pin 1024xFs 0101h Control Data Test Tab Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum Message Length Length Length Length bytes bytes bytes 9 Disable 45 Continuous Test Duration Throughput Message Delay TxCmd msgs msgs s Gunton Pattern Type TxCmd Nr TxCmd ms Disable 5000 500 Enable Byte Counter ControlBreak 240 20 Table 8 13 mitb_t1338_3pin_1024fs_c_1q User Manual Copyright 2011 SMSC Page 90 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X smsc 8 2 1
218. s mitb 12650 6pin 307215 14 Basic 3072xFs test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 32 Bytes Packet Delay 2000 us Table 8 25 Asynchronous Test Overview Part 3 User Manual Copyright O 2011 SMSC Page 106 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e smsc V2 2 X Test Name Test Characteristics MediaLB 6 pin Tests 3072xFs test with min max packet length max bandwidth Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 27 quadlet per frame Varied Packet Length Packet Delay 6000 us mitb_t2660_6pin_4096fs_a_1q Basic 4096xFs test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 quadlet per frame Fixed Packet Length 32 Bytes Packet Delay 2000 us mitb_t2651_6pin_3072fs_a_27q Table 8 26 Asynchronous Test Overview Part 4 Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 107 MediaLB Interface Test Bench e smnsc V2 2 X 8 3 1 12310 3pin 256fs a 1q Basic 256xFs test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 per frame Fixed Packet Length 14
219. s MEP Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum A Packet Length Length Length jos Length bytes bytes bytes p Disable 14 Continuous Test Duration Packet Delay Packet Test okts us Counter Pattern Type RxResp Nr RxResp Pas Enable 5000 2000 Enable Byte Counter ReceiverBusy 20 110 Table 8 39 12338 1024fs 14 Copyright O 2011 SMSC User Manual Page 121 MediaLB Interface Test Bench e smsc V2 2 X 8 3 12 mitb 12339 3pin 1024fs 44 The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is transmitting async data and the receiving device OS81110 connected to the MDUT is responding with ReceiverBreak responses After the data transfer is started the MITB will generate 32 ReceiverBreak responses on the Async Rx Channel ChannelAddress 0x0002 of the OS81110 ReceiverBreak responses are generated with a delay of 5 ms between consecutive HeceiverBreaks The MDUT transmitting async packets needs to detect the ReceiverBreak responses Following the detection of the ReceiverBreak the MDUT must stop packet transmission The user needs to verify manually that the MDUT is properly terminating the packet transmission Additionally it may be verified if MDUT internally a status indicating the detection of the ReceiverBreak response is signalled The MITB does not provide an indi
220. s O MEP PGA Copyright O 2011 SMSC User Manual Document Version 2 2 Date 2011 12 09 Page 202 MediaLB Interface Test Bench e cnmnsc V2 2 X Appendix C Spare Part List The following spare parts are available for this SMSC product Part Name Part Number Optical fiber set Yazaki 2 0 X10166 MOST150 oPHY 240 PHYplus Interface Board Variante1 X13363 MOST150 oPHY 240 PHYplus Interface Board Variante3 X13365 Powersupply 12V 3A5 TR45 Binder VO1 00 00 X13167 RS232 Interface Cable X10162 USB RS232 Adapter FTDI X13179 Copyright O 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 203 MediaLB Interface Test Bench e smsc V2 2 X Appendix D List of Figures Figure 2 1 Figure 2 2 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 MediaLB Device Setup 12 MOST150 Device 14 MediaLB Interface Test Bench Platform 25 Configuration Debug Header 29 Phy4 Board Connector aca rid a dui fase 30 MediaLB 3 6 Pin High Speed Debug
221. s stopped Number of transmitted and received packets equal Table 6 6 Asynchronous Tab Parameters 6 2 3 2 Asynchronous Results Log The PGA s Asynchronous Results Log displays information about the pattern analyzer s state and provides error indications The information displayed in the Asynchronous Results Log is described in the following table Name Description PacketMsg_MEP PGA configured to transfer MEP Once Result report is generated once Forever Result report is generated successive 1s Iftestis started manually the period used to generate the result report is 1 s xs If test is started by loading a configuration file the period used to generate the result report is defined in the loaded file LockState Pattern Unlock Pattern Analyzer receives invalid packets Pattern Search Pattern Analyzer received a valid packet and waits to receive the next packet in the correct sequence Pattern Locked Pattern Analyzer receives valid packets No Error No error detected Corrupted Msg Packet incorporates error in payload Missed Msg Error in received packet sequence detected Table 6 7 Asynchronous Results Log User Manual Copyright 2011 SMSC Page 52 Document Version 2 2 Date 2011 12 09 MediaLB Interface Test Bench e smscC V2 2 X A successful asynchronous data test indicates e Locks 11 Errors 0 e MDP MEP Missed 0 pkts The test result is ind
222. sed Total number of missed messages MCM Tx Total MCM Rx Total Table 6 5 Control Statistics Log Copyright 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 49 MediaLB Interface Test Bench er smsc V2 2 X 6 2 3 Asynchronous Tab The following figure shows the asynchronous tab of the GUI In this tab parameters can be entered which define the characteristics of the generated asynchronous test patterns A button is available to manually start and stop the pattern processing Log windows display the PGA results and statistics Dedicated test status fields indicate the test status Asynchronous PGA Statistics Status Field Asynchronous Tab Parameters Asynchronous PGA Result Status Field Asynchronous Start Stop Button Asynchronous Test Status Field 7 GUI V220 MediaLB Interface Test Bench Pattern Generator and Analyzer GUI 2 2 0 Configuration Control Asynchronous Synchronous Isochronous System Comman s Asynchronous Data Test Tx ChannelAddress 0006 hex Rx ChannelAddress oo08 hex Start Test Blockwidth 10 quadlets frame RxResponse None Number 5 dec Delay 100 ms TxCommand Number 5 dec Delay 100 ms 112233445566 Varied Packet Length Fixed Length 1014 bytes Pattern Generator and Analyzer Statistics Pattern Type Byte Counter Packet D
223. ses in ms Defines special TxCommands to be generated by the MITB The following TxCommands are defined None AsyncBreak Indicates number of special TxCommands to be generated TxCommands in ms Length of asynchronous packets in case Varied Packet Length has been disabled Value Range 6 1524 Bytes Minimum length of asynchronous packets in case Varied Packet Length has been enabled Value Range 6 1524 Bytes with Minimum Maximum Maximum length of asynchronous packets in case Varied Packet Length has been enabled Value Range 6 1524 Bytes with Maximum Minimum Number of bytes the length of consecutive packets are incremented in case Varied Packet Length has been enabled Number of consecutive packets generated with the same length in case Varied Packet Length has been enabled Two types of patterns are supported Byte Counter and Random For details about pattern formats refer to chapter 7 Defines the delay between the end of a transmitted packet and the start of the following packet This value is only valid in case the configured Packet delay is higher than the transfer time of the generated packets Minimum packet delay 1000 us maximum up to 65535 us Check box to enable disable the successive transmission of asynchronous packets If Continuous Test has been disabled the Test Duration defines how many packets are transmitted Button to clear the PGA Results and Statistics windows Button to manually start and
224. sion V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X XILINX Virtex4 FX60 15 MOST 150 11 N Naming 71 On Off switch 25 Optical MOST150 interface 14 0581110 MOST150 transceiver 11 OSS 27 Pattern Generator amp Analyzer PGA 10 POA c n 10 PGA Active LED 26 Phy Board Variant 1 13 15 Phy Board Variant 3 13 PHY2 3 3 power LED 26 PHY2 Active LED 26 PHY2 MediaLB Lock LED 26 PHY2 MOST Lock LED 26 PHY2 Phy Board 26 Physical Interface Board 0581110 11 Power Supply 25 PowerP 10 Predefined test cases 61 PR 69 70 RS232 10 12 14 RS232 to host PC connection 25 S Scope of delivery 9 Single ended MediaLB 3 Pin interfa
225. ssage the MITB will indicate a missing message and a TEST FAILED If the broken message is re transmitted by the MDUT after receiving the ReceiverProtocolError response the MITB will not detect any errors User Manual Copyright O 2011 SMSC Page 96 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X smsc 2048xFs test with ReceiverProtocolErr responses generated by Concurrent Rx and Tx transfer of MediaL control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes Document Version V2 2 X Date 2011 12 0902 Description Throughput 500 msgs s MITB generates 20 ReceiverProtocolError responses on the Control Rx Channel ChannelAddress 0x0002 of the DUT 0581110 ReceiverProtocolError responses generated with a delay of 100 ms between consecutive ReceiverProtocolError See mitb t1643 6pin 2048fs c 1q cfg setup txt Manual setup of test via Files mitb t1643 6pin 2048fs c 19 start txt GUI possible ediaLB atio Interface Transferred Physical Channel Port Mode Mode Clock Speed Data Type Channel Address Allocated Transfer PCO 0x01FE PC1 0x0004 Control Tx Device 6 Pin 2048xFs Control FOR oe Control Rx PC57 0x003E Unused GUI Configuration Configuration Tab DUT MediaLB DUT MOST RS232 Port Interface Address User 6 Pin 2048xFs 0101h config
226. ssumed for inaccuracies Specifications and other documents mentioned in this document are subject to change without notice SMSC reserves the right to make changes to this document and to the products at any time without notice Neither the provision of this information nor the sale of the described products conveys any licenses under any patent rights or other intellectual property rights of SMSC or others There a number of patents and patents pending on the MOST technology and other technologies No rights under these patents are conveyed without any specific agreement between the users and the patent owners The products may contain design defects or errors known as anomalies including but not necessarily limited to any which may be identified in this document which may cause the product to deviate from published descriptions Anomalies are described in errata sheets available upon request SMSC products are not designed intended authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage Any and all such uses without prior written approval of an officer of SMSC will be fully at your own risk MediaLB SMSC and MOST are registered trademarks of Standard Microsystems Corporation SMSC or its subsidiaries Other names mentioned may be trademarks of their respective holders SMSC disclaims and excludes any and all warranties including
227. st Duration Throughput Message Pattern Type RxRes Nr RxRes 66 Test msgs msgs s Counter ms P Disable 5000 500 Enable Byte Counter ReceiverProtocolError 20 100 Table 8 12 mitb 11337 1024fs 14 User Manual Copyright O 2011 SMSC Page 88 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 8 2 10 mitb t1338 3pin 1024fs 14 The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is receiving control data and the transmitting device OS81110 connected to the MDUT is sending ControlBreak commands After the data transfer is started the MITB will transmit 240 ControlBreak command on the Control Tx Channel ChannelAddress 0x0004 of the OS81110 ControlBreak commands are generated with a delay of 20 ms between consecutive ControlBreaks The MDUT receiving control messages needs to detect the ControlBreak commands Following the detection of the ControlBreak the MDUT must stop an ongoing message reception Already received data quadlets are considered to be invalid and should be rejected The user needs to verify manually that the MDUT is properly terminating the message reception Additionally it may be verified if MDUT internally a status indicating the detection of the ControlBreak command is signalled properly The MITB does not provide an indication if the MDUT is handling the ControlBreak as expected To verify the MDUT behavior and
228. st Status Field The Sync Test Status Field provides an indication of the overall state of a test The state is indicated by four colors Grey Test Default state no active test Yellow Test Running Test active and running Red TEST FAILED Test is stopped and failed with errors detected in either the PGA Results Green TEST PASSED Test is stopped and passed PGA Results Status The Sync Results Status Field provides an indication of the PGA test results Field of actually received test patterns The state is indicated by four colors Grey PGA Results Default state no active test Yellow Test Running Test active and running Red PGA Results NOT OK Test is stopped Test failed with Pattern Errors as indicated in the PGA Results window Green PGA Results OK Test is stopped No pattern errors in received stream detected PGA Statistics The Sync Statistics Status Field is not enabled since currently there are no Status Field PGA statistics available for Synchronous data transfer Grey PGA Statistics n a Default state no PGA statistics available Table 6 9 Synchronous Tab Parameters 6 2 4 2 Synchronous Results Log The PGA s Synchronous Results Log displays information about the pattern analyzer s state and provides error indications The information displayed in the Synchronous Results Log is described in the following table Name Description Sync PGA configured
229. start txt GUI possible ediaL O Interface Clock Transferred Physical Channel Par Mede Mode Speed Data Types Channel Address Allocated PCO 0x01FE PC1 0x000E Isoc Rx Device 6 Pin 3072xFs Isoc PC2 0x0010 Isoc Tx PC86 0x0000 DUT Dur Most RS232 Port MediaLB Clock Target Pin Mode Speed Address User configurable 6 Pin 3072xFs 0101h lsochronous Data Test Tab Tx Rx Blockwidth Packet Size Packet Channel Channel quadlets Flow Control bytes Throughput Address Address frame y kbit s 0x000E 0x0010 1 Disable 188 1000 Continuous UR Packet Pattern Test okts Counter Type Disable 5000 Enable Rus ounter Table 8 83 mitb 14650 6pin 3072fs i 1q User Manual Copyright O 2011 SMSC Page 172 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 5 13 mitb t4651 6pin 3072fs i 27q 3072xFs test with maximum blockwidth Concurrent Rx and Tx transfer of MediaLB isochronous data Y Blockwidth 2 x 27 quadlet per frame Description Packet size 196 bytes E mitb_t4651_6pin_3072fs_i_27q_cfg_setup txt Manual setup of test via E mitb 14651 307215 i 27q start txt GUI possible ediaLB O Interface Clock Transferred Physical Channel PON Mede Mode Speed Data Types Channel Address 0x01FE PC1 0x000E Isoc Rx PC27 0x000E
230. start txt GUI possible D ediaL B atio Interface Clock Transferred Physical Channel Pan Meze Mode Speed Data Types Channel Address 0x01FE PC1 0x000E Isoc Rx Device 3 Pin 256xFs Isoc PC2 0x0010 Tx PC7 0x0000 DUT eens RS232 Port MediaLB Clock Target Pin Mode Speed Address User 3 Pin 256xFs 0101h configurable isochronous Data Test Tab Tx Rx Blockwidth Packet Size Packet Channel Channel quadlets Flow Control bytes Throughput Address Address frame kbit s 0x000E 0x0010 1 Disable 188 1000 Continuous Pattern Test okts Counter Type Disable 5000 Enable Counter Table 8 72 mitb_t4310_3pin_256fs_i_1q Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 161 MediaLB Interface Test Bench e smsc V2 2 X 8 5 2 mitb t4320 3pin 512fs i 1q Basic 512xFs test Description Concurrent Rx and Tx transfer MediaLB isochronous data Blockwidth 2 x 1 quadlet per frame mitb 14320 512fs i 19 setup txt Manual setup of test via mitb_t4320_3pin_512fs_i_1q_cfg_start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Pori Moste Mode Speed Data Types Channel Address mansir PCO 0x01FE 1 0 000 Isoc Rx Device 3 Pin 512xFs Isoc PC2 0x0010 Isoc Tx PC15 0x0000 DUT DUT MOST RS2
231. sted on the GUI and the loop back function has been enabled Step 3 Execute Test Step 3 1 Click Load Config File button and load start file for selected test case Step 3 2 Wait until number of expected test patterns are generated Step 3 3 Click Stop Test button to hold pattern generation Step 4 Verify Test Results Step 4 1 Check error log of result log and or test status field Step 5 Re run Test To re run the test click the Start Test button and go to Step 3 2 Copyright O 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 63 MediaLB Interface Test Bench e smsc V2 2 X 6 4 Log Files The GUI generates several log files The files store the content of the log windows and are saved in the folder which contains the MITB GUI V02 02 XX exe file If no test configuration file is loaded on the GUI the following log files are created log cfg txt Includes configuration and debug messages log_pga_ctrl txt Includes PGA results and statistics of control data test log pga async txt Includes PGA results and statistics of asynchronous data test log pga sync txt Includes PGA results and statistics of synchronous data test log isoc txt Includes PGA results and statistics of isochronous data test If a configuration file for a specific test case is loaded on the GUI log files incorporating the test name as prefix are created log Includes configuration and de
232. sync Tx PC57 0x0000 DUT DUT MediaLB MOST RS232 Port Target Interface Clock Address Mode Speed User 6 Pin 2048 0101h configurable Asynchronous Data Test Tab Tx Rx Blockwidth MEP MEP Channel Channel quadlets Destination Source Address Address frame Address Address 0x007C 0x007E 5 Disable Varied Fixed Minimum Maximum Length Length Length B brodo de Length bytes bytes bytes Enable 22 1014 Continuous ae Pattern Test Counter Type okts us Disable 5000 2000 Enable Counter Table 8 45 12642 6pin 2048fs a 5q User Manual Copyright O 2011 SMSC Page 130 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 8 3 18 mitb 12643 6pin 2048fs 14 The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is transmitting Async data and the receiving device OS81110 connected to the MDUT is responding with ReceiverBusy responses After the data transfer is started the MITB will generate a series of 20 consecutive ReceiverBusy response periods on the Async Rx Channel ChannelAddress 0x0008 of the OS81110 During each period the OS81110 generates ReceiverBusy responses in every frame on the Async Rx Channel for approximately 2 ms After a delay of 110 ms at which the OS81110 is able to receive data indicated by ReceiverReady respo
233. t PC File Browse Flash File on MITB ISP ML405 Upload Flash Upload Flash Flash INIC 1 Flash INIC 2 Upload Progress Commands DDR RAM Memory Usage Reset FPGA SUCCESS BY DESIGN 1 Flash Memory Usage Delete Flash File Send 2 Figure 5 6 Verify Connection to MITB Platform User Manual Copyright 2011 SMSC Page 40 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 4 Load Pattern Generator amp Analyzer firmware file to MITB platform Open the Browse dialog and select the file to be flashed e g MITB_PGA_V02_02_00 01 srec The firmware file needs to be available in srec format The selected file name must have less than 63 characters Configure PCFlasher to PowerPC Application via the Mode menu Select the Upload check box and click the Upload File button The log window indicates if the selected file has been properly loaded to the MITB platform SEM MMC Ext ClearLog Device IP amp ddress 19 188 0 100 Reconnect Flashing Host PC File Browse j Flash File MITB ISP ML405 MITB PGA 02 01 00 00 Y Upload Flash Upload Flash Upload File Upload Progress M Info Commands DDR RAM Memory Usage Reset FPGA SUCCESS BY DESIGN Flash Memory Usage Delete Flash File E Send Figure 5 7 Load Pattern Generator amp Analy
234. tegrity on the physical layer of the MediaLB interface an oscilloscope may be useful 2 5 User Hardware Requirements Dependent on the type of MITB setup MediaLB Device Setup or MOST150 Device Setup used different requirements apply for the user hardware 2 5 1 MediaLB Device Setup To build up the MITB as MediaLB Device Setup see Figure 2 1 MediaLB Device Setup the user needs to provide the following components and functionality on the user hardware e MediaLB 3 6 Device Under Test MDUT o Connected to Phy Board connector via 3 Pin single ended and or 6 Pin differential MediaLB interface o Must provide loop back functionality required to provide reception and re transmission of test patterns Phy Board connector o Used to connect Phy Board Variant 1 and 3 o Supports single ended MediaLB 3 Pin interface Phy Board Variant 3 o Supports differential MediaLB 6 Pin interface Phy Board Variant 1 o Required to connect MediaLB Analyzer For layout information on the Phy Board connector refer to section 3 6 User Manual Copyright O 2011 SMSC Page 22 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 2 5 2 MOST150 Device Setup If the MOST150 Device Setup is used to verify the proper operation of the MDUT see Figure 2 2 MOST150 Device Setup for details the following components and functionality needs to be implemented on the user hardware e MediaLB
235. test with alternating Tx Rx ChannelAddresses Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 3 quadlet per frame 0 003 amp CA 0x003E mitb_t3333_3pin_1024fs_s_7q 1024xFs test with alternating Tx Rx ChannelAddresses Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 7 quadlet per frame mitb_t3334_3pin_1024fs_s_7q 1024xFs test with alternating Tx Rx ChannelAddresses Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 7 quadlet per frame mitb 13335 Spin 102415 s 154 1024xFs test with high blockwidth Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 15 quadlet per frame MediaLB 6 pin Tests mitb_t3640_6pin_2048fs_s_1q Basic 2048xFs test Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame mitb_t3641_6pin_2048fs_s_15q 2048 xFs test with 2 x 15 quadlets blockwidth Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 15 quadlet per frame mitb_t3642_6pin_2048fs_s_4q 2048xFs test with ChannelAddresses in the upper address range Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 4 quadlet per frame CA 0x0042 amp CA 0x007E Table 8 53 Synchronous Test Overview Part 1 User Manual Copyright O 2011 SMSC Page 142 Document Version V2 2 X Date 2011 12 0
236. the Isochronous Statistic Log are described in the following table Description Isochronous throughput kbit no of packets transmitted TimeWindow Isoc Tx Total Total isochronous throughput k M GBytes of packets transmitted from start of test Isochronous throughput in kbit no of packets received in TimeWindow Isoc Rx Total Total isochronous throughput k M GBytes of packets received from start of test Isoc Missed Total missed isochronous throughput in k M GBytes no of packets Isoc Tx Total Isoc Rx Total Table 6 13 Isochronous Statistics Log User Manual Copyright O 2011 SMSC Page 60 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench smsc V2 2 X 6 2 6 System Commands Tab The following figure shows the system commands tab of the GUI This tab provides the functionality required to generate MediaLB System Commands System Commands Tab Parameters Generate System Command Button bola MiTR MediaLB Interface Test Bench Pattern Generator and Analyzer GUI 2 2 0 Configuration Control Asynchronous Isochronofis System Commands Generate System Commands L MITB GUI V2 2 0 0 System Command MLBReset X No of System Commands 200 dec Generata Cmd Delay System Commands ms Configuration and Debug Messages Clear Log r EN
237. the MITB deliverables and must be purchased separately Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 9 MediaLB Interface Test Bench e smsc V2 2 X 2 Introduction The MediaLB Interface Test Bench MITB represents a hardware platform used to verify the link layer implementation of a MediaLB device Verification is based on the loop back functionality of the MediaLB Device Under Test MDUT and test patterns required to check for a proper implementation Test patterns are generated by the Pattern Generator amp Analyzer PGA software which is an integral part of the MITB For a test the MDUT might be connected to the test bench The PGA generates the test patterns and transmits them over the MediaLB Port to be received by the MDUT The loop back functionality provided on the MDUT needs to facilitate reception and re transmission of the test patterns The re transmitted test patterns are received by the MITB and verified against the transmitted patterns To verify proper operation of a MediaLB device the MITB supports various test modes and parameters including MediaLB port configurations and data types Typical parameters for the port configuration are MediaLB interface mode 3 Pin or 6 Pin MediaLB clock speed 256xFs 512xFs 1024xFs and transferred data types control message data asynchronous packet data synchronous and isochronous data The MITB provides an RS232 interface t
238. tics Green TEST PASSED Test is stopped and passed PGA Results Status The Isoc Results Status Field provides an indication of the PGA test results Field of actually received test patterns The state is indicated by four colors Grey No PGA Results Default state no active test Yellow Test Running Test active and running Red PGA Results NOT OK Test is stopped Test failed with Pattern Errors as indicated in the PGA Results window Green PGA Results OK Test is stopped No pattern errors in received packets detected PGA Statistics The Isoc Statistics Status Field provides an indication of the PGA test Status Field statistics The state is indicated by four colors Grey No PGA Statistics Default state no active test Yellow Test Running Test active and running Red Statistics NOT Test is stopped Test failed with uneven number of transmitted and received packets Green PGA Statistics OK Test is stopped Number of transmitted and received packets equal Table 6 11 Isochronous Tab Parameters User Manual Copyright O 2011 SMSC Page 58 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e lt lt V2 2 X 6 2 5 2 Isochronous Results Log The PGA s Isochronous Results Log displays information about the pattern analyzer s state and provides error indications The information displayed in the Isochronous Results Log is des
239. tion Tab Parameters Part 1 User Manual Copyright 2011 SMSC Page 44 Document Version 2 2 Date 2011 12 09 MediaLB Interface Test Bench e smsc V2 2 X Name Description Initialization RS232 Port Serial COM port of the host PC used for RS232 communication with MITB platform Initialize MITB Button used to initialize MITB with the parameters entered on the Configuration tab Defines the MediaLB interface mode 3 Pin or 6 Pin of the 581110 connected to the MDUT Defines the MediaLB clock speed 256xFs 512xFs of the 0581110 connected to the MDUT MDUT MOST Target Address Defines the MOST target address of the 0581110 connected to the MDUT Load Config File Button to load test configuration files Trigger on Error Check box used to enable disable the generation of events on the trigger connector in case of detected errors Check box is valid for all data types Configuration Debug Messages Check box used to enable disable the visibility of a debug window showing the communication between GUI PGA and the INIC on the user hardware Table 6 2 Configuration Tab Parameters Part 2 6 2 1 2 Configuration and Debug Messages Log The visibility of the Configuration and Debug Messages Log can be enabled and disabled by the Configuration Debug Messages check box on the configuration tab of the GUI The log window displays the messages transferred between the GUI and the PGA as well as the messages exchang
240. ts 1024xFs test with RxBreak Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length45 Bytes Throughput 500 msgs s mitb_t1337_3pin_1024fs_c_1q 1024xFs test with RxProtErr Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes Throughput 500 msgs s mitb_t1338_3pin_1024fs_c_1q 1024xFs test with TxBreak Commands generated by MITB Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes Throughput 500 msgs s MediaLB 6 pin Tests mitb_t1640_6pin_2048fs_c_1q Basic 2048xFs test Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 32 Bytes Throughput 450 msgs s mitb t1641 6pin 2048fs c 14 2048xFs test with RxBusy Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes Throughput 500 msgs s mitb t1642 6pin 2048fs c 1q 2048xFs test with RxBreak Responses generated by MITB Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length45 Bytes Throughput 500 msgs s mitb 11643 6pin 2048fs 14 2048xFs test with RxProtErr Responses generated by MITB Concurre
241. unning on the MITB Platform Status LEDs for o MOST Lock detection o MediaLB Lock detection o Power indication For testing the MediaL B 3 Pin or 6 Pin port of a MDUT different Phy Boards are required MediaLB 3 Pin port testing requires Phy Board Variant 3 27 Phy Board MediaLB 6 Pin port testing requires Phy Board Variant 1 3 Phy Board The requirements for the user hardware realizing a MediaLB device are described in section 2 5 1 Copyright 2011 SMSC User Manual Document Version V2 2 X Date 201 1 12 0902 Page 13 MediaLB Interface Test Bench e smsc V2 2 X 2 1 2 MOST150 Device Setup The following figure outlines the block diagram of the MOST150 Device Setup MediaLB Analyzer Host PC INIC Host PC RS232 Explorer MITB GUI Interface MediaLB Sorte raven Box Monitor Rs232 Header 44 Pin N Ribbon 7 Cable Platform MOST150 Device Dedicated MITB 0881110 E x 5232 XILINX Virtex4 MEE D Test Firmware acr FX60 FPGA LCD 5 PowerPC 2 1 1 prosa H Pattern MediaLB Device 5 Generator amp System Host Bus Interface Macro 2 LEl 0881110 PHY 0581110 4 gt 8
242. up of test via Em mitb 12321 512fs 7q start txt GUI possible DUT MediaLB Configuration Interface Clock Transferred Physical Channel Por Mere Mode Speed Data Type Channel Address Allocated PCO 0x01FE PC1 0x0006 Async Rx Device 3 Pin 512xFs Async PC7 Async Rx PC8 0x0008 Async Tx PC14 0x0008 Async Tx PC15 0x0000 GUI Configuration Configuration Tab DUT DUT MediaLB PUT MOST RS232 Port Target Interface Clock Address Mode Speed aem 3 Pin 512xFs 0101h ono BEIE Rx Blockwidth MEP MEP Channel Channel quadlets MEP Destination Source Address Address frame Address Address 0x0006 0x0008 7 Disable i Varied Fixed Minimum Maximum Repetition Packet Length Length Length bytes E Poem j Length bytes bytes bytes 2 Enable 6 1014 1 3 Test Packet Duration Delay ee Eon pkts us Disable 5000 5200 Enable Random Table 8 29 mitb 12321 3pin 512fs a 7q User Manual Copyright O 2011 SMSC Page 110 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 8 3 4 mitb 12330 1024fs a 14 Basic 1024xFs test Concurrent Rx and Tx transfer of MediaLB asynchronous data Blockwidth 2 x 1 per frame Fixed Packet Length 14 Bytes Packet Delay 2000 us E mitb_t2330_3pin_1024fs_a_1q_cfg_setup txt Manual setup of test via Em mitb 12
243. up txt Manual setup of test via T es mitb 13642 6pin 2048fs s 4q cfg start txt GUI possible D ediaL B Interface Clock Transferred Physical Channel Pori Moce Mode Speed Data Types Channel Address Tensen 0x01FE PC1 0x0042 Sync Rx 4 0x0042 Sync Rx Device 6 Pin 2048xFs Sync 5 0x007E Sync Tx PC8 0x007E Sync Tx PC57 0x0000 DUT Medial DUT MOST RS232 Port MediaLB Clock Target Pin Mode Speed Address User configurable 6 Pin 2048xFs 0101h ono Vata Tx Rx Blockwidth Frame quadlets Address Address frame 0x0042 0x007E 4 Enable Byte Counter Table 8 65 13642 2048fs s 44 User Manual Copyright 2011 SMSC Page 154 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cSnmnsc V2 2 X 8 4 12 mitb t3650 6pin 3072fs s 1q Basic 3072xFs test Concurrent Rx and Tx transfer of MediaLB synchronous data Blockwidth 2 x 1 quadlet per frame Description E mitb_t3650_6pin_3072fs_s_1q_cfg_setup txt Manual setup of test via E mitb 13650 307215 s 1q start txt GUI possible 000 MediaLB Configuration Interface Clock Transferred Physical Channel Par Mede Mode Speed Data Types Channel Address Allocated Een PCO 0x01FE 1 0x000A Sync Rx Device
244. urable Control Data Test Tab Tx Rx Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum Message Length Length Length Length bytes bytes bytes 9 Disable 45 Continuous Test Duration Throughput Message Pattern RxRes Nr RxRes ee Test msgs msgs s Counter yp ms Disable 5000 500 Enable Byte Counter ReceiverProtocolError 5 100 Table 8 17 mitb_t1643_6pin_2048fs_c_1q Copyright 2011 SMSC User Manual Page 97 MediaLB Interface Test Bench e smsc V2 2 X 8 2 15 mitb t1644 6pin 204815 14 The purpose of this test is to verify the correct behavior of the MediaLB DUT in case it is receiving control data and the transmitting device 0581110 connected to the MDUT is sending ControlBreak commands After the data transfer is started the MITB will transmit 240 ControlBreak command on the Control Tx Channel ChannelAddress 0x0004 of the 0581110 ControlBreak commands are generated with a delay of 20 ms between consecutive Contro Breaks The MDUT receiving control messages needs to detect the Contro Break commands Following the detection of the Contro Break the MDUT must stop an ongoing message reception Already received data quadlets are considered to be invalid and should be rejected The user needs to verify manually that the MDUT is properly terminating the message reception Additionally it may be verified if MDUT internally a status indicating the detection
245. width Packet Size Packet Channel Channel quadlets Flow Control bytes Throughput Address Address frame kbit s 0 000 0 0010 1 Disable 188 1000 Continuous Test Packet Pattern Test Counter Type pkts Disable 5000 Enable Caunter Table 8 94 mitb 15331 1024fs casi Part 2 Copyright 2011 SMSC Document Version V2 2 X Date 2011 12 0902 User Manual Page 183 MediaLB Interface Test Bench e SmS V2 2 X 8 6 5 mitb_t5332_3pin_1024fs_casi 1024xFs test 4 data types Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous and isochronous data Blockwidth 2 x 1 quadlet per frame per loopback Fixed packet msg length control 8 bytes asynchronous 14 bytes isochronous 188 bytes Packet Delay 12 000 us Message Throughput 50mgs s 1000 kbit s Test 7 Configuration mitb 15332 3pin 1024fs casi cfg setup txt Manual setup of test via Files mitb 15332 Spin 1024fs casi cfg start txt GUI possible ediaLb O Interface Clock Transferred Physical Channel PON ses Mode Speed Data Types Channel Address eder tarsier PCO 0x01FE PC1 0x0004 Control Tx PC2 0x0002 Control Rx PC3 0x0006 Rx Control 4 0 0008 Device 3 Pin 1024xFs ae 5 0x000A Sync Rx nc Isoc d PC6 0x000C Sync Tx PC7 0x000E Isoc Rx PC8 0x0010 Isoc Tx PC3
246. will not detect any errors Copyright O 2011 SMSC User Manual Document Version V2 2 X Date 2011 12 0902 Page 87 MediaLB Interface Test Bench V2 2 X smsc 1024xFs test with ReceiverProtocolErr responses generated by MITB Concurrent Rx and Tx transfer of MediaLB control data Blockwidth 2 x 1 quadlet per frame Fixed Message Length 45 Bytes Description Throughput 500 msgs s MITB generates 20 ReceiverProtocolError responses on the Control Rx Channel ChannelAddress 0x0002 of the DUT OS81110 ReceiverProtocolError responses generated with a delay of 100 ms between consecutive ReceiverProtocolError C mU Em mitb t1337 1024fs c 1q cfg setup txt Manual setup of test via ee mitb_t1337_3pin_1024fs_c_1q_cfg_start txt GUI possible DUT MediaLB Configuration Interface Transferred Physical Channel Port Mode Clock Speed Data Type channel Aios Allocated Transfer PCO 0x01FE 1 0 0004 Control Tx Device 3 Pin 1024xFs Control PC2 0x0002 Control Rx PC31 0x003E DUT MediaLB DUT MOST RS232 Port Interface Address 3 Pin 1024xFs 0101h Control Data Test Tab Channel Channel Address Address 0x0002 0x0004 Varied Fixed Minimum Maximum ma Message Length Length Length e Length bytes bytes bytes Ja 9 Disable 45 Continuous Te
247. ytes bytes 9 Disable 8 5 gt Conti Test ontinuous Duration Throughput Message Pattern Test msgs msgs s Counter Type Byte Disable 10000 450 Enable Counter Table 8 87 mitb_t5310_3pin_256fs_cas Part 1 User Manual Copyright 2011 SMSC Page 176 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench V2 2 X smsc Basic 256xFs test Test Concurrent Rx and Tx transfer of MediaLB control asynchronous synchronous data Charactenstic Blockwidth 2 x 1 quadlet per frame per data type Fixed Packet Length Control 8 bytes Asynchronous 14 bytes Packet Delay 2000 us message Throughput 450mgs s mitb 15310 Spin 25615 cas setup txt Manual setup of test via EIER 15310 Spin 256fs cas start txt GUI possible GUI Configuration Asynchronous Data Test Tab Tx Rx Blockwidth MEP MEP Channel Channel quadlets Destination Source Address Address frame Address Address 0x0006 0x0008 1 Disable Varied Fixed Minimum Maximum T Packet Length Length Length EO E Length bytes bytes bytes Disable 14 Continuous vesi Parei Packet Pattern Test pkts us Disable 10000 2000 Enable Counter Tx Rx Blockwidth Frame Pattern Channel Channel quadlets Address Address frame counei 0x000A 0x000C 1 Enable Co nter Table
248. zer Firmware MITB Platform 5 Flash Pattern Generator amp Analyzer firmware MITB Platform Select the Flash check box and click the Flash Board button Do not interrupt flash process Flashing of the firmware will take several seconds The log window indicates if the selected file has been properly flashed Ext ClearLog Device IP Address 19 168 0 100 Reconnect Flashing Host PC File 2 ts Brown Flash File on MITB ISP ML405 Upload Flash Upload Flash Flash INIC 1 Flash INIC 2 Flash Progress Info Commands DDR RAM Memory Usage Reset FPG SUCCESS BY DESIGN ik Flash Memory Usage Delete Flash File Send Figure 5 8 Flash Pattern Generator amp Analyzer to MITB Platform Copyright 2011 SMSC User Manual Document Version 2 2 Date 2011 12 0902 Page 41 MediaLB Interface Test Bench e smsc V2 2 X 6 Run Pattern Generator amp Analyzer Power up MITB platform Do not press any button Flashed Pattern Generator amp Analyzer will be loaded The version of the flashed Pattern Generator amp Analyzer is indicated on the LCD display next to the user buttons User Manual Copyright O 2011 SMSC Page 42 Document Version V2 2 X Date 2011 12 09 MediaLB Interface Test Bench e cnmnsc V2 2 X 6 Configure the Test Bench To verify the proper implementation of an MDUT it is required to configure the MITB and the generated

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