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MIPS32® 4K™ Processor Core Family Software User`s Manual

1. If this bit is set watch exceptions are enabled for 0 for Cold instruction fetches that match the address Reset only If this bit is set watch exceptions are enabled for loads that 0 for Cold match the address Reset only w 0 If this bit is set watch exceptions are enabled for stores that R W 0 for Cold match the address Reset only 100 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 19 WatchHi Register CPO Register 19 The WatchLo and WatchHi registers together provide the interface to a watchpoint debug facility that initiates a watch exception if an instruction or data access matches the address specified in the registers As such they duplicate some functions of the EJTAG debug solution Watch exceptions are taken only if the EXL and ERL bits are zero in the Status register If either bit is a one the WP bit is set in the Cause register and the watch exception is deferred until both the EXL and ERL bits are zero The WatchHi register contains information that qualifies the virtual address specified in the WatchLo register an ASID a Global G bit and an optional address mask If the G bit is 1 any virtual address reference that matches the specified address will cause a watch exception If the G bit is a 0 only those virtual address references for which the ASID value in the WatchHi register m
2. 188 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Table 11 13 Values of the hint Field for the PREF Instruction 8 24 Reserved Reserved treated as a NOP oe writeback_invalidate Use Data is no longer expected to be used also known as nudge Treated as a NOP 26 29 Deedee Reserved treated as a NOP Use Prepare the cache for writing an entire line without the 30 PrepareForStore overhead involved in filling the line from memory Reserved treated as a NOP 31 bee Reserved treated as a NOP MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 189 Chapter 11 MIPS32 4K Processor Core Instructions Prefetch cont PREF 190 Restrictions None Operation vAddr GPR base sign_extend offset pAddr CCA lt AddressTranslation vAddr DATA LOAD Prefetch CCA pAddr vAddr DATA hint Exceptions Prefetch does not take any TLB related or address related exceptions under any circumstances Programming Notes Prefetch cannot prefetch data from a mapped location unless the translation for that location is present in the TLB Locations in memory pages that have not been accessed recently may not have translations in the TLB so prefetch may not be ef
3. Operation Type of Usage of Effective Address Requires an Cache The effective address is translated by the MMU to a physical address The physical ae Physical address is then used to address the cache The effective address is translated by the MMU to a physical address It is implementation dependent whether the effective address or the translated physical address is used to index the cache Assuming that the total cache size in bytes is CS the associativity is A and the number of bytes per tag is BPT the following calculations give the fields of the address which specify the way and the index Index N A OffsetBit lt Log2 BPT IndexBit lt Log2 CS A WayBit lt IndexBit Ceiling Log2 A Way amp Addrwaypit 1 IndexBit Index amp Addrindexpit 1 0ffsetBit For a direct mapped cache the Way calculation is ignored and the Index value fully specifies the cache tag This is shown symbolically in the figure below MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 177 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 11 MIPS32 4K Processor Core Instructions Perform Cache Operation CACHE Figure 11 1 Usage of Address Fields to Select Index and Way WayBit IndexBit OffsetBit ia aa 0 A TLB Refill and TLB Invalid both with cause code equal TLBL exception can occur on any operation For index operations where the address is used to index the cache but need not matc
4. The S _EXL signal represents the state of the EXL bit 1 in the CPO Status register The S _ERL signal represents the state of the ERL bit 2 in the CPO Status register e The EJ_DebugM signal indicates that the processor has entered debug mode MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 119 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 8 Power Management 8 2 Instruction Controlled Power Management The second mechanism for invoking power down mode is through execution of the WAIT instruction If the bus is idle at the time the WAIT instruction reaches the M stage of the pipeline the internal clocks are suspended and the pipeline is frozen However the internal timer and some of the input pins SZ _Int 5 0 SI_NMI SI_Reset SI_ColdReset and EJ_DINT continue to run If the bus is not idle at the time the WAIT instruction reaches the M stage the pipeline stalls until the bus becomes idle at which time the clocks are stopped Once the CPU is in instruction controlled power management mode any enabled interrupt NMI debug interrupt or reset condition causes the CPU to exit this mode and resume normal operation While the part is in this low power mode the SZ _SLEEP signal is asserted to indicate to external agents what the state of the chip is 120 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies
5. The core also supports a data cache locking mechanism identical to the instruction cache Critical data segments to be locked into the cache on a per line basis The locked contents can be updated on a store hit but cannot be selected for replacement on a miss The cache locking function is always enabled on all data cache entries Entries can then be marked as locked or unlocked on a per entry basis using the CACHE instruction 7 5 Memory Coherence Issues 118 A cache presents coherency issues within the memory hierarchy which must be considered in the system design Since a cache holds a copy of memory data it is possible for another memory master to modify a memory location thus making other copies of that location stale if those copies are still in use A detailed discussion of memory coherence is beyond the scope of this document but following are a few related comments A 4K processor contains no direct hardware support for managing coherency with respect to its caches so it must be handled via system design or software The 4K caches are write through so all data writes will eventually be sent to memory Due to write buffers however there could be a delay in how long it takes for the write to memory to actually occur If another memory master updates cacheable memory which could also be in the 4K caches then those locations may need to be flushed from the cache The only way to accomplish this invalidation is by use of the C
6. Computational instructions perform the following operations on register values Arithmetic Logical Shift Multiply Divide These operations fit in the following four categories of computational instructions ALU Immediate instructions Three operand Register type Instructions Shift Instructions Multiply And Divide Instructions 10 3 1 Cycle Timing for Multiply and Divide Instructions Any multiply instruction in the integer pipeline is transferred to the multiplier as remaining instructions continue through the pipeline the product of the multiply instruction is saved in the HI and LO registers If the multiply instruction is MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 165 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 10 Instruction Set Overview followed by an MFHI or MFLO before the product is available the pipeline interlocks until this product does become available Refer to Chapter 2 Pipeline for more information on instruction latency and repeat rates 10 4 Jump and Branch Instructions Jump and branch instructions change the control flow of a program All jump and branch instructions occur with a delay of one instruction that is the instruction immediately following the jump or branch this is known as the instruction in the delay slot always executes while the target instruction is being fetched from storage 10 4
7. If both data breakpoints without and with data value compare would match the same transaction and generate a debug exception then the following rules apply with respect to updating the BS n bits e On both a load and store the BS n bits are required to be set for all matching breakpoints without data value compare e Ona store then BS n bits are allowed but not required to be set for all matching breakpoints with data value compare but either all or none of the BS n bits must be set for these breakpoints e On a load then no of the BS n bits are allowed to be set since the load is not allowed to occur due to the debug exception from a breakpoint without data value compare and a valid data value is therefore not returned Any BS n bit set prior to the match and debug exception are kept set since BS n bits are only cleared by debug software The debug handler usually returns to the instruction causing the debug data break exception whereby the instruction is re executed This re execution may result in a repeated load from system memory since the load may have occurred previously in order to evaluate the breakpoint as described above I O devices with side effects on load must be able to MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints allow such reloads or debug software should alternatively avoid set
8. amp 4Kp processor cores The three products are similar in design hence the majority of information contained in this manual refers to all three cores Throughout this manual the terms the core or the processor refers to the 4Kc 4Km and 4Kp devices Some information in this manual specifically in Chapters 2 and 4 is specific to one or more of the cores but not all three This information is called out in the text wherever necessary For example the section dealing with the TLB is denoted as being 4Kc core specific whereas the section dealing with the BAT is denoted as being 4Kkm and 4Kp core specific Product Differentiation The three products contained in this manual are similar in design The main differences are in memory management and the multiply divide unit In general the differences are as follows 4Kc processor Contains pipelined multiplier and translation lookaside buffer TLB 4Km processor Contains pipelined multiplier and block address translator BAT 4Kp processor Contains non pipelined multiplier and block address translator BAT MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 iii Copyright 2000 2002 MIPS Technologies Inc All rights reserved Table of Contents Chapter 1 Introduction to the MIPS32 4K Processor Core Family o ccc eceecesceeseessececeseceecseesecseeseceseeseceeeeeeseneeaaeeneeags 1 Leb Re atures iiaia a M
9. int Rt DIN Divide HI int Rs int Rt i LO uns Rs uns Rt DIVU Unsigned Divide HI uns Rs uns Rt if SR 2 PC ErrorEPC else ERET Return from Exception PC EPC SR 1 0 SR 2 0 LL 0 J Unconditional Jump PC PC 31 28 Il offset lt lt 2 GPR 31 PC 8 JAL Jump and Link PC PC 31 28 Il offset lt lt 2 Rd PC 8 JALR Jump and Link Register PC Rs JR Jump Register PC Rs LB Load Byte Rt byte Mem Rs offset LBU Unsigned Load Byte Rt ubyte Mem Rs offset LH Load Halfword Rt half Mem Rs offset LHU Unsigned Load Halfword Rt uhalf Mem Rs offset Rt Mem Rs offset LL Load Linked Word LL 1 LLAdr Rs offset LUI Load Upper Immediate Rt immediate lt lt 16 LW Load Word Rt Mem Rs offset LWL Load Word Left Refer to Architecture Reference Manual LWR Load Word Right Refer to Architecture Reference Manual MADD Multiply Add HI LO int Rs int Rt MADDU Multiply Add Unsigned HI LO uns Rs uns Rt MFCO Move From Coprocessor 0 Rt CPR O n sel Rt MFHI Move From HI Rd HI MFLO Move From LO Rd LO ae if GPR rt 4 0 then MOVN Move Conditional on Not Zero GPR rd lt GPR rs MOVZ Move Conditional on Zero open Se MSUB Multiply Subtract HI LO int Rs int Rt MSUBU Multiply Subtract Unsigned HI LO uns Rs uns Rt MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 173 Chap
10. It is possible to set instruction breakpoints on addresses even in ROM area and set data breakpoints to cause a debug exception on a specific data transaction Instruction and data hardware breakpoints are alike for may aspects and are thus described in parallel in the following The term hardware is not applied to breakpoint unless required to distinguish it from software breakpoint There are two types of simple hardware breakpoints implemented in the 4K cores Instruction breakpoints and Data breakpoints Each core can be configured with the following breakpoint options e No data or instruction breakpoints e Two instruction and one data breakpoint e Four instruction and two data breakpoints 9 2 1 Features of Instruction Breakpoint Instruction breaks occur on instruction fetch operations and the break is set on the virtual address on the bus between the CPU and the instruction cache Instruction breaks can also be made on the ASID value used by the MMU 4Kc core only Finally a mask can be applied to the virtual address to set breakpoints on a range of instructions Instruction breakpoints compare the virtual address of the executed instructions PC and the ASID with the registers for each instruction breakpoint including masking of address and ASID An overview is shown in Figure 9 1 and Figure 9 2 Instruction Debug Exception Hardware Breakpoint Trigger Indication gt Figure 9 1 Instruction Hardware Breakpo
11. Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers Table 5 22 Config Register Field Descriptions Select 1 Continued Description Reset State This field contains the data cache line size If a data cache is present it must contain a line size of 16 bytes 0x0 No Deache present 0x3 16 bytes 0x1 0x2 0x4 0x7 Reserved This field contains the type of set associativity for the data cache 0x0 Direct mapped Ox1 2 way 0x2 3 way 0x3 4 way 0x4 0x7 Reserved HHLA Must be written as zero returns zero on read Performance Counter registers implemented Always a 0 since the cores do not implement any Watch registers implemented This bit always reads as 1 since the cores each contain one pair of Watch registers Code compression MIPS16 implemented This bit always reads as 0 because MIPS16 is not supported EJTAG present This bit is always set to indicate that the ai f core implements EJTAG FPU implemented This bit is always zero since the core FP 0 gt R 0 does not contain a floating point unit 5 2 17 Load Linked Address CP0 Register 17 Select 0 The LLAddr register contains the physical address read by the most recent Load Linked LL instruction This register is for diagnostic purposes only and serves no function during normal operation LLAdar Regis
12. TLB 0 Refer to Table 5 21 for the field encoding This field indicates the presence of an I side scratchpad 24 RAM R 23 This field indicates the presence of a D side scratchpad R RAM FM 010 TLB 000 Preset Preset 22 Must be written as 0 Returns 0 on read 0 SB Indicates whether SimpleBE bus mode is enabled Set via SI_SimpleBE 0 input pin 0 No reserved byte enables on EC interface 1 Only simple byte enables allowed on EC interface Externally Set MDU This bit indicates the MDU type 0 Fast Multiplier Array 4Kc and 4Km cores 1 Iterative multiplier 4Kp cores 19 Must be written as 0 Returns 0 on read 0 Preset MM This field contains the merge mode for the 32 byte collapsing write buffer 18 17 00 No Merging R 01 SysAD Valid merging 10 Full merging 11 Reserved Externally Set MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 95 Chapter 5 CPO Registers 96 Table 5 20 Config Register Field Descriptions Continued Read Description Write Reset State Burst order 0 Sequential R Externally Set 1 SubBlock Indicates the endian mode in which the processor is running R Externally Set 0 Little endian 1 Big endian Architecture type implemented by the processor This field R 00 is always 00 to indicate MIPS32 A
13. 11 3 Instruction Set Load Linked Word cont LL Exceptions TLB Refill TLB Invalid Address Error Reserved Instruction Programming Notes There is no Load Linked Word Unsigned operation corresponding to Load Word Unsigned MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 185 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 11 MIPS32 4K Processor Core Instructions Prefetch PREF 31 26 25 21 20 16 15 0 PREF base hint offset 110011 6 5 5 16 Format PREF hint offset base MIPS32 Purpose 186 To move data between memory and cache Description prefetch_memory base offset PREF adds the 16 bit signed offset to the contents of GPR base to form an effective byte address The hint field sup plies information about the way that the data is expected to be used PREF is an advisory instruction that may change the performance of the program However for all hint values and all effective addresses it neither changes the architecturally visible state nor does it alter the meaning of the program PREF does not cause addressing related exceptions If the address specified would cause an addressing exception the exception condition is ignored and no data movement occurs However even if no data is prefetched some action that is not architecturally visible such as writeback of a dirty cache line can take place PREF never generates a memory op
14. 3 7 94 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 15 Config Register CPO Register 16 Select 0 The Config register specifies various configuration and capabilities information Most of the fields in the Config register are initialized by hardware during the Reset exception process or are constant One field KO must be initialized by software in the Reset exception handler Config Register Format Select 0 3130 2827 25 24 23 2221 20 19 1817 16 15 14 13 12 10 9 7 6 M K23 KU ISP DSP 0 SB MDU R MM BM BE AT AR MT Name Fields Table 5 20 Config Register Field Descriptions Read Description Write Reset State K23 This bit is hardwired to 1 to indicate the presence of the R Config register This field controls the cacheability of the kseg2 and kseg3 address segments in FM implementations This field is FM R W valid in the 4Kp and 4Km processor and is reserved in the 4Kc processor must be written as 0 returns 0 on read TLB 0 Refer to Table 5 21 for the field encoding FM 010 TLB 000 KU ISP DSP This field controls the cacheability of the kuseg and useg address segments in FM implementations This field is FM R W valid in the 4Kp and 4Km processor and is reserved in the i 4Kc processor must be written as 0 returns 0 on read
15. 4 6 11 TLB Refill Exception Instruction Fetch or Data Access 4Kc core During an instruction fetch or data access a TLB refill exception occurs when no TLB entry in a TLB based MMU matches a reference to a mapped address space and the EXL bit is 0 in the Status register Note that this is distinct from the case in which an entry matches but has the valid bit off In that case a TLB Invalid exception occurs Cause Register ExcCode Value TLBL Reference was a load or an instruction fetch TLBS Reference was a store Additional State Saved Table 4 9 CPO Register States on a TLB Refill Exception Register State Value BadVAddr failing address The BadVPN2 fields contains VA3 3 of the failing Context address The VPN2 field contains VA31 13 of the failing address EntryHi the ASID field contains the ASID of the reference that missed EntryLo0 UNPREDICTABLE EntryLol UNPREDICTABLE Entry Vector Used TLB refill vector offset 0x000 if Statuspyx 0 at the time of exception general exception vector offset 0x 180 if Statusgx 1 at the time of exception 62 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 6 Exceptions 4 6 12 TLB Invalid Exception Instruction Fetch or Data Access 4Kc core During an instruction fetch or data access a TLB invalid exception occurs in one of the foll
16. Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 11 Instruction Interlocks Figure 2 23 shows a diagram of a two cycle slip In the first clock cycle the pipeline is full and the cache miss is detected Instruction I0 is in the A stage instruction I1 is in the M stage instruction I2 is in the E stage and instruction I3 is in the I stage The cache miss occurs in clock 2 when the I4 instruction fetch is attempted I4 advances to the E stage and waits for the instruction to be fetched from main memory In this example it takes two clocks 3 and 4 to fetch the 14 instruction from memory Once the cache miss is resolved in clock 4 and the instruction is bypassed to the cache the pipeline is restarted causing the I4 instruction to finally execute it s E stage operations 2 11 Instruction Interlocks Most instructions can be issued at a rate of one per clock cycle In some cases in order to ensure a sequential programming model the issue of an instruction is delayed to ensure that the results of a prior instruction will be available Table 2 5 details the instruction interactions that delay the issuance of an instruction into the processor pipeline Table 2 5 Instruction Interlocks Instruction Interlocks Issue Delay in First Instruction Second Instruction Clock Cycles Slip Stage LB LBU LH LHU LL LW LWL LWR Consumer of load data 1 E stage MFCO aa of destinatio
17. Executed as a no op MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 179 Chapter 11 MIPS32 4K Processor Core Instructions Table 11 10 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl WST SPR Cleared Effective Address Operand Type Operation Implemented Hit Invalidate If the cache block contains the specified address set the state of the cache block to invalid This encoding may be used by software to invalidate a range of addresses from the instruction cache by stepping through the address range by the line size of the cache Address Fill the cache from the specified address The cache line is refetched even if it is already in the cache Hit Invalidate Address Reserved Reserved Address If the cache block contains the specified address set the state of the cache block to invalid This encoding may be used by software to invalidate a range of addresses from the data cache by stepping through the address range by the line size of the cache Executed as a no op 180 Fetch and Lock MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 If the cache does not contain the entire line at the specified address it is fetched from memory and the state is set to locked If the cache already contains the line set the stat
18. If the Reset State of this field is Undefined software must write this field with zero before it is guaranteed to read as zero MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 75 Chapter 5 CPO Registers 5 2 1 Index Register CPO Register 0 Select 0 The Index register is a 32 bit read write register that contains the index used to access the TLB for TLBP TLBR and TLBWI instructions The width of the index field is implementation dependent as a function of the number of TLB entries that are implemented The minimum value for TLB based MMUs is Ceiling Log gt TLBEntries The operation of the processor is UNDEFINED if a value greater than or equal to the number of TLB entries is written to the Index register This register is only valid with the TLB 4Kc core It is reserved if the FM is implemented 4Km and 4Kp Index Register Format 31 30 4 3 0 P 0 Index Table 5 3 Index Register Field Descriptions Fields Description Reset State Probe Failure Set to 1 when the previous TLBProbe Undefined TLBP instruction failed to find a match in the TLB Must be written as zero returns zero on read Index to the TLB entry affected by the TLBRead and TLBWrite instructions Undefined 76 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MI
19. Processor Core Family Software User s Manual Revision 01 18 151 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support Table 9 21 Device Identification Register Fields Name Description Reset State Version 4 bits Version This field identifies the version number of the EJ_Version 3 0 processor derivative Part Number 16 bits PartNumber This field identifies the part number of the processor EJ_PartNumber 15 0 derivative Manufacturer Identity 11 bits ManufID Accordingly to IEEE 1149 1 1990 the manufacturer EJ_ManufID 10 0 identity code shall be a compressed form of the JEDEC Publications 106 A R 0 reserved 1 9 4 2 3 Implementation Register This 32 bit read only register is used to identify the features of the EJTAG implementation Some of the reset value are set by inputs to the core The register is selected when the Instruction register is loaded with the IMPCODE instruction 31 29 28 Fields 25 24 23 Table 9 22 Implementation Register Descriptions Implementation Register Format 21 20 15 13 Description Reset State EJTAGver EJTAG Version 1 Version 2 5 core revisions before 3 5 2 Version 2 6 core revisions 3 5 and later Preset reserved DINTsup reserved DINT Signal Supported from Probe This bit indicates if the DINT signal from the probe is supported 0 DINT signal from the probe is not supported
20. Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 93 Chapter 5 CPO Registers 5 2 14 Processor Identification CP0 Register 15 Select 0 The Processor Identification PRId register is a 32 bit read only register that contains information identifying the manufacturer manufacturer options processor identification and revision level of the processor PRid Register Format 31 24 23 16 15 8 7 0 R Company ID Processor ID Revision Table 5 19 PRId Register Field Descriptions Fields poo Read Name Bit s Description Write Reset State R 31 24 Reserved Must be ignored on write and read as zero R 0 Combat Identifies the company that designed or manufactured the ie y 23 16 processor In all three cores this field contains a value of R 1 1 to indicate MIPS Technologies Inc Identifies the type of processor This field allows software 4Kc Processor to distinguish between the various types of MIPS core 0x80 ID 15 8 Technologies processors This field contains a value of R 0x80 for the 4Kc processor The value is 0x83 for the 4Kp 4Km amp 4Kp and 4Km processors cores 0x83 Specifies the revision number of the processor This field allows software to distinguish between one revision and another of the same processor type Current values 0x1 1 1 2 2 0x2 2 3 2 4 0x3 2 5 2 6 Revision 7 0 0x4 3 0 R Preset 0x5 3 1 0x6 3 2 0x7 3 3 0x8 3 4 0x9 3 5 Oxa 3 6 Oxb
21. Virtually indexed physically tagged Cache line locking support Non blocking prefetches e ScratchPad RAM support Replace one way of I Cache and or D Cache Max 20 bit index 1M address Memory mapped registers attached to scratchpad port can be used as a co processor interface e R4000 Style Privileged Resource Architecture Count compare registers for real time timer interrupts Instruction and data watch registers for software breakpoints Separate interrupt exception vector e Programmable Memory Management Unit 4Kc core only 16 dual entry R4000 style JTLB with variable page sizes 3 entry instruction TLB 3 entry data TLB 2 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 1 2 Block Diagram e Programmable Memory Management Unit 4Km and 4Kp cores only fixed mapping no JTLB ITLB or DTLB Address spaces mapped using register bits e Simple Bus Interface Unit BIU All I Os fully registered Separate unidirectional 32 bit address and data buses Two 16 byte collapsing write buffers e Multiply Divide Unit 4Kc and 4Km cores Max issue rate of one 32x16 multiply per clock Max issue rate of one 32x32 multiply every other clock Early in divide control Minimum 11 maximum 34 clock latency on divide e Multiply Divide Unit 4Kp cores Iterative multiply and divide 32 or
22. ac ssscisscesse aes sceecs pees O aE os sesh costs aper E o AE eves ees SECES NE E OERE EASE NENES PA EN EE DESSES 23 Figure 2 19 IU Pipeline Data Bypass eee nsee ee eae ersen ee AE o oea Ka a Ier S EET osen oua en oie T Iae eUe Erare 24 Figur 2 20 LU Pipeline M t E bDypaS Srs seit eee e A N E E E ae E EE SEa S AER S 24 Figure 2 21 IU Pipeline A to E Data Bypass sessessseesseresessssesersrerrsreerssrsrsstssestesertrsretnsentestetesteestrsrersrentesentestesesreseeers 25 Fig re 2 22 IU Pipeline Slip after MPH e e aar e aaa csove sotancsecblsugeese puasveeseceutesvactes svasshessh conse testes scbaee dee ats 25 Figure 2 23 Instruction Cache Miss Slip isi e e e a o TE E E aT eea Oie eSEE EAE eE ET INES 26 Figure 3 1 Address Translation During a Cache Access in the 4K Core eesssseesesseeeseseersseerrsresesrrererrsseereseresrnsesreseeees 32 Figure 3 2 Address Translation During a Cache Access in the 4Km and 4Kp cores ssesessseesesseerseereessrereserrrseesesreeeeers 32 Figure 3 3 4K Processor Core Virtual Memory Map 0 ccccesceessesseecceseeeeecseeceecacesaecaaesaecaeceseceecseseeeaeseaseseseeecnaseaesaee 34 Figure 3 4 User Mode Virtual Address Space o cceeececeseeesceseeseceseessceseeesecaeecaecaeesaecsaesaecaecaseceeeseseeeseseaseaeseaecaaeeneeaee 35 Figure 3 5 Kernel Mode Virtual Address Space neresine ieor en E E EE ra SERENE EES 37 Figure 3 6 Debug Mode Virtual Address Space 00 0 eeeeccesseesceseeeeces
23. as a second divide can be in the RS Adjust stage when the first divide is in the Reg WR stage Clock Clock Clock Clock 1 2 3 4 10 11 12 13 Estage P E Mupu Stage P Mupu Stage P Mupu Stage lt Mupu Stage P Ampu Stage Pl Wunu Stage Lo LI LI LI LI LI LI RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust Reg WR Early In Figure 2 11 MDU Pipeline Flow During an 8 bit Divide DIV Operation 1 2 3 4 18 19 20 21 Estage PE Munu Stage P Mupu Stage Mapu Stage Muu Stage P Ampu Stage P Wo Stage P PP ea ee ey Te td RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust Early In Figure 2 12 MDU Pipeline Flow During a 16 bit Divide DIV Operation 1 2 3 4 26 27 28 29 e E Stage gt je Mmpu Stage gt lt Mmpu Stage gt Mmpu Stage gt Mmpu Stage gt Ampu Stage gt Wmpu Stage gt RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust Reg WR Figure 2 13 MDU Pipeline Flow During a 24 bit Divide DIV Operation 1 2 3 4 34 35 36 37 J Estage P E Mupu Stage P Mupu Stage P Mapu Stage lt Munu Stage P Ampu Stage P Wunu Stage P RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust Early In Figure 2 14 MDU Pipeline Flow During a 32 bit Divide DIV Operation Reg WR MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technolo
24. at the debug exception vector 55 Chapter 4 Exceptions The value loaded into DEPC represents the restart address for the debug exception and need not be modified by the debug exception handler software in the usual case Debug software need not look at the DBD bit in the Debug register unless it wishes to identify the address of the instruction that actually caused the debug exception A unique debug exception is indicated through the DSS DBp DDBL DDBS DIB and DINT bits D bits at 5 0 in the Debug register No other CPO registers or fields are changed due to the debug exception thus no additional state is saved Operation if InstructionInBranchDelaySlot then DEPC lt PC 4 Debugpgp lt 1 else DEPC lt PC Debugpgp lt 0 endif Debugp pits at at 5 0 lt 7 DebugExceptionType Debugya t lt HaltStatusAtDebugException Debugpoze lt DozeStatusAtDebugException Debugpy lt 1 iE EJTAGControlRegisterprobTrap 1 then PC lt OxFF20_0200 else PC lt OxBFCO0_0480 endif The same debug exception vector location is used for all debug exceptions The location is determined by the ProbTrap bit in the EJTAG Control register ECR as shown in Table 4 5 Table 4 5 Debug Exception Vector Addresses ProbTrap bit in ECR Register Debug Exception Vector Address 0 OxBFCO_0480 1 OxFF20_0200 in dmseg 4 6 Exceptions 56 The following subsections describe each of the exceptions listed in th
25. buffer TLB in the case of the 4Kc core or a fixed mapping FM in the case of the 4Km and 4Kp cores Refer to Chapter 3 Memory Management on page 31 for more information Off Chip MD l h zm Cache TAP 7 Debug I F D Execution A g Core l MMU Cache a RF ALU Shift Controller aa e 9 6 System Mgmt Fixed Required Optional Figure 1 1 4K Processor Core Block Diagram 1 3 Required Logic Blocks The following subsections describe the various required logic blocks of the 4K processor cores 1 3 1 Execution Unit The core execution unit implements a load store architecture with single cycle Arithmetic Logic Unit ALU operations logical shift add subtract and an autonomous multiply divide unit The core contains thirty two 32 bit general purpose registers used for scalar integer operations and address calculation The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline The execution unit includes 32 bit adder used for calculating the data address Address unit for calculating the next instruction address Logic for branch determination and branch target address calculation Load aligner Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results Zero One detect unit for impleme
26. 1 Probe can use DINT signal to make debug interrupt EJ_DINTsup Size of ASID field in implementation 4Kc core 2 0 No ASID in implementation 4Km 4Kp cores ASIDsize 1 6 bit ASID 4Km 4Kp 2 8 bit ASID 4Kc core cores 0 3 Reserved reserved 20 15 reserved 0 NoDMA 14 No EJTAG DMA Support 1 152 0 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 4 EJTAG TAP Registers Table 9 22 Implementation Register Descriptions Read Description Write Reset State reserved 1 Eg 0 reserved 9 4 2 4 EJTAG Control Register This 32 bit register controls the various operations of the TAP modules This register is selected by shifting in the CONTROL instruction Bits in the EJTAG Control register can be set cleared by shifting in data status is read by shifting out the contents of this register This EJTAG Control register can only be accessed by the TAP interface The EJTAG Control register is not updated in the Update DR state unless the Reset occurred Rocce bit 31 is either 0 or written to 0 This is in order to ensure prober handling of processor accesses The value used for reset indicated in the table below takes effect on both hard and soft CPU reset but no on TAP controller reset by e g TRST_N TCK clock is not required when the hard or soft CPU reset occurs but the bits are still updated to
27. 1 Wired and Random Entries in the TLB ss essesesssssseseeeresrsreerssesrssrssesreserresrernrentesreresteesrrsrerrsreetesrntesresesreseeees 82 Figure 7 1Cache Array POA S eese eves ave eE EEEE SPEE EEEo ipes gus o EEE O ves tues seuss eves apace te seus cdoubsoras eee iden 116 Figure 9 1 Instruction Hardware Breakpoint Overview 4K Corfe ccc eecesecseceseeseceseeseceseeeeeeseeeseaeeeeecaeesaecasenseenees 124 Figure 9 2 Instruction Hardware Breakpoint Overview 4Km and 4Kp Core cccceseescesceesceeeeeeeeseeeeecaeessecseesaeenees 124 Figure 9 3 Data Hardware Breakpoint Overview 4Kc Core ececesceesessecsecssecsecesceseceseesecesceseceeseseeeaeecaecaessaecaeenaeenees 125 Figure 9 4 Data Hardware Breakpoint Overview 4Km 4Kp Core eee ceeesecseceecneceseeseceseeseeeeeeeeseseeeeecaeeenecaeeaeenees 125 Figure 9 5 TAP Controller State Diagrams nissene osiin soian erie aE eip E EEK E Eeo oe eoten aO Ka eSEE ENE Se ES 146 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All right reserved Figure 9 6 Concatenation of the EJTAG Address Data and Control Registers 20 0 0 eee eceeceeeeeeeeseeeeecaeeeaeeeeeaeenees 150 Figure 9 7 TDI to TDO Path when in Shift DR State and FASTDATA Instruction is Selected 00 eee 150 Figure 9 8 Endian Formats for the PAD Register ee ce eeeeeceeeeeeeeeesecoeecneceaesaecsacsaecsseesecseseeceaeeaeeaeeeaecaeesae
28. 1 Fetch Load and Store from to the EJTAG Probe through dmseg ou eee eeeeessesecsecreeeceseceeeeceecsaeeeseeeeeens 160 Chapter 10 Tnstr cton Set OVervie W heretter preen e aE NE EEE sores stash O aE ab Sones rede g eee eae ER ESEE R one 163 10 1 CPU Instruction Formats same E a Ee Eaa actos ees S ee ee RU ee eas 163 10 2 Load and Store INStrUCtlONS isisi e E a EEEE EESE N E E AEE AE RE EA N 164 10 2 1 Scheduling a Load Delay Slot ss eseseeseserseseeerererereererereresserersrereseerensrerusesserererueeererersreensrerererserersrerereeeere 164 OAA Di AAE A D E EEEE E EE E E E E E E A EEEE 164 10 3 Computational Instructions oo cece eee ea e e E E E aE a o E a E EEEE EKE 165 10 3 1 Cycle Timing for Multiply and Divide Instructions sessesseeessesesesresessssesresreresresrssrsresrnerresenrenreneereeees 165 10 4 Jump and Branch Instructions o eeceeeeeeeeecceseeeeceseeeeecaeecsecacesaecsacsaecsecssecsecsesseeeseseeseseseaeeseseaecseesaesaaeasensenaes 166 104 1 Overview of J mp INStru CONS e re ee oe e e areren pees i apenes so oe saben tues SEIE cpteoep ousth E Epen S Eo popie ls 166 10 4 2 Overview of Branch Instructions oo cece csesececesseceeceseceeceseeecseeeeseseseaeeseecaecaaecaecaeaecesesseseseeeeeees 166 10 5 Control InstrU Ct OMs iee reie canbe exe an Wieder A E E E aaa sees auton eed ease E N E ERN 166 10 6 Coprocessor Instructions ea p e Gh A ROG he eee EE E eeepc teu elie nl SR 166 10 7 Enhancements to the MIPS Arch
29. 101 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 20 Debug Register CPO Register 23 The Debug register is used to control the debug exception and provide information about the cause of the debug exception and when re entering at the debug exception vector due to a normal exception in debug mode The read only information bits are updated every time the debug exception is taken or when a normal exception is taken when already in debug mode Only the DM bit and the EJTAGver field are valid when read from non debug mode the value of all other bits and fields is UNPREDICTABLE Operation of the processor is UNDEFINED if the Debug register is written from non debug mode Some of the bits and fields are only updated on debug exceptions and or exceptions in debug mode as shown below e DSS DBp DDBL DDBS DIB DINT are updated on both debug exceptions and on exceptions in debug modes e DExcCode is updated on exceptions in debug mode and is undefined after a debug exception e Halt and Doze are updated on a debug exception and is undefined after an exception in debug mode e DBD is updated on both debug and on exceptions in debug modes All bits and fields are undefined when read from normal mode except those explicitly described to be defined e g EJTAGver and DM Debug Register Format 31 30 29 28 27 26 25 24 23 22 21 20 19 DBD DM NoDCR LSNM Doze Halt Co
30. 178 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Perform Cache Operation CACHE Table 11 10 Encoding of Bits 20 18 of the CACHE Instruction ErrCtlI WST SPR Cleared Code Caches Name Effective Address Operand Type Operation Implemented Index Invalidate Index Invalidate Reserved Index Load Tag Index Store Tag Reserved Unspecified Set the state of the cache block at the specified index to invalid This encoding may be used by software to invalidate the entire instruction cache by stepping through all valid indices Set the state of the cache block at the specified index to invalid This encoding may be used by software to invalidate the entire data cache by stepping through all valid indices Note that Index Store Tag should be used to initialize the cache at powerup Read the tag for the cache block at the specified index into the TagLo Coprocessor 0 register Also read the data corresponding to the byte index into the DataLo register Write the tag for the cache block at the specified index from the TagLo Coprocessor 0 register This encoding may be used by software to initialize the entire instruction or data caches by stepping through all valid indices Doing so requires that the TagLo and TagHi registers associated with the cache be initialized first
31. 2 20 Debug Register CPO Register 23 neers Era i E E EE ERES E 102 5 2 21 Debug Exception Program Counter Register CPO Register 24 sessssseseeresssreresrerrsreersrrererrerrerrsreresee 105 5 2 22 ErrCtl Register CPO Register 26 Select 0 ssori serenite pe essee eeens peee ip teser Nesi ensi kE ep e PERE OS pen EEn oS 106 5 2 23 TagLo Register CPO Register 28 Select 0 oie eee cecesecesceseeesceseeeeeeseseeeeseecaecaeecaecsaessecsaeeseseeeeeeeees 106 5 2 24 DataLo Register CPO Register 28 Select 1 riimien keroent E EEE SEER NEEE e 108 5 2 25 ErrorEPC CPO Register 30 Select 0 oi eee ceesecssccessecencecsseeeeceeseeeeseceseecsaeceaceceeeeesaeeeeeesseeeeaeceeeecaeeaees 109 5 2 20 DeSave Register CPO REgistet 31 e E r e EN a E EEOSE Eo eE Re CERE DEE ESES 110 Chapter 6 Hardware and Software Initialization 00 00 eeecsscseeseesecsecsseecssecsseececcsseesscceecseeseesecsecaseeesaecaseecueesaeeeseneneeners 111 6 1 Hardware Initialized Processor State seseseeesseeesseeereseesrsesrerestertssrersststesteertestettssetssenteseeesresesresrereseeeteseneste 111 6l FCoprocessor Zero States ces erans ae oe r aE S enS Sve cayeelss sumed sates fuss EE NEEE OSE ECSERI EREEREER SER 111 6 1 2 TLB Initialization 4Ke core OnLy sereniserisiicies riiin eieiei eiei i ieii aiia 112 6 1 3 Bus State Machines giim noa e E R E E E E E E EE NRE 112 6 1 4 Static Configuration Inputs oo cece eseseesececseeecssecsseeceecsaeesseceecsevscesecsecaeesessecaeceessesaecas
32. 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline LOT LOT LL Lf Le E M A A A l A W 1 RegR ALUI D Cache l l i l l i T l i B ASel Bus U DC Bypass Align l l l l l h l l i i l Contains all of the time that address and data are utilizing the bus Figure 2 7 Load Store Cache Miss Timing 4Km and 4Kp cores 2 4 Multiply Divide Operations All three cores implement the standard MIPS II multiply and divide instructions Additionally several new instructions were added for enhanced performance The targeted multiply instruction MUL specifies that multiply results be placed in the general purpose register file instead of the HI LO register pair By avoiding the explicit MFLO instruction required when using the LO register and by supporting multiple destination registers the throughput of multiply intensive operations is increased Four instructions multiply add MADD multiply add unsigned MADDU multiply subtract MSUB and multiply subtract unsigned MSUBU are used to perform the multiply accumulate and multiply subtract operations The MADD MADDU instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers Similarly the MSUB MSUBU instruction multiplies two operands and then subtracts the product from the HI and LO registers The MADD MADDU and MSUB MSUBU operations ar
33. 4 Pipeline Interlocks Continued Interlock Type Sources Slip Stage DTLB Miss 4Kc core Data TLB M Stage Load that misses in data cache Multi cycle cache Op Data Cache Miss Store when write thru buffer full EJTAG breakpoint on store VA match needing data value comparison Store hitting in fill buffer In general MIPS processors support two types of hardware interlocks e Stalls which are resolved by halting the pipeline Slips which allow one part of the pipeline to advance while another part of the pipeline is held static In the 4K processor cores all interlocks are handled as slips 2 10 Slip Conditions On every clock internal logic determines whether each pipe stage is allowed to advance These slip conditions propagate backwards down the pipe For example if the M stage does not advance neither will the E or I stages Slipped instructions are retried on subsequent cycles until they issue The back end of the pipeline advances normally during slips in an attempt to resolve the conflict NOPS are inserted into the bubble in the pipeline Figure 2 23 shows an instruction cache miss Clock 1 2 3 4 5 6 Stage 4 1 E LLI u u L G M LI LI O ofl 4 A Ty lh de 0 0 dq Cache miss detected Q Critical word received GB Execute E stage Figure 2 23 Instruction Cache Miss Slip 26 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18
34. 5 7 Context Register Field Descriptions Fields Name Description Reset State This field is for use by the operating system and is PTEBase normally written with a value that allows the operating system to use the Context Register as a pointer into the current PTE array in memory Undefined This field is written by hardware on a TLB miss for the BadVPN2 22 4 4Kc core It contains bits VA31 3 of the virtual address R Undefined that missed 0 3 0 Must be written as zero returns zero on read 0 0 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 5 PageMask Register CPO Register 5 Select 0 The PageMask register is a read write register used for reading from and writing to the TLB It holds a comparison mask that sets the variable page size for each TLB entry as shown in Table 5 9 Behavior is UNDEFINED if a value other than those listed is used This register is only valid with the TLB 4Kc core It is reserved if the FM is implemented 4Km and 4Kp PageMask Register Format 31 25 24 13 12 0 0 Mask 0 Table 5 8 PageMask Register Field Descriptions Fields Read Name Bit s Description Write Reset State The Mask field is a bit mask in which a 1 indicates that Mask 24 13 the corresponding bit of the virtual address should not R W Undefined participate
35. Core Family Software User s Manual Revision 01 18 195 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 11 MIPS32 4K Processor Core Instructions Read Indexed TLB Entry TLBR 31 26 25 24 6 5 0 COPO CO 0 TLBR 010000 1 000 0000 0000 0000 0000 000001 6 1 19 6 Format TLBR MIPS32 Purpose 196 To read an entry from the TLB Description The EntryHi EntryLo0 EntryLol and PageMask registers are loaded with the contents of the TLB entry pointed to by the Index register Note that the value written to the EntryHi EntryLoO and EntryLo1 registers may be different from that originally written to the TLB via these registers in that e The value returned in the G bit in both the EntryLo0 and EntryLo registers comes from the single G bit in the TLB entry Recall that this bit was set from the logical AND of the two G bits in EntryLo0 and EntryLol when the TLB was written e The value returned in the ASID field of the EntryHi register is zero for those chips that implement a BAT based MMU organization Restrictions The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB entries in the processor MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Read Indexed TLB En
36. Descriptions Continued Description Reset State EJTAG Break Setting this bit to 1 causes a debug exception to the processor unless the CPU was in debug mode or another debug exception occurred When the debug exception occurs the processor core Oor 1 clock is restarted if the CPU was in low power mode This bit is cleared by hardware when the debug exception is taken EJTAGBOOT EjtagBrk from The reset value of the bit depends on whether the EJTAGBOOT indication is given or not No EJTAGBOOT indication given 0 EJTAGBOOT indication given 1 reserved 0 Debug Mode This bit indicates the debug or non debug mode 0 Processor is in non debug mode 1 Processor is in debug mode The bit is sampled in the Capture DR state of the TAP controller 9 4 3 Processor Access Address Register The Processor Access Address PAA register is used to provide the address of the processor access in the dmseg and the register is only valid when a processor access is pending The length of the Address register is 32 bits and this register is selected by shifting in the ADDRESS instruction 9 4 3 1 Processor Access Data Register The Processor Access Data PAD register is used to provide data value to and from a processor access The length of the Data register is 32 bits and this register is selected by shifting in the DATA instruction The register has the written value for a processor access write due to a CPU
37. E E E E E E E A EE EE E ON 171 Appendix A Revision History iiser en en E A E E A E oar A EE SSE EEEREN 205 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All right reserved vii viii List of Figures Figure 1 1 4K Processor Core Block Diagram csee orere ioe eeen pen oa En EPEE oE E SEENE PE SEE ENPE REES TE ERr e e Et 4 Figure 1 2 Address Translation during a Cache Access in the 4K Kce Core eseseeeseseesssreseseerrsresrsrrsrrersseereseeresessrrresreresre 6 Figure 1 3 Address Translation during a Cache Access in the 4Km and 4Kp Cores ssssessseseessesrseesressrereseerrsresrsresreersre 7 Figure 2 1 4Kc Core Pipeline Stages ee ern eea eae E E EEE E Ra p AVA SE S EEN p Eere AET Ee TEER R E 12 Figure 2 2 4K Core Pipeline Sta Bes opere resene eves d feed e ca sot costh E EEE o a O puts pees SETE E NE E OSSEA E REENE STE PESEE E E DESSES 12 Figure 2 3 4Kp Core Pipeline Stages inen eee ee eae eE a AE E ea E a TEE S EET osen URE e ea TISE AUE EEr 12 Figure 2 4 Instruction Cache Miss Timing 4KC core essseesssseresrsreerssesresrsrsrestrresrerreestesentesteestesrerrsrentesreresessesreeeeees 14 Figure 2 5 Instruction Cache Miss Timing 4Km and 4Kp cores esesessssessssesrsersresresesresrerrsreserrrsreersseeresrnresrnsesreneeees 15 Figure 2 6 Load Store Cache Miss Timing 4K COre eeeeceeeesceeeeseceseeeeecseeceecaeesaecsacsaecneceaecesese
38. E o eE A EEEN amen ae E Oone Een 119 8 1 Register Controlled Power Management 0 0 cece ceceeseesseeceeseeeecseesaeceeceaecseceseesecseeeceseeeaeeseseaecaeesaecaaesaeensenaee 119 8 2 Instruction Controlled Power Management 0 0 eee eeeeeeeseescecsceseecaeceaeceecssessecseeeceseeseseseseaecseesaecaeesaecseenaes 120 Chapter EITAG Debug Support ssccse ices sesey cases aeee e a tense esa shed sop Aves sepa eee wee eer eben 121 9 1 Debug Control Reister seccei sug aon nie ee asia doe a ain Ret eee elas 122 9 2 Hardware Break points iaeiei E devesvenushtecseesagust gagevens as tas tein E E lueenepes dives sepesceusevanteee 124 9 2 1 Features of Instruction Breakpoint o ee e eee ceeeeceeceseceseeseeeeceseeseeeseseseeseeeaecaaecsecsasaecseesesneeeseeeees 124 972 2 Features Of Data Br akpoint a 3c sccoossrewessucsteeondestesh sesce rvs suseg ince seg e Nea E E EO EKERN POLER SNE coebeaes 124 9 2 3 Overview of Registers for Instruction Breakpoints eee eeeeceeeeeeceseeeeeeseeceecaeecaecsaeaecsaeesesneeeeeeeees 125 9 2 4 Registers for Data Breakpoint Setup eemnes ii a E NE E EEEE ENTES 126 9 2 5 Conditions for Matching Breakpoints oo eee cece ceeceseceeceseeeeceseeeeeeseseaeeseecsecaeecaecsaeeaecaseaeseeeeseeeeees 126 9 2 6 Debug Exceptions from Breakpoints oo eee ceeeecseesecneceseceeceseesccseeseceseveasesacsaecasecaecsaesaecsaseneseeeeeeseees 127 9 2 7 Breakpoint used as Triggerpoint oo eee ceecsesecsseeseceecesececeseeeeeeeeeaeeseseaee
39. ERET 0 Set of IP in Cause Register Interrupted Instruction 3 Any Other Move to Coprocessor 0 Registers 2 CACHE instruction operating on I 3 LL Move From LLAddr 1 Move to Compare Instruction not seeing TimerInterrupt 4 28 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 12 Instruction Hazards 1 This is the minimum value Actual value is system dependent since it is a function of the sequential logic between the SI_TimerInt output and the external logic which feeds SI_TimerInt back into one of the SI_Int inputs MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 29 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline 30 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management The MIPS32 4K processor cores contain a Memory Management Unit MMU that interfaces between the execution unit and the cache controller The MIPS32 4Kc cores contain a Translation Lookaside Buffer TLB while the MIPS32 4Km and MIPS32 4Kp cores implement a simpler Fixed Mapping FM style MMU This chapter contains the following sections e Section 3 1 Introduction e Section 3 2 Modes of Operation e Section 3 3 Translation Lookaside Buffer 4Kc Core Only e Secti
40. Family Software User s Manual Revision 01 18 5 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 4K Processor Core Family translate the address and refill the micro TLB If the entry is not found in the JTLB an exception is taken To minimize the micro TLB miss penalty the JTLB is looked up in parallel with the DTLB for data references This results in a 1 cycle stall for a DTLB miss and a 2 cycle stall for an ITLB miss The 4Km and 4Kp cores implement an FM based MMU instead of a TLB based MMU The FM replaces both the JTLB ITLB and DTLB in the 4Kc core The FM performs a simple translation to get the physical address from the virtual address Refer to Chapter 3 Memory Management on page 31 for more information on the FM Figure 1 2 shows how the ITLB DTLB and JTLB are used in the 4Kc core Figure 1 3 show how the FM is used in the 4Km and 4Kp cores Virtual Address Instruction Address Comparator Calculator Instruction Hit Miss Data Hit Miss Data Address Comparator Calculator Virtual Address Figure 1 2 Address Translation during a Cache Access in the 4Kc Core 6 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 1 3 Required Logic Blocks Virtual Address l Cache Instruction Address Comparator Calcu
41. GPR rd is 32 10 7 3 MADD Multiply and Add Word The MADD instruction multiplies two words and adds the result to the HI LO register pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as signed values to produce a 64 bit result The product is added to the 64 bit concatenated values in the HI and LO register pair The resulting value is then written back to the HI and LO registers No arithmetic exception occurs under any circumstances 10 7 4 MADDU Multiply and Add Unsigned Word The MADDU instruction multiplies two unsigned words and adds the result to the HI LO register pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as unsigned values to produce a 64 bit result The product is added to the 64 bit concatenated values in the HI and LO register pair The resulting value is then written back to the HI and LO registers No arithmetic exception occurs under any conditions 10 7 5 MSUB Multiply and Subtract Word The MSUB instruction multiplies two words and subtracts the result from the HI LO register pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as signed values to produce a 64 bit result The product is subtracted from the 64 bit concatenated values in the HI and LO register pair The resulting value is then written back to the HI and LO registers
42. Inc All rights reserved Chapter 9 EJTAG Debug Support The EJTAG debug logic in the MIPS32 4K processor cores provides two optional modules one for hardware breakpoints and the other is a Test Access Port TAP for a dedicated connection to a debug host This chapter contains the following sections e Section 9 1 Debug Control Register e Section 9 2 Hardware Breakpoints e Section 9 3 Test Access Port TAP e Section 9 4 EJTAG TAP Registers e Section 9 5 Processor Accesses MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 1 Debug Control Register The Debug Control Register DCR register controls and provides information about debug issues and is always provided with the CPU core The register is memory mapped in drseg at offset 0x0 The DataBrk and InstBrk bits indicates if hardware breakpoints are included in the implementation and debug software is expected to read hardware breakpoint registers for additional information Hardware and software interrupts are maskable for non debug mode with the INTE bit which works in addition to the other mechanisms for interrupt masking and enabling NMI is maskable in non debug mode with the NMIE bit and a pending NMI is indicated through the NMIP bit The SRE bit allows implementation dependent masking of none some or all sources
43. MIPS Technologies Inc All rights reserved Chapter 11 MIPS32 4K Processor Core Instructions 170 Table 11 2 Special Opcode Encoding of Function Field function bits 2 0 bits 5 3 000 001 010 O11 100 101 110 111 SED Nf Rl WLM ejo function bits 2 0 Table 11 3 Spedial2 Opcode Encoding of Function Field bits 5 3 0 000 1 001 2 010 3 O11 4 100 5 101 6 110 7 111 a a of 04 a a a SDBBP 7 010 O11 11 BLTZL BGEZL a 1 Ol TGEI TGEIU TLTI TLTIU TEQI a TNEI a 2 10 BLTZAL BGEZAL BLTZALL BGEZALL a a a a 3 11 a a of a a a a a Table 11 5 COPO Encoding of rs Field bits 23 21 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set bits 2 0 function Table 11 6 COPO Encoding of Function Field When rs CO bits 5 3 TLBWR 4Kc a 4Km p TLBP 4Kc a 4Km p Qa a ERET 11 3 Instruction Set This section describes the core instructions Table 11 7 lists the instructions in alphabetical order followed by a detailed description of each instruction Table 11 7 Instruction Set Instruction Description Function ADD Integer Add Rd Rs Rt A
44. MIPS Technologies does not assume any liability arising out of the application or use of this information or of any error of omission in such information Any warranties whether express statutory implied or otherwise including but not limited to the implied warranties of merchantability or fitness for a particular purpose are excluded Any license under patent rights or any other intellectual property rights owned by MIPS Technologies or third parties shall be conveyed by MIPS Technologies or any contractually authorized third party in a separate license agreement between the parties The information contained in this document shall not be exported or transferred for the purpose of reexporting in violation of any U S or non U S regulation treaty Executive Order law statute amendment or supplement thereto The information contained in this document constitutes one or more of the following commercial computer software commercial computer software documentation or other commercial items If the user of this information or any related documentation of any kind including related technical data or manuals is an agency department or other entity of the United States government Government the use duplication reproduction release modification disclosure or transfer of this information or any related documentation of any kind is restricted in accordance with Federal Acquisition Regulation 12 212 for civilian agencies and Defense Fe
45. MSUB MSUBU MFHI MFLO MULT MULTU MADD MADDU 32 bit MADD MADDJU or MSUB MSUBU or 2 MSUB MSUBU MFHI MFLO 16 bit MUL Integer operation 2131 32 bit Integer operation 23 8 bit MFHI MFLO 9 16 bit MFHI MFLO 17 24 bit MFHI MFLO 25 32 bit DIVU MFHI MFLO 33 8 bit DIV MFHI MFLO 10141 16 bit DIV MFHI MFLO 18 4 24 bit DIV MFHI MFLO 26 4 32 bit DIV MFHI MFLO 34 4 any MFHI MFLO Integer operation 2 MADD MADDU or any MTHI MTLO MSUB MSUBU 1 Note 1 For multiply operations this is the rt operand For divide operations this is the rs operand Note 2 Integer Operation refers to any integer instruction that uses the result of a previous MDU operation Note 3 This does not include the 1 or 2 IU pipeline stalls 16 bit or 32 bit that MUL operation causes irrespective of the following instruction These stalls do not add to the latency of 2 Note 4 If both operands are positive the Sign Adjust stage is bypassed Latency is then the same as for DIVU In Table 2 1 a latency of one means that the first and second instruction can be issued back to back in the code without the MDU causing any stalls in the IU pipeline A latency of two means that if issued back to back the IU pipeline will be stalled for one cycle MUL operations are special because it needs to stall the IU pipeline in order to maintain its register file write slot Consequently the MUL 16x16 or 32x16 operation will always force a one cycle stall of the IU
46. PFNO 31 12 PFN1 31 12 Cacheability Contains an encoded value of the cacheability attributes and determines whether the page should be placed in the cache or not The field is encoded as follows C 2 0 000 001 010 Coherency Attribute Maps to entry 011b Maps to entry 011b Uncached CO 2 0 C1 2 0 Cacheable noncoherent write through on no write allocated 100 101 Maps to entry 011b 110 Maps to entry 011b 111 Maps to entry 010b Maps to entry 011b Note These mappings are not used on the 4K proces sor cores but do have meaning in other MIPS Dirty or Write enable Bit Indicates that the page has been written and or is writable If this bit is set stores to the page are permitted If the bit is cleared stores to the page cause a TLB Modified exception DO D1 Valid Bit Indicates that the TLB entry and thus the virtual page mapping are valid If this bit is set accesses to the page are permitted If the bit is cleared accesses to the page cause a TLB Invalid exception VO V1 In order to fill an entry in the JTLB software executes a TLBWI or TLBWR instruction See Section 3 4 3 TLB Instructions on page 47 Prior to invoking one of these instructions several CPO registers must be updated with the information to be written to a TLB entry e PageMask is set in the CPO PageMask register e VPN2 and ASID are set in the CPO EntryHi regist
47. Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Table 11 7 Instruction Set Continued Instruction Description Function SSNOP Superscalar Inhibit No Operation SUB Integer Subtract Rt int Rs int Rd SUBU Unsigned Subtract Rt uns Rs uns Rd SW Store Word Mem Rs offset Rt SWL Store Word Left Refer to Architecture Reference Manual soe Refer to Architecture Reference SWR Store Word Right Manual SYNC Synchronize See SYNC instruction on page 194 SYSCALL System Call SystemCallException if Rs Rt TEQ Trap if Equal TrapException if Rs int Immed TEQI Trap if Equal Immediate TrapException TGE Trap if Greater Than or Equal oo gt int Rt rapException n if int Rs gt int Immed TGEI Trap if Greater Than or Equal Immediate TrapException TGEIU Trap if Greater Than or Equal Immediate if uns Rs gt uns Immed Unsigned TrapException TGEU Trap if Greater Than or Equal Unsigned T car uns Rt rapException TLBWI Write Indexed TLB Entry 4K core oe LB WI imstiuction on page 198 TLBWR Write Random TLB Entry 4K core See TLP WR imstraction on page 200 TLBP Probe TLB for Matching Entry 4K core See Architecture Reference Manual TLBR Read Index for TLB Entry 4K core See TLBR instruction on page 196 TLT Trap if Less Than if int Rs lt GnRt P TrapException TLTI Trap if Less Than Immedi
48. aa Bac ates A Rashes He Needs Bad bos aa Ra ainda 23 2B LOdd DeLay Eeee ENEE E souks fhe gesapvess sau E E E conte acute puegs cause gece E EEES 24 2 8 2 Move from HI LO and CPO Delay oo cece eee ceeecceeeeeeecseeeeecaeesaecaeesaecsecsaecsecsesseeeseseaseseseaeeseseaecsaeeaeenaes 25 P29 Interlock Hand lyn gs msee sape iea cathe ees se vane sevei dean E E a cous ty oes essevatesivtue A EEEE 25 2 10 Ship COnditiONS 2 3 5 es spice SSSR ete RIA ees ee BG AA AT OGRE RSE ES 26 QU TnistructionlniterlOCkS ecscessed Hest scses cc gchceeiecesuasutvens cacest vende e ae e e e aae eE Eee cossbelenecsgebentunes 27 242 Instruction Hazards soeren ha ceves ie a e a tran ease ted ke ensbee a a a deen tad eee tas 28 Chapter 3 Memory Management siai nara soba Suk coset ve viens Bocebuces tses tosis cohen bance ESEE EEE Eia ible utes Asus DEAE E aes 31 By LTO Gt OM MEER EE A sah asveeeidteacetscagsih soeca bach vuaddugesehacsa dda veces igesseesostecanpuabodsnobassena ssbebisvuveagnaeotudes 31 3 2 MOdeS Gf Operations a rrea eE eE e bes EEE EEEE EE EEEE EEE OKE E EEEO EREE EERE EE EE N E E 32 3 2 1 Virtual Memory Segments circe iieu arepane E asap EE E EER EES ESERE aR ea EE ESEE E 33 3 2 2 User MOde oisin reterii iia E ER EE E Bic T E Sb hat E A E n wee a a aa 35 3 2 3 Kernel Mode sssri aeeie Eoo ao opaa e E Eose indevasteeatlsessssopsonaues o EE Se e eE Eaa bane 36 3 24 Debus Mode aesae on nene Aisi a Er E R EE E E EEE OEE Depeasubs EEE EES EE EEEE EEEE dpe E
49. access type of cached coherent Uniprocessor atomicity To provide atomic RMW on a single processor all accesses to the location must be made with memory access type of either cached noncoherent or cached coherent All accesses must be to one or the other access type and they may not be mixed T O System To provide atomic RMW with a coherent I O system all accesses to the location must be made with a memory access type of cached coherent If the I O system does not use coherent memory operations then atomic RMW cannot be provided with respect to the I O reads and writes Restrictions The addressed location must have a memory access type of cached noncoherent or cached coherent if it does not the result is undefined The effective address must be naturally aligned If either of the 2 least significant bits of the address is non zero an Address Error exception occurs Operation vAddr lt sign_extend offset GPR base if yRddt o 0 then SignalException AddressError endif pAddr CCA AddressTranslation vAddr DATA STORE dataword GPR rt if LLbit then StoreMemory CCA WORD dataword pAddr vAddr DATA endif GPR rt 07 LLbit MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Store Conditional Word cont Exceptions SC TLB Refill TLB Invalid TLB Modified Address Erro
50. another exception EPC lt PC 4 EPC lt PC Cause BD lt 1 Cause BD lt 0 Processor forced to Kernel To General Exception Servicing Guidelines Mode amp interrupt disabled 0 normal 1 bootstrap PC lt 0x8000_0000 180 PC lt OxBFC0_0200 180 unmapped cached unmapped uncached To General Exception Servicing Guidelines Figure 4 1 General Exception Handler HW 68 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 7 Exception Handling and Servicing Flowcharts Comments Unmapped vector so TLBMod TLBInv or TLB MECO Refill exceptions not possible 4Kc core only Context EPC Status Cause EXL 1 so Watch Interrupt exceptions disabled OS System to avoid all other exceptions Only Reset Soft Reset NMI exceptions possible A MTCO Set Status bits Optional only to enable Interrupts while keeping UM lt 0 EXL lt 0 Kernel Mode IE lt 1 Check Cause value amp Jump to After EXL 0 all exceptions allowed appropriate Service Code except interrupt if masked by IE MTCO EPC STATUS ERET is not allowed in the branch delay slot of another Jump Instruction Processor does not execute the instruction ERET which is in the ERET s branch delay slot PC lt EPC EXL lt 0 LLbit lt 0 Figure 4 2 General Exception Servi
51. assertion of an unmasked interrupt to fetch of the first instructions at the exception vector is a minimum of 5 clock cycles More may be needed if a committed instruction has to complete before the exception can be taken A SYNC instruction which has already started flushing the cache and write buffers must wait until this is completed before the interrupt exception can be taken Register ExcCode Value Int Additional State Saved Table 4 6 Register States an Interrupt Exception Register State Value Cause p indicates the interrupts that are pending Entry Vector Used General exception vector offset 0x180 if the IV bit in the Cause register is 0 interrupt vector offset 0x200 if the IV bit in the Cause register is 1 4 6 8 Debug Instruction Break Exception A debug instruction break exception occurs when an instruction hardware breakpoint matches an executed instruction The DEPC register and DBD bit in the Debug register indicates the instruction that caused the instruction hardware breakpoint to match This exception can only occur if instruction hardware breakpoints are implemented Debug Register Debug Status Bit Set DIB MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 6 Exceptions Additional State Saved None Entry Vector Used Debug exception vector 4 6 9 Watch Exception Instruction Fe
52. bit in Debug register read write so software can 01 12 January 3 2001 control whether Count register increments in Debug Mode Miscellaneous minor text tweaks based on review feedback 01 13 March 3 2001 Tagged source to make core specific document MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 207 Copyright 2000 2002 MIPS Technologies Inc All right reserved Appendix A Revision History Revision Date Description e Fixed some core specific tagging e Updated to document template revision 01 04 e Updated the instruction descriptions from the Architecture Manual e Added missing footnote in Table 2 6 on page 28 e Fixed typo in description of LSNM field in Table 5 26 on page 102 e Correct name of ASIDsup field in IBS Table 9 7 on page 131 and DBS Table 9 13 on page 137 registers e Correct name of ASIDuse field in IBCn Table 9 11 on page 135 01 14 June 20 2001 and DBCn Table 9 17 on page 141 registers e Updated reset state of Doze and Halt bits in EJTAG Control register Table 9 23 on page 153 e First collom in sub table for Psz field is changed from PA to PAA Table 9 23 on page 153 e Added a better Restriction example Section 11 1 6 Restrictions Field on page 172 e Added B BAL and NOP to list of instructions Table 11 7 on page 171 In functions fields for LWL LWR SWL SWR SYNC TLBWI TLBWR TLBP and TLBR Pointed reader to see instruction descr
53. bit is set appropriately in the Cause register If the instruction is not in the delay slot of a branch the BD bit in Cause will be cleared and the value loaded into the EPC register is the current PC If the instruction is in the delay slot of a branch the BD bit in Cause is set and EPC is loaded with PC 4 If the EXL bit in the Status register is set the EPC register is not loaded and the BD bit is not changed in the Cause register e The CE and ExcCode fields of the Cause registers are loaded with the values appropriate to the exception The CE field is loaded but not defined for any exception type other than a coprocessor unusable exception e The EXL bit is set in the Status register 54 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 5 Debug Exception Processing e The processor is started at the exception vector The value loaded into EPC represents the restart address for the exception and need not be modified by exception handler software in the normal case Software need not look at the BD bit in the Cause register unless is wishes to identify the address of the instruction that actually caused the exception Note that individual exception types may load additional information into other registers This is noted in the description of each exception type below Operation if StatusSpy 0 then if InstructionInBranchD
54. block transfers between dmseg on the probe and target memory on the processor An upload is defined as a sequence of processor loads from target memory and stores to dmseg A download is a sequence of processor loads from dmseg and stores to target memory The Fastdata area specifies the legal range of dmseg addresses OxFF20 0000 OxFF20 000F that can be used for uploads and downloads The Data MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 5 Processor Accesses Fastdata registers selected with the FASTDATA instruction allow efficient completion of pending Fastdata area accesses During Fastdata uploads and downloads the processor will stall on accesses to the Fastdata area The PrAcc processor access pending bit will be 1 indicating the probe is required to complete the access Both upload and download accesses are attempted by shifting in a zero SPrAcc value to request access completion and shifting out SPrAcc to see if the attempt will be successful i e there was an access pending and a legal Fastdata area address was used Downloads will also shift in the data to be used to satisfy the load from dmseg s Fastdata area while uploads will shift out the data being stored to dmseg s Fastdata area As noted above two conditions must be true for the Fastdata access to succeed These are e PrAcc must be 1
55. can then decide whether to reduce the clock frequency and place the core into power down mode If an interrupt is taken while the device is in power down mode that interrupt may need to be serviced depending on the needs of the application The interrupt causes an exception which in turn causes the EXL bit to be set The setting of the EXL bit causes the assertion of the S _EXL signal on the external bus indicating to the external agent that an interrupt has occurred At this time the external agent can choose to either speed up the clocks and service the interrupt or let it be serviced at the lower clock speed The setting of the ERL bit causes the assertion of the S7_ERL signal on the external bus indicating to the external agent that an error has occurred At this time the external agent can choose to either speed up the clocks and service the error or let it be serviced at the lower clock speed Similarly the EJ_DebugM signal indicates that the processor is in debug mode Debug mode is entered when the processor takes a debug exception If fast handling of this is desired the external agent can speed up the clocks The core provides four power down signals that are part of the system interface Three of the pins change state as the corresponding bits in the CPO Status register are set or cleared The fourth pin indicates that the processor is in debug mode e The SI_RP signal represents the state of the RP bit 27 in the CPO Status register
56. cores EntryLo0 Low order portion of the TLB entry for even numbered virtual pages 4Kc core This register is reserved in the 4Kp and 4Km cores EntryLol l Low order portion of the TLB entry for odd numbered virtual pages 4Kc core This register is reserved in the 4Kp and 4Km cores Context Pointer to page table entry in memory 4Kc core This register is reserved in the 4Kp and 4Km cores PageMask Wired Controls the variable page sizes in TLB entries 4Kc core This register is reserved in the 4Kp and 4Km cores Controls the number of fixed wired TLB entries 4Kc core This register is reserved in the 4Kp and 4Km cores Reserved Reserved 2 Reports the address for the most recent address related 8 BadVAddr exception 9 Count Processor cycle count MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 73 Chapter 5 CPO Registers 74 Register Table 5 1 CPO Registers Continued Number Register Name Function EntryHi i Compare High order portion of the TLB entry 4Kc core This register is reserved in the 4Kp and 4Km cores Timer interrupt control Status Processor status and control Cause of last exception Program counter at last exception PRId Processor identification and revision Config Config1 Configuration registers LLAdd
57. data load are precise Other bus errors such as stores or non critical words of a burst read can be imprecise These errors are taken when the EB_RBErr or EB_WBErr signals are asserted and may occur on an instruction that was not the source of the offending bus cycle Cause Register ExcCode Value IBE Error on an instruction reference DBE Error on a data reference Additional State Saved None MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 63 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions Entry Vector Used General exception vector offset 0x180 4 6 14 Debug Software Breakpoint Exception A debug software breakpoint exception occurs when an SDBBP instruction is executed The DEPC register and DBD bit in the Debug register will indicate the SDBBP instruction that caused the debug exception Debug Register Debug Status Bit Set DBp Additional State Saved None Entry Vector Used Debug exception vector 4 6 15 Execution Exception System Call The system call exception is one of the six execution exceptions All of these exceptions have the same priority A system call exception occurs when a SYSCALL instruction is executed Cause Register ExcCode Value Sys Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 6 16 Execution Exception Breakpoint The breakpoint exception is one of the
58. ee aoa ne See epetan 53 4 4 General Exception Processing smsna e a a E E NE a E E a a aa E EE S es 54 4 5 Debug Exception Processing resson e EERE ERE E E N SRE AEE R S 55 AG a oIa 0 REE S EE E S EET 56 A E SLEE Dec OLAT a MRTE eE E ETE AAOS E EEE EEEE E EE EA 56 462 Soft Reset Exception a ee aaa ead a a a EE E R 57 4 6 3 Debug Sinele Step EXCDO soii e E S E E E ee ove EA EEE SERS 58 4 6 4 Debug Interrupt Exception veeo orae ana ee a reae E aA a RE E AAE EEE Eas eE E Eoen E E E Roos 59 4 6 5 Non Maskable Interrupt NMI Exception oo cece cssecseceseesecescesececesecesceseeeeeeeseaesseeeaesseeeaecsasaeenaes 59 4 6 6 Machine Check Exception 4KC core oe eeeeeescescecsseceseeceneecssceeeeeeseeseneceseecsaeceaeeceeessaeeeaeesseeeeaeceeeecaeeeaeeee 60 4 6 7 Interrupt ExCeptlon essesscescisesvevsecspsuuadenneucegersuiaualeareetesd ieecesn E eatunes Me E E EER 60 4 6 8 Debug Instruction Break Exception oc cceseeseeseecsecesecsecescesecsaesaecescssecesceseseeeeseseaesseeeaecaaeeaecsaesaeenaes 60 4 6 9 Watch Exception Instruction Fetch or Data ACCESS oo eeteseceseeseceecesecesceeeeeceeseaeeseeeaseaeecaecsaeeaeenaes 6l 4 6 10 Address Error Exception Instruction Fetch Data Access ssessseeseseeeesseeerssesrrseesrsrrererrerrerrsererseeersreet 6l 4 6 11 TLB Refill Exception Instruction Fetch or Data Access 4KC core e sssessssssessssrsesseesserssrrsrrsressrssree 62 4 6 12 TLB Invalid Exception Instruction Fetch or Data Access
59. for soft reset The soft reset masking may only be applied to a soft reset source if that source can be efficiently masked in the system thus resulting on no reset at all If that is not possible then that soft reset source should not be masked since a half soft reset may cause the system to fail or hang There is no automatic indication of whether the SRE is effective but the user must consult system documentation The PE bit reflects the ProbEn bit from the EJTAG Control register ECR whereby the probe can indicate to the debug software running on the CPU if the probe expects to service dmseg accesses The reset value in the table below takes effect on both hard and soft reset Debug Control Register 31 30 29 28 18 17 16 15 5 4 3 2 1 0 Res ENM Res DB IB Res INTE NMIE NMIP SRE PE Table 9 1 Debug Control Register Field Descriptions Description Reset State reserved Endianess in Kernel and Debug mode This bit indicates the endianess in Kernel and Debug mode 0 Little Endian 1 Big Endian reserved Data Break Implemented This bit indicates if the Data Break feature is implemented Preset 0 No Data Break feature implemented 1 Data Break feature is implemented Instruction Break Implemented This bit indicates if the Instruction Break feature is implemented Preset 0 No Instruction Break feature implemented 1 Instruction Break feature is implemented Res 15 5 reserved R 0 122 MIPS
60. if both operands were positive or if this is an unsigned division both of the sign adjust cycles are skipped If the rs operand was negative one of the sign adjust cycles is skipped If only the rs operand was negative none of the sign adjust cycles are skipped Register writeback to HI and LO are done in the A stage Figure 2 17 shows the latency for a divide operation The repeat rate is either 34 35 or 36 cycles depending on how many sign adjust cycles are skipped as a second divide can be in the E stage when the first divide is in the last Mypny stage Clock 1 2 3 34 35 36 37 38 e E Stage P Mou Stage gt lt Mupu Stage Muu StageD Mpu StageP Anpu Stage P Wave Stage P Figure 2 17 4Kp MDU Pipeline Flow During a Divide DIV Operation 22 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 7 Branch Delay 2 7 Branch Delay The pipeline has a branch delay of one cycle The one cycle branch delay is a result of the branch decision logic operating during the E pipeline stage This allows the branch target address calculated in the previous stage to be used for the instruction access in the following E stage The branch delay slot means that no bubbles are injected into the pipeline on branch instructions The address calculation and branch condition check are both performed in the E stage The target PC is used for the next instr
61. instruction The DBD bit in the Debug register is never set for a debug single step exception since the jump branch and the instruction in the delay slot is executed in one step Exceptions occurring on the instruction s executed with debug single step exception enabled are taken even though debug single step was enabled For a normal exception other than reset a debug single step exception is then taken on the first instruction in the normal exception handler Debug exceptions are unaffected by single step mode e g returning to a SDBBP instruction with debug single step exceptions enabled causes a debug software breakpoint exception and the DEPC will point to the SDBBP instruction However returning to an instruction not jump branch just before the SDBBP instruction causes a debug single step exception with the DEPC pointing to the SDBBP instruction To ensure proper functionality of single step the debug single step exception has priority over all other exceptions except reset and soft reset Debug Register Debug Status Bit Set DSS Additional State Saved None Entry Vector Used Debug exception vector MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 6 Exceptions 4 6 4 Debug Interrupt Exception A debug interrupt exception is either caused by the EjtagBrk bit in the EJTAG Control register controlled through the TAP o
62. load or store which is located on the EJTAG Probe This occurs in a serial way through the EJTAG interface the core can thus execute instructions e g debug monitor code without occupying the user s memory MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 159 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support Accessing the dmseg segment EJTAG memory can only occur when the processor accesses an address in the range from OxFF20 0000 to OXFF2F FFFF the ProbEn bit is set and the processor is in debug mode DM 1 In addition the LSNM bit in the CPO Debug register controls transactions to from the dmseg When a debug exception is taken while the ProbTrap bit is set the processor will start fetching instructions from address OxFF20 0200 A pending processor access can only finish if the probe writes 0 to PrAcc or by soft or hard reset 9 5 1 Fetch Load and Store from to the EJTAG Probe through dmseg 160 1 The internal hardware latches the requested address into the PA Address register in case of the Debug exception OxFF20_0200 2 The internal hardware sets the following bits in the EJTAG Control register PrAcc 1 selects Processor Access operation PRnW 0 selects processor read operation Psz 1 0 value depending on the transfer size 3 The EJTAG Probe selects the EJTAG Control register shifts out this control register s data and tests
63. match The load store instruction that caused the debug exception has not completed e g not updated the register file and the instruction can be re executed after returning from the debug handler Debug Register Debug Status Bit Set DDBL for a load instruction or DDBS for a store instruction Additional State Saved None Entry Vector Used Debug exception vector 4 6 22 TLB Modified Exception Data Access 4Kc core During a data access a TLB modified exception occurs on a store reference to a mapped address if the following condition is true e The matching TLB entry in a TLB based MMU is valid but not dirty Cause Register ExcCode Value Mod Additional State Saved Table 4 12 Register States on a TLB Modified Exception Register State Value BadVAddr Context failing address The BadVPN2 field contains VA3 3 of the failing address EntryHi EntryLoO EntryLol The VPN2 field contains VA31 13 of the failing address the ASID field contains the ASID of the reference that missed UNPREDICTABLE UNPREDICTABLE MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 7 Exception Handling and Servicing Flowcharts Entry Vector Used General exception vector offset 0x180 4 7 Exception Handling and Servicing Flowcharts The remainder of this chapter contains flowcharts for
64. of the way select and data RAM arrays for both the ICache and DCache The way selection RAM test mode is enabled by setting the WST bit It modifies the functionality of the CACHE Index Load Tag and Index Store Tag operations so that they modify the way selection RAM and leave the Tag RAMs untouched When this bit is set the lower 6 bits of the PA field in the TagLo register are used as the source and destination for Index Load Tag and Index Store Tag CACHE operations The WST bit also enables the data RAM test mode When this bit is set the Index Store Data CACHE instruction is enabled This CACHE operation writes the contents of the DataLo register to the word in the data array that is indicated by the index and byte address The SPR bit enables CACHE accesses to the optional Scratchpad RAMs When this bit is set Index Load Tag Index Store Tag and Index Store Data CACHE instructions will send reads or writes to the Scratchpad RAM port The effects of these operations are dependent on the particular Scratchpad implementation This register was added to version 3 5 of the core It is reserved in earlier versions ErrCtl Register Format 3130 29 28 27 0 R WST SPR R Table 5 28 ErrCtl Register Field Descriptions Fields Description Reset State Indicates whether the tag array or the way select array should be read written on Index Load Store Tag CACHE instructions Also enables the Index Store Data CACHE instruction whi
65. one stores to the page are permitted If this bit is a zero stores to the page cause a TLB Modified exception Valid bit indicating that the TLB entry and thus the virtual page mapping are valid If this bit is a one accesses to the page are permitted If this bit is a zero accesses to the page cause a TLB Invalid exception Undefined R W Undefined Undefined Undefined Global bit On a TLB write the logical AND of the G bits in both the EntryLo0 and EntryLol1 registers become the G bit in the TLB entry If the TLB entry G bit is a one ASID comparisons are ignored during TLB matches On a read from a TLB entry the G bits of both EntryLo0 and EntryLol reflect the state of the TLB G bit 7 Undefined Table 5 6 lists the encoding of the C field of the EntryLo0 and EntryLo registers and the KO field of the Config register Table 5 6 Cache Coherency Attributes C 5 3 Value Cache Coherency Attribute 0 1 3 4 5 6 Cacheable noncoherent write through no write allocate Pre Uncached MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers Table 5 6 Cache Coherency Attributes C 5 3 Value Cache Coherency Attribute Note These two values are required by the MIPS32 architecture All other values are not used For example values 0 1 4 5 and 6 are not used and are mapped to
66. ra 85 HS Bod cls RA sth BE i oll Rae i alta sina 13 21 3 Mi Stage Memory BEtCh ee rrer e e sau ae r ae pee se ipe ereo pegs cause dune svassseaesdy susvhesecpdeabessepescenoesiees 13 2 1 4 A Stage Align Accumulate si aea aaao a ee case sendicusvesodptevsben a E A A naa EA S PEE Ei 13 2A W Stage Writeback sieren nenea ss Mende E E E A E E lew pea EEEN 14 2 2 Instruction Cache MASS ereenn iee tage A E A N N E N E A R R a es 14 2 3 Data Cache MASS ESNE EE AE PEE EEEE E E E E EE EE E EEEE 15 2 4 Multiply Divide Operations sinocni e e ati a a E E a a E e EE SEE 16 2 5 MDU Pip line 4KC and 4 Kim Cores ronnie E EE EEA EE E E E E A R 16 2 5 1 32x16 Multiply 4Kc and 4Km Cores esssssessssessesesessssesrssreresresrsresrestssestssertesretsrentesrntentnerteneerrerentereeeses 19 2 5 2 32x32 Multiply 4Kc and 4Km Cores r ear ae roseau pee tpe ppe eres OOE Opoe Poe SETE E Nei pen ENR pe SEEPS POSEE PE eE 19 2 5 3 Divide 4Kc and 4Km Cores soreer cierto re eds ekr r E lest e erret iak deee deee ereen ekti ae 19 2 6 MDU Pipeline 4p Core Only cis ie vase Aes Ee S E quedo R ons eerie Leese EE EER 21 2 63 Multiply 4K p Core sc ccn cate ae eevee BAA AAG Sa ae hi eid a had aoa 21 2 6 2 Muluply Accumulate AK pi Core ss 2s raae or ope Ea EE aeo En NS NEE Epon b eSEE EO EP OSERE SPEE 22 20 3 Divide AK pC Ore innn n e E E e ease aleve a E a ae le N 22 2 T Branch Delay enres ai nee e E E E E e E E E E E 23 2 3 Data Bypassing re a a a
67. registers are used to enable the breakpoints Debug software should not configure breakpoints to compare on ASID value unless a TLB is present in the implementation 4Kc core only 9 2 5 1 Conditions for Matching Instruction Breakpoint When an instruction breakpoint is enabled that breakpoint is evaluated for the address of every executed instruction in non debug mode including execution of instructions at an address causing an address error on instruction fetch The breakpoint is not evaluated on instructions from speculative fetch or execution nor for addresses which are unaligned with an executed instruction Match of the breakpoint depends on the virtual address of the executed instruction PC which can be masked at bit level and match may also include optional compare of ASID value The registers for each instruction breakpoint have the values and mask used in the compare and the equation that determines the match is shown below in C like notation IB_match IBCnastpuse ASID IBASIDnastp amp amp lt all 1 s gt IBMnypy PC IBAnzpa The match indication for instruction breakpoints is always precise i e indicated on the instruction causing the IB_match to be true MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 5 2 Conditions for Matching Data Breakpoints Whe
68. six execution exceptions All of these exceptions have the same priority A breakpoint exception occurs when a BREAK instruction is executed Cause Register ExcCode Value Bp Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 6 17 Execution Exception Reserved Instruction The reserved instruction exception is one of the six execution exceptions All of these exceptions have the same priority A reserved instruction exception occurs when a reserved or undefined major opcode or function field is executed 64 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 6 Exceptions Cause Register ExcCode Value RI Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 6 18 Execution Exception Coprocessor Unusable The coprocessor unusable exception is one of the six execution exceptions All of these exceptions have the same priority A coprocessor unusable exception occurs when an attempt is made to execute a coprocessor instruction for one of the following e a corresponding coprocessor unit that has not been marked usable by setting its CU bit in the Status register e CPO instructions when the unit has not been marked usable and the processor is executing in user mode Cause Register ExcCode Value CpU Additional State Saved Table 4 11 Regis
69. store instruction is executed A true DB_match can thereby be indicated on the very same instruction causing the DB_match to be true 9 2 6 Debug Exceptions from Breakpoints Instruction and data breakpoints may be set up to generate a debug exception when the match condition is true as described below MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 127 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 128 9 2 6 1 Debug Exception by Instruction Breakpoint If the breakpoint is enabled by BE in the BCn register then a debug instruction break exception occurs if the IB_match equation is true The corresponding BS n bit in the ZBS register is set when the breakpoint generates the debug exception The debug instruction break exception is always precise so the DEPC register and DBD bit in the Debug register points to the instruction that caused the IB_match equation to be true The instruction receiving the debug exception does not update any registers due to the instruction nor does any load or store by that instruction occur Thus a debug exception from a data breakpoint can not occur for instructions receiving a debug instruction break exception The debug handler usually returns to the instruction causing the debug instruction break exception whereby the instruction is executed Debug software is responsible for disabling the breakpoint when returning
70. store to the dmseg and the output from this register is only valid when a processor access write is pending The register is used to provide the data value for processor access read due to a CPU load or fetch from the dmseg and the register should only be updated with a new value when a processor access write is pending The PAD register is 32 bits wide Data alignment is not used for this register so the value in the PAD register matches data on the internal bus The undefined bytes for a PA write are undefined and for a PAD read then 0 zero must be shifted in for the unused bytes The organization of bytes in the PAD register depends on the endianess of the core as shown in Figure 9 8 The endian mode for debug kernel mode is determined by the state of the EB_Endian input at power up MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 157 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 158 MSB LSB bit 31 24 23 16 15 87 0 BIG ENDIAN Aino 4 5 Jl 6e 7 Amaz A n 0 0 1 2 3 A n 2 0 Most significant byte is at lowest address Word is addressed by byte address of most significant byte MSB LSB bit 31 24 23 16 15 8 7 0 Ain o 7 6 4 Afn2 1 5 A n 0 3 2 1 0 A n 2 0 Least significant byte is at lowest address Word is addressed by byte address of least significant byte LITTLE ENDIAN Fi
71. the PrAcc status bit Processor Access when the PrAcc bit is found 1 it means that the requested address is available and can be shifted out 4 The EJTAG Probe checks the PRnW bit to determine the required access 5 The EJTAG Probe selects the PA Address register and shifts out the requested address 6 The EJTAG Probe selects the PA Data register and shifts in the instruction corresponding to this address 7 The EJTAG Probe selects the EJTAG Control register and shifts a PrAcc 0 bit into this register to indicate to the processor that the instruction is available 8 The instruction becomes available in the instruction register and the processor starts executing 9 The processor increments the program counter and outputs an instruction read request for the next instruction This starts the whole sequence again Using the same protocol the processor can also execute a load instruction to access the EJTAG Probe s memory For this to happen the processor must execute a load instruction e g a LW LH LB with the target address in the appropriate range Almost the same protocol is used to execute a store instruction to the EJTAG Probe s memory through dmseg The store address must be in the range OxFF20_0000 to OxFF2F_FFFF the ProbEn bit must be set and the processor has to be in debug mode DM 1 The sequence of actions is found below 1 The internal hardware latches the requested address into the PA Address register 2 The
72. 0 Indicates that a debug interrupt exception occurred Cleared on exception in debug mode DINT 5 R W Undefined 0 No debug interrupt exception 1 Debug interrupt exception Indicates that a debug instruction break exception occurred Cleared on exception in debug mode DIB 4 R Undefined 0 No debug instruction exception 1 Debug instruction exception Indicates that a debug data break exception occurred on a store Cleared on exception in debug mode DDBS 3 R Undefined 0 No debug data exception on a store 1 Debug instruction exception on a store Indicates that a debug data break exception occurred on a load Cleared on exception in debug mode DDBL 2 R Undefined 0 No debug data exception on a load 1 Debug instruction exception on a load Indicates that a debug software breakpoint exception occurred Cleared on exception in debug mode DBp 1 R Undefined 0 No debug software breakpoint exception 1 Debug software breakpoint exception Indicates that a debug single step exception occurred Cleared on exception in debug mode DSS 0 R Undefined 0 No debug single step exception 1 Debug single step exception 104 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 21 Debug Exception Program Counter Register CP0 Register 24 The Debug Exception Program Counter DEPC register is a read writ
73. 0 Register 9 Select 0 The Count register acts as a timer incrementing at a constant rate whether or not an instruction is executed retired or any forward progress is made through the pipeline The counter increments every other clock The Count register can be written for functional or diagnostic purposes including at reset or to synchronize processors Whether the Count register continues incrementing while the processor is in debug mode is determined by the CountDM bit in the Debug register see Section 5 2 20 Debug Register CPO Register 23 on page 102 Count Register Format 31 0 Count Table 5 12 Count Register Field Description Name Bits Description Write Reset State Count 31 0 Interval counter R W Undefined 84 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 9 EntryHi Register CP0 Register 10 Select 0 The EntryHi register contains the virtual address match information used for TLB read write and access operations A TLB exception TLB Refill TLB Invalid or TLB Modified causes bits VA31 3 of the virtual address to be written into the VPN2 field of the EntryHi register The ASID field is written by software with the current address space identifier value and is used during the TLB comparison process to determine TLB match The VPN2 field of the EntryHi register i
74. 1 Overview of Jump Instructions Subroutine calls in high level languages are usually implemented with Jump or Jump and Link instructions both of which are J type instructions In J type format the 26 bit target address shifts left 2 bits and combines with the high order 4 bits of the current program counter to form an absolute address Returns dispatches and large cross page jumps are usually implemented with the Jump Register or Jump and Link Register instructions Both are R type instructions that take the 32 bit byte address contained in one of the general purpose registers For more information about jump instructions refer to the individual instructions in Section 11 3 Instruction Set 10 4 2 Overview of Branch Instructions All branch instruction target addresses are computed by adding the address of the instruction in the delay slot to the 16 bit offset shifted left 2 bits and sign extended to 32 bits All branches occur with a delay of one instruction If a conditional branch likely is not taken the instruction in the delay slot is nullified Branches jumps ERET and DERET instructions should not be placed in the delay slot of a branch or jump 10 5 Control Instructions Control instructions allow the software to initiate traps they are always R type 10 6 Coprocessor Instructions CPO instructions perform operations on the System Control Coprocessor registers to manipulate the memory management and exception handlin
75. 2 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers The System Control Coprocessor CPO provides the register interface to the MIPS32 4K processor cores and supports memory management address translation exception handling and other privileged operations Each CPO register has a unique number that identifies it this number is referred to as the register number For instance the PageMask register is register number 5 For more information on the EJTAG registers refer to Chapter 9 EJTAG Debug Support After updating a CPO register there is a hazard period of zero or more instructions from the update instruction MTCO and until the effect of the update has taken place in the core Please refer to Chapter 2 Pipeline for further detail on CPO hazards The current chapter contains the following sections e Section 5 1 CPO Register Summary e Section 5 2 CPO Registers 5 1 CPO Register Summary Table 5 1 lists the CPO registers in numerical order The individual registers are described throughout this chapter Table 5 1 CPO Registers Register Number Register Name Index Function Index into the TLB array 4Kc core This register is reserved in the 4Kp and 4Km cores Random Randomly generated index into the TLB array 4Kc core This register is reserved in the 4Kp and 4Km
76. 3 The value 7 is not used and is mapped to 2 Note that these values do have meaning in other MIPS Technologies processor implementations Refer to the MIPS32 specification for more information MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 79 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 80 5 2 4 Context Register CPO Register 4 Select 0 The Context register is a read write register containing a pointer to an entry in the page table entry PTE array This array is an operating system data structure that stores virtual to physical translations During a TLB miss the operating system loads the TLB with the missing translation from the PTE array The Context register duplicates some of the information provided in the BadVAddr register but is organized in such a way that the operating system can directly reference an 8 byte page table entry PTE in memory A TLB exception TLB Refill TLB Invalid or TLB Modified causes bits VA31 3 of the virtual address to be written into the BadVPN2 field of the Context register The PTEBase field is written and used by the operating system The BadVPN2 field of the Context register is not defined after an address error exception This register is only valid with the TLB 4Kc core It is reserved if the FM is implemented 4Km and 4Kp Context Register Format 31 23 22 4 3 0 PTEBase BadVPN2 0 Table
77. 3 4 User Mode Virtual Address Space The user segment starts at address 0xO0000_0000 and ends at address 0x7FFF_FFFF Accesses to all other addresses cause an address error exception The processor operates in User mode when the Status register contains the following bit values e UM 1 e EXL 0 e ERL 0 In addition to the above values the DM bit in the Debug register must be 0 Table 3 1 lists the characteristics of the useg User mode segments MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 35 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management 36 Table 3 1 User Mode Segments Status Register Bit Value Segment Address 8 Bit Value EXL ERL UM Name Address Range Segment Size 32 bit 0x0000_0000 gt 2 GByte 0 0 1 useg 3 5 Hae A 1 0 0x7FFF_FFFF y All valid user mode virtual addresses have their most significant bit cleared to 0 indicating that user mode can only access the lower half of the virtual memory map Any attempt to reference an address with the most significant bit set while in user mode causes an address error exception The system maps all references to useg through the TLB 4Kc core or FM 4Km and 4Kp cores For the 4Kc core the The virtual address is extended with the contents of the 8 bit ASID field to form a unique virtual address before translation Bit settings within the TLB ent
78. 32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 1 Debug Control Register Table 9 1 Debug Control Register Field Descriptions Continued Description Reset State Interrupt Enable in Normal Mode This bit provides the hardware and software interrupt enable for non debug mode in addition to other masking mechanisms O Interrupt disabled 1 Interrupts enabled depending on other enabling mechanisms Non Maskable Interrupt Enable for non debug mode 0 NMI disabled 1 NMI enabled NMI Pending Indication 0 No NMI pending 1 NMI pending Soft Reset Enable This bit allows the system to mask soft resets The core does not internally mask soft reset Rather the state of this bit appears on the EJ_SRstE external output signal allowing the system to mask soft resets if desired Probe Enable This bit reflects the ProbEn bit in the EJTAG Control Same value as register ProbEn in ECR 0 No accesses to dmseg allowed1 EJTAG probe services see Table 9 23 accesses to dmseg MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 123 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 2 Hardware Breakpoints Hardware breakpoints provide for the comparison by hardware of executed instructions and data load store transactions
79. 52 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 3 Exception Vector Locations Table 4 1 Priority of Exceptions Continued Exception Description Load TLB miss 4Kc core Load TLB hit to page with V 0 4Kc core Store TLB miss 4Kc core TLBS Store TLB hit to page with V 0 4Kc core TLB Mod Store to TLB page with D 0 4Kc core DBE Load or store bus error DDBL EJTAG data hardware breakpoint matched in load data compare 4 3 Exception Vector Locations The Reset Soft Reset and NMI exceptions are always vectored to location 0xBFCO_0000 Debug exceptions are vectored to location 0xBFC0_0480 or to location OxFF20_0200 if the ProbTrap bit is 0 or 1 respectively in the EJTAG Control register ECR Addresses for all other exceptions are a combination of a vector offset and a base address Table 4 2 gives the base address as a function of the exception and whether the BEV bit is set in the Status register Table 4 3 gives the offsets from the base address as a function of the exception Table 4 4 combines these two tables into one that contains all possible vector addresses as a function of the state that can affect the vector selection Table 4 2 Exception Vector Base Addresses Exception Status pry Reset Soft Reset NMI OxBFC0O_0000 Debug with ProbTrap 0 in the ECR OxBFC0
80. 9 3 2 1 Test Logic Reset State In the Test Logic Reset state the boundary scan test logic is disabled The test logic enters the Test Logic Reset state when the TMS input is held HIGH for at least five rising edges of TCK The BYPASS instruction is forced into the instruction register output latches during this state The controller remains in the Test Logic Reset state as long as TMS is HIGH 9 3 2 2 Run Test Idle State The controller enters the Run Test Idle state between scan operations The controller remains in this state as long as TMS is held LOW The instruction register and all test data registers retain their previous state The instruction cannot change when the TAP controller is in this state When TMS is sampled HIGH at the rising edge of TCK the controller transitions to the Select_DR state 9 3 2 3 Select_DR_Scan State This is a temporary controller state in which all test data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Capture_DR state A HIGH on TMS causes the controller to transition to the Select_IR state The instruction cannot change while the TAP controller is in this state 9 3 2 4 Select_IR_Scan State This is a temporary controller state in which all test data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitio
81. ACHE instruction The SYNC instruction may also be useful to software enforcing memory coherence as it flushes the 4K processor s write buffers MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter amp Power Management The MIPS32 4K processor cores offers a number of power management features including low power design active power management and power down modes of operation The core is a static design that supports a WAIT instruction designed to signal the rest of the device that execution and clocking should be halted reducing system power consumption during idle periods The core provides two mechanisms for system level low power support discussed in the following sections e Section 8 1 Register Controlled Power Management e Section 8 2 Instruction Controlled Power Management 8 1 Register Controlled Power Management The RP bit in the CPO Status register a standard software mechanism for placing the system into a low power state The state of the RP bit is available externally via the S7_RP signal Three additional pins S7_EXL SI_ERL and EJ_DebugM support the power management function by allowing the user to change the power state if an exception or error occurs while the core is in a low power state Setting the RP bit of the CPO Status register causes the core to assert the SZ _RP signal The external agent
82. AKC core sesssssessssssessessserserrsrrsressrssree 63 4 6 13 Bus Error Exception Instruction Fetch or Data Access ssseseeeeseeeseeseererssrerrsresrsrrerereereereserresreeesreee 63 4 6 14 Debug Software Breakpoint Exception ssessssseeserereesreessseeresessesrestsresrtrtnserssreresreestesrerteseereseeteseeresreet 64 4 615 Execution Exception System Call serseri enois iie e n E E EE EEEE R 64 4 6 16 Execution Exception Breakpoint sesessesesessessseesrssesresrsseereseesestesestestettsseerssresesreertesrereeseernseeteseeresreet 64 4 6 17 Execution Exception Reserved Instruction essseesesseeessereseseesrsresesrestrrrsreerssretestetsrenrerreeernseeresenresreet 64 4 6 18 Execution Exception Coprocessor Unusable sssesseseeeesseeessseesrsesesresrrrrsseerssrnresteestesrereneereseeresenresrent 65 4 6 19 Execution Exception Integer Overflow oo cee ceecseceseeeceseesecescesecesceeeeeeeseseaesseeeaeeseeeaesnaeaeenaes 65 4 6 20 Execution Exception Trap o eeececeeeecssesecsesseeseeseecsecaecaecacssecsacssecesceseceseeseseeeeseseaesseeeaecaaeeaesaeaeenaes 65 4 6 21 Debus Data Break EXCeptiony 6 e deassvpeensacesh cos sprsssesogtees ceusegveseseusdeebe dau E NEON K REREN EEn OEE eenean 66 4 6 22 TLB Modified Exception Data Access AKC core oo eeeseenessreeeseceerecesecencececessaeeeneesseeeeaeceseecsaeeeaeesee 66 4 7 Exception Handling and Servicing Flowcharts oo eee cesceeceseeseceseesecesceseceseeeeeeae
83. B Entries 1 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 77 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 78 5 2 3 EntryLo0 EntryLol CP0 Registers 2 and 3 Select 0 The pair of EntryLo registers act as the interface between the TLB and the TLBR TLBWI and TLBWR instructions For a TLB based MMU EntryLo0 holds the entries for even pages and EntryLo holds the entries for odd pages The contents of the EntryLo0 and EntryLo registers are undefined after an address error TLB invalid TLB modified or TLB refill exceptions These registers are only valid with the TLB 4Kc core They are reserved if the FM is implemented 4Km and 4Kp EntryLoo EntryLo1 Register Format 31 30 29 26 25 R 0 PFN 6 5 3 2 1 0 C DIV G Description Table 5 5 EntryLo0 EntryLo1 Register Field Descriptions Reset State Reserved Should be ignored on writes returns zero on read 0 These 4 bits are normally part of the PFN However since the core supports only 32 bits of physical address the PFN is only 20 bits wide Therefore bits 29 26 of this register must be written with zeros Page Frame Number Corresponds to bits 31 12 of the physical address Coherency attribute of the page See Table 5 6 Dirty or write enable bit indicating that the page has been written and or is writable If this bit is a
84. DDI Integer Add Immediate Rt Rs Immed ADDIU Unsigned Integer Add Immediate Rt Rs y Immed ADDU Unsigned Integer Add Rd Rs y Rt AND Logical AND Rd Rs amp Rt ANDI Logical AND Immediate Rt Rs amp 0j Il Immed Unconditional Branch Lg E Asembler idiom for BEQ 10 r0 offset PC int offset BAL Branch and Link GPR 31 PC 8 Asembler idiom for BGEZAL 10 offset PC int offset if Rs Rt BEQ Branch On Equal PC int offset if Rs Rt BEQL Branch On Equal Likely TO RUPA Ignore Next Instruction if Rs 31 BGEZ Branch on Greater Than or Equal To Zero PC int offset BGEZAL re on Greater Than or Equal To Zero And TR ee PC int offset MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 171 Chapter 11 MIPS32 4K Processor Core Instructions 172 Instruction Table 11 7 Instruction Set Continued Description Function BGEZALL Branch on Greater Than or Equal To Zero And Link Likely GPR 31 PC 8 if Rs 31 PC int offset else Ignore Next Instruction BGEZL Branch on Greater Than or Equal To Zero Likely if Rs 31 PC int offset else Ignore Next Instruction BGTZ BGTZL Branch on Greater Than Zero Branch on Greater Than Zero Likely if Rs 31 amp amp Rs 0 PC int offset if Rs 31 amp amp Rs 0 PC int offset else Ignore Next Instruct
85. DR DBAnppa amp amp lt all 0 s gt BAI amp BYTELANE The size of DBCnga and BYTELANE is 4 bits Data value compare is included in the match condition for the data breakpoint depending on the bytes BYTELANE as described above accessed by the transaction and the contents of breakpoint registers The DB_no_value_compare is shown below DB_no_value_compare lt all 1 s gt DBCnpyy DBCnga BYTELANE The size of DBCnpy yy DBCngay and BYTELANE is 4 bits In case data value compare is required DB_no_value_compare is false then the data value from the data bus DATA is compared and masked with the registers for the data breakpoint The endianess is not considered in these match equations for value as the compare uses the data bus value directly thus debug software is responsible for setup of the breakpoint corresponding with endianess DB_value_match DATA 7 0 DBVnppy 7 0 BYTELANE 0 DBCnppyjo DBCMgarjo amp amp DATA 15 8 DBVnppyris g BYTELANE 1 DBCngpyj1 DBCrgarj1 amp amp DATA 23 16 DBVnpsy o3 16 BYTELANE 2 DBCngryj2 DBCngarj2 amp amp DATA 31 24 DBVnppyj3i 24 BYTELANE 3 DBCngmm 3 DBCMgar 3 The match for a data breakpoint is always precise since the match expression is fully evaluated at the time the load
86. E 0 m A Oe Rew l l i al MUL z l l Mult Macc 16x16 32x16 CPA RegW 5l CPA a l l Ry Mult Mace Mult Mace 32x32 CPA RegwW BI Divide l l il Sign Adjust l l Divide J Sign Adjust Regw l i I Tag and Data read TLB Look up Instruction Decode Register file read Instruction Address Calculation stage 1 and 2 Arithmetic Logic and Shift operations Data Address Calculation D Tag and Data read D TLB Look up Load data aligner Register file write or HI LO write The MUL instruction Uses MDU Pipeline write Reg file Carry Propagate Adder Multiply and Multiply Accumulate instructions Divide instructions Last stage of Divide is a sign adjustment One or more stall cycles Figure 2 1 4Kc Core Pipeline Stages Figure 2 2 shows the operations performed in each pipeline stage of the 4Km processor core 1 I 1 l l I E M A WwW I i I Cache A gt E Bypass l l SEBYpASS l l I Dec RegRd I Cache RegRd ALU Op l l l I AC1 I AC2 IDec D AC D Cache Align RegW El Z ALU Op l a l lt i D AC LACI L AC2 l 7 r i D Cache r K A gt E Bypass Ali t ign i l MUL RegW RegW l l MUL l al Mult Macc 16x16 32x16 Carry Prop Add RegW l CPA p l E Mult Mace i i Mult Mace 32x32 Carry Pr
87. E E E 38 3 3 Translation Lookaside Buffer 4Kc Core Only esssssesessssessssssssseseseeserssessrtssesstestesstesressesseesseetesersetseteseeseeeseeseeenes 40 iv MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All right reserved 3 3L Joint N E o AE 8 eles Mesegiesvadl alvin hetebeeiedl te Relea hel A E 40 3 3 2 Instruction GELB oe sceieces ddsck EEEN EOE EEEE EE cues sd estisspaiedaues gues EOE 42 3 3 3 Datars D B s E E A ie akin sled eva te Ren ea 43 3 4 Virtual to Physical Address Translation 4K Core oe eeecesscceseessseceececereessceseneessecesceceueecaaeceaeeceeeeeneeeeeeesaeceneeeeaes 43 3 4 1 Hits Misses and Multiple Matches eee eeseeceessecesceceseecseceececeeesneeeeeeesaeceeecsaeecaaeceaeeceeeeaeceeeeesaeeeseeenees 45 3 4 2 Page Sizes and Replacement Algorithm oo ec ceeesecseeneceecesecesceeeeeeeeeeeeseseecaeesaecaecsaecsecaeeneseeeeseees 46 3 4 3 TLB Instructions 05 2 a E ie a Mase ae ve ee aS 47 3 5 Fixed Mapping MMU 4Km amp 4Kp Cores uresen inneir iieo e EE EE R E EE 47 3 6 System Control Coprocessor arseen eiaa E aE a aR TEE EE E e E o eeen Ea EEE ASES EEE EaR Ein ea 49 Chapter 4 Exceptions r lie ee eee ee ee ee AA Re a ee et 51 41 Exception Conditions vsere E e E SA r A a E E E E E R a 51 A 2 EXCepuon ee n SA m A E eee AES SESE E ios T Co dia eel 52 4 3 Exception Vector Locations spse ena e rees e a EE e spied etd REEN E e
88. IZES nren ea ean r E E E EN Ea RE E EE N A EE 116 Table 9 1 Debug Control Register Field Descriptions 0 0 0 0 eee csesseceeceseceeceseeeceseesecesceesceseeaecaeeseeeneesaecaaesaecasenaeenees 122 Table 9 2 Overview of Status Register for Instruction Breakpoints seesesssesseseesresssrstsresessterrersrsreenseseseetsserrersrseerresse 125 Table 9 3 Overview of Registers for each Instruction Breakpoint sssesessseeeseesresssrstsresssrtterersrereessesesretssetrersrseeerese 125 Table 9 4 Overview of Status Register for Data Breakpoints 0 cc ceceeesecsecseesessecseeeceseeaecesseceaeneeseesecneeseeseeaecaseneaeeas 126 Table 9 5 Overview of Registers for each Data Breakpoint 0 ee eeceeseeecnecseeseesecseeecssceaecessecsaeseeseesecnesseeseeaecaeeeeeneeas 126 Table 9 6 Addresses for Instruction Breakpoint Registers cceccecssssesececseeessecsseecescsaecesscceaeseeseesecnecaeeseaecaeeeeaeeas 130 Table 9 7 IBS Register Field Descriptions 00 0 0 eee ec eecceseceseeeeesecseesaecseesaecaecsaeceecsaeeseesseeeeeaeseeeeseseaecaeeeaecaaesaecasenaeenees 131 Tabl e9 8 IBAN Register Field DES CLIPtlONS reena re n setae NE AEREE Ea SEARE NEEE 132 Table 9 9 IBMn Register Field Descriptions 00 0 eee eceeeeeeseeeeecseesecacesaecaecuaeceeceseeseesseeseseaeeeeeeseseaecaeseaecaassaecaeenaeenees 133 Table 9 10 IBASTDn Register Field Descriptions 200 0 eee ceeeseescessecnsesaeceecaecneceseeseeseeeceseseeeeseseaecaeeeaecaassaecsaeaee
89. Kc and 4Km Cores The 32x16 multiply operation begins in the last phase of the E stage which is shared between the integer and MDU pipelines In the latter phase of the E stage the rs and rt operands arrive and the booth recoding function occurs at this time The multiply calculation requires one clock and occurs in the Myqpy stage In the Ampu Stage the carry propagate add function occurs and the operation is completed The result is written back to the HI LO register pair in the first half of the Wypy stage Figure 2 9 shows a diagram of a 32x16 multiply operation Clock 1 2 3 4 J E Plt Muu gt Amu gt Wuv gt Booth Array CPA Reg wAl Figure 2 9 MDU Pipeline Flow During a 32x16 Multiply Operation 2 5 2 32x32 Multiply 4Kc and 4Km Cores The 32x32 multiply operation begins in the last phase of the E stage which is shared between the integer and MDU pipelines In the latter phase or the E stage the rs and rt operands arrive and the booth recoding function occurs at this time The multiply calculation requires two clocks and occurs in the Mypv Stage In the Ampu stage the carry propagate add CPA function occurs and the operation is completed The result is written back to the HI LO register pair in the first half of the Wyypy stage Figure 2 10 shows a diagram of a 32x32 multiply operation Clock 1 2 3 4 5 J E Pit Muu Pl Muu Pl Amu gt E Wwou gt Figure 2 10 MDU Pipeline Flow During a 32x32 Multip
90. Mis TECHNOLOGIES MIPS32 4K Processor Core Family Software User s Manual Document Number MD00016 Revision 01 18 November 15 2004 MIPS Technologies Inc 1225 Charleston Road Mountain View CA 94043 1353 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Copyright 2000 2002 MIPS Technologies Inc All rights reserved Unpublished rights if any are reserved under the Copyright Laws of the United States of America If this document is provided in source format i e in a modifiable form such as in FrameMaker or Microsoft Word format then its use and distribution is subject to a written agreement with MIPS Technologies Inc MIPS Technologies UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY WITHOUT THE EXPRESS WRITTEN CONSENT OF MIPS TECHNOLOGIES This document contains information that is proprietary to MIPS Technologies Any copying reproducing modifying or use of this information in whole or in part which is not expressly permitted in writing by MIPS Technologies or a contractually authorized third party is strictly prohibited At a minimum this information is protected under unfair competition and copyright laws Violations thereof may result in criminal penalties and fines MIPS Technologies or any contractually authorized third party reserves the right to change the information contained in this document to improve function design or otherwise
91. No arithmetic exception occurs under any circumstances 10 7 6 MSUBU Multiply and Subtract Unsigned Word The MSUBU instruction multiplies two unsigned words and subtracts the result from the HI LO register pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as unsigned values to produce a 64 bit result The product is subtracted from the 64 bit concatenated values in the HI and LO register pair The resulting value is then written back to the HI and LO registers No arithmetic exception occurs under any circumstances MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 167 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 10 Instruction Set Overview 10 7 7 MUL Multiply Word The MUL instruction multiplies two words and writes the result to a GPR The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as signed values to produce a 64 bit result The least significant 32 bits of the product are written to the GPR rd The contents of the HI and LO register pair are not defined after the operation No arithmetic exception occurs under any circumstances 10 7 8 SSNOP Superscalar Inhibit NOP The MIPS32 4K processor cores treats this instruction as a regular NOP 168 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technolog
92. None Entry Vector Used Reset OxBFCO_0000 Operation StatuSpry lt 1 StatuSrg lt 0 StatuSsg lt 0 StatuSymr lt 1 StatuSpp lt 1 if InstructionInBranchDelaySlot then ErrorEPC lt PC 4 else ErrorEPC lt PC endif PC lt O0xBFCO_0000 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 59 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions 4 6 6 Machine Check Exception 4Kc core A machine check exception occurs when the processor detects an internal inconsistency The following condition causes a machine check exception e The detection of multiple matching entries in the TLB in a TLB based MMU The core detects this condition on a TLB write and prevents the write from being completed The TS bit in the Status register is set to indicate this condition This bit is only a status flag and does not affect the operation of the device Software clears this bit at the appropriate time This condition is resolved by flushing the conflicting TLB entries The TLB write can then be completed Cause Register ExcCode Value MCheck Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 6 7 Interrupt Exception 60 The interrupt exception occurs when one or more of the eight interrupt requests is enabled by the Status register and the interrupt input is asserted The delay from
93. O_0480 Debug with ProbTrap 1 in the ECR OxFF20_0200 in dmseg handled by probe and not system memory Other 0x8000_0000 OxBFC0_0200 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 53 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions Table 4 3 Exception Vector Offsets Exception Vector Offset TLB refill EXL 0 4Kc core Reset Soft Reset NMI 0x000 0x000 uses reset base address General Exception 0x180 Interrupt Causey 1 0x200 Table 4 4 Exception Vectors EJTAG Exception BEV EXL IV ProbTrap Vector Reset Soft Reset NMI Debug OxBFC0O_0000 OxBFC0O_0480 Debug OxFF20_0200 in dmseg TLB Refill 4Kc core 0x8000_0000 TLB Refill 4Kc core TLB Refill 4Kc core TLB Refill 4Kc core Interrupt 0x8000_0180 x x 0 Xx 0x8000_0180 Interrupt x 0x8000_0200 Interrupt Xx OxBFC0O_0380 Interrupt All others All others OxBFC0O_0400 1 x Note x denotes don t care 4 4 General Exception Processing With the exception of Reset Soft Reset NMI and Debug exceptions which have their own special processing as described below exceptions have the same basic processing flow If the EXL bit in the Status register is cleared the EPC register is loaded with the PC at which execution will be restarted and the BD
94. PS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 2 Random Register CPO Register 1 Select 0 The Random register is a read only register whose value is used to index the TLB during a TLBWR instruction The width of the Random field is calculated in the same manner as that described for the Index register above The value of the register varies between an upper and lower bound as follow e A lower bound is set by the number of TLB entries reserved for exclusive use by the operating system the contents of the Wired register The entry indexed by the Wired register is the first entry available to be written by a TLB Write Random operation An upper bound is set by the total number of TLB entries minus 1 The Random register is decremented by one almost every clock wrapping after the value in the Wired register is reached To enhance the level of randomness and reduce the possibility of a live lock condition an LFSR register is used that prevents the decrement pseudo randomly The processor initializes the Random register to the upper bound on a Reset exception and when the Wired register is written This register is only valid with the TLB 4Kc core It is reserved if the FM is implemented 4Km and 4Kp Random Register Format 31 4 3 0 0 Random Table 5 4 Random Register Field Descriptions Fields Description Reset State Must be written as zero returns zero on read 0 TLB Random Index TL
95. Reset OxBFCO_0000 Operation Random lt TLBEntries 1 Wired lt 0 Config lt ConfigurationState StatuSpp lt 0 StatuSpry lt 1 StatuSrgs lt 0 StatuScop lt 0 Statusyyr lt 0 StatuSpp lt 1 WatchLo lt 0 WatchLop lt 0 WatchLoy lt 0 if InstructionInBranchDelaySlot then ErrorEPC lt PC 4 else ErrorEPC lt PC endif PC lt O0xBFCO0_0000 4 6 2 Soft Reset Exception A soft reset exception occurs when the S7_Reset signal is asserted to the processor This exception is not maskable When a soft reset exception occurs the processor performs a subset of the full reset initialization Although a soft reset exception does not unnecessarily change the state of the processor it may be forced to do so in order to place the processor in a state in which it can execute instructions from uncached unmapped address space Since bus cache or other operations may be interrupted portions of the cache memory or other processor state may be inconsistent In addition to any hardware initialization required the following state is established on a soft reset exception e The BEV TS SR NMI and ERL fields of the Status register are initialized to a specified state e The ErrorEPC register is loaded with PC 4 if the state of the processor indicates that it was executing an instruction in the delay slot of a branch Otherwise the ErrorEPC register is loaded with PC Note that thi
96. SC If either of the following events occurs between the execution of LL and SC the SC may succeed or it may fail the success or failure is not predictable Portable programs should not cause one of these events e A load store or prefetch is executed on the processor executing the LL SC e The instructions executed starting with the LL and ending with the SC do not lie in a 2048 byte contiguous region of virtual memory The region does not have to be aligned other than the alignment required for instruction words The following conditions must be true or the result of the SC is undefined e Execution of SC must have been preceded by execution of an LL instruction e A RMW sequence executed without intervening exceptions must use the same address in the LL and SC The address is the same if the virtual address physical address and cache coherence algorithm are identical MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 191 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 11 MIPS32 4K Processor Core Instructions Store Conditional Word cont SC 192 Atomic RMW is provided only for cached memory locations The extent to which the detection of atomicity operates correctly depends on the system implementation and the memory access type used for the location MP atomicity To provide atomic RMW among multiple processors all accesses to the location must be made with a memory
97. Software User s Manual Revision 01 18 163 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 10 Instruction Set Overview I Type Immediate 31 2625 2120 1615 0 op ts ot immediate J Type Jump 31 26 25 0 op target R Type Register 31 2625 2120 1615 1110 65 0 op rs rt rd sa funct op 6 bit operation code TS 5 bit source register specifier i 5 bit target source destination register or branch condition mimnediit 16 bit immediate value branch displacement or address displacement target 26 bit jump target address rd 5 bit destination register specifier sa 5 bit shift amount funct 6 bit function field Figure 10 1 Instruction Formats 10 2 Load and Store Instructions Load and store are immediate I type instructions that move data between memory and the general registers The only addressing mode that load and store instructions directly support is base register plus 16 bit signed immediate offset 10 2 1 Scheduling a Load Delay Slot A load instruction that does not allow its result to be used by the instruction immediately following is called a delayed load instruction The instruction slot immediately following this delayed load instruction is referred to as the load delay slot In the 4K cores the instruction immediately following a load instruction can use the contents of the loaded register however in such cases hardware interlocks insert additional real cycles Alt
98. This bit must be ignored on writes and read as zero bit must be ignored on writes and read as zero Used to enable reverse endian memory references while the processor is running in user mode 0 User mode uses configured endianness Undefined 1 User mode uses reversed endianness Kernel or debug mode references are not affected by the state of this bit This bit must be written as zero returns zero on read Controls the location of exception vectors 0 Normal 1 Bootstrap TLB shutdown This bit is set if a TLBWI or TLBWR instruction is issued that would cause a TLB shutdown condition if allowed to complete This bit is only used in the 4Kc processor and is reserved in the 4Kp and 4Km processors Software can only write a 0 to this bit to clear it and cannot force a 0 1 transition Indicates that the entry through the reset exception vector was due to a Soft Reset 1 for Soft Reset 0 otherwise 0 Not Soft Reset NMI or hard reset 1 Soft Reset Software can only write a 0 to this bit to clear it and cannot force a 0 1 transition 88 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers Table 5 15 Status Register Field Descriptions Continued Read Description Write Reset State Indicates that the entry through the reset exception vector was due to an NMI 0 Not NMI so
99. VAddr 14 0000_0000_1111 64KB VAddr 16 0000_0011_1111 256KB VAddr 18 0000_1111_1111 1MB VAddr 20 0011_1111_1111 4MB VAddr 22 1111_1111_1111 16MB VAddr 24 The PageMask column above show all the legal values for PageMask Because each pair of bits can only have the same value the physical entry in the JTLB will only save a compressed version of the PageMask using only 6 bits This is however transparent to software which will always work with a 12 bit field VPN2 31 13 Virtual Page Number divided by 2 This field contains the upper bits of the virtual page number Because it represents a pair of TLB pages it is divided by 2 Bits 31 25 are always included in the TLB lookup comparison Bits 24 13 are included depending on the page size defined by PageMask ASID 7 0 Global Bit When set indicates that this entry is global to all processes and or threads and thus disables inclusion of the ASID in the comparison Address Space Identifier Identifies which process or thread this TLB entry is associated with MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 41 Chapter 3 Memory Management Table 3 7 TLB Data Entry Fields Field Name Description Physical Frame Number Defines the upper bits of the physical address For page sizes larger than 4 KBytes only a subset of these bits is actually used
100. _TimerInt pin can be fed back into the core on one of the interrupt pins to generate an interrupt Traditionally this has been done by multiplexing it with hardware interrupt 5 to set interrupt bit IP 7 in the Cause register For diagnostic purposes the Compare register is a read write register In normal use however the Compare register is write only Writing a value to the Compare register as a side effect clears the timer interrupt Compare Register Format 31 0 Compare Table 5 14 Compare Register Field Description Name Bit s Description Write Reset State Compare 31 0 Interval count compare value R W Undefined MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 11 Status Register CPO Register 12 Select 0 The Status register SR is a read write register that contains the operating mode interrupt enabling and the diagnostic states of the processor Fields of this register combine to create operating modes for the processor as follows Interrupt Enable Interrupts are enabled when all of the following conditions are true e IE 1 e EXL 0 e ERL 0 e DM 0 If these conditions are met the settings of the IM and JE bits enable the interrupt Operating Modes If the DM bit in the Debug register is 1 the processor is in debug mode Otherwise the processor is in either kernel o
101. a is returned to the core the critical word is written to the instruction register for immediate use The bypass mechanism allows the core to use the data once it becomes available as opposed to having the entire cache line written to the instruction cache then reading out the required word Figure 2 4 shows a timing diagram of an instruction cache miss for the 4Kc core Figure 2 5 shows a timing diagram of an instruction cache miss for the 4Km and 4Kp cores L L L L E i E E E Cache N l i RegRd ALU Op l TLB I TLB B ASel Bus IC Bypass Dec i l T A1 I A2 Contains all of the cycles that address and data are utilizing the bus Figure 2 4 Instruction Cache Miss Timing 4Kc core 14 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 3 Data Cache Miss LOLOT LOOT LOT LOT E ee eand i i RegRd ALU Op l Cache B ASel_ Bus IC Bypass Dec i i i l i I A I A2 Contains all of the cycles that address and data are utilizing the bus Figure 2 5 Instruction Cache Miss Timing 4Km and 4Kp cores 2 3 Data Cache Miss When the data cache is indexed the data address is translated to determine if the required data resides in the cache A data cache miss occurs when the requested data address does not reside in the data cache When a data cache miss is detected in the M st
102. ache Miss Section 2 3 Data Cache Miss Section 2 4 Multiply Divide Operations Section 2 5 MDU Pipeline 4Kc and 4Km Cores Section 2 6 MDU Pipeline 4Kp Core Only Section 2 7 Branch Delay Section 2 8 Data Bypassing Section 2 9 Interlock Handling Section 2 10 Slip Conditions Section 2 11 Instruction Interlocks Section 2 12 Instruction Hazards 2 1 Pipeline Stages The pipeline consists of five stages e Instruction I stage e Execution E stage e Memory M stage e Align Accumulate A stage e Writeback W stage All three cores implement a Bypass mechanism that allows the result of an operation to be sent directly to the instruction that needs it without having to write the result to the register and then read it back Figure 2 1 shows the operations performed in each pipeline stage of the 4Kc processor MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 Chapter 2 Pipeline i I i I Cache l I TLB I E M A WwW ED ec A gt E Bypass SEB RegRd l 1 l taci rac2 I Cache RegRd ALU Op ALU Op I TLB IDec D AC D Cache Align RegwW v DAG El gt i D TLB El l l Ell D Cache i I AC1 1 AC2 l Fal TT A gt EB l 2I a l x 1 pe Bypass Align i LES
103. age D TLB the core transitions to the A stage The pipeline stalls in the A stage until the miss is resolved requested data is returned The bus interface unit arbitrates between multiple requests and selects the correct address to be driven onto the bus B ASel in Figure 2 6 and Figure 2 7 The core drives the selected address onto the bus The number of clocks required to access the bus is determined by the access time of the array containing the data The number of clocks required to return the data once the bus is accessed is also determined by the access time of the array Once the data is returned to the core the critical word of data passes through the aligner before being forwarded to the execution unit and register file The bypass mechanism allows the core to use the data once it becomes available as opposed to having the entire cache line written to the data cache then reading out the required word Figure 2 6 shows a timing diagram of a data cache miss for the 4Kc core Figure 2 7 shows a timing diagram of a data cache miss for the 4Km and 4Kp cores i i f i RegR ALUI D Cache D TLB l l l l l i B ASel Bus U DC Bypass Align RegW l l l i i l l l Contains all of the time that address and data are utilizing the bus Figure 2 6 Load Store Cache Miss Timing 4Kc core MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 15 Copyright
104. ain in a functional mode and selects the Bypass register to be connected between TDI and TDO The BYPASS instruction allows serial data to be transferred through the processor from TDI to TDO without affecting its operation The bit code of this instruction is defined to be all ones by the IEEE 1149 1 standard Any unused instruction is defaulted to the BYPASS instruction 9 3 3 2 IDCODE Instruction The IDCODE instruction allows the processor in its functional mode and selects the Device Identification ID register to be connected between TDI and TDO The Device ID register is a 32 bit shift register containing information regarding the IC manufacturer device type and version code Accessing the Identification Register does not interfere with the operation of the processor Also access to the Identification Register is immediately available via a TAP data scan operation after power up when the TAP has been reset with on chip power on or through the optional TRST_N pin 9 3 3 3 IMPCODE Instruction This instruction selects the Implementation register for output which is always 32 bits 9 3 3 4 ADDRESS Instruction This instruction is used to select the Address register to be connected between TDI and TDO The EJTAG Probe shifts 32 bits through the TDI pin into the Address register and shifts out the captured address via the TDO pin 9 3 3 5 DATA Instruction This instruction is used to select the Data register to be connected between TDI
105. ain memory to be accessed in the presence of cache errors Behavior is UNDEFINED if ERL is set while executing code in useg kuseg MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 89 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers Table 5 15 Status Register Field Descriptions Continued Read Description Write Reset State Exception Level Set by the processor when any exception other than a Reset Soft Reset or NMI exception is taken 0 normal level 1 exception level When EXL is set R W Undefined The processor is running in kernel mode Interrupts are disabled In the 4Kc core TLB refill exceptions use the general exception vector instead of the TLB refill vector EPC is not updated if another exception is taken Interrupt Enable Acts as the master enable for software and hardware interrupts R W Undefined 0 disables interrupts 1 enables interrupts 90 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 12 Cause Register CPO Register 13 Select 0 The Cause register primarily describes the cause of the most recent exception In addition fields also control software interrupt requests and the vector through which interrupts are dispatched With the exception of the IP 1 0 TV and WP fields all fields in the C
106. al EJTAG Debug Single Step EJTAG Debug Interrupt Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register Asserting edge of SI_NMI signal Machine Check TLB write that conflicts with an existing entry 4Kc core Interrupt Assertion of unmasked HW or SW interrupt signal Deferred Watch Deferred Watch unmasked by KIDM gt KIDM transition EJTAG debug hardware instruction break matched WATCH A reference to an address in one of the watch registers fetch Fetch address alignment error AdEL User mode fetch reference to kernel address Fetch TLB miss 4Kc core TLBL Fetch TLB hit to page with V 0 4Kc core IBE Instruction fetch bus error Execution of a Reserved Instruction Execution of an arithmetic instruction that overflowed Ov Tr Execution of a trap when trap condition is true DDBL DDBS EJTAG Data Address Break address only or EJTAG Data Value Break on Store address and value WATCH A reference to an address in one of the watch registers data Load address alignment error AdEL User mode load reference to kernel address Store address alignment error AdES User mode store to kernel address C DBp EJTAG Breakpoint execution of SDBBP instruction Sys Execution of SYSCALL instruction Bp Execution of BREAK instruction CpU Execution of a coprocessor instruction for a coprocessor that is not enabled a
107. amily Software User s Manual Revision 01 18 11 3 Instruction Set Write Indexed TLB Entry Operation i amp Index L mask lt PageMaskyas ven2 lt EntryHivypy2 as p amp EntryHigsqp c amp EntryLol and EntryLo0g pry amp EntryLolppy TLB TLB TLB TLB TLB TLB TEB TLB TLB TLB TLB TLB Exceptions H H H H H H H H H H H H ci Entry p amp Entry Olc Olp vi Entry Oly prno lt EntryLo0Opry co amp Entry 006 po amp Entry 100p yo lt Entry 00y Coprocessor Unusable MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved TLBWI 199 Chapter 11 MIPS32 4K Processor Core Instructions Write Random TLB Entry TLBWR 31 26 25 24 6 5 0 COPO CO 0 TLBWR 010000 1 000 0000 0000 0000 0000 000110 6 1 19 6 Format TLBWR MIPS32 Purpose 200 To write a TLB entry indexed by the Random register Description The TLB entry pointed to by the Random register is written from the contents of the EntryHi EntryLo0 EntryLo1 and PageMask registers The information written to the TLB entry may be different from that in the EntryHi EntryLo0 and EntryLo registers in that e The value returned in the G bit in both the EntryLo0 and EntryLo registers comes from the single G bit in the TLB entry R
108. an not assume that there will never be a reference to dmseg if the ProbEn bit in the DCR register is 0 because there is an inherent race between the debug software sampling the ProbEn bit as 1 and the probe clearing it to 0 3 3 Translation Lookaside Buffer 4Kc Core Only 40 The following subsections discuss the TLB memory management scheme used in the 4Kc processor core The TLB consists of one joint and two micro address translation buffers e 16 dual entry fully associative Joint TLB JTLB e 3 entry fully associative Instruction micro TLB ITLB e 3 entry fully associative Data micro TLB DTLB 3 3 1 Joint TLB The 4Kc core implements a 16 dual entry fully associative Joint TLB that maps 32 virtual pages to their corresponding physical addresses The JTLB is organized as 16 pairs of even and odd entries containing pages that range in size from 4 KBytes to 16 MBytes into the 4 GByte physical address space The purpose of the TLB is to translate virtual addresses and their corresponding Address Space Identifier ASID into a physical memory address The translation is performed by comparing the upper bits of the virtual address along with the ASID bits against each of the entries in the tag portion of the JTLB structure Because this structure is used to translate both instruction and data virtual addresses it is referred to as a joint TLB The JTLB is organized in page pairs to minimize its overall size Each virtual tag entry co
109. and TDO The EJTAG Probe shifts 32 bits of TDI data into the Data register and shifts out the captured data via the TDO pin 9 3 3 6 CONTROL Instruction This instruction is used to select the EJTAG Control register to be connected between TDI and TDO The EJTAG Probe shifts 32 bits of TDI data into the EJTAG Control register and shifts out the EJTAG Control register bits via TDO 9 3 3 7 ALL Instruction This instruction is used to select the concatenation of the Address and Data register and the EJTAG Control register between TDI and TDO It can be used in particular if switching instructions in the instruction register takes too many TCK cycles The first bit shifted out is bit 0 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 149 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support TDI Address 0 ac Data 0 IK L EJTAG Control o gt TDO Figure 9 6 Concatenation of the EJTAG Address Data and Control Registers 9 3 3 8 EJTAGBOOT Instruction When the EJTAGBOOT instruction is given and Update IR state is left then the reset value of the ProbTrap ProbEn and EjtagBrk bits in the EJTAG Control register are set to 1 after hard or soft reset This EJTAGBOOT indication is effective until NORMALBOOT instruction is given TRST_N is asserted or rising edge of TCK occurs when TAP controller is in Test Logic Reset state It is thereby p
110. anism whereby a programmable number of mappings can be locked into the TLB via the CPO Wired register thus avoiding random replacement Please refer to Section 5 2 6 Wired Register CPO Register 6 Select 0 on page 82 for further details For valid address Virtual Address Input space see the section describing Modes of operation in this chapter User Address Exception Address TLB Noncacheable TLB TLB Modified Invalid Refill Physical Address Output Figure 3 10 TLB Address Translation Flow in the 4Kc Processor Core MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 5 Fixed Mapping MMU 4Km amp 4Kp Cores 3 4 3 TLB Instructions Table 3 8 lists the 4Kc core s TLB related instructions Refer to Chapter 11 MIPS32 4K Processor Core Instructions on page 169 for more information on these instructions Table 3 8 TLB Instructions Op Code Description of Instruction TLBP Translation Lookaside Buffer Probe TLBR Translation Lookaside Buffer Read TLBWI Translation Lookaside Buffer Write Index TLBWR Translation Lookaside Buffer Write Random 3 5 Fixed Mapping MMU 4Km amp 4Kp Cores The 4Km and 4Kp cores implement a simple Fixed Mapping FM memory management unit that is smaller than the 4Kc TLB and more easily synthesized Like the 4Kc TLB the FM perform
111. anual Revision 01 18 161 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 162 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 10 Instruction Set Overview This chapter provides a general overview on the three CPU instruction set formats of the MIPS architecture Immediate Jump and Register Refer to Chapter 11 MIPS32 4K Processor Core Instructions on page 169 for a complete listing and description of instructions This chapter discusses the following topics e Section 10 1 CPU Instruction Formats e Section 10 2 Load and Store Instructions e Section 10 3 Computational Instructions Section 10 4 Jump and Branch Instructions Section 10 5 Control Instructions Section 10 6 Coprocessor Instructions Section 10 7 Enhancements to the MIPS Architecture 10 1 CPU Instruction Formats Each CPU instruction consists of a single 32 bit word aligned on a word boundary There are three instruction formats immediate I type jump J type and register R type as shown in Figure 10 1 The use of a small number of instruction formats simplifies instruction decoding allowing the compiler to synthesize more complicated and less frequently used operations and addressing modes from these three formats as needed MIPS32 4K Processor Core Family
112. as zero returns zero on read Break status for breakpoint n is at BS n with n as 0 to 3 The BS 3 0 bit is set to 1 when the condition for the corresponding R W Undefined breakpoint has matched Note a Based on actual hardware implemented Note b In case of only 2 Instruction breakpoints bit 2 and 3 become reserved MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 131 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 2 8 2 Instruction Breakpoint Address n BAn Register Compliance Level Implemented only for implemented instruction breakpoints The Instruction Breakpoint Address n BAn register has the address used in the condition for instruction breakpoint n IBAn Register Format IBA Table 9 8 IBAn Register Field Descriptions Fields Read Name Description Write Reset State IBA 31 0 Instruction breakpoint address for condition R W Undefined 132 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 8 3 Instruction Breakpoint Address Mask n IBMn Register Compliance Level Implemented only for implemented instruction breakpoints The Instruction Breakpoint Address Mask n BMn register has the mask for address compare used in the condition for instruction breakpoi
113. asato ae ashe ee ei a ee aes 2 E2 Block Dia rainy a see ceies saves eetthsewsseteskdseuseeveae dh E E E E A E E a E E R 3 1 3 Required Loric BlOCKS nioi n ech E ead ste ate a gpI Sp oe Na aes Bo a E EE E eh 4 V3 1 EX OCULLOD DA ai i aana EE EENE EASE E EE E EENE EE ae nen 4 1 3 2 Multiply Divide Unit MDU sensasine iar e a a e a E ea a Eea AEE REEE 5 1 3 3 System Control Coprocessor CPO sinoi A enean ne a E E aR aes E E R neon aS 5 1 3 4 Memory Management Unit MMU oo eee ce cece cesceseeeeceseeeeeeseeeaeeseecaecaaecaecsacsaecsacseseeeeseseeseseseaeeaeeeneeags 5 1 35 Cache Controllers site seis A E SEESE E E E E E EE E EEE 7 1 3 6 Bus Interface Unit BIW enmener e aE eek tie eee a eae iat 7 1 3 7 Power Management sarsi E E lems seseouie at iauesethas even N R E E intents 7 14 Optional Logic Blocks n 3 4 has hetiecteskg Rislest nN BG ask ies ahs A te ng EN ads BA en A Ree Ree 8 1 41 Instruction Cache vesecccesdsshecesy coves sours ov ecesapeesd cvesseuesseusece ove duedh coeds odvath codegscptes tues seucesetcsaggusch OEE EROARE SERERE BANOS 8 1 4 2 Data Caches a n a E A eoes Waa ea ee beach ta vad ese van tee E ENA AEN HetbTet tds 8 1 43 EJTAG Controler rinna E A AA E cacouth E E EE ions EE E E EE 8 Chapter 2 Pipe me ive EEE E EE EEE EE E O EEE EEE EEE 11 2I Pipeline Sa ET aes i Aiea kava cee a ER gk te ee akin 11 Zt Stage Instruct on Fetch c si avesessaee sesscna n E ed E ss uinvon RE E E E S R 13 2E ESt ge EXCcuuone oreiro a n
114. atches the ASID value in the EntryHi register cause a watch exception The optional mask field provides address masking to qualify the address specified in WatchLo WatchHi Register Format 31 30 29 24 23 16 15 1211 3 2 0 0 G 0 ASID 0 MASK 0 Table 5 25 WatchHi Register Field Descriptions Fields Name Description Read Write Reset State 0 Must be written as zero returns zero on read 0 0 4Kc core If this bit is one any address that matches that specified in the WatchLo register causes a watch exception If this bit is zero the ASID field of the WatchHi register must 4Kc core R W G match the ASID field of the EntryHi register to cause a watch Undefined exception 4Km 4Kp cores 0 4Km 4Kp cores Must be written as zero returns zero on read 0 Must be written as zero returns zero on read 0 4Kc core ASID value which is required to match that in the 4Ke core R W ASID EntryHi register if the G bit is zero in the WatchHi register Undefined 4Km 4Kp cores Must be written as zero returns zero on read sue Core 0 Must be written as zero returns zero on read 0 0 Bit mask that qualifies the address in the WatchLo register Any Mask bit in this field that is a set inhibits the corresponding address R W Undefined bit from participating in the address match 0 i Must be written as zero returns zero on read 0 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18
115. ate oo int Immed rapException TLTIU Trap if Less Than Immediate Unsigned ie lt uns Immed rapException if uns Rs lt uns Rt TLTU Trap if Less Than Unsigned TrapException if Rs Rt TNE Trap if Not Equal TrapException TNEI Trap if Not Equal Immediate ae Gnt immed rapException WAIT Wait for Interrupts Stall until interrupt occurs MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 175 Chapter 11 MIPS32 4K Processor Core Instructions 176 Table 11 7 Instruction Set Continued Instruction Description Function XOR Exclusive OR Rd Rs Rt XORI Exclusive OR Immediate Rt Rs uns Immed MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Perform Cache Operation CACHE 31 26 25 21 20 16 15 0 CACHE base op offset 101111 6 5 5 16 Format CACHE op offset base MIPS32 Purpose To perform the cache operation specified by op Description The 16 bit offset is sign extended and added to the contents of the base register to form an effective address The effective address is used in one of the following ways based on the operation to be performed and the type of cache as described in the following table Table 11 8 Usage of Effective Address
116. ates Normally the Shift state follows the Capture state so that test data or status information can be shifted out for inspection and new data shifted in Following the Shift state the TAP either returns to the Run Test Idle state via the Exit and Update states or enters the Pause state via Exit The reason for entering the Pause state is to temporarily suspend the shifting of data through either the Data or Instruction Register while a required operation such as refilling a host memory buffer is performed From the Pause state shifting can resume by re entering the Shift state via the Exit2 state or terminated by entering the Run Test Idle state via the Exit2 and Update states Upon entering the data or Instruction register scan blocks shadow latches in the selected scan path are forced to hold their present state during the Capture and Shift operations The data being shifted into the selected scan path is not output through the shadow latch until the TAP enters the Update DR or Update IR state The Update state causes the shadow latches to update or parallel load with the new data that has been shifted into the selected scan path MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 145 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 146 1 Test Logic Reset 0 o Run Test Idle Update_DR Figure 9 5 TAP Controller State Diagram
117. ation specified by the aligned effective address are fetched sign extended to the GPR register length if necessary and written into GPR rt This begins a RMW sequence on the current processor There can be only one active RMW sequence per processor When an LL is executed it starts an active RMW sequence replacing any other sequence that was active The RMW sequence is completed by a subsequent SC instruction that either completes the RMW sequence atomi cally and succeeds or does not and fails Executing LL on one processor does not cause an action that by itself causes an SC for the same block to fail on another processor An execution of LL does not have to be followed by execution of SC a program is free to abandon the RMW sequence without attempting a write Restrictions The addressed location must be cached if it is not the result is undefined The effective address must be naturally aligned If either of the 2 least significant bits of the effective address is non zero an Address Error exception occurs Operation vAddr lt sign_extend offset GPR base if vAddr 9 0 then SignalException AddressError endif pAddr CCA lt AddressTranslation vAddr DATA LOAD memword lt LoadMemory CCA WORD pAddr vAddr DATA GPR rt lt memword LLbit lt 1 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved
118. ause register are read only Cause Register Format 31 30 29 28 27 2423 22 21 16 15 10 9 8 765432410 BD 0 CE 0 IV WP 0 IP 7 2 IP 1 0 0 Exc Code 0 Table 5 16 Cause Register Field Descriptions Description Reset State Indicates whether the last exception taken occurred in a branch delay slot 0 Not in delay slot 1 In delay slot Undefined Note that the BD bit is not updated on a new exception if the EXL bit is set Coprocessor unit number referenced when a Coprocessor Unusable exception is taken This field is loaded by hardware on every exception but is unpredictable for all exceptions except for Coprocessor Unusable Undefined Indicates whether an interrupt exception uses the general exception vector or a special interrupt vector Undefined 0 Use the general exception vector 0x180 1 Use the special interrupt vector 0x200 Indicates that a watch exception was deferred because Statusgxy or Statusppy were a one at the time the watch exception was detected This bit both indicates that the watch exception was deferred and causes the exception to be initiated once Statuspy and Statusppy are both zero As such software Undefined must clear this bit as part of the watch exception handler to prevent a watch exception loop Software can only write a 0 to this bit to clear it and cannot force a 0 1 transition Indicates an external interrupt is pending 15 Hardware interrupt 5 or timer i
119. ble It is also used to store the program counter on Reset Soft Reset and non maskable interrupt NMJ exceptions The ErrorEPC register contains the virtual address at which instruction processing can resume after servicing an error This address can be e The virtual address of the instruction that caused the exception e The virtual address of the immediately preceding branch or jump instruction when the error causing instruction is in a branch delay slot Unlike the EPC register there is no corresponding branch delay slot indication for the ErrorEPC register ErrorEPC Register Format 31 ErrorEPC Table 5 31 ErrorEPC Register Field Description Fields Read Name Bit s Description Write Reset State ErrorEPC 31 0 Error Exception Program Counter R W Undefined MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 109 Chapter 5 CPO Registers 5 2 26 DeSave Register CPO Register 31 The Debug Exception Save DeSave register is a read write register that functions as a simple memory location This register is used by the debug exception handler to save one of the GPRs that is then used to save the rest of the context to a pre determined memory area such as in the EJTAG Probe This register allows the safe debugging of exception handlers and other types of code where the existence of a valid sta
120. bus clock was stopped when the debug exception occurred Undefined 0 Internal system bus clock stopped 1 Internal system bus clock running Indicates the Count register behavior in debug mode CountDM Encoding of the bit is 0 Count register stopped in debug mode 1 Count register increments in debug mode Instruction fetch Bus Error exception Pending Set when an instruction fetch bus error event occurs or if a 1 is written to the bit by software Cleared when a Bus IBusEP Error exception on instruction fetch is taken by the processor and by reset If IBusEP is set when IEXI is cleared a Bus Error exception on instruction fetch is taken by the processor and IBusEP is cleared Indicates that an imprecise Machine Check expception MCheckP is pending All Machine Check exceptions are precise on the 4K processors so this bit will always read as 0 Indicates that an imprecise Cache Error is pending CacheEP Cache Errors cannot be taken by the 4K cores so this bit will always read as 0 Data access Bus Error exception Pending Covers imprecise bus errors on data access similar to behavior of IBusEP for imprecise bus errors on an instruction fetch Imprecise Error eXception Inhibit controls exceptions taken due to imprecise error indications Set when the processor takes a debug exception or exception in debug mode Cleared by execution of the DERET instruction Otherwise modifiable by debug mode software When IEXI is set then t
121. cal data segments to be locked into the cache on a per line basis The locked contents cannot be selected for replacement on a cache miss but can be updated on a store hit Cache locking is always available on all data cache entries Entries can be marked as locked or unlocked on a per entry basis using the CACHE instruction The physical data cache memory must be byte writable to support non word store operations 1 4 3 EJTAG Controller All cores provide basic EJTAG support with debug mode run control single step and software breakpoint instruction SDBBP as part of the core These features allow for the basic software debug of user and kernel code 8 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 1 4 Optional Logic Blocks Optional EJTAG features include hardware breakpoints A 4K core may have four instruction breakpoints and two data breakpoints two instruction breakpoints and one data breakpoint or no breakpoints The hardware instruction breakpoints can be configured to generate a debug exception when an instruction is executed anywhere in the virtual address space Bit mask and address space identifier ASID values may apply in the address compare These breakpoints are not limited to code in RAM like the software instruction breakpoint SDBBP The data breakpoints can be configured to generate a debug exception on a data tra
122. cate ap E Ned saree ash toes ea ENER ORE S 54 Table 4 5 Debug Exception Vector Addresses osese ee poesies ponerse penon ke pipes KEE e e eOe PoE E YCEE NEE ESER ESERE EN hEn PE PERKER E PEO PEES 56 Table 4 6 Register States an Interrupt Exception eee ceeeeceeeeeeceseeeeecaeeceecaeesaecsaesaecsecsseceeceseeeseseseaseaeseaesaeeeaecaes 60 Table 4 7 Register States on a Watch Exception 20 ce eeseescosscnesesnconseensonseoeeconsversoeescessersserssessessessosseonsvensonssens sees 61 Table 4 8 CPO Register States on an Address Exception Error oo ccceeceececseeecscesseceseesececseceeeseeeeeeeseaseaeseaecaasenesaee 62 Table 4 9 CPO Register States on a TLB Refill Exception oo eee eceeeeeecseeceeceeaecseaecescseceeeeseseeseaeseaseaeseaesaaeeaesaee 62 Table 4 10 CPO Register States on a TLB Invalid Exception oo cecseeesecseeesecseenececesececeseeeeeeseeeaeeaeseaesaaseaeeaee 63 Table 4 11 Register States on a Coprocessor Unusable Exception eee ceeesecssessecsseesecesceseceeceseeseeeeseeeeseeeaeeneeeneaes 65 Table 4 12 Register States on a TLB Modified Exception cece eceseeecseeeseceesecsesaececeseceeeeseseeeeseseeeeseseaecaaseneeaes 66 Table d2le CPO RE SISters sovseas csvedes foccs sere ccechsuees so gtesspecss vad evaes pave EE cape cu evtisspvssdsutss cscs euueevaesapausch EEE E 73 Table 5 2 CP0 Register Field Types v c gcteata niente inne nub EE A dina ain Gain 75 Table 5 3 Index Register Field Descriptions 5 22 sce ue vis
123. ces to proceed simultaneously Both caches are virtually indexed and physically tagged allowing cache access to occur in parallel with virtual to physical address translation The instruction and data caches are independently configured For example the data cache can be 2 KBytes in size and 2 way set associative while the instruction cache can be 8 KBytes in size and 4 way set associative Each cache is accessed in a single processor cycle Cache refills are performed using a 4 word fill buffer which holds data returned from memory during a 4 beat burst transaction The critical miss word is always returned first The caches are blocking until the critical word is returned but the pipeline may proceed while the other 3 beats of the burst are still active on the bus Table 7 1 lists the instruction and data cache attributes Table 7 1 Instruction and Data Cache Attributes Parameter Instruction Data Size 0 16 KBytes 0 16 KBytes Number of Cache Sets 0 64 128 and 256 0 64 128 and 256 Lines Per Set Associativity 1 4 way set associative 1 4 way set associative Line Size 16 Bytes 16 Bytes Read Unit 32 bits 32 bits Write Policy N A Sa crs o Miss restart after transfer of miss word miss word Cache Locking per line per line Table 7 2 shows the cache size and organization options note that the same total cache size may be achieved with several different set associativities Software can identify the inst
124. cessor Core Family Software User s Manual Revision 01 18 125 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 2 4 Registers for Data Breakpoint Setup The register with implementation indication and status for data breakpoints in general is shown in Table 9 4 Table 9 4 Overview of Status Register for Data Breakpoints Register Mnemonic Register Name and Description DBS Data Breakpoint Status The two data breakpoints are numbered 0 and for registers and breakpoints and the number is indicated by n The registers for each breakpoint are shown in Table 9 5 Table 9 5 Overview of Registers for each Data Breakpoint Register Mnemonic Register Name and Description DBAn Data Breakpoint Address n DBMn Data Breakpoint Address Mask n DBASIDn Data Breakpoint ASID n 4Kc core DBCn Data Breakpoint Control n DBVn Data Breakpoint Value n 9 2 5 Conditions for Matching Breakpoints 126 A number of conditions must be fulfilled in order for a breakpoint to match on an executed instruction or a data transaction and the conditions for matching instruction and data breakpoints are described below The breakpoints only match for instructions executed in non debug mode thus never on instructions executed in debug mode The match of an enabled breakpoint can either generate a debug exception or a trigger indication The BE and or TE bits in the JBCn or DBCn
125. ch cont PREF Table 11 13 Values of the hint Field for the PREF Instruction Value Name Data Use and Desired Prefetch Action Use Prefetched data is expected to be read not modified 0 load Action Fetch data as if for a load Use Prefetched data is expected to be stored or modified 1 store Action Fetch data as if for a store 2 3 Reserved Reserved treated as a NOP Use Prefetched data is expected to be read not modified but not reused extensively it streams through cache 4 load_streamed Action Fetch data as if for a load and place it in the cache so that it does not displace data prefetched as retained Use Prefetched data is expected to be stored or modified but not reused extensively it streams through cache 5 store_streamed Action Fetch data as if for a store and place it in the cache so that it does not displace data prefetched as retained Use Prefetched data is expected to be read not modified and reused extensively it should be retained in the cache 6 load_retained Action Fetch data as if for a load and place it in the cache so that it is not displaced by data prefetched as streamed Use Prefetched data is expected to be stored or modified and reused extensively it should be retained in the cache 7 store_retained Action Fetch data as if for a store and place it in the cache so that it is not displaced by data prefetched as streamed
126. ch writes the contents of DataLo to the data array Forces indexed CACHE instructions to operate on the SPR 2 ScratchPad RAM instead of the cache RW 0 R DT 7 Must be written as zero returns zero on reads 0 0 5 2 23 TagLo Register CP0 Register 28 Select 0 The TagLo register acts as the interface to the cache tag array The Index Store Tag and Index Load Tag operations of the CACHE instruction use the TagLo register as the source of tag information respectively Note that the 4K cores does not implement the TagHi register TagLo Register Format 31 109 8 765 4 3 2 1 0 PA R Valid R L LRF R 106 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers Table 5 29 TagLo Register Field Descriptions Fields Description Reset State 31 10 Must be written as zero returns zero on read This field contains the physical address of the cache line being stored This field indicates whether the corresponding word in the cache line is valid in the cache Undefined Undefined Must be written as zero returns zero on read Specifies the lock bit for the cache tag When this bit is set the corresponding cache line should not be replaced by the cache replacement algorithm LRF One bit of the LRF bits for the set this cache line is a part of This bit is inverted every time a
127. chnologies Inc All rights reserved 143 Chapter 9 EJTAG Debug Support 9 3 Test Access Port TAP The following main features are supported by the TAP module e 5 pin industry standard JTAG Test Access Port TCK TMS TDI TDO TRST_N interface which is compatible with IEEE Std 1149 1 e Target chip and EJTAG feature identification available through the Test Access Port TAP controller e The processor can access external memory on the EJTAG Probe serially through the EJTAG pins This is achieved through so called Processor Access PA and is used to eliminate the use of the user s system memory for debug routines e Support for both ROM based debugger and debugging both through TAP 9 3 1 EJTAG Internal and External Interfaces The external interface of the EJTAG Module consists of the 5 signals defined by the IEEE standard Table 9 19 EJTAG Interface Pins Pin Type Description Test Clock Input Input clock used to shift data into or out of the Instruction or data registers The TCK clock is independent of the processor clock so the EJTAG probe can drive TCK independently of the processor clock frequency TCK The core signal for this is called EJ_TCK Test Mode Select Input The TMS input signal is decoded by the TAP controller to control test se operation TMS is sampled on the rising edge of TCK The core signal for this is called EJ_TMS Test Data Input Serial input data TDD is shifted in
128. cing Guidelines SW MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 69 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions EntryHi lt VPN2 ASID Context lt VPN2 Set Cause EXCCode CE BadVA lt VA Check if exception within another exception EPC lt PC ens cia Cause BD lt 0 Cause BL lt 1 Vec Off 0x000 Vec Off 0x180 Points to General Exception Processor forced to Kernel Mode amp interrupt disabled 0 normal 1 bootstrap PC lt 0x8000_0000 Vec Off unmapped cached PC lt OxBFCO_0200 Vec Off unmapped uncached To TLB Exception Servicing Guidelines Figure 4 3 TLB Miss Exception Handler HW 4Kc Core only 70 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 7 Exception Handling and Servicing Flowcharts MFCO CONTEXT l Service Code l ERET Comments Unmapped vector so TLBMod TLBInv or TLB Refill exceptions not possible EXL 1 so Watch Interrupt exceptions disabled OS System to avoid all other exceptions Only Reset Soft Reset NMI exceptions possible Load the mapping of the virtual address in Context Reg Move it to EntryLo and wri
129. ck for context saving cannot be assumed DeSave Register Format DESAVE Table 5 32 DeSave Register Field Description Fields Read Description Write Reset State DESAVE Debug exception save contents Undefined 110 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 6 Hardware and Software Initialization The MIPS32 4K processor cores have has only a minimal amount of hardware initialization and rely relies on software to fully initialize the device This chapter contains the following sections e Section 6 1 Hardware Initialized Processor State e Section 6 2 Software Initialized Processor State 6 1 Hardware Initialized Processor State The 4K processor cores like most MIPS processors are is not fully initialized by reset Only a minimal subset of the processor state is cleared This is enough to bring the core up while running in unmapped and uncached code space All other processor states can then be initialized by software SJ_ColdReset is asserted after power up to bring the device into a known state Soft reset can be forced by asserting the S _Reset pin This can be used when the device is already up and running and does not need as much initialization 6 1 1 Coprocessor Zero State Much of the hardware initialization occurs in Coprocessor Zero e Random 4Kc core only set to maxim
130. cnecssecaecseeseeeseseeseaeseaecaaeeaesaes 99 Table 5 24 WatchLo Register Field Descriptions 00 00 00 eee eceeeeeceseeeseescecaeceaecaeceacsseceseeseceseseeeaeeeeseseseecaeesaecsaesaeenees 100 Table 5 25 WatchHi Register Field Descriptions 20 0 0 eee eceeeesceseeeseeseecaecsaecaecsacsaecsseeseceeeseeeaeeseseaeeeaecaaesaessaeaeeaees 101 Table 5 26 Debug Register Field Descriptions 2 0 0 eee eeeecceeseeeceeeeseeseecaeceaecaeceacsaecsaeeseceseeseeeeeeseseneeeeecaaesaecseenaeenees 102 Table 5 27 DEPC Register Formats vireo e e a she lec ct esbapduvee db E aA EERE e a E E ates 105 Table 5 28 ErrCtl Register Field Descriptions sepopo orenen perapi e e Eno EEan EN N eop h renhe C tne Sean reae O 106 Table 5 29 TagLo Register Field Descriptions eesessssesssseerssresesrssrerssreresreestenterestertsserersresestentetentereneressereesreeenteneten 107 Table 5 30 DataLo Register Field Description niresisiessncisonerreseiioree iei e E aN EE REEE aE EE EEEE 108 Table 5 31 ErrorEPC Register Field Description ssesesseesseeesesssseesssreesreresresrsrrssetsserersreerstentstentereneressereesrenenreneees 109 Table 5 32 DeSave Register Field Description nsss penisin espoeseseespevor poe peros vrese SE poise Pes Ss Nei pe kskee Spose k Seppe yrki poep 110 Table 7 1 Instruction and Data Cache Attributes essseeesseeeesseesesssstesssreresreestestertssetsserersreerstentetenteesentsseteesreeestrenetes 115 Tabl 7 2 Instruction and Data Cache S
131. csaeaeenees 158 Figure 10 1 Instruct on Horm ats ossis sovoseevtonlvadbeoset r R E vaste E E ERA 164 Figure 11 1 Usage of Address Fields to Select Index and Way sseesessesessssesesresrssrsreerssesrssenresreresrrsrerrereerssenresrnresresee 178 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All right reserved MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All right reserved List of Tables Table 2 1 4Kc and 4Km Core Instruction Latencies oo cece eeeecceeceeeseseeeeecseeesecacesaecsaesaeceecsaecesceseseeeaeseeseaeseeecaasenesaes 17 Table 2 2 4Kc and 4Km Core Instruction Repeat Rates eee ececessceseeeeecseeesecaeesaecsaesaecsecesecseceseseeeeseseaeeaeseaecaeeeaeeaes 18 Table 2 3 4Kp Core Instrict on Latencies seire ea ENE EESE RE EEE ge aneente EE ES REES 21 Table 2 4 Pipeline nier oC KS e a fe ach sates Ree Aa a ae Nad seek Gach aes Rea alsa Reese 25 Table 2 5 Instruction MOOO KS re en raean eae aeee eE TE sess EE Na Apes sculsceesd woes PEES CETE NESE OSRE soieg deeb estapesecpsbeveseades 27 Table 2 62 Instruction Haz rds renmen n a ae ious aE A E a A a AE ENS eT SE SUREE Ea IEE AE EAAS 28 Table 3 1 User Mode SeSments ennn E e e ET A RE EE a E E SENN ERS 36 Table 3 2 Kernel Mode Segments eneee ea E aE E AEE EE eE aE EEE EE N S 37 Table 3 3 Physical Address an
132. d Cache Attributes for dseg dmseg and drseg Address Spaces eeeseresseresrseeeeseeeeene 39 Table 3 4 CPU Access to drseg Address Range ceececesesscssseesceeeeesceseeseecseecsecaaesaecsaesaecnecusecuecsaeeeseseseaseaeseaecaeeenesaes 39 Table 3 5 CPU Acce ss to dims s Address Ran 86 ssosccscvsseeseesdesssceeatipwecsoteoages steen cies E EE E E sip ENE 40 Table 3 6 TEB Tag Entry Fields oij ccc cages gic recesses ech dk oa each saves Seu a stata seden big te teh does lacey sees Sgveb EEE EE ENS EEE RRE 41 Table 3572 TLB Data Entry Bields r ssees secu sevice e ee E E soe Suoch sopae cc EEE o pecs ents PEES EE OESE NSE EEE EAS e REEE S PE PENERE SEEEN 42 Table 3 82 TEB Instructions a ats ati nie ie ian es ee end E Dia Soe eae 47 Table 3 9 Cache Coherency A ttt DUtes se vsspsncices cacy a e R acoee ty Wess lestoek E raS ENNER 47 Table 3 10 Cacheability of Segments with Block Address Translation 00 0 0 cc ceceseceseeseceecesecesceseeeeceeeeeeeseeeeecaeeeneeaes 47 Tabe AT Priority ob EXCeptrons xs cescs scvsg xo es seces oe ted cvsce dics s tess Ws ch sovsh scone satapce set sogpece O EE eE ESEAS Mes EES EE een e EE NES 52 Table 4 2 Exception Vector Base Addresses 0 0 0 0 cecescecessessceseeseceseeeeceseeeeecaeecaecasesaecsaesaecuscssecasesseeseseseseaseaeseaecaasenesaes 53 Table 4 3 Exception Vector Oftsets iei tinon n Eea E ra E ceeded tas ieee O EEE R E dab aree pte ees 54 Table 4 4 Exception V OC OTS a a Gach odes Rete
133. d caching policy for example the kseg1 is always uncacheable Other segments of memory allow the caching policy to be selected by software Generally the cache policy for these programmable regions is defined by a cacheability attribute field associated with that region of memory See Chapter 3 Memory Management on page 31 for further details 7 2 3 Replacement Policy The replacement policy refers to how a way is chosen to hold an incoming cache line on a miss which will result in a cache fill when a cache is at least two way set associative In a direct mapped cache one way set associative the replacement policy is irrelevant since there is only one way available The replacement policy is least recently filled LRF first considering invalid ways and excluding any locked ways On a cache miss the valid lock and LRF bits for each tag entry of the selected line may be used to determine the way which will be chosen The number of tag entries which are looked at depends on the set associativity of the cache First the valid bits are inspected If an invalid way is available as determined by all 4 of the valid bits in a tag being zero then that way will be selected If more than one invalid way is available then the first one found starting from way0 will be selected If all ways are valid then any locked ways will be excluded from consideration for replacement If all ways are locked then no replacement can occur to that line For th
134. d only for implemented instruction breakpoints The Instruction Breakpoint Control n BCn register controls setup of instruction breakpoint n IBCn Register Format 24 23 22 3 2 1 0 Table 9 11 IBCn Register Field Descriptions Fields Read Name Bits Description Write Reset State Res 31 24 Must be written as zero returns zero on read 0 0 Use ASID value in compare for instruction breakpoint n 4Kc core ASIDuse 23 0 Don t use ASID value in compare ake rore KIW Undefined 1 Use ASID value in compare Soe been Must be written as zero returns zero on read 4Km 4Kp cores Res 22 3 Must be written as zero returns zero on read 0 0 Use instruction breakpoint n as triggerpoint TE 2 0 Don t use it as triggerpoint R W 0 1 Use it as triggerpoint Res 1 Must be written as zero returns zero on read 0 0 Use instruction breakpoint n as breakpoint BE 0 0 Don t use it as breakpoint R W 0 1 Use it as breakpoint MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 135 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 2 9 Data Breakpoint Registers The registers for data breakpoints are described below These registers have implementation information and are used to set up the data breakpoints All registers are in drseg and the addresses are shown in section Table 9 12 Table 9 12 Addresses for Data Breakpoin
135. ddition while in Debug mode the core has access to the debug segment dseg This area overlays part of the kernel segment kseg3 dseg access in Debug mode can be turned on or off allowing full access to the entire kseg3 in Debug mode if so desired MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 33 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management 34 Virtual Address User Mode Kernel Mode Debug Mode OXPPFF_COFFFF a kseg3 e E kseg3 at kseg2 So a oS 1 SS 1 kseg1 x9FFF_FFFF ksegO 0x8000_0000 Ox7FFF_FFFF useg kuseg 0x0000_0000 Figure 3 3 4K Processor Core Virtual Memory Map Each of the segments shown in Figure 3 3 is either mapped or unmapped The following two subsections explain the distinction Then Section 3 2 2 User Mode Section 3 2 3 Kernel Mode and Section 3 2 4 Debug Mode specify which segments are actually mapped and unmapped 3 2 1 1 Unmapped Segments An unmapped segment does not use the TLB 4Kc core or the FM 4Km and 4Kp cores to translate from virtual to physical address Especially after reset it is important to have unmapped memory segments because the TLB is not yet programmed to perform the translation Unmapped segments have a fixed simple translation from virtual to physical address This is much like the translations the FM pro
136. deral Acquisition Regulation Supplement 227 7202 for military agencies The use of this information by the Government is further restricted in accordance with the terms of the license agreement s and or applicable contract terms and conditions covering this information from MIPS Technologies or any contractually authorized third party MIPS R3000 R4000 R5000 and R10000 are among the registered trademarks of MIPS Technologies Inc in the United States and certain other countries and MIPS16 MIPS16e MIPS32 MIPS64 MIPS 3D MIPS based MIPS I MIPS II MIPS III MIPS IV MIPS V MDMX MIPSsim MIPSsimCA MIPSsimIA QuickMIPS SmartMIPS MIPS Technologies logo 4K 4Kc 4Km 4Kp 4KE 4KEc 4KEm 4KEp 4KS 4KSc M4K 5K 5Kc 5Kf 20K 20Kc 25Kf R4300 ASMACRO ATLAS BusBridge CoreFPGA CoreLV EC JALGO MALTA MGB PDtrace SEAD SEAD 2 SOC it The Pipeline and YAMON are among the trademarks of MIPS Technologies Inc All other trademarks referred to herein are the property of their respective owners Template B1 06 Build with Conditional Tags 2B JADE MIPS32 PROC MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved References to Product Names This manual encompasses the 4Kc 4Km
137. e LE byte 1 BE byte 2 Byte LE byte 2 BE byte 1 Byte LE byte 3 BE byte 0 Undefined Halfword LE bytes 1 0 BE bytes 3 2 Halfword LE bytes 3 2 BE bytes 1 0 Word LE BE bytes 3 2 1 0 Triple LE bytes 2 1 0 BE bytes 3 2 1 Triple LE bytes 3 2 1 BE bytes 2 1 0 Reserved Note LE little endian BE big endian the byte refers to the byte number in a 32 bit register where byte 3 bits 31 24 byte 2 bits 23 16 byte 1 bits 15 8 byte O bits 7 0 independently of the endianess reserved 0 Doze state The Doze bit indicates any kind of low power mode The value is sampled in the Capture DR state of the TAP controller Doze 22 0 CPU not in low power mode s i 1 CPU is in low power mode Doze includes the Reduced Power RP and WAIT power reduction modes Halt state The Halt bit indicates if the internal system bus clock is Halt 21 running or stopped The value is sampled in the R 0 Capture DR state of the TAP controller 0 Internal system clock is running 1 Internal system clock is stopped 154 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 4 EJTAG TAP Registers Table 9 23 EJTAG Control Register Descriptions Continued Description Reset State Peripheral Reset When the bit is set to 1 it is only guaranteed that the periphera
138. e 3 there is no activity in the M stage of the integer pipeline at this time 4 Incycle 4 the Sub instruction enters I stage The second multiply operation Mult enters the E stage And the Add operation enters M stage of the integer pipe Since the Mult multiply is a 32x16 operation only one clock is required for the Mypy stage hence the Mult operation passes to the Ayypy stage of the MDU pipeline MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 5 MDU Pipeline 4Kc and 4Km Cores 5 In cycle 5 the Sub instruction enters E stage The Mult multiply enters the Mypy stage The Add operation enters the A stage of the integer pipeline The Mult operation completes and is written back in to the HI LO register pair in the Wypy stage 6 Since a 32x32 multiply requires two passes through the multiplier with each pass requiring one clock the 32x32 Mult remains in the Myqpy stage in cycle 6 The Sub instruction enters M stage in the integer pipeline The Add operation completes and is written to the register file in the W stage of the integer pipeline 7 The Mult multiply operation progresses to the Aypy stage and the Sub instruction progress to A stage 8 The Mult operation completes and is written to the HI LO registers pair the Wypy stage while the Sub instruction write to the register file in W stage 2 5 1 32x16 Multiply 4
139. e commonly used in DSP algorithms All multiply operations except the MUL instruction write to the HI LO register pair All integer operations write to the general purpose registers GPR Because MDU operations write to different registers than integer operations following integer instructions can execute before the MDU operation has completed The MFLO and MFHI instructions are used to move data from the HI LO register pair to the GPR file If a MFLO or MFHI instruction is issued before the MDU operation completes it will stall to wait for the data 2 5 MDU Pipeline 4Kc and 4Km Cores The 4Kc and 4Km processor cores contain an autonomous multiply divide unit MDU with a separate pipeline for multiply and divide operations This pipeline operates in parallel with the integer unit IU pipeline and does not stall when the IU pipeline stalls This allows long running MDU operations such as a divide to be partially masked by system stalls and or other integer unit instructions The MDU consists of a 32x16 booth encoded multiplier result accumulation registers HI and LO a divide state machine and all necessary multiplexers and control logic The first number shown 32 of 32x16 represents the rs operand The second number 16 of 32x16 represents the rt operand The core only checks the latter rt operand value to determine how many times the operation must pass through the multiplier The 16x16 and 32x16 operations pass through th
140. e configuration parameters include encodings for the number of sets per way the line size and the associativity The total cache size for a cache is therefore Associativity Line Size Sets Per Way If the line size is zero there is no cache implemented Config1 Register Format Select 1 31 30 2524 2221 1918 16 15 1312 109 7654 3 210 M MMU Size IS IL IA DS DL DA 0 PC WR CA EP FP Table 5 22 Config1 Register Field Descriptions Select 1 Name Bit s Description Reset State This bit is hardwired to 0 to indicate the absence of the M 31 Config2 register This field contains the number of entries in the TLB minus MMU Size one The field is read as 15 decimal in the 4Kc processor and as 0 decimal in the 4Kp and 4Km processors This field contains the number of instruction cache sets per way Three options are available All others values are reserved 1S 0x0 64 0x1 128 0x2 256 0x3 0x7 Reserved This field contains the instruction cache line size If an instruction cache is present it must contain a fixed line size of 16 bytes 0x0 No Icache present 0x3 16 bytes 0x1 0x2 0x4 0x7 Reserved This field contains the level of instruction cache associativity 0x0 Direct mapped IA 0x1 2 way Preset 0x2 3 way 0x3 4 way 0x4 0x7 Reserved This field contains the number of data cache sets per way 0x0 64 DS 0x1 128 Preset 0x2 256 0x3 0x7 Reserved MIPS32 4K
141. e fetcs lean i r eqgeven acoeae ts Sess E E E raS ENE EES 76 Table 5 4 Random Register Field Descriptions 2 0 0 0 ce eeeeceseeeeceseeeeceseeececaeecaecacesaecsaesaecsecseceecsseeseeeseseaseaeseaecaaeeaeeaee 77 Table 5 5 EntryLo0 EntryLoI Register Field Descriptions 2 0 0 ee ee eceeeeecseeesecscessececeeneceecesecusceseeseeeseeeaeeseseeeeseeeaesaes 78 Table 5 6 Cache Coherency Attribute Secon aav i e e ee E a E ea e eee Ea EEE e ARS 78 Table 5 7 Context Register Field Descriptions iessen seirene ii e EE EE EEE SE AEE EREE 80 Table 5 8 PageMask Register Field Descriptions 00 0 0 eee ceeeecceeeeeeceseeeeecaeecsecaeesaecsaesaecaecsseceecsseseeeseseaseneseaeeaaeenesaes 81 Table 5 9 Values for the Mask Field of the PageMask Register sccesscsssssecssceeeseeseeeceecsaeseeeeceecnacseesecnecaeeateaesaeeateeeeas 81 Table 5 10 Wired Register Field Descriptions 0 eee ceeeecceseeeeceseeseceseeececaeeeaecaeesaecaaesaecnecssecesesseeeeseaeseaseaeseaecaeeenesaes 82 Table 5 11 BadVAddr Register Field Description 2 0 0 0 eceecceseesceeeeeeceseeeeecaeeceecaeesaecaaesaecnecsaecnecseeeeeseeeaseaeseneeaaeenesaes 83 Table 5 12 Count Register Field Description cece ceceeceseeesceeeeeeceseeeeecaeecaecaacsaecsacsaecnecsaeceeesseeseeeseseaeeaeseaecaeeeaeaes 84 Table 5 13 EntryHi Register Field Descriptions eee eeeeceseeeeceeeeeeceseeeeecaeeeaecaeesaeceaesaecascsaecuscssesaeeeseseaseaeseaecaaeenesaes 85 Table 5 14 Compare Register Field Descrip
142. e multiplier once A 32x32 operation passes through the multiplier twice The MDU supports execution of a 16x16 or 32x16 multiply operation every clock cycle 32x32 multiply operations can be issued every other clock cycle Appropriate interlocks are implemented to stall the issue of back to back 32x32 multiply operations Multiply operand size is automatically determined by logic built into the MDU Divide operations are implemented with a simple bit per clock iterative algorithm with an early in detection of sign extension on the MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 5 MDU Pipeline 4Kc and 4Km Cores dividend rs Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed Table 2 1 lists the latencies number of cycles until a result is available for multiply and divide instructions The latencies are listed in terms of pipeline clocks In this table latency refers to the number of cycles necessary for the first instruction to produce the result needed by the second instruction Table 2 1 4Kc and 4Km Core Instruction Latencies Instruction Sequence Size of operand Latency 1st Instruction 1st Instruction 2nd instruction clocks MULT MULTU MADD MADDU 16 bit MADD MADDU or MSUB MSUBU or 1
143. e performed and a hit miss determination is made A 16x16 or 32x16 MUL operation completes in the array and stalls for one clock in the M stage to complete the carry propagate add in the M stage 4Kc and 4Km cores A 32x32 MUL operation stalls for two clocks in the M stage to complete second cycle of the array and the carry propagate add in the M stage 4Kc and 4Km cores A 16x16 or 32x16 MULT MADD MSUB operation completes in the array 4Kc and 4Km cores A 32x32 MULT MADD MSUB operation stalls for one clock in the Myny stage of the MDU pipeline to complete second cycle in the array 4Kc and 4Km cores A divide operation stalls for a maximum of 32 clocks in the Myyny stage of the MDU pipeline 4Kc and 4Km cores A multiply operation stalls for 31 clocks in Myypy stage 4Kp core only A multiply accumulate operation stalls for 33 clocks in Myqpy stage 4Kp core only e A divide operation stalls for 32 clocks in the Myyny stage 4Kp core only 2 1 4 A Stage Align Accumulate During the Align Accumulate stage e A separate aligner aligns loaded data with its word boundary MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 13 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline e A MUL operation makes the result available for writeback The actual register writeback is performed in the W stage all 4K cores A MULT MADD MSUB operation performs the carry propaga
144. e register that contains the address at which processing resumes after a debug exception or debug mode exception has been serviced For synchronous precise debug and debug mode exceptions the DEPC contains either e The virtual address of the instruction that was the direct cause of the debug exception or e The virtual address of the immediately preceding branch or jump instruction when the debug exception causing instruction is in a branch delay slot and the Debug Branch Delay BDB bit in the Debug register is set For asynchronous debug exceptions debug interrupt the DEPC contains the virtual address of the instruction where execution should resume after the debug handler code is executed DEPC Register Format 31 0 DEPC Table 5 27 DEPC Register Formats Description The DEPC register is updated with the virtual address of the instruction that caused the debug exception If the instruction is in the branch delay slot the virtual address of the immediately preceding branch or jump instruction Undefined is placed in this register Execution of the DERET instruction causes a jump to the address in the DEPC MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 105 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 22 ErrCtl Register CPO Register 26 Select 0 The ErrCtl register provides a mechanism for enabling software testing
145. e rising edge of TCK the controller transitions to the Pause_IR state A HIGH on TMS causes the controller to transition to the Update_IR state which terminates the scanning process The instruction cannot change while the TAP controller is in this state and the instruction register retains its previous state 9 3 2 14 Pause_IR State The Pause_IR state allows the controller to temporarily halt the shifting of data through the instruction register in the serial path between TDI and TDO If TMS is sampled LOW at the rising edge of TCK the controller remains in the Pause_IR state A HIGH on TMS causes the controller to transition to the Exit2_IR state The instruction cannot change while the TAP controller is in this state 9 3 2 15 Exit2_IR State This is a temporary controller state in which the instruction register retains its previous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift_IR state to allow another serial shift of data A HIGH on TMS causes the controller to transition to the Update_IR state which terminates the scanning process The instruction cannot change while the TAP controller is in this state 9 3 2 16 Update_IR State The instruction shifted into the instruction register takes effect on the rising edge of TCK If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Run Test Idle state A HIGH on TMS causes the controller to transition to the Select_DR_Scan
146. e same sequence as shown in Table 4 1 4 6 1 Reset Exception A reset exception occurs when the S7_ColdReset signal is asserted to the processor This exception is not maskable When a Reset exception occurs the processor performs a full reset initialization including aborting state machines establishing critical state and generally placing the processor in a state in which it can execute instructions from uncached unmapped address space On a Reset exception the state of the processor in not defined with the following exceptions The Random register is initialized to the number of TLB entries 1 4Kc core e The Wired register is initialized to zero 4Kc core e The Config register is initialized with its boot state MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 6 Exceptions The RP BEV TS SR NMI and ERL fields of the Status register are initialized to a specified state e The I R and W fields of the WatchLo register are initialized to 0 e The ErrorEPC register is loaded with PC 4 if the state of the processor indicates that it was executing an instruction in the delay slot of a branch Otherwise the ErrorEPC register is loaded with PC Note that this value may or may not be predictable PC is loaded with OxBFCO_0000 Cause Register ExcCode Value None Additional State Saved None Entry Vector Used
147. e to locked The lock state may be cleared by executing an Index Invalidate or Hit Invalidate operation to the locked line or via an Index Store Tag operation to the line that clears the lock bit Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Table 11 11 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl WST Set ErrCtl SPR Cleared Code Caches Name Effective Operation Implemented Address Operand Type Write the DataLo Coprocessor 0 register alt Index Store Data contents at the way and byte index specified All All All of the other codes behave the same as when Others ErrCtl WST is cleared MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 181 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 11 MIPS32 4K Processor Core Instructions Table 11 12 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl SPR Set Effective Operation Implemented Address Operand Type Read the SPRAM tag at the specified index into Index Load Tag the TagLo Coprocessor 0 register Update the SPRAM tag at the specified index Index Store Tag from the TagLo Coprocessor 0 register Write the DataLo Coprocessor 0 register Index Store Data contents into the SPRAM at the word index specified All All All of the other codes behave the same as when Others ErrCtl SPR is cleared 182 MIPS32 4K Process
148. e unlocked ways the LRF bits from each tag are used to identify the way which has been filled least recently and that way is selected for replacement When the new tag is written during the line fill its LRF bit is modified to indicate that way is no longer the least recently filled 7 3 Instruction Cache The instruction cache is an optional on chip memory block of up to 16 KBytes The virtually indexed physically tagged cache allows the virtual to physical address translation to occur in parallel with the cache access rather than having to wait for the physical address translation All of the cores support instruction cache locking Cache locking allows critical code or data segments to be locked into the cache on a per line basis enabling the system programmer to maximize the efficiency of the system cache The cache locking function is always enabled on all instruction cache entries Entries can then be marked as locked or unlocked on a per entry basis using the CACHE instruction 7 4 Data Cache The data cache is an optional on chip memory block of up to 16 KBytes The virtually indexed physically tagged cache allows the virtual to physical address translation to occur in parallel with the cache access rather than having to wait for the physical address translation MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 117 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 7 Caches
149. ecall that this bit was set from the logical AND of the two G bits in EntryLo0 and EntryLol when the TLB was written Restrictions The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB entries in the processor MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Write Random TLB Entry Operation i lt Random Mask PageMaSkmask ven2 amp EntryHiypy2 as p amp EntryHiasrp c EntryLol and EntryLo0g pry amp EntryLolppy TLB TLB TLB TLB TLB TLB TLB TLB TLB TLB TLB TLB Exceptions H H H H H H H H H H H H ci S Entry Olc p amp Entry y amp Entry Olp oly prno lt EntryLo0ppy co amp Entry po amp Entry 006 100p vo amp Entry Coprocessor Unusable MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 00y TLBWR 201 Chapter 11 MIPS32 4K Processor Core Instructions 202 Enter Standby Mode WAIT 31 26 25 24 0 COPO CO WAIT Implementation Dependent Code 010000 1 100000 6 1 19 6 Format WAIT MIPS32 Purpose Wait for Event Description The WAIT instruction forces the core into low power mode The pipeli
150. eceessasesseeaeeners 112 G21 DS Fetch AGresS aie csssvedscpes ses vests ovens setncoves sucoves sensu ovsedexdesbecien svege E AEE copaeaneed 112 6 2 Software Initialized Processor State iiceoe e e ea e E e eS ee iei Ee eaei eie ES 112 6 2 Register FUS parearea a EEE E E E EE E A EEE E ER 112 6 2 2 TLB 4Ke Core Only er p a e E E aie Mani ol Rahs oui nla E N RER 112 6 23 ETO 1 EE ES EEEE EAEE E E AE EEEE 112 6 2 4 Coprocessor Zero state e can e ian a E a oe ein are E E sean 113 Chapter 7 Caches asir ne iae EN ase Sioa va te Ste det Acciatdi E E E E E e EE E R E s aisa 115 TV EAEKO IDLE ATO 1 MEARE EE ER EST 115 T2 Cach Protocols trieri reee Sessa Tig Dante E RE Eeo EEE EEEE EEE case EE E E E a E REE E E E SES 116 7 2 1 Cache Organization issssissgescsesssseus shsscessysss pases o EEEE A EEEO A E AE EE E EEE SEEDERS RE EE EEES 116 72 2 Cacheability Attributes cratie nk ena shies ies hee Beh a E ecb ea reas hole tases E eke EE Aa Sek eee nde 117 72 3 Replacement Policy si sssscsecsssssssbiscsssspetstascssutoszeasaeveeedesbsassdaiesevs Erer a ERa STEE sense nbucoosesshasestatessasSbesesexpessaesvens 117 T3 ISTIC HON Cache nres n eE E EEEE EEE EERE EEE EE td EN E utente E EEEE E EE E EEEE 117 TA Data Cache reani ETS e EE EEE EEEE E EE R EEEE REE E E E EEE EEA S 117 71 5 Memory Coherence stes ainiai erie ees esa cas EET A soe ESE EEEE E EE lasts EE oboe cases EE whee 118 Chapter 8 Power Management isaisip eenn opeke rrei ee ees Reone PRE re eE
151. ed at physical addresses 0xC000_0000 0xDFFF_FFFF in the 4Km and 4Kp processor cores This space is mapped through the TLB in the 4Kc processor core 3 2 3 5 Kernel Mode Kernel Space 3 kseg3 In Kernel mode when the most significant three bits of the 32 bit virtual address are 111 the kseg3 virtual address space is selected This 2 _byte 512 MByte kernel virtual space is located at physical addresses 0xEO00_0000 OxFFFF_FFFF in the 4Km and 4Kp processor cores This space is mapped through the TLB in the 4Kc processor core 3 2 4 Debug Mode Debug mode address space is identical to Kernel mode address space with respect to mapped and unmapped areas except for kseg3 In kseg3 a debug segment dseg co exists in the virtual address range 0xFF20_0000 to OxFF3F_FFFF The layout is shown in Figure 3 6 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation OxFFFF_FFFF OxFF40_0000_ oxFF20_0000 98e9 kseg1 0x0000_0000 ksegO Unmapped Figure 3 6 Debug Mode Virtual Address Space Mapped if mapped in Kernel Mode The dseg is sub divided into the dmseg segment at 0xFF20_0000 to OxFF2F_FFFF which is used when the probe services the memory segment and the drseg segment at 0xFF30_0000 to OxFF3F_FFFF which is used when memory mapped debug registers are accessed The subdivision and attribut
152. ed when the destination register is written Stores are completed when the stored value is visible to every other processor in the system SYNC is required potentially in conjunction with SSNOP to guarantee that memory reference results are visible across operating mode changes For example a SYNC is required on some implementations on entry to and exit from Debug Mode to guarantee that memory affects are handled correctly Detailed Description SYNC does not guarantee the order in which instruction fetches are performed The stype values 1 31 are reserved they produce the same result as the value zero Executing the SYNC instruction causes the write through buffer to be flushed The SYNC instruction stalls until all loads and stores are completed The innformation presented here refers to the MIPS 4K core implementation of the SYNC instruction For a more detailed description of the programming effects of SYNC on a generic MIPS32 processor refer to the MIPS32 Architecture Reference Manual MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Synchronize Shared Memory cont SYNC Restrictions The effect of SYNC on the global order of loads and stores for memory access types other than uncached and cached coherent is UNPREDICTABLE Operation SyncOperation stype Exceptions None MIPS32 4K Processor
153. eeeecseeseecaeesaecaecsaeaecaeeeseeeeeeees 67 Chapter 5 CPO Registers oie cous vesscaseskspscscdeshassssasescsasuenessesscasneauouss conte siasbap sesauessnasbeasesexesusaessesscasgeasoussnapsondescassussbesens spansesvaees 73 D1 CPO R gister SUMMATY eiee piren tis oE E EEEE cr E EEE ET beset E TEE EEE EE OE EE ETEN 73 3 2 CPO Registers ssiri snr eera er e aE E EERE ERSE uh eben EAE a r EEEE EER ES k EEES 75 5 2 1 Index Register CPO Register 0 Select 0 esesessesessssssessssreessresrsresresrerestsseerrsrersreeresrntestnertesrerrsreetereneses 76 5 2 2 Random Register CPO Register 1 Select 0 occ eee csesecssesseceeeaeceecsececeseeeeeseseeeeseseaseaeseaesaaeeaeenaes 77 5 2 3 EntryLoO EntryLo1 CPO Registers 2 and 3 Select 0 oo ee eseceeeeseceeceecesceseeeeeeseeeeceseseaeeseeeaecseeeaeenaes 78 5 2 4 Context Register CPO Register 4 Select 0 oo eee eeceeseeecseessecseaececesecseceseeseesseseaeeaeseaseaeeeaesnaeeaeenaes 80 5 2 5 PageMask Register CPO Register 5 Select 0 eee ecceeesecssessecssessececesecesceseeesceseeeaeeseseaeeaeeeaesnaeeaeenaes 81 5 2 6 Wired Register CPO Register 6 Select 0 ooo eee eeeeeecseeesecseessecseeaecnecsecseceseeeceseesaseseseaseaeseaecnaeeaeenaes 82 5 2 7 BadVAddr Register CPO Register 8 Select 0 oo eeecseecsecsseeseceseeeceseesecesceeseeeeeseaeeseeeaesseecaessaeeaeenaes 83 5 2 8 Count Register CPO Register 9 Select O seccsessastssepescseissensseaesssayos sosessasvasuacesyeoveessasssbvsascas svsupensaesbens
154. eeeeecaeeesecaeesaecaaesaecsecssecusesseeeseaeseaeeaesaecaasenesaee 39 Figure 3 7 JE LB Eoy AA and Datars sc curd sc r Sosa toons aiess sone cote tees deb Ee Na EE SE meee eek todos name aes 41 Figure 3 8 Overview of a Virtual to Physical Address Translation in the 4Kc Core tec ceceseeeeceeeeeeeeseeeeeeseeeneenes 44 Figure 3 9 32 bit Virtual Address Translation sinense e EEE EEE E ENTE SEESE AREE 45 Figure 3 10 TLB Address Translation Flow in the 4Kc Processor Core s eessssesesseeeseseereseerrsrestsresrerrsseeresreresreserreeeeees 46 Figure 3 11 FM Memory Map ERL 0 in the 4Km and 4Kp Processor Cores sssessessesesssesesresrsererrerssrereseerrsreeesreereees 48 Figure 3 12 FM Memory Map ERL 1 in the 4Km and 4Kp Processor Cores ssseesessesessseeseseesrsrrsreersseeresreresresesreeeeers 49 Figure 4 1 General Exception Handler HW erene r e soutien Ses ae E deve SE EE EERS 68 Figure 4 2 General Exception Servicing Guidelines SW essssesssssseesssresssrssrsresrsresrerrssesresteresreestrsrersseeresreresresesresenees 69 Figure 4 3 TLB Miss Exception Handler HW 4Kc Core only oo ecee ce eeeseesecscecseceneseceseaecescseceseeseeeeeeseseaesnaeenesnes 70 Figure 4 4 TLB Exception Servicing Guidelines SW 4Kc Core only nee ec eecceceseeseceeesecesceseceeeeseeeeeeeeseeeeaeeeneaee 71 Figure 4 5 Reset Soft Reset and NMI Exception Handling and Servicing Guidelines icc ceeesesseeeceecneeeeeeceeeeeeeeees 12 Figure 5
155. eeeeseaeeseseaecaessaecaassaecaeenaeenees 152 Table 9 22 Implementation Register Descriptions 00 0 0 eee eeeesecscesseceseeseceecesecnecsseeseeseeeeesessaeeseseaecaeeeaecaaesaecsaeeaeenees 152 Table 9 23 EJTAG Control Register Descriptions 0 ee eee eeeeeecseessececeseceecseceeceseeseesseeseeeaeeeaeeseseeecaeeeaecaeesaecsaesaeenees 153 Table 9 24 Fastdata Register Field Description 20 0 eee ee ceececseesseccesaeceecseceecseeseceseeeeseseeseeeseseeecseesaecaaesaecasenaeenees 158 Table 9 25 Operation of the FASTDATA access oo eee cseeecseessecceeaeceecsecnecsscesecseeeceaeeseeeseseeecaeesaecaeesaecasenaeenees 159 Table 10 12 Byte Access within a WOrd 5 oc e oaea aa e seuss coscbsetes segue sotsese a Ea S N NEE eE E ee REN EE tes ECEE 165 Table 11 1 Encoding of the Opcode Field oo ieee eeceeeeeeeeseeeeeceesaececaeceeceaecsecseesecsesseseseseaeeseseaecaeesaecaassaecasenaeenees 169 Table 11 2 Special Opcode Encoding of Function Field oo eee eee ceeseceeceseceeceseeeeceseeeecesesseeeaeeseecseesaecsaesaecseeaeenees 170 Table 11 3 Spedial2 Opcode Encoding of Function Field oo eee ceceeseceeceeceeceseeeeeeseeseceeeeeeeeseeeeecaeeesecaaeaecasenaeenees 170 Table 11 4 RegImm Encoding of rt Field 2 c scscesesescssescesesenssessesesesesseneon sosevesonsensncuonnessnssetpenstoanenenserosenensesonenennenes 170 Table 11 5 COPO Encoding of rs Field oo eee eeeeceeeeeeeseeeeecaeesaecasesaecaeceaecsecaeesecsseseseaeseeeesesaecaeesaecaeesaecas
156. eg kseg0 kseg1 kseg2 3 Figure 3 1 shows how the memory management unit interacts with cache accesses in the 4Kc core while Figure 3 2 shows how the memory management unit interacts with caches accesses for the 4Km and 4Kp cores In the 4Km and 4Kp cores note that the FM MMU replaces the ITLB DTLB and JTLB found in the 4Kc core MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 31 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management Instruction Virtual Address IVA Data Virtual Address DVA Instruction Tag IPA Cache g IPA RAM Instruction Physical Address IPA Comparator Instruction IVA Hit Miss gt Data Physical Data Address gt Hit Miss DPA e gt DTLB Comparator xz Data Tag DPA Cache RAM Figure 3 1 Address Translation During a Cache Access in the 4Kc Core Instruction Virtual Address IVA Data Virtual Address DVA Instruction Cache RAM Tag IPA Instruction Physical Address IPA FM MMU Comparator Instruction Hit Miss Data Physical Data DPA Comparator Data Cache RAM Tag DPA Figure 3 2 Address Translation During a Cache Access in the 4Km and 4Kp cores 3 2 Modes of Operation All The 4K processor cores supports three modes of operation 32 MIPS32 4K Proce
157. eger pipeline until early in the A stage The A to E bypass is available for this data But as for Loads the instruction immediately after one of these instructions can not use this data right away If it does it will cause an instruction interlock slip in E stage see Section 2 11 Instruction Interlocks on page 27 An interlock slip after an MFHI is illustrated in Figure 2 22 One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle A Ww l E M MFHI to R3 gt Data bypass from A to E ADD R4 R3 R5 gt slip E M A Ww Figure 2 22 IU Pipeline Slip after MFHI 2 9 Interlock Handling Smooth pipeline flow is interrupted when cache misses occur or when data dependencies are detected Interruptions handled using hardware such as cache misses are referred to as interlocks At each cycle interlock conditions are checked for all active instructions Table 2 4 lists the types of pipeline interlocks for the 4K processor cores Table 2 4 Pipeline Interlocks Interlock Type Sources Slip Stage ITLB Miss 4Kc core Instruction TLB I Stage ICache Miss Instruction cache Producer consumer hazards E M Stage Instruction Hardware Dependencies MDU TLB E Stage MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 25 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline Table 2
158. elaySlot then EPC lt PC 4 CausS pp lt 1 else EPC lt PC Cause pp lt 0 endif if ExceptionType TLBRefill then vectorOffset lt 0x000 elseif ExceptionType Interrupt and Causey 1 then vectorOffset lt 0x200 else vectorof endif else fset lt 0x180 vectorOffset lt 0x180 endif Cause g lt Faul CauSegxccode lt 7 StatuSpy lt 1 if Statusppy tingCoprocessorNumber ExceptionType L then PC lt OxBFCO0O_0200 vectorOffset else PC lt 0x8000_0000 vectorOffset endif 4 5 Debug Exception Processing All debug exceptions have the same basic processing flow e The DEPC register is loaded with the program counter PC value at which execution will be restarted and the DBD bit is set appropriately in the Debug register The value loaded into the DEPC register is the current PC if the instruction is not in the delay slot of a branch or the PC 4 of the branch if the instruction is in the delay slot of a branch e The DSS DBp DDBL DDBS DIB and DINT bits D bits at 5 0 in the Debug register are updated appropriately depending on the debug exception type e Halt and Doze bits in the Debug register are updated appropriately e DM bit in the Debug register is set to 1 e The processor is started MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved
159. en initializing the TLB care must be taken to avoid creating a TLB Shutdown condition where two TLB entries could match on a single address Unique virtual addresses should be written to each TLB entry to avoid this 6 2 3 Caches The cache tag and data arrays power up to an unknown state and are not affected by reset Every tag in the cache arrays should be initialized to an invalid state using the CACHE instruction typically the Index Invalidate function This can be a long process especially since the instruction cache initialization needs to be run in an uncached address region 112 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 6 2 Software Initialized Processor State 6 2 4 Coprocessor Zero state Miscellaneous Cop0 states need to be initialized prior to leaving the boot code There are various exceptions that are blocked by ERL 1 or EXL 1 and that are not cleared by Reset These can be cleared to avoid taking spurious exceptions when leaving the boot code e Cause WP Watch Pending SW0 1 Software Interrupts should be cleared Config KO should be set to the desired Cache Coherency Algorithm CCA prior to accessing kseg0 Config 4Km and 4Kp cores only KU and K23 should be set to the desired CCA for useg kuseg and kseg2 3 respectively prior to accessing those regions Count Should be set to a known value if Timer Inte
160. enaeenees 170 Table 11 6 COPO Encoding of Function Field When rs CO 0 0 eeeeessesecsecseesessecaeeecsceaecesseesaeneeseesecnesseeseaecaeeneeaseas 171 Table TI Instruction Set 03 sc ssc hecsig hie a ee Se E AG REG eis Shue nd heh IR E 171 Fable 1 82 Usage of Effective A ddress 4 544 sors lespecusecde e aa saz evasesotiess os e escent penaa ae peN an EPEE erraia 177 Table 11 9 Encoding of Bits 17 16 of CACHE Instruction 20 0 eeseeeseeeeeeecseceececeseeesceceeeecsaeseaeeneeesaeceeeeceseeenaeenees 178 Table 11 10 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl WST SPR Cleared 0 0 eeceeeeeeeeeeneeeeees 179 Table 11 11 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl WST Set ErrCtl SPR Cleared 0 000 181 Table 11 12 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl SPR Set eee eeeeeseeeeeeeneceeeeceeeeeneeeeees 182 Table 11 13 Values of the hint Field for the PREF Instruction o eee ce ceeeceeceseeeeceseeeeceeeeeeeeseseeecaeeeaecaeesaecseeaeenees 188 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All right reserved Chapter 1 Introduction to the MIPS32 4K Processor Core Family The MIPS32 4K processor cores from MIPS Technologies are is a high performance low power 32 bit MIPS RISC cores intended for custom system on silicon applications The cores are is designed for semiconductor manufac
161. enalty of at least 2 cycles if the JTLB is busy with other operations it may take additional cycles 3 3 3 Data TLB The DTLB is a small 3 entry fully associative TLB which provides a faster translation for Load Store addresses than is possible with the JTLB The DTLB only maps 4 Kbyte pages sub pages Like the ITLB the DTLB is managed by hardware and is transparent to software Unlike the ITLB when translating Load Store addresses the JTLB is accessed in parallel with the DTLB If there is a DTLB miss and a JTLB hit the DTLB can be reloaded that cycle The DTLB is then re accessed and the translation will be successful This parallel access reduces the DTLB miss penalty to 1 cycle 3 4 Virtual to Physical Address Translation 4Kc Core Converting a virtual address to a physical address begins by comparing the virtual address from the processor with the virtual addresses in the TLB There is a match when the virtual page number VPN of the address is the same as the VPN field of the entry and either e The Global G bit of both the even and odd pages of the TLB entry are set or The ASID field of the virtual address is the same as the ASID field of the TLB entry This match is referred to as a TLB hit If there is no match a TLB miss exception is taken by the processor and software is allowed to refill the TLB from a page table of virtual physical addresses in memory Figure 3 8 shows the logical translation of a virtual address in
162. ent 1 4 Optional Logic Blocks The core consists of the following optional logic blocks as shown in the block diagram in Figure 1 1 1 4 1 Instruction Cache The instruction cache is an optional on chip memory array of up to 16 Kbytes The cache is virtually indexed and physically tagged allowing the virtual to physical address translation to occur in parallel with the cache access rather than having to wait for the physical address translation The tag holds 22 bits of the physical address 4 valid bits a lock bit and the LRF Least Recently Filled replacement bit All cores support instruction cache locking Cache locking allows critical code to be locked into the cache on a per line basis enabling the system designer to maximize the efficiency of the system cache Cache locking is always available on all instruction cache entries Entries can be marked as locked or unlocked by setting or clearing the lock bit on a per entry basis using the CACHE instruction 1 4 2 Data Cache The data cache is an optional on chip memory array of up to 16 Kbytes The cache is virtually indexed and physically tagged allowing the virtual to physical address translation to occur in parallel with the cache access The tag holds 22 bits of the physical address 4 valid bits a lock bit and the LRF replacement bit In addition to instruction cache locking all cores also support a data cache locking mechanism identical to the instruction cache with criti
163. entry is written and is included in the match detection Therefore uninitialized TLB entries will not cause a TLB shutdown Note This hidden initialization bit leaves the entire JTLB invalid after a ColdReset eliminating the need to flush the TLB But to be compatible with other MIPS processors it is recommended that software initialize all TLB entries with unique tag values and V bits cleared before the first access to a mapped location MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 45 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management 46 3 4 2 Page Sizes and Replacement Algorithm To assist in controlling both the amount of mapped space and the replacement characteristics of various memory regions the 4Kc core provides two mechanisms First the page size can be configured on a per entry basis to map page sizes ranging from 4 KByte to 16 MByte in multiples of 4 The CPO PageMask register is loaded with the desired page size which is then entered into the TLB when a new entry is written Thus operating systems can provide special purpose maps For example a typical frame buffer can be memory mapped with only one TLB entry The second mechanism controls the replacement algorithm when a TLB miss occurs To select a TLB entry to be written with a new mapping the 4Kc core provides a random replacement algorithm However the processor also provides a mech
164. eption 13 Tr Trap exception 14 22 Reserved 23 WATCH Reference to WatchHi WatchLo address 24 MCheck Machine check 4Kc core or Reserved 4Km and 4Kp cores 25 31 Reserved MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 13 Exception Program Counter CPO Register 14 Select 0 The Exception Program Counter EPC is a read write register that contains the address at which processing resumes after an exception has been serviced All bits of the EPC register are significant and must be writable For synchronous precise exceptions the EPC contains one of the following e The virtual address of the instruction that was the direct cause of the exception e The virtual address of the immediately preceding branch or jump instruction when the exception causing instruction is in a branch delay slot and the Branch Delay bit in the Cause register is set On new exceptions the processor does not write to the EPC register when the EXL bit in the Status register is set However the register can still be written via the MTCO instruction EPC Register Format 31 EPC Table 5 18 EPC Register Field Description Fields Read Name Bit s Description Write Reset State EPC 31 0 Exception Program Counter R W Undefined MIPS32 4K Processor Core Family Software User s Manual
165. equential programming model The Spacing field indicates the number of unrelated instructions such as NOPs or SSNOPs that should be placed between the first and second instructions of the hazard in order to ensure that the effects of the first instruction are seen by the second instruction Entries in the table that are listed as 0 are traditional MIPS hazards which are not hazards on the 4K cores MT Compare to Timer Interrupt cleared is system dependent since Timer Interrupt is an output of the core that can be returned to the core on one of the SI_Int pins This number is the minimum time due to going through the core s I O registers Typical implementations will not add any latency to this Table 2 6 Instruction Hazards Instruction Hazards First Instruction Second Instruction Instructions Instruction Fetch Matching Watch Register 2 Wai Register Write Load Store Reference Matching Watch 0 Register Instruction fetch affected by new page 3 mapping TEB WUT EBY R CHC COTE Load Store affected by new page mapping 0 Move to EntryHi 4Kc core TLBWR TLBWI TLBP 1 Move to EntryLo0 or EntryLol 4Kc core TLBWR TLBWI 0 Move to EntryHi 4Kc core Load Store affected by new ASID 1 Move to EntryHi 4Kc core Instruction fetch affected by new ASID 3 Move to Index Register 1 Change to CU Bits in Status Register Coprocessor Instruction 1 Move to EPC ErrorPC or DEPC ERET 1 Move to Status Register
166. er e PFNO CO DO VO and G bit are set in the CPO EntryLo0 register e PFN1 C1 D1 V1 and G bit are set in the CPO EntryLo register Note that the global bit G is part of both EntryLo0 and EntryLo1 The resulting G bit in the JTLB entry is the logical AND between the two fields in EntryLo0 and EntryLo1 Please refer to Chapter 5 CPO Registers on page 73 for further details The address space identifier ASID helps to reduce the frequency of TLB flushing on a context switch The existence of the ASID allows multiple processes to exist in both the TLB and instruction caches The ASID value is stored in the EntryHi register and is compared to the ASID value of each entry 3 3 2 Instruction TLB The ITLB is a small 3 entry fully associative TLB dedicated to performing translations for the instruction stream The ITLB only maps 4 Kbyte pages sub pages 42 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 4 Virtual to Physical Address Translation 4Kc Core The ITLB is managed by hardware and is transparent to software If a fetch address cannot be translated by the ITLB the JTLB is accessed to attempt to translate it in the following clock cycle If successful the translation information is copied into the ITLB The ITLB is then re accessed and the address will be successfully translated This results in an ITLB miss p
167. er transitions to the Run Test Idle state A HIGH on TMS causes the controller to transition to the Select_DR_Scan state The instruction cannot change while the TAP controller is in this state and all shift register stages in the test data registers selected by the current instruction retain their previous state 9 3 2 11 Capture_IR State In this state the shift register contained in the Instruction register loads a fixed pattern 00001 on the rising edge of TCK The data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift_IR state A HIGH on TMS causes the controller to transition to the Exit _IR state The instruction cannot change while the TAP controller is in this state MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 147 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 3 2 12 Shift_IR State In this state the instruction register is connected between TDI and TDO and shifts data one stage toward its serial output on the rising edge of TCK If TMS is sampled LOW at the rising edge of TCK the controller remains in the Shift_IR state A HIGH on TMS causes the controller to transition to the Exit _IR state 9 3 2 13 Exit1_IR State This is a temporary controller state in which all registers retain their previous state If TMS is sampled LOW at th
168. eration for a location with an uncached memory access type If PREF results in a memory operation the memory access type used for the operation is determined by the memory access type of the effective address just as it would be if the memory operation had been caused by a load or store to the effective address The hint field supplies information about the way the data is expected to be used A hint value cannot cause an action to modify architecturally visible state MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Prefetch cont PREF Any of the following conditions causes the 4K core to treat a PREF instruction as a NOP e A reserved hint value is used e Writeback invalidate 25 hint value is used e The address has a translation error e The address maps to an uncacheable page e The data is already in the cache e There is already another load prefetch outstanding In all other cases except when hint equals 25 execution of the PREF instruction initiates an external bus read trans action PREF is a non blocking operation and does not cause the pipeline to stall while waiting for the data to be returned MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 187 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 11 MIPS32 4K Processor Core Instructions Prefet
169. es EEs 84 5 2 9 EntryHi Register CPO Register 10 Select 0 eee cece csecsseeseceseeseceecesecesceeeseeeeseaeeseesaeeseeeaecnaeeaeenaes 85 5 2 10 Compare Register CPO Register 11 Select 0 oo ceseeseceseesecescesecesceseeeeceeseaeeseeeaeeseecaessaeeneenaes 86 5 2 11 Status Register CPO Register 12 Select 0 eee eee cseecsecsseeseceseeecescesecesceseeseeeeeeeaeeseesaessaeeaesnaeeneenaes 87 5 2 12 Cause Register CPO Register 13 Select 0 sercis siester siene eest es paseri 91 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All right reserved 5 2 13 Exception Program Counter CPO Register 14 Select 0 oie esceeceseceeceseeeeceseeeeeeseseaeeseeeaecsaeeneenaes 93 5 2 14 Processor Identification CPO Register 15 Select 0 eceeeeseesessecsceeeeceecesecerceseeeceseeeeceseeeaceaeeesecneeeaeenaes 94 5 2 15 Config Register CPO Register 16 Select 0 ooo ec ceeesecscesseceeesaececssececeseeseceseseeeeaeseaseaeeeaecnaeeaeenaes 95 5 2 16 Config Register CPO Register 16 Select 1 oe eeeeeecssessecssesaececesececeseeseceseseeeeseseaeeaeeeaesaaeeaeenaes 98 5 2 17 Load Linked Address CPO Register 17 Select O oo eeeeeceeeceesesesseceececeeeeeaeceececeeeenceeeeeesaeceeeeceeeesaeeeneeee 99 5 2 18 WatchLo Register CPO Register 18 oo eenen persere epsa eene e aa E E pee o eepe EET Erea SEE 100 5 2 19 WatchHi Register CPO Register 19 sessment nren isini e e eene iVE e 101 5
170. es for the segments are shown in Table 3 3 Accesses to memory that would normally cause an exception if tried from kernel mode cause the core to re enter debug mode via a debug mode exception This includes accesses usually causing a TLB exception 4Kc core only with the result that such accesses are not handled by the usual memory management routines The unmapped kseg0 and kseg1 segments from kernel mode address space are available from debug mode which allows the debug handler to be executed from uncached and unmapped memory Table 3 3 Physical Address and Cache Attributes for dseg dmseg and drseg Address Spaces Segment Name Sub Segment Name Virtual Address Generates Physical Address Cache Attribute OxFF20_0000 dmseg maps to addresses 0x0_0000 OxF_FFFF in EJTAG probe memory space through OxFF2F_FFFF OxFF30_0000 drseg maps to the breakpoint through registers 0x0_0000 0xF_FFFF OxFF3F_FFFF 3 2 4 1 Conditions and Behavior for Access to drseg EJTAG Registers Uncached The behavior of CPU access to the drseg address range at OxFF30_0000 to OxFF3F_FFFF is determined as shown in Table 3 4 Table 3 4 CPU Access to drseg Address Range LSNM bit in Debug Transaction register Access Load Store Kernel mode address space kseg3 Fetch Don t care drseg see comments below Load Store MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyrig
171. et input in the Soft Reset description Clarified effective address calculation in the description of the CACHE instruction Small wording updates in the entire document Added Scratch Pad bullet in Feature list Added Multiply divide bullet for 4Kp core in Feature list Added Data bypass section to Pipeline chapter Added abbreviation explanation to Figure 2 1 Figure 2 2 and Figure 2 3 Corrected latency numbers for Divide in Table 2 1 01 09 October 27 2000 Modified Figure 2 8 to make it more obvious what goes on Corrected clock numbers for divide in Figure 2 11 Figure 2 12 and Figure 2 13 Re arranged Chapter 3 Memory Management on page 31 Modes of operation is moved first and JTLB entry contents is now included in the TLB translation section Changed SR to Status when CPO Status register was referenced in Chapter 4 Exceptions Changed some references from instruction to data in the data breakpoint section of Chapter 9 EJTAG Debug Support Moved instruction Hazard section from Chapter 11 MIPS32 4K Processor Core Instructions to Chapter 2 Pipeline Changed all references of Block Address Translation BAT to Fixed Mapping FM for consistency with other MIPS documents 01 10 October 31 2000 Converted document to new template Fixed typo in opcode Table 11 2 on page 170 MUTLU gt MULTU 01 11 December 4 2000 Changed MFCz MTCz in Table 11 5 on page 170 to MFCO MTCO e Made CountDM
172. execution of a software exception processor called a handler located at a fixed address The handler saves the context of the processor including the contents of the program counter the current operating mode and the status of the interrupts enabled or disabled This context is saved so it can be restored when the exception has been serviced When an exception occurs the core loads the Exception Program Counter EPC register with a location where execution can restart after the exception has been serviced The restart location in the EPC register is the address of the instruction that caused the exception or if the instruction was executing in a branch delay slot the address of the branch instruction immediately preceding the delay slot To distinguish between the two software must read the BD bit in the CPO Cause register This chapter contains the following sections e Section 4 1 Exception Conditions e Section 4 2 Exception Priority e Section 4 3 Exception Vector Locations e Section 4 4 General Exception Processing e Section 4 5 Debug Exception Processing e Section 4 6 Exceptions e Section 4 7 Exception Handling and Servicing Flowcharts 4 1 Exception Conditions When an exception condition occurs the relevant instruction and all those that follow it in the pipeline are cancelled Accordingly any stall conditions and any later exception conditions that may have referenced this instruction are inhibited t
173. f different sizes ranging from 4 KB to 16 MB in powers of 4 If a match is found but the entry is invalid i e the V bit in the data field is 0 a TLB Invalid exception is taken If no match occurs TLB miss an exception is taken and software refills the TLB from the page table resident in memory Figure 3 10 show the translation and exception flow of the TLB Software can write over a selected TLB entry or use a hardware mechanism to write into a random entry The Random register selects which TLB entry to use on a TLBWR This register decrements almost every cycle wrapping to the maximum once it s value is equal to the Wired register Thus TLB entries below the Wired value cannot be replaced by a TLBWR allowing important mappings to be preserved In order to reduce the possibility for a livelock situation the Random register includes a 10b LFSR that introduces a pseudo random perturbation into the decrementing The 4Kc core implements a TLB write compare mechanism to ensure that multiple TLB matches do not occur On the TLB write operation the VPN2 field to be written is compared with all other entries in the TLB If a match occurs the 4Kc core takes a machine check exception sets the TS bit in the CPO Status register and aborts the write operation For further details on exceptions please refer to Chapter 4 Exceptions on page 51 There is a hidden bit in each TLB entry that is cleared on a ColdReset This bit is set once the TLB
174. fective for such locations Prefetch does not cause addressing exceptions It does not cause an exception to prefetch using an address pointer value before the validity of a pointer is determined MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Store Conditional Word SC 31 26 25 21 20 16 15 0 SC base rt offset 111000 6 5 5 16 Format SC rt offset base MIPS32 Purpose To store a word to memory to complete an atomic read modify write Description if atomic_update then memory basetoffset amp rt rt 1 else rte 0 The LL and SC instructions provide primitives to implement atomic read modify write RMW operations for cached memory locations The 16 bit signed offset is added to the contents of GPR base to form an effective address The SC completes the RMW sequence begun by the preceding LL instruction executed on the processor To complete the RMW sequence atomically the following occur The least significant 32 bit word of GPR rt is stored into memory at the location specified by the aligned effective address e A l indicating success is written into GPR rt Otherwise memory is not modified and a 0 indicating failure is written into GPR rt If the following event occurs between the execution of LL and SC the SC fails An exception occurs on the processor executing the LL
175. ffset 0x180 4 6 10 Address Error Exception Instruction Fetch Data Access An address error exception occurs on an instruction or data access when an attempt is made to execute one of the following e Fetch an instruction load a word or store a word that is not aligned on a word boundary e Load or store a halfword that is not aligned on a halfword boundary e Reference the kernel address space from user mode Note that in the case of an instruction fetch that is not aligned on a word boundary PC is updated before the condition is detected Therefore both EPC and BadVAddr point to the unaligned instruction address In the case of a data access the exception is taken if either an unaligned address or an address that was inaccessible in the current processor mode was referenced by a load or store instruction MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 61 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions Cause Register ExcCode Value ADEL Reference was a load or an instruction fetch ADES Reference was a store Additional State Saved Table 4 8 CPO Register States on an Address Exception Error Register State Value BadVAddr failing address Contextypyy UNPREDICTABLE EntryHiypy UNPREDICTABLE 4Kc core EntryLo0 UNPREDICTABLE 4Kc core EntryLol UNPREDICTABLE 4Kc core Entry Vector Used General exception vector offset 0x180
176. ft or hard reset 1 for NMI 0 1 NMI otherwise Software can only write a 0 to this bit to clear it and cannot force a 0 1 transition Note that the processor can also be in kernel mode if EXR or ERL are set This condition does not affect the state of the UM bit a e Reserved Must be ignored on write and read as zero fF oR o Error Level Set by the processor when a Reset Soft Reset or NMI exception is taken R W Must be written as zero returns zero on read R Reserved Must be ignored on write and read as zero R Interrupt Mask Controls the enabling of each of the external internal and software interrupts An interrupt is taken if interrupts are enabled and the corresponding bits are set in both the Interrupt Mask field of the Status IM 7 0 register and the Interrupt Pending field of the Cause R W Undefined register and the IE bit is set in the Status register 0 Interrupt request disabled 1 Interrupt request enabled Reserved Must be ignored on write and read as zero R Indicates that the processor is operating in user mode 0 processor is operating in kernel mode 1 processor is operating in user mode R W Undefined 0 normal level 1 error level When ERL is set The processor is running in kernel mode ERL 2 R W 1 Interrupts are disabled The ERET instruction uses the return address held in ErrorEPC instead of EPC kuseg is treated as an unmapped and uncached region This allows m
177. g facilities of the processor Refer to Chapter Chapter 11 MIPS32 4K Processor Core Instructions on page 169 for a listing of CPO instructions 10 7 Enhancements to the MIPS Architecture 166 The core execution unit implements the MIPS32 architecture which includes the following instructions e CLO Count Leading Ones e CLZ Count Leading Zeros e MADD Multiply and Add Word MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 10 7 Enhancements to the MIPS Architecture e MADDU Multiply and Add Unsigned Word e MSUB Multiply and Subtract Word e MSUBU Multiply and Subtract Unsigned Word e MUL Multiply Word to Register e SSNOP Superscalar Inhibit NOP 10 7 1 CLO Count Leading Ones The CLO instruction counts the number of leading ones in a word The 32 bit word in the GPR rs is scanned from most significant to least significant bit The number of leading ones is counted and the result is written to the GPR rd If all 32 bits are set in the GPR rs the result written to the GPR rd is 32 10 7 2 CLZ Count Leading Zeros The CLZ instruction counts the number of leading zeros in a word The 32 bit word in the GPR rs is scanned from most significant to least significant bit The number of leading zeros is counted and the result is written to the GPR rd If all 32 bits are cleared in the GPR rs the result written to the
178. gies Inc All rights reserved 2 6 MDU Pipeline 4Kp Core Only 2 6 MDU Pipeline 4Kp Core Only The multiply divide unit MDU is a separate autonomous block for multiply and divide operations The MDU is not pipelined but rather performed the computations iteratively in parallel with the integer unit IU pipeline It does not stall when the IU pipeline stalls This allows the long running MDU operations to be partially masked by system stalls and or other integer unit instructions The MDU consists of one 32 bit adder result accumulate registers HI and LO a combined multiply divide state machine and all multiplexers and control logic A simple 1 bit per clock recursive algorithm is used for both multiply and divide operations Using booth s algorithm all multiply operations complete in 32 clocks Two extra clocks are needed for multiply accumulate The non restoring algorithm used for divide operations will not work with negative numbers Adjustment before and after are thus required depending on the sign of the operands All divide operations complete in 33 to 35 clocks Table 2 3 lists the latencies number of cycles until a result is available for multiply and divide instructions The latencies are listed in terms of pipeline clocks In this table latency refers to the number of cycles necessary for the second instruction to use the results of the first Table 2 3 4Kp Core Instruction Latencies Operand Signs of Instruc
179. gister has the mask for address compare used in the condition for data breakpoint n DBMn Register Format 31 DBM Table 9 15 DBMn Register Field Descriptions Fields Name Bit s Description Read Write Reset State DBM 31 0 Data breakpoint address mask for condition 0 Corresponding address bit not masked 1 Corresponding address bit masked MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Undefined 139 Chapter 9 EJTAG Debug Support 140 9 2 9 4 Data Breakpoint ASID n DBASIDn Register Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint ASID n DBASIDn register has the ASID value used in the compare for data breakpoint n This register is only valid in the 4Kc core DBASIDn Register Format 31 Res ASID Table 9 16 DBASIDn Register Field Descriptions Fields Description Reset State 31 8 Must be written as zero returns zero on read 0 0 7 0 Data breakpoint ASID value for compare R W Undefined MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 9 5 Data Breakpoint Control n DBCn Register Compliance Level Implemented only for implemented data break
180. gure 9 8 Endian Formats for the PAD Register The size of the transaction and thus the number of bytes available required for the PAD register is determined by the Psz field in the ECR 9 4 4 Fastdata Register TAP Instruction FASTDATA The width of the Fastdata register is 1 bit During a Fastdata access the Fastdata register is written and read i e a bit is shifted in and a bit is shifted out During a Fastdata access the Fastdata register value shifted in specifies whether the Fastdata access should be completed or not The value shifted out is a flag that indicates whether the Fastdata access was successful or not if completion was requested Fastdata Register Format 0 Table 9 24 Fastdata Register Field Description Power up Description State Shifting in a zero value requests completion of the Fastdata access The PrAcc bit in the EJTAG Control register is overwritten with zero when the access succeeds The access succeeds if PrAcc is one and the operation address is in the legal dmseg Fastdata area When successful a one is shifted out Shifting out a zero SPrAcc 0 indicates a Fastdata access failure R W Undefined Shifting in a one does not complete the Fastdata access and the PrAcc bit is unchanged Shifting out a one indicates that the access would have been successful if allowed to complete and a zero indicates the access would not have successfully completed The FASTDATA access is used for efficient
181. h the cache tag software should use unmapped addresses to avoid TLB exceptions This instruction never causes TLB Modified exceptions nor TLB Refill exceptions with a cause code of TLBS nor data Watch exceptions A Cache Error exception may occur as a byproduct of some operations performed by this instruction For example if a Writeback operation detects a cache or bus error during the processing of the operation that error is reported via a Cache Error exception Similarly a Bus Error Exception may occur if a bus operation invoked by this instruction is terminated in an error An address Error Exception with cause code equal AdEL occurs if the effective address references a portion of the kernel address space which would normally result in such an exception Data watch is not triggered by a cache instruc tion whose address matches the Watch register address match conditions Bits 17 16 of the instruction specify the cache on which to perform the operation as follows Table 11 9 Encoding of Bits 17 16 of CACHE Instruction Code Cache 2 00 Primary Instruction 2 01 pe Primary Data 2 10 Not supported 2 11 S Not supported Bits 20 18 of the instruction specify the operation to perform On Index Load Tag and Index Store Data operations the specific wordthat is addressed is loaded into read from the DataLo All other cache instructions are line based and the word and byte indexes will not affect their operation
182. he imprecise error exceptions from bus error on instruction fetch or data access cache error or machine check are inhibited and deferred until the bit is cleared Indicates that an imprecise Debug Data Break Store DDBSImpr 19 exception was taken All data breaks are precise on the R 0 4K cores so this bit will always read as 0 Indicates that an imprecise Debug Data Break Load DDBLImpr 18 exception was taken All data breaks are precise on the R 0 4K cores so this bit will always read as 0 Ver 17 15 EJTAG version R 0x2 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 103 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers Table 5 26 Debug Register Field Descriptions Continued Description i Reset State Indicates the cause of the latest exception in debug mode The field is encoded as the ExcCode field in the DExcCode Cause register for those normal exceptions that may Undefined occur in debug mode Value is undefined after a debug exception Indicates whether the single step feature controllable by the SSt bit is available in this implementation 0 Single step feature available 1 No single step feature available R W Controls if debug single step exception is enabled SSt 8 0 No debug single step exception enabled 0 1 Debug single step exception enabled R 7 6 Reserved Must be written as zero returns zero on read R
183. here is no benefit in servicing stalls for a cancelled instruction When an exception condition is detected on an instruction fetch the core aborts that instruction and all instructions that follow When this instruction reaches the W stage the exception flag causes it to write various CPO registers with the exception state change the current program counter PC to the appropriate exception vector address and clear the exception bits of earlier pipeline stages This implementation allows all preceding instructions to complete execution and prevents all subsequent instructions from completing Thus the value in the EPC ErrorEPC for errors or DEPC for debug exceptions is sufficient to restart execution It also ensures that exceptions are taken in the order of execution an instruction taking an exception may itself be killed by an instruction further down the pipeline that takes an exception in a later cycle MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 51 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions 4 2 Exception Priority Table 4 1 lists all possible exceptions and the relative priority of each highest to lowest Several of these exceptions can happen simultaneously in that event the exception with the highest priority is the one taken Table 4 1 Priority of Exceptions Exception Description Assertion of SI_ColdReset signal Assertion of SI_Reset sign
184. hough not required the scheduling of load delay slots can be desirable both for performance and R Series processor compatibility 10 2 2 Defining Access Types Access type indicates the size of a core data item to be loaded or stored set by the load or store instruction opcode Regardless of access type or byte ordering endianness the address given specifies the low order byte in the addressed field For a big endian configuration the low order byte is the most significant byte for a little endian configuration the low order byte is the least significant byte 164 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 10 3 Computational Instructions The access type together with the three low order bits of the address define the bytes accessed within the addressed word as shown in Table 10 1 Only the combinations shown in Table 10 1 are permissible other combinations cause address error exceptions Table 10 1 Byte Access within a Word Bytes Accessed Low Order Big Endia Little Endian Address Bits 31 0 31 0 Access Type Triplebyte Halfword 10 3 Computational Instructions Computational instructions can be either in register R type format in which both operands are registers or in immediate I type format in which one operand is a 16 bit immediate
185. ht 2000 2002 MIPS Technologies Inc All rights reserved 39 Chapter 3 Memory Management Debug software is expected to read the debug control register DCR to determine which other memory mapped registers exist in drseg The value returned in response to a read of any unimplemented memory mapped register is unpredictable and writes are ignored to any unimplemented register in the drseg Refer to Chapter 9 EJTAG Debug Support on page 121 for more information on the DCR The allowed access size is limited for the drseg Only word size transactions are allowed Operation of the processor is undefined for other transaction sizes 3 2 4 2 Conditions and Behavior for Access to dmseg EJTAG Memory The behavior of CPU access to the dmseg address range at OxFF20_0000 to OxFF2F_FFFF is determined by Table 3 5 Table 3 5 CPU Access to dmseg Address Range ProbEn bit in LSNM bit in Transaction DCR register Debug register Access Load Store Don t care 1 Kernel mode address space kseg3 Fetch 1 Don t care dmseg Load Store 1 0 Fetch 0 Don t care See comments below Load Store 0 0 The case with access to the dmseg when the ProbEn bit in the DCR register is 0 is not expected to happen Debug software is expected to check the state of the ProbEn bit in DCR register before attempting to reference dmseg If such a reference does happen the reference hangs until it is satisfied by the probe The probe c
186. i e there must be a pending processor access e The Fastdata operation must use a valid Fastdata area address in dmseg OxFF20 0000 to OxFF20 000F Table 9 25 shows the values of the PrAcc and SPrAcc bits and the results of a Fastdata access Table 9 25 Operation of the FASTDATA access PrAccin Address the LSB LSB Probe Match Control SPrAcc Action in the PrAcc shifted Data shifted Operation check Register shifted in Data Register changes to out out Fails x x none unchanged 0 invalid 1 1 none unchanged 1 invalid Download using valid FASTDATA Passes 1 0 write data 0 SPrAcc 1 previous data 0 x none unchanged 0 invalid Fails x x none unchanged 0 invalid Upload 1 1 none unchanged 1 invalid using FASTDATA Passes 1 0 read data 0 SPrAcc 1 valid data 0 x none unchanged 0 invalid There is no restriction on the contents of the Data register It is expected that the transfer size is negotiated between the download upload transfer code and the probe software Note that the most efficient transfer size is a 32 bit word The Rocc bit of the Control register is not used for the FASTDATA operation 9 5 Processor Accesses The TAP modules support handling of fetch load and store from the CPU through the dmseg segment whereby the TAP module can operate like a is a slave unit connected to the on chip bus The core can then execute code taken from the EJTAG Probe and it can access data via
187. ies Inc All rights reserved Chapter 11 MIPS32 4K Processor Core Instructions This chapter provides a detailed guide to understanding the instruction set for the MIPS32 4K processor cores which is a subset of the MIPS32 architecture The chapter is divided into the following sections e Section 11 1 Understanding the Instruction Descriptions on page 169 e Section 11 2 CPU Opcode Map on page 169 e Section 11 3 Instruction Set on page 171 11 1 Understanding the Instruction Descriptions Refer to Volume II of the MIPS32 Architecture Reference Manual for more information about the instruction descriptions There is a description of the instruction fields definition of terms and a description function notation available in that document 11 2 CPU Opcode Map Key e CAPITALIZED text indicates an opcode mnemonic e Italicized text indicates to look at the specified opcode submap for further instruction bit decode e Entries containing the amp symbol indicate that a reserved instruction fault occurs if the core executes this instruction e Entries containing the B symbol indicate that a coprocessor unusable exception occurs if the core executes this instruction Table 11 1 Encoding of the Opcode Field opcode bits 28 26 001 Special Regimm ADDI ADDIU COPO Special2 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 169 Copyright 2000 2002
188. in the TLB match 0 i a 2 Must be written as zero returns zero on read 0 0 Table 5 9 Values for the Mask Field of the PageMask Register Bit Page Size 24 23 22 21 20 19 18 17 16 15 14 13 4 KBytes 0 0 0 0 0 0 0 0 0 0 0 0 16 KBytes 0 0 0 0 0 0 0 0 0 0 1 1 64 KBytes 0 0 0 0 0 0 0 0 1 1 1 1 256 KBytes 0 0 0 0 0 0 1 1 1 1 1 1 1 MByte 0 0 0 0 1 1 1 1 1 1 1 1 4 MByte 0 0 1 1 1 1 1 1 1 1 1 1 16 Mbyte 1 1 1 1 1 1 1 1 1 1 1 1 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 81 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 6 Wired Register CPO Register 6 Select 0 The Wired register is a read write register that specifies the boundary between the wired and random entries in the TLB as shown in Figure 5 1 The width of the Wired field is calculated in the same manner as that described for the Index register above Wired entries are fixed non replaceable entries that are not overwritten by a TLBWR instruction Wired entries can be overwritten by a TLBWI instruction The Wired register is set to zero by a Reset exception Writing the Wired register causes the Random register to reset to its upper bound The operation of the processor is undefined if a value greater than or equal to the number of TLB entries is written to the Wired register This register is only valid with a TLB 4Kc core I
189. int Overview 4Kc Core Instruction Debug Exception PC Hardware Trigger Indication Breakpoint gt Figure 9 2 Instruction Hardware Breakpoint Overview 4Km and 4Kp Core When a instruction breakpoint matches a debug exception and or a trigger is generated An internal bit in the instruction breakpoint registers is set to indicate that the match occurred 9 2 2 Features of Data Breakpoint Data breakpoints occur on load store transactions Breakpoints are set on virtual address and ASID values similar to the Instruction breakpoint Data breakpoints can be set on a load a store or both Data breakpoints can also be set based on the value of the load store operation Finally masks can be applied to both the virtual address and the load store value 124 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints Data breakpoints compare the transaction type TYPE which may be load or store the virtual address of the transaction ADDR the ASID accessed bytes B YTELANE and data value DATA with the registers for each data breakpoint including masking or qualification on the transaction properties An overview is shown in Figure 9 3 and Figure 9 4 TYPE hi ADDR a m Data ASID gt Hardware BYTELANE Breakpoint oo Debug Exception Trigger Indication DATA p Figure 9 3 Da
190. internal hardware latches the data to be written into the PA Data register 3 The internal hardware sets the following bits in the EJTAG Control register PrAcc 1 selects Processor Access operation PRnW 1 selects processor write operation Psz 1 0 value depending on the transfer size 4 The EJTAG Probe selects the EJTAG Control register shifts out this control register s data and tests the PrAcc status bit Processor Access when the PrAcc bit is found 1 it means that the requested address is available and can be shifted out 5 The EJTAG Probe checks the PRnW bit to determine the required access 6 The EJTAG Probe selects the PA Address register and shifts out the requested address MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 5 Processor Accesses 7 The EJTAG Probe selects the PA Data register and shifts out the data to be written 8 The EJTAG Probe selects the EJTAG Control register and shifts a PrAcc 0 bit into this register to indicate to the processor that the write access is finished 9 The EJTAG Probe writes the data to the requested address in its memory 10 The processor detects that PrAcc bit 0 which means that it is ready to handle a new access The above examples imply that no reset occurs during the operations and that Rocc is cleared MIPS32 4K Processor Core Family Software User s M
191. ion BLEZ Branch on Less Than or Equal to Zero if Rs 31 ll Rs PC int offset BLEZL BLITZ Branch on Less Than or Equal to Zero Likely Branch on Less Than Zero if Rs 31 ll Rs PC int offset else Ignore Next Instruction if Rs 31 PC int offset BLTZAL BLTZALL BLTZL Branch on Less Than Zero And Link Branch on Less Than Zero And Link Likely Branch on Less Than Zero Likely GPR 31 PC 8 if Rs 31 PC int offset GPR 31 PC 8 if Rs 31 PC int offset else Ignore Next Instruction if Rs 31 PC int offset else Ignore Next Instruction BNE Branch on Not Equal if Rs Rt PC int offset BNEL BREAK CACHE Branch on Not Equal Likely Breakpoint Cache Operation if Rs Rt PC int offset else Ignore Next Instruction Break Exception See Cache Description COPO Coprocessor 0 Operation See Coprocessor Description CLO Count Leading Ones Rd NumLeadingOnes Rs CLZ DERET Count Leading Zeroes Return from Debug Exception Rd NumLeadingZeroes Rs PC DEPC Exit Debug Mode MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Table 11 7 Instruction Set Continued Instruction Description Function ae LO int Rs
192. iption Table 11 7 on page 171 e Added details on new core features Index Store Data CACHE instn ErrCtl Cop0 register EJTAG FASTDATA instruction e Updated EJTAG Version in Debug register 01 15 September 25 2001 e Added description of constant fields in Debug register NoDCR NoSSt MCheckP CacheEP DDBSImpr DDBLImpr 01 16 March 13 2002 e Document SB bit in Config indicates whether SimpleBE mode is active or not e Added ISP DSP bits in Config register Indicate whether ISPRAM or DSPRAM are present 01 17 September 25 2002 01 18 November 15 2004 Correction to copyright year 208 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All right reserved
193. ision 01 18 47 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management Table 3 10 Cacheability of Segments with Block Address Translation Virtual Address Segment Range Cacheability kseg3 0xE000_0000 Controlled by K23 field bits 30 28 of the Config register Refer to seg OxFFFF_FFFF Table 3 9 for the encoding The FM performs a simple translation to map from virtual addresses to physical addresses This mapping is shown in Figure 3 11 When ERL 1 useg and kuseg become unmapped and uncached The ERL behavior is the same as if there was a JTLB The ERL mapping is shown in Figure 3 12 The ERL bit is usually never asserted by software It is asserted by hardware after a Reset SoftReset or NMI Please see Section 4 6 Exceptions on page 56 for further information on exceptions Virtual Address Physical Address kseg3 kseg3 0xE000_0000 0xE000_0000 kseg2 kseg2 OxC000_0000 OxCO000_0000 kseg1 OxA000_0000 ksegO Ox8000_0000 useg kuseg useg kuseg 0x4000_0000 reserved Ox2000_0000 kseg0 kseg1 Ox0000_0000 Ox0000_0000 Figure 3 11 FM Memory Map ERL 0 in the 4Km and 4Kp Processor Cores 48 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 6 System Control Coprocessor Virtual Address Physical Address kseg3 k
194. itecture oo eeecsececssessecssesseceecesecesceseeseeeseeeeseseseaeeseesaecaaesaecaaesaesssenaes 166 10 7 0 CLO Count Leading Ones s moei oe ei en hin alin eee eae 167 10 72 CEZ Count Leading Zeros menre ne scours AE EEEE veer pose eben RE E EE E EE ESER 167 10 7 3 MADD Multiply and Add Word occ cecessecssesseceeceseceeceseeeeceseeseceseseaeeseeeaecaaecaecsaeeaecaeeaeenseeseeeeees 167 10 7 4 MADDU Multiply and Add Unsigned Word oo ceceseeesceeeeeeceseeseceseeesecaaecaecsaeeaeceaseaeseseeeeeees 167 10 7 5 MSUB Multiply and Subtract Word oo ceeeseceeceseceeceseeesceseeeeeeseseaeeseeeaecaaecaecsaeeaecaeeaeseseeseeeees 167 10 7 6 MSUBU Multiply and Subtract Unsigned Word ou eeeeceeeeeeceeeeeeceseeesecaeecaecsaesaeceaeeaesnseeeeneees 167 10 7 7 MUL Multiply Word sci cc eniienusgats eet E Mek GEL BARE ea aside aie 168 10 7 8 SSNOP Superscalat Inhibit NOP ose sceees secs aenea ecsceevssusopie covets poses cuedbpeversadsseeccepecestsesepsuseusdeencerebatted 168 Chapter 11 MIPS32 4K Processor Core Instructions 0 cece eseceseeseceeceseceeceseeeseeseseaceseeeaeeseecaecsaecaecasesecneesseseseeseeeeees 169 11 1 Understanding the Instruction Descriptions oo eee ceececessecsseeseceeceseceeceseesecseeeeceaeseaseaeeeaecaeesaecsaesaecnsenaes 169 1 2 CPU Opcode Maps oeseri erreteko anesor aaee oaeee i a Ea EE spe ESEE nET EDE EREE bes sbestaanssapastisices dhadsgeavespasdvens 169 TIS IMSUHUCTION SEL ea eer EE E EE EEE E
195. ized as direct mapped 2 way 3 way or 4 way set associative On a cache miss loads are blocked only until the first critical word becomes available The pipeline resumes execution while the remaining words are being written to the cache Both caches are virtually indexed and physically tagged Virtual indexing allows the cache to be indexed in the same clock in which the address is generated rather than waiting for the virtual to physical address translation in the Memory Management Unit MMU All The cores executes the MIPS32 instruction set architecture ISA The MIPS32 ISA contains all MIPS II instructions as well as special multiply accumulate conditional move prefetch wait and zero one detect instructions The R4000 style memory management unit of the 4Kc core contains a 3 entry instruction TLB ITLB a 3 entry data TLB DTLB and a 16 dual entry joint TLB JTLB with variable page sizes The 4Km and 4Kp processor cores contain a simplified fixed mapping FM mechanism where the mapping of address spaces is determined through bits in the CPO Config select 0 register The 4Kc and 4Km multiply divide unit MDU supports a maximum issue rate of one 32x16 multiply MUL MULT MULTU multiply add MADD MADDU or multiply subtract MSUB MSUBVU operation per clock or one 32x32 MUL MADD or MSUB every other clock The basic Enhanced JTAG EJTAG features provide CPU run control with stop single stepping and re start and with software breakpoint
196. l reset has occurred in the system when the read value of this bit is also 1 This is to ensure that the setting from the TCK clock domain gets effect in the CPU clock PerRst domain and in peripherals 0 When the bit is written to 0 then the bit must also be read as 0 before it is guaranteed that the indication is cleared in the CPU clock domain also This bit controls the EJ_PerRst signal on the core Processor Access Read and Write This bit indicates if the pending processor access is for a read or write transaction and the bit is only valid while Undefined PrAcc is set 0 Read transaction 1 Write transaction Processor Access PA Read value of this bit indicates if a Processor Access PA to the EJTAG memory is pending 0 No pending processor access 1 Pending processor access The probe s software must clear this bit to 0 to indicate the end of the PA Write of 1 is ignored 0 A pending PA is cleared when Rocc is set but another PA may occur just after the reset if a debug exception occurs Finishing a PA is not accepted while the Rocc bit is set This is to avoid that a PA occurring after the reset is finished due to indication of a PA that occurred before the reset Processor Reset Implementation dependent behavior When the bit is set to 1 then itis only guaranteed that this setting has taken effect in the system when the read value of this bit is also 1 This is to ensure that the setting from
197. lation cache protocols the exception control system the processor s diagnostics capability operating mode selection kernel vs user mode and the enabling disabling of interrupts Configuration information such as cache size set associativity and EJTAG debug features are available by accessing the CPO registers Refer to Chapter 5 CPO Registers on page 73 for more information on the CPO registers Refer to Chapter 9 EJTAG Debug Support on page 121 for more information on EJTAG debug registers 1 3 4 Memory Management Unit MMU Each The core contains an MMU that interfaces between the execution unit and the cache controller shown in Figure 1 1 Although the 4Kc core implements a 32 bit architecture the Memory Management Unit MMU is modeled after the MMU found in the 64 bit R4000 family as defined by the MIPS32 architecture The 4Kc core implements an MMU based on a Translation Lookaside Buffer TLB The TLB actually consists of three translation buffers a 16 dual entry fully associative Joint TLB JTLB a 3 entry fully associative Instruction TLB ITLB and a 3 entry fully associative data TLB DTLB The ITLB and DTLB also referred to as the micro TLBs are managed by the hardware and are not software visible The micro TLBs contain subsets of the JTLB When translating addresses the corresponding micro TLB I or D is accessed first If there is not a matching entry the JTLB is used to MIPS32 4K Processor Core
198. lator Instruction Hit Miss Data Hit Miss Data Comparator Address p Calculator Virtual Address Figure 1 3 Address Translation during a Cache Access in the 4Km and 4Kp Cores 1 3 5 Cache Controllers The data and instruction cache controllers support caches of various sizes organizations and set associativity For example the data cache can be 2 Kbytes in size and 2 way set associative while the instruction cache can be 8 Kbytes in size and 4 way set associative There are separate cache controllers for the I Cache and D Cache Each cache controller contains and manages a one line fill buffer Besides accumulating data to be written to the cache the fill buffer is accessed in parallel with the cache and data can be bypassed back to the core Refer to Chapter 7 Caches on page 115 for more information on the instruction and data cache controllers 1 3 6 Bus Interface Unit BIU The Bus Interface Unit BIU controls the external interface signals Additionally it contains the implementation of a 32 byte collapsing write buffer The purpose of this buffer is to hold and combine write transactions before issuing them to the external interface Since the data caches for all cores follow a write through cache policy the write buffer significantly reduces the number of write transactions on the external interface as well as reducing the amount of stalling in the core due to issuance of multiple writes in a short period of
199. ly by hardware Hardware updates of this field are visible by software read Software updates of this field are R W visible by hardware read If the reset state of this field is Undefined either software or hardware must initialize the value before the first read will return a predictable value This should not be confused with the formal definition of UNDEFINED behavior A field that is either static or is updated only by A field to which the value written by software hardware is ignored by hardware Software may write If the Reset State of this field is either O or any value to this field without affecting _ Preset hardware initializes this field to zero anlar reborn so ros a this field R or to the appropriate state respectively on E a a ataware powerup If the Reset State of this field is Undefined If the Reset State of this field is Undefined software reads of this field result in an hardware updates this field only under those ee te ae sees R ae conditions specified in the description of the au eed hai i One ae et f i SeA IONS field specified in the description of the field A field to which the value written by software must be zero Software writes of non zero values to this field may result in UNDEFINED behavior of the hardware Software reads of 0 A field that hardware does not update and for this field return zero as long as all previous which hardware can assume a zero value software writes are zero
200. ly Operation 2 5 3 Divide 4Kc and 4Km Cores Divide operations are implemented using a simple non restoring division algorithm This algorithm works only for positive operands hence the first cycle of the Mypy stage is used to negate the rs operand RS Adjust if needed Note MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 19 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline 20 that this cycle is executed even if the adjustment is not necessary At maximum the next 32 clocks 3 34 execute an iterative add subtract function In cycle 3 an early in detection is performed in parallel with the add subtract The adjusted rs operand is detected to be zero extended on the upper most 8 16 or 24 bits If this is the case the following 7 15 or 23 cycles of the add subtract iterations are skipped The remainder adjust Rem Adjust cycle is required if the remainder was negative Note that this cycle is taken even if the remainder was positive A sign adjust is performed on the quotient and or remainder if necessary Note that the sign adjust cycle is skipped if both operands are positive In this case the Rem Adjust is moved to the Aypy stage Figure 2 11 Figure 2 12 Figure 2 13 and Figure 2 14 show the latency for 8 16 24 and 32 bit divide operations respectively The repeat rate is either 11 19 27 or 35 cycles one less if the sign adjust stage is skipped
201. m being generated by the power up values in the TLB array when two or more TLB entries match on a single address This bit is not visible to software 6 1 3 Bus State Machines All pending bus transactions are aborted and the state machines in the bus interface unit are reset when a Reset or SoftReset exception is taken 6 1 4 Static Configuration Inputs All static configuration inputs defining the bus mode and cache size for example should only be changed during Reset 6 1 5 Fetch Address Upon Reset SoftReset unless the EJTAGBOOT option is used the fetch is directed to VA 0xBFC00000 PA Ox 1FC00000 This address is in kseg1 which is unmapped and uncached so that the TLB and caches do not require hardware unitization 6 2 Software Initialized Processor State Software is required to initialize the following parts of the device 6 2 1 Register File The register file powers up in an unknown state with the exception of rO which is always 0 Initializing the rest of the register file is not required for proper operation Good code will generally not read a register before writing to it but the boot code can initialize the register file for added safety 6 2 2 TLB 4Kc Core Only Because of the hidden bit indicating initialization the 4Kc core does not require TLB initialization upon ColdReset This is an implementation specific feature of the 4Kc core and cannot be relied upon if writing generic code for MIPS32 64 processors Wh
202. more cycles for each instruction e Power Control No minimum frequency Power down mode triggered by WAIT instruction Support for software controlled clock divider e EJTAG Debug Support CPU control with start stop and single stepping Software breakpoints via the SDBBP instruction Optional hardware breakpoints on virtual addresses 4 instruction and 2 data breakpoints 2 instruction and 1 data breakpoint or no breakpoints Test Access Port TAP facilitates high speed download of application code 1 2 Block Diagram All cores contain both required and optional blocks Required blocks are the lightly shaded areas of the block diagram and must be implemented to remain MIPS compliant Optional blocks can be added to the cores based on the needs of the implementation The required blocks are as follows e Execution Unit Multiply Divide Unit MDU System Control Coprocessor CPO Memory Management Unit MMU Cache Controller Bus Interface Unit BIU Power Management Optional blocks include e Instruction Cache I Cache MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 3 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 4K Processor Core Family e Data Cache D Cache e Enhanced JTAG EJTAG Controller Figure 1 1 shows a block diagram of a 4K core The MMU can be implemented using either a translation lookaside
203. n 1 E stage MULT MADD MSUB 16bx32b 0 M stage MFLO MFHI 4Kc and 4Km cores 32bx32b 1 M stage MUL 16bx32b 2 E stage 4Kc and 4Km cores Consumer of target data 32bx32b 3 E stage 16bx32b 1 E stage MUL Non Consumer of target data g 4Kc and 4Km cores 32bx32b 2 E stage MFHI MFLO Consumer of target data 1 E stage MULT MADD MSUB 16bx32b MULT MUL MADD MSUB E stage 4Kc and 4Km cores 32bx32b MTHI MTLO DIV 1 E stage MULT MUL MADD MSUB Until DIV DIV MTHI MTLO MFHI MFL completes E stage O DIV MULT MUL MADD MSUB MTHI MTLO Neti MADDI MeL Until 1st MDU op eas MFHI MFLO DIV 4Kp core O DIV completes 8 Until MUL MUL 4Kp core Any Instruction completes E stage MFCO Consumer of target data 1 E stage TLBWR TLBWI 4Kc core Load Store PREF CACHE 2 E stage TLBR 4Kc core Cop0 op 1 E stage MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 27 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline 2 12 Instruction Hazards In general the core ensures that instructions are executed following a fully sequential program model Each instruction in the program sees the results of the previous instruction There are some exceptions to this model These exceptions are referred to as instruction hazards The following table shows the instruction hazards that exist in the core The first and second instruction fields indicate the combination of instructions that do not ensure a s
204. n a data breakpoint is enabled that breakpoint is evaluated for every data transaction due to a load store instruction executed in non debug mode including load store for coprocessor and transactions causing an address error on data access The breakpoint is not evaluated due to PREF instruction or other transactions which are not part of explicit load store transactions in the execution flow nor for addresses which are not the explicit load store source or destination address Match of the breakpoint depends on the transaction type TYPE as load or store the address and optionally the data value of a transaction The registers for each data breakpoint has the values and mask used in the compare and the equations that determine the match are shown below in C like notation The overall match equation is DB_match DB_match TYPE load amp amp DBCnyozp TYPE store amp amp DBCnyosp amp amp DB_addr_match amp amp DB_no_value_compare DB_value_match Match on the address part DB_addr_match depends on virtual address of the transaction ADDR the ASID value and the accessed bytes BYTELANE where BYTELANE 0 is 1 only if the byte at bits 7 0 on the bus is accessed and BYTELANE 1 is 1 only if byte at bits 15 8 is accessed etc The DB_addr_match is shown below DB_addr_match DBCnastpuse ASID DBASIDnaszp amp amp lt all 1 s gt DBMnppy AD
205. n this setting the kuseg virtual address maps directly to the same physical address and does not include the ASID field 3 2 3 2 Kernel Mode Kernel Space 0 kseg0 In Kernel mode when the most significant three bits of the virtual address are 1005 32 bit kseg0 virtual address space is selected it is the 2 _byte 512 MByte kernel virtual space located at addresses 0x8000_0000 Ox9FFF_FFFF References to ksegO are unmapped the physical address selected is defined by subtracting 0x8000_0000 from the virtual address The KO field of the Config register controls cacheability 3 2 3 3 Kernel Mode Kernel Space 1 kseg1 In Kernel mode when the most significant three bits of the 32 bit virtual address are 1015 32 bit kseg1 virtual address space is selected kseg is the 27 byte 512 MByte kernel virtual space located at addresses 0x AO00_0000 OxBFFF_FFFF References to kseg1 are unmapped the physical address selected is defined by subtracting 0xA000_0000 from the virtual address Caches are disabled for accesses to these addresses and physical memory or memory mapped I O device registers are accessed directly 3 2 3 4 Kernel Mode Kernel Space 2 kseg2 In Kernel mode when UM 0 ERL 1 or EXL 1 in the Status register and DM 0 in the Debug register and the most significant three bits of the 32 bit virtual address are 110 32 bit kseg2 virtual address space is selected This 27 _byte 512 MByte kernel virtual space is locat
206. ne is stalled and when all external requests are completed the processor s main clock is stopped The processor will restart when reset SI_Reset ro SI_ColdReset is signaled or a non masked interrupt is taken SI_NMI SI_Int or EJ_DINT Note that the 4Kc 4Kp amp 4Km cores do not use the code field in this instruction Restrictions The operation of the processor is UNDEFINED if a WAIT instruction is placed in the delay slot of a branch or a jump Copyright 2000 2002 MIPS Technologies Inc All rights reserved MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 11 3 Instruction Set Enter Standby Mode cont WAIT Operation Enter lower power mod Exceptions Coprocessor Unusable Exception MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 203 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 11 MIPS32 4K Processor Core Instructions 204 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Appendix A Revision History Revision Date 1 0 August 1999 Description First released version 1 1 November 1999 Re organization to be more of a SoftWare User s Manual Removed System Interface chapter Count register no longer stops incrementing in DebugMode New bit added to Debug register to indicate this C
207. nees 134 Table 9 11 JBCn Register Field Descriptions ee ei eeeeeeeseeesecscessecocesaeceeceaeceecsseeseesseeeeeeeeseseseseeecaeseaecaaesaecaeenaeenees 135 Table 9 12 Addresses for Data Breakpoint Registers 0 0 eee eee csessecsseeseceeceseceeceseesecseeeeceseeseeeaeseaesaeesaecsaesaecasenaeenees 136 Table 9 13 DBS Register Field Descriptions 20 00 ei eceeeeeesceeseccesecacesaeceeceaeceecsacesecsseeseceseseeeeaeeeeecaeesaecaaesaecaseaeenees 137 Table 9 14 DBAn Register Field Descriptions 00 eee eceeceeeesceesecsceseecocesaeceeceaeceecseesecsseseceeeseeeeaeseeeeaeeeaecaaesaecaeenaeenees 138 Table 9 15 DBMn Register Field Descriptions 20 0 0 eee eee eeseesecscessececesaeceecaecnecsseesecseeseeeaeseeeeseseaecaeeeaecaaesaecaeenaeenees 139 Table 9 16 DBASIDn Register Field Descriptions eee eeeeeecscessecncesseceecsececsseesecseeeesesesseeeseseaeeseeeeecaaesaecsasaeenees 140 Table 9 17 DBCn Register Field Descriptions 20 0 eee eeeeseeesecseessececeaeceeceaecescsseesecseseeeeeseaeeseeeeecseseaecaassaecaeseaeenees 141 Table 9 18 DBVn Register Field Descriptions 00 eee eeeeeeeseeeseceessecaeesaeceeceaeceeceseesecseeeceeeseeeeseseaseseeeaecaaesaecaeenaeenees 143 Table 9 19 EJTAG Interface Pins ntenni en e ate ag bin ene Uae ae A 144 Table 9 20 Implemented EJTAG Instructions sensen nres ii EEE AE E EEE EE E EEEE 148 Table 9 21 Device Identification Register 0 0 ee ec eecceeseeseeseeeeeceesecseesaecaeceaecescsseeseesseese
208. new cache line is filled in the cache entry Must be written as zero returns zero on read 0 Undefined Undefined 0 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 107 Chapter 5 CPO Registers 5 2 24 DataLo Register CP0 Register 28 Select 1 108 The DataLo register acts as the interface to the cache data array The Index Load Tag operation of the CACHE instruction reads the corresponding data values into the DataLo register This register was made writeable on revision 3 5 and the Index Store Data operation of the CACHE instruction was added This operation will write the cache data array with the value of this register Note that the 4K cores does not implement the DataHi register DataLo Register Format 31 DATA Table 5 30 DataLo Register Field Description Fields Read Reset Name Bit s Description Write State DATA 31 0 Low order data read from the cache data array R W Undefined MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 25 ErrorEPC CP0 Register 30 Select 0 The ErrorEPC register is a read write register similar to the EPC register except that ErrorEPC is used on error exceptions All bits of the ErrorEPC register are significant and must be writa
209. ns to the Capture_IR state A HIGH on TMS causes the controller to transition to the Test Reset Logic state The instruction cannot change while the TAP controller is in this state MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 3 Test Access Port TAP 9 3 2 5 Capture_DR State In this state the boundary scan register captures value of the register addressed by the Instruction register and the value is then shifted out in the Shift_DR If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift_DR state A HIGH on TMS causes the controller to transition to the Exit _DR state The instruction cannot change while the TAP controller is in this state 9 3 2 6 Shift_DR State In this state the test data register connected between TDI and TDO as a result of the current instruction shifts data one stage toward its serial output on the rising edge of TCK If TMS is sampled LOW at the rising edge of TCK the controller remains in the Shift_DR state A HIGH on TMS causes the controller to transition to the Exit _DR state The instruction cannot change while the TAP controller is in this state 9 3 2 7 Exit1_DR State This is a temporary controller state in which all test data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitio
210. ns to the Pause_DR state A HIGH on TMS causes the controller to transition to the Update_DR state which terminates the scanning process The instruction cannot change while the TAP controller is in this state 9 3 2 8 Pause_DR State The Pause_DR state allows the controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO All test data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller remains in the Pause_DR state A HIGH on TMS causes the controller to transition to the Exit2_DR state The instruction cannot change while the TAP controller is in this state 9 3 2 9 Exit2_DR State This is a temporary controller state in which all test data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift_DR state to allow another serial shift of data A HIGH on TMS causes the controller to transition to the Update_DR state which terminates the scanning process The instruction cannot change while the TAP controller is in this state 9 3 2 10 Update_DR State When the TAP controller is in this state the value shifted in during the Shift_DR state takes effect at the rising edge of the TCK for the register indicated by the Instruction register If TMS is sampled LOW at the rising edge of TCK the controll
211. nsaction The data transaction may be qualified with both virtual address data value size and load store transaction type Bit mask and ASID values may apply in the address compare and byte mask may apply in the value compare Refer to Chapter 9 EJTAG Debug Support on page 121 for more information on hardware breakpoints An optional Test Access Port TAP provides for the communication from an EJTAG probe to the CPU through a dedicated port may also be applied to the core This provides the possibility for debugging without debug code in the application and for download of application code to the system Refer to Chapter 9 EJTAG Debug Support on page 121 for more information on the EJTAG features MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 9 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 4K Processor Core Family 10 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline The MIPS32 4K processor cores implements a 5 stage pipeline similar to the original R3000 pipeline The pipeline allows the processor to achieve high frequency while minimizing device complexity reducing both cost and power consumption This chapter contains the following sections Section 2 1 Pipeline Stages Section 2 2 Instruction C
212. nt n IBMn Register Format 31 0 IBM Table 9 9 IBMn Register Field Descriptions Fields Read Name Bit s Description Write Reset State Instruction breakpoint address mask for condition IBM 31 0 0 Corresponding address bit not masked Undefined 1 Corresponding address bit masked MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 133 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 2 8 4 Instruction Breakpoint ASID n IBASIDn Register Compliance Level Implemented only for implemented instruction breakpoints The Instruction Breakpoint ASID n JBAS Dn register has the ASID value used in the compare for instruction breakpoint n The number of bits in the ASID field is 8 to match the ASID size in the TLB This register is only valid for the 4Kc core IBASIDn Register Format 31 8 7 0 Res ASID Table 9 10 IBASIDn Register Field Descriptions Fields Read Name Bit s Description Write Reset State Res 31 8 Must be written as zero returns zero on read 0 0 ASID 7 0 Instruction breakpoint ASID value for compare R W Undefined 134 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 8 5 Instruction Breakpoint Control n IBCn Register Compliance Level Implemente
213. nterrupt 14 Hardware interrupt 4 IP 7 2 13 Hardware interrupt 3 12 Hardware interrupt 2 11 Hardware interrupt 1 10 Hardware interrupt 0 Undefined Controls the request for software interrupts IP 1 0 Undefined 9 Request software interrupt 1 8 Request software interrupt 0 Exc Code 6 2 Exception code see Table 5 17 Undefined MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 91 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 92 Table 5 16 Cause Register Field Descriptions Continued Read Description Write Reset State 30 0 ie Must be written as zero returns zero on read R 0 1 0 Table 5 17 Cause Register ExcCode Field Descriptions Exception Code Value Mnemonic Description 0 Int Interrupt 1 Mod TLB modification exception 4Kc core or Reserved 4Km and 4Kp cores 2 TLBL TLB exception load or instruction fetch 4Kc core or Reserved 4Km and 4Kp cores 3 TLBS TLB exception store 4Kc core or Reserved 4Km and 4Kp cores 4 AdEL Address error exception load or instruction fetch 5 AdES Address error exception store 6 IBE Bus error exception instruction fetch 7 DBE Bus error exception data reference load or store 8 Sys Syscall exception 9 Bp Breakpoint exception 10 RI Reserved instruction exception 11 CpU Coprocessor Unusable exception 12 Ov Integer Overflow exc
214. nting the CLZ and CLO instructions ALU for performing bitwise logical operations 4 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 1 3 Required Logic Blocks e Shifter and Store aligner 1 3 2 Multiply Divide Unit MDU The Multiply Divide unit performs multiply and divide operations In the 4Kc and 4Km processors the MDU consists of a 32x16 booth encoded multiplier result accumulation registers HI and LO a divide state machine and all multiplexers and control logic required to perform these functions This pipelined MDU supports execution of a 16x16 or 32x16 multiply operation every clock cycle 32x32 multiply operations can be issued every other clock cycle Appropriate interlocks are implemented to stall the issue of back to back 32x32 multiply operations Divide operations are implemented with a simple 1 bit per clock iterative algorithm and require 35 clock cycles in worst case to complete Early in to the algorithm detects sign extension of the dividend if it is actual size is 24 16 or 8 bit the divider will skip 7 15 or 23 of the 32 iterations An attempt to issue a subsequent MDU instruction while a divide is still active causes a pipeline stall until the divide operation is completed In the 4Kp processor the non pipelined MDU consists of a 32 bit full adder result accumulation registers HI and LO a combined multiply divide s
215. of Table of Contents List of Figures and List of Tables e Added timing information regarding Early In to divide algorithm for 4Kc and 4Km e Fixed CLO CLZ description in section 10 7 to reflect rt gt rd change in definition 01 04 March 23 2000 e Cleaned up Config register definition Defined BM field defined reset state of several fields Changed reserved fields to 0 fields e Cleaned up decode tables fixed font problems and multi line instn text e Updated PREF description e Made reset state of Statuspp 0 e Fixed some Spell check issues e Clarified Fetch and Lock CACHE description 01 05 May 8 2000 e Removed text saying that the upper bits of PrID were available for implementors e Rephrased field description of DataLo register 01 06 June 8 2000 Updated copyright and trademark notices e Clarified initialization of Status RP and WatchLo I R W bits 01 07 June 12 20909 during Cold Reset in Chapters 4 and 5 206 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All right reserved Revision Date Description Added bit numbering to Table 10 1 on page 165 describing the active bytes in various access types 01 08 July 18 2000 Reformatted Cover sheet added MD Removed PrID column from this table Corrected PrRst bit in EJTAG Control Register to control EJ_PrRst pin was EJ_PerRst pin Clarified use of S7 _Res
216. on 3 4 Virtual to Physical Address Translation 4Kc Core e Section 3 5 Fixed Mapping MMU 4Km amp 4Kp Cores e Section 3 6 System Control Coprocessor 3 1 Introduction The MMU in a 4K processor core will translate any virtual address to a physical address before a request is sent to the cache controllers for tag comparison or to the bus interface unit for an external memory reference This translation is a very useful feature for operating systems when trying to manage physical memory to accommodate multiple tasks active in the same memory possibly on the same virtual address but of course in different locations in physical memory 4Kc core only Other features handled by the MMU are protection of memory areas and defining the cache protocol In the 4Kc processor core the MMU is TLB based The TLB consists of three address translation buffers a 16 dual entry fully associative Joint TLB JTLB a 3 entry instruction micro TLB ITLB and a 3 entry data micro TLB DTLB When an address is translated the appropriate micro TLB ITLB or DTLB is accessed first If the translation is not found in the micro TLB the JTLB is accessed If there is a miss in the JTLB an exception is taken In the 4Km and 4Kp processor cores the MMU is based on a simple algorithm to translate virtual addresses into physical addresses via a Fixed Mapping FM mechanism These translations are different for various regions of the virtual address space useg kus
217. op Ada Regw 3 Divide l i l Si Sign Adjust Divide J Sign Adjust RegwW Figure 2 2 4Km Core Pipeline I Tag and Data read Instruction Decode Register file read Instruction Address Calculation stage 1 and 2 Arithmetic Logic and Shift operations Data Address Calculation D Tag and Data read Load data aligner Register file write or HI LO write The MUL instruction Uses MDU Pipeline write Reg file Carry Propagate Adder Multiply and Multiply Accumulate instructions Divide instructions Last stage of Divide is a sign adjustment One or more stall cycles Stages Figure 2 3 shows the operations performed in each pipeline stage of the 4Kp processor core 12 l l I E M A WwW l i I Cache I Dec l RegRd L act 1 AC2 I TLB IDec D AC D Cache Align Regw 2l AUO P l D TLB l l D AC l LACI AC2 i Sa Cache l A gt E Bypass l B 2 i i Align 9 l l MUL 7 L Regw gl RegW 7 ol l MUL l l l Fal Rae Sl Multiply Divide i Multiply Divid RegW 5 Ty 5 i 1 i I Tag and Data read Instruction Decode Register file read Instruction Address Calculation stage 1 and 2 Arithmetic Logic and Shift operations Data Address Calculation D Tag and Data read Load data aligner Register file wri
218. or Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 Instruction Set Perform Cache Operation cont CACHE Restrictions The operation of this instruction is UNDEFINED for any operation cache combination that is not implemented The operation of this instruction is UNDEFINED if the operaation requires an address and that address is uncache able Operation vAddr GPR base sign_extend offset pAddr uncached lt AddressTranslation vAddr DataReadReference CacheOp op vAddr pAddr Exceptions TLB Refill Exception TLB Invalid Exception Coprocessor Unusable Exception Address Error Exception Bus Error Exception MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 183 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 11 MIPS32 4K Processor Core Instructions Load Linked Word LL 31 26 25 21 20 16 15 0 LL base rt offset 110000 6 5 5 16 Format LL rt offset base MIPS32 Purpose 184 To load a word from memory for an atomic read modify write Description rt lt memory basetoffset The LL and SC instructions provide the primitives to implement atomic read modify write RMW operations for cached memory locations The 16 bit signed offset is added to the contents of GPR base to form an effective address The contents of the 32 bit word at the memory loc
219. ores 0 4Kc core 1 4Km 4Kp cores 0 Must be written as zero returns zero on read Number of data breakpoints implemented Must be written as zero returns zero on read Break status for breakpoint n is at BS n with n as 0 to 1 The bit is set to 1 when the condition for the corresponding breakpoint has matched Note a Based on actual hardware implemented Note b In case of only 1 data breakpoint bit 1 become reserved MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Undefined 137 Chapter 9 EJTAG Debug Support 9 2 9 2 Data Breakpoint Address n DBAn Register Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Address n DBAn register has the address used in the condition for data breakpoint n DBAn Register Format DBA Table 9 14 DBAn Register Field Descriptions Fields Read Name Description Write Reset State DBA 31 0 Data breakpoint address for condition R W Undefined 138 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 9 3 Data Breakpoint Address Mask n DBMn Register Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Address Mask n DBMn re
220. ossible to make the CPU go into debug mode just after hard or soft reset without fetching or executing any instructions from the normal memory area This can be used for download of code to a system which have no code in ROM The Bypass register is selected when the EJTAGBOOT instruction is given 9 3 3 9 NORMALBOOT Instruction When the NORMALBOOT instruction is given and Update IR state is left then the reset value of the ProbTrap ProbEn and EjtagBrk bits in the EJTAG Control register are set to 0 after hard or soft reset The Bypass register is selected when the NORMALBOOT instruction is given 9 3 3 10 FASTDATA Instruction This selects the Data and the Fastdata registers at once as shown in Figure 9 7 This TAP instruction was added to version 3 5 of the core In previous versions this instruction would act as a bypass This is also indicated by the change from EJTAG version 2 5 to 2 6 in the Implementation register TDI Data OY Fastdatal__ TDO Figure 9 7 TDI to TDO Path when in Shift DR State and FASTDATA Instruction is Selected 9 4 EJTAG TAP Registers The EJTAG TAP Module has one Instruction register and a number of data registers all accessible through the TAP 9 4 1 Instruction Register 150 The Instruction register is accessed when the TAP receives an Instruction register scan protocol During an Instruction register scan operation the TAP controller selects the output of the Instruction register
221. ountDM New Bits added to Debug register for handling of imprecise exceptions IEXI DBusEP IBusEP Added description of SubBlock ordering New MDU timing Updated pipeline diagrams and text in Chap 2 to reflect new timing Modified Reset description SoftReset cannot be masked by the core SoftReset does not need to be asserted when Reset is asserted ASID is not used in EJTAG breakpoint comparisons if the TLB is not implemented Added MT Compare to Timer Interrupt cleared to list of Hazard conditions Fixed Hazard from setting of SW Interrupt to Interrupted instruction Changed SPECIAL opcode map to reflect MOVCI FP instn as a Coprocessor Instn rather than a Reserved Instn L2 Cache encodings of CACHE instn are reserved Added note that I Fill CACHE instn will cause a re fetch even if the line is in the cache MUL instn description reiterates that the contents of HI LO are unpredictable after the MUL operation Added ERL 1 as possible reason for being in kernel mode in the kseg descriptions Swapped priority of RI and CU exceptions Changed general exception code pseudo code to have correct vector offset of 0x180 Fixed typo in bus error description stores OR non critical words not stores of non critical words Changed TLBWI to TLBWR in Random register description Added note that behavior is undefined if illegal page mask value is used Added note that Statusrs Statusgp and Statusyyy bits and Causeyp cannot be se
222. owing cases e No TLB entry in a TLB based MMU matches a reference to a mapped address space and the EXL bit is 1 in the Status register e A TLB entry in a TLB based MMU matches a reference to a mapped address space but the matched entry has the valid bit off e The virtual address is greater than or equal to the bounds address in a FM based MMU Cause Register ExcCode Value TLBL Reference was a load or an instruction fetch TLBS Reference was a store Additional State Saved Table 4 10 CPO Register States on a TLB Invalid Exception Register State Value BadVAddr failing address The BadVPN2 field contains VA3 3 of the failing Context addr ss The VPN2 field contains VA31 13 of the failing address EntryHi the ASID field contains the ASID of the reference that missed EntryLo0 UNPREDICTABLE EntryLol UNPREDICTABLE Entry Vector Used General exception vector offset 0x180 4 6 13 Bus Error Exception Instruction Fetch or Data Access A bus error exception occurs when an instruction or data access makes a bus request due to a cache miss or an uncacheable reference and that request terminates in an error The bus error exception can occur on either an instruction fetch or a data access Bus error exceptions that occur on an instruction fetch have a higher priority than bus error exceptions that occur on a data access Bus errors taken on the requested critical word of an instruction fetch or
223. pipeline and the MUL 32x32 will force a two cycle stall If the integer instruction immediately following the MUL operation uses its result an additional stall is forced on the IU pipeline Table 2 2 lists the repeat rates peak issue rate of cycles until the operation can be reissued for multiply accumulate subtract instructions The repeat rates are listed in terms of pipeline clocks In this table repeat rate refers to the case where the first MDU instruction in the table below if back to back with the second instruction MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 17 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline Table 2 2 4Kc and 4Km Core Instruction Repeat Rates Instruction Sequence Operand Size of Repeat 1st Instruction 1st Instruction 2nd instruction Rate MULT MULTU MADD MADDU 16 bit MADD MADDU MSUB MSUBU 1 MSUB MSUBU MULT MULTU MADD MADDU 32 bit MADD MADDU MSUB MSUBU 2 MSUB MSUBU Figure 2 8 below shows the pipeline flow for the following sequence 1 32x16 multiply Mult The 32x16 multiply operation requires one clock of each pipeline stage to complete The 32x32 requires two clocks in the Mypy pipe stage The MDU pipeline is shown as the shaded areas of Figure 2 8 and always starts a computation in the final phase of the E stage As shown in the figure the Mypy pipe stage of the MDU pipeline occurs in parallel
224. points The Data Breakpoint Control n DBCn register controls setup of data breakpoint n DBCn Register Format 24 23 22 18 17 14 13 12 11 4 3 2 1 Table 9 17 DBCn Register Field Descriptions Fields Description Read Write Reset State Must be written as zero returns zero on read Use ASID value in compare for data breakpoint n 4Kc core 0 Don t use ASID value in compare 4KG core R W ASIDuse 4Km 4Kp Undefined 1 Use ASID value in compare cores 0 Must be written as zero returns zero on read 4Km 4Kp cores Must be written as zero returns zero on read Byte access ignore controls ignore of access to specific byte BAI 0 ignores access to byte at bits 7 0 of the data bus BAI 1 ignores access to byte at bits 15 8 etc Undefined 0 Condition depends on access to corresponding byte 1 Access for corresponding byte is ignored Controls if condition for data breakpoint is never fulfilled on a store transaction 0 Condition may be fulfilled on store transaction Undefined 1 Condition is never fulfilled on store transaction Controls if condition for data breakpoint is never fulfilled on a load transaction 0 Condition may be fulfilled on load transaction Undefined 1 Condition is never fulfilled on load transaction Must be written as zero returns zero on read Byte lane mask for value compare on data breakpoint BLM 0 masks byte at bits 7 0 of the data bus BLM 1 mask
225. r Load linked address WatchLo Watchpoint address low order WatchHi Watchpoint address high order and mask Reserved Reserved Debug control and exception status DEPC Program counter at last debug exception Reserved Controls access to data and SPRAM arrays for CACHE instruction Reserved Reserved TagLo DataLo Low order portion of cache tag interface Reserved Reserved ErrorEPC Program counter at last error DESAVE 1 Registers used in memory management 2 Registers used in exception processing 3 Registers used in debug Debug handler scratchpad register MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 CPO Registers The CPO registers provide the interface between the ISA and the architecture Each register is discussed below with the registers presented in numerical order first by register number then by select field number For each register described below field descriptions include the read write properties of the field and the reset state of the field For the read write properties of the field the following notation is used Table 5 2 CPO Register Field Types Read Write Notation Hardware Interpretation Software Interpretation A field in which all bits are readable and writable by software and potential
226. r Reserved Instruction Programming Notes LL and SC are used to atomically update memory locations as shown below Lily LL 1 TO ADDI T2y EA eat SC 2 T0 BEQ 2 0 Ll NOP load counter increment try to store checking for atomicity if not atomic 0 try again branch delay slot Exceptions between the LL and SC cause SC to fail so persistent exceptions must be avoided Some examples of these are arithmetic operations that trap system calls and floating point operations that trap or require software emu lation assistance LL and SC function on a single processor for cached noncoherent memory so that parallel programs can be run on uniprocessor systems that do not support cached coherent memory access types MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 193 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 11 MIPS32 4K Processor Core Instructions Synchronize Shared Memory SYNC 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 0 SYNC stype 000000 00 0000 0000 0000 0 001111 6 15 5 6 Format SYNC stype 0 implied MIPS32 Purpose 194 To order loads and stores Description Simple Description SYNC affects only uncached and cached coherent loads and stores The loads and stores that occur before the SYNC must be completed before the loads and stores after the SYNC are allowed to start Loads are complet
227. r caused by the debug interrupt request signal to the CPU The debug interrupt exception is an asynchronous debug exception which is taken as soon as possible but with no specific relation to the executed instructions The DEPC register is set to the instruction where execution should continue after the debug handler is through The DBD bit is set based on whether the interrupted instruction was executing in the delay slot of a branch Debug Register Debug Status Bit Set DINT Additional State Saved None Entry Vector Used Debug exception vector 4 6 5 Non Maskable Interrupt NMI Exception A non maskable interrupt exception occurs when the SZ_NMI signal is asserted to the processor SJ_NMT is an edge sensitive signal only one NMI exception will be taken each time it is asserted An NMI exception occurs only at instruction boundaries so it does not cause any reset or other hardware initialization The state of the cache memory and other processor states are consistent and all registers are preserved with the following exceptions e The BEV TS SR NMI and ERL fields of the Status register are initialized to a specified state e The ErrorEPC register is loaded with PC 4 if the state of the processor indicates that it was executing an instruction in the delay slot of a branch Otherwise the ErrorEPC register is loaded with PC e PC is loaded with OxBFCO_0000 Cause Register ExcCode Value None Additional State Saved
228. r user mode The following CPU Status register bit settings determine user or kernel mode e User mode UM 1 EXL 0 and ERL 0 e Kernel mode UM 0 or EXL 1 or ERL 1 Coprocessor Accessibility The Status register CU bits control coprocessor accessibility If any coprocessor is unusable an instruction that accesses it generates an exception Coprocessor 0 is always enabled in kernel mode regardless of the setting of the CUO bit MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 87 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers Status Register Format 31 28 27 26 25 2423 22 21 20 19 18 17 16 15 87 543 2 1 0 CU3 CU0 RP R RE 0 BEV TS SR NMI 0 0 IM7 IMO R UM R ERL EXL IE Table 5 15 Status Register Field Descriptions Description i Reset State Controls access to coprocessors 3 2 1 and 0 respectively 0 access not allowed 1 access allowed Coprocessor 0 is always usable when the processor is CU3 CU0 31 28 running in kernel mode independent of the state of the Undefined CUO bit The core does not support coprocessors 1 3 but CU3 1 can still be set However processor behavior is unpredictable if a coprocessor instruction to coprocessors 1 3 is attempted with the corresponding CU3 1 bit set Enables reduced power mode The state of the RP bit is 0 for Cold available on the bus interface as the SI_RP signal Reset only Ee
229. ration the TAP selects the output of the data register to drive the TDO pin The register is updated in the Update DR state with respect to write bits This description applies in general to the following data registers e Bypass Register e Device Identification Register e Implementation Register e EJTAG Control Register ECR e Processor Access Address Register e Processor Access Data Register e FastData Register 9 4 2 1 Bypass Register The Bypass register consists of a single scan register bit When selected the Bypass register provides a single bit scan path between TDI and TDO The Bypass register allows abbreviating the scan path through devices that are not involved in the test The Bypass register is selected when the Instruction register is loaded with a pattern of all ones to satisfy the TEEE 1149 1 Bypass instruction requirement 9 4 2 2 Device Identification ID Register The Device Identification register is defined by IEEE 1149 1 to identify the device s manufacturer part number revision and other device specific information Table 9 21 shows the bit assignments defined for the read only Device Identification Register and inputs to the core determine the value of these bits These bits can be scanned out of the JD register after being selected The register is selected when the Instruction register is loaded with the IDCODE instruction Device Identification Register Format 31 28 27 12 11 1 0 a e MIPS32 4K
230. rchitecture revision level This field is always 000 to indicate revision 1 R 000 0 Revision 1 1 7 Reserved 1 Standard TLB 4Kc core R Preset 3 Fixed Mapping 4Kp 4Km cores All other values Reserved fT Kseg0 coherency algorithm Refer to Table 5 21 for the R W 010 field encoding Table 5 21 Cache Coherency Attributes C 2 0 Value Cache Coherency Attribute 0 1 3 4 5 6 Cacheable noncoherent write through no write allocate QF Uncached Note These two values are required by the MIPS32 architecture In the 4K processor cores all other values are not used For ex ample values 0 1 4 5 and 6 are not used and are mapped to 3 The value 7 is not used and is mapped to 2 Note that these values do have meaning in other MIPS Technologies processor implementations Refer to the MIPS32 specification for more information MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 97 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 98 5 2 16 Config Register CP0 Register 16 Select 1 The Config register is an adjunct to the Config register and encodes additional capabilities information All fields in the Config register are read only The instruction and data cach
231. re 2 20 IU Pipeline M to E bypass 2 8 1 Load Delay Load delay refers to the fact that data fetched by a load instruction is not available in the integer pipeline until after the load aligner in A stage All instructions need the source operands available in E stage An instruction immediately following a load instruction will if it has the same source register as was the target of the load cause an instruction interlock pipeline slip in E stage see Section 2 11 Instruction Interlocks on page 27 If not the first but the second instruction after the load use the data from the load the A to E bypass see Figure 2 19 exists to provide for stall free operation An instruction flow of this shown in Figure 2 21 24 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 9 Interlock Handling One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle WwW Load Instruction E M A Data bypass from A to E M A Consumer of Load Data Instruction One Clock Load Delay Figure 2 21 IU Pipeline A to E Data Bypass 2 8 2 Move from HI LO and CP0 Delay As indicated in Figure 2 19 not only load data but also data from a move from the HI or LO register instruction MFHI MFLO and a move from CPO MFCO0 enter the U Pipeline in A stage That is data is not available in the int
232. ring a Multiply Operation 2 6 2 Multiply Accumulate 4Kp Core Multiply accumulate operations use the same multiply machine as used for multiply only Two extra stages are needed to perform the addition subtraction The operations uses 34 cycles in Mypy stage to complete the multiply accumulate The register writeback to HI and LO are done in the A stage Figure 2 16 shows the latency for a multiply accumulate operation The repeat rate is 35 cycles as a second multiply accumulate can be in the E stage when the first multiply is in the last Mypy stage Clock 1 2 33 34 35 36 37 e EStage P Munu Stage gt Munu Stage lt Mupu Stage Ampu Stage gt Wopu Stage P gt Add Subtract Shift Accumulate LO Accumulate HI HI LO Write Figure 2 16 4Kp MDU Pipeline Flow During a Multiply Accumulate Operation 2 6 3 Divide 4Kp Core Divide operations also implement a simple non restoring algorithm This algorithm works only for positive operands hence the first cycle of the Mypvu stage is used to negate the rs operand RS Adjust if needed Note that this cycle is executed even if negation is not needed The next 32 cycle 3 34 executes an interactive add subtract shift function Two sign adjust Sign Adjust 1 2 cycles are used to change the sign of one or both the quotient and the remainder Note that one or both of these cycles are skipped if they are not needed The rule is
233. rresponds to two physical data entries an even page entry and an odd page entry The highest order virtual address bit not participating in the tag MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 3 Translation Lookaside Buffer 4Kc Core Only comparison is used to determine which of the two data entries is used Since page size can vary on a page pair basis the determination of which address bits participate in the comparison and which bit is used to make the even odd determination must be determined dynamically during the TLB lookup Figure 3 7 show the contents of one of the 16 dual entries in the JTLB Tag Entry Data Entries PFNO 31 12 Co 2 0 DO PFN1 31 12 C1 2 0 1l 20 3 1 PageMask 24 13 VPN2 31 13 ASID 7 0 19 1 8 Figure 3 7 JTLB Entry Tag and Data Table 3 6 and Table 3 7 explain each of the fields in a JTLB entry Field Name Table 3 6 TLB Tag Entry Fields Description PageMask 24 13 Page Mask Value The Page Mask defines the page size by masking the appropriate VPN2 bits from being involved in a comparison It is also used to determine which address bit is used to make the even odd page PFNO PFN1 determination See the table below PageMask 11 0 Page Size Even Odd Bank Select Bit 0000_0000_0000 4KB VAddr 12 0000_0000_0011 16KB
234. rrupts are used Compare Should be set to a known value if Timer Interrupts are used The write to compare will also clear any pending Timer Interrupts Thus Count should be set before Compare to avoid any unexpected interrupts Status Desired state of the device should be set Other Cop0 state Other registers should be written before they are read Some registers are not explicitly writable and are only updated as a by product of instruction execution or a taken exception Uninitialized bits should be masked off after reading these registers MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 113 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 6 Hardware and Software Initialization 114 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 7 Caches This chapter describes the caches present in a MIPS32 4K processor core It contains the following sections e Section 7 1 Introduction e Section 7 2 Cache Protocols e Section 7 3 Instruction Cache e Section 7 4 Data Cache e Section 7 5 Memory Coherence Issues 7 1 Introduction A 4K processor core supports separate instruction and data caches which may be flexibly configured at build time for various sizes organizations and set associativities The use of separate caches allows instruction and data referen
235. ruction or data cache configuration on a 4K core by reading the appropriate bits of the Config register see Section 5 2 16 Config Register CPO Register 16 Select 1 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 115 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 7 Caches Table 7 2 Instruction and Data Cache Sizes Cache Size bytes Way Organization Options OK No cache 1K One 1K way One 2K way 2K Two 1K ways 3K Three 1K ways One 4K way 4K Two 2K ways Four 1K ways 6K Three 2K ways Two 4K ways 8K Four 2K ways 12K Three 4K ways 16K Four 4K ways 7 2 Cache Protocols 7 2 1 Cache Organization The instruction and data caches each consist of two arrays a tag array and a data array The caches are virtually indexed since a virtual address is used to select the appropriate line within both the tag and data arrays The caches are physically tagged as the tag array contains a physical not virtual address The tag and data arrays hold n ways of information per line corresponding to the n way set associativity of the cache where n can be between 1 and 4 for a cache in a 4K core Figure 7 1 shows the format of each line of the tag and data arrays for each way A tag entry consists of the upper 22 bits of the physical address bits 31 10 4 valid bits one for each data word in the line a lock bit and a LRF bit A data entry contains
236. ry for the page determine the cacheability of a reference For the 4Km and 4Kp cores the cacheability is set via the KU field of the CPO Config register 3 2 3 Kernel Mode The processor operates in Kernel mode when the DM bit in the Debug register is 0 and the Status register contains one or more of the following values e UM 0 e ERL 1 e EXL 1 When a non debug exception is detected EXL or ERL will be set and the processor will enter Kernel mode At the end of the exception handler routine an Exception Return ERET instruction is generally executed The ERET instruction jumps to the Exception PC clears ERL and clears EXL if ERL 0 This may return the processor to User mode Kernel mode virtual address space is divided into regions differentiated by the high order bits of the virtual address as shown in Figure 3 5 Also Table 3 2 lists the characteristics of the Kernel mode segments MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation OxFFFF_FFFF 0xE000_0000 Kernel virtual address space Mapped 512MB kseg3 OxDFFF_FFFF 0xC000_0000 Kernel virtual address space Mapped 512MB kseg2 OxBFFF_FFFE 0xA000_0000 Ox9FFF_FFFF 0x8000_0000 Kernel virtual address space Unmapped Uncached 512MB Kernel virtual address space Unmapped 512MB kseg1 ksegO Ox7FFE_FFFF 0
237. s byte at bits 15 8 etc Undefined 0 Compare corresponding byte lane 1 Mask corresponding byte lane Must be written as zero returns zero on read MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 141 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support Table 9 17 DBCn Register Field Descriptions Continued Description Read Write Reset State Use data breakpoint n as triggerpoint 0 Don t use it as triggerpoint 1 Use it as triggerpoint Must be written as zero returns zero on read Use data breakpoint n as breakpoint BE 0 0 Don t use it as breakpoint R W 0 1 Use it as breakpoint 142 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 9 6 Data Breakpoint Value n DBVn Register Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Value n DBVn register has the value used in the condition for data breakpoint n DBVn Register Format DBV Table 9 18 DBVn Register Field Descriptions Fields Description Reset State DBV 31 0 Data breakpoint value for condition R W Undefined MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Te
238. s not defined after an address error exception This register is only valid with the TLB 4Kc core It is reserved if the FM is implemented 4Km and 4Kp cores EntryHi Register Format 31 13 12 8 7 VPN2 0 Table 5 13 EntryHi Register Field Descriptions Description Reset State VA3 13 Of the virtual address virtual page number 2 This field is written by hardware on a TLB exception or ona TLB read and is written by software before a TLB write 0 12 8 Must be written as zero returns zero on read 0 Undefined Address space identifier This field is written by hardware on a TLB read and by software to establish ASID 7 0 the current ASID value for TLB write and against R W which TLB references match each entry s TLB ASID field Undefined MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 85 Chapter 5 CPO Registers 86 5 2 10 Compare Register CP0 Register 11 Select 0 The Compare register acts in conjunction with the Count register to implement a timer and timer interrupt function The timer interrupt is an output of the cores The Compare register maintains a stable value and does not change on its own When the value of the Count register equals the value of the Compare register the SI_TimerInt pin is asserted This pin will remain asserted until the Compare register is written The SI
239. s through the SDBBP instruction In addition optional instruction and data virtual address hardware breakpoints and optional connection to an external EJTAG probe through the Test Access Port TAP may be included This chapter provides an overview of the MIPS32 4K processor cores and consists of the following sections e Section 1 1 Features e Section 1 2 Block Diagram MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 1 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 4K Processor Core Family e Section 1 3 Required Logic Blocks e Section 1 4 Optional Logic Blocks 1 1 Features e 32 bit Address and Data Paths e MIPS32 compatible instruction set All MIPSII instructions Multiply add and multiply subtract instructions MADD MADDU MSUB MSUBU Targeted multiply instruction MUL Zero and one detect instructions CLZ CLO Wait instruction WAIT Conditional move instructions MOVZ MOVN Prefetch instruction PREF e Programmable Cache Sizes Individually configurable instruction and data caches Sizes from 0 up to 16 Kbyte Direct mapped 2 3 or 4 Way set associative Loads that miss in the cache are blocked only until critical word is available Write through no write allocate 128 bit 16 byte cache line size word sectored suitable for standard 32 bit wide single port SRAM
240. s value may or may not be predictable e PC is loaded with OxBFCO_0000 Cause Register ExcCode Value None MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 57 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions 58 Additional State Saved None Entry Vector Used Reset OxBFCO_0000 Operation StatuSppy lt 1 Statusr lt 0 StatusSsp lt 1 Statusymr lt 0 StatuSgg lt 1 if InstructionInBranchDelaySlot then BrrorEPC lt PC 4 else ErrorEPC lt PC endif PC lt O0xBFCO_0000 4 6 3 Debug Single Step Exception A debug single step exception occurs after the CPU has executed one two instructions in non debug mode when returning to non debug mode after debug mode One instruction is allowed to execute when returning to a non jump branch instruction otherwise two instructions are allowed to execute since the jump branch and the instruction in the delay slot are executed as one step Debug single step exceptions are enabled by the SSt bit in the Debug register and are always disabled for the first one two instructions after a DERET The DEPC register points to the instruction on which the debug single step exception occurred which is also the next instruction to single step or execute when returning from debug mode So the DEPC will not point to the instruction which has just been single stepped but rather the following
241. s virtual to physical address translation and provides attributes for the different memory segments Those memory segments which are unmapped in the 4Kc TLB implementation kseg0 and kseg1 are translated identically by the FM in the 4Km and 4Kp MMU The FM also determines the cacheability of each segment These attributes are controlled via bits in the Config register Table 3 9 shows the encoding for the K23 bits 30 28 KU bits 27 25 and KO bits 2 0 of the Config register Table 3 9 Cache Coherency Attributes Config Register Fields K23 KU and K0 Cache Coherency Attribute 0 1 3 4 5 6 Cacheable noncoherent write through no write allocate 2 7 Uncached In the 4Km and 4Kp cores no translation exceptions can be taken although address errors are still possible Table 3 10 Cacheability of Segments with Block Address Translation Virtual Address Segment Range Cacheability Geenseuse 0x0000_0000 Controlled by the KU field bits 27 25 of the Config register Refer to 8 8 0x7EFF_FFFF Table 3 9 for the encoding kseg0 0x8000_0000 Controlled by the KO field bits 2 0 of the Config register See Table 0x9FFF_FFFF 3 9 for the encoding 0xA000_0000 kseg1 Always uncacheable OxBFFF_FFFF cece O0xC000_0000 Controlled by the K23 field bits 30 28 of the Config register Refer to 8 0xDFFF_FFFF Table 3 9 for the encoding MIPS32 4K Processor Core Family Software User s Manual Rev
242. saecaecaeecaecsaeaecesesesnsseeeeaeees 129 9 2 8 Insteuction Breakpoint Registers cf sesso ce e dius E condense E a E E E E E ESEAS ENRE 130 9 2 9 Data Breakpoint Registers Aongea eee Ea reae Eea EE r Ep BIE EEES RAE EOK Ea EEE E ENEE EUNT ER 136 9 3 Test Access oa A D a A E E E EE A SE PE E E E E E deeds 144 9 3 1 EJTAG Internal and External Interfaces 2 ceecesecesceseeeeceseeeeceseeeaeeseecaecaeecaecsaeaecsaeeesneeeneeeees 144 9 3 2 Test Access Port Operation ssiri neee e E EES A E E E E EA 145 vi MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All right reserved 9 3 3 Test Access Port TAP Instructions 3 c0 cs5s ccecccceeeccaceced ca sdeda ced ecbeedateteshcededpccesesgaenesecdcustecceessaateneeeveantanes 148 DA EYTAG TAP EALES KoE EE ENE stees EEE EE su tes uyaters E E supe oceatls sostess vues saes spans evnesipeuces E E 150 9 4 Instruction Repistet lt 36 sis ae naa a eee Sneath a as 150 9 4 2 Data Re pisters Overview aiee E e Deena dune stnes A EN ch can coues E E E elites E EEEE EEN 151 9 4 3 Processor Access Address Register oo ieeceseeccescesscesceseeeeceeeeeaeeseecsecsaecaecsaecaecsaeaecseessceseeeseaeeeeseaeeaaeens 157 9 4 4 Fastdata Register TAP Instruction FASTDATA ooo eee eeeceeeecesseceececeseeensecenceceeeeeneeeeneesaeceeeeceseecsaeeaees 158 J S PLOCESSOFACCESSES iis heae ss Bea a apes Ne ated os MO os ee ek Mas 159 9 5
243. seg3 0xE00 0_0 000 0xE000_0000 kseg2 kseg2 0xC000_0000 OxCO00_0000 kseg1 0xA000_0000 reserved ksegO Ox8000_0000 useg kuseg useg kuseg kseg0 kseg1 Ox0000_0000 Ox0000_0000 Figure 3 12 FM Memory Map ERL 1 in the 4Km and 4Kp Processor Cores 3 6 System Control Coprocessor The System Control Coprocessor CPO is implemented as an integral part of the 4K processor cores and supports memory management address translation exception handling and other privileged operations Certain CPO registers are used to support memory management Refer to Chapter 5 CPO Registers on page 73 for more information on the CPO register set MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 49 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management 50 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions All The MIPS32 4K processor cores receives exceptions from a number of sources including translation lookaside buffer TLB misses 4Kc core only arithmetic overflows I O interrupts and system calls When the CPU detects one of these exceptions the normal sequence of instruction execution is suspended and the processor enters kernel mode In kernel mode the core disables interrupts and forces
244. sseseaeseaseseseaeeaaeeaesaes 15 Figure 2 7 Load Store Cache Miss Timing 4Km and 4Kp Cores 00 eeeeceeceeseeecsceeseceseeaeceecseceseeseeeeeeseseaeeeseaeeaeeeaeaee 16 Figure 2 8 MDU Pipeline Behavior during Multiply Operations 4Kc and 4Km processors ecceeeesseeeeeeeseeeseeeee 18 Figure 2 9 MDU Pipeline Flow During a 32x16 Multiply Operation 200 0 ceseeseceeceeceeceseeeeeeeseeeeseeeeecaeeeaeeaee 19 Figure 2 10 MDU Pipeline Flow During a 32x32 Multiply Operation 00 eee ceseeeeceeceeceeeeseeeeeeeeeeeeseeeeeeneeeneeaee 19 Figure 2 11 MDU Pipeline Flow During an 8 bit Divide DIV Operation 00 0 cece ceceseceeceseeeeeeseseeeeseeeeeeseeeaeenes 20 Figure 2 12 MDU Pipeline Flow During a 16 bit Divide DIV Operation 000 0 eee eee ceceseceeeeseeeeeeeeeeeceseeeeeeaeeeaenes 20 Figure 2 13 MDU Pipeline Flow During a 24 bit Divide DIV Operation 0 0 0 eee ceceseceeceseeeeeeseeeeeeseeeeeeseeeaenee 20 Figure 2 14 MDU Pipeline Flow During a 32 bit Divide DIV Operation 000 0 cece eee ceceseceeceseeeeeeseeeeeeseseeeeaeeeneeaee 20 Figure 2 15 4Kp MDU Pipeline Flow During a Multiply Operation eee ceeeeceeceeceeceseeeeeeeeeeeeaeeeaecaeeeneaes 22 Figure 2 16 4Kp MDU Pipeline Flow During a Multiply Accumulate Operation 0 0 0 0 eee eee cesses ceeeeeeeeseeeeeeseeeneenes 22 Figure 2 17 4Kp MDU Pipeline Flow During a Divide DIV Operation 0 eee eee ceseeseceeeeeeceeeeseeeeeeeeeeeeeaeeeaeaes 22 Figure 2 18 TU Pipeline Branch Delay
245. ssor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation e User mode e Kernel mode e Debug mode User mode is most often used for application programs Kernel mode is typically used for handling exceptions and privileged operating system functions including CPO management and I O device accesses Debug mode is used for software debugging and most likely occurs within a software development tool The address translation performed by the MMU depends on the mode in which the processor is operating 3 2 1 Virtual Memory Segments The Virtual memory segments are different depending on the mode of operation Figure 3 3 shows the segmentation for the 4 GByte 23 bytes virtual memory space addressed by a 32 bit virtual address for the three modes of operation The core enters Kernel mode both at reset and when an exception is recognized While in Kernel mode software has access to the entire address space as well as all CPO registers User mode accesses are limited to a subset of the virtual address space 0x0000_0000 to 0x7FFF_FFFF and can be inhibited from accessing CPO functions In User mode virtual addresses 0x8000_0000 to OXFFFF_FFFF are invalid and cause an exception if accessed Debug mode is entered on a debug exception While in Debug mode the debug software has access to the same address space and CPO registers as for Kernel mode In a
246. state 9 3 3 Test Access Port TAP Instructions The TAP Instruction register allows instructions to be serially input into the device when TAP controller is in the Shift IR state Instructions are decoded and define the serial test data register path that is used to shift data between TDI and TDO during data register scanning The Instruction register is a 5 bit register In the current EJTAG implementation only some instructions have been decoded the unused instructions are set default to the BYPASS instruction Table 9 20 Implemented EJTAG Instructions Value Instruction Function 0x01 IDCODE Select Chip Identification data register 0x03 IMPCODE Select Implementation Register 0x08 ADDRESS Select Address register 0x09 DATA Select Data register 148 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 3 Test Access Port TAP Table 9 20 Implemented EJTAG Instructions Value Instruction Function Ox0A CONTROL Select EJTAG Control register 0x0B ALL Select the Address Data and EJTAG Control registers 0x0C EJTAGBOOT Set EjtagBrk ProbEn and ProbTrap to 1 as reset value 0x0D NORMALBOOT Set EjtagBrk ProbEn and ProbTrap to 0 as reset value Ox0E FASTDATA Selects the Data and Fastdata registers Ox1F BYPASS Bypass mode 9 3 3 1 BYPASS Instruction The required BYPASS instruction allows the processor to rem
247. t Registers Register Offset in drseg Mnemonic Register Name and Description 0x2000 DBS Data Breakpoint Status 0x2100 0x100 n DBAn Data Breakpoint Address n 0x2108 0x100 n DBMn Data Breakpoint Address Mask n 0x2110 0x100 n DBASIDn Data Breakpoint ASID n 4K core 0x2118 0x100 n DBCn Data Breakpoint Control n 0x2120 0x100 n DBVn Data Breakpoint Value n Note n is breakpoint number as 0 or 1 or just 0 depending on the implemented hardware An example of some of the registers DBMO is at offset 0x2108 and DBV J is at offset 0x2220 136 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 9 1 Data Breakpoint Status DBS Register Compliance Level Implemented only if any data breakpoints The Data Breakpoint Status DBS register holds implementation and status information about the data breakpoints The ASID applies to all the data breakpoints for the 4Kc core DBS Register Format 31 30 29 28 27 24 23 21 0 Res ASID Res BCN Res BS sup Table 9 13 DBS Register Field Descriptions Fields Description Reset State Must be written as zero returns zero on read 4Kc core Indicates that ASID compare is supported in data breakpoints ASIDsup 4Km 4Kp cores Must be written as zero returns zero on read 4Kc core R 4Km 4Kp c
248. t by software Noted undefined behavior if Statusppy is set while executing code in useg kuseg Added Config pc and Configl bits Both wired to 0 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 205 Copyright 2000 2002 MIPS Technologies Inc All right reserved Appendix A Revision History Revision Date Description e Changed Reset state of Watch Watchp and Watchw to 0 from undefined e Removed some false statements about WAIT induced sleep mode e CLO CLZ instn description changed to reflect use of rd as destination register instead of rt 1 1 continue November 1999 e Add sel field to format statements in MFCO MTCO instns e Removed redundant statement about writeback invalidate from PREF instn e Add programming note to multiply instructions that smaller source value should be placed in rt e Updated listing of HW initialized Cop0 bits in Reset chapter e Removed implication of internal mux for SI_TimerInt from Ka December 27 description of Compare register e Cleaned up old references to both cores e Fixed some typos Fixed pipe stages in figure 2 12 e Added details on D side micro TLB 01 03 January 28 2000 e Cleaned up usage of trademarks e Renamed title to MIPS32 4k Processor Core Family Software User s Manual e Changed revision numbering to xx yy format for consistency with other documents e Cleaned up some old paragraph leftovers e Changed look
249. t is reserved if the FM is implemented 4Km and 4Kp cores Entry n 1 A z 0 gr Cc oO ia Wired Register v A ke 2 Entry 0 v Figure 5 1 Wired and Random Entries in the TLB Wired Register Format 31 4 3 0 0 Wired Table 5 10 Wired Register Field Descriptions Fields Bit s Description 0 31 4 Must be written as zero returns zero on read 0 0 Wired 3 0 TLB wired boundary R W 0 82 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers 5 2 7 BadVAddr Register CPO Register 8 Select 0 The BadVAdar register is a read only register that captures the most recent virtual address that caused one of the following exceptions e Address error AdEL or AdES e TLB Refill 4Kc core e TLB Invalid 4Kc core e TLB Modified 4Kc core The BadVAddr register does not capture address information for cache or bus errors since neither is an addressing error BadVAdar Register Format 31 0 BadVAddr Table 5 11 BadVAddr Register Field Description Fields Read Name Bits Description Write Reset State BadVAddr 31 0 Bad virtual address R Undefined MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 83 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 8 Count Register CP
250. ta Hardware Breakpoint Overview 4Kc Core TYPE J ADDR Data Debug Exception a Hardware oe BYTELANE Breakpoint Trigger Indication DATA p Figure 9 4 Data Hardware Breakpoint Overview 4Km 4Kp Core When a data breakpoint matches a debug exception and or a trigger is generated and an internal bit in the data breakpoint registers is set to indicate that the match occurred The match is either precise whereby the debug exception or trigger occurs on the instruction that caused the breakpoint to match or it is imprecise whereby the debug exception or trigger occurs later in the program flow 9 2 3 Overview of Registers for Instruction Breakpoints The register with implementation indication and status for instruction breakpoints in general is shown in Table 9 2 Table 9 2 Overview of Status Register for Instruction Breakpoints Register Mnemonic Register Name and Description IBS Instruction Breakpoint Status The four instruction breakpoints are numbered 0 to 3 for registers and breakpoints and the number is indicated by n The registers for each breakpoint are shown in Table 9 3 Table 9 3 Overview of Registers for each Instruction Breakpoint Register Mnemonic Register Name and Description IBAn Instruction Breakpoint Address n IBMn Instruction Breakpoint Address Mask n IBASIDn Instruction Breakpoint ASID n 4Kc core IBCn Instruction Breakpoint Control n MIPS32 4K Pro
251. tate machine and all multiplexers and control logic required to perform these functions It performs any multiply using 32 cycles in an iterative 1 bit per clock algorithm Divide operations are also implemented with a simple 1 bit per clock iterative algorithm no early in and require 35 clock cycles to complete An attempt to issue a subsequent MDU instruction while a multiply divide is still active causes a pipeline stall until the operation is completed An additional multiply instruction MUL is implemented which specifies that the lower 32 bits of the multiply result be placed in the register file instead of the HI LO register pair By avoiding the explicit move from LO MFLO instruction required when using the LO register and by supporting multiple destination registers the throughput of multiply intensive operations is increased Two instructions multiply add MADD MADDU and multiply subtract MSUB MSUBU are used to perform the multiply add and multiply subtract operations The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers Similarly the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers The MADD MADDU and MSUB MSUBU operations are commonly used in Digital Signal Processor DSP algorithms 1 3 3 System Control Coprocessor CPO In the MIPS architecture CPO is responsible for the virtual to physical address trans
252. tch or Data Access The Watch facility provides a software debugging vehicle by initiating a watch exception when an instruction or data reference matches the address information stored in the WatchHi and WatchLo registers A Watch exception is taken immediately if the EXL and ERL bits of the Status register are both zero and the DM bit of the Debug is also zero If any of those bits is a one at the time that a watch exception would normally be taken the WP bit in the Cause register is set and the exception is deferred until both all three bits are zero Software may use the WP bit in the Cause register to determine if the EPC register points at the instruction that caused the watch exception or if the exception actually occurred while in kernel mode The Watch exception can occur on either an instruction fetch or a data access Watch exceptions that occur on an instruction fetch have a higher priority than watch exceptions that occur on a data access Register ExcCode Value WATCH Additional State Saved Table 4 7 Register States on a Watch Exception Register State Value Indicates that the watch exception was deferred until after Statuspy Statusgry and Debugpyy were zero This bit directly causes a watch exception so software must clear this bit as part of the exception handler to prevent a watch exception loop at the end of the current handler execution Causewp Entry Vector Used General exception vector o
253. te add This includes the accumulate step for the MADD MSUB operations The actual register writeback to HI and LO is performed in the W stage 4Kc and 4Km cores e A divide operation perform the final Sign Adjust The actual register writeback to HI and LO is performed in the W stage 4Kc and 4Km cores A multiply divide operation writes to HI LO registers 4Kp core only 2 1 5 W Stage Writeback e For register to register or load instructions the result is written back to the register file during the W stage 2 2 Instruction Cache Miss When the instruction cache is indexed the instruction address is translated to determine if the required instruction resides in the cache An instruction cache miss occurs when the requested instruction address does not reside in the instruction cache When a cache miss is detected in the I stage the core transitions to the E stage The pipeline stalls in the E stage until the miss is resolved The bus interface unit must select the address from multiple sources If the address bus is busy the request will remain in this arbitration stage B ASel in Figure 2 4 and Figure 2 5 until the bus is available The core drives the selected address onto the bus The number of clocks required to access the bus is determined by the access time of the array that contains the data The number of clocks required to return the data once the bus is accessed is also determined by the access time of the array Once the dat
254. te into the TLB There could be a TLB miss again during the mapping of the data or instruction address The processor will jump to the general exception vector since the EXL is 1 Option to complete the first level refill in the general exception handler or ERET to the original instruction and take the exception again ERET is not allowed in the branch delay slot of another Jump Instruction Processor does not execute the instruction which is in the ERET s branch delay slot PC lt EPC EXL lt 0 LLbit lt 0 Figure 4 4 TLB Exception Servicing Guidelines SW 4Kc Core only MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 71 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions Reset Exception Random lt TLBENTRIES 1 4Kc core only Wil 0 4K Soft Reset or NMI Exception Haiti oe y Status Status BEV lt 1 RP lt 0 ie BEV lt 1 SR lt 1 0 TS lt 0 NMI lt 0 1 SR lt 0 ERL lt 1 NMI lt 0 ERL lt 1 WatchLo R W lt 0 ErrorEPC lt PC Reset Soft Reset amp NMI Exception Handling HW PC lt 0xBFCO_0000 Guidelines SW Reset Soft Reset amp NMI Servicing 3 Soft Reset Service Code i Reset Service Code l a e 2564 5 SS SS Se See E ere E Se Optional Figure 4 5 Reset Soft Reset and NMI Exception Handling and Servicing Guidelines 72 MIPS3
255. te or HI LO write The MUL instruction Uses MDU Pipeline write Reg file Multiply Multiply Accumulate and Divide instructions One or more stall cycles Figure 2 3 4Kp Core Pipeline Stages MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 1 Pipeline Stages 2 1 1 I Stage Instruction Fetch During the Instruction fetch stage e An instruction is fetched from the instruction cache The I TLB performs a virtual to physical address translation 4Kc core only 2 1 2 E Stage Execution During the Execution stage e Operands are fetched from the register file Operands from M and A stage are bypassed to this stage The Arithmetic Logic Unit ALU begins the arithmetic or logical operation for register to register instructions The ALU calculates the data virtual address for load and store instructions The ALU determines whether the branch condition is true and calculates the virtual branch target address for branch instructions Instruction logic selects an instruction address All multiply and divide operations begin in this stage 2 1 3 M Stage Memory Fetch During the Memory Fetch stage The arithmetic or logic ALU operation completes The data cache fetch and the data virtual to physical address translation are performed for load and store instructions Data TLB 4Kc core only and data cache lookup ar
256. ter 11 MIPS32 4K Processor Core Instructions 174 Table 11 7 Instruction Set Continued Instruction Description Function MTCO Move To Coprocessor 0 CPR O n Rt SEL MTHI Move To HI HI Rs MTLO Move To LO LO Rs MUL Multiply with register write T Go MULT Integer Multiply HI LO int Rs int Rd MULTU Unsigned Multiply HI LO uns Rs uns Rd No Operation NOP Asembler idiom for SLL r0 r0 r0 NOR Logical NOR Rd Rs Rt OR Logical OR Rd Rs Rt ORI Logical OR Immediate Rt Rs Immed PREF Prefetch Load Specified Line into Cache SB Store Byte byte Mem Rs offset Rt if LL 1 SC Store Conditional Word mem Rxoffs Rt Rt LL SDBBP Software Debug Break Point Trap to SW Debug Handler SH Store Half halfyMem Rs offset Rt SLL Shift Left Logical Rd Rt lt lt sa SLLV Shift Left Logical Variable Rd Rt lt lt Rs 4 0 if int Rs lt int Rt SLT Set on Less Than Ro else Rd 0 if int Rs lt int Immed SLTI Set on Less Than Immediate Ee i d Rt 0 if uns Rs lt uns Immed SLTIU Set on Less Than Immediate Unsigned T t l Rt 0 if uns Rs lt uns Immed SLTU Set on Less Than Unsigned a 3 l Rd 0 SRA Shift Right Arithmetic Rd int Rt gt gt sa SRAV Shift Right Arithmetic Variable Rd int Rt gt gt Rs 4 0 SRL Shift Right Logical Rd uns Rt gt gt sa SRLV Shift Right Logical Variable Rd uns Rt gt gt Rs 4 0 MIPS32 4K Processor Core Family
257. ter Format 31 28 27 0 0 PAddr 31 4 Table 5 23 LLAddr Register Field Descriptions Description Reset State Must be written as zero returns zero on read This field encodes the physical address read by the most PAddr 31 4 27 0 recent Load Linked instruction B Undefined MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 99 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 18 WatchLo Register CP0 Register 18 The WatchLo and WatchHi registers together provide the interface to a watchpoint debug facility that initiates a watch exception if an instruction or data access matches the address specified in the registers As such they duplicate some functions of the EJTAG debug solution Watch exceptions are taken only if the EXL and ERL bits are zero in the Status register If either bit is a one the WP bit is set in the Cause register and the watch exception is deferred until both the EXL and ERL bits are zero The WatchLo register specifies the base virtual address and the type of reference instruction fetch load store to match WatchLo Register Format 31 3 2 1 0 VAddr I R W Table 5 24 WatchLo Register Field Descriptions Description Reset State This field specifies the virtual address to match Note that this is a doubleword address since bits 2 0 are used to Undefined control the type of match
258. ter States on a Coprocessor Unusable Exception Register State Value Causecg unit number of the coprocessor being referenced Entry Vector Used General exception vector offset 0x180 4 6 19 Execution Exception Integer Overflow The integer overflow exception is one of the six execution exceptions All of these exceptions have the same priority An integer overflow exception occurs when selected integer instructions result in a 2 s complement overflow Cause Register ExcCode Value Ov Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 6 20 Execution Exception Trap The trap exception is one of the six execution exceptions All of these exceptions have the same priority A trap exception occurs when a trap instruction results in a TRUE value MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 65 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions 66 Cause Register ExcCode Value Tr Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 6 21 Debug Data Break Exception A debug data break exception occurs when a data hardware breakpoint matches the load store transaction of an executed load store instruction The DEPC register and DBD bit in the Debug register will indicate the load store instruction that caused the data hardware breakpoint to
259. the TCK clock domain gets effect in the CPU clock domain and in peripherals When the bit is written to 0 then the bit must also be read as 0 before it is guaranteed that the indication is cleared in the CPU clock domain also PrRst 16 This bit controls the EJ_PrRst signal If the signal is used in the system then it must be ensured that both the processor and all devices required for a reset are properly reset Otherwise the system may fail or hang The bit resets itself since the EJTAG Control register is reset by hard or soft reset MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 155 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support Table 9 23 EJTAG Control Register Descriptions Continued Description Reset State Probe Enable This bit indicates to the CPU if the EJTAG memory is handled by the probe so processor accesses are answered 0 The probe does not handle EJTAG memory transactions 1 The probe does handle EJTAG memory transactions It is an error by the software controlling the probe if it sets the ProbTrap to 1 but the ProbEn to 0 The operation of the processor is UNDEFINED in this case Oorl1 ProbEn The ProbEn bit is reflected as a read only bit in the from ProbEn bit bit 0 in the Debug Control Register DCR EJTAGBOOT The read value indicates the effective value in the DCR due to synchronization issues bet
260. the following exceptions and guidelines for their handlers e General exceptions and their exception handler e TLB miss exceptions and their exception handler 4Kc core e Reset soft reset and NMI exceptions and a guideline to their handler e Debug exceptions Generally speaking the exceptions are handled by hardware HW the exceptions are then serviced by software SW Note that unexpected debug exceptions to the debug exception vector at OxBFCO_0200 may be viewed as a reserved instruction since uncontrolled execution of a SDBBP instruction caused the exception The DERET instruction must be used at return from the debug exception handler in order to leave debug mode and return to non debug mode The DERET instruction returns to the address in the DEPC register MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 67 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions Exceptions other than Reset Soft Reset NMI or first level TLB miss 4Kc core only Note Interrupts can be masked by IE or IMs and Watch is masked if EXL 1 Comments EntryHi lt VPN2 ASID Context lt VPN2 Set Cause EXCCode CE BadVA lt VA EntryHi and Context are set only for TLB Invalid Modified amp Refill exceptions 4Kc core only BadVA is set only for TLB Invalid Modified and Refill exceptions 4Kc core only Note not set on Bus Errors Check if exception within
261. the four 32 bit words in the line for a total of 16 bytes Not every word need be present in the data array hence the per word validity information stored with the tag A word is the minimum valid quanta so it is not possible to hold a partially valid subword Once a valid word is resident in the cache byte halfword or tri byte stores can update a portion of the word 22 4 1 1 Tag PA Valid L LRF 32 32 32 32 Data Word3 Word2 Word1 Word0 Figure 7 1 Cache Array Formats 116 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 7 3 Instruction Cache 7 2 2 Cacheability Attributes All the The 4K cores supports the following cacheability attributes Uncached Addresses in a memory area indicated as uncached are not read from the cache Stores to such addresses are written directly to main memory without changing cache contents Write through Loads and instruction fetches first search the cache reading main memory only if the desired data does not reside in the cache On data store operations the cache is first searched to see if the target address is cache resident If it is resident the cache contents are updated and main memory is also written If the cache lookup misses on a store only main memory is written Hence the allocation policy on a cache miss is read allocate only Some segments of memory employ a fixe
262. the page size The remaining 20 bits of the address represent the virtual page number VPN that index the 1M entry page table The bottom portion of Figure 3 9 shows the virtual address for a 16 MByte page size The remaining 8 bits of the address represent the VPN that index the 256 entry page table 44 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 4 Virtual to Physical Address Translation 4Kc Core Virtual address with 1M 22 4 KByte pages 39 32 31 20 bits 1M pages 12 11 0 ASID VPN Offset Va Virtual to physical Offset passed unchanged translation in TLB to physical memory Bit 31 of the virtual address selects user and kernel y 32 bit Physical Address address spaces 31 0 PFNO Offset Virtual to physical Offset passed unchanged translation in TLB to physical memory M TLB A ai SN A 39 32 31 24 23 0 ASID VPN Offset 8 bits 256 pages Virtual Address with 256 28 1 6 MByte pages Figure 3 9 32 bit Virtual Address Translation 3 4 1 Hits Misses and Multiple Matches Each JTLB entry contains a tag and two data fields If a match is found the upper bits of the virtual address are replaced with the page frame number PFN stored in the corresponding entry in the data array of the JTLB The granularity of JTLB mappings is defined in terms of TLB pages The 4Kc core JTLB supports pages o
263. the reset value when the TCK applies The first 5 TCK clocks after hard or soft CPU reset may result in reset of the bits due to synchronization between clock domains ETAG Control Register Format 31 30 29 28 23 22 21 20 18 17 16 11 43 2 0 CS e A a e E Table 9 23 EJTAG Control Register Descriptions Fields Bit s Description i Reset State Reset Occurred The bit indicates if hard or soft reset has occurred 0 No reset occurred since bit last cleared 1 Reset occurred since bit last cleared The Rocc bit will keep the 1 value as long as hard or soft Rocce 31 reset is applied 1 This bit must be cleared by the probe to acknowledge that the incident was detected The EJTAG Control register is not updated in the Update DR state unless Rocc is 0 or written to 0 This is in order to ensure prober handling of processor access MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 153 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support Table 9 23 EJTAG Control Register Descriptions Continued Description Reset State Processor Access Transfer Size These bits are used in combination with the lower two address bits of the Address register to determine the size of a processor access transaction The bits are only valid when processor access is pending PAA 1 0 Psz 1 0 Transfer Size 00 00 Byte LE byte 0 BE byte 3 Byt
264. time The write buffer is organized as two 16 byte buffers Each buffer contains data from a single 16 byte aligned block of memory One buffer contains the data currently being transferred on the external interface while the other buffer contains accumulating data from the core 1 3 7 Power Management MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 The core offers a number of power management features including low power design active power management and power down modes of operation The core is a static design that supports a WAIT instruction designed to signal the rest Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 4K Processor Core Family of the device that execution and clocking should be halted hence reducing system power consumption during idle periods The core provides two mechanisms for system level low power support e Register controlled power management e Instruction controlled power management In register controlled power management mode the core provides three bits in the CPO Status register for software control of the power management function and allows interrupts to be serviced even when the core is in power down mode In instruction controlled power down mode execution of the WAIT instruction is used to invoke low power mode Refer to Chapter 8 Power Management on page 119 for more information on power managem
265. ting data breakpoint with data value compare on such T O devices Debug software is responsible for disabling breakpoints when returning to the instruction otherwise the debug data break exception will reoccur 9 2 7 Breakpoint used as Triggerpoint Both instruction and data hardware breakpoints may be set up by software so a matching breakpoint does not generate a debug exception but only an indications through the BS n bit The TE bit in the JBCn or DBCn register controls if a instruction respectively data breakpoint is used as a so called triggerpoint The triggerpoints are like breakpoints only compared for instructions executed in non debug mode The BS n bit in the JBS or DBS register is set when the respective IB_match or DB_match bit is true MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 129 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 2 8 Instruction Breakpoint Registers The registers for instruction breakpoints are described below These registers have implementation information and are used to set up the instruction breakpoints All registers are in drseg and the addresses are shown in Table 9 6 Table 9 6 Addresses for Instruction Breakpoint Registers Register Offset in drseg Mnemonic Register Name and Description 0x1000 IBS Instruction Breakpoint Status 0x1100 n 0x100 IBAn Instruction Breakpoint Address n 0
266. tion eee eee ceseeeceeeeseceseeeeecaeeesecaeesaecaaesaecnecssecuecsaeeaeeeseseaeeaeseneeaaeenecaes 86 Table 5 gt 132 Status Re sister Field Descriptions rcssesscescepessestesdeausependipeecseteoages einen E steerer E E A REEE 88 Table 5 16 Cause Register Field Descriptions 20 0 0 eee eeeeceseeeeceeeeeeceseeeeecaeecaecaeesaecaaesaecnecssecuscseeeeeseseaseaeseaecaeeeaesaes 91 Table 5 17 Cause Register ExcCode Field Descriptions 0 0 0 eee eeeecseseeeeecseeesecseesaecsaeeaeceeceaeceeceseeeeeseseaseaeseesaaseaesaee 92 Table 5 18 EPC Register Field Description ce ceseeesceseeeeceseeeeceseeeeecaeeeaecaaesaecaacsaecnscsseceeeseeeeeseseaeeaeseaesaeeeaeeaes 93 Table 5 19 PRid Register Field Descriptions erennere carves E Ns eae AEAEE bans canteen eee oa ooet 94 Table 5 20 Config Register Field Descriptions 2 0 0 eee ce ceeecseceeeseceseesecesceseceeeeseeeaeeeeecseesaecaeesaecaecsaeceesaesseeeeeeeeeeeees 95 Table 5 21 Cache Coherency A ttri Dates a e e a a e E costa EEE E aT O SE E ETEO EPKER S EHEN EES NE Epro e EE aes 96 Table 5 22 Config1 Register Field Descriptions Select 1 sesssessesesseeesssessrsresrsrrsresrsresresrsresreststrsrerrssretesreresresesreneeees 98 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All right reserved xi xii Table 5 23 LLAddr Register Field Descriptions 2 00 00 eee ceeeecesseesceseeeeceseeeeecaeecaecacesaecsaesae
267. tion Sequence 1st Instruction Latency Rs Rt 1st Instruction 2nd instruction clocks MADD MADDU any any MULT MULTU MSUB MSUBU or 32 MFHI MFLO MADD MADDU any any MADD MADDU MSUB MSUBU or 34 MSUB MSUBU MFHI MFLO any any Integer operation 32 any any MFHI MFLO 33 pos pos MFHI MFLO 33 any neg DIV MFHI MFLO ag any any MFHI MFLO Integer operation 2 MADD MADDU any any MTHI MTLO MSUB MSUBU 1 Note 1 Integer Operation refers to any integer instruction that uses the result of a previous MDU operation 2 6 1 Multiply 4Kp Core Multiply operations implement a simple iterative multiply algorithm Using Booth s approach this algorithm works for both positive and negative operands The operation uses 32 cycles in Mypy stage to complete a multiplication The register writeback to HI and LO are done in the A stage For MUL operations the register file writeback is done in the Ww Stage Figure 2 15 shows the latency for a multiply operation The repeat rate is 33 cycles as a second multiply can be in the first Myspy stage when the first multiply is in Ayny stage MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 21 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline Clock 1 2 33 34 35 E Stage gt 4Mupu Stage P Aunu Stage gt 4 Wupu Stage gt Add sub shift HI LO Write Reg WR Figure 2 15 4Kp MDU Pipeline Flow Du
268. to a physical address In this figure the virtual address is extended with an 8 bit address space identifier ASID which reduces the frequency of TLB flushing during a context switch This 8 bit ASID contains the number assigned to that process and is stored in the CPO EntryHi register MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 43 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management Virtual Address Offset 1 Virtual address VA represented by the virtual page number VPN is compared with tag in TLB 2 If there is a match the page frame ASID VPN2 number PFNO or PFN1 representing the upper bits of the f TLB physical address PA is output from y 3 The Offset which does not pass through the TLB is then concatenated Offset with the PFN Physical Address Figure 3 8 Overview of a Virtual to Physical Address Translation in the 4Kc Core If there is a virtual address match in the TLB the physical frame number PFN is output from the TLB and concatenated with the Offset to form the physical address The Offset represents an address within the page frame space As shown in Figure 3 8 the Offset does not pass through the TLB Figure 3 9 shows a flow diagram of the 4Kc core address translation process The top portion of the figure shows a virtual address for a 4 KByte page size The width of the Offset is defined by
269. to drive the TDO pin The shift register consists of a series of bits arranged to form a single scan path between TDI and TDO During an Instruction MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 4 EJTAG TAP Registers register scan operations the TAP controls the register to capture status information and shift data from TDI to TDO Both the capture and shift operations occur on the rising edge of TCK However the data shifted out from the TDO occurs on the falling edge of TCK In the Test Logic Reset and Capture JR state the instruction shift register is set to 000015 as for IDCODE instruction This forces the device into the functional mode and selects the Device ID register The Instruction register is 5 bits wide The instruction shifted in takes effect for the following data register scan operation A list of the implemented instructions are listed in Table 9 20 on page 148 9 4 2 Data Registers Overview The EJTAG uses several data registers which are arranged in parallel from the primary TDI input to the primary TDO output The Instruction register supplies the address that allows one of the data registers to be accessed during a data register scan operation During a data register scan operation the addressed scan register receives TAP control signals to capture the register and shift data from TDI to TDO During a data register scan ope
270. to the Instruction register or data registers on the rising edge of the TCK clock depending on the TAP controller state TDI The core signal for this is called EJ_TDI Test Data Output Serial output data is shifted from the Instruction or data register to the TDO o TDO pin at the falling edge of the TCK clock When no data is shifted out the TDO is 3 stated The core signal for this is called EJ_TDO with output enable control by EJ_TDOzstate 144 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 3 Test Access Port TAP Table 9 19 EJTAG Interface Pins Continued Pin Type Description Test Reset Input Optional pin The TRST_N pin is an active low signal for asynchronous reset of the TAP controller and instruction in the TAP module independent of the processor logic The processor is not reset by the assertion of TRST_N TRST_N I The core signal for this is called EJ_TRST_N This signal is optional but power on reset must apply a low pulse on this is signal at power on and then leave it high in case the signal is not available as a pin on the chip If available on the chip then it must be low on the board when the EJTAG debug features are unused by the probe 9 3 2 Test Access Port Operation The TAP controller is controlled by the Test Clock TCK and Test Mode Select TMS inputs These two inp
271. to the instruction otherwise the debug instruction break exception reoccurs 9 2 6 2 Debug Exception by Data Breakpoint If the breakpoint is enabled by BE in the DBCn register then a debug exception occurs when the DB_match condition is true The corresponding BS n bit in the DBS register is set when the breakpoint generates the debug exception A debug data break exception occurs when a data breakpoint indicates a match In this case the DEPC register and DBD bit in the Debug register points to the instruction that caused the DB_match equation to be true The instruction causing the debug data break exception does not update any registers due to the instruction and the following applies to the load or store transaction causing the debug exception e A store transaction is not allowed to complete the store to the memory system e A load transaction with no data value compare i e where the DB_no_value_compare is true for the match is not allowed to complete the load e A load transaction for a breakpoint with data value compare must occur from the memory system since the value is required in order to evaluate the breakpoint The result of this is that the load or store instruction causing the debug data break exception appears as not executed with the exception that a load from the memory system do occur for a breakpoint with data value compare but the result of this load is discarded since the register file is not updated by the load
272. try Operation i lt Index if i gt TLBEntries 1 then UNDEFINED endif PageMaskyas y lt TLB il masz EntryHi lt TER il vpn2 Ov Tl TEB i lasrpD EntryLol lt lt 0 I TLB ilppya TLB ile LB ilpi EntryLo0 lt 0 TLB 1 ppno LB ileo LB i po Exceptions Coprocessor Unusable TLB i v TLB ilyo TLB il g TLB ilg MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved TLBR 197 Chapter 11 MIPS32 4K Processor Core Instructions 198 Write Indexed TLB Entry TLBWI 31 26 25 24 0 COPO CO 0 TLBWI 010000 1 000 0000 0000 0000 0000 000010 6 1 19 6 Format TLBWI MIPS32 Purpose To write a TLB entry indexed by the Index register Description The TLB entry pointed to by the Index register is written from the contents of the EntryHi EntryLo0 EntryLo1 and PageMask registers The information written to the TLB entry may be different from that in the EntryHi EntryLo0 and EntryLo registers in that e The single G bit in the TLB entry is set from the logical AND of the G bits in the EntryLo0 and EntryLol registers Restrictions The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB entries in the processor Copyright 2000 2002 MIPS Technologies Inc All rights reserved MIPS32 4K Processor Core F
273. turing companies ASIC developers and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high performance RISC processor The cores are is fully synthesizable to allow maximum flexibility they are it is highly portable across processes and can be easily integrated into full system on silicon designs allowing developers to focus their attention on end user products The cores are is ideally positioned to support new products for emerging segments of the digital consumer network systems and information management markets enabling new tailored solutions for embedded applications The 4K family has three members the 4Kc 4Km and 4Kp cores The cores incorporates aspects of both the MIPS Technologies R3000 and R4000 processors It The three devices differ mainly in the type of multiply divide unit MDU and the memory management unit MMU The 4Kc core contains a fully associative translation lookaside buffer TLB based MMU and a pipelined MDU e The 4Km core contains a fixed mapping FM mechanism in the MMU that is smaller and simpler than the TLB based implementation used in the 4Kc core and a pipelined MDU as in the 4Kc core is used e The 4Kp core contains a fixed mapping FM mechanism in the MMU like the 4Km core and a smaller non pipelined iterative MDU Optional instruction and data caches are fully programmable from 0 16 Kbytes in size In addition each cache can be organ
274. uction in the I stage 2nd instruction after the branch The pipeline begins the fetch of either the branch path or the fall through path in the cycle following the delay slot After the branch decision is made the processor continues with the fetch of either the branch path for a taken branch or the fall through path for the non taken branch The branch delay means that the instruction immediately following a branch is always executed regardless of the branch direction If no useful instruction can be placed after the branch then the compiler or assembler must insert a NOP instruction in the delay slot Figure 2 18 illustrates the branch delay One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle Jump or Branch E M A W Delay Slot Instruction t E M A W Jump Target Instruction gt l E M A One Clock Branch Delay Figure 2 18 IU Pipeline Branch Delay 2 8 Data Bypassing Most MIPS32 instructions use one or two register values as source operands for the execution These operands are fetched from the register file in the first part of E stage The ALU straddles the E to M boundary and can present the result early in M stage however the result is not written in the register file until W stage This leaves following instructions unable to use the result for 3 cycles To overcome this problem Data bypassing is used Between the register file and the ALU a data b
275. um value on Reset Wired 4Kc core only set to 0 on Reset Status pry set to 1 on Reset SoftReset Status ys cleared to 0 on Reset SoftReset Status sp cleared to 0 on Reset set to 1 on SoftReset Status yyy cleared to 0 on Reset SoftReset Status pry set to 1 on Reset SoftReset StatuSpp Cleared to 0 on Reset WatchLo g w Cleared to 0 on Reset Config fields related to static inputs set to input value by Reset Config go set to 010 uncached on Reset Config xy set to 010 uncached on Reset 4Km and 4Kp cores only Config x3 set to 010 uncached on Reset 4Km and 4Kp cores only DebugDM cleared to 0 on Reset SoftReset unless EJTAGBOOT option is used to boot into DebugMode see Chapter 9 EJTAG Debug Support for details Debug snm Cleared to 0 on Reset SoftReset Debug jgysep Cleared to 0 on Reset SoftReset Debug pgusgp Cleared to 0 on Reset SoftReset MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 111 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 6 Hardware and Software Initialization e Debug jy cleared to 0 on Reset SoftReset Debug ss cleared to 0 on Reset SoftReset 6 1 2 TLB Initialization 4Kc core only Each 4Kc TLB entry has a hidden state bit which is set by Reset SoftReset and is cleared when the TLB entry is written This bit disables matches and prevents TLB Shutdown conditions fro
276. untDM IBusEP MCheckP CacheEP DBusEP IEXI DDBSImpr 18 DDBLImpr 17 Ver 15 14 10 9 8 76 5 4 DExcCode NoSST SSt R DINT DIB DDBS DDBLI DBp DSS 3 2 1 0 Table 5 26 Debug Register Field Descriptions Description Read Write Reset State Gg Indicates whether the last debug exception or exception in debug mode occurred in a branch delay slot 0 Not in delay slot 1 In delay slot Indicates that the processor is operating in debug mode 0 Processor is operating in non debug mode 1 Processor is operating in debug mode Undefined 31 DM 30 NoDCR 29 LSNM 28 Indicates whether the dseg memory segment is present 0 dseg is present 1 No dseg present Controls access of load store between dseg and main memory 0 Load stores in dseg address range goes to dseg 1 Load stores in dseg address range goes to main memory 102 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Registers Table 5 26 Debug Register Field Descriptions Continued Description Reset State Indicates that the processor was in any kind of low power mode when a debug exception occurred 0 Processor not in low power mode when debug Undefined exception occurred 1 Processor in low power mode when debug exception occurred Indicates that the internal system
277. uts determine whether an the Instruction register scan or data register scan is performed The TAP consists of a small controller driven by the TCK input which responds to the TMS input as shown in the state diagram in Figure 9 5 The TAP uses both clock edges of TCK TMS and TDI are sampled on the rising edge of TCK while TDO changes on the falling edge of TCK At power up the TAP is forced into the Test Logic Reset either by low value on TRST_N The TAP instruction register is thereby reset to IDCODE No other parts of the EJTAG hardware are reset through the Test Logic Reset state When test access is required a protocol is applied via the TMS and TCK inputs causing the TAP to exit the Test Logic Reset state and move through the appropriate states From the Run Test Idle state an Instruction register scan or a data register scan can be issued to transition the TAP through the appropriate states shown in Figure 9 5 The states of the data and instruction register scan blocks are mirror images of each other adding symmetry to the protocol sequences The first action that occurs when either block is entered is a capture operation For the data registers the Capture DR state is used to capture or parallel load the data into the selected serial data path In the Instruction register the Capture IR state is used to capture status information into the Instruction register From the Capture states the TAP transitions to either the Shift or Exit st
278. vides for the 4Km and 4Kp cores but we will still make the distinction Except for kseg0 unmapped segments are always uncached The cacheability of kseg0 is set in the KO field of the CPO register Config see Section 5 2 15 Config Register CPO Register 16 Select 0 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation 3 2 1 2 Mapped Segments A mapped segment does use the TLB 4Kc core or the FM 4Km and 4Kp cores to translate from virtual to physical address For the 4Kc core the translation of mapped segments is handled on a per page basis Included in this translation is information defining whether the page is cacheable or not and the protection attributes that apply to the page For the 4Km and 4Kp cores the mapped segments have a fixed translation from virtual to physical address The cacheability of the segment is defined in the CPO register Config fields K23 and KU see Section 5 2 15 Config Register CPO Register 16 Select 0 Write protection of segments is not possible during FM translation 3 2 2 User Mode In user mode a single 2 GByte Oo bytes uniform virtual address space called the user segment useg is available Figure 3 4 shows the location of user mode virtual address space 32 bit OxFFFF_FFFF Address Error 0x8000_0000 Ox7FFF_FFFF 2GB Mapped useg 0x0000_0000 Figure
279. ween TCK and CPU clock domains However it is ensured that change of the ProbEn prior to setting the EjtagBrk bit will have effect for the debug handler executed due to the debug exception The reset value of the bit depends on whether the EJTAGBOOT indication is given or not No EJTAGBOOT indication given 0 EJTAGBOOT indication given 1 Probe Trap This bit controls the location of the debug exception vector 0 In normal memory 0xBFC0 0480 1 In EJTAG memory at 0xFF20 0200 in dmseg Valid setting of the ProbTrap bit depends on the setting of the ProbEn bit see comment under ProbEn bit The ProbTrap should not be set to 1 for debug exception Oorl vector in EJTAG memory unless the ProbEn bit is also ProbTrap 14 set to 1 to indicate that the EJTAG memory may be R W from accessed EJTAGBOOT The read value indicates the effective value to the CPU due to synchronization issues between TCK and CPU clock domains However it is ensured that change of the ProbTrap prior to setting the EjtagBrk bit will have effect for the EjtagBrk The reset value of the bit depends on whether the EJTAGBOOT indication is given or not No EJTAGBOOT indication given 0 EJTAGBOOT indication given 1 Res 13 reserved R 0 156 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 4 EJTAG TAP Registers Table 9 23 EJTAG Control Register
280. with the M stage of the IU pipeline the Ampy stage occurs in parallel with the A stage and the Wyypy stage occurs in parallel with the W stage However in case the instruction in the MDU pipeline needs multiple passes through the same MDU stage this parallel behavior will be skewed by one or more clocks This is not a problem because results in the MDU pipeline are written to HI and LO registers while the integer pipeline results are written to the register file 2 Add 3 32x32 multiply Mult 4 Sub cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 Y j b j l i i Mult I E Mmpu Ampu Wmou l f oF oo Add I E M A w i l l l Mult i I E Mmpu Mmpu Ampu WmDpU Sub I E M A W i Figure 2 8 MDU Pipeline Behavior during Multiply Operations 4Kc and 4Km processors The following is a cycle by cycle analysis of Figure 2 8 1 The first 32x16 multiply operation Mult enters the I stage and is fetched from the instruction cache 2 An Add operation enters the I stage The Mult operation enters the E stage The integer and MDU pipelines share the I and E pipeline stages At the end of the E stage in cycle 2 the multiply operation Mult is passed to the MDU pipeline 3 In cycle 3 a 32x32 multiply operation Mult enters the I stage and is fetched from the instruction cache Since the Add operation has not yet reached the M stage by cycl
281. x0000_0000 Mapped 2048MB kuseg Figure 3 5 Kernel Mode Virtual Address Space Table 3 2 Kernel Mode Segments Status Register Is One of These Values Address Bit Segment Segment Values UM Name Address Range Size 0x0000_0000 A 31 0 through 2 GBytes A 31 29 1005 Ox7FFF_FFFF 27 bytes UM 0 or A 31 29 101 A 31 29 110 A 31 29 111 0x8000_0000 through Ox9FFF_FFFF 512 MBytes 27 bytes EXL 1 or ERL 1 and DM 0 kseg3 0xA000_0000 through OxBFFF_FFFF 0xC000_0000 through OxDFFF_FFFF 0xE000_0000 through OxFFFF_FFFF 512 MBytes 27 bytes 512 MBytes 27 bytes 512 MBytes 27 bytes Copyright 2000 2002 MIPS Technologies Inc All rights reserved MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 37 Chapter 3 Memory Management 38 3 2 3 1 Kernel Mode User Space kuseg In Kernel mode when the most significant bit of the virtual address A31 is cleared the 32 bit kuseg virtual address space is selected and covers the full 7 bytes 2 GByte of the current user address space mapped to addresses 0x0000_0000 0x7FFF_FFFF For the 4Kc core the virtual address is extended with the contents of the 8 bit ASID field to form a unique virtual address When ERL 1 in the Status register the user address region becomes a 23 _byte unmapped and uncached address space While i
282. x1108 n 0x100 IBMn Instruction Breakpoint Address Mask n 0x1110 n 0x100 IBASIDn Instruction Breakpoint ASID n 4Kc core 0x1118 n 0x100 IBCn Instruction Breakpoint Control n Note n is breakpoint number in range 0 to 3 or 0 to 1 depending on the implemented hardware An example of some of the registers BAO is at offset 0x1100 and JBC2 is at offset 0x1318 130 MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 8 1 Instruction Breakpoint Status IBS Register Compliance Level Implemented only if any instruction breakpoints The Instruction Breakpoint Status BS register holds implementation and status information about the instruction breakpoints The ASID applies to all the instruction breakpoints for the 4K core IBS Register Format 31 30 29 28 27 24 23 Res ASID Res sup Table 9 7 IBS Register Field Descriptions Fields Description Read Write Reset State Must be written as zero returns zero on read This bit indicates that ASID compare is supported in ASIDsup instruction breakpoints 4Kc core 4Kc cores R 4Kc core 1 4Km 4Kp cores 0 4Km 4Kp cores 0 Must be written as zero returns zero on read 4Km 4Kp cores 29 28 Must be written as zero returns zero on read E 7 e 27 24 Number of instruction breakpoints implemented ME ae a Must be written
283. ypass multiplexer is placed on both operands see Figure 2 19 This enables the 4K core to forward data from preceding instructions which have the target register of the first instruction as one of the source operands An M to E bypass and an A to E bypass feed the bypass multiplexers A W to E bypass is not needed as the register file is capable of making an internal bypass of Rd write data directly to the Rs and Rt read ports MIPS32 4K Processor Core Family Software User s Manual Revision 01 18 23 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline Istage E stage i M stage A stage W stage A to E bypass M to E bypass Instruction Bypass Load data HI LO Data multiplexers or CPO data Figure 2 19 IU Pipeline Data Bypass Figure 2 20 shows the Data bypass for an Add instruction followed by a Sub and another Add instruction The Sub instruction uses the output from the Add instruction as one of the operands and thus the M to E bypass is used The following Add uses the result from both the first Add instruction and the Sub instruction Since the Add data is now in A stage the A to E bypass is used and the M to E bypass is used to bypass the Sub data to the Add instruction One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle soo et R3 R2 R1 SUB gt R4 R3 R7 M to E bypa ADD gt E M A R5 R3 R4 Figu

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