V977 User Manual
Contents
1. E tenen 17 4 10 INTERRUPT MASKE ROUTER EEA RSet ae 17 4 11 OUTPUT CLEAR REGISTER eerte tentent N N ttt ttt ttt ttt 17 Filename Number of pages Page 21 3 NPO 00118 01 V977X MUTX 01 V977_REV1 DOC CALE Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 4 12 SINGLEHIT READ CLEAR REGISTER ivesi nrerin oN EE EERE O EESE EE E E E E 18 4 13 MULTIHIT READ CLEAR REGISTER siosioina iier ene EERTE EERE EEEE 18 4 14 TEST CON RO R G OTER tere RII RRES 18 4 15 INTERRUPET EEVEBL 1 4 Ab e edet E EA E EET 19 4 16 INTERR PT VEGTOR ere tert er repete gente pee rie era er aes 19 4 17 SERIAL NUMBER ri erede rie CEU ee i irm pe c e eb reb e e ERES 19 4 18 FIRMWARE REVISION Re e ER eth RR eo e Pee ERR eine e pr E PEN DERE teas 19 4 19 CONTROL REGISTER inr E RR RR RS REESE 19 4 20 DUMMY1O dissidia RE RET RIS RR RC REB ED GREEN ERU ER RORIS 20 4 21 SOETWARE RESET voto TR GRE ERU OTRA ean C ERU FEE QNT a ORE REG GER ER EUH ERES 20 eto n Ere m EM REI VU VE EM eei 21 LIST OF FIGURES FIG 2 V977 FRONT PANEE 8 FIG 351 MOD V977 CHANNEL STRUCTURE eR ope e eei 9 FIG 3 2 1 O2. 7 2 5 TECHNICAL SPECIFICATION TABLES net ERREICHEN RE DOM DERE 7 2 6 PRONE PANEL ere RR REUNIR EROR END RS 8 3 OPERATING MODES 66 reo 9 3 1 BUNCTIONAL DESCRIPTION e a dede rae o Ee ead te aet pte e dee eds 9 3 1 1 register mode ion Vaan 10 3 1 2 Multihit pattern unit mode eee deett ete e ca idee eene eerie ge epe 10 3 1 3 HAITI MH 11 3 2 OR LOGIC 12 33 INTERR PTER CAPABILITY b en aO ERREUR ERAS 12 4 MIMEVINTEREA lO D 14 41 ADDRESSING CAPABILITY rote eer Ecol varese ep P ege epa euet ve ba eee ev 14 4 2 DATA TRANSFER CAPABILITY EL ee teo Pa ute peor Ra ERRAT 14 4 3 INPUTSETREGISTER oT ORAE ER SENT sudden c OBTENER 15 44 INPUT MASK REGISTER RIEN EAT GENS ANE EERIE 16 4 5 INPUT READ REGISTER nn o ne e E RR oth Se ee eti ete e ovde Ne ee 16 4 6 SINGLE HIT READ REGISTER teh ERR e Oe Eee EVER E TR 16 4 7 MUETI HIT READ REGISTER e rod e e on be veo e eet atte Ed 16 4 8 OUTPUT SET REGISTER erster a WR ER WR E E b vt e 17 4 9 OUTPUT MASK REGISTER 020
3. 4 8 TS 3T T TS OUTPUT MASK This register default content is 0x0000 all channels outputs are enabled 4 10 Interrupt mask Base address 000 read write Each register s bit corresponds to one channel and it is masked as the corresponding bit is set to 1 The interrupt request whose level is set by the INTERRUPT LEVEL register value is produced when the OR of the channels non mascherati has a TRUE status papa psp o s SD D T Di D INTERRUPT MASK This register default content is 0x0000 all channels are unmasked 4 11 Output clear register Base address 960010 read write A dummy write access to this register clears all the channels FLIP FLOP NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 17 CAE Fal Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 4 12 Singlehit read clear register Base address 0016 read only Each register s bit corresponds to one channel This is a different way to access the SINGLE HIT READ REGISTER a read access to this register clears the first FLIP FLOP see 3 1 of all channels BE RPE PPE PE EE EPLyy SINGLEHIT READ CLEAR 4 13 Multihit read clear register Base address 0018 read only Each register s bit corresponds to one channel This is a different way to access the MULTI HIT READ REGISTER a read access
4. TEST CHANNEL LOGIC IRQ7 INTERRUPT LEVEL VME REGISTER Fig 3 5 Interrupter scheme NPO Filename Number of pages 00118 01 V977X MUTX 01 V977_REV1 DOC 21 Page 13 CAE Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 1 4 VME Interface 4 1 Addressing capability 4 2 NPO The module works in A32 A24 mode This means that the module address must be specified in a field of 32 or 24 bits The Address Modifiers code recognized by the module are AM 39 A24 non privileged data access AM 3D A24 supervisory data access AM 09 A32 non privileged data access AM 0D A32 supervisory data access The module s Base Address is fixed by 4 internal rotary switches housed on two piggy back boards plugged into the main printed circuit board see Fig 4 1 The Base Address can be selected in the range 0x000000 lt gt OxFF0000 A24 mode 0x00000000 OxFFFF0000 A32 mode The address map of the page is shown in table 4 1 Data transfer capability The V977 registers are accessible in D16 mode Table 4 1 Address Map for the Mod V977 ADDRESS REGISTER CONTENT ADDR DATA Base 0000 INPUT SET A24 A32 read write Base 0002 INPUT MASK A24 A32 read write Base 0004 INPUT READ A24 A32 read only Base 0006 SINGLEHIT READ A24 A32 read only Base 0008 MULTIHIT READ A24 A32 read only Base 000A OUTPUT SET A24 A32 read write Base 000
5. 8 2004 TEST INPUT PUSHBUTTON 1 TEST CHANNEL CLEAR BIT TEST CHANNEL MASK BIT TEST CHANNEL READ BIT FROM TEST CHANNEL CHANNELS INTERRUPT LOGIC MASK BIT OR TEST CHANNEL OUTPUT OR MASK BIT CONTROL REGISTER OR MASK BIT TEST CONTROL REGISTER TO IRQ LOGIC Fig 3 4 Test channel 3 2 OR logic As shown in Fig 3 1 the channels OR and OR are available as front panel signals and can be eventually masked Also the TEST signal participates to the OR logic it can also be masked 3 3 Interrupter capability The Mod V977 house a VME INTERRUPTER The module responds to D16 Interrupt Acknowledge cycles providing a word whose 8 LSB are the STATUS ID The interrupt STATUS ID is 8bit wide and it is contained in the 8 LSB of the Interrupt Vector Register see 4 16 The module s interrupter produces its request on one of the 7 IRQ lines The interrupt level is programmable via VME see 4 15 An Interrupt is generated when the OR of channels output is True The channels outputs sent to the interrupt logic can be masked via the INTERRUPT MASK REGISTER The TEST channel can participate to the IRQ logic as well see 4 10 NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 12 CAE R Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 1 IRQ 1 FROM CHANNELS LOGIC FROM
6. C OUTPUT MASK A24 A32 read write Base 000E INTERRUPT MASK A24 A32 read write Base 0010 CLEAR OUTPUT A24 A32 write only Base 0012 RESERVED 5 Base 0014 RESERVED Base 0016 SINGLEHIT READ CLEAR A24 A32 read only Base 0018 MULTIHIT READ CLEAR A24 A32 read only Base 001A TEST CONTROL REGISTER A24 A32 read write Base 001C RESERVED 5 001 RESERVED Base 0020 INTERRUPT LEVEL A24 A32 read write Base 0022 INTERRUPT VECTOR A24 A32 read write Base 0024 SERIAL NUMBER A24 A32 read only Base 0026 FIRMWARE REVISION A24 A32 read only Base 0028 CONTROL REGISTER A24 A32 read write Base 002A DUMMY REGISTER A24 A32 read write Base 002C RESERVED Base 002 SOFTWARE RESET A24 A32 write only Filename Number of pages Page 14 00118 01 V977X MUTX 01 V977_REV1 DOC 21 CAE R Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 1 Rotary switches for VME address selection Base address bit lt 19 16 gt Base address bit lt 23 20 gt Base address bit lt 27 24 gt Jumper for output type Base address bit lt 31 28 gt selection SW2 Fig 4 1 Mod V977 Base address setting and output selection 4 3 Input set register Base address 0000 read write Each register s bit corresponds to one channel If one bit is set to 1 the relevant channel FLIP FLOP see 3 1 is set regardless the correspondi
7. REGISTER MODE eR RERO E RR RENE RR E aaa ce eee 10 FIG 3 3 MUETIHIT PATTERN UNIT MODE cie I Ere ER ERE TAREA E FH Da m RO He rare pe ba eres 11 FIG 3 4 TEST CHANNBL eii nic pei ner recae a d RR OH OE RE ERE e E eti ee E Ee Ys 12 FIG 352 INTERRUPTER SCHEME EE ONT E eU E EE AREE UR eet Dee repete rei des 13 FIG 4 1 MOD V977 BASE ADDRESS SETTING AND OUTPUT SELECTION cerent nennen ttes 15 LIST OF TABLES TABLE 2 T REPRE erre Rare torpe hen mee eoe ei rq e rene TABLE 20 TECHNICAL FEATURES eee eee revertit eret ier e ieu repe tei tied 7 TABLE 4 1 ADDRESS MAP FOR THE MOD V977 esses eene 14 Filename Number of pages Page V977 REVI DOC 21 4 NPO 00118 01 V977X MUTX 01 CAE Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 1 Overview 1 1 Module description The Mod V977 is a 1 unit wide VME module that can work either as 16 channel general purpose I O Register or as Multihit Pattern Unit the operating mode is selected via VME and is signalled via front panel LED The module has 16 channels each channel is provided with one input and one output connector Input signals can be indifferently NIM or TTL an on board switch allows to select between NIM and TTL signals for the outputs 2 LEDs signal the I O
8. S connector 16 CHANNELS INPUTS NIMor TTL _ LEMOO0 150 0 impedance 16 CHANNELS OUTPUTS NIM or TTL selectable LEMO0O 1 TESTOUTPUT 7 NIMorTTL selectable CLEAR INPUT NMorTIL 1 J LEMO 00 1500 impedance 2 and NOT OR OUTPUT or TTL selectable LEMO 00 16 16 1 1 2 LEDS Depends on the module s programming status see 3 1 Depends on the module s programming status see 3 1 each time a VME access is performed pushbutton 1 PATTERN Indicates the module s programming status Yellow lights up as the module is programmed in PATTERN mode see 3 1 1 NIM TTL Indicates the selected outputs level Red Green RED NIM GREEN TTL All LEDs also lights up for a while at power ON to indicate that the board is configuring PUSHBUTTON No 1 to send the TEST input pulse NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 6 CAE Fal Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 2 3 Internal components SWITCHES see Fig 4 1 No 4 rotary switches for the module VME Base address selection No 1 jumper for the output signal type selection up NIM down TTL 2 4 Power requirements Table 2 1 Power requirements 2 5 Technical specification tables Table 2 2 Technical features Pac
9. T echnical Information M anual Revision n 1 27 August 2004 MOD V977 16 CHANNEL Register Status MANUAL REV 1 NPO 00118 01 V 977X M UTX 01 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice CALE Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 TABLE OF CONTENTS OV EER VDE WY eee 5 1 1 MODUEE DESGRIPTION OR eae I 5 2 SPECTBICA 6 2 1 PACKAGING ano ORDRE UIS ETUR OTRO IRR IER 6 2 2 EXTERNAL COMPONENTS 4 on HU HH REGE RES PUE HUE DERE ee RE A eG HA ERE 6 23 INTERNAL COMPONENTS NURSES DRESS URN CIE ERRANT PERI ARN XE ANNUS AES ERA TR nex 7 24 POWER REQUIREMENTS s
10. annel is composed by a couple of FLIP FLOPs which perform the memory functions The two cascaded FLIP FLOPs as shown in Fig 3 1 allow to detect the following events none one or two input hits The FLIP FLOPs status of all channels can be read via VME in the SINGLEHIT READ REGISTER and MULTIHIT READ REGISTER which are related respectively to the first and to the second cascaded FLIP FLOP The content of such register can also be read by accessing the SINGLEHIT READ CLEAR REGISTER and MULTIHIT READ CLEAR REGISTER in this case the FLIP FLOPs are cleared after readout The FLIP FLOPs of all channels can also be cleared both via VME by accessing the CLEAR OUTPUT REGISTER and via the front panel CLEAR signal The FLIP FLOPs are set either via an input hit or via VME write access INPUT SET REGISTER By accessing the CLEAR OUTPUT REGISTER the INPUT SET REGISTER is cleared The capabilty of receiving input hits can be masked via VME through the INPUT MASK REGISTER individually for each channel or via the input GATE signal common to all channels which can be masked in its turn The status of the inputs can also be read directly via VME in the INPUT READ REGISTER The status of the channel LEDs and of the outputs depend on the module s programming NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 9 CAE Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Registe
11. anual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 CH in INPUT GATE INPUT OUTPUT MASK OUTPUTSET PATTERN 1 VME REGISTER VME REGISTER EN EVA E gt MULTIHIT READ VME REGISTER INPUT MASK VMEREGISTER PES D Q 5 P SINGLE HIT READ VME REGISTER lt to OR and IRQ LOGIC NI INPUT READ INPUT SET VME REGISTER VME REGISTER AR HA Je CONTROL CLEAR CLEAR OUTPUT REGISTER INPUT VME REGISTER GATE MASK BIT 7 Fig 3 3 Multihit pattern unit mode In this operating mode the output of one channel is active when a double hit from front panel or VME generated is present The output can also be set by a write access to the OUTPUT SET REGISTER The outputs can also be masked individually for each channel through the OUTPUT MASK REGISTER In this operating mode the two channel LEDs identify the channel status in the following way Left LED single hit received Right LED double hit received and output signal active 3 Test channel The module is provided with an extra channel TEST CHANNEL which differs from the others since the input pulse is sent by a pushbutton The TEST channel is completely handled by the Test control register see 4 20 Filename Number of pages Page 21 11 NPO 00118 01 V977X MUTX 01 V977_REV1 DOC CAE R Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 0
12. ddress 002A read write This register allows to perform 16 bit test accesses for test purposes Default setting is 0x5555 4 21 Software reset Base address 002 write only A dummy write access to this register allows to generate a single shot RESET of the module which restores the default conditions NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 20 CAE Revision date Revision 1 Document type Title User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 References 1 VMEbus Specification Manual Revision C 1 October 1985 2 VMEBus for Physics Application Recommendations amp Guidelines Vita23 199x draft 1 0 22 May 1997 NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 21
13. e This register contains the STATUS ID that the V977 places on the VME data bus during the interrupt acknowledge cycle Bits 8 to 15 are meaningless 8 7 6 s 4 3 2 i Jo 7 STATUSID Default setting is OxDD 4 17 Serial number Base address 0024 read only This word reproduces the module s serial number papa popu PPP D D T Di D SERIAL NUMBER 4 18 Firmware revision Base address 960026 read only This word reproduces the module s firmware revision in the Rev X Y format TAS SESS ESTEE S p uui 4 19 Control register Base address 960028 read write This register controls the functions common to all channels NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 19 CAE Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 pop Ts Ts 3 5 2 3 v PATTERN BIT read write 0 the module works as I O REGISTER default setting 1 the module works as a MULTIHIT PATTERN UNIT GATE MASK read write 1 the GATE sent via FRONT PANEL signal is masked default setting 0 the GATE sent via FRONT PANEL signal is enabled incoming hits are accepted only as the GATE is active OR MASK read write 2 0 the OR and OR FRONT PANEL outputs are enabled default setting 1 the OR and OR FRONT PANEL outputs are masked 4 20 Dummy16 Base a
14. h bit is set to one as the corresponding channel as received one hit from front panel or VME generated papa psp o s s D Te Di De SINGLEHIT READ 4 7 Multi hit read register Base address 960008 read only Each register s bit corresponds to one channel Each bit reproduces the relevant FLIP FLOPs Qs regardless the OUTPUT MASK register s status This register is used only if the module operates in multihit pattern unit mode and signals if one channel has received a double input hit from front panel or VME generated spe TS ETSTSTSS ES NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 16 CAE Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 4 8 Output set register Base address 000 read write Each register s bit corresponds to one channel If one bit is set to 1 the corresponding channel output is active regardless the corresponding input connector s and FLIP FLOPs Qs status papa poppe s T T Di D OUTPUT SET This register default content is 0x0000 4 9 Output mask register Base address 96000C read write Each register s bit corresponds to one channel If one bit is set to 1 the relevant output is masked and no output signal is produced regardless the FLIP FLOPs status The output signal can be produced anyway via the relevant bit in the OUTPUT SET register see
15. kaging 1U wide VME unit Input channels 16 NIM TTL levels 50 Q impedance 16 NIM TTL levels selectable Output channels to be terminated on 50 Q NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 7 CAE Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 1 2 6 Front Panel OUTPUT CONNECTORS INPUT CONNECTORS STATUS A REGISTER PATTERN UNIT 9 Fig 2 1 977 Front Panel NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 8 CAE Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 3 Operating modes 3 1 Functional description The Mod V977 is a 16 channel general purpose I O Register or as Multihit Pattern Unit The following figure shows the simplified scheme of a single channel CONTROL REGISTER PATTERN BIT 3 Z 5 CH n INPUT MASK UT 4 L VME REGISTER vA SINGLE HIT READ gt CH fin INPUT E lt 7 VME REGISTER INPUT READ INPUT SET VME REGISTER VME REGISTER INTERRUPT MASK OR AR VME REGISTER ourPuT GATE E 7 INPUT 6 OR OUTPUT UA lt CLEAR CONTROL CONTROL input 6 T UT REGISTER REGISTER OR MASK BIT GATE MASK BIT TO IRQ FROM TEST LOGIC CHANNEL LOGIC Fig 3 1 Mod V977 channel structure The core of each ch
16. ng input connector s status BPP bP Ts PTSTS AT T2 TS INPUT SET In Multihit pattern unit mode this register allows to obtain a double hit on a channel via VME by setting and then resetting two times the corresponding bit in this register This register default content is 0x0000 NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 15 CAE Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 4 4 Input mask register Base address 0002 read write Each register s bit corresponds to one channel If one bit is set to 1 the related input signal is masked i e if a channel is masked the relevant FLIP FLOP does not receive the front panel signal The FLIP FLOPs Qs can be activated anyway via the relevant bit in the INPUT SET register see 4 3 papa popu PPP PEELE T Di D INPUT MASK This register default content is 0x0000 all channels inputs are enabled 4 5 Input read register Base address 960004 read only Each registers bit corresponds to one channel it reproduces the relevant input connector s logic level regardless the INPUT MASK register s status TS ST T TS 4 6 Single hit read register Base address 960006 read only Each register s bit corresponds to one channel it reproduces the relevant FLIP FLOPs Qs regardless the OUTPUT MASK register s status Eac
17. r Status A 27 08 2004 3 1 1 I O register mode The module operates as I O register if the PATTERN bit of the CONTROL REGISTER is set to 0 default setting In this case the simplified channel scheme is shown in Fig 3 2 PATTERN 0 OUTPUT MASK OUTPUT SET X VME REGISTER VMEREGISTER N INPUT MASK 4 VME REGISTER i V 1 OUTPUT CH in M 5 i input P SINGLE HIT READ VME REGISTER INPUT READ INPUT SET VME REGISTER VME REGISTER AR SSS to OR and IRQ GATE INPUT ae 96 WY CONTROL CLEAR CLEAR OUTPUT REGISTER INPUT VME REGISTER GATE MASK BIT N IVA Fig 3 2 I O register mode In this operating mode the output of one channel is active when a single hit from front panel or VME generated is received The output can also be set by a write access to the OUTPUT SET REGISTER The outputs can also be masked individually for each channel through the OUTPUT MASK REGISTER In this operating mode the two channel LEDs identify the channel status in the following way Left LED input signal active Right LED output signal active 3 1 2 Multihit pattern unit mode The module operates as multihit pattern unit if the PATTERN bit of the CONTROL REGISTER is set to 1 In this case the simplified channel scheme is shown in Fig 3 3 NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 10 CAE Document type Title Revision date Revision User s M
18. status of each channel The module features an additional channel TEST CHANNEL which allows to send a test pulse via a front panel pushbutton The TEST output signal can be either NIM or TTL selected with the same on board switch of the channels output Input signals can be individually masked via VME or globally via a front panel GATE input The channel status can be cleared either via VME or via the front panel common CLEAR input GATE and CLEAR signals can be indifferently NIM or TTL The channels global OR and OR outputs are available as front panel signals and can be eventually masked OR and OR can be either NIM or TTL selected with the same on board switch of the channels output The module houses also a fully programmable VME RORA INTERRUPTER that generates a VME interrupt request when the OR of a selected set of output channels has a TRUE status The module uses the VME P1 and P2 connectors then it fits into both standard and V430 VMEbus crates All the models have a special circuitry that allows the board to be removed from and inserted in a powered crate without switching the crate off Live Insertion NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 5 CAE R Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 2 Specifications 2 1 Packaging 1 unit wide VME unit Height 6U 2 2 External components CONNECTOR
19. to this register clears the second FLIP FLOP see 3 1 of all channels GE BP EPP EP EEEEPLL MULTIHIT READ CLEAR 4 14 Test control register Base address 001A read write This register handles all the TEST INPUT channel operations SEELE EEEE CLEAR BIT write only setting this bit to 1 the TEST CHANNEL FLIP FLOP is cleared MASK BIT read write If this bit is set to 1 the TEST output is masked it does not produce an output signal default setting 0 OR MASK BIT read write If this bit is set to 1 the Q signal of the TEST channel is not sent to the OR logic default setting 0 INTERRUPT MASK BIT read write If this bit is set to 1 the Q signal of the TEST channel is not sent to the INTERRUPT logic default setting 0 READ BIT read only It reproduces the pushbutton status regardless the MASK bit status NPO Filename Number of pages Page 00118 01 V977X MUTX 01 V977 REVI DOC 21 18 CAE Fal Document type Title Revision date Revision User s Manual MUT Mod V977 16 Channel I O Register Status A 27 08 2004 4 15 Interrupt level Base address 0020 read write The 3 LSB of this register contain the value of the interrupt level Bits 3 to 15 are meaningless ur fio of 6 514 3 2 i Jo Default setting is 0 0 in this case interrupt generation is disabled 4 16 Interrupt vector Base address 0022 read writ
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