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STEREO-CIT-005.A P24 MISC Processor Manual 1 P24 MISC

1. h test memeory address 68 LIT 700 LIT 700 LIT prove gt R R gt R S4D LIT gt R R R gt AND Nor prove next can run 1 LIT 6A LIT FOR 1 LIT UM DROP NEXT LF CRR se COED VC diagnose CR SLIT P24 v 66 LIT lt CHAR 2E LIT HOLD gt TYPE CR QUIT 8 15 Control Structure Words CRR Structures CRR m R IF A HERE 80000 LIT IMMEDIATE FOR a 71E79E LIT HERE IMMEDIATE BEGIN a HERE IMMEDIATE AHEAD A HERE 0 LIT IMMEDIATE P24 MISC Processor Manual 54 STEREO CIT 005 A CRR AGAIN a IMMEDIATE THEN A HERE SWAP IMMEDIATE NEXT a COMPILE doNEXT IMMEDIATE UNTIL a 80000 LIT IMMEDIATE CRR REPEAT A a AGAIN THEN IMMEDIATE AFT a a A DROP AHEAD BEGIN SWAP IMMEDIATE ELSE A A AHEAD SWAP THEN IMMEDIATE WHILE a A a IF SWAP IMMEDIATE 8 16 Redefine Macro Words CRR macro words CRR CODE EXIT pop drop ret CODE EXECUTE push ret CODE sta st ret CODE sta ld ret CRR CODE R gt pop sta pop lda push ret CODE R pop sta pop dup push lda push ret CODE gt R sta pop push lda ret CRR CODE SWAP push sta pop lda ret CODE OVER push dup sta pop lda ret CODE 2DROP dro
2. his P24 simulator is t nt Windows function and produces the It must b builds a P24 eForth system in the array RAM from the RAM memory and execute the instructions contained i LOCK has a 29 bit program word count filed ld sequences program word fetch a pointer to switch between FROM OR the base address of either FROM or FROM forces accessing registers in the FROM upper 29 bit field in the counter hat it can vector the KEY so that the simulator can identical output as the t was proven that the the simulator can be used Now that i loaded after META24 F which The simulator reads program words n these program lary They are thus distinguished TH and ASM24 vocabularies and act like circular buffers or 8KW the size of RAM array and a 3 bit SLOT field and execution of up to array and TO array TO array array array and stacks are CONSTANT LIMIT stack depth FFF CONSTANT RANGE size of memory array RIABLE CLOCK slot is in the last 3 bits RIABLE REGISTER where registers RIABLE BREAK address of break point On the rising edge of clock copy TO array to FROM array REGISTER REGISTER FROM PAD REGISTER TO PAD 180 REGISTER P program counter T accumulator R top of return stack A address register I instruction latch I0 4 machine instruction storage RP return stack pointer SP data stack pointer 57
3. LDI Code OA Usage 001010 cceecc ccccce ceccce nnnnnn nnnnnn nnnnnn nnnnnn cococo 001010 Gcccec ceccce nnnnnn nnnnnn nnnnnn nnnnnn ecccce Gececc 001010 cecccc nnnnnn nnnnnn nnnnnn nnnnnn ceCa ccocco ceccec OOTOLO nnnnnn nnnnnn nnnnnn nnnnnn Stack Effects ewm Carry no change Function P24 MISC Processor Manual 13 STEREO CIT 005 A Fetch the contents of the next word and push that number onto the data stack Coding Example Push 1 2 3 4 on data stack LD Code Usage Stack Effects Carry Function This instruction also resets the carry flag Bit 24 The program counter PC is incremented passing the next word This instruction allows a program to enter numbers onto the data stack for later use in the T register Ldi ldi ldi ldi 1 2 3 4 0B 001011 cccccc cccccc 001011 Cccccce cccccc ececce cecoce o m3 no change ECCEEE Gooceo 001011 eodcec CECCCE ececce cccccc 001011 Fetch the contents of a memory location whose 24 bit address is in the A register and push that number onto the data stack register is not modified Coding Example STP Code Usage Stack Effects Carry Function P24 MISC Processor Manual OD 001101 cccccc cccccc 001101 ceccce ccccce ececcce ccccce Cam Ss no change This instruction also resets the carry flag Bit 24 The address in the A This fetch instruction is
4. L238 Functional Block Diagram of P24 This section applies to Dr Ting s VHDL definition and has not been updated to correspond to the ACTEL implementation which is somewhat different These data path diagrams should be read with the CPU24 VHD file The instruction decoding logic simply apply the proper control signals to the following register loading and multiplexer selecting signals CLT Master reset Clk Master clock 0 40 MHz t sel Select input to T register tload If set load t in into T register Spop If set pop the data stack spush If set push T on the data stack a_sel Select input to A register aload If set load a_in inot A register r_sel Select input to R register rload If set load r_in into R register rpop If set Pop the return stack rpush If set push R on the return stack p_sel Select input to P register pload If set load P_in into P register m_sel Select output to Address bus iload If set load instruction from data bus to I register reset Clear the machine instruction counter slot Output of machine instruction counter to select instruction The synchronous program execution unit clocks the slot signal which selects the proper 6 bit instructions in the I register to produce the above control signals At the rising clock edge the selected data are latched into the proper register and stacks All data signals must st
5. EIGHT displays one line of memory attribute for VHDL BLOCKRAM displays one block of memory attributes for VHDL BRAM dumps the entire memory blocks for VHDL ud 0 lt gt type Bs 0 gt type Cue ve gt type string a 8 10 mod swap attribute INIT b n W qq b of memory OF and c label is 22 emit eight 8 dup 8 0 DO 1 DUP RAM ud LOOP DROP blockram a 10 0 DO CR DUP string eight 22 emit 3B emit LOOP cr BRAM base hex 0 OF 0 do blockram loop drop base 3 Calling Other Building Blocks Now we compile the structured optimizing assembler for P24 CR include asm24 include ok24 Now we compile the kernel portion of the P24 eForth system 18 org CR include eforth kernel include kern24 i T DR E This set of words will be used to build high level control structures in the body of eForth system BEGIN AGAIN FOR NEXT FOR AFT THEN NEXT LIT let LDI to assemble a literal SLIT compiles a counted ASCII string packed thr bytes to a 24 bit program word again a jump foto xe push begin next a doNEXT jump next next aft m ecu csl forthDROP begin 0 jump begin forthSWAP LIT d ldi P24 MISC Processor Manual 30 STEREO CIT 005 A SEER c 4 22 forthWORD forthCOUNT forthDUP B compile count 0 DO forthCOUNT B compile characte
6. STEREO CIT 005 A comment meta24 f 07nov00cht change for P24 p24c 02dec00cht interpreter ok debugging compiler This meta compiler was originally written by Chuck Moore to build Forth systems for the MuP21 microprocessor It can be easily hanged and used to compile code for any CPU Q This file loads all the source code and construct an image of P24 which can be ported to VHDL for Xilinx XCV300 1000 FPGA It runs under Win32Forth a public domain Forth system authored by Andrew McKewan and Tom Zimmer It can be downloaded from the web at www forth org under the category of Compiler Windows Click on the download button and it will be downloaded to your computer and automatically installed Run Win32Forth from your desktop or from Start Program Win32Forth and you will see a window opened Open the WinView editor from the File menu Open the file META24 F through the directory tree Then click back the Win32Forth window and type fload meta24 Youu will see the list of all the words compiled into the P24 target image Type showram to show the image dumped out in hexidecimal Type bram to s the image dumped in a form acceptable by Xilinx VHDL Cut and paste this image into your VHDL code and synthesize the P24 system 4 2 Tools of Metacompiler create two vocabularies ASM24 will contain the assembler woprds and the words in the P24 target SIM24 will contain words which build a cyc
7. gt R 0 LIT OVER COUNT a 0b n OVER CHAR 24 LIT IF HEX SWAP 1 SWAP 1 THEN a 0 D n OVER CHAR 2D LIT gt R a 0 bn SWAP R SWAP RQ a 0 b n DUP IF 1 a0b n FOR DUP gt R BAS WHILE SWAP BAS NEXT DROP R b THEN DUP H THEN R gt n sign his is the set of evice O is an internal acked string on t nd then move th ELSE R gt R gt b DIGIT de RASTE IF NEGATE THEN SWAP 2DROP digit number 2DROP 0 LIT E E E m P sign index 2DROP R BASE words displaying characters to the output system word which unpacks a packed string compiled n line with program words It digs up the starting address of the he return stack unpacks the string to location a return address passing the packed string Then P24 MISC Processor Manual 47 STEREO CIT 005 A 1 er er nnm the execution can continue skipping the packed string in line is compiled before a packed string It unpacks the string and returns the address of the TEXT buffer where the unpack string is stored is also compiled before a packed string It unpacks the string and displays it on the output device RR Basic I O CRR SPACE BL EMIT CHARS n c SWAP 0 LIT MAX FOR AFT DUP EMIT THEN NEXT DROP
8. nstruction like CALL BZ or BNZ new BEGIN Hi 10 AND 0 WHILE nop REPEAT 0 Bi H Hw OR RU E JMP A defining word to assemble a 4 slot long instruction The machine instruction thus defined will take an address on the Stack and assemble the least significant 18 bits of the address E ai P24 MISC Processor Manual 33 STEREO CIT 005 A CM E S 0 CO lE LY LY LP E LIRE SATIS DT Du ER PR P ARM o ON ER E E at RE into the address field of the inst JMP call CONSTANT DOES anew SWA terminates a colon word by cha into a jump This is tail re return instruction at the end of a LDI add begi ldi n assembles a Load Immedia the literal value to the next n anew HQ Hw RAM DUP SFC0000 AND 1 ruction P 3FFFF AND OR ALIGN BEGIN starts a new program word and marks its address on stack nging the last subroutine cursion which saves the colon word te machine instruction and word 00000 IF 100000 OR Hw RAM ELS 28A28A I CALL assembles a 18 bit call instr E DROP THEN uction to a location in the current page of 256K words JUMP assembles a 18 bit jump instruction to a location in the current page of 256K words BZ assembles a 18 bit conditional branch to a location in the current page of 256K words Br
9. md ne nlt n2 Carry change according to nl and n2 Function Pop S on the data stack and add it to the T register Coding Example The primitive addition in eForth is thus defined CODE UM nn n carry don t use this if you want speed WRC add if 1 ldi ret then dup dup xor 0 ret P24 MISC Processor Manual 21 STEREO CIT 005 A POP Code 18 Usage 011000 ccccce ccccce cccecc ceccce 011000 cceccec ceccce cccccc cccccc 011000 ccccce ecceco ceccece ceeded 0117000 Stack Effects ese a Fe EE xU S Carry unchanged Function Pop the R register on the return stack to the T register Original contents in T are pushed on the data stack Coding Example Exchanging A and T lda push sta pop Exchanging A and R lda pop sta push Increment T sta ldp drop lda now use one add Decrement T dup dup xor com add now use zero com add LDA Code 19 Usage 011001 cccccc ccecccce cccccc ceccec 011001 cccecec ccccec ccccce ceccooc OTIOO0I cocccc Cccc cocco ccecce OITOOT Stack Effects a Carry unchanged Function Copy the contents in the A register to the T register The original content of the T register is pushed on the data stack With LDA and STA the A register can serve as a scratch pad register to save and restore the contents of the T register Coding Example s xample for POP DUP Code 1A Usage OLTOTT Gecece ccecc
10. reset sync Ssloti 2 0 glk Gli acana On power up all registers and the stacks are cleared to zero when clr is held high When clr is lowered to zero the master clock clk will start the CPU from memory location 0 as the initialized P register is pointing to Chapter 2 Device Characteristics Dik Input and Output Signals P24 is very flexible in packaging depending on the memory configuration These are the signals normally brought to I O pins In certain applications the memory is included on chip and the address bus and data bus do not have to be brought out CLK 1 40 MHz master clock A0 23 Address bus to RAM SRAM and I O devices D0 23 Data bus for RAM SRAM and I O devices CLR Low system reset active low Vdd 5V power supply Vss Ground WE Write enable active low INTO 4 External interrupt inputs UART_IN RS232 serial input pin UART_OUT RS232 serial output pin 202 Timing All time periods noted in the following timing diagrams are in periods of the master clock Figure 3 Timing of P24 instruction executions Master Clock Slot0 Signal slot5 slot0 sroti slot2 slot3 slot5 P24 MISC Processor Manual 5 STEREO CIT 005 A N i i T i S A labeled int0 int6 are implemen a a ese two all jump jz jnc Sas TS eeu slot5 slotO slot5 ze l fetch Instr xecut xecut xecut xecut xecut OP and RET instr
11. 13 Usage 010011 eccede ececce ceccce ccecce 010011 codcec ceccce ceccec ceccoece 010011 cceccce eccece cccccc cccccc 010011 Stack Effects nl n2 nl n3 Carry unchanged Function Conditionally add the S register on the data stack to the T register if Bit 0 in A is set If Bit 0 in A is reset T register is not modified The T A register pair is now shifted to the right by one bit This MUL instruction is useful as a multiplication step in implementing a fast software multiplication routine Repeating this instruction 24 times will multiply A and S and produce a 48 bit product in the T A pair T is normally initialized to zero prior to the multiply sequence However any non zero initial value in T adds to the final result in the T A pair Coding Example Multiply two 24 bit unsigned integers Multiplicand is in S Multiplier is in A mul mul mul mul mul mul mul mul P24 MISC Processor Manual 18 STEREO CIT 005 A mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul The 48 bit product is in T A register pair and the multiplicand in S is preserved Primitive multiplication routines are thus defined CODE UM uu ud sta 0 ldi mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul push drop lda pop ret XOR Code 14 Usage 0
12. 60 r SYNC executes the current machine instruction using CLOCK to determine which uns one clock cycle and displays all the registers and stacks simulating the hardware reset PUSH push a new integer into the T register and push the data stack F This is a much more fficient way to set breakpoints and then run till breakpoint is triggered t allows the user to execute a large portion of the program and stop only STEREO CIT 005 A DUP 2 IF I2 C8 execute DROP EXIT THEN DUP 3 IF I3 C8 execute DROP EXIT THEN DUP 4 IF I4 C8 execute THEN DROP NEXT C sync CYCLE S reset FROM P 300 ERASE 0 CLOCK reset G addr CR Press any key to stop CR BREAK BEGIN sync P BREAK IF CYCLE C EXIT ELSE CYCLE THEN KEY UNTIL PUSH d pushs TOT POP pops 9b User Interface This simulator has very simple text based user interface The most used commands are C for single steps RUN to continue stepping with any key and terminated by ESC If the target address is know then G is a convenient choice P allows the user to start simulating at any address D P 1 FOUR FOUR M SHOW RUN CR Press ESC to stop CR BEGIN C KEY 1B UNTIL P RANGE AND DUP FROM P TOP HELP CR eM24 Simulator copyright eMAST Technology 2000 CR C execute next cycle CR S show all register
13. DUP 1 AND gt R 2 TOT FROM A SFFFFFF AND 2 R IF 800000 OR THEN TO A andd SPOPP TO AND SFFFFFF AND T xorr SPOPP TO T XOR SFFFFFF AND T div FROM SSTACK SFFFFFF AND T SFFFFFF AND DUP 1000000 AND DUP gt R IF ELSE DROP T THEN SFFFFFF AND 2 diff A 800000 AND IF 1 THEN TO T FROM A 2 SFFFFFF AND R gt IF 1 THEN TO A add SPOPP SFFFFFF AND TO T Q SFFFFFF AND TOT popr RPOPP SPUSH pushs FROM T SPUSH lda FROM A SPUSH pushr SPOPP RPUSH sta SPOPP TO A pops SPOPP DROP nop NEXT GET forces the simulator to get a key from the keyboard under Windows OS PUT forces the simulator to send a character to the display window i get KEY DUP 1B ABORT done SPUSH ret put SPOPP 7F AND EMIT ret EXECUTE decodes a machine instruction and performs the required operations HEX execute code DUP 0 IF DROP jmp EXIT HEN DUP 1 IF DROP ret EXIT HEN DUP 2 IF DROP jz EXIT THEN DUP 3 IF DROP jnc EXIT HEN DUP 4 IF DROP call EXI HEN P24 MISC Processor Manual 59 STEREO CIT 005 A DUP 6 IF DROP get EXIIT HEN DUP 7 IF DROP put EXI HEN DUP 9 IF DROP lap X 11 HEN DUP OB IF DROP ld EXI HEN DUP 0A IF DROP ldi EXI THEN DUP OD IF DROP stp EXI HEN DUP OF IF DROP st EXI HEN DUP 10 IF DROP com EXI HEN DUP 11 I
14. ECHO PROMPT CSP NUMBER HANDLER CURRENT NP Only these user variables remain and are macros HLD SPAN gt IN TIB TIB EVAL BASE tmp CP CONTEXT LAST ABORT TEXT The P24 eForth system can be summarized in the following words a nd their pseudo code COLD boots Forth print sign on message and jump to QUIT QUIT repeats the sequenc accepts a line of text and executes the commands in sequenc The pseudo code is QUIT BEGIN QUERY EVAL AGAIN QUERY accepts one line of text of 80 characters or terminated by a carriage return EVAL parses out tokens in the text and evaluates them EVAL BEGIN TOKEN WHILE EVAL EXECUTE REPEAT 0K TOKEN parses out one word from the input text EVAL contains SINTERPRET in the interpret mode or COMPILE in the compiling mode EXECUTE executes either SINTERPRET or SCOMPILE OK prints out the OK message SINTERPRET a searches the dictionary for a word of the text string at a If the word exists execute it Else convert the string into a number on the stack Failing to convert the string to a number prints an error message and abort to QUIT SINTERPRET NAME IF EXECUTE ELSE NUMBER IF ELSE ERROR THEN THEN SCOMPILE a searches the dictionary for a word of the text string at
15. Gi ldi st mr UNPACKS unpacks a packed string at a into a counted byte string at b It calls gt B to unpack a 24 bit word into three bytes It allows names of words to be printed and in line packed strings to be accessed as byte strings UNPACKS a b b DUP gt R save b gt B 1F LIT AND 3 LIT FOR AFT gt B DROP THEN NEXT 2DROP R gt Fr eo i n LUE a m 8 6 Number Output Words All numbers in P24 are stored internally as 24 bit binary patterns To make the numbers visual to the user they are converted to strings of digits to be printed A number is converted one digit at a time It is divided by the value stored in BASE and the remainder is converted to a digit by DIGIT The quotient is divided further by BASE to build a complete numeric string suitable for printing The output numeric string is built backward below the memory buffer at PAD using HLD as the pointer moving backward Additional formating characters can be inserted into the output string by HOLD do d P E GEE EET ER d This numeric output mechanism is extremely flexible and can produce P24 MISC Processor Manual 46 STEREO CIT 005 A numbers in a wide variety of formats for tables and arrays It al
16. lda Effec on regis sta 3S Effec on do Example O1110l ccecce teccet cccecc 011101 cedeec cccccc cccccc 011101 CCCCCC CCCCCC CCCCCC wl w2 w3 w2 w3 wl h sta pop ret 1D ts Usa cm no change Example w t ret 011110 xxxxxx XXXXXX cccccc 011110 xxxxxx ecccoc cecce OOLITO coocce deoccec Occcee ts v iem no change cccccc cccccc cccccc 011101 Pop S on the data stack and store it to the T register in the T register is copied into the A register ter so that it can be used to fetch data from memory or store data emory XXXXXX XXXXXX XXXXXX 011110 The original contents This instruction will force th Actually this is what the NOP but in the current ACT LE P24 MISC Processor Manual xecut stat to slot 5 This instruction initializes to get EL implementation the NOP instead passes control to the next instruction slot 24 usually inserted by assembler STEREO CIT 005 A Usage OlITTIl cecce ecocee ceco ceccce 011111 coccec cececec ceccee ececec OIIIIIl ceeccc eccece ceccec ececec 011111 Stack Effects giu Carry unchanged Function Pop S on the data stack and store it to the T register The original contents in the T register are lost Coding Example s xample for jump Chapter 3 1 G Buss Instructions Ga Code 2G where G is 4bit G Buss address Usage T Oggggi Ce
17. 0 lt MAX nn n 2DUP lt IF SWAP THEN DROP MIN nn n 2DUP SWAP lt IF SWAP THEN DROP WITHIN u ul uh t ul lt u lt uh 8 TN SSD A LO RS Be Be d POE E OVER gt R R gt U lt 3 Division UM MOD and MOD share the same body to do division of a 48 bit divident by a 24 bit divisor using the DIV machine instruction The higher half of the divident is placed in T and the lower half is placed in A The divisor is negated and placed on the data stack below T The negated divsor is added to T in the adder If a carry is generated indicating that T is big enought to subtract the divisor The sum is accepted into T and then T A combination is shifted left by one bit The most significant bit in A is shifted into T 0 and Carry is shifted into A 0 If the adder does not generate a carry the subtraction will not be done The T A combination is shifted left by one bit and a 0 is shifted into A 0 M road cd The above divide step DIV instructions is repeated 25 times to generate the proper quotient in A The remainder is in T if it is shifted right by one bit The only restriction in this division procedure is that the divisor and the divident must be positive It cannot handle negative divisor or negative divident This is not a serious limitation because the special word M MOD does signed division by first convert both divisor and divident to postive
18. 7F LIT BL WITHIN IF DROP CHAR 5F LIT THEN CRR Memory access CRR HERE a CP PAD a CB SOULLT 33 TIB a TIB CRR EXECUTE a DUP IF EXECUTE THEN ONE AR C LP AA LE CMOVE bbu FOR AFT gt R DUP R 1 R gt 1 THEN NEXT 2DROP PILE b uu e SWAP FOR SWAP AFT 2DUP 1 THEN NEXT 2DROP 6 String Packing and Unpacking Words PACKS packs the string at b with length u into memory located at a three bytes to a 24 bit program word It calls B gt to do the packing This packing function greatly reduces the total size of the P24 code image The packing also speeds up the dictionary searches because thr bytes are compared at once The system scratch variable TMP is used to store the byte count which directs the bytes to their proper location After the byte string is fully packed the last packed program word is left justified and empty slots are filled with NUL bytes PACKS bua a null fill dup push P24 MISC Processor Manual 45 STEREO CIT 005 A 1 ldi tmp sta st sta dup push st lda pop FOR AFT b a B tmp sta ld IF ld 1 ldi xor IF dup dup xor st 1 ldi add E 2 ldi st N TH ELSE 1 THEN THEN NEXT tmp sta ld IF ld 2 ldi xor IF sta ld shl shl shl sh shl shl shl sh st lda THEN sta ld shl shl shl sh shl shl shl sh st lda THEN drop drop pop
19. Gcccce 010001 ccecccoc ceccce ecccce cceccc 010001 cecece ecccce ccecec codeec 010001 Stack Effects n 2n Carry Bit 23 of T is shifted into carry Function Shift all lower 24 bits in the T register to the left by 1 bit The lowest Bit 0 is cleared Coding Example Multiply T by 3 dup shl add Multiply by 5 dup shl shl add Multiply by 6 dup shl add shl SHL allows the negative bit of T 23 to be tested as carry T 24 CODE O n f shl if drop 1 ldi ret then dup xor 0 ldi ret SHR Code 12 Usage 0l0010 cccecc cccecoe ceecce cecoecc 0I0010 Gooccec ceccce ececec ceccee 010010 CECE eceece Gcecocc ecdecce 010010 Stack Effects n n 2 Carry no change Function Shift the contents of the T register right by one bit Bit 0 is shifted to the bit banged UART serial output The sign Bit23 is preserved Coding Example P24 MISC Processor Manual 17 STEREO CIT 005 A SHR is used to implement a simple UART The lowest bit in T T 0 is shifted out to the UART serial output pin and the UART serial input pin is loaded into carry for testing CODE EMIT c S7F ldi and shl SFFFFO1 ldi xor 0A ldi FOR shr 100us NEXT drop ret CODE KEY c SFFFFFF ldi begin shr until repeat wait for start bit 50us 35 rear FOR 100us shr if 80 ldi xor then NEXT SFF ldi and 100us ret MUL Code
20. P SWAP DROP re a F Terminal Input It up the character pointer and erased the character preceeding TAP echoes an input character and deposit it into the terminal input buffer kTAP Detects a Carriage Return to terminate the input stream to process a Back Space al so cal ls H characters It and TAP to process ordinary These words allows the interpreter to handle a human user on the termi H C THEN TAP nal Terminal bbb ER R gt SWAE BkSp smoothly D CR bb OV and friendly R b backspace R XOR Ld 8 EMI iT h MIT distructive TT bot eot cu D DUE kTAP DUP IF EMIT OVER Cr BkSp bot eot cu OD 8 LET EMIT backspace r c bot eot cur 1 FF rc bot eot cur LIT XOR XOR IF BL TAP F LSE EXIT THI QUI pu compiling EN DROP SWAP ERY accepts them in t DRO a li The li H THEN P DUP 277 ne of characters typed in by the user and he terminal input buffer for interpreting or ne is terminated at the 80th input character or a Carriage Return accept minal input buffer at b with length u same buffer address b with the length of the character string Cer actual waits for y received EXPECT variabl input characters and pla
21. SPACES n BL CHARS TYPE bu FOR AFT DUP gt CHAR EMIT 1 THEN NEXT DROP CR Cr OA LIT OD LIT EMIT EMIT dos a R gt R TEXT UNPACKS R R gt 3FFFFF LIT AND 30000 LIT 1 gt R SWAP gt R CRR ee S AR pe a doS do COUNT TYPE R n n gt R str R gt OVER SPACES TYPE U R u n gt R lt 4S gt R gt OVER SPACES TYPE Tio C ur RS S gt SPACE TYPE e T E S BASE OA LIT XOR 8 TOKEN parses out the next word in the input stream delimited by spaces The word is packed and placed on the top of the dictionary so that it can be used to do dictionary searches and becomes the Pe T T EIE dae e EM ET ee AN IF U EXIT THEN str SPACE TYPE 7 Word Parser name field if the word just happed to be the name of a new definition PARSE allows the user to specify the delimiting character to parse out the next word in the input stream It calls parse to do the dirty work parse scans the input stream and skips the leading blanks if PACE is the delimiting character The parsed word starts with he next non delimiting character and is terminated by the next elimiting character It returns b the beginning address of the arsed word u the length of the remaining characters in the input tream an
22. STEREO CIT 005 A RSTACK returns address of top of return stack SSTACK returns address of top of data stack P REGISTER T REGISTER 4 R REGISTER 8 A REGISTER 12 I REGISTER 24 10 REGISTER 28 Il REGISTER 29 I2 REGISTER 30 13 REGISTER 31 I4 REGISTER 32 RP REGISTER 33 SP REGISTER 34 RSTACK RP C LIMIT AND CELLS REGISTER 40 SSTACK SP C LIMIT AND CELLS REGISTER 80 9 2 Machine Cycles Here are a set of words supporting the simulator CYCLE simulate rising edge of master clock Copy TO array to FROM array NEX forces fetching the next program word RPUSH push a integer d on return stack RPOPP pop return stack and leave the integer on the Forth stack SPUSH push a integer d on data stack SPOPP pop data stack and leave the integer on the Forth stack CONTINUE fetch next program word and deposit the 4 machine instructions in 11 14 CYCLE TO P FROM P 180 CMOVE 1 CLOCK NEXT CLOCK 7 OR CLOCK RPUSH d push d on return stack FROM R RP C 1 LIMIT AND TO RP C RSTACK R RPOPP d pop d from return stack FROM R RSTACK RP CQ 1 LIMIT AND TO RP C R SPUSH d push d on data stack FROM T SP C 1 LIMIT AND TO SP C SSTACK
23. a If the word exists compile it P24 MISC Processor Manual 41 STEREO CIT 005 A Else convert the string to a number and compile the number as a literal Failing the conversion prints a message and abort to QUIT SCOMPILE NAME IF ELSE NUMBER IF LITERAL ELSE ERROR THEN THEN NAME calls find to locate a word of the name parsed out out the input text string NUMBER a converts the text string at a to a number ERROR prints the offending text string and aborts to QUIT ITERAL n compiles n as a literal into the current word being compiled The above words serve as a top down map of the eForth operating system The eForth system source code builds up to QUIT and COLD Most words in EF24 F are necessary in the building process The eForth system can be viewed as a very sophisticated application of P24 Most applications are much simplier than eForth system You can model your application code to eForth and use all the tools contained therein gu Serial Port 50us delays 52 us half of a bit at 9600 baud 100us delays 104 us one bit frame at 9600 baud a Lr EMIT c sends character c to the serial output port KEY c waits for a character from the serial input port The serial ports are actually connected to the T register x LA The No Cost UART On executing SHR instruction the least signi
24. a zero the multiplicant is not added The T A combination is shifted to the right and a zero is shifted into T 23 After the MUL instruction is repeated 24 times a 48 bit product is produced in the 1 Tr has the more significant T A combination half and A has the less significant half of the product P dh E a AS QU M E p Both UM and do the unsigned multiplication M does signed multiplication For correctness should call M to do the multiplicant However here calls UM for speed You should P P24 MISC Processor Manual 44 STEREO CIT 005 A be aware of this property in your applications As the eForth system only does unsigned multiplications it is not a problem CRR Multiply CRR CODE UM u u ud sta 0 ldi mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul mul push drop lda pop ret so cen auf y UM DROP 5 M nn d 2DUP XOR 0 lt gt R ABS SWAP ABS UM R gt IF DNEGATE THEN MOD nnn rq gt R M R gt M MOD nnn q MOD SWAP DROP 8 5 Memory Access Words 8 6 gt CHAR filters out non printable characters for TYPE It thus ensures that TYPEing a non printable character will not choke the printer CRR Bits amp Bytes CRR gt CHAR c c S7F LIT AND DUP
25. about 75 of 54SX72A registers and logic modules Current implementation runs at 10 MHz t x x X X 0x 1 2 Architecture of P24 CPU P24 has the following registers Address Register supplying address for memory read and write Instruction Latch holding instructions to be executed Program Counter pointing to the next program word in memory Top of Return Stack Top of Data stack Accumulator for ALU Hn DOH Pp P24 MISC Processor Manual 1 STEREO CIT 005 A All registers are 24 bit wide Original text Applies to D implementation T R S and r Ting s VHDL model but not to the current Actel A are all 25 bits wide The most significant bit in T T 24 is the carry produced by the 24 bit adder This carry bit is preserved as data in T is tra preservation of carry bit gre allows interrupts to be servi nsferred to other registers and to the stacks The atly simplifies the logic processing of data and memory without having to sav ces when the next program word is fetches from the e the carry bit and restore it on return Unlike the original specifica Does not provide the extra bi bit is rather held in a dedic operation affecting the carry P24 has two stacks tion by Dr Ting the current ACTEL implementation t width needed to preserve the carry bit The carry ated flip flop and is preserved only until the next bit S stack Data stack 17 levels deep R stack Return stack 3
26. l to memory at A to memory at A Increment A Costa Increment A 08 RR8 Rotate right T by 8 bits OC NIP Pop S Equivalent to SWAP DROP 10 COM Complement all bits in T 11 SHL Shift T left 1 bit 12 SHR Shift T right 1 bit 13 MUL Multiplication step 14 XOR Pop S and Exclusive OR it to T 15 AND Pop S and AND it to T 16 DIV Division step 17 ADD Pop S and add it to T Register Instructions 18 POP Pop R to push T 19 LDA Push A to T 1A DUP Duplicate T 1B OVER S to T push original T LG PUSH Pop T to push R 1D STA Pop T to A lE NOP Do nothing 1F DROP Pop T OE Reserved 3 62 P24 Instructions JUMP SKIP ELSE AGAIN REPEAT Code 0 Usage 00000 aaaaaa aaaaaa aaaaaa Stack Effects none Carry no change Function P24 MISC Processor Manual Post decrement R STEREO CIT 005 A Jump to the 18 bit address in the bit field 17 0 in the current 256K word page of memory It must be in slot 0 of Restriction locations outside of a memory page a word This instruction allows the program to be redirected to any location within an 256K word page of memory It does not cross page boundaries To jump to one has to push the target address on the return stack and execute the RET instruction to effect a long jump This restriction also applies to CALL JZ Coding Example CODE 50us 2 ldi skip CODE 100us 1 Adr then sta 138 ldi begi
27. n2 nl n2 nl push dup sta pop lda 2DROP ww drop drop ww w add NOT w W com NEGATE n n com 1 ldi add tool moa 1 ldi add Tr cara ldi add BL 32 20 ldi dol neges sta ld add st i ww W add com add 1 ldi a3 Forth Words Coded in Assembler 38 than ns in shorter code r there are also machine ue the packing from nstructions STEREO CIT 005 A Foll code word dt ui c d following doVAR doNEXT terminates a FOR NEXT loop on the return stack CR kernel words CR CODE doVAR pop ret CODE doNEXT pop pop dup if 1 ldi add push owing words are complicated and hav doVAR starts a variable or an array to be defined as It returns the address It decrements the counter It exits the loop when the count is O0 decrement count push ret if index is not 0 loop back then drop 1 ldi add index is 0 exit loop and continue push ret Following are Forth words which are too long for macros yet still easily expressible in machine instructions They are all commonly used Forth words UM nn sum carry is a special word in eForth to provide carry in addition However it is not used here because carry is readily accessible using if or BNC Note that BZ removes the flag tested from the stack while BNC does not disturb the data stack Thus BZ c
28. numbers for division P24 MISC Processor Manual 43 STEREO CIT 005 A DE operations and then place appropriate signs in front of quotient and remainder ee UM MOD MOD and MOD all assume that divisors and dividents are positive In the eForth system this is not a problem Nevertheless users must be aware of this limitation when writing code which must handle negative numbers CRR Divide CRR CODE UM MOD ud u ur uq com 1 ldi add sta push lda push sta pop pop Skip CODE MOD nn rq com 1 ldi add push sta pop 0 ldi then div div div div div div div div div div div div div div div div div div div div div div div div div 1 ldi xor shr push drop pop lda ret CODE MOD nn r MOD drop ret CODE nn q MOD push drop pop ret M MOD dn r q floored DUP O DUP gt R IF NEGATE gt R DNEGATE R gt THEN gt R DUP 0 lt IF R THEN R gt UM MOD R gt IF SWAP NEGATE SWAP THEN 8 4 Multiplication Words UM multiplies two unsigned 24 bit integers and produces a 48 bit product The multiplier is placed in A register and the multiplicant is placed on the data stack below T T is cleared to zero The MUL machine instruction looks at A 0 bit If it is a one the multiplicant is added to T and the T A combination is shifted to the right by one bit Carry us shifted into T 23 It A 0 is
29. returns the address of the packed string and a 0 for a false flag IA find runs through the dictionary very quickly because it compares the length and the first two characters in the names Most Forth words are unique in these three characters For words with the same lengths and identical first two characters find calls SAME to determine whether the remaining characters of the packed strings match NAME gt converts a name field address na to a code field address xt CRR Dictionary Search CRR 1 NAME gt na xt DUP S3FFFFF LIT AND 30000 LIT lt 7 SAME aau aa 0 30000 LIT FOR AFT OVER R OVER R DUP IF R gt DROP EXIT THEN THEN NEXT 0 LIT find a va xt na aF SWAP va a P24 MISC Processor Manual 49 STEREO CIT 005 A 8 EC I A e De CRR POG eee Rae I Ee ON Be EO ES UP Up n Ou IN G IF LE UP t gt SWAP DU va va a a PO rua DUP T3 ok Lll h HI 9 the Bac ELS m E P 1 tmp N DRO 1 DRO E SWAP at nd H processes the Back Space encountered in the input stream backs k Sapce P SWAP 1 xt na get cell count count a a Va na na P Q S3FFFFF LIT AND R XOR ignore lexicon bits SAME SWAP EXIT a F la
30. shown above Gbuss addresses 2 and 3 are currently read only returning 0 and 1 respectively Special assembler words zero and one compile the instructions to read Gbuss addresses 2 and 3 P24 MISC Processor Manual 26 STEREO CIT 005 A Gbuss addresses 2 and 3 are available for write only applications Gbuss addresses 4 15 ar ntirely available Typical Gbuss peripherals that might be added depending on application include 1 A timer to produce periodic interrupts at a programmable interval 2 A FIFO for buffering event data producing an interrupt when full or half full 3 Scratch pad registers 4 Hardware single step multiplier with operands taken from pair of scratch pad registers 5 I O ports 6 Registers to control and monitor app specific on chip functions 7 Additional UARTs Chapter 4 P24 Metacompiler i This section has not been updated to reflect changes made for the ACTEL implementation See the comments in files meta24i f ok24i f kern24i f and ef24i f for a log of the changes The main changes are use of the hardware UART inclusion of target resident assembly words and the repositioning of certain buffers and system variables used by Forth Multi tasking words and buffered interrupt driven serial i o words are in the file multi3 f and are not o f p e urrently present at boot Multi tasking words are doc
31. written in assembly are so done However much more optimization is achieved by a set of macros which try to convert the most commonly used high level Forth words into machine instructions and packs these machine instruction as tightly as possible Th nd results are that the code size is significantly reduced and the execution speed greatly increased The use of macros will be further explained along with the code The code words in this file alse serve as programming examples for the optimal use of the P24 CPU It is worth you while to study them carefully and use them as templates when you like to convert high level application words into assembly The Forth Virtual Engine is T top of stack S data stack 16 levels R return stack 16 levels Both the data and return stacks are in CPU The A register is used by the memory fetching and storing instructions to provide address to the external memory When not used to address memory A can be used as a scratched register P24 MISC Processor Manual 36 STEREO CIT 005 A In the Subroutine thread model eliminates IP doColon and MUL and DIV instructions the A register serves as the extension to the T register to hold the lower half of the partial product or the divident 16 levels of stacks are enough for most applications Memory wrap around when exhausted allocation 0 Boot code 10 Initial variables
32. 00 AA RAM 9s Running P24 Simulator From Windows load Win32Forth by clicking its icon on the desktop or run it in the Start Programs Win32Forth Win32Forth Win32Forth opens a window Click File OpenFile and navigate to the directory in which all the P24 files are stored Select one of the files say META24 F and an WinView window is opened displaying the META24 F file Go back to the Win32Forth window and type Fload meta24 You will see a list of names and compiled addresses scrolling on the screen This list of names and addresses are very useful in running the simulator You can interpret the addresses and determine which word is being executed and you can select specific words to simulate You can inspect the compiled target image by typing 0 show show show to dump the memory 128 words at a time SHOW will change the starting address So that you can use it to dump consecutive blocks of target memory without giving the address explicitly Load simulator file by typing Fload sim24 Type HELP to see all the useful commands in the simulator Then use C RUN G P commands to step through programs you want to debug Type BRAM to dump the target memory in a form acceptable to the VHDL synthesizer in the Foundation FPGA development system The eForth system can be synthesized with the P24 core and run in XCV300 FPGA or its large cousins from Xilinx P24 system is still u
33. 1 NEXT UMP b u gt R HEX 8 LIT AFT CR 8 LIT 2DUP dm EXT DROP R BASE Ld NAME XOR E SWAP DROP EXIT T SWAP DROP a 4 UNPACKS NT 01F LIT AND TYPE H 155 Sx H SPACE SEE string BEGIN LIT FOR DUP DUP FC0000 LIT AND DUP IF 100000 TB ELSE LIT XOR SPACE 3FFFF LIT AND gt NAM UP IF ID THEN 1 KEY OD LIT ROP THEN Ld can t use CONTEXT DUP UP SPACE I 2 LD l P24 MISC Processor Manual EVAL ESC on terminal 53 STEREO CIT 005 A po EPEAT CODE S dump all 17 stack items AD sta stp tp stp stp stp stp stp stp tp stp stp stp stp stp stp ROP PAD 10 LIT OR DUP 1 NEXT ROP PAD G CR Onicooonunou Ug st ko 8 14 Start Up CRR Hardware reset CRR DIAGNOSE E 65 LIT F prove UM 0 lt carry TRUE FALSE O LIT 0 lt 2 LIT 0 lt 0 FFFF UM DROP V FFFF 1 3 LIT UM UM DROP 3 43 LIT UM DROP NEI o logic XOR AND OR 4F LIT 6F LIT XOR 20h SFO LIT AND 4F LIT OR r stack DUP OVER SWAP DROP 8 LIT 6 LIT SWAP OVER XOR 3 LIT AND AND 70 LIT UM DROP Ux t prove BRANCH BRANCH O LIT IF 3F LIT THEN 1 LIT IF 74 LIT ELSE 21 LIT THEN
34. 10100 cccccc ccccce cccccc cccccc 010100 cccccc cccccc ceccee ceccec 010100 ccecce ccecce cccocc ceccece 010100 Stack Effects neh ngz um3 Carry unchanged Function Pop S on the data stack and exclusive OR it to the T register All 24 bits in T are affected Coding Example To clear T to zero dup xor now use more transparent drop zero To generate a zero in T register dup dup xor now use faster zero T is duplicated twice to save its contents The two duplicated copies of T are XOR ed together All the reset bits remained reset All set bits get reset Thus a 0 is created in T It costs 5 slots to produce a 1 lidi CEccte ceccco iocoedco Td P24 MISC Processor Manual 19 STEREO CIT 005 A vs dup dup xor com now use faster zero com AND Code 15 Usage O1010l cceeec ccecce ceccce ccecce 010101 docce cecec e ccecce cecece 010101 cecece cococc ceceo Ceecee 010101 Stack Effects n i nn2 n3 Carry unchanged Function Pop S on the data stack and AND it to the T register All 24 bits in T are affected Coding Example DIV Code 16 Usage 010110 cecco coGecec ceccce ccecce 010110 ceccec ceccce ececee ececcde 010110 ceccce Gogcoe ecccce cceccec OLOLLO Stack Effects ni n2 nl n3 Carry unchanged Function Add the S register on the data stack to the T register If the addition produces a carry place the sum in T otherwise leave T un
35. 18 Kernel 9A Forth words 700 RAM variables 710 Text buffer 730 TIB 780 User dictionary TEE End of memory 6 1 data SR EAS ee PAN TIB TIB BASE System Variable All the system variables are defined as macros assembled as literal LD points to buffer for output numeric string EXIT They will They will be ls in the form of LDI instructions On execution they will return their respective addresses on the stack It is assumed that the target system has RAM starting from location 700 For a different target system to change the locations in these macros you have variable to hold the length of input text string length of the input text string location of the terminal input buffer base for number conversions CONT LAST EVA EXT pointer to start dictionary searches CP points to the top of the dictionary points to the name field of the last word ABO TEXT tmp ex CRR E SR ETC un unt SD ee eee SPAN gt IN TIB TIB BASE HLD 700 ldi RT points to error recovery routine points to text buffer to unpack strings a scratch pad variable CRR scratch 701 ldi chars input by EXPECT System variables N N 702 ldi input buffer offset TOS dai 3 704 ldi TIB 705 ldi number base CRR CON GP Y LAST EXT 706 ldi first search vocabulary 07 ld
36. 3 The return stack is used to p data stack is used to pass pa these two stacks in the CPU h programming language levels deep reserve return addresses on subroutine calls The rameters among the nested subroutine calls With ardware P24 is optimized to support the Forth The 24 bit P24 CPU sports a small RISC like instruction set Four 6 bit instructions are packed into after a word is fetched from memory that is easily programmed in T and the return stack is 3 The following diagram shows t registers the stacks and th Not shown in the diagram is t data bus When reading data address to the address bus a register When writing data and data is written to the da one 24 bit word and are executed consecutively The P24 CPU has a two stack architecture Forth The data stack is 17 levels deep including 3 levels depth he architecture of the P24 processor It shows the e data paths among them he connection between T register and the external from memory the A register supplies the memory nd data is latch from the data bus into the T into memory the address is supplied by A register ta bus from the T register Figure 1 The architecture of P24 Data Bus Address Bus v HS em I P A i V V c P24 MISC Processor Manual 2 STEREO CIT 005 A Return Stack R gt T gt S Data Stack
37. CRR t alias forth count alias forthCOUNT Chuck Moore preferred this name for XOR OR XOR RAM is a large array to hold the binary image of P24 target P24 is a 24 bit CPU One 24 bit program word is compiled into a 32 bit word in this array RESET clears the RAM array RAM a uses a word address to fetch a program word in RAM RAM na stores a word n into RAM at address a EATE ram 8000 ALLOT RESET ram 8000 ERASE RESET RAM 4 ram Q RAM 4 ram FOUR displays four consecutive words in target SHOW displays 128 words in target from address a It also returns at128 so you can SHOW the next block of 128 words SHOWRAM displays th ntire image 2048 words FOUR 4 0 DO DUP RAM 7 U R 1 LOOP SHOW a 10 0 DO CR DUP 7 R SPACE FOUR SPACE FOUR LOOP showram 0 0c 0 do show loop drop UD displays a 24 bit word in 8 digits with leading zeros P24 MISC Processor Manual 29 STEREO CIT 005 A gu ue CAIO MO Ru TR LS QE TIA 1 4 B displays one byte in two digits C displays nibble in one digit STRING displays the attribute init string in the VHDL format required by Xilinx Foundation synthesizer The string attribute INIT is temporarily replaced by qq to avoid lines broken by Forth output routine When the whol attribute blocks are pasted into the VHDL code qq must be globally replaced by attribute INIT_
38. F DROP sh EXI HEN DUP 12 IF DROP shr EXI HEN DUP 13 IF DROP mul EXI HEN DUP 14 IF DROP xorr EXI HEN DUP 15 IF DROP andd EXI HEN DUP 16 IF DROP div EXI HEN DUP 17 IF DROP add EXI HEN DUP 18 IF DROP popr EXI HEN DUP 19 IF DROP lda EXI HEN DUP 1A IF DROP pushs EXI THE DUP 1C IF DROP pushr EXIT THE DUP 1D IF DROP sta EXI HEN DUP 1E IF DROP nop EXI HEN DUP 1F IF DROP pops EXI HEN CR illegal code ABORT r 9 4 Instruction Execution STACK displays the contents of a sta SSTACK displays the contents of data stack RSTACK displays the contents of return stack REGISTERS displays contents of all the relevant registers S show all the registers and stack at this cycle slot is being executed Cr RESET clear both FROM and TO arrays G run and stop at the address given on the Forth stack e I on specified location POP discard the contents in T and pop data stack back into T stack add 0 DO DUP 4 LOOP DROP CR sstack S T SSTACK SP CQ s rstack R R RSTACK RP CQ s registers P I IQ 2 IT2 TLI C I2 12 CQ I32 I3 CQ I4 I4 CQ eM VACCA QE S S CR CLOCK CLOCK registers Sstack rstack sync CLOCK 7 AND ck tack tack CR DUP 0 IF continue DROP EXIT DUP 1 IF Il C execute DROP THEN P24 MISC Processor Manual THEN EXIT
39. STEREO CIT 005 A P24 MISC Microprocessor User s Manual Dici Ci Ho Ting c Copyright 2000 eMAST Technology Corp Hsinchu Taiwan Republic of China Updated by Walter Cook 1 23 01 to reflect adaptation to the ACTEL 54SX72A Caltech document number STEREO CIT 004 A Carry bit documentation corrected 10 9 01 WRC Chapter 1 INTRODUCTION Teas General Information P24 is Minimal Instruction Set Computer design patterned after Mr Chuck Moore s MuP21 P24 has a 24 bit CPU core with dual stack architecture intended to efficiently execute Forth like instructions The processor design is simple to allow implementation within field programmable gate arrays P24 employs a RISC like instruction set with four 6 bit instructions packed into 24 bit words The most significant bit of each instruction designates an I O Buss operation when set For I O Buss instructions the I O buss will be referred to as the G buss the second most significant bit specifies a write when set read when cleared while the remaining four bits specify the G buss address For non G buss instructions the most significant bit is cleared and the remaining 5 bits specify 32 possible instructions 31 of which are implemented Following is a list of unique features of P24 24 bit address and data buses 6 bit RISC like CPU instructions 4 deep instruction cache 17 deep data stack 33 deep return stack Uses
40. T SPOPP d pop d from data stack FROM T SSTACK SP C 1 LIMIT AND TO SP C T continue FROM P DUP 1 TO RANGE AND P RAM DUP I 64 MOD SWAP 14 C 64 MOD SWAP I3 C 64 MOD SWAP I2 C 63 AND I1 C 93 Machine Instructions Machine instructions in the simulator take current values in the FROM registers and stacks and compute the desired new values and deposit them in the TO registers Their functions in the real P24 CPU are performed by multiplexers and logic circuits Nevertheless these instructions truthfully describe the behavior of all the machine instructions P24 MISC Processor Manual 58 STEREO CIT 005 A jmp FROM I RANGE AND TO P NEXT call FROM P RPUSH jmp ret RPOPP TO RANGE AND P NEXT jz SPOPP SFFFFFF AND IF NEXT EXIT THEN jmp jnc FROM T 1000000 AND IF NEXT EXIT THEN jmp ld FROM A 8 RANGE AND RAM SPUSH ldp ld FROM A 1 TO A ldi FROM P 1 RANGE AND TO P FROM P RANGE AND RAM SPUSH st SPOPP FROM A RANGE AND RAM stp st FROM A 1 TOA com FROM SFFFFFF AND SFFFFFF XOR TO T shr FROM T 2 SFFFFFF AND TO T shl FROM T 2 SIFFFFFF AND TOT mul FROM A 8 1 AND IF SSTACK 8 T SIFFFFFF AND ELSE T 8 THEN
41. abilize before the next rising clock edge strikes The architecture is very simple and components are very similar to one another It should be very easy to do a good layout and the routing should not be difficult Figure 2 The block diagrams of P24 components The T and Data Stack Data Path P24 MISC Processor Manual 3 STEREO CIT 005 A Sa i a spop stt 2 tload spush 4 nia elk s clk c amp t 2 elpc elre SFE 25555 2 5 p ARd EX2 n We accom B ti prin alate PI MAS data b sel The A Register and A Mux b a in a atl stt amp a 2 aload A a 2tc clk cle a selss 5 ol e The Return Stack Data Path See Sse o 1 i1bhzc r out tif R E r_stack n 0u0t pulse fpop e possa oEload rpush Cclk clk clir elr r sel dcr Teese i le The Program Counter Data Path interrupt p amp i 17 0 p_in P p address Prisa enn gut lors poc ee pload clk Clin HS a p sei t a m sel data I 1 23 0 code 5 0 iload P24 MISC Processor Manual 4 STEREO CIT 005 A N
42. an be used to code IF directly and BNC will let IF to test T repeatedly using the SHL instruction CR CODE 0 lt n f shl if drop 1 ldi ret then dup xor 0 ldi ret CODE OR nn n com push com pop and com ret CODE UM Con an Carry add if 1 ldi ret then dup dup xor 0 ret CODE DUP w ww 0 dup if dup ret then ret CODE ROT wl w2 w3 w2 w3 wl push push sta pop pop lda ret CODE 2DUP wl w2 wl w2 wl w2 dup push push dup sta pop lda pop ret CR P24 MISC Processor Manual 39 STEREO CIT 005 A COD COD CR COD COD COD COD 6 4 o B O cd E DNEGATE d d com push com 1 ldi add if pop ret hen op 1 ldi add ret ABS n n up shl if drop com 1 ldi add ret then drop ret E ww t Xor if dup dup xor ret then 1 ldi ret E 2t Cd amas sta push stp pop st ret E20 a d sta ldp ld ret E COUNT a acl n sta ldp push lda pop ret Packing and Unpacking Text Strings B adds one byte at b to the word at a It shifts the existing data in a left by 8 bits Returns b 1 and a and is ready to pack in the next byte S gt a f u gt R OD OQ Qe e ae COD tring B gt is used by PACKS to pack a byte string into a packed B unpacks three bytes in a and puts them at b Returns 1 and b 3 so it is ready to unpack the next word The irst byte unpacked is also
43. anch on T 0 BNC assembles a 18 bit conditional branch to a location in the current page of 256K words Branch on Carry Not Set UNTIL assembles a branch on T 0 UNTIL assembles a branch on no carry 0000 JMP call JMP jump 80000 JMP bz C0000 JMP bnc 80000 JUMP until C0000 JMP until The following words build structures in assembly code words much like those in the high level code Since we use the Subroutine Thread Model for colon words these structure words will be used in the colon words as well The structures are IF THEN IF ELSE THEN SKIP THE BEGIN AGIAN BEGIN UNTIL BEGIN WHILE REPEAT IF WHILE UNTIL are similar to IF WHILE UNTIL except that they assemble BNC instead of BZ Pf begin 0 bz EE begin 0 bnc Skip begin 0 jump then DUP gt R gt R begin 3FFFF AND R gt RAM OR R gt RAM else Skip SWAP then while if SWAP whi repe agai 3 Here RET le if SWAP at jump then n jump Single Slot Instructions is the list of all the single returns from subroutine call A is auto incremented P24 MISC Processor Manual slot machine instructions LDP loads a word and pushes it to T Address of word is in A 34 STEREO CIT 005 A LD load a word and pushes it to T Address of word is in A STP pops a word from T and stores it to memory Address of word is in A A is auto incre
44. ccce cecco ececce cccccc 10gggg cccccc cecccc ccecce ceccoc 10gggg cecccc ececce Geecce ccecce l0gggg Stack Effects Gn Soo Carry unchanged Function Read G buss address gggg and store in T push original contents of T to data stack Coding example CODE KEY c waits for a serial character and returns it begin g0 10000 ldi and until gl ret Note Presently assembler words are implemented only for reading Gbuss addresses 0 1 2 and 3 The corresponding assembler words are g0 gl zero and one See discussion below G Code 3G where G is 4bit G Buss address Usage llgggg Gcceocc ceccce cecece ccecce llgggg cccccc ccecce cceccec cccccc llgggg cccccc ececee cecece ccecce TLlgggg Stack Effects e P24 MISC Processor Manual 25 STEREO CIT 005 A Carry unchanged Function Pop S from data stack into T Original contents of T are written to G buss address gggg Coding example CODE EMIT c waits for previous transmit to complete then sends character begin g0 20000 ldi and until gl Ret Chapter 3 2 G Buss Peripherals Interrupt Register and UART Currently G buss peripherals include only an interrupt control and status register at address 0 the UART send receive data register at address 1 and read only zero and one at addresses 2 and 3 respectively The interrupt control register at add
45. ce them in the It returns the receives the input stream and stores the length in the le SPAN P24 MISC Processor Manual 50 STEREO CIT 005 A CRR accept bu bu OVER OVER BEGIN 2DUP XOR WHILE KEY DUP BL 5F LIT U lt IE AP ELSE KTAP THEN REPEAT DROP OVER EXPECT bu accept SPAN DROP QUERY TIB 50 LIT accept TIB DROP 0 LIT gt IN G 8 10 Error Handling Words ABORT actually executes QUIT which is defined much later Here it is defined as a vectored execution word which gets the execution address in the system variable ABORT This mechanism also gives the user some flexibility in how the application should handle an error condition abort aborts after a warning message is displayed ERROR prints the character string store in the TEXT buffer before aborting The TEXT buffer contains the word just parsed out of the input stream This is the word which the interpreter compiler fail to recognize The natural error message is this word followed by a mark CRR Error handling CRR ABORT ABORT EXECUTE abort f IF do COUNT TYPE ABORT THEN do DROP ERROR a SPACE TEXT COUNT TYPE 3F LIT EMIT CR ABORT 8 11 Text Interpreter SINTERPRET interprets the word just parsed out of the in
46. changed The T A register pair is now shifted to the left by one bit Carry is shifted into A 0 This DIV instruction is useful as a division step in implementing a fast software division routine Repeating this instruction 25 times will divide a 48 bit number originally in the T A register pair by the negative of the number in S leaving the result in A and remainder in T Coding Example Divide a 48 bit positive integer by a positive divisor The negated divisor is Ln cS div div div div div div div div div div div div div div div div P24 MISC Processor Manual 20 STEREO CIT 005 A div div div div div div div div div shr Note I think that this last shr undoes the most recent shl that is part of div aligning the remainder properly in T Also I think this division actually only works properly for 47 bit unsigned numbers in T A WRC Primitive division routines are thus defined CODE UM MOD ud u ur uq com 1 ldi add sta push lda push sta pop pop skip CODE MOD nn rq com 1 ldi add push sta pop 0 ldi then div div div div div div div div div div div div div div div div div div div div div div div div div 1 ldi xor shr push drop pop lda ret ADD Code 17 Usage 010111 ceccce cecco coccec ececed 010111 cococoec cocccc ecooccco cooococ 0L0I 11 CCEecce ececee ccecco cecece OLOLTI Stack Effects
47. ched P is auto incremented and ready to read the next instruction When a CALL instruction is executed the address in P is pushed on the return stack When a return RET instructions is executed the previously saved address in R is popped back into P The execution sequence interrupted by CALL can now be resumed P24 is a microprocessor with 24 bit instructions Each instruction contains up to 4 6 bit machine codes The instruction fields in a program word can be shown as follows Bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Instruction 1 Instruction 2 Instruction 3 Instruction 4 There are 64 possible instructions in a 6 bit field Half of these are used for G Buss access and are specified by a one in the most significant bit of the six bit field For G Buss access instructions the next most significant bit specifies write if set read if cleared while the remaining 4 bits are the G Buss address The G Buss is intended to provide fast access to on chip application specific functions such a timers i o registers UART general purpose registers etc The non G Buss instructions are of four classes Transfer Instructions Memory Access Instructions ALU Instructions Register Instructions CO N02 nL CO JUMP CALL JZ and JNC instructions must appear in Slot0 of a program word ie bits 23 18 The last 18 bits 17 0 contain the address inside the current 256K
48. d delta the length of the parsed word It is a very ong word with many nested and interlaced structures It is a hallenge even to the very experienced Forth programmers aramat CRR Parsing CRR parse b u c b u delta lt string gt P24 MISC Processor Manual 48 STEREO CIT 005 A tmp OVER gt R DUP bu u IF 1 tmp BL IF bu skip FOR BL OVER 0 lt NOT WHILE 1 b R gt DROP 0 LIT DUP EXIT all delim EN R gt ER SWAP b b u scan p OVER tmp BL THEN WHILE 1 J R gt DROP DUP 1 gt R OVER R gt R gt EXIT THEN ER R gt PARSI bu lt string gt gt R TIB gt IN TIB gt IN R gt parse gt IN TOKEN a lt string gt BL PARSE 1F LIT MIN 2DUP DUP TEXT TEXT 1 SWAP CMOV HERE 1 PACKS WORD c a lt string gt PARSE HERE 1 PACKS tut Du DI 8 8 Dictionary Search find follows the linked list in the dictionary and compares the names of each compiled word with the packed string stored at a va points to the starting name field of the dictionary If a match is found it returns the execution address code field address and the name field address of the matching word in the dictionary If it failed to find a match it
49. different from the instruction in Forth which uses the address on the top of the data stack in the T register eecece CCCCCC 001101 CCCCCC 14 CECCCE cccccc cccccc 001101 STEREO CIT 005 A Pop the number off the data stack and store it into the memory location whose 24 bit address is in Register A The address in the A register is then incremented to facilitate the next memory access It is most useful in storing values to a table in the memory This store instruction is different from the instruction in Forth which uses the address on the top of the data stack Coding Example See the copying program shown in LDP ST Code OF Usage 001111 cccccc ceecce ccecce ecocce O0lITTLI ccocec cecece ecocce cococc 001111 cescce ec ecce coccceG ceccec 001111 Stack Effects C roe 2 Carry no change Function Pop the number off the data stack and store it into the memory location whose 24 bit address is in Register A The address in the A register is not modified This store instruction is different from the instruction in Forth which uses the address on the top of the data stack Coding Example CODE na sta st ret RR8 Code 08 Usage 001000 cccccc ccecccce cccccc cocca 001100 docce ceeece ccecce ccecce O0IT00 cocccco eccece cccecce Ccccccc 001000 Stack Effects nb n2 Carry no change Function All 24 bits in the T register are rotated right by 8 b
50. e Compiler CRR PUNIQUE a a DUP NAME IF TEXT COUNT TYPE THEN DROP S a 2 DUP IF UNIQU na DUP na DUP na 1 la CONTEXT SWAP ERROR CRR SLIT reDef G Ld DUP NAME CP LAST for OVERT anaa EXIT THEN 8 12 Compiler SCOMPI E compil stream is found immediate If a matc a number If not su RR FORT SCOMPILE NAME DU IF 800 ee Qa Za E AZ m It searches the dictionary for this word es the word just parsed out of the input If a match compiles it word h is not found in the dictionary unless the word is marked as an An immediate word is executed by the compil convert the word ler into If successful the number is compile as a literal ccessful exit with ERROR H Compiler CRR fe ode 4 D 000 LIT AND IF EXEC UTE P24 MISC Processor Manual 52 STEREO CIT 005 A ELSE 3FFFF LIT AND 100000 LIT OR THEN EXIT HEN DROP TEXT NUMBER IF LITERAL EXIT HEN ERROR OVERT LAST CONTEXT RA emi 5E79E LIT OVERT IMMEDIATE Ge th COMPILE gt body forth LIT for i lt string gt TOKEN n 8 13 Debugging Tools CRR Tools CRR Ta OM li der eb OVER 7 LIT U R SPAC FOR AFT DUP 7 LIT U R
51. e cocco ececeo 011010 cGcocec cocccc P24 MISC Processor Manual 22 STEREO CIT 005 A CEccce ccoeoc 011010 ccecee ececce ceococc ceecec 011010 Stack Effects n n n Carry unchanged Function Duplicate T register and push it on the data stack Coding Example Decrement T dup dup xor com add now use zero com add OVER Code 1B Usage OlTOTIl cccecc cec cecec ceccce ececce 01LOLI cecce ecocce eccece ccecce 011011 c cece cecece ccecce Occccc OITOTI Stack Effects nl n2 n1 n2 n1 Carry unchanged Function S is transferred into T register The original contents in the T register is pushed onto the data stack Coding Example CODE 2DUP nl n2 nl n2 nl n2 over over ret PUSH Code 1C Usage 011100 ccoccoc ccecce Cccc ceococc OITITIO0O0 cGocccec CETO ecccce cecece 011100 Ecce eccece Ccccccc cccccc 011100 Stack Effects un co wc Re GT Carry unchanged Function Pop S on the data stack and store it to the T register The original contents in the T register is pushed onto the return stack Coding Example P24 MISC Processor Manual 23 STEREO CIT 005 A CODE ROT push pus pop STA Code Usage Stack Carry Functi the A into m Coding COD tj NOP Code Usage Stack Carry Functi No operation the next word to be fetched and executed SHOULD Coding DROP Code
52. e design from software development so that hardware and software can be developed simultaneously This P24 simulator served well in the process of building the P24 CPU and the eForth system which proves that the hardware software system works correctly This P24 simulator faithfully replicates the logic behavior of the P24 CPU on a cycle by cycle basis As the P24 CPU is composed of a set of registers and two Stacks and the registers and stacks acquire new contents only on the rising edge of the master clock it is very simple to emulate this behavior Each register and each level in the two stacks are represented by two 32 bit words The first word contains the current value of the register and the Second word contains the value to be latched into the register on the next rising edge of the master clock This simple mechanism very conveniently replicates the behavior of a synchronously clocked flip flops and forms the basis of the P24 simulator Two large arrays are opened to host these 32 bit word sets The FROM array contains the current values of all the registers and all the stack levels and the TO array contains the new values to be stored into the registers and stacks on the next clock The rising edge of the clock forces th ntire TO array to be copied into the FROM array and these is functionally one machine cycle Th multiplexers in P24 are replaced by Forth words which perform the logic
53. er This ASM24 F file contains a Structured Optimized Assembler for P24 CPU It packs up to four machine instructions into one 24 bit program word It also builds structures similar to those in high level Forth The structures are build in a single pass without labels P24 eForth adopts the Subroutine Thread Model in which the colon words contain lists of subroutine calls instead of lists of addresses Using this model the assembler assumes the duties of the compiler Another advantage of the Subroutine Thread Model is that machine instructions can be assembled in lin with the colon words Deal Assembly Tools Put all the assembly words and words in the P24 target into the ASM24 vocabulary ONLY FORTH ALSO ASM24 ASM24 DEFINITIONS H points to the next free location in the target image to receive new code or data LOC marks a target location to be reference later It is not used in the P24 system VARIABLE H LOC CONSTANT DOES 8 H UA SZ ERE MC LASTH contains the link field address of the last word to build the linked list of Forth words variable lastH 0 lastH init linkfield address lfa NAMER stored n into the next location in target It was useful if you want to assemble names in a separated names dictionary nameR n H RAM store double to code buffer 1H bump nameH COMPILE ONLY marks the current w
54. ficant bit in T T 0 is shifted to a flip flop whose output is connected to the serial output port At the same time the state of the serial input port is latched into the carry bit which is bit T 24 Repeating SHR 8 times a character is sent out One character is captured by waiting for the start bit on the serial input port and then test the port at the intervals of 100 us One must be very careful in using the SHR instruction In order not to disturb the output port you should always set T 0 to a 1 before executing SHR This way the serial output port stays at the mark level BOO ET M T S ONE QE EE DI o CRR Chararter IO CRR CODE 50us 2 ldi skip 100us 1 ldi then sta 138 ldi begin lda add until drop ret CODE EMIT c td bi CODI P24 MISC Processor Manual 42 STEREO CIT 005 A S7F ldi and shl SFFFFO1 ldi xor SOA ldi FOR shr 100us NEXT drop ret CODE KEY amp 8 SFFFFFF ldi begin shr until repeat wait for start bit 50us 7 ldi FOR 100us shr if 80 ldi xor then NEXT SFF ldi and 100us ret 2 Simple Utility Words These common functions are too complicated to code in machine instructions and are left in the high level form CRR Common functions CRR U lt uu t 2DUP XOR 0 lt IF SWAP DROP 0 lt EXIT THEN 0 lt lt nn t 2DUP XOR 0 lt IF DROP 0 lt EXIT THEN
55. functions and update values in the TO array P24 MISC Processor Manual 56 STEREO CIT 005 A Th ex bi to 29 gi Th an ac ac simulator runs identically to the actual P24 computer in place of a real P24 computer fo Th WO ON OA A AAA ZA 424 ZZ r3 F a 15 1 VA VA VA PE EE EO E Lu E P24 MISC Processor Manual tructions in this word word from memory and sequences the is simulated by a 32 3 bit in this counter steps through slots 0 3 bit field is cleared to zero and the upper th e Slot Machine which fetches a program ecution of the four machine ins t counter The less significant 4 in 5 clock cycles Then this bit counter is incremented Therefore ves an accurate program word count e most interesting feature of t d EMIT function to the equivale tually run P24 eForth interactively tual P24 computer would do on a terminal r software development e simulator code is in SIM24 F rds The Registers and the Stacks Put all simulator words in SIM24 vocabul from words of the same names in the FORI LY FORTH ALSO SIM24 DEFINITIONS Stacks are limited to 16 levels Program are limited to 32KB C he SLOT fiel our instructions in the program word REGISTER REAK breakpoint address EGIST d B R I TO forces accessing registers in the TO CIMAL
56. g LASTH and then packs the name count and name into the name field three bytes per word MAKEHEAD builds a header while retains the word pointer so that the name string is still available to be printed makeHead anew 20 word get name of new definition lastH 8 nameR fill link field of last word H lastH save nfa in lastH forthdup c B store count count 0 do count B fill name field loop forthdrop anew makeHead gt IN 8 gt R P24 MISC Processor Manual save int 35 erpreter pointer STEREO CIT 005 A makeHead R gt gt IN restore word pointer SLIT packs a counted string into the next available space in the target image thr bytes to a word 2 SEIT anew 22 WORD forthDUP c B compile count count 0 DO count B compile characters LOOP forthDROP anew builds a new subroutine in the target without a header CODE builds a new code word in the target with a header 1 builds a new colon word in the target with a header As we are using the Subroutine Thread Model is the same as CODE and colon words shared all the structure building tools with code words Saf begin head CONSTANT DOES gt call CODE makeHead CODE Chapter 6 The P24 Kernel The KERN24 F file contains most of the words which are written in assembly for speed considerations P24 eForth is optimized as all the words which can be
57. i dictionary code pointer 708 ldi ptr to last name compiled P24 MISC Processor Manual 37 chars in the input buffer H S gt IN offset to the text string currently being interpreted points to SINTERPRET or COMPILE to evaluate words STEREO CIT 005 A 8 O24 2 24 2 A OT OO OO OO sa 6 P24 MISC Processor Manual EVAL 709 ldi ABORT 70A ldi TEXT 710 ldi tmp 70B ldi unpack buffer 2 Assembly Macros for Code Optimizing interpret compile vector ptr to converted string Many Forth words have corresponding P24 machine instructions or can be represented by a short sequence of P24 machine instructions Instead of representing t they are defined as macros which invok hem in subroutines the assembler mneumonics to pack as many machine instr words Obviously four machine instrucitons there are gai Howev if a Forth words can be translated to less uctions to program sizes and faster execution speed significant gains when a Forth word is defined as a 4 instruction macro because it may contin the previous word to the next word These macros together with the machine i DUP DROP AND XOR tend to pack the code tightly macro words CR EXIT ret EXECUTE a push ret ma sta st a n sta ld R n pop RE n pop dup push gt R n push SWAP nl n2 n2 nl push sta pop lda OVER nl
58. in the current 256K page of memory It does not cross page boundaries Coding Example All Forth words are compiled as subroutine calls This is the most efficient way to build lists in Forth NEXT Code 5 Usage 000101 aaaaaa aaaaaa aaaaaa Stack Effects Cria Carry no change Function If R is non zero jump to the 18 bit address in the bit field 17 0 in the current 256K word page of memory and post decrement R If R is zero pop R It must be in slot 0 of a word Coding Example FUN n FOR RQ NEXT prints the numbers 0 through n in reverse order P24 MISC Processor Manual 11 STEREO CIT 005 A TIMES Code 6 Usage 000110 eccece ccccce ccccce cccccc 000110 cccccc cccccc ecccce ccecccce 000110 cecccc ecccce cecece cccccce V00LI10 Stack Effects 3 Carry no change Function If R is non zero jump back to the beginning of the current instruction word and post decrement R If R is zero pop R Coding Example CODE LSHIFT nl n2 n1 2 n2 zero com add push subtract one from n2 and push to R shl times ret shift nl left n2 times then return RTI Code 7 Usage 000111 XXXXXX XXXXXX XXXXXX cccccc 000111 xxxxxx xxxxxx Ccccccc cccccc 000111 xxxxxx cecco Gecece ececoc O00TIT Stack Effects eL oS Ride Carry no change Function Pop the address of the top of the return stack into the program counter P to resume execution at completion of a
59. its The least significant byte of T moves to the position of the most significant byte Useful for fast accessing of byte data and data formatting packing P24 MISC Processor Manual 15 STEREO CIT 005 A Coding Example BYTE nl n2 n3 n3 is byte number n2 of nl for DUP n2 expected equal 0 10r 2 IF zero com add push rr8 times THEN FF and NIP Code 0C Usage 001100 cccccc ccecce coccec eccocce 001100 ceecee ceccce ecccce Gece 001100 cecece eccece CCcCCCC Cccccc 001100 Stack Effects CAL mn a Ze Carry no change Function Pop S leaving T unchanged Coding Example You hopefully never need this one A good candidate for replacement with something more useful Suggest not using COM Code 10 Usage 010000 cccccc ccecce cccccc cccccc 010000 cccccc cccccc eccocc ecccco 010000 ccccce CCCCCC CCCCCC cceccecc 010000 Stack Effects mb Carry no change Function Complement all 24 bits in the T register This is a one s complement operation Coding Example To generate a 1 in T register zero com OR has to be synthesized from COM and AND using A or B not not A and not B CODE OR nn n this looks pretty awkward maybe P24 MISC Processor Manual 16 STEREO CIT 005 A com push com the last available opcode or NIP pop and com ret should be replaced with OR SHL Code 11 Usage 010001 cccccc ccccce ccccce
60. le based simulator to exercise code in the P24 target VOCABULARY ASM24 VOCABULARY SIM24 following are tools words added to the baseline Forth system ONLY FORTH ALSO DEFINITIONS turn off the warnings normally supplied by Win32Forth on duplicated names and stack changes They clutter the symbol table HEX WARNING OFF NOOP IS STACK CHECK type debugging on and you can pace the meta compiler by hitting SPACE for the next steps Hit RET to stop This is useful when you want to locate errors before a full compilation variable debugging debugging off Pe Oe LES P24 MISC Processor Manual 28 STEREO CIT 005 A CI aE Qa tttm et LAO 4 A HEAD prints teh name of a new word to be compiled head addr addr gt IN 20 word count type space gt IN dup CR is redefined so you can step through the compilation by setting debuggin on CR CR debugging Q if s KEY OD abort done then Here is a group of Forth words which clash with words in the target You can use the aliases to ensure that you still has the behavior of the original Forth words alias forth dup alias forthDUP drop alias forthDROP over alias forthOVER swap alias forthSWAP alias forth alias forth and alias forthAND alias forth alias forth word alias forthWORD CR alias
61. mented ST pops a word from T and stores it to memory Address of word is in A COM compliments T ones compliment SHL left shifts T by one bit SHR right shifts T by one bit Arithmetic right shift MUL multiply step XOR pops data stack and XORs it to T AND pops data stack and ANDs it to T DIV divide step ADD pops data stack and ADDs it to T POP pushes T on data stack and pops return stack to T LDA pushes T on data stack and copy A to T DUP pushes T on data stack PUSH pushes T on return stack and pops data stack to T STA Copies T to A and pops data stack to T DROP pops data stack to T 41041 INST ret 249249 INST lap 2CB2CB INST ld 34D34D INST stp 3CF3CF INST st 410410 INST com 451451 INST shl 492492 INST shr 4D34D3 INST mul 514514 INST xor 555555 INST and 596596 INST div 5D75D7 INST add 618618 INST pop 659659 INST lda 69A69A INST dup 71C71C INST push 75D75D INST sta 79E79E INST nop 7DF7DF INST drop 5 4 Miscellaneous Assembly Tools POPS alias of DROP useful after high level DROP is defined PUSHS alias of DUP useful after high level DUP is defined ro i e pops drop ushs dup LJUMP a long jump to a 24 bit address Pushes the address on the return stack and then execute RET ljump body 8 ldi get address of target word push ret long jump MAKEHEAD builds a header for a new word First builds the link field usin
62. n interrupt service routine Re enables slot4 interrupt servicing This instruction can be placed in any slot of a word The instructions before RTI are executed The instructions following return are ignored Coding Example RCV 1 ASSIGN uart receive interrupt service routine see multi3 file lda IF 1 ELSE 0 THEN save A and carry on data stk G1 RCVFULL IF DROP ELSE RCV THEN service interrupt WAKE OPERATOR service interrupt shl drop sta rti restore carry and A then rti P24 MISC Processor Manual 12 STEREO CIT 005 A LDP Code 9 Usage 001001 ccccccc cccecccc cccecce coeccecc 001001 cccccce eccccec eccecce ececece 001001 cceccec eeccocc eececec ccccecc 001001 Stack Effects Sam Carry no change Function Fetch the contents of a memory location whose 24 bit address is in the A register and push that number onto the data stack The address in the A register is then incremented to facilitate accessing the next memory It is most useful in reading values from a table in the memory This fetch instruction is different from the instruction in Forth which uses the address on the top of the data stack This instruction also resets the carry flag Bit 24 in the T register Coding Example Increment T sta ldp drop lda Otherwise eccece cecece radi add 000000 000000 000000 000001 costs 6 slots
63. n lda add until drop ret SKIP makes an unconditional jump to with 100us RET 7 Code 1 Usage 000001 xxxxx ecccce 00000 ecco Gceed eccecc Cace Stack Effects fp RY a Carry no change Function Pop the address of the top of the re and JNC See also RET THEN to let 50us sharing the delay loop X XXXXXX XXXXXX 1 XXXXXX XXXXXX c 000001 xxxxxx c cccccc 000001 Sar turn stack into the program counter P thus resume th xecution sequence interrupted by the last CALL instruction Besides terminating a subroutine this instr a location outside of the current me uction may be used to effect a long jump to mory page This instruction can be placed in any slot of a word The instructions before return are executed The instructio Coding Example In the subroutine thread model RET colon words The Forth word simpl P24 MISC Processor Manual ns following return are ignored is used to terminate all code words and y compiles a RET to end a Forth word STEREO CIT 005 A JZ IF WHILE UNTIL Code 2 Usage 000010 aaaaaa aaaaaa aaaaaa Stack Effects AR eu Carry no change Function Conditionally jump to the 18 bit address in the bit field 17 0 in the current 256K word page of memory if the T register contains a 0 It must be in slot 0 of a word The T register is destroyed and the data stack is popped back to T This ins tr
64. ndergoing modifications and enhancements Check with eMAST Technolgoy or Offete Enterpries for latest updates P24 MISC Processor Manual 62
65. ord so it can only be compiled in a colon word It cannot b xecuted interactively IMMEDIATE marks the current word so it will be executed in a colon word All structure building words are so marked compile only 400000 lastH RAM OR lastH RAM immediate 800000 lastH RAM OR lastH RAM RR Derived from Chuck Moore s P21 20 bit assembler HI selects one of four masks to assemble a machine instruction into one of the four slots in a 24 bit program word HW points to the program word into which new machine instructions are to be assembled H may advance from HW as literal values ee ae eR E a P24 MISC Processor Manual 32 STEREO CIT 005 A are assembled following the program word BI points to one of the 3 bytes in a 24 bit program word It allows the assembler to pack 3 ASCII characters into one word VARIABLE Hi VARIABLE Hw VARIABLE Bi for packing ALIGN forces the next instruction to be assembled into the next word ORG a changes H to a to start assembling at a new location ALIGN 10 Hi ORG DUP CR He ALIGN MASK contains four mask patterns to assemble a machine instruction into one 6 bit slot of a program word The mask is selected by HI NV n assembles n into the next free location pointed by H Advance H afterwards W n assembles a machine instruction to the next free slot in the current program
66. p drop ret CRR CODE add ret CODE NOT com ret CODE NEGATE com 1 ldi add ret CODE 1 1 ldi add ret CODE 1 1 ldi add ret CRR CODE BL 20 ldi ret CODE sta ld add st ret CODE com add 1 ldi add ret CRR CODE DUP dup ret P24 MISC Processor Manual 55 STEREO CIT 005 A CODE DROP drop ret CODE AND and ret CODE XOR xor ret CODE COM com ret 8 17 Final System Words CRR ABORT string COMPILE abort IMMEDIATE string COMPILE IMMEDIATE lt string gt COMPILE IMMEDIATE CODE lt string gt TOKEN n OVERT CREATE lt string gt CODE doVAR VARIABLE string CREATE 0 LIT CRR 29 LIT PARSE TYPE IMMEDIATE 7 TIB gt IN IMMEDIATE 29 LIT PARSE 2DROP IMMEDIATE IMMEDIATE 800000 LIT LAST OR LAST CRR Chapter 9 P24 Cycle Based Simulator An accurate and fast logic simulator is extremely valuable in the design and testing of a new CPU It is also very useful in separating the hardwar
67. pports a powerful embedded Forth system ystem This simple UART was very valuable in bringing up the ACTEL mplementation but is no longer used a S i C E d S T r a t i required by eForth ss the resources pr to control and to pr hapter 3 P24 Instruction Set 1 Instructions on the S preserved tched onto the This very P24 core As this simple ovided by P24 ogram the P24 he P24 instruction set can be best explained using the register and data flow and 2 The T register is the center of the ALU which takes data from the T and S registers and routes the results back to the T egister The contents of T can be moved to the A register pushe iagram as shown in Figures 1 Register A holds a memory address he T register or write the data in T register to external memory n A can be auto incremented memory P24 MISC Processor Manual tack S and pushed on the return stack S d on the data he T register connects the data stack and the return stack as a large shift egister Data can be shifted towards the return stack by the PUSH instruction nd shifted towards the data stack by the POP instruction which is used to read data from memory into The address so that P24 can conveniently access data arrays in STEREO CIT 005 A P is the program counter and it holds the address of the next instruction to be fetched from the memory After an instruction is fet
68. put stream It searches the dictionary for this word If a match is found executes it unless the word is marked as a compile only word It a match is now found in the dictionary convert the word into a number If successful the number is left on the data stack If not successful exit with ERROR CRR Interpret CRR SINTERPRET a NAME DUP IF 400000 LIT AND ABORT SLIT compile only EXECUTE EXIT HEN DROP TEXT NUMBER IF EXIT THEN ERROR Le forth SINTERPRET gt body forth LIT EVAL IMMEDIATE OK forth SINTERPRET gt body forth LIT Eri VAL P24 MISC Processor Manual 51 STEREO CIT 005 A IF SLIT OK CR THEN EVAL BEGIN TOKEN DUP WHILE EVAL EXECUTE STACK REPEAT DROP OK CRR Shell CRR QUIT TIB 730 LIT TIB BEGIN QUERY EVAL AGAIN Compiler Primitives fo 2 SSX TOKEN NAME IF ERROR ALLOT n w HERE DUP 1 CP COMPILE string 100000 LIT OR IMMEDIATE CRR CRR EXIT THEN GPL ws CRR COMPILE R gt DUP LITERAL 29E79E LIT IMMEDIATE CHAR 22 LIT WORD 8 1 ALLOT 1 gt R r Nam
69. ress 0 is defined as follows BitO0 lsb r w global interrupt enable 1 to enable Bitl r w enable for interrupt 0 highest priority Bit2 r w enable for interrupt 1 Bit3 r w enable for interrupt 2 Bit4 r w enable for interrupt 3 Bit 5 r w enable for interrupt 4 Bit 6 r w enable for interrupt 5 Bit7 r w enable for interrupt 6 Bits8 15 not used read as 0 Bitl6 Tr status of interrupt line 0 Bitl7 r status of interrupt line 1 Bit18 r status of interrupt line 2 Bit19 status of interrupt line 3 Bit20 f status of interrupt line 4 Bit21 ie status of interrupt line 5 Bit22 r status of interrupt line 6 Bit23 r logical OR of enabled interrupt lines The interrupt enable bits are all initialized to 0 by power on reset Note that after performing an interrupt the interrupt controller will without clearing bit 0 disable further interrupt servicing until after the next RTI instruction is executed Interrupt lines 0 and 1 are currently dedicated to the UART receive and transmit functions respectively Interrupt line 0 is set after a character is received by the UART and is cleared by reading the data at Gbuss address 1 least significant byte Interrupt line 1 is set after the UART has completed a character transmission and is cleared by writing a character to Gbuss address 1 least significant byte An example of the programming of the UART for interrupt driven i o is in file multi3 f Examples of polled i o are the KEY and EMIT words
70. return as a count which is seful when this word is the first word of a packed string B is called by UNPACKS to convert a packed string to a ounted byte string EB ba btla push sta ldp push lda pop pop sta ld shl shl shl shl shl shl shl sh add st lda ret push sta ldp push lda pop pop atl n b dup push SFF ldi and pop SFFFF00 ldi and FF ldi xor shr shr shr shr shr shr shr shr P24 MISC Processor Manual pack B and unpack gt B strings E gt B ab atl b 3 count 40 STEREO CIT 005 A dup push SFF ldi SFFFFOO shr shr shr shr SFF ldi stp stp lda pop and ldi shr shr and stp ret po sh sh Chapter 7 P T E atl dup push Cc High Level Words i and SFF ldi xor n P24 eForth The file EF24 F contains all the high level words in P24 eForth This implementation follows closely the eForth model The following set of words are removed because they are not absolutely necessary for embedded applications In this implementation the size constrain is severe and th xistence of every word must be justified rigorously Words removed from the eForth model CATCH THROW PRESET XIO FILE HAND I O CONSOLE RECURSE USER VER HI BOOT Most of the user variables are eliminated SPO RPO KEY EMIT EXPECT TAP
71. rs LOOP forthDROP 77 terminates a high level colon word with a ret WAIT pauses the execution Restart by any key This is a cheap breakpoint mechanism now replaced by the simulator EXIT alias NV WAIT alias debugger CREATE builds a new array word doVAR returns the array address VARIABLE builds a variable in P24 target CREATE makeHead begin head CONSTANT doVAR DOES forth call VARIABLE CREATE 0 won Ready to compile the high level portion of the P24 eForth CR include eforth24 include ef24 Compile Forth words used as macros in assembler but now needed so the Forth interpreter and compiler have access to these functions CR include k24 4 4 Boot Code Build the boot code starting at location 0 This piece of code initializes the variables in RAM memory and then jumps to COLD 0 ORG 10 LIT 704 LIT 6 LIT forth COLD gt body forth LIT push push anew H forth push sta ldp push lda pop pop sta stp lda next pops pops ret V Build the table of initial values for the variables to be copied to RAM memory on booting 10 ORG 730 OA 4 lastH forth 4 780 lastH forth 4 forth SINTERPRET gt body forth forth QUIT gt body forth P24 MISC Processor Manual 31 STEREO CIT 005 A Chapter 5 The Optimizing P24 Assembl
72. s CR D display next 8 words CR addr M display 128 words from addr CR addr P start execution at addr CR addr G run and stop at addr CR RUN execute one key per cycle CRA 92 6 Simulating Running Forth System The simulator is the most effective in debugging short sequences of program words to verify that the sequences ar xecuted correctly After the P24 machine instructions are verified one can use the G command to execute a long stretch of program and break only at specific locations This allows large segment of programs to be tested The simulator can run eForth system if KEY and EMIT are vectored to the keyboard input and screen display in Windows This is accomplished by defining two new P24 MISC Processor Manual 61 STEREO CIT 005 A machine instructions GET and PUT with the proper Windows interface GET and PUT is then patched into KEY and EMIT in the target memory Now executing 800 G will start the P24 eForth running because 800 is a location it will never reach In the meantime the user can interact with the eForth in the simulator like using any other eForth system It is possible to build this simulator into a full P24 program development System by vectoring input streams from text files maintained under Windows This however will have to wait in the next revision of the simulator patch KEY and EMIT to run eForth interactively 180000 B7 RAM 1C00
73. so allows the user to display numbers in any reasonable base like decimal hexidecimal octal and binary among other non conventional bases CRR Numeric Output CRR single precision fi DIGIT Mi 9 LIT OVER lt 7 LIT AND CHAR 0 30 GIT 77 EXTRACT n base n c O LIT SWAP UM MOD SWAP DIGIT PAD HLD HOLD c HLD 1 DUP HID u u BASE EXTRACT HOLD sins S u 0 BEGIN DUP WHILE REPEAT CRR SIGN n 0 lt IF CHAR 2D LIT HOLD THEN gt w b u DROP HLD PAD OVER str n b u DUP gt R ABS S R gt SIGN gt HEX 10 LIT BASE DECIMAL OA LIT BASE 8 7 Number Input Words Numbers ar ntered into P24 as strings of digits delimited by spaces and other white characters like CR TAB NUL etc Numeric strings are converted to internal binary form by multiply the digits most significant digit first by the value in BASE and accumulate the product until the digits are exhausted NUMBER does the conversion It allows a leading to indicate that the numeric string is in hexidecimal It also allows a leading sign for negative numbers CRR Pd adi n cd ge 9 or UO Numeric Input DIGIT c base gt R CHAR 0 30 LIT 9 LIT OVER lt IF 7 LIT DUP 0A CRR single precision ut LIT OR THEN DUP R gt U NUMBER a nT a F BASE
74. uction is different from JNC which does not pop the data stack and removes Coding Example CODE DUP w ww 0 dup if dup ret then ret JNC UNTIL IF WHILE Code 3 Usage 000011 aaaaaa aaaaaa aaaaaa Stack Effects n n Carry no change Function Conditionally jump to the 18 bit address in the bit field 17 0 in the current 256 in The fro K word page of memory if the Carry flag Bit 24 of T is reset It must be slot 0 of a word register and the data stack are preserved This instruction is different m the instructions JZ which pop the data stack and removes T Coding Example To JNC COD test the negative flag T 23 it is shifted into carry T 24 and tested using compiled by IF E ABS n n dup shl if drop com 1 ldi add ret then P24 MISC Processor Manual 10 STEREO CIT 005 A drop ret CALL Code 4 Usage 000100 aaaaaa aaaaaa aaaaaa Stack Effects met RURSUS Carry no change Function Call a subroutine whose address is in the bit field 17 0 in the current 256K word page of memory It must be in slot 0 of a word The address of the next word is pushed on the return stack When a return instruction in the subroutine is encountered this address is popped off the return stack and the next word is executed to resume the interrupted execution sequence Restriction This instruction allows the program to call to any subroutine with
75. uctions can be in any of the four slots When th nstructions are executed slot5 will be forced into the next slot and the next nterrupt is pending an extra nterrupt vector is placed in ddress 1 int2 to address 2 ssigned to the UART receive f slot slot4 unction assigned to the UART transmit function e execution of an RTI instructio h When executing a right shift i B U S t xecution of slot4 servicing ighest priority pending interrupt if nstruction words will be fetched and then executed wo are used Int0 ve he ACTEL implementation contains a prioritized interrupt controller If an is added to the sequence following lot3 During slot4 the program counter is pushed to return stack and the the program counter Currently 7 int ted and only t etc The highest priority int0 is currently errupt lines GboOrs to while the next highest priority intl is Once an interrupt is serviced via n Immediately a any wi nstruction SHR its T 23 1 are shifted to the right by one ART OUT pin and UART IN pin is latched into imple mechanism allows a simple RS232 serial devic of interrupts is automatically disabled until the fter the RTI executi ll be serviced the sign bit T 23 i bit Bit T 0 is la the carry bit T 24 port to be built in he serial port is the only p ripheral serial port opens a window for the user to acc nd su
76. umented by comments in the ile multi3 f In addition some words were added in meta24i f to facilitate rom burning etc see prom and image The details of the boot method have hanged Presently booting can occur from EEPROM or serially To be documented later Changes near th nd of meta24i f relate to booting WRC Metacompiler is a term used by Forth programmers to describe the process of building a new Forth system on an existing Forth system The new Forth system may run on the same platform as the old Forth system It may be targeted to a new platform or to a new CPU The new Forth system may share a large portion of the Forth code with the old system and hence the term metacompilation In a sense a metacompiler is very similar to a conventional cross assembler compiler The P24 eForth metacompiler is contained in the source code file META24 F which runs under Win32Forth a public domain Forth for Windows 95 98 2000 NT It calls on the following files to build the P24 eForth system ASM24 F P24 assembler KERN24 F Kernel words in P24 eForth EF24 F High level words in P24 eForth K24 F Words to replace assembly macros In this chapter I take the source code in META24 F and explain the functions of the Forth words which build the eForth system 4 1 Start Up the Metacompiler Copyrighted by eMAST Technology Corp 2000 All rights reserved P24 MISC Processor Manual 27
77. word page They can access code within the current page To reach other pages of memory you will have to push a 24 bit address on the return stack and execute the RET instruction The transfer instructions thus has the following forms JUMP aaaaaa aaaaaa aaaaaa CALL aaaaaa aaaaaa aaaaaa JZ aaaaaa aaaaaa aaaaaa JNC aaaaaa aaaaaa aaaaaa The conditional jump instruction JZ is used to implement the IF WHILE and UNTIL words in Forth in that it does pop the number being tested in T The conditional jump instruction JNC causes a jump if the carry bit T 24 is cleared It is useful in multiple precision math operations JNC does not pop the T register so its contents can be tested again Table 1 P24 Machine Code Code Name Function Transfer Instructions 00 JUMP Jump to 18 bit address Must in Slot0 01 RET Subroutine return G P24 MISC Processor Manual 7 STEREO CIT 005 A 02 JZ 03 JNC 04 CALL 05 NEXT 06 TIMES 07 RTI Memory 09 LDP 0A LDI 0B LD OD STP OF ST ALU Instructions Jump if T is 0 Must in Slot0 Jump if carry is reset Must in Slot0 Call subroutine Must in Slot0 Jump if R is not 0 Post decrement R Pops R if R is 0 Must be in Slot0 Repeat instruction word if R is not 0 Pops R if R is 0 Return from interrupt Access Instructions memory at A to Push Push Push Pop Pop in line literal memory at A to
78. word pointed to by HW I n assembles a machine instruction It the current word is full assemble the instruction into the next word NV B 0c packs a character c into the current word Uses BI to determine the character postion in a 24 bit word Pack it to the next word if the current word is full CREATE mask FC0000 3F000 FCO 3E FFFFFF AND H RAM 1H4 QW Hw RAM OR FFFFFF AND Hw RAM QI Hi 10 AND IF O Hi H Hw 0 THEN Hi mask AND w 4 Hi B c Bi 0 IF 1 Bi HG Hw O 10000 w EXIT THEN Bi 1 IF 2 Bi 100 w EXIT THEN Q Br f yw 922 Transfer Instruction Assembler INST A defining word to define a single slot machine instruction When the machine instruction word is executed it assembles the desired machine instruction into the current program word If the current word is full start a new program word The constant contained in the machine instruction word has four identical machine code patterns in the four slots so that the word I can select one of them and add it to the current program word NOP machine instruction word has 1E in all four slots They make up the 24 bit pattern 79E79E INST CONSTANT DOES 8 _ I E79E INST nop DM up p A a N WO ANEW starts a new program word by filling the current word with NOPs It is required when we have to assemble a 4 slot i a

STEREO-CIT-005.A P24 MISC Processor Manual 1 P24 MISC

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