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1. A G Recommended PCB Land Pattern Dimensions Symbol Description A e Lead pitch 0 5 mm X Pad width 0 25 mm y Pad length See Note 2 0 mm A 7 75 mm G 9 0 mm Note The y dimension has been elongated to allow for hand soldering and reworking Production assembly may allow this dimension to be reduced as long as the G dimension is maintained Rev 1 1 99 78 6612 Data Sheet DS 6612 001 6 2 68 QFN Package 6 2 1 Pinout 588 e aa lt lt g POE a 3 Bz os 4 5 2 55 lt 52096 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 GNDD 1 510 RESET E_RXTX SEG38 2 500 V2P5 TX1 DIO2 3 49 VBAT TMUXOUT 4 DIO3 5 47 SEG40 DIO20 6 46 SEG31 DIO11 SEG3 7 450 SEG30 DIO10 V3P3D 8 TERIDI AN 44 SEG29 DIO9 CKTEST SEG19 9 SEG28 DIO8 V3P3SYS 110 78M661 2 IM 42 SEG27 DIO7 SEG4 11 41 SEG26 DIO6 SEG5 112 40 SEG25 DIO5 SEG37 DIO17 113 39 SEG24 DIO4 COMO 114 38 ICE E COMI 115 37 SEG18 COM 16 3e SEG17 COMS 117 35 SEG16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 S5gzzoec 7o0588 7r 2222 60065 oonodaas aooodoiuluiuli uiu 3542 O nnn 0 Figure 43 68 QFN Pinout 100 Rev 1 1
2. Parameter Condition Min Typ Max Unit Recommended Input Range dE 250 550 21 Vin V3P3A peak Vin 200 mV peak Voltage to Current Crosstalk 65 Hz on VA 6 x 1 1 10 Verosstalk Vin ZVcrosstalk Verosstalk largest 9 Bor quB Vin measurement on or IB THD First 10 harmonics Vin 65 Hz 250 mV pk 64 kpts FFT Blackman 75 dB 20 mV pk Harris window 90 dB Input Impedance Vin 65 Hz 40 90 kQ Temperature coefficient of Input Vin 65 Hz 17 Impedance FIR_LEN 0 357 LSB size FIR_LEN 1 151 nV LSB 884736 FIR LEN 0 T Digital Full Scale FIR LEN A x im LSB ADC Gain Error vs Power Supply Variation Vin 200 mV pk 65 Hz 55 ppm 10 357nV IV y V3P3A 3 0V 3 6V 100AV3P3A 3 3 Input Offset 10 10 mV 5 4 13 UART1 Interface Parameter Condition Min Typ Max Unit TX1 VoH V3P3D TX1 ISOURCE 1 mA 0 4 V TX1 VOL ISINK 20 mA 0 7 V 5 4 14 Temperature Sensor Parameter Condition Min Typ Max Unit Nominal Sensitivity S 25 75 2180 LSB C FIR LEN 1 5 t Nominal relationship 10 Nominal N N T Sa T T N 1 0 LSB Temperature Error TA 40 C to 85 C o nn r 80 2 Tn 25 C 19 10 RT TLSB values do not include the 9 bit left shift at CE input is measured at T during calibration and is stored in MPU or CE for use in temperature calculations
3. TMUX 4 0 Mode Function 0 Analog DGND 1 Analog Reserved 2 Analog DGND 3 5 Analog Reserved 6 Analog VBIAS 7 Analog Not used 8 0x0F Reserved 0x10 0x13 Not used 0x14 Digital RTM Real time output from CE 0x15 Digital WDTR_EN Comparator 1 Output AND V1LT3 0x16 0x17 Not used 0x18 Digital RXD from Optical interface w optional inversion 0x19 Digital MUX SYNC 0 1 Digital CK_10M 10 MHz clock 0x1B Digital CK_MPU MPU clock 0 1 Reserved 0X1D Digital RTCLK output of the oscillator circuit nominally 32 786 Hz OX1E Digital CE BUSY busy interrupt generated by CE 396 us OX1F Digital XFER_BUSY transfer busy interrupt generated by CE nominally every 999 7 ms Rev 1 1 49 78 6612 Data Sheet DS 6612 001 2 Functional Description 2 1 Theory of Operation The energy delivered by a power source into a load can be expressed as E V t 1 t dt 0 Assuming phase angles are constant the following formulae apply for narrow band mode Real Energy Wh V A cos g t Reactive Energy VARh V A sing t S Apparent Energy VAh JP 0 For actual measurement equations refer to the applicable 78M6612 Firmware Description Document For a practical measurement not only voltage and current amplitudes but also phase angles and harmonic content may change constantly Thus simple RMS measurements are inherently inaccu
4. ausa 105 9 nc mie stamet ences Deren 106 10 Related Documentation esses nnmnnn nnn anseres 106 11 Contact Information iili aeui E 106 Revision FISTONY c 107 4 Rev 1 1 DS 6612 001 78M6612 Data Sheet Figures Figure 1 IC Functional Block 7 Figure 2 General Topology of a Chopped 10 Figure 3 AFE Block Diagrami iis 11 Figure 4 Samples from Multiplexer Cycle sss enne nnne nennen nnne 14 Figure 5 Accumulation Interval 11000 14 Figure 6 Interrupt Structure aada ec ev a co uada doe dee sua Roa 38 Figure 7 Optical Interface peccet cap ceto ca egre deep eoe 41 Figure 8 Connecting an External Load to 0200 00 enne 43 Figure 9 3 Wire Interface Write Command 7 0 46 Figure 10 3 Wire Interface Write Command 2 1 nnne nnns 47 Figure 11 3 Wire Interface Read 2 0 0 4 1 0 0
5. 78 6612 Data Sheet DS 6612 001 LCD19 2043 Not Used LCD SEGI9 3 0 LCD24 2048 Not Used LCD SEG24 3 0 iss 52 Not Used 2 LCD38 2056 Not Used LCD SEG38 3 0 LCD BLNK 205A LCD BLKMAPI9 3 0 LCD BLKMAPI8 3 0 RTM Probes RTMO RTMO RTMO RTMO RTM1 JRTM1 RTM1 RTM1 RTM2 RTM2 RTM2 RTM2 RTM3 RTM3 RTM3 Pulse Generator PLS_W PLS_ PLS_W PLS_W PLS 1 PLS 1 PLS 1 Only available on QFN 68 package Reserved in the LQFP 64 package 4 2 SFR Map SFRs Specific to Teridian 80515 Not Used bits are blacked out and contain no memory and are read by the MPU as zero Reserved bits are in use and should not be changed This table lists only the SFR registers that are not generic 8051 SFR registers Table 49 SFR Map In Numerical Order Name SFR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Digital I O DIO7 80 DIO 0 7 4 Port 0 DIO 0 3 DIO 0 2 1 Reserved 008 A2 DIO_DIRO 7 4 DIO DIRO 2 1 Reserved DIO9 90 DIO 1 7 6 Reserved DIO 1 3 0 Port 1 DIO10 91 DIO DIRI 7 6 Reserved DIO DIR1 3 0 01011 AO Not Used Not Used DIO_2 5 DIO_2 4 3 Reserved DIO 2 1 0 Port 2 DIO12 A1 Not Used Not Used uc a DIO DIR2 4 3 Reserved DIO DIR2 1 0 Interrupts and WD Timer INTBITS F8 INT6 INTS I
6. MSB LSB ESI Bit Symbol Function IEN2 0 ESI ES1 0 disable serial channel 1 interrupt Timer Counter Control Register TCON Table 27 The TCON Register MSB LSB TFI TRI TFO TRO IEI ITI ITO Bit Symbol Function TCON 7 1 Timer 1 overflow flag TCON 6 TRI Not used for interrupt control TCON 5 Timer 0 overflow flag TCON 4 TRO Not used for interrupt control TCON 3 IE External interrupt 1 flag TCON 2 ITI External interrupt 1 type control bit TCON I External interrupt 0 flag TCON 0 ITO External interrupt O type control bit Timer2 Counter2 Control Register T2CON Table 28 The 72CON Bit Functions Bit Symbol Function T2CON 7 Not used T2CON 6 I3FR Polarity control for INT3 0 falling edge 1 rising edge T2CON 5 I2FR Polarity control for INT3 0 falling edge 1 rising edge TCON 4 Not used T2CONI0 32 Rev 1 1 DS 6612 001 78M6612 Data Sheet Interrupt Request Register IRCON Table 29 The IRCON Register MSB LSB B EX6 IEX5 IEX4 IEX3 IEX2 Bit Symbol Function IRCON 7 IRCON 6 IRCON 5 IEX6 External interrupt 6 edge flag IRCON 4 IEX5 External interrupt 5 edge flag IRCON 3 IEX4 External interrupt 4 edge flag IRCON 2 IEX3 External interrupt 3 edge flag IRCON 1 IEX2 External interrupt 2 edge flag
7. MSB LSB SM SM21 RENI 81 81 Bit Symbol Function SICON 7 SM Sets the baud rate for UART1 SM Mode Description Baud Rate 0 A 9 bit UART variable 1 B 8 bit UART variable SICON 5 SM21 Enables the inter processor communication feature SICON 4 RENI If set enables serial reception Cleared by software to disable reception SICON 3 81 9 transmitted data bit in Mode A Set or cleared by the MPU depending on the function it performs parity check multiprocessor communication etc SICON 2 RB61 In Modes A and B it is the 9 data bit received In Mode B if M21 is 0 81 is the stop bit Must be cleared by software SICON 1 Transmit interrupt flag set by hardware after completion of a serial transfer Must be cleared by software SICON O RII Receive interrupt flag set by hardware after completion of a serial reception Must be cleared by software Rev 1 1 25 78 6612 Data Sheet DS 6612 001 1 4 7 Timers and Counters The 80515 has two 16 bit timer counter registers Timer 0 and Timer 1 These registers can be configured for counter or timer operations In timer mode the register is incremented every machine cycle meaning that it counts up after every 12 periods of the MPU clock signal In counter mode the register is incremented when the falling edge is observed at the corresponding input signal TO or T1 TO and T1 are the timer gating inputs
8. tne dealing tel de dae e de de eda 40 1 5 6 Opticalnterface noti ede e He He dE e He 41 15 7 Digitall O a de ce dt i LAE ee dts 42 1 5 8 LOD Drivers dn itt o awd t Hte E dg He m a RE Rt dag eed 44 1 5 9 Battery Monitor iei dee devs He ute deeded este deus del deve Dee dede 44 1 5 10 EEPROM Interface 2 ri dide lL intel 45 1 5 11 Hardware Watchdog 48 1 512 Program Security d lL E d c He c a d ieee 48 1 5319 Test Ports ete e e ee ge Hed m i d n dt Eee utes 49 2 Functional Description 50 2 Lrieory ot ODSratlloni ott ttti t tms ovem tui 50 2 2 System Timing senten nnns nnns sn nene inneren nannte nnns 51 2 9 1 niet oie Ae eet ib es dieti Ant 52 2 3 1 BROWNOUT aa 53 2 325 d 54 2 9 9 SLEEP MOGO fedt rte Ded 54 2 4 Fault and Heset Behavior 1 aio ete obs eie aide iege kr Aue 59 2 5 eate tmt ete enter Aden eese etaed e 60 2 571 Wake On TImer a dte e eeiam b ede a o eiue 60 2 6 Dala FOW EN 60 2 7 CE MPU Communication
9. nannten ns 61 2 Rev 1 1 DS 6612 001 78M6612 Data Sheet 3 Application nennen nnne nnne nnn nnne ununun nennt nunne nn nasus nnnm nnne nennt 62 3 1 Connection of Sensors CT Resistive Shunt sse enne 62 3 2 Temperature Measurement 63 3 3 Temperature 63 3 4 Temperature Compensation and Mains Frequency Stabilization for the RTO 64 23 5 Connecting iode tete ra ditt ha TRA ete Lee uda e Fete 65 3 6 Connecting eiie iterat prati eere ites etaed ect S ERRAT TL Eee RUM ete Rhen 66 3 7 Connecting lC BEEP RONG seta atis tort eS 68 3 8 Connecting 3 Wire 5 2 10 10000 69 3 9 UARTO TXRX EE 69 3 10 Interface 70 3 11 Connecting V1 and Reset 70 3 12 Connecting the Emulator Port 44 10001 nnne nnne nennen 71 3 19 Crystal Oscillator d 72 3 14 72 3 15 MPU Fir
10. 96 Figure 42 64 Pin LQFP PINOUT enm aee e a eee dene eade 97 43 68 itin terme dg a lene dna aao eee e ada d aa 100 Rev 1 1 5 78 6612 Data Sheet DS 6612 001 Tables Table 1 Inputs Selected in Regular and Alternate Multiplexer 9 Table 2 CE DRAM Locations for ADC 12 Table 3 Memory traderent tende Idee ceu deu ddnde dee fatal 16 Table 4 Stretch Memory Cycle Width sse eene nnne 17 Table 5 Internal Data Memory Map 18 Table 6 Special Function Registers Locations 18 Table 7 Special Function Registers Reset Values ssssssssssssssseseeeene enne 19 Tabl 8 PSW BeglslBr ic io IEEE tege RARE stun ies ead acetate 20 Table 9z Port Fegisters 2 eue c pte bh aie Eie EE due desine cds 21 Table 10 Special Function Registers nnne 21 Table 11 Baud Rate 23 Table 12 UART Mods iie the pr 23 Table 13 Th SOCON H8glstar n cte 24 Table 14 The SICON 25 Tabl 15 The TCON ReGISten a a ede een ee td ace dee nee
11. Total Number of SEG in Addition LCD Segment DIO PINS in Total Humber Of LCD_NUM Addition to DIO1 DIO Pins Including to SEGO SEG18 Pins Including DIO2 DIO1 DIO2 SEGO SEG18 0 None 19 4 11 14 17 19 21 18 1 41 20 4 11 14 17 19 20 17 2 40 41 21 4 11 14 17 19 16 3 39 41 22 4 11 14 17 15 4 39 41 22 4 11 14 17 15 5 37 39 41 23 4 11 14 16 14 6 36 37 39 41 24 4 11 14 15 13 7 35 37 39 41 25 4 11 14 12 8 34 37 39 41 26 4 11 11 9 34 37 39 41 26 4 11 11 10 34 37 39 41 26 4 11 11 11 31 34 37 39 41 27 4 10 10 30 31 34 37 12 39 41 28 4 9 9 29 31 34 37 13 39 41 29 4 8 8 28 31 34 37 14 39 41 30 4 7 7 27 31 34 37 15 39 41 31 4 6 6 26 31 34 37 16 39 41 32 4 5 5 25 31 34 37 17 39 41 33 4 4 24 31 34 37 18 39 41 34 None 3 Note LCD segment numbers are given without CKTEST SEG19 E RXTX SEG38 E_TCLK SEG33 and E RST SEG32 Rev 1 1 67 78M6612 Data Sheet DS 6612 001 Table 47 LCD and DIO Pin Assignment by LCD NUM for the LQFP 64 Package Tote NUBE DIO Pinsin Total Number of DIO LCD NUM 2 2 9 bs DIO1 Pins DIO1 SEG18 0 17 4 11 14 17 19 20 16 1 17 4 11 14 17 19 20 16 2 40 18 4 11 14 17 19 15 3 39 40 19 4 11 14 17 14 4 39 40 19 4 11 14 17 14 5 37 39 40 20 4 11 14 16 13 6 36 37 39 40 21 4 11 14 15 12 7 35 37 39 40 22 4 11 14 11 8 34
12. 47 Figure 12 3 Wire Interface Write Command when 0 2 0424 0 00 00 47 Figure 13 3 Wire Interface Write Command when 2 1 and 1 47 Figure 14 Functions Defined by 1 48 Figure 15 Voltage Current Momentary and Accumulated Energy 50 Figure 16 Timing Relationship between ADC MUX Compute Engine and Serial Transfers 51 Figure 17 RTM Output ceed marie terne enne end act cuan dde enu aa e nen dua onn 51 Figure 18 Operation Modes State Diagram entente nenne 54 Figure 19 Functional Blocks BROWNOUT Mode inactive blocks grayed 55 Figure 20 Functional Blocks in LCD Mode inactive blocks grayed 56 Figure 21 Functional Blocks SLEEP Mode inactive blocks grayed 57 Figure 22 Transition from BROWNOUT to MISSION Mode when System Power Returns 58 Figure 23 Power Up Timing with V3P3SYS and VBAT Tied Together 58 Figure 24 Power Up Timing with VBAT Only sss nennen nennen nennen 59 Figure 25 MPU GE Data Flow sc tre dede nena cde eed nde vides aes 60 Figure 26 MPU CE 2 9 61 Figure 27 Res
13. 94 5 4 FRESE WAGs Tos essen cia Eb 94 bbib sBIOi Tercera eee 94 5 5 6 Typical Performance Data 0 44 00 0000 95 Rev 1 1 3 78 6612 Data Sheet DS 6612 001 6 PACKAGING noie errem i M e DM DM EDI D T TAL as 97 oZibQEPAPackage iusautawete cete e oval ero 97 MEI M M E 97 6 1 2 Package Outline LQFP 64 enne trennen 98 6 1 3 Recommended PCB Land Pattern for the LQFP 64 Package 99 6 2 68 Pin QEN Package ne eser ne D Ie Beh tud Ln Re ea ae de e dad eee Lek n A 100 56 2 1 3PIDIOUE E LM E DNE E 100 6 2 2 Package Outllrie iei ne Ree e ee v Lo oi TEA eie Dade ER ERR RN AR 101 6 2 3 Recommended PCB Land Pattern for the QFN 68 102 72 Pin Descriptions meinen cases Sa es Bad ta uice d 103 Ta sPOWer Ground PINS desse rais a eh deis aer 103 7 2 VAMAIOG PINS o te ae ee peu el edet b oet tend 103 753 e 104 8 Equivalent
14. CKFIR V2P5 SECIS Terour poez 2 5V to logic V3P3D CK GEN CK 2x LCD GEN VLC2 ECK DIS MPU_DIV CE RAM VLC1 MUX SYNC 0 958 LCD MODE WC STRT L J WPULSE LCD_E 0 gt VARPULSE MUX CKCE SEG13 and SEG 14 gt E o l _ lt 4 9MHz RTM Y LCD DISPLAY on 68 Pin Package 32 bit Compute DE DRIVER 4 Only TEST Engine i gt gt TEST ODE MEMORY SHARE cp yum COMO 3 LCD MODE m 245 SEGO 18 CE T LCD E SEG32 33 CONTRO 000 7FF 1000 ITRE LCD BLKMAP gt SEG19 38 SEG24 D104 LCD_SEG LCD Y SEGS31 DIO11 0 3 SEG34 DIO14 PLS INV E DIGITAL SEG37 DIO17 5_ DIO_EEX PLS_INTERVAL WPULSE ea SEG39 DIO19 PLS MAXWIDTH z VARPULSE J f pio DIR SEG40 DIO20 gt z 90101 2 7 3 EEPROM DIOR 8 LCD_NUM PRE_SAMPS o ox INTERFACE En SUM CYCLES E 2 RTC 5 L RTCLK CKMPU DEC SEC 249 2 RTC_INC_SEC CONFIGURATION SDCK_y PARAMETERS RX gt SDOUT CONFIG UART lt 68 Pin Package Only TX DIN 2000 20FF I DATA DIO3 MPU sooo L DIO21 SEG41 RX1 OPTICAL 80515 0000 07 MPU XRAM lt 0101 2KB EE TX1 0000 MOD FLASH DIO2 1 4 PROG memory FIF 32KB APOLT Pr TXMDD 0000 ERE SPARE VARPULSE PT FDC TXINV CELCIN RLSHGSET VBIAS Y MPU RSTZ POWER FAULT E ORT Mux TMUXOUT FAULTZ
15. sse enne nnns 89 5 3 Recommended Operating Conditions nennen nennen 89 5 4 Performance lt nennen nnne nnns 90 5 4 1 Input Logic 44244 90 5 4 2 Output Logic 90 5 4 3 Power Fault Comparator 04 10 eene nennen enne 90 5 44 Battery MONOT 5 90 545 Supply Cument e denne ae 91 S ROME IRE EIE 91 5 4 7 2 5V Voltage Regulator E EE E EEE eese trennen nnn nennen 91 5 4 8 Low Power Voltage Regulator 91 54 9 Crystal OscillatOr oie e ER LU err a Loc cd agus 92 5 410 VBEE VBIAS mtu tiem 92 SO MEMESBUBI EM ER 92 5 4 12 ADC Converter Referenced 0 0 93 TATUARI TInterface s s oi a edd ipe rise 93 5 4 14 Temperature 5 93 5 5 Timing SpecifiCatiOris cire tet rp S a a p 94 5 5 1 RAM and Flash 94 5 5 2 Flash Memory 0 94 55 9
16. Rev 1 1 93 78 6612 Data Sheet DS 6612 001 5 5 Timing Specifications 5 5 1 RAM and Flash Memory Parameter Condition Min Typ Max Unit CKMPU 4 9152 MHz Cycles CE DRAM wait states CKMPU 1 25 MHz Cycles CKMPU 614 kHz Cycles Flash Read Pulse Width M Cp ee 30 100 ns BROWNOUT MODE Flash write cycles 40 C to 85 20 000 Cycles Flash data retention 25 C 100 Years Flash data retention 85 C 10 Years Flash byte writes between page or 2 Cycles mass erase operations 5 5 2 Flash Memory Timing Parameter Condition Min Typ Max Unit Write Time per Byte 42 us Page Erase 512 bytes 20 ms Mass Erase 200 ms 5 5 3 EEPROM Interface Parameter Condition Min Typ Max Unit CKMPU 4 91 52 MHz 78 kHz 2 Using interrupts Write Clock frequency I C CKMPU 4 9152 MHz 150 kHz bit banging DIO4 5 Write Clock frequency 3 wire CKMPU 4 9152 MHz 500 kHz 5 5 4 RESET and V1 Parameter Condition Min Typ Max Unit Reset pulse fall time 1 us Reset pulse width 5 us V1 Response Time 100 mv overdrive 10 37 100 uS 5 5 5 RTC Parameter Condition Min Typ Max Unit Range for date 2000 2255 year 94 Rev 1 1 DS 6612 001 78M6612 Data Sheet 5 5 6 Typical Performance Data 0 5 0 4 0 3 0 2 0 1 0 1 0 2 0 3 0 4 0 5 Accuracy Wh A
17. Y LCD 0 amp on 68 Pin Package 32 bit Compute DATA DRIVER 4 Only TEST Engine 00 7F TEST EMORY SHARE yum 3 LCD_MODE gue a LCD CLK SEGO 18 LCD E SEG32 33 CONTBOE 000 7FF 1000 11 FF LCD BLKMAP gt SEG19 38 A SEG24 D104 SEG31 DIO11 LCD Y 0 3 SEG34 DIO14 TM E DIGITAL SEG37 DIO17 po p M EE WPULSE L 5 010 EEX SEG39 DIO19 PLS MAXWIDTH VARPULSE J amp 4 5 SEG40 DI020 CE LCTN Za 9 0 090101 2 e a3 EEPROM DIOR EQU LCD_NUM PRE_SAMPS mom INTERFACE NE DIO SUM CYCLES Bs uU gt RTC 5 _ CKMPU RTC_DEC_SEC ETE RTC_INC_SEC CONFIGURATION SDCK PARAMETERS gt SDOUT CONFIG IL UART SDIN 68 Pin Package Only 50 2000 20FF TALS DATA 0103 MPU 0000 FFFF E DIO21 SEG41 RX1 80515 0000 07FF MPU XRAM DIO1 2KB ox 0000 MOD 7FFF FLASH DIO2 4 RXDIS PROG MEMORY 32KB WPULSE pu 0000 7FFF SHARE 2 CE_LCTN VARPULSE FDC TXINV FLSH66ZT VBIAS MPU RSTZ POWER FAULT wo i lt TEST FAULTZ MUX TMUXOUT COMP_STAT E TCLK TMUX 4 0 E_RST Open Drain TROI RESET E RXTX SEG38 ICE E January 14 2009 E TCLK SEG33 4 E RST SEG32 Figure 1 IC Functional Block Diagram Rev 1 1 78 6612 Data Sheet DS 6612 001 1 Hardware Descript
18. see Table 29 e The interrupt priority registers and see Table 33 and Table 34 Interrupt Enable 0 Register Table 24 Register MSB LSB EAL WDT ESO ETI EX ETO Bit Symbol Function IENO 7 EAL EAL 0 disable all interrupts IENO 6 WDT Notused for interrupt control IENO 5 IENO 4 ESO ES0 0 disable serial channel 0 interrupt IENO 3 ETI 1 0 disable timer 1 overflow interrupt IENO 2 EXI EX1 0 disable external interrupt 1 IENO 1 ETO 0 disable timer 0 overflow interrupt IENO 0 Ex0 0 disable external interrupt 0 Interrupt Enable 1 Register Table 25 Register MSB LSB SWDT EX6 EX5 EX4 EX3 EX2 Bit Symbol Function IENI1 7 IENI 6 SWDT Not used for interrupt control IENI 5 EX6 EX6 0 disable external interrupt 6 IEN1 4 5 5 0 disable external interrupt 5 IEN1 3 4 EX4 0 disable external interrupt 4 IENI 2 EX3 0 disable external interrupt 3 IENI 1 EX2 EX2 0 disable external interrupt 2 IENI 0 Rev 1 1 31 78 6612 Data Sheet DS 6612 001 Interrupt Enable 2 Register EN2 Table 26 The JEN2 Register
19. 70 Rev 1 1 DS 6612 001 78M6612 Data Sheet Figure 36 Voltage Divider for V1 Even though a functional power and measurement unit will not necessarily need a reset switch it is useful to have a reset pushbutton switch for prototyping as shown in Figure 37 left side The RESET signal may be sourced from V3P3SYS functional in MISSION mode only V3P3D MISSION and BROWNOUT modes VBAT all modes if battery is present or from a combination of these sources depending on the application For a production unit the RESET pin should be protected by the external components shown in Figure 37 right side R should be in the range of 100 and mounted as closely as possible to the IC The RESET pin can also be directly connected to ground Since the 78M6612 generates its own power on reset a reset button or circuitry as shown in Figure 37 left side is only required for test units and prototypes Gp eee V3P3D V3P3D 1 78M6612 78M6612 2 LIA 1kQ Reset Switch l 5 RESET RESET I 100 0 10kQ O R 1 DGND Y l 7 Figure 37 External Components for RESET Development Circuit Left Production Circuit Right 3 12 Connecting the Emulator Port Pins Capacitors to ground must be used for protection from EMI Production boards should have the ICE E pin connected to ground If the ICE pins are used to drive LCD segments the pull up
20. TERIDIAN 78M6612 WAKE UP W 54 REGULATOR VBAT V2 5 BATTERY VOLTAGE REF TEMP SENSOR DIO PULSE VREF VBIAS RAM SEGO 18 FLASH SEG 24 31 gt 0104 11 SERIAL PORTS OPTIONAL SEG 34 37 COMPUTE DIO 14 147 Cor uWire ENGINE EEPROM SEG 32 33 38 ICE POWER FAULT i RTC TIMERS OSC PLL N XII 7 GNDD 32kHz XOUT 2009 FEATURES Measures each outlet of a duplex receptacle with a single IC Provides complete energy measurement and communication protocol capability in a single IC Intelligent switch control capability e lt 0 5 Wh accuracy over 2000 1 current range and over temperature Exceeds IEC62053 ANSIC12 20 standards Voltage reference 40 ppm C Four sensor inputs VDD referenced Low jitter Wh and VARh pulse test outputs 10 kHz maximum Pulse count for pulse outputs Line frequency count for RTC Digital temperature compensation Sag detection for phase A and B Independent 32 bit compute engine 46 64 Hz line frequency range with same calibration Phase compensation 7 Battery backup for RTC and battery monitor Three battery modes with wake up timer Brownout mode 48 uA LCD mode 5 7 nA Sleep mode 2 9 uA Energy display on main power failure Wake up timer 22 bit delta sigma ADC 8 bit MPU 80515 1 clock cycle per instruction w integ
21. S When configured as inputs the dual function DIO SEG pins should not be pulled above The control resources selectable for the DIO pins are listed in Table 40 If more than one input is connected to the same resource the resources are combined using a logical OR 78M6612 78M6612 gt 4 ES LED 2 001 4 R DGND O n 4 Not recommended Recommended Figure 8 Connecting an External Load to DIO Pins Rev 1 1 43 q 3P3SYS 3 3V 2 78 6612 Data Sheet DS 6612 001 Table 40 Selectable Controls using the DIO DIR Bits DIO R Value Resource Selected for DIO Pin NONE Reserved TO counterO clock T1 counter1 clock High priority I O interrupt INTO rising Low priority I O interrupt INT1 rising High priority I O interrupt INTO falling Low priority I O interrupt INT1 falling o 1 5 8 LCD Drivers The device in the 68 pin QFN package contains 20 dedicated LCD segment drivers in addition to the 18 multi use pins described above Thus the device is capable of driving between 80 to 152 pixels of LCD display with 2596 duty cycle or 60 to 114 pixels with 3396 duty cycle At eight pixels per digit this corresponds to 10 to 19 digits The device in the 64 pin LQFP package contains 18 dedicated LCD segment drivers in addition to the 17 multi use pins described above Thus the device is capable
22. 8 curve fit 32767 6 inverse curve 32767 5 50 25 0 25 50 Figure 30 Crystal Compensation The MPU Demo Code supplied with the Teridian Demo Kits has a direct interface for these coefficients and it directly controls the RTC DEC SEC or RTC INC SEC registers The Demo Code uses the coefficients in the form Y CAL Y CALC n Y_CALC2 T LATO 10 100 1000 Note that the coefficients are scaled by 10 100 and 1000 to provide more resolution For our example case the coefficients would then become after rounding CORRECTION ppm Y CAL 109 Y CALC 12 Y_CALC2 7 Alternatively the mains frequency may be used to stabilize or check the function of the RTC For this purpose the CE provides a count of the zero crossings detected for the selected line voltage in the MAIN EDGE X address This count is equivalent to twice the line frequency and can be used to synchronize and or correct the RTC 3 5 Connecting 5V Devices All digital input pins of the 78M6612 are compatible with external 5V devices I O pins configured as inputs do not require current limiting resistors when they are connected to external 5V devices Rev 1 1 65 78 6612 Data Sheet DS 6612 001 3 6 Connecting LCDs The 78M6612 has a LCD controller on chip capable of controlling static or multiplexed LCDs Figure 31 shows the basic connection for a LCD 78M66
23. DS 6612 001 78M6612 Data Sheet 8 I O Equivalent Circuits V3P3D V3P3D 110K p vut H s cmos Pin Input 4 GNDD rH Digital Input Equivalent Circuit Type 1 Standard Digital Input or pin configured as DIO Input with Internal Pull Up V3P3D Digital CMOS Input Pin Input 110K GNDD GNDD Digital Input Type 2 Pin configured as DIO Input with Internal Pull Down V3P3D Digital CMOS Input Pin GNDD Digital Input 3 Standard Digital Input or pin configured as DIO Input V3P3D E V3P3D CMOS Digital Output Output Pin GNDD GNDD Digital Output Equivalent Circuit Type 4 Standard Digital Output or pin configured as DIO Output LCD LCD SEG Driver Output Pin GNDD LCD Output Equivalent Circuit Type 5 LCD SEG or pin configured as LCD SEG V3P3A 7 d To npu MUX Pin GNDA Vv Analog Input Equivalent Circuit Type 6 ADC Input V3P3A Pin Comparator GNDA mparator In Equivalen Circuit Type 7 Comparator Input Oscillator To Pin Oscillator GNDD Oscillator Equivalent Circuit Type 8 Oscillator I O V3P3A from VREF internal Pin reference GNDA VREF Equivalent Circuit Type 9 VREF V3P3D from V2P5 internal Pin reference GNDD V2P5 Equivalent Circuit Type 10 V2P5 VBAT Power Down Circuits 2 GNDD wv VBAT Equivalent Circuit Type 12 VBAT Power 10
24. Figure 16 summarizes the timing relationships between the input MUX states the CE BUSY signal and the two serial output streams In this example MUX DIV 1 0 4 and FIR LEN 1 384 The duration of each frame is 1 DIV 1 0 2 if FIR LEN 0 288 and 1 DIV 1 0 3 if FIR LEN 1 384 An ADC conversion will always consume an integer number of CK32 clocks Followed by the conversions is a single CK32 cycle where the bandgap voltage is allowed to recover from the change in CROSS Each CE program pass begins when ADCO channel IA conversion begins Depending on the length of the CE program it may continue running until the end of the ADC3 VB conversion CE opcodes are constructed to ensure that all CE code passes consume exactly the same number of cycles The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete The CE code is written to tolerate sudden changes in ADC data The exact CK count when each ADC value is loaded into DRAM is shown in Figure 16 Figure 16 also shows that the serial RTM data stream begins transmitting at the beginning of state S RTM consisting of 140 CK cycles will always finish before the next code pass starts ADC MUX Frame gt ADC le MUX_DIV Conversions MUX DIV 1 0 01 4 conversions is shown gt Settle 2 1 1
25. LI LJ 4 150 gt MUX SYNC MUX STATE S X 0 X 1 X 2 X 3 X 5 X ADC EXECUTION p uU t Lu ADCO ADC1 ADC2 ADC3 0 450 00 350 1800 9 CE_EXECUTION gD CK COUNT CE_CYCLES floor CE_CYCLES 2 5 gt CK COUNT BUSY _ XFER_BUSY A INITIATED BY CE OPCODE AT END OF SUM INTERVAL RTM TIMING lt gt NOTES 1 ALL DIMENSIONS ARE 5MHZ CK COUNTS 2 THE PRECISE FREQUENCY OF CK IS 150 CRYSTAL FREQUENCY 4 9152MHz 3 XFER_BUSY OCCURS ONCE EVERY PRESAMPS SUM CYCLESEODE PASSES Figure 16 Timing Relationship between ADC MUX Compute Engine and Serial Transfers cka2 SYNC dac SRE eRe TMXOUDRTM ae mm gt FLAG FLAG 2 FLAG SIM Tij RTM DATAO 32 bits 3 M 5 RTM DATA 32 bits 2 RTM DATA2 32 bits 2 RTM DATAS 32 bits Figure 17 RTM Output Format Rev 1 1 51 78 6612 Data Sheet DS 6612 001 2 3 Battery Modes Shortly after system power V3P3SYS is applied the part will be in MISSION mode MISSION mode means that the part is operating with system power and that the internal PLL is stable This mode is the normal operation mode where the part is capable of measuring energy When system power is not available i e when V1 VBIAS t
26. SEMICONDUCTOR CORP 78M6612 Single Phase Dual Outlet Power and Energy Measurement IC Simplifying System Integration DATASHEET DESCRIPTION The Teridian 78 6612 is a highly integrated single phase power and energy measurement and monitoring SOC which includes a 32 bit compute engine CE an MPU core RTC and Flash The Teridian patented Single Converter Technology with a 22 bit delta sigma ADC 4 analog inputs digital temperature compensation and precision voltage reference supports a wide range of single phase dual outlet power measurement applications with very few external components With measurement technology leveraged from Teridian s flagship utility metering IC s it offers features including 32 KB of Flash program memory 2 KB shared RAM three low power modes with internal timer or external event wake up 2 UARTs wire EEPROM I F and an in system programmable Flash Complete Outlet Measurement Unit OMU and AC Power Monitor AC PMON firmware is available or can be pre loaded into the IC A complete array of ICE and development tools programming libraries and reference designs enable rapid development and certification of Power and Energy Measurement solutions that meet the most demanding worldwide electricity metering standards RRR 1 OUTLET POWER SUPPLY 1 1 CONVERTER V33A ae GNDA GNDD PWR MODE OPTIONAL CONTROL
27. gt FIR ADC_E VREF VBAT qx e p VREF FIR_LEN MUX VREF_CAL VBAT l VREF DIS A A MUX cross CTRL EQU CK32 ALT VOLT CHOP_E REG MUX_DIV 5 RTCLK 32KHz MCK cK32 DIV XIN 32KHz PLL 0 4 LCD ONLY JGNDD SLEEP XOUT CKADC CKTEST CKOUT E CKFIR L V2P5 SEGI9 CKOUT_E SMa 2 2 5V to logic V3P3D CK GEN CK 2X Spo LCD vLc2 ECK DIS MPU DIV CE RAM VLCI 0 5 MUX SYNC LCD MODE VLCO STRT J WPULSE LCD_E J5VARPULSE MUX CKCE SEG13 and SEG 14 u lt 4 9MHz LCD DISPLAY on 68 Pin Package 32 bit Compute DRIVER 4 Only TEST Engine a E dl 5 ODE MEMORY SHARE Num COMO 3 LCD MODE F F y m M pope SEGO 18 CE LCD_E SEG32 33 CONTROL 000 7FF 1000 11r LCD BLKMAP gt SEG19 38 SEG24 DIO4 ECDLSEG SEG31 DIO11 LCD Y 0 3 SEG34 DIO14 PLS INV EE DIGITAL SEG37 DIO17 5 DIO_EEX PLS_INTERVAL WPULSE SEG39 DIO19 PLS MAXWIDTH VARPULSE 3 f pio DIR SEG40 D1020 LCTN gt Oo z 90101 2 3 EEPROM DIO R 280 2 LCD_NUM PRE_SAMPS INTERFACE geb 7 7 SUM_CYCLES 2 RTC 5 RTCLK CKMPU RTC_DEC_SEC 4 9MHz SEC CONFIGURATION SDCK PARAMETERS RX gt SDOUT CONFIG e 68 Pin Package Only L MART SPIN 2000 20FF DATA DIO3 MPU ooo 1 DIO21 SEG41 RX1 OCA 80515 0000 07 MP
28. 1 13 1 32 Real Time Monitor 13 1 9 3 Pulse Generatotis i nti e e a OR a Ee eed debe AE p o DoD 13 1 3 4 CE Functional Overview 14 1 4 80515 a Mee Aa ees 15 1 4 1 Memory Organization sse en nennen 16 1 4 2 Special Function Registers 18 1 4 3 Special Function Registers Generic 80515 19 1 4 4 Special Function Registers Specific to the 78 6612 21 1 4 5 Instr ction tape le Hd doe e Hed ce i d e He P 23 1 4 6 WARTS iini iit Hd Hr e dde ete bed gt He da 23 1 4 7 Timers and Counters 26 1 4 8 WD Timer Software Watchdog Timer sssssssssseeneeeeenen en 28 1 49 EM 30 1 5 On Chip RReSoUrcas aie c e dg edd 39 ueri 39 1 5 2 PLL and Internal 39 1 5 8 Real Time Clock 39 1 5 4 Temperature Sensor sisisihin 40 1 5 5 Physical 2 2
29. 34 Table 32 Priority Level seen sitet enne 35 Table 333 The TPO heglster ue oen ete tenait Latet deleti tdt dur ts 36 Table 34 The PT Register eiie e eet a va t nen ass 36 T ble 35 Priority Eevels 36 Table 36 Interrupt Polling 36 Tabl 37 Interrupt Vectofs retten om rtp eei aer 37 Table 38 Data Direction Registers and Internal Resources for DIO Pin 42 Table 39 DIO DIR 42 Table 40 Selectable Controls using the DIO DIR nnns 44 Table 41 EECTRE Status Bits eed ideae eet dor d a a du d due Dt ede 45 Table 42 EECTRL Bits for 3 Wire 46 Table 3 FMUX A4 0 SelectlohSg 5 teta ex petet verte 49 Table 44 Available Circuit sensere ens 53 Table 45 Frequency over Temperature 64 Table 46 LCD and DIO Pin Assignment by LCD NUM for the QFN 68 Package 67 Table 47 LCD and DIO Pin Assignment by LCD NUM for the LQFP 64 Package 68 Table 48
30. DIO_R9 2 0 2000 6 4 0 DIO RI0 2 0 200E 2 0 0 0 010 TO TimerO clock or gate OR gt 200EI6 4 0 0 011 T1 Timer1 clock or gate OR DIO R11 2 0 6 4 100 High priority IO interrupt intO rising OR 101 Low priority IO interrupt int1 rising OR 110 High priority IO interrupt intO falling OR 111 Low priority IO interrupt int1 falling OR DIO DIRO 7 1 SFRA2 0 0 R W Programs the direction of pins DIO7 DIO1 DIO3 is only 7 1 available on the 68 pin package 1 indicates output Ignored if the pin is not configured as l O See DIO PV and DIO PW for special option for DIO6 and DIO7 outputs See DIO EEX for special option for DIO4 and DIO5 Rev 1 1 75 78 6612 Data Sheet DS 6612 001 Name Location Rst Wk Dir Description DIO DIR1 7 6 3 0 SFR91 0 0 R W Programs the direction of pins DIO15 DIO14 DIO11 DIO8 7 6 3 0 1 indicates output Ignored if the pin is not configured as DIO_DIR2 5 3 2 1 SFRA1 0 0 R W Programs the direction of pins DIO20 DIO19 and DIO17 5 3 2 1 DIO16 and DIO21 for the 68 QFN package 1 indicates output Ignored if the pin is not configured as DIO 0 7 1 SFR80 0 0 R W The value on the pins DIO7 DIO1 0103 is only available 7 1 on the 68 pin package Pins configured as LCD will read zero When written changes data on pins c
31. E8 WDI EF E0 A E7 D8 WDCON DF DO PSW D7 C8 T2CON CF CO IRCON C7 B8 IENI IPI SORELH SIRELH USR2 BF BO FLSHCTL FPAG B7 A8 IENO IPO SORELL AF 2 DIR2 DIRO A7 98 SOCON SOBUF IEN2 SICON SIBUF SIRELL EEDATA EECTRL 9F 90 DIRI DPS ERASE 97 88 TCON TMOD TLO TLI THO 1 CKCON 8F 80 PO SP DPL DPH DPLI DPHI WDTREL PCON 87 Only a few addresses are occupied the others are not implemented SFRs specific to the 78M6612 are shown in bold print Any read access to unimplemented addresses will return undefined data while any write access will have no effect The registers at 0x80 0x88 0x90 etc are bit addressable all others are byte addressable 18 Rev 1 1 DS 6612 001 78M6612 Data Sheet 1 4 8 Special Function Registers Generic 80515 SFRs Table 7 shows the location of the SFRs and the value they assume at reset or power up Table 7 Special Function Registers Reset Values Name Location Reset Value Description Page 0 80 OxFF Port 0 DIOO 21 SP 0x81 0x07 Stack Pointer 20 DPL 0x82 0x00 Data Pointer 0 Low Standard Data Pointer 20 DPH 0x83 0x00 Data Pointer 0 High Standard Data Pointer 20 DPLI 0x84 0x00 Data Pointer 1 Low Second Data Pointer 17 DPHI 0x85 0x00 Data Pointer 1 High Second Data Pointer 17 WDTREL 0x86 0x00 Watchdog Timer Reload register 30 P
32. MOV DPL data8 It is generally used to access external code or data space e g MOVC A A DPTR or MOVX A DPTR respectively Program Counter The program counter PC is 2 bytes wide and initialized to 0 0000 after reset This register is incremented when fetching operation code or when operating on data from program memory 20 Rev 1 1 DS 6612 001 78M6612 Data Sheet Port Registers The I O ports are controlled by Special Function Registers PO P1 and P2 The contents of the SFR can be observed on corresponding pins on the chip Writing a 1 to any of the ports see Table 9 causes the corresponding pin to be at high level V3P3 and writing a 0 causes the corresponding pin to be held at low level GND The data direction registers DIRO DIR and DIR2 define individual pins as input or output pins see the Section 1 5 7 Digital I O for details Table 9 Port Registers SFR Register Address R W Description PO 0x80 R W Register for port 0 read and write operations pins DIO4 DIO7 DIRO 2 R W Data direction register for port 0 Setting a bit to 1 means that the corresponding pin is an output PI 0x90 RAW Register for port 1 read and write operations pins DIO8 DIO11 DIO14 DIO15 DIRI 0x91 RAW Data direction register for port 1 P2 OxAO RAW Register for port 2 read and write operations pins DIO16 DIO17 DIO19 DIO21 DIR2 OxA1 RAW Data direction regis
33. VA VB 6 internal A D converter Typically they are connected to the outputs of resistor dividers Unused pins must be connected to V3P3A or tied to the voltage sense input that is in use Comparator Input This pin is a voltage input to the internal power fail comparator The input voltage is compared to the internal BIAS V1 7 voltage 1 6 V If the input voltage is above VBIAS the comparator output will be high 1 If the comparator output is lower a voltage fault will occur and the chip will be forced to battery mode Voltage Reference for the ADC This pin is normally disabled by VREF 9 setting the VREF_CAL bit in the I O RAM and can then be left unconnected If enabled a 0 1 uF capacitor to GNDA should be connected Crystal Inputs A 32 kHz crystal should be connected across these XIN 8 pins Typically 27 pF capacitor is also connected from each pin to XOUT GNDA It is important to minimize the capacitance between these pins See the crystal manufacturer datasheet for details Pin types Power Output Input I O Input Output S The circuit number denotes the equivalent circuit as specified under I O Equivalent Circuits Rev 1 1 103 78 6612 Data Sheet DS 6612 001 7T 3 Digital Pins Name Type Circuit Description COMS 2 5 LCD common outputs These four pins provide the select signals for the COM1 LCD display
34. erased during the Page Erase cycle default 0x00 Must be re written for each new Page Erase cycle Rev 1 1 21 78M6612 Data Sheet DS 6612 001 Register Alternative Name SFR Address R W Description EEDATA Ox9E R W IC EEPROM interface data register EECTRL Ox9F R W EEPROM interface control register If the MPU wishes to write a byte of data to EEPROM it places the data in EEDATA and then writes the Transmit code to EECTRL The write to EECTRL initiates the transmit sequence See Section 1 5 10 EEPROM Interface for a description of the command and status bits available for EECTRL FLSHCRL 0 2 R W R W Bit 0 FLSH_PWE Program Write Enable 0 MOVX commands refer to XRAM Space normal operation default 1 MOVX DPTR A moves A to Program Space Flash DPTR This bit is automatically reset after each byte written to Flash Writes to this bit are inhibited when interrupts are enabled Bit 1 FLSH MEEN Mass Erase Enable 0 Mass Erase disabled default 1 Mass Erase enabled Must be re written for each new Mass Erase cycle Bit 6 SECURE Enables security provisions that prevent external reading of Flash memory and CE program RAM This bit is reset on chip reset and may only be set Attempts to write zero are ignored Bit 7 PREBOOT Indicates that the preboot sequence is active WDI OxE8 R
35. it can be interrupted only by a higher priority interrupt The interrupt service is terminated by a return from the RETI instruction When a RETI is performed the MPU will return to the instruction that would have been next when the interrupt occurred When the interrupt condition occurs the MPU will also indicate this by setting a flag bit This bit is set regardless of whether the interrupt is enabled or disabled Each interrupt flag is sampled once per machine cycle then samples are polled by the hardware If the sample indicates a pending interrupt when the interrupt is enabled then the interrupt request flag is set On the next instruction cycle the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address if the following conditions are met e interrupt of equal or higher priority is already in progress e Aninstruction is currently being executed and is not completed e The instruction in progress is not RETI or any write access to the registers IEN1 IEN2 IPO or 30 1 1 DS 6612 001 78M6612 Data Sheet Special Function Registers for Interrupts The following SFR registers control the interrupt functions e The interrupt enable Registers IENO IEN1 and IEN2 see Table 24 Table 25 and Table 26 e The Timer Counter control registers The Timer Counter control registers TCON and T2CON see Table 27 and Table 28 e The interrupt request register
36. 0 5to 6 V Configured as Digital Outputs 15mA to 15mA 0 5V to V3P3D 0 5V All other pins 0 5V to V3P3D 0 5V Operating junction temperature peak 100 ms 140 C Operating junction temperature continuous 125 C Storage temperature 45 C to 165 Solder temperature 10 second duration 250 C ESD stress on all pins 4 kV Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability All voltages are with respect to GNDA 88 Rev 1 1 DS 6612 001 78M6612 Data Sheet 5 2 Recommended External Components Name From To Function Value Unit C1 V3P3A AGND Bypass capacitor for 3 3V supply uF C2 V3P3D DGND Bypass capacitor for 3 3V output 0 1420 uF CSYS 36 5 Bypass capacitor for V3P3SYS 21 p 2 5 V2P5 DGND Bypass capacitor for V2P5 0 1 20 32 768 kHz crystal electrically similar to XTAL XIN XOUT ECS 327 12 5 17X or Vishay XT26T load 32 768 kHz capacitance 12 5 pF cxst XIN AGND Load capacitor for crystal exact value 27 10 pF t depends on crystal specifications and CXL XOUT AGND parasitic capacitan
37. 37 39 40 23 4 11 10 9 34 37 39 40 23 4 11 10 10 34 37 39 40 23 4 11 10 11 81 34 37 39 40 24 4 10 9 12 30 31 34 37 39 40 25 4 9 8 13 29 31 34 37 39 40 26 4 8 7 14 28 31 34 37 39 40 27 4 7 6 15 27 31 34 37 39 40 28 4 6 5 16 26 31 34 37 39 40 29 4 5 4 17 25 31 34 37 39 40 30 4 3 18 24 31 34 37 39 40 31 None 2 Note LCD segment numbers are given without CKTEST SEG19 E RXTX SEG38 E_TCLK SEG33 and E RST SEG32 Note SEG14 and SEG15 are not available in the 64 pin package 3 7 Connecting EEPROMs EEPROMs or other compatible devices should be connected to the DIO pins DIO4 and DIOS as shown in Figure 32 Pull up resistors of roughly 10 to V3P3D to ensure operation in BROWNOUT mode should be used for both SCL and SDA signals The DIO EEX register RAM must be set to 01 in order to convert the DIO pins DIO4 and DIOS to IC pins SCL and SDA V3P3D 10kOQ 78M6612 5 10kQ EEPROM DIO4 SOL 005 lt SDA Figure 32 EEPROM Connection 68 Rev 1 1 DS 6612 001 78M6612 Data Sheet 3 8 Connecting 3 Wire EEPROMs uWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5 as shown in Figure 33 0105 connects to both the DI and DO pins of the three wire device The CS pin must be connected to a vacant DIO pin of the 78M6612 A pull up resistor of roughly 10 to to ens
38. 4 4 7 4 Pulse Generation CE Det Address Name Default Description Kh VMAX IMAX 47 1132 WRATE X Wh pulse The default value results in a Kh of 3 2 Wh pulse when 2520 OxOF WRATE 486 samples are taken in each accumulation interval and VMAX 600 IMAX 52 X 6 The maximum value for WRATE is 2 1 WRATE controls the number of pulses that are generated per measured Wh and VARh quantities The lower WRATE is the slower the pulse rate for measured energy quantity The measurement constant Kh is derived from WRATE as the amount of energy measured for each pulse That is if Kh 1Wh pulse a power applied to the measurement unit of 120 V and 30 A results in one pulse per second If the load is 240 V at 150 A ten pulses per second will be generated The maximum pulse rate is 7 5 kHz The maximum time jitter is 67 us and is independent of the number of pulses measured Thus if the pulse generator is monitored for 1 second the peak jitter is 67 ppm After 10 seconds the peak jitter is 6 7 ppm The average jitter is always zero If it is attempted to drive either pulse generator faster than its maximum rate it will simply output at its maximum rate without exhibiting any rollover characteristics The actual pulse rate using WSUM as an example is RATE _ WRATE WSUM F X Hz 746 where Fs sampling frequency 2520 6 Hz X Pulse speed factor 86 Rev 1 1 DS 66
39. 5 4 2 Output Logic Levels Parameter Condition Min Typ Max Unit V3P3D 1 mA 0 4 V Digital high level output voltage 15 1 mA 0 0 4 V Digital low level output voltage VoL lLoap 15 mA 0 8 V 1 VoH V3P3D TX1 ISOURCE 1 mA 0 4 V TX1 VoL ISINK 20 mA 0 7 V 5 4 3 Power Fault Comparator Parameter Condition Min Typ Max Unit Offset Voltage V1 VBIAS 20 15 Hysteresis Current a M V1 Vin VBIAS 100 mV 0 8 12 uA Time 100 mV overdrive 2 5 10 us WDT Disable Threshold V1 V3P3A 400 10 mV 5 4 4 Battery Monitor BME 1 Parameter Condition Min Typ Max Unit Load Resistor 27 45 63 kQ LSB Value does not include the 9 bit LEN O 6 0 5 4 4 9 uV left shift at CE input FIR_LEN 1 2 6 2 3 2 0 uV Offset Error 200 72 100 mV 90 Rev 1 1 DS 6612 001 78M6612 Data Sheet 5 4 5 Supply Current Parameter Condition Min Typ Max Unit Normal Operation V3P3A V3P3SYS current V3P3A V3P3SYS 3 3V 6 1 7 7 mA MPU_DIV 1 0 3 614 kHz CKOUT E 1 0 00 CE_EN 1 VBAT current E 0 DIS 1 E 1 300 300 nA ICE_E 0 V3P3A V3P3SYS current mA vs MPU clock frequency Same conditions as above 0 5 MHz V3P3A V3P3SYS current Normal Operation as above except write Fl
40. 7 0 CONFIG2 2007 TXIE 1 0 EX PLL EX FWCOL Reserved OPT FDC 1 0 CE3 20A8 Not Used Not Used Not Used LCTN 4 0 WAKE 20 9 WAKE ARM SLEEP LCD ONLY Not Used WAKE RES WAKE PRD 2 0 TMUX 20 Not Used Not Used Not Used TMUX 4 0 Digital DIOO 2008 DIO EEX 1 0 RXIDIS RXIINV DIO PW DIO PV TXIMOD TXIINV DIO1 2009 Not Used DIO R1 2 0 Not Used Reserved 000 DIO2 200 Not Used DIO R3 2 0 Not Used DIO R2 2 0 DIO3 200B Not Used DIO R5 2 0 Not Used DIO R4 2 0 DIO4 1 200 Not Used DIO R7 2 0 Not Used DIO R6 2 0 005 2000 Not Used DIO R9 2 0 Not Used DIO R6 2 0 DIO6 200E Not Used DIO R11 2 0 Not Used DIO R10 2 0 Real Time Clock RTCO 2015 Not Used Not Used RTC SEC 5 0 RTC1 2016 Not Used Not Used RTC_MIN 5 0 RTC2 2017 Not Used Not Used Not Used RTC_HR 4 0 2018 Not Used Not Used Not Used Not Used Not Used RTC_DAY 2 0 RTC4 2019 Not Used Not Used Not Used RTC_DATE 4 0 RTC5 201 Not Used Not Used Not Used Not Used RTC_MO 3 0 RTC6 201 YR 7 0 RTC7 201 Not Used Not Used Not Used Not Used Not Used Not Used DEC SEC INC SEC WE 201F Write enable for RTC LCD Display Interface LCDX 2020 Not Used BME Reserved LCD NUM 4 0 LCDY 2021 Not Used LCD Y LCD E LCD MODE 2 0 LCD CLK 1 0 LCDZ 2022 Not Used Not Used Not Used Reserved LCDO 2030 Not Used LCD SEGO 3 0 Not Used Rev 1 1 73
41. 9 bit shift of the ADC value and then inserting the results into the above formula using 2220 for LSB C _ 449 648 000 518 203 584 512 2220 425 85 3 It is recommended to base temperature measurements on TEMP_RAW_X which is the sum of two consecutive temperature readings thus being higher by a factor of two than the raw sensor readings 3 3 Temperature Compensation Temperature Coefficients The internal voltage reference is calibrated during device manufacture The temperature coefficients TC1 and TC2 are given as constants that represent typical component behavior in uV C and uV C respectively Since TC1 and TC2 are given in uV C and uV C respectively the value of the VREF voltage 1 195V has to be taken into account when transitioning to PPM C and PPM C This means that PPMC 26 84 TC1 1 195 and PPMC2 1374 TC2 1 195 Temperature Compensation The CE provides the bandgap temperature to the MPU which then may digitally compensate the power outputs for the temperature dependence of VREF using the CE register GAIN ADJ Since the band gap amplifier is chopper stabilized via the EN bits the most significant long term drift mechanism in the voltage reference is removed The MPU not the CE is entirely in charge of providing temperature compensation The MPU applies the following formula to determine GAIN ADJ address 0x12 In this formula TEMP X is the deviation from nominal or calibr
42. Condition Min Typ Max Unit Maximum Output Power to Crystal Crystal connected 1 uW XIN to XOUT Capacitance 3 pF Capacitance to XIN 5 pF XOUT 5 pF 5 4 10 VREF VBIAS Unless otherwise specified VREF_DIS 0 Parameter Condition Min Typ Max Unit VREF output voltage VNOM 25 Ta 22 C 1 193 1 195 1 197 V VREF chop step 50 mV VREF CAL 1 VREF output impedance 10 pA 10 pA 2 5 kQ definition VREF 22 T 22 TC1 T 22 2 V VREF temperature coefficients TC1 7 0 uV 2C TC2 0 341 uV c VREF aging 25 year VREF T deviation from VNOM T je VREF T VNOM T 10 40 to 85 40 40 PRO VNOM 62 25 C 1 1 6 1 V VBIAS voltage Ta 40 C to 85 4 16 44 v This relationship describes the nominal behavior of VREF at different temperatures 5 4 11 LCD Drivers Applies to all COM and SEG pins Parameter Condition Min Typ Max Unit VLC2 Max Voltage With respect to VLCD 0 1 0 1 V VLC1 Voltage bias With respect to 2 VLC2 3 4 0 96 Ye bias With respect to VLC2 2 3 2 VLCO Voltage 7 bias With respect to VLC2 3 3 2 Ve bias With respect to VLC2 2 3 2 VLCD is V3P3SYS in MISSION mode VBAT BROWNOUT and LCD modes 5 4 12 92 Rev 1 1 DS 6612 001 78M6612 Data Sheet ADC Converter V3P3A Referenced FIR LEN 0 VREF_DIS 0 LSB values do not include the 9 bit left shift at CE input
43. External interrupt 5 EX6 SFR B8 5 IEX6 SFR External interrupt 6 EX XFER 2002 0 IE XFER SFR 8 0 XFER BUSY interrupt int 6 EX RTC 2002 1 IE RTC SFR 8 1 RTC 1SEC interrupt int 6 IE FWCOLO SFR 8 3 FWCOLO interrupt int 2 EX FWCOL 2007 4 IE FWCOLI SFR 8 2 FWCOLt1 interrupt int 2 IE PLLRISE SFRE8 6 PLL_OK rise interrupt int 4 EX_PLL 2007 5 IE PLLFALL SFRES 7 PLL OK fall interrupt int 4 IE WAKE SFRE8 5 AUTOWAKE flag The AUTOWAKE flag bit is shown in Table 31 because it behaves similarly to interrupt flags even though it is not actually related to an interrupt This bit is set by hardware when the MPU wakes from a rising edge on wake timer timeout The bit is reset by writing a zero Each interrupt has its own flag bit which is set by the interrupt hardware and is reset automatically by the MPU interrupt handler 0 through 5 BUSY RTC_1SEC which are OR ed together have their own enable and flag bits in addition to the interrupt 6 enable and flag bits see Table 31 and these interrupts must be cleared by the MPU software When servicing the XFER_BUSY and RTC_1SEC interrupts special care must be taken to JA avoid lock up conditions If for example the XFER_BUSY interrupt is serviced control must not return to the main program without checking the RTC_ISEC flag If this rule is ignored a 5 RTC_1SEC interrupt appearing during the XFER_BUSY service routine will disabl
44. I O RAM Map In Numerical sss ener 73 Table 49 SFR Map In Numerical Order 2 74 Table 50 I O RAM Map Alphabetical nnne enne 75 Rev 1 1 DS_6612_00 1 78 6612 Data Sheet VREF V3P3A GNDA V3P3SYS AX ADC IA gt CONVERTER V3P3D gt VBIAS VBIAS gt VB gt VBAT gt gt L_ V3P3D gt gt c FIR ADC E VREF VBAT TEMP VREF MUX VREF CAL FIR LEN VREF DIS MUX cross A CTRL es EQU 1 CK32 MUX_ALT VOLT CHOP_E REG MUX_DIV OSC RTCLK 32KHz 2 DIV XIN 82KHz gt PL Mu ADC lt 4 LCD_ONLY GNDD SLEEP XOUT CKADO 4 9 CKTEST CKOUT z 2 5 SEGI9 4 9MHz 2 5V to logic V3P3D CK_GEN CK 2X 1 LCD GEN 2 ECK DIS MPU_DIV CE RAM VLCI 0 5 MUX SYNC LCD MODE P STRT L J WPULSE LCD_E gt VARPULSE MUX CKCE SEG13 and SEG 14 5 CE lt 4 9MHz gt
45. MAXWIDTH 1 81 4 203ns 65 9us PLS MAXWIDTH 131 5us If the pulse period corresponding to the pulse rate exceeds the desired pulse width a square wave with 5096 duty cycle is generated Rev 1 1 13 78 6612 Data Sheet DS 6612 001 The CE pulse output polarity is programmable to be either positive or negative Pulse polarity may be inverted with PLS INV When this bit is set the pulses are active high rather than the more usual active low 1 3 4 CE Functional Overview The ADC processes one sample per channel per multiplexer cycle Figure 4 shows the timing of the samples taken during one multiplexer cycle The number of samples processed during one accumulation cycle is controlled by the I O RAM registers PRE SAMPS 0x2001 7 6 and SUM CYCLES 0x2001 5 0 The integration time for each energy output is PRE SAMPS SUM CYCLES 2520 6 where 2520 6 is the sample rate Hz for demo firmware 6612 OMU S2 URT V1 07 For example PRE SAMPS 42 and SUM CYCLES 50 will establish 2100 samples per accumulation cycle PRE SAMPS 100 and SUM CYCLES 21 will result in the exact same accumulation cycle of 2100 samples or 833 ms After an accumulation cycle is completed the XFER BUSY interrupt signals to the MPU that accumulated data are available 1 32768Hz 30 518ys 13 32768Hz 3975 Figure 4 Samples from Multiplexer Cycle The end of each multiplexer cycle is signaled
46. R W Invert TX1 when 1 This inversion occurs before modulation TXIMOD 2008 1 0 0 R W Enables modulation of TX1 When is set TX1 is modulated when it would otherwise have been zero The modulation is applied after any inversion caused by TXIINV PLL_OK 2003 6 0 0 Indicates that system power is present and the clock generation PLL is settled PLS_MAXWIDTH 2080 7 0 FF FF R W Determines the maximum width of the pulse low going 7 0 pulse Maximum pulse width is 2 PLS_MAXWIDTH 1 Where T is PLS INTERVAL If PLS_INTERVAL 0 T is the sample time 397us If 255 disable MAXWIDTH PLS INTERVAL 2081 7 0 0 0 R W If the FIFO is used PLS INTERVAL must be set to 81 f 7 0 PLS INTERVAL 0 the FIFO is not used and pulses are output as soon as the CE issues them PLS INV 2004 6 0 0 R W Inverts the polarity of WPULSE and VARPULSE Normally these pulses are active low When inverted they become active high PREBOOT SFRB2 7 R Indicates that preboot sequence is active The duration of the pre summer in samples PRE_SAMPS 1 0 2001 7 6 0 0 R W 00 42 01 50 10 84 11 100 RTC_SEC 5 0 2015 R W The RTC interface These the year month day RTC_MIN 5 0 2016 R W hour minute and second parameters of the The RTC_HR 4 0 2017 R W RTC is set by writing to these registers Year 00 and all RTC DAY 2 0 2018 R W others
47. Ri or MOVX A DPTR instruction SFR USR2 provides the upper 8 bytes for the MOVX A Ri instruction Clock Stretching MOVX instructions can access fast or slow external RAM and external peripherals The three low order bits of the CKCON register define the stretch memory cycles Setting all the CKCON stretch bits to one allows access to very slow external RAM or external peripherals Table 4 shows how the signals of the External Memory Interface change when stretch values are set from 0 to 7 The widths of the signals are counted in MPU clock cycles The post reset state of the CKCON register which is in bold in the table performs the MOVX instructions with a stretch value equal to 1 16 Rev 1 1 DS 6612 001 78M6612 Data Sheet Table 4 Stretch Memory Cycle Width CKCON Register Stretch Read Signals Width Write Signal Width CKCONI2 CkcoN 1 Value memaddr memrd memaddr memwr 0 0 0 0 1 1 2 1 0 0 1 1 2 2 3 1 0 1 0 2 3 3 4 2 0 1 1 3 4 4 5 3 1 0 0 4 5 5 6 4 1 0 1 5 6 6 7 5 1 1 0 6 7 7 8 6 1 1 1 7 8 8 9 7 There are two types of instructions differing in whether they provide an eight bit or sixteen bit indirect address to the external data RAM In the first type MOVX A Ri the contents of RO or R1 in the current register bank provide the eight lower ordered bits of address The eight high ordered bits of address are specified with the USR2 SF
48. SDATA output Z HiZ BUSY bit BUSY bit Figure 12 3 Wire Interface Write Command when CNT 0 EECTRL Byte Written 5 CNT Cycles 6 shown Write With HiZ and WFR 4 SCLK output SDATA out in 7 X 16 5 D4 X D3 BUSY READY 6520 From EEPROM M9 SDATA output Z LoZ HiZ BUSY bit 3 Figure 13 3 Wire Interface Write Command when HiZ 1 WFR 1 Rev 1 1 47 78M6612 Data Sheet DS 6612 001 1 5 11 Hardware Watchdog Timer In addition to the basic watchdog timer included in the 80515 MPU an independent robust fixed duration watchdog timer WDT is included in the device It uses the RTC crystal oscillator as its time WDT dis and must be refreshed by the MPU firmware at least every 1 5 abled seconds When not refreshed on time the WDT overflows and the part is reset as if the RESET pin were pulled high except that the I O RAM bits will be in the same state as after a wake up from SLEEP or LCD modes see Section 4 3 I O RAM Description for a list of I O Normal RAM bit states after RESET and wake up 4100 oscillator cycles or 125 ms after the WDT overflow the MPU will be launched from 0 0000 enabled V1 V3P3 V3P3 10mV V3P3 400mV A status bit WD OVF is set when WDT overflow occurs This bit is powered by the non volatile supply and can be read by the MPU to determine if the par
49. SEG5 SEG26 DIO6 SEG37 DIO17 SEG25 DIO5 COMO SEG24 DIO4 1 ICE E COM2 SEG18 COMS SEG17 e T PPEEEPEPPPPEEREM NONNO CO OOOO NNN 0 Figure 42 64 Pin LQFP Pinout Rev 1 1 97 78 6612 Data Sheet DS 6612 001 6 1 2 Package Outline LQFP 64 11 7 12 3 BREBRRBRRBRRBRRR 11 7 12 3 A BEHH PIN No 1 Indicator 0 00 0 20 1 40 0 50 0 14 160 0 60 0 28 ue NOTE Controlling dimensions are in mm 98 Rev 1 1 DS 6612 001 78M6612 Data Sheet 6 1 3 Recommended PCB Land Pattern for the LQFP 64 Package
50. data memory address is always 1 byte wide and can be accessed by either direct or indirect addressing The Special Function Registers occupy the upper 128 bytes This SFR area is available only by direct addressing Indirect addressing accesses the upper 128 bytes of Internal RAM Internal Data Memory The lower 128 bytes contain working registers and bit addressable memory The lower 32 bytes form four banks of eight registers RO R7 Two bits on the program memory status word PSW select which bank is in use The next 16 bytes form a block of bit addressable memory space at bit addresses 0x00 0x7F All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing Table 5 shows the internal data memory map Rev 1 1 17 78 6612 Data Sheet DS 6612 001 Table 5 Internal Data Memory Map Addres Direct Addressing 5 Indirect Addressing OxFF 0x80 Special Function Registers SFRs RAM Ox7F 0x30 Byte addressable area Ox2F 0x20 Bit addressable area Ox1F 0x00 Register banks RO R7 1 4 2 Special Function Registers SFRs A map of the Special Function Registers is shown in Table 6 Table 6 Special Function Registers Locations nur Byte Addressable Hex Bin able Hex Bin X000 X001 X010 X011 X100 X101 X110 X111 F8 INTBITS FF FO B F7
51. derived from certain DIO pins see the DIO Ports section Since it takes 2 machine cycles to recognize a 1 to 0 event the maximum input count rate is 1 2 of the oscillator frequency There are no restrictions on the duty cycle however to ensure proper recognition of 0 or 1 state an input should be stable for at least 1 machine cycle The timers counters are controlled by the TCON Register Timer Counter Control Register TCON Table 15 The TCON Register MSB LSB TFI TRI TFO TRO IEI ITI IEO ITO Bit Symbol Function The Timer 1 overflow flag is set by hardware when Timer 1 overflows TCON 7 1 This flag can be cleared by software and is automatically cleared when an interrupt is processed TCON 6 TRI Timer 1 Run control bit If cleared Timer 1 stops Timer 0 overflow flag set by hardware when Timer 0 overflows This TCON 5 TFO flag can be cleared by software and is automatically cleared when an interrupt is processed TCON 4 TRO Timer 0 Run control bit If cleared Timer 0 stops TCONI 3 IEI Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is observed Cleared when an interrupt is processed Interrupt 1 type control bit Selects either the falling edge or low level TCONTAL n on input pin to cause an interrupt Interrupt 0 edge flag is set by hardware when the falling edge on ze external pin intO is observed Cleared when a
52. divisible by 4 are defined as leap years RTC_DATE 4 0 2019 R W SEC 00 to 59 RTC_MO 3 0 201A R W MIN 00 to 59 RTC YR 7 0 201B R W HR 001023 00 Midnight DAY 011007 01 Sunday DATE 01 to 31 MO 011012 YR 001099 Each write to one of these registers must be preceded by a write to 201F WE Rev 1 1 79 78 6612 Data Sheet DS 6612 001 Name Location Rst Wk Dir Description RTC DEC SEC RTC INC SEC 201C 1 201C 0 RTC time correction bits Only one bit may be pulsed at a time When pulsed causes the RTC time value to be incremented or decremented by an additional second the next time the SEC register is clocked The pulse width may be any value If an additional correction is desired the MPU must wait 2 seconds before pulsing one of the bits again Each write to one of these bits must be preceded by a write to 201F WE RTM E 2002 3 R W Real Time Monitor enable When 0 the RTM output is low This bit enables the 2 wire version of RTM RTMO 7 0 RTM1 7 0 RTM2 7 0 RTM3 7 0 2060 2061 2062 2063 R W Four RTM probes Before each CE code pass the values of these registers are serially output on the RTM pin The RTM registers are ignored when RTM_E 0 SECURE SFRB2 6 R W Enables security provisions that prevent external reading of Flash memory and CE program RAM This bit i
53. frequency CK32 by 150 The CE clock frequency is always CK32 150 or 4 9152 MHz where CK32 is the 32 kHz clock The MPU clock frequency is determined by MPU DIV and can be 4 9152 MHz 2 Hz where MPU DIV varies from 0 to 7 MPU DIV is 0 on power up This makes the MPU clock scalable from 4 9152 MHz down to 38 4 kHz The circuit also generates a 2x MPU clock for use by the emulator This 2x MPU clock is not generated when ECK DIS is asserted by the MPU The setting of MPU DIV is maintained when the device transitions to BROWNOUT mode but the time base in BROWNOUT mode is 28 672 Hz 1 5 3 Real Time Clock RTC The RTC is driven directly by the crystal oscillator It is powered by the either a battery or super capacitor that is connected to the VBAT pin If the battery or super capacitor is not used then the VBAT pin must be directly connected to the V3P3SYS pin The RTC consists of a counter chain and output registers The counter chain consists of seconds minutes hours day of week day of month month and year The RTC is capable of processing leap years Each counter has its own output register Whenever the MPU reads the seconds register all other output registers are automatically updated Since the RTC clock is not coherent to the MPU clock the MPU must read the seconds register until two consecutive reads are the same requires either 2 or 3 reads At this point all RTC output registers will have the correct time Regardle
54. is present Modulation is not available in BROWNOUT mode The TX MOD bit enables modulation The duty cycle is controlled by FDC 1 0 which can select 50 25 12 5 and 6 25 duty cycle A 6 25 duty cycle means TX1 is low for 6 2596 of the period The receive pin RX1 may need an analog filter when receiving modulated optical signals With modulation an optical emitter can be operated at higher current than nominal enabling it to increase the distance along the optical path If operation in BROWNOUT mode is desired the external components should be connected to V3P3D V3P3SYS Fuse AERE 78M6612 10 100 1 Phototransistor M a a OV3P3SYS 1 WN LEDY gt i TX 4 Figure 35 Connection for Optical Components 3 11 Connecting V1 and Reset Pins A voltage divider should be used to establish that V1 is in a safe range when the power measurement unit is in mission mode V1 must be lower than 2 9 V in all cases in order to keep the hardware watchdog timer enabled For proper debugging or loading code into the 78M6612 mounted on a PCB it is necessary to have a provision like the header shown above H1 in Figure 36 A shorting jumper on this header pulls V1 up to V3P3 disabling the hardware watchdog timer The parallel impedance of R1 and R2 should be approximately 8 to 10 kO in order to provide hysteresis for the power fault monitor
55. or 4 multiplexer states per cycle Multiplexer states above 4 are reserved and must not be used The multiplexer always starts at the beginning of its list and proceeds until MUX_DIV states have been converted The MUX_ALT bit requests an alternative multiplexer frame The bit may be asserted on any MPU cycle and may be subsequently de asserted on any cycle including the next one A rising edge on MUX_ALT will cause the multiplexer control circuit to wait until the next multiplexer cycle and implement a single alternate cycle The multiplexer control circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage VREF The multiplexer control circuit is clocked by CK32 the 32768 Hz clock from the PLL block and launches with each new pass of the CE program 1 2 2 A D Converter ADC A single delta sigma A D converter digitizes the voltage and current inputs to the 78 6612 The resolution of the ADC is programmable using the FIR LEN register as shown in Section 4 3 I O RAM Description ADC resolution can be selected to be 21 bits FIR_LEN 0 or 22 bits FIR_LEN 1 Conversion time is two cycles of CK32 with FIR_LEN 0 and three cycles with FIR_LEN 1 In order to provide the maximum resolution the ADC should be operated with FIR LEN 1 Accuracy and timing specifications in this data sheet are based on FIR_LEN 1 Rev 1 1 9 78 6612 Data Sheet DS 6612 001 Initiation of each ADC conversion is cont
56. register CE_LCTN 4 0 defines which 1 KB boundary contains the CE code Thus the first CE instruction is located at 1024 CE LCTN 4 0 The CE DRAM can be accessed by the FIR filter block the RTM circuit the CE and the MPU Assigned time slots are reserved for FIR RTM and MPU respectively to prevent bus contention for CE DRAM data access Holding registers are used to convert 8 bit wide MPU data to from 32 bit wide CE DRAM data and wait states are inserted as needed depending on the frequency of CKMPU The CE DRAM contains 128 32 bit words The MPU can read and write the CE DRAM as the primary means of data communication between the two processors Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE Table 2 CE DRAM Locations for ADC Results Address Hex Name Description 1000 Branch A current 1004 VA A voltage 1008 IB Branch B current 100C VB B voltage 1010 Not used 1014 Not used 1018 TEMP Temperature 101C VBAT Battery voltage 12 Rev 1 1 DS 6612 001 78M6612 Data Sheet The CE of the 78M6612 is aided by support hardware that facilitates implementation of equations pulse counters and accumulators This support hardware is controlled through I O RAM locations EQU equation assist D O PV and DIO PW pulse count assist and PRE SAMPS and SUM CYCLES accumulation assist PRE SAMPS and SUM CYCLES support a dual level accumulation scheme wh
57. resistors should be omitted as shown in Figure 38 and 22 pF capacitors to GNDD should be used for protection from EMI It is important to bring out the ICE E pin to the programming interface in order to create a way for reprogramming parts that have the Flash SECURE bit SFR OxB2 6 set Providing access to ICE E ensures that the part can be reset between erase and program cycles which will enable programming devices to reprogram the part The reset required is implemented with a watchdog timer reset i e the hardware WDT must be enabled Rev 1 1 71 78 6612 Data Sheet DS 6612 001 LCD Segments V3P3D optional 78M6612 ICE E 620 i 5 RST 620 O RXTX 1 O 620 22pF 22 22 i 1 Figure 38 External Components for the Emulator Interface 3 13 Crystal Oscillator The oscillator of the 78M6612 drives a standard 32 768 kHz watch crystal The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT Board layouts with minimum capacitance from XIN to XOUT will require less battery current Good layouts will have XIN and XOUT shielded from each other Q Since the oscillator is self biasing an external resistor m
58. those shown in Figure 9 through Figure 13 are then sent via EECTRL and EEDATA When the transaction is finished CS must be lowered At the end of a Read transaction the EEPROM will be driving SDATA but will transition to HiZ high impedance when CS falls The firmware should then immediately issue a write command with CNT 0 and HiZ 0 to take control of SDATA and force it to a low Z state EECTRL Byte Written INT5 CNT Cycles 6 shown Write No HiZ SOLK output T4 SDATA o SDATAouputZ N BUSY bi LLL Figure 9 3 Wire Interface Write Command HiZ 0 46 Rev 1 1 DS 6612 001 78M6612 Data Sheet Write With HiZ SCLK output SDATA output oo X os OA Ke SDATA output Z LoZ HiZ BUSY bit Figure 10 3 Wire Interface Write Command HiZ 1 EECTRL Byte Written 5 I CNT Cycles 6 shown EECTRL Byte Written 5 CNT Cycles 8 shown READ SCLK output SDATA input X gt X SDATA output Z HiZ BUSY bit Figure 11 3 Wire Interface Read Command EECTRL Byte Written INT5 not issued EECTRL Byte Written INT5 not issued Write No HiZ CNT Cycles 0 shown Write HiZ CNT Cycles 0 shown SCLK output SCLK output SDATA output SDATA output 771211112222 SDATA output Z LoZ
59. 12 LCD segment gt 3 common Figure 31 Connecting LCDs The LCD segment pins can be organized in the following groups 1 Seventeen pins are dedicated LCD segment pins SEGO to SEG13 SEG16 to SEG18 2 Four pins are dual function pins CKTEST SEG19 E_RXTX SEG38 E_TCLK SEG33 and E RST SEG32 3 Fourteen pins are available as combined DIO and segment pins SEG24 DIO4 to SEG31 DIO 1 1 SEG34 DIO14 to SEG37 DIO17 SEG39 DIO19 and SEG40 DIO20 4 The QFN 68 package adds an additional combination pin SEG41 DIO21 Also adds two additional LCD segment pins SEG13 and SEG14 The split between DIO and LCD use of the combined pins is controlled with the DIO register LCD NUM LCD NUM can be assigned any number between 0 and 18 The first dual purpose pin to be allocated as LCD is SEG41 DIO21 on the 68 pin QFN package Thus if LCD NUM 2 SEG41 and SEG 40 will be configured as LCD The remaining SEG39 to SEG24 will be configured as DIO19 to DIO4 DIO1 and DIC2 are always available if not used for UART1 Note that pins CKTEST SEG19 E RXTX SEG38 E TCLK SEG33 and E RST SEG32 are not affected by LCD NUM Table 46 and Table 47 show the allocation of DIO and segment pins as a function of LCD NUM for both package types 66 Rev 1 1 DS 6612 001 78M6612 Data Sheet Table 46 LCD and DIO Pin Assignment by LCD NUM for the QFN 68 Package
60. 12 01 12 10 12 11 ty LCD E 2021 5 0 B R W Enables the LCD display When disabled VLC2 VLC1 and VLCO are ground as are the COM and SEG outputs LCD MODE 2 0 2021 4 2 0 R W LCD bias mode 000 4 states bias 001 3 states bias 010 2 states 1 2 bias 011 3 states gt bias 100 static display LCD NUM 4 0 2020 4 0 0 R W Number of dual purpose LCD DIO pins to be configured as LCD This will be a number between 0 and 18 The first dual purpose pin to be allocated as LCD is SEG41 DIO21 SEG40 DIO20 on the 64 LQFP package Thus if LCD NUM 2 SEG41 and SEG 40 will be configured as LCD The remaining SEG39 to SEG24 will be configured as DIO19 to DIO4 DIO1 and DIO2 plus DIOS on the QFN 68 package are always available if not used for UARTI1 See tables in Application Section LCD ONLY 20A9 5 0 0 W Takes the 78M6612 to LCD mode Ignored if system power is present The part will awaken when autowake timer times out or when system power returns LCD SEGO 3 0 2030 3 0 0 R W LCD Segment Data Each word contains information for n from 1 to 4 time divisions of each segment In each word LCD SEGI9 3 0 2043 3 0 0 bit 0 corresponds to COMO on up to bit for LCD SEG24 3 0 2048 3 0 0 B R W These bits are preserved in LCD and SLEEP modes even if their pin is not configured as LCD_SEG38 3 0 2056 3 0 0 E SEG In this case they can be useful as general purpose non volati
61. 12 001 If there is no battery when system power returns the part will switch to mission mode when PLL OK rises All configuration bits will be in reset state and RTC and MPU RAM data will be unknown and must be initialized by the MPU 2 5 Wake Up Behavior As described above the 78M6612 will always wake up in mission mode when system power is restored Additionally the part will wake up in BROWNOUT mode when a timeout of the wake up timer occurs 2 5 1 Wake on Timer If the part is in SLEEP or LCD mode it can be awakened by the wake up timer Until this timer times out the MPU is in reset due to WAKE being low When the wake up timer times out the WAKE signal rises and within three crystal cycles the MPU begins to execute The MPU can determine whether the timer woke it by checking the AUTOWAKE interrupt flag JE WAKE The wake up timer begins timing when the part enters LCD or SLEEP mode Its duration is controlled by WAKE PRD 2 0 and WAKE RES WAKE RES selects a timer LSB of either 1 minute WAKE 5 1 or 2 5 seconds WAKE RES 0 PRD 2 0 selects a duration of from 1 to 7 LSBs The timer is armed by WAKE ARM 1 It must be armed at least three RTC cycles before SLEEP or LCD ONLY is initiated Setting WAKE ARM presets the timer with the values in WAKE RES and WAKE PRD and readies the timer to start when the MPU writes to SLEEP or LCD ONLY The timer is reset and disarmed whenever the MPU is awake Thus if it is desired
62. 12 001 78M6612 Data Sheet 4 4 7 5 CE Calibration Parameters The table below lists the parameters that are typically entered to effect calibration of measurement accuracy GF Name Default Description Address 0x08 CAL_IA 16384 These constants control the gain of their respective channels 0x09 CAL IB 16384 The nominal value for each parameters is 2 16384 The gain of each channel is directly proportional to its CAL 0x0A CAL VA 16384 parameter Thus if the gain of a channel is 196 slow CAL OxOB CAL VB 16384 should be scaled by 1 1 0 01 These two constants control the CT phase compensation No compensation occurs when PHADJ X 0 As PHADJ X is 0 0 A 0 increased more compensation lag is introduced Range 2 _1 If itis desired to delay the current by the angle PHAD 2 0022299 TAND at 60 Hz 0 1487 0 0131 TAN OxOD PHADJ B 0 X 2 0 0155 TANO at 50 Hz 0 1241 0 009695 TAN D 4 4 7 6 Other CE Parameters The table below shows CE parameters used for suppression of noise due to scaling and truncation effects SE Name Default Description Address P This parameter is added to the Watt calculation for element 0 0x12 QUANTA 0 to compensate for input noise and truncation LSB VMAX IMAX 1 8541 10 W This parameter is added to the Watt calculation for element 1 0x13 QUANTB 0 to com
63. 612 001 78M6612 Data Sheet the CHOP E bits The extra CK32 cycle allows time for the chopped VREF to settle During this cycle MUXSYNC is held high The leading edge of muxsync initiates a pass through the CE program sequence The beginning of the sequence is the serial readout of the four RTM words CHOP E has states positive reverse and chop In the positive state CROSS is held low In the reverse state CROSS is held high In the chop state CROSS is toggled near the end of each Mux Frame as described above It is desirable that CROSS take on alternate values at the beginning of each Mux cycle For this reason if chop state is selected CROSS will not toggle at the end of the last Mux cycle in a SUM cycle The internal bias voltage VBIAS typically 1 6 V is used by the ADC when measuring the temperature and battery monitor signals 1 2 5 Temperature Sensor The 78M6612 includes an on chip temperature sensor implemented as a bandgap reference It is used to determine the die temperature The MPU may request an alternate multiplexer cycle containing the temperature sensor output by asserting MUX ALT The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system see Section 3 3 Temperature Compensation 1 2 6 Battery Monitor The battery voltage is measured by the ADC during alternative multiplexer frames if the BME Battery Measure Enable b
64. 612 Demo Code creep function halts pulse generation CECONFIG bit Name Default Description 80 Number of consecutive voltage samples below SAG_THR 15 8 SAG CNT 0x50 before a sag alarm is declared The maximum value is 255 SAG THR is at address 0x14 7 0 Unused 6 0 Unused 5 0 Unused Selects outlet to be used for pulse generation 4 PULSESEL 0 0 1 B Current sensor selection 3 2 SENSORSEL 11 00 CT 11 Shunt When PULSE_SLOW 1 the pulse generator input is reduced by a factor of 64 When PULSE_FAST 1 the 1 PULSE_FAST 0 pulse generator input is increased 16x These two parameters control the pulse gain factor X see table below Allowed values are 1 or 0 Default is 01 X 6 64 0 PULSE_SLOW 0 4 4 7 CE Transfer Variables When the MPU receives the XFER_BUSY interrupt it knows that fresh data is available in the transfer variables The transfer variables can be categorized as Fundamental energy measurement variables Instantaneous RMS values Other measurement parameters Pulse generation variables Current shunt variables Calibration parameters 84 Rev 1 1 o grim o mo DS 6612 001 78M6612 Data Sheet 4 4 7 1 Fundamental Energy Measurement Variables The table below describes each transfer variable for fundamental energy measurement All variables are signed 32 bit integers Accumulated variables such as WSUM are internally scale
65. 6612 001 78M6612 Data Sheet Name Location Rst Wk Dir Description WAKE ARM 20A9 7 Arm the autowake timer Writing a 1 to this bit arms the autowake timer and presets it with the values presently in WAKE PRD and WAKE RES The autowake timer is reset and disarmed whenever the MPU is in MISSION mode or BROWNOUT mode The timer must be armed at least three RTC cycles before the SLEEP or LCD ONLY mode is commanded WAKE PRD 20A9 2 0 001 R W Sleep time Time WAKE_PRD 2 0 WAKE_RES Default 001 Maximum value is 7 WAKE_RES 20A9 3 R W Resolution of WAKE timer 1 1 minute 0 2 5 seconds WD_RST SFRES 7 WD timer bit Possible operations to this bit are Read Gets the status of the flag IE PLLFALL Write 0 Clears the flag Write 1 Resets the WDT WD OVF 2002 2 R W The WD overflow status bit This bit is set when the WD timer overflows It is powered by the non volatile supply and at bootup will indicate if the part is recovering from a WD overflow or a power fault This bit should be cleared by the MPU on bootup It is also automatically cleared when RESET is high WE 201F 7 0 Write operations on the RTC registers must be preceded by a write operation to WE Rev 1 1 81 78 6612 Data Sheet DS 6612 001 4 4 CE Interface Description 4 4 4 CE Program The CE program is supplied by Teridian as a data image t
66. 8 6612 Data Sheet DS 6612 001 System Power V3P3SYS V1 OK Battery Current MPU Mode WAKE MPU Clock Source i 2048 4096 CK32 cycles t i gt time Figure 22 Transition from BROWNOUT to MISSION Mode when System Power Returns V3P3SYS and VBAT V1_OK 20 4 Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal 1024 CK32 RESETZ gt cycles gt time Figure 23 Power Up Timing with V3P3SYS and VBAT Tied Together 58 Rev 1 1 DS 6612 001 78M6612 Data Sheet VBAT Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ VBAT_OK gt time Figure 24 Power Up Timing with VBAT Only 2 4 Fault and Reset Behavior Reset Mode When the RESET pin is pulled high all digital activity stops The oscillator and RTC module continue to run Additionally all RAM bits are set to their default states As long as V1 the input voltage at the power fault block is greater than VBIAS the internal 2 5 V regulator will continue to provide power to the digital section Once initiated the reset mode will persist until the reset timer times out signified by the internal signal WAKE rising This will occur in 4100 cycles of the real time clock after RESET goes low at which time the MPU will begin executing its preboot and boot sequences fro
67. ARTO depends on the setting of the Serial Port Control Register SOCON Table 13 The SOCON Register MSB LSB SMO SMI SM20 RENO 80 80 TIO RIO Bit Symbol Function SOCON 7 SMO These two bits set the UARTO mode Mode Description SMO SMI 0 N A 0 0 SOCONI6 SMI 1 8 bit UART 0 1 2 9 bit UART 1 0 3 9 bit UART 1 1 SOCON 5 SM20 Enables the inter processor communication feature SOCON 4 RENO If set enables serial reception Cleared by software to disable reception SOCON 3 8 The 9 transmitted data bit in Modes 2 and 3 Set or cleared by the MPU depending on the function it performs parity check multiprocessor communication etc SOCON 2 RB80 In modes 2 and 3 it is the 9 data bit received In Mode 1 if M20 is 0 RB80 is the stop bit In mode 0 this bit is not used Must be cleared by software SOCON 1 TIO Transmit interrupt flag set by hardware after completion of a serial transfer Must be cleared by software SOCON 0 RIO Receive interrupt flag set by hardware after completion of a serial reception Must be cleared by software 24 Rev 1 1 DS 6612 001 78M6612 Data Sheet Serial Interface 1 Control Register S7 CON The function of the serial port depends on the setting of the Serial Port Control Register SICON Table 14 The S7CON Register
68. CKCE 2 lt 4 9MHz Y LCD DISPLAY on 68 Pin Package 32 bit Compute DRIVER 4 Only TEST Engine a 5 ODE MEMORY SHARE cp yum COMO 3 LCD MODE F m m M E SEGO 18 CE LCD_E SEG32 33 QUEUE 000 7FF 1000 LCD BLKMAP sEG1938 SEG24 DIOA LCD SEG SEG31 DIO11 LCD_Y 0 3 SEG34 DIO14 pem TME DIGITAL SEG37 DIO17 z _ DIO_EEX PLS INTERVAL WPULSE c 9 DEVO SEG39 DIO19 PLS MAXWIDTH VARPULSE 2 DIR SEGA40 DIO20 CE LCTN gt 90101 2 T EEPROM DR eee 8 INTERFACE LCD NUM PRE_SAMPS DIO SUM CYCLES 2 RTC 5 L RTCLK CKMPU o RTC DEC SEC SOMES RTC_INC_SEC Dk CONFIGURATION SDCK PARAMETERS nX gt SDOUT CONFIG T UART 60007 68 Pin Package Only lt gt 501 2000 20 DATA DIO3 MPU 0000 FFFF DIO21 SEG41 RX1 SEHGAL 80515 0000 07 MPU XRAM DIO1 gt 2KB TX1 0000 MOD FLASH DIO2 lt lt lt PROG memory 32KB WPULSE 25 0000 7FFF VARPULSE TXINV FLSH66ZT VBIAS cm Y MPU RSTZ POWER FAULT J ae vij L 4423 TEST FAULTZ E FOCIX MUX TMUXOUT COMP_STAT E TCLK E_RST Open Drain E RXTX SEG38 lt gt ICE E January 14 2009 E TCLK SEG33 4 E RST SEG32 4 Figure 21 Functional Blocks in SLEEP Mode inactive blocks grayed out Rev 1 1 57 7
69. COMO Dedicated LCD segment output pins SEG 14 and SEG15 are only SEGO SEGIB 2 available on the 68 pin package Multi use pins configurable as either LCD SEG driver or DIO DIO4 SEG24 D104 SCK DIO5 SDA when configured as EEPROM interface WPULSE SEG31 DIO1 4 3 4 5 DIO6 VARPULSE DIO7 when configured as pulse outputs If unused these pins must be configured as DIOs and set to outputs by the firmware SEGS34 DIO14 Multi use pins configurable as either LCD SEG driver or DIO If unused SEGS37 DIO17 3 4 5 these pins must be configured as DIOs and set to outputs by the SEG39 D1019 firmware SEGA40 DIO20 Multi use pins configurable as LCD driver or DIO QFN 68 package only SEG44 DIO 21 3 4 5 If unused this pin must be configured as a DIO and set an output by the firmware E RXTX SEG38 1 4 5 Multi use pins configurable as either emulator port pins when ICE E E SEGUE ulled high or LCD SEG drivers when ICE E tied to GND E TCLKSEG33 O 4 5 79279 ICE enable When zero E RST E TCLK and E RXTX become SEG32 SEG33 and SEG38 respectively For production units this pin should be ICE E 2 pulled to GND to disable the emulator port This pin should be brought out to the programming interface in order to create a way for reprogramming parts that have the SECURE bit set CKTEST SEG1 45 Multi use pin configurable as either Clock PLL output or LCD segment 9 driver Can be ena
70. CON 0x87 0x00 UART Speed Control 28 TCON 0x88 0x00 Timer Counter Control 26 TMOD 0x89 0x00 Timer Mode Control 27 TLO 0x8A 0x00 Timer 0 low byte 27 TL1 0x8B 0x00 Timer 1 high byte 27 THO 0x8C 0x00 Timer 0 low byte 27 1 0x8D 0x00 Timer 1 high byte 27 CKCON 0 8 0x01 Clock Control Stretch 1 16 PI 0x90 OxFF Port 1 DIO1 21 DPS 0x92 0x00 Data Pointer select Register 17 SOCON 0x98 0x00 Serial Port 0 Control Register 24 SOBUF 0x99 0x00 Serial Port 0 Data Buffer 23 IEN2 0x9A 0x00 Interrupt Enable Register 2 32 SICON Ox9B 0x00 Serial Port 1 Control Register 25 SIBUF 0 9 0x00 Serial Port 1 Data Buffer 23 SIRELL 0 9 0x00 Serial Port 1 Reload Register low byte 23 P2 OxAO 0x00 Port 2 DIO2 21 IENO OxA8 0x00 Interrupt Enable Register 0 31 IPO 0 0 00 Interrupt Priority Register 0 29 SORELL OxAA OxD9 Serial Port 0 Reload Register low byte 23 IENI 0xB8 0x00 Interrupt Enable Register 1 31 9 0 00 Interrupt Priority Register 1 36 SORELH OxBA 0x03 Serial Port 0 Reload Register high byte 23 SIRELH OxBB 0x03 Serial Port 1 Reload Register high byte 23 USR2 OxBF 0x00 User 2 Port high address byte for MOVX Ri 16 IRCON 0xCO 0x00 Interrupt Request Control Register 33 T2CON 0xC8 0x00 Polarity for INT2 and INT3 32 PSW OxDO 0x00 Program Status Word 20 WDCON 0xD8 0x00 Baud Rate Control Register only WDCON 7 bit used 23 A OxEO 0x00 Accumulator 20 B OxFO 0x00 B Register 20 Rev 1 1 19 78 6612 Data She
71. Canyon Road Suite 100 Irvine CA 92618 5201 Telephone 714 508 8800 FAX 714 508 8878 Email omu support teridian com For a complete list of worldwide sales offices go to http www teridian com 106 Rev 1 1 DS 6612 001 78M6612 Data Sheet Revision History Revision Date Description 1 0 4 1 2009 First publication 1 1 5 6 2009 Replaced Figure 39 with improved performance data Miscellaneous editorial corrections 2009 Teridian Semiconductor Corporation All rights reserved Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation Simplifying System Integration is a trademark of Teridian Semiconductor Corporation MicroDAA is a registered trademark of Teridian Semiconductor Corporation All other trademarks are the property of their respective owners Teridian Semiconductor Corporation makes no warranty for the use of its products other than expressly contained in the Company s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein Accordingly the reader is cautioned to verify that this document is current by comparing it to the latest version on http ww
72. DS 6612 001 78M6612 Data Sheet 6 2 2 Package Outline PIN 1 DOT 2 00030050 6 300 0 050 ira PIN 1 IDENTIFICATION BY MARKING Exp DAP CHAMFER 0 500 X 45 y 0 40050 050 4 0 400 B xn 68L TZSLP 6 300 0 050 8 000 0 050 Exp DAP C8x8mm o 200 0 050 1 6 400 E Ref UP VIEW BOTTOM VIEW Dimensions Pin length is nominally 0 4mm min 0 3 mm max 0 4 mm Exposed pad is internally connected to Rev 1 1 101 78 6612 Data Sheet DS 6612 001 6 2 3 Recommended PCB Land Pattern for the QFN 68 Package Av 25 mm Si Ea d EI mu d 1 Eu KHHBBHHHBBHHEEBHHE y lt gt K G Recommended PCB Land Pattern Dimensions ER Typical Symbol Description Dimension e Lead pitch 0 4 mm Pad width 0 23 mm y Pad length See Note 3 0 8 mm d See Note 1 6 3 mm A 6 63 mm G 7 2mm Note 1 Do not place unmasked vias in region denoted by dimension d Note 2 Soldering of bottom internal pad is not required for proper operation Note 3 The y dimension has been elongated to allow for hand soldering and reworking Production assembly may allow this dimension to be reduced as long as th
73. ESET amp VBAT_OK SLEEP or VBAT_OK VBAT_OK RESET amp VBAT_OK Figure 18 Operation Modes State Diagram 2 3 2 LCD Mode In LCD mode the data contained in the LCD SEG registers is displayed i e up to four LCD segments connected to each of the pins SEG18 and SEG19 can be made to blink without the involvement of the MPU which is disabled in LCD mode This mode can be exited only by system power up or by a timeout of the wake up timer Figure 20 shows the functional blocks active in LCD mode 2 3 8 SLEEP Mode In SLEEP mode the battery current is minimized and only the Oscillator and RTC functions are active This mode can be exited only by system power up or by a timeout of the wake up timer Figure 21 shows the functional blocks active in SLEEP mode 54 Rev 1 1 DS 6612 001 78M6612 Data Sheet VREF V3P3A GNDA V3P3SYS AE ADC CONVERTER V3P3D p 50 VBIAS VBIAS VB gt VBAT VSP3A anann _ V3P3D m Pit
74. Eme MUX TMUXOU STAT E ined RST Open Drain 49 0 RESET E RXTX SEG38 ICE E January 14 2009 E TCLK SEG33 4 E RST SEG32 4 Figure 20 Functional Blocks in LCD Mode inactive blocks grayed out 56 Rev 1 1 DS 6612 001 78M6612 Data Sheet VREF V3P3A GNDA V3P3SYS AE ADC CONVERTER V3P3D IB 9 mux VBIAS VBIAS VB gt VBAT V3PSA ff _ V3P3D gt gt L FIR ADC_E VREF VBAT 4 VREF FIR LEN MUX VREF_CAL VBAT l VREF DIS A a MUX ae cross EQU 1 cK32 ALT VOLT CHOP E REG DIV osc RTCLK 32KHz MCK cK32 DIV XIN 32KHz gt PLL 4 LCD ONLY JGNDD SLEEP XOUT CKADC CKTEST E 4 9MHz d V2P5 SEG19 sz 9MHz 4 9MHz 2 5V to logic V3P3D CK_GEN CK 2X LCD GEN 2 ECK DIS MPU DIV CE RAM VLC1 0 5KB MUX SYNC VLCO STRT L J WPULSE LCD E J5VARPULSE MUX CKCE SEG13 and SEG 14
75. Frequency Frequenc Temperature Hz PPM 50 32767 98 0 61 25 32768 28 8 545 0 32768 38 11 597 25 32768 08 2 441 50 32767 58 12 817 The values show that even at nominal temperature the temperature at which the chip was calibrated for energy the deviation from the ideal crystal frequency is 11 6 PPM resulting in about one second inaccuracy per day i e more than some standards allow As Figure 29 shows even a constant compensation would not bring much improvement since the temperature characteristics of the crystal are a mix of constant linear and quadratic effects 32768 5 32768 4 32768 3 32768 2 32768 1 32768 32767 9 32767 8 32767 7 32767 6 32767 5 50 25 0 25 50 Figure 29 Crystal Frequency over Temperature One method to correct the temperature characteristics of the crystal is to obtain coefficients from the curve in Figure 29 by curve fitting the PPM deviations A fairly close curve fit is achieved with the coefficients a 10 89 b 0 122 and 0 00714 see Figure 30 a b 2 41 T f Snom 10 10 10 When applying the inverted coefficients a curve see Figure 30 will result that effectively neutralizes the original crystal characteristics 64 Rev 1 1 DS 6612 001 78M6612 Data Sheet 32768 5 32768 4 32768 3 32768 2 32768 1 32768 32767 9 32767 8 crystal 32767 7
76. IO pins can be implemented in software to accommodate various requirements In addition to the temperature trimmed ultra precision voltage reference the on chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on measurement and RTC accuracy e g to meet the requirements of ANSI and IEC standards Temperature dependent external components such as crystal oscillator current transformers CTs and their corresponding signal conditioning circuits can be characterized and their correction factors can be programmed to produce measurements with exceptional accuracy over the industrial temperature range if desired One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense configuration and can also function as a standard UART The optical output can be modulated at 38 kHz A block diagram of the IC is shown in Figure 1 A detailed description of various functional blocks follows 8 Rev 1 1 DS 6612 001 78M6612 Data Sheet 1 2 Analog Front End AFE The AFE of the 78M6612 is comprised of an input multiplexer a delta sigma A D converter and a voltage reference 1 2 1 Input Multiplexer The input multiplexer supports up to four input signals that are applied to pins IA VA IB and VB of the device Additionally using the alternate mux selection it has the ability to select temperature and the battery volt
77. IRCON 0 JA Only and TF timer 0 and timer 1 overflow flag will be automatically cleared by hardware when the service routine is called Signals and T1ACK port ISR active high when the service routine is called 1 4 9 2 External Interrupts The 78 6612 MPU allows seven external interrupts These are connected as shown in Table 30 The direction of interrupts 2 and 3 is programmable in the MPU Interrupts 2 and 3 should be programmed for falling sensitivity The generic 8051 MPU literature states that interrupt 4 through 6 are defined as rising edge sensitive Thus the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 30 Table 30 External MPU Interrupts Connection Polarity ae 0 Digital I O High Priority see DIO_Rx automatic 1 Digital Low Priority see DIO_Rx automatic 2 FWCOLO FWCOL1 falling automatic 3 CE_BUSY falling automatic 4 PLL_OK rising PLL_OK falling rising automatic 5 EEPROM busy falling automatic 6 XFER_BUSY OR RTC_1SEC falling manual FWCOLx interrupts occur when the CE collides with a Flash write attempt See the Flash write description in Section 1 5 5 for more detail SFR special function register enable bits must be set to permit any of these interrupts to occur Likewise each interrupt has its own flag bit which is set by the inter
78. NT4 2 IE PLLFALL IFLAGS E8 WD RST IE PLLRISE IE WAKE Reserved FWCOLI UE FWCOLO IE IE XFER Flash ERASE 94 FLSH ERASE 7 0 FLSHCTL B2 PREBOOT SECURE Not Used Not Used Not Used Not Used FLSH_MEEN FLSH PWE FPAG B7 FLSH PGADR 6 0 Not Used Serial EEPROM EEDATA 9E EEDATA 7 0 EECTRL 9F EECTRL 7 0 Only available on QFN 68 package Reserved in the LQFP 64 package 74 Rev 1 1 DS 6612 001 78M6612 Data Sheet 4 3 I O RAM Description Alphabetical Order Bits with a W write direction are written by the MPU into configuration RAM Typically they are initially stored in Flash memory and copied to the configuration RAM by the MPU Some of the more frequently programmed bits are mapped to the MPU SFR memory space The remaining bits are mapped to the address range 0x2xxx Bits with read direction can be read by the MPU Columns labeled Rst and Wk describe the bit values upon reset wake respectively No entry in one of these columns means the bit is either read only or is powered by the non volatile supply and is not initialized Write only bits will return zero when they are read Table 50 I O RAM Map Alphabetical Order Name Location Rst Wk Dir Description ADC E 2005 3 0 0 R W Enables ADC and VREF When disabled removes bias current BME 2020 6 0 B R W Battery Measure Enable When set a load current is immedi
79. PU boot code are called the preboot phase because during this phase the ICE is inhibited A read only status bit PREBOOT identifies these cycles to the MPU Upon completion of preboot the ICE can be enabled and is permitted to take control of the MPU SECURE the security enable bit is reset whenever the chip is reset Hardware associated with the bit permits only ones to be written to it Thus preboot code may set SECURE to enable the security feature but may not reset it Once SECURE is set the preboot code is protected and no external read of program code is possible 48 Rev 1 1 DS 6612 001 78M6612 Data Sheet Specifically when SECURE is set e The ICE is limited to bulk Flash erase only e zero of Flash memory the preferred location for the user s preboot code may not be page erased by either MPU or ICE Page zero may only be erased with global Flash erase e Writes to page zero whether by MPU or ICE are inhibited the part via the ICE interface if no mechanism for actively resetting the part between reset and The SECURE bit is to be used with caution Inadvertently setting this bit will inhibit access to erase operations is provided 1 5 13 Test Ports TMUXOUT Pin One out of 16 digital or 8 analog signals can be selected to be output on the TMUXOUT pin The function of the multiplexer is controlled with the I O RAM register TMUX 0x20AA 4 0 as shown in Table 43 Table 43 TMUX 4 0 Selections
80. R This method allows the user paged access 256 pages of 256 bytes each to all ranges of the external data RAM In the second type of MOVX instruction MOVX A DPTR the data pointer generates a sixteen bit address This form is faster and more efficient when accessing very large data arrays up to 64 Kbytes since no additional instructions are needed to set up the eight high ordered bits of address It is possible to mix the two MOVX types This provides the user with four separate data pointers two with direct access and two with paged access to the entire 64 KB of external memory range Dual Data Pointer The Dual Data Pointer accelerates the block moves of data The standard Data Pointer DPTR is a 16 bit register DPH DPL that is used to address external memory or peripherals In the 80515 core the standard data pointer is called DPTR the second data pointer is called DPTR1 DPHI DPLI The data pointer select bit chooses the active pointer The data pointer select bit is located at the LSB of the DPS register DPS 0 DPTR is selected when DPS 0 0 and DPTR1 is selected when DPS 0 1 The user switches between pointers by toggling the LSB of the DPS register All data pointer related instructions use the currently selected data pointer for any activity The second data pointer may not be supported by certain compilers Internal Data Memory The Internal data memory provides 256 bytes 0x00 to OxFF of data memory The internal
81. Sequence gt 1 UART1 EM l p optical gt EE mm Flash E m gt _ n iA _ CE_BUSY gt PLL OK fam gt Interrupt Vecto r di UARTO gt 1 EEPROM 12 gt 8 15 ELE v v DEDE OS DEL 8 Figure 6 Interrupt Structure 38 Rev 1 1 DS 6612 001 78M6612 Data Sheet 1 5 On Chip Resources 1 5 4 Oscillator The 78M6612 oscillator drives a standard 32 768 kHz watch crystal These crystals are accurate and do not require a high current oscillator circuit The 78M6612 oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability 1 5 2 PLL and Internal Clocks Timing for the device is derived from the 32 768 kHz oscillator output On chip timing functions include the MPU master clock a real time clock RTC and the delta sigma sample clock In addition the MPU has two general counter timers The ADC master clock CKADC is generated by an on chip PLL It multiplies the oscillator output
82. U XRAM TX1 0000 MOD FLASH DIO2 RXDIS PROG memory 7FFF 32KB WPULSE aa pe y 0000 7FFF SHARE CE_LCTN VARPULSE OPT TXINV VBIAS Y MPU RSTZ POWER FAULT _ WAKE EMULATOR PORT L lt ___ TEST FAULTZ E RXT MUX TMUXOUT COMP_STAT E ere Open Drain 14 07 RESET E_RXTX SEG38 lt gt ICE_E January 14 2009 E_TCLK SEG33 4 E RST SEG32 4 Figure 19 Functional Blocks in BROWNOUT Mode inactive blocks grayed out Rev 1 1 55 78 6612 Data Sheet DS 6612 001 VREF V3P3A GNDA V3P3SYS AE ADC CONVERTER VES V3P3D pL mux VBIAS gt VB gt VBAT VSPSA B0 VA _ V8P3D gt gt FIR ADC E VREF VBAT TEMP m e VREF FIR_LEN MUX VREF_CAL l VREF DIS A A MUX cross CTRL EQU L CK32 Muar MUX_DIV REG osc MCK DIV RTCLK 32KHz CK32 XIN 32KHz gt PLL a ADC lt 1m GNDD SLEEP XOUT CKADC 4 9MH CKTEST KOUTA
83. VARSUM_X internal pulse generation The I O RAM bits DIO PV and DIO PW as described in the Section 1 5 7 Digital can be programmed to route WPULSE to the output pin DIO6 and VARPULSE to the output pin DIO7 Pulses can also be output on TX1 see TX7E 1 0 for details During each CE code pass the hardware stores exported sign bits in an 8 bit FIFO and outputs them at a specified interval This permits the CE code to calculate all of the pulse generator outputs at the beginning of its code pass and to rely on hardware to spread them over the MUX frame The FIFO is reset at the beginning of each MUX frame PLS INTERVAL controls the delay to the first pulse update and the interval between subsequent updates Its LSB is four CK FIR cycles or 4 203ns If PLS INTERVAL is zero the FIFO is deactivated and the pulse outputs are updated immediately Thus NINTERVAL is 4 PLS INTERVAL For use with the standard CE code supplied by Teridian 5 INTERVAL is set to a fixed value of 81 PLS INTERVAL is specified so that all of the pulse updates are output before the MUX frame completes On chip hardware provides a maximum pulse width feature PL MAXWIDTH 7 0 selects a maximum negative pulse width to be Nmax updates per multiplexer cycle according to the formula Nmax 2 PLS MAXWIDTH41 lf PLS_MAXWIDTH 255 no width checking is performed Given that PLS INTERVAL 81 the maximum pulse width is determined by Maximum Pulse Width 2 PLS
84. W R W JA Only byte operations on the whole WDI x register should be used when writing S The byte must have all bits set except the D bits that are to be cleared The multi purpose register WDI contains the following bits Bit JE XFER XFER Interrupt Flag This flag monitors the XFER_BUSY interrupt It is set by hardware and must be cleared by the interrupt handler Bit 1 JE RTC RTC Interrupt Flag This flag monitors the RTC_1SEC interrupt It is set by hardware and must be cleared by the interrupt handler Bit 7 WD RST WD Timer Reset Read Reads the PLL FALL interrupt flag Write 0 Clears the PLL FALL interrupt flag Write 1 Resets the watch dog timer INTBITS INTO INT6 OxF8 Interrupt inputs The MPU may read these bits to see the input to external interrupts INTO INT1 up to INT6 These bits do not have any memory and are primarily intended for debug use 22 Rev 1 1 DS 6612 001 78M6612 Data Sheet 1 4 5 Instruction Set All instructions of the generic 8051 microcontroller are supported A complete list of the instruction set and of the associated op codes is contained in the Teridian 78M6612 Firmware Developer s Manual 1 4 6 UARTs The 78M6612 includes a UART UARTO that can be programmed to communicate with a variety of external devices A second UART UART1 is connected to the optical port as described in Section 1 5 6 Optical Interface The UARTS are dedi
85. age The multiplexer can be operated in two modes e During a normal multiplexer cycle the signals from the IA IB VA and VB pins are selected e During the alternate multiplexer cycle the temperature signal TEMP and the battery monitor are selected along with the signal sources shown in Table 1 To prevent unnecessary drainage on the battery the battery monitor is enabled only with the BME bit 0x2020 6 in the RAM The alternate mux cycles are usually performed infrequently e g every second by the MPU In order to prevent disruption of the voltage tracking PLL and voltage allpass networks VA is not replaced in the ALT mux selections Table 1 details the regular and alternative MUX sequences Missing samples due to an ALT multiplexer sequence are filled in by the CE Table 1 Inputs Selected in Regular and Alternate Multiplexer Cycles Regular MUX Sequence ALT MUX Sequence Mux State Mux State EQU 0 1 2 3 0 1 2 3 2 IA VA IB VB TEMP VA IB VBAT In a typical application IA and IB are connected to current sensors that sense the current on each branch of the line voltage VA and VB are typically connected to voltage sensors through resistor dividers The multiplexer control circuit handles the setting of the multiplexer The function of the control circuit is governed by the I O RAM registers MUX_ALT MUX_DIV and EQU MUX_DIV controls the number of samples per cycle It can request 2 3
86. ash at maximum 9 1 10 mA Write Flash rate CE_E 0 ADC_E 0 VBAT 3 6V BROWNOUT mode lt 25 C 48 120 pA BROWNOUT mode lt gt 5 65 150 pA t VET CUNEN LCD Mode 25 C 57 85 uA LCD mode over temperature 15 SLEEP Mode 25 C 2 9 5 0 uA Sleep mode over temperature 10 uA Current into V3P3A and V3P3SYS pins is not zero if voltage is applied at these pins in brownout LCD or sleep modes 5 4 6 V3P3D Switch Parameter Condition Min Typ Max Unit On resistance V3P3SYS to V3P3D lyaesp lt 1 MA 10 Q On resistance VBAT to V3P3D lt 1 MA 40 Q 5 4 7 2 5V Voltage Regulator Unless otherwise specified load 5 mA Parameter Condition Min Typ Max Unit Reduce V3P3 until Voltage overhead V3P3 V2P5 V2P5 drops 200 mV 440 mV PSSR AV2P5 AV3P3 RESET 0 iload 0 3 3 mV V 5 4 8 Low Power Voltage Regulator Unless otherwise specified V3P3SYS V3P3A 0 Parameter Condition Min Typ Max Unit V2P5 ILOAD 0 2 0 2 5 2 7 V V2P5 load regulation ILOAD 0 mA to 1 mA 30 mV ILOAD 1 mA VBAT voltage requirement Reduce VBAT until 3 0 V REG LP 0 PSRR AV2P5 AVBAT ILOAD 0 50 50 mV V Rev 1 1 91 78 6612 Data Sheet DS 6612 001 5 4 9 Crystal Oscillator Parameter
87. ately applied to the battery and it is connected to the ADC to be measured on Alternative Mux Cycles See ALT bit E 2000 4 0 0 R W CE enable CE LCTN 4 0 20A8 4 0 31 31 R W CE program location The starting address for the CE program is 1024 CE_LCTN CE_LCTN must be defined before the CE is enabled CHOP_E 1 0 2002 5 4 0 0 R W Chop enable for the reference bandgap circuit The value of CHOP will change on the rising edge of MUXSYNC according to the value in E 00 toggle 01 positive 10 reversed 11 toggle except at the mux sync edge at the end of SUMCYCLE CKOUT E 1 0 2004 5 4 00 00 R W CKTEST Enable The default is 00 00 SEG19 01 CK FIR 5 MHz Mission 32 kHz Brownout 10 Not allowed reserved for production test 11 Same as 10 D COMP STAT 0 2003 0 The status of the power fail comparator for V1 DIO R1 2 0 2009 6 4 0 0 R W Connects dedicated I O pins DIO2 through DIO11 as well DIO R2 2 0 200A 2 0 0 0 as input pin DIO1 to internal resources DIO R3 2 0 is DIO R3 2 0 200A 6 4 0 0 only available in the 68 pin package If more than one DIO R4 2 0 200B 2 0 0 0 input is connected to the same resource the MULTIPLE DIO R5 2 0 200B 6 4 0 0 column below specifies how they are combined DIO R6 2 0 200C 2 0 0 0 DIO R7 2 0 200C 6 4 0 0 DIO Rx Resource Multiple 000 NONE DIO_R8 2 0 200D 2 0 0 0 001 R J OR
88. ation temperature expressed in multiples of 0 1 TEMP _ X PPMC TEMP _ X PPMC2 24 2 GAIN _ ADJ 16385 In a power and energy measurement unit the 78M6612 is not the only component contributing to temperature dependency A whole range of components e g current transformers resistor dividers power sources filter capacitors will contribute temperature effects Since the output of the on chip temperature sensor is accessible to the MPU temperature compensation mechanisms with great flexibility are possible MPU access to GAIN ADJ permits a system wide temperature correction over the entire unit rather than local to the chip Rev 1 1 63 78 6612 Data Sheet DS 6612 001 3 4 Temperature Compensation and Mains Frequency Stabilization for the RTC The flexibility provided by the MPU allows for compensation of the RTC using the substrate temperature To achieve this the crystal has to be characterized over temperature and the three coefficients Y CAL Y CALC and Y CAL C2 have to be calculated Provided the IC substrate temperatures tracks the crystal temperature the coefficients can be used in the MPU firmware to trigger occasional corrections of the RTC seconds count using the DEC SEC INC SEC registers in RAM Example Let us assume a crystal characterized by the measurements shown in Table 45 Table 45 Frequency over Temperature Deviation from Measured m Nominal
89. ble int 4 or more precisely because PLL_OK fell Note this bit will not be set if the part wakes c into BROWNOUT mode because of the N WAKE timer Firmware must write a zero to this bit to clear it IE XFER IE RTC SFRE8 0 SFRE8 1 R W Interrupt flags These flags monitor the XFER_BUSY interrupt and the RTC_1SEC interrupt The flags are set by hardware and must be cleared by the interrupt handler Note that IE6 the interrupt 6 flag bit in the MPU must also be cleared when either of these interrupts occur IE_WAKE SFRES 5 R W Indicates that the MPU was woken by the autowake timer This bit is typically read by the MPU on bootup Firmware must write a zero to this bit to clear it Rev 1 1 77 78 6612 Data Sheet DS 6612 001 Name Location Rst Wk Dir Description INTBITS SFRF8 6 0 R W Interrupt inputs The MPU may read these bits to see the input to external interrupts INTO INT1 up to INT6 These bits do not have any memory and are primarily intended for debug use LCD BLKMAPI9 3 0 205A 7 4 0 R W Identifies which segments connected to SEG18 and LCD_BLKMAP18 3 0 205A 3 0 SEG19 should blink 1 means blink Most significant bit corresponds to COMG Least significant to COMO LCD CLK I 0 2021 1 0 0 R W Sets the LCD clock frequency for COM SEG pins not frame rate JA x Note fy 32768 Hz cw 007
90. bled and disabled by CKOUT EN TMUXOUT 4 Digital output test multiplexer Controlled by TMUX 4 0 Multi use pin configurable as UART1 Input or general DIO When con figured as RX1 this pin can optionally receive a signal from an external RX1 DIO1 3 4 7 photo detector used in an IR serial interface If unused this pin must be terminated to V3P3D or GNDD or configured as a DIO and set to an output by the firmware Multi use pin configurable as a transmit output from UART1 or optionally an Optical LED Transmit Output WPULSE RPULSE or general DIO TX1 DIO2 3 4 When configured as TX1 this pin is capable of directly driving an LED for transmitting data in an IR serial interface If unused this pin must be left open or configured as a DIO and set to an output by the firmware DIO3 3 4 DIO pin QFN 68 package only This input pin resets the chip into a known state For normal operation this RESET 3 pin is connected to GNDD To reset the chip this pin should be pulled high No external reset circuitry is necessary Direct connect to ground in normal operation 3 UART input If unused this pin must be terminated to V3P3D or GNDD TXO 4 UART output TEST 7 Enables Production Test Must be grounded in normal operation 9 S Pin types P Power O Output Input I O Input Output The circuit number denotes the equivalent circuit as specified on the following page 104 Rev 1 1
91. cated 2 wire serial interfaces which can communicate with an external device at up to 38 400 bits s The operation of each pin is as follows e UART RX Serial input data are applied at this pin Conforming to RS 232 standard the bytes are input LSB first e UART TX This pin is used to output the serial data The bytes are output LSB first The 78M6612 has several UART related registers for the control and buffering of serial data The serial buffers consist of sets of two separate registers one set for each UART a transmit buffer SOBUF SIBUF and a receive buffer ROBUF RIBUF Writing data to the transmit buffer starts the transmission by the associated UART Received data are available by reading from the receive buffer Both UARTs can simultaneously transmit and receive data WDCON 7 selects whether timer 1 or the internal baud rate generator is used All UART transfers are pro grammable for parity enable parity 2 stop bits 1 stop bit and XON XOFF options for variable communication baud rates from 300 to 38 400 bps Table 11 shows how the baud rates are calculated Table 12 shows the selectable UART operation modes Table 11 Baud Rate Generation Using Timer 1 Using Internal Baud Rate Generator WDCONJ7 0 WDCON 7 1 UART 0 g5MOD 384 256 TH1 25 fopmpu 64 2 SORELY UART 1 N A foxmeu 32 2 9 SI REL SOREL and SIREL are 10 bit values derived by combining bits fro
92. ccuracy 96 Wh Accuracy 96 0 01 0 1 1 10 Current A Figure 39 Wh Accuracy 20 mA to 20 A at 120 V 60 Hz and Room Temperature Using a 4 mO Current Shunt Error 2 Harmonic Data 60Hz Harmonic Data o Measured at current distortion amplitude of 40 and voltage distortion amplitude of 10 Figure 40 Measurement Accuracy over Harmonics at 240 V 30A per IEC62053 2x 3 5 7 9 11 13 15 17 Harmonic Rev 1 1 95 78 6612 Data Sheet DS 6612 001 Relative Accuracy over Temperature Accuracy PPM C 60 40 20 0 20 40 60 80 100 Temperature C Figure 41 Typical Measurement Accuracy over Temperature Relative to 25 C 96 Rev 1 1 DS 6612 001 78M6612 Data Sheet 6 Packaging 6 1 64 LQFP Package 6 1 1 Pinout e ip x 0 zi a lt 02050 05 m m 95 lt 90 1 TY O O O LO 1O 1 LO LO GNDD 1 48 mm RESET E RXTX SEG38 mm 2 47mm V2P5 TX1 DIO2 um 3 46mm VBAT TMUXOUT 45 TXO mm 5 44 SEG40 D1020 SEG3 mm 6 43 mg SEG31 D1011 V3P3D 7 42 SEG30 DI010 SEG19 CKTEST mw 8 TERIDIAN 41 SEG29 DIO9 V3P3SYS 78M6612 IGT SEG28 DIO8 SEG4 SEG27 DIO7
93. ce of board 27410 pF Depending on trace capacitance higher or lower values for CXS and CXL must be used Capacitance from XIN to GNDD and XOUT to GNDD combining pin trace and crystal capacitance should be 35 pF to 37 pF 5 3 Recommended Operating Conditions Parameter Condition Min Typ Max Unit 3 3V Supply Voltage V3P3SYS Normal Operation 3 0 3 3 3 6 V Battery Back 0 3 6 V V3P3A and V3P3SYS must be at the same voltage No Battery Externally Connect to V3P3SYS Battery Backup VBAT BRN and LCD 3 0 3 8 V modes 2 0 3 8 V SLEEP mode Operating Temperature 40 85 C Maximum input voltage on DIO SEG MISSION mode V3P3SYS 0 3 V pins configured as DIO input BROWNOUT mode VBAT 0 3 V LCD mode VBAT 0 3 V Exceeding this limit will distort the LCD waveforms on other pins Rev 1 1 89 78 6612 Data Sheet DS_6612_001 5 4 Performance Specifications 5 4 1 Input Logic Levels Parameter Condition Min Typ Max Unit Digital high level input voltage 2 V Digital low level input voltage Vi 0 8 V Input pull up current VIN 0V ICE 1 E RXTX 10 100 RST CKTEST 10 100 uA Other digital inputs 1 0 1 uA Input pull down current IIH VIN V3P3D ICE_E 10 100 Other digital inputs 1 0 1 tin battery powered modes digital inputs should be below 0 3 V or above 2 5 V to minimize battery current
94. d by the JE PLLFALL interrupt flag in SFR OxE8 7 The transition in the other direction is signaled by the PLLRISE interrupt flag SFR OxE8 6 when the PLL becomes stable Transitions from both LCD and SLEEP mode back to BROWNOUT mode are initiated by wake up timer timeout conditions or wake up pin events In the absence of system power if the voltage margin for the LDO regulator providing 2 5 V to the internal circuitry becomes too low to be safe the part automatically enters sleep mode BAT OK false The battery voltage must stay above 3 V to ensure that BAT OK remains true Under this condition the 78M6612 stays SLEEP mode even if the voltage margin for the LDO improves BAT OK true Table 44 shows the circuit functions available in each operating mode 52 Rev 1 1 DS 6612 001 78M6612 Data Sheet 2 3 1 Table 44 Available Circuit Functions Circuit Function System Power Battery Power Non volatile Supply MISSION BROWNOUT LCD SLEEP CE Yes Data RAM Yes Yes FIR Yes Analog circuits Yes _ PLL ADC VREF BME etc 4 92 MHz 28 672 kHz MPU clock rate from PLL 7 8 of 32768 ES Hz MPU_DIV Yes ICE Yes Yes DIO Pins Yes Yes Watchdog Timer Yes Yes LCD Yes Yes Yes EEPROM Interface 2 Yes Yes 8kb s _ wire EEPROM Interface 3 Yes Yes 16kb s _ wire UART Yes Yes Optica
95. d so they have at least 2x margin before overflow when the integration time is 1 second Additionally the hardware will not permit output values to fold back upon overflow CE zs Address Name Description 0x74 WOSUM_X The sum of Watt samples from each measurement element n_8 is the gain configured by JA_SHUNT or IB_SHUNT Mem WISUM_X sp 1 67380 10 VMAX In 8 Wh 0x76 VAROSUM X The sum of VAR samples from each measurement element In 8 is the gain configured by SHUNT or IB SHUNT d VARISUM_X 5B 1 67380 1072 VMAX In 8 Wh WxSUM X is the Wh value accumulated for element X in the last accumulation interval and can be computed based on the specified LSB value For example with VMAX 600V and IMAX 52A LSB for WxSUM X is 0 005222 Wh 4 4 7 2 Instantaneous Energy Measurement Variables The Frequency measurement is computed using the Frequency locked loop for the selected phase IxXSQSUM X and VxSQSUM are the squared current and voltage samples acquired during the last accumulation interval INSQSUM X be used for computing the neutral current CE Description Address 6 0x72 FREQ_X Fundamental frequency LSB 2 0 587 10 7 Hz 0 78 105050 _ The sum of squared current samples from each element 0x79 IISQSUM_X LSB 4 1845 10 IMAX A h Ox7A VOSQSUM X The sum of squared voltage samples from each el
96. ding the ADC LSB size and the conversion accuracy 44 Rev 1 1 DS 6612 001 78M6612 Data Sheet 1 5 10 EEPROM Interface The 78M6612 provides hardware support for a two pin or a three pin EEPROM interface The EEPROM interface uses the EECTRL and EEDATA registers for communication 1 5 10 1 Two Pin EEPROM Interface The dedicated 2 pin serial interface communicates with external EEPROM devices The interface is multiplexed onto pins DIO4 SCK and DIO5 SDA controlled by the I O RAM bits DIO EEX 1 0 see the RAM Table Set DIO EEX 1 0 01 to select the two wire EEPROM interface The MPU communicates with the interface through two SFR registers EEDATA and EECTRL f the MPU wishes to write a byte of data to EEPROM it places the data in EEDATA and then writes the Transmit command CMD 0011 to EECTRL This initiates the transmit operation The transmit operation is finished when the BUSY bit falls Interrupt INT5 is also asserted when BUSY falls The MPU can then check the RX ACK bit to see if the EEPROM acknowledged the transmission A byte is read by writing the Receive command CMD 3 0 0001 to EECTRL and waiting for the BUSY bit to fall Upon completion the received data is in EEDATA The serial transmit and receive clock is 78 kHz during each transmission and the clock is held in a high state until the next transmission The bits in EECTRL are shown in Table 41 The EEPROM interface can also be operated by con
97. e G dimension is maintained 102 Rev 1 1 DS 6612 001 78M6612 Data Sheet 7 Pin Descriptions 7 1 Power Ground Pins Name Type Circuit Description GNDA Analog ground This pin should be connected directly to the ground plane GNDD p _ Digital ground This pin should be connected directly to the ground plane V3P3A _ Analog power supply 3 3V power supply should be connected to this pin must be the same voltage as V3P3SYS _ System 3 3 V supply This pin should be connected to 3 3 V power V3P3SYS P supply Auxiliary voltage output of the chip controlled by the internal 3 3 V V3P3D 13 selection switch In mission mode this pin is internally connected to V3P3SYS In BROWNOUT mode it is internally connected to VBAT This pin is floating in LCD and sleep mode Battery backup power supply A battery or super capacitor is to be VBAT P 12 connected between VBAT and GNDD If no battery is used connect VBAT to V3P3SYS V2P5 10 Output of the internal 2 5 V regulator A 0 1 uF capacitor to GNDA should be connected to this pin 7 2 Analog Pins Name Type Circuit Description Line Current Sense Inputs These pins are voltage inputs to the IB 6 internal A D converter Typically they are connected to the outputs of current sensors Unused pins must be connected to V3P3A Line Voltage Sense Inputs These pins are voltage inputs to the
98. e the processing of any XFER_BUSY or RTC_1SEC interrupt since both interrupts are edge triggered The external interrupts are connected as shown in Table 31 The polarity of interrupts 2 and 3 is programmable in the MPU via the 3FR and I2FR bits in T2CON Interrupts 2 and should be programmed for falling sensitivity The generic 8051 MPU literature states that interrupts 4 through 6 are defined as rising edge sensitive Thus the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 31 34 Rev 1 1 DS 6612 001 78M6612 Data Sheet SFR special function register enable bits must be set to permit any of these interrupts to occur Likewise each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler 0 through 5 XFER BUSY ISEC which are OR ed together have their own enable and flag bits in addition to the interrupt 6 enable and flag bits and these interrupts must be cleared by the MPU software 1 4 9 3 Interrupt Priority Level Structure All interrupt sources are combined in groups as shown in Table 32 Table 32 Priority Level Groups Group 0 External interrupt 0 Serial channel 1 interrupt 1 Timer 0 interrupt External interrupt 2 2 External interrupt 1 External interrupt 3 3 Timer 1 interrupt External interrupt 4 4 Serial channel 0 interrupt External i
99. edad 26 Table 16 The TMOD Register ansint edi a i i a a E a i ii aaa 27 Table 17 Timers Counters Mode Description esee nennen 27 Table 18 Timer Modes Lupo diu 27 Table 19 The PCON 222422 1 einen a trn ene 28 Table 20 The ZENO E a 29 Table 212 The TENT ReGISte fais endi diii irato AE 29 Table 22 Th TPO Her ee ue utet 29 Table 23 WDTREL Reglister aneor iini tieit AALE EA ii AE EA TE A EE ES A EE aS 30 Table 24 The ZENO Registel u eoii ei i A E S nnn 31 Table 29 The Registar iit eae e AAEE S 31 Table 26 The 2 ReQIStel enren eaae e a eae 1000000 a ae r e 32 Table 27 The TCON Register ceros tnne a eaa a e a a araa eT N Ea 32 Tabl e 28 The 72CON ten ded EKES 32 Table 29 The IRCON Register sonson enn a AAA AE E EA KAA a NA 33 Table 30 External MPU Interrupts 0 ccccceeseceeeee cesses eeeeeeeeeeeceaeeeeaaesaeeseaaeeeeaeeseaaesgeeeseaeeeseaeeeeeneesneeeeaas 33 Table 31 Interrupt Enable and Flag
100. ement 0x7C VISQSUM X LSB 6 6952 107 VMAX Vh Ox7D WSUM ACCUM These are roll over accumulators for WPULSE and VARPULSE Ox7E VSUM ACCUM __ respectively The RMS values can be computed by the MPU from the squared current and voltage samples as follows IxSQSUM LSB 3600 F VxSQSUM LSB 3600 F N RMS N ACC ACC Rev 1 1 85 78 6612 Data Sheet DS 6612 001 4 4 7 3 Other Measurement Parameters MAINEDGE X is useful for implementing a real time clock based on the input AC signal MAINEDGE X is the number of half cycles accounted for in the last accumulated interval for the AC signal TEMP RAW may be used by the MPU to monitor chip temperature or to implement temperature compensation CE Name Default Description Address The number of zero crossings of the selected voltage in 0x73 MAINEDGE_X N A the previous accumulation interval Zero crossings are either direction and are debounced 0x71 TEMP_RAW_X N A Filtered unscaled reading from the temperature sensor 0x18 GAIN_ADJ 16384 UM all voltage and current inputs 16384 provides unity The threshold for sag warnings The default value is 0x11 SAG_THR 313000 equivalent to 80V RMS if VMAX 600V The LSB value is VMAX 4 255 10 V peak GAIN ADJ is a scaling factor for measurements based on the temperature GAIN ADJ is controlled by the MPU for temperature compensation
101. erator VARPULSE 3 Internal 3P3 WPULSE gt 2 OPT_TX VW TET DIO2 lt gt 1 from OPT_TX UART 2 22 8 EN DUTY OPT TXMOD OPT_TXE 1 0 OPT_TXMOD 1 OPT_FDC 2 25 NN LE 670 2 B U U U 1 38kHz Figure 7 Optical Interface When not needed for the optical UART the TX1 pin can alternatively be configured as DIO2 WPULSE or VARPULSE The configuration bits are TX7E 1 0 Likewise RX1 can alternately be configured as DIO 1 Its control is RX DIS Rev 1 1 41 78 6612 Data Sheet DS 6612 001 1 5 7 Digital I O The device includes up to 18 pins QFN 68 package or 16 pins LQFP 64 package of general purpose digital I O These pins are compatible with 5V inputs no current limiting resistors are needed Some of them are dedicated DIO DIOS some are dual function that can alternatively be used as LCD drivers 0104 11 14 17 19 21 and some share functions with the optical port DIO1 DIO2 On reset or power up all DIO pins are inputs until they are configured for the desired direction under MPU control The pins are configured by the DIO registers and by the five bits of the LCD NUM register located in I O RAM Once declared as DIO each pin can be configured independently as an input or output with the DIO DIRn bits A 3 bit configuration word DIO Rx can be used for certain pins when configured as DIO to individually assign an int
102. ere the first accumulator accumulates results from PRE SAMPS samples and the second accumulator accumulates up to SUM CYCLES of the first accumulator results The integration time for each energy output is PRE SAMPS SUM CYCLES 2520 6 with MUX_DIV 01 CE hardware issues the BUSY interrupt when the accumulation is complete 1 3 1 Measurement Equations Refer to the applicable 78M6612 Firmware Description Document for further details 1 3 2 Real Time Monitor The CE contains a Real Time Monitor RTM which can be programmed through the UART to monitor four selectable CE DRAM locations at full sample rate for system debug purposes The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass The RTM can be enabled and disabled with RTM_EN The RTM output is clocked by CKTEST Each RTM word is clocked out in 35 cycles and contains a leading flag bit See Section 2 Functional Description for the RTM output format RTM is low when not in use 1 3 3 Pulse Generator The chip contains two pulse generators that create low jitter pulses at a rate set by either CE or MPU for calibration purposes The function is distinguished by EXT_PULSE a CE input variable in CE DRAM e f EXT PULSE 1 APULSEW WRATE APULSER control the pulse rate external pulse generation e If EXT_PULSE is 0 APULSEW is replaced with WSUM_X and APULSER is replaced with
103. ernal resource such as an interrupt or a timer control Table 38 lists the direction registers and configurability associated with each group of DIO pins Table 39 shows the con figuration for a DIO pin through its associated bit in its 010 DIR register Tables showing the relationship between LCD NUM and the available segment DIO pins can be found in the Applications section and in Section 4 3 Description under LCD NUM 4 0 Table 38 Data Direction Registers and Internal Resources for DIO Pin Groups 1 DIO x 12 3 4 5 6 7 849 olil2isials 5 333344404 2 2 Pin no 64 LQFP 7 6 1 6 34444444 2 2 Pin no 68 QFN 0 315 1 12 1 15161 11112 1 2 3 4 5 6 7 0 1 2 3 647 Data Register DIO1 P1 SFR 0x90 1121 13 3 4 5 61 17 01 1121 13 617 Direction Register DIO_DIR1 SFR 0x91 Internal Resources lv 1121 Configurable 11122212 16 172 1 2 1 214 Pin no 64 LQFP 22 3 4 7 47 1 21416 68 23 31 14178 Data Recist 01 3450 ata Register 9 DIO2 P2 SFR OxA0 01 3450 irection Register DIO DIR2 SFR OxA1 Internal Resources Configurable NL TINI e Table 39 DIO DIR Control Bi
104. et DS 6612 001 Accumulator ACC A ACC is the accumulator register Most instructions use the accumulator to hold the operand The mnemonics for accumulator specific instructions refer to accumulator as A not ACC B Register The B register is used during multiply and divide instructions It can also be used as a scratch pad register to hold temporary data Program Status Word PSW Table 8 PSW Register MSB LSB cv ac ro e jov P Bit Symbol Function PSW 7 CV Carry flag PSWI 6 AC Auxiliary Carry flag for BCD operations PSW 5 FO General purpose Flag 0 available for user F0 is not to be confused with the F0 flag in the CE STATUS register PSW 4 RSI Register bank select control bits The contents of RS7 and 50 select the working register bank RSI RSO Bank Selected PSWI3 RSO 0x00 0x07 0x08 0x0F 1 PSW 2 OV Overflow flag PSW 1 User defined flag PSW O P Parity flag affected by hardware to indicate odd even number of one bits in the Accumulator i e even parity Stack Pointer SP The stack pointer is a 1 byte register initialized to 0x07 after reset This register is incremented before PUSH and CALL instructions causing the stack to begin at location 0x08 Data Pointer The data pointer DPTR is 2 bytes wide The lower part is DPL and the highest is DPH It can be loaded as two registers e g
105. f the MPU firmware any calibration method such as calibration based on energy or current and voltage can be implemented It is also possible to implement segment wise calibration depending on current range The 78M6612 supports common industry standard calibration techniques such as single point energy only multi point energy Vrms Irms and auto calibration 72 Rev 1 1 DS 6612 001 78M6612 Data Sheet 4 Firmware Interface 4 1 RAM Map Not Used bits are grayed out contain no memory and are read by the MPU as zero Reserved bits may be in use and should not be changed This table lists only the SFR registers that are not generic 8051 SFR registers Table 48 I O RAM Map In Numerical Order Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Configuration CEO 2000 EQU 2 0 CE E Reserved CE1 2001 PRE SAMPS 1 0 SUM CYCLES 5 0 CE2 2002 MUX DIV 1 0 CHOP E 1 0 RTM E WD OVF EX RTC EX XFR COMPO 2003 Not Used OK Not Used Reserved Reserved Reserved STAT 0 CONFIGO 2004 VREF_CAL PLS INV CKOUT 1 0 VREF DIS MPU DIV 2 0 CONFIG1 2005 Reserved Reserved DIS FIR LEN ADC E MUX ALT FLSH66Z Reserved VERSION 2006 VERSION
106. fier It is assumed that an offset voltage Voff appears at the positive amplifier input With all switches as controlled by CROSS in the A position the output voltage is Voutp Voutn Vinp Voff Vinn Vinp Vinn Voff With all switches set to the B position by applying the inverted CROSS signal the output voltage is Voutn Voutp G Vinn Vinp G Vinn G Voff or Voutp Voutn G Vinp Vinn G Voff Thus when CROSS is toggled e g after each multiplexer cycle the offset will alternately appear on the output as positive and negative which results in the offset effectively being eliminated regardless of its polarity or magnitude When CROSS is high the hookup of the amplifier input devices is reversed This preserves the overall polarity of that amplifier gain it inverts its input offset By alternately reversing the connection the amplifier s offset is averaged to zero This removes the most significant long term drift mechanism in the voltage reference The CHOP_E bits control the behavior of CROSS The CROSS signal will reverse the amplifier connection in the voltage reference in order to negate the effects of its offset On the first CK32 rising edge after the last mux state of its sequence the mux will wait one additional CK32 cycle before beginning a new frame At the beginning of this cycle the value of CROSS will be updated according to 10 Rev 1 1 DS 6
107. from AA V3P3SYS V3P3D Pin 40 from AA VBAT V3P3D Equivalent Circuit Type 13 V3P3D Rev 1 1 105 78M6612 Data Sheet DS 6612 001 9 Ordering Information Part Description Flash Part Package Memory Packaging Ordering Number Package a Marking accuracy Size 78 6612 64 LQFP 0 5 32KB Bulk 78M6612 IGT F 78M6612 IGT 78 6612 64 LQFP 0 5 32KB amp Reel 78M6612 IGTR F 78M6612 IGT 78M6612 64 pin LQFP 0 5 32KB 78M6612 IGT F P 78M6612 IGT Programmed i 78M6612 64 pin LQFP 0 5 32KB Tape amp Reel 78M6612 IGTR F P_ 78M6612 IGT 78M6612 68 pin QFN 0 5 32KB Bulk 78M6612 IM F 78M6612 IM 78M6612 68 pin QFN 0 5 32KB Tape amp Reel 78M6612 IMR F 78 6612 78M6612 68 pin QFN 0 5 32KB 78M6612 IM F P 78 6612 Programmed 4 E 78M6612 68 pin QFN 0 596 32KB Tape amp Reel 78 6612 78 6612 10 Related Documentation The following documents applicable to the 78 6612 are available from Teridian Semiconductor Corporation 78M6612 OMU Demo Board User s Manual 78M6612 OMU Firmware Description Document 78M6612 ACPMON Demo Board User Manual 78M6612 ACPMON Firmware Description Document 78M6612 Firmware Developer s Manual 11 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 78M6612 contact us at 6440 Oak
108. hat can be merged with the MPU operational code for measurement applications Typically the CE program covers most applications and does not need to be modified Other variations of CE code may be available from Teridian The description in this section applies to CE code revision 6612 S2 A01 V1 0 4 4 2 Formats All CE words are 4 bytes Unless specified otherwise they are in 32 bit two s complement 1 OxFFFFFFFF Calibration parameters are defined in Flash memory or external EEPROM and must be copied to CE data memory by the MPU before enabling the CE Internal variables are used in internal CE calculations Input variables allow the MPU to control the behavior of the CE code Output variables are outputs of the CE calculations The corresponding MPU address for the most significant byte is given by 0x1000 4 x CE address and 0x1003 4 x CE address for the least significant byte 4 4 3 Constants Constants used in the CE Data Memory tables are Fg 32768 Hz 13 2520 62 Hz the fundamental frequency MAX is the external rms current corresponding to 250 mV pk at the inputs and IB VMAX is the external rms voltage corresponding to 250 mV pk at the VA and VB inputs the accumulation count for energy measurements is PRE SAMPS SUM CYCLES Accumulation count time for energy measurements is PRE SAMPS SUM CYCLES Fs The system constants MAX and VMAX are used by the MPU to convert
109. hdog timer is a 16 bit counter that is incremented once every 24 or 384 clock cycles After a reset the watchdog timer is disabled and all registers are set to zero The watchdog consists of a 16 bit counter WDT a reload register WDTREL prescalers by 2 and by 16 and control logic Once the watchdog is started it cannot be stopped unless the internal reset signal becomes active Note It is recommended to use the hardware watchdog timer instead of the software 5 watchdog timer WD Timer Start Procedure The WDT is started by setting the SWDT flag When the WDT register enters the state Ox7CFF an asynchronous WDTS signal will become active The signal WDTS sets bit 6 in the register and requests a reset state WDTS is cleared either by the reset signal or by changing the state of the WDT timer Refreshing the WD Timer The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming active This requirement imposes an obligation on the programmer to issue two instructions The first instruction sets WDT and the second instruction sets SWDT The maximum delay allowed between setting WDT and SWDT is 12 clock cycles If this period has expired and SWDT has not been set the WDT is automatically reset otherwise the watchdog timer is reloaded with the content of the WDTREL register and the WDT is automatically reset Since the WDT requires exact timing firmware needs to be designed with special care in orde
110. he 78M6612 can be in one of three battery modes i e BROWNOUT LCD or SLEEP mode As soon as V1 falls below VBIAS or when the part wakes up under battery power with sufficient voltage margin the part will automatically enter BROWN OUT mode see Section 2 5 Wake Up Behavior From BROWNOUT mode the MPU may enter either LCD mode or SLEEP mode by setting either the LCD ONLY or SLEEP RAM bits only one bit can be set at the same time in BROWNOUT mode since setting one bit will already force the part into SLEEP or LCD mode disabling the MPU Figure 18 shows a state diagram of the various operation modes with the possible transitions between modes For information on the timing of mode transitions refer to Figure 22 through Figure 24 Power and Energy Measurement devices that do not require functionality in the battery Q modes e g Power and Energy Measurement devices that only use the SLEEP mode to maintain the RTC still need to contain code that brings the chip from BROWNOUT mode to SLEEP mode Otherwise the chip remains in BROWNOUT mode once the system power is missing and consumes more current than intended contain code that transitions the chip to SLEEP mode as soon as the battery is attached in production Otherwise remaining in BROWNOUT mode would add unnecessary drain to the battery Q Similarly Power and Energy Measurement devices equipped with batteries need to The transition from MISSION mode to BROWNOUT mode is signale
111. internal quantities as used by the CE to external i e measurement quantities Their values are determined by the off chip scaling of the voltage and current sensors used in an actual measurement unit The LSB values used in this document relate digital quantities at the CE or MPU interface to external measurement input quantities For example if a SAG threshold of 80V peak is desired at the measurement input the digital value that should be programmed into SAG_THR would be 80V SAG THRLSB where SAG THRLSB is the LSB value in the description of SAG THR The parameters EQU E PRE SAMPS and SUM CYCLES essential to the function of the CE are stored in I O RAM see the I O RAM section 4 4 4 Environment Before starting the CE using the CE E bit the MPU has to establish the proper environment for the CE by implementing the following steps Load the CE data into CE DRAM Establish the equation to be applied in EQU Establish the accumulation period and number of samples in PRE SAMPS and SUM CYCLES Establish the number of cycles per ADC mux frame Set PLS_INTERVAL 7 0 81 Set FIR LEN 1 and MUX DIV 1 0 01 There must be thirteen 32768 Hz cycles per ADC mux frame see System Timing Diagram Figure 16 This means that the product of the number of cycles per frame and the number of conversions per frame must be 12 allowing for one settling cycle The required configuration is FIR LEN 1 three cycles per conve
112. ion 1 1 Hardware Overview The Teridian 78M6612 single chip measurement unit integrates all primary functional blocks required to implement a solid state electricity Power and Energy Measurement function Included on chips are e Ananalog front end AFE independent digital computation engine CE e An 8051 compatible microprocessor MPU which executes one instruction per clock cycle 80515 e Avoltage reference e Atemperature sensor e LCD drivers e RAM and Flash memory Areal time clock RTC e A variety of I O pins Various current sensor technologies are supported including Current Transformers CT and Resistive Shunts In a typical application the 32 bit compute engine CE of the 78M6612 sequentially processes the samples from the voltage inputs on pins IA VA IB VB and performs calculations to measure active energy Wh reactive energy VARh and V h for four quadrant measurement These measurements are then accessed by the MPU processed further and output using the peripheral devices available to the MPU In addition to advanced measurement functions the real time clock function allows the 78M6612 to record time of use TOU measurement information for multi rate applications and to time stamp events Measurements can be displayed on 3 3 V LCDs if desired Flexible mapping of LCD display segments will facilitate utilization of existing custom LCDs Design trade off between number of LCD segments vs D
113. istive Voltage Divider Left Current Transformer Right sess 62 Figure 28 RESISTIVE SMU drca 62 Figure 29 Crystal Frequency over Temperature eee 64 Figure 30 Crystal Compensation enne enr 65 Figure 31 Connecting EG DS eene ls decay e a o 66 Figure 32 C EEPHOM CONHGEHOR cde cs tut Sect ous I P 68 Figure 33 3 Wire EEPROM 69 Figure 34 Connections for the RX Pin seesssssssssssssssseeee eene enne 69 Figure 35 Connection for Optical Components sse eene nnns nnne nene 70 Figure 36 Voltage Divider for 1 resin nnns enne en 71 Figure 37 External Components for RESET Development Circuit Left Production Circuit Right 71 Figure 38 External Components for the Emulator 224400 0 72 Figure 39 Wh Accuracy 10 mA to 20 A at 120 V 60 Hz and Room Temperature Using a 4 mO Current SHUN adde pescado n pov 95 Figure 40 Measurement Accuracy over Harmonics at 240 V 30A per IEC62053 2x Section 8 2 1 95 Figure 41 Typical Measurement Accuracy over Temperature Relative to 25
114. it in the I O RAM is set While BME is set an on chip 45 load resistor is applied to the battery and a scaled fraction of the battery voltage is applied to the ADC input After each alternative MUX frame the result of the ADC conversion is available at CE DRAM address 07 BME is ignored and assumed zero when system power is not available V1 VBIAS See Section 5 4 4 Battery Monitor for details regarding the ADC LSB size and the conversion accuracy 1 2 7 Functional Description The AFE functions as a data acquisition system controlled by the MPU The main signals IA VA IB VB are sampled and the ADC counts obtained are stored in CE DRAM where they can be accessed by the CE and if necessary by the MPU Alternate multiplexer cycles are initiated less frequently by the MPU to gather access to the slow temperature and battery signals VREF AZ ADC gt CONVERTER Y VBIAS gt VBIAS gt VB gt V3P3A gt gt gt FIR ADC_E VREF TEMP e MUX VREF_CAL VREF FIR_LEN VREF_DIS MUX CROSS CTRL EQU CK32 4 9MHz MUX ALT FIR DONE CHORE FIR_START MUX_DIV Figure 3 AFE Block Diagram Rev 1 1 11 78 6612 Data Sheet DS 6612 001 1 3 Digital Computation Engine CE The CE a dedicated 32 bit signal processor performs the precision computations necessa
115. l TX modulation Yes Flash Read Yes Yes Flash Page Erase Yes Yes Flash Write Yes RAM Read and Write Yes Yes Wakeup Timer Yes Yes Yes Yes Oscillator and RTC Yes Yes Yes Yes DRAM data preservation Yes Yes V3P3D voltage output pin Yes Yes means not active BROWNOUT Mode In BROWNOUT mode most non measurement digital functions as shown in Table 44 are active including ICE UART EEPROM LCD and RTC In BROWNOUT mode a low bias current regulator will provide 2 5 Volts to V2P5 and V2P5NV The regulator has an output called BAT_OK to indicate that it has sufficient overhead When BAT OK 0 the part will enter SLEEP mode From BROWNOUT mode the MPU can voluntarily enter LCD or SLEEP modes When system power is restored the part will automatically transition from any of the battery modes to mission mode once the PLL has settled The MPU will run at crystal clock rate in BROWNOUT The value of MPU_DIV will be remembered not changed as the part enters and exits BROWNOUT MPU_DIV will be ignored during BROWNOUT Rev 1 1 53 78 6612 Data Sheet DS 6612 001 While PLL OK 0 the I O RAM bits ADC E and CE E are held in zero state disabling both ADC and CE When PLL OK falls the CE program counter is cleared immediately and all FIR processing halts Figure 19 shows the functional blocks active in BROWNOUT mode V1 VBIAS V1 lt VBIAS V3P3SYS rises R
116. l2 0 1 1 1 0 1 Level3 highest Table 36 Interrupt Polling Sequence External interrupt O Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 External interrupt 6 Polling sequence 36 Rev 1 1 DS 6612 001 78M6612 Data Sheet 1 4 9 4 Interrupt Sources and Vectors Table 37 shows the interrupts with their associated flags and vector addresses Table 37 Interrupt Vectors Interrupt Request Flag Description Interrupt Vector Address External interrupt 0 0x0003 TFO Timer 0 interrupt 0x000B IEI External interrupt 1 0x0013 TFI Timer 1 interrupt 0x001B RIO TIO Serial channel 0 interrupt 0x0023 RII TII Serial channel 1 interrupt 0x0083 IEX2 External interrupt 2 0x004B IEX3 External interrupt 3 0x0053 IEX4 External interrupt 4 0x005B 5 External interrupt 5 0x0063 IEX6 External interrupt 6 0x006B Rev 1 1 37 78 6612 Data Sheet DS_6612_001 Internal Individual Genera Logic and Interrupt Interrupt mE External Interrupt Ihterrupt Polarity Contro Enabl Priority _ Source Flag Flag Selection Registe Assignment r t 5 E Pollihg
117. le storage LCD Y 2021 6 0 0 R W LCD Blink Frequency ignored if blink is disabled or if segment is off 0 1 Hz 500 ms ON 500 ms OFF 1 0 5 Hz 1s ON 1s OFF MPU DIV 2 0 2004 2 0 0 0 R W The MPU clock divider from 4 9152 MHz These bits may be programmed by the MPU without risk of losing control 000 4 9152 MHz 001 4 9152 MHz 2 111 4 9152 MHz 2 MPU_DIV remains unchanged when the part enters BROWNOUT mode MUX ALT 2005 2 0 0 R W The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an alternate set of inputs MUX_DIV 1 0 2002 7 6 0 0 R W The number of states in the input multiplexer 00 illegal 01 4states 10 3 states 11 2 states 78 Rev 1 1 DS 6612 001 78M6612 Data Sheet Name Location Rst Wk Dir Description OPT FDC 1 0 2007 1 0 0 0 R W Selects TX1 modulation duty cycle OPT FDC Function 00 5096 Low 01 2596 Low 10 12 596 Low 11 6 2596 Low RXIDIS 2008 5 0 0 R W RX1 can be configured as an analog input to the UART1 comparator or as a digital input output DIO1 0 RX4 1 DIO1 RXIINV 2008 4 0 0 R W Inverts result from RX1 comparator when 1 Affects only the UART1 input Has no effect when RX1 is used as a DIO input TXIE 1 0 2007 7 6 00 00 R W Configures the TX1 output pin 00 TX1 01 DIO2 10 WPULSE 11 VARPULSE 2008 0 0 0
118. m address 00 See Section 1 5 12 Program Security for more description of preboot and boot If system power is not present the reset timer duration will be 2 cycles of the crystal clock at which time the MPU will begin executing in BROWNOUT mode starting at address 00 Power Fault Circuit The 78M6612 includes a comparator to monitor system power fault conditions When the output of the comparator falls V1 VBIAS the RAM bits PLL OK is zeroed and the part switches to BROWNOUT mode if a battery is present Once system power returns the MPU remains in reset and does not start Mission Mode until 4100 oscillator clocks later when PLL OK rises If a battery is not present indicated by BAT_OK 0 WAKE will fall and the part will enter SLEEP mode There are several conditions the part could be in as system power returns If the part is in BROWNOUT mode it will automatically switch to mission mode when PLL OK rises It will receive an interrupt indicating this No configuration bits will be reset or reconfigured during this transition If the part is in LCD or SLEEP mode when system power returns it will also switch to mission mode when PLL OK rises In this case all configuration bits will be in the reset state due to WAKE having been zero The RTC clock will not be disturbed but the MPU RAM must be re initialized The hardware watchdog timer will become active when the part enters MISSION mode Rev 1 1 59 78 6612 Data Sheet DS 66
119. m the respective timer reload registers SMOD is the SMOD bit in the SFR PCON THI is the high byte of timer 1 Table 12 UART Modes UART 0 UART 1 Start bit 8 data bits parity stop bit Mode 0 N A variable baud rate internal baud rate generator S Aara top Dic variable Start bit 8 data bits stop bit variable Mode 1 baud rate internal baud rate generator baud rate internal baud rate generator or timer 1 Mode 2 Start bit 8 data bits parity stop bit N A fixed baud rate 1 32 or 1 64 of foxmeu Start bit 8 data bits parity stop bit Mode 3 variable baud rate internal baud rate N A generator or timer 1 Rev 1 1 23 78 6612 Data Sheet DS 6612 001 Parity of serial data is available through the P flag of the accumulator Seven bit serial modes with parity such as those used by the FLAG protocol can be simulated by setting and reading bit 7 of 8 bit output data Seven bit serial modes without parity can be simulated by setting bit 7 to a constant 1 8 bit serial modes with parity can be simulated by setting and reading the 9 bit using the control bits TB80 SOCON 3 and TB81 SICON 3 in the SOCON and SI CON SFRs for transmit and RB61 SICON 2 for receive operations SM20 SOCON 5 and SM21 SICON 5 can be used as handshake signals for inter processor communication in multi processor systems Serial Interface 0 Control Register S0CON The function of the U
120. mware Library iae eee ciere iecit 72 3 16 Measurement nnne nnne renes nnne nnns 72 4 Firmware Interface 73 4 1 VO BUE C aval eae tie 73 4 2 SFR Map SFRs Specific to Teridian 80515 2 044 4 0000000 74 4 3 RAM Description Alphabetical Order 0024 111 75 4 4 CE Interface 82 GE Program ic eec adn epe ec ade 82 rc AMET LII m 82 4 43 GonsStants need e teca d dee de Bae 82 44 4 Environment cer eerte ah ete E ees ae tes 82 4 4 5 GE Calculations 5 ich ra ace desta dade up dva rode 83 4 4 6 rte c de ce a ee 83 4 4 CE Transfer nnne entente intranet 84 5 Electrical 88 5 1 Absolute Maximum 88 5 2 Recommended External Components
121. n interrupt is processed TCON 0 ITO Interrupt 0 type control bit Selects either the falling edge or low level on input pin to cause interrupt Four operating modes can be selected for Timer 0 and Timer 1 Two Special Function Registers and TCON are used to select the appropriate mode 26 Rev 1 1 DS 6612 001 78M6612 Data Sheet Timer Counter Mode Control Register TMOD Bits TRI TCON 6 and TRO TCON 4 in the TCON register see Table 15 start their associated timers when set Table 16 The TMOD Register MSB LSB GATE C T MI MO GATE C T MI MO Timer 1 Timer 0 Bit Symbol Function TMOD 7 If set enables external gate control pin intO or int1 for Counter or 1 TMODI3 Gate respectively When intO or int1 is high and TRX bit is set see TCON register a counter is incremented every falling edge on t0 or t1 input pin TMODIG Selects Timer or Counter operation When set to 1 a Counter operation is C T performed When cleared to 0 the corresponding register will function as a TMOD 2 Timer TMOD 5 MI Selects the mode for Timer Counter 0 or Timer Counter 1 as shown in TMOD 1 TMOD description TMOD 4 mo Selects the mode for Timer Counter 0 or Timer Counter 1 as shown in TMOD 0 TMOD description Table 17 Timers Counters Mode Description 1 MO Function 0 0 Mode 0 13 bit Counter Timer with 5 lower bit
122. ncy which are useful for generating early power fail warnings e g to initiate necessary data storage CESTATUS represents the status flags for the preceding CE code pass CE busy interrupt Sag alarms are not remembered from one code pass to the next The CE Status word is refreshed at every CE_BUSY interrupt The significance of the bits in CESTATUS is shown in the table below Do Name Description 31 29 Not Used These unused bits will always be zero 28 FO is a square wave at the exact fundamental input frequency 27 Reserved 26 SAG B Normally zero Becomes one when VB remains below 5 for SAG_CNT samples Will not return to zero until VB rises above SAG_THR 25 Normally zero Becomes one when VA remains below SAG_THR for E SAG samples Will not return to zero until VA rises above SAG 24 0 Not Used These unused bits will always be zero Rev 1 1 83 78 6612 Data Sheet DS 6612 001 The CE is initialized by the MPU using CECONFIG CESTATE This register contains in packed form SAG FREQSEL EXT PULSE IO SHUNT I1 SHUNT PULSE SLOW and PULSE FAST CE Address Name Default Description OxOE CECONFIG 0x5001 See description of CECONFIG below The significance of the bits in CECONFIG is shown in the table below CE controls the pulse rate based on WOSUM X WISUM X and VAROSUM X VARISUM X Note The 78M6
123. nterrupt 5 5 External interrupt 6 Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IPO and one If requests of the same priority level are received simultaneously an internal polling sequence as per Table 36 determines which request is serviced first An overview of the interrupt structure is given in Figure 6 IEN enable bits must be set to permit any of these interrupts to occur Likewise each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler 0 through 5 BUSY and RTC_1SEC which are OR ed together have their own enable and flag bits in addition to the interrupt 6 enable and flag bits and these interrupts must be cleared by the MPU software Rev 1 1 35 78 6612 Data Sheet DS 6612 001 Interrupt Priority 0 Register Table 33 The 0 Register MSB LSB WDTS IPO 5 IPO 4 IPO 3 IPO 2 IPO 1 IPO O Note WDTS is not used for interrupt controls Interrupt Priority 1 Register IPI Table 34 Register MSB LSB B IP1 5 IP1 4 IP1 3 IP1 2 IP1 1 IP1 0 Table 35 Priority Levels IPI x IPO x Priority Level 0 0 LevelO lowest Level1 Leve
124. occur on the falling edges of the XFER BUSY and CE BUSY signals PULSES VAR DIO7 W DIO6 DISPLAY me L 4 mory mapped LCD segments L SERIAL m UARTO 1 EEPROM 12C DIO INTERRUPTS RAM CONFIGURATION RAM Figure 26 MPU CE Communication Rev 1 1 61 78 6612 Data Sheet DS 6612 001 3 Application Information 3 1 Connection of Sensors CT Resistive Shunt Figure 27 and Figure 28 show how resistive dividers current transformers and restive shunts are connected to the voltage and current inputs of the 78M6612 core Vout R li 47 R InN VA Ra lin lout 1N Figure 28 Resistive Shunt 62 Rev 1 1 DS 6612 001 78M6612 Data Sheet 3 2 Temperature Measurement Measurement of absolute temperature uses the on chip temperature sensor while applying the following formula N T N Me Jim n T In the above formula T is the temperature in C N T is the ADC count at temperature T N is the ADC count at 25 C S is the sensitivity in LSB C as stated in the Electrical Specifications and T is 25 C Example At 25 C a temperature sensor value of 518 203 584 N is read by the ADC by a 78M6612 in the 64 pin LQFP package At an unknown temperature T the value 449 648 000 is read at N T The absolute temperature is then determined by dividing both N and N T by 512 to account for the
125. of driving between 72 to 140 pixels of LCD display with 2596 duty cycle or 60 to 105 pixels with 3396 duty cycle At eight pixels per digit this corresponds to 9 to 17 digits The LCD drivers are grouped into four commons and up to 38 segment drivers 68 pin package or 4 commons and 35 segment drivers 64 pin package The LCD interface is flexible and can drive either digit segments or enunciator symbols Segment drivers SEG18 and SEG19 can be configured to blink at either 0 5 Hz or 1 Hz The blink rate is controlled by LCD Y There can be up to four pixels segments connected to each of these drivers LCD 18 3 01 and LCD BLKMAPI19 3 0 identify which pixels if any are to blink LCD interface memory is powered by the non volatile supply The bits of the LCD memory are preserved in LCD and SLEEP modes even if their pin is not configured as SEG In this case they can be useful as general purpose non volatile storage 1 5 9 Battery Monitor The battery voltage is measured by the ADC during alternative MUX frames if the BME Battery Measure Enable bit is set While BME is set an on chip 45 load resistor is applied to the battery and a scaled fraction of the battery voltage is applied to the ADC input After each alternative MUX frame the result of the ADC conversion is available at CE DRAM address 0x07 BME is ignored and assumed zero when system power is not available See Section 5 4 4 Battery Monitor for details regar
126. on 1 5 5 Physical Memory Flash Memory The 78M6612 includes 32 KB of on chip Flash memory The Flash memory primarily contains MPU and CE program code It also contains images of the CE DRAM MPU RAM and RAM On power up before enabling the CE the MPU copies these images to their respective locations Allocated Flash space for the CE program cannot exceed 1024 words 2 KB The CE program must begin on a 1 KB boundary of the Flash address The CE LCTN 4 0 word defines which 1 KB boundary contains the CE code Thus the first CE instruction is located at 1024 CE LCTN 4 0 CE LCTN must be defined before the CE is enabled The Flash memory is segmented into 512 byte individually erasable pages The CE engine cannot access its program memory when Flash write occurs Thus the Flash write procedure is to begin a sequence of Flash writes when BUSY falls CE BUSY interrupt and to make sure there is sufficient time to complete the sequence before CE BUSY rises again The actual time for the Flash write operation will depend on the exact number of cycles required by the CE program Typically CE program is 512 instructions mux frame is 18 CK32 cycles there will be 200 us of Flash write time enough for 4 bytes of Flash write If the CE code is shorter there will be even more time Two interrupts warn of collisions between the MPU firmware and the CE timing If a Flash write is attempted while the CE is busy the Flash write will not e
127. onfigured as outputs Pins configured as LCD or input will ignore write operations DIO 1 7 6 3 0 SFR90 0 0 R W The value on the pins DIO15 DIO14 and 0011 0108 7 6 3 0 Pins configured as LCD will read zero When written changes data on pins configured as outputs Pins configured as LCD or input will ignore write operations DIO 2 5 3 1 0 SFRAO 0 0 R W The value on the pins DIO20 DIO19 and DIO17 DIO16 5 3 1 0 and DIO21 for the 68 QFN package Pins configured as LCD will read zero When written changes data on pins configured as outputs Pins configured as LCD or input will ignore write operations DIO EEX 1 0 2008 7 6 0 0 R W When set converts DIO4 and DIOS to interface with external EEPROM DIO4 becomes SDCK and DIO5 becomes bi directional SDATA LCD NUM must be less than or equal to 18 DIO EEX 1 0 Function 00 Disable EEPROM interface 01 2 Wire EEPROM interface 10 3 Wire EEPROM interface 11 Not used DIO PV 2008 2 0 0 R W Causes VARPULSE to be output on DIO7 if DIO7 is configured as output LCD NUM must be less than 15 DIO PW 2008 3 0 0 R W Causes WPULSE to be output on DIO6 if DIO6 is configured as output LCD NUM must be less than 16 EEDATA 7 0 SFR9E 0 0 R W Serial EEPROM interface data EECTRL 7 0 SFR9F 30 30 R W Serial EEPROM interface control ECK DIS 2005 5 0 0 RAN Emulator clock disable When one the emulator clock is disabled This bit is to be used with caution Inadvertently setting
128. pensate for input noise and truncation Same LSB as QUANTA This parameter is added to the VAR calculation for element A 0x14 QUANT_VARA 0 to compensate for input noise and truncation LSB VMAX IMAX 1 854171079 W This parameter is added to the VAR calculation for element B 0x15 QUANT VARB 0 to compensate for input noise and truncation Same LSB as for QUANT VARA This parameter is added to compensate for input noise and truncation in the squaring calculations for I QUANT 0x16 QUANT 0 affects only IOSQSUM LSB IMAX 4 6351 101 This parameter is added to compensate for input noise and truncation in the squaring calculations for I QUANT IB 0 17 QUANT_IB 0 affects only 118050 Same LSB as for QUANT_IA Rev 1 1 87 78 6612 Data Sheet DS 6612 001 5 Electrical Specifications 5 1 Absolute Maximum Ratings Supplies and Ground Pins V3PS3SYS 0 5 V to 4 6 V VBAT 0 5 V to 4 6 V GNDD 0 5 V to 0 5 V Analog Output Pins 10 mA to 10 mA V3P3D 0 5 V to 4 6 V 10 mA to 10 mA VREF 0 5 V to V3P3A 0 5 V 1 A 1 A 0 mA to 10 mA 0 5 V to 3 0 V Analog Input Pins IA VA IB VB V1 10 mA to 10 mA 0 5 V to V3P3A 0 5 V XIN XOUT 10 mA to 10 mA 0 5 V to 3 0 V All Other Pins Configured as SEG or COM drivers 1 mA to 1 mA 0 5 to V3P3D 0 5 Configured as Digital Inputs 10 mA to 10 mA
129. r to avoid unwanted WDT resets Teridian strongly discourages the use of the software WDT 28 Rev 1 1 DS 6612 001 78M6612 Data Sheet Special Function Registers for the WD Timer Interrupt Enable 0 Register Table 20 The JENO Register MSB LSB EAL WDT ET2 ESO ETI EXI ETO Bit Symbol Function IENO 6 WDT Watchdog timer refresh flag Set to initiate a refresh of the watchdog timer Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer WDT is reset by hardware 12 clock cycles after it has been set a S Note The remaining bits in the ZENO register are not used for watchdog control Interrupt Enable 1 Register Table 21 Register MSB LSB EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 Bit Symbol Function IENI 6 SWDT Watchdog timer start refresh flag Set to activate refresh the watchdog timer When directly set after setting WDT a watchdog timer refresh is performed Bit SWDT is reset by the hardware 12 clock cycles after it has been set cd Note The remaining bits in the JEN register are not used for watchdog control Interrupt Priority 0 Register Table 22 0 Register MSB LSB WDTS 0 5 4 IPO 3 IPO 2 IPO 1 IPO 0 Bit Symbol Function IPO 6 WDTS Wa
130. rate A modern solid state electricity Power and Energy Measurement IC such as the Teridian 78M6612 functions by emulating the integral operation above i e it processes current and voltage samples through an ADC at a constant frequency As long as the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest the current and voltage samples multiplied with the time period of sampling will yield an accurate quantity for the momentary energy Summing up the momentary energy quantities over time will result in accumulated energy 500 a Current A 300 Voltage V id s ES i Liu E usse Energy per Interval Ws 400 4 Accumulated Energy Ws 500 Figure 15 Voltage Current Momentary and Accumulated Energy Figure 15 shows the shapes of V t I t the momentary power and the accumulated power resulting from 50 samples of the voltage and current signals over a period of 20 ms The application of 240 VAC and 100 A results in an accumulation of 480 Ws 0 133 Wh over the 20 ms period as indicated by the Accumulated Power curve The described sampling method works reliably even in the presence of dynamic phase shift and harmonic distortion 50 Rev 1 1 DS 6612 001 78M6612 Data Sheet 2 2 System Timing Summary
131. rated ICE for MPU debug RTC with temperature compensation Auto Calibration Hardware watchdog timer power fail monitor LCD driver up to 152 pixels Up to 18 general purpose pins 32 kHz time base 32 KB Flash with security 2 KB MPU XRAM Two UARTs Digital I O pins compatible with 5 V inputs 64 pin LQFP or 68 pin QFN package RoHS compliant 6 6 lead free packages Complete Application Firmware available Rev 1 1 2009 Teridian Semiconductor Corporation 1 78 6612 Data Sheet DS 6612 001 Table of Contents 1 Hardware 8 1 1 Hardware Overview dee eate eer ha ated 8 1 2 Analog Front End Heide e Genie 9 1 231 Input Multiplexer Pet dd Heint dede Fe er Ped 9 1 2 2 A D Converter aiti edid E eget ie Den dude He Pr a 9 1 2 9 FIR Filter t Ho e e dt He me E dq rat E aD 10 1 2 4 Voltage References 4 4 snnt enne nennen nnne 10 1 2 5 11 12 6 Battery Monitor dele E ee ect eee genie cence deh deve tee nen 11 1 2 7 Functional Description a ei NAN 11 1 3 Digital Computation Engine 12 1 31 Measurement
132. rolled by the multiplexer control circuit as described previously At the end of each ADC conversion the FIR filter output data is stored into the CE DRAM location determined by the multiplexer selection 1 2 3 FIR Filter The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer The purpose of the FIR filter is to decimate the ADC output to the desired resolution At the end of each ADC conversion the output data is stored into the fixed CE DRAM location determined by the multiplexer selection FIR data is stored LSB justified but shifted left by nine bits 1 2 4 Voltage References The device includes an on chip precision bandgap voltage reference that incorporates auto zero techniques The reference is trimmed to minimize errors caused by component mismatch and drift The result is a voltage output with a predictable temperature coefficient The amplifier within the reference is chopper stabilized i e the polarity can be switched by the MPU using the I O RAM register E 0 2002 5 4 The two bits in the E register enable the MPU to operate the chopper circuit in regular or inverted operation or in toggling mode When the chopper circuit is toggled in between multiplexer cycles DC offsets on the measured signals will automatically be averaged out The general topology of a chopped amplifier is given in Figure 2 Figure 2 General Topology of a Chopped Ampli
133. rsion and MUX DIV 1 0 01 4 conversions per frame 82 Rev 1 1 DS 6612 001 78M6612 Data Sheet During operation the MPU is in charge of controlling the multiplexer cycles for example by inserting an alternate multiplexer sequence at regular intervals using MUX ALT This enables temperature measurement The polarity of chopping circuitry must be altered for each sample It must also alternate for each alternate multiplexer reading This is accomplished by maintaining CHOP E 00 4 4 5 CE Calculations The CE performs the precision computations necessary to accurately measure energy These computations include offset cancellation products product smoothing product summation frequency detection VAR calculation sag detection peak detection and voltage phase measurement Refer to the applicable 78M6612 Firmware Description Document 4 4 6 CE Status Since the BUSY interrupt occurs at 2520 6 Hz it is desirable to minimize the computation required in the interrupt handler of the MPU The MPU can read the CE status word at every CE_BUSY interrupt CE Address Name Description oxra CESTATUS See description of CE status word below The CE Status Word is used for generating early warnings to the MPU It contains sag warnings for VA as well as FO the derived clock operating at the fundamental input frequency CESTATUS provides information about the status of voltage and input AC signal freque
134. rt must be enabled Any other pattern written to FLSH ERASE will have no effect FLSH MEEN SFRB2 1 Mass Erase Enable 0 Mass Erase disabled default 1 Mass Erase enabled Must be re written for each new Mass Erase cycle FLSH_PGADR 6 0 FPAG SFRB7 7 1 Flash Page Erase Address FLSH_PGADR 6 0 Flash Page Address page 0 thru 127 that will be erased during the Page Erase cycle default 0x00 Must be re written for each new Page Erase cycle FLSH_PWE 2 0 R W Program Write Enable 0 MOVX commands refer to XRAM Space normal operation default 1 MOVX DPTR A moves A to Program Space Flash DPTR This bit is automatically reset after each byte written to Flash Writes to this bit are inhibited when interrupts are enabled FOVRIDE 20FD 4 R W Permits the values written by MPU to temporarily override the values in the fuse register reserved for production test IE_FWCOLO IE FWCOLI SFRE8 2 SFRES 3 R W R W Interrupt flags for Firmware Collision Interrupt See Flash Memory Section for details IE PLLRISE SFRES 6 R W Indicates that the MPU was woken or interrupted int 4 by System power becoming available or more precisely by PLL_OK rising Firmware must write a zero to this bit to clear it IE PLLFALL SFRE8 7 R W Indicates that the MPU has entered BROWNOUT mode because System power has become unavaila
135. ructions in one clock cycle Using a 5 MHz 4 9152 MHz clock results in a processing throughput of 5 MIPS The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases Normally a machine cycle is aligned with a memory fetch therefore most of the 1 byte instructions are performed in a single cycle This leads to an 8x performance in average improvement in terms of MIPS over the Intel 8051 device running at the same clock frequency Actual processor clocking speed can be adjusted to the total processing demand of the application measurement calculations AMR management memory management LCD driver management and I O management using the I O RAM register MPU DIV 2 0 Typical power and energy measurement functions based on the results provided by the internal 32 bit compute engine CE are available for the MPU as part of Teridian s standard library A standard ANSI C 80515 application program library is available to help reduce design cycle Rev 1 1 15 78 6612 Data Sheet DS 6612 001 1 4 4 Memory Organization The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces Memory organization in the 80515 is similar to that of the industry standard 8051 There are three memory areas Program memory Flash external data memory XRAM physically consisting of XRAM CE DRAM and I O RAM and internal data memory Internal RAM Table shows
136. rupt hardware and reset by the MPU interrupt handler Note that XFER BUSY RTC 15 FWCOLO FWCOL1 PLLRISE PLLFALL have their own enable and flag bits in addition to the interrupt 6 4 and 2 enable and flag bits Rev 1 1 33 78 6612 Data Sheet DS 6612 001 IEO through IEX6 are cleared automatically when the hardware vectors to the interrupt handler The other flags IE XFER through IE WAKE are cleared by writing a zero to them Since these bits in a bit addressable SFR byte common practice would be to clear them with a bit operation This is to be avoided The hardware implements bit operations as a byte wide read modify write hardware macro If an interrupt occurs after the read but before the write its flag will be cleared unintentionally The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a zero in the location of the bit to be cleared The flag bits are configured in hardware to ignore ones written to them Table 31 Interrupt Enable and Flag Bits Interrupt Enable Interrupt Flag Interrupt Description Name Location Name Location EXO SFR A8 0 SFR 88 1 External interrupt 0 1 SFR 8 2 IE SFR 88 3 External interrupt 1 EX2 SFR B8 1 IEX2 SFR CO 1 External interrupt 2 EX3 SFR B8 2 IEX3 SFR CO 2 External interrupt 3 4 SFR 8 3 IEX4 SFR CO 3 External interrupt 4 5 SFR B8 4 IEX5 SFR 4
137. ry to accurately measure energy The CE calculations and processes include e Multiplication of each current sample with its associated voltage sample to obtain the energy per sample when multiplied with the constant sample time e Frequency insensitive delay cancellation on all four channels to compensate for the delay between samples caused by the multiplexing scheme e 90 phase shifter for VAR calculations e Pulse generation e Monitoring of the input signal frequency for frequency and phase information e Monitoring of the input signal amplitude for sag detection e Scaling of the processed samples based on calibration coefficients CE code is provided by Teridian as a part of the application firmware available The CE is not programmable by the user Measurement algorithms in the CE code can be customized by Teridian upon request The CE program resides in Flash memory Common access to Flash memory by CE and MPU is controlled by a memory share circuit Each CE instruction word is two bytes long Allocated Flash space for the CE program cannot exceed 1024 words 2 KB The CE program counter begins a pass through the CE code each time multiplexer state 0 begins The code pass ends when a HALT instruction is executed For proper operation the code pass must be completed before the multiplexer cycle ends see Section 2 2 System Timing Summary The CE program must begin on a 1 Kbyte boundary of the Flash address The I O RAM
138. s in the TLO or TL1 register and the remaining 8 bits in the THO or 1 register for Timer 0 and Timer 1 respectively The high order bits of TLO and TL are held at zero 0 1 Mode 1 16 bit Counter Timer 1 0 Mode 2 8 bit auto reload Counter Timer The reload value is kept in THO or THI while TLO or TL1 is incremented every machine cycle When TL x overflows a value from TH x is copied to TL x 1 1 Mode If Timer 1 1 and bits are set to 1 Timer 1 stops If Timer 0 M and bits are set to 1 Timer 0 acts as two independent 8 bit Timer Counters T Note Mode 3 TLO is affected by TRO and gate control bits and sets the flag on S overflow while THO is affected by the TRI bit and the flag is set on overflow Table 18 specifies the combinations of operation modes allowed for timer 0 and timer 1 Table 18 Timer Modes Timer 1 Mode 0 Mode 1 Mode 2 Timer 0 mode 0 YES YES YES Timer 0 mode 1 YES YES YES Timer 0 mode 2 Not allowed Not allowed YES Rev 1 1 27 78 6612 Data Sheet DS 6612 001 Timer Counter Mode Control Register PCON The SMOD bit in the PCON register doubles the baud rate when set Table 19 The PCON Register MSB LSB SMOD Bit Symbol Function PCON 7 SMOD Baud rate control 1 4 8 WD Timer Software Watchdog Timer The software watc
139. s reset on chip reset and may only be set Attempts to write zero are ignored SLEEP 20A9 6 Takes the 78M6612 to sleep mode Ignored if system power is present The part will wake when the autowake timer times out or when system power returns SUM CYCLES 5 0 2001 5 0 R W The number of pre summer outputs summed in the final summer TMUX 4 0 20AA 4 0 R W Selects one of 32 signals for TMUXOUT 4 0 Selected Signal 4 0 Selected Signal 0x00 DGND analog 0x01 Reserved 0x02 Reserved 0x03 Reserved 0x04 Reserved 0x05 Reserved 0x06 VBIAS analog 0x07 Not used 0x08 Reserved 0x09 Reserved OxOA Reserved 0x0 Reserved B 0x13 0 14 RTM Real time output from CE 0x15 WDTR_E comparator 1 Output AND V1LT3 0x16 Not used 0x18 RXD from optical in terface after optional 0x17 inversion 0x19 SYNC 0x1 A CK_MPU 0x1 CK_10M 0 1 Reserved 0 1 RTCLK 2 5 0 1 CE_BUSY Ox1F XFER BUSY VERSION 7 0 2006 7 0 The version index This word may be read by firmware to determine the silicon version VERSION 7 0 0000 0110 VREF CAL 2004 7 R W Brings VREF to VREF pad This feature is disabled when VREF_DIS 1 VREF_DIS 2004 3 R W Disables the internal voltage reference 80 Rev 1 1 DS
140. ss of the MPU clock speed RTC reads require one wait state RTC time is set by writing to the RTC registers in RAM Each byte written to RTC must be delayed at least 3 RTC cycles from any previous byte written to RTC Hardware RTC write protection requires that a write to address 0x201F occur before each RTC write Writing to address 0x201F opens a hardware enable gate that remains open until an RTC write occurs and then closes It is not necessary to disable interrupts between the write operation to 0x201F and the RTC write because the enable gate will remain open until the RTC write finally occurs Two time correction bits RTC_DEC_SEC and RTC_INC_SEC are provided to adjust the RTC time A pulse on one of these bits causes the time to be decremented or incremented by an additional second at the next update of the RTC_SEC register Thus if the crystal temperature coefficient is known the MPU firmware can integrate temperature and correct the RTC time as necessary Rev 1 1 39 78 6612 Data Sheet DS 6612 001 1 5 4 Temperature Sensor The device includes an on chip temperature sensor for determining the temperature of the bandgap reference The MPU may request an alternate multiplexer frame containing the temperature sensor output by asserting MUX ALT The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system see Section 3 3 Temperature Compensati
141. sually requires that the cell is erased first Since cells cannot be erased individually the page has to be copied to RAM followed by a page erase After this the page can be updated in RAM and then written back to the Flash memory MPU RAM The 78M6612 includes 2k bytes of static RAM memory on chip XRAM plus 256 bytes of internal RAM in the MPU core The 2K bytes of static RAM are used for data storage during normal MPU operations CE DRAM The CE DRAM is the working data memory of the CE 128 32 bit words The MPU can read and write the CE DRAM as the primary means of data communication between the two processors 1 5 6 Optical Interface The device includes an interface to implement an IR optical port The pin TX1 is designed to directly drive an external LED for transmitting data on an optical link The pin RX1 is designed to sense the input from an external photo detector used as the receiver for the optical link These two pins are connected to a dedicated UART port UART1 The TX1 and RX1 pins can be inverted with configuration bits and respectively Additionally the TX1 output may be modulated at 38 kHz Modulation is available when system power is present i e not in BROWNOUT mode The TX MOD bit enables modulation Duty cycle is controlled by OPT FDC 1 0 which can select 50 25 12 596 and 6 25 duty cycle 6 25 duty cycle means TX1 is low for 6 2596 of the period Figure 7 illustrates the TX1 gen
142. t DIO DIR n 0 1 DIO Pin n Function Input Output 42 Rev 1 1 DS 6612 001 78M6612 Data Sheet Additionally if DIO6 and DIO7 are declared outputs they can be configured as dedicated pulse outputs WPULSE DIO6 VARPULSE DIO7 using DIO PW and DIO PV registers In this case DIO6 and DIO7 are under CE control DIO4 and DIO5 can be configured to implement the EEPROM Interface If the optical UART is not used TX1 and RX1 can be configured as dedicated DIO pins DIO1 DIO2 see Section 1 5 6 Optical Interface A 3 bit configuration word I O RAM register DIO Rx 0x2009 2 0 through 0x200E 6 4 can be used for certain pins when configured as DIO to individually assign an internal resource such as an interrupt or a timer control see Table 38 for DIO pins available for this option This way DIO pins can be tracked even if they are configured as outputs Tracking DIO pins configured as outputs is useful for pulse counting without external hardware shown in Figure 8 right not source it from V3P3D as shown in Figure 8 left This is due to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT When driving LEDs relay coils etc the DIO pins should sink the current ground as V3P3SYS in MISSION and above VBAT in LCD and BROWNOUT modes Doing so will distort the LCD waveforms of the other pins This limitation applies to any pin that can be configured as a LCD driver
143. t is initializing after a WDT overflow event or after a power up After it is read MPU firmware must clear WD OVF The WD OVF bit is cleared by the RESET pin VBIAS Battery There is no internal digital state that deactivates the WDT For modes debug purposes however the WDT can be disabled by tying the V1 pin to see Figure 36 Of course this also deactivates V1 power fault detection Since there is no method in firmware to disable the crystal oscillator or the WDT it is guaranteed that whatever state the part might find itself in upon WDT overflow the part will be reset to a known state oV Figure 14 Functions Defined by V1 Asserting ICE_E will also deactivate the WDT This is the only method that will disable the WDT in BROWNOUT mode In normal operation the WDT is reset by periodically writing a one to the WDT_RST bit The watchdog timer is also reset when the internal signal WAKE 0 see Section 2 5 Wake Up Behavior 1 5 12 Program Security When enabled the security feature limits the ICE to global Flash erase operations only All other ICE operations are blocked This guarantees the security of the user s MPU and CE program code Security is enabled by MPU code that is executed in a 32 cycle preboot interval before the primary boot sequence begins Once security is enabled the only way to disable it is to perform a global erase of the Flash followed by a chip reset The first 32 cycles of the M
144. tchdog timer status flag Set when the watchdog timer was started Can be read by software os Note The remaining bits in the ZPO register are not used for watchdog control Rev 1 1 29 78 6612 Data Sheet DS 6612 001 Watchdog Timer Reload Register WDTREL Table 23 The WDTREL Register MSB LSB 7 6 5 4 3 2 1 0 Bit Symbol Function Prescaler select bit When set the watchdog is clocked through an d additional divide by 16 prescaler WDTREL 6 Seven bit reload value for the high byte of the watchdog timer This to 6 0 value is loaded to the WDT when a refresh is triggered by a consecutive WDTREL 0 setting of bits WDT and SWDT The WDTREL register can be loaded and read at any time 1 4 9 Interrupts The 80515 provides 11 interrupt sources with four priority levels Each source has its own request flag s located in a special function register TCON IRCON and SCON Each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits SFRs ZENO IEN1 and IEN2 External interrupts are the interrupts external to the 80515 core i e signals that originate in other parts of the 78M6612 for example the CE DIO RTC EEPROM interface 1 4 9 1 Interrupt Overview When an interrupt occurs the MPU will vector to the predetermined address as shown in Table 37 Once interrupt service has begun
145. ter for port 2 All DIO ports on the chip are bi directional Each consists of a Latch SFR PO to P2 an output driver and an input buffer therefore the MPU can output or read data through any of these ports Even if a DIO pin is configured as an output the state of the pin can still be read by the MPU for example when counting pulses issued via DIO pins that are under CE control The technique of reading the status of or generating interrupts based on DIO pins configured as outputs can be used to implement pulse counting 1 4 4 Special Function Registers Specific to the 78M6612 Table 10 shows the location and description of the 78M6612 specific SFRs Table 10 Special Function Registers Alternative SFR T Register Address R W Description ERASE FLSH_ERASE 0x94 W _ This register is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle default 0x00 0x55 Initiate Flash Page Erase cycle Must be preceded by a write to FLSH_PGADR SFR 0xB7 OxAA Initiate Flash Mass Erase cycle Must be preceded by a write to FLSH_MEEN SFR 0 2 and the debug port must be enabled Any other pattern written to FL H ERASE will have effect FPAG FLSH PGADR 0 7 R W Flash Page Erase Address register containing the Flash memory page address page 0 through 127 that will be
146. the memory map Table 3 Memory Map Address Memory Wait Memory Memory Type Typical Usage States Size hex Technology at 5 MHz bytes MPU Program and 0000 7FFF Flash Memory Non volatile n nsvalatile data 0 32K Flash Memory Non volatile CE program 0 2K boundary 0000 07FF Static RAM Volatile MPU data XRAM 0 2K 1000 11FF Static RAM Volatile CE data 6 512 Configuration RAM 2000 20FF Static RAM Volatile VO RAM 0 256 Internal and External Data Memory Both internal and external data memory are physically located on the 78 6612 IC External data memory is defined as external to the 80515 MPU Program Memory The 80515 can theoretically address up to 64 KB of program memory space from 0x0000 to OxFFFF Program memory is read when the MPU fetches instructions or performs a MOVC operation After reset the MPU starts program execution from location 0x0000 The lower part of the program memory includes reset and interrupt vectors The interrupt vectors are spaced at 8 byte intervals starting from 0x0003 External Data Memory While the 80515 is capable of addressing up to 64 KB of external data memory 0x0000 to OxFFFF only the memory ranges shown in Table 3 are supported by the 78M6612 Contain Physical Memory The 80515 writes into external data memory when the MPU executes a MOVX Ri A or MOVX QDPTR A instruction The MPU reads external data memory by executing a MOVX A
147. this bit will inhibit access to the part with the ICE interface and thus preclude Flash erase and programming operations If ECK ENA is set it should be done at least 1000 ms after power up to give emulators and programming devices enough time to complete an erase operation EQU 2 0 2000 7 5 0 0 R W Specifies the power equation to be used by the CE EX_XFR 2002 0 0 0 R W Interrupt enable bits These bits enable the BUSY EX RTC 2002 1 0 0 the RTC_1SEC the FirmWareCollision and PLL EX FWCOL 2007 4 0 0 interrupts Note that if one of these interrupts is to be EX PLL 2007 5 0 0 enabled its corresponding EX enable bit must also be set See the Interrupts section for details FIR LEN 2005 4 0 0 R W The length of the ADC decimation FIR filter 1 384 cycles 0 288 cycles When FIR LEN 1 the ADC has 2 370370x higher gain 76 Rev 1 1 DS 6612 001 78M6612 Data Sheet Name Location Rst Wk Dir Description FLSH ERASE 7 0 SFR94 7 0 Flash Erase Initiate FLSH ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle default 0x00 0x55 Initiate Flash Page Erase cycle Must be proceeded by a write to FLSH_PGADR SFR OxB7 OxAA Initiate Flash Mass Erase cycle Must be proceeded by a write to FLSH_MEEN SFR 0 2 and the debug CC po
148. to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM depending on the values of the EECTRL bits Table 42 EECTRL Bits for 3 Wire Interface Contro I Bit Name Read Write Description Wait for Ready If this bit is set the trailing edge of BUSY will be delayed until a rising edge is seen on the data line This bit can 7 WFR be used during the last byte of a Write command cause the INT5 interrupt to occur when the EEPROM has finished its internal write sequence This bit is ignored if HiZ 0 Asserted while serial data bus is busy When the BUSY bit falls 6 BUSY R an INT5 interrupt occurs Indicates that the SD signal is to be floated to high impedance 2 MiZ d immediately after the last SCK rising edge 4 RD Indicates that EEDATA is to be filled with data from EEPROM Specifies the number of clocks to be issued Allowed values are 0 through 8 If RD 1 CNT bits of data will be read MSB first and 3 0 CNT 3 0 right justified into the low order bits of EEDATA If RD 0 CNT bits will be sent MSB first to EEPROM shifted out of EEDATA s MSB If CNT is zero SDATA will simply obey the HiZ bit The timing diagrams in Figure 9 through Figure 13 describe the 3 wire EEPROM interface behavior All commands begin when the EECTRL register is written Transactions start by first raising the DIO pin that is connected to CS Multiple 8 bit or less commands such as
149. to the MPU by the CE_BUSY interrupt At the end of each multiplexer cycle status information such as sag data and the digitized input signal is available to the MPU 833ms 20ms XFER_BUSY Interrupt to MPU Figure 5 Accumulation Interval Figure 5 shows the accumulation interval resulting from PRE_SAMPS 42 and SUM_CYCLES 50 consisting of 2100 samples of 397us each followed by the XFER_BUSY interrupt The sampling in this example is applied to a 50Hz signal 14 Rev 1 1 DS 6612 001 78M6612 Data Sheet There is no correlation between the line signal frequency and the choice of PRE SAMPS or SUM CYCLES even though when SUM CYCLES 42 one set of SUM CYCLES happens to sample a period of 16 6 ms Furthermore sampling does not have to start when the line voltage crosses the zero line and the length of the accumulation interval need not be an integer multiple of the signal cycles It is important to note that the length of the accumulation interval as determined by Nacc the product of SUM CYCLES SAMPS is not an exact multiple of 1000 ms For example if SUM CYCLES 60 and PRE SAMPS 00 42 the resulting accumulation interval is a 60 42 _ 2520 f 32768Hz 2520 62 13 999 75 5 This means that accurate time measurements should be based on the RTC not the accumulation interval 1 4 80515 MPU Core The 78M6612 includes an 80515 MPU 8 bit 8051 compatible that processes most inst
150. to wake the MPU periodically every 5 seconds for example the timer must be rearmed every time the MPU is awakened 2 6 Data Flow The data flow between CE and MPU is shown in Figure 25 In a typical application the 32 bit compute engine CE sequentially processes the samples from the voltage inputs on pins IA VA IB and VB performing calculations to measure active power Wh reactive power VARh and V h for four quadrant measurement These measurements are then accessed by the MPU processed further and output using the peripheral devices available to the MPU Pulses Processed Metering Data Processor Processor I O RAM Configuration RAM Figure 25 MPU CE Data Flow 60 Rev 1 1 DS 6612 001 78M6612 Data Sheet 2 7 CE MPU Communication Figure 26 shows the functional relationship between CE and MPU The CE is controlled by the MPU via shared registers in the RAM and by registers in the CE DRAM The CE outputs two interrupt signals to the MPU CE BUSY and XFER BUSY which are connected to the MPU interrupt service inputs as external interrupts CE BUSY indicates that the CE is actively processing data This signal will occur once every multiplexer cycle XFER BUSY indicates that the CE is updating data to the output region of the CE DRAM This will occur whenever the CE has finished generating a sum by completing an accumulation interval determined by SUM CYCLES PRE SAMPS samples Interrupts to the MPU
151. trolling the 0104 and DIO5 pins directly bit banging However controlling DIO4 and DIOS directly is discouraged because it may tie up the MPU to the point where it may become too busy to process interrupts Table 41 EECTRL Status Bits Read Status Name Polarity Description Bit Wri State rite 7 ERROR R 0 Positive 1 when an illegal command is received 6 BUSY R 0 Positive 1 when serial data bus is busy 5 RX_ACK R 1 Negativ 0 indicates that the EEPROM sent an ACK bit e 4 TX_ACK R 1 Negativ 0 indicates when an ACK bit has been sent to e the EEPROM CMD Operation 0000 No op Applying the no op command will stop the IC clock SCK DIO4 Failure to issue the no op command will keep the SCK signal toggling Positive 0001 Receive a byte from EEPROM and 3 0 CMDI 3 0 W 0 OND send ACK Table 0011 Transmit a byte to EEPROM 0101 Issue a STOP sequence 0110 Receive the last byte from EEPROM do not send ACK 1001 Issue a START sequence Others No Operation set the ERROR bit Rev 1 1 45 78 6612 Data Sheet DS 6612 001 1 5 10 2 3 Wire EEPROM Interface A 500 kHz 3 wire interface using SDATA SCK and a DIO pin for CS is available The interface is selected with DIO EEX 1 0 2 10 The same 2 wire EECTRL register is used except the bits are reconfigured as shown in Table 42 When EECTRL is written up
152. ure operation in BROWNOUT mode should be used for the DI DO signals and the CS pin should be pulled down with a resistor to prevent that the 3 wire device is selected on power up before the 78M6612 can establish a stable signal for CS The DIO EEX register RAM must be set to 10 in order to convert the DIO pins 0104 and DIO5 to uWire pins The pull up resistor for DIO5 may not be necessary V3P3 78M6612 10kQ 10kO EEPRO DIO4 gt 2 5 DIO5 b DIOn Figure 33 3 Wire EEPROM Connection 3 9 UARTO TX RX The RX pin should be pulled down by a 10 kQ resistor and additionally protected by a 100 pF ceramic capacitor as shown in Figure 34 78 6612 1 1 10 RX 1006 ii RX T T TX 6 O TX Figure 34 Connections for the RX Pin Rev 1 1 69 78 6612 Data Sheet DS 6612 001 3 10 UART1 Interface The pins TX1 and RX1 can be used for a regular serial interface e g by connecting RS 232 transceiver or they can be used to directly operate optical components e g an infrared diode and phototransistor implementing a FLAG interface Figure 35 shows the basic connections The TX1 pin becomes active when the I O RAM register TX DIS is set to 0 The polarity of the TX1 and RX1 pins can be inverted with configuration bits and RXIINV respectively The TX1 output may be modulated at 38 kHz when system power
153. ust not be connected across the crystal 3 14 Flash Programming Operational or test code can be programmed into the Flash memory using either an in circuit emulator or the Flash Programmer Module TFP 1 available from Teridian The Flash programming procedure uses the E RST E RXTX and E TCLK pins 3 15 MPU Firmware Library All application specific MPU functions mentioned above under Application Information are available from Teridian as a standard ANSI C library and as ANSI C source code The code is available as part of the Demonstration Kit for the 78M6612 IC The Demonstration Kits come with the 78M6612 IC preprogrammed with demo firmware mounted on a functional sample PCB Demo Board The Demo Boards allow for quick and efficient evaluation of the IC without having to write firmware or having to supply an in circuit emulator ICE 3 16 Measurement Calibration Once the 78M6612 Power and Energy Measurement device has been installed in a measurement system it is typically calibrated for tolerances of the current sensors voltage dividers and signal conditioning components The device can be calibrated using the gain and phase adjustment factors accessible to the CE The gain adjustment is used to compensate for tolerances of components used for signal conditioning especially the resistive components Phase adjustment is provided to compensate for phase shifts introduced by certain types of current sensors Due to the flexibility o
154. w teridian com by checking with your sales representative Teridian Semiconductor Corp 6440 Oak Canyon Suite 100 Irvine CA 92618 TEL 714 508 8800 FAX 714 508 8877 http www teridian com Rev 1 1 107
155. xecute and the FW COLO interrupt will be issued If a Flash write is still in progress when the CE would otherwise begin a code pass the code pass is skipped the write is completed and the FW_COL1 interrupt is issued The bit FLASH66Z see Table 50 defines the speed for accessing Flash memory To minimize supply current draw this bit should be set to 1 Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence These special pattern sequence requirements prevent inadvertent erasure of the Flash memory The mass erase sequence is 1 Write 1 to the FLSH MEEN bit SFR address OxB2 1 2 Write pattern OxAA to FLSH_ERASE SFR address 0x94 The page erase sequence is The mass erase cycle can only be initiated when the ICE port is enabled 1 Write the page address to FLSH_PGADR SFR address 0xB7 7 1 2 Write pattern 0x55 to FLSH_ERASE SFR address 0x94 The MPU may write to the Flash memory This is one of the non volatile storage options available to the user in addition to external EEPROM 40 Rev 1 1 DS 6612 001 78M6612 Data Sheet FLSH PWE Flash program write enable differentiates 80515 data store instructions MOVX DPTR A between Flash and XRAM writes Updating individual bytes in Flash memory The original state of a Flash byte is OxFF all ones Once a value other than OxFF is written to a Flash memory cell overwriting with a different value u

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