Home

phyCORE-Vybrid Hardware Manual

1. 2 _ e sm mE eeo mm 11111111 ee 4 4 Fig 21 1 SD MMC Interface The phyCORE Vybrid Carrier Board provides a standard Secure Digital Memory SDHC card slot at X9 for connection to SD MMC cards Power to the SD interface is supplied by inserting the appropriate card into the SD MMC connector PHYTEC America LLC 2012 59 Il Chapter 22 Audio L 783e 0 1222 Fig 22 1 Audio Interface The audio interface provides a method of exploring the VFx00 s audio capabilities The phyCORE Vybrid Carrier Board is populated with a Freescale Semiconductors SGTL5000 audio codec at U12 The SGTL5000 is connected to the VFx00 s audio interface to support mono microphone input stereo headphone output stereo line out and stereo line in The phyCORE Vybrid accesses the SGTL5000 registers via the I2C2 interface at address 7 bit MSB addressing The Carrier Board s audio interface includes two hardware configuration jumpers J2 and JP5 These are described in detail below J2 Enables the crystal oscillator which can be selected for the audio master clock by JP5 The default configuration J2 2 3 disables this oscillator JP5 Selects the audio codec s master clock source MCLK The audio codec s master clock input accepts frequencies f
2. 3 1 3 Block 6 rk ER M a we egies ee ging 4 1 4 View of the phyCORE Vybrid 5 ZEE 7 ha ere ota 16 3 1 Jumper 0 17 4 error een Sa aE ae dec er Pa ae 19 4 1 Primary System Power 3 3 19 42 DDR3 POWer 2 ink geek ues fed pie 20 4 3 Vybrid Processor Core 20 4 4 Backup Power 20 cae hea te Ra tae OG 21 6 System Configuration and Booting 22 7 System 23 7 1 DDRSSODRAM nem ex aa ae bale We 23 T2 NAND at e 23 7 3 QSPI NOR Flasher eum E 23 TA EEPROM tene E ee ae 23 7 4 1 Setting the EEPROM Lower Address 5 24 7 4 2 EEPROM Write Protection Control 46
3. 67 Table 26 1 Tamper Signals at Connector 21 68 Part PCM 957 GPIO Expansion 69 Table 28 1 Analog Signal Map 71 Table 29 1 Control Signal Map 72 Table 30 1 Processor Signal Map 73 Table 31 1 Power Signal Map 75 Revision History n hl ST REGRESAR 76 Table 32 1 Revision History 76 PHYTEC America LLC 2012 iii List of Figures L 783e_0 List of Figures Part 1 PCM 052 phyCORE Vybrid System 1 Fig 1 1 phyCORE Vybrid Block 4 Fig 1 2 Top View of the phyCORE Vybrid Controller 5 4 5 Fig 1 3 Bottom View of the phyCORE Vybrid Connector Side 6 Fig 2 1 Pin out of the phyCORE Connector View with Cross Section Insert 8 Fig 3 1 Jumper 16 Fig 3 2 Jumper 5 17 Fig 4 1 phyCO
4. 5 5 X14 0000000000 1 1 zd Ens e e 1 5 XB X22 X25 X20 X27 X28 s anna 2 9 P JP5 a aun 77 JP23 25 e JP16 s x2 Se i m Low 07 xs 021 xi 20 JP15 JP14 JP28 17 m l Im ele of TIE 5 JP18 mmm E 5 JP27 012 T5 JP1o 9 F ESIP pisi Bp i JP24 017 238 m 8 Di Fe D14 Fig 12 1 Overview of Peripherals The phyCORE Vybrid Carrier Board is depicted in Figure 11 1 It is equipped with the components and peripherals listed in the tables below For a more detailed description of each peripheral refer to the appropriate chapter listed in the applicable table Figure 12 1 highlights the location of each peripheral for easy identification PHYTEC America LLC 2012 34 Il Chapter 12 Overview of Peripherals L 783e_0 12 1 Connectors and Pin Headers I PETS 000000000 x30a LES EB sel JA LIEN s m i LEET n a
5. SCI2 Tx MCU PTB7 6A 6A 3V3 SCI2 Rx MCU PTB10 7B 7B IO VCC 3V3 Interrupt from the touch screen controller control signal out to User LED1 Resistor R138 must be installed to connect this signal to LED1 MCU_PTB18 11B 11B IO 3V3 GPIO MCU_PTB19 128 14 SPI CS to the PHYTEC Display Interface MCU_PTB20 13B 13C SPI MOSI to the PHYTEC Display Interface PTB21 13A 18B IO VCC 3V3 SPI MISO to the PHYTEC Display Interface MCU PTB22 14A 11C SPI SCK to the PHYTEC Display Interface MCU PTB23 15 15A IO VCC 3V3 Can connect the RTC interrupt from the SOM back to the Vybrid MCU PTB24 16 16A IO NAND Flash write enable MCU_PTB25 15B 15B Flash chip enable MCU 26 168 16 GPIO MCU 27 178 17 Flash read enable MCU PTB28 18 18B GPIO 40B 40B VCC RMIIO MDC PTC1 41B 41B IO VCC RMII1 MDIO MCU PTC2 42B 42B VCC RMIIO CRS PTC3 43B 43B VCC 3V3 RMIIO RXD1 MCU 4 43A 43A IO VCC 3V3 RMIIO RXDO MCU PTC5 44A 44A 3V3 RMIIO MCU 6 45A 45A VCC 3V3 RMIIO TXD1 MCU PTC7 46A 46A IO VCC 3V3 RMIIO TXDO MCU PTC9 46B 46B VCC RMII1 MDC MCU PTC10 47B 47B VCC 3V3 RMII1 MDIO MCU PTC11 48B 48B IO VCC 3V3 RMII1 CRS
6. 48 Fig 18 1 CAN Interface Connectors and 5 50 Fig 19 1 USB 52 20 1 P 53 Fig 21 1 SD MMC Interface 59 22 1 Audio Interface 60 Fig 23 1 JTAG Connectivity 62 24 1 an vues A EAE a 64 F1g 25 1 K20 2 sed Rx dea aos ER oe 66 Fig 26 1 tein vitae tanta eR Yee 68 Part PCM 957 GPIO Expansion 69 Fig 27 1 PCM 957 GPIO Expansion Board and Patch Field 70 PHYTEC America LLC 2012 iv L 783e_0 Conventions Abbreviations and Acronyms Conventions The conventions used in this manual are as follows Signals that are preceded by a character are designated as active low signals Their active state is when they are driven low or are driving low for example RESET Tables show the default setting or jumper position in bold teal text e Text in blue indicates a hyperlink either internal or external to the document Click these links to q
7. 5 Em m BERRRRRMRM 7 BEER WE WENN mmmmmmmM gg a mm 00000000 uu 2m Lum mEREM m m m B m n u HN m Wm um EN n m Fig 3 2 Jumper Locations Table 3 1 provides a functional summary of solder jumpers that can be changed to adapt the phyCORE Vybrid for specific needs It
8. E EL phyCORE Vybrid System on Module and Carrier Board Hardware Manual Document No L 783e 0 Product No PCM 052 PCM 952 SOM PCB No 1374 0 CB PCB No 1375 2 Edition December 11 2012 phyCORE Vybrid L 783e 0 In this manual are descriptions for copyrighted products that are not explicitly indicated as such The absence of the trademark TV and copyright symbols does not imply that a product is not protected Additionally registered patents and trademarks are similarly not expressly indicated in this manual The information in this document has been carefully checked and is believed to be entirely reliable However PHYTEC America LLC assumes no responsibility for any inaccuracies PHYTEC America LLC neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product PHYTEC America LLC reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result Additionally PHYTEC America LLC offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC America LLC further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability for doing so Copyright 2011 PH
9. PHYTEC America LLC 2012 2 Part Chapter 1 Introduction L 783e 0 Two 10 100 MBit Ethernet interfaces with internal L2 Switch and IEEE1588 for Realtime Ethernet available as RMII TTL signals or 10 100 differential pairs One interface with SMBUS support e Four Serial Peripheral Interfaces SPI Two Quad SPI QSPI supporting XIP Two FlexCAN interfaces with transceivers Display interface with 24 data bits 125 audio e Two 12 bit digital to analog converter DAC outputs e Two 10 12 bit analog to digital ADC inputs e JTAG 16 bit Trace Two active and two passive tamper security signals e 4 bit Secure Digital Host interface SD MMC Real Time Clock e 40 to 85 C operating temperature range 1 2 Minimum Requirements to Operate the phyCORE Vybrid Basic operation of the phyCORE Vybrid requires a 3 3V 5 supply voltage with at least 1 0A current capacity Connect power and ground to the following pins on connector X1 to power the SOM 3 3V X1 1C 2C 1D 2D GND X1 3C 3D 7C 7D Please refer to Chapter 2 for information on additional GND pins located at the phyCORE Connector X1 CAUTION We recommend connecting all available 3 3V input pins to the power supply system on a custom carrier board housing the phyCORE Vybrid and at least the matching number of GND pins neighboring the 3 3V pins In addition proper implementation of the phyCORE Vybrid module into a t
10. DDR3 Memory Controller 4 Supervisor DDR3 Memory 4 1 5 Volt DO RSV clade Regulator Fig 1 1 phyCORE Vybrid Block Diagram PHYTEC America LLC 2012 4 L 783e_0 Eu 1 4 View of the phyCORE Vybri Part Chapter 1 Introduction TM B omn on Fig 1 2 Top View of the phyCORE Vybrid Controller Side PHYTEC America LLC 2012 Part Chapter 1 Introduction L 783e 0 p S MA N TE _ still mes 08 T MT A RD Tl ome E UE Fig 1 3 Bottom View of the phyCORE Vybrid Connector Side PHYTEC America LLC 2012 6 Chapter 2 Pin Description L 783e_0 2 Pin Description Please note that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller manuals datasheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals All controller signals extend to surface mount technology SMT connectors 0 5 mm lining two sides of the module referred to as the phyCORE Connector This allows the phyCORE Vybrid to be plugged into any target applicati
11. 24 7 5 Memory Model 1 2 daa Rma d 24 8 Serial 1 25 81 9Cl RS 292 24 9 GR UR A Rank aom URL 25 82 whe aurea hire ere Rat Re pua tee dude hr Ree Er idend REM 25 B 3 FlexGAN d e Re p edo e 26 9 Technical Specifications 27 10 Integrating and Handling the 29 10 1 Integrating the 29 10 2 Handling the phyCORE Vybrid 30 Part Il PCM 952 phyCORE Vybrid Carrier Board 31 14 Introduction eee eh dis dul ee Rr aod dd 32 12 Overview of Peripherals 34 12 1 Connectors and Pin Headers 35 12 2 Buttons and Switches 37 12 2 1 System Reset 37 12 2 2 User Programmable Push Buttons 38 12 2 3 Boot Configura
12. The phyCORE Vybrid comes populated with two Micrel Ethernet PHYs at U2 and U3 supporting 10 100 Mbps Ethernet connectivity These PHYs connect over RMII to the Dual Ethernet MAC integrated in the The Ethernet PHYs support the HP Auto MDIX function eliminating the need for consideration of a direct connect LAN cable or a cross over patch cable The PHYs detects the TX and RX pins of the connected device and automatically configures its own TX and RX pins accordingly Interfacing the Ethernet ports involves adding RJ45 connectors and appropriate magnetic devices in your design Please consult the phyCORE Vybrid Carrier Board schematics as a reference If the Ethernet ports will not be used the transceivers on the SOM can be disabled allowing these signals to be designated for other uses PHYTEC America LLC 2012 25 Part Chapter 8 Serial Interfaces L 783e 0 8 3 FlexCAN The Controller Area Network CAN is a serial communications protocol which efficiently supports distributed real time control with a high level of security The includes two CAN interfaces These support bitrates up to 1 MBit s and are compliant to the FlexCAN3 protocol specification The phyCORE Vybrid provides two CAN transceivers at U13 and U14 These transceivers can be used to translate the signal voltages out of the VFx00 to CAN levels and ISO 11898 requirements For configurations which do not require CAN level translation or w
13. 47B PTC10 IO VDD_3V3 RMII1 Management Data Input Output MDIO 48B MCU_PTC11 IO VDD_3V3 RMII1 Carrier Sense CRS 49B GND Ground 0 V 50B 12 IO VDD_3V3 RMII1 Receive Data 1 51B PTC17 IO VDD_3V3 RMII1 Transmit Enable 52B PTAG IO VDD_3V3 RMII1 clock 538 IO VDD_3V3 SD write protect 54B GND Ground 0 558 ADCOSE8 Analog 3V3 Analog signal 568 ADCOSE9 Analog 3V3 Analog signal 57B ADCT1SEB8 Analog 3V3 Analog signal PHYTEC America LLC 2012 11 Part Chapter 2 Pin Description L 783e_0 Table 2 2 Pinout of the phyCORE Connector X1 Row B Continued Pin Signal Type SL Description 58B ADC1SE9 Analog VDD_3V3 Analog signal 59B GND Ground 0 V 60B VREFL ADC REF VDD 3V3 Analog reference voltage Table 2 3 Pinout of the phyCORE Connector X1 Row C Pin Signal Type SL Description C1 VDD_3V3 PWR VDD_3V3 3 3 V supply voltage C2 VDD_3V3 PWR VDD_3V3 3 3 V supply voltage C3 GND Ground 0 C4 VBAT PWR VBAT 3 0 V backup voltage for the Real Time Clock C5 RESETn IO VDD_3V3 System reset C6 VDD_1V5_EN IN VDD_3V3 RESERVED C7 GND Ground 0 V C8 SCI1 TX RS232 OUT 3V3or MCU_PTB4 or RS232 1 Tx from transceiver RS232 U15 depending on SOM configuration C9 SCI1 RX RS232 IN 3V3or PTB5or RS232 1 Rxfrom transceiver RS232 U15 depending on SOM co
14. Fig 14 1 phyCORE Vybrid SOM Connectivity to the Carrier Board Connectors X1 on the Carrier Board provide connectivity to the phyCORE SOM and are keyed for proper insertion Figure 14 1 shows the location of these connectors Pin numbering scheme is shown in Figure 2 1 Please refer to Chapter 9 Table 9 2 for more information about the phyCORE connectors including manufacturer part number and ordering PHYTEC America LLC 2012 44 Il Chapter 15 Power L 783e 0 15 Power R135 D3 a JP1 e e 014 Hita Fig 15 1 Powering Scheme The primary input power of the phyCORE Vybrid Carrier Board is supplied from the wall adapter jack at X2 5V with 3A capacity An alternate 5V input connector at X26 is an optional feature with a 16A capacity This option is provided for using high powered PHYTEC Displays that exceed the 5V 3A provided by X2 The input connector at X26 does not come standard on the phyCORE Vybrid Carrier Board it must be special ordered Use only one of these two connectors A switching regulator generates 3 3V to supply the SOM and components on the Carrier Board The following table lists the voltage domains and their uses Table 15 1 Voltage Domains Mad Description omain 5 0 Main supply voltage from wall adapter input at X2 or X26 5 0 powers the other supplies on the Carrier Board VCC 3V3 VCC 3V3 powers the SOM and various components on the Carrier Bo
15. shown below Table 29 1 Control Signal Map L 783e_0 Signal A aS SL Description RESETn 5C 5C IPU VCC_3V3 System reset VDD_1V5_EN 6C 6C IPU 3V3 RESERVED PHYWIRE 16C 3V3 PHYWIRE to the PHYTEC Display Interface TS WP 17C IN 3V3 Touch screen wiper contact 5 wire only for PHYTEC Display Interface NF WPn 10B 10B IPU VCC 3V3 Write protect for NAND Flash on SOM CAN EN 10A 10A IPU VCC 3V3 Enable for CAN transceivers on SOM EXT TAMPERO 10D 10D Vybrid TamperO security signal EXT TAMPER1 11D 11D 3V3 Vybrid 1 security signal EXT_TAMPER2 12D 12D IO VCC 3V3 Vybrid Tamper2 security signal EXT TAMPER3 13D 13D Vybrid Tamper3 security signal PHYTEC America LLC 2012 72 Part Chapter 30 Processor Signal Mapping 30 Processor Signal Mapping Processor signals on the GPIO Expansion Board are shown below Table 30 1 Processor Signal Map L 783e_0 Signal SL Description MCU PTA6 52 52B RMII Clock MCU_PTB1 1B 1B Audio Data Out MCU_PTB2 2B 2B Vybrid configuration signal This signal must low during system reset MCU_PTB3 3B 3B IO VCC 3V3 Display Enable for Display Interface MCU_PTB6 5A 5A
16. while the other provides power and auxiliary control X30B The PDI uses LVDS for the display data signaling and SPI and USB as potential control sources The Carrier Board provides an LVDS transmitter IC to convert the TTL level signals provided by the Vybrid processor into the LVDS level signals required by the PHYTEC Display Interface JP4 Enables the LVDS transmitter U3 for the PHYTEC Display Interface at X30 To enable the interface jumper JP4 must be removed Table 20 3 and Table 20 4 below give detailed descriptions of the signals on connectors X30A and X30B Table 20 3 PDI Connector X30A Signal Descriptions Pin Signal Type SL Description 1 GND Ground 0 V 2 VCC_3V3 PWR VCC_3V3 3 3 V supply voltage 3 GND Ground 0 V 4 VCC 5 0 PWR VCC 5 0 5 0 V supply voltage PHYTEC America LLC 2012 56 Part Il Chapter 20 Display L 783e 0 Table 20 3 PDI Connector X30A Signal Descriptions Continued Pin Signal Type SL Description 5 GND Ground 0 V 6 5 0 PWR 5VO 5 0 V supply voltage 7 GND Ground 0 V 8 5 0 PWR 5 0 5 0 V supply voltage 9 GND Ground 0 V 10 MCU_PTBO IO VCC_3V3 Ground 0 V 11 no connect not connected 12 no connect not connected Table 20 4 PDI Connector X30B Signal Descriptions Pin Signal Type SL Description 1 MCU_PTB22 OU
17. MCU PTC12 508 50B VCC 3V3 RMII1 RXD1 MCU PTC13 48A 48A VCC 3V3 RMII1 RXDO MCU PTC14 49A 49A RMII1 PHYTEC America LLC 2012 73 Part Chapter 30 Processor Signal Mapping Table 30 1 Processor Signal Map Continued SOM GPIO L 783e_0 Signal Pin EB Pin Type SL Description MCU PTC15 50A 50A VCC 3V3 RMII1 TXD1 MCU PTC16 51A 51A IO VCC 3V3 RMII1 TXDO MCU PTC17 51B 51B IO 3V3 RMII1_TXEN MCU PTC26 28A 28A VCC 3V3 Flash Ready Busy MCU PTC27 29A 29A IO VCC NAND Flash Address Latch Enable MCU_PTC28 30A 30A IO NAND Flash Command Latch Enable MCU_PTC29 31A 31A GPIO MCU PTC31 30 GPIO PTD7 31B 31B 3V3 QSPIO CLK PTD8 32B 32B IO VCC 3V3 QSPIO B CS MCU PTD9 33B 33B 3V3 QSPIO B D3 MCU PTD10 35 35B 3V3 QSPIO 02 PTD11 36B 36B IO VCC_3V3 QSPIO_B D1 PTD12 37B 37B QSPIO B DO MCU PTD13 38 38B GPIO MCU_PTD16 18 18 NAND Flash 100 MCU_PTD17 19 19A VCC 3V3 Flash 101 MCU_PTD18 20A 20A 3V3 Flash 102 MCU_PTD19 21 21 NAND Flash 103 MCU_P
18. 19B GND Ground 0 V 20B MCU_PTD20 IO VDD_3V3 NAND Flash 104 PHYTEC America LLC 2012 10 Part Chapter 2 Pin Description L 783e_0 Table 2 2 Pinout of the phyCORE Connector X1 Row B Continued Pin Signal Type SL Description 21B MCU PTD21 IO VDD_3V3 NAND Flash 105 228 MCU PTD22 IO VDD_3V3 NAND Flash 106 238 MCU_PTD23 IO VDD_3V3 NAND Flash 107 24B GND Ground 0 V 25B PTD28 IO VDD_3V3 NAND Flash 1012 268 29 IO VDD_3V3 NAND Flash 1013 278 PTD30 IO VDD_3V3 NAND Flash 1014 28B PTD31 IO VDD_3V3 NAND Flash 1015 298 GND Ground 0 V 30B 1 IO VDD_3V3 GPIO 318 IO VDD_3V3 QSPIO B clock 328 PTD8 IO VDD_3V3 QSPIO B chip select 33B PTD9 IO VDD_3V3 QSPIO B data 3 348 GND Ground 0 V 35B PTD10 IO VDD_3V3 QSPIO B data 2 36B PTD11 IO VDD_3V3 QSPIO B data 1 378 PTD12 IO VDD_3V3 QSPIO B data 0 388 PTD13 IO VDD_3V3 GPIO 39B GND Ground 0 V 40B MCU PTCO VDD_3V3 RMIIO Management Data Clock MDC 41B PTC1 IO VDD_3V3 Management Data Input Output 428 2 IO VDD_3V3 RMIIO Carrier Sense CRS 43B PTC3 IO VDD_3V3 RMIIO Receive Data 1 44B GND Ground 0 V 45B PTC8 IO VDD_3V3 RMIIO Transmit Enable 468 MCU_PTC9 IO VDD_3V3 RMII1 Management Data Clock MDC
19. PTA19 IO Trace Data 3 25 MCU_PTA30 10 VCC 3V3 Trace Data 14 26 PTA18 VCC 3V3 Trace Data 2 27 PTA29 10 3V3 Trace Data 13 28 MCU PTA17 VCC 3V3 Trace Data 1 29 PTA28 VCC 3V3 Trace Data 12 30 no connect 31 PTA27 VCC 3V3 Trace Data 11 32 no connect 33 MCU PTA26 10 3V3 Trace Data 10 34 no connect 35 PTA25 VCC 3V3 Trace Data 9 36 MCU PTB13 3V3 Trace Control 37 PTA24 10 VCC_3V3 Trace Data 8 38 PTA16 VCC 3V3 Trace Data 0 39 43 GND Ground PHYTEC America LLC 2012 65 Il Chapter 25 K20 L 783e_0 25 K20 ut 15 JP28 JP26 e 012 Fig 25 1 K20 USB Mini AB connector X13 provides OpenSDA and CMSIS DAP access to the Vybrid processor for debugging purposes OpenSDA and CMSIS DAP debugging are implemented through a Freescale K20 processor U13 on the Carrier Board When connector X13 is not connected to a USB host the K20 processor is held in reset Jumpers 26 and JP27 can be installed to connect the K20 to the Vybrid s SCI1 interface In order to avoid signal conflicts with the Vybrid s default serial communication these are not normally installed In addition to save time the K20 processor can be used to program the SPI Flash EEPROMs on the phyCORE Vybrid quickly To program the SPI Flash devices on the SO
20. Pin Signal Type SL Description C27 GND Ground 0 V C28 MCU_PTA8 IO VDD_3V3 JTAG Chain TCLK C29 9 IO VDD_3V3 JTAG Chain TDI C30 MCU_PTA10 IO VDD 3V3 JTAG Chain TDO C31 PTA11 IO VDD_3V3 JTAG Chain TMS C32 GND Ground 0 V C33 17 IO VDD 3V3 Trace data 1 C34 PTA18 IO VDD 3V3 Trace data 2 C35 PTA19 IO VDD_3V3 Trace data 3 C36 MCU 20 IO VDD 3V3 Trace data 4 C37 GND Ground 0 V C38 25 IO VDD_3V3 Trace data 9 C39 MCU 26 IO VDD 3V3 Trace data 10 C40 PTA27 IO VDD 3V3 Trace data 11 C41 PTA28 IO VDD 3V3 Trace data 12 C42 GND Ground 0 V 43 PTE1 OUT VDD_3V3 Display vertical sync C44 MCU PTE2 OUT VDD_3V3 Display clock C45 IO VDD 3V3 GPIO C46 4 OUT VDD_3V3 Display enable C47 GND Ground 0 V C48 OUT VDD_3V3 Display red 4 C49 PTE10 OUT VDD 3V3 Display red 5 C50 11 OUT VDD 3V3 Display red 6 C51 12 OUT VDD 3V3 Display red 7 C52 GND Ground 0 V C53 PTE17 OUT VDD 3V3 Display green 4 C54 PTE18 OUT VDD 3V3 Display green 5 C55 MCU PTE19 OUT VDD 3V3 Display green 6 C56 PTE20 OUT VDD 3V3 Display green 7 C57 GND Ground 0 V C58 MCU PTE25 OUT VDD 3V3 Display blue 4 C59 PTE26 OUT VDD 3V3 Display blue 5 C60 27 OUT VDD_3V3 Display blue 6 PHYTEC America LLC 2012 13 Part Chapter 2 Pin Description L 783e_0
21. PoR Power on reset RTC Real time clock SMT Surface mount technology SOM System on Module used in reference to the PCM 052 phyCORE Vybrid System on Module PHYTEC America LLC 2012 Table 1 1 Abbreviations and Acronyms Used This Manual L 783e_0 Abbreviation Definition Sx User button Sx S1 S2 etc used in reference to the available user buttons or DIP switches on the Carrier Board Sx_y Switch y of DIP switch Sx used in reference to the DIP switch on the Carrier Board TRM Technical Reference Manual VBAT SOM battery supply input Different types of signals are brought out at the phyCORE Connector The following table lists the abbreviations used to specify the type of a signal Table 1 2 Types of Signals Type of Signal Description Abbreviation Power Supply voltage PWR Ref Voltage Reference voltage REF USB Power USB voltage USB Input Digital input IN Output Digital output OUT Input with pull up Input with pull up jumper or open collector output Input output Bidirectional input output IO 5V Input with pull down 5V tolerant input with pull down 5V_PD LVDS Differential line pairs 100 Ohm LVDS Pegel LVDS Differential 90 Ohm Differential line pairs 90 Ohm DIFF90 Differential 100 Ohm Differential line pairs 100 Ohm DIFF100 Analog Analog input or output Analog PHYTEC America LLC 2012 vi L 783e_0 Preface This phyCORE Vybrid Hardware Manual describes
22. Samtec www samtec com PHYTEC America LLC 2012 28 Part Chapter 10 Integrating and Handling the phyCORE Vybrid L 783e 0 10 Integrating and Handling the phyCORE Vybrid 10 1 Integrating the phyCORE Vybrid Successful integration of the phyCORE Vybrid into a custom carrier board requires adherence to the layout design rules for the GND connections of the phyCORE module As a general design rule we recommend connecting all GND pins neighboring signals which are being used in the application circuitry At minimum four GND pins should be connected in addition to the four VDD pins used for SOM power see Chapter 1 2 for details For maximum EMI performance all GND pins should be connected to a solid ground plane To facilitate the integration of the phyCORE Vybrid into your design the footprint of the phyCORE Vybrid is shown in Figure 10 1 1 21mm 3 86mm dimensions referenced to the outside edges have a tolerance of 0 2 mm all other dimensions have a tolerance of 0 1 mm unless otherwise noted shaded area represents space to place noncritical components no RF emission no thermal radiation etc underneath the module please bear in mind the maximum height of the components given by the height of the connectors and the components on the bottom side of the SOM Fig 10 1 phyCORE Vybrid Footprint PHYTEC America LLC 2012 29 Chapter 10 Integrating and Handling the phyCORE Vybrid L 783e_0 Beside
23. Signals vi Part PCM 052 phyCORE Vybrid System on Module 1 Table 2 1 Pinout of the phyCORE Connector X1 8 Table 2 2 Pinout of the phyCORE Connector X1 Row B 10 Table 2 3 Pinout of the phyCORE Connector X1 12 Table 2 4 Pinout of the phyCORE Connector X1 Row D 14 Table 3 1 SOM Jumper Settings 18 Table 6 1 Boot Device Selection 22 Table 7 1 06 EEPROM Address 1 and J2 24 Table 7 2 EEPROM Write Protection States J6 24 Table 8 1 RS 232 Signal Locations 25 Table 9 1 Technical Specifications 28 Table 9 2 Part information for phyCORE Connectors X1 28 Part Il PCM 952 phyCORE Vybrid Carrier Board 31 Table 12 1 phyCORE Vybrid Connectors 36 Table 12 2 Button Descriptions 37 Table 12 3 Switch Settings 85 38 Table 12 4 Boot Config
24. Table 2 4 Pinout of the phyCORE Connector X1 Row D Pin Signal Type SL Description D1 VDD_3V3 PWR VDD_3V3 3 3 V power input D2 VDD_3V3 PWR VDD_3V3 3 3 V power input D3 GND Ground 0 04 BOOTMODO IN VDD_3V3 Boot configuration input D5 BOOTMOD1 IN VDD 3V3 Boot configuration input D6 RCON5 IN VDD 3V3 Boot configuration input 07 RCONG IN VDD 3V3 Boot configuration input D8 RCON7 IN VDD 3V3 Boot configuration input D9 GND Ground 0 V D10 EXT TAMPERO IN VDD 3V3 Vybrid physical security tamper detection D11 EXT TAMPER1 IN VDD 3V3 Vybrid physical security tamper detection 012 EXT TAMPER2 VDD 3V3 Vybrid physical security tamper detection D13 EXT VDD 3V3 Vybrid physical security tamper detection 014 GND Ground 0 V D15 VBUS 0881 USB VBUS USB1 5 0 USB1 VBUS supply 016 0581 VBUS D 5V PD Detect signal for USB1 VBUS supply ETECT D17 USB1 DP DIFF90 3V3 USB1 data plus D18 USB1 DM DIFF90 3V3 05 1 data mins D19 GND Ground 0 V D20 12 SCL OUT VDD 3V3 I2C2 clock D21 2 SDA lO VDD_3V3 12 2 data D22 ETHO LEDO OUT VDD 3V3 EthernetO LED 0 control D23 ETHO LED1 OUT VDD 3V3 EthernetO LED 1 control D24 GND Ground 0 V 025 ETH1 RXM LVDS 0 3V3 Ethernet1 receive data minus D26 ETH1 RXP LVDS VDD 3 3 Ethernet1 receive data plus D27 ETH1 TXM LVDS 0 3V3 Ethernet
25. U7 U8 U9 U13 U14 U15 U17 SOM devices 01 gt 016 02 Fig 4 1 phyCORE Vybrid Power Design The following sections of this chapter describe each component of the power design of the phyCORE Vybrid CAUTION As a general design rule we recommend connecting all GND pins neighboring signals which are being used in the application circuitry For maximum EMI performance all GND pins should be connected to a solid ground plane 4 1 Primary System Power VDD 3V3 The phyCORE Vybrid operates off of a primary voltage supply with a nominal value of 3 3V An on board switching regulator at U5 generates the 1 5V voltage supply required by the DDR3 memory U6 Voltage regulators integrated in the Vybrid processor generate the 1 1V and 1 2V supplies needed by the Vybrid processor core PHYTEC America LLC 2012 19 Chapter 4 Power L 783e 0 An optional backup battery voltage VBAT be supplied for the external Real Time Clock 016 the Real Time Clock which is integrated in the 00 All of the on board components except for the DDR3 memory interface and the RTCs are powered directly from the primary 3 3V supplied to the SOM The phyCORE Vybrid includes a voltage supervisor at U1 which asserts the system reset when the voltage of the primary system power is below 3V For proper operation the phyCORE Vybrid must be supplied with a voltage
26. VCC_CAN Supply Configuration Configuration JP17 JP18 JP24 CAN transceiver on SOM OPEN 5 6 OPEN CAN transceiver on CB use system power OPEN 3 4 5 6 CAN transceiver CB use DC isolated power 3 4 CLOSED PHYTEC America LLC 2012 51 Il Chapter 19 USB L 783e_0 19 USB 0000 ee TRITT 7 FT E Tues ig m b VLL 11 4 nui iss 2 I eke 3 E 1 2 eee agg a mm mo a iii 2 2 m 7 L 1 1 1 es le H 2 7 m WU ira e 0158 8016 ag 38 834 5 8 gg 08 MA KR ER ccoo LEJ eee 0000 0000 E eo 4 eee 0000 x8 00000 eoo o ecce 9 m ilill m ecco e 1 Fig 19 1 USB Interface The 0580 and 0581 interfaces route to connector X8 USB Dual Standard A Although both of these interfaces are USB OTG ports they are limited to host operation due to the USB A style connectors USBO is accessible at the bottom connector while USB1 is at the top connector 19 1 VCC USB Each of the USB interfaces has its own voltage supply LED 016 indicates when VCC_USBO is powered and LE
27. cycle completes these pins may be used for other purposes When using these pins for other purposes make sure their secondary functions are tri stated or disabled during the reset cycle to avoid interfering with the latched boot mode PHYTEC America LLC 2012 22 Chapter 7 System Memory L 783e_0 7 System Memory The phyCORE Vybrid provides four types of on board memory 1 DDR3 SDRAM 128MB to 512MB 2 NAND Flash 256MB to 2GB 3 SPINOR Flash 16 MB to 128MB 4 4KB to 32KB The following sections of this chapter detail each memory type used on the phyCORE Vybrid SOM 7 1 DDR3 SDRAM The RAM memory of the phyCORE Vybrid is comprised of one 16 bit wide DDR3 SDRAM chip at U6 The chip is connected to the dedicated DDR interface of the VFx00 processor Typically the DDR3 SDRAM initialization is performed by a boot loader or operating system following a power on reset and must not be changed at a later point by any application code When writing custom code independent of an operating system or boot loader SDRAM must be initialized through the appropriate SDRAM configuration registers on the VFx00 controller Refer to the VFx00 TRM about accessing and configuring these registers 7 2 NAND Flash The use of flash as non volatile memory on the phyCORE Vybrid provides an easily reprogrammable means of code storage The NAND Flash memory is connected to the VFx00 GPMC interface with a bus width of 16
28. described in the tables below Table 12 2 Button Descriptions Button Description Chapter S2 Reset System Reset Button issues a system warm reset 6 53 User button 1 User button BTN1 Toggles the MCU_PTB8 signal if jumper JP20 is 12 2 2 installed on the Carrier Board 4 User button 2 User button BTN2 Toggles the 9 signal if jumper JP21 is 12 2 2 installed on the Carrier Board S7 SPI Flash System reset if jumper 15 lt 1 2 This is for programming the SPI 25 Flash devices on the SOM through K20 processor 12 2 1 System Reset Button The phyCORE Carrier Board is equipped with a system reset button at S2 Pressing the button will not only reset the phyCORE mounted the phyCORE Vybrid Carrier Board but also the peripheral devices such as the display The red LED at D21 will light while system reset is asserted PHYTEC America LLC 2012 37 Part Il Chapter 12 Overview of Peripherals L 783e 0 12 2 2 User Programmable Push Buttons Two user programmable push buttons are located at S3 and S4 Each of these can connect through a jumper to a Vybrid GPIO signal to facilitate software development The jumpers can be removed to make the Vybrid GPIO signals available for other uses JP20 Connects 53 to Vybrid signal MCU 8 JP21 Connects S4 to Vybrid signal MCU PTB9 12 2 3 Boot Configuration Switch The 8 position DIP switch at S5 provides a way to override the default boot option of
29. rmm 7 fe 11 m ER wl L a 5 1 a F2 ES 4 2 E Pur E E oo BHO 8 i aa x1 thas 2 ir e 26 e e e e e 2 29 0000000000 8 e 0000000000 000000 0000000000 m ee ee ee ee ee ee ee ee ee ee ee ee oe ee ee ee ee ee ee e 00000 ee e ee 000000000000 ee ee ee ee 0000 0000 6269 ee ecco Fig 12 3 phyCORE Vybrid Connectors Bottom PHYTEC America LLC 2012 35 Il Chapter 12 Overview of Peripherals L 783e 0 The table below lists the connectors on the phyCORE Vybrid Carrier Board Table 12 1 phyCORE Vybrid Connectors DECIES Description Chapter X1 phyCORE Connectors for SOM connectivity 2 X2 5 V power input primary power input 3 A capacity 15 XT RJ45 connector 16 X8 USB 2 0 Dual Standard A 19 X9 Secure Digital Memory MultiMedia Card slot 21 X10 RS 232 Dual DB9 Female 17 X11 Ethernet1 16 RJ45 X12 CAN Dual DB9 Male 18 X13 USB Mini AB for K20 Debug Circuit 24 X
30. shows default positions possible alternative positions and functions A detailed description of each solder jumper can be found in the applicable chapter listed in the table Some jumpers designed into the schematic are not listed in this manual These jumpers should not be modified as they are for special purposes outside of normal functional configuration If manual jumper modification is required pay special attention to the TYPE column in Table 3 1 ensuring the use of the correct jumper type 0 Ohms 10k Ohms etc All jumpers are 0805 package or 0402 package with a 1 8W or better power rating A detailed description of each solder jumper can be found in the applicable chapter listed in the table PHYTEC America LLC 2012 17 Chapter 3 Jumpers Table 3 1 SOM Jumper Settings L 783e_0 Jumper Setting Description Type Chapter J1 1 2 Sets EEPROM lower address bit 1 OR 0402 7 4 1 2 3 Sets EEPROM lower address bit A1 0 J2 1 2 Sets EEPROM lower address bit A2 1 OR 0402 7 4 1 2 3 Sets EEPROM lower address bit A2 0 J6 1 2 The EEPROM is writeable 0402 7 4 2 The EEPROM is write protected PHYTEC America LLC 2012 18 Chapter 4 Power L 783e 0 4 Power The phyCORE Vybrid operates off of a single 3 3V system power supply An overview of the power design is shown in the figure below U6 DDR3 Memory VDD_1V5_ DOG VDD 1V controller VDD 3V3 U2 U3
31. 0 19A PTD17 lO VDD 3V3 Flash 101 20A PTD18 IO VDD_3V3 NAND Flash 102 21 MCU PTD19 IO VDD_3V3 NAND Flash 103 22A GND Ground 0 V 23A MCU PTD24 VDD_3V3 NAND Flash 108 24 MCU PTD25 IO VDD_3V3 NAND Flash 109 25 MCU PTD26 lO VDD 3V3 NAND Flash 1010 26 MCU PTD27 VDD_3V3 NAND Flash 1011 27A GND Ground 0 V 28A 26 lO VDD_3V3 NAND Flash Ready Busy 29A 27 IO VDD_3V3 NAND Flash address latch enable 30A MCU 28 lO VDD_3V3 NAND Flash command latch enable 31A MCU 29 3V3 32A GND Ground 0 V PTC30 3V3 34 PTDO OUT VDD_3V3 QSPIO A clock 35A PTD1 3V3 QSPIO A chip select 36A MCU PTD2 lO VDD_3V3 QSPIO A hold 37A GND Ground 0 V 38A MCU_PTD3 IO VDD_3V3 QSPIO write protect 39A MCU PTD4 3V3 QSPIO A data 1 40 MCU_PTD5 lO VDD_3V3 QSPIO A data 0 41A PTD6 IO VDD_3V3 SD Card Detect SDCD 42A GND Ground 0 V 43A 4 lO VDD_3V3 RMIIO Receive Data 0 44A 5 VDD_3V3 RMIIO Receive Error 45 6 IO VDD_3V3 RMIIO Transmit Data 1 46 PTC7 IO VDD_3V3 RMIIO Transmit Data 0 47A GND Ground 0 V PHYTEC America LLC 2012 Part Chapter 2 Pin Description L 783e_0 Table 2 1 Pinout of the phyCORE Connector X1 Row A Continued Pin Signal Type SL Descriptio
32. 1 Jumper Locations and Default Settings The phyCORE Carrier Board comes pre configured with 22 removable jumpers and 4 solder jumpers Figure 13 1 provides a detailed view of the phyCORE Vybrid Carrier Board jumpers and their default settings The jumpers allow the user flexibility of configuring a limited number of features for development purposes Figure 13 2 depicts the jumper pad numbering scheme for reference when altering jumper settings on the development board a beveled edge indicates the location of pin 1 removable jumper solder jumper 2 1 4 6 2 1 8 3 2 Fig 13 2 Jumper Numbering Scheme 1 5 5 7 Before making connections to peripheral connectors consult the applicable sections in this manual for setting the associated jumpers Table 13 1 is a list of all Carrier Board jumpers their default positions and their functions in each position The table only provides a concise summary of jumper descriptions For a detailed descriptions see the applicable chapter listing in the right hand column of the table PHYTEC America LLC 2012 41 Il Chapter 13 Jumpers L 783e_0 The following conventions were used in naming jumpers on the Carrier Board e J solder jumper JP removable jumper Table 13 1 Jumper Settings and Descriptions Jumper Setting Description Chapter JP1 CLOSED The SOM s VBAT supply connect
33. 1 transmit data minus D28 ETH1 TXP LVDS VDD 3V3 Ethernet1 transmit data plus D29 GND Ground 0 V 030 ETH1 LEDO OUT VDD 3V3 Ethernet1 LED 0 D31 ETH1 LED1 OUT VDD 3V3 Ethernet1 LED 1 D32 MCU PTA12 IO VDD_3V3 Trace clock 033 16 IO VDD_3V3 Trace Data 0 034 GND Ground 0 V 035 PTA21 IO VDD_3V3 Trace data 5 036 PTA22 IO VDD_3V3 Trace data 6 PHYTEC America LLC 2012 14 Part Chapter 2 Pin Description L 783e_0 Table 2 4 Pinout of the phyCORE Connector X1 Row D Continued Pin Signal Type SL Description 037 PTA23 IO VDD_3V3 Trace data 7 D38 PTA24 lO VDD_3V3 Trace data 8 039 GND Ground 0 V 040 PTA29 IO VDD_3V3 Trace data 13 041 lO VDD_3V3 Trace data 14 042 1 IO VDD_3V3 Trace data 15 043 OUT VDD_3V3 Display horizontal sync D44 GND Ground 0 V 045 PTE5 OUT VDD_3V3 Display red 0 046 MCU OUT VDD_3V3 Display red 1 047 MCU_PTE7 OUT VDD_3V3 Display red 2 048 MCU PTE8 OUT VDD_3V3 Display red 3 D49 GND Ground 0 V D50 1 OUT VDD_3V3 Display green 0 051 PTE14 OUT VDD_3V3 Display green 1 052 MCU 15 OUT VDD_3V3 Display green 2 053 MCU PTE16 OUT VDD_3V3 Display green 3 D54 GND Ground 0 V 055 MCU PTE21 OUT VDD_3V3 Display blue 0 056 MCU PTE22 OUT VDD_3V3 Display blue 1 057 MCU PTE23 OUT VDD_3V3 Display bl
34. 12 76
35. 16 1 27mm JTAG Reduced Trace pin header 24 X19 VFx00 2 54mm JTAG pin header 24 X20 Line in 3 5 mm audio jack 22 21 Expansion connectors 27 X22 VFx00 JTAG Full Trace Mictor connector 24 X24 Display pin header 20 X25 Microphone 3 5 mm audio jack 22 X26 5 V power input alternate connector 16 A capacity 15 X27 Line out 3 5 mm audio jack 22 X28 Headphone 3 5 mm audio jack 22 X29 Display connector for the TTL display 20 X30A amp X30B Display PHYTEC Display Interface data and power connectors 20 X31 RS 232 pin header 17 CAUTION Ensure that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller User s Manual Data Sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals PHYTEC America LLC 2012 36 Il Chapter 12 Overview of Peripherals L 783e 0 12 2 Buttons and Switches 021 21 4220 Fig 12 4 Buttons and Switches The phyCORE Vybrid Carrier Board is populated with four push button switches and an 8 position DIP switch These are essential for the operation of the phyCORE Vybrid module on the Carrier Board Figure 12 4 shows their locations while their functions are
36. 3V3 JTAG Chain Test Mode Select signal 3 GND Ground 4 MCU IN VCC 3V3 JTAG Chain Test Clock signal 5 GND Ground 6 MCU PTA10 OUT VCC 3V3 JTAG Chain Test Data Output 7 no pin Should be removed from the connector 8 MCU PTA9 IN VCC 3V3 JTAG Chain Test Data Input PHYTEC America LLC 2012 62 Part Il Chapter 23 JTAG L 783e 0 Table 23 1 JTAG Connector X16 Signals Continued Pin Signal Type SL Description 9 no connect 10 RESETn System Reset 11 5 V Supply PWR 5 0 5 12 PTA12 VCC 3V3 Trace clock 13 5 V Supply PWR 5 0 5 V Supply 14 PTA16 10 3V3 Trace Data 0 15 17 GND Ground 19 16 PTA17 10 VCC 3V3 Trace D1 18 PTA18 10 VCC 3V3 Trace D2 20 PTA19 VCC_3V3 Trace D3 Table 23 2 JTAG Connector X19 Signals Pin Signal Type SL Description 1 2 VCC_3V3 REF VCC_3V3 JTAG Chain Reference Voltage 3 TRSTn IN VCC 3V3 JTAG Chain Test Reset 4 6 8 Ground 10 12 14 18 20 5 MCU PTA9 IN VCC 3V3 JTAG Chain Test Data Input 7 MCU PTA11 IN VCC 3V3 JTAG Chain Test Mode Select signal 9 MCU IN VCC 3V3 JTAG Chain Test Clock signal 11 no connect JTAG Chain Return Test Clock signal 13 MCU PTA10 OUT VCC 3V3 JTAG Chain Test Data Output 15 SRST OUT VCC 3V3 System Reset PHYTEC America LLC 2012 63 Il Chapter 24 Trace 24 Tr
37. 6 of all EMI Electro Magnetic Interference problems stem from insufficient supply voltage grounding of electronic components in high frequency environments the phyCORE board design features an increased pin package The increased pin package allows dedication of approximately 2096 of all connector pins on the phyCORE boards to ground This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards even in high noise environments phyCORE boards achieve their small size through modern SMD technology and multi layer design In accordance with the complexity of the module 0402 packaged SMD components and laser drilled Microvias are used on the boards providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own design The phyCORE Vybrid is a sub miniature 41 x 51 mm insert ready SOM populated with Freescale FVx00 processor Its universal design enables its insertion into a wide range of embedded applications All processor signals and ports extend from the processor to high density pitch 0 5 mm connectors aligning two sides of the board This allows the SOM to be plugged like a big chip into a target application Precise specifications for the processor populating the board can be found in the applicable processor users manual and datasheet The descriptions in this manual are based on the Freescale FVx00 processo
38. D 015 indicates when 0581 is powered If either of these supplies goes into an over current condition the Vybrid will disable both PHYTEC America LLC 2012 52 Il Chapter 20 Display L 783e 0 20 Display JP4 Fig 20 1 Display Three separate display interface connections are provided on the Carrier Board Only one may be used at any given time three connection interfaces are sourced from the same display interface on the Vybrid processor Locations for X24 and X30 are found in Figure 20 1 the location of X29 is found in Figure 12 3 the only connector on the underside of the board Descriptions for the three connection interfaces are X24 This connector provides the 3 3V TTL level display signals power 3 3V and GND on a 2 54mm pin header for easy access x29 This connector connects to a low cost display provided by PHYTEC The display is a 7 TFT panel with a resolution of 800x480 24bpp manufactured by the HTDISPLAY ELECTRON ICS CO LTD This display has no touch interface X30A These connectors comply with the PHYTEC Display Interface PDI for connection to a X30B range of LCD display boards provided by PHYTEC X30A provides data and control signals while X30B provides power and auxiliary control PHYTEC America LLC 2012 53 Part Il Chapter 20 Display L 783e 0 20 1 Display Signals Connector X24 has been provided to give easy access to the Vybrid pr
39. Install jumper JP1 1 2 to connect the VBAT supply to the phyCORE Vybrid 15 3 Current Measurement To facilitate current measurement jumper JP22 is provided as a current measurement access point When JP22 is removed the voltage across its pins reflects the current supplied to the SOM through resistor R153 By default the value of R153 is 0 07 Ohm 1 PHYTEC America LLC 2012 46 Il Chapter 16 Ethernet L 783e 0 16 Ethernet p arz E MITES BUNI g m E o anm mimm tee UB VERIS d E ARE c un 1 0000000000 2000000000 MUT 5REmra xd 11 2 m T I m e HH e e TEREC z mm Be z mom E a 1 Ze a EB BE KE ER eee Fig 16 1 Ethernet Interface Connectors The 10 100 Ethernet interfaces on the SOM are accessible at RJ 45 connectors X7 and X11 EthernetO routes to connector X7 and Ethernet1 routes to X11 The LEDs for LINK green and SPEED yellow indication are integrated
40. M through the K20 the system must be held in reset and jumper JP28 must be configured to select one of the two Flash devices as the programming target As of the writing of this manual software support for programming the SPI Flashes through the K20 circuit is not available The system can be reset directly with the K20 s GPIO signal PTB1 or there are options for putting the system in reset with a jumper across X15 pins Table 25 1 shows options to put the system in reset with X15 and the JP28 jumper settings to select the target device PHYTEC America LLC 2012 66 Part Il Chapter 25 K20 L 783e 0 Table 25 1 K20 Jumper Configurations Jumper Setting Description Chapter X15 1 2 The system is reset while the SPI Flash Button 7 is pressed 25 3 4 The system is reset with the K20 SPIO select signal K20 SPIO CS 5 6 The system is reset with the K20 GPIO signal 20 GPIO PTD6 7 8 The system is reset while this jumper is installed JP28 1 2 Select SPI Flash 25 2 3 Select SPI Flash B PHYTEC America LLC 2012 67 Il Chapter 26 Tamper L 783e_0 26 Tamper 19 9e 152 Fig 26 1 Tamper The phyCORE Vybrid provides access to two passive TAMPER 1 0 and two active TAMPER 3 2 tamper detection signals from the 00 Security violations from the VFx00 tamper detection mechanism can be enabled to be a source of reset In addition to routing all four of these signals to the GPIO Expan
41. RE Vybrid Power 19 Fig 9 1 phyCORE Vybrid Physical Dimensions 27 Fig 10 1 phyCORE Vybrid 29 Part Il PCM 952 phyCORE Vybrid Carrier 31 Fig 11 1 phyCORE Vybrid Carrier 32 Fig 12 1 Overview of 5 34 Fig 12 2 phyCORE Vybrid Connectors 35 Fig 12 3 phyCORE Vybrid Connectors 35 Fig 12 4 Buttons and 37 Fig 12 5 2254 puma Re ide imis desee des DRACO EIE 39 Fig 13 1 Jumper Locations and Default 5 41 Fig 13 2 Jumper Numbering Scheme 41 Fig 14 1 phyCORE Vybrid SOM Connectivity to the Carrier Board 44 Fig 15 1 Powering Scheme oi csse iss rue s heh n 45 Fig 16 1 Ethernet Interface 5 47 Fig 17 1 RS 232 Interface 5 48 Fig 17 2 DB 9 RS 232 Connectors P1B Pin
42. RNA RN RENE GRE YE HET nage 55 20 3 PHYTEC Display Interface 56 20 4 Touch Screen iiu d uc 5 Vx Oe UR eR RO Rm RR 58 20 5 Light Sensor 22 da bade cid Perd raro v Re Fever 58 21 e sott Rem n Re tert e ate D Pam Pains SCR RR RD e Pe dt 59 22 AUdlO ridge DRUG ER Vea TORRE 60 RNC PR Pp 62 24 l i eia deed Rue ibid oe Exe Lore telat d is LR e i 64 DM M Pr 66 26 PRETI 68 Part PCM 957 GPIO Expansion 69 yai 70 28 Analog Signal 71 29 Control Signal 72 30 Processor Signal 73 31 Power Signal 75 Revision History rx 76 PHYTEC America LLC 2012 ii List of Tables L 783e_0 List of Tables Conventions Abbreviations and Acronyms Table 1 1 Abbreviations and Acronyms Used This Manual Table 1 2 Types of
43. T VCC_3V3 SPI 0 clock 2 MCU_PTB21 IN VCC 3V3 SPI 0 master data in slave data out 3 MCU PTB20 OUT VCC 3V3 SPI 0 master data out slave data in 4 MCU PTB19 OUT VCC 3V3 SPI 0 chip select display adapter 5 no connect not connected 6 VCC 3V3 PWR VCC 3V3 Logic supply voltage 7 2 SCL OUT VCC 3V3 2 clock signal 8 2 SDA VCC_3V3 2 data signal 9 GND Ground 10 MCU PTBO OUT VCC 3V3 PWM brightness control 11 VCC 3V3 PWR VCC 3V3 Logic supply voltage 12 no connect not connected 13 MCU PTB3 OUT VCC 3V3 Display enable signal 14 no connect not connected 15 GND Ground 16 USB1 DP USB Data plus 17 USB1_DM IO USB Data minus 18 GND Ground 19 DISP_LVDS_0 LVDS VCC 3V3 LVDS data channel 0 negative output 20 DISP LVDS 0 LVDS VCC 3V3 LVDS data channel 0 positive output 21 GND Ground 22 DISP LVDS 1 LVDS VCC 3V3 LVDS data channel 1 negative output 23 DISP LVDS 1 LVDS VCC 3V3 LVDS data channel 1 positive output 24 GND Ground 25 DISP LVDS 2 LVDS VCC 3V3 LVDS data channel 2 negative output 26 DISP LVDS 2 LVDS VCC 3V3 LVDS data channel 2 positive output PHYTEC America LLC 2012 57 Part Il Chapter 20 Display L 783e_0 Table 20 4 PDI Connector X30B Signal Descriptions Continued Pin Signal Type SL Description 27 GND Ground 28 DISP LVDS 3 LVDS VCC 3V3 LVDS data channel 3 negative output 29 DISP LVDS 3 LVDS VCC 3V3 LVDS data ch
44. TD20 208 20B 3V3 Flash 104 MCU PTD21 218 21B 3V3 NAND Flash 105 MCU PTD22 228 22B IO VCC NAND Flash 106 MCU_PTD23 23B 23B IO 3V3 NAND Flash 107 MCU_PTD24 23A 23A Flash 8 MCU_PTD25 24 24 3V3 NAND Flash 109 MCU PTD26 25A 25A 3V3 Flash 1010 MCU PTD27 26A 26A 3V3 Flash 1011 MCU_PTD28 258 25 NAND Flash 1012 MCU_PTD29 268 268 3V3 Flash 1013 MCU_PTD30 278 27 3V3 Flash 1014 MCU PTD31 28 28B IO NAND Flash 1015 MCU PTE3 45C 8C GPIO 16 19 VCC 3V3 MCU PTB16 through CAN transceiver on SOM CANH1 15C 20C IO VCC_3V3 MCU_PTB17 through CAN transceiver on SOM PHYTEC America LLC 2012 74 Part 1 Chapter 31 Power Signal Mapping 31 Power Signal Mapping The power signals on the GPIO Expansion Board are shown below Table 31 1 Power Signal Map L 783e_0 Carrier Board Signal GPIO EB Pin GPIO EB Signal GND 49C 50C 51C 49D 50D 51D VCC4 VCC_3V3 52C 53C 54C 52C 53D 54D VCC3 GND 55C 56C 57C 55D 56D 57D VCC2 590 58 59 60 580 590 600 VCC1 PHYTEC America LLC 2012 75 L 783e_0 Revision History Table 32 1 Revision History Date Version Number Changes in this Manual 12 11 12 L 783e 0 Preliminary release PHYTEC America LLC 20
45. The phyCORE Vybrid Carrier Board provides a flexible development platform enabling quick and easy start up and subsequent programming of the phyCORE Vybrid System on Module The Carrier Board design allows easy connection of additional expansion boards featuring various functions that support fast and convenient prototyping and software evaluation The phyCORE Vybrid Carrier Board is designed for evaluation testing and prototyping of PHYTEC SOMs in laboratory environments prior to their use in customer designed applications This modular development platform concept includes the following components The phyCORE Vybrid System on Module populated with the VFx00 processor and all applicable SOM circuitry such as DDR3 SDRAM Flash and Ethernet transceivers to name a few The phyCORE Vybrid Carrier Board offers all essential components and connectors for start up including a power socket enabling connection to an external power adapter and interface connectors such as RS 232 USB CAN Ethernet allowing for use of the SOM s interfaces with standard cables The P eT Carrier Board has the following features for supporting the phyCORE Vybrid SOM Power supply circuits to supply the phyCORE Vybrid and the peripheral devices of the Carrier Board Two RS 232 interfaces brought out to a RS 232 connector and to a pin header Two USB interfaces brought out to a dual USB Standard A connector Two 10 100 Mbps Ethernet interfaces with RJ45 jacks Two CAN i
46. YTEC America LLC Bainbridge Island WA Rights including those of translation reprint broadcast photomechanical or similar reproduction and storage or processing in computer systems in whole or in part are reserved No reproduction may occur without the express written consent from PHYTEC America LLC EUROPE NORTH AMERICA Address PHYTEC Technologie Holding AG PHYTEC America LLC Robert Koch Str 39 203 Parfitt Way SW Suite G100 D 55129 Mainz Bainbridge Island WA 98110 GERMANY USA Ordering Information 49 800 0749832 1 800 278 9913 sales phytec de sales phytec com Technical Support 49 6131 9221 31 1 800 278 9913 support phytec de support phytec com Fax 49 6131 9221 33 1 206 780 9135 Website http Avww phytec eu http www phytec com http www phytec de PHYTEC America LLC 2012 L 783e_0 Table of Contents L 783e_0 Table of Contents List of 5 ee eee nmn ee iii List of iv Conventions Abbreviations and Acronyms PCM 052 phyCORE Vybrid System on Module 1 1 InitroduCtlonz uiu a p hen he etg eoe ges ae beg hae eal ae 2 1 1 phyCORE Vybrid 2 1 2 Minimum Requirements to Operate the phyCORE Vybrid
47. _PTE24 VCC_3V3 Display blue 3 28 MCU_PTE2 VCC 3V3 Display clock 29 GND GND Ground Ground 30 VCC 3V3 PWR VCC 3V3 Power PHYTEC America LLC 2012 54 Il Chapter 20 Display 20 2 TFT Display The FPC connector X29 connects to a 7 TFT panel with a resolution of 800x480 24bpp manufactured by the HTDISPLAY ELECTRONICS CO LTD Connector X29 is located on the bottom side of the board This display has no touch screen interface J1 JP30 Table 20 2 TTL Display Connector X29 L 783e 0 Selects the source for the 10 4 voltage to this display The J1 jumper setting should not be changed Installing JP30 enables the TTL display power 16V Removing the jumper disables it By default this jumper is installed and generally should not be removed Pin Signal Type SL Description 1 2 VCC 9V6 PWR VCC 9V6 9 6 V supply voltage 3 4 5 GND GND Ground 6 VDD 3V7 REF VDD 3V7 3 7 V reference voltage 7 VCC 3V3 PWR VCC 3V3 3 3 V supply voltage 8 DISP2 MODE OUT VCC 3V3 Display mode 9 MCU 4 OUT VCC 3V3 Display Enable 10 MCU PTE1 OUT VCC 3V3 Vertical Sync 11 MCU PTEO OUT VCC 3V3 Horizontal Sync 12 MCU PTE28 OUT VCC 3V3 Blue 7 13 MCU PTE27 OUT VCC 3V3 Blue 6 14 MCU PTE26 OUT VCC 3V3 Blue 5 15 MCU PTE25 OUT VCC 3V3 Blue 4 16 MCU PTE24 OUT VCC 3V3 Blue 3 17 MCU PTE23 OUT VCC 3V3 Blue 2 18 MCU PTE22 OUT VCC 3V3 Bl
48. able 12 5 LED Descriptions LED Label Color Description Chapter D3 5V red 5 V input power 15 07 LED3 green User LED 3 Vybrid analog control 12 3 D12 K20 green K20 Debug 12 3 D14 3V3 green 3 3 V power 15 D15 VBUS1 red USB1 VBUS 19 D16 VBUSO red USBO VBUS 19 D17 CAN green 5 V power to the CAN connector 18 D20 LED1 green User LED 1 Vybrid on off control 12 3 1 021 System reset 12 2 1 PHYTEC America LLC 2012 39 Part Il Chapter 12 Overview of Peripherals L 783e 0 12 3 1 User Programmable LEDs The phyCORE Carrier Board is equipped with two user programmable LEDs D7 D20 to facilitate software development Each LED can be disconnected from its processor signal to make the signal available for other uses D7 Is controlled by the Vybrid processor on the SOM The brightness can be set in 4096 steps from off to fully bright with the analog Vybrid DAC1 signal when jumper JP23 is installed D20 Is controlled by the Vybrid processor on the SOM and can be turned on and off by the Vybrid GPIO signal 10 when resistor R138 is installed PHYTEC America LLC 2012 40 Il Chapter 13 Jumpers L 783e_0 13 Jumpers JP4 JP23 JP16 JP15 JP14 28 TEER 5 JP18 Eees JP6 JPT 9 9 e 9 jp7 0 5 JP24 238 44 JP1 e Fig 13
49. ace Fig 24 1 Trace L 783e_0 22 MICTOR Connector X22 is an optional feature which provides direct connectivity to the phyCORE Vybrid processor Trace interface This connector does not come standard it must be special ordered Table 24 1 shows the signal locations and descriptions on connector X22 Table 24 1 Trace Connector X22 Pins Pin Signal Type SL Description 1 4 no connect 5 GND Ground 6 PTA12 10 VCC 3V3 Trace clock 7 8 no connect 9 RESETn OUT VCC 3V3 System reset 10 no connect 11 PTA10 OUT VCC 3V3 JTAG Chain Test Data Output 12 VCC 3V3 PWR VCC 3V3 3 3 V Supply 13 RTCK X22 OUT VCC 3V3 JTAG Chain Return Clock 14 VCC 3V3 PWR VCC 3V3 3 3 V Supply 15 IN VCC 3V3 JTAG Chain Test Clock signal 16 MCU PTA23 VCC 3V3 Trace Data 7 17 MCU PTA11 IN VCC 3V3 JTAG Chain Test Mode Select signal 18 PTA22 10 VCC_3V3 Trace Data 6 19 MCU 9 IN VCC_3V3 JTAG Chain Test Data Input signal PHYTEC America LLC 2012 64 Il Chapter 24 Trace Table 24 1 Trace Connector X22 Pins Continued L 783e_0 Pin Signal Type SL Description 20 PTA21 10 VCC_3V3 Trace Data 5 21 TRSTn_X22 VCC_3V3 JTAG Chain Target Reset signal 22 PTA20 10 3V3 4 23 PTA31 10 VCC_3V3 Trace Data 15 24
50. annel 3 positive output 30 GND Ground 31 LVDS CLKOUTM LVDS VCC 3V3 LVDS clock channel negative output 32 LVDS CLKOUTP LVDS VCC 3V3 LVDS clock channel positive output 33 GND Ground 34 TS Analog VCC 3V3 Touch 35 TS X Analog VCC 3V3 Touch X 36 TS Analog VCC 3V3 Touch Y 37 TS Y Analog VCC 3V3 Touch Y 38 TS WP OUT Touch write protect 39 GND Ground 40 LS ANA Analog Light sensor output a Provided to supply any logic on the display adapter 20 4 Touch Screen A touch screen controller at U14 on the Carrier Board provides a 4 wire resistive touch interface for displays connected to the PHYTEC Display Interface Note that this touch screen controller does not provide touch screen capabilities to the TFT LCD display that connects at X29 The touch screen controller connects to the Vybrid via I2C2 at address 0x41 7 MSB 20 5 Light Sensor An 8 bit ADC at U21 on the Carrier Board provides the analog input required for reading a light sensor located on one of the PDI compatible PHYTEC displays The ADC connects to the Vybrid via 12 2 at address 0x64 MSB PHYTEC America LLC 2012 58 Il Chapter 21 SD MMC L 783e_0 21 SD MMC 9000000000 e m 2 sd an too le m 2 ee 999 99 nn i
51. ard VBAT The VBAT V backup battery powers the on the SOM if jumper JP1 is installed Power LEDs on the phyCORE Vybrid Carrier Board are shown in the following table Table 15 2 Power LEDs LED Color Description D3 red 5VO supply voltage D14 green 3V3 supply voltage PHYTEC America LLC 2012 45 Il Chapter 15 Power L 783e_0 15 1 Wall Adapter Input Permissible input voltage at X2 or X26 5 V DC 10 CAUTION Do not use a laboratory adapter to supply power to the Carrier Board Power spikes during power on could destroy the phyCORE module mounted on the Carrier Board Do not change modules or jumper settings while the Carrier Board is supplied with power The required current load capacity of the power supply depends on the specific configuration of the phyCORE mounted on the Carrier Board the particular interfaces enabled while executing software and any optional expansion board connected to the Carrier Board An adapter with a minimum supply of 1 5A is recommended To power up the phyCORE plug in the power supply connector the red 5V LED and the green 3 3V LED should light up 15 2 VBAT To backup the RTC on the SOM a secondary voltage source of 3V can be attached to the phyCORE Vybrid at pin X1 C4 This voltage source supplies the backup voltage domain VBAT of the VFx00 which supplies the RTC and some critical registers when the primary system power is removed
52. arget application also requires connecting all GND pins neighboring signals that are being used in the application circuitry Please refer to Chapter 4 for more information PHYTEC America LLC 2012 3 Part Chapter 1 Introduction L 783e 0 1 3 Block Diagram QSPI Flash x2 SP with XIP x2 gt 4 SAI x4 ESAI SPDIF p gt Nexus Trace 16 bit 4 gt EthernetO gt SDHCO T PHY Ethernet1 gt 1 gt 4 SDHC1 gt NAND Flash FlexBus 16 bit gt Dual 4 5 x6 RS 232 RS232 x2 transceiver gt enable 2 lt CAN x2 transceiver a Vybrid 0 Processor bypas E 4 TAMPER gt 5 o Camera VIU gt SVGA TFT Display gt 8 46 2 10 channel 12 bit 2 12 bit DAC gt USB x2 gt gt 4 Flextimer 8 2 2 8 channels GPIO IRQ gt 4 DSPI x4 gt 147 120 with SMBUS support x4 4 Switch ERE BOOT configuration Reset 3 3 Volt
53. ate driver of the BSP To support all features of the phyCORE Vybrid Carrier Board a few changes have been made in the BSP delivered with the module Table 2 1 Pinout of the phyCORE Connector X1 Row A Pin Signal Type SL Description 1A MCU_PTBO IO VDD_3V3 Display brightness control 2A GND Ground 0 V 3A MCU_PTB4 IO VDD_3V3 serial transmit signal 4A MCU_PTB5 IO VDD_3V3 SCI1 RX serial receive signal 5A MCU PTB6 3V3 SCI22 TX serial transmit signal SCI1 RTS request to send 6A MCU PTB7 IO VDD_3V3 5 12 serial receive signal or SCI1 CTS clear to send GND Ground 0 8A MCU_PTB12 3V3 Display Up Down control 9A MCU_PTB13 lO VDD_3V3 Trace control PHYTEC America LLC 2012 Part Chapter 2 Pin Description L 783e_0 Table 2 1 Pinout of the phyCORE Connector X1 Row A Continued Pin Signal Type SL Description 10A EN IPU VDD 3V3 Drive low to disable the CAN transceivers on the SOM 11A RTC INTn OUT VDD 3V3 External Real Time Clock interrupt alarm 12A GND Ground 0 V 13 21 lO VDD 3V3 SPIO Master In Slave Out MISO 14A PTB22 IO VDD_3V3 SPIO clock 15A PTB23 IO VDD_3V3 GPIO 16 PTB24 VDD_3V3 NAND Flash write enable 17A GND Ground 0 V 18A PTD16 lO VDD 3V3 NAND Flash 10
54. bits The Flash device is programmable with 3 3V No dedicated programming voltage is required As of the printing of this manual NAND Flash devices generally have a life expectancy of at least 100 000 erase program cycles and a data retention rate of 10 years 7 3 QSPI NOR Flash The phyCORE Vybrid can be populated with one or two QSPI NOR Flash memories as an ordering option The flash devices connect to QSPIO A port and QSPIO B port QSPI Flash is substantially faster than traditional SPI flash devices due to four I O pins for data transfers as opposed to only one In addition QSPI is XIP compatible allowing the processor to boot directly from it The use of QSPI NOR Flash is suitable for systems which require a small code footprint or lack the software drivers required for bad block management in NAND Flash It can also potentially reduce BOM costs and free up NAND signals for other devices uses on the VFx00 Flexbus interface 7 4 EEPROM The phyCORE Vybrid can be populated with non volatile IC EEPROM as an ordering option This memory can be used to store configuration data or other general purpose data This device is accessed through port 2 on the Solder jumpers J1 and J2 are provided to set two of the lower address bits Refer to Chapter 7 4 1 for details on using these jumpers to set the EEPROM s address 1 The maximum memory size listed is as of the printing of this manual Please contact PHYTEC for
55. d Carrier Board design for a reference circuit The only default boot mode setting that should be changed by the user is the selection of the boot device The boot device is selected with five of the Vybrid configuration signals as shown in Table 6 1 The default configuration is to boot from UART or USBO The user can select an alternate boot device either by changing the resistor stuffing on the SOM for these signals or by overriding these signals from the Carrier Board Chapter 12 2 3 describes the switch on the Vybrid Carrier Board which can override the SOM default boot device configuration Table 6 1 Boot Device Selection Boot Device BOOTMOD1 BOOTMODO RCON7 RCONG RCON5 MCU PTEO MCU PTE1 MCU PTE16 PTE15 MCU PTE12 SPI 1 0 0 0 SD Card 1 0 1 1 0 NAND 1 0 0 0 1 UART USBO 0 1 0 0 0 Fuses 0 0 X X X The internal ROM code is the first code executed during the initialization process of the 00 after power on reset The ROM code detects the selected boot device by examining the latched state of the boot mode configuration pins For peripheral boot devices the ROM code polls the communication interface selected initiates the download of the code into the internal RAM and triggers its execution from there Peripheral booting is normally not applicable only after a warm reset Like most pins on the processor the boot mode configuration pins are multiplexed with other peripheral functions After the reset
56. d in this hardware manual particularly in respect to the pin header row connectors power connector and serial interface to a host PC Implementation of PHYTEC products into target devices as well as user modifications and extensions of PHYTEC products is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems The phyCORE Vybrid is one of a series of PHYTEC System on Modules that can be populated with different controllers and hence offers various functions and configurations PHYTEC supports a variety of 8 16 and 32 bit controllers in two ways 1 As the basis for Rapid Development Kits which serve as a reference and evaluation platform 2 insert ready fully functional phyCORE OEM modules which can be embedded directly into the user s peripheral hardware design Implementation of an OEM able SOM subassembly as the core of your embedded design allows you to focus on hardware peripherals and firmware without expending resources to re invent microcontroller circuitry Furthermore much of the value of the phyCORE module lies in its layout and test Production ready Board Support Packages BSPs and Design Services for our hardware further reduce development time and expenses Take advantage of PHYTEC products to shorten time to market reduce developme
57. de early change notifications concerning functional relevant changes of our Products Change management in rare event of an obsolete and non replaceable part Ensure long term availability by stocking parts through last time buy management according to product forecasts Offer long term frame contract to customers We refrain from providing detailed part specific information within this manual which is subject to changes due to ongoing part maintenance for our products PHYTEC America LLC 2012 viii PCM 052 phyCORE Vybrid System on Module L 783e_0 Part 1 PCM 052 phyCORE Vybrid System on Module Part 1 of this three part manual provides detailed information on the phyCORE Vybrid System on Module SOM designed for custom integration into customer applications The information in the following chapters is applicable to the 1374 0 PCB revision of the phyCORE Vybrid SOM PHYTEC America LLC 2012 1 Part Chapter 1 Introduction L 783e 0 1 Introduction The phyCORE Vybrid belongs to PHYTEC s phyCORE System on Module SOM family The phyCORE SOMs represent the continuous development of PHYTEC SOM technology Like its mini micro and nanoMODUL predecessors the phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments As independent research indicates that approximately 709
58. des a secondary time keeping source along with a secondary alarm mechanism to the processor via its interrupt signal The RTC is interfaced to the processor via the 12 2 port The 2 address of the device is binary 1101000x where the x bit is the read write operation bit The interrupt from the RTC routes to the phyCORE connector pin X1 A11 providing the Carrier Board the opportunity to use it for system wake circuitry or to connect it to a processor signal as an alarm interrupt The RTC is powered via the primary system 3 3V supply during normal operation and via the VBAT power input if itis present during power off See Chapter 4 4 for detailed information on providing backup power to the RTC via the VBAT power input PHYTEC America LLC 2012 21 Chapter 6 System Configuration and Booting L 783e_0 6 System Configuration and Booting Although most features of the VFx00 microcontroller are configured or programmed during software initialization other features which impact program execution must be configured prior to initialization via pin termination The system start up configuration includes e Clock configuration e Boot device configuration The processor boot mode is configured by latching the state of 24 boot mode configuration pins during a power on reset event The SOM includes a circuit which sets 23 of these CAUTION The Carrier Board must set the signal MCU PTB2 low during reset Please see the Vybri
59. erating Temperature to 70 commercial 40 C to 85 C industrial Humidity 95 r F not condensed Operating Voltage VCC 3 3V 5 VBAT 3 0 3 6V Power Consumption Typical VCC 3 3V 0 6A 1 98 Watts Maximum VCC 3 3V 1 0A 3 3 Watts Operating Conditions VF600 256 MB DDR3 SDRAM 512 MB NAND Flash Flash Ethernet 450 MHz CPU frequency 20 C a These specifications describe the standard configuration of the phyCORE Vybrid as of the printing of this manual b In order to guarantee reliable functioning of the SOM up to the maximum temperature appropriate cooling measures must be provided Use of the SOM at high temperature impacts the SOM s life span Table 9 2 Part information for phyCORE Connectors X1 Manufacturer Samtec Part Number lead free BSH 060 01 L D A receptacle Mating Connector BTH 060 01 L D A header Mated Height 5 mm Number of Pins Per Contact Rows 120 2 Rows of 60 pins each Different heights are offered for the receptacle sockets that correspond to the connectors populating the underside of the phyCORE Vybrid The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding Carrier Board In order to get the exact spacing the maximum component height 2 0 mm on the bottom side of the phyCORE must be subtracted Please refer to the corresponding datasheets and mechanical specifications provided by
60. hich require full DC DC isolation on the CAN interfaces the CAN transceivers can be removed and 0 Ohm resistors can be installed to bypass them In this configuration there is a direct connection between the TTL level signals and the CAN level signals leaving the CAN level signals operating at TTL levels If full DC isolation is required isolating transceivers can be designed into a Carrier Board Please see the phyCORE Vybrid Carrier Board schematic for a reference implementation PHYTEC America LLC 2012 26 Part Chapter 9 Technical Specifications L 783e 0 9 Technical Specifications The physical dimensions of the phyCORE Vybrid are presented in Figure 9 1 The module s profile is max 5 5 mm thick with a maximum component height of 2 0 mm on the bottom connector side of the PCB and approximately 2 5 mm on the top microcontroller side The board itself is approximately 1 0 mm thick gt ii rei 51mm D2 2mm mounting hole dimensions referenced to the outside edges have a tolerance of 0 2 mm all other dimensions have a tolerance of 0 1 mm unless otherwise noted Fig 9 1 phyCORE Vybrid Physical Dimensions PHYTEC America LLC 2012 27 Part Chapter 9 Technical Specifications L 783e 0 Table 9 1 Technical Specifications Dimensions 41 mm x 51 mm Weight Approximately 10 g with all optional components mounted on the circuit board Storage Temperature 40 to 125 Op
61. in the connectors This Ethernet PHYs on the SOM support the HP Auto MDIX function eliminating the need for considerations of a direct connect LAN cable or a cross over patch cable The transceivers detect the TX and RX signals of the connected devices and automatically configure their TX and RX pins accordingly PHYTEC America LLC 2012 47 Il Chapter 17 RS 232 L 783e_0 17 RS 232 eo utu nx 1 PE EI M ELO 16 mmm em sas i nimimm LXX nana TM m Tl 55 455 2000000000 uini TRITT 2 2 11 jee Bonz IF p E ee leo EMEN jee Ex F joe 1 le o le el eje lee AOC se feo ojoo mr n 6 1 Pm jim a e Titi a m n H m H A 3 ms a eee E m 1 E AP 357 000 eoo e ele e Fig 17 1 RS 232 Interface Connectors The DB 9 connector X10 provides the SCI1 signals of the 00 at RS 232 level it i
62. ing to the memory mapping of the Vybrid processor Please refer to the VFx00 TRM for the memory map PHYTEC America LLC 2012 24 Part Chapter 8 Serial Interfaces L 783e 0 8 Serial Interfaces The phyCORE Vybrid provides on board transceivers for three different serial interfaces 1 One RS 232 transceiver supporting two RX TX channels 2 Two 10 100 Ethernet PHYs 3 Two CAN transceivers The following sections of this chapter detail each of these serial interfaces and any applicable configuration jumpers 8 1 SCI RS 232 The phyCORE Vybrid provides an on board RS 232 transceiver at U15 This device provides RS 232 voltage level translation for either the SCI1 interface data signals with its RTS CTS hardware flow control signals or for both of the SCI1 and SCI2 interface data signals These 5 and RS 232 signals are available at the phyCORE connector Their locations are shown in Table 8 1 Table 8 1 5 RS 232 Signal Locations Signal Type SL Description 3A MCU 4 IO VDD 3V3 5 1 4A MCU PTB5 IO VDD_3V3 5 1 Rx 5A MCU_PTB6 IO VDD_3V3 5 1 RTS or SCI2 Tx 6A MCU PTB7 IO VDD_3V3 SCI1 CTS or SCI2 Rx 5 1 TX RS232 10 3 3 5 1 Tx at RS232 voltage 10C SCI2 TX RS232 10 3V3 5 1 RTS or SCI2 Tx at RS232 voltage 9C RS232 0 3V3 5 1 Rx at RS232 voltage 11C SCI2 RS232 0 3V3 SCI1 CTS or SCI2 Rx at RS232 voltage 8 2 Ethernet
63. le are performed regardless of their nature the manufacturer warranty is voided PHYTEC America LLC 2012 30 PCM 952 phyCORE Vybrid Carrier Board L 783e_0 Part Il PCM 952 phyCORE Vybrid Carrier Board Part 2 of this three part manual provides detailed information on the phyCORE Vybrid Carrier Board and its usage with the phyCORE Vybrid SOM The information and all board images in the following chapters are applicable to the 1375 2 PCB revision of the phyCORE Vybrid Carrier Board The Carrier Board can also serve as a reference design for development of custom target hardware in which the phyCORE SOM is deployed Carrier Board schematics with BoM are available under a Non Disclosure Agreement NDA Re use of Carrier Board circuitry likewise enables users of PHYTEC SOMs to shorten time to market reduce development costs and avoid substantial design issues and risks PHYTEC America LLC 2012 31 Part Il Chapter 11 Introduction L 783e 0 11 Introduction annnm ninm m 28 C 000000000 0 000000000 Pa LULA aa 000000 onm TUI E x 2 lt e 444 e Fig 11 1 phyCORE Vybrid Carrier Board
64. lternate configuration the signals route directly from the Vybrid processor to their phyCORE connector pins To use this configuration the transceivers must be physically removed from the SOM Please contact PHYTEC for more information about this configuration option On the Carrier Board 1 2 Default CANO signals route directly to DB9 connector X12 Alternate configuration CANO signals from the SOM route through a CAN transceiver before routing to X12 The transceiver on the Carrier Board meets or exceeds ISO 11898 specifications and it supports full DC isolation To use the transceiver on the Carrier Board the SOM must be configured to route the CANO signals directly to the phyCORE with the CANO transceiver physi cally removed from the SOM Although many configurations are possible generally the CANO interface will be run in one of three configurations 1 SOM Mode non isolated mode using the CANO transceiver on the SOM This is the default con figuration 2 CB Isolated Mode Isolated mode using the CANO transceiver on the Carrier Board Both data and power are isolated 3 CB Non Isolated Mode non isolated mode using the CANO transceiver on the Carrier Board PHYTEC America LLC 2012 50 Il Chapter 18 CAN Controller Area Network L 783e_0 Note that for both CB operating modes the CANO transceiver must be removed from the SOM Please contact PHYTEC for assistance in removing CAN transceviers on the SOM A s
65. more information about additional or new module configurations available PHYTEC America LLC 2012 23 Chapter 7 System Memory L 783e_0 Write protection to the device is accomplished via jumper J6 Refer to Chapter 7 4 2 for details on using the write protect feature 7 4 1 Setting the EEPROM Lower Address Bits The four upper address bits of the 12 EEPROM s 7 bit address are fixed at 1010 Lower address bit AO is wired to GND The phyCORE Vybrid SOM allows the user to configure the lower address bits A1 and A2 with jumpers J1 and J2 respectively Table 7 1 below shows the resulting seven bit device address for the four possible jumper configurations Table 7 1 U6 EEPROM Address J1 and J2 U9 Device Address J1 J2 1010 000x 2 3 2 3 1010 010 1 2 2 3 1010 100 2 3 1 2 1010 110 1 2 1 2 7 4 2 EEPROM Write Protection Control 46 Jumper J6 controls write access to the EEPROM U9 device Closing this jumper allows write access to the device while removing this jumper will cause the EEPROM to enter write protect mode thereby disabling write access to the device The following configurations are possible Table 7 2 EEPROM Write Protection States J6 EEPROM Write Protection State J6 Write access allowed closed Write protected open 7 5 Memory Model There is no special address decoding device on the phyCORE Vybrid which means that the memory model is given accord
66. n 48A 1 VDD_3V3 RMII1 Receive Data 0 49A MCU_PTC14 VDD_3V3 RMII1 Receive Error 50A 15 VDD_3V3 RMII1 Transmit Data 1 51A MCU_PTC16 RMII1 Transmit Data 0 52A GND Ground 0 53A VADCSEO Analog VDD 3V3 Analog signal 54A VADCSE1 Analog 3V3 Analog signal 55A VADCSE2 Analog 3V3 Analog signal 56A VADCSE3 Analog 3V3 Analog signal 57A GND Ground 0 V 58A DACOO Analog 3V3 Analog signal 59A DACO1 Analog 3V3 Analog signal 60A VREFH REF VDD 3V3 Analog reference voltage Table 2 2 Pinout of the phyCORE Connector X1 Row B Pin Signal Type SL Description 1B MCU PTB1 IO VDD_3V3 Audio 25 DOUT 2B MCU_PTB2 lO VDD_3V3 GPIO and 1 boot signal must be low during system reset 3B MCU_PTB3 lO VDD_3V3 Display enable control signal 4B GND Ground 0 V 5B MCU PTB8 IO VDD_3V3 GPIO 6B MCU_PTB9 IO VDD_3V3 GPIO 7B MCU_PTB10 IO VDD_3V3 GPIO 8B MCU PTB11 IO VDD_3V3 Audio codec master clock 9B GND Ground 0 V 10B WPn VDD_3V3 NAND Flash write protect 11B 18 IO VDD_3V3 GPIO 128 PTB19 IO VDD_3V3 GPIO 13B PTB20 SPIO Master Out Slave In MOSI 14B GND Ground 0 V 15B 25 IO VDD_3V3 NAND Flash chip enable 168 MCU_PTB26 IO VDD_3V3 GPIO 17B MCU PTB27 IO VDD_3V3 NAND Flash read enable 188 MCU PTB28 lO VDD_3V3 GPIO
67. nfiguration C10 SCI2 TX RS232 OUT 3V3or PTB6 or RS232 2 Tx from transceiver RS232 U15 depending on SOM configuration C11 5 2 RS232 IN 3V3or PTB7 or RS232 2 Rx from transceiver RS232 U15 depending on SOM configuration C12 GND Ground 0 V C13 CANO HI IO VDD_3V3 or MCU_PTB15 or CANO HI from transceiver CAN U13 depending on SOM configuration C14 LO IO VDD_3V3 or MCU_PTB14 or CANO LO from transceiver CAN U13 depending on SOM configuration C15 IO VDD_3V3 or MCU_PTB17 or CAN1 HI from transceiver CAN U14 depending on SOM configuration C16 LO IO VDD_3V3 or MCU_PTB16 or CAN1 LO from transceiver CAN U14 depending on SOM configuration C17 GND Ground 0 V C18 VBUS_USBO USB VBUS 0580 5 0 V USBO VBUS supply C19 0580 VBUS DETECT IN 5 PD Detect signal for the USBO VBUS supply C20 USBO DP DIFF90 VDD 3V3 USBO data plus C21 0580 DM DIFF90 VDD 3V3 USBO data minus C22 GND Ground 0 V C23 LVDS 0 3V3 EthernetO receive data minus C24 ETHO RXP LVDS 0 3V3 EthernetO receive data plus C25 LVDS 0 3 3 EthernetO transmit data minus C26 TXP LVDS 0 3V3 EthernetO transmit data plus PHYTEC America LLC 2012 12 Part Chapter 2 Pin Description L 783e_0 Table 2 3 Pinout of the phyCORE Connector X1 Row C Continued
68. nt costs and avoid substantial design issues and risks For more information go to http www phytec com services design services index html PHYTEC America LLC 2012 vii L 783e_0 Product Change Management In addition to our HW and SW offerings the buyer will receive a free obsolescence maintenance service for the HW provided when purchasing a PHYTEC SOM Our Product Change Management Team of developers is continuously processing all incoming PCN s Product Change Notifications from vendors and distributors concerning parts which are being used in our products Possible impacts to the functionality of our products due to changes of functionality or obsolesce of a certain part are evaluated in order to take the right measures in purchasing or within our HW SW design Our general philosophy here is We never discontinue a product as long as there is demand for it Therefore a set of methods has been established to fulfill our philosophy Avoidance strategies e Avoid changes by evaluating longevity of a parts during design in phase Ensure availability of equivalent second source parts Maintain close contact with part vendors for awareness of roadmap strategies Change management in case of functional changes Avoid impacts on Product functionality by choosing equivalent replacement parts Avoid impacts on Product functionality by compensating changes through HW redesign or backward compatibility SW maintenance e Provi
69. nterfaces one available at a male DB9 connector with optional optical isolation and another available at the GPIO Expansion Connector Audio codec and connectors supporting MIC in stereo headphone out stereo line out and stereo line in PHYTEC America LLC 2012 32 Part Il Chapter 11 Introduction L 783e 0 Display Interface connector with touch screen and light sensor support TTL display connector supporting a low cost display panel made by HTDisplay Electronics Co Ltd Display pin header enabling connection of custom display interfaces and easy access to display signals e Secure Digital Memory Card MultiMedia Card Interface SD MMC e K20 processor supporting openSDA protocol and CMSIS DAP for multicore debugging with the ARM Development Studio 5 tool suite JTAG connector for the VFx00 processor on the SOM e Access to phyCORE Vybrid s TAMPER security signals Expansion board connectors for easy access to most processor signals switch to configure processor boot source e Backup battery to power the Real Time Clock Reset power and user buttons and LEDs The following sections contain information specific to the operation of the phyCORE Vybrid SOM mounted on the phyCORE Vybrid Carrier Board PHYTEC America LLC 2012 33 Il Chapter 12 Overview of Peripherals L 783e 0 12 Overview of Peripherals
70. ocessor s display interface When using the following signals for display signal type will change to OUT The pin out for connector X24 is provided below Table 20 1 TTL Display Pin Header X24 Pin Signal Type SL Description 1 MCU PTE7 VCC 3V3 Display red 2 2 MCU PTE25 VCC_3V3 Display blue 4 3 MCU_PTE8 VCC 3V3 Display red 3 4 MCU PTE26 VCC_3V3 Display blue 5 5 MCU_PTE9 VCC 3V3 Display red 4 6 MCU PTE27 3V3 6 7 PTE10 VCC_3V3 Display red 5 8 MCU_PTE28 3V3 7 9 1 VCC 3V3 Display red 6 10 MCU PTE5 3V3 0 11 PTE12 VCC_3V3 Display red 7 12 MCU_PTE6 VCC_3V3 Display red 1 13 MCU_PTE15 Display green 2 14 MCU_PTE13 VCC 3V3 Display green 0 15 MCU PTE16 VCC 3V3 Display green 3 16 MCU PTE14 VCC_3V3 Display green 1 17 MCU_PTE17 VCC_3V3 Display green 4 18 MCU_PTE21 3V3 0 19 PTE18 VCC_3V3 Display green 5 20 MCU_PTE22 VCC 3V3 Display blue 1 21 MCU PTE19 VCC 3V3 Display green 6 22 MCU PTEO Display horizontal sync 23 MCU_PTE20 VCC 3V3 Display green 7 24 MCU PTE1 3V3 Display vertical sync 25 MCU_PTE23 VCC 3V3 Display blue 2 26 MCU 4 3V3 Display enable 27 MCU
71. on like a big chip The numbering scheme for the phyCORE Connector is based on a two dimensional matrix in which column positions are identified by a letter and row position by a number Pin 1A for example is always located in the upper left hand corner of the matrix The pin numbering values increase moving down on the board Lettering of the pin connector rows progresses alphabetically from left to right refer to Figure 2 1 The numbered matrix can be aligned with the phyCORE Vybrid viewed from above phyCORE Connector pointing down or with the socket of the corresponding phyCORE Carrier Board user target circuitry The upper left hand corner of the numbered matrix pin 1A is thus covered with the corner of the phyCORE Vybrid marked with a number 1 The numbering scheme is always in relation to the PCB as viewed from above even if all connector contacts extend to the bottom of the module The numbering scheme is thus consistent for both the module s phyCORE Connector as well as mating connectors on the phyCORE Carrier Board or target hardware thereby considerably reducing the risk of pin identification errors Since the pins are exactly defined according to the numbered matrix previously described the phyCORE Connector is usually assigned a single designator for its position X2 for example In this manner the phyCORE Connector comprises a single logical unit regardless of the fact that it could consist of more than one physical socke
72. ot have 20 power OPEN U28 supplies power for the TTL display connector X15 1 2 Reset with the SPI Flash Button 24 3 4 Reset the Vybrid with the K20 SPIO CS signal 5 6 Reset the Vybrid with the K20_GPIO_PTD6 signal 7 8 Reset while this jumper is installed OPEN Normal system use J1 1 2 10 4 is supplied by U6 20 2 2 3 10 4 is supplied by Q1 J2 CLOSED The audio codec external oscillator OZ1 is enabled 22 2 3 The audio codec external oscillator OZ1 is disabled J3 J4 1 2 USB1 routes to Display Connector X30 19 2 3 USB1 routes to USB1 connector 8 PHYTEC America LLC 2012 43 Il Chapter 14 phyCORE Vybrid SOM Connectivity L 783e_0 14 phyCORE Vybrid SOM Connectivity 0000000 1 1 2000000 5 E a z 7i a LE ni s c bool 3 E x1 E E By 200 900 ee own 1 nm un iii ee a 900900 EX H H a sa te ene H 49 eo ow ee eee 1 ccoo 5 5 a 0000 SE 00000 eoo o ecce 9 9 ei A
73. r No description of compatible processor derivative functions is included as such functions are not relevant for the basic functioning of the phyCORE Vybrid 1 1 phyCORE Vybrid Features Insert ready sub miniature 41 mm x 51 mm System on Module SOM subassembly in low EMI design achieved through advanced SMD technology e Populated with the Freescale FVx00 Single Cortex A5 or heterogenous Dual Core Cortex A5 and Cortex M4 processor e 500 MHz core clock frequency for the Cortex A5 167 MHz for the Cortex M4 Boot from NAND Flash or SPI Flash e Controller signals and ports extend to two high density 0 5 mm Samtec connectors aligning two sides of the board enabling it to be plugged like a big chip into target application Single supply voltage of 3 3 V max 1 A All controller required supplies generated on board Improved interference safety achieved through multi layer PCB technology and dedicated ground pins 256 MB up to 2 GB on board NAND Flash 128 256 512 MB DDR3 SDRAM 1 up to 32 I2C EEPROM e 32 MB up to 128 MB SPI Flash e Two RS 232 two signal Tx Rx serial interfaces one RS 232 interface with hardware flow control configured through software Dual USB OTG 2 0 High Speed Controller with PHY 1 The maximum memory size listed is as of the printing of this manual Please contact PHYTEC for more information about additional or new module configurations available
74. rd PCM 957 is made available through PHYTEC to connect to the GPIO Expansion Connectors This Expansion Board provides a patch field for easy access to signals and additional board space for testing and prototyping Tables detailing signal mapping between the phyCORE connectors and the patch field on the GPIO Expansion Board are provided in the following chapters PHYTEC America LLC 2012 70 Part Chapter 28 Analog Signal Mapping 28 Analog Signal Mapping The processor s analog signals on the GPIO Expansion Board are shown below Table 28 1 Analog Signal Map L 783e_0 Signal SOM Pin GPIO EB Pin Type SL Description VADCSEO 53A 53A lO analog VADCSE1 54A 54A IO 3V3 analog IO VADCSE2 55A 55A IO 3V3 analog IO VADCSE3 56A 56A IO analog DACOO 58A 58A 3V3 analog IO 1 59 59 analog ADCOSE8 55B 55B lO VCC_3V3 analog ADCOSE9 56B 56B lO 3V3 analog IO ADC1SE8 57B 57B 3V3 analog ADC1SE9 58B 58B analog VREFL_ADC 60B 60B REF VCC 3V3 Analog reference voltage high 60 60A REF 3V3 Analog reference voltage low PHYTEC America LLC 2012 71 Part Chapter 29 Control Signal Mapping 29 Control Signal Mapping Various control signals and other Carrier Board circuitry made available on the GPIO Expansion Board are
75. rom 12 288 MHz to 50 MHz In the default position JP5 2 3 the codec is clocked from the module s MCU_PTA11 audio clock signal The 11 signal is also used for the K20 debug interface To use the K20 and audio functions at the same time the audio codec can instead be clocked by the crystal oscillator by setting JP5 1 2 PHYTEC America LLC 2012 60 Il Chapter 22 Audio L 783e_0 Audio devices can be connected at X20 X25 X27 and X28 The audio connectors descriptions are listed in Table 22 1 Table 22 1 Audio Connectors Connector Description X20 Stereo line in X25 Mono microphone in X27 Stereo line out X28 Stereo headphone out PHYTEC America LLC 2012 61 Il Chapter 23 JTAG L 783e_0 23 JTAG Fig 23 1 JTAG Connectivity The JTAG interface of the phyCORE Vybrid is accessible at connectors X16 and X19 on the Carrier Board This interface is compliant with JTAG specification IEEE 1149 1 and IEEE 1149 7 X16 Provides JTAG signal access with a limited number of trace signals on a 1 27mm header X19 Provides JTAG signal access on a standard 2 54mm ARM JTAG header The signal connections for each of these connectors are described in the tables below When referencing contact numbers note that pin 1 is located at the beveled corner Table 23 1 JTAG Connector X16 Signals Pin Signal Type SL Description 1 VCC 3V3 PWR VCC 3V3 3 3 V Power 2 MCU PTA11 IN VCC
76. s the default communication port The X31 pin header provides the SCI2 signals at RS 232 level Table 17 2 and Table 17 1 show the signal locations and descriptions for these connectors wk Ye Fig 17 2 DB 9 RS 232 Connectors P1B Pin Numbering PHYTEC America LLC 2012 48 Part Il Chapter 17 RS 232 Table 17 1 X10 Pin Descriptions L 783e_0 Pin Signal Type SL Description 1 N C Not connected 2 SCI1 TX RS232 OUT RS 232 UARTI transmit signal at RS232 level 3 SCI1 RX RS232 IN RS 232 UARTI receive signal at RS232 level 4 N C Not connected 5 GND Ground 6 N C Not connected 7 N C Not connected 8 N C Not connected 9 N C Not connected Table 17 2 X31 Pin Descriptions Pin Signal Type SL Description 1 MCU PTB6 OUT RS 2232 SCI2 TX at RS 232 level GND Ground 0 V 3 MCU PTB7 IN RS 232 SCI2 at RS 232 level PHYTEC America LLC 2012 49 Il Chapter 18 CAN Controller Area Network L 783e_0 18 CAN Controller Area Network 15 JP14 eese 6 e ej e e 22224 JP18 JP9 JP6 9 Fig 18 1 CAN Interface Connectors and Jumpers The CAN interfaces are configurable on both the SOM and the Carrier Board On the SOM 1 2 Default the signals route through CAN transceivers The CAN transceivers on the SOM are com patible with ISO 11898 They do not support full DC isolation A
77. s this hardware manual other information is available to facilitate the integration of the phyCORE Vybrid into customer applications design of the phyCORE Vybrid Carrier Board be used as a reference for any customer application Reference schematics are available upon request Answers to many common questions can be found at www phytec de de support faq faq phycore Vybrid html or www phytec eu europe support faq faq phycore Vybrid html Different support packages are available to support you in all stages of your embedded development For North America please visit http www phytec com support contract html For Europe and Asia please visit www phytec de de support support pakete html www phytec eu europe support supportpackages html or contact our sales team for more details 10 2 Handling the phyCORE Vybrid Removal of various components such as the microcontroller and the standard quartz is not advisable given the compact nature of the module Should this nonetheless be necessary please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds CAUTION If any modifications to the modu
78. s to the battery 15 2 OPEN The SOM s VBAT supply is disconnected JP4 CLOSED The LVDS transmitter is disabled 20 OPEN The LVDS transmitter is enabled JP5 1 2 The external crystal oscillator provides the audio codec master 22 clock J2 must be installed at 1 2 to enable the oscillator 2 3 The Vybrid MCU PTB11 signal provides the audio codec master clock JP7 CLOSED The termination is connected 18 OPEN The CANO termination is not connected JP6 1 2 The signals route through the transceivers the Carrier 18 JP9 Board JP14 2 3 The CAN signals bypass the transceivers on the Carrier JP15 Board JP16 CLOSED RTC_INTn connects to the Vybrid signal MCU_PTB23 5 OPEN RTC_INTn does not connect to Vybrid signals MCU_PTB23 is available on the Expansion Connector JP17 1 2 Connects isolated 5 V power to the CAN connectors 18 3 4 Connects isolated 5 V power to the CAN transceivers OPEN The CAN circuits are not connected to isolated 5 V power JP18 1 2 Connects system 5 V power to the CAN connectors 5 6 must 18 also be installed 3 4 Connects system 5 V power to the CAN trance i vers 5 6 must also be installed 5 6 Connects system GND to CAN_GND OPEN The CAN circuits are not connected to system 5 V power or GND JP19 CLOSED Tamper2 and Tamper3 signals are connected This allows 26 testing of normal physical security operating condition OPEN Tamper2 and Tamper3 signals are disconnected This allow test ing of a physical security fa
79. sion Connector the phyCORE Vybrid Carrier Board provides test pads and 4 on the TAMPER 1 0 signals and jumper JP19 across the TAMPER 3 2 signals JP19 allows testing of the Vybrid s Tamper2 Tamper3 active physical tamper security circuit Table 26 1 Tamper Signals at Connector X21 Pin Signal Type SL Connects to D10 EXT_TAMPERO IN 3 3 011 EXT TAMPER1 IN 3 3V Test point 4 D12 EXT TAMPER2 IO 3 3 V Jumper JP19 1 D13 EXT_TAMPER3 IO 3 3 V Jumper JP19 2 PHYTEC America LLC 2012 68 PCM 957 GPIO Expansion Board L 783e 0 Part PCM 957 GPIO Expansion Board Part 3 of this three part manual provides detailed information on the GPIO Expansion Board and how it enables easy access to most phyCORE Vybrid SOM signals The information in the following chapters is applicable to the 1351 0 PCB revision of the GPIO Expansion Board PHYTEC America LLC 2012 69 Part Chapter 27 Introduction L 714e 1 27 Introduction Fig 27 1 PCM 957 GPIO Expansion Board and Patch Field The GPIO Expansion Connectors at X21 on the Carrier Board provide access to many of the phyCORE Vybrid signals Although a large majority of the SOM signals are made available at X21 not all processor signals are routed to X21 In addition X21 may contain some signals which are not connected to the processor at all but instead to circuits only on the Carrier Board As an accessory a GPIO Expansion Boa
80. source of 3 3V 5 with at least 1 0 A capacity at the VDD_3V3 pins on the phyCORE Connector X1 A matching number of GND pins should also be used Connect power and ground to the following pins on connector X1 to power the SOM 3 3V X1 1C 2C 1D 2D GND X1 3C 3D 7C 7D Please refer to Table 2 3 for the location of additional GND pins located on the phyCORE Connector 1 4 2 DDR3 Power The 3 3V primary system power supplies a 1 5V regulator at U5 for the DDR3 memory at U6 4 3 Vybrid Processor Core Power The 1 1V and 1 2V power supplies needed by the Vybrid processor core are generated by regulators internal to the Vybrid processor from the main system 3 3V supply 4 4 Backup Power VBAT To backup the RTC on the module a secondary voltage source VBAT can be attached to the phyCORE Vybrid at pin X1 C4 This voltage source supplies the backup voltage domain VBAT to the external RTC 016 and to the VFx00 to supply its internal and some critical registers when the primary system power 3V3 is removed The voltage range for VBAT for the VFx00 RTC is 3 0 3 6V The range for the external RTC is 2 0V 5 0V Applications not requiring a backup mode should connect the VBAT pin to the primary system power supply VDD_3V3 PHYTEC America LLC 2012 20 Part Chapter 5 External RTC L 783e 0 5 External RTC An external RTC at 016 has been provided in addition to the VFx00 on chip RTC This additional RTC provi
81. ted connector The location of row 1 on the board is marked by a number 1 on the PCB to allow easy identification Figure 2 1 illustrates the numbered matrix system It shows a phyCORE Vybrid with SMT phyCORE Connectors on its underside defined as dotted lines mounted on a Carrier Board In order to facilitate understanding of the pin assignment scheme the diagram presents a cross view of the phyCORE module showing these phyCORE Connectors mounted on the underside of the module s PCB PHYTEC America LLC 2012 7 Chapter 2 Pin Description L 783e_0 Fig 2 1 Pin out of the phyCORE Connector Top View with Cross Section Insert The following tables provide an overview of the pinouts of the phyCORE Connector with signal names and descriptions specific to the phyCORE Vybrid It also provides the appropriate signal level interface voltages listed in the SL Signal Level column and the signal direction CAUTION Most of the controller pins have multiple functions Because most of these pins are connected directly to the phyCORE Connector the functions are also available there Signal names and descriptions below are in regard to the specification of the phyCORE Vybrid and the functions defined therein Please refer to the VFx00 datasheet or TRM for more information about alternative functions In order to utilize a spe cific pin s alternative function the corresponding registers must be configured within the appropri
82. the System on Module s design and functions Precise specifications for the Freescale VFx00 processor can be found in the processor datasheet and or user s manual In this hardware manual and in the schematics active low signals are denoted by preceding the signal name for example RD 0 represents a logic zero or low level signal while a 1 represents a logic one or high level signal Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE Vybrid PHYTEC System on Modules SOMs are designed for installation in electrical appliances combined with the PHYTEC Carrier Board can be used as dedicated Evaluation Boards for use as a test and prototype platform for hardware software development in laboratory environments CAUTION PHYTEC products lacking protective enclosures are subject to damage by ESD and hence may only be unpacked handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD dangers It is also necessary that only appropriately trained personnel such as electricians technicians and engineers handle and or operate these products Moreover PHYTEC products should not be operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Conformity only in accordance to the descriptions and rules of usage indicate
83. the VFx00 which is defined by resistors on the phyCORE Vybrid SOM please refer to Chapter 6 for more information Table 12 3 below shows the state of each boot mode signal when the corresponding switch position is turned ON Table 12 4 shows the required switch positions to configure the desired boot device Table 12 3 Switch Settings S5 55 Setting Description ON to pull BOOTMODO low ON to pull BOOTMOD 1 high ON to pull RCONS high ON to pull RCONG high ON to pull RCON7 high 8 Not used 8 OIN gt Table 12 4 Boot Configuration Settings 55 1 5 Boot Device on on on on off SD Card on on off off on NAND on on off off off QSPI off off off off off UART USBO 12 2 4 SPI Flash Button Button S7 is part of the K20 debug circuit It is for programming the SPI Flash devices on the SOM through the K20 processor It can be used as a system reset if jumper 15 1 2 For a detailed description of this button and associated uses please see Chapter 25 PHYTEC America LLC 2012 38 Il Chapter 12 Overview of Peripherals L 783e 0 12 3 LEDs JP23 e 57 021 020 E 012 0158 16 014 Fig 12 5 LEDs The phyCORE Vybrid Carrier Board is populated with numerous LEDs to indicate the status of various interfaces as well as the input power supply Figure 12 5 shows the location of the LEDs Their functions are listed in the table below T
84. tion 38 12 24 SPI Flash Button omen RE 38 rc TT 39 12 3 1 User Programmable 40 T3 JUMPERS aca cane ac a ih Roe dca pee CI 41 PHYTEC America LLC 2012 Table of Contents L 783e_0 14 phyCORE Vybrid SOM 44 15 POWOl cuca duis hae ux exer und dees ERA 45 15 1 Wall Adapter Input sess cde ERR ER MEREA C RE e ERA ead 46 15 2 VBAT 46 15 3 Current 46 16 Etherhet us on et 47 16 ROSIA Ue d 48 18 CAN Controller Area 50 18 1 CAN E DERE 51 19 USB Conriectlvity iu EG 52 19 1 VOC USB a Ree Gale A So eR E us 52 20 Display 22 eek du Edd EEG 53 20 1 Display Signals i e bee a eR Ee ei phd eee a 54 20 2 TFT Display sso ON IR U
85. ue 1 19 MCU PTE21 OUT VCC 3V3 Blue 0 20 MCU PTE20 OUT VCC 3V3 Green 7 21 MCU PTE19 OUT VCC 3V3 Green 6 22 MCU PTE18 OUT VCC 3V3 Green 5 23 MCU PTE17 OUT VCC 3V3 Green 4 24 MCU PTE16 OUT VCC 3V3 Green 3 25 MCU PTE15 OUT VCC 3V3 Green 2 26 MCU PTE14 OUT VCC 3V3 Green 1 27 PTE13 OUT VCC 3V3 Green 0 28 MCU PTE12 OUT VCC 3V3 Red 7 29 MCU PTE11 OUT VCC 3V3 Red 6 30 MCU PTE10 OUT VCC 3V3 Red 5 31 MCU PTE9 OUT VCC 3V3 Red 4 PHYTEC America LLC 2012 55 Part Il Chapter 20 Display L 783e 0 Table 20 2 TTL Display Connector X29 Continued Pin Signal Type SL Description 32 MCU PTE8 OUT VCC 3V3 Red 3 33 PTE7 OUT VCC 3V3 Red 2 34 OUT VCC 3V3 Red 1 35 MCU 5 OUT VCC 3V3 Red 0 36 GND Ground 37 MCU PTE2 OUT VCC 3V3 Clock 38 GND Ground 39 MCU PTB9 OUT VCC 3V3 Left right 40 MCU PTB12 OUT VCC 3V3 Up down 41 VCC 16V REF VCC 16V 16 V reference voltage 42 VCC 7V REF VCC 7V 7 V reference voltage 43 10 4 PWR VCC_10V4 10 4 V supply voltage 44 RESETn OUT VCC_3V3 System reset 45 no connect 46 VDD_3V7 REF VDD_3V7 3 7 V reference voltage 47 MCU PTB8 OUT VCC 3V3 Dither 48 GND GND Ground 49 50 no connect 20 3 PHYTEC Display Interface The PHYTEC Display Interface PDI is a standardized connection interface for connecting to various PHYTEC provided displays One connector provides data and control X30A
86. ue 2 058 24 OUT VDD_3V3 Display blue 3 D59 GND Ground 0 V 060 MCU PTE28 OUT VDD_3V3 Display blue 7 PHYTEC America LLC 2012 15 Chapter 3 Jumpers L 783e_0 3 Jumpers For configuration purposes the phyCORE Vybrid has three solder jumpers which have been installed prior to delivery Figure 3 1 illustrates the jumper pad numbering scheme for reference when altering jumper settings on the board Three and four position jumpers have pin 1 marked with a GREEN pad The beveled edge in the silk screen around the jumper indicates the location of pin 1 Figure 3 2 shows the location of the jumpers solder jumper WN OOO NA Fig 3 1 Jumper Numbering PHYTEC America LLC 2012 16 Part Chapter 3 Jumpers L 783e 0 3 1 Jumper Settings 7 8 zz ong EH arm J6 u mm E 888 __ A Bee Pee B wm
87. uickly jump to the applicable URL part chapter table or figure e References made to the phyCORE Connector always refer to the high density Samtec connectors on the underside of the phyCORE Vybrid System on Module Abbreviations and Acronyms Many acronyms and abbreviations are used throughout this manual Use the table below to navigate unfamiliar terms used in this document Table 1 1 Abbreviations and Acronyms Used in This Manual Abbreviation Definition BSP Board Support Package Software delivered with the Development Kit including an operating system Windows or Linux preinstalled on the module and Development Tools CB Carrier Board used in reference to the PCM 952 phyCORE Vybrid Carrier Board DFF D flip flop EMB External memory bus EMI Electromagnetic Interference GPI General purpose input GPIO General purpose input and output GPO General purpose output IRAM Internal RAM the internal static RAM on the Freescale processor J Solder jumper these types of jumpers require solder equipment to remove and place JP Solderless jumper these types of jumpers can be removed and placed by hand with no special tools PCB Printed circuit board PDI PHYTEC Display Interface defined to connect PHYTEC display adapter boards or custom adapters PEB PHYTEC Extension Board PMIC Power Management Integrated Circuit PoE Power over Ethernet PoP Package on Package
88. ult condition such as of a panel being opened JP20 CLOSED User Button 1 is connected to the signal MCU_PTB8 12 2 OPEN User Button 1 is not connected to the signal MCU_PTB8 JP21 CLOSED User Button 2 is connected to the signal MCU_PTB9 12 2 OPEN User Button 2 is not connected to the signal MCU_PTB9 PHYTEC America LLC 2012 42 Il Chapter 13 Jumpers Table 13 1 Jumper Settings and Descriptions Continued L 783e_0 Jumper Setting Description Chapter JP22 CLOSED Normal system use 15 OPEN Calculate the current to the SOM by measuring the voltage across the JP22 pins The resistance across this path is set by resistor R153 default value 0 070 Ohms 1 Current volt age resistance JP23 CLOSED The DACO1 signals can control User LED 3 12 3 amp 11 OPEN The DACO1 signal does not connect to User LED DACO1 is available at the Expansion Connector X21 for custom uses JP24 CLOSED The CAN isolated power converter is enabled 18 OPEN The CAN isolated power converter is dis abed JP26 CLOSED The K20 s UART is connected to the Vybrid s UART1 24 JP27 OPEN K20 s UART is not connected to the Vybrid JP28 1 2 The K20 SPI interface connects to the SOM s SPI A Flash U7 24 2 3 The K20 SPI interface connects to the SOM s SPI B Flash U8 OPEN The K20 SPI interface does not connect to the SOM s SPI Flash devices JP30 CLOSED 128 is disabled the TTL display connector does n
89. ummary of the jumper settings for each operating mode is presented in Table 18 1 Table 18 1 CANO Jumper Settings Jumper SOM Mode CB Non Isolated Mode CB Isolated Mode JP6 2 3 1 2 1 2 JP9 2 3 1 2 1 2 JP14 2 3 1 2 1 2 JP15 2 3 1 2 1 2 JP17 OPEN OPEN 3 4 JP18 5 6 3 4 5 6 OPEN JP24 OPEN OPEN CLOSED On the Carrier Board the CAN1 signals from the phyCORE route directly to the Expansion Connector X21 See Table 30 1 Processor Signal in Chapter 30 for the signal locations JP7 When closed connects a 120 Ohm termination across the CANO H L signal pair This termi nation should be connected when the CANO signals connect at the physical end of a line with a cable that does not provide integrated termination 18 1 VCC CAN In general the configuration of VCC CAN jumpers should be adjusted according to the operating modes listed in Table 18 1 However a more detailed description of the CAN configuration is also presented here for reference In the default configuration the CAN signals route through a transceiver on the SOM Alternately these signals route instead through a transceiver on the Carrier Board The Carrier Board transceiver can operate on either system power or DC isolated power The jumper settings for each of these configurations are shown in the table below D17 indicates if 5V system power is provided to the CAN connector which can be connected with JP18 1 2 Table 18 2
90. uration Settings 38 Table 12 5 LED Descriptions 39 Table 13 1 Jumper Settings and Descriptions 42 Table 15 1 Voltage Domains 45 Table 15 2 Power LEDS copa hadi Siete rhe LARES 45 Table 17 1 X10 Pin Descriptions 49 Table 17 2 X31 Pin Descriptions 49 Table 18 1 CANO Jumper Settings 51 Table 18 2 CAN Supply Configuration 51 Table 20 1 TTL Display Pin Header X24 54 Table 20 2 TTL Display Connector X29 55 Table 20 3 PDI Connector X30A Signal Descriptions 56 Table 20 4 PDI Connector X30B Signal Descriptions 57 Table 22 1 Audio Connectors 61 Table 23 1 JTAG Connector X16 Signals 62 Table 23 2 JTAG Connector X19 Signals 63 Table 24 1 Trace Connector X22 Pins 64 Table 25 1 K20 Jumper Configurations

phyCORE-Vybrid Hardware Manual

Contents

Download Pdf Manuals

Related Search

Related Contents