User Manual - ESA Microelectronics Section
Contents
1. This test checks the TX AHB master and slave interfaces and the RX AHB master interface Checking the TX AHB master slave of one spacewire is done by verifying that the data received by the other spacewire block is correct The RX AHB master is checked for normal operations and for operations performed when the host memory area limit is reached VHDL blocks have been developed to emulate the behaviour of the spacewire block environment The VHDL emulators used for the test are e emu spwr generates error characters for Spacewire 2 to simulate transmission errors e emu apbmst is used for the spacewire block configuration through APB bus e emu set sig sets signals e emu test sig checks signals e arbiter manages the AHB master slave traffic e emu ahbslv sm interfaces between AHB slave and SoftMem R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 15 e SoftMem is an advanced memory block e emu mem spy checks the memory data e emu ahbslv is an AHB slave used to give RETRY SPLIT or ERROR response to the spacewire e emu ahbmst is an AHB master used to communicate with the spacewire AHB slave interface 4 3 1 Test sequences run during the test of the host interface 4 3 1 1 introduction Only one simulation is run that contains 39 test sequences The testbench checks the correctness of the results by reading in the memory or by checking signal activation The following paragraphs give a brief description of each test2. 4 3 4 2 TX AHB master interface test 1 nominal operation Data packets are transmitted using TX AHB master and the received data are checked in the SoftMem e Spacewire 1 amp 2 programmation tx mode master linkstart 1 e Spacewire 1 amp 2 descriptor initialization e Spacewire 1 amp 2 memory area 1 initialization e Spacewire 1 amp 2 memory area 1 validation e Received data are stored in the Softmem e Comparison between reference data and received data 4 3 1 3 RX AHB master interface test 1 area middle address area end address e Spacewire 1 amp 2 programmation tx mode 1 test mode tx 1linkstart 1 e Spacewire 1 amp 2 descriptor initialization e Spacewire 1 amp 2 memory area 1 initialization e Spacewire 1 amp 2 memory area 1 validation e Spacewire 1 amp 2 interrupts clearing e Spacewire 2 verify that no null is written at area 1 end e Spacewire 1 amp 2 check the exceed mem IT and no area valid IT generation 4 3 1 4 RX AHB master interface test 2 RX FIFO is full and RX FIFO dumping e Spacewire 1 amp 2 memory area 1 initialization e Spacewire 1 amp 2 memory area 1 validation 4 3 1 5 RX AHB master interface test 3 area middle address area end address e Spacewire 1 amp 2 programmation tx mode 1 test mode tx 1linkstartz1 e Spacewire 1 amp 2 descriptor initialization e Spacewire 1 amp 2 memory area 1 initialization e Spacewire 1 amp 2 memory area 1 validation e Spacewire 1 amp 2 interrupt
3. D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 18 4 3 1 17 TX AHB master interface test 6 Check the reception of RETRY SPLIT or ERROR response when the FSM reads the data value e Spacewire 1 descriptor initialization IT reset e Emu ahbslv generates RETRY SPLIT then ERROR response when the TX AHB master FSM reads the data value e Spacewire 1 verify the amba error IT activation 4 3 1 18 TX AHB master interface test 7 Check the reception of RETRY SPLIT or ERROR response when the FSM reads the next packet address e Spacewire 1 descriptor initialization IT reset e Emu ahbslv generates RETRY SPLIT then ERROR response when the TX AHB master FSM reads the next packet address e Spacewire 1 verify the amba error IT activation 4 3 1 19 Test of LINK NOT ENABLED IT e Spacewire 1 autostart 0 link start O link_disabled 0 e Spacewire 1 check the link not enabled IT activation e Spacewire 1 IT reset e Spacewire 1 autostart 1 link start 1 link disabled 1 e Spacewire 1 check the link not enabled IT activation 4 3 1 20 TX AHB slave interface test 2 nominal operation e Spacewire 1 IT reset packet abortion e Spacewire 1 Reception of data packet through the AHB slave interface single amp burst transfers The data is transmitted to the spacewire 2 then stored in the softmem A data check is performed in the softmem by the emu mem spy 4 3 1 21 RX AHB master interface test 7 Check the reception of RETRY SPLIT or E
4. INTERFACE The spacewire VHDL core without its host interface is connected to the Austrian Aerospace spacewire emulator as depicted in Figure 3 3 3 1 The verification is done by reading the FIFOs data and comparing them to expected results spwr ctrl spwr ctrl user d out i F l m Astrium Spacewire Emulator 9 9 SpaceWire Block sin s_out Under Verification spwr_check din d out Spwr check user Figure 3 3 3 1 Austrian Aerospace test bench The Austrian Aerospace test bench checks the protocol initialization the TX interface the RX interface and the Time Code FCT and data management The test cases performed are e Link Startup e Normal operation e Error cases e Stress Cases TX and RX rates are different For more information read protocol verification pdf and testbench user manual pdf included in the your path docref directory 4 3 TEST OF THE HOST INTERFACE R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 14 Two spacewire blocks are connected together in Astrium testbench as depicted in Figure 3 3 3 1 emu mem Spy AHB BUS SoftMem emu apb mst APB BUS emu controleur A de eee eui QI CU GN ye Li err int nom int i i tickout_ctm i emu test sig character 7 Spacewire1 generator E emu_set_sig gen_char clk clk_tx rstn test mode h ard tickin ctm emu spwr Spacewire2 Figure 3 3 3 1 Test bench for host interface test
5. Some parameters can be personalized in the VHDL code in order to dimension the FIFO size to change counter widths and to choose the TX clock type gated or not 3 3 4 FIFO configuration For each FIFO RX TX or AHB the user can specify e The address width of the FIFO corresponding to the FIFO depth xxFIFOABITS The recommended values are the following o for RX RXFIFOABITS must be greater than or equal to 6 o forTX TXFIFOABITS must be greater than or equal to 3 o for AHB AHBFIFOABITS must be greater than or equal to 2 This FIFO is a 32 bit word size FIFO its size depends on the AHB latency xxFIFODBITS is the width of the data Its is set at 9 and shall not be changed xxFIFODEPTH is the number of words of the FIFO It is worked out from xxFIFOABITS and shall not be modified These parameters are included in the sw pack vhd file The configuration of the RX FIFO TX FIFO and AHB FIFO is described hereafter constant RXFIFOABITS integer 6 constant RXFIFODBITS integer 9 shall not be modified constant RXFIFODEPTH integer 2 RXFIFOABITS shall not be modified constant TXFIFOABITS integer 3 constant TXFIFODBITS integer 9 shall not be modified constant TXFIFODEPTH integer 2 TXFIFOABITS shall not be modified constant AHBFIFOABITS integer 2 constant AHBFIFODBITS integer 32 shall not be modified constant AHBFIFODEPTH integer 2 AHBFIFOABITS shall not b
6. data packet into Spacewire 1 e The data packet is transmitted from the Spacewire 1 to the Spacewire 2 e Spacewire 2 storage of the received data by writing into the emu ahbslv e The current area is full and there is one data left e Spacewire 2 storage of the left data into a new area e Check the amba error IT and the memory 4 3 1 27 RX AHB master interface test 13 Start a new area to store 2 data left from the current packet e Spacewire 2 in TX AHB slave mode initialization of the areas e Emu ahbmst write a data packet into Spacewire 1 e The data packet is transmitted from the Spacewire 1 to the Spacewire 2 e Spacewire 2 storage of the received data by writing into the emu ahbslv e The current area is full and there are 2 data left e Spacewire 2 storage of the left data into a new area e Check the amba error IT and the memory 4 3 1 28 RX AHB master interface test 14 Start a new area to store 4 data left from the current packet e Spacewire 2 in TX AHB slave mode initialization of the areas e Emu ahbmst write a data packet into Spacewire 1 e The data packet is transmitted from the Spacewire 1 to the Spacewire 2 e Spacewire 2 storage of the received data by writing into the emu ahbslv e The current area is full and there are 4 data left e Spacewire 2 storage of the left data into a new area e Check the amba error IT and the memory 4 3 1 29 RX AHB master interface test 15 Start a new area to store a new packet e Spacewire 2 i
7. made with the Synplify software These files are spacewire prj project file and spacewire sdc constraints file All the result files are in the REV X sub directory such as the spacewire edf edif file and the spacewire srr report file The ROUTAGE directory contains the result files of the Xilinx software that performs the place and route task authorization Ref R amp D SOC NT 295 V ASTR Issue 0 Rev 1 Date 25 04 2002 Page 9 3 2 THE VHDL SOURCE DESCRIPTION All the VHDL source files and the level hierarchy are shown hereafter TOP LEVEL LEVEL 2 LEVEL 3 tx mgt vhd rx mgt vhd sw counters vhd sw vhd sw_resync vhd sw_reg vhd delay_cnt vhd init_fsm vhd ahb_mst_slv_tx vhd sw_fifo vhd AHB FIFO host_int vhd ahb tx int vhd ahb mst rx vhd rx resync vhd rx decod vhd spacewire vhd rx vhd rx_shiftreg vhd disconnection vhd tx_resync vhd tx_select vhd tx vhd txcnt vhd txshiftreg vhd ds gen vhd tx ack vhd clk tx gen vhd sw fifo vhd TX FIFO sw fifo vhd RX FIFO Figure 3 3 1 1 Source files hierarchy The top file spacewire noamba vhd does not include the host interface The architecture spacewire noamba is used to the Austrian Aerospace testbench In SCOC project the top file spacewire vhd is used In this case the sw noamba vhd file is replaced by the sw vhd file R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 10 3 8 CONFIGURATION OF THE SPACEWIRE BLOCK
8. 1 Tickin ctm activation Spacewire 2 Check the tickout bit activation in the IT register Check the tickout ctm output activation Spacewire 2 force all internal IT to 0 Spacewire 2 Check the received time code value Spacewire 1 Activate the tickin bit of the management register Spacewire 2 Check the tickout bit activation in the IT register Check the tickout ctm output activation Spacewire 2 Check the received time code value 4 3 1 14 TX AHB slave interface test 1 ERROR response Verify the generation of error response to unfit request Spacewire 2 tx mode master Spacewire 2 TX AHB slave write access requested Spacewire 2 check the wrong mode IT activation Spacewire 2 TX AHB slave read access requested Spacewire 2 check the rd access error IT activation 4 3 1 15 TX AHB master interface test 4 Check the reception of RETRY SPLIT or ERROR response when the FSM reads the packet size Spacewire 1 descriptor initialization Emu_ahbslv generates RETRY SPLIT then ERROR response when the TX AHB master FSM reads the packet size Spacewire 1 verify the amba_error IT activation 4 3 1 16 TX AHB master interface test 5 Check the reception of RETRY SPLIT or ERROR response when the FSM reads the data address Spacewire 1 descriptor initialization IT reset Emu_ahbslv generates RETRY SPLIT then ERROR response when the TX AHB master FSM reads the data address Spacewire 1 verify the amba_error IT activation R amp
9. 5 V ASTR 0 Rev 1 25 04 2002 27 TS clk tx PERIOD TIMEGRP clk tx 10 n S HIGH 50 000000 TS_clk_txin PERIOD TIMEGRP clk_txin 10 000ns 9 172ns 5 10 nS HIGH 50 000000 TS c rx clk rx PERIOD TIMEGRP c_rx clk 20 000ns 10 122ns 6 _rx 20 nS HIGH 50 000000 TS clk sw PERIOD TIMEGRP clk sw 50 n 50 000ns 19 761ns 7 S HIGH 50 000000 All constraints were met Dumping design to file spacewire ncd All signals are completely routed Total REAL time to PAR completion 4 mins 2 secs Total CPU time to PAR completion 4 mins 1 secs Placement Completed No errors found Routing Completed No errors found Timing Completed No errors found Timing summary Timing errors 0 Score 0 Constraints cover 35204 paths 0 nets and 6738 connections 75 5 coverage Design statistics Minimum period 19 761ns Maximum frequency 50 605MHz 6 4 LAYOUT CONCLUSION The place and route is successful The timings are met 6 5 CAO TOOLS CONFIGURATION The configuration of the tools used by Astrium to develop the spacewire core is the following e VHDL simulator Mentor Modelsim version 5 5a e Synthesis tool Synplify version 6 0 e place and route tool Xilinx Design Manager 4 1i R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 28
10. RROR response when the FSM is in WR DATA state e Spacewire 2 in TX AHB slave mode initialization of the areas e Emu ahbmst write a data packet into Spacewire 1 e The data packet is transmitted from the Spacewire 1 to the Spacewire 2 e Spacewire 2 storage of the received data by writing into the emu ahbslv e Emu ahbsiv responses with RETRY SPLIT or ERROR when the RX AHB master FSM is in the WR DATA state e Check the amba error IT and the memory 4 3 1 22 RX AHB master interface test 8 R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 19 Check the reception of RETRY SPLIT or ERROR response when the FSM is in WR HEADER state Spacewire 2 in TX AHB slave mode initialization of the areas Emu ahbmst write data packets into Spacewire 1 Data packets are transmitted from the Spacewire 1 to the Spacewire 2 Spacewire 2 storage of the received data by writing into the emu ahbslv Emu ahbslv responses with RETRY SPLIT or ERROR when the RX AHB master FSM is in the WR HEADER state Check the amba error IT and the memory 4 3 1 23 RX AHB master interface test 9 Check the reception of RETRY SPLIT or ERROR response when the FSM is in WR NULL state Spacewire 2 in TX AHB slave mode initialization of the areas Emu ahbmst write data packets into Spacewire 1 Data packets are transmitted from the Spacewire 1 to the Spacewire 2 Spacewire 2 storage of the received data by writing into the emu ahbslv Emu ahbslv responses wit
11. Ref R amp D SOC NT 295 V ASTR Issue 0 Rev 1 Date 25 04 2002 Page i ESA 13345 3 Building Block for System On a chip SPACEWIRE IP CORE HARDWARE USER MANUAL i Name and Function Tam Le Ngoc Prepared by Marc Lefebvre Verified by Approved by Marc Souyri Authorised by MA mm CharNb 27880 WordsNb 5538 Astrium FileName SW USERMAN 01 DOC R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 di DOCUMENT CHANGE LOG LX Modification Nb Modified pages evision Creation 25 04 02 Included comments from ESA 04 03 03 Adding TX clock configuration PAGE ISSUE RECORD Issue of this document comprises the following pages at the issue shown CharNb 27880 WordsNb 5538 Astrium FileName SW USERMAN 01 DOC Ref R amp D SOC NT 295 V ASTR Issue 0 Rev 1 Date 25 04 2002 Page 3 ZR gc IE E EE 5 PEN DOCUIMENCS AN acronym E S S 0S S Sn G S 6 24 Applicable documents s sose 6 2 2 Reference documents 6 2 3 ACLONYIMS q 7 Bo Dunedin 8 3 1 Lenin c tooa ess e Sio 8 3 2 The VHDL source description ss ssssssssesrssissssesssocesossissssrsssosessosiu soosis setas esos s esses eese tastes sesso 9 3 3 Configuration of the spacewire block eere eee eee eee eese en notes tasa sen
12. Spacecraft Controller on a Chip SpaceWire Block Reference Document RX Host Interface System On a Chip TX Host Interface R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 7 Ref R amp D SOC NT 295 V ASTR Issue 0 Rev 1 Date 25 04 2002 Page 8 3 DESIGN DESCRIPTION 3 1 ACCOUNT STRUCTURE The path of the working account used for the design is called your path in the present document The organization is shown hereafter home scoc archi spacewire cur codrf docref routage simenv1 simenv2 source spwref synth b tbref Work work2 Figure 3 3 1 1 Account structure The SOURCE directory contains all the VHDL files of the Spacewire VHDL core SWB The CODRF DOCREF SPWREF TBREF directories contain documentations testbench and emulators provided by Austrian Aerospace to test the spacewire protocol on the link side The Modelsim compilation of the Austrian Aerospace test bench is stored in the WORK2 directory The SIMENV2 directory is used to simulate the Austrian Aerospace bench The TB directory contains the second test bench mainly used to test the host interface of the spacewire core The result of the Modelsim compilation of the second testbench is stored in the WORK directory The SIMENV1 directory is dedicated to launch the second testbench simulation The sw tb file contains all the tests performed on the spacewire The SYNTH directory contains specific files for the synthesis
13. acewire 1 transmission of data to the Spacewire 2 e Spacewire 2 link disabled while it receives data e Spacewire 2 an EEP is added into the RX FIFO 4 3 1 40 Test of the initialization protocol to increase the test coverage e Go from ERRORWAIT state to ERRORRESET state e Go from READY state to ERRORRESET state e Go from STARTED state to ERRORRESET state e Go from CONNECTING state to ERRORRESET state e Go from RUN state to ERRORRESET state e Generation of ESC error character sequence error outstanding error credit error disconnection error 4 4 SIMULATION DESCRIPTION To compile the VHDL code for simulation go into the your path simenv1 directory then type compile Do the same in the your path simenv2 directory 4 4 4 Simulation without the host interface The Austrian Aerospace testbench is in the your path tbref directory The script files are in the your_path codrf directory The spacewire emulator is in the your path spwref directory To execute these simulations go to the your path simenv2 directory compile the test bench by typing compile then type RUN to launch the simulation Then check the transcript window of Modelsim 4 4 2 Simulation with the host interface The test bench tb5 vhd is in the your_path tb directory The sofmem block uses a file named ram dat that contains the elements of a linked list The data in this file are randomly generated by using the script generate csh The script files sw tb a
14. atu seen senatu ano 10 3 3 1 PIFO confor ora eee eei ette thi ni ah i D en eL EP Peer e i eee PR EP eR 10 3 3 2 COUNtet COMMUTATION P 10 3 3 3 TX clock confiputatiOns encre o rrr er e D NR SR eva Ten e TR RET 11 3 4 Porting of the spacewire core to different technology eere eee eee eee ee eese en seen neto seta 11 Wap Ppg pg M 13 4 1 jnnnn 13 4 2 Test of the spacewire without the host interface ccsscsscssscssscssscsssssssscssscssssssssssescoees 13 4 3 Test of the host interface ES 13 4 3 1 Test sequences run during the test of the host interface 15 4 4 Simulation einn m 22 4 4 1 Simulation without the host interface oerion eiks E enne nennen nennen enn 22 4 4 2 Sim lation with the host Intetface i ces ut te ee LE RR Yr UR UE EE LUE E LESE 22 4 5 utniieniiiodq 23 mo Xu Sputheslen ceca tene ote eu pm Hate uds t IT E 23 5 1 Set up and device 23 5 2 Compilation and mapping options cccccsscssscsssccssscssscssscnssssssssessssssssssessscssssssesssssoees 23 5 3 jUOnn A 23 5 4 ccs 23 5 5 QA IDSCES IIo m 25 6 Xilinx plac and rote iie rere tte tide o gris ue EUR rebar E o DIOE eei sete s dE eR Saisi 25 6 1
15. d AHB Each FIFO is made by a dual port RAM By now the VHDL code is targeted for Xilinx and Synplify Thus the synthesis tool is able to recognize that the VHDL code corresponds to Xilinx RAMB block This part would have to be changed for another technology otherwise fil flops will be inferred e he TX clock generator that is not included in the spacewire block The user has to generate this high frequency clock the Spacewire Block contains only the divider that generates the TX clock In addition there are 4 clocks used in the Spacewire Block that the user must balance according to the capability of the target technology e The System clock clk sw that controls about 700 flip flops R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 12 e The Input TX clock clk_txin that controls about 20 flip flops e The TX clock obtained after divide of clk_txin clock that controls about 150 flip flops e The RX clock clk_rx that controls about 150 flip flops R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 13 4 SIMULATION PLAN 4 1 INTRODUCTION Two testbenches are used e A testbench based on the Austrian Aerospace testbench This testbench is used to test the Spacewire VHDL core on the link side Some sequences were added to the Austrian Aerospace testbench provided by ESA to test the time code e Atestbench developed by Astrium that allows testing the host interface 4 2 TEST OF THE SPACEWIRE WITHOUT THE HOST
16. e VHDL core It is intended for users that would like to use the VHDL block It explains the following elements e Structure of the UNIX directories containing the core and the testbench e adaptation of the core to other technologies e Structure of the two testbenches used to verify the core e test plan of the testbenches e run of the simulation e synthesis of the core R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 6 2 DOCUMENTS AND ACRONYMS 2 1 APPLICABLE DOCUMENTS AD8 SCOC Requirement Specification R amp D RP SOC 214 MMV Issue 2 June 2000 AD9 AMBA Specification Rev 2 0 ARM IHI 0011A AD10 Spacecraft Controller On a Chip Architectural Design Document AD11 ECSS E 50 12 Draft 1 ESA SpaceWire March 2001 Specification 2 2 REFERENCE DOCUMENTS RD21 System On a Chip Feasibility Study December 99 Issue 2 R amp D RP SOC 154 MMV RD26 Austrian Aerospace Spacewire Test bench User November 2000 Manual RD27 Austrian Aerospace Spacewire X Protocol November 2000 Verification 2 3 ACRONYMS AD APB AHB DMA ESA ESTEC FPGA FSM HKPF HKAPB Applicable Document Advanced Peripheral Bus Advanced High Performance Bus Direct Memory Access European Space Agency European Space Research and Technology Centre Field Programmable Gate Array Finite State Machine Housekeeping Function Housekeeping Advanced Peripheral Bus Intellectual Property Interrupt Low Voltage Differential Signals
17. e modified 3 3 2 Counter configuration R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 11 The size of the counter used for the 6 4 us delay generation is defined by the DELAYWIDTH constant The maximum value for DELAYWIDTH is 16 since only 16 bits are reserved in the Time_Out Register to store the maximum value of the counter The size of the counter used to store the number of RX FIFO empty space is defined by the CWIDTH constant The CMAX constant has the value of RXFIFODEPTH but in std logic vector format These constants are included in the sw pack vhd constant DELAYWIDTH integer 8 constant CWIDTH integer 7 constant CMAX std logic vector CWIDTH 1 downto 0 conv std logic vector 2 RXFIFOABITS CWIDTH shall not be modified 3 3 8 TX clock configuration The TX frequency can be generated by either a gated clock with a 2 n 1 frequency divider or a not gated clock using an enable clock signal In the last case a n 1 frequency divider is used Configuration To use a gated TX clock you must have constant GATED TX CLK Boolean true To use a not gated TX clock you must have constant GATED TX CLK Boolean false 3 4 PORTING OF THE SPACEWIRE CORE TO DIFFERENT TECHNOLOGY All the Spacewire code is written in synthesizable VHDL Most of the code is independent from the target technology The specific parts concern only e The three FIFOs RX TX an
18. h RETRY SPLIT or ERROR when the RX AHB master FSM is in the WR NULL state Check the amba error IT and the memory 4 3 1 24 RX AHB master interface test 10 Verify the recovery of the data once an error response appears quantity of data to be recovered 2 Spacewire 2 in TX AHB slave mode initialization of the areas Emu ahbmst write a data packet into Spacewire 1 The data packet is transmitted from the Spacewire 1 to the Spacewire 2 Spacewire 2 storage of the received data by writing into the emu ahbslv Emu ahbslv responses with RETRY SPLIT or ERROR when the RX AHB master FSM is in the WR DATA state Check the amba error IT and the memory 4 3 1 25 RX AHB master interface test 11 Check the recovery of the data once an error response appears quantity of data to be recovered 1 Spacewire 2 in TX AHB slave mode initialization of the areas Emu_ahbmst write a data packet into Spacewire 1 The data packet is transmitted from the Spacewire 1 to the Spacewire 2 Spacewire 2 storage of the received data by writing into the emu_ahbslv Emu_ahbslv responses with RETRY SPLIT or ERROR when the RX AHB master FSM is in the WR_DATA state Check the amba_error IT and the memory 4 3 1 26 RX AHB master interface test 12 R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 20 Start a new area to store one data left from the current packet e Spacewire 2 in TX AHB slave mode initialization of the areas e Emu ahbmst write a
19. is performed in the your_path routage directory The input netlist file is spacewire edf R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 26 Note The AMBA interface is connected to the ports So the timings on the AMBA bus are not taken into account 6 2 CONSTRAINTS Input TX clock clk txin 100 MHz System clock clk sw 20 MHz TX clock obtained after divide of clk txin clk tx 100 MHz RX clock clk rx 50 MHz NET clk tx TNM NET clk tx TIMESPEC TS cIk tx PERIOD clk tx 10 ns HIGH 50 96 NET clk txin TNM NET clk txin TIMESPEC TS cIk txin PERIOD clk txin 10 ns HIGH 50 96 NET c rx clk rx TNM NET c rx clk rx TIMESPEC TS c rx clk rx PERIOD c rx clk rx 20 ns HIGH 50 96 NET clk sw TNM NET clk sw TIMESPEC TS clk sw PERIOD clk sw 50 ns HIGH 50 96 The two clocks clk tx and clk rx must be routed by using backbones of the Virtex structures The following constraints must be added NET clk tx USELOWSKEWLINES NET c_rx clk_rx USELOWSKEWLINES 6 3 RESULT 6 3 1 Device utilization summary Number of External GCLKIOBs 2outof4 50 Number of External IOBs 371 out of 404 91 Number of LOCed External OBs 0O outof 371 0 Number of SLICEs 1332 out of 19200 6 Number of GCLKs 2outof4 50 Number of TBUFs 36 out of 19520 1 6 3 2 Constraint report Constraint Requested Actual Logic R amp D SOC NT 29
20. ju Un 25 6 2 jUOnnn 26 6 3 Result de sisseeeses eee Pao E E VRUIS Re PERURVAE RS Ro PERS ERUPEUERERS FOEe PERUBVSSRERP RO RSPERORERER ERE D ERE PER ONe Ned 26 Ref R amp D SOC NT 295 V ASTR Issue 0 Rev 1 Date 25 04 2002 Page 4 6 3 1 D vice utilization summaty etes ene repe eet pereo ae ee ER eee osuere eaa pado 26 6 3 2 Constraint LEP OTT e dien esti eie eate de inen hr ee tee pe deos 26 jn 27 6 5 CAO Tools Configuration P 27 Figure 3 3 d 1 Account Structute scc rit aoa Ier duh nen uid ivi e aenea ie 8 Fipute 3 3 1 1 Source files Hierarchy i eom eret ies te eee a eere diu E EAE 9 Figure 3 5 1 1 Austrian Aerospace test bench te ete nerd ai derer een in ens 13 Figure 3 5 2 1 s Test bench for host interlace fest x eesescote petebat dese Sido ic Qus So ee additae CET ga ee euge 14 Ref R amp D SOC NT 295 V ASTR Issue 0 Rev 1 Date 25 04 2002 Page 5 1 SCOPE The present document is written in the frame of the ESA 13345 3 contract Building block for System on a Chip It is part of Phase 3 of the contract related to the design of a System On a Chip for Space application The present activity concerns the design of a Spacewire VHDL core to be integrated in the System On a CHip This document is the Hardware User Manual of th
21. n TX AHB slave mode initialization of the areas e Emu ahbmst write a data packet into Spacewire 1 e The data packet is transmitted from the Spacewire 1 to the Spacewire 2 e Spacewire 2 storage of the received data by writing into the emu ahbslv e The current area is full and there is no data left e Spacewire 2 storage of the left data into a new area e Check the amba error IT and the memory 4 3 1 30 RX AHB master interface test 16 Packet contains less than 4 data e Spacewire 2 reception of a packet containing 3 data e Spacewire 2 storage the area becomes full R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 21 e Spacewire 2 loads a new area then stores next packet e Check the memory 4 3 1 31 RX AHB master interface test 17 Packet contains less than 4 data e Spacewire 2 reception of a packet containing 3 data e Spacewire 2 storage the area becomes full e Spacewire 2 loads a new area then stores a new packet containing less than 4 data e Check the memory 4 3 1 32 RX AHB master interface test 18 Area2 valid flag clearing e Spacewire 2 area2 initialization e Spacewire 2 storage the area 2 becomes full e Check the flag 4 3 1 33 RX AHB master interface test 19 Check the last part of the packet e Spacewire 2 area2 initialization e Spacewire 2 storage the area 2 becomes full but the packet is not entirely stored e Spacewire 2 storage of the last part of the packet into the new area e Check the memory fo
22. nd constante tb contain commands for the emulators The user must type tbpp sw tb PROJ archi spec emu to update testbench each time the sw tb or constante tb file is modified R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 28 To execute the simulation go to the your path simenv1 directory compile the test bench if necessary by typing compile then type run simu5 to launch the simulation The transcript file shall not contain any error message 4 5 SIMULATION REPORT The VHDL simulation has been performed All the functions have been checked No functional error has been detected 5 XILINX SYNTHESIS Synthesis scripts are in your path synth 5 1 SET UP AND DEVICE Synplify is used for the synthesis The Xilinx component must be specified the following component was chosen for our breadboard e Technology VIRTEX E e Part XCV2000E e Package BG560 e speed_grade 6 5 2 COMPILATION AND MAPPING OPTIONS The following options are set in Synplify e default enum encoding default e symbolic fsm compiler true e resource sharing true e top module spacewire e fanout limit 100 5 3 CONSTRAINTS The constraints are e clk_txin 110 MHz e cClk tx internal 110 MHz e Clk sw system clock 25 MHz e cClk rx internal 255MHz 5 4 RESULTS Performance Summary R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 24 KKKKKKKKKKKKKKKKKKKKK Req
23. r the last packet part 4 3 1 34 TX AHB master interface test 8 the FSM reads a packet size 0 e Spacewire 1 TX AHB master mode descriptor programmation e Spacewire 1 the FSM reads a packet size 0 e Spacewire 1 the FSM reads the next packet address e Spacewire 1 the FSM reads the next packet then transmits it e Check in the memory for the next packet 4 3 1 35 Test 1 of the interface between the AHB FIFO and the TX FIFO Test the abort packet signal in WR SIZE state e Spacewire 1 TX AHB slave mode e Spacewire 2 initialization of the memory area e Emu ahbmst writes the packet size e The Abort packet flag is asserted while the FSM of the ahb tx int block is in the WR SIZE state 4 3 1 36 Test 2 of the interface between the AHB FIFO and the TX FIFO Test the abort packet signal in WR DAT state The same scenario as in 4 3 1 35 but the abort packet flag is asserted in the WR DAT state 4 3 1 37 Test of the TX FIFO flush when the link is disabled e Fill the TX FIFO with data e Disables the link while the TX FIFO is not empty R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 22 e Observe the TX FIFO flush 4 3 1 38 Test 1 to increase the test coverage test of the sw_reg block e RD WR accesses to the TIMEOUT register RD access to the CUR_BUF_END register WR access to the TIMECODE register e RD WR accesses to invalid register address 4 3 1 39 Test 2 to increase the test coverage adds an EEP to the RX FIFO e Sp
24. s clearing R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 16 e Spacewire 1 amp 2 verify that a null is written at area 1 end e Spacewire 1 amp 2 check the no area valid IT generation 4 3 1 6 RX AHB master interface test 4 RX FIFO dumping e Spacewire 1 amp 2 memory area 1 initialization e Spacewire 1 amp 2 memory area 1 validation 4 3 1 7 RX AHB master interface test 5 memory area swap e Spacewire 1 amp 2 programmation tx mode 1 test mode tx 1linkstart 1 e Spacewire 1 amp 2 descriptor initialization e Spacewire 1 amp 2 memory area 1 initialization e Spacewire 1 amp 2 memory area 2 initialization e Spacewire 1 amp 2 memory area 1 amp 2 validation e Spacewire 1 amp 2 verify the memory area swap by reading the area1 used and area2 used flag e Spacewire 1 amp 2 verify that the status 10 is in the header of the last packet written in the area 1 because this packet is not entirely stored in the area1 e Spacewire 1 amp 2 verify that the last part of this packet is stored in the area 2 e Spacewire 1 amp 2 memory area 1 reinitialization e Spacewire 1 amp 2 memory area 1 validation e Spacewire 1 amp 2 check the change from the area 2 to area 1 4 3 1 8 RX AHB master interface test 6 RX FIFO dumping e Spacewire 1 amp 2 memory area 1 initialization e Spacewire 1 amp 2 memory area 1 validation 4 3 4 9 TX AHB master interface test 2 packet abortion The spacewire 1 transmits da
25. ta to the spacewire2 then receives an abortion command e Spacewire 1 amp 2 interrupts clearing e Spacewire 1 descriptor initialization e Spacewire 2 memory area 1 validation e Spacewire 1 abort_packet flag activated e Spacewire 2 verify the EEP REC IT activation e Spacewire 2 check the status 01 in the last packet header 4 3 1 10 Test of Area1_valid and Area2_valid flags These flags cannot be reset by the user except in test mode e Spacewire 1 write and read of areax valid in test mode e Spacewire 1 write and read of areax valid in normal mode 4 3 1 11 TX AHB master interface test 3 new transfer after packet abortion e Spacewire 1 descriptor initialization e Spacewire 1 check the end list IT activation e Compare the data received by the spacewire 2 with the reference 4 3 1 12 Test of the interrupts IT R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 147 Spacewire 1 force ITmask to 0000 then check the value Spacewire 1 force ITmask to FFFF then check the value Spacewire 1 force all the internal IT to 0 then activate only one IT each time and check each IT by reading the IT register Spacewire 1 check the nominal or error IT output with the emu test sig emulator 4 3 1 13 Test of time code The spacewire 1 sends time codes during the data transmission The spacewire 2 is checked for time code reception Spacewire 2 force all internal IT to 0 Spacewire 1 descriptor initialization Spacewire
26. uested Estimated Requested Estimated Clock Frequency Frequency Period Period Slack clk_tx 109 9 MHz 106 7 MHz oq 9 4 0 3 Co rxgccLkK crx 55 0 MHz 84 0 MHz 18 2 12 9 clk_sw 25 0 MHz 40 7 MHz 40 0 24 6 KOSS clk_txin 109 9 MHz 119 0 MHz 9 1 8 4 Cell usage FDCE Q Q G V FDR MUXF5 MUXF6 XORCY MUXCY L FDRE FDS MULT AND keepbuf MUXCY Resource Usage Report Mapping to part xcv2000ebg560 6 533 uses 37 uses 302 uses 10 uses 1 use 10 uses 25 uses 36 uses 1 use 1 use 36 uses 15 uses 1 use 250 uses 337 uses 36 uses 16 uses 51 uses 2 uses 4 uses R amp D SOC NT 295 V ASTR 0 Rev 1 25 04 2002 25 I O primitives OBUF 247 uses IBUF 124 uses BUFGP 2 uses I O Register bits 1 Register bits not including I Os 1041 2 Internal tri state buffer usage summary BUFTs BUFEs 36 of 19200 0 RAM ROM usage summary Dual Port Rams RAM16X1D 77 Global buffer usage summary BUFGs BUFGPs 2 of 4 50 Mapping Summary Total LUTs 1973 5 Found clock clk tx with period 9 09091ns Found clock clk sw with period 40ns Found clock clk txin with period 9 09091ns Found clock clk rx with period 18 1818ns 5 5 SYNTHESIS CONCLUSION The synthesis is successful The expected transmission rate is about 100 Mbits s so the timing report is satisfactory 6 XILINX PLACE AND ROUTE 6 1 PRESENTATION The place and route task
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