Microcomputer Components C501
Contents
1. SIEMENS C301 Table 3 Contents of the SFRs SFRs in numeric order of their addresses Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit2 Bit1 Bit 0 after Reset 80 4 PO T 6 5 4 3 2 0 81 SP 07H 37 6 5 4 3 2 4 0 824 DPL 00H 7 6 m 4 3 2 4 0 834 DPH 00H 7 6 29 4 3 2 4 0 874 PCON OXXX SMOD GF1 GFO PDE IDLE 0000p 884 00 1 TR1 TFO TRO IE1 IT1 IEO ITO 894 TMOD GATE C T M1 MO GATE M1 MO 110 00H 7 6 4 3 2 0 8By ITLI 00H 27 6 5 4 3 2 0 8 THO 00H Ti 6 D 4 3 2 0 80 1 00H 7 6 5 4 3 2 0 9012 1 3 6 i5 4 3 2 0 982 SCON 00 SMO 5 1 SM2 REN TB8 RB8 TI RI 99 SBUF 7 6 Ba 4 3 2 4 0 2 P2 T 6 5 4 28 0 IE 0X00 ET2 ES EX1 ETO EXO 0000p WR T1 TO INT1 INTO TxD RxD B8 4 XX00 PT2 PS PT1 PX1 PTO PXO 0000p 00 TF2 EXF2 RCLK 2 C T2 CP RL2 C94 T2AMOD DCEN XXXO0p RC2L 00H 7 6 5 4 3 2 4 0 RC2H 00H 7 6 5 4 3 2 4 0 TL2 00H 7 6 ES E 3 2 4 0 TH2 00H 7 6 5 4 3 2 4 0 DOW PSW 00 FO RS1 RSO OV F1 P ACC 00H a 6 5 4 2 0 00H T 6 5 4 3 0 1 X means that the value is undefined a2. 17 53 t042 16 56 0 05 ndex Marking 1 0 035 x 45 16 56 5005 77 17 53 012 018 A B D es not include plastic or metal protrusion of 0 15 max per side GPL05882 Figure 23 P LCC 44 Package Outlines Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information SMD Surface Mounted Device Dimensions in mm Semiconductor Group 47 1997 04 01 SIEMENS C501 Plastic Package P MQFP 44 SMD for C501G L C501G 1R Plastic Metric Quad Flat Package 4 i 13 2 101 10 01 44 Index Marking Figure 24 P MQFP 44 Package Outlines Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information SMD Surface Mounted Device Semiconductor Group 48 GPM05957 Dimensions in mm 1997 04 01
3. zo 5 ns Vi Vas 0 5 F 0 5 V XTAL2 N C RESET EA Vas PortO all other pins are disconnected max at other frequencies is given by active mode Icc 1 27 X fosc 5 73 idle mode Icc 0 28 X fosc 1 45 C501 L and C501 1R only where fosc is the oscillator frequency in MHz values are given in mA and measured at 5 V Semiconductor Group 32 1997 04 01 SIEMENS C501 AC Characteristics for C501 L C501 1R C501 1E 0 70 25V 10 15 Vss 0 Program Memory Characteristics for the SAB C501 40 85 C for the SAF C501 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Parameter Symbol Limit Values Unit 12 MHz Variable Clock Clock 3 5 MHz to 12 MHz min max min max ALE pulse width 127 40 5 Address setup to ALE 43 40 ns Address hold after ALE 30 53 ns ALE low to valid instr in fiy 233 100 ns ALE to PSEN Tipi 58 25 ns PSEN pulse width dora 215 35 ns PSEN to valid instr in foni 150 100 ns Input instruction hold after PSEN 0 0 ns Input instruction float after PSEN 12 63 20 ns Address valid after PSEN 75 fecic 8 ns Address to valid instr in ta
4. 0 1 RESET Input low voltage EA 0 5 0 2 2 0 3 Input low voltage RESET Vio 0 5 0 2 0 1 V Input high voltage except 0 2 0 9 0 5 V XTAL1 EA RESET Input high voltage to XTAL1 Vi 0 7 0 5 Input high voltage to EA Vins 0 6 Voc 0 5 V RESET Output low voltage Vor 0 45 Ig 1 6 mA ports 1 2 3 Output low voltage Vout 0 45 V 3 2 mA port 0 ALE PSEN Output high voltage Vou 2 4 80 ports 1 2 3 0 9 2 10 uA Output high voltage Vou 1 2 4 800 port 0 in external bus mode 0 9 80 uA ALE PSEN Logic 0 input current 1 10 50 Vy 0 45 V ports 1 2 3 Logical 1 0 transition 65 650 Vn 2V current ports 1 2 3 Input leakage current n t1 10 45 lt Vin Voc port 0 EA Pin capacitance Cio 10 pF fc 1MHz 25 Power supply current Active mode 12 MHz cc 21 mA Voc 5 V 4 Idle mode 12 MHz 4 8 mA 5 5 Active mode 24 MHz 1 36 2 mA 5 4 Idle mode 24 MHz 8 2 mA 5 5 Active mode 40 MHz 1 56 5 mA 5 4 Idle mode 40 MHz 12 7 mA 5 5 Power Down Mode Ipp 50 2 5 5 V9 Notes see 32 Semiconductor Group 30 1997 04 01 SIEMENS C501 DC Characteri
5. 00H DPH Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 82H 00H PSW Program Status Word Register 00H SP Stack Pointer 81H 07H Interrupt IE Interrupt Enable Register A8y 0 000000 System IP Interrupt Priority Register 8 XX000000p Ports PO Port 0 80H FFH P1 Port 1 90H FFH P2 Port 2 3 Serial PCON Power Control Register 87 0XXX0000p Channel SBUF Serial Channel Buffer Register 99H XXH SCON Serial Channel Control Register 98H Timer 0 Timer 0 1 Control Register 88H 00H Timer 1 THO Timer 0 High Byte 8CH 00H TH1 Timer 1 High Byte 00H TLO Timer 0 Low Byte 8AH 00H TL1 Timer 1 Low Byte 8BH 00H TMOD Timer Mode Register 89H Timer2 T2CON Timer 2 Control Register 00H T2MOD Timer 2 Mode Register C9H XXXXXXXOp RC2H Timer 2 Reload Capture Register High Byte CBy 00H RC2L Timer 2 Reload Capture Register Low Byt CAH 00H TH2 Timer 2 High Byte CDH 00H TL2 Timer 2 Low Byte CCH 00H Pow Sav PCON Power Control Register 87H OXXX0000p Modes 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is undefined and the location is reserved Semiconductor Group 17 1997 04 01
6. fcucx ns Rise time 21 12 ns Fall time 12 ns Semiconductor Group 36 1997 04 01 SIEMENS 6997 AC Characteristics for C501 L40 C501 1R40 Vcc25V 10 15 20V 0 70 for the SAB C501 40 Cto85 C for the SAF C501 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Program Memory Characteristics Parameter Symbol Limit Values Unit 40 MHz Variable Clock Clock 3 5 MHz to 40 MHz min max min max ALE pulse width 35 2 toc 15 ns Address setup to ALE 10 15 ns Address hold after ALE 10 15 ns ALE low to valid instr in fiy 55 45 ns ALE to PSEN TEM 10 faucib ns PSEN pulse width dor 60 15 ns PSEN to valid instr in fori 25 50 ns Input instruction hold after PSEN 0 0 ns Input instruction float after PSEN 12 20 toc 5 ns Address valid after PSEN 20 torce 5 ns Address to valid instr in tavy 65 60 ns Address float to PSEN fiot 5 5 ns Interfacing the C501 to devices with float times up to 25ns is permissible This limited bus contention will not cause any damage to port 0 Drivers Semiconductor Group 37 1997 04 01 SIEMENS C501 AC Characteristics for C501 L40 C501 1R40 cont d External Data M
7. TxD P3 1 ALE PROG INTO P3 2 PSEN INT1 P3 3 P2 7 M5 TO P3 4 P2 6 M4 T1 P3 5 P2 5 A13 21 22 23 MCP03214 Figure 2 Pin Configuration P LCC 44 Package Top view Semiconductor Group 5 1997 04 01 SIEMENS C301 2 1 1 2 P0 0 ADO P0 1 AD1 P0 2 AD2 P0 3 AD3 P0 4 AD4 PO 5 AD5 P0 6 AD6 P0 7 AD7 EAVpp ALE PROG INTO P3 2 12 PSEN INT1 P3 3 13 P2 7 A15 P2 6 A14 P2 5 A13 P2 4 A12 P2 3 A11 2 2 10 2 1 9 P2 0 A8 03215 Figure 3 Pin Configuration P DIP 40 Package top view Semiconductor Group 6 1997 04 01 SIEMENS om LIT P0 4 AD4 T 1 P0 5 AD5 I1 1 P2 6 A14 IT 1 P2 5 A13 3 32 4 23 P0 3 AD3 P2 4 A12 P0 2 AD2 P2 3 A11 P0 1 AD1 P2 2 M0 P0 0 ADO P2 1 A9 Vec P2 0 A8 N C N C P1 0 T2 Veg P1 1 T2EX 1 2 XTAL2 1 3 RD P3 7 P14 WR P3 6 03216 INT1 P3 3 lt 0 34 T1 P3 5 Figure 4 Pin Configuration P MQFP 44 Package top view Port 0 8 Bit Digital 1 0 Port 1 8 Bit Digital 1 0 RESET gt 2 8 Bit Digital 1 0 ALE PROG mou Port 3 PSEN 8 Bit Digital 1 0 MCL03217 Figure 5 Logic Symbol Semiconductor Group 7 1997 04 01 SIEMENS C501 Table 1 Pin Definitions and Functions Symbol Pin Number P LCC 44 P DIP 40 P MQFP 44 Function P1 0 P1 7 2 9 1 8
8. 5 Active mode 24 MHz ec 36 2 mA 5 V Idle mode 24 MHz Icc 20 mA Voc25V 9 Power Down Mode 50 2 5 5 V9 Notes see next page Semiconductor Group 31 1997 04 01 SIEMENS 6997 Notes 1 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo of ALE and port 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 0 transitions during bus operation In the worst case capacitive loading gt 100 pF the noise pulse on ALE line may exceed 0 8 V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input Capacitive loading on ports 0 and 2 may cause the Vo on ALE and PSEN to momentarily fall bellow the 0 9 specification when the address lines are stabilizing Power Down Mode is measured under following conditions EA RESET Vss XTAL2 N C XTAL1 Vss all other pins are disconnected Icc active mode is measured with XTAL1 driven with 5 ns Vi Vas 0 5 0 5 V XTAL2 N C EA 0 RESET all other pins are disconnected would be slightly higher if a crystal oscillator is used appr 1 mA Idle mode is measured with all output pins disconnected and with all peripherals disabled XTAL1 driven with
9. 40 44 1 3 40 Port 1 is a quasi bidirectional I O port with internal pull up resistors Port 1 pins that have 1s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 1 pins being externally pulled low will source current J the DC character istics because of the internal pull up resistors Port 1 also contains the timer 2 pins as secondary function The output latch corresponding to a secondary function must be pro grammed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 1 as follows P1 0 T2 Input to counter 2 1 1 T2EX Capture Reload trigger of timer 2 Up Down count Semiconductor Group 1997 04 01 SIEMENS C501 Table 1 Pin Definitions and Functions cont d Symbol Pin Number P LCC 44 P DIP 40 P MQFP 44 Function P3 0 P3 7 11 18 19 16 17 18 10 17 10 11 12 13 14 15 16 17 5 7 13 10 11 12 13 Port 3 is a quasi bidirectional I O port with internal pull up resistors Port 3 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state they can be used as inputs As inputs port 3 pins being externally pulled low will source current Z in the DC characteristics because of the internal pull u
10. DIP 40 Pin 18 P DIP 40 Pin 18 M QFP 44 Pin 14 M QFP 44 Pin 14 3 5 40 MHz C External Oscillator Signal XTAL1 XTAL1 P LCC 44 Pin 21 P LCC 44 Pin 21 P DIP 40 Pin 19 P DIP 40 Pin 19 44 15 M QFP 44 Pin 15 20pF 10 pF 502459 incl stray capacitance Note During programming and verification of the C501 1E OTP memory a clock signal of 4 6 MHz must be applied to the device Figure 21 Recommended Oscillator Circuits Semiconductor Group 45 1997 04 01 SIEMENS 6997 Package Outlines Plastic Package P DIP 40 for C501G L C501G 1R Plastic Dual in Line Package 45 245038 18 71 5025 4 83 MAX 1 27 0 05 10 25 38 MIN 11 0 ETE 0 461 0 1 L p S 4340 2 40 21 Eon pn any nS p pg pn pg rh 52 3 1057 Index Marking 1 Does not include plastic or metal protrusion of 0 25 max per side GPD05883 Figure 22 P DIP 40 Package Outlines Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information Dimensions in mm Semiconductor Group 46 1997 04 01 SIEMENS nd Plastic Package P LCC 44 SMD for C501G L C501G 1R C501G 1E Plastic Leaded Chip Carrier 3 86 t0 0t lt lt 4 57 MAX 15 5108
11. Semiconductor Group 19 1997 04 01 SIEMENS C501 Timer 2 Timer 2 is a 16 bit timer counter with an up down count feature It can operate either as timer or as an event counter which is selected by bit C T2 T2CON 1 It has three operating modes as shown in table 5 Table 5 Timer Counter 2 Operating Modes T2CON T2MOD T2CON Input Clock Mode PXCLK cp P11 Remarks external or m 182 2 P1 0 T2 TxCLK DCEN EXEN 16 bit 0 0 1 0 0 X reload upon Auto overflow reload 0 0 1 0 1 reload trigger falling edge fosc 24 0 0 1 1 X 0 Down counting 0 0 1 1 X 1 Up counting 16 bit 1 1 X 0 X 16 bit Timer Cap Counter only ture up counting 0 1 1 X 1 capture TH2 OSE fosc 24 TL2 RC2H RC2L Baud 1 X 1 X 0 X no overflow Rate interrupt Gene request TF2 fose 2 max rator 1 X 1 X 1 extra external 2 fosc 24 interrupt Timer 2 off X X 0 X X X 2 stops Note falling edge Semiconductor Group 20 1997 04 01 SIEMENS 6997 Serial Interface USART The serial port is full duplex and can operate in four modes one synchronous mode three asynchronous modes as illustrated in table 6 The possible baudrates can be calculated using the formulas given in table 7 Table 6 USART Operating Modes SCON Baudrate Description SMO 5 1 0 0 0 12 Serial data enters and exits
12. Teig 65 to 150 C Voltage pins with respect to ground Vss 0 5V to 6 5 V Voltage on any pin with respect to ground 0 5 V to 40 5 V Input current on any pin during overload 10 mA to 10 mA Absolute sum of all input currents during overload condition 1100 mA Power dissIDallOl o e t a elie tba a dis eee TBD Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overload conditions gt or lt Vss the Voltage on pins with respect to ground Vss must not exceed the values defined by the absolute maximum ratings Semiconductor Group 29 1997 04 01 SIEMENS C501 DC Characteristics for C501 L C501 1R Voc 25V 10 15 9 Vss 0 V Ta 0 70 C T 40 C to 85 C for the SAB C501 for the SAF C501 Parameter Symbol Limit Values Unit Test Condition min max Input low voltage except EA Vi 0 5 0 2
13. Variable Clock Freq 3 5 MHz to 12 MHz min max Oscillator period 83 3 285 7 ns High time 20 ns Low time cicx 20 ns Rise time m 20 ns Fall time 20 ns Semiconductor Group 34 1997 04 01 SIEMENS C501 AC Characteristics for C501 L24 C501 1R24 C501 1E24 Voc 5 V 10 15 96 Vss 0 V Program Memory Characteristics T 0 C to 70 for the SAB C501 40 C to 85 C forthe SAF C501 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Parameter Symbol Limit Values Unit 24 MHz Variable Clock Clock 3 5 MHz to 24 MHz min max min max ALE pulse width 43 40 5 Address setup to ALE 17 25 ns Address hold after ALE 17 25 ns ALE low to valid instr in fiy 80 87 ns ALE to PSEN fini 22 20 ns PSEN pulse width dora 95 30 ns PSEN to valid instr in foni 60 65 ns Input instruction hold after PSEN 0 0 ns Input instruction float after PSEN 12 32 fauci 10 ns Address valid after PSEN Ix 37 ns Address to valid instr in tavy 148 60 ns Address float to PSEN fpi 0 0 ns Interfacing the C501 to devices with float times up to 37 ns is permiss
14. activated every six oscillator periods except during external data memory accesses Remains high during internal program execution RESET 10 9 4 RESET A high level on this pin for two machine cycles while the oscillator is running resets the device An internal diffused resistor to Vss permits power on reset using only an external capacitor to ALE PROG 33 30 27 The Address Latch Enable output is used for latching the low byte of the address into external memory during normal operation It is activated every six oscillator periods except during an external data memory access For the C501 1E this pin is also the program pulse input PROG during OTP memory programming EA V pp 35 31 29 External Access Enable When held at high level instructions are fetched from the internal ROM C501 1R and C501 1E when the PC is less than 2000 When held at low level the C501 fetches all instructions from external program memory For the C501 L this pin must be tied low This pin also receives the programming supply voltage Vpp during OTP memory programming C501 1E only Input Output Semiconductor Group 11 1997 04 01 SIEMENS C501 Table 1 Pin Definitions and Functions cont d Symbol Pin Number Function P LCC 44 P DIP 40 P MQFP 44 0 7 43 36 39 32 37 30 PortO is an 8 bit ope
15. external clock signal since the input to the internal clocking circuitry is divided down by a divide by two flip flop Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed P2 0 P2 7 24 31 21 28 18 25 2 is quasi bidirectional I O port with internal pull up resistors Port 2 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state they can be used as inputs As inputs port 2 pins being externally pulled low will source current Z in the DC characteristics because of the internal pull up resistors Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pull up resistors when issuing 1s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 issues the contents of the P2 special function register Input Output Semiconductor Group 10 1997 04 01 SIEMENS C501 Table 1 Pin Definitions and Functions cont d Symbol Pin Number P LCC 44 P DIP 40 44 Function PSEN 32 29 26 The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations It is
16. interrupt 000 IE1 External interrupt 1 0013H TF1 Timer 1 interrupt 001BH RI TI Serial port interrupt 0023H TF2 EXF2 Timer 2 interrupt 002By A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt cannot be interrupted by any other interrupt source If two requests of different priority level are received simultaneously the request of higher priority is serviced If requests of the same priority are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 9 Table 9 Interrupt Priority Within Level Interrupt Source Priority External Interrupt 0 IEO High Timer 0 Interrupt TFO External Interrupt 1 IE1 Timer 1 Interrupt TF1 Serial Channel RI TI Timer 2 Interrupt TF2 EXF2 Low Semiconductor Group 23 1997 04 01 SIEMENS nd Power Saving Modes Two power down modes are available the Idle Mode and Power Down Mode The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode respectively If the Power Down mode and the Idle mode are set at the same time the Power Down mode takes precedence Table 10 gives a general overview of the power saving modes Table 10 Power Saving Modes Overview Mode Entering Lea
17. its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain hu man life If they fail it is reasonable to assume that the health of the user may be endangered SIEMENS 8 Bit CMOS Microcontroller C501 Preliminary Fully compatible to standard 8051 microcontroller Versions for 12 24 40 MHz operating frequency Program memory completely external C501 L 8K x 8 ROM C501 1R 8K x 8 OTP memory C501 1E e 256 x 8 RAM Four 8 bit ports Three 16 bit timers counters timer 2 with up down counter feature USART e Six interrupt sources two priority levels Power saving modes e Quick Pulse programming algorithm C501 1E only 2 Level program memory lock C501 1E only P DIP 40 P LCC 44 and P MQFP 44 package e Temperature ranges SAB C501 0 to 70 C SAF C501 T 40 C to 85 E AM Mo E x8 1 0 1 1 0 ROM C501 1R 8K x 8 1 03238 Figure 1 C501G Functional Units Semiconductor Group 3 1997 04 01 C501 SIEMENS The C501 1R contains a non volatile 8K x 8 read only program memory a volatile 256 x 8 read write data memory four ports three 16 bit timers counters a seven source two priority level interrupt structure and a serial port The C501 L is identical exce
18. reading the signature byte and for programming the program memory the encryption table and the security bits The circuit configuration and waveforms for quick pulse programming are shown in figures 10 to 12 Table 11 OTP Programming Modes Mode RESET PSEN ALE EA Vpp P2 7 P2 6 P3 7 P3 6 PROG Read signature 1 0 1 1 0 0 0 0 Program code data 1 0 0 Vpp 1 0 1 1 Verify code data 1 0 1 1 0 0 1 1 Progam encryption table 1 0 0 Vpp 1 0 1 0 Program security bit 1 1 0 0 Vpp 1 1 1 1 Program security bit 2 1 0 0 Vpp 1 1 0 0 Notes 1 0 valid low for that pin 1 valid high for that pin 2 Vpp 12 75 V 0 25V 3 Vec 5 V 10 during programming and verification 4 ALE PROG receives 25 programming pulses while Vpp is held at 12 75 V Each programming pulse is low for 100 us 10 us and high for a minimum of 10 us 1 Quick Pulse Programming is a trademark phrase of Intel Corporation Semiconductor Group 25 1997 04 01 SIEMENS Quick Pulse Programming The setup for microcontroller quick pulse programming is shown in figure 10 Note that the C501 1E is running with a 4 to 6 MHz oscillator The reason the oscillator needs to be running is that the device is executing internal address and program data transfers The address of the OTP memory location to be programmed is applied to port 1 and 2 as shown in figure 10 The code byte to be programmed into t
19. through RxD TxD outputs the shift clock 8 bit are transmitted received LSB first 1 0 1 Timer 1 2 overflow rate 8 bit UART 10 bits are transmitted through TxD or received RxD 2 1 0 82 64 9 bit UART 11 bits are transmitted TxD or received RxD 3 1 1 Timer 1 2 overflow rate 9 bit UART Like mode 2 except the variable baud rate Mode Table 7 Formulas for Calculating Baudrates Baud Rate Interface Mode Baudrate derived from Oscillator 0 fosc 12 2 29V0P x fosc 64 Timer 1 16 bit timer 1 3 25 00 x timer 1 overflow rate 32 8 bit timer with 1 3 2500 x fosc 32 x 12 x 256 TH1 8 bit autoreload Timer 2 1 3 fosc 32 x 65536 RC2H RC2L Semiconductor Group 21 1997 04 01 SIEMENS nd Interrupt System The C501 provides 6 interrupt sources with two priority levels Figure 9 gives a general overview of the interrupt sources and illustrates the request and control flags High Priority Timer 0 Overflow Low Priority TCON 5 ETO IE 4 Timer 1 Overflow TCON 0 TCON 7 Timer 2 Overflow T2CON 6 IE 2 IE 7 i 501783 Figure 9 Interrupt Request Sources Semiconductor Group 22 1997 04 01 SIEMENS om Table 8 Interrupt Sources and their Corresponding Interrupt Vectors Source Request Flags Vector Vector Address IEO External interrupt 0 0003H TFO Timer 0
20. 9 1997 04 01 SIEMENS nd RiorDPL P2 0 P2 7 or A8 A15 from A8 A15 from PCH MCT00097 Figure 14 Data Memory Read Cycle Semiconductor Group 40 1997 04 01 SIEMENS nd Instr IN P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH MCT00098 Figure 15 Data Memory Write Cycle MCT00033 Figure 16 External Clock Drive at XTAL2 Semiconductor Group 41 1997 04 01 SIEMENS 6997 ROM Verification Characteristics for C501 1R ROM Verification Mode 1 Parameter Symbol Limit Values Unit min max Address to valid data 4815 cL ns ENABLE to valid data 48to ci ns Data float after ENABLE 0 48tci cL ns Oscillator frequency 4 6 MHz P1 0 P1 7 P2 0 P2 4 P2 7 ENABLE MCT00049 Address P1 0 P1 7 0 A7 P2 0 P2 4 A8 A12 Data P0 0 P0 7 DO D7 Figure 17 ROM Verification Mode 1 Semiconductor Group 42 1997 04 01 SIEMENS C501 OTP Programming and Verification Characteristics 25V c 1096 Vss 0 V 21 27 Parameter Symbol Limit Values Unit min max Programming supply voltage Vpp 12 5 13 0 V Programming supply current lpp 50 mA Oscillator frequency 1 toe 4 6 MHz Address setup to ALE PROG low Lives 48 t
21. SIEMENS M icrocomputer Components 8 Bit CM OS M icrocontroller Data Sheet 04 97 C501 Data Sheet Revision History 1997 04 01 Previous Releases 11 92 11 93 08 94 08 95 10 96 Page Page Subjects changes since last revision previous new version version general C501G 1E OTP version included 4 4 Ordering information resorted and C501G 1E types added 5 5 Table with literature hints added 5 7 5 7 Pin configuration logic symbol for pins EA Vpp and ALE PROG updated 11 11 Pin description for ALE PROG and EA Vpp completed 8 9 10 8 9 10 Port 1 3 2 pin description bidirectional replaced by quasi bidirectional 13 13 Block diagram updated for C501G 1E 14 14 New design of register PSW description 15 Memory organization added 15 18 16 18 Actualized design of the SFR tables 17 17 Reset value of T2CON corrected 25 28 Description for the C501 1E OTP version added 31 DC characteristics for C501 1E added 41 41 Timing External Clock Drive now behind Data Memory Cycle 43 44 AC characteristics for C501 1E added Edition 1997 04 01 Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 M nchen Siemens AG 1997 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits imple
22. ces up to 64 Kbyte of internal external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area Figure 7 illustrates the memory address spaces of the C501 External External Indirect Direct Address Address Internal BAN Register 80 H Internal External Internal EA 1 EA 0 RAM 0000 00 Y n Code Space Data Space Internal Data Space MCD03224 Figure 7 C501 Memory Map Semiconductor Group 15 1997 04 01 SIEMENS om Special Function Registers The registers except the program counter and the four general purpose register banks reside in the special function register area The 27 special function registers SFRs include pointers and registers that provide an interface between the CPU and the other on chip peripherals All SFRs with addresses where address bits 0 2 are 0 e g 80H 88 4 90 98 8 FFH are bitaddressable The SFRs of the C501 are listed in table 2 and table 3 In table 2 they are organized in groups which refer to the functional blocks of the C501 Table 3 illustrates the contents of the SFRs in numeric order of their addresses Semiconductor Group 16 1997 04 01 SIEMENS C501 Table 2 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC Accumulator 00H B B Register
23. emory Characteristics Parameter Symbol Limit Values Unit 40 MHz Variable Clock Clock 3 5 MHz to 40 MHz min min max RD pulse width fai RH 120 30 ns WR pulse width food 120 30 ns Address hold after ALE 10 torc 15 ns RD to valid data in bv 75 50 ns Data hold after RD Palins 0 0 ns Data float after RD 38 2 toc 12 ns ALE to valid data in 150 8 torco 50 ns Address to valid data in 150 9 torci 75 ns ALE to WR or RD fiw 60 90 terco 15 15 ns Address valid to WR or RD bn 70 4 30 ns WR or RD high to ALE high 10 40 terc 15 faic 15 ns Data valid to WR transition fox 5 1 20 ns Data setup before WR fave 125 7 50 ns Data hold after WR 5 1 20 ns Address float after RD ions 0 0 ns External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Clock Freq 3 5 MHz to 40 MHz min max Oscillator period 25 285 7 ns High time 10 terel ns Low time cicx 10 ns Rise time 10 ns Fall time 10 ns Semiconductor Group 38 1997 04 01 SIEMENS nd MCT00096 Figure 13 Program Memory Read Cycle Semiconductor Group 3
24. for this operation If the encryption table has been programmed the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes The user will have to know the encryption table contents in order to correctly decode the verification data The encryption table itself cannot be read out Reading the Slgnature Bytes The signature bytes are read by the same procedure as a normal verification of loctions 304 and except that P3 6 and P3 7 need to be pulled to a logic low The values are indicates manufacturer 31H 71 indicates C501 1E Semiconductor Group 26 1997 04 01 SIEMENS 201 Voc Port 0 Programming Data EAVop 41275 V ALE PROG 25 x 100 us Low Pulses PSEN P2 7 P2 6 P2 0 P2 4 MCS03232 Figure 10 C501 1E OTP Memory Programming Configuration 25 Pulses AEPROG fy YT 1005 min 100 Us 1018 1 ALE PROG 0 MCT03234 Figure 11 C501 1E ALE PROG Waveform Semiconductor Group 27 1997 04 01 SIEMENS S291 Voc Programming Data Port 0 ALE PROG PSEN P2 7 0 Enable P2 6 0 P2 0 P2 4 503235 12 501 1 Memory Verification Semiconductor Group 28 1997 04 01 SIEMENS C301 Absolute Maximum Ratings Ambient temperature under bias 40 to 85 Storage temperature
25. hat location is applied to port 0 RESET PSEN and pins of port 2 and 3 specified in table 11 are held at the Program code data levels The ALE PROG signal is pulsed low 25 times as shown in figure 11 For programming of the encryption table the 25 pulse programming sequence must be repeated for addresses 0 through using the Program encrytion table levels After the encryption table is programmed verification cycles will produce only encrypted data For programming of the security bits the 25 pulse programming sequence must be repeat using the Program security bit levels After one security bit is programmed further programming of the code memory and encryption table is disabled However the other security bit can still be programmed Note that the EA Vpp pin must not be allowed to go above the maximum specified Vpp level for any amount of time Even a narrow glitch above that voltage can cause permanent damage to the device The Vpp source should be well regulated and free of glitches and overshoots Program Verification If security bit 2 has not been programmed the on chip OTP program memory can be read out for program verification The address of the OTP program memory locations to be read is applied to ports 1 and 2 as shown in figure 12 The other pins are held at the Verify code data levels indicated in table 11 The contents of the address location will be emitted on port 0 External pullups are required on port 0
26. ible This limited bus contention will not cause any damage to port 0 Drivers Semiconductor Group 35 1997 04 01 SIEMENS AC Characteristics for C501 L24 C501 1R24 C501 1E24 cont d External Data Memory Characteristics Parameter Symbol Limit Values Unit 24 MHz Variable Clock Clock 3 5 MHz to 24 MHz min min max RD pulse width 180 70 5 WR pulse width Tula 180 70 ns Address hold after ALE 15 27 5 RD to valid data in bv 118 90 ns Data hold after RD Palins 0 0 ns Data float after RD 63 2 20 ns ALE to valid data in 200 133 ns Address to valid data in 220 155 ns ALE to WR or RD fw 75 175 Stoic 50 Stoic 50 ns Address valid to WR or RD ont 67 97 ns WR or RD high to ALE high Pisas c 1 25 ns Data valid to WR transition fox 5 37 ns Data setup before WR fave 170 122 ns Data hold after WR Lis 15 fore ns Address float after RD ions 0 0 ns External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Clock Freq 3 5 MHz to 24 MHz min max Oscillator period 41 7 285 7 ns High time 12 terel ns Low time cicx 12
27. mented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semiconductor Group Siemens AG is an approved CECC manufacturer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs in curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect
28. n drain bidirectional I O port Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this application it uses strong internal pull up resistors when issuing 1s Port 0 also outputs the code bytes during program verification in the C501 1R and C501 1E External pull up resistors are required during program verification Vss 22 20 16 Circuit ground potential Vec 44 40 38 Supply terminal for all operating modes N C 1 12 6 17 No connection 23 34 28 39 O Output Semiconductor Group 12 1997 04 01 SIEMENS 201 Functional Description The C501 is fully compatible to the standard 8051 microcontroller family It is compatible with the 80C32 52 82C52 While maintaining all architectural and operational characteristics of the 8051microcontroller family the C501 incorporates some enhancements in the timer 2 unit Figure 6 shows a block diagram of the C501 C501 1R ROM C501 1E OTP XTAL1 8K x 8 XTAL2 RESET ALE PROG Port 0 8 Bit Digit 1 0 Port 1 8 Bit Digit 1 0 Port 2 8 Bit Digit 1 0 Port 3 Serial Channel 8 Bit Digit USART MCB03219 Figure 6 Block Diagram of the C501 Semiconductor Group 13 1997 04 01 SIEMENS C30 CPU The C501 is efficient both as a cont
29. nd the location is reserved 2 Bit addressable special function registers Semiconductor Group 18 1997 04 01 SIEMENS Timer Counter 0 and 1 Timer counter 0 and 1 can be used in four operating modes as listed in table 4 Table 4 Timer Counter 0 and 1 Operating Modes Mode Description TMOD Input Clock Gate C T M1 MO internal external max 0 8 bit timer counter with a X X 0 foscli2ex92 086 24 divide by 32 prescaler 1 16 bit timer counter X X 1 1 foscli 4 2 8 bit timer counter with X X 0 0 fosclio 4 8 bit autoreload 3 Timer counter 0 used as one X X 1 1 fosc 12 4 8 bit timer counter and 8 bit timer Timer 1 stops In the timer function C T 0 the register is incremented every machine cycle Therefore the count rate is fosc 12 In the counter function the register is incremented in response to 1 to O transition at its corresponding external input pin P3 4 TO P3 5 T1 Since it takes two machine cycles to detect a falling edge the max count rate is 24 External inputs INTO and INT1 P3 2 P3 3 can be programmed to function as a gate to facilitate pulse width measurements Figure 8 illustrates the input clock logic gt fosc 12 P3 4 TO Timer 0 1 P3 5 T1 Input Clock max 24 P3 2 INTO P3 3 INT1 501768 8 Timer Counter 0 1 Input Clock Logic
30. oe ns Address hold after ALE PROG GHAX 48 ns Data setup to ALE PROG low Isid 48 ns Data hold after ALE PROG fox 48 ns P2 7 ENABLE high to 48 tcc ns Vpp setup to ALE PROG low tsHeL 10 us Vpp hold after ALE PROG low 10 us ALE PROG width 90 110 us Address to data valid tavav 48 toc ns ENABLE low to data valid leroy 48 tec ns Data float after ENABLE 0 48 ns ALE PROG high to ALE PROG low fauc 10 us Semiconductor Group 43 1997 04 01 SIEMENS S291 Programming Verification P1 0 1 7 ALE PROG ENABLE MCT03237 Figure 18 C501 1E OTP Memory Program Read Cycle Semiconductor Group 44 1997 04 01 SIEMENS nd 0 2 V c 0 9 Test Points 0 45 V 00039 AC Inputs during testing are driven at 0 5 V for a logic 1 and 0 45 V for a logic 0 Timing measurements are made at for a logic 1 and for a logic 0 Figure 19 AC Testing Input Output Waveforms Timing Reference Points VoL 40 1 V MCT00038 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when 100 mV change from the loaded Von Vo level occurs 20 Figure 20 AC Testing Float Waveforms Crystal Oscillator Mode Driving from External Source XTAL2 XTAL2 P LCC 44 Pin 20 P LCC 44 Pin 20 P
31. p resistors Port 3 also contains the interrupt timer serial port 0 and external memory strobe pins which are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 3 as follows P3 0 RxD receiver data input asyn chronous or data input output synchronous of serial interface 0 transmitter data output asynchronous or clock output synchronous of the serial interface 0 interrupt 0 input timer 0 gate control interrupt 1 input timer 1 gate control P3 1 TxD P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 counter 0 input counter 1 input the write control signal lat ches the data byte from port 0 into the external data memory the read control signal enables the external data memory to port O Output Semiconductor Group 1997 04 01 SIEMENS C501 Table 1 Pin Definitions and Functions cont d Symbol Pin Number P LCC 44 P DIP 40 44 Function XTAL2 20 18 14 XTAL2 Output of the inverting oscillator amplifier XTAL1 21 19 15 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected There are no requirements on the duty cycle of the
32. pt that it lacks the program memory on chip The C501 1E contains a one time programmable OTP program memory on chip The term C501 refers to all versions within this specification unless otherwise noted Further the term C501 refers to all versions which are available in the different temperature ranges marked with SAB C501 or SAF C501 Ordering Information Type Ordering Code Package Description 8 Bit CMOS microcontroller SAB C501G LN Q67120 C969 44 for external memory 12 MHz SAB C501G LP Q67120 C968 40 SAB C501G LM Q67127 C970 P MQFP 44 SAB C501G L24N 067120 1001 P LCC 44 for external memory 24 MHz SAB C501G L24P 1067120 999 40 SAB C501G L24M 067127 1014 P MQFP 44 SAB C501G L40N Q67120 C1002 P LCC 44 for external memory 40 MHz SAB C501G L40P Q67120 C1000 P DIP 40 SAB C501G LA0M 067127 1009 P MQFP 44 SAF C501G L24N 067120 1011 P LCC 44 for external memory 24 MHz SAF C501G L24P Q67120 C1010 P MQFP 44 ext temp 40 C to 85 C SAB C501G 1RN Q67120 DXXX P LCC 44 with mask programmable ROM 12 MHz SAB C501G 1RP Q67120 DXXX P DIP 40 SAB C501G 1RM Q67127 DXXX P MQFP 44 SAB C501G 1R24N Q67120 DXXX P LCC 44 with mask programmable ROM 24 MHz SAB C501G 1R24P Q67120 DXXX P DIP 40 SAB C501G 1R24M Q67127 DXXX_ P MQFP 44 SAB C501G 1R40N Q67120 DXXX P LCC 44 with mask prog
33. rammable ROM 40 MHz SAB C501G 1R40P Q67120 DXXX P DIP 40 SAB C501G 1R40M Q67127 DXXX_ P MQFP 44 SAF C501G 1R24N Q67120 DXXX P LCC 44 with mask programmable ROM 24 MHz SAF C501G 1R24P Q67120 DXXX_ P DIP 40 ext temp 40 C to 85 C SAB C501G 1EN Q67120 C1054 P LCC 44 with OTP memory 12 MHz SAB C501G 1EP Q67120 C1056 P DIP 40 SAF C501G 1EN Q67120 C2002 P LCC 44 with OTP memory 12 MHz SAF C501G 1EP Q67120 C2003 P DIP 40 ext temp 40 C to 85 C SAB C501G 1E24N 067120 2005 P LCC 44 with OTP memory 24 MHz SAB C501G 1E24P Q67120 C2006 P DIP 40 SAF C501G 1E24N Q67120 C2008 P LCC 44 with OTP memory 24 2 SAF C501G 1E24P Q67120 C2009 P DIP 40 ext temp 40 C to 85 C Semiconductor Group 4 1997 04 01 SIEMENS Note Versions for extended temperature range 40 C to 110 C SAH C501G request The ordering number of ROM types DXXX extensions is defined after program release verification of the customer Additional Literature For further information about the C501 the following literature is available Title Ordering Number C501 8 Bit CMOS Microcontroller User s Manual B158 H6723 X X 7600 C500 Microcontroller Family B158 H6987 X X 7600 Architecture and Instruction Set User s Manual C500 Microcontroller Family Pocket Guide B158 H6986 X X 7600 P1 5 PO A AD4 P16 PO 5 AD5 P17 PO 6 AD6 RESET P0 7 AD7 RxD P3 0 N C N C
34. roller and as an arithmetic processor It has extensive facilities for binary and BCD arithmetic and excels in its bit handling capabilities Efficient use of program memory results from an instruction set consisting of 44 one byte 41 two byte and 15 three byte instructions With a 12 MHz crystal 5896 of the instructions are executed in 1 0 us 24 MHz 500 ns 40 MHz 300 ns Special Function Register PSW Address Reset Value Bit No MSB LSB D7y D3y D24 DOH FO RS1 RSO OV F1 P PSW Bit Function CY Carry Flag Used by arithmetic instruction AC Auxiliary Carry Flag Used by instructions which execute BCD operations FO General Purpose Flag RS1 Register Bank select control bits RSO These bits are used to select one of the four register banks RS1 RSO Function 0 0 Bank 0 selected data address 001 07 0 1 Bank 1 selected data address 084 0FH 1 0 Bank 2 selected data address 10 17 1 1 Bank selected data address 18 1 OV Overflow Flag Used by arithmetic instruction F1 General Purpose Flag P Parity Flag Set cleared by hardware after each instruction to indicate an odd even number of one bits in the accumulator i e even parity Semiconductor Group 14 1997 04 01 SIEMENS nd Memory Organization The C501 CPU manipulates data and operands in the following four address spa
35. stics for C501 1E Voc 25V 10 15 9 Vss 0 V T 0 70 T 40 to 85 C for the SAB C501 for the SAF C501 Parameter Symbol Limit Values Unit Test Condition min max Input low voltage except 0 5 0 2 0 1 EA Vpp RESET Input low voltage EA Vpp 0 5 0 1 Vec 0 1 V Input low voltage RESET Vio 0 5 0 2 0 1 V Input high voltage except 0 2 0 9 0 5 V XTAL1 EA Vpp RESET Input high voltage to XTAL1 Vj 0 7 Voc 0 5 V Input high voltage to EA Vpp 0 6 0 5 V RESET Output low voltage Vor 0 45 Ig 1 6 mA ports 1 2 3 Output low voltage Vout 0 45 V 3 2 mA port 0 ALE PROG PSEN Output high voltage Vou 2 4 80 ports 1 2 3 0 9 2 10 uA Output high voltage Vou 1 2 4 800 port 0 in external bus mode 0 9 80 uA ALE PROG PSEN Logic 0 input current 1 10 50 Vy 0 45 V ports 1 2 3 Logical 1 to 0 transition 65 650 Vn 2V current ports 1 2 3 Input leakage current n t1 10 45 lt Vin Voc port 0 EA Vpp Pin capacitance Cio 10 pF 1 MHz 25 Power supply current Active mode 12 MHz cc 21 mA 5 V Idle mode 12 MHz 18 mA 5
36. ving by Remarks Instruction Example Idle mode ORL PCON 01H enabled interrupt CPU is gated off Hardware Reset CPU status registers maintain their data Peripherals are active Power Down ORL PCON 02 Hardware Reset Oscillator is stopped contents Mode of on chip RAM and SFR s are maintained leaving Power Down Mode means redefinition of SFR contents In the Power Down mode of operation can be reduced to minimize power consumption It must be ensured however that is not reduced before the Power Down mode is invoked and that is restored to its normal operating level before the Power Down mode is terminated The reset signal that terminates the Power Down mode also restarts the oscillator The reset should not be activated before is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize similar to power on reset Semiconductor Group 24 1997 04 01 SIEMENS 6997 Operation The C501 1E is programmed by usng modified Quick Pulse Programming 1 algorithm It differs from older methods in the value used for programming supply voltage and in the width and number of the ALE PROG pulses The C501 1E contains two signature bytes that can be read and used by a programming system to identify the device The signature bytes identify the manufacturer of the device Table 11 shows the logic levels for
37. vy 302 115 ns Address float to PSEN fpi 0 0 ns Interfacing the C501 to devices with float times up to 75 ns is permissible This limited bus contention will not cause any damage to port 0 Drivers Semiconductor Group 33 1997 04 01 SIEMENS AC Characteristics for C501 L 501 18 501 1 contd External Data Memory Characteristics Parameter Symbol Limit Values Unit 12 MHz Variable Clock Clock 3 5 MHz to 12 MHz min max min max RD pulse width 400 100 ns WR pulse width Tua 400 100 ns Address hold after ALE 30 53 ns RD to valid data in bv 252 165 Ins Data hold after RD Palins 0 0 ns Data float after RD 97 70 ns ALE to valid data in tiipv 517 150 ns Address to valid data in 585 165 ALE to WR or RD fw 200 1300 Stoic 50 Stoic 50 ns Address valid to WR or RD bon 203 4tac 130 ns WR or RD high to ALE high ix 40 ns Data valid to WR transition fox 33 50 ns Data setup before WR fave 433 150 ns Data hold after WR 33 50 ns Address float after RD fano 0 0 ns External Clock Drive Characteristics Parameter Symbol Limit Values Unit
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