USER MANUAL - ID TECH JAPAN
Contents
1. with all error bits cleared De asserting the chip select signal aborts all SPI commands and return to an idle state with all error bits cleared Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 14 of 18 TriMag MagStripe Decode ASIC 4 0 TriMag Physical Information 4 1 Pin I O Descriptions Pin Name Pad Description 1 HD1 Magnetic head input track 1 SPI mode connect to GND MSRD mode not used tie low SPI mode SPI chip select MSRD mode Track1 CLK MSRD mode Track1 DATA MSRD mode Track2 CLK MSRD mode Media Detect Open drain SPI mode Slave Out Normal Hi Z MSRD mode PRO 0 Date rate 1 2 card speed rate PRO 1 Date rate card speed rate SPI mode SPI interface clock MSRD mode not used tie low SPI mode Slave input data 18 3V operation connect to 3 3V supply voltage VDD_3V 5V operation connect regulator decoupling capacitor 3V operation connect to 3 3V supply voltage 5V operation connect to 5V supply voltage Ground connection Figure 9 ASIC Pin Out List The supply voltage must always have a decoupling capacitor Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 15 of 18 TriMag MagStripe Decode ASIC 00 1 00 133 o 14 Yd n 1 00 a S e 20 0 19 0 36 0 90 TOP VIEW END VIEW 1 10 MAX 6 50 0 10 PEANES SIDE VIEW Figure 10 ASIC Package amp Pi2. End of Cycle Reset None 0x00 or OxFF NoOp Empty unless in preferably OxFF sequential read in which case the read continues unaffected Figure 8 SPI Communication Commands List Note The track designations are based on read head location to the card reference surface in the reader The head connections for the MagStripe tracks match the head wires associated with the magnetic stripe tracks The three decoding channels in the ASIC are identical any head track signal can be applied to any track pins input pair The outputs will provide the decoded data from the applied inputs Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 13 of 18 TriMag MagStripe Decode ASIC 3 4 4 Sequential Reads Vs Byte Reads When reading a track or all tracks sequentially as long as the nCS SPI Chip Select is asserted and the SPI clock is toggling data is sent to the master During this time the incoming instructions should be NoOp s the number of data bytes n plus 2 For example when reading one track the entire data are streamed out in one 1 96 1 98 byte block 784 bits When reading the entire buffer the message length is 1 3 96 1 290 bytes 2320 bits If the host continues to clock out data after the end of the LRC empty OxFF is transmitted A byte read is different The initial read command returns the header information If the RAM is not busy amp not empty then th
3. Output This output indicates the presence of recorded magnetic media passing the read head on at least one card data track This signal is normally high impedance a low output indicates media The output is an open drain type A pull up resistor is needed for proper operation when used The Media Detect output occurs after circuit synchronization which is the detection of six consecutive amp consistent zero bits are from any one track After Media Detect is low there is a 3uS 50 delay before the first Data Strobe Clock output Note The track designations are based on read head location to the card reference surface in the reader The head connections for the MagStripe tracks match the head wires associated with the magnetic stripe tracks The three decoding channels in the ASIC are identical any head track signal can be applied to any track pins input pair The outputs will provide the decoded data from the applied inputs Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 9 of 18 TriMag MagStripe Decode ASIC SIGNAL INPUT DATA OUTPUT STROBE OUTPUT Figure 5 Clock and Data Timing Diagram Symbo Parameter Timing Setup Time DATA Change to STROBE Falling Edge STROBE Rising Edge to DATA Change lw Pulse Width STROBE 50 of bit width 3uS 3uS 50 50 of bit width 3uS Figure 6 Clock and Data AC Characteristics The Clock amp Da
4. head input is saved in locations 0x300 through 0x5FF and data from the track 3 head input is saved in locations 0x600 to 0x8FF The decoded leading and trailing Zero bits synchronization bits are saved in the RAM along with the data bits The processor must ignore the synchronization bits and format the data characters using pattern matching and parsing techniques Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 11 of 18 TriMag MagStripe Decode ASIC 3 4 2 SPI Normal Mode Operation The SPI interface is primarily for reading the contents of the RAM to retrieve the MagStripe data The SPI data block is preceded by a header and is followed with a validation byte consisting of a Longitudinal Redundancy Check LRC which is computed as a bit wise XOR across all previous data bytes The header byte consists of several status bits BitO This is the Busy bit When bit is high it signals that the RAM is busy with an active swipe Bit 1 This is the Empty bit When it is high it signals that the RAM is currently empty If the RAM is busy or empty only the header is returned to the host There is no data and no LRC in this case The header status is set to not busy amp not empty after a new swipe is detected amp while old buffer data is erased Bit2 This is the Power on Reset POR bit and when high it signals that a POR event has occurred This bit is cleared immediately after re
5. initiate the operation This timing is less than one millisecond When the erase is initiated the data read header status changes to indicate the RAM is busy When the erase is finished the status is changed to empty Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 12 of 18 TriMag MagStripe Decode ASIC When any read request is made that does not return the busy or empty flag the SPI initiates a transaction and receives exclusive access to the RAM The transaction ends when the Arm to Read Flush RAM buffer command is given Any new card swipe made during a transaction is ignored Any new read made during a transaction is also ignored and the out of order error bit is set 3 4 3 SPI Operational Command Descriptions Serial Action Serial Output Command 0x01 Read track one data sequentially Header Track 1 data LRC 0x02 Read track two data sequentially Header Track 2 data LRC 0x03 Read track three data sequentially Header Track 3 data LRC 0x04 Read all tracks sequentially Header Track one data Track two data Track three data LRC 0x05 Arm to Read Flush RAM buffer 0x05 0x06 Report Status Header 0x11 Byte read track one data Header 0x12 Byte read track two data Header 0x13 Byte read track three data Header 0x14 Byte read all track data Header 0x15 Continue reading data Data or LRC see below 0x16
6. oer 1 2 Abbreviations senten pue eter Cot tpe Page Coe Ceo Doer Cer rien Deor RR DI Ue 0 Operating Parameters and Conditions sssssseneee 2 1 Recommend Operation Conditions ssssseeeneeeeeneee 2 2 Absolute Maximum Ratings cccccceeeeeeeeeeeeeceeeeeeeeeeseeneaeeeeeeeeeeeeeeeeeaaeees 2 3 External Component Parameters esesssssessseeeeeeeennnen 3 0 General Functional Description eee tenete ete unen onu eee tee eee 3 1 General Functional Description ssesssseeeeeennennnee 9 2 Sleep Mode FUNCHOM usta RAISED Ma DN eod 3 3 MSRD Mode OUIpLe erred de toledo queer epe tele dee dedic depende dedero 3 3 1 Dara OUIDUD 5 sosta caca S DAMES 3 3 2 Data Strobe Clock Output e tet o a e oti tex eo ha ee eU DE 3 3 3 Media Detect QUIDEUL etitm hetero oett e ereete eaten 3 4 SPI Mode Operation amp Oulpuls 5 ip ende e eda e deleti istas 3 4 1 Static RAM Buffer sai e teca cu ocio addu al qure i eausa 3 4 2 SPI Normal Mode Operation ccccceeeeeeeeeseeeeeeeeeeeeeeeeeeeeneeeeeeeeees 3 4 3 SPI Operational Command Descriptions ccccceeeeeeeeeeeeeeeteeeeeeeees 3 4 4 Sequential Reads Vs Byte Reads ssssssseeeeesse 4 0 TriMag Physical Information sesessssseeenenennnnnnn 43 Pin VO Descripliolis oio htt dote ett tne ette ettet btc 42 Schematic DIaGramis
7. of the Data output with the corresponding strobe Clock represents each Data bit that was recorded on the magnetic strip track The first 6 to 9 bits after Wake up from the leading edge of a magnetic stripe are not provided as output these bits are used for circuit synchronization A Data output high level is a ZERO value data bit and a low level is a ONE value data bit The Data output matches the card data when media is moved by the head in a forward direction The Data output is a mirror image of card data when media is moved by the head in a reverse direction 3 3 2 Data Strobe Clock Output The Data Strobe is a clocking output indicating the magnetic data bit value is present at the Data output The Strobe output is normally high and goes low to indicate the start of a data sample time The Data output is stable and may be sampled on the falling or rising edge of Data Strobe or at anytime within a window defined by the card speed and media data density The receiving interface for the magstripe Data must sense the Hi to Lo Strobe transition leading edge and acquire the Data bit level within a time not exceeding the timing of the next Clock output Since the MagStripe data is buffered into RAM the Clock output is NOT synchronized real time with the card speed amp data density like found in previous versions of decoding ASIC A Half Clock timing mode is selectable to allow data retrieval at a slower rate 3 3 3 Media Detect
8. IDT CH Valuetnrsugh Innevation through Innovation USER MANUAL TriMag Triple Track MagStripe Decoding ASIC 80053501 001 A 12 26 2008 TriMag MagStripe Decode ASIC LIMITED WARRANTY ID TECH warrants to the original purchaser for a period of 12 months from the date of invoice that this product is in good working order and free from defects in material and workmanship under normal use and service ID TECH s obligation under this warranty is limited to at its option replacing repairing or giving credit for any product which has within the warranty period been returned to the factory of origin transportation charges and insurance prepaid and which is after examination disclosed to ID TECH s satisfaction to be thus defective The expense of removal and reinstallation of any item or items of equipment is not included in this warranty No person firm or corporation is authorized to assume for ID TECH any other liabilities in connection with the sales of any product In no event shall ID TECH be liable for any special incidental or consequential damages to purchaser or any third party caused by any defective item of equipment whether that defect is warranted against or not Purchaser s sole and exclusive remedy for defective equipment which does not conform to the requirements of sales is to have such equipment replaced or repaired by ID TECH For limited warranty service during the warranty period please contact ID TECH to obt
9. ading Bit6 This is an Error bit indicating an invalid not recognized command was given Bit7 This is an Out of Order bit indicating a command was given out of order and could not be serviced The Error amp Out of Order bits are cleared immediately after they have been read or after an ATR or a POR event The normal sequence is for the processor SPI Master to read the data blocks in a looping construct polling When all magnetic data is reported in the RAM the magstripe data is transferred from TriMag The Busy amp Empty bits provide the status Bit O Bit 1 Status Description 0 O Data in RAM amp Ready to read 0 1 No data available 1 O Magstripe read in progress 1 1 Same as Magstripe read in progress SPI commands are shown in the table below For all commands the SPI interface logic counts SPCK transitions while nCS signal is low A command counter uses eight clock edges to capture the command word and decode it A transition on nCS resets the count If the implementation has nCS chip select tied low at all times A timeout is provided to reset the command counter The timeout is approximately 64 milliseconds and is active even in sleep mode Activity on the SPI CLK line resets the timeout The SPI supports a dedicated command to flush the RAM All three buffers are erased in one operation This process is clocked by the master system clock and is completed in 2304 cycles plus a few more to
10. ain a Return Material Authorization RMA number amp instructions for returning the product THIS WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES OF MERCHANTABILITY OR FITNESS FOR PARTICULAR PURPOSE THERE ARE NO OTHER WARRANTIES OR GUARANTEES EXPRESS OR IMPLIED OTHER THAN THOSE HEREIN STATED THIS PRODUCT IS SOLD AS IS IN NO EVENT SHALL ID TECH BE LIABLE FOR CLAIMS BASED UPON BREACH OF EXPRESS OR IMPLIED WARRANTY OF NEGLIGENCE OF ANY OTHER DAMAGES WHETHER DIRECT IMMEDIATE FORESEEABLE CONSEQUENTIAL OR SPECIAL OR FOR ANY EXPENSE INCURRED BY REASON OF THE USE OR MISUSE SALE OR FABRICATIONS OF PRODUCTS WHICH DO NOT CONFORM TO THE TERMS AND CONDITIONS OF THE CONTRACT The information contained herein is provided to the user as a convenience While every effort has been made to ensure accuracy ID TECH is not responsible for damages that might occur because of errors or omissions including any loss of profit or other commercial damage nor for any infringements or patents or other rights of third parties that may result from its use The specifications described herein were current at the time of publication but are subject to change at any time without prior notice ID TECH is a registered trademark of International Technologies amp Systems Corporation EzWriter WorkShop and Value through Innovation are trademarks of International Technologies amp Systems Corporation ID TECH 10721 Walker Street Cypress CA 90630 714 761 6368 Copyr
11. e host follows with multiple Continue reading data commands n 1 time Each successive Continue command returns the next byte of data until the last byte After the last byte is received a NoOp command is sent while the LRC is received If an extra continue command is issued the out of order error bit is set but the LRC byte is still received on the n2 cycle Further Continue commands return empty OxFF and the out of order error bit is set If another command is issued during the n2 cycle while the LRC byte shifts out that command is serviced normally If a new status or read command is issued before the data has been completely read the new read process is ignored the error bit is set and data for a sequential read or empty for a byte read is returned as if a NoOp had been issued The exception is that if a status or read command is sent while a header is being sent out no error would be set This is because the host cannot know the header was valid or not and that a read began until it receives the header If this is the case the host issues one fewer NoOp n 1 or Continue n commands to stream out all data EOC and ATR have the same priority This is the second highest priority They can interrupt all other modes Issuing the Reset EOC command ends the read process early without setting the error status bit The Arm to Read ATR commands exits the read erase the memory and returns the SPI to an idle state
12. e used for extended noise or ESD immunity Contact ID TECH Support for additional information Component Nominal Tolerance Value Capacitor Required decoupling capacitor 0 1 20 uF for 3 3V or 5V applications 20 Capacitor Required decoupling only 0 1 20 uF when used in 5V application 20 Head Head Inductance per track 100 30 mH at 1kHz Inductance 60 100uA RMS Head Head DC Resistance per 280 30 Ohms Resistance track Figure 3 External Component Values Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 7 of 18 TriMag MagStripe Decode ASIC 3 0 General Functional Description VDD IO VDD 3V HD1A Track 1 CLK1 HD2A Analog RE DA1 HIB Track 2 re Track CLK2 HD2B Analog Processing DA2 HD1C Track 3 lt _ CLK3 HD2C Analog 9 DA3 MD MISO X X X MSR SPI Test m MOSI Interface PRO SPCK v vv il le RAM SPI Interface Interface gt RAM ncs T GND Figure 4 ASIC Architectural Block Diagram 3 1 General Functional Description Three analog sections process the incoming head signals Each section contains a signal filtering and noise reduction elements Each analog section interfaces to an identical digital section that monitors the amplitude of the recovered analog si
13. emperature Tlead Lead Temperature Tslew Input Slew Rate TSSOP Thin Shrink Small Outline Package V Voltage VDD Supply voltage that corresponds to a logic 1 rail Vil Voltage input low representative of a logic 0 at an input Vih Voltage input high representative of a logic 1 at an input Vol Voltage output low representative of a logic 0 on an output Voh Voltage output high representative of a logic 1 on an output VSS Supply voltage that corresponds to a logic 0 rail Typically OV uA micro Amperes 2 0 Operating Parameters and Conditions The ASIC has two application interface modes The interface mode is selectable One mode is a standard real time MagStripe Reader Data MSRD a k a Clock amp Data interface The other mode is a standard Serial Peripheral Interface SPI interface in slave operation The MSRD interface has seven signals There is a Data output and a corresponding Clock output for each magnetic stripe track input There is a single Media Detect output common to the three decoding circuits The timing of the MSRD mode is shown in the timing diagram There are two selectable clock speeds Clock speed is selected to be the same rate as card data read rate or half of the card data read rate The TriMag can provide data output as an SPI slave mode The SPI interface receives commands from the application and sends buffered magnetic stripe data to the application via the SPI Data Out pin Copyright 2007 Internat
14. gnal and provides AGC settings and bandwidth adjustments The analog sections have sophisticated peak detection for signals representing the recorded data bits Digital circuits delineate the data bit stream and store the bit values in internal RAM storage The TriMag ASIC has two primary data output modes Magnetic Stripe Reader Data MSRD mode and SPI mode In either mode the recovered data is stored RAM and is output through the chosen data interface In MSRD mode data is provided through three traditional Clock amp Data outputs The Clock amp Data information is captured by an external processor A valid level on the Media Detect pin indicates the reading process In SPI mode an external processor communicates with the RAM via the SPI interface to retrieve the decoded track data SPI commands amp status control the interface operation Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 8 of 18 TriMag MagStripe Decode ASIC 3 2 Sleep Mode Function TriMag will automatically enter a power down sleep mode when a magnetic head signal is not present The MagChip will automatically wake up when a magnetic head signal is present The outputs Data Strobe amp Media Detect are at a high level during sleep mode 3 3 MSRD Mode Outputs 3 3 1 Data Output The Data output is a serial stream of digital bits which are the decoded information from the magnetic stripe media card The bit level
15. ie rise pte t pite ele t pater pode t puse pim euen 43 PCB Layout SUGGESHONS iii eiu eo tio Lx ne Ex Ee UN REN LESER epe etie TriMag MagStripe Decode ASIC 1 0 Introduction The TriMag ASIC is a complete three tracks MagStripe data decoder with internal memory and industry standard interfaces TriMag ASIC provides three identical F2F decoding channels TriMag amplifies read head signals and decodes the signal into a digital data format The decoded signal is buffered into internal ASIC memory TriMag has two data output formats Clock amp Data for each track or a full duplex SPI Signal amplitudes from magstripe read heads can range from 3mVpp to 1Vpp the TriMag automatic gain control operates over this range and has a fast adaptation algorithm which compensate for magnetic signal variations caused by magnetic or mechanical stripe damage TriMag easily decodes F2F data rates from 200 to over 42 000 data indices per second translating to media speeds from 3 to 100 inches per second The powerful decoding algorithms compensate for typical decoding problems like dropout skew low amplitude jitter stripe noise and magnetic bias The Clock amp Data outputs are buffered and available at real time data rates or half time data rates The SPI port transfers the buffered data at the SPCK rate TriMag is a fully contained fully functional electronic decoding component The only external component required is decoupling capacitance for power s
16. ight 2007 International Technologies amp Systems Corp All rights reserved Page 2 of 18 TriMag MagStripe Decode ASIC Table of Contents 1 2 Table of Figures Figure 1 Operating Parameters essere 6 Figure 2 Absolute Maximum Ratings sse 7 Figure 3 External Component Values sese 7 Figure 4 ASIC Architectural Block Diagram sess 8 Figure 5 Clock and Data Timing Diagram sess 10 Figure 6 Clock and Data AC Characteristics ssssssssssss 10 Figure 7 SPI Communication Timing Diagram sss 11 Figure 8 SPI Communication Commands List sssssssse 13 Figure 9 ASIC PIn OUE EISE sten RE ie elsi qu Mir E 15 Figure 10 ASIC Package amp Pin Assignment Drawing 16 Figure 11 Schematic Diagram SPI w 3 3V supply 17 Figure 12 Schematic Diagram Clock amp Data w 5V supply 17 Figure 13 PCB layout Recommendation 3 3V operation 18 Figure 14 PCB layout Recommendation 5V operation 18 Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 3 of 18 BO VEFOCU CHO sacs sane nian atra A a Rae ral etd E R ies tcn tun Wl General FOALS CE Mp daved AEA eceteds Cavcinds
17. ional Technologies amp Systems Corp All rights reserved Page 5 of 18 TriMag MagStripe Decode ASIC 2 1 Recommend Operation Conditions TriMag is powered by either a 5V or a 3V volt supply When powered by a 5V supply the VDD O pin is tied to 5V supply and a 0 1uf decoupling capacitor The VDD 3V pin is tied to a 0 1uf decoupling capacitor used for an internal regulator circuit When powered by a 3V supply the VDD IO pin and VDD 53V pin are tied together to the 3V supply and a 0 1uf decupling capacitor See Section 4 for ASIC Pin outs Schematics amp Layout Recommendations Operating ranges define the limits for functional operation and parametric characteristics of the device Note that the functionality of the ASIC outside the operating ranges may cause damage to the device or produce erratic operation Operating outside the recommended operating ranges for extended periods may affect device reliability SYMBOL PARAMETER MIN MAX UNITS NOTES E E lass Standby Current sleep 85 uA 5V mode 4 lass Standby Current sleep 80 uA SVmode 4 Brem T 50 7 GM UN RE REDI RM Dvs jDigtalGrud 0 V T Ambient Temperature 40 85 C T Junction Temperature 40 90 C 5 Figure 1 Operating Parameters Notes 1 TriMag is operated in a single voltage mode either 5V or 3V 2 If 3V mode is used the 5V supply is externally tied to the 3V supp
18. ly 3 Dynamic current is with oscillator running all analog cells out of power down mode and digital cells running a calculation All outputs unloaded All inputs are driven amp not floating 4 Standby current is with the low frequency clock powering the signal detect and wake up circuits All other analog cells are in power down and all other digital logic are powered up with no clocks running All outputs are unloaded and inputs are tied high or low No inputs are floating There is No SPI activity 5 TSSOP Theta J is 118 6 deg C W for single sided board with no ground plane Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 6 of 18 TriMag MagStripe Decode ASIC 2 2 Absolute Maximum Ratings Stresses above those listed in this section may cause immediate device failure PARAMETER MN MAX UNTS _ 5V DC Supply Voltage p sr dp cel qp cWwes 2 3V DC Supply Voltage D 90 37 V e nput Pin Voltage 5V mode VSS 0 3 VDD_5 0 3 V nput Pin Voltage 3V mode VSS 0 3 VDD 3 0 3 V nput Pin Current Storage Temperature 55 a eO 4 Lead Temperature NA 260 C Direct contact ESD V NES Capacitive The parasitic capacitance at p 50 Load outputs driven 19kHz V V V V A C C KV pF Figure 2 Absolute Maximum Ratings 2 3 External Component Parameters These component parameters apply to the minimum ASIC circuit configuration Other components may b
19. n Assignment Drawing The TriMag brand name and a manufacturing data code are printed on the ASIC package TriMag is a RoHS compliant component Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 16 of 18 TriMag MagStripe Decode ASIC 4 2 Schematic Diagrams 3V O VDD IO VDD 3V CLK1 DATA1 CLK2 DATA2 CLK3 DATA3 MD MISO MSRD SPI VDD_IO VDD_3V CLK1 DATA1 CLK2 DATA2 cr MEE er 0000 M coro NNREENEEEENE HEAD 2B CLK3 DATA3 MD MISO PRO SPCK HEAD 3A HEAD 3B CH GND MOSI nCS MSRD SPI Figure 12 Schematic Diagram Clock amp Data w 5V supply Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 17 of 18 TriMag MagStripe Decode ASIC 4 3 PCB Layout Suggestions The PCB layout should keep the head input signals lines as short as possible and separated from the digital outputs to minimize external noise pick up and digital to analog cross talk Pin 1 is denoted with a dot in the package corner next to pin 1 Figure 13 PCB layout Recommendation 3 3V operation Figure 14 PCB layout Recommendation 5V operation Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 18 of 18
20. ta output width is doubled when PRO control pin is connected to power supply common This feature allows for slower data acquisition timing for low speed microprocessors Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 10 of 18 TriMag MagStripe Decode ASIC 3 4 SPI Mode Operation amp Outputs The SPI operation implements a common SPI slave only interface Although there are many permutations of SPI the TriMag offers only a single communication format This format is the most common Its characteristics are as follows Input data is latched on the rising edge of the serial clock Output data is shifted out on the falling edge of the serial clock SPI is enabled when nCS is low Output data is tri stated when SPI is not enabled nCS is high The maximum SPI clock rate is less than 500 kHz ensuring memory reads have sufficient time to complete for back to back SPI reads These relationships are shown below for a simple 8 bit command followed by an 8 bit response V V MOSI MSB A i A LSB j MISO MSB LsB Figure 7 SPI Communication Timing Diagram 3 4 1 Static RAM Buffer Decoded data is buffer in a single 2304 x 1 single port static RAM The RAM is used as three 768 bit buffers One buffer is used for each MagStripe track Data from the Track 1 head input is saved in locations 0x000 through 0x2FF data from the track 2
21. upply input s 1 1 General Features State of the art mixed signal Application Specific IC ASIC Compact standard IC package TSSOP 20 pin Simultaneously decodes and buffers three magnetic stripe tracks Easily decodes standard 75 amp 210 BPI decoding for used cards Reads data from card swipe speeds from 3 to 100 IPS Supports two power supply voltages 3 0V to 3 6V or 4 5V to 5 5V Operating temperature range from 40 C to 85 C Low power sleep mode current 80p4A with 3V supply Low power operation during read decoding lt 3mA Two options for card data output are provided SPI or individual Clock amp Data Card Present or SPI Status Byte for indication of MagStripe data Automated internal head compensation to support most head types Automatic Gain Control for magnetic signal range from 3mV to 1V Simple to integrate amp cost effective decoding solution High immunity to ambient noise and electrostatic discharge Copyright 2007 International Technologies amp Systems Corp All rights reserved Page 4 of 18 TriMag MagStripe Decode ASIC 1 2 Abbreviations AGC Automatic Gain Control ESD Electrostatic Discharge mA milli Amperes MISO SPI Master in Slave Out data line MOSI SPI Master Out Slave In data line MSRD MagStripe Reader Data PCB Printed Circuit Board RAM Random Access Memory SPCK SPI Clock signal line SPI Serial Peripheral interface Ta Ambient Temperature Tj Junction Temperature Tjmax Maximum Junction T
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