FIPSOC User Manual
Contents
1. Fig 1 1 Block Diagram of the Interrupt System 1 1 8051 Interrupt Service Routine The mP8051 provides five interrupt sources with two priority levels as shown in figure 1 2 v The 8051 external interrupts can each be either level activated or transition activated depending on bits ITO and ITI in register TCON The flags that actually generate these interrupts are bits IEO and IE1 of TCON The interrupt flag is cleared a by the hardware when the service routine is vectored to only if the interrupt was transition activated b by the external requesting source which controls the request flag if the interrupt was level activated rogram Address Bus lt a S ID S A Semiconductor Design Solutions v Timer0 and Timerl interrupts are generated by The interrupt sources are described in table 1 1 Note bits TFO and TF1 which are set by the rollover in that one of the sources can only interrupt thshare the their respective timer counter registers The same interrupt interrupt flag is cleared by the on chip hardware when the service routine is vectored to Source Description Serial Communication Block Interrupt mw INTO A i f Programmable Hardware interrupt 5 CABint End of Conversion of the ADCs v The Serial Port Interrupt is generated by the logical OR of RI and TI Neither of these flags is cleared by hardware when the service routine is vectored to D gt o 22. Name Byte VDBG B4 VDBGL B5 VDBGH Description DEBUG Interrupt Vector Pseudovector used when extended interrupt mode is enabled INTM 1 external interrupt and DBGint are enabled and a memory location is debbuged a breakpoint is reached DBG Interrupt Vector Low Byte DBG Interrupt Vector High Byte Programmable Hardware Reset vector 3 h0000 after Address B7 B6 Name Byte VHW3 B6 VHW3L B7 VHW3H Description HW3 Interrupt Vector Pseudovector used when extended interrupt mode is enabled INTM 1 external interrupt and HW3int are enabled and an Interrupt from the Plblock happens through HWS3INT input HW3 Interrupt Vector Low Byte HW3 Interrupt Vector High Byte Address CO Name EIMRO Bit EIMRO 7 EIMR0 6 EIMRO0 5 EIMR0 4 EIMR0 3 EIMRO 2 EIMRO 1 EIMRO0 0 Description Extended Interrupt Mask Register for External Interrupt 0 A 0 means that the corresponding source is masked Enable or Disable PLL interrupt through IXO HW1 COM interrupt through External Int 0 if 1 HW1 is selected Enable or Disable CLK interrupt through External Int 0 Enable or Disable HW2 interrupt through External Int 0 Enable or Disable DBG interrupt through External Int 0 Enable or Disable HW3 interrupt through External Int 0 Enable or Disable HW4 interrupt through External Int 0 Enable or Disable ANA interrupt through External Int 0 Extended I
3. system of the 8051 see Microprocessor Document v EIC Registers used to control this block The registers are two mask and two polarity registers one pair for each channel used to control each interrupt source signal and the Interrupt Status Register from which information is obtained v Interrupt related Registers included in the different subsystems of the FIPSOC These registers are explained in their corresponding Documents Configurable Analog Block Document Software Debugging Block Document Clock Generation Block Document and PL Block Document The SFR used to control the External Interrupt Controller Block are described below PLL Interrupt Vector hO000 after Reset Semiconductor Design Solutions Register 3 h02 after Reset System Control 12x8 device Address Name Bit 9B RG3 RG3 7 RG3 6 RG3 5 RG3 4 RG3 3 INTM RG3 2 CM1 RG3 1 CMO RG3 0 Description System Control Register 3 Interrupt mode If 1 extended interrupt vectors mode is entered if 0 basic 8051 interrupt mode is selected External Memory Compatible map bit 1 External Memory Compatible map bit 0 Programmable Hardware vector I h0000 after Reset Address Name Byte Description A7 A6 VHW1 HW Interrupt Vector 1 A6 VHWIL A7 VHW1H Pseudovector used when extended interrupt mode is enabled INTM 1 external interrupt is enabled and a HWlint are enabled and an Interrupt from the PLblock happens o
4. S B S 3 al ie 2 A 8 TFO gt Table 1 1 Interrupt Sources Each interrupt signal is connected to the internal n ea gt El gt channels of the External Interrupt Controller Block E t L The output of these channels is connected to the external interrupt inputs INTO and INT1 of the TFO gt mP8051 RI gt All the signals may be independently inverted and y Tl Se masked in each channel A priority circuitry is provided to solve simultaneous request conflicts Fig 1 2 mP8051 Interrupt Sources between different sources Figure 1 3 schematically All the bits that generate interrupts can be set or shows the block diagram of the External Interrupt Controller cleared by software with the same result as though it had been set or cleared by hardware Each of these interrupt sources may be individually SNU IMRO enabled or disabled The 8051 also provides a global 5 disable bit which disables all interrupts at once COM INT E u anma Channel 0 Each interrupt source can also be individually PLL INT gt gt j E programmed to one of two priori
5. ZG SIDSA Chapter 6 External Interrupts Controller FIPSOC User s Manual SIDSA Semiconductor Design Solutions External Interrupts Controller Overview The Field Programmable System On Chip FIPSOC constitutes a new concept in system integration It provides the user with the possibility of integrating a microprocessor core along with programmable digital and analog cells within the same integrated circuit This chip can be considered as a large granularity FPGA with a FPAA Field Programmable Analog Array and a built in microprocessor core that does not only act as a general purpose processing element but also configures the programmable cells and their interconnections Therefore there is a strong interaction between hardware and software as long as signal values and configuration data within the programmable cells are accessible from microprocessor programs This chapter describes the interrupt controller added to the external interrupts service circuitry of the built in 8051 This block is used to extend the two available external interrupt sources in the standard mP8051 to all the on chip subsystems of the FIPSOC Thus a full interrupt service interface has been customized and integrated in the FIPSOC chip The control logic for each external interrupt input is duplicated so the same interrupt sources are available for each input Masks are different for each duplicated input and in fact this is a convenient
6. al InterruptO 0003 FF03 XX15 XX18 LCALL 0003 0003 LIMP VANA XX20 LCALL 0003 0003 LIMP VHW1 ANAINT Table 4 1 Interrupt vectors table 4 2 Extended Mode Same table as the basic mode interrupt vector table is used in the extended mode When an external interrupt flag is set and the hardware LCALL jumps to the routine address 0004 and 0013 for flags IEO and IE1 respectively a HW LJMP instruction is executed The address field of the instruction depends on the source of the interrupt see figure3 1 Values from the SFR map are used as shown in Table 4 2 Note that the same vectors are used in both external interrupts DBG INT HW1 INT Interrupts arrived XX21 LCALL 0003 0003 LIMP VDBG XX23 XX26 Polling sequence selection RETI RETI Execution time Figure 3 1 Interrupt registering in the extended mode b When an external interrupt is generated the flag that generated it and the flag bit in the Temporal Status Register of the corresponding channel of the EIC block are cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated Note that the clearing action updates the Temporal Status Registers not to the Interrupt Status Register ISR Chapter 6 External Interrupts Controller 7 SIDSA Semiconductor Design Solutions If the interrupt system is working on the extended mode only one routi
7. ce is set The level are used see table 4 3 Note that if the Auxiliary Memory is enabled a user definable vector table is obtained These vectors can be dynamically modified because Auxiliary Memory can be mapped in both program and data memories Interrupt Input vector 0003 SEFO3 000B FFOB 0013 SFFI3 TF1 001B FF1B 0023 FF23 Table 4 3 On chip ROM Interrupt Table activated configuration is set with ITO 0 See Software Debugging Document for further information Chapter 6 External Interrupts Controller 8
8. ed The 8051 core can be externally interrupted by one of the nine new interrupt sources through any of the external interrupt inputs that is hardware for both interrupt inputs has been duplicated to provide higher flexibility Chapter 6 External Interrupts Controller 3 Finally an enhanced mode is provided from the External Interrupt Controller Block This mode supports multiple interrupt vectors for the 8051 external interrupt sources That is only one interrupt vector each external interrupt input is provided by the on circuitry when the interrupt routine is called If the enhanced mode is disabled the programmer would have to identify which of the nine new sources has caused the interrupt This mode is called normal or basic mode In the enhanced mode a user definable vector table is provided located in the SFR map of the 8051 and no action from the programmer is needed since the interface selects the corresponding vector This operation is totally transparent to the mP8051 as long as the register is multiplexed via hardware The corresponding flag in the Interrupt Status Register is also cleared when the service routine is vectored to only if the interrupt was transition activated 2 EIC Block Registers The Global Interrupt system of the FIPSOC is controlled using registers located in the SFR map These registers can be divided into three groups v Original 8051 registers used to control the on core interrupt
9. een added to the SFR map When the processor acknowledges an interrupt request hardware LCALL to the appropriate servicing routine will be executed on the next instruction The start address of the routine which is going to be vectored to depends on the source of the interrupt and it will be internally chosen Addresses execution XX14 Semiconductor Design Solutions 4 Interrupt Routine Vectors The interrupt flags are sampled at S5P2 of every machine cycle The samples are polled during the following machine cycle If one of the flags was in a set condition at S5P2 of the preceding cycle the polling cycle will find it and the interrupt system will generate a hardware LCALL to the appropriate service routine The address field of the instruction is hardware generated and its value depends on the source of the interrupt As mentioned before a different vector table is used depending on the selected mode 4 1 Basic Mode The routines of the five interrupt sources of the 8051 occupy the lowest locations of the Program Memory Execution proceeds from the location determined by the vector until the RETI instruction is encountered Table 4 1 shows the vector table used in the basic mode The Internal ROM includes a LJMP to FFXX instructions in each vector address These instructions point to the auxiliary memory where users may define their interrupt routine Interrupt Input vector request flag Interrupt Source Extern
10. external interrupt x is edge triggered in this mode if successive samples of the INTx input show a high in one cycle and a low in the next cycle interrupt request flag IE x in TCON register is set Flag bit IE x then requests the interrupt v If various external sources interrupt simultaneously the EIC block will register them Each time one of the request interrupts is acknowledged the EIC block sets the corresponding JE x flag until all of the interrupts arrived were serviced see figure 3 1 Y Besides the EIC Interrupt Status Registers also status registers from other blocks must be correctly reinitialized if the interrupt system is to be used Programmers would handle carefully The 8051 of the FIPSOC is provided with two different operating modes Bit 2 of the RG3 SFR 9B selects the active mode normal or basic mode SIDSA is selected if RG3 2 0 extended mode is entered by setting this bit This modes affects how the interrupt service routine is vectored to In particular 3 1 Basic Mode RG3 2 0 a Only one vector register for each channel external inputs is provided Programmer would decode by software which of the external subsystem has interrupted b When an external interrupt is generated the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated 3 2 Extended Mode RG3 2 1 a Eight vector registers have b
11. ne location is possible there exists a dedicated hardware to execute the LJMP using SFR vectors Interrupt request Input vector flag of ISR Interrupt Source ICLK Clock stop VCLK See Microprocessor Document for further information THW3 Programmable HW 3 VHW3 THW4 Programmable HW 4 VHW4 End of Conversion VANA REG gt value stored in REG regsiter 5 Step by step Execution The 8051 interrupt system allows step by step execution with very little software overhead Once an interrupt routine has been entered it cannot be re entered until at least one instruction of the interrupted program is executed Table 4 2 Extended Interrupt vectors table The first LCALL instruction is done to locations of the Program Memory Different routines may be accessed depending on the portion of the program memory enabled That is three different destination routines can be called on chip ROM external program memory and Regular Configuration memory mapped in the program memory The on chip ROM has stored another LJMP instructions in all the routines New pseudovectors One way to use this feature for step by step operation is setting one of the two external interrupts to be level activated and a continuous active level high or low level depending on the SGNx bit in its input The continuous active level is set by manipulating the SFR E2 If bit 7 in this register is set to 1 a high level in the DBG interrupt sour
12. nterrupt Mask Register 1 h00 after Reset Programmable Hardware Reset vector 4 h0000 after Address BD BC Name Byte VHW4 BC VHW4L BD VHW4H Description HW4 Interrupt Vector Pseudovector used when extended interrupt mode is enabled external interrupt and HW4int are enabled and an Interrupt from the PLblock happens through HW4INT input HW4 Interrupt Vector Low Byte HW4 Interrupt Vector High Byte End of Conversion Interrupt Vector h0000 after Reset Address BF BE Name Byte VANA BE VANAL BF VANAH Description Analog Interrupt Vector Pseudovector used when extended interrupt mode is enabled INTM 1 external interrupt and analog inerrupt enabled and an A D conversion is finished Analog Interrupt Vector Low Byte Analog Interrupt Vector High Byte Address C1 Name EIMR1 Bit EIMR1 7 EIMR1 6 EIMR1 5 EIMR1 4 EIMR1 3 EIMR1 2 EIMRI1 1 EIMR1 0 Description Extended Interrupt Mask Register for External Interrupt 1 A 0 means that the corresponding source is masked Enable or Disable PLL interrupt through External Int 1 Enable or Disable HW1 interrupt through External Int 1 Enable or Disable CLK interrupt through External Int 1 Enable or Disable HW2 interrupt through External Int 1 Enable or Disable DBG interrupt through External Int 1 Enable or Disable HW3 interrupt through External Int 1 Enable or Disable HW4 interr
13. r b HWlint is disabled BOOTint is enabled and an the communication system produce HW1 Interrupt Vector Low Byte HW1 Interrupt Vector High Byte Clock Interrupt Vector hO000 after Reset Address Name Byte Description A5 A4 VPLL PLL Interrupt Vector Pseudovector used when extended interrupt mode is enabled INTM 1 external interrupt and PLLint are enabled and an Interrupt from PLL happens A4 VPLLL PLL Interrupt Vector Low Byte A5 VPLLH PLL Interrupt Vector High Byte Address Name Byte Description AD AC VCLK CLK Interrupt Vector Pseudovector used when extended interrupt mode is enabled INTM 1 external interrupt and CLKint are enabled and clocks are frozen either by software or hardware AC VCLKL CLK Interrupt Vector Low Byte AD VCLKH CLK Interrupt Vector High Byte Programmable Hardware vector 2 h0000 after Reset Address Name Byte Description AF AE VHW2 HW2 Interrupt Vector AE VHW2L AF VHW2H Pseudovector used when extended interrupt mode is enabled INTM 1 external interrupt and HW2int are enabled and an Interrupt from the PLblock happens through HW2 INT input HW2 Interrupt Vector Low Byte HW2 Interrupt Vector High Byte Chapter 6 External Interrupts Controller SIDSA SW Breakpoints Interrupt Vector h0000 after Reset Semiconductor Design Solutions Extended Interrupt Mask Register 0 h00 after Reset Address B5 B4
14. rupt system and the EIC 8051 system of the FIPSOC Each of the interrupt sources can be individually enabled or disabled by setting or clearing the corresponding bit v JE Register SFR A8 enables or disables the five original interrupt sources of the 8051 INTO INTI TFO TFI and RI TD by setting or clearing its corresponding bit respectively v Extended interrupt sources can be enabled or disabled writing on the corresponding bit of EIMRO and EIMRI masks registers SFR C0 and SFR C1 Not that bits IE O and IE 2 are used as a global disable for both channel 0 INTO and channel 1 INTI respectively v There is an special bit in EJMRO EIMRO 6 used as a selecting bit instead of a masking bit If this bit is set Programmable Hardware Interrupt 1 is selected otherwise Serial Communication Block Interrupt is enabled v JE register contains a global disable bit IE 7 which disables all interrupts at once v Note that each subsystem interrupt signal may be programmed to be connected to both channels Due to this flexibility it is strongly recommended not to enable the same interrupt source in both channels Each of the original interrupt sources can also be individually programmed to one of two priority levels low and high by setting or clearing a bit in ZP register SFR B8 v Note that the priority of the external interrupts sources of the 8051 INTO and INTI is propagated to the non masked extended inp
15. ty levels by setting HW1 gt 3 gt p INTO or clearing a bit on the register located in B8 of the CK INT gt 3l SFR map A lower priority interrupt can itself be HW2 y interrupted by a higher priority interrupt but no t by Deant S L L DE a lower priority interrupt If request of the same Gi N gt priority level are received simultaneously an internal DWA a 5 INT 1 polling sequence determines which request is 3 serviced see Microprocessor Document for further ee K TSR1 zy information Channel 1 1 2 External Interrupts ial ne Controller Fig 1 3 Block Diagram of the EIC Block Both channels of the EIC Block are independently controlled they have separate registers mask and polarity registers are duplicated Only the Interrupt Status Register is not available on each channel since this register is the logical OR of the Temporal Status Register TSRO and TSRI of the channels as depicted from figure 1 3 An interrupt controller block to complement the interrupt system of the built in 8051 has been inergrated This controller expands to nine the number of interrupt sources connected to the interrupt system Therefor different subsystems would be able to request a hardware interrupt in the microprocessor Signal HW1 in channel 0 has a double function if its corresponding bit in the mask register is set the Programmable Hardware Interrupt 1 is selected otherwise Serial Communication Block Interrupt is select
16. upt through External Int 1 Enable or Disable ANA interrupt through External Int 1 Polarity Register 0 h00 after Reset Chapter 6 External Interrupts Controller Address C2 Name SGNIO Byte Description Inverting extended external Interrupts through Ext Int 0 For each bit of this register if 1 inverts the corresponding interrupt input high level or rising edge interrupts Polarity Register I h00 after Reset Address C3 Name SGNIL Byte Description Inverting extended external Interrupts through Ext Int 1 For each bit of this register if 1 inverts the corresponding interrupt input high level or rising edge interrupts SIDSA Extended Interrupt Status Register h00 after Reset Address Name Bit Description C4 IRS Extended Interrupt Status Register Each bit is set by HW when the corresponding interrupt occurs and also cleared by HW when IRS is read see later in the text IPLL ISR 7 PLL Interrupt flag IHW1 ISR 6 HW 1 Interrupt flag ICLK ISR 5 Clock Stop Interrupt flag IHW2 ISR 4 HW2 Interrupt flag THW3 ISR 3 HW3 Interrupt flag IDBG ISR 2 SW Breakpoints Interrupt flag THW4 ISR 1 HW4 Interrupt flag IANA ISR O Analog Interrupt flag 3 Programming the EIC Block This section will describe how the external interrupts INTO and INTI of the 8051 core may be programmed There are not big differences between programming the original inter
17. uts Chapter 6 External Interrupts Controller Semiconductor Design Solutions that is PLL interrupt Hardware sources etc of the corresponding channel in the EJC Block Vv A low priority interrupt can itself be interrupted by a high priority interrupt v A high priority interrupt cannot be interrupted by any other interrupt source Even more no interrupt source can be interrupted by any other source within level v If two requests of the same priority level are received simultaneously an internal polling sequence determines which request is serviced see figure 1 2 and Table 1 1 External Interrupt sources in the on chip 8051 can only interrupt if a low level or a 1 to 0 transition is entered depending on the configuration of bits ITO and IT1 of TCON SFR 88 Two new registers have been added to the SFR map of the 8051 core of the FIPSOC to configure the polarity of the incoming interrupt signal Each interrupt input of both channels of the External Interrupt Controller Block can be individually inverted clearing the corresponding bit of SGNIO and SGNII SFR C2 and SFR C3 Table 3 1 shows this configuration SGNII i IT1 TCON 1 o o mawa ai f o f oa o n omiri Table 3 1 Interrupt triggering condition When an interrupt is produced the JSR register set the corresponding bit If the conditions are right for it the IE x flag of SFR 88 will be set during the polling cycle v If IT x 1
18. way to specify relative priorities between two interrupt sources There are nine interrupt sources independently masked for each interrupt input Each one may be inverted so both low and high levels and rising and falling transitions are allowed Multiple interrupt vectors are also supported In normal operation the interrupt vector is unique for each one of the two external interrupt inputs The External Interrupt Controller EIC block provides an enhanced multiple interrupt vector mode which selects the interrupt vector from a user defined table of registers Chapter 6 External Interrupts Controller 1 Interrupt System Description The interrupts service system of the on chip core of the 8051 keeps the same interrupt requesting system of the original 8051 even though there has been integrated an external interrupt controller to expand the limit of two external interrupt sources allowed by the original 8051 see figure 1 1 These sources may be grouped into two e Interrupts generated by the on chip subsystems e Custom interrupts generated in the Programmable Logic Block g a g PL Block cae a ss 8 SS 1S Programmable Hardware Interrupts 1 4 3 SoS E W i RESTA End of Conversion A 5 5 PLL stabilization n EIC Stop Interrupt A Clock Block Generation m aa Block N i BR INTO INTI z 2 Y Es aes a SES Serial S gt Comm a Block
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