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MIDAS USER`s MANUAL

1. PCI CONNECTORS PMC I PXB _ P2 1 0 CONNECTOR Not R option o A 1 22 INTERRUPT RACEway FLASH JUMPERS JUMPERS JUMPERS Figure 5 MIDAS Board Layout No model has all parts mounted Installation of PMC Modules The MIDAS 15 shipped with two PMC filler panels mounted in the front panel They act as EMC shielding in unused PMC positions Before installing a PMC module the filler panel s must be removed This is done by pushing them out from the backside of the front panel Four screws must be used to secure each PMC on the MIDAS board 8 e Installation MIDAS USER s MANUAL Note extremely careful when inserting screws to secure modules Touching component leads or the printed circuit board itself with a screwdriver may cause permanent damage to the board Assembly Procedure for MIDAS x50 STEP 1 STEP 2 The MIDAS x50 is a dual slot VMEbus board that mates the back plane connectors in two neighbor slots The MIDAS x50 module can handle the insertion and extraction forces applied when installing or removing it from the backplane However this requires that the assembly procedure described in this section be followed WARNING The MIDAS x50 boards may be destroyed during insertion or extraction from a VMEbus system if this procedure is not followed Dismount MEZZ
2. 5 B of JP1 DOWN VME Register Access Image DISABLED gt gt 5 5 JP1 UP VME Register Access Image ENABLED lt KI 0 E VME Register Access Image ADDRESS SIZE The VME Register Access Image can accept A16 A24 or A32 AM codes depending on the positioning of SIZE jumpers JP2 amp At power up this slave image accepts AM codes for Supervisor User Data and Code Jumpers Function JP2 UP UP VME Register Access Image A24 ER o JP2 DOWN DOWN VME Register Access Image A32 SO e JP2 UP DOWN VME Register Access Image A16 VME Register Access BASE ADDRESS The DIPswitch is used to define the base address for the VME Register Access Image The size of this image is fixed to 4KB MIDAS USER s MANUAL Functional Description e 21 BASE ADDRESS VRAI EX 24 16 12 me NA From switch 4 From switch 4 MSB M Table 4 VRAI Base Address Definition Net Bed CSR BASE 2 Most significant bit MSB ee r 1 i 7 7 8 72 DOWN 0 UP 1 Figure 13 Switch Details Shown switch value 0x61 VME64 Auto Slot ID ENABLE DISABLE By using new address space for CR CSR accesses the VME64 specification defines a method for implementing Plug amp Play on the VMEbus called Auto S
3. sINTD sINTC sINTB sINTA Universe UARTI W gt UART2 9 PxB INTERRUPT 7 9 1 E y B ROUTER PLD gt i 2 09 PINT1A D i960 RP 2 i0 i0 i960 RP 1 il il i2 i2 i3 i3 i4 lt a TTS 15 4 gt i5 i6 4 gt i6 i7 gt i7 Interrupt Mode Selection Interrupt mode is selected by i960 RD 1 through two register bits in its UART MIDAS USER s MANUAL Functional Description 29 Register Name MCR Address 0xDF00 0004 Function Description Name Type Reset Function State INT MODE R W Interrupt Mode 00 Interrupt Mode 0 01 Interrupt Mode 1 10 Interrupt Mode 2 Table 10 Interrupt Mode Selection Interrupt Jumpers Currently these jumpers are only used for MIDAS xxxR boards to control whether the PCI RACEway bridge should be treated as an interrupt source or a destination Jumpers Function JP15 3 IN OUT PXB Treated as interrupt destination wo 5 5 Other combinations Treated interrupt source 0 This jumper setting must be used if a MIDAS board with RACEway R option is plugged into a non RACEway slot Interrupt Routing Tables The tables below show how the interrupts are routed for the three defin
4. MIDAS USER s MANUAL Description Reset Function State UNAL R W Unaligned 1 unaligned 0 aligned For most normal operations aligned operation is used NAL R W No auto load Used to control if the PCI mask registers are auto loaded for each RACEway to PCI transaction Should always be 0 for secondary PXBs PPAGE Primary Page Read only Table 32 PXB Misc Register X Side Register Descriptions X side Internal Registers Offset MailBox Write 400 Generate Clear Interrupts 408 MISCON 410 Force Test Increment test only 418 Interrupt Mask Load Status Read 420 1 MIDAS USER s MANUAL Appendix 11 PXB Information e 51 Table 33 PXB X side CSR Registers Miscellaneous PXB Information Configuration Serial EEPROM In typical P2P applications the configuration PROM is normally used only by the primary PXB Secondary PXBs are set up from the host using config cycles type 1 through the primary PXB 52 Appendix PXB Information MIDAS USER s MANUAL embedded application using a fixed predetermined address map where no off the shelf POST initialization code is running all PXBs may be initialized almost completely from the configuration PROM The only bit field which must be set is the Routes to Primary bit in the Miscon register 0 410 e All configuration registers inside the may be initialized from either si
5. MEZZ x50 PMC MODULE 5 PMC MODULE 4 PMC MODULE 3 1 52 1 M42 432 en H DECchip 21052 BB N51 452 nt MODULE 2 PMC MODULE 1 Figure 6 Steps 2 amp 3 Mount PMC modules on the MEZZ x50 and MIDAS x20 boards Q Note Before proceeding make sure the switch and jumper settings of the MIDAS x20 board are set according to the needs of your application 10 e Installation MIDAS USER s MANUAL STEP 4 Mount MEZZ x50 with PMC modules on the MIDAS x20 board Ifthe SPACER x50 board and the five metal spacers are not already mounted on the bottom side of the MEZZ x50 board do it now Place the MIDAS x20 board on a smooth static protected work surface Carefully position the MEZZ x50 board over the MIDAS x20 so that the three connectors on the bottom side of the spacer are aligned with the connectors J50 J51 and J52 on the MIDAS x20 Make sure that none of the five metal spacers mounted on the MEZZ x50 board touch components or component leads
6. 000 Adaptive Route F first Example Route entry 0xFACx xxxA is used to route transfer through 4 crossbars ports A B C and D with splitable bit set and priority 01 BigMem Enables addition of high order address bits when addressing RACEway from PCI Not to be used for P2P operation Split Disable A 1 disables split transactions on RACEway Split should always be enabled Priority Two bit priority code Ref RACEway specification Note Never use 11b as priority for I O space Broadcast Set for broadcast operations on RACEway In broadcast mode the meaning of route codes change Ref RACEway specification Requires split disabled and no BigMem Table 34 PXB Route Format PXB Return Route Format Function Big Address 54 e Appendix 11 PXB Information MIDAS USER s MANUAL PXB Return Route Description Return Routes Concatenated three bit route codes used in the response of split RACEway transactions one three bit field per hop Return Route codes 111 2 Port A 110 Port B 101 Port C 100 Port D 011 Port E 010 Port 001 Adaptive Route E first 000 Adaptive Route F first If Split Disable in the route is set the return route is not used BigAddress In BigMem Mode a number of bits number is depending on prefetchable memory window size from this field replaces the most significant address bits when going from PCI into RACEway Bit 0 of this field replaces the least s
7. MIDAS USER s MANUAL Appendix I I O Routing 35 Appendix Il Universe Il Configuration Examples General Information Note that the Universe PCI VME Bridge performs byte swapping of the data lanes on all transactions between VMEbus and PCI bus This is also the case for accesses to the internal registers The internal register bank is located on the PCI side of the byte swapping This means that when registers are read or written from the VMEbus all bytes are shuffled compared to the bit numbering used in the Universe II User Manual VMEbus Slave Images PCI Master Enable In addition to the configuration registers for the VMEbus slave images one control register bit is essential for mapping VMEbus cycles to PCI bus cycles through the Universe The PCI master enable bit located in the PCI CSR register space offset 0x004 This bit 1s set as default after power up Some VMEbus Slave Image examples are shown in Figure 14 36 Appendix Il Universe Configuration Examples MIDAS USER s MANUAL VMEbus PCI bus UNIVERSE II 0 000000 VMEbus A24 all VME Register codes Access Image 0x000FFF 0x0000 VMEbus A16 supervisor VME SI AM codes 20 magg gt PCI bus Config Space 0x4FFF 0x100000 0x02100000 VMEbus A24 all codes No write posting or read prefetching PCI Slave Image gt PCI bus I O Space Lock of VMEbus RMW
8. on the MIDAS x20 in the process Push the MEZZ x50 board down so that all connectors mate completely v9 op 8i F 4 7 1 nmm 052 PMC MODULE 5 H Ust 152 al Le PMC MODULE 4 l PMC MODULE 3 Figure 7 Step 4 Mount the MEZZ x50 with PMC modules on the MIDAS x20 board STEP 5 Mount and fasten screws to all metal spacers on the back of the MIDAS x20 board Take the 5 screws removed in step 1 of this procedure and mount them on the back side of the MIDAS x20 board through the holes which mate the 5 metal spacers on the MEZZ x50 Fasten all five screws with a suitable screwdriver Verify that the screws attaching the metal spacers to the MEZZ x50 are also fastened screws holding the five metal spacers on both boards must be firmly fastened in order to make the MIDAS x50 mechanically stable MIDAS USER s MANUAL Installation e 11 Installation VMEbus System Slot selection The MIDAS can be installed in any slot in a GU VMEbus chassis as long as the daisy chains for the bus grant and interrupt acknowledge signals are continuous from slot 1 to the slot in which the MIDAS is installed Installation into slot 1 of
9. 1 enabled 0x3FFFFF 0x023FFFFF 0x4000 0000 0x6000 0000 VMEbus A32 all codes Write posting and Slave Image gt PCI bus Memory Space read prefetching enabled 2 0x7FFF FFFF 0x9FFF FFFF VME Slave Image 3 not used Figure 14 Configuration Example for VMEbus Slave Images VMEbus Register Access Image In this configuration example the VMEbus Register Access Image is set up by use of the DIPswitch and jumpers MIDAS USER s MANUAL Appendix II Universe Configuration Examples 37 Locate JP1 in its upper position VME RAI is enabled Locate JP2 amp 3 in their upper positions VME RAI is mapped A24 address space Set the DIP switch with all switches VME RAI base address is set to pointing down 0x000000 Locate 1 4 in its lower position Disable Auto slot ID protocol Table 11 VME RAI Setup With the jumper settings described above the Universe II will power up in a state where VMEbus accesses with A24 AM codes in the address range 0x0 OxFFF will map into Universe registers The VME RAI will be utilized to set up the VMEbus slave images described below VMEbus Slave Image 0 In this configuration example the VMEbus Slave Image 0 is set up to map A16 supervisory accesses in the address range 0x0 0x4FFF from VMEbus to Configuration Cycles on the PCI bus Write from PCI Data Base Address set to 0000000 Bound Address set to 0s005000 D 0x0000 0000 to A 0x0
10. 132 Mbytes sec The PCI to PCI bridge provides a connection path between two independent 32 bit PCI buses and provides the ability to overcome PCI electrical loading limits The addition of the 1960 core processor brings intelligence to the PCI bus bridge Local Memory SS EET Memory Controller 80960 Processor 80960 Local Bus Processor CS Processor to PCI Address DMA Address Translation Unit 5 Translation Unit P Direct Transfer Indirect Transfer Direct Transfer S E C 0 A PCI to Memory PCI to Memory R 5 DMA Access 10 Primary P Access to Secondary a P C PCI to PCI Bridge 8 U 6 M Figure 3 i960 RD Data Flow MIDAS USER s MANUAL Product Overview e 5 The 1960 RD processor is a multi function PCI device Function 0 is the PCI to PCI bridge Function 1 is the Address Translation Unit The 1960 RD processor contains PCI configuration space which is accessible through the primary PCI bus This multi function PCI device is fully compliant with the PCI Local Bus Specification Revision 2 1 Universe 1 PCI VMEbus Bridge The Universe II is a second generation high performance VMEbus to PCI bridge manufactured by Tundra Semiconductor It features Fully compliant 33 MHz PCI local bus interface e Fully compliant high performance 64 bit VMEbus interface e Integral FIFOs for write posting to maximize bandwid
11. 2 2 i960 RD 1 Device 0 PXB PCI RACEwa VME PCI BRIDGE Table 6 Primary PCI Bus Arbiter RD 1 MIDAS 100 Series with RACEway Interface For MIDAS models with RACEway interface and with only one or none i960 RDs the PCI bus arbitration unit in the PXB is responsible for arbitration on the primary PCI bus This arbiter is programmable and uses a round robin arbitration scheme with two priority levels 26 e Functional Description MIDAS USER s MANUAL Assignments to Arbiter Req Gnt Pairs PCI DEVICE Req Gnt Pairs PMC 1 Req1 Gnt1 PMC 2 Req2 Gnt2 i9609RD 1 Reg4 Gnt4 VME PCI BRIDGE Req3 Gnt3 Table 7 Primary PCI Bus Arbiter PXB Other MIDAS 1x0 Models For MIDAS 120 and 150 models without RACEway interface the arbiter for the primary PCI bus is implemented in a PLD This arbiter uses a single level round robin arbitration scheme IDSEL Generation PCI bus uses a separate address space for initialization called Configuration Space This address space uses a geographic addressing signal IDSEL to select target for all transactions The standard way of assigning IDSEL to PCI devices amp boards is to connect the IDSEL pin of each device board to a unique AD bit This is also how IDSEL is generated on MIDAS amp shows IDSEL assignments PCI DEVICE BOARD IDSEL PCI ADDRESS FOR VME BASE ADDRESS CONFIG CYCLE FOR PCI CONFIG CYCLE PMC 1 pAD 16 0 00010 0 222800
12. 7F 23 27 Length of ROM to be checksummed NMSB Length of ROM to be checksummed LSB CR Data access width 0x81 D08 EO every forth byte CSR Data access width 0x81 DO8 EO every forth byte NN 27 24 bit IEEE Assigned Manufacturers ID 2B 60 0x006046 VMETRO 00 Board ID VMETRO Assigned 37 00 0x00020020 MIDAS 20R 50R 0 00000120 MIDAS 120xx 150xx 0 00000220 MIDAS 220xx 250xx 43 0 Revision ID VMETRO Assigned 00 Example 0 0000 001 Rev B ECO level 1 53 0 Pointer to null terminated ASCII string Revision ID VMETRO Assigned 257 00 0x000000 No string 5B 5F 7B 20002 Reserved for future use Program ID Code 0x01 No program ID ROM only Table 3 MIDAS Configuration ROM 20 e Functional Description MIDAS USER s MANUAL Switch amp Jumper Descriptions MIDAS has a DIPswitch and a number of jumpers for board configuration For easy identification their functions are indicated with silk screen text on the printed circuit board VME Register Access Image ENABLE DISABLE The VME Register Access Image VRAI permits accesses from VMEbus to the VME PCI bridge internal registers at power up Unless the Auto Slot ID protocol which uses its own slave image is used this slave image must be enabled to allow initialization from VMEbus Jumpers Function
13. FFFF 0000 0000 1FFF FFFF PMCONO 1 p i960 RP Physical Memory MIDAS Memory Map Reaions Figure 9 Local Memory Address Space i960 RD Power Up Options i960 RD monitors a number of pins during reset to define its mode of operation The most important are Secondary PCI Arbiter Enable Disable For both i960 RDs the secondary PCI arbiter is always enabled i960 RD Boot Modes Two of the power up options control the boot process of the i960 RD These two options can be controlled through two jumpers JP9 amp JP14 located in the top right corner of the board i960 RD 1 i960 RD 2 Processor Boot directly Processor Boot directly PCI Retry until CSR set PCI Retry until CSR set Processor Boot directly Processor Sleep until CSR set Retry until CSR set Accept config cycles MIDAS USER s MANUAL Functional Description e 15 Sleep until CSR Processor Boot directly PCI Retry until CSR set PCI Accept config cycles FLASH Memory Each i960 RD on MIDAS 220 has a private 16Mbit FLASH device 95ns 2 8 flash file device is used Jumpers JP13 Removed JP11 Inserted Locked FLASH blocks are write erase protected With some restrictions blocks can be locked Ref 128 0165 55 datasheet pin is at level with this jumper setting JP13 amp JP11 Removed Entire F
14. Information MIDAS USER s MANUAL PCI Command Register Register Name PCMDR Size 16 bits Offset 0 04 Function PERR_EN PCMDR Description State SERR EN EN SERREN RW 0 SERREnable SERR SERR Enable 454520 ww Table 21 PCI Command Register PCI Status Register Register Name PSR Size 16 bits Offset 0x06 Bits Function RESERVED 000000 PSR Description Name Type Reset Function State ET 0002 sese en eae om xw o parro Table 22 PCI Status Register MIDAS USER s MANUAL Appendix Ill PXB Information e 45 Secondary Status Register Register Name SSR Size 16 bits Offset 0 1 Bits Function RESERVED 000000 SSR Description State De RW Detected parity error Detected parity error parity error Lm poem 2 0 ww ET ww CT me x TT EE Com ww e penes 01 Table 23 Secondary Status Register Memory Mapped Base Address Register Register Name MIOBAR Size 16 bits Offset 0x20 5 31 Po moan 24 MIOBA 23 16 0000 MIOBAR Description Name Type Reset Function State MIOBA R W Base Address inclusive for Memory Mapped I O 20 Isb assumed 0 Alignment 1MB Table 24 Memory Mapped I O Base Address Register 46 Appendix Ill PXB Information MIDAS USER s MANU
15. use of the daisy chained IACK signal CR CSR space Plug amp Pl Ses accesses are enabled for one VME slot at a time Thus the Monarch host for initialization is able to recognize installed modules and initialize them to achieve Plug amp Play VMEbus systems e Enabling of the Auto Slot ID feature causes IRQ2 to be asserted this may cause problems in systems containing VMEbus boards which do not support the Auto Slot ID feature In such cases the Auto Slot ID feature must be disabled Configuration ROM To support the Auto slot ID protocol the MIDAS board implements a configuration ROM This ROM is implemented as a PCI bus slave only device which responds in PCI I O space using subtractive decoding MIDAS USER s MANUAL Functional Description e 19 e Note that parity is not generated when reading the MIDAS configuration ROM Parity errors should therefor be disregarded when reading these locations In the power up state of the Universe II VME PCI bridge parity errors are disregarded The configuration ROM is disabled by any write in PCI Configuration Space with address bit 30 set to 1 This way boot software may remove the CROM from PCI I O space to allow another subtractive decoding agent or to avoid parity errors on reads from present devices MIDAS x20 Configuration ROM CROM Offset 03 VME CR CSR Space Offset ROM Description Value Checksum Eight bit 2s complement binary checksum CR bytes 03
16. 00F0C 0x0000 0000 Translation Offset set to 0 000000 D 0x0200 E080 to A 0x000F00 Ox80E0 0002 Enable Image VAS A16 LAS Config Space PGM both SUPER Supervisor other options disabled D This column shows write data for configuration from PCI Table 12 VME Slave Image 0 Setup VMEbus Slave Image 1 The VMEbus Slave Image 1 is set up to map A24 accesses in the address range 0x100000 0x3FFFFF from VMEbus to I O Cycles on the PCI bus with PCI addresses starting from 0x02100000 38 e Appendix Il Universe Configuration Examples MIDAS USER s MANUAL Write from VME PCI Data Base Address set to 0x100000 Bound Address set to 0400000 D 0x0000 0002 to A 0x000F20 0x0200 0000 Translation Offset set to 0x2000000 D 0x4100 F180 to A 0x000F14 0x80F1 0041 Enable Image VAS A24 LAS I 0 Space PGM both SUPER both LLRMW enabled other options disabled D This column shows write data for configuration from PCI Table 13 VME Slave Image 1 Setup VMEbus Slave Image 2 VMEbus Slave Image 2 is set up to map A32 accesses in the address range 0x4000 0000 0x 7FFF FFFF from VMEbus to Memory Cycles on the PCI bus with PCI addresses starting from 0x6000 0000 Write posting and read prefetching is enabled D 0x0000 F2E0 to A 0x000F28 OxEOF2 0000 Enable Image VAS A32 LAS Mem Space PGM both SUPER both PWEN amp PREN enabled other options disabled This column shows write data for configuration from PCI Tabl
17. AL Memory Mapped I O Limit Address Register Register Name MIOLAR Size 16 bits Offset 0 22 Function MIOLA 31 24 MIOLA 23 16 0000 MIOLAR Description Name Type Reset Function State MIOLA R W Base Limit inclusive for Memory Mapped I O 20 185 assumed 1 Alignment 1MB Table 25 Memory Mapped 1 0 Limit Address Register Prefetchable Memory Base Address Register Register Name PMBAR Size 16 bits Offset 0x24 Function PMBA 31 24 PMBA 23 16 0000 PMBAR Description Name Type Reset Function State PMBA R W Base Address inclusive for Prefetchable Memory space 20 lsb assumed 0 Alignment 1MB Table 26 Prefetchable Memory Base Address Register Prefetchable Memory Limit Address Register Register Name PMLAR Size 16 bits Offset 0x26 Function PMLA 31 24 PMLA 23 16 0000 MIDAS USER s MANUAL Appendix Ill PXB Information e 47 PMLAR Description Name Type Reset Function State PMLA R W Base Limit inclusive for PrefetchableMemory space 20 Isb assumed 1 Alignment 1MB Table 27 Prefetchable Memory Limit Address Register Bridge Control Register Register Name BCR Size 16 bits Offset 0x3E EDD NE RESERVED D RESERVED 0000 0009 0000 BCR Description Name Type Reset Function State FBTB BECOME ANUS Fast Back to Back Enable SBRES Secondary Bus Reset 0 Do not assert RST 1 Assert RST on secondary bus MAM R W Master Abort Mode 0 Do not report master a
18. CI Bus PCI Bus 4 Both a memory mapped I O window and a prefetchable memory window must be defined in order to make the bridge operation from secondary to primary side work correctly BAR and limit registers of the secondary PXB are set to values corresponding to the address space on their PCI side PXB will calculate the size of the big window BAR limit on primary PXB based on the BAR and window size Widow sizes set in 0x40 must be the same for primary and secondary PXBs 56 Appendix Ill PXB Information MIDAS USER s MANUAL PXB Initialization Example Below is an example on how to setup registers of two PXB chips so that they provide a PCI to PCI bridge across RACEway interlink ILK4 The PXB in the RACEway slot A is referred to as the primary PXB and the PXB in the slot B as the secondary PXB The following example creates an 8 Mbytes window at PCI Memory space addresses 0x80000000 0x807fffff from the primary to the secondary side i e the primary PXB will respond to address cycles between 0x80000000 0x807fffff and forward them to the secondary side The secondary PXB will forward transactions in address ranges 0x0 OX7FFFFFFF and 0x81000000 OxFFFFFFFF to the primary side The initialization values may easily be programmed into the PXB using PCI Configuration Type 0 cycles The offsets for each register are given PCI to PCI Bridge Configuration Space Header Registers of the P
19. Dairy Ashford Suite 535 Houston TX 77077 USA Tel 281 584 0728 Fax 281 584 9034 Email Europe Asia VMETRO asa Brynsveien 5 N 0667 OSLO Norway Tel 47 2210 6090 Fax 47 2210 6202 Email nfo vmetro no http www vmetro com MIDAS USER s MANUAL iii iv Contents MIDAS USER s MANUAL Contents MIDAS USER s MANUAL Contents vi Contents MIDAS USER s MANUAL General Information This document This document has been prepared to help the customer integrate MIDAS their VMEbus system The following models are covered by this document MIDAS 1 20 Intelligent I O Subsystem with single i960 RD and memory and two PMC positions MIDAS 150 Intelligent I O Subsystem with single i960 RD and memory and five PMC positions Occupies two VMEbus slots MIDAS 220 Intelligent I O Subsystem containing dual i960 RD with independent memories and two PMC positions MIDAS 250 Intelligent I O Subsystem containing dual i960 RD with independent memories and five PMC positions Occupies two VMEbus slots The following options are described R RACEway option Interface to 160 MB s RACEway crossbar S Symmetrical configuration Configuration option with one PMC position on each PCI bus Applies to MIDAS 120 and MIDAS 220 only Conventions used in this document Symbols e The following section describes conventions used in this document Meaning The STOP symbol indicates a section
20. Errata Application Notes p www tundra com Intel Corporation 80960RD I O Processor e User Manual Not used on MIDAS 20 50 e Device Errata e Application Notes and more ttp www intel com design i960 2 e General Information MIDAS USER s MANUAL Product Overview MIDAS Family The MIDAS family provides complete PMC Sub systems for VMEbus and or RACEway The boards may carry two or five PMC PCI Mezzanine Cards and are designed for effective integration of high performance PCI I O functions into VME systems The family ranges from a very simple 2x PMC Carrier MIDAS 20 to a powerful Twin 1960 amp Memory 5x PMC Carrier MIDAS 250 in which twin memories and processing power from two CPUS are available The MIDAS 200 Series AFront Panel 1 0 Front Panel I O DRAM RS232 16 64MB i960RD DMA PCI Mezzanine Card PCI Mezzanine Card PCI Mezzanine Card PMC 3 PMC 4 PMC 5 i960RD DMA 1 VMEbus P2 1 0 MIDAS 220 MIDAS 250 Figure 1 MIDAS 220 250 Block Diagram The MIDAS 220 series utilize unique independent dual 1960 processor and Memory arrays each coupled to a PMC I O Sub System for maximum data through put to both VMEbus and or RACEway The boards carry two or five PMC PCI Mezzanine Cards a
21. LASH is write protected JP13 amp JP11 Inserted No Protection Entire FLASH can be erased written Lock bits can be altered JP13 Inserted JP11 Removed Indeterminate state Memory contents is not protected Normal Operation Unlocked flash blocks may be erased and re programmed This setting should only be used DURING flash updates of locked flash blocks Normally only the MIDAS Monitor If U44 a PLD mounted on the backside of the i960 RD 1 on the opposite side of the board is labeled 1002 i960 RDZ1 will boot directly If U44 is labeled 1002 the PCI bus will accept config cycles 16 e Functional Description MIDAS USER s MANUAL FEFF FF30 Boot Record es 8 0000 FEFF FFFF 0 0000 FEO7 FFFF Figure 10 FLASH Boot Address RS232 Interface Each i960 RD on the MIDAS 220 has a private UART for serial port communication The TL16C550 is used for this purpose Both RS 232 interfaces share a mini DIN connector for connection through the front panel The UART is located at a fixed address in the 1960 address space The base address is 0 0000 The eight most significant address bits are used for the address decoding which means that a 16MB window is occupied RS232 Cables MIDAS 100 and MIDAS 200 series boards are shipped with a short converter cable to allow standard D SUB cables to connect t
22. PMC 2 pAD 17 0x00020XXX 0 223000 i960 RD 1 pAD 18 0x00040XXX OxYYZZ3800 PXB PCI RACEway pAD 19 0 00080 0 224000 i960 RD 2 pAD 20 0x00100XXX 0 224800 VME PCI BRIDGE pAD 31 0x80000XXX ZZ PCI Bus Number as defined in Universe II MAST register YY VME base address for slave image Table 8 IDSEL Assignments for Primary PCI Bus MIDAS USER s MANUAL Functional Description e 27 PCI DEVICE BOARD IDSEL PCI ADDRESS FOR VME BASE ADDRESS CONFIG CYCLE FOR PCI CONFIG CYCLE 3 16 0 00010 OxYYWW PMC 4 sAD 17 0x00020XXX OxYYWW 0800 WW PCI Bus Number for secondary bus as defined in i960 RD YY VME base address for slave image Table 9 IDSEL Assignments for Secondary PCI Bus Subtractive Decoding Agent The CR CSR PLD utilizes subtractive decoding in the PCI bus O Space No other PCI devices are allowed to do the same Subtractive decoding in Memory Space may be used For further information please refer to description of Configuration ROM 28 e Functional Description MIDAS USER s MANUAL Interrupt Routing The MIDAS board has a number of interrupt sources and destinations In order to provide a flexible interrupt routing scheme which also allows customization all interrupts are routed through a JTAG programmable PLD PMC 5 PMC 4 PMC 3 PMC 2 PMC 1 A BCD A BCD A BCD A BCD ABCD INT2A D
23. User s Manual MIDAS 100 200 series PMC Subsystem for VMEbus and RACEway Rev 1 0b Valid for MIDAS PCB B 7 8 m J information in this document is subject to change without notice and should not be construed as commitment by While reasonable precautions have been taken VMETRO assumes no responsibility for any errors that may appear in this document Copyright VMETRO 2000 This document may not be furnished or disclosed to any third party and may not be copied or reproduced in any form electronic mechanical or otherwise in whole or in part without prior written consent of VMETRO Inc Houston TX USA or VMETRO A S Oslo Norway UMETRO MIDAS USER s MANUAL Warranty VMETRO products are warranted against defective materials and workmanship within the warranty period of 1 one year from date of invoice Within the warranty period VMETRO will free of charge repair or replace any defective unit covered by this warranty shipping prepaid Return Authorization Code should be obtained from prior to return of any defective product With any returned product a written description of the nature of malfunction should be enclosed The product must be shipped in its original shipping container or similar packaging with sufficient mechanical and electrical protection in order to maintain warranty This warranty assumes normal use Products subjected to unreasonabl
24. a VMEbus system is automatically detected as specified in the VME64 specification System controller functions are also enabled as a consequence WARNING Do not install the board in a powered system Power consumption air cooling for reliable operation Operation on extender boards is not WARNING Due to its power consumption the MIDAS board requires forced 2 recommended typ 5 MIDAS 220Y M 32MB Both processors are in the idle state 14 5W MIDAS 220 32MB One processor transferring data 14 7W other processor idle MIDAS 220 Y M 32MB One processor transferring data 15 2W across VME and Raceway the other processor performing an extended selftest MIDAS 220 SR 128MB Both processors are in the idle state 15 0W MIDAS 220 SR 128MB One processor transferring data 15 7W other processor idle MIDAS 220 SR 128MB One processor transferring data 17 0W across VME and Raceway the other processor performing an extended selftest MIDAS 120 32MB Processor Idle 10 5W MIDAS 120 32MB Processor running selftest 11 5W MIDAS 120 32MB Processor transferring data over 11 5W VME Table 1 Power Consumption 12 Installation MIDAS USER s MANUAL Configuration Switch amp Jumpers The MIDAS has a large number of configuration registers which need to be initialized before the board is operational Most registers are normally initialized by i960 RD but in some applications an external host processor can perform thi
25. bort all 1 1 Report master abort with target abort Enable for system errors detected on C bus and reported to primary bus PERREN PERREN RW 0 Enable for parity errors response on secondary bus Enable for parity errors response on secondary bus for parity errors response on secondary bus Table 28 Bridge Control Register PXB Bridge Control Register Register Name PBCR Offset 0x40 48 e Appendix Ill PXB Information MIDAS USER s MANUAL Description Reset Function State EIBAR E EM ee Enable memory internal BAR 1 enable 0 disable MODE Operating Mode 0 Bridge Mode 1 Endpoint Mode This bit should always be cleared use Bridge Mode WSWAP 1 Word Swap 1 0 disable BSWAP Byte Swap 1 enable 0 disable Prim Sec Mode 0 Secondary Mode 1 Primary Mode wmm x eea Enable prefetchable memory BAR 1 enable 0 disable Table 29 PXB Bridge Control Register Memory Window Register Register Name MWR Offset 0x41 Function PPAGE MWSHIFT MWR Description Name Type Reset Function State PPAGE W Primary Page Used by secondary PXB as index into page ram when out of bounds accesses occurs should be set to unused page register Returns zeros when read MWSHIFT R W Memory window shift Selects which address bits are used to index page ram during memory accesses Bits Wi
26. de of the chip In order for a primary PXB to do Typel to TypeO configuration operations or virtual Typel to TypeO operations accessing CSRs in secondary PXBs the lookup tables for config ops in the PROM must be initialized The contents of these tables are used to index the route table for configuration type 1 accesses The tables are located in PROM address ranges 0 80 0 and 0 220 gt PCl to RACEway Addressing e Three bits of PCI address are used to index the Route Table This table holds the routes used to set up a connection through the crossbars With Big Mem enabled the least significant portion of the Return Route holds the most significant bits of the RACEway address Bit 0 of the Return Route will replace the least significant PCI bus address bit used to index the Route Table The most significant bit replaced is always bit 27 of the PCI address Big Mem is only used for prefetchable memory space Big Mem is not used for P2P applications Configuration Cycles e Lookup table in EEPROM is used to index the route table for each PCI bus device PXB Route Format Function Routes Du Rs 7 0 BigMem Not Priority B cast Splitable MIDAS USER s MANUAL Appendix Ill PXB Information e 53 PXB Route Description Routes Concatenated three bit route codes one per crossbar hop Route codes 111 Port A 110 Port B 101 Port C 100 Port D 011 Port E 010 Port 001 Adaptive Route E first
27. discharge Always wear grounded anti static wrist strap and use grounded static protected work surfaces when touching the circuit board and its components When the board is not installed always keep in the static protective envelope Unpacking precautions described above must be taken when unpacking the MIDAS from its shipping container Verify that no damage has occurred in the shipment Refer to packing list and verify that all items are present MIDAS USER s MANUAL Installation e 7 Board Layout VMEbus CONFIGURATION BOOT MODE JUMPERS amp SWITCH SELECTION 7 A ose m mm zio VRAI ASIZE x RS232 CONNECTOR ssp 2 39 0 m gt L 995 JP7 2 RESET BUTTON a 1 VME VME to PCI BRIDGE 9 PCI CONNECTOR PMC 2b amp MIDAS x50 Expansion 2 8 5 O PCI CONNECTOR PMC 2a NUM Not mounted for 5 option RESET SWITCH S OPTION P2 1 0 CONNECTOR PMC 2a i960RD Not mounted for S or R options
28. e 14 VME Slave Image 2 Setup Initialization Sequence By performing the list of cycles shown in the table below the mapping for this configuration example is achieved D 0x0200 E080 to A 0x000F00 Ox80E0 0002 VS 0 Enable Image VAS A16 LAS Config Space PGM both SUPER Supervisor other options disabled MIDAS USER s MANUAL Appendix II Universe Configuration Examples 39 PGM both SUPER both LLRMW enabled other options disabled VSI 2 Base Address set to 0x4000 0000 VSI 2 Translation Offset set to 0x2000 0000 D 0x0000 F2E0 to A 0x000F28 0 2 0000 VSI 2 Enable Image VAS A32 LAS Mem Space PGM both SUPER both PWEN amp PREN enabled other options disabled This column shows write data for configuration from PCI Table 15 Initialization Sequence for VMEbus Slave Image Config Example PCI Slave Images The VME RAI described in the VMEbus Slave Images section is also utilized to set up PCI slave images in the examples below PCI Target Enable Memory amp I O Space In addition to the configuration registers for the PCI slave images two control register bits are essential for mapping PCI bus cycles to VMEbus cycles through the Universe II The PCI Target Memory Enable MS and Target IO Enable IOS bits located in the PCI_CSR register offset 0x004 must be set to allow the Universe II to respond to PCI memory and I O commands 40 Appendix Universe Configuration E
29. ed interrupt modes interrupt sources and destinations are present for MIDAS 250R only For other models the routing scheme is the same but sources and destinations not present should be ignored 30 e Functional Description MIDAS USER s MANUAL Interrupt Mode 0 INTERRUPT PIN SOURCE i960 RD PMC 1 PMC 2 PMC 3 PMC 4 PMC 5 UNIVERSE UART PMC 2b 8182 mermon EEE O INTERRUPT PIN SOURCE PMC 4 I960RD 1 I960RD 2 C A EE Pl MIDAS USER s MANUAL Functional Description 31 Interrupt Mode 1 INTERRUPT PIN SOURCE mu 32 e Functional Description MIDAS USER s MANUAL INTERRUPT PIN SOURCE PXB PMC 1 PMC 2 4 PMC 5 1960RD 1 1960RD 2 PMC 2b c DA e lejoja B 2114 j ej i960 RD 1 i960 RD 2 LE oc A E ERN EE c FR Se MIDAS USER s MANUAL Functional Description e 33 INTERRUPT PIN SOURCE UNIVERSE Il PMC 1 PMC 2 PMC 3 PMC 4 PMC 5 I960RD 1 I960RD 2 PMC 2b INTERRUPT PIN SOURCE 1 2 PMc 3 PMc 4 5 960 81 96080 2 PMC 2b 34 e Functional Description MIDAS USER s MANUAL Appendix I PMC I O Routing PMC I O Routing Scheme J4 24 suci 04 24
30. f it is disabled ref VMEbus Slave Image section 1 51 0 Bound Address set to 0x0000 1000 LSI 0 Translation Offset set to 0x0000 1000 D 0x0110 4180 to A 0x000100 0x8041 1001 17 0 Enable Image VAS A24 VDW D16 1 5 4 Space PGM data SUPER supervisor other options disabled LSI 1 Base Address set to 0x1000 0000 LSI 1 Bound Address set to 0x3000 0000 LSI 1 Translation Offset set to 0 1000 0000 D 0x0001 82C0 to A 0x000114 0 082 0100 17 I Enable Image VAS A32 VDW D32 LAS Mem Space PGM data SUPER non priv Posted Write enabled BLT allowed LSI 2 Bound Address set to 0x6000 0000 LSI 2 Translation Offset set to 0xC000 0000 D 0x0001 C2C0 to 0 000128 OxC0C2 0100 LS 2 Enable Image VAS A32 VDW D64 LAS Mem Space PGM data SUPER non priv Posted Write enabled BLT allowed D This column shows write data for configuration from PCI Table 19 Initialization Sequence for PCI Slave Image Config Example MIDAS USER s MANUAL Appendix II Universe Configuration Examples 43 Appendix Ill PXB Information PXB Register Descriptions P Side Register Descriptions If no valid PROM is present the PXB powers up in endpoint mode but should always be used in bridge mode This is done by clearing bit 6 in register 0x40 Class Code 060000 z x 40 E 5 T x 2 Table 20 P side CSR Registers 44 e Appendix 11 PXB
31. he PCI Slave Image 1 is set up to map PCI Memory Space transactions in the address range 0x1000 0000 0x2FFF FFFF to A32 D32 VMEbus cycles in the address range 0x2000 0000 0x3FFF FFFF D 0x0001 82C0 to A 0x000114 0xC082 0100 Enable Image VAS A32 VDW D32 LAS Mem Space PGM data SUPER non priv Posted Write enabled BLT allowed This column shows write data for configuration from PCI Table 17 PCI Slave Image I Setup PCI Slave Image 2 PCI Slave Image 2 is set up to map PCI Memory Space transactions in the address range 0x4000 0000 0x 5FFF FFFF to 32 064 VMEbus cycles in the address range 0x0000 0000 0x 1 FFF FFFF Write from VME PCI Data Base Addres set to 0x4000 0000 Bound Address set to 0x6000 0000 D 0x0000 00C0 to A 0x000134 0xC000 0000 Translation Offset set to 0000 D 0x0001 C2C0 to 0 000128 0 0 2 0100 Enable Image VAS A32 VDW D64 LAS Mem Space PGM data SUPER non priv Posted Write enabled BLT allowed D This column shows write data for configuration from PCI Table 18 PCI Slave Image 2 Setup 42 Appendix Universe Configuration Examples MIDAS USER s MANUAL Initialization Sequence By performing the list of cycles shown in the table below the mapping for this configuration example is achieved Write from VME PCI Data D 0x0700 8002 to A 0x000004 0x0200 0007 PCI Target Enable bits set this write cycle also sets the PCI master enable bit i
32. ignificant bit used to index the page table The most significant bit replaced is always bit 27 of the PCI address With 256MByte windows no bits are replaced If BigMem Mode is not used always the case for P2P applications this field is not used Table 35 PXB Return Route Format RACEway to PCI Addressing Mask registers one for each address window are always used by secondary PXB to generate the high order PCI address bits bits from the least significant 17 and up to 3 are used as PCI bus addresses These registers are normally loaded automatically from the BARS for each transaction 1 e as long as the no autoload bit in register 0x40 is cleared The register is not used by primary PXB MIDAS USER s MANUAL Appendix Ill PXB Information e 55 PCI to PCI Bridge Operation PCI Bus 0 In Primary Config PROM Look up tables for PCI Config Cycles Type 1 to sec PXBs 0x80 100 Look up tables for 1 to Type 0 config cycles to devices on sec PCI busses 0 220 gt Route Table with Route and Return Route for transactions initiated on primary PCI Bus Control Registers see example PCI Bus 1 Virtual PXB 2 PXB 3 PXB 4 PXB 1 primary In Secondary Config PROMs Route Table with Route and Return Route for transactions initiated on secondary PCI Bus Control Registers see example secondary secondary secondary PCI Bus 2 P
33. is independent of PROM contents This setting is normally used for the initial programming of the PROM or if the board is plugged into a non RACEway slot Note that before programming the PROM the PXB must be set in bridge mode ref PXB description Jumpers JP6 JP10 RACEway Function JP6 Inserted PXB registers not loaded from EEPROM JP10 RACEway O JP6 JP6 Removed PXB registers loaded from EEPROM 24 e Functional Description MIDAS USER s MANUAL Reset from When the Reset from X jumper is removed the PCI RACEway bridge receives reset from PCI bus i e MIDAS reset circuitry and drives reset to the RACEway interlink This setting should always be used Inserting this jumper may be destructive for the MIDAS board and is likely to cause system malfunction Function 10 Removed This setting should always be used PCI Bus Details Arbitration Secondary PCI bus The PCI bus arbitration unit in the i960 RD 1 is responsible for arbitration on the secondary PCI bus for all MIDAS models The secondary bus arbiter of the i960 RD supports up to six secondary bus masters plus its own secondary bus interface Each request can be disabled or programmed to one of three priority levels A memory mapped control register programmed by the application software sets the priorities for each of the bus masters Each priority level is ha
34. k Diagram The MIDAS 100 series are versatile PMC I O Sub System amp Memory modules for VMEbus and or RACEway holding two or five PMC PCI Mezzanine Cards The boards are designed for cost effective integration of PCI I O functions into the VME or RACEway systems where local memory and or processing power is required i960RD I O processor A central element of the MIDAS 100 series is the Intel 1960RD processor The highly integrated 1960RD features a powerful RISC I O processor a PCI to PCI bridge a memory controller and a flexible DMA controller with linked list capability The 1960 has direct access to FLASH PROM RS232 UART all of the PCI resources on the board and of course the DRAM This allows it to offload the 4 e Product Overview MIDAS USER s MANUAL host CPU running dedicated I O drivers for the PMC modules mounted on the board Main Components i960 RD 1 0 Processor The 1960 RD processor integrates a high performance 80960 core into Peripheral Components Interconnect PCT functionality This integrated processor addresses the needs of intelligent I O applications The primary functional units include an 1960 core processor PCI to PCI bus bridge PCI to 80960 Address Translation Unit Messaging Unit Direct Memory Access DMA Controller Memory Controller and Secondary PCI bus Arbitration Unit The PCI Bus is an industry standard high performance low latency system bus which operates up to
35. lot ID JP6 controls the enabling of the VME64 Auto Slot ID mechanism AUTO ID JP4 AUTO ID JP4 Jumpers JP5 SFAIL JP5 SFAIL Function JP4 UP VME64 AUTO SLOT ID ENABLED JP4 DOWN VME64 AUTO SLOT ID DISABLED SYSFAIL Assertion ENABLE DISABLE The VMEbus interface provides the option to assert the VMEbus signal SYSFAIL during power up When this feature is enabled the MIDAS board will assert SYSFAIL on the VMEbus until the boot initialization software has completed the power up selftest and configuration routines SYSFAIL is then de asserted to signal to the VMEbus system that the board is ready to operate JP5 controls the enabling of this mechanism 22 Functional Description MIDAS USER s MANUAL Jumpers Function 508 JP5 UP SYSFAIL ASSERTION DISABLED z Q A _ JP5 DOWN SYSFAIL ASSERTION ENABLED SYSRST Assertion ENABLE DISABLE If this jumper is removed pushing of the reset button will perform both a local and a global reset In order to perform only a local reset without assertion of the SYSRST signal on the VMEbus the jumper should be inserted Jumpers Function JP7 INSERTED SYSRST ASSERTION DISABLED 5 DS a JP7 REMOVED SYSRST ASSERTION ENABLED When disabling SYSRST assertion the Universe II chip is partly reset by fron
36. n two PCI busses like on the MIDAS 220 introduces restrictions on the programming of the address translation units as well as on the P2P bridge The P2P bridge in i960 RD 2 should not be enabled in order to simplify the generation of a valid address map VMEbus Interface Universe VME PCI Bridge The VME PCI bridge on MIDAS has a number of configuration registers which need to be initialized before the bridge is fully operational One 196089 RD processor or a host processor residing on VMEbus does this initialization Universe Power Up Options The Universe II loads a number of power up options after power up or system reset A detailed description of these options is found in the UNIVERSE II USER MANUAL shows how they are controlled on the MIDAS 18 e Functional Description MIDAS USER s MANUAL Option Enabled Register Field by EN Register Access Slave Image PPWR SYS VRAI CTL Jumper JP1 Jumpers JP2 3 VRAI BS Switch SW1 CR CSR Slave Image VCSR_TO PCI CSR Slave Image Disabled Mem space A16 5 0 0 0 0 PWR SYS PCI BS SPACE I O Space RST MISC STAT LCLSIZE PWR SYS MISC STAT DY4AUTO Disabled PWR SYS MISC WR SYS VCSR_ SET SYSFAIL Jumper JP5 Detect SYS SYSCON Table 2 Universe Power Up Options Auto Slot ID The MIDAS supports the Auto Slot ID mechanism as defined by the VME64 specification By
37. nd are designed for effective integration of high performance PCI I O functions into the VME or RACEway systems where twin memories and or processing power from two CPUs is required The MIDAS 220 series is particularly well suited for applications such as Imaging Data Acquisition and Signal Processing Twin i960RD 1 processors A central element of the MIDAS 220 series is the twin Intel 1960RD processor architecture The highly integrated 1960RD features a powerful RISC I O MIDAS USER s MANUAL Product Overview e 3 processor a PCI to PCI bridge a memory controller and a flexible DMA controller with linked list capability Each of the two 1960 05 has direct access to its own FLASH PROM a RS232 UART all of the PCI resources on the board and of course its associated DRAM bank This allows it to offload the host CPU by running dedicated I O drivers for the PMC modules mounted on the board For applications that do not need the processing power of the 1960RD but only twin DRAM memories and or DMA the processors may rest idle during normal operation The MIDAS 100 Series Front Panel RS232 Front Panel 1 0 F Y PCI PCI PCI Mezzanine Mezzanine Mezzanine Card Card Card PMC 3 PMC 4 PMC 5 P2 VO VMEbus P2 VO MIDAS 120 MIDAS 150 Figure 2 MIDAS 120 150 Bloc
38. ndled in a round robin fashion The three levels define a low medium and high priority Using the round robin mechanism ensures there is a winner for each priority level To enforce the concept of fairness a slot is reserved for the winner of each priority level except the highest in the next highest priority When the winner of a priority level is not granted the bus during that particular arbitration sequence it is promoted to the next highest level of priority Once its bus ownership is removed the device is reset to its initially programmed priority and may start arbitration once again For more information on the arbitration scheme and on the programming of the arbiter please refer to the i960 RD User s Manual MIDAS USER s MANUAL Functional Description e 25 Assignments to Arbiter RD 1 Device Numbers PCI DEVICE DEVICE NUMBER 2b PMC 3 Device 2 PMC 4 Device 4 5 0 i960 RD 2 Device 1 Table 5 Secondary PCI Bus Primary PCI bus The arbitration of the primary PCI bus is handled in three different ways depending on MIDAS model MIDAS 200 Series The PCI bus arbitration unit in the i960 RD 2 is responsible for arbitration on the primary PCI bus for all MIDAS 200 series models For more information refer to the brief description Secondary PCI Bus page 25 or the 1960 User s manual Assignments to Arbiter RD 2 Device Numbers DEVICE DEVICE NUMBER 1
39. ndow Small Window 0000 31 28 4GB 256 MB 0001 30 27 2 GB 128 MB 0010 29 26 1 GB 64 MB 0011 28 25 512 MB 32MB 0100 27 24 256 16 MB 0101 26 23 128 MB 8 MB 0110 25 22 64 MB 4MB 0111 2421 32 2 23 20 16 MB 1 MB Table 30 Memory Window Register MIDAS USER s MANUAL Appendix Ill PXB Information e 49 Window Register Function IOSHIFT MIOSHIFT MWR Description Name Type Reset Function State IOMIOWR Offset 0 42 Register Name IOSHIFT R W window shift Selects which address bits are used to index page ram during 1 accesses Bits Big Window Small Window 0000 23 20 16 MB 1 MB 0001 22 19 8 MB 512 KB 0010 21 18 4MB 256 KB 0011 20 17 2MB 128 KB 0100 19 16 1 MB 64 KB 0101 18 15 512 KB 32 KB 0110 17 14 256 16 0111 16 13 128 8 KB 15 12 64 KB 4KB Memory Mapped window shift Selects which address bits are used to index page ram during memory mapped I O accesses 1 0000 0001 0010 0011 0100 0101 0110 0111 Bits 29 26 28 25 27 24 26 23 25 22 24 21 23 20 22 19 21 18 Big Window 1 GB 512 MB 256 MB 128 MB 64 MB 32 MB 16 MB 8 MB 4 MB Table 31 Window Register PXB Misc Register Register Name PMR Small Window 64 MB 32 MB 16 MB 8 MB 4 MB 2 1 512 256 Offset 0 43 50 Appendix PXB Information Func mw
40. o the non standard Mini DIN MIDAS connector The cable for the MIDAS 200 board is a split cable with one 9 pin D sub connector for each processor The shorter cable connects to the UART of i960 RD 1 while the longer cable connects to processor number two PIN 1 TxD1 2 E 1 2 TxD2 16 151 14 3 RxD1 PIN 4 RxD2 UE 1 PINS GND Figure 11 Pin definition for the RS232 female connector mounted on the front panel Connecting two i960 RDs To maximize the utilization of the i960 RD s resources the two processors are connected as shown in MIDAS USER s MANUAL Functional Description e 17 The primary PCI bus interface on 1960 RD 1 is connected to the secondary interface on 1960 RD 2 and vice versa The primary PCI bus in MIDAS terms connects to the primary side of i960 RD 1 Primary PCI Bus RS 232 through front panel mini DIN eos ex ros Interface Interface FLASH i960JF 2 8 UART Memory 5 16550 Controller PCI to Local Bus I F PCI Bridge PCI to Local Bus I F Memory S Controller PCI to Local Bus I F PCI to Local Bus I F 1960 FLASH Gore 2 8 16 32 64 Secondary PCI Bus RS 232 through front panel mini DIN Figure 12 Connection of two i960 RDs MIDAS 220 Note that for any connection of two 1960 RDs in parallel betwee
41. of critical importance Overlooking this information may cause damage to the MIDAS and or other equipment Indicates important but not crucial information Still you should take notice 1f you want to use all capabilities built into your MIDAS MIDAS USER s MANUAL General Information e 1 Related Documents This document does not include detailed information about the following main board components i960 RD Intelligent I O Processor e Universe VME to PCI bridge chip PXB RACEway to PCI bridge chip Since a majority of the control registers and a large part of the complexity of the MIDAS is implemented in these chips their documentation contains information which is essential to the understanding of the product VMEbus PCI Tundra UNIVERSE 117 USER MANUAL i960 RD Intel Corp i9609Rx I O MICROPROCESSOR DEVELOPER S MANUAL i9609RD DATA SHEET RACEway PCI PXB OVERVIEW PXB BRIDGE SPECIFICATION Documentation can be obtained from VMETRO by ordering a MIDAS Documentation Package The vendors of some of the major components used on MIDAS publish device data via Internet Some components may contain design defects or errors known as errata which may cause the component to deviate from published specifications The respective vendors on their web pages document current characterized errata Available documentation Tundra formerly Newbridge Universe Bridge User Manual Device
42. rimary PXB 0 0 0 0 0 00030100 0 04800111 0 00000010 Ox80f08000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000100 0 10880826 0 00000000 0 00004773 04 0x00000000 0 00000000 0 00000000 0 00000000 0 00000000 MIDAS USER s MANUAL Appendix Ill PXB Information e 57 Route Table for the Primary PXB 0 0000083 0000000 0000084 0000000 0000085 0000000 0x 0000086 0000000 0000087 0000000 Ox 0000088 0000000 0000089 20000000 000008 0000000 0000000 0x 80000000 0000000 80000000 PCI to PCI Bridge Configuration Space Header Registers of the Secondary PXB 58 Appendix PXB Information MIDAS USER s MANUAL 04 0x00000000 Route Table for the Secondary PXB MIDAS USER s MANUAL Appendix Ill PXB Information e 59 60 Appendix Ill PXB Information MIDAS USER s MANUAL Appendix List of Tables MIDAS USER s MANUAL Appendix IV 61 List of Figures igure 3 1960 RD Data Flow 1 idge functional diagram 62 Appendix IV MIDAS USER s MANUAL
43. s initialization or parts of it over VMEbus or RACEway To allow this power up options in some MIDAS components are loaded from jumpers or a DIPswitch A detailed description of each jumper is included in the relevant part of the Functional Description section MIDAS USER s MANUAL Installation 13 Functional Description i960 RD and Surroundings As indicated in each i960 RD on MIDAS has its own private FLASH memory and RS 232 interface in addition to its own block of DRAM Note that the UART and FLASH must be located in memory regions with an 8 bit bus width Primary PCI Bus DRAM 16 32 64 MB Primary PCI Interface i960 RD Memory Controller UART FLASH 2 16C550 2Mx8 ore PCI to Local Bus PCI to Local Bus Secondary PCI Interface Secondary PCI Bus RS 232 through front panel mini DIN Figure 8 i960 RD with External Devices 14 e Functional Description MIDAS USER s MANUAL i960 RD Address FE00 0000 FEFF FFFF E000 0000 FFFF FFFF 1523 15 PRIE DF00 0000 DFFF FFFF 000 0000 DFFF FFFF 42 13 000 0000 BFFF FFFF 10 11 A 8000 0000 9FFF FFFF PMCON8 9 000 0000 DEFF FFFF 6000 0000 7FFF FFFF 6 7 I ATU Transl 8000 0000 9002 FFFF both PCI 4000 0000 5FFF FFFF PMCON4_5 Direct ATU 2000 0000 3FFF FFFF PMCON2 3 bin PCD 0000 1000 7FFF
44. t panel reset button This may have undesired side effects The RST DIS jumper is included to support reset isolation in certain development systems e MIDAS USER s MANUAL Functional Description e 23 Reset Button 9 Pushing the reset button will perform both local a global reset In order to perform only a local reset without assertion of the SYSRST signal on the VMEbus the soft reset mechanism must be utilized This can be done from the host by setting the bit 23 of the Universe II MISC register offset 404 RACEway Interface PXB RACEway PCI Bridge Some MIDAS models with R option incorporate the PXB chip a PCI RACEway bridge developed by Mercury Computer Systems Jumper Descriptions MIDAS has two jumpers for configuration of the RACEway interface They are located close to the bottom edge of the board indicated with silk screen text RACEway As explained in the description below both RACEway jumpers are removed during normal operation No EEPROM When the No EEPROM jumper is removed the PCI RACEway bridge chip loads its internal registers from a serial EEPROM This setting should always be used except for cases where the PROM is blank or corrupted If the PROM is corrupted and this jumper is removed the PCI RACEway bridge may reset to a state which causes the MIDAS board in worst case the entire system to hang If the No EEPROM jumper is inserted the PCI RACEway bridge reset state
45. th utilization e Programmable DMA controller with linked list support e VMEbus transfer rates of 60 70 Mbytes sec e Complete suite of VMEbus address and data transfer modes A32 A24 A16 master and slave D64 MBLT D32 D16 D08 master and slave BLT ADOH RMW LOCK e Flexible register set programmable from both the PCI bus and VMEbus ports e Full VMEbus system controller functionality DMA Channel PCI BUS Interface VMEbus Interface posted writes FIFO prefetch read FIFO coupled read posted writes FIFO coupled read logic PCI BUS VMEbus Interrupt Handler Interruptor Register Channel Figure 4 PCI VME bridge functional diagram 6 Product Overview MIDAS USER s MANUAL PCI RACEway Bridge The PXB is a high performance RACEway to PCI bridge developed by Mercury Computer Systems It features Bridges 32 33MHz PCI bus with 32 bit 2 RACEway switching fabric Compliant to Rev 2 1 PCI local bus specification including delayed operations Compliant to Rev 1 0 PCI to PCI Bridge specification Bridges up to sixteen 32 bit 33MHz PCI busses Able to sustain up to 125MB sec with large memory write transfers and 100MB sec with large memory read transfers Integral FIFOs for write posting to maximize bandwidth utilization Installation Board Precautions The MIDAS circuit board is sensitive to static electricity and can be damaged by a static
46. x50 board from MIDAS x20 board Place the MIDAS x50 board on a smooth static protected work surface with the bottom side of the MIDAS x20 board facing up From the bottom side of the MIDAS x20 PCB remove the 5 screws holding the metal spacers between the MEZZ x50 and MIDAS x20 these screws are located close to the edge of the board in each corner and between the VMEbus connectors Note Do not throw away the screws They are needed later in this procedure Pull the boards carefully apart Use hand force only applied to the two upper VMEbus connectors for both boards If the small SPACER x50 PCB is attached to the MIDAS x20 PCB after the separation remove it and mount it on the bottom side of the MEZZ x50 board instead Mount PMC modules 1 and 2 on the MIDAS x20 board Place the MIDAS x20 board on a smooth static protected work surface Install PMC module 1 in the lower PMC position Install PMC module 2 in the upper PMC position Secure PMC modules with screws on the bottom side of the MIDAS x20 board MIDAS USER s MANUAL Installation e 9 STEP 3 Mount PMC modules 3 4 and 5 on the MEZZ x50 board Place the MEZZ x50 board on a smooth static protected work surface Install PMC module 23 in the lower PMC position Install PMC module 4 in the middle PMC position Install PMC module 5 in the upper PMC position Secure the PMC modules with screws on the bottom side of the MEZZ x50 board 0
47. xamples MIDAS USER s MANUAL VMEbus PCI bus UNIVERSE II 0x000000 VMEbus A24 all AM VME Register codes Access Image 0 000 0 001000 0 00000000 VMEbus 24 D16 PCI Slave Image supervisor data 40 PCI bus I O Space 0x001FFF 0 0000 0 20000000 0 10000000 VMEbus A32 032 non privileged data allow Fol mage PCI bus Memory Space BLT Ox3FFFFFFF Ox2FFFFFFF 0x0000 0000 0x4000 0000 VMEbus A32 064 non privileged data allow dis Image PCI bus Memory Space BLT Ox1FFF FFFF Ox5FFF FFFF PCI Slave Image 3 not used Figure 15 Configuration Example for PCI Slave Images PCI Slave Image 0 In this configuration example the PCI Slave Image 0 is set up to map PCI I O Space transactions in the address range 0x0 OxFFF to A24 D16 VMEbus cycles in the address range 0 1000 0 1 MIDAS USER s MANUAL Appendix Il Universe Configuration Examples 41 Write from VME PCI Data Base Address set to 0000 0000 Bound Address set to 0x0000 1000 D 0x0010 0000 to A 0x00010C 0 0000 1000 Translation Offset set to 0x0000 1000 D 0x0110 4180 to A 0x000100 0 8041 1001 Enable Image VAS A24 VDW D16 LAS I O Space PGM data SUPER supervisor other options disabled D This column shows write data for configuration from PCI Table 16 PCI Slave Image 0 Setup PCI Slave Image 1 In this configuration example t
48. y rough handling negligence abnormal voltages abrasion unauthorized parts replacement and repairs or theft are not covered by this warranty and will if possible be repaired for time and material charges in effect at the time of repair VMETRO s warranty is limited to the repair or replacement policy described above and neither VMETRO pnor its agent shall be responsible for consequential or special damages related to the use of their products Limited Liability VMETRO does not assume any liability arising out of the application or use of any product described herein neither does it convey any license under its patent rights nor the rights of others VMETRO products are not designed intended or authorized for use as components in systems intended to support or sustain life or for any application in which failure of the VMETRO product could create a situation where personal injury or death may occur Should Buyer purchase or use VMETRO products for any such unintended or unauthorized application Buyer shall indemnify and hold VMETRO and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that VMETRO was negligent regarding the design or manufacture of the part USA VMETRO Inc 1880

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