FMC30RF User Manual - 4DSP LLC
Contents
1. LNA OUT LPC notavalable from front panel RX VCO IN TRF3765 RXLOOUTA e RX CLK REF RX VCO CTRL TCXO 30 72MHz cpce6s005_REFEN uap uep SEC_REF PEE REF OUT urn CDCE62005 vsr LK M2C P N TOW PRI REF4 ft REF IN Figure 6 Clock paths 6 Controlling the FMC30RF Good knowledge of the internal structure and communication protocol of relevant on board devices is required for controlling the FMC30RF This document only provides guidelines for programming the devices For detailed information it is recommended to refer to the datasheets listed in the related documents section of this document 6 1 Guidelines for controlling the RF path The following control signals controls the RF frontend e TRX SWITCH CTRL e LNA BYPASS CTRL e HF ATT V 1 5 Refer to Appendix A for a description of these signals The LNA in the RX path depends on the RF coverage specified at the time of order RF coverage option 1 400MHz 1200MHz SKY67101 396LF RF coverage option 2 1200MHz 3000MHz SKY67100 396LF The gain is 18 20dB for each LNA stage 6 2 Guidelines for controlling the CDCE62005 The following control signals connect from the FMC connector to the CDCE62005 e SCLK shared with other devices e SDATA shared with other devices e CDCE62005_CS e CDCE62005 SDOUT e CDCE62005 PD UMO015 www 4dsp com 11 FMC30RF User Manual et SEH r1 3 e CDCE2. 7 424 optet ce ES 7 4 3 Main characteristic ostensae disse tateru din mutat udutusdiodi a inside d urbtue dus is 9 5 Mo od s of OP cio t tesco peice 10 5 1 Time Division Duplex TDD sisciacessuvcaitiarwcaressaveesiosmcantss vcvaicebinvericuceeandes ete reeeiwenstaat 10 5 2 Frequency Diwision Duplex FDE iiie ise tint tinte re era era Beaten cise neice 10 5 3 Multiple Input Multiple Output MIMO eeeeeeenem 10 6 Controlling the FMC3ORF eiii iae etta ento tonc ch ua Peu ap au dean dee erus p eu Pena Ere xIuuE 11 6 1 Guidelines for controlling the RF path Lien tnr tha eret uas 11 6 2 Guidelines for controlling the CDCE62005 sseesn 11 6 3 Guidelines for controlling the TRF3765 sseeeeseeeeeneeennn 12 6 4 Guidelines for controlling the TRF3711 esseeeee 12 6 5 Guidelines for controlling the TRF3720 sssseeem 12 6 6 Guidelines for controlling the AFE7225 sese 12 6 7 Guidelines for controlling the AMC7823 sseeeseseeeeeneenennn 13 2E 7 55 13 ME E UeonIIOMee c 14 NUMEN UPPER EE EUER eee ere eer 14 8 2 MODILOTPIDE iersinii eae EEE E URL tasti mr tU bin bm Mee E NU E M UR UAE 15 83 Pai 15 CPC MEME S oun pgiece oM T
3. LA15_N TRF3765_CS Connects to TRF3765 STROBE DE FMCSORF User Manual r1 3 LA15 P AFE7225 RESET Connects to AFE7225 RESET LA16 N AFE7225_CS Connects to AFE7225 SEN LA16_P AFE7225 PD Connects to AFE7225 PDN LA17 N CC RF ATT V4 Connects to SKY12329 350LF V4 LA17 P CC RF ATT V3 Connects to SKY12329 350LF V3 LA18 N CC AMC7823_CS Connects to AMC7823 SS LA18 P CC AMC7823_RESET Connects to AMC7823 RESET LA19_N CDCE62005_LOCK Connects to CDCE62005 PLL_LOCK LA19 P TRF3765 LOCK Connects to TRF3765 LD LA20 N RF ATT V5 Connects to SKY12329 350LF V5 LA20 P TRF3720 LOCK Connects to TRF3720 LD LA21 N SCLK Connects to CDCE62005 SPI CLK TRF3765 CLOCK TRF3720 CLK TRF3711 CLOCK AFE7225 SCLK AMC7823 SCLK LA21 P TRF3720_CS Connects to TRF3720 LE LA22 N RX VCO CTRL Behavior on RX CLK connector 0 RX CLK connector is VCO output from TRF3765 LO4 OUT 1 RX CLK connector is VCO input to TRF3765 EXTVCO IN LA22 P TRF3720 PS Connects to TRF3720 PS LA23 N TX VCO CTRL Behavior on TX CLK connector 0 TX CLK connector is VCO output from TRF3720 LO OUT 1 TX CLK connector is VCO input to TRF3720 EXT VCO LA23 P TRF3711_PD Connects to TRF3711 CHIP_EN LA24 N TRF3711_CS Connects to TRF3711 STROBE LA24 P SDATA Connects to CDCE62005 MOSI TRF3765 DATA TRF3720 DATA TRF3711 DATA AFE7225 SDATA AMC7
4. LAO1 N CC ADC FCLKOUT N Connects to AFE7225 LAO1 P CC ADC FCLKOUT P Connects to AFE7225 LAO2 N ADCB DATA1 N Connects to AFE7225 LAO2 P ADCB DATA P Connects to AFE7225 LAOS N ADCB DATAO N Connects to AFE7225 LAOS P ADCB DATAO P Connects to AFE7225 LA04_N ADCA_DATA1_N Connects to AFE7225 LA04_P ADCA_DATA1_P Connects to AFE7225 LAO5_N ADCA DATAO N Connects to AFE7225 LAO5 P ADCA DATAO P Connects to AFE7225 LAO6 N DAC FCLKIN N Connects to AFE7225 LAO6 P DAC FCLKIN P Connects to AFE7225 LAO7 N DACA DATA1 N Connects to AFE7225 LAO7 P DACA DATA1 P Connects to AFE7225 LAO8 N DACA DATAO N Connects to AFE7225 LAO8 P DACA DATAO P Connects to AFE7225 LAO9 N DACB DATAO N Connects to AFE7225 LAO9 P DACB DATAO P Connects to AFE7225 LA10 N DAC DCLKIN N Connects to AFE7225 LA10 P DAC DCLKIN P Connects to AFE7225 LA11 N DAC SYNCIN N Connects to AFE7225 LA11 P DAC SYNCIN P Connects to AFE7225 LA12 N DACB DATA1 N Connects to AFE7225 LA12 P DACB DATA1 P Connects to AFE7225 LA13 N LNA BYPASS CTRL 0 2 LNA is excluded from the RX path 1 2 LNA is included in the RX path LA13_P TRX_SWITCH_CTRL Behavior on RF I O connector 0 RF I O connector is receiving RX T RF I O connector is transmitting TX Behavior on RF IN connector 0 RF IN connector is disconnected T RF IN connector is receiving RX LA14_N RF_ATT_V1 Connects to SKY12329 350LF V1 LA14_P RF_ATT_V2 Connects to SKY12329 350LF V2
5. FMC30RF User Manual et SEH r1 3 9 Safety This module presents no hazard to the user 10 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system 11 Ordering information Part Number FMC3ORF 2 1 1 1 Card Type FMC30RF Temperature Range Industrial 40 C to 85 C 1 Commercial 0 C to 70 C 2 Connector Type Standard Feature MMCX snap coupling 1 SSMC screw coupling 2 RF coverage 400MHz 1200MHz 1 1200MHz 3000MHz 2 Mil I 46058c Conformal Coating No Conformal Coating 1 Add Conformal Coating 2 12 Warranty Basic Warranty 1 Year from Date of Shipment 90 Days from Date of Shipment included Extended Warranty 2 Years from Date of Shipment 1 Year from Date of Shipment optional UMO015 www 4dsp com 16 Appendix A LPC pin out FMC30RF FMC label FMC30RF Signal Description CLKO_M2C_N CLK_TO_FPGA_N Output from CDCE62005 CLKO_M2C_P CLK_TO_FPGA_P Output from CDCE62005 LAO0 N CC ADC DCLKOUT N Connects to AFE7225 LAO0 P CC ADC DCLKOUT P Connects to AFE7225
6. VCO IN rT 9 TRF372017 TX LO OUT ple r TX CLK pM BEA Md TX VCO CTRL AFE7225 LNA BYPASS CTRL eA RFO TRF371109 RE Le zl TRF371125 RF IN P8 LO FMC A LNA_OUT TRX_SWITCH_CTRL LPC not avalable from front panel RX VCO IN TRF3765 RXLOOUT ole 9 Rok REF RX VCO CTRL ie I CDCE65005_REFEN bg SEC HEE REF OUT CDCE62005 FRLREF d E REF IN Figure 5 Signal Path 5 1 Time Division Duplex TDD The FMC30RF supports TDD using the RF I O connector The RF I O connector is either receiving TRX SWITCH CTRL 20 or transmitting TRX SWITCH CTRL 1 The TRX SWITCH CTRL signal should be driven by the FPGA trough the FMC connector 5 2 Frequency Division Duplex FDD The FMCS3ORF supports FDD using the RF I O connector for transmitting and the RF IN connector for receiving The TRX SWITCH CTRL signal should be driven high by the FPGA trough the FMC connector 5 3 Multiple Input Multiple Output MIMO With two FMCS3ORF boards a 2x2 MIMO setup can be realised UMO015 www 4dsp com 10 FMC30RF User Manual LE gt r1 3 REF TX VCO IN __ TRF372017 DLO OUTS Fg LO TX_VCO_CTRL AFE7225 LNA_BYPASS CTRL i lee RF I O TRF371109 are I Jm TRF371125 t T RFN 1 I2 j LO FMC TRX SWITCH CTRL
7. m 15 8 3 2 Conduction coollg i rtp RAE RO MERE pIA RM ENEE O REISEN MM BUE U EM ERNE EEEE 15 EE 2i eem 16 MEI cm s EARE 16 EE uenerit OUR 16 12 Waranty ee B Ce 16 UM015 www 4dsp com 3 FMC30RF User Manual ef SEH Appendix A LPC pin out FMC30ORP eeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeeeeeeenneees 1 Acronyms and related documents 1 4 Acronyms ADC DDR DoubleDataRate Cd FMC LED LSB Least Significant Bit s MGT MSB Most Significant Bit s PCB PLL Table 1 Glossary 1 2 Related Documents FPGA Mezzanine Card FMC standard ANSI VITA 57 1 2010 CDCE62005 datasheet TI August 201 1 TRF3765 datasheet Tl November 201 1 TRF371109 datasheet TI May 2011 TRF371125 datasheet Tl December 2010 TRF372017 datasheet TI August 2010 AMC7823 datasheet TI January 2010 UM015 www 4dsp com FMC30RF User Manual LJE gt r1 3 2 General description The FMC30RF is an FMC Daughter Card which is fully compliant with the VITA 57 1 2010 standard The FMC30RF offers in a small footprint a low power and fully featured Rx Tx signal path for the development and deployment of advanced RF solutions With a frequency range coverage from 400MHz to 3 0GHz two ranges and up to 60MHz bandwidth the FMC30RF provides flexibility and reconfigurability to a host of applications Based on Texas Instruments RF technology the FMC30RF
8. 3dBm Maximum Input Level RF OUT LO Range 300MHz 4800MHz Bandwidth 70MHz tA O Output Impedance Full Scale Maximum Output Level 3dBm depending on LO frequency Receiver LO RX CLK Programmable trough fractional PLL TRF3765 Output Frequency Range 300MHz to 4800MHz Cn S Output Impedance Output Level 0 5dBm typ Input Frequency Range 300MHz to 4800MHz Input Impedance High impedance OdBm Input Level Transmitter LO TX CLK Programmable trough fractional PLL TRF372017 Output Frequency Range 300MHz to 4800MHz Cn S Output Impedance Output Level 0 5dBm typ Input Frequency Range 300MHz to 4800MHz Input Impedance High impedance Input Level OdBm External Reference Input REF IN Input Level 0 2Vpp 3 3Vpp 10MHz 250MHz Input Frequency nn O Input Impedance External Reference Output REF OUT Output Level 3 3Vpp AC coupled LVCMOS Output Frequency 10MHz 250MHz Table 2 FMC30RF daughter card main characteristics Make sure minimum gain is configured refer to section 4 2 4 UMO015 www 4dsp com 9 FMC30RF User Manual ef SEH r1 3 5 Modes of operation The FMCS3ORF support different modes of operation TDD and FDD REF la TX
9. 62005_SYNC e CDCE62005_LOCK e CDCE62005_REFEN Refer to Appendix A for a description of these signals 6 3 Guidelines for controlling the TRF3765 The following control signals connect from the FMC connector to the TRF3765 e SCLK shared with other devices e SDATA shared with other devices e TRF3765 CS e TRF3765 SDOUT e TRF3765 LOCK e RX_VCO_CTRL Refer to Appendix A for a description of these signals 6 4 Guidelines for controlling the TRF3711 The following control signals connect from the FMC connector to the TRF3711 e SCLK shared with other devices e SDATA shared with other devices e TRF3711_CS e TRF3711 SDOUT e TRF3711 PD e TRF3711 GAIN BJ O 2 Refer to Appendix A for a description of these signals 6 5 Guidelines for controlling the TRF3720 The following control signals connect from the FMC connector to the TRF3720 e SCLK shared with other devices e SDATA shared with other devices e TRF3720_CS e TRF3720 SDOUT e THRF3720 PS e TRF3720 LOCK e TX VCO CTRL Refer to Appendix A for a description of these signals 6 6 Guidelines for controlling the AFE7225 The following control signals connect from the FMC connector to the AFE7225 e SCLK shared with other devices e SDATA shared with other devices e AFE7225 CS UMO015 www 4dsp com 12 FMC30RF User Manual et SEH r1 3 e AFE7225 SDOUT e AFE7225 RESET e AFE7225 PD Refer to Appendix A for a description of these signals 6 7 Guidelines for controlling
10. 8001 201mA 5 5V gt 4 0V TPS7A8001 360mA 5 5V gt 5 0V RF_4p0 TRF3711_5p0 FMCSORF User Manual r1 3 Power plane Typical Maximum VADJ 100mA 200mA 3P3V 1 3A 1 6A 12P0V 0 5A 0 6A 3P3VAUX Operating 0 1 mA 3mA 3P3VAUX Standby 0 01 pA 1 uA Table 4 Typical Maximum current drawn from FMC carrier card 5 5V 3 8V 14A 3 3V 5563020 0 754 3 3V gt 5 5V 0 5A 12V_ Tpg5430 1 30A 12V gt 3 8V Do VoD 1p8 Dom VOD 1p8 i TPS7A8001 40mA 5VOA DAC Typical power SNZ SON consumption P Te V3A DAC 10 Watt TPS7A800 580mA CDCE 3p3 oe TCKO ap Figure 7 FMC30RF Power Supply Architecture 8 Environment 8 1 Temperature Operating temperature e 40 C to 85 C Industrial TPS74401 148mA 5 5V gt 5 0V TPS74401 250mA 3 8V gt 3 3V TPS74401 190mA 3 8V gt 3 3V TRF3720 5p0 TRF3720 3p3 TRF3765 3p3 UMO015 www 4dsp com 14 FMC30RF User Manual et SEH r1 3 Storage temperature e 40 C to 120 C 8 2 Monitoring The AMC7823 device may be used to monitor the voltage on the different power rails as well as the temperature It is recommended that the carrier card and or host software uses the power down features in the devices in the case the temperature is too high Normal operations can resume once the temperature is within the operating conditions boundaries Parameter Voltage Formula Channel 0 5 0V Analog DAC 2 ADCO Channel 1 3 3V Digital C
11. 823 MOSI LA25 N TRF3711 GAIN BO Connects to TRF3711 GAIN BO LA25 P TRF3711 GAIN B1 Connects to TRF3711 GAIN B1 LA26 N CDCE62005 REFEN Behavior on on board reference clock 0 the on board reference clock is powered down the on board reference clock is enabled LA26 P TRF3711 GAIN B2 Connects to TRF3711 GAIN B2 LA27 N CDCE62005 SDOUT Connects to CDCE62005 MISO LA27 P AFE7225 SDOUT Connects to AFE7225 SDOUT LA28 N CDCE62005 PD Connects to CDCE62005 POWER DOWN LA28 P CDCE62005 SYNC Connects to CDCE62005 SYNC LA29 N TRF3720 SDOUT Connects to TRF3720 RDBK UM015 www 4dsp com 18 DE FMC3ORF User Manual r1 3 LA29_P TRF3711_SDOUT Connects to TRF3711 READBACK LA30_N AMC7823 SDOUT Connects to AMC7823 MISO LA30 P CDCE62005_CS Connects to CDCE62005 SPI_LE LA31_N AMC7823_GALR Connects to AMC7823 GALR LA31_P TRF3765_SDOUT Connects to TRF3765 READBACK LA32_N Not connected LA32_P Not connected LA33_N Not connected LA33_P Not connected PRSNT_M2C_L PRSNT_M2C_L Connects to GND PG_C2M PG_C2M Connects to PS_EN UM015 www 4dsp com 19
12. FMC30RF User Manual et SEH r1 3 FMC30RF User Manual it 4DSP LLC USA Email support 4dsp com This document is the property of 4DSP LLC and may not be copied nor communicated to a third party without the written permission of 4DSP LLC 4DSP LLC 2015 FMC30RF User Manual et SEH r1 3 Revision History 2012 05 30 Release after review 2012 10 05 Additional info on LNA and reference oscillator 2014 06 11 Update voltage monitoring section Additional info in Figure 5 and pin out 2015 02 12 Added RF input analog line up description updated RF in out characteristics UMO015 www 4dsp com 2 FMCSORF User Manual r1 3 Table of Contents 1 Acronyms and related documents eseeeeeeeeeeeeeeeeeennnnennnnnnnnn nnn 4 DOEME Cod mE 4 1 2 Related DOWD sc sacra onis diee nce cede usce lm d eR omae erai dudit 4 2 General lin mec M 5 XB Sc cO EEUU 5 3 1 Requirements and handling instructions seseessee 5 EE eee 6 4 1 Phycisal specifications 5 35 90m 9 2086 0 9500 00 m i POE IND HETUE 6 41 1 Board DIMENSIONS aun iiit compiti uisus ati e usse iin wap uius Deci pu 6 4 1 2 Front panel coax INDUS uei noatra egeta up etre dui iie tue obti iile EE 6 4 2 Electrical epa e 6 cere eee nee eee er pitt iii arene eee ener rae ee ee ere IE 6 421 dg eee ee TE 7 scr an oc 7 4 2 3 Uere 0 12 0118 ERES m
13. comprises of a dual DAC Tx IQ modulator a dual ADC Rx IQ demodulator with PGA and LNA front end and on board clocking with integrated PLL VCO The FMC30RF allows flexible control on sampling frequency through serial communication busses Furthermore the card is equipped with power supply and temperature monitoring and offers several power down modes to switch off unused functions REF TX VCO IN ra M __ TRF372017 TXLOOUT QI vt ue cc TX_VCO_CTRL AFE7225 LNA BYPASS CTRL lee RF I O TRF371109 FA S Fe if eH s TRF371125 le T we RF IN t a LO FMC A LNA OUT TRX_SWITCH_CTRL LPC not avalable from front panel TRF3765 REF RX VCO IN RX LO OUT ple RX CLK RX_VCO_CTRL TCXO 30 72MHz Lag SEC_REF REF OUT CDCE62005 PRLREF a REF IN Figure 1 FMC30RF block diagram CDCE65005 REFEN 3 Installation 3 1 Requirements and handling instructions e The FMC30RF daughter card must be installed on a carrier card compliant to the FMC standard e The FMC carrier card must support the low pin count connector LPC 160 pins High pin count is permitted e The FMC carrier card must support VADJ VIO B voltage between 1 65V and 5 5V e Do not flex the card an
14. d prevent electrostatic discharges by observing ESD precautions when handling the card UMO015 www 4dsp com 5 FMC30RF User Manual a SE r1 3 4 Design 4 1 Phycisal specifications 4 1 1 Board Dimensions The FMC30RF card complies with the FMC standard known as ANSI VITA 57 1 The card is a single width conduction cooled mezzanine module with region 1 and front panel I O A front rib on the carrier hardware is not supported The stacking height is 10mm z le 1 58mm 9k19 88mm gt 61 78mm aad o T 2 amm T 1 1 99 21 Sle aal mae REF IN RX CLK af RFN Tel pia ald y m REF OUT B51 00mm B8 00mm NEC Ee sax m Sma Sere T in Oe 9 a DTE m Ly 3 30mm Ri RF VO E 27 10mm gt 56 9mm Figure 2 FMC30RF dimensions 4 1 2 Front panel coax inputs The FMC30RF can be ordered with MMCX or SSMC connector type Six connectors are available on the front panel Figure 3 FMC30RF bezel layout 4 2 Electrical specifications The FMC30RF card uses a mix of LVDS and LVCMOS signals According to the FMC standard VADJ should be 2 5V to support LVDS but the FMCS3ORF is designed to accept any level on VADJ ranging between 1 65V and 5 5V VIO B M2C connections are connected to VADJ on the FMC30RF Level translators are implemented to guarantee VADJ level on the FMC connector for all single e
15. lock 2 ADC1 Channel 2 1 8V Analog Digital 2 ADC2 Channel 3 4 0V RF 2 ADC3 Channel 4 5 0V Analog 2 ADC4 Channel 5 3 3V Analog 2 ADC5 Channel 6 3 3V TCXO 2 ADC6 Channel 7 VADJ 2 ADC7 Temperature Ch 8 Table 5 Temperature and voltage parameters 8 3 Cooling Two different types of cooling will be available for the FMC30RF 8 3 1 Convection cooling The air flow provided by the chassis fans the FMCS3ORF is enclosed in will dissipate the heat generated by the on board components A minimum airflow of 300 LFM is recommended For stand alone operations such as on a Xilinx development kit it is highly recommended to blow air across the FMC and ensure that the temperature of the devices is within the allowed range 4DSP s warranty does not cover boards on which the maximum allowed temperature has been exceeded 8 3 2 Conduction cooling In demanding environments the ambient temperature inside a chassis could be close to the operating temperature defined in this document It is very likely that in these conditions the junction temperature of power consuming devices will exceed the operating conditions recommended by the devices manufacturers mostly 85 C The FMC30RF is designed for maximum heat transfer to conduction cooled ribs A customized cooling frame that connects directly to the surface of the devices is allowed contact 4DSP for detailed mechanical information UMO015 www 4dsp com 15
16. nded communication and control signals UMO015 www 4dsp com 6 FMC30RF User Manual a SEH r1 3 4 2 1 EEPROM The FMC30RF card carries a 2Kbit EEPROM 24LC02B which is accessible from the carrier card through the IC bus The EEPROM is powered by 3P3VAUX The standby current is only 0 01HA when SCL and SDA are kept at 3PSVAUX level These signals may also be left floating since pull up resistors are present on the card 4 2 2 JTAG The FMCSORF card TDO pin is connected to the TDI pin through an SN74LVC1G126 buffer to ensure continuity of the JTAG chain TCK TMS and TRST are left unconnected on the FMC30RF 4 2 3 FMC connector The low pin count connector has only bank LA available and two dedicated LVDS clock pairs The recommendations from AV57 1 2010 Table 14 have been taking into account resulting in the following arrangement e The ADC data clock pair ADC DCLKOUT and ADC frame clock pair ADC FCLKOUT are connected to clock capable pins LAO0 CC and LAO1 CC respectively The ADC data pairs are mapped to LAO2 to LAO5 e The DAC clock frame and data pairs are mapped to LAO6 to LA12 Since all pairs are outputs as seen from the FPGA there is no need to have the clock and frame pair on clock capable pins e LA13 to LA31 are used for low speed single ended communication and control signals e The remaining connections LA32 LAS33 are used left unconnected e An LVDS output of the CDCE62005 is connected to a dedicated LVDS con
17. nections on the FMC CLKO_M2C The other dedicated LVDS connection is not used Refer also to the appendix for the detailed LPC connector pinout 4 2 4 RF input The RF input circuit comprises tuneable and fixed gain stages The analog line up is depicted in Figure 4 LNA BYPASS CTRL 3 e RF I O TRF371109 e Le ew AFE7225 TRE371125 ANT ES ele RF IN f A 4 in LNA2 LNA1 pod 18dB 18dB 24dB ATT 1dBto SW3 Sw2 swi 32dB 0 5dB 0 5dB 0 5dB Figure 4 RF input analog line up UMO015 www 4dsp com 7 FMC30RF User Manual a SEH r1 3 Guidelines of controlling tuneable gain and attenuators are provided in section 6 The maximum input level at the RF input is 3dBm and can be applied to the board when the total gain of the analog line up is set to minimum This is done by Bypass LNA2 Set the stepped attenuator to 32dB attenuation Set the BB gain of the TRF3711 to OdB default setting is 15dB refer to the datasheet of the TRF3711 Applying a signal of 3dBm to the first stage LNA drives the LNA close to its input 1dB compression point UMO015 www 4dsp com 8 FMC30RF User Manual a SEH r1 3 4 3 Main characteristic RF IN Low range option 400MHz 1200MHz LO Range High range option 1200MHz 3000MHz Bandwidth 60MHz when LPF in TRF3711xx bypassed tA c O Input Impedance
18. the AMC7823 The following control signals connect from the FMC connector to the AMC7823 e SCLK shared with other devices e SDATA shared with other devices e AMC7823_CS e AMC7823_SDOUT e AMC7823_GALR e AMC7823_RESET Refer to Appendix A for a description of these signals 7 Power supply Power is supplied to the FMC30RF card through the FMC connector The pin current rating is 2 7A but the overall maximum as specified by the FMC standard is limited according to Table 3 Voltage pins Max Amps Max Watt 3 3V 4 3A 10 W 12V 2 1A 12W VADJ 2 5V 4 4A 10 W VIO B 2 5V 2 1 15 A 2 3 W Table 3 FMC standard power specification The power provided by the carrier card can be very noisy Special care is taken with the power supply generation on the FMC30RF card to minimize the effect of power supply noise on clock generation de modulation and data conversion Clean supply is derived from 3 3V and 12V in two steps for maximum efficiency The first step uses a high efficient switched regulators to generate 3 8V and 5 5V power rails From these power rail the analog and digital supplies are derived with a low dropout low noise high PSRR linear regulator At several stages in the power supply there is additional noise filtering with beads and capacitance Power supplies for different devices are isolated where necessary UMO015 www 4dsp com 13 DE TPS7A
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