V850ES/Sx1, V850ES/Sx2, V850ES/Sx3 Microcontrollers Usage
Contents
1. 4 Document revision history Document Number ZBG BF 05 0004 July 8 2005 1st edition Restriction nos 1 and 2 ZBG BF 09 0015 November 9 2009 Restriction no 3 ZBG BF 09 0015 Attachment 1 1 1 V850ES Sx1 V850ES Sx2 and V850ES Sx3 Microcontrollers Y V850ES SG1 UPD703249Y uwPD703252Y uPD703253Y Y V850ES SG2 UPD703260 Y uPD703261 Y uPD703262 Y PD703263 Y PD70F3261 Y UPD70F3263 Y uPD703270 Y PD703271 Y uPD703272 Y uPD703273 Y UPD70F3271 Y uPD70F3273 Y uPD703280 Y PD703281 Y PD703282 Y UPD703283 Y uPD70F3281 Y uPD70F3283 Y uPD703262HY PD703263HY UPD70F3263HY PD703272HY uPD703273HY uPD70F3273HY uPD703282HY UPD703283HY uPD70F3283HY Y V850ES SJ2 UPD703264 Y uPD703265 Y u PD703266 Y u PD70F3264 Y uPD70F3266 Y UPD703274 Y uPD703275 Y uPD703276 Y uPD70F3274 Y uPD70F3276 Y UPD703284 Y uPD703285 Y PD703286 Y uPD703287 Y uPD703288 Y UPD70F3284 Y u PD70F3286 Y uPD70F3288 Y PD703265HY uwPD703266HY UPD70F3266HY PD703275HY wPD703276HY uwPD70F3276HY uPD703285HY UPD703286HY PD70F3286HY wPD703287HY uwPD703288HY uPD70F3288HY Y V850ES SG3 UPD70F 3333 uPD70F3334 uPD70F3335 uPD70F3336 uPD70F3340 uPD70F3341 UPD70F3342 uPD70F3343 uPD70F3350 wPD70F3351 uPD70F3352 uPD70F3353 Y V850ES SJ3 UPD70F3344 uwPD70F 3345 uPD70F3346 vPD70F3347 wPD70F3348 u PD70F3354 UPD70F3355 uPD70F 3356 PD70F3352. 4 1 2 3 Software Continuous select X y trigger Continuous scan V x Note 4 One shot select One shot scan Note 3 External Select x Note 4 timer trigger Scan Note 3 X Restriction applies V Restriction does not apply Not relevant Notes 1 For the timing details see the user s manual for each product 2 There are two types of reconversion trigger a Write to an A D conversion register ADA0M0 ADA0M2 ADA0S ADA0PFM or ADAOPFT b External trigger detection of the ADTRG pin s edge or timer trigger TMP2 compare match interrupt request signal Ifa reconversion trigger occurs during A D conversion the conversion is suspended and then restarts 3 This restriction applies if ADAOS 00H in scan mode 4 Either 2 or 3 occurs depending on the internal status when the end of conversion conflicts with the input of the reconversion trigger Workaround 1 If the external trigger or timer trigger is selected set high speed conversion mode Do not input a trigger during the stabilization time that is inserted only once after A D conversion is enabled ADAOCE bit 0 gt 1 2 Before writing to an A D control register conversion in high speed conversion mode stop A D conversion ADAOMO ADAOCE 0 and then enable A D conversion ADAOMO ADAOCE 1 Note in normal conversion mode or during one shot Note A D control register ADAOMO ADAOM2 ADA
3. the internal ROM or RAM ZBG BF 09 0015 3 4 Notes 1 This restriction applies if a different instruction is executed between the load instructions in 1 and 2 and the access by the instruction in 1 ends at the same time as the instruction in 2 accesses the internal RAM 2 For a mul or mulu instruction the operation described in this restriction occurs if ro is specified for the third operand reg3 or the same register is specified for the second operand reg2 and third operand reg3 as shown below mul reg1 reg2 reg3 reg3 r0 or reg2 reg3 mul imm9 reg2 reg3 reg3 r0 or reg2 reg3 mulu regl reg2 reg3 reg3 r0 or reg2 reg3 mulu imm9 reg2 reg3 reg3 r0 or reg2 reg3 For a program written in C the CA850 does not generate the mul and mulu instructions if the same register is specified for the reg2 and reg3 operands 3 This restriction applies if it takes 2 clock cycles or less between the instructions in 3 and 4 This restriction does not apply in any of the following cases An external bus and CAN controller are not used The data read by the load instruction in 1 is used to specify the target address of the load instruction in 2 The data read by the load instruction in 1 is referenced by an instruction executed between the instructions in 1 and 2 The data read by the load instruction in 2 is referenced by the multiplication instruction in 3 The data obtai
4. to add the above workaround The following table shows the version and release schedule for the C compiler package CA850 and the software package SP850 that includes the CA850 Product Name Current CA850 Version of CA850 Language Release Schedule Version After Upgrade SP850 V3 40 V3 42 Japanese November 9 2009 CA850 English November 9 2009 Action for already developed systems Use the interview sheet in attachment 3 to check whether the restriction applies Application of this restriction to embedded software products This restriction applies to NEC Electronics real time OSs and middleware as follows e Real time OSs RX850 The restriction does not apply RX850 Pro The restriction does not apply RX850V4 The restriction does not apply e Middleware GOFAST The restriction does not apply JPEG The restriction does not apply For products other than the above contact an NEC Electronics sales representative For third party products contact the vendor of the product Modification The device will not be corrected so regard this restriction as a specification Use the latest compiler to avoid this restriction 3 Development environment required to work around this restriction Use NEC Electronics compiler CA850 V3 42 or later Note that the outputs from the above version might differ from the outputs from the older versions If you are using another compiler contact an NEC Electronics sales representative
5. 7 u PD70F 3358 PD70F3364 uwPD70F3365 UPD70F3366 u PD70F3367 PD70F3368 ZBG BF 09 0015 Attachment 2 1 6 V850ES Sx1 V850ES Sx2 and V850ES Sx3 Microcontroller Usage Restrictions Restriction Nickname Product Development Environment in Which the Restriction Can Be Worked Around Restriction on continuous write V850ES SG1 All products access to WDTM2 register in V850ES SG2 watchdog timer 2 V850ES SJ2 Restrictions on rewriting to A D V850ES SG3 All products control register and external timer V850ES SJ3 trigger input during A D conversion Restriction on executing a mu1 or All products Category Compiler mulu instruction Product name CA850 Version V3 42 or later Note Whether or not the restriction applies Remark The meaning of each symbol for Note is as follows Restriction does not apply Restriction is already corrected Restriction applies correction is planned Restriction applies correction is not planned gt x O No 1 ZBG BF 09 0015 Attachment 2 2 6 Restriction on continuous write access to WDTM2 register in watchdog timer 2 Description When a write access is made to the WDTM2 register twice or more after a reset the CPU judges that the program is inadvertently looping and forcibly generates an overflow signal However an overflow signal cannot be generated during a continuous write to WDTM2 The overflow signal is generated after the c
6. Document No ZBG BF 09 0015 V850ES Sx1 V850ES Sx2 V850ES Sx3 Date issued November 9 2009 Microcontrollers Issued by Car Audio Solution Development Group Automotive Systems Division Usage Restrictions Microcomputer Operations Unit Related documents NEC Electronics Corporation V850ES SG1 Hardware User s Manual U17329EJ2V0UD00 2nd edition Notification y Usage restriction V850ES SG2 V850ES SG2 H Hardware User s Manual nics U16541EJ5V1UD00 5th edition Classification Upgrade V850ES SJ2 V850ES SJ2 H Hardware User s Manual Document modification U16603EJ5V1UD00 5th edition V850ES SG3 Hardware User s Manual U17728EJ3V1UD00 3rd edition V850ES SJ3 Hardware User s Manual U17790EJ3V1UD00 3rd edition V850ES Architecture User s Manual U15943EJ3VOUMOO 3rd edition Other notification 1 Affected products All V850ES Sx1 V850ES Sx2 and V850ES Sx3 microcontrollers For the names of the specific products in each series see attachment 1 2 Notification The following restriction for the V850ES Sx1 V850ES Sx2 and V850ES Sx3 microcontrollers has been found No 3 Restriction on executing a mul or mulu instruction Description The following occur if a specific instruction sequence sequence 1 or 2 below is executed e The result of executing a multiplication instruction is not stored in the relevant general purpose register e Asaresult of executing an 1d instruction for a m
7. OS ADAOPFT and ADAOPFM registers ZBG BF 09 0015 Attachment 2 4 6 No 3 Restriction on executing a mu1 or mulu instruction Description The following occur if a specific instruction sequence sequence 1 or 2 below is executed The result of executing a multiplication instruction is not stored in the relevant general purpose register As a result of executing an 1d instruction for a mis aligned address the data at an incorrect address is read and stored in the relevant general purpose register Sequence 1 In the following instruction sequence the RAM is read by one of the instructions in 2 at the same time as the RAM is accessed by a DMA transfer 1 1 2 3 4 dorsld A load instruction for the internal ROM ldorsid A load instruction for the internal RAM mul or mulu An instruction that multiplies word data and whose result is truncated to 32 bits Rote 1 Note 2 1dorsl1ld A load instruction for a mis aligned address in the internal ROM or RAM Notes 1 For a mul or mulu instruction the operation described in this restriction occurs if ro is specified for the third operand reg3 or the same register is specified for the second operand reg2 and third operand reg3 as shown below mul regi reg2 reg3 reg3 r0 or reg2 reg3 mul imm9 reg2 reg3 reg3 r0 or reg2 reg3 mulu regl reg2 reg3 reg3 r0 or reg2 reg3 mulu imm9 reg2 reg3 reg3 r0 or reg2 reg3 F
8. RAM using DMA Yes No Not relevant 2 An on chip CAN controller is used LI Yes No Not relevant 3 An external bus interface is used O Yes No Not relevant ZBG BF 09 0015 Attachment 3 2 2 e Second judgment Judgment based on compiling conditions Interview Sheet for second judgment Use the following flowchart to judge whether the restriction applies If the restriction might apply a third judgment using check tools is required Yes Check both the assembly source and C source Checking the assembly source C source Is amul or mulu instruction used in the source code Yes Go to third judgment using check tools Restriction does not apply Be sure to also check the C source according to the procedure following in this flowchart If the restriction is not judged to apply to either assembly or C the restriction does not apply to your code Use the check tool for hex objects When executing the check tool specify the Missalign y option Be sure to also check the C source according to the procedure following in this flowchart Note 1 When using the CA850 The restriction might apply if either the following conditions is satisfied No Restriction does not apply 1 pragma pack 1 or pragma pack 2 is specified in the source code 2 Xp
9. ack 1 or Xpack 2 is specified as a compiler option Note 2 When using a GHS compiler The restriction might apply if either the following conditions is satisfied 1 pragma pack 1 or pragma pack 2 is specified in the source code and misalign_pack is specified as a compiler option 2 pack 1 or pack 2 and misalign_pack are specified as compiler options Checking the Is structure packing specified Note 2 Use the check tool for the assembly list When executing the char ptr_char abcdef check tool specify int data ptr_int the Missalign Y p option ptr_int int ptr_char 2 data ptr_int Is the source code available and is the CA850 or a GHS compiler used Go to third judgment No using check tools Use the check tool for hex objects When executing the check tool specify the Missalign Y Yes Is there assembly option code No Is accessing a mis 7 aligned address specified qaman end intentionally in the C Yes check tools source Note 3 Use the check tool for the assembly list When executing the check tool specify the Missalign Y option No Is the compiler CA850 made by NECEL used Yes CA850 No GHS compiler Is structure packing at compile time specified Note 1 2 at compile time No Res
10. ction in 1 ends at the same time as the instruction in 2 accesses the internal RAM 1 1dorsid A load instruction for an external memory or a CAN peripheral I O register Note 1 2 1dorsid A load instruction for the internal RAM 3 mul or mulu An instruction that multiplies word data and whose result is truncated to 32 bits Note 2 Note 3 4 ldorsid A load instruction for a mis aligned address in the internal ROM or RAM Notes 1 This restriction applies if a different instruction is executed between the load instructions in 1 and 2 and the access by the instruction in 1 ends at the same time as the instruction in 2 accesses the internal RAM For a mul or mulu instruction the operation described in this restriction occurs if ro is specified for the third operand reg3 or the same register is specified for the second operand reg2 and third operand reg3 as shown below mul reg1 reg2 reg3 reg3 r0 or reg2 reg3 mul imm9 reg2 reg3 reg3 r0 or reg2 reg3 mulu regl reg2 reg3 reg3 r0 or reg2 reg3 mulu imm9 reg2 reg3 reg3 r0 or reg2 reg3 For a program written in C the CA850 does not generate the mul and mulu instructions if the same register is specified for the reg2 and reg3 operands This restriction applies if it takes 2 clock cycles or less between the instructions in 3 and 4 This restriction does not apply in any of the following cases e Anexternal b
11. e data read by the load instruction in 1 is used to specify the target address of the load instruction in 2 The data read by the load instruction in 2 is referenced by the multiplication instruction in 3 The data obtained by the multiplication instruction in 3 is used to specify the target address of the load instruction in 4 The data obtained by the multiplication instruction in 3 is referenced by an instruction executed between the instructions in 3 and 4 At least one of the following instructions is executed between the instructions in 3 and 4 gt A multiplication instruction mul mulh mulhi mulu gt Abit manipulation instruction clr1 not1 set1 tst1 gt A special instruction callt dispose switch The instruction in 4 is a load instruction that accesses the memory in bytes 1d b 1d bu sld b or sld bu The instructions in 1 to 4 are located in an external memory or the internal RAM Sequence 2 In the following instruction sequence access by the instruction in 1 ends at the same time as the instruction in 2 accesses the internal RAM 1 ldorsid A load instruction for an external memory or a CAN peripheral I O register 2 1 3 mul or mulu An instruction that multiplies word data and whose result is truncated to 32 bits Note 1 dorsid A load instruction for the internal RAM Note 2 Note 3 4 ldorsid A load instruction for a mis aligned address in
12. is aligned address the data at an incorrect address is read and stored in the relevant general purpose register Sequence 1 In the following instruction sequence the RAM is read by one of the instructions in 2 at the same time as the RAM is accessed by a DMA transfer 1 1dorsid A load instruction for the internal ROM 2 1dorsid A load instruction for the internal RAM 3 mul or mulu An instruction that multiplies word data and whose result is truncated to 32 bits ote 1 Note 2 4 ldorsid A load instruction for a mis aligned address in the internal ROM or RAM ZBG BF 09 0015 2 4 Notes 1 For a mul or mulu instruction the operation described in this restriction occurs if ro is specified for the third operand reg3 or the same register is specified for the second operand reg2 and third operand reg3 as shown below mul reg1 reg2 reg3 reg3 r0 or reg2 reg3 mul imm9 reg2 reg3 reg3 r0 or reg2 reg3 mulu reg1 reg2 reg3 reg3 r0 or reg2 reg3 mulu imm9 reg2 reg3 reg3 r0 or reg2 reg3 For a program written in C the CA850 does not generate the mu1 and mu1u instructions if the same register is specified for the reg2 and reg3 operands 2 This restriction applies if it takes 2 clock cycles or less between the instructions in 3 and 4 This restriction does not apply in any of the following cases DMA is not used to transfer data to or from the internal RAM Th
13. me have elapsed when the A D converter is using an external or timer trigger conversion starts jNote1 at the same time In normal conversion mode if an A D conversion ends prior to the wait time Note 2 as a reconversion trigger is input the conversion that should restart does not restart and conversion ends while A D conversion remains enabled ADAOCE 1 and A D conversion is running ADAOMO ADAOEF 1 No A D conversion end interrupt occurs and the conversion result is not stored Note 2 If a reconversion trigger occurs in this state conversion starts again 4 In high speed conversion mode and software conversion start trigger mode if one shot select conversion or one shot scan conversion ends Note 1 Note 2 when a reconversion trigger is input the conversion that should restart does not restart and conversion ends while A D conversion remains enabled ADAOCE 1 but is stopped ADAOMO ADAOEF 0 No A D conversion end interrupt occurs and the conversion result is not stored In this state if 1 is written to the ADAOCE bit or if A D conversion is stopped ADAOCE 1 0 and then enabled again ADAOCE 0 gt 1 conversion starts again ZBG BF 09 0015 Attachment 2 3 6 Correspondence Between A D Converter Operation Mode and Restriction Conversion Conversion Mode High Speed Conversion Mode Normal Conversion Mode Trigger Without Intermittent Operation with Intermittent Operation 1
14. ned by the multiplication instruction in 3 is used to specify the target address of the load instruction in 4 The data obtained by the multiplication instruction in 3 is referenced by an instruction executed between the instructions in 3 and 4 At least one of the following instructions is executed between the instructions in 3 and 4 gt A multiplication instruction mul mulh mulhi mulu gt Abit manipulation instruction clr1 not1 set1 tst1 gt A special instruction callt dispose switch The instruction in 4 is a load instruction that accesses the memory in bytes 1d b 1d bu s1d b or sld bu The instructions in 1 to 4 are located in an external memory or the internal RAM Workaround Action for systems being developed and to be developed in future We regard this as a restriction related to the CPU s features and do not intend to correct the microcontroller Instead the CA850 compiler will be modified to automatically prevent instructions to which this restriction applies from being generated This workaround does not work for instructions in assembly code so the CA850 outputs a message for such instructions How NEC Electronics will provide the update for the compiler is shown below If you are using another compiler contact an NEC Electronics sales representative ZBG BF 09 0015 4 4 e f your compiler is the NEC Electronics compiler CA850 The CA850 will be upgraded
15. ontinuous write is suspended Workaround Do not write to the WDTM2 register three times or more immediately after a reset until the next reset is applied No 2 Restrictions on rewriting to A D control register and external timer trigger input during A D conversion Description 1 After A D conversion is enabled if a reconversion trigger is input 2 at the same time as the 3 stabilization time 1 for A D converter setup ends the stabilization time is inserted again for 64 clock cycles Furthermore if the reinserted stabilization time ends at the same time as another reconversion trigger is input the stabilization time will be inserted again Although the stabilization time is inserted again conversion ends normally Note 2 In normal conversion mode if a reconversion trigger is input at the same time as conversion in one shot select conversion mode or external timer trigger select conversion mode ends prior to the wait time 1 A D conversion remains enabled ADAOCE 1 but is stopped ADAOMO ADAOEF 0 No A D conversion end interrupt occurs and the conversion result is not stored the conversion that should restart does not restart and conversion ends while To continue A D conversion in one shot select conversion mode A D conversion must be stopped ADAOCE 1 gt 0 and then enabled ADAOCE 0 gt 1 If the selected trigger signal is input and the wait time and stabilization ti
16. or a program written in C the CA850 does not generate the mul and mulu instructions if the same register is specified for the reg2 and reg3 operands 2 This restriction applies if it takes 2 clock cycles or less between the instructions in 3 and 4 This restriction does not apply in any of the following cases DMA is not used to transfer data to or from the internal RAM The data read by the load instruction in 1 is used to specify the target address of the load instruction in 2 The data read by the load instruction in 2 is referenced by the multiplication instruction in 3 The data obtained by the multiplication instruction in 3 is used to specify the target address of the load instruction in 4 The data obtained by the multiplication instruction in 3 is referenced by an instruction executed between the instructions in 3 and 4 At least one of the following instructions is executed between the instructions in 3 and 4 gt A multiplication instruction mul mulh mulhi mulu gt Abit manipulation instruction clr1 not1 set1 tst1 gt A special instruction callt dispose switch ZBG BF 09 0015 Attachment 2 5 6 e The instruction in 4 is a load instruction that accesses the memory in bytes 1d b 1d bu s1d b or sld bu e The instructions in 1 to 4 are located in an external memory or the internal RAM Sequence 2 In the following instruction sequence access by the instru
17. rkaround does not work for instructions in assembly code so the CA850 outputs a message for such instructions How NEC Electronics will provide the update for the compiler is shown below If you are using another compiler contact an NEC Electronics sales representative e If your compiler is the NEC Electronics compiler CA850 The CA850 will be upgraded to add the above workaround The following table shows the version and release schedule for the C compiler package CA850 and the software package SP850 that includes the CA850 Product Name Current CA850 Version of CA850 Language Release Schedule Version After Upgrade SP850 V3 40 V3 42 Japanese November 9 2009 CA850 English November 9 2009 ZBG BF 09 0015 Attachment 3 1 2 No 3 Restriction on executing a mu1 or mulu instruction e First judgment Judgment based on product usage conditions Check the conditions under which you are using the product to see whether the restriction applies to the product If the restriction might apply perform a second judgment If the restriction is judged to be not applicable subsequent checking is not necessary Checking the usage conditions Select Yes or No for whether each feature from 1 to 3 below is used If the product does not incorporate a feature select Not relevant for the feature If there is no item for which Yes is selected the restriction does not apply 1 Data is not transferred to or from the internal
18. triction does not apply Yes Yes Note 3 A mis aligned address might be accessed if a pointer to a char is cast to a pointer to an int to reference the int as shown below Go to third judgment using check tools func l
19. us and CAN controller are not used e The data read by the load instruction in 1 is used to specify the target address of the load instruction in 2 e The data read by the load instruction in 1 is referenced by an instruction executed between the instructions in 1 and 2 e The data read by the load instruction in 2 is referenced by the multiplication instruction in 3 e The data obtained by the multiplication instruction in 3 is used to specify the target address of the load instruction in 4 e The data obtained by the multiplication instruction in 3 is referenced by an instruction executed between the instructions in 3 and 4 ZBG BF 09 0015 Attachment 2 6 6 e Atleast one of the following instructions is executed between the instructions in 3 and 4 gt A multiplication instruction mul mulh mulhi mulu gt Abit manipulation instruction clr1 not1 set1 tst1 gt A special instruction callt dispose switch e The instruction in 4 is a load instruction that accesses the memory in bytes 1d b 1d bu sld b or sld bu e The instructions in 1 to 4 are located in an external memory or the internal RAM Workaround We regard this as a restriction related to the CPU s features and do not intend to correct the microcontroller Instead the CA850 compiler will be modified to automatically prevent instructions to which this restriction applies from being generated This wo
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