mm537-Handbuch englisch
Contents
1. 31 Physical Dimensions not shown at scale 35 Pinout with EXplattatlOTns sue eset eee ere ete 9 ROVISIOBSu 38 PHYTEC Me technik GmbH 1999 L 244e 4 Preface Preface This mini MODUL 537 509 Hardware Manual describes the board s design and functions Precise specifications for the SAB80C537 microcontroller can be found in the enclosed microcontroller Data Sheet Users Manual If software is included please also refer to additional documentation for this software In this hardware manual and in the attached schematics low active signals are denoted by a in front of the signal name 1 RD 0 indicates a logic zero or low level signal while a 1 represents a logic one or high level signal Declaration regarding EMV Conformity of the miniMODUL 537 509 PHYTEC Single Board Computers henceforth products are designed for installation in electrical appliances or as dedicated Evaluation Boards ie for use as test and prototype platform for hardware software development in laboratory environments Attention PHYTEC products lacking protective enclosures are subject to damage by ESD and hence may only be unpacked handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD dangers It is also necessary that only appropriately t2. 64 32B 63 32 x 2B 23 12A 00 24 128 _ 2B ALA Eoo 64 32 ia 9 63 32A 32 ee Figure 2 Pinout of the miniMODUL 537 509 PHYTEC Me technik GmbH 1999 1 244 4 7 miniMODUL 537 509 PIN Connection Comments Pin row X1A NC Not used P4 0 P4 7 Port4 MDIS PSEP WRP RDP P3 0 P3 5 IWR P3 6 RD P3 7 1 7 1 0 PSEN VPD RES RES ICS1 ICS2 CS3 PFI HPD 41 43 51 52 TI1 TI4 21A 22A 26A 26B VBAT 44 54 50 ROL RO3 22B 27B 25B RII RI3 23A 28A 25A 47 46 48 56 TOI TO4 24A 23B 24B 28B RSDIS ALE RESP 59 30A CSRTC ARTC RESI WDP NC b Memory Disable Input for U4 and U5 separable Program Store Enable signal of the controller separable WR signal of the controller separable RD signal of the controller Port 3 separable WR signal of the module separable RD signal of the module Port 1 separable Program Store Enable signal of the module Voltage output for external buffer Reset output of the module separable Reset Input Output of the module predecoded Chip Select signal 1 predecoded Chip Select signal 2 predecoded Chip Select signal 3 Power Fail Output Power Fail Input optional HWPD Input for the C509 C517A Transmitter Inputs 1 4 of the RS 232 driver and TI2 conected via Jumpers J5 and J8 to the
3. Pi Wi eli miniMODUL 537 509 Hardware Manual Edition June 1999 A product of a Technology Holding company miniMODUL 537 509 In this manual are descriptions for copyrighted products which are not explicitly indicated as such The absence of the trademark symbol does not infer that a product is not protected Additionally registered patents and trademarks are similarly not expressly indicated in this manual The information in this document has been carefully checked and is believed to be entirely reliable However PHYTEC Me technik GmbH assumes no responsibi lity for any inaccuracies PHYTEC Me technik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product PHYTEC MeBtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result Additionally PHYTEC Me technik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Me technik GmbH further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability for doing so Copyright 1999 Meftechnik GmbH D 55129 Mainz Rights including those of translation reprint broadcas
4. Ctrl Addr Ctrl Addr 2 8 P2 Cntrl INFINION RTC 8583 80 517 digital l O Ports C509 analog I Ports Transceiver Transceiver Transceiver Reset Watchdog Figure 1 Block Diagram PHYTEC Me technik GmbH 1999 L 244e 4 5 miniMODUL 537 509 6 PHYTEC Me technik GmbH 1999 L 244e 4 Pinout 2 Pinout Please note that all module connections are not to exceed their ex pressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller manuals data sheets As damage from improper connections varies according to use and appli cation it is the user s responsibility to take appropriate safety meas ures to ensure that the module connections are protected from over loading through connected peripherals AS Figure 2 indicates all controller signals extend to standard width 2 54 mm pin rows lining three sides the board referred to as miniMODUL Connector This allows the board to be plugged into any target application like a big chip Table 1 provides an overview of the pinout of the mini MODUL Connector Attention The miniMODUL 537 509 has been reengineered for Flash technology in an manner ensuring the highest possible compatibility to earlier non Flash fitted versions of the mini MODUL 537 However some differences in pinout to earlier versions as described in the chapter 9 were unavoidable
5. 28 C Memory Model 19 Chip Enable of the RTC72423 16 15 abus den m miniMODUL Connector 7 ontrol Register 2 5 O dcc bin i Oscillator Watchdog 16 ata Enable Input Default Memory model 19 P F Physical Dimensions 35 POUT eee estela i ine 9 ees 25 Power Consumption 36 Pete s t ovo petet Ree 4 Power Saving Modes Watchdog Flash Memory e 31 SIME qeu ede MO BOO 16 H emitte elei isa 21 Program execution Finis for Handling te Modules d from external memory 15 I from internal memory 15 reb Herr etos 12 R poo x MED T x 26 22 RAMESW eras 24 VV isters of the address decoder g 20 15 Revisions History 38 T E e 12 14 507 5 4 Reus 13 14 74 RS A35 Transceiver 13 16 PHYTEC Me technik GmbH 1999 1 244 4 39 miniMODUL 537 509 S T Serial Interface Jumpers 12 Technical Specifications 35 Special Features 15 V 24 40 PHYTEC Me technik GmbH 1999 L 244e 4 Suggestions for Improvement Document
6. OOOOOO0000000000000000000000000QG 7 62mm OQ OO OO OO OO miniMODUL 537 509 0 27 94mm OC 25 54 90mm OO OO 7 62 Y pe 2 54 2 54mm 78 74mm gt la 85mm PHYTEC MESSTECHNIK Figure 11 Physical Dimensions not shown at scale PHYTEC Me technik GmbH 1999 L 244e 4 35 miniMODUL 537 509 Additional specifications e Dimensions e Weight e Storage temperature e Operating temperature e Humidity e Operating voltage e Power consumption e Power consumption with battery buffer 54 9 x 85 mm 0 01mm approximately 32 g with 32 kByte RAM device 128 kByte Flash device 40 C to 90 C standard 0 to 70 C extended 40 C to 85 maximum 95 r F not condensed 5 5 VBAT 20 maximum 140 mA typ 100 mA at 12 MHz oscillator frequency and 128 kByte RAM at 20 C maximum 10 uA per RAM device typically 1 per RAM device at 20 These specifications describe the standard configuration of the miniMODUL 537 509 as of the pressing of this manual Please note that utilizing the battery buffer for the RAMs the storage temperature is only 0 C to 70 C 36 PHYTEC Me technik GmbH 1999 L 244e 4 Hints for Handling the Module 8 Hints for Handling the Module When changing controllers please ensure that
7. available free Chip Select Signals The signal CS REG is solely a signal internal to the decoder which is necessary in order to access the internal register This latter signal is not available PHYTEC Me technik GmbH 1999 L 244e 4 23 miniMODUL 537 509 RAM SW VN EN Connection of peripheral devices to the area of CS REG should not take place under any circumstances in order to maintain the correct function of the FlashTools for programming of the Flash The internal register is to occupy only the address ranges 7 7 and or The rest of the CS REG block remains unused and is reserved for future expansion This bit enables exchange of 32 kByte memory areas of the devices installed at U4 and U5 Following a hardware reset RAM SW 0 the RAM U4 is mirrored in the area from 0000H to 7FFFh and the RAM EEPROM at 05 is addressable from 8000H to FFFH After setting the RAM SW bit the RAM at U4 populates the area from 8000H FFFFH Likewise the RAM EEPROM U5 populates the area from 0000H 7FFFH In the corresponding I O areas there is no access to the memory devices This bit enables free selection of von Neumann memory within the address space of the controller A Reset renders a Harvard Architecture available as the default configuration Von Neumann memory is especially useful when programming code is to be downloaded and subsequently run during running time as is the c
8. 3l miniMODUL 537 509 Please note that this firmware protects itself against any intentional or accidental erasure or copy over As the Flash device s hardware protection mechanism is not utilized protection is limited to the software level In the event that you might wish to download your own programming algorithms or tools into the Flash please ensure that a programming tool remains in the Flash Memory Refer to the QuickStart Instructions for a detailed description of the on board programming Use of a Flash device as the only code memory results in no or only a limited usability of the Flash Memory as non volatile memory for data This is due to the internal structure of the Flash device as during the Flash internal programming process the reading of data from Flash is not possible Hence for Flash programming program execution must be transferred out of Flash such as into von Neumann RAM This usually equals the interruption of a normal program execution cycle As of the printing of this manual Flash devices generally have a life expectancy of at least 100 000 Erase Program cycles 32 PHYTEC Me technik GmbH 1999 L 244e 4 Battery Buffer 6 The Battery Buffer The battery which buffers the memory is not otherwise essential to the functioning of the miniMODUL 537 509 However this battery buffer embodies an economical and practical means of storing nonvolatile data The VBAT input pin 42 21B at X1A
9. Me technik GmbH 1999 1 244 4 17 miniMODUL 537 509 18 PHYTEC Me technik GmbH 1999 L 244e 4 Memory Models 4 Memory Models The miniMODUL 537 509 allows for flexible address decoding which can be adjusted by software to different memory models A Hardware RESET activates a default memory configuration that is suitable for a variety of applications However this memory model can be changed or adjusted at the beginning of a particular application Configuration of the memory is done within the address decoder by means of decoder internal registers two control registers one address register and one mask register All named registers are carried out as Write Only Registers with access to the XDATA memory of the con troller There are two distinct address areas selectable by means of the bit IO SW in control register 1 by which the registers can be ac cessed refer to the description of the bit IO SW below Due to a lack of read access a copy of all register contents should be maintained within the application Reserved bits may not be changed during the writing of the register contents must remain at 0 A Hardware RESET erases all registers while preserving the configuration of the default memory Attention In the event that you use the FlashTools PHYTEC s proprietary firmware allowing convenient on board Flash programming the ad dress FA16 is preset at the start of your application software This is to b
10. appropriate PLCC ex traction tools are used and that the socket and all components remain free from intrusive damage It is also advisable to ensure that all in sertable controllers are pin compatible with the 80C32 and that all special hardware features are compatible with the layout of the board Removal of the standard quartz or oscillator is not advisable given the compact nature of the module Should this nonetheless be necessary please ensure that the board as well as surrounding components and sockets remains undamaged while unsweating Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip AI ternatively a hot air gun can be used to heat and loosen the bonds PHYTEC Me technik GmbH 1999 L 244e 4 37 miniMODUL 537 509 9 Revision History of mini MODUL 537 509 Due to the conversion to Flash Memories some changes appeared in regard to the specifications of the mini MODUL 537 509 PHYTEC tried to gain as much compatibility as possible but some differences are necessary The Table below shows the differences in function and pinout and points out the interchangeability between the versions MM 101 miniMODUL 537 and 103 miniMODUL 537 509 Pin 1 2 Pin 13 Pin 35 Pin 37 Pin 58 Pin 634 64 U3 Table 2 Pin 12 Pinl4 Pi
11. bit of the pattern is compared with the corresponding address line of the controller HA15 with A15 HAIO with A10 As address lines 15 A10 are used to define Harvard addressing space only Harvard fields of at least 1 kByte can be configured Areas smaller than 1 kByte can not be configured l Memory area in which no difference exists between CODE and XDATA access This means that both accesses use the same physical memory device usually a RAM Memory area in which CODE and XDATA accesses use different physical memory devices usually CODE access uses a ROM or Flash device whereas XDATA access uses a RAM Reserved bits are not to be changed the default value 0 must remain PHYTEC Me technik GmbH 1999 L 244e 4 27 miniMODUL 537 509 4 4 Mask Register The mask register addresses 7 serves the masking of single bits in the address register see above Following a hardware reset all bits within the address register are relevant By setting the individual bits in the mask register all corresponding bits in the ad dress register will no longer be subject to an address comparison Mask Register Address 7C03H Bit 7 Bit 0 15 MA14 MAI3 MA12 MAIO Res Res It is to be noted that in the case of a single 32 kByte RAM the memory area is mirrored within the controller s addressing area On account of the insufficient utiliza
12. delivery of the module the Oscillator Watchdog is activated enabling a quick Power On Reset of and stable operation of the con troller Oscillator Watchdog 14 Deactivated closed Activated open Chip Enable of the RTC72423 Closing Jumper J13 connects the Real Time Clock RTC2423 with the address decoders pre decoded Chip Select signal CS1 Opening Jumper J13 allows the user to connect any desired Chip Select signal via the CSRTC signal of the module module pin 59 30A at X1A Chip Enable RTC 72423 CS1 of the address decoder closed external CSRTC at module pin 59 30A at X1A open 16 PHYTEC Me technik GmbH 1999 L 244e 4 Jumpers Internal Progamming Mode of the C509 Jumper J14 is only relevant for modules fitted with the C509 control ler Connecting jumper pads 2 3 enables an optional programming mode for the C509 which can be activated per software This ex changes XDATA and CODE memory areas and enables an application running from the RAM to program the Flash Memory This is facilitated by a special WRF signal which writes to Flash The design of the board however does not utilize this mode for programming the Flash Memory This is done via the FlashTools re fer to Sections 5 and the Quickstart Instructions Hence it is recommended that 114 remain closed at 1 2 Programming Mode C509 J14 Deactivated 1 2 Activated 2 3 PHYTEC
13. is provided for connecting the external battery As of the pressing of this manual a lithium battery is recommended as it offers relatively high capacity at low discharge In the event of a power failure at Vcc the RAM memory blocks will be buffered by a connected battery via VBAT Attention The battery device on the mini MODUL 537 509 is not appropriate to supply an EEPROM if installed at U5 Therefore jumper J2 has to be closed at 1 2 in order to avoid fast discharge of the battery Power consumption depends on the components used and memory size This is typically lt 1 uA per 32 kByte RAM device installed on the mini MODUL For reasons of operating safety please be advised that despite the battery buffer changes in the data content within the RAM can occur given disturbances The battery buffer does not completely remove the danger of data destruction PHYTEC Me technik GmbH 1999 L 244e 4 33 miniMODUL 537 509 34 PHYTEC Me technik GmbH 1999 L 244e 4 Technical Specifications 7 Technical Specifications The physical dimensions of the mini MODUL 537 509 are represented in Figure 11 The module s profile is ca 10 mm thick with a maximum component height of 3 mm on the back side of the PCB and approximately 5 mm on the front side The board itself is approximately 1 5 mm thick 2 54mm
14. miniMODUL 537 509 Document number L 244e_4 June 1999 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC Technologie Holding AG Postfach 100403 D 55135 Mainz Germany Fax 49 6131 9221 33 Me technik GmbH 1999 L 244e 4 Published by Y PHYTEC MeBtechnik GmbH 1999 Ordering No L 244e_4 Printed in Germany
15. of the module and functions as described above only in connection with RAM devices of at least 128 kByte at U4 1 N A Not Accessible 26 PHYTEC Me technik GmbH 1999 L 244e 4 Memory Models 4 3 Address Register The address register 7C02H FCO2H functions in conjunction with the mask register see below to define the von Neumann and Har vard memory in the controller s addressing area By setting the bit VN EN in control register 1 the values of the address and the mask register become valid for the definition of the von Neumann and the Harvard addressing space and incorporated in access addressing refer to control register 1 The location of one or more Harvard areas can be configured with both registers The remaining sections of the addressing area is con figured as von Neumann area in which RAM is accessible through XDATA as well as through CODE The mechanism through which the areas are differentiated is based on a comparison of the current address with a predefined address pattern of variable width If the relevant bit position of the addresses conform to one another access occurs according to the Harvard architecture In the case of non conformity access occurs according to the von Neumann architecture Address Register Address 7 2 2 Bit 7 Bit 0 15 14 HAI3 12 HAIO Res Res The address register holds the address pattern mentioned above Each
16. 41 Control Register Tonics 21 Control 26 4 3 Address Hai tte ta etus 24 4A Mask o ned eH tO 28 1 The Battery Buffer rette Technical Specifications 25 Hints for Handling the 0 37 Revision History of mini MODUL 537 509 38 hri PHYTEC Me technik GmbH 1999 1 244 4 miniMODUL 537 509 Index of Figures and Tables Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Table 1 Table 2 Block DIaBrdmi ne ee tix ero Den eap ado adde 5 Pinout of the 0 1 537 509 7 Numbering of the 11 Location of the Jumper view of the component side 11 Location of the Jumper view of the soldering side 11 Default memory model after Hardware Reset 20 Memory model for Flash Programming sss 22 Partitioning of the I O Area ioter tret tyre etra 23 Example of Memory 30 Memory Areas of the Flash
17. 8A and 16 8B of the module P3 0 and P3 1 At the time of delivery the RS 232 interface is active by default The following signal qualities can be configured for serial interface 0 Signal Quality SerialO 15 J6 RS 232 closed closed modul pins 45 23 and 47 24A at X1A TTL open open modul pins 15 8A and 16 8B at X1A Jumpers J7 J8 Jumpers J7 and J8 connect both pins of the controller s serial interface 1 Seriall with RS 232 RS 485 transceiver of the miniMODUL Likewise TTL connection is enabled when controller signals are directly connected to pins 56 28B and 57 29A at X1B P6 1 and P6 2 12 PHYTEC Me technik GmbH 1999 L 244e 4 Jumpers The following signal qualities can be configured for serial interface 1 Signal Quality Serial 18 RS 232 243 243 modul pins 46 23 and 55 28A at X1A TTL open open modul pins 56 28B and 57 29A at X1B modul pins 31 16A and 33 17A at X1B Jumper J9 Closing Jumper J9 connects the Data Enable Input of the RS 485 transceiver to pin P5 1 of the controller This allows software configuration of the RS 485 transmitter for networking purposes such as networking the module within the proprietary PHYTEC RS 485 network RS 485 Transmitter J9 P5 1 RES Enabled closed Low Low closed High n a Disabled closed n a High open n a Jumper J10 Closing Jumper 10 e
18. FFH 8000H 7FFFH Flash U3 0000H PRG EN 1 RAM SW 0 Read Only Write Only Read Write Memory model for Flash Programming By means of this bit the I O area of the module can be selectively mapped either to the upper or to the lower 32 kByte of the address space After a Hardware Reset IO SW 0 the I O area is located in the address area from FCOOH to FFFFH Following setting of the IO SW bit the I O area is located in the address area from 7 to 7FFFH This generally consists of 4 blocks of 256 bytes each In three of these blocks the address decoder provides a predecoded Chip Select Signal which simplifies the connection of peripheral hardware to the module 22 PHYTEC Me technik GmbH 1999 L 244e 4 Memory Models Figure 8 This Chip Select Signals are activated by XDATA ac cess Read Write access to the corresponding address area The fourth block is reserved for accessing the register internal to the decoder Write Only access Hence this block is not available for connection of pe ripheral hardware to the module The following diagram illustrates the partitioning of the I O area 7FFFH FFFFH CS3 7FOOH FFOOH 7EFFH FEFFH CS2 FEOOH 7DFFH FDFFH CS1 7D00H FDOOH 7CFFH FCFFH CS REG 7 FC00H Write Only Read Write Default Setting Partitioning of the I O Area Given this partition CS1 through CS3 function as the
19. U11 30 15B D Data input of the RS 485 transmitter connected via Jumper 78 to the serial interface of the controller 31 16 differentiated B line of the RS 485 driver 32 16B R Data output of the RS 485 receiver connected via Jumper J7 to the serial interface of the controller 33 17 A differentiated A line of the RS 485 driver 34 17B R inverted Data output of the RS 485 receiver connected via Jumper 711 to P3 2 of the controller 35 18A DE inverted Data Enable input of the RS 485 transmitter connected via Jumper 79 with P5 1 of the controller 36 18B RE Receive Enable input of the RS 485 receiver connected via Jumper J10 to GND 37 44 19 22B P9 7 P9 0 Port 9 of the C509 controller 45 52 23 26 5 7 5 0 Port 5 53 27 Reset Output of the controller 54 27 Watchdog Timer Power Save mode of the controller connected via Jumper 73 to GND 55 62 28 31B 6 0 6 7 Port 6 63 64 32 32B_ GND Ground 0 V PinrowXIC 1 5 9 13 15 17 AGND Analog input 0 V 19 21 1 5A 7A 8A 9A 10A 11A 3 7 11 P8 4 P8 6 Analog inputs AN12 ANI4 only for the C509 2A 4A 6A AN12 AN14 controller 8 6 4 2 P8 3 P8 0 Analog inputs ANI1 ANO 24 22 20 18 16 P7 7 P7 0 14 12 10 ANII ANO 4B 3B 2B 1B 12 11B 10 OB 8B 7B 6B 23 12 Referenc
20. ase with a Monitor program The location of the optional von Neumann memory is defined through the address and mask registers see below 1 Software tools for on board Flash programming are pre installed in the Flash device upon delivery 2 Memory area in which no difference is made between CODE and XDATA access This means that both accesses use the same physical memory device usually a RAM Memory area in which CODE and XDATA accesses use physical different memory devices CODE access typically uses a ROM or Flash device whereas XDATA access uses a RAM 24 PHYTEC Me technik GmbH 1999 L 244e 4 Memory Models FA 18 15 Following a hardware reset VN EN 0 the settings in the address and mask registers are not released which means that no von Neumann memory is avail able After setting the bit VN EN 1 the settings in the address and mask registers are valid and incorpo rated in access addressing This bit is only relevant in the Runtime model PRG EN 0 In the Program ming model PRG EN 1 it is unimportant and ignored The module can be equipped with an optional 512 kByte Flash Memory As the controller s address space is limited to 64 kByte the remainder of the Flash Memory can only be accessed by means of bank memory switching In the Runtime model PRG EN 0 64 kByte banks can be switched by controlling the high address lines A 18 16 for the Flash through software For this pu
21. e Voltage Analog inputs 4 5 V Table 1 Pinout with Explanations PHYTEC Me technik GmbH 1999 L 244e 4 miniMODUL 537 509 10 PHYTEC Me technik GmbH 1999 L 244e 4 Jumpers 3 Jumpers For configuration purposes the mini MODUL 537 509 has 14 solder ing jumpers some of which have been installed prior to delivery Figure 3 illustrates the numbering of the jumper pads while Figure 4 and Figure 5 indicates the location of the jumpers on the board Figure 3 Numbering of the jumper pads x AN W 11111111111 m mms mm 1 5 fom 29 3 Figure 4 Location of the Jumper view of the component side Figure 5 Location of the Jumper view of the soldering side PHYTEC Me technik GmbH 1999 L 244e 4 11 miniMODUL 537 509 The jumpers can be divided into three groups 1 Serial Interface Jumpers J5 J6 J7 J8 J9 J10 J11 and J12 2 Memory Model Selection Jumper J2 U5 3 Special Features Jumpers J1 J3 J4 J13 and J14 3 1 Serial Interface Jumpers Jumpers J5 and J6 Jumpers J5 and J6 connect both signals of the controller s serial interface 0 SerialO0 with the RS 232 transceiver of the mini MODUL at pins 45 23A 47 24A at X1A Additionally a TTL connection is enabled when controller signals are directly connected to pins 15
22. e noted upon installation of the software copy of the register contents PHYTEC Me technik GmbH 1999 L 244e 4 19 miniMODUL 537 509 The following Figure displays the default memory model CODE XDATA FFFFH RAM or EEPROM U5 8000H 0000H PRG EN 0 VN EN 0 lIO SW 0 RAM SW 0 Figure 6 Default memory model after Hardware Reset It should be noted that the memory block U4 and U5 comprise sepa rate 32 kByte memory areas in the XDATA address area of the controller In the event that a 128 kByte RAM device is installed at U4 then blocks of 32 kByte be accessed and switched via bank latching In the event that U4 and U5 are not populated by memory devices then there is no possible access to the corresponding XDATA memories The corresponding current I O area is concentrated in an XDATA address area in which there is no access to any existing RAM In the following sections the registers of the address decoder for con figuration of the memory are explained 20 PHYTEC Me technik GmbH 1999 L 244e 4 Memory Models 4 1 Control Register 1 iu em 1 S mm 71 Bit m IO sve RAM 18 15 Bit invalid programming model refer PRG EN Bit valid only in programming model refer to PRG EN PRG EN Activates the special Flash programming memory model PRG EN 1 This configuration is used within the FlashTools for Flash programming On acco
23. ia J2 1 2 is required in order to prevent a expedited depletion of any external battery buffer Installation of a RAM device at U5 however requires sourcing power via VPD J2 2 3 Memory Device at U5 J2 EEPROM 1 2 2 3 3 3 Special Features Jumpers Jumpers Jl J3 4 and 114 are used to activate the special features of the particular controller fitted on the module Execution out of internal or external program memory At the time of delivery Jumper J1 is preconnected at pads 142 This default configuration means that the program stored in the external program memory is executed after a Hardware Reset In order to allow the execution of a specific controller s internal pro gram memory the pads 2 3 on jumper 11 must be connected The following configurations are possible Code Fetch J1 Execution from external program memory 1 2 Execution from internal program memory 2 3 Me technik GmbH 1999 1 244 4 15 miniMODUL 537 509 Power Saving Modes Watchdog Timer Opening Jumper J3 deactivates the Power Save mode This also automatically starts the Watchdog timer after a Hardware Reset Upon delivery the Watchdog timer is deactivated Jumper J3 allows activation of either the timer or the Power Save mode Power Save Mode Watchdog Timer J3 Activated Deactivated closed Deactivated Activated Oscillator Watchdog Upon
24. ll as a 15 bit A D converter with 10 bit resolution Refer to the corresponding Controller User s Manual for detailed in formation The module itself features 32 kByte SRAM and 128 kByte Flash which can be programmed on board using the PHYTEC FlashTools All board components are addressable with signals available at the pin rows aligning three edges of the board The miniMODUL 509 537 can also accommodate an external address decoder One of two RS 232 serial interfaces can be optionally configured as an RS 485 transceiver hence allowing the module to be networked with other boards with RS 485 connectivity The module is easily programmable with the included 8051 compatible evaluation software development tools These versatile on chip and peripheral characteristics of the mini MODUL 537 509 render the module a complete microprocessor system Insertion of the miniMODUL 537 509 into a project allows engineers to forgo development of a digital microprocessor system to be embedded within application hardware hence shortening development time horizons The miniMODUL 537 509 can also be inserted as a big chip into application hardware Compare the cost performance of PHYTEC s insert ready mini MODUL 537 509 with the development design and testing costs of your internal development Me technik GmbH 1999 L 244e 4 3 miniMODUL 537 509 miniMODUL 537 509 offers the following features SBC in credit card size dimensio
25. n36 40 Pin 60 Pin9l Pin92 Pin93 101 102 103 Pin 104 Pin 105 Pinl06 Pin 107 Pin108 miniMODUL 537 old MM 101 OFF BRES RES2 WDO WRO PWR Low Line A15 STDP GND BO RS 485 2 2 XCERAMI XRAMI XOEROM XROM suitable for OTPs EPROMs 32Kx8 64Kx8 in PLCC LCC case Revisions with miniMODUL 537 509 new MM 103 No connection Use Pins 65 66 only this improves radio interference behavior PSEP WRP RDP CS1 CS2 CS3 HPD RESP IRTC No connection Use Pins 1274128 only this improves radio interference behavior PRGEN No connection DE Port9 7 of C509 Port9 6 of C509 Port9 4 of C509 Port9 3 of C509 Port9 2 of C509 Port9 1 of C509 9 5 of C509 Port9 0 of C509 Suitable for Flash Memories 29F010 29F040 with 128Kx8 512Kx8 or OTPs with 128Kx8 in PLCC case 38 PHYTEC Me technik GmbH 1999 L 244e 4 Index EE 12 A NU 12 Address Decoding 19 12 Address Register 27 12 CP 13 14 Battery 33 Block Diagram 5 Mask Register
26. nables receptivity of the RS 485 Receiver RS 485 Receiver Reception Enabled closed Reception Disabled open PHYTEC Me technik GmbH 1999 L 244e 4 13 miniMODUL 537 509 Jumper J11 Closing Jumper J11 connects the inverted Data Output of the RS 485 receiver with pin P3 2 of the controller As this pin is bit addressable Jumper Jll enables bit addressed commands regarding the status of the data output Controller Pin P3 2 Connected with the inverted Data Output closed Disconnected with the open inverted Data Output If the module is to be routed in the proprietary PHYTEC uNET RS 485 network then the jumpers J9 J10 and J11 must be closed in order to enable UNET network connectivity Jumper J12 Opening Jumper J12 deactivates the RS 232 transceiver If this transceiver is deactivated it is possible to control the transceiver s activities via the RSDIS input of the module module pin 53 27A at X1A Upon delivery of the module Jumper J12 is closed and hence the RS 232 transceiver is activated 5 232 Transceiver J12 RSDIS Activated closed N C open Low Deactivated open N C open High 14 PHYTEC Me technik GmbH 1999 L 244e 4 Jumpers 3 2 Memory Model Selection Jumper J2 U5 Jumper J2 Jumper J2 enables selection of a power source for the spe cific memory device installed at U5 If an EEPROM is installed at US a power source v
27. ns 55 x 85 mm achieved through advanced SMD technology fitted with Infineon 8051 compatible SAB80C509 QFP 100 socket or C537 controller in a PLCC 84 socket improved interference safety through multi layer technology controller signals and ports extend to standard width 2 54 mm pins aligning board edges allowing the board to be plugged into any target application like a big chip requires a single low power supply 5 V typ 100 mA 128 to 512 kByte Flash on board PLCC on board Flash programming no dedicated Flash programming voltage required through use of 5 V Flash devices 32 to 160 kByte RAM on board SMD 32 kByte EEPROM SMD can also be accommodated on the board supplemental 3 kByte XRAM on chip and BOOT ROM with the C509 flexible software configured address decoding through complex logic device bank latches for Flash and RAM integrated in address decoder 2 serial interfaces via RS 232 one of which is optionally configur able as an RS 485 transceiver to enable networking Real Time Clock RTC8583 or RTC72423 SRAM and Real Time Clock buffered by external battery 3 free Chip Select signals for easy connection external peripherals operates within a standard range of 0 to 70 degrees PHYTEC Me technik GmbH 1999 L 244e 4 Introduction 1 1 Block Diagram RAM A BATTERY FLASH 32 KB RAM 128 512 32 128 8 32 64
28. r pose register bits FA 18 16 of the address decoder provide a Latch to which the desired higher addresses can be written Of particular note is the bit FA15 which is solely rele vant in the programming model PRG EN 1 As in this model only 32 kByte of Flash can be accessed it serves as address line A15 for the Flash Memory In the Runtime model PRG EN 0 with a 64 kByte Flash Memory area to contrast the address line A15 of the controller is attached directly to the Flash The function of the bits FA 18 16 is dependent on the hardware configuration of the module and functions as described above only in connection with Flash devices of 512 kByte PHYTEC Me technik GmbH 1999 L 244e 4 25 miniMODUL 537 509 4 2 Control Register 2 Control Register 2 Address 7 FCO1H Bit 7 N A NA NA NA NA NA 16 RAIS 16 XE Bit 0 The module can optionally accommodate a 128 kByte RAM device at U4 As the address space at U4 is limited to 32 kByte in the XDATA area of the control ler the remainder of the RAM can only be accessed by means of bank switching Four memory banks of 32 kByte banks can be switched by setting the high address lines A 16 15 through software For this purpose register bit RA 16 15 of the address decoder provides a Latch to which the desired higher addresses can be written The function of this bit is dependent on the hardware configuration
29. rained personnel such as electricians and engineers handle and or operate these products Moreover PHYTEC products should not be operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC Me technik GmbH 1999 L 244e 4 1 miniMODUL 537 509 PHYTEC products fulfill the norms of the EMVG statute only in accordance to the descriptions and rules of usage indicated in this hardware manual particularly in respect to the pin header row connectors power connector and serial interface to host PC Implementation of PHYTEC products into target devices as well as user modifications and extensions of PHYTEC products is subject to renewed establishment of conformity to and certification of EMV Statutes Only after doing so the devices are allowed to be put into circulation The miniMODUL 537 509 is one of a series of PHYTEC nano micro minIMODULs which can be fitted with different controllers and hence offers various functions and configurations PHYTEC supports all common Infineon 8 and 16 bit controllers in two ways 1 as the basis for Starter Kits in which user designed hardware can be implemented on a wrap field around the controller and 2 as insert ready fully functional micro and mini MODULS which can be embedded directly into the user s peripheral hardware design PHYTEC s microcontroller modules allow engineers to shorten devel opment horizons reduce de
30. serial interface of the controller Input for conection to external buffer battery Receiver Outputs 1 3 of the RS 232 driver ROI and RO2 are connected via Jumpers J6 and J7 to the serial interface of the controller Receiver Inputs 1 3 of the RS 232 driver Transmitter Outputs 1 4 of the RS 232 driver RS 232 driver Disable Input Address Latch Enable Output separable Reset signal of the controller Chip Select signal of RTC72423 connected via Jumper J13 to ICS1 Interrupt Output of both RTCs Reset Input of the module Watchdog Input of the module not used In order to implement an emulator the controller signals XXP can be separated from the XX signals used in the module enabling external input Applicable signals are PSEN RD WR and RES PHYTEC Me technik GmbH 1999 L 244e 4 Pinout PIN Connection Comments PinrowXIB 1 2 1A 1B_ Voltage input 5 V 3 10 2 5 7 0 Data bus Port 0 multiplexed with low byte of address bus 11 18 6A 9B 7 0 Address bus low byte 19 20 26 9 8 All Address bus high byte 10A 10 13 10 A13 A12 15 14 27 14 Program Enable Input only C509 28 14 NC Not used 29 15 Data Enable Input of the RS 485 driver connected via Pin 13 to
31. sign costs and speed project concepts from design to market Please contact PHYTEC for additional information EUROPE NORTH AMERICA Address PHYTEC Technologie PHYTEC America LLC Holding AG 255 Ericksen Avenue NE Robert Koch Str 39 Bainbridge Island WA 98110 D 55129 Mainz USA GERMANY Web Site http www phytec de http www phytec com e mail info phytec de info phytec com Voice 49 6131 9221 0 1 800 278 9913 Fax 49 6131 9221 33 206 780 9135 2 PHYTEC Me technik GmbH 1999 L 244e 4 Introduction 1 Introduction The mini MODUL 537 509 is a continuation of PHYTEC s successful line of credit card sized microcomputers The core of the mini MODUL 537 version is the Infineon SAB80C537 8 bit controller which is closely compatible to the 80C535 yet boasts the following integrated hardware additions 4 timers a 12 channel A D converter two serial interfaces a Watchdog Timer eight data pointers six ports and high performance arithmetic unit The mini MODUL 5009 ver sion is based on the 80C509 controller which in turn extends the functionality of the C537 The C509 has a standard internal frequency booster which doubles its clock speed from 12 to 24 MHz Its maxi mum clock frequency of 16 MHz allows it to attain the processing speed of an 8032 board running at a 32 frequency delivering an instruction cycle in 375 ns It also offers 3 kByte on chip RAM and Boot ROM as we
32. st example in the Table is further illustrated by the following Figure CODE XDATA Von Neumann A800H Flash U3 ATEEN Harvard PRG EN 0 VN EN 1 IO SW 0 RAM SW 0 Addr Reg 10100X00b Mask Reg 000001000 Figure 9 Example of a Memory model 30 PHYTEC Me technik GmbH 1999 L 244e 4 Flash Memory 5 Flash Memory Flash is a highly functional means of storing non volatile data Having the miniMODUL 537 509 equipped with a Flash device makes this modern technique available The mini MODUL 537 509 can house a Flash device of type 29F010 with two banks of 64 kByte each or of type 29F040 with 8 banks of 64 kByte each Use of Flash devices allows incorporation of on board programming capability The Flash devices are programmable with 5V Consequently no dedicated programming voltage is required A firmware to programm the Flash device the so called FlashTools is pre installed in the first bank bank 0 of the Flash device Hence the total memory available is 64 kByte or 448 kByte refer to Figure 10 Attention Should this software be erased from the Flash device without having a back up or an equivalent replacement reprogramming is no longer possible 29F010 29F040 FFFFH FFFFH bank 1 8000H 8000H 7FFFH 7FFFH 0000H 0000H 1 FlashTools firmware software protected Figure 10 Memory Areas of the Flash Device PHYTEC Me technik GmbH 1999 L 244e 4
33. t photomechanical or similar reproduction and storage or processing in computer systems in whole or in part are reserved No reproduction may occur without the express written consent from Me technik GmbH EUROPE NORTH AMERICA Address PHYTEC Technologie Holding PHYTEC America LLC Robert Koch Str 39 255 Ericksen Avenue NE D 55129 Mainz Bainbridge Island WA 98110 GERMANY USA Ordering 49 800 0749832 1 800 278 9913 Information order phytec de order phytec com Technical 49 6131 9221 31 1 800 278 9913 Support support phytec de support phytec com Fax 49 6131 9221 33 1 206 780 9135 Web Site http www phytec de http www phytec com 4th Edition June 1999 PHYTEC Me technik GmbH 1999 L 244e 4 Contents PRCT ACC 1 5 00 2 Introduction 3 EL Block DIABramadu oe esee oido e uan 5 PUM OU TUN DES l 3 1 Serial Interface JUIDGIS eee tree Pe e Pte beer 12 3 2 Memory Model Selection Jumper J2 U5 15 3 3 Special Features Jumpers oes teste delen lec 15 Memory
34. tion of A15 in this configuration memory accesses to addresses higher than 8000H are reduced to accesses to the memory area from 0000H to 7FFFH This should be taken into consideration when choosing the memory model Otherwise function failure could result from overlapping access l Reserved bits are not to be changed the default value 0 must remain 28 PHYTEC Me technik GmbH 1999 L 244e 4 Memory Models The following examples of different combinations of the address and mask registers illustrate these functions X specific bit irrelevant Address Reg Mask Reg Comments only for VN EN 1 1XXXXX00b 0111110060 Harvard 8000H FFFFH Von Neumann _0000 7 OXXXXX00b 011111000 Harvard 0000 7 Von Neumann 8000H FFFFH 11111100b 00000000b Harvard FC00H FFFFH Von Neumann 0000 010X0000b 000100006 Harvard 4000H 43FFH and 5000H 53FFH Von Neumann and 0000H 3FFFH 4400H 4FFFH 5400H FFFFH 10000000b 000000006 Harvard 8000H 83FFH Von Neumann 0000 7 8400H FFFFH 10100X00b 000001000 Harvard A000H A7FFH Reserved bits Von Neumann and 0000H 9FFFH A800H FFFFH without function for address refer to description of the register decoding X irrelevant on account of a bit set in the mask register PHYTEC Me technik GmbH 1999 L 244e 4 29 miniMODUL 537 509 The la
35. unt of existing restrictions it is either of no or of restricted use in your application In this model 32 kByte Flash Memory located within the address range 0000H 7FFFH 15 accessible as well as 32 kByte RAM within the range 8000H FFFFH The Flash Memory can only be written in the XDATA area and can only be read from the CODE area The RAM can be read and written in the XDATA area RAM can also be read from the CODE area The address line A15 of the Flash is derived from the Control Register 1 Bit 0 FAI5 only in the programming configuration In the Run time configuration PRG EN 0 the address line A15 of the controller leads directly to the Flash device 1 n the event that you use the FlashTools a firmware allowing convenient on board Flash programming it should be noted that the Bit FA16 will be preset at the start of your application software This is to be noted upon installation of the software copy of the register contents 2 firmware allowing convenient on board Flash programming at purchase of the module including a Flash device this software is already installed in the Flash device PHYTEC Me technik GmbH 1999 1 244 4 21 miniMODUL 537 509 Figure 7 IO SW The bits IO SW and VN EN is also relevant to the programming configuration whereas the bit VN EN is not relevant The following Figure illustrates the programming configuration the I O field is not represented CODE XDATA FF
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