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LC871A00 SERIES USER`S MANUAL

1. Table 3 18 1 Endpoint Configuration Transfer Type Settings Maximum RAM Address size bytes Receive 64 0200H to 023FH EPO Control Transmit 0240H to 027FH Offset 0 0280H to 02 Offset 1 0290H to 02 Bank 0 Offset 2 02A0H to 02DFH Interrupt Offset 3 64 2 to 02EFH bulk Offset 0 02 to 02 Offset 1 02D0H to 030FH Bank 1 Offset 2 02bE0H to 031FH Offset 3 02F0H to 032FH Offset 0 0300H to 033FH Offset 1 0310H to 034FH Bank 0 Offset 2 0320H to 035FH Interrupt Offset 3 64 0330H to 036FH EP2 bulk isochronous Offset 0 0340H to 037FH Offset 1 0350H to 038FH Bank 1 Offset 2 0360H to 039FH Offset 3 0370H to 03AFH Offset 0 0380H to 03 Offset 1 0390H to 03CFH Bank 0 Offset 2 03A0H to 03DFH Interrupt Offset 3 64 03B0H to 03EFH EP3 bulk isochironous Offset 0 03 to 03FFH Offset 1 03D0H to 040FH Bank 1 Offset 2 to 041FH Offset 3 03F0H to 042FH Offset 0 0380H to 03BFH Offset 1 0390H to 03CFH Bank 0 Offset 2 03A0H to 03DFH Interrupt Offset 3 64 to 03EFH EP4 bulk Offset 0 03 to 03FFH Offset 1 03D0H to 040FH Bank 1 Offset 2 to 041FH Offset 3 to 042FH 3 121 USB 3 18 3 7 Related I O pins
2. 3 36 3 8 3 Circuit Configuration 3 38 3 8 4 Related Registers 3 43 Timers 6 and 7 T6 T7 samansasanansauanausanansananansananausananausanansananansausnausanansananannuan 3 47 3 9 1 Overview 3 47 3 9 2 Functions shssshsssnsusnsuunsuunassnansnassnansuanunanusnanunanunanusanusenusanusanusanusanusasusanusasusasusae 3 47 ii 3 10 3 11 3 12 3 13 3 14 3 15 3 16 Contents 3 9 3 Circuit Configuration rennen nennen 3 47 3 9 4 Related 3 50 Base Timer BT 3 52 ROUND 3 52 3 10 2 Functions 3 52 3 10 3 Circuit Configuration mnn 3 53 3 10 4 Related
3. 3 17 3 5 3 Related Registers 3 1 8 3 5 4 Options 3 22 3 5 5 HALT and HOLD Mode Operation 3 22 Timer Counter 0 TO PARARRARRRARRARRRSARARARRARARARRARARRARARARRARARARRARARARRARARRARARARRARARARRARRRAE 3 23 3 6 1 Overview 3 23 3 6 2 Functions 3 23 3 6 3 Circuit Configuration
4. 3 1 3 1 2 Functions 3 1 3 1 3 Related Registers 3 2 3 1 4 Options 3 4 3 1 5 HALT and HOLD Mode Operation 3 5 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 Contents Port 1 See EE EERE EERE EEE ES 3 6 3 2 1 Overview 3 6 3 2 2 Functions 3 6 3 2 3 Related Registers rasashsasusasusuunsuensuensusnsenssenssenssenssenssanssenssea
5. 3 14 Port 3 See EERE EEE ES 3 1 5 3 4 1 Overview 3 1 5 3 4 2 Functions 3 1 5 3 4 3 Related Registers 3 1 5 3 4 4 Options 3 1 6 3 4 5 HALT and HOLD Mode Operation IPT itt ete eee 3 1 6 Port 7 RRARRRRRARRARRARRARRARRARRARRARRARRARRARRARRRARRARRARRARRRARRARRARRARERARRARRARRARRRARRARRARRARRARRARRARRRRRAR 3 1 7 3 5 1 Overview 3 17 3 5 2 Functions
6. wmox mw em tes tux mm mwmm Wwe LL EL mm wwmm Ww 6 LC871A00 APPENDIX I Address Initial value R W LC871A00 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEBB HHHH HHHH None mw wmm ww pad mm mwmm Wwe LL m mwmm wwe 6 mm wmm we S ma Wwe LC mz wwmm Wwe SSCS ms mwmm Wwe IL LLL ma wmm Wwe ms mwmm Wwe ms wwmm we Sd Wwe SSCS FEC9 HHHH HHHH None a CT SI ms mwmm Wwe LL mm wwmm Wwe mao mwmm wwe e we mx mwmm Wwe SSCS 0000 ox ww O o REGN STRERR RECEN mw 0000 0000 wm eer sper Tere TRISTE cmo wr wn
7. 3 146 3 1 9 4 Related Registers Peete etree errr t ee etree rere rere rere reer LC Fa 3 1 50 3 19 5 Remote Control Receiver Circuit Operation 3 156 Chapter 4 Control Functions 4 1 4 1 Interrupt Function Pee eee eee eee ee eee eee eee eee eee eee eee eee eee eee eee eee eee eee eee eee 4 1 4 1 1 Overview eter errr errr errr errr errr eer reer rete tree rete 4 1 4 1 2 Functions Peete eee treet rere rere rere rere rer reer reer reer reer eter eter rere rere treet rete etree terete erie 4 1 4 1 3 Circuit Configuration 4 2 4 1 4 Related Registers Peer etree ree rere eer ee eee ee ree eee etree etree eee eer ee eet eee eee eee eee eee 4 3 4 2 System Clock Generator Function 4 6 4 2 1 Overview Pree reer teeter etre terete errr terete terre reer reer errr errr errr rer r errr etre treet 4 6 4 2 2 Functions eee eee eee eee eee rere rere rere rere er reer reer reer rer eter eter eter etree teeter treet etree ee 4 6 4 2 3 Circuit Configuration
8. 3 24 3 6 4 Related Registers 3 29 High speed Clock Counter sanassasanausanansananansauansssanansauanauuanansananansananaasananusananan 3 32 3 7 1 Overview 3 32 3 7 2 Functions rhssshsusnsusnauunsuenussnansunassnassnanunanunanunanunanusanusenusanusasuuanusanusasusasusasusasusae 3 32 3 7 3 Circuit Coufiguration 3 33 3 7 4 Related Registers 3 34 Timer Counter 1 T1 sanansasanansauanausanansananansananausanansasanansananansananausanansananansanuunan 3 36 3 8 1 Overview 3 36 3 8 2 Functions
9. 2 3 2 6 Register mme 2 3 27 C Register C RRR 2 4 2 8 Program Status Word PSW mme 2 4 2 9 Stack Pointer SP 2 5 2 10 Indirect Addressing Registers 2 5 2 11 Addressing Modes mme 2 6 2 1 1 1 Immediate Addressing 2 6 2 1 1 2 Indirect Register Indirect Addressing Rn 2 7 2 11 3 Indirect Register C Register Indirect Addressing Rn C 2 7 2 11 4 Indirect Register RO Offset Value indirect Addressing 2 8 2 1 1 5 Direct Addressing dst 2 8 2 1 1 6 Table Look up Addressing 2 9 2 1 1 7 External Data Memory Addressing 2 9 2 12 Wait Sequences 2 10 2 12 1 Wait Sequence Occurrence 2 1 0 2 12 2 What is a Wait Sequence 2 1 0 Chapter 3 Peripheral System Configuration META E 3 1 3 1 3 1 1 Overview
10. 1 Set according to the output type CMOS N channel open drain selected 2 Since CRC encoding is performed on the input data select the port P22 P23 that is configured for output when performing CRC encoding on the output 3 81 5104 3 13 4 5 04 shift register SIABUF 1 5104 shift register is an 8 bit shift register for 5104 serial data transfer 2 Data to be transmitted or received is written to or read from this shift register directly Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FEDD 0000 0000 SI4BUF S4BUF7 S4BUF6 54 0 5 S4BUF4 S4BUF3 S4BUF2 SABUFI SABUFO 3 13 4 6 04 baudrate register SABAUD 1 The S4BAUD baudrate register is an 8 bit register that sets the transfer rate of SIO4 serial transfer 2 The transfer rate is computed as follows TS4BAUD 4 x SABAUD value x 1 3 Tcyc S4BAUD can take a value from 1 to 255 and the valid value range of TS4BAUD is from 4 3 to 1020 3 Tcyc The S4BAUD value of 00 H is disallowed 3 fSCLK Tcyc Minimum instruction cycle time fSCLK System clock frequency Example Tcyc 250 ns when fSCLK 12 MHz Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FEDE 0000 0000 R W S4BAUD S4BAU7 S4BAU6 SABAUS S4BAU4 S4BAU3 S4BAU2 SABAUI S4BAU0 3 13 4 7 SIO4 RAM address register low byte S4ADRL 1 S4ADRL register defi
11. 3 54 Serial Interface 0 100 3 56 3111 LR 3 56 3 11 2 3 56 3 11 3 Circuit Configuration meme 3 57 3 11 4 Related 3 60 3 11 5 SIOO Transmission Examples 3 62 3 11 6 5100 HALT Mode Operation 3 64 Serial Interface 1 SIO1 3 65 3 65 3 12 2 _ _ __ _ _ __ _ ____ 3 65 3 12 3 Circuit Configuration mener nnne 3 66 3 12 4 SIO1 Transmission Examples mme 3 70 3 12 5 Related Registers 3 74 Serial Interface 4 5104 3 76 3 13 1 LM 3 76 3 13 2 FUNCTIONS mmm mm 3 76 3 13 3 Circuit Configuration mmn 3 77 3 13 4 Related 3 78 3 13 5 5104 Transmission Examples 3 85 3 13 6 5104 HALT Mode Operation mH eee 3 88 3 89 3 141 3 89 3 14 2 Functions s 3 89 3 14 3 Related 3 89 3 14 4 Parallel Interface Programming Example mmm 3 90 Asynchronous Serial Interfac
12. 4 21 452 Functions RaRESESERRRRRARBRRRARSSRERARRRARRRARRARRSSRESRRRRRRRRRRRARRSRESARRRARRRRRRRRRRSRESARRRARRRRRRRARESRSESARRRRRAR 4 21 4 5 3 Circuit Configuration 4 21 4 5 4 Related Registers RARSESSERERRRRRARARARSSSARRERRRRRRRRARRRSSARRRRRRRRRRARRRHRRARARRRRRRRARERRSRARRARRRRR RR 4 22 4 5 5 Using the Watchdog Timer 4 24 Appendix Special Functions Register SFR Al 1 8 Appendix Port Block Diagrams All 1 6 Contents vi LC871A00 Chapter 1 1 Overview 1 1 Overview The LC871A00 series microcontrollers is an 8 bit microcomputer that centered around a CPU running at a minimum bus cycle time of 83 3 ns integrate on a single chip a number of hardware features such as 32K byte flash ROM onboard programmable 2048 byte RAM an on chip debugger sophisticated 16 bit timers counters may be divided into 8 bit timers 16 bit timers may be divided into 8 bit timers or PWMs two 8 bit timers with prescalers base timer serving as a time of day clock a high speed clock counter two synchronous SIO interfaces with automatic block transmission reception capabilities an asynchronous synchronous SIO interface a UART interface full duplex a full speed USB interface with function control functio
13. 1 The table below lists the I O pins that are associated with the USB interface control circuit Table 3 18 2 USB Related I O Pins Pin Name Description D USB serial data I O pin D USB serial data I O pin P34 Connected to the internal PLL filter circuit P70 D pull up control pin 2 USB port peripheral circuit is shown in the figure below 3 The pull up resistor 1 5 at the D pin must be connected to the P70 pin so that it can be turned on and off according to the presence or absence of Vbus The on off control of this register must be accomplished through bit 5 VD3OEN of the USCTRL register FE80H VD30EN gt P70 1 5 N gt E The values of the resistors and capacitors ZF need to be adjusted according to the actual board in use Bm gt 77 Figure 3 18 2 USB Port Peripheral Circuit 4 To generate the USB 48 MHz clock using the internal PLL circuit it is necessary to connect an external filter circuit that looks like as shown below to the P34 UFILT pin External filter circuit See the data sheet document for constant values 2 Figure 3 18 3 External PLL Filter Circuit for the Internal PLL Circuit 3 122 LC871A00 Chapter 3 3 18 4 Related Registers 3 1841 USB frequency divided clock control register USBDIV 1 The USB frequency divided clock control re
14. EOTX2 EOTXI _ 0000 0000 0000 0000 0000 0000 FEos R W EPICNT EICN EICNS EICN4 EICN3 EICN2 EICNO EIRXS FE9A H000 0000 R W EP2CNT E2CN6 E2CN5 E2CN4 E2CN2 E2CNI E2CNO EP2RX E2RXS E3CN4 E3CN2 E3CNI E3CNO E3RX4 E3RX2 E3RX0 E4CN2 E4CNI E4CNO 4 4 2 H000 0000 6 5 escra E3CN3 E3CN2 E3CNI E3CNO H000 0000 E EACNS EACN3 EACN2 0000 EARXS 0000 0000 0000 0000 TESTRI 0000 0000 E3RX6 E3RXS 3 118 LC871A00 Chapter 3 3 18 3 Circuit Configuration The USB interface control circuit is made up of the functional blocks shown below N LL Oscillator circuit Clock control aClock start stop circuit CPU I F aTransmit receive clock generation sampling E register E 1 m EOP detection minterrupt m uBus reset detection request access USB transceiver USB device controller uNRZI conversion uBit stuff unstuff uSerial parallel conversion uPacket detection mDevice address detection mEndpoint detection aCRC generation check umProtocol control USB control circuit 1 4 Figure 3 18 1 USB Interface Control
15. 3 20 LC871A00 Chapter 3 INTSIF bit 5 INT3 interrupt source flag This bit is set when the conditions specified by INT3HEG and INT3LEG are satisfied When this bit and the INT3 interrupt request enable bit INT3IE are set to 1 an interrupt request to vector address 001BH are generated This bit must be cleared with an instruction as it is not cleared automatically INTSIE bit 4 INT3 interrupt request enable When this bit and INT3IF are set to 1 an interrupt request to vector address 001BH are generated INT2HEG bit 3 INT2 rising edge detection control INT2LEG bit 2 INT2 falling edge detection control INT2HEG INT2LEG INT2 Interrupt Conditions P72 Pin Data No detection INT2IF bit 1 INT2 interrupt source flag This bit is set when the conditions specified by INT2HEG and INT2LEG are satisfied When this bit and the INT2 interrupt request enable bit INT2IE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated The interrupt flag however cannot be set by a rising edge occurring when P72 data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when P72 data which is established when the HOLD mode is entered is in the low state Consequently to release the HOLD mode with P72 it is recommended that P72 be used in the double edge interrupt mode This bit must be cleared with an instruction
16. Isochronous Max payload 64 64 64 64 64 Watchdog timer External RC watchdog timer e Interrupt and reset signals selectable e Interrupts 28 sources and 10 vectors 1 Provides three levels low L high H and highest X of multiplexed interrupt control Any interrupt requests of the level equal to or lower than the current interrupt are not accepted 2 When interrupt requests to two or more vector addresses occur at the same time the interrupt of the highest level takes precedence over the other interrupts For interrupts of the same level the interrupt into the smallest vector address is honored 1 3 Vector Level Interrupt Source 1 00003H XorL INTO 2 0000BH XorL INTI 3 00013H HorL INT2 TOL INT4 USB bus active remote control receiver 4 0001BH HorL INT3 INT5 base timer 5 00023H HorL TOH 6 0002BH HorL TIL TIH 7 00033H HorL SIOO USB bus reset USB receive 8 0003 SIO1 USB endpoint USB SOF SIO4 UART1 transmit 9 00043H HorL ADC T6 T7 10 0004BH HorL Port e Priority levels X gt H gt L Of interrupts of the same level the one with the smallest vector address takes precedence Subroutine stack levels 1 024 levels maximum The stack is allocated in RAM e High speed multiplication division instructions 16 bits x 8 bits execution time 5 Tcyc 2
17. 1 2 RO lower RO 0 Fig 2 10 1 Allocation of Indirect Registers 2 11 Addressing Modes The LC870000 series microcontrollers support the following seven addressing modes 1 Immediate immediate data refers to data whose value has been established at program preparation assembly time 2 Indirect register Rn indirect 0 n 5 63 3 Indirect register Rn C register indirect 0 n 63 4 Indirect register RO Offset value indirect 5 Direct 6 table look up 7 External data memory access The rest of this section describes these addressing modes 2111 Immediate Addressing The immediate addressing mode allows 8 bite 1 byte or 16 bit 1 word immediate data to be handled Examples are given below Examples LD 12 Loads the accumulator with byte data 12H Li LDW 1234 Loads the BA register pair with word data 1234H PUSH 349 Loads the stack with byte data 34H ADD 56H Adds byte data 56H to the accumulator BE 78H 11 Compares byte data 78H with the accumulator for a branch 2 6 LC871A00 Chapter 2 2 11 2 Indirect Register Indirect Addressing Rn In the indirect register indirect addressing mode it is possible to select one of the indirect registers RO to R63 and use its contents to designate an address in RAM or SFR When the selected register contains for example 2 it designates the C register Example When R3 contains 123H RAM addre
18. 2957 je Set in register ISL FEBFh Match Match Comparator gt Match buffer TOLCMP Match buffer flag set register TOHCMP register flag set Reload Reload TOLR TOHR 8 bit programmable 8 bit programmable timer with counter programmable prescaler Figure 3 6 2 Mode 1 Block Diagram TOLONG 0 TOLEXT 1 3 27 Clock Clear gt Prescaler TOPRR Registers 101CR FE5Dh 123 ISL FE5Fh 145CR FE4Ah and 14551 4 need setting Match Match buffer register R TOHR TOLR 16 bit programmable timer with programmable prescaler gt Figure 3 6 3 Mode 2 Block Diagram TOLONG 1 TOLEXT 0 TOLCMP TOHCMP goad flag set Capture amp Capture trigger External Ed Clear input gt Set in registe r Comparator Register 01 CR FE5Dh l23CR FESEh ISL FE5Fh l45CR FE4Ah and l45SL FE4Bh need setting Match buffer register TOLCMP R TOHR TOLR lt 16 bit programmable counter gt Figure 3 6 4 Mode 3 Block Diagram TOLONG 1 TOLEXT 1 3 28 LC871A00 Chapter 3 3 6 4 Related Registers 3 6 4 1 Timer counter 0 control register TOCNT 1 This register is an 8 bit register that controls the operation and interrupts of TOL and TOH Address Initial Value R W Name BIT7 BIT6 BIT
19. P72 and P73 are assigned to INT2 and INT3 respectively and used to detect a low high edge or both edges and set the interrupt flag Timer 0 count input function A count signal is sent to timer 0 each time a signal change such that the interrupt flag is set is supplied to the port selected from P72 and P73 Timer OL capture input function A timer OL capture signal is generated each time a signal change such that the interrupt flag is set is supplied to the port selected from P70 and P72 When a selected level of signal is input to P70 that is specified for level triggered interrupts a timer OL capture signal is generated at 1 cycle interval for the duration of the signal Timer OH capture input function A timer OH capture signal is generated each time a signal change such that the interrupt flag is set is supplied to the port selected from P71 and P73 When a selected level of signal is input to P71 that is specified for level triggered interrupts a timer OH capture signal is generated at 1 cycle interval for the duration of the signal 6 HOLD mode release function When the interrupt flag and interrupt enable flag are set by INTO INTI or INT2 a HOLD mode release signal is generated releasing the HOLD mode The CPU then enters the HALT mode main oscillation by CR When the interrupt is accepted the CPU switches from the HALT mode to normal operating mode When a signal change such that the int
20. 1 0 1 1 IN 1 0 1 1 Continued next page 3 141 c U Continued from preceding page EPOSTA 3 0 Receive Receive Receive EPOSTA 3 0 Token Response End flag ACK CSU CST CRW toggle data buffer ACK CSU CST CRW Invalid Update 1 1 0 0 Error SETUP Valid Update ACK 0 1 0 0 Mis Invalid 1 1 0 0 Error 1 0 0 OUT match Valid ACK 1 1 0 0 Match Invalid Update 1 1 0 0 Error ares valid Update 0 1 0 0 IN Status IN 1 0 0 0 0 ps Invalid Update 1 1 0 1 Error SETUP Valid Update ACK 0 1 0 0 Invalid 1 1 0 1 Error 0 Valid ACK 0 1 1 1 Tx Data ACK IN 2 0 1 0 1 3 Invalid Update 1 1 1 0 Error SETUR Valid Update ACK 0 1 0 0 Invalid 1 1 1 0 Error QUT Valid STALL 1 1 1 0 STALL IN Status IN 1 0 0 0 0 a Invalid Update 1 1 1 1 Error SETUR Valid Update ACK 0 1 0 0 1 1 1 1 Invalid 1 1 1 1 Error Valid ACK 0 1 1 1 IN STALL 1 1 1 1 STALL Shaded columns contain register contents a receive buffer update or a responses to the token from the host 2 3 data packet containing no data is transmi
21. 1s Shift data 1s lt 8 lt Input pin Output Input SBUFI H L bit8 Clock lt 9 lt lt Low output Internal on falling edge of 8th clock Operation start SIIRUNT lt 1 On left 1 On right 1 Clock side released on falling edge of when SIIRUN 1 2 Start bit 2 pa detected bit on rising SILRUN 0 and SILEND 0 Low below Period 2 to 512 lt 8 to 2048 lt 2 to 512Tcyc lt 2 to 512Tcyc lt Tcyc Tcyc SILRUN Set Instruction lt Instruction Already set Already set Start bit bit 5 Instruction detected Clear End of lt End of stop 1 St op lt processing bit condition condition detected detected 2 When 2 Ack 1 arbitration detected lost Note 1 SIIEND Set End of lt End of stop 1 Rising lt 1 Falling bit 1 processing bit edge of 9th edge of 8th clock clock 2 Stop 2 Stop condition condition detected detected Continued on next page 3 67 Table 3 12 1 SIO1 Operations and Operating Modes cont Synchronous Mode 0 UART Mode 1 Bus Master Mode 2 Slave Mode 3 Transmit Transmit Receive Transmit Receive Transmit Receive SHREC 0 SHREC 1 SHREC 0 SHREC 1 SI1REC 0 1 5 0 1 5 Set 1 Falling lt 1 Falling lt 1 SHEND lt 1 Falling p bit 2 edge of edge of set edge of clock clock conditions clock detected detected met when detected when
22. FED6 0000 0000 R W S4ADRL S4ADL7 S4ADL6 SAADLS SAADLA S4ADL3 S4ADL2 SAADLI S4ADLO 3 13 3 Circuit Configuration 3 13 31 SIO4 transfer RAM address register low byte SAADRL 8 bit register 1 The S4ADRL register is used to define the starting address of the RAM area to be used for data transfer 3 13 3 2 04 transfer data byte register high byte S4BYTH 8 bit register 1 The SABYTH register is used to define the number of data bytes to be transferred via the SIO4 in the continuous data transmission mode 3 13 3 3 CRC Cyclic Redundancy Check registers CRCL CRCH 8 bit register 1 The CRC registers set up the circuit for calculating cyclic redundancy check CRC generator polynomials 3 13 3 4 CRC computation results register CRC16 16 bit register 1 The CRC computation results register stores the results of CRC computation 3 13 3 5 CRC control register CRCCNT 8 bit register 1 The CRCCNT register controls the operation of cyclic redundancy check CRC processing 2 This register also controls the suspension of the serial interface ports in the continuous data transmission reception mode 3 13 3 6 5104 control register 0 SIACNO 8 bit register 1 SI4CNO control register controls the operation and interrupts of 5104 3 13 3 7 04 control register 1 SI4CN1 8 bit register 1 SI4CN1 register controls 5104 interface ports 3 13 3 8 5104 shift register SIABUF 8 bit
23. ros ros Too En wwo mu mus mone mms Tuo f rono 0000 0000 TOLR7 TOLR6 TOLR2 TOLRI TOLRO seis mmo ww rom tone roms mem roms rom mer momo TOCAL7 TOCAL6 TOCALS tocara TOCAL3 TOCAL2 TOCALI TOCALO FEI7 TOCAH 6 TOCAHS Tocana TOCAH3 TOCAH2 TOCAHI 3 7 8 Circuit Configuration 3 7 3 1 High speed clock counter control register NKREG 8 bit register 1 The high speed clock counter control register controls the high speed clock counter It contains the start count value setting and counter value capture bits 2 Start stop Controlled by the start stop operation of timer counter 0 low byte TOL when NKEN 1 3 Count clock External input signals from pins P72 INT2 TOIN NKIN 4 Realtime output The realtime output port must be placed in the output mode When NKEN BIT7 is set to 0 the realtime output port relinquishes its realtime output capability and synchronizes itself with the data in the port latch When the value that will result in NKEN 1 is written into NKREG the realtime output port restores its realtime output capability and holds the output data In this state the contents of the port latch must be replaced by the next realtime output value When the high speed clock counter keeps counting and
24. that it is O 5 4 0 SCKOSL5 4 CKODV2 1 0 8 Source oscillator UDVSEL2 1 0 Q clock selected as system clock USB freq divided clock RC clock 48MHz PLL oscillator CF oscillator RC oscillator Subclock oscillator 4012925 bes To P05 400995 Figure 3 1 1 05 Output Clock Selector Circuit 3 1 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output 3 4 LC871A00 Chapter 3 3 1 5 HALT and HOLD Mode Operation When in the HALT or HOLD mode port 0 retains the state that is established when the HALT or HOLD mode is entered 3 2 Port 1 3 2 1 Overview Port 1 is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register a function control register and a control circuit Control of the input output signal direction is accomplished by the data direction register on a bit basis Port 1 can also be used as a serial interface I O port or PWM output port by manipulating its function control register As a user option either CMOS output with a programmable pull up resistor or N channel open drain output can be selected as the output type on a bit basis 3 2 2 Functions 1 I O port 8 bits P10 to P17 The port output data is controlled by the port 1 data latch
25. All oscillators stopped Normal operating mode Start stop of oscillators e X tal HOLD mode Main clock RC oscillator and PLL oscillator are stopped Subclock retains the state established when X tal HOLD mode is entered Contents of OCR register Since OCS register bits 0 1 4 and programmable PLLCNT register 5 are cleared the main clock and unchanged RC oscillator are started and the RC Contents of USBDIV register oscillator is designated as system unchanged clock when HOLD mode is reset CPU enters this mode after HALT mode selecting subclock or RC gt All oscillation circuits retain the oscillator as system clock state established when HALT source and stopping main clock mode is entered When X tal HOLD mode is exited the oscillators return to the state established when the mode is entered 6 Tocontrol the system clock it 15 necessary to manipulate the following special function registers USBDIV PCON CLKDIV PLLCNT OCR Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 04 0000 0000 R W USBDIV CF480N P73NDL 12 UDVSEL2 UDVSELI UDVSELO mo reoc ww __ exxpva eov 4 2 3 Circuit Configuration 4 2 3 1 clock oscillation
26. to is accomplished by POLDDR PODDR FE41 bit 0 control of P04 to 7 is accomplished by POHDDR PODDR FE41 bit 1 Port bits selected as CMOS outputs as user options are provided with programmable pull up resistors The programmable pull up resistors for POO to are controlled by the POLPU PODDR FE41 bit 2 The programmable pull up resistors for P04 to 7 are controlled by POHPU PODDR FE41 bit 3 2 Interrupt pin function POFLG PODDR 41 bit 5 is set when an input port is specified and 0 level data is input to one of port bits whose corresponding bit in the port 0 data latch PO FE40 is set to 1 In this case if PODDR FE41 bit 4 is 1 the HOLD mode is released and an interrupt request to vector address 004BH is generated 3 Shared pin function Pin 05 also serves as the system clock output pin pin P06 as the timer 6 toggle output and pin P07 as the timer 7 toggle output to P07 are also used as analog input channel pins ANO to AN7 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO 4 0000 0000 R W P07 LES ESSERE ww roe scosca 3 1 3 1 3 Related Registers 3 1 3 1 Port 0 data latch 1 The port 0 data latch is an 8 bit register for controlling po
27. 3 19 4 8 Remote control receive data 1 pulse width setup register RM2DT1W 1 remote control receive data 1 pulse width setup register is an 8 bit register that defines the width of the data 1 pulse or timings 3 and 4 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE2E 0000 0000 R W RM2DTIW RM2D1H3 RM2DIH2 RM2DIHI RM2DIHO RM2DIL3 RM2DIL2 RM2DILI RM2DILO 3 19 4 9 Remote control receive guide pulse amp data pulse width high byte setup register RM2XHW 1 remote control receive guide pulse amp data pulse width high byte setup register is 7 bit register that defines the width of the guide pulse and data pulse or sets the highest bit of timings 1 through 4 It is also used to control the direction in which data is loaded in RM2SFT Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE2F 0 00 0000 R W RM2XHW RM2RDIR RM2D1H4 RM2D1L4 RM2D0H4 RM2DOLA RM2GPH4 RM2GPLA RM2RDIR bit 7 Remote control receive shift register loading data direction control When this bit is set to 0 the data received by the remote control is loaded into the RM2SFT on an LSB first basis When this bit is set to 1 the data received by the remote control is loaded into the RM2SFT on an MSB first basis RM2D1H4 to RM2D1H0 RM2XHW bit 5 and RM2DT1W bits 7 to 4 These bits are used to define the higher side of the data 1 pulse width or to generate timing 4
28. See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction NKSEN bit 4 EP3 NAK interrupt request enable flag 1 An interrupt to vector address 003BH is generated when this bit NK3FG and ENPEN are all set to 1 ER3FG bit 3 EP3 error end flag 1 Set to 1 when the endpoint 3 transaction terminates with an error See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction bit 2 EP3 error interrupt request enable flag 1 An interrupt to vector address 003BH is generated when this bit ER3FG and ENPEN are all set to 1 ST3FG bit 1 EP3 stall end flag 1 Set to 1 when the endpoint 3 transaction terminates with a stall See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction STSEN bit 0 EP3 stall interrupt request enable flag 1 An interrupt to vector address 003BH is generated when this bit ST3FG and ENPEN are all set to 1 3 18 4 10 EPA interrupt control register EPAINT 1 The EP4 interrupt control register controls endpoint 4 interrupts Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT2 BIT1 BITO FE87 0000 0000 R W EP4INT AK4FG AK4EN NK4FG NK4EN ER4FG ER4EN ST4FG ST4EN AK4FG bit 7 EP4 ACK end flag 1 Set to 1 when the endpoint 4 transaction terminates normally with ACK See the column entitled End Flags in Table 3 18
29. Selecting the parallel data port SI4CN1 e PI P0 1 port 1 Accessing the port 1 External memory read mode Execute an instruction e g PUSH for reading data from P1 and generate a read signal at P22 at the timing of S2 Read mode timing chart 1 tcyc 1 tcyc 1 tcyc 1 52 53 51 52 53 51 52 53 51 3 90 LC871A00 Chapter 3 2 External memory write mode Execute an instruction e g POP for writing data into P1 to generate a write signal at P23 at the timing of S1 Write mode timing chart c o o c Port 1 3 91 UART 3 15 Asynchronous Serial Interface 1 UART1 3 15 1 Overview This series of microcontrollers incorporates an asynchronous serial interface 1 UARTI that has the following characteristics and features 1 Data length 7 8 and 9 bits LSB first 2 Stop bits 1 bit 2 bits in continuous communication mode 3 Parity bits None 4 Clock rate e to 2 Tcyc 5 Full duplex communication The independent transmitter and receiver blocks allow both transmit and receive operations to be performed at the same time Both transmitter and receiver blocks adopt a double buffer configuration so that data can be transmitted and received continuously 3 15 2 Functions 1 Asynchronous serial UARTI Performs full duplex asynchronous serial communication using a data length of 7 8 or 9 bits with 1 stop bi
30. as oscillator output 2 data be read through a register OCR FEOEH e Feedback resistor between and XT2 is controlled by a program CF oscillator inverter input e Enabled disabled by register OCR FEOEH Feedback resistor present between CF1 and CF2 CF oscillator inverter output e Enabled disabled by register OCR FEOEH Always set to level regardless of state when oscillation is suspended Continued on next page 4 16 Oscillation suspended when used as X tal oscillator input pin Oscillation state maintained in X tal HOLD mode Feedback resistor between 1 and XT2 is in the state established at entry time Oscillation suspended when used as oscillator input pin Always set to VDD level regardless of state Oscillation state maintained in X tal HOLD mode Feedback resistor between 1 and XT2 is in state established at entry time CF oscillator inverter input Oscillation enabled Feedback resistor present between CF2 CF oscillator inverter output Oscillation suspended Always set to VDD level regardless of CF1 state lt e HOLD mode established at entry time e HOLD mode established at entry time e Same as reset time e Same as reset time LC871A00 Pin Reset Normal Mode HALT Mode HOLD Mode On Exit from Name T
31. Return to step 4 to repeat the conversion processing 3 114 LC871A00 Chapter 3 3 17 6 Hints on the Use of the ADC 1 2 3 4 5 6 The conversion time that the user can select varies depending on the frequency of the cycle clock When preparing a program refer to the latest edition of Semiconductor News to select an appropriate conversion time Setting ADSTART to 0 while conversion is in progress will stop the conversion function Do not place the microcontroller in the HALT or HOLD mode while AD conversion processing is in progress Make sure that ADSTART is set to 0 before putting the microcontroller in the HALT or HOLD mode ADSTART is automatically reset and the AD converter stops operation if a reset is triggered while AD conversion processing is in progress When conversion is finished the end of AD conversion flag ADENDF is set and at the same time the AD conversion operation control bit ADSTART is reset The end of conversion condition can be identified by monitoring ADENDF An interrupt request to vector address 0043H is generated by setting ADIE The conversion time is doubled in the following cases The AD conversion is carried out in the 12 bit AD conversion mode for the first time after a system reset The AD conversion is carried out for the first time after the AD conversion mode is switched from 8 bit to 12 bit AD conversion mode The conversion time determined by the formula g
32. o 2048TBST 1_ 2TBST 8 5 BTIF1 bit 3 Base timer interrupt 1 This flag is set at the interval equal to the base timer interrupt 1 period that is defined by BTFST BTC11 and BTC10 This flag must be cleared with an instruction BTIE1 bit 2 Base timer interrupt 1 request enable control Setting this bit and BTIF1 to 1 generates X tal HOLD mode reset signal and interrupt request to vector address 001BH conditions BTIFO bit 1 Base timer interrupt 0 flag This flag is set at the interval equal to the base timer interrupt 0 period that is defined by BTFST BTC11 and BTC10 This flag must be cleared with an instruction 3 54 LC871A00 Chapter 3 BTIEO bit 0 Base timer interrupt 0 request enable control Setting this bit and BTIFO to 1 generates the X tal HOLD mode reset signal and interrupt request to vector address 001 BH conditions Notes of the system clock and base timer clock must not be selected as the subclock at the same time when BTFST BTCIO 1 high speed mode e Note that 1 is likely to be set to 1 when and BTC10 are rewritten Ifthe hold mode is entered while running the base timer when the cycle clock or subclock is selected as the base timer clock source the base timer is subject to the influence of unstable oscillations caused by the main clock and subclock when they are started following the resetting of the hold mode resulting in a
33. 3 154 LC871A00 Chapter 3 RM2D1L4 to RM2D1L0 RM2XHW bit 4 and RM2DT1W bits 3 to 0 These bits are used to define the lower side of the data 1 pulse width or to generate timing 3 RM2D0H4 to 2 RM2XHW bit and RM2DTOW bits 7 to 4 These bits are used to define the higher side of the data 0 pulse width or to generate timing 2 RM2D0L4 to RM2DOLO RM2XHW bit 2 and RM2DTOW bits to 0 These bits are used to define the lower side of the data 0 pulse width or to generate timing 1 RM2GPH4 to 2 RM2XHW bit 1 and RM2GPW bits 7 10 4 These bits are used to define the higher side of the guide pulse width RM2GPL4 to RM2GPLO RM2XHW bit 0 and RM2GPW bits to 0 These bits are used to define the lower side of the guide pulse width Note See the subsection entitled Operation of the remote control receiver circuit for the operation of the REMOREC2 in various receive format modes 3 155 REMOREC2 3 19 5 Remote Control Receiver Circuit Operation 3 19 5 1 Receive operation when receive format A is specified Receive format A outline Guide pulse Half clock Data encoding system PPM Stop bits No Example of a receive format A receive operation positive phase input RM2RUN set to 1 P73 RMIN Data i Data Data Check end of 4 o 4 reception Data 1 pulse Data 1 pulse Overflow detected criterion value low side criterion value high side high
34. Fundamental PWM mode register PWMOL 0 Fundamental wave period 916256 programmable in 16 increments common to PWMI High level pulse width 0 to Fundamental wave period i Tcyc programmable in 4 Teye increments Fundamental wave Additional pulse PWM mode Fundamental wave period 1916256 programmable in 19 increments common to PWM1 Overall period Fundamental wave period x 16 High level pulse width 0 to Overall period 1 programmable 4 Teye increments PWMI Fundamental wave PWM mode register PWM1L 0 Fundamental wave period programmable in 15 increments common to PWMO High level pulse width 0 to Fundamental wave period Teye programmable in 4 Teye increments PWM1 Fundamental wave Additional pulse PWM mode Fundamental wave period 6259 programmable in 16 increments common to PWMO Overall period 2 Fundamental wave period x 16 High level pulse width 0 to Overall period programmable in 4 Teye increments Interrupt generation Interrupt requests are generated at the intervals equal to the overall PWM period if the interrupt request enable bit is set Shared input pin function The PWMO pins can also serve as input port pins 3 102 LC871A00 Chapter 3 7 control and PWMI it is necessary to manipulate t
35. I O LC871A00 Chapter 1 1 6 Port Output Types The table below lists the types of port outputs and the presence absence of a pull up resistor Data can be read into an input port even if it is in the output mode Option Port name selection Output type Pull up resister unit POO to P07 1 bit Programmable Note 1 N channel open drain No P10 to P17 1 CMOS Programmable P20 to P27 N channel open drain Programmable P30 to P34 P70 N channel open drain Programmable P71 to P73 No CMOS Programmable PWMO PWMI No CMOS No D D No CMOS No XTI Input only No XT2 Output for 32 768kHz crystal N oscillator N channel open drain when in general purpose output mode Note 1 Programmable pull up resistors for port 0 are controlled 4 bit units 04 07 1 7 USB Reference Power Supply Option The USB port output reference voltage is generated by supplying 4 5 to 5 5V to VDD1 and activating the internal USB reference voltage generator circuit The operation of this reference voltage generator circuit can be selected by configuring the USB reference power supply option Select the option as summarized below according to the level of the voltage to be applied to VDDI VDDI voltage V 4 5 to 5 5 3 0 to 3 6 Option setting USB Regulator Use Use Use Nonuse USB Regulator in Use Nonuse Nonuse Nonuse HOLD mode USB Regulator in HALT Use Nonuse Use Nonuse mode Reference Nor
36. Interrupt request Figure 3 12 1 5101 Mode 0 Synchronous 8 bit Serial I O Block Diagram SI1M1 0 511 0 0 3 68 Shift input 8 bit shift register SIOSF1 Shift clock Stop bit data input SBUF1 FE35h Stop bit input clock Clock generation circuit Baud rate SET SI1END when generator stop bit data ends SBR1 FE36h Overrun flag SCONT FE34h Shift input Start stop bit additional circuit ope ration starts LSB MSB first control LC871A00 Chapter 3 Start bit additional circuit 101 output control P13 port latch P13 output control 101 output control P14 port latch P14 output control Interrupt request Figure 3 12 2 5101 Mode 1 Asynchronous Serial UART Block Diagram SI1M1 0 511 0 1 3 69 o 3 12 4 5101 Transmission Examples 3 12 4 1 Synchronous serial transmission mode 0 1 Setting the clock e Set up SBRI when using an internal clock 2 Setting the transmission mode e Set as follows 5 1 0 0 51 1 0 SIIDIR 1 3 up the ports and SIIREC Clock Port P15 Internal clock Output External clock Input Data Output Port Data I O Port SI1REC P13 P14 Data transmission only Output Data transmission reception 3 wire Output Data transmission reception 2 wire N channel open drain output 4 Setting up output data e Write outpu
37. Mode 3 16 bit counter with a 16 bit capture register Timer 1 16 bit timer counter that supports PWM toggle outputs Mode 0 8 bit timer with an 8 bit prescaler with toggle outputs 8 bit timer counter with an 8 bit prescaler with toggle outputs Mode 1 8 bit PWM with an 8 bit prescaler x 2 channels Mode 2 16 bit timer counter with an 8 bit prescaler with toggle outputs toggle outputs also from the lower order 8 bits Mode 3 16 bit timer with an 8 bit prescaler with toggle outputs The lower order 8 bits can be used as a PWM e Timer 6 8 bit timer with a 6 bit prescaler with toggle output e Timer 7 8 bit timer with a 6 bit prescaler with toggle output e Base timer 1 The clock is selectable from subclock 32 768 kHz crystal oscillator system clock and timer 0 prescaler output 2 Interrupts programmable in 5 different time schemes Serial I O e 100 Synchronous serial interface 1 LSB first MSB first modes selectable 2 Transfer clock cycle to i Tcyc 3 Automatic continuous data communication 1 to 256 bits selectable on a bit basis suspension and resumption of transfer controllable on a byte basis e SIO1 8 bit asynchronous synchronous serial interface Mode 0 Synchronous 8 bit serial I O 2 or 3 wire configuration 2 to 512 Tcyc transfer clocks Mode 1 Asynchronous serial I O half duplex 8 data bits 1 stop bit 8 to 2 048 Tcyc baudrates Mode 2 Bus mode 1 start bit 8 data bits
38. O sms FED3 0000 0000 R W TBUF TBUF7 TBUF6 TBUF5 4 TBUF2 TBUF 1 TBUFO ww m O rr Raves mura ms mwmm Wwe Lu mo emo ww sux O Ss SEU m cm ox ww sem O mw emo mu ee es oma cus FED9 0000 0000 R W CRCH CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8 AI 7 LC871A00 APPENDIX I Address Initial value R W LC871A00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FEDA 0000 0000 R W CRCCNT CRCON CRCLRZ CRCRD 1 05 S4STPCEN S4STPCHI S4STPSL1 S4STPSLO m sux sew stant m ww sum O Mt ze eorr Pazour sur O SF sasore ww O O SU mo sum O saora snow ww sent
39. SI DIR bit 3 MSB LSB first select 1 Setting this bit to 1 places SIOI into the MSB first mode 2 Setting this bit to 0 places SIOI into the LSB first mode SI1OVR bit 2 5101 overrun flag 1 This bit is set when a falling edge of the input clock is detected when SI1RUN is set to 1 in mode 0 1 or 3 2 This bit is set when a falling edge of the input clock is detected when SI1RUN is set to 1 in mode 0 1 or 3 3 In mode 3 this bit is set when the start condition is detected 4 This bit must be cleared with an instruction SITEND bit 1 End of serial transmission 1 This bit is set when serial transmission terminates see Table 3 12 1 2 Thisbit must be cleared with an instruction SI1IE bit 0 SIO1 interrupt request enable control When this bit and are set to 1 an interrupt request to vector address 003BH is generated 3 74 LC871A00 Chapter 3 3 12 5 2 Serial buffer 1 SBUF1 1 Serial buffer 1 is 9 bit register used to store data to be handled during 5101 serial transmission 2 lower order 8 bits of SBUFI are transferred to the data shift register for data transmission reception at the beginning of transmission processing and the contents of the shift register are placed in the lower order 8 bits of SBUF1 when 8 bit data is transferred 3 In modes 1 2 and 3 bit 8 of SBUFI is loaded with the 9th data bit that is received data about the position of the stop bit FE35 00000
40. Setting up the receive format D timings The REMOREC2 generates four timing signals to check for the reception of a remote control signal Timing 1 sampling Value given by RM2DOLA to RM2DOLO 1 x RM2CK Timing 2 data identification Value given by RM2D0H4 to RM2DOHO 1 x RM2CK Timing 3 sampling Value given by RM2DILA to RM2DILO 1 x RM2CK Timing 4 detecting end of reception Value given by RM2D1H4 to RM2D1HO 1 x RM2CK or greater The remote control signal is sampled at timings 1 and 3 The resultant two data bits are tested for 0 1 and error conditions Note The register values must be such that value given by RM2DOL4 to RM2DOLO lt value given by RM2D0H4 to RM2DOHO lt value given by RM2D1LA to RM2DILO lt value given by RM2D1H4 to RM2DIHO Note The minimum criterion value is RM2CK x 4 The interval between timings 1 to 4 must be set up at intervals of RM2CK x 4 or greater Receive format D receive operation 1 When the REMOREC2 detects the first rising edge of the remote control signal at the beginning or resumption of a receive operation it resets the RM2SFT and RM2BCT 2 Attiming 1 the REMOREC2 samples the remote control signal 3 Attiming 2 the tests and identifies the data that are sampled in steps 2 and 6 When identifying the first data the REMOREC identifies it as data 1 if an H is sampled at timing 1 a data error is identified if an L is sampled 4 the
41. VDD1 VDD2 power supply pin Ta USB reference power supply pin 8 bit I O port Tu to P07 O specifiable in 4 bit units Pull up resistors can be turned on and off in 4 bit units HOLD release input Port 0 interrupt input Pin functions AD converter input port pins ANO to AN7 P00 to P07 P05 System clock output P06 Timer 6 toggle output P07 Timer 7 toggle output 8 bit I O port P10 to P17 O specifiable in 1 bit units Pull up resistors can be turned on and off in 1 bit units Pin functions P10 SIOO data output P11 SIOO data input bus I O P12 SIOO clock I O P13 5101 data output P14 5101 data input bus I O P15 5101 clock P16 Timer 1 PWML output P17 Timer 1PWMH output beeper output Pot2 2 8 bit I O port te to P27 I O specifiable in 1 bit units Pull up resistors can be turned on and off in 1 bit units Pin functions P20 P23 INT4 input HOLD release input timer 1 event input timer OL capture input timer capture input P24 P27 INT5 input HOLD release input timer 1 event input timer OL capture input timer OH capture input P20 UARTI transmit P21 UARTI receive P22 8104 data I O parallel interface RD output P23 8104 data I O parallel interface WR output P24 8104 clock I O 5 ka type a PERE 5 Continued next page 1 9 Pin Functions continued Description Option 5 bit I O port Yes I O specifiable in 1 bit un
42. and the match register have the same value when in inactive state TIHRUN 0 If active TIHRUN 1 the match buffer register is loaded with the contents of TIHR when the value of T1H reaches 0 Timer 1 low byte output TTPWML The TIPWML output is fixed at the high level when TIL is inactive If TIL is active the TIPWML output is fixed at the low level when TILR FFH Timer 1 low byte output is a toggle output whose state changes on a TIL match signal when TIPWM timer 0 control register bit 4 is set to 0 When TIPWM timer 0 control register bit 4 is set to 1 this PWM output is cleared on an TIL overflow and set on a TIL match signal Timer 1 high byte output TTPWMH The TIPWMH output is fixed at the high level when TIH is inactive If TIH is active the TIPWMH output is fixed at the low level when TIHR FFH The timer 1 high byte output is a toggle output whose state changes on a TIH match signal when TIPWM 0 TILONG 1 When TIPWM 1 and T1LONG 0 this PWM output is cleared on overflow and set on a match signal 3 40 LC871A00 Chapter 3 Clock 2Tcyc gt or external events Set in l45CR FE4Ah I45SL FE4Bh registers Clock 2Tcyc gt T1H prescaler T1PWML output T1L prescaler Match Comparator Clear Invert T1PWMH output Match buffer register Match buffer register Reload Reload SS 8 T1LCMP 1 TILR
43. of start bits is 1 i bit D 11 bit shift register RSFT js At end of receive operation RSFT gt RBUF RBUF FED4h E Data bit 8 9 bit data receive mode only Clock generator circuit Start bit Baudrate Falling edge detector 21 enerator At beginning of circuit Note UBR FED2h UCONO FEDOh Interrupt request Note Bit 1 of P2DDR at FE49 must be set to 0 when the UARTI is to be used in the receive mode the UARTI will not function normally if bit 1 is set to 1 Figure 3 15 1 UART1 Block Diagram Receive Mode 3 94 LC871A00 Chapter 3 Stop bit Note The position of the stop bit differs depending on the bit length to be transferred bit 11 bit shift register TSFT Clock Data output LSB first cae End of transfer to shift register At beginning of transmit operation TBUF gt TSFT TBUF FED3h Clock generator Data bit 8 circuit only for 9 bit transfer data length Baudrate generator UBR FED2h UART1 output M poo UART1 output format control Note FED1h Interrupt UCONO FEDOh bit 7 reques Note Bit 0 of P2DDR at FE49H must be set to 0 when the UARTI is to be used in the transmit mode the UARTI will not function normally if bit 0 is set to 1 Figure 3 15 2 UART1 Block Diagram Transmit Mode 3 15 4 Related Registers 3 1541 UART1 control re
44. ww LL ug wah wwe l mss mwmm ww ms mmmm ww 4 mw mwmm wwe 1 ms Wee ms noone S AnoHstLo ADSTART AE _ Feso ww O w sw sow mw muc S uo Mz 0000 0000 res 0000 0000 Rw Pr iib G ko Pow Prom Pow rm rm en P5 FESD 0000 0000 R W 1010 INTILH INTILV INTOLH INTOLV INTOIF INTOIE AI 3 LC871A00 APPENDIX I Address Initial value R W LC871A00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO 0000 0000 R W 1230 INT3HEG INTSLEG INTSIF INT2HEG INT2LEG INT2IF INT21E ms Raf ist O O sre OI ub WE ms ww LL LL LLLI mg wwe l m ww L LL me ww me ww
45. Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 R W TOCNT TOHRUN TOLRUN TOLONG TOLEXT TOHCMP TOHIE TOLCMP TOLIE TOPRR4 TOPRR2 re 0000000 m ro roe Toro 00000000 T TOLR TOCAL7 TOCAL6 TOCALS TOCAL4 TOCAL3 TOCAL2 TOCALI EN 17 TOCALS TOCALA TOCAL3 TOCAL2 TOCAH 7 TOCAH6 5 Tocana TOCAH2 TOCAHI 7 TOCAILS TOCAILA TocA1L2 R 3 6 3 Circuit Configuration 3 6 3 1 Timer counter 0 control register TOCNT 8 bit register 1 This register controls the operation and interrupts of TOL and TOH 3 6 3 2 Programmable prescaler match register TOPRR 8 bit register 1 This register stores the match data for the programmable prescaler 3 24 3 6 3 3 2 3 4 3 6 3 4 2 3 4 3 6 3 5 2 3 4 3 6 3 6 2 3 6 3 7 2 LC871A00 Chapter 3 Programmable prescaler 8 bit counter Start stop This register runs in modes other than the HOLD mode Count clock Cycle clock period 1 Match signal match signal is generated when the count
46. P1 FE44 and the I O direction is controlled by the port 1 data direction register PIDDR FE45 Each port bit is provided with a programmable pull up resistor 2 Shared functions P17 is also used as the timer 1 PWMH base timer BUZ output P16 as the timer 1 PWML output P15 to P13 as 5101 I O and P12 to P10 as 5100 I O Address Initial Value R W BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE44 0000 0000 R W P11 P10 ona Eo rene tens panne euis Reo 0000 ww rircn ister eisrcn Prince 3 2 3 Related Registers 3 2 3 1 Port 1 data latch P1 1 The port 1 data latch is an 8 bit register for controlling port 1 output data and pull up resistors 2 When this register is read with an instruction data at pins P10 to P17 is read in If P1 FE44 is manipulated with an instruction NOT1 CLR1 SET1 DBZ DBNZ INC or DEC the contents of the register are referenced instead of the data at port pins 3 Port 1 data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE44 0000 0000 R W Pl P17 P16 P15 P14 P13 P12 P11 P10 3 6 LC871A00 Chapter 3 3 2 3 2 Port 1 data direction register P1DDR 1 The port 1 data direction register is an 8 bit register that controls the I O direction of port 1 data on bit basis Port
47. PI PIDDR PIFCR 3 52 3 10 3 3 10 3 1 1 3 10 3 2 1 3 10 3 3 1 LC871A00 Chapter 3 Circuit Configuration 8 bit binary up counter This counter is an up counter that receives as its input the signal selected by the input signal select register ISL It generates 2 kHz buzzer output and base timer interrupt 1 flag set signals The overflow out of this counter serves as the clock to the 6 bit binary counter 6 bit binary up counter This counter is a 6 bit up counter that receives as its input the signal selected by the special function register ISL or the overflow signal from the 8 bit counter and generates set signals for base timer interrupts 0 and 1 The switching of the input clock is accomplished by the base timer control register BTCR Base timer input clock source The clock input to the base timer fBST can be selected from cycle clock and subclock via the input signal select register ISL timer 0 prescaler Set in ISL FE5Fh register 16 5 Buzzer output Tcyc 5 Timer 0 prescaler 3 BST _ 8 bit counter Sub clock 256TBST 8 6 bit counter 16384 64TBST gt set gt flag set Selector 2048 8 5 Figure 3 10 1 Base Timer Block Diagram 3 53 3 10 4 Related Registers 3 10 4 1 Base timer control register BTCR 1 The base timer control register is an
48. TIH Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE18 0000 0000 R W TICNT TIHRUN TILRUN TILONG TIPWM TIHCMP TILCMP T1HRUN bit 7 count control When this bit is set to 0 timer 1 high byte T1H stops on a count value of 0 The match buffer register of 1 has the same value as TIHR When this bit is set to 1 timer 1 high byte T1H performs the required counting operation TA1LRUN bit 6 count control When this bit is set to 0 timer 1 low byte TIL stops on a count value of 0 The match buffer register of TIL has the same value as TILR When this bit is set to 1 timer 1 low byte T1L performs the required counting operation T1LONG bit 5 Timer 1 bit length select When this bit is set to 0 timer 15 higher and lower order bytes serve as independent 8 bit timers When this bit is set to 1 timer 1 serves as a 16 bit timer since the timer 1 high byte T1H counts up at the interval of the timer 1 low byte T1L Independent match signals are generated from and TIL when their count value matches the contents of the corresponding match buffer register regardless of the value of this bit T1PWM bit 4 T1 output mode select This bit and TILONG bit 5 determine the output mode of TI TIPWMH TIPWML as summarized in Table 3 8 1 Table 3 8 1 Timer 1 Output T1PWMH T1PWML T1PWMH T1PWM
49. When T6CO and T67CNT FE78 bit 4 and 5 are set to 0 the timer 6 counter stops at a count value of 0 In the other cases the timer 6 counter continues operation 3 When data is written into while timer 6 is running both the timer 6 s prescaler and counter are temporarily cleared then restart counting 3 47 T6 T7 3 9 4 2 Timer 6 prescaler TGPR 6 bit counter 1 This prescaler is used to define the clock period for the timer 6 determined by T6CO and T6C1 T67CNT FE78 bits 4 and 5 Table 3 9 1 Timer 6 Count Clocks T6 Count Clock Timer 6 prescaler and timer counter are reset 3 9 42 Timer 6 period setting register 8 bit register 1 Thisregister defines the period of timer 6 2 When data is written into T6R while timer 6 is running both the timer 6 s prescaler and counter are temporarily cleared then restart counting 3 9 4 2 Timer 7 counter T7CTR 8 bit counter 1 The timer 7 counter counts the number of clocks from the timer 7 prescaler T7PR The value of timer 7 counter T7CTR reaches 0 on the clock following the clock that brought about the value specified in the timer 7 period register T7R when the interrupt flag T7OV is set 2 When 7 and 7 T67CNT FE78 bits 6 and 7 are set to 0 the timer 7 counter stops at a count value of 0 In the other cases the timer 7 counter continues operation 3 When data is written into T7R while timer 7 is running both th
50. 0 1 0 Error 1 0 Valid Update ACK 0 1 0 0 ACK OUT 0 1 0 IN 0 0 1 0 Invalid Update 0 0 1 1 Error 0 0 1 1 SETUP Valid Update ACK 0 1 0 0 OUT 0 0 1 1 IN 0 0 1 1 Invalid Update 0 1 0 0 Error SETUR Valid Update ACK 0 1 0 0 ACK 0 1 0 0 Invalid 0 1 0 0 Valid NAK 0 1 0 0 IN NAK 0 1 0 0 Invalid Update 0 1 0 1 Error Valid Update ACK 0 1 0 0 ACK 0 1 0 1 Invalid 0 1 0 1 QUI Valid NAK 0 1 0 1 NAK IN NAK 0 1 0 1 NAK Invalid Update 0 1 1 0 Error Valid Update ACK 0 1 0 0 ACK 0 1 1 0 Invalid 0 1 1 0 Valid NAK 0 1 1 0 IN NAK 0 1 1 0 Invalid Update 0 1 1 1 Error SETUP Valid Update ACK 0 1 0 0 ACK 0 1 1 1 Invalid 0 1 1 1 ad Valid NAK 0 1 1 1 IN NAK 0 1 1 1 Invalid Update 1 0 0 0 Error 1 0 0 0 SETUP Valid Update ACK 0 1 0 0 OUT 1 0 0 0 IN 1 0 0 0 Invalid Update 1 0 0 1 1 0 0 SELUE Valid Update ACK 0 1 0 0 OUT 1 0 0 1 IN 1 0 0 1 Invalid Update 1 0 1 0 Error 0 1 0 Valid Update 0 1 0 0 OUT 1 0 1 0 IN 1 0 1 0 Invalid Update 1 0 1 1 Error 1 0 1 SETUP Valid Update ACK 0 1 0 0 OUT
51. 1 Mode 2 The contents of TOL are captured into the capture register TOCAL on external input detection signals from the P70 INTO TOLCP and P72 INT2 TOIN and P20 to P27 timer OL capture input pins The contents of TOH are captured into the capture register TOCAH on external input detection signals from the P71 INTI TOHCP and P73 INT3 TOIN and P20 to P27 timer OH capture input pins TOL period TOLR 1 x TOPRR 1 x Tcyc period 1 x 1 x Period of cycle clock register 8 bit programmable counter equipped with an 8 bit capture register TOL serves as an 8 bit programmable counter that counts the number of external input detection signals from the P72 INT2 TOIN and P73 INT3 TOIN pins serves as an 8 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on external input detection signals from the P70 INTO TOLCP and P72 INT2 TOIN and P20 to P27 timer OL capture input pins The contents of TOH are captured into the capture register TOCAH on external input detection signals from the P71 INTI TOHCP and P73 INT3 TOIN and P20 to P27 timer OH capture input pins TOL period TOLR 1 period TOHR 1 x TOPRR 1 x Tcyc capture register 3 23 8 bit programmable timer with a programmable prescaler equipped with an 8 bit captu
52. 1 64 1 1 1 0 128 1 1 1 1 256 4 Reset When the timer 1 stops operation or a reset signal is generated LC871A00 Chapter 3 3 8 3 4 Timer 1 prescaler high byte 8 bit counter 1 Start stop The start stop of timer 1 prescaler high byte is controlled by the 0 1 value of TIHRUN timer 1 control register bit 7 2 Count clock Varies with the mode Mode T1LONG T1PWM T1H Prescaler Count Clock 0 0 0 2 Tcyc 1 0 1 1 2 1 0 TIL match signal 3 1 1 256 x TILPRC count x 3 Prescaler count Determined by the TIPRC value The count clock for is generated at the intervals determined by the prescaler count T1HPRE T1HPRC2 T1HPRC1 1 Prescaler Count 0 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 4 Reset When the timer 1 stops operation or a T1H reset signal is generated 3 8 3 5 1 low byte 8 bit counter 1 Start stop The start stop of the timer 1 low byte is controlled by the 0 1 value of TILRUN timer 1 control register bit 6 2 Count clock prescaler output clock 3 Match signal A match signal is generated when the count value matches the value of the match buffer register 4 Reset The timer 1 low byte is reset when it stops operation or a match signal occurs on the mode 0 or 2 condition 3 8 3 6 Timer 1 h
53. 12 2 This flag must be cleared with an instruction 3 130 LC871A00 Chapter 3 AK4EN bit 6 EP4 ACK interrupt request enable flag 1 interrupt to vector address 003BH is generated when this bit AKAFG and ENPEN are all set to 1 NK4FG bit 5 EPA end flag 1 Set to 1 when the endpoint 4 transaction terminates with See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction NKAEN bit 4 4 interrupt request enable flag 1 An interrupt to vector address 003BH is generated when this bit NK4FG and ENPEN are all set to 1 ER4FG bit 3 EP4 error end flag 1 Set to 1 when the endpoint 4 transaction terminates with an error See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction ER4EN bit 2 EPA error interrupt request enable flag 1 An interrupt to vector address 003BH is generated when this bit ER4FG and ENPEN are all set to 1 ST4FG bit 1 4 stall end flag 1 Set to 1 when the endpoint 4 transaction terminates with a stall See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction ST4EN bit 0 4 stall interrupt request enable flag 1 An interrupt to vector address 003BH is generated when this bit ST4FG and ENPEN are all set to 1 3 18 4 11 Frame number register FRAMEL FRAMEH 1 The frame number register is loaded with the frame nu
54. 4 14 LC871A00 Table 4 3 1 Standby Mode Operations Item mode Reset State HALT Mode HOLD Mode X tal HOLD Mode Entry conditions RES applied PCON register PCON register PCON register Reset from watchdog pit 1 0 Bit 220 Bit 2 1 timer Bit 0 1 Bit 1 1 Bit 1 1 Data changed on Initialized as shown WDT bits 2 to Oare 1 15 d e are s ee is x DE are cleared 1 register cleared 1 register entry in separate table cleared if WDT FEOF bit 4 is 2 FEOF bit 4 is register FEOF bit 4 e PCON bit 0 turns to 1 e PCON bit 0 turns to 1 15 set OCR register FEOE bits 5 4 1 and 0 are cleared Main clock Running State established at Stopped Stopped oscillation entry time Built in RC Running State established at Stopped Stopped oscillation entry time Subclock Stopped State established at Stopped State established at oscillation entry time entry time USB dedicated Running State established at Stopped Stopped PLL oscillation entry time CPU Stopped Stopped Stopped RAM RES Unpredictable Data preserved Data preserved Data preserved When watchdog timer reset Data preserved Base timer Stopped State established at Stopped State established at entry time entry time Peripheral Stopped State established at Stopped Stopped modules except entry time Note 2 base timer Exit conditions Entry conditions Interrupt request Interrupt request from e Interrupt request from accepted INTO to INT2 INT4 INT
55. 4 7 4 2 4 Related Registers Pee errr ee ee ere reer eee ee ee eee ee eee ere eee ee ere ee ete ee eee eee eee eee 4 9 4 3 Standby Function ee 4 14 4 3 1 Overview Peete eee eee etre etree ree treet reer reer retiree reer rrr reer 4 14 4 3 2 Functions Peete etree ere rere rere rere reer reer ree rr eer r rere terete rere rere terre errr err tert retire 4 14 4 3 3 Related Registers M n 4 14 4 4 Reset Function reer rire errr etre rire 4 1 9 4 4 1 Overview eee eee eee eee terete rere etree treet reer rete teeter ALD 4 1 9 4 4 2 Functions Peer eee ere 4 1 9 iv Contents 4 4 3 Reset State 4 20 4 5 Watchdog Timer Function 4 21 4 5 1 Overview
56. 4 and 5 NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select STOIN bit 0 Timer 0 counter clock input port select These 3 bits have nothing to do with the control function on the base timer 3 55 00 3 11 Serial Interface 0 5100 3 11 1 Overview The serial interface SIOO incorporated in this series of microcontrollers has the following two major functions 1 Synchronous 8 bit serial I O 2 or 3 wire system clock rates of 4 to 212 2 Continuous data transmission reception transmission of data whose length varies between 1 256 bits in bit units clock rates of 3 to 542 3 11 2 Functions 1 Synchronous 8 bit serial I O Performs 2 or 3 wire synchronous serial communication The clock may be an internal or external clock The clock rate of the internal clock is programmable within the range of 1 x 2 n 1 to 255 Note n 0 is inhibited 2 Continuous data transmission reception Transmits and receives bit streams whose length is variable in 1 bit units between and 256 bits Transmission is carried out in the clock synchronization mode Either internal or external clock can be used The clock rate of the internal clock is programmable within the range of 1 x 2 n to 255 Note 0 is inhibited 1 to 256 bits of send data is automatically transferred from RAM to the data shift register SBUFO and receive data is
57. 40 H Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE98 H000 0000 EPICNT 5 EICN4 E1CN3 1 2 EICNI 3 18 4 23 1 receive data count register EP1RX 1 EPI receive data count register indicates the number of data bytes received at endpoint 1 2 The contents of this register are updated when an OUT transaction for endpoint 1 terminates normally with an ACK Address Initial Value R W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE99 H000 0000 R EPIRX EIRX6 EIRXS EIRX4 EIRX3 EIRX2 EIRXI EIRXO 3 18 4 24 EP2 count register EP2CNT 1 The EP2 count register must be loaded with the number of transmit data bytes for endpoint 2 1f the transfer direction of endpoint 2 is IN E2DIR 1 2 If the transfer direction of endpoint 2 is OUT E2DIR 0 this register must be loaded with the maximum payload size of endpoint 2 3 The legitimate value range is from 00 H to 40 H Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE9A 000 0000 R W EP2CNT E2CN6 E2CN5 E2CN4 E2CN3 E2CN2 E2CNI E2CNO 3 18 4 25 EP2 receive data count register EP2RX 1 The EP2 receive data count register indicates the number of data bytes received at endpoint 2 2 The contents of this register are updated when an OUT transaction for endpoint 2 terminates normally with an ACK Address Initial Value R W Name BIT7 BI
58. 5 When the REMOREC2 detects the end of reception condition it sets the RM2REND and RM2HOLD flags and suspends operation Subsequently when the RM2SFT is read the 2 clears the RM2HOLD flag and enters the idle state waiting for a guide pulse resuming the receive operation 3 19 5 2 Receive operation when receive format B is specified Receive format outline Guide pulse Clock Data encoding system PPM Stop bits Yes Example of a receive format B receive operation positive phase input RM2RUN set to 1 V P73 RMIN 1 i i 4 Data 0 Check end of reception Guide pulse criterion value high side Guide pulse criterion value low side Data 1 pulse criterion value Data 1 pulse criterion Overflow detected low side value high side RM2MJCT count value Edge detected Edge detected Data 0 pulse Data 0 pulse End of Count start Count reset amp criterion value criterion value reception start low side high side Setting up the receive format B criterion values 1 Check the pulse width from rising edge to rising edge of the guide pulse 2 3 Check the pulse width from rising edge to rising edge of data and 1 4 Detect an end of reception condition from rising edge to overflow of data 1 criterion value The criterion values are the same as those for the receive format A Receive format B receive operation The REMOREC 2 takes the same acti
59. BIT1 BITO FE4C 0000 R W P3 P34 P33 P32 P31 P30 ru ww boc gt espor 3 4 3 Related Registers 3 4 3 1 Port 3 data latch P3 1 This data latch is a 5 bit register for controlling the port 3 output data and its pull up resistors 2 When this register is read with an instruction the data at pins P30 to P34 is read in If P3 FE4C is manipulated using the NOT1 CLR1 SET1 DBZ DBNZ INC or DEC instruction the contents of the register is referenced instead of the data at the pins 3 Data can always be read from port 3 regardless of its I O state Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE4C HHHO 0000 R W P34 P33 P32 P31 P30 3 4 3 2 Port 3 data direction register P3DDR 1 The port 3 data direction register is 5 bit register for controlling the I O direction of 3 port data on a bit basis Port P3n is placed in the output mode when bit P3nDDR is set to 1 and in the input mode when bit P3nDDR is set to 0 2 Port P3n is designated as an input with a pull up resistor when bit P3nDDR is set to 0 and bit P3n of port 3 data latch is set to 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE4D HHHO 0000 R W P3DDR P34DDR P33DDR P32DDR P31DDR P30DDR Register Data Port P3n State Built in Pull up Input Resistor Enabled Enabled CMOS N ch
60. Circuit Block Diagram 3 18 3 1 USB interface PLL circuit The internal USB interface PLL circuit generates the USB data sampling clock 48 MHz 3 18 3 2 Clock control circuit The clock control circuit turns on and off the clock to the DPLL and USB device controller 3 18 33 circuit 1 Generates the transmit receive clock 12 MHz 2 Samples the received data 3 Detects EOP 4 Detects the bus reset signal 5 Detects the suspend condition 3 18 3 4 USB device controller circuit 1 Performs NRZI encoding decoding 2 Performs bit stuffing unstuffing 3 Performs serial to parallel conversion 3 119 4 5 6 7 3 18 3 5 1 2 3 4 5 3 18 3 6 1 2 Detects packets Detects the device address and endpoints Performs CRC generation and check Exercises protocol control CPU interface circuit Contains registers for controlling the operation of the USB interface circuit Generates interrupt requests to the CPU Has a data transmit receive buffer Transfers transmit data from RAM endpoint buffer to the transmit receive buffer Transfers receive data from the transmit receive buffer to RAM end point buffer Endpoint configuration The USB interface circuit allows a maximum of 5 endpoints to be configured The table below lists the transfer types that each endpoint supports buffer sizes and the RAM addresses to which the data buffers are mapped 3 120 LC871A00 Chapter 3
61. EPO ACK flag 1 Set to when the endpoint 0 transaction terminates with an ACK See the column entitled End Flags in Table 3 18 11 2 This flag must be cleared with an instruction AKOEN bit 6 EPO ACK interrupt request enable flag 1 interrupt to vector address 003BH is generated when this bit AKOFG and ENPEN are all set to 1 NKOFG bit 5 EPO NAK end flag 1 Set to 1 when the endpoint 0 transaction terminates with a See the column entitled End Flags in Table 3 18 11 2 This flag must be cleared with an instruction NKOEN bit 4 EPO NAK interrupt request enable flag 1 interrupt to vector address 003BH is generated when this bit NKOFG and ENPEN are all set to 1 EROFG bit 3 EPO error end flag 1 Set to 1 when the endpoint 0 transaction terminates with an error See the column entitled End Flags in Table 3 18 11 2 This flag must be cleared with an instruction 3 127 USB EROEN bit 2 EPO error interrupt request enable flag 1 interrupt to vector address 003BH is generated when this bit EROFG and ENPEN are all set to 1 STOFG bit 1 EPO stall end flag 1 Set to 1 when the endpoint 0 transaction terminates with a stall See the column entitled End Flags in Table 3 18 11 2 This flag must be cleared with an instruction STOEN bit 0 EPO stall interrupt request enable flag 1 interrupt to vector address 003BH is generated when this bit STOFG and ENPEN are all set to
62. HOLD X tal HOLD See Section 4 3 Standby Function for the procedures to enter and exit the microcontroller operating modes Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEO7 HHHH H000 R W PCON XTIDLE PDN IDLE bits 7 to 3 These bits do not exist They are always read 1 XTIDLE bit 2 X tal HOLD mode flag PDN bit 1 HOLD mode setting flag XTIDLE PDN Operating mode Normal or HALT mode 0 Poot HOLD mode HOLD mode 1 These bits must be set with an instruction Ifthe microcontroller enters the HOLD mode all oscillations main clock subclock RC and PLL are suspended and bits 0 1 4 and 5 of the OCR are set to 0 When the microcontroller returns from the HOLD mode the main clock and RC oscillators resume oscillation The subclock and PLL oscillators restore the state that 1s established before the HOLD mode is entered and the system clock 15 set to RC When the microcontroller enters the X tal HOLD mode all oscillations except XT main clock RC and PLL are suspended but the contents of the OCR register remain unchanged When the microcontroller returns from the X tal HOLD mode the system clock to be used when the X tal HOLD mode is entered needs to be set to either subclock or RC because it 1s impossible to reserve the oscillation stabilization time for the main clock 4 8 LC871A00 Since the X tal HOLD mode is used usuall
63. P1DDR FUNCTION outputs 5 0 Table of Port 1 Shared Pin Functions P1FCR FE46 bits 5 0 gt abet W P1FCR R P1FCR 4 P1 FE44 bits 5 0 DHe Pin Q Nch OD OR P15 P10 W P1 5 L 1 P1DDR FE45 bits 5 0 Q W P1DDR R P1DDR Port 1 Block Diagram Option Output type CMOS or N channel OD selectable on a bit basis 2 LC871A00 APPENDIX II P2 FE48 bits 7 5 1 W P2 P27 P25 P21 Special input P21 R P2 P2DDR FE49 bits 7 5 1 W P2DDR R P2DDR sng FUNCTION outputs 4 2 0 P2 FE48 bits 4 2 0 W P2 Pin P24 P22 P20 R P2 P2DDR FE49 bits 4 2 0 D Q W P2DDR R P2DDR 5104 data input 104 data output UART1 data input UART1 data output Table of Port 2 Shared Pin Functions Port 2 Pin Block Diagram Option Output type CMOS or N channel OD selectable on a bit basis 3 Port Block Diagrams P27 P26 S P25 E 24 Timer 1 count clock Timer OL capture signal Timer OH capture signal Int request to address 00013 Int request to address 0001B Timer 1 count clock 23 22 L S lt gt 5 E Y E Pe Timer OL capture signal Timer OH capture signal Port 2 Interrupt Block Diagram 4 LC871A00 APPENDIX II 4 bits 4 0 P34 P30 R P3 P3DDR FE4D bits 4 0 W PSDDR R PSDDR Port 3 Block Diagram Opti
64. P1n are placed in the output mode when bit PInDDR is set to 1 and in the input mode when bit PInDDR is set to 0 2 When bit PInDDR is set to 0 and the bit P1n of the port 1 data latch is set to 1 port PIn becomes input with a pull up resistor Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE45 0000 0000 R W PIDDR PI7DDR PI6DDR PI5DDR P14DDR PI3DDR P12DDR P11DDR P10DDR Register Data Port Pin State Built in Pull up Resistor Input Enabled ae Enabled High open CMOS N channel open drain 3 2 3 3 Port 1 function control register P1FCR 1 The port 1 function control register is an 8 bit register that controls the shared functions of port 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE46 0000 0000 R W PIFCR PI6FCR PISFCR PI4FCR P13FCR PI2FCR PIOFCR PinFCR Pin Pin Data in Output Mode P1nDDR 1 Value of Ped data latch P17 ee U 1 Nawborimer PWMHawwenmerBuz 1 9 Wale oF por data ach ris 1 ERE 1 9 ki m n cupo ERE Value of port data latch P12 SIOO clock output data High output Value of port data latch P11 ome ge Value of port data latch P10 The high data output at a
65. The baudrate is programmable within the range of 8 to 2048 Tcyc 3 Mode 2 Bus master SIOI is used as a bus master controller The start conditions are automatically generated but the stop conditions must be generated by manipulating ports Clock synchronization is used Since it is possible to verify the transfer time bus data at the end of transfer this mode can be combined with mode 3 to provide support for multi master configurations The period of the output clock is programmable within the range of 2 to 512 Tcyc 4 Mode 3 Bus slave 5101 is used as a slave device of the bus Start stop condition detection processing is performed but the detection of an address match condition and the generation of an acknowledge require program intervention SIOI can generate an interrupt after automatically placing the clock line at the low level on the falling edge of the eighth clock for recognition by a program 5 Interrupt generation An interrupt request is generated at the end of communication if the interrupt request enable flag is set 6 Tocontrol serial interface 1 SIO1 it is necessary to control the following special function registers SCONI SBUFI SBR1 PI PIDDR PIFCR Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE34 0000 0000 R W SCONI SIIMI SIIMO SIIRUN SH REC SIIDIR 5 SILEND SIE 000000 ser ssmcr7 ssgcie
66. To control the parallel interface it is necessary to manipulate the following special function registers e SIACNO SIACNI SIABUF PI PIDDR P2 P2DDR Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEDB 0000 0000 R W SI4CNO SI4RUN SBITON MSBSEL S4RAM S4CKPL SI4WRT SI4END SIME 3 14 3 Related Registers See Subsection 3 13 4 for a description of the special function registers SI4CNO SI4CN1 and SI4BUF for controlling the parallel interface 3 89 3 14 4 Parallel Interface Programming Example An example of configuring the special function registers for using the parallel interface is shown below followed by related timing charts 1 2 3 4 5 Initialization Before using the parallel interface it is necessary to perform the following sequence of initialization steps shifting the SIO4 shift register by 1 bit and loading a 1 into the output data latch once Load SIACNI with OO H Load SIABUF with FF H loading FF H into the shift register Load SIACNO with 80 H setting SIARUN to 1 Set P2 bit 4 to 1 and P2DDR bit 4 to 1 to generate a 1 from P24 Set P2 bit 4 to 0 to generate 0 from P24 Set P2DDR bit 4 to 0 Load SIACNO with OO0 H Setting up the parallel interface mode SIACNI PARA 1 Setting up the port SIACNI e P220UT 1 P22MOS 1 to generate the read signal e P230UT 1 P23MOS 1 to generate the write signal
67. UUUUUUUUUUT AARROSRRESSZ CORSBE SSOUEATS gt 25 GOGGSUOB 3 asezz Z ASG EZB dz EX eu E gt NIWI NIOL C LNI CLd 1 6 LC871A00 Chapter 1 SQFP48 NAME SQFP48 NAME P23 INT4 SI4 WR 3 mas 1 7 1 4 System Block Diagram Interrupt controller 4 zc Standby controller IR PLA FROM PLL for USB RC 0 0 Clock generator 100 gt 101 gt 5104 0 gt gt id ACC Bus interface gt Port 0 Port 1 M 4 Port 2 Timer 1 gt Port 3 lt gt Port 7 INTO to INT5 Noise filter UART1 ADC Timer 6 7 I Base timer M 4 PWMO gt PWM1 4 gt USB Interface E Infrared remote control 1 8 Lr B register C resister gt PSW y w Watchdog timer Stack pointer On chip debugger LC871A00 Chapter 1 1 5 Pin Functions Pin Description VSS1 VSS2 power supply pin VSS3
68. Value R W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE95 0000 0000 R W EP4STA E4EN E4TGL E4OVR E4STL E4ACK E4DIR E4ISO E4BNK E4EN bit 7 EP4 enable flag 1 If this bit is set to 1 the USB interface processes the token at endpoint 4 2 Ifthis bit is set to 0 the USB interface does not process the token at endpoint 4 E4TGL bit 6 EP4 data toggle 1 Onan OUT transaction the receive data is transferred to RAM only when the packet ID in the data packet from the host matches E4TGL The state of E4TGL is automatically inverted when the transaction terminates normally with an ACK The E4TGL state does not invert however for isochronous transfers 2 IN transaction the USB interface transmits the data packet with a packet ID matching E4TGL The state of E4TGL is automatically inverted when the USB interface receives an ACK from the host E4OVR bit 5 EP4 payload over flag 1 This bit is automatically set to 1 when the USB interface receives a volume of data exceeding the maximum payload size defined in EPACNT 2 This flag must be cleared with an instruction E4STL bit 4 EP4 stall flag 1 USB interface returns a STALL handshake for IN and OUT transactions E4ACK bit 3 EP4 1 this bit is set to 1 the USB interface transmits a data packet for an IN transaction and an handshake for an OUT transaction 2 Ifthis bit is set to 0 the USB interface return
69. address from the master if there is an unexpected restart just after slave s transmission when SIIREC is not set by instruction When a stop condition is detected an interrupt is generated and processing returns to 2 in step 7 3 73 8 Terminating communication Set SILREC Return to in step 6 to cause communication to automatically terminate To force communication to termination clear SITRUN and SIIEND release the clock port e An interrupt occurs when a stop condition is detected Then clear and SILOVR and return to 2 in step 4 3 12 5 Related Registers 3 12 51 5101 control register 5 1 1 5101 control register is an 8 bit register that controls the operation and interrupts of 5101 Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE34 0000 0000 R W SCONI SIIMO SIIRUN SIIREC SIIDIR 5 SEND SIE 1 bit 7 5101 mode control SI1MO bit 6 SIO1 mode control Table 3 12 2 gt SIO1 Operation Modes Mode SH M1 SHMO Operating Mode Synchronous 8 bit SIO UART 1 stop bit no parity SIT RUN bit 5 5101 operation 1 A 1 in this bit indicates that SIO1 is running 2 See Table 3 12 1 for the conditions for setting and clearing this bit SI REC bit 4 5101 receive send control 1 Setting this bit to 1 places SIOI into the receive mode 2 Setting this bit to O places SIOI into the send mode
70. as it is not cleared automatically INT2IE bit 0 INT2 interrupt request enable When this bit and INT2IF are set to 1 HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 5 3 4 Input signal select register ISL 1 This register is an 8 bit register for controlling the timer input noise filter time constant buzzer output and base timer clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESF 0000 0000 R W ISL STOHCP STOLCP BTIMCI BTIMCO BUZON NFSEL NFON STOIN STOHCP bit 7 Timer capture signal input port select This bit selects the timer OH capture signal input port When set to 1 a timer OH capture signal is generated when an input that satisfies the INT1 interrupt detection conditions is supplied to P71 If the INT1 interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P71 When this bit is set to 0 a timer OH capture signal is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P73 STOLCP bit 6 Timer OL capture signal input port select This bit selects the timer OL capture signal input port When set to 1 a timer OL capture signal is generated when an input that satisfies the INTO interrupt detection conditions is supplied to P70 If the INTO interrupt detection mode is set to level detec
71. automatically transferred from the data shift register SBUFO to RAM 3 Interrupt generation An interrupt request is generated at the end of transmission when the interrupt request enable bit is set 4 control serial interface 0 5100 it is necessary to manipulate the following special function registers SCONO SBUFO SBRO SCTRO SWCONO PI PIDDR PIFCR 0000 0000 R W SCONO SIOBNK SIOWRT SIORUN SIOCTR SIODIR SIOOVR SIOEND SIOIE SBUFO2 SBUFOI SBRGO2 SBRGOI SCTRO2 SCTROI SOXBYT2 soXBYTI 3 56 3 11 3 3 11 3 1 1 3 11 3 2 1 3 11 3 3 1 2 3 11 3 4 1 3 11 3 5 1 2 LC871A00 Chapter 3 Circuit Configuration 100 control register SCONO 8 bit register The SIOO control register controls the operation and interrupts of SIOO 100 data shift register SBUFO 8 bit register The SIOO data shift register is an 8 bit shift register that performs data input and output operations at the same time 100 baudrate generator register SBRO 8 bit reload counter This is an 8 bit register that defines the baudrate for SIOO serial transmission It can generate clocks at intervals of n 1 x n 1 to 255 Note n 0 is inhibited Continuous data bit register SCTRO 8 bit register The continuous data bit register controls the bit length of data to be transmitted or received in the continuous data transmission reception mode Continuous data transfer contro
72. bit is also cleared when the receive operation is stopped RM2RUN set to 0 3 153 REMOREC2 RM2BCT2 bit 2 RM2BCT1 bit 1 Receive data counter RM2BCTO bit 0 The REMOREC2 allows the number of last less than 8 bits data block to be read at the end of a receive operation From this value the user can identify the number of valid received data bits that are left in the RM2SFT Note value that is set in RM2GPRI and RM2GPRO will exert no influence on the receive operation when RM2FMT 2 through RM2FMTO are set to give a value of 2 or 3 3 19 4 6 Remote control receive guide pulse width setup register RM2GPW 1 remote control receive guide pulse width setup register is 8 bit register that defines the width of the guide pulse FE2C 0000 0000 RM2GPW 2 2 2 RM2GPHI 2 RM2GPL3 RM2GPL2 RM2GPL1 RM2GPLO Note The values of this register exerts no influence on the receive operation when RM2FMT2 through RM2FMTO are set to give a value of 2 or 3 3 19 4 7 Remote control receive data 0 pulse width setup register RM2DTOW 1 remote control receive data 0 pulse width setup register is an 8 bit register that defines the width of the data 0 pulse or timings 1 and 2 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE2D 0000 0000 RM2DTOW RM2D0H3 RM2D0H2 RM2DOHI RM2DOHO RM2D0L3 RM2DOL2 RM2D0L1 RM2DOLO
73. bits 4 and 5 is used as the system clock EXTOSC bit 6 XT1 XT2 function control 1 When this bit is set to 1 the and XT 2 pins serve as the pins for subclock oscillation and get ready for oscillation when a crystal oscillator 32 768 kHz standard capacitors feedback resistors and damping resistors are connected When the OCR register is read in this case bit 3 reads the data at the XT2 pin and bit 2 reads 0 2 When this bit is set to 0 the and XT2 pins serve as input pins When the OCR register is read in this case bit 3 reads the data at the X T2 pin and bit 2 reads the data at the pin CLKCB5 bit 5 System clock select CLKCBA bit 4 System clock select 1 CLKCBS and CLKCBA are used to select the system clock 2 5 and CLKCBA are cleared at reset time or when the HOLD mode is entered CLKCB5 CLKCB4 System Clock Internal RC oscillator 0 0 eur Peet ode 0 _______ XT2IN bit 3 2 data read only 4 9 System Clock XT1IN bit 2 XT1 data read only Data that can be read via varies as summarized below according to the value of EXTOSC 1 1 2 3 bit 6 EXTOSC XT2IN XT1IN XT2 pin data 0 2 pin data RCSTOP bit 1 Internal RC oscillator control Setting this bit to 1 stops the oscillation of the built in RC oscillation circuit XTI pin data Setting this bit to 0 starts the oscillat
74. data at pin P13 When is placed in the output mode PI3DDR 1 and P13FCR is set to 1 the OR of the 5101 output data and the port data latch is placed at pin P13 P12FCR bit 2 P12 function control SIOO clock output control This bit controls the output data at pin P12 When P12 is placed in the output mode P12DDR 1 and P12FCR is set to 1 the OR of the 5100 clock output data and the port data latch is placed at pin P12 P11FCR bit 1 P11 function control SIOO data output control This bit controls the output data at pin P11 When P11 is placed in the output mode PI 1IDDR 1 and P11FCR is set to 1 the OR of the SIOO output data and the port data latch is placed at pin P11 When the SIOO is active SIOO input data is read from P11 regardless of the I O state of P11 P10FCR bit 0 P10 function control SIOO data output control This bit controls the output data at pin P10 When P10 is placed in the output mode PIODDR 1 and PIOFCR is set to 1 the OR of the SIOO output data and the port data latch is placed at pin P10 3 8 LC871A00 Chapter 3 3 2 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 2 5 HALT and HOLD Mode Operation When in the HALT or HOLD mode port 1 retains the state that is established when the HALT or HOLD mode is entered 3 9 3 3 Port 2 3 3 1
75. element and capacitance across and CF2 pins An external circuit see the data sheet must be connected to the UFILT P34 pin The 48 MHz clock for the USB is generated by the internal multiplier circuit using the main clock as the reference A 4 to 16 MHz clock which is derived by frequency dividing the 48 MHz USB clock can be supplied as the system clock However it is necessary to configure the frequency of this clock to 8 16 MHz to drive the USB function control circuit Power control register PCON 3 bit register The power control register specifies the operating mode Normal HALT HOLD X tal HOLD Oscillation control register OCR 8 bit register The oscillation control register controls the start stop operation of the oscillation circuits This register selects the system clock The register sets the division ratio of the oscillation clock to be used as the system clock to i Or 1 The state of the XT2 pins be read as bits 2 and 3 of this register XT2 general purpose port output control register XT2PC 8 bit register The XT2 general purpose port output control register controls the general purpose output N channel open drain type at the XT2 pin USB dedicated PLL oscillation circuit control register PLLCNT 8 bit register The USB dedicated PLL oscillation circuit control register controls the start stop operation of the PLL oscillation circuit The register defines the frequency
76. flag must be cleared with an instruction BRSEN bit 6 Bus reset interrupt request enable flag 1 interrupt request to vector address 0033H is generated when this bit and BRSFG are set to 1 BACFG bit 5 Bus active detect flag 1 This flag is set when a USB bus active state bus state other than bus idle 15 detected 2 This flag must be cleared with an instruction 3 126 LC871A00 Chapter 3 BACEN bit 4 Bus active interrupt request enable flag 1 interrupt request to vector address 0013H is generated when this bit and BACFG are set to 1 SOFFG bit 3 SOF detect flag 1 This flag is set when an SOF is detected 2 This flag must be cleared with an instruction SOFEN bit 2 SOF interrupt request enable flag 1 interrupt request to vector address 003BH is generated when this bit and SOFFG are set to 1 USBINT1 bit 1 Reserved Must always be set to 0 ENPEN bit 0 Endpoint interrupt request enable flag 1 interrupt request to vector address 003BH is generated when this bit is set to 1 and either one of interrupt sources EPOINT EP2INT EP3INT and EP4INT is established 3 18 4 6 interrupt control register EPOINT 1 EPO interrupt control register controls endpoint 0 interrupts Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT2 BIT1 BITO FE83 0000 0000 R W EPOINT AKOFG AKOEN NKOFG NKOEN EROFG EROEN STOFG STOEN AKOFG bit 7 End of
77. flag set T1HR flag set lt 8 bit programmable timer 8 bit programmable timer Fig 3 8 1 Mode 0 T1LONG 0 T1PWM 0 Block Diagram 1 gt T1L prescaler Clock 1Tcyc gt T1H prescaler Overflow Reset Overflow T1PWML output Set Reset T1PWMH output Set Match buffer register Match buffer register lt heload gt 2 Reload T1LCMP tage Pr lt 8 bit PWM gt 8 bit PWM Fig 3 8 2 Mode 1 T1LONG 0 T1PWM 1 Block Diagram 3 4 Clock Clock 2Tcyc gt 1 prescaler or external events Set in 145CR FE4Ah 145SL FE4Bh registers gt T1H prescaler Invert T1PWMH output Invert T1PWML output Match buffer Match buffer register 2 Reload 2 Reload T1LCMP T1HCMP TILR flag set lt 6 6 programmable timericounter gt Fig 3 8 3 Mode 2 T1LONG 1 T1PWM 0 Block Diagram register T1H prescaler T1H Match Invert output Match buffer Match buffer register register Reload Reload 5 1 T1HCMP T1HR flag set 4 16 bit programmable timer gt Fig 3 8 4 Mode 3 T1LONG 1 T1PWM 1 Block Diagram Clear 3 42 LC871A00 Chapter 3 3 8 4 Related Registers 3 8 4 1 Timer 1 control register T1CNT 1 Timer 1 control register is 8 bit register that controls the operation and interrupts of TIL and
78. functional areas as explained in Section 2 1 namely 1 system reserved area FF00 to FFFF 2 SFR area FEOO to FEFF and 3 RAM stack area 0000 to FDFF Consequently it is disallowed to point to a different area using the value of the C register from the basic area designated by the contents of Rn For example if the instruction LD R5 C is executed when 5 contains OFDFFH and the register contains 1 since the basic area is 3 RAM stack area 0000 to FDFF the intended address OFDFFH 1 lies outside the basic area and OFFH as the result of LD is consequently placed in the ACC If the instruction LD R5 C is executed when 5 contains OFEFFH and the register contains 2 since the basic area is 2 SFR area to FEFF the intended address OFEFFH 2 OFF01H lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the 8 bit address space is ignored and the contents of OFEO1H B register are placed in the ACC as the result of the computation OFF01 H amp OFFH 0FE00H 2 7 2 11 4 Indirect Register RO Offset Value indirect Addressing off In this addressing mode the results of adding the 7 bit signed offset data off 64 to 63 to the contents of the indirect register RO designate an address in RAM or SFR If RO contains FEO02H and off has value of 7EH 2 for example the A register FE
79. input pins when TOLONG timer 0 control register bit 5 is set to 1 Capture data Contents of timer counter 0 low byte TOL Timer counter 0 capture register high byte TOCAH 8 bit register Captureclock External input detection signals from the P71 INTI TOHCP and P73 INT3 TOIN and P20 to P27 timer 0H capture input pins Capture data Contents of timer counter 0 high byte Table 3 6 1 Timer 0 TOH TOL Count Clocks Mode TOLONG TOLEXT Count Clock TOL Count Clock TOH TOL Count Clock 0 0 0 TOPRR match signal TOPRR match signal E ea TOPRR match signal External signal NEL CENE oL memasga 3 26 LC871A00 Chapter 3 Clock Clear gt Prescaler Capture trigger Registers 101 CR FE5Dh I23C R FESEh ISL FESFh I45CR FEA4Ah I45SL FEABh and I67CR FE4Eh need setting TOCAH TOCA1H Capture TOLCMP Match buffer TOHCMP flag set register flag set Match Comparator Match buffer register H TOLR 8 bit programmable timer with 8 bit programmable timer with programmable prescaler programmable prescaler Figure 3 6 1 Mode 0 Block Diagram TOLONG 0 TOLEXT 0 Clock Clear Capture trigger Toyc Registers 101 OCI gt I23CR FEBEh ISL FE5Fh Match I45CR FE4Ah and f I45SL FEA4Bh need setting TOPRR External Capture Capture Clock
80. into the RM2SFT The data from the RM2SFT is transferred to the RM2RDT every time the REMOREC2 receives 8 bits of data At this moment the REMOREC2 sets the RM2SFUL flag and resets the RM2SFT 6 If the data is identified as error the REMOREC2 sets the RM2DERR flag and returns into the idle state waiting for a guide pulse 7 At timing 3 in step 3 or 8 the REMOREC2 samples the remote control signal If the REMOREC2 detects an edge after starting the detection of an edge at this timing and before timing 4 it resets the RM2MJCT and returns to operation in step 3 3 160 8 9 10 11 12 13 14 15 LC871A00 Chapter 3 When the REMOREC2 detects the end of reception condition it sets the RM2REND RM2HOLD flags and suspends operation Subsequently when the RM2SFT is read the clears the RM2HOLD flag and enters the idle state waiting for a guide pulse resuming the receive operation After three cycles of steps 3 through 7 the REMOREC2 samples the remote control signal at timing 1 in step 4 At timing 2 in step 4 the REMOREC2 tests the data that is sampled in step 7 or 9 If the data is identified as 0 or 1 the REMOREC2 performs the step similar to step 5 It also resets the RM2MJCT and divides the frequency of RM2CK by 2 If the data is identified as error the REMOREC2 performs the step similar to step 6 At timing in step 5 REMOREC2 samples the remote cont
81. low power operation using the HOLD mode it is necessary not to use the watchdog timer at all or to disable the watchdog timer from running in the HOLD mode by setting WDTHLT to 1 sure to set WDTCLR to 0 when the watchdog timer is not to be used The P70 INTO TOLCP pin has two input levels The threshold level of the input pins of the watchdog timer circuit is higher than that of the port inputs and the interrupt detection level Refer to the latest SANYO Semiconductor Data Sheet for the input levels High threshold R P70 INTO gt Watchdog timer TOLCP Port 7 circuit interrupt MOV 55H WDT instruction Fig 4 5 2 Pin without an Optional Pull up Resistor 4 25 Watchdog Timer 3 external resistor to be connected to the watchdog timer can be omitted by setting bits 4 and 0 of the port7 control register P7 FESC to 1 0 and connecting a pull up resistor to the P70 INTO TOLCP pin see Figure 4 5 3 The resistance of the pull up resistor to be adopted in this case varies according to the power source voltage VDD Calculate the time constant of the watchdog timer while referring to the latest SANYO Semiconductor Data Sheet P70 INTO TOLCP me P70DDR FESC BIT4 P70DT 5 BITO Watchdog timer Roo Port 7 circuit interrupt MOV 55 WDT instruction P70DDR FESC BIT4 P70DT FESC BITO Fig 4 5 3 Sample Applic
82. of the clock TS4BAUD WAIT request lt gt SCK4 514 504 When S4CKPL 1 SCKA is held low when the clock is stopped the data state is changed on the rising edge of a clock and data is taken in on the falling edge of the clock TS4BAUD WAIT request SCK4 514 504 Notes In the continuous data transfer mode wait request occurs every 8 bit data transfer and the CPU performs 1 cycle of wait operation data transfer between RAM and shift register If a wait request has been issued by another module 5100 or USB the wait operation for the 5104 is made pending the wait operation for the SIO4 is carried out after the wait operation for the other module is finished see S104 Serial Input Output Characteristics in the data sheet The CPU suspends instruction execution for 1 instruction cycle while it is performing a wait operation For details on the wait operation see section 2 12 Wait Operation in the User s Manual Figure 3 13 2 Continuous data transfer timing chart 3 84 LC871A00 Chapter 3 3 13 5 6104 Transmission Examples 3 13 5 1 Synchronous serial interface Example 1 Sending continuous data on the internal clock 1 Setting up the transmission ports P24 P23 and P22 P2DDR P24DDR 0 P23DDR 0 P22DDR 0 P2 24 0 P2320 P2220 e S4ADDR S4PTSEL 0 2 Setting up the communication mode SI4CNO SBITON 0 MSBSEL 1 0 S4RAM 1 SI4WRT 0 SI4TE 1 IE 7 1 3 Settin
83. of the four systems of oscillators to be executed independently through microcontroller instructions 4 Shared I O pin function The crystal oscillator pins 1 and XT2 can be used as input ports Pin XT2 can also be used as an input output port 5 Oscillator circuit states and operating modes Mode clock Main Clock Subclock RC Oscillator USB dedicated System Clock PLL oscillator Reset Running Stopped Running Running RC oscillator Programmable Programmable Programmable Programmable Programmable HALT State established at State established at State established at State established at State established at entry time entry time entry time entry time time HOLD Stopped Stopped Stopped Stopped Stopped Immediately after Running State established at Running State established at RC oscillator resetting of HOLD entry time entry time mode X tal HOLD Stopped State established at Stopped Stopped Stopped entry time Immediately after State established at State established at State established at State established at State established at resetting of X tal entry time entry time entry time entry time entry time HOLD Note See Section 4 3 Standby Function for the procedures to enter and exit the microcontroller operating modes 4 5 System Clock Reset Main clock started Subclock stopped RC oscillator started USB dedicated PLL oscillator started HOLD mode
84. operation control 0 Maintains watchdog timer operating state 1 Starts watchdog timer operation WDTFLG bit 7 Runaway detection flag This bit is set when a program runaway condition is detected by the watchdog timer The application can identify the occurrence of a program runaway condition by monitoring this bit provided that WDTRST is set to 1 WDTRST bit 1 Runaway time reset control 0 Suppresses resetting on a runaway condition 1 Triggers a reset on a runway condition This bit is not reset automatically It must be reset with an instruction 4 22 LC871A00 WDTB5 bit 5 General purpose flag This bit can be used as a general purpose flag Manipulating this bit exerts no influence on the operation of the functional block WDTHLT bit 4 HALT HOLD mode function control This bit enables 0 or disables 1 the watchdog timer when the microcontroller is in the HALT or HOLD state When this bit is set to 1 WDTCLR WDTRST and WDTRUN are reset and the watchdog timer is stopped in the HALT or HOLD state When this bit is set to 0 WDTCLR WDTRST and WDTRUN remain unchanged and the watchdog timer continues operation even when the microcontroller enters the HALT or HOLD state Using watchdog timer when 1 and released from HALT HOLD to normal operation mode initialize set its condition again and start the watchdog timer WDTCLR bit 2 Watchdog timer clear control When watchdog timer is running WDTRUN 1
85. period 14 wave period 15 Fundamental Fundamental Fundamental period 0 signal PWMH PWML 010 PWMH 011 PWML 012 PWMH PWML 013 PWMH PWML 014 PWMH PWML 015 PWMH PWML 016 PWMH PWML 017 PWMH PWML 018 PWMH PWML 019 PWMH PWML 01A PWMH PWML 01B PWMH PWML 01C PWMH PWML 01D PWMH PWML 01E PWMH PWML 01F 10 11 112 113 14 15 munninn a_i IL TLTUILTLILTUILTLIL TUL TUIL TUIL JI JI JI JI The fundamental wave period is variable within the range of Fundamental wave period Value represented by PWM4C7 to PWMACA 1 16 The overall period be changed by changing the fundamental wave period The overall period is made up of 16 fundamental wave periods 3 107 PWM Examples Wave comparison when the 12 bit PWM contains 237 H 12 bit register configuration gt PWMH PWML 237 H 1 Pulse added system LC871A00 series beg period gt PME D PWML 237 2 Ordinary system Since the ripple component of the integral output in this system is greater than that of the pulse added system as seen from the figure below the pulse added system is considered better for motor controlling uses lt Overall period l PWM
86. pin that is selected as an N channel open drain output user option is represented by an open circuit 3 7 P17FCR bit 7 P17 function control timer 1 PWMH amp base timer BUZ output control This bit controls the output data at pin P17 When P17 is placed in the output mode P17DDR 1 and P17FCR is set to 1 the AND of timer 1 PWMH output and BUS output from the base timer is EORed with the port data latch and the result is placed at pin 17 P16FCR bit 6 P16 function control timer 1 PWML output control This bit controls the output data at pin P16 When P16 is placed in the output mode P16DDR 1 and P16FCR is set to 1 the EOR of timer 1 PWML output data and the port data latch is placed at pin 16 P15FCR bit 5 P15 function control SIO1 clock output control This bit controls the output data at pin P15 When P15 is placed in the output mode PISDDR 1 and 15 is set to 1 OR of the 5101 clock output data and the port data latch is placed at pin 15 P14FCR bit 4 P14 function control SIO1 data output control This bit controls the output data at pin P14 When P14 is placed in the output mode PI4DDR 1 and 14 is set to 1 the OR of 5101 output data and the port data latch is placed at pin P14 When the 5101 is active 5101 input data is read from P14 regardless of the I O state of P14 P13FCR bit 3 P13 function control SIO1 data output control This bit controls the output
87. side Guide pulse criterion value low side RM2MJCT Count value Edge detected Edge detected Data 0 pulse Data 0 pulse End of Count start Count reset amp criterion value criterion value reception start low side high side Setting up the receive format A criterion values 1 Check the pulse width from rising edge to falling edge of the guide pulse RM2CK in guide pulse receive mode Period selected by RM2CK2 to RM2CKO Count value selected by RM2GPR1 RM2GPRO Guide pulse criterion value Value given by RM2GPLA to RM2GPL0 1 x RM2CK or greater to Value given by RM2GPH4 to 2 1 x Less than RM2CK Note The register values must be such that value given 2 to RM2GPLO0 lt value given by RM2GPH4 to RM2GPHO 2 3 Check the pulse width from falling edge to falling edge of data and 1 RM2CK in data pulse receive mode Period selected by RM2CK2 to RM2CKO x count value selected by RM2DPR1 RM2DPRO Data 0 criterion value Value given by RM2D0L4 to RM2DOLO 1 x RM2CK or greater to Value given by RM2D0H4 to RM2DOHO 1 x less than RM2CK Data 1 criterion value RM2D1L4 to RM2DILO 1 x RM2CK or greater to Value given by RM2D1H4 to RM2D1HO 1 x less than RM2CK Note The register values must be such that Value given by RM2DOL4 to RM2DOLO lt value given by RM2D0H4 to RM2D0H0 Svalue given by RM2D1L4 to RM2DILO lt value given by RM2D1H4 to RM2D1HO0
88. ssgois sect 88013 sRG12 5 3 65 o 3 12 3 3 12 3 1 1 3 12 3 2 1 2 3 12 3 3 1 2 3 12 3 4 1 2 Circuit Configuration 5101 control register SCON1 8 bit register The 5101 control register controls the operation and interrupts of 5101 5101 shift register SIOSF1 8 bit shift register This register is a shift register used to transfer and receive 5101 data This register cannot be accessed with an instruction It is accessed via SBUFI SIO1 data register SBUF1 9 bit register The lower order 8 bits of SBUF1 are transferred to SIOSFI at the beginning of data transfer At the end of data transfer the contents of SIOSFI are placed in the lower order 8 bits of SBUFI In modes 1 2 and 3 since the 9th input data is placed in bit 8 of SBUFI it is possible to check for a stop bit SIO1 baudrate generator register SBR1 8 bit reload counter This is a reload counter for generating internal clocks The generator can generate clocks of 2 to 512 Tcyc in modes 0 and 2 and clocks of 8 to 2048 Tcyc in mode 1 3 66 LC871A00 Chapter 3 Table 3 12 1 SIO1 Operations and Operating Modes Bus Master Mode 2 Bus Slave Mode 3 Transmit Receive Transmit Receive Transmit Receive Transmit Receive 0 SHREC 1 SI1REC 0 SHREC 1 0 SI1REC 1 0 SI1REC 1 None None Output Input See 1 and 2 Not required Not required Note 2 8 8 8
89. the clock output from the prescaler RM2CKPR which counts the 1 to 128 Tcyc or subclock oscillation source the RM2CK reference clock is selected out of 8 sources to identify the data as 0 1 or error The data that is found normal is stored in the remote control receive shift register RM2SFT Every time 8 bits of data are stored in the register the 8 bits are transferred to the remote control receive data register RM2RDT At this moment the data transfer flag is set The end of reception flag 15 set when the end of receive format condition is detected 2 Interrupt generation An interrupt request to vector address 0013H is generated when an interrupt request occurs in the remote control receiver circuit provided that the interrupt request enable bit is set The remote control receiver circuit can generate the following four types of interrupt requests 3 145 REMOREC2 1 Guide pulse detection 2 Receive data test error 3 RM2SFT to RM2RDT data transfer 4 End of reception 3 X tal HOLD mode operation and X tal HOLD mode release function The remote control receiver circuit is enabled for operation by setting bits 2 and 1 of the power control register PCON after the circuit is started for receive operation with RM2CK being selected as the subclock oscillation source The X tal HOLD mode can also be released by making use of the interrupt from the remote control receiver circuit This function makes it possible to realize l
90. the same time in the 16 bit mode 3 6 4 2 Timer 0 programmable prescaler match register TOPRR 1 Timer 0 programmable prescaler match register is an 8 bit register that is used to define the clock period Tpr of timer counter 0 2 The count value of the prescaler starts at 0 when TOPRR is loaded with data 3 1 x Tcyc Period of cycle clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 0000 0000 R W TOPRR TOPRR7 TOPRR6 TOPRR5 TOPRR4 TOPRR3 TOPRR2 TOPRRI TOPRRO 3 6 43 Timer counter 0 low byte TOL 1 This is a read only 8 bite timer counter It counts the number of match signals from the prescaler or external signals Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE12 0000 0000 R TOL TOL7 TOL6 TOLS TOL4 TOL3 TOL2 TOLO 3 644 0 high byte 1 This is a read only 8 bite timer counter It counts the number of match signals from the prescaler or overflows occurring TOL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE13 0000 0000 R TOH TOH7 TOH6 TOHS TOH4 TOH3 TOH2 TOHI TOHO 3 6 4 5 Timer counter 0 match data register low byte 1 This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the lower order byte of time
91. this bit enables 1 or disables 0 the discharge of capacitance from the external capacitor Setting the bit to 1 and executing instruction of clearing the watchdog timer drives the pin P70 INTO TOLCP N channel transistors discharging the external capacitors and clearing the watchdog timer The pulse stretcher also functions during this process Setting the bit to 0 disables operation of the N channel transistors and the clearing of the watchdog timer Also during watchdog timer is not in operation WDTRUN 0 and when setting to 1 P70 INTO TOLCP pin s N channel transistor is turned on and discharges external capacitor then clears the watchdog timer WDTRST bit 1 Runaway time reset control This bit enables 1 or disables 0 the watchdog timer from triggering a reset when it detects a program hangup When this bit set to 1 a reset is generated and execution restarts at program address 0000H when a program hangup is detected When the bit is set to no reset occurs when a program hangup is detected Instead an external interrupt INTO is generated and a call is made to vector address 0003H WDTRUN bit 0 Watchdog timer operation control This bit starts 1 or maintains the state of 0 the watchdog timer A 1 in this bit starts the watchdog timer function and a 0 exerts no influence on the operation of the watchdog timer This means that once the watchdog timer is started a program will not be able to stop the watchdog time
92. this bit is set to 1 the count clock for TOL is an external input signal TOHCMP bit 3 TOH match flag This bit is set when the value of TOH matches the value of the match buffer register for TOH while is running TOHRUN 1 and a match signal is generated Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match needs to occur in all 16 bits of data for a match signal to occur TOHIE bit 2 TOH interrupt request enable control When this bit and TOHCMP are set to 1 an interrupt request to vector address 0023H is generated 3 29 4 IO TOLCMP bit 1 TOL match flag This bit is set when the value of TOL matches the value of the match buffer register for TOL while TOL is running TOLRUN 1 and a match signal is generated Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match needs to occur in all 16 bits of data for a match signal to bit 0 TOL interrupt request enable control When this bit and TOLCMP are set to 1 an interrupt request to vector address 0013H is generated Notes TOHCMP TOLCMP must be cleared to 0 with an instruction When the 16 bit mode is to be used TOLRUN and must be set to the same value to control operation TOLCMP and TOHCMP are set at
93. this purpose In this case only Rn are configured as 17 bit registers 128K byte space For models with having bank in ROM it is possible to reference the ROM data in the ROM bank 128K bytes identified by the LDCBNK flag bit 3 in the PSW Consequently when looking into the ROM table on a series model with banked ROM execute the LDCW instruction after switching the bank using the instruction such as SET1 or CLRI so that the LDCBNK flag designates the ROM bank where the ROM table resides Examples TBL DB 34H DB 12H DW 5678H LDW TBL Loads the BA register pair with the TBL address CHGP3 TBL gt gt 17 amp 1 Loads LDCBNK in PSW with bit 17 of the TBL address Note 1 TBL gt gt 16 amp 1 Loads 1 in PSW with bit 16 of TBL address STW RO Load indirect register RO with the TBL address bits 16 to 0 LDCW 1 Reads out the ROM table B 78H ACC 12H MOV 1 C Loads the C register with 01H LDCW Reads out the ROM table B 78H 12 INC C Increments the C register by 1 LDCW _ Reads out the ROM table B 56H ACC 78H Note 1 LDCBNK bit 3 of PSW needs to be set up only for models with having bank in ROM 2 11 7 External Data Memory Addressing The LC870000 series microcontrollers can access external data memory spaces of up to 16M bytes 24 bits using the LDX and STX instructions To designate a 24 bit space specify the contents of the B register 8 bits as the highe
94. trigger a reset The RES pin can serve as a power on reset pin when it is provided with an external time constant element Runaway detection reset function using a watchdog timer The watchdog timer of this series of microcontrollers can be used to detect and reset runaway conditions by connecting a resistor and a capacitor to its external interrupt pin P70 INTO TOLCP and making an appropriate time constant element A sample of resetting circuit is shown in Figure 4 4 1 Exterior of Interior of microcontroller microcontroller Watchdog timer P70 INTO Internal reset signal Synchronization circuit Fig 4 4 1 Reset Circuit Block Diagram 4 19 Reset 4 4 3 Reset State When a reset is generated by the RES pin or watchdog timer the hardware functional blocks of the microcontroller are initialized by a reset signal that is in synchronization with the system clock Since the system clock is switched to the built in RC oscillator when a reset occurs hardware initialization is also carried out immediately even at power on time The system clock must be switched to the main clock when the main clock gets stabilized The program counter is initialized to 0000 on a reset See Appendix 87 Register Map for the initial values for the special function registers SFR lt Notes and precautions gt The stack pointer is initialized to 0000H Data is never initialized by a reset Consequently the content
95. up of two registers SPL at address and SPH at address FEOB It is initialized to 0000H on a reset The SP is incremented by 1 before data is saved in stack memory and decremented by 1 after the data is restored from stack memory FEOA 0000 0000 R W SPL SP7 SP6 5 5 SP4 SP3 SP2 SPI SPO The value of the SP changes as follows 1 When the PUSH instruction is executed SP SP 1 RAM SP DATA 2 When the CALL instruction is executed SP SP 1 RAM SP ROMBANK ADL SP SP 1 RAM SP ADH 3 When the POP instruction is executed DATA RAM SP SP SP 1 4 When the RET instruction is executed ADH RAM SP 5 SP 1 ROM BANK ADL RAM SP SP SP 2 10 Indirect Addressing Registers The LC870000 series microcontrollers are provided with three addressing schemes Rn Rn C off that use the contents of indirect registers indirect addressing modes See Section 2 11 for the addressing modes Used for these addressing modes are 64 2 byte indirect registers RO to R63 allocated to RAM addresses 0 to 7EH The indirect registers can also be used as general purpose registers e g for saving 2 byte data Naturally these addresses can be used as ordinary RAM on a byte 9 bits basis if they are not used as indirect registers RO to R63 are system reserved words to the assembler and need not be defined by the user 2 5 Reserved for system Address R63 upper R63 7EH
96. 00 to OV bit 2 Overflow flag OV is set to 1 when an overflow occurs as the result of an arithmetic operation and cleared to 0 otherwise An overflow occurs in the following cases 1 When MSB is used as the sign bit and when the result of negative number negative number or negative number positive number is a positive number 2 When MSB is used as the sign bit and when the result of positive number positive number or positive number negative number is a negative number LC871A00 Chapter 2 3 When the higher order 8 bits of a 16 bits x 8 bits multiplication is nonzero 4 When the higher order 16 bits of a 24 bits 16 bits multiplication is nonzero 5 When the divisor of a division is 0 There are some instructions that do not affect this flag at all P1 bit 1 RAM bit 8 data flag is used to manipulate bit 8 of 9 bit internal data RAM 0000H to FDFFH Its behavior varies depending on the instruction executed See Table 2 12 1 for details PARITY bit 0 Parity flag This bit shows the parity of the accumulator A register The parity flag is set to 1 when there are an odd number of 1s in the A register It is cleared to 0 when there are an even number of 1s in the A register 2 9 Stack Pointer SP The LC870000 microcontrollers can use RAM addresses 0000H to FDFFH as a stack area The size of RAM however varies depending on the model of the microcontroller The SP is 16 bits long and made
97. 000 R W IE XFLG HFLG LFLG 5 5 XCNT1 XCNTO 4 1 3 Circuit Configuration 4 1 3 1 Master interrupt enable control register IE 6 bit register 1 The master interrupt enable control registers enables and disables H and L level interrupts 2 The interrupt level flag of the register can be read 3 Theregister selects the level L or X of interrupts to vector addresses 00003H and 0000BH 4 1 3 2 Interrupt priority control register IP 8 bit register 1 The interrupt priority control register selects the level or L of interrupts to vector addresses 00013H to 0004BH 4 2 LC871A00 4 1 4 Related Registers 4 1 4 1 Master interrupt enable control register IE 6 bit register 1 The master interrupt enable control register is a 6 bit register for controlling the interrupts Bits 6 to 4 of this register are read only Address Initial value R W Name BIT7 BIT6 BITS BIT4 2 BIT1 BITO FE08 0000 HH00 R W IE IE7 XFLG HFLG LFLG XCNTI XCNTO bit 7 H L level interrupt enable disable control Alin this bit enables H and L level interrupt requests to be accepted this bit disables H and L level interrupt request to be accepted e X level interrupt requests are always enabled regardless of the state of this bit XFLG bit 6 X level interrupt flag R O This bit is set when an X level interrupt 15 accepted and reset when execution returns from the processi
98. 000 R W IP IP4B IP43 IP3B IP33 IP2B 23 IP13 Interrupt IP Bit Interrupt Level Vector Address Value 0004BH IP4B i 0003BH IP3B 00033 IP33 E 0002BH 00023H 1 23 0001 00013 LC871A00 4 2 System Clock Generator Function 4 2 1 Overview This series of microcontrollers incorporates four systems of oscillation circuits i e the main clock oscillator subclock oscillator RC oscillator and USB dedicated PLL oscillator as system clock generator circuits The RC oscillation circuit has built in resistors and capacitors so that no external circuit is required The system clock can be selected from these four types of clock sources under program control 4 2 2 Functions 1 System clock select Allows the system clock to be selected under program control from four types of clocks generated by the main clock oscillator subclock oscillator RC oscillator and USB dedicated PLL oscillator 2 System clock frequency division Divides the frequency of the oscillator clock selected as the system clock and supplies the resultant clock to the system as the system clock The frequency divider circuit is made up of two stages The first stage allows the selection of division ratios of i and i The second stage allows the selection of division ratios of X NUN and aS 64 128 3 Oscillator circuit control Allows the start stop control
99. 0000 R W SBUFI SBUFIS8 SBUF17 SBUF16 SBUFI5 SBUF14 SBUFI3 SBUF12 SBUF11 SBUFIO 3 12 5 3 Baudrate generator register SBR1 1 baudrate generator register is an 8 bit register that defines the baudrate of SIO1 2 Loading this register with data causes the baudrate generating counter to be initialized immediately 3 baudrate varies from mode to mode the baudrate generator is disabled in mode 3 Modes 0 2 TSBRI SBRI value 1 x 2Tcyc Value range 2 to 512 Tcyc Mode 1 TSBRI z SBRI value 1 x 8Tcyc Value range 8 to 2048Tcyc Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE36 0000 0000 R W SBRI SBRGI7 SBRGI6 SBRGI5 SBRG14 SBRG13 SBRG12 SBRG11 SBRG10 3 75 3 13 Serial Interface 4 104 3 13 1 Overview The serial interface SIO4 incorporated in this series of microcontrollers is a synchronous serial interface providing the following functions 1 Continuous synchronous data transfer Data transfer of arbitrary number of bytes between 1 and 2 048 bytes Clock period master operation 4 3 to 1 020 3 Tcyc 2 16 bit CRC code calculation 3 13 2 Functions 1 Synchronous continuous data transmission reception Performs 2 or 3 wire synchronous serial communication The clock may be an internal clock master operation or external clock slave operation The clock period of the internal clock master operation is 4
100. 1 3 18 4 7 EP1 interrupt control register EP1INT 1 The EPI interrupt control register controls endpoint 1 interrupts Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT2 BIT1 BITO FE84 0000 0000 AKIFG AKIEN NKIFG NKIEN ERIFG ERIEN STIFG STIEN AK1FG bit 7 EP1 ACK end flag 1 Set to 1 when the endpoint 1 transaction terminates normally with an ACK See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction AK1EN bit 6 EP1 ACK interrupt request enable flag 1 interrupt to vector address 003BH is generated when this bit AK1FG and ENPEN are all set to 1 NK1FG bit 5 EP1 end flag 1 Set to 1 when the endpoint 1 transaction terminates with a See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction NK1EN bit 4 EP1 NAK interrupt request enable flag 1 An interrupt to vector address 003BH is generated when this bit NK1FG and ENPEN are all set to 1 ER1FG bit 3 error end 1 Set to 1 when the endpoint 1 transaction terminates with an error See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction ER1EN bit 2 EP1 error interrupt request enable flag 1 An interrupt to vector address 003BH is generated when this bit ERIFG and ENPEN are all set tol ST1FG bit 1 EP1 stall end flag 1 Se
101. 12 bit AD conversion mode Set the ADMD3 bit of the AD mode register ADMRC to 0 2 Setting up the conversion time To set the conversion time to 1 32 set bit 0 ADTM2 of the AD conversion results register low byte to 1 bit 1 ADTMI of the AD mode register to 0 and bit 0 ADTMO of the AD mode register to 1 3 Setting up the input channel When using AD channel input ANS set AD control register ADCRC bit 7 ADCHSEL3 to 0 bit 6 ADCHSEL2 to 1 bit 5 ADCHSEL1 to 0 and bit 4 ADCHSELO to 1 4 Starting AD conversion Set bit 2 ADSTART of the AD mode register ADCRC to 1 The conversion time will be twice the normal conversion time immediately after a system reset and for the first AD conversion that is carried out after the AD conversion mode is switched from 8 bit to 12 bit conversion mode In the second and subsequent AD conversions the normal conversion time is taken 5 Testing the end of AD conversion flag Monitor bit 1 ADENDF of the AD mode register ADCRC until it is set to 1 After verifying that bit 1 ADENDF is set to 1 clear it to zero 6 Reading the AD conversion results Read the contents of the AD conversion results registers high byte ADRHC and low byte ADRLC The read conversion data contains some errors quantization error combination error Be sure to use only valid conversion results while referring to the latest Semiconductor News bulletin Pass the read data to the application software
102. 2 to 512 Tcyc transfer clocks Mode 3 Bus mode 2 start detect 8 data bits stop detect e SIO4 Synchronous serial interface 1 LSB first MSB first modes selectable 2 Transfer clock cycle 4 to M Tcyc 3 Automatic continuous data communication 1 to 2 048 bytes selectable on a byte basis suspension and resumption of transfer controllable on a byte or word basis 4 Auto start on falling edge feature 5 Clock polarity selectable 6 Built in CRC16 computation circuit 1 2 LC871A00 Chapter 1 Full duplex UART e UART1 1 Data length 7 8 9 bits 2 Stop bits 1 bit 2 bits in continuous transmission mode 3 Baudrate D Tcyc AD converter 12 bit x 12 channels 12 8 bit resolution selectable Reference voltage automatic generation control PWM Multifrequency 12 bit PWM x 2 channels Infrared remote control receiver circuit 1 Noise rejection function Noise filter time constant Approx 120 s when 32 768kHz crystal oscillator is selected as the clock source 2 Supports data encoding formats such as PPM Pulse Position Modulation and Manchester encoding 3 X tal HOLD mode release function USB interface with function control functions Conforms to USB specification version 2 0 full speed Supports a maximum 4 user defined endpoints Endpoint EPO EP2 EP3 EPA B Control x 5 x 5 Bulk Interrupt
103. 256 x TIHPRC count x Tcyc TIPWMH low period T1HR 1 x TIHPRC count x Tcyc Mode2 16 bit programmable timer counter with an 8 bit prescaler with toggle output the lower order 8 bits may be used as a timer counter with toggle output A 16 bit programmable timer counter runs that counts the number of signals whose frequency is equal to that of the cycle clock divided by 2 or the number of external events Since interrupts can occur from the lower order 8 bit timer T1L at the interval of TIL period the lower order 8 bits of this 16 bit programmable timer counter can be used as the reference timer TIPWML and TIPWMH generate a signal that toggles at the interval of TIL and TI periods respectively Note 1 3 36 LC871A00 Chapter 3 TIL period TILR 1 x TILPRC count x 2 or TILR 1 x TILPRC count events detected TIPWML period period x 2 T1 period 1 1 x TIHPRC count x TIL period TIPWMH period T1 period x 2 4 Mode3 16 bit programmable timer with an 8 bit prescaler with toggle output the lower order 8 bits may be used as a PWM A 16 bit programmable timer runs on the cycle clock The lower order 8 bits run as PWM TIPWML having a period of 256 TIPWMH generates a signal that toggles at the interval of T1 period Note 1 TIPWML period 256 x TILPRC count x Tcyc TIPWML low period TILR 1 x TILPRC count x Tcyc T1 period 1 1 x TILPRC count x TIPW
104. 3 is read into bits 0 to 3 Bits 4 to 7 are loaded with bits 4 to 7 of register P7 If P7 FESC is manipulated with an instruction NOTI CLRI SET1 DBZ DBNZ INC or DEC the contents of the register are referenced as bits 0 to 3 instead of the data at port pins 3 Port 7 data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESC 0000 0000 R W P7 P73DDR P72DDR P71DDR P7ODDR P73DT P72DT P7IDT P70DT LC871A00 Chapter 3 Register Data Port P7n State Built in Pull up Resistor P7nDDR Input P Enabled OFF 0 0 P73DDR bit 7 P73 I O control A 1 or 0 in this bit controls the output CMOS or input of pin P73 P72DDR bit 6 P72 control A 1 or 0 in this bit controls the output CMOS or input of pin P72 P71DDR bit 5 P71 control A 1 or 0 in this bit controls the output CMOS or input of pin P71 P70DDR bit 4 P70 control A 1 or 0 in this bit controls the output N channel open drain or input of pin P70 P73DT bit 3 P73 data The value of this bit is output from pin P73 when P73DDR is set to 1 A 1 or 0 in this bit turns on and off the built in pull up resistor for pin P73 P72DT bit 2 P72 data The value of this bit is output from pin P72 when P72DDR is set to 1 A 1 or 0 in this bit turns on and off the built in pull up resistor for pin P72 P71DT bit 1 P71 data The value of this bit is outp
105. 4 Detect an end of reception condition from falling edge to overflow of data 1 criterion value End of reception detection Value given by RM2D1H4 to RM2D1HO 1 x RM2CK or greater Note The minimum criterion value is RM2CK x 8 The interval between the low and high values of guide and data pulses must be set up at intervals of RM2CK 8 or greater 3 156 LC871A00 Chapter 3 Receive format A receive operation 1 The REMOREC2 remains idle in the wait state until it receives a guide pulse normally When the guide pulse falls within the valid criterion value range the REMOREC2 resets the RM2MJCT and set the RM2GPOK flag then starts checking for the next data pulse At this time RM2SFT and RM2BCT are reset 2 When the data pulse falls within the valid criterion value range the REMOREC2 resets the RM2MJCT and loads the data 0 1 into the RM2SFT The data from the RM2SFT is transferred to the RM2RDT every time the REMOREC2 receives 8 bits of data At this moment the REMOREC2 sets the RM2SFUL flag and resets the RM2SFT 3 If the data pulse goes out of the valid criterion value range the REMOREC2 sets the RM2DERR flag and returns into the idle state waiting for a guide pulse 4 The number of received data bits is counted by the RM2BCT When receiving the number of data bits that is not an integral multiple of 8 the REMOREC2 references this value at the end of reception to determine the number of valid data bits in the RM2SFT
106. 4 Fixed bit This bit must always be set to 0 ADMD O bit 3 Fixed bit This bit must always be set to 0 ADMR2 bit 2 Fixed bit This bit must always be set to 0 ADTM1 bit 1 bit 0 These bits and bit 0 ADTMO2 of the AD conversion results register low byte define the conversion time AD conversion time control ADRLC ADMRC Register Register Frequency Division Ratio 3 112 LC871A00 Chapter 3 How to calculate the conversion time 12 bit AD conversion mode Conversion time 52 division ratio 2 x 1 3 8 bit AD conversion mode Conversion time 32 division ratio 2 x 1 3 xTcyc Notes The conversion time is doubled in the following cases 1 The AD conversion is carried out in the 12 bit AD conversion mode for the first time after a system reset 2 The AD conversion is carried out for the first time after the AD conversion mode is switched from 8 bit to 12 bit AD conversion mode The conversion time determined by the above formula is taken in the second and subsequent conversions or in the AD conversions that are carried out in the 8 bit AD conversion mode 3 17 4 3 conversion results register low byte ADRLC 1 The AD conversion results register low byte is used to hold the lower order 4 bits of the results of an AD conversion carried out in the 12 bit AD conversion mode and to control the conversion time 2 Since the data in this register is not esta
107. 4 SCK4 pin master operation 0 No SIO4 sync clock is transmitted out of P24 SCK4 pin slave operation P23MOS bit 3 P23 serial data output type select flag 1 CMOS output 0 N channel open drain output P230UT bit 2 P23 serial data I O control 1 5104 serial data is transmitted out of P23 514 pin 0 No 5104 serial data is transmitted out of P23 514 pin P22MOS bit 1 P22 serial data output type select flag 1 CMOS output 0 N channel open drain output P220UT bit 0 P22 serial data I O control 1 104 serial data is transmitted out of P22 SO4 pin 0 No SIO4 serial data is transmitted out of P22 SO4 pin Mode SI4CN1 register Clock Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Transmit Receive E PARA 1 P22 P23 P24OUT P23MOS P230UT P22MOS P220UT P22 data Intemd o 1 M transmit None External 0 2 0 l P23 data RA 0 1 1 _ transmit None External 9 2 0 l l 9 P23 amp 22 Internal 1 ut ee f data transmit Notie External i 2 0 l l i l None Paz data ils c a eee EE 0 0 receive External 0 pe dani 0 0 p i 0 0 receive External 0 P22 data P23 Internal d eee 1 0 1 transmit receive External 0 P23data P22daa p PSEA _ transmit receive External 0
108. 4 bits x 16 bits execution time 12 Tcyc 16 bits 8 bits execution time 8 Tcyc 24 bits 16 bits execution time 12 Tcyc Oscillation circuits and PLL RC oscillator circuit built in For system clock CF oscillator circuit For system clock Crystal oscillator circuit For system clock and time of day clock PLL circuit built in For USB interface Standby function e HALT mode Halts instruction execution while allowing the peripheral circuits to continue operation 1 Oscillation will not stop automatically 2 Reset by a system reset or interrupt e HOLD mode Suspends instruction execution and the operation of the peripheral circuits 1 The PLL base clock generator CF oscillator and RC oscillator automatically stop operation 2 There are four ways of releasing the HOLD mode 1 Setting the reset pin to the lower level 2 Setting at least one of the INTO INT1 INT2 INT4 and 5 pins to the specified level 3 Having an interrupt source established at port 0 4 Having a bus active interrupt source established in the USB interface circuit e X tal HOLD mode Suspends instruction execution and the operation of the peripheral circuits except the base timer and infrared remote control receiver 1 The PLL base clock generator and RC oscillators automatically stop operation 2 state of crystal oscillation established when the hold mode is entered is retained 3 There are six ways o
109. 5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 TOCNT TOLRUN TOLONG TOLEXT TOHIE TOLCMP TOHRUN bit 7 TOH count control When this bit is set to 0 timer counter 0 high byte TOH stops on a count value of 0 The match buffer register of TOH has the same value as TOHR When this bit is set to 1 timer counter 0 high byte TOH performs the required counting operation The match buffer register of TOH is loaded with the contents of TOHR when a match signal is generated TOLRUN bit 6 TOL count control When this bit is set to 0 timer counter 0 low byte TOL stops on a count value of 0 The match buffer register of TOL has the same value as TOLR When this bit is set to 1 timer counter 0 low byte TOL performs the required counting operation The match buffer register of TOL is loaded with the contents of TOLR when a match signal is generated TOLONG bit 5 Timer counter 0 bit length select When this bit is set to 0 timer counter 05 higher and lower order bytes serve as independent 8 bit timers counters When this bit is set to 1 timer counter 0 functions as a 16 bit timer counter A match signal is generated when the count value of the 16 bit counter comprising TOH and TOL matches the contents of the match buffer register of TOH and TOL TOLEXT bit 4 TOL input clock select When this bit is set to 0 the count clock for TOL is the match signal for the prescaler When
110. 8 8 2 buffer areas E2BNK 20 1 2 address 0 0 0300H to 033FH 0 0 1 0310H to 034 0 1 0 0320H to 035 0 1 1 0330H to 036FH 1 0 0 0340H to 037FH 1 0 1 0350H to 038FH 1 1 0 0360H to 039FH 1 1 1 0370H to 3 18 4 20 EP3 status register Address Initial Value BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE94 00000000 R W EP3STA E3EN E3TGL E3OVR E3STL E3ACK E3DIR E3ISO E3BNK ESEN bit 7 EP3 enable flag 1 Ifthis bit is set to 1 the USB interface processes the token at endpoint 3 2 Ifthis bit is set to 0 the USB interface does not process the token at endpoint 3 E3TGL bit 6 EP3 data toggle 1 Onan OUT transaction the receive data is transferred to RAM only when the packet ID in the data packet from the host matches E3TGL The state of E3TGL is automatically inverted when the transaction terminates normally with an ACK The E3TGL state does not invert however for isochronous transfers 2 IN transaction the USB interface transmits the data packet with a packet ID matching E3TGL The state of E3TGL is automatically inverted when the USB interface receives an ACK from the host ESOVR bit 5 EP3 payload over 1 This bit is automatically set to when the USB interface receives a volume of data exceeding the maximum payload size defined in EP3CNT 2 This flag must be cleared with an instruction ESSTL bit 4
111. 8 bit address space is ignored and the contents of B register are placed in the ACC as the result of computation OFFO1H amp OFFH 0FE00H 2 11 5 Direct Addressing dst The direct addressing mode allows a RAM or SFR address to be specified directly in an operand In this addressing mode the assembler automatically generates optimum instruction code from the address specified in the operand the number of instruction bytes varies according to the address specified in the operand Long middle range instructions identified by an L M at the end of the mnemonic are available to make the byte count of instructions constant align instructions with the longest one Examples LD 123H Transfers the contents of RAM address 123H to the accumulator 2 byte instruction LDL 123H Transfers the contents of RAM address 123H to the accumulator 3 byte instruction 11 STW 123H Transfers the contents of the BA register pair to RAM address 123H PUSH 123H Saves the contents of RAM address 123H in the stack SUB 123H Subtracts the contents of RAM address 123H from the accumulator DBZ 123H 11 Decrements the contents of RAM address 123H by 1 and causes a branch if zero 2 8 LC871A00 Chapter 2 2 11 6 ROM Table Look up Addressing The LC870000 series microcontrollers can read 2 byte data into the BA register pair at once using the LDCW instruction Three addressing modes Rn Rn C and off are available for
112. 8 bit register that controls the operation of the base timer Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE7F 0000 0000 R W BTCR BTFST BTON 1 BTC10 BTIF1 BTIFO BTFST bit 7 Base timer interrupt 0 period control Used to select the interval at which base timer interrupt 0 is to occur If this bit is set to 1 the base timer interrupt 0 flag is set when an overflow occurs in the 6 bit counter The interval at which overflows occur is 64TBST If this bit is set to 0 the base timer interrupt 0 flag is set when an overflow occurs in the 14 bit counter The interval at which overflows occur is 16384TBST This bit must be set to 1 when the high speed mode is to be used TBST Is the period of the input clock to the base timer that is selected by the input signal select register ISL bits 4 and 5 BTON bit 6 Base timer operation control When this bit is set to 0 the base timer stops when a count value of 0 is reached When this bit is set to 1 the base timer continues operation BTC11 bit 5 Base timer interrupt 1 period control BTC10 bit 4 Base timer interrupt 1 period control BTIEO BTFST BTC11 BTC10 Base Timer Interrupt Cycle 0 Base Timer Interrupt Cycle 1 16384TBST 32TBST 0 0 0 L1 68 32TBST __ 164757 I28TBST S NNI 128TBST 1 512TBST Eso
113. AM and shift register are automatically exchanged in the continuous data transfer mode 0 Transmission only the contents of RAM are automatically transferred to the shift register in the continuous data transfer mode but the contents of RAM remain unchanged SI4END bit 1 End of SIO4 transfer flag This bit is automatically set at the end of 5104 transfer It must be cleared under program control SI4IE bit 0 Interrupt enable flag An interrupt request to vector address 003BH is generated when this bit and SIAEND are all set to 1 3 13 4 4 5104 control register 1 SIACN1 1 SI4CN1 register is an 8 bit register that sets up 5104 communication ports PARA bit 7 Parallel mode select 1 Turns on the parallel mode 0 Turns off the parallel mode serial mode 3 80 LC871A00 Chapter 3 P1 PO bit 6 Parallel serial control flag Parallel mode When PARA 1 PI PO select flag 1 The data I O port for the 8 bit parallel interface is assigned to P1 0 The data I O port for the 8 bit parallel interface is assigned to PO Serial mode When PARA 0 P24 5104 clock output type select flag 1 CMOS output 0 N channel open drain output P22 P23 bit 5 104 serial data input port select flag 1 Serial data to SIO4 is received via P22 04 pin 0 Serial data to SIO4 is received via P23 SIA pin P240UT bit 4 P24 sync clock I O control flag 1 The SIO4 sync clock is transmitted out of P2
114. CMOS 8 BIT MICROCONTROLLER LC871A00 SERIES USER S MANUAL iis REV 1 02 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the
115. CONO RECRUN is set when a falling edge of the signal at the receive port P21 is detected 3 Endofreceive operation When the receive operation ends UCONO RECRUN is automatically cleared and UCONO RECEND is set The UARTI then waits for the start bit of the next received data 4 Receive interrupt processing Read the received data RBUF Clear UCONO RECEND and STRERR and exit the interrupt processing routine When changing the data length and baudrate for the next receive operation do so before the start bit falling edge of the signal is detected at the receive port P21 5 Nextreceive data processing Subsequently repeat steps 2 3 and 4 shown above To terminate continuous mode receive processing clear UCONO STRDET during a receive operation and this receive operation will be the last receive operation that the executes 3 09 UART 3 15 5 2 Continuous 8 bit data transmit mode first transmit data 55H Stop bit ANET Next start bit Beginning of Start bit Beginning of transmission Transmit data LSB first trasmission d Y ees m 1 ix Tee NENNEN UN id transmission DELE A 1 gt lt 3 gt 5 1 1 t 2 4 Figure 3 15 4 Example of Continuous 8 bit Data Transmit Mode Processing 1 Setting the clock Set the baudrate Setting up transmit data Load the transmit data TBUF 55 Setting the data length transmit po
116. D are set to 1 an interrupt request to vector address 0033H is generated 3 60 LC871A00 Chapter 3 3 11 4 2 100 data shift register SBUFO 1 5100 data shift register is an 8 bit shift register for serial transmission 2 Data to be transmitted received is written to and read from this shift register directly Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE31 0000 0000 R W SBUFO SBUFO7 SBUF06 SBUFOS SBUF04 SBUFO3 SBUFO2 SBUFO1 SBUFOO 3 11 4 3 Baudrate generator register SBRO 1 baudrate generator register is 8 bit register that defines the baudrate of 5100 2 Thebaudrate is computed as follows TSBRO SBRO value 1 x Tcyc SBRO can take a value from 1 to 255 and the valid value range of TSBRO is from 4 to 3 The SBRO value of OO H is disallowed Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE32 0000 0000 R W SBRO SBRGO7 SBRG06 SBRGOS SBRG04 SBRGO3 SBRGO2 SBRGO1 SBRGOO 512 3 3 11 4 4 Continuous data bit register SCTRO 1 The continuous data bit register is used to specify the bit length of serial data to be transmitted received through SIOO in the continuous data transmission reception mode 2 valid value range is from 00 to FF H 3 When continuous data transmission reception is started with this register set to OO H 1 bit of data transmission reception is carried ou
117. DPIEZ bit 1 D pin input enable flag 1 Setting this bit to 1 disables the D pin for data read 2 Setting this bit to 0 enables the D pin for data read 3 This bit must be set to 0 when performing USB communication DMIEZ bit 0 D pin input enable flag 1 Setting this bit to 1 disables the D pin for data read 2 Setting this bit to 0 enables the D pin for data read 3 This bit must be set to 0 when performing USB communication 3 18 4 4 USB port control register USPORT Address Initial Value R W Name BIT7 6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE81 0000 0000 R W DDRSOF P72NDL USBSIO SUSPND DDRDP DDRDM PORTDP PORTDM DDRSOF bit 7 SOF detect pulse output control 1 Setting DDRSOF to 1 P7 FESCH bit 6 P72DDR to 1 and P7 5 bit 2 P72 to 0 causes an SOF detect pulse approx 80 ns to be generated from P72 on reception of an SOF 3 125 USB P72NDL bit 6 Reserved bit Must always be set to 0 USBSIO bit 5 Reserved bit Must always be set to 0 SUSPND bit 4 USB transceiver operation control flag 1 Setting this bit to 1 places the USB transceiver into the suspended state The USB transceiver can detect bus active conditions even in this state 2 Ifthis bit is set to 0 the USB transceiver continues its normal operation DDRDP bit 3 D pin general purpose output control 1 If this bit is set to 1 PORTDP data is generated out of the D pin 2 Th
118. ED3 0000 0000 R W TIBUF6 TIBUF5 TIBUF4 2 TIBUFI TIBUFO 3 15 4 5 UART1 receive data register RBUF 1 The UARTI receive data register is an 8 bit register that stores the data that is received through the UARTI 2 The data from the receive shift register RSFT is transferred to this RBUF at the end of a receive operation Bit8 of the received data is placed in the receive data b it 8 storage bit UCONO RBITS Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FED4 0000 0000 R W RBUF RIBUF7 RIBUF6 RIBUF5 RIBUF4 RIBUF3 RIBUE2 RIBUFI RIBUFO 3 98 LC871A00 Chapter 3 3 15 5 UART1 Continuous Communication Processing Examples 3 15 5 1 Continuous 8 bit data receive mode first received data 55H Start bit Next start bit Beginning of 5 End of reception Receive data LSB first reception mE v 5 gt y mE P21 input 1 1 gt Stop bit lt 4 5 1 1 2 3 Figure 3 15 3 Example of Continuous 8 bit Data Reception Mode Processing Setting the clock Set the baudrate Setting the data length mode e Clear UCONI 8 9BIT Configuring the UARTI for receive processing and setting up the receive port and receive interrupts Setup the receive control register UCONO 41H Set P21DDR P2DDR BIT1 to 0 and P21 P2 BIT1 to 0 2 Starting a receive operation U
119. EG3 AREG2 AREGO The B register is combined with the ACC to form a 16 bit arithmetic register during the execution of a 16 bit arithmetic instruction During a multiplication or division instruction the B register is used with the ACC and C register to store the results of computation In addition during an external memory access instruction LDX or STX the B register designates the higher order 8 bits of the 24 bit address The B register is allocated to address FEO1H of the internal data memory space and initialized to on a reset Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO 1 0000 0000 R W BREG BREG7 BREG6 BREGS BREG4 BREG3 BREG2 BREGI BREGO 2 3 2 7 Register The register is used with the ACC register to store the results of computation during the execution of a multiplication or division instruction In addition during a C register offset indirect instruction the C register stores the offset data 128 to 127 to the contents of an indirect register The C register is allocated to address 2 of the internal data memory space and initialized to on reset Address Initial value R W Name BIT7 BIT6 BITS BIT4 2 BIT1 BITO FE02 0000 0000 R W CREG CREG7 CREG6 CREGS CREG4 CREG3 CREG2 CREGI CREGO 2 8 Program Status Word PSW The program status word PSW is made up of flag
120. EP3 stall flag 1 USB interface returns STALL handshake for IN and OUT transactions ESACK bit 3 EP3 ACK flag 1 this bit is set to 1 the USB interface transmits a data packet for an IN transaction and an handshake for an OUT transaction 2 Ifthis bit is set to 0 the USB interface returns handshake for IN and OUT transactions 3 See Table 3 18 12 E3DIR bit 2 EP3 transfer direction flag 1 115 bit is set to 1 the USB interface processes only IN tokens at endpoint 3 2 Ifthis bit is set to 0 the USB interface processes only OUT tokens at endpoint 3 3 See Table 3 18 12 ESISO bit 1 EP3 isochronous transfer 1 Setting this bit to 1 sets the transfer type of endpoint 3 to isochronous 2 Ifthis bit is set to 0 the transfer type of endpoint 3 is either bulk transfer or interrupt transfer 3 See Table 3 18 12 3 136 LC871A00 Chapter 3 E3BNK bit 0 EP3 transfer RAM address control flag 1 Setting this bit and E3OF 1 0 EPADOF bits5 and 4 allocates the data transmit receive buffer areas for endpoint 3 Table 3 18 9 EP3 buffer areas ESBNK 1 ESOFO RAM address 0 0 0 0380H to 0 0 1 0390H to 03 0 1 0 03A0H to 03DFH 0 1 1 03BOH to 1 0 0 03COH to 1 0 1 03DOH to 040 1 1 0 03 to 041FH 1 1 1 03F0H to 042FH 3 18 4 21 EP4 status register EP4STA Address Initial
121. H PWML 237 Ripple 3 16 4 6 PWMO1 port input register PWMO1P 2 bit register 1 PWMO data can be read into this register as bit 0 2 PWMI data can be read into this register as bit 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE25 HHHHHHXX PWMOIP PWMIIN PWMOIN Bits 7 to 2 Not available always read as 1 PWM1IN bit 1 PWM1 data read only PWMOIN bit 0 PWMO data read only 3 108 LC871A00 Chapter 3 3 17 AD Converter ADC12 3 17 1 Overview This series of microcontrollers incorporates a 12 bit resolution AD converter that has the features listed below It allows the microcontroller to take in analog signals easily 3 17 2 1 12 bit resolution 2 Successive approximation 3 AD conversion mode select resolution switching 4 12 analog input 5 Conversion time select 6 Automatic reference voltage generation control Functions 1 Successive approximation The ADC has a resolution of 12 bits Requires some conversion time The conversion results are placed in the AD conversion results registers ADRLC 2 AD conversion select resolution switching The AD converter supports two AD conversion modes 12 and 8 bit conversion modes so that the appropriate conversion resolution can be selected according to the operating conditions of the application The AD mode register ADMRC is used to select
122. IOO suspends processing when the HALT mode is entered while running in the continuous data transmission reception mode immediately before the contents of RAM and SBUFO are exchanged After the HALT mode is entered SIOO continues processing until immediately before the contents of first RAM address and SBUFO are exchanged After the HALT mode is reset SIOO resumes the suspended processing Since SIOO processing is suspended by the HALT mode it is impossible to reset the HALT mode using a continuous data transmission reception mode SIOO interrupt 3 64 LC871A00 Chapter 3 3 12 Serial Interface 1 101 3 12 1 Overview The serial interface SIO1 incorporated in this series of microcontrollers provides the following four functions 1 Mode 0 Synchronous 8 bit serial I O 2 or 3 wire system clock rates of 2 to 512 Tcyc 2 Mode 1 Asynchronous serial I O Half duplex 8 data bits 1 stop bit baud rates of 8 to 2048 Tcyc 3 Mode 2 Bus master start bit 8 data bits transfer clock of 2 to 512 Tcyc 4 Mode 3 Bus slave start detection 8 data bits stop detection 3 12 2 Functions 1 Mode 0 Synchronous 8 bit serial I O Performs 2 or 3 wire synchronous serial communication The clock may be an internal or external clock The clock rate of the internal clock is programmable within the range of 2 to 512 Tcyc 2 Mode 1 Asynchronous serial UART Performs half duplex 8 data bits 1 stop bit asynchronous serial communication
123. Ifthis bit is set to 0 the transfer type of endpoint 1 is either bulk transfer or interrupt transfer 3 See Table 3 18 12 E1BNK bit 0 EP1 transfer RAM address control flag 1 Setting this bit and EIOF 1 0 EPADOF bits and 0 allocates the data transmit receive buffer areas for endpoint 1 Table 3 18 7 buffer areas E1BNK E10F1 E10F0 RAM address 0 0 0 0280H to 02 0 0 1 0290H to 02 0 1 0 02 to 02 0 1 1 02 to 02 1 0 0 02COH to 02 1 0 1 02DOH to 030FH 1 1 0 02 to 031FH 1 1 1 02F0H to 032FH 3 18 4 19 EP2 status register EP2STA Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITO FE93 00000000 R W EP2STA E2EN E2TGL E20VR E2STL E2ACK E2DIR E2ISO E2BNK E2EN bit 7 EP2 enable flag 1 Ifthis bit is set to 1 the USB interface processes the token at endpoint 2 2 If this bit is set to 0 the USB interface does not process the token at endpoint 2 E2TGL bit 6 EP2 data toggle 1 Onan OUT transaction the receive data is transferred to RAM only when the packet ID in the data packet from the host matches E2TGL The state of E2TGL 15 automatically inverted when the transaction terminates normally with an ACK The E2TGL state does not invert however for isochronous transfers 2 IN transaction the USB interface transmits the data packet with a packet ID matching E2TGL The state of E
124. Internal Pull up P20 P20DDR TDDR TCMOS Resistor 0 1 1 CMOS output Off 0 0 1 0 N channel open drain output Off 0 1 0 N channel open drain output On The UART transmits no data if P20DDR is set to 1 UART1 HALT Mode Operation Receive mode UARTI s receive mode processing is enabled in the HALT mode If UCONO STRDET is set to 1 when the microcontroller enters the HALT mode receive processing will be restarted if data such that UCONO RECRUN is set at the end of a receive operation The HALT mode can be reset using the UARTI receive interrupt Transmit mode UARTI s transmit mode processing is enabled in the HALT mode If the continuous transmission mode is specified when the microcontroller enters the HALT mode the UARTI will restart transmission processing after terminating a transmit operation Since UCONI TEPTY cannot be cleared in this case the UARTI stops processing after completing that transmit operation The HALT mode can be reset using the UARTI transmit interrupt 3 101 PWM 3 16 PWMO and PWM1 3 16 1 Overview This series of microcontrollers incorporates two 12 bit PWMs named PWMO and PWM1 Each PWM is made up of a PWM generator circuit that generates multifrequency 8 bit fundamental PWM waves and a 4 bit additional pulse generator PWM0 and PWM 1 are provided with dedicated output pins PWMO and respectively 3 16 2 1 2 3 4 5 Functions
125. L Toggle output Period T1HR 1 x TIHPRC count x Toggle output Period TILR 1 x TILPRC 2 2 count x 2Tcyc x 2 Period TILR 1 x TILPRC count x events x 2 RAR PWM output Period 256 x T1HPRC count x PWM output Period 256 x TILPRC count x 2 1 Toggle output Period T1HR 1 x TIHPRC count x Toggle output Period TILR 1 x TILPRC TILR 1 x TILPRC count x 2 2 count x2Tcyc x 2 or Period 1 x TIHPRC count x or Period TILR 1 x TILR 1 x TILPRC x events x 2 count x events x 2 3 1 1 Toggle output Period T1HR 1 x TIHPRC count PWM output Period 256 x TILPRC count 256 x TILPRC count 2 x Tcyc T1HCMP bit 3 T1H match flag This flag is set if T1H reaches 0 when is active TIHRUN 1 This flag must be cleared with an instruction 3 43 Ti T1HIE bit 2 interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and TIHCMP are set to 1 bit 1 T1L match flag This flag is set if TIL reaches 0 when TIL is active TILRUN 1 This flag must be cleared with an instruction 1 bit 0 T1L interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and TILCMP are set to 1 Note TIHCMP and TILCMP must be cleared to 0 with an instruction 3 8 4 2 Timer 1 prescaler control register T1P
126. ML period TIPWMH period 1 period x 2 5 Interrupt generation TIL or T1H interrupt request is generated at the counter period of the TIL or TIH timer if the interrupt request enable bit 1 set 6 Tocontrol timer 1 T1 it is necessary to manipulate the following special function registers TICNT TIL TIH TILR TIHR TIPRR PI PIDDR PIFCR P2 P2DDR I45CR I45SL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE18 0000 0000 R W TIHRUN TILRUN TILONG TIPWM TIHCMP TILCMP 1 0000 0000 TIL TIL7 116 TILS TIL3 1112 TILO FEIB 0000 0000 R 6 5 4 T1H3 2 T1HO FEIC 0000 0000 R W TILR TILR7 TILR6 TILRS TILR4 TILR3 TILR2 TILRI TILRO FEID 00000000 R W TIHR 1 7 TIHR6 5 TIHR4 TIHR3 TIHR2 TIHRO FE19 0000 0000 R W 2 TIPRC2 TILPRCI TILPRCO Note 1 The output of the TIPWML is fixed at the high level if the TIL is stopped If the TIL is running the output of the TIPWML is fixed at the low level when TILR FFH The output of TIPWMH is fixed at the high level if the T1H is stopped If the T1H is running the output of the TIPWMH is fixed at the low level when Ti 3 8 3 Circuit Configuration 3 8 3 1 Timer 1 control
127. MP EOMP6 5 4 2 1 3 18 4 16 receive data count register EPORX 1 receive data count register indicates the number of data bytes received at endpoint 0 2 The contents of this register are updated when a SETUP or OUT transaction for endpoint 0 terminates normally with an ACK 3 133 USB Address Initial Value BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE90 H000 0000 EPORX EORX6 EORX5 EORX4 EORX3 EORX2 EORXI EORXO 3 18 4 17 EPO transmit data count register EPOTX 1 The EPO transmit data count register must be loaded with the number of data bytes to be transmitted through endpoint 0 2 The legitimate value range is from 00 H to 40 H Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE91 H000 0000 EPOTX EOTX6 5 EOTX4 EOTX3 EOTX2 EOTXI EOTXO 3 18 4 18 status register EP1STA Address Initial Value R W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE92 0000 0000 R W EPISTA ELEN EITGL EIOVR EISTL EIDIR E1EN bit 7 EP1 enable flag 1 If this bit is set to 1 the USB interface processes the token at endpoint 1 2 Ifthis bit is set to 0 the USB interface does not process the token at endpoint 1 E1TGL bit 6 EP1 data toggle 1 OUT transaction the receive data is transferred to RAM only when the packet ID in the d
128. N bit 7 USB clock control flag USBRUN bit 6 USB clock control flag 1 These bits turn on and off the USB clock Table 3 18 5 USB Clock Control Settings USBON USBRUN USB Operation 0 Enables the function to detect only USB bus active conditions 1 The other USB functions are disabled Enables the function to detect only USB bus reset and USB bus active 1 0 conditions The other USB functions are disabled 1 1 Enables the entire USB block Bus state other than bus idle J state 1 state or SEO VD30EN bit 5 D pull up control flag 1 Setting this bit to 1 causes a high D pull up level to be presented at the P70 pin In this case bit 4 P70DDR and bit 0 P70 of the P7 register FESCH must be set to 0 2 Setting this bit to 0 inhibits the high D pull up level from being generated at the P70 pin In this case the P70 pin is held in the Hi Z state if bit 4 P70DDR and bit 0 P70 of the P7 register FESCH are set to 0 VD3KIL bit 4 Reserved Must always be set to 0 IDLFG bit 3 Suspend detection flag 1 This flag is set when a suspend condition staying in bus idle state for 3 ms or longer is detected 2 This bit remains set until the suspend condition is reset 3 This flag must be cleared with an instruction IDLEN bit 2 Suspend interrupt request enable flag 1 interrupt request to vector address 0033H is generated when this bit and IDLFG are set to 1
129. O to INT2 INTA e Reset entry conditions INTS POINT or USB INTS5 POINT USB bus established bus active active base timer or Reset entry conditions remote controller established receiver circuit Reset entry conditions established Returned mode Normal mode Note1 HALT Notel HALT Notel Data changed on PCON register bit 0 PCON register bit 1 0 register bit 1 0 exit 0 Note 1 The microcontroller switches into the reset state if it exits the current mode on the establishment of reset entry conditions canceled Note 2 Parts of the serial transmission function and USB host control circuit are stopped 4 15 Standby Table 4 3 2 Pin States and Operating Modes Normal Mode HALT Mode HOLD Mode On Exit from HOLD Input e X tal oscillator will not start e Feedback resistor between and XT2 is turned off Input e X tal oscillator will not start Feedback resistor between 1 and XT2 is turned off oscillator inverter input e Feedback resistor present between CF1 and CF2 oscillator inverter output Oscillation enabled Controlled by register OCR as X tal oscillator input data can be read through a register FEOEH 0 is always read in oscillation mode Feedback resistor between and XT2 15 controlled by a program Controlled by register OCR
130. O2H 2 is designated Examples When contains 123 RAM address 0 23H RAM address 1 01H LD 10H Transfers the contents of RAM address 133H to the accumulator Li STW 10H Transfers the contents of the BA register pair to RAM address 133H PUSH 10H Saves the contents of RAM address 133H in the stack SUB 10H Subtracts the contents of RAM address 133H from the accumulator DBZ 10H L1 Decrements the contents of RAM address 133H by 1 and causes a branch if Zero Notes on this addressing mode The internal data memory space is divided into three closed functional areas as explained in Section 2 1 namely 1 system reserved area FF00 to FFFF 2 SFR area FEOO to FEFF and 3 RAM stack area 0000 to FDFF Consequently it is disallowed to point to a different area using an offset value from the basic area designated by the contents of RO For example if the instruction LD 1 is executed when RO contains OFDFFH since the basic area is 3 RAM stack area 0000 to FDFF the intended address 1 OFEOOH lies outside the basic area and is placed in the ACC as the results of LD If the instruction LD 2 is executed when RO contains OFEFFH since the basic area is 2 SFR to FEFF the intended address 2 OFFO1H lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the
131. Overview Port 2 is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register and a control circuit Control of the input output signal direction is accomplished by the data direction register on a bit basis Port 2 can also serve as an input port for external interrupts It can also be used as an input port for the timer 1 count clock input timer 0 capture signal input and HOLD mode release signal input As user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type on a bit basis 3 3 2 Functions 1 Input output port 8 bits P20 to P27 The port 2 data latch P2 48 is used to control port output data and the port 2 data direction register P2DDR FE49 to control the I O direction of port data Each port bit is provided with a programmable pull up resistor 2 Interrupt input pin function The port INT4 selected out of P20 to P23 and the port 5 selected out of P24 to P27 are provided with a pin interrupt function This function senses a low edge a high edge or both edges and sets the interrupt flag These two selected ports can also serve as timer 1 counter clock input and timer 0 capture signal input 3 Hold mode release function When the interrupt flag and interrupt enable flag are set by INT4 or INT5 a HOLD mode release signal i
132. PNO3 EPNO2 TKNO CTKNI CTKNO EPNOS bit 7 Endpoint number EPNO2 bit 6 Endpoint number EPNO bit 5 Endpoint number EPNOO bit 4 Endpoint number 1 These register bit positions are loaded with the endpoint number from the token packet when one of the following conditions is established 1 The transaction terminates normally with an ACK 2 NKREN n 0 to 8 is set to 1 and the transaction for endpoint n terminates with an 3 ERnEN n 0 to 8 is set to 1 and the transaction for endpoint n terminates with an error 4 STnEN n 0 to 8 is set to 1 and the transaction terminates with a stall 1 bit 3 Token ID TKNO bit 2 Token ID 1 These register bit positions are loaded with the token ID when either of the above conditions 1 to 4 is established CTKN1 bit 1 EPO token ID CTKNO bit 0 EPO token ID 1 These register bit positions are loaded with the token ID when either of the above conditions 1 to 4 Is established for an endpoint 0 transaction Table 3 18 6 Token IDs Token Token ID OUT 00 IN 10 SETUP 11 3 18 4 14 status register EPOSTA Address Initial Value R W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 00000000 R W EPOSTA EOTGL EOOVR EOSTL EOACK EOCSU EOCST EOCRW EOEN bit 7 EPO enable 1 If this bit is set to 1 the USB interface processes the token at end
133. PTSEL 1 Serial data I O pin 04 P22 P13 Serial data I O pin 514 23 14 Sync clock I O pin SCK4 P24 P15 When SAPTSEL is set to 1 make settings explained 3 13 4 4 5104 control register 1 SI4CN1 while substituting P22 P23 and P24 for P13 P14 and P15 respectively SAADRS to 0 bit 5 to 0 RAM start address highest 6 bits The lowest order 6 bits of S ADDR and the 8 bits of SAADRL are used to define the start address of the RAM area to be used for data transfer 3 82 LC871A00 Chapter 3 S4ADDR lowest order 6 bits S4ADRL RAM start address H H H 00 00 0000 00 01 0001 07 3 13 4 9 5104 transfer data byte register high byte S4BYTH 1 The SABYTH register is used to specify continuous data transfer processing is to be suspended on a 1 or 2 byte basis 2 Theregister is also used to control how to read the number of transferred data bytes 3 The register is used to define the highest order 4 bits of the number of data bytes to be transferred in the continuous data transfer mode Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FED7 0000 0000 R W SABYTH SASTPWD S4BYTRD S4BYTHS S4BYTH4 SABYTHG3 S4BYTH2 SABYTHI S4BYTHO S4STPWD bit 7 1 2 byte boundary suspension control flag 1 Continuous mode data transfer is suspended on a 2 byte boundary 0 Continuous mode data transfer is suspended on 1 byte bounda
134. Port P27 I5SL1 bit 5 INT5 pin function select 15510 bit 4 INT5 pin function select When the data change specified in the external interrupt 4 5 control register 145 is given to the pin that is assigned to INTS timer 1 count clock input and timer 0 capture signal are generated 15511 15510 Function other than INT5 Interrupt None 14513 bit 3 INT4 pin select 14512 bit 2 INT4 pin select 14513 14512 Pin Assigned to INT4 0 0 Port P20 Port P23 14511 bit 1 INT4 pin function select 14510 bit 0 INT4 pin function select When the data change specified in the external interrupt 4 5 control register 145 is given to the pin that is assigned to INT4 timer 1 count clock input and timer 0 capture signal are generated 14511 14510 Function other than INT4 Interrupt None Timer 1 count clock input 0 0 Eu Tm Timer OL capture signal input Timer OH capture signal input Notes 1 When timer OL capture signal input or timer OH capture signal input is specified for INT4 or INTS together with port 7 the signal from port 7 is ignored 2 When INT4 and INT5 are specified in duplicate for timer 1 count clock input timer OL capture signal input or timer OH capture signal input both interrupts are accepted If both INT4 and INTS events occur at the same time however only one event is recognized 3 When at least one of INT4 and INT5 is specified as timer 1 co
135. RM2GPH3 RM2GPH2 M2GPL3 RM2GPL2 RM2D0H2 LODIR SBRGO2 SI TEND SBUF11 SBRG11 SBRG10 SOXBYT1 SOXBYTO FE32 R W SBRGO7 88606 88605 88604 88603 FE34 SIDIR FE36 Rw sea SBRG13 FE38 HHHH HHHH rm FESA HHHH HHHH ru SI10VR SBUF12 SBRG12 SOXBYT2 FE3C HHHH HHHH FE3D HHHH HHHH 2 LC871A00 APPENDIX I Address Initial value R W LC871A00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO HHHH HHHH None ur Ee s mg omo mit sor f 000 000 m r5 v rs 0000 0000 ww wm Pacbor Poon 00 _ ru uen msie manes rus ww wx S gt isi 60 meo m m 0000 ww Piano POOR ue mew we I rur war wr O gt www we ms mmm
136. RR 1 Thisregister sets up the count values for the timer 1 prescaler 2 When the register value is changed while the timer is running the change is reflected in the prescaler operation at the same timing when the match buffer register for the timer T1L T1H is updated Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE19 0000 0000 R W TIHPRE TIHPRC2 TILPRE TILPRC2 TILPRCI TILPRCO T1HPRE bit 7 Controls the timer 1 prescaler high byte T1HPRC2 bit 6 Controls the timer 1 prescaler high byte bit 5 Controls the timer 1 prescaler high byte T1HPRCO bit 4 Controls the timer 1 prescaler high byte T1HPRE T1HPRC2 T1HPRC1 T1HPRCO T1H Prescaler Count 0 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 T1LPRE bit 3 Controls the timer 1 prescaler low byte T1LPRC2 bit 2 Controls the timer 1 prescaler low byte T1LPRC1 bit 1 Controls the timer 1 prescaler low byte T1LPRCO bit 0 Controls the timer 1 prescaler low byte 3 44 LC871A00 Chapter 3 T1LPRE T1LPRC2 T1LPRC1 T1LPRCO T1L Prescaler Count 0 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 3 8 4 3 Timer 1 lo
137. Realtime output realtime output is placed at pin P17 Realtime output is a function to change the state of output at a port into realtime when the count value of a counter reaches the required value This change in output occurs asynchronously with any clock for the microcontroller 3 Capture operation The value of high speed clock counter is captured into NKCOV and NKCAP2 to NKCAPO in synchronization with the capture operation of TOL timer 0 low byte NKCOV is a carry into timer counter 0 When this bit is set to 1 the capture value of timer counter 0 must be corrected by 1 NKCAP2 to NKCAPO carry the capture value of the high speed clock counter 4 Interrupt generation The required timer counter flag is set when the high speed clock counter and timer counter 0 keep counting and their count value reaches timer O s match register value 1 x 8 NKCMP2 to NKCMPO In this case a TOL interrupt request is generated if the interrupt request enable bit is set 3 32 LC871A00 Chapter 3 5 To control the high speed clock counter it is necessary to manipulate the following special function registers NKREG PITST TOCNT TOL TOH TOLR TOHR P7 ISL 1 D3CR e P2 P2DDR 145 14551 FE7D 0000 0000 R W NKREG NKEN NKCMP2 NKCMPI NKCOV NKCAP2 NKCAPO rm rw PrTST mxo DSNKOT mo FEI2 00000000 R TOL
138. Setting up the communication mode SIACNO SI4RUN 0 SBITON 1 MSBSEL 1 0 SARAM O SI4WRT 1 SI4TE 1 IE 7 1 SBITON 1 The SIO4 detects the falling edge of the signal at the serial data input port and starts automatic SIO4 transfer 3 Setting up the clock SI4CNO S4CKPL 1 0 SIACNI PARA 0 4 Setting up ports SIACNI For data reception from P13 gt P22 P23z1 P240UT 0 P220UT 0 For data reception from 14 gt 22 23 0 P240UT 0 P230UT 0 5 Setting the byte count SABYTH SABYTE Specify the number of bytes to be received continuously 6 Setting up the 5104 data transfer RAM address offset register SAADDR S4ADRL Load SIO4 RAM address register with the starting address of the RAM data area to be used for continuous serial data reception 7 Starting data transfer The SIO4 sets SIARUN SIACNO bit 7 and starts automatic SIO4 transfer when it detects the falling edge of the signal at the serial data input port 8 Endof transfer processing SIARUN SIO4CNO bit 7 is automatically cleared SI4END SI4CNO bit 1 is set and an interrupt request to vector address 003B H is generated when the last data byte of the data whose byte count is specified in step 5 is transferred to the shift register 9 Reading received data Received data is stored in RAM sequentially starting at the RAM starting address specified in 6 The last data byte is held in the shift register and n
139. T3 TDAT2 TDATI TDATO 3 18 4 32 Endpoint buffer offset register EPADOF 1 Theendpoint buffer offset register designates the buffer offsets for endpoints 1 to 4 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEAE 0000 0000 4 4 0 E2OFI 20 0 EIOFI E1OFO E40F1 bit 7 buffer offset bit 6 EP4 buffer offset 1 See Table 3 18 10 ESOF1 bit 5 buffer offset ESOFO bit 4 EP3 buffer offset 1 See Table 3 18 9 2 1 bit 3 EP2 buffer offset 2 bit 2 2 buffer offset 1 See Table 3 18 8 E10F1 bit 1 buffer offset bit 0 buffer offset 1 See Table 3 18 7 3 140 LC871A00 Chapter 3 Table 3 18 11 Endpoint 0 Status Register Transition Chart EPOSTA 3 0 Receive Receive Receive EPOSTA 3 0 Token Response End flag ACK CSU CST CRW toggle data buffer ACK CSU CST CRW Invalid Update 0 0 0 0 0 0 Poe Valid Update ACK 0 1 0 0 ACK 20 OUT 01010 0 IN 0 0 0 0 Invalid Update 0 0 0 1 Error 0 Update 0 1 0 0 OUT s m 9 9 0 1 IN 0 0 0 1 Invalid Update 0
140. T6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE9B H000 0000 R W EP2RX E2RX6 E2RX5 E2RX4 E2RX3 E2RX2 E2RXI E2RX0 3 18 4 26 EP3 count register EP3CNT 1 The EP3 count register must be loaded with the number of transmit data bytes for endpoint 3 if the transfer direction of endpoint 3 is IN E3DIR 1 3 138 LC871A00 Chapter 3 2 If the transfer direction of endpoint 3 is OUT E3DIR 0 this register must be loaded with the maximum payload size of endpoint 3 3 The legitimate value range is from 00 H to 40 H Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE9C H000 0000 E3CN6 E3CN5 E3CN4 E3CN3 E3CN2 E3CNI E3CNO 3 18 4 27 EP3 receive data count register EP3RX 1 The EP3 receive data count register indicates the number of data bytes received at endpoint 3 2 The contents of this register are updated when an OUT transaction for endpoint 3 terminates normally with an ACK Address Initial Value R W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE9D H000 0000 E3RX6 E3RX5 E3RX4 E3RX3 E3RX2 E3RX1 E3RX0 3 18 4 28 EP4 count register EP4CNT 1 The EP4 count register must be loaded with the number of transmit data bytes for endpoint 4 if the transfer direction of endpoint 4 is IN E4DIR 1 2 If the transfer direction of endpoint 4 is OUT E4DIR 0 this register must be loaded with the maximum payload size of endpoint 4 3 The legitimate value ra
141. UF FEDD H RAM S4ADDR S4ADRL 0500 H 3 87 3 13 6 1 2 SIO4 HALT Mode Operation The SIO4 suspends processing immediately before the contents of RAM and SI4BUF are exchanged after the microcontroller enters the HALT mode Even after the microcontroller enters the HALT mode the SIO4 continues processing until the contents of the first RAM location and SI4BUF are exchanged The SIO4 resumes and continues processing after the microcontroller exits the HALT mode Since the SIO4 suspends processing on entry into the HALT mode the HALT mode cannot be released using the interrupt to SIO4 3 88 LC871A00 Chapter 3 3 14 Parallel Interface 3 14 1 Overview This series of microcontrollers can generate a read or write signal to external memory when an instruction accessing a port PO or P1 is executed The generation of the address needs to be set up under program control 3 14 2 Functions 1 External memory read mode Execution of an instruction PUSH LD etc for reading data from a port PO or P1 generates a read signal RD from pin P22 or P13 2 External memory write mode Execution of an instruction POP ST etc for writing data into a port PO or P1 generates a write signal WR from pin P23 or P14 The ports are assigned using S4PTSEL S4ADDR bit 6 Port assignment y o Description P22 P13 Output Read signal output pin 23 14 Output Write signal output pin 3
142. USB Application Note 3 18 6 USB Interface HALT Mode Operation 1 When the HALT mode is entered USB communication involving data transmission and reception cannot proceed normally since the automatic data transfer between RAM endpoint buffer and the transmit receive buffer is interrupted in that case 2 The HALT mode can be reset by generating a USB interface interrupt that involves neither data transmission nor reception 3 144 LC871A00 Chapter 3 3 19 Infrared Remote Control Receiver Circuit 2 REMOREC2 3 19 1 Overview This series of microcontrollers is equipped with an infrared remote control receiver circuit 2 REMOREC2 that has the following features and functions 1 Noise filtering 2 Supports 5 receive formats Receive format A Guide pulse Half clock Data encoding system PPM Pulse Position Modulation Stop bits No Receive format supporting repeat code reception Guide pulse Clock Data encoding system PPM Stop bits Yes Receive format C Guide pulse None Data encoding system PPM Stop bits Yes Receive format D Guide pulse None Data encoding system Manchester coding Stop bits No Receive format E Guide pulse Clock Data encoding system Manchester coding Stop bits No 3 HOLD mode release function 3 19 2 Functions 1 Remote control receive function The REMOREC2 tests the pulses of the remote control signal input from the P73 RMIN pin using
143. Valid 1 0 0 1 IN 1 0 0 1 i 0 0 1 0 1 0 IN STALL 1 0 1 0 STALL i 0 1 0 1 1 IN Tx 0 1 1 0 1 1 OUT _ Invalid 1 1 0 0 Error 1 1 0 0 Valid STALL 1 0 0 STALL IN 1 0 0 OUT _ Invalid Update 1 1 0 1 Error 1 1 0 1 Valid Update 1 0 0 1 IN 1 0 1 i 0 1 1 1 0 IN STALL 1 1 1 0 STALL OUT 1 1 1 1 1 l IN 3 Eos 1 0 1 1 Shaded columns contain register contents receive buffer update a responses to the token from the host 1 A data packet containing no data is transmitted 2 The number of bytes specified in EPnTX are transmitted 3 143 USB 3 18 5 USB Communication Examples 3 18 5 1 Setting up clocks 1 Setup the PLLCNT register according to the frequency of the ceramic oscillator element connected across the CF1 and CF2 pins See 3 18 4 2 USB PLL control register 2 Set OCR register bit 7 CLKSGL and bit 4 CLKCB4 to 1 to designate the main clock as the system clock perform USB communication it is necessary to set the system clock frequency to 8 MHz or higher Table 3 18 13 Sample Clock Settings Ceramic oscillator frequency PLLCNT OCR 8 MHz 00 H 90 H 12 MHz 80 H 90 H 3 18 5 2 Configuration for USB communication Refer to the separate document entitled
144. W is popped BIT8 ignored INC 9 bits INC 17 bits DEC 9 bits DEC 17 bits DEC 9 bits check lower order 8 bits DEC 9 bits check lower order 8 bits Bit 8 of RAM address for storing results is set to 1 REGHS REGL6 Bit 8 of the higher order byte of a RAM location SFR bit 8 of the lower order byte RAMS Bit 6 of a RAM location RAMHS8 RAMLS gt Bit 8 of the higher order byte of a RAM location bit 8 of the lower order byte 2 12 LC871A00 Chapter 3 3 Peripheral System Configuration This chapter describes the built in functional blocks peripheral system of the LC871A00 series microcontrollers except the CPU core RAM and ROM Port block diagrams are provided in Appendix for reference 3 1 Port 0 311 Overview Port 0 is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register and a control circuit Control of the input output signal direction and the pull up resistors is accomplished through the data direction register in 4 bit units This port can also serve as a terminal for external interrupts and can release the HOLD mode As a user option either CMOS output with a programmable pull up resistor or N channel open drain output can be selected as the output type on a bit basis 3 1 2 Functions 1 Input output port 8 bits POO P07 The port output data is controlled by port 0 data latch FE40 on a bit basis control of
145. Z2TGL is automatically inverted when the USB interface receives an ACK from the host 2 bit 5 EP2 payload over flag 1 This bit is automatically set to 1 when the USB interface receives a volume of data exceeding the maximum payload size defined in EP2CNT 2 This flag must be cleared with an instruction E2STL bit 4 EP2 stall flag 1 The USB interface returns STALL handshake for IN and OUT transactions E2ACK bit 3 EP2 ACK flag 1 this bit is set to 1 the USB interface transmits a data packet for an IN transaction and an handshake for an OUT transaction 2 If this bit is set to 0 the USB interface returns handshake for IN and OUT transactions 3 See Table 3 18 12 E2DIR bi 2 EP2 transfer direction flag 1 If this bit is set to 1 the USB interface processes only IN tokens at endpoint 2 2 If this bit is set to 0 the USB interface processes only OUT tokens at endpoint 2 3 See Table 3 18 12 2 5 bit 1 2 isochronous transfer flag 1 Setting this bit to 1 sets the transfer type of endpoint 2 to isochronous 3 135 U 2 Ifthis bit is set to O the transfer type of endpoint 2 is either bulk transfer or interrupt transfer 3 See Table 3 18 12 E2BNK bit 0 EP2 transfer RAM address control flag 1 Setting this bit and E2OF 1 0 EPADOF bits3 and 2 allocates the data transmit receive buffer areas for endpoint 2 Table 3 1
146. ability and changes its state in synchronization with the data in the port latch The realtime output function and match detection function will not be resumed until the next NKREG write operation is performed NKCOV 2 bits 3 0 Capture register The NK counter value is captured into these bits in synchronization with the timer OL capture operation NKCOV is a carry into timer 0 When this bit is set to 1 the capture value of timer 0 must be corrected by 1 NKCAP2 to NKCAPO carry the capture value of the NK counter These bits are read only 3 34 LC871A00 Chapter 3 NK Comparison Value TOL Comparison Value NK Counter 3 Bits NK Carry TOL Counter 8 Bits TOL Match Signal NK Capture TOL Capture m Capture Signal Figure 3 7 1 TOLONG 0 Timer 0 8 bit mode Block Diagram NK Comparison Value TOL Comparison Value TOH Comparison Value NK Counter 3 Bits NK TOL Counter 8 Bits TOH Counter 8 Bits TOL Match Signal NK Capture j TOL Capture Capture Capture Signal Figure 3 7 2 TOLONG 1 Timer 0 16 bit mode Block Diagram 3 35 3 8 3 8 1 Timer Counter 1 T1 Overview The timer counter 1 T1 incorporated in this series of microcontrollers is a 16 bit timer counter with a prescaler that provides the following four functions 1 2 3 4 3 8 2 1 2 3 Mode 0 Two channels of 8 bit programmable timer with 8 bit prescaler with to
147. address 004BH POHPU bit 3 7 04 pull up resistor control When this bit is set to 1 and POHDDR to 0 pull up resistors are connected to port bits PO7to P04 that are selected as CMOS output POLPU bit 2 PO3 POO pull up resistor control When this bit is set to 1 and POLDDR to 0 pull up resistors are connected to port bits to POO that are selected as CMOS output POHDDR bit 1 7 4 1 0 control A in this bit places PO7 to P04 into the output mode in which case the contents of the corresponding port 0 data latch PO are output When this bit is set to 0 PO7 to 4 are placed into the input mode and POFLG is set when low level is detected at a port whose corresponding port 0 data latch PO bit is set 1 POLDDR bit 0 to I O control A 1 in this bit places to into the output mode in which case the contents of the corresponding port 0 data latch PO are output When this bit is set to 0 to are placed into the input mode and POFLG is set when a low level is detected at a port whose corresponding port 0 data latch PO bit is set 1 LC871A00 Chapter 3 3 1 3 3 Port 0 function control register POFCRU 1 This 6 bit register controls Port 0 s shared output pins Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE4F 0000 0000 R W POFCRU 7 T6OE SCKOSL5 SCKOSL4 CLKOEN CKODV2 CKODV1 CKODVO 7 bit 7 Controls the outp
148. age and a control circuit that controls the reference voltage generator circuit and the conversion results The end of conversion bit ADENDF of the AD control register ADCRC is set when an analog input channel is selected and the AD conversion terminates in the conversion time designated by the conversion time control register The conversion results are placed in the AD conversion results registers ADRHC ADRLC 3 17 3 3 Multiplexer 1 MPX1 1 Multiplexer 1 is used to select the analog signal to be subject to AD conversion from 12 channels of analog signals 3 17 3 4 Automatic reference voltage generator circuit 1 The reference voltage generator circuit consists of a network of ladder resistors and a multiplexer MPX2 and generates the reference voltage that is supplied to the comparator circuit Generation of the reference voltage is automatically started when an AD conversion starts and stopped when the conversion ends The reference voltage output ranges from VDD to VSS 3 17 4 Related Registers 3 17 4 1 control register ADCRC 1 The AD control register is an 8 bit register that controls the operation of the AD converter Initial value 7 Bits AD AD AD AD AD AD FE58 0000 0000 R W ADCRC ADCR3 ADIE CHSEL3 CHSEL2 CHSELI CHSELO START ENDF ADCHSELS bit 7 ADCHSEL2 bit 6 ADCHSEL1 bit 5 AD conversion input signal select ADCHSELO bit 4 The
149. an transmit and receive 1 to 256 bits of serial data in the continuous data transmission reception mode using RAM area from 01CO H to 01FF H 1 2 3 3 11 5 3 11 5 1 1 2 3 4 5 The RAM area ranging from addresses 01CO H to 01DF H is used when SIOBNK 0 The RAM area ranging from addresses to 01FF H is used when SIOBNK 1 In the continuous data transmission reception mode data transmission reception is started after the operation flag is set and RAM data at the lowest address is transferred to SBUFO after the contents of RAM and SBUFO are exchanged when SIOWRT 1 After 8 bits of data are transmitted and received the RAM data from the next RAM address is transferred to SBUFO the contents of RAM and SBUFO are exchanged when SIOWRT 1 and data transmission reception processing is continued The last 8 bits or less of received data are left in SBUFO and not exchanged with data in RAM If the volume of data to transmit receive is set to 8 bits or less after the operation flag is set and RAM data is transferred to SBUFO after the contents of RAM and SBUFO are exchanged when SIOWRT 1 data transmission and reception are carried out Any data received after the transmission reception processing terminated is left in SBUFO and not exchanged with data in RAM 100 Transmission Examples Synchronous 8 bit mode Setting the clock Setup SBRO when using an internal clock Setting the transmissi
150. annel open drain 3 4 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 4 5 HALT and HOLD Mode Operation When in the HALT or HOLD mode port 3 retains the state that is established when the HALT or HOLD mode is entered 3 5 3 5 1 LC871A00 Chapter 3 Port 7 Overview Port 7 is a 4 bit I O port equipped with programmable pull up resistors It is made up of a data control latch and a control circuit The input output direction of port data can be controlled on a bit basis Port 7 can be used as an input port for external interrupts It can also be used as an input port for the timer 0 count clock input capture signal input and HOLD mode release signal input There is no user option for this port 3 5 2 1 2 3 4 5 Functions Input output port 4 bits P70 to P73 The lower order 4 bits of the port 7 control register P7 FESC are used to control the port output data and the higher order 4 bits to control the I O direction of port data P70 is of the N channel open drain output type and P71 to P73 are of CMOS output type Each port bit is provided with a programmable pull up resistor Interrupt input pin function e P70 and P71 are assigned to INTO and INTI respectively and used to detect low high level or a low or high edge and set the interrupt flag
151. arious receive format modes RM2DINV bit 3 REMOREC2 receive input polarity control This bit must be set to 0 when the remote control input signal is a positive phase signal This bit must be set to 1 when the input signal is a negative phase signal REMOREC starts receive processing assuming the detection of a start edge immediately when it is activated if the positive phase input mode is specified for the high level of the remote control input signal or if the negative phase input mode is specified for the low level of the remote control input signal 3 150 LC871A00 Chapter 3 2 2 bit 2 RM2CK1 bit 1 REMOREC2 receive base clock RM2CK select 2 bit 0 0 0 0 4 Tcyc 0 0 1 8 0 1 0 16 0 1 1 32 1 0 0 64 1 0 1 128 1 1 0 Subclock source oscillation 1 1 1 1 Notes The registers in the remote control receiver circuit must be set up when RM2RUN is set to 0 operation stopped When releasing the X tal HOLD mode set the RM2CK to subclock source oscillation The REMOREC2 will not run with any other RM2CK settings in the X tal HOLD mode since the cycle clock is stopped in the X tal HOLD mode 3 19 4 2 Remote control receive interrupt control register RM2INT 1 remote control receive interrupt control register is an 8 bit register that controls the handling of interrupts occurring in the remote control receiver circ
152. ata packet from the host matches EITGL The state of EITGL is automatically inverted when the transaction terminates normally with an ACK The EITGL state does not invert however for isochronous transfers 2 IN transaction the USB interface transmits the data packet with a packet ID matching EITGL The state of is automatically inverted when the USB interface receives an ACK from the host bit 5 payload over flag 1 This bit is automatically set to 1 when the USB interface receives a volume of data exceeding the maximum payload size defined in EPICNT 2 This flag must be cleared with an instruction E1STL bit 4 EP1 stall flag 1 USB interface returns a STALL handshake for IN and OUT transactions E1ACK bit 3 EP1 ACK flag 1 this bit is set to 1 the USB interface transmits a data packet for an IN transaction and an handshake for an OUT transaction 2 If this bit is set to 0 the USB interface returns handshake for IN and OUT transactions 3 See Table 3 18 12 E1DIR bit 2 EP1 transfer direction flag 1 If this bit is set to 1 the USB interface processes only IN tokens at endpoint 1 2 If this bit is set to 0 the USB interface processes only OUT tokens at endpoint 1 3 See Table 3 18 12 3 134 LC871A00 Chapter 3 E11SO bit 1 EP1 isochronous transfer 1 Setting this bit to 1 sets the transfer type of endpoint 1 to isochronous 2
153. ation Circuit with a Pull up Resistor 4 Entering HALT HOLD mode when the condition is WDTHLT 1 WDTCLR WDTRST and WDTRUN is reset Returning from HALT HOLD to normal operation mode initialize set its condition again and start the watchdog timer 4 26 Appendixes Table of Contents Appendix Special Functions Register SFR Appendix Il e Port 0 Block Diagram Port 1 Block Diagram Port 2 Block Diagram Port 3 Block Diagram Port 7 Block Diagram Port PWMOI Block Diagram LC871A00 APPENDIX I Address Initial value R W LC871A00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO 0 7 XXXX R W 9 bits long wt Mcr 1 LC871A00 APPENDIX I Address Initial value R W LC871A00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FETE HHHH HHHH None FE20 PIINOL FE22 PIIMTL ae ae FE24 ENPWMT mw ae cur cs m N2DINV RM2GPOK M2SFUL RM2SFIE a aes NES a s LV c RMZSFT7 RMZSFT RM2SFTS RHZSFTA RN2SFTS RM2RDT5 RM2RDT3 2 see arc EMEN al EL FE28 RAI FE 0000 R REST FE2A R RMRDT FE2C R W RM2GPW FE2D FE2E gt
154. blished during an AD conversion the conversion results must be read out after the AD conversion is completed Name ADRLC DATALS bit 7 DATAEZ DILG Lower order 4 bits of AD conversion results DATAL1 bit 5 DATALO bit 4 ADRL3 bit 3 Fixed bit This bit must always be set to 0 ADRL2 bit 2 Fixed bit This bit must always be set to 0 ADRL1 bit 1 Fixed bit This bit must always be set to 0 2 bit 0 AD conversion time control This bit and AD mode register bits ADTM1 and ADTMO are used to control the conversion time See the subsection on the AD mode register for the procedure to set the conversion time Note The conversion results data contains some errors quantization error combination error Be sure to use only valid conversion results while referring to the latest Semiconductor News 3 17 4 4 conversion results register high byte ADRHC 1 The AD conversion results register high byte is used to hold the higher order 8 bits of the results of an AD conversion that is carried out in the 12 bit AD conversion mode The register stores the whole 8 bits of an AD conversion that is carried out in the 8 bit AD conversion mode 2 Since the data in this register is not established during an AD conversion the conversion results must be read out after the AD conversion is completed 3 113 ADC12 3 17 5 AD Conversion Example 3 17 5 1 12 bit AD conversion mode 1 Setting up the
155. body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner Contents Chapter 1 orien riu e er rer re eer rere ree te tr cere rer cer terry 1 1 1 1 1 1 1 2 a 1 1 1 3 eee 1 6 1 4 System Block Diagram mmm 1 8 1 5 FUNCTIONS 1 9 1 6 Port Output Types meme 1 11 1 7 USB Reference Power Supply 1 12 2 Internal Configuration 2 1 2 1 Memory Space memes 2 1 2 2 Program Counter emen 2 1 2 3 Program Memory ROM 2 2 2 4 Internal Data Memory mme 2 2 25 Accumulator A Register ACC A
156. bort the receive operation When a receive operation is forced to terminate prematurely RECEND is set to 1 and the contents of the receive shift register are transferred to RBUF STPERR is set to 1 if the state of the last data bit that is received on the forced termination is low STPERR bit 4 UART1 stop bit error flag 1 This bit is set at the end of a receive operation if the state of the received stop bit the last data bit received is low 2 This bit must be cleared with an instruction UOB3 bit 3 General purpose flag 1 This bit can be used as a general purpose flag bit Any attempt to manipulate this bit exerts no influence on the operation of this functional block RBITS bit 2 UART1 receive data bit 8 storage bit 1 This bit position is loaded with bit 8 of the received data when the data length is set to 9 bits UCONI 8 9BIT 1 If the receive operation is terminated prematurely this bit position is loaded with the last received bit but one 2 This bit must be cleared with an instruction RECEND bit 1 End of UART1 reception flag 1 This bit is set at the end of a receive operation When this bit is set the received data is transferred from the receive shift register RSFT to the receive data register RBUF 2 This bit must be cleared with an instruction Tn the continuous receive mode the next receive operation is not carried out even when the UARTI detects such data as sets the start of receive op
157. can occur Shield both ends of analog signal lines with noise free ground shields 3 115 ADC12 Make sure that no digital pulses are applied to or generated out of pins adjacent to the analog input pin that is being subject to conversion Correct conversion results may not be obtained because of noise interferences if the state of port outputs is changing To minimize the adverse influences of noise interferences it is necessary to keep the line resistance across the power supply and the VDD pins of the microcontroller at minimum This should be kept in mind when designing an application circuit Adjust the amplitudes of the voltage at the oscillator pin and the I O voltages at the other pins so that they fall within the voltage range between VDD and VSS 10 To obtain valid conversion data perform conversion operations on the input several times discard the maximum and minimum values of the conversion results and take an average of the remaining data 3 116 LC871A00 Chapter 3 3 18 USB Interface 3 18 1 Overview This series of microcontrollers is provided with a USB Universal Serial Bus function control circuit that has the following features 1 Compatible with the USB Specification Version 2 0 2 Compatible with Full Speed 12 Mbps specifications 3 Supports the control transfer bulk transfer interrupt transfer and isochronous transfer modes 3 18 2 Functions 1 USB function control Can define a maximum of 5 endp
158. ch P12 output control Baud rate generator Serial transfer end flag SBRO FE32h 5100 overrun flag Emm SCONO FESOh Interrupt request Figure 3 11 2 5100 Continuous Data Transmission Reception Block Diagram SIOCTR 1 3 59 00 3 11 4 Related Registers 3 11 4 1 5100 control register SCONO 1 The SIOO control register is an 8 bit register that controls the operation and interrupts of SIOO Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE30 0000 0000 R W SCONO SIOBNK SIOWRT SIORUN SIOCTR SIODIR SIOOVR SIOEND SIOIE SIOBNK bit 7 Transfer RAM address control during continuous data transmission reception 1 When this bit is set to 1 transfer of continuous transmission reception data is carried out between RAM addresses 01E0 H to 01FF H and SBUFO 2 When this bit is set to transfer of continuous transmission reception data is carried out between RAM addresses 01CO H to 01DF H and SBUFO SIOWRT bit 6 RAM write control during continuous data transmission reception 1 When this bit is set to 1 the contents of data RAM and SBUFO are automatically exchanged during continuous mode data transmission reception 2 When this bit is set to 0 the contents of data RAM are automatically transferred to SBUFO during continuous mode data transmission reception but the contents of data RAM remain unchanged SIORUN bit 5 SIOO operation flag 1 A 1 in
159. ch buffer register A match signal is generated when the value of this match buffer register coincides with the lower order byte of timer counter 0 16 bits of data need to match in the 16 bit mode The match buffer register is updated as follows The match register matches TOLR when it is inactive TOLRUN 0 When the match register is running TOLRUN 1 it is loaded with the contents of TOLR when a match signal is generated Timer counter 0 match data register high byte 8 bit register with a match buffer register This register is used to store the match data for TOH It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the higher order byte of timer counter 0 16 bits of data need to match in the 16 bit mode The match buffer register is updated as follows The match register matches TOHR when it is inactive TOHRUN 0 When the match register is running TOHRUN 1 it is loaded with the contents of when a match signal is generated 3 25 3 6 3 8 1 2 3 6 3 9 1 2 Timer counter 0 capture register low byte TOCAL 8 bit register Capture clock External input detection signals from the P70 INTO TOLCP and P72 INT2 TOIN and P20 to P27 timer OL capture input pins when TOLONG timer 0 control register bit 5 18 set to 0 External input detection signals from the P71 INTI TOHCP and P73 INT3 TOIN and P20 to P27 timer OL capture
160. circuit 1 main clock oscillation circuit gets ready for oscillation by connecting a ceramic oscillator and a capacitor to the CF1 and CF2 pins 2 CFI must be connected to VDD and CF2 must be released when the main clock is not to be used 4 2 3 2 Subclock oscillation circuit 1 The subclock oscillation circuit gets ready for oscillation by connecting a crystal oscillator 32 768 kHz standard a capacitor feedback resistor and a damping resistor to the XT1 and XT2 pins 2 The state ofthe and XT2 pins can be read as bits 2 and 3 of the register OCR 3 When the subclock is not to be used XT1 must be connected to VDD XT2 must be released and bit 6 of the OCR register must be set 4 2 3 3 Built in RC oscillation circuit 1 Thebuild in RC oscillation circuit oscillates according to the built in resistance and capacitance 2 The clock from the RC oscillation circuit is selected as the system clock after the microcontroller exits the reset or HOLD mode 3 Unlike main clock and subclock oscillation circuits the RC oscillation circuit starts oscillation from the beginning of oscillation at a normal frequency 4 6 4 2 3 4 D 2 3 4 4 2 3 5 D 4 2 3 6 D 2 3 4 4 2 3 7 1 4 2 3 8 1 2 4 2 3 9 1 2 4 2 3 10 LC871A00 USB dedicated internal PLL oscillation circuit The USB dedicated PLL oscillation circuit oscillates to drive the main clock by connecting a ceramic oscillator
161. d then restart counting Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7A 0000 0000 R W T6R T6R7 T6R6 T6R5 T6R4 T6R3 T6R2 6 T6RO 3 50 LC871A00 Chapter 3 3 9 4 3 Timer 7 period setting register T7R 1 This register is an 8 bit register for defining the period of timer 7 Timer 7 period T7R value 1 x Timer 7 prescaler value 4 16 or 64 Tcyc 2 When data is written into T7R while timer 7 is running both the timer 7 s prescaler and counter are temporarily cleared then restart counting 0000 0000 3 9 4 4 Port 0 function control register POFCRU 1 This register is a 6 bit register that controls the shared functions of port 0 pins It controls the timer 6 and timer 7 toggle output Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE42 0000 0000 POFCRU T7OE T6OE SCKOSLS SCKOSLA CLKOEN CKODV2 CKODV1 CKODVO 7 bit 7 This flag is used to control the timer 7 toggle output at pin P07 This flag is disabled when pin 7 is set in the input mode When pin 07 is set in the output mode A 0 in this bit causes the value of port data latch to be presented at pin 07 A 1 in this bit causes the OR of the value of the port data latch and the waveform which toggles at the interval equal to the timer 7 period at pin 07 6 bit 6 This flag is used to control the timer 6 toggle output at pin PO6 This flag is disable
162. d Edge detected Timing 1 RM2CK Timing 2 End of Count start Count reset amp sampling divided by 2 Identify reception start Setting up the receive format E criterion values timings The procedure for setting up the guide pulse criterion values for receive format E is identical to that for receive format B The procedure for setting up the data pulse receive timings for receive format E 15 identical to that for receive format D Note The minimum criterion value is RM2CK x 4 The interval between upper and lower guide pulse must be set up at intervals of RM2CK x 4 or greater Receive format E receive operation 1 The REMOREC2 remains in the idle state until it receives a guide pulse normally When the guide pulse falls within the valid criterion value range the REMOREC2 resets the RM2MJCT and sets the RM2GPOK flag and tests the next data pulse At this moment the RM2SFT and RM2BCT are reset 2 At timing 1 in step 2 the REMOREC2 samples the remote control signal If the REMOREC2 detects an edge after starting the detection of an edge at this timing and before timing 3 it resets the 2 and proceeds with the next step a data error is identified if no edge is detected 3 At timing 1 in step 3 or 8 the REMOREC2 samples the remote control signal 4 At timing 2 in step 3 or 8 the REMOREC2 tests the data that is sampled in step 2 7 3 5 If the data is identified as or 1 it 0 1 is loaded
163. d when pin is set in the input mode When pin P06 is set in the output mode A 0 in this bit causes the value of port data latch to be presented at pin A 1 in this bit causes the OR of the value of the port data latch and the waveform which toggles at the interval equal to the timer 6 period at pin P06 SCKOSLS bit 5 SCKOSLA bit 4 The above two bits have no bearing on the control of timers 6 and 7 See the description of port 0 for details on these bits CLKOEN bit 3 CKODV2 bit 2 CKODV1 bit 1 CKODVO bit 0 The above four bits have no bearing on the control of timers 6 and 7 See the description of port 0 for details on these bits 3 51 3 10 3 10 1 Base Timer BT Overview The base timer BT incorporated in this series of microcontrollers is a 14 bit binary up counter that provides the following five functions 1 2 3 4 5 3 10 2 1 2 3 4 5 7 Clock timer 14 bit binary up counter High speed mode when used as a 6 bit base timer Buzzer output Hold mode reset Functions Clock timer The base timer can count clocks at 0 5 second intervals when a 32 768 kHz subclock is used as the count clock for the base timer In this case one of the three clocks namely cycle clock timer counter 0 prescaler output and subclock must be loaded in the input signal select register ISL as the base timer count clock 14 bit binary up counter A 14 bit bi
164. data is identified as 0 or 1 it 0 1 is loaded into the RM2SFT The data from the RM2SFT 15 transferred to the RM2RDT every time the REMOREC2 receives 8 bits of data At this moment the sets the RM2SFUL flag and resets the RM2SFT 5 If the data is identified as error the REMOREC2 sets the RM2DERR flag and returns into the idle state waiting for a next rising edge 6 At timing 3 the REMOREC2 samples the remote control signal If the REMOREC2 detects an edge after starting the detection of an edge at this timing and before timing 4 it resets the RM2MJCT and returns to step 2 7 When the REMOREC2 detects the end of reception condition it sets RM2REND and RM2HOLD flags and suspends operation Subsequently when the RMO2SFT is read the REMOREC 2 clears the RM2HOLD flag and enters the idle state waiting for a next rising edge resuming the receive operation 3 159 REMOREC2 3 19 5 5 Receive operation when receive format E is specified Receive format E outline Guide pulse Yes Data encoding system Manchester Stop bits No Example of a receive format E receive operation positive phase input RM2RUN set to 1 P73 RMIN Data Data i i q a us B Check end of reception Guide pulse Timing 3 Timing 4 criterion value sampling End or reception detected Overflow detected high side Guide pulse criterion value low side RM2MJCT count value Edge detecte
165. detection conditions is supplied to P72 Note When timer OL capture signal input or timer OH capture signal input is specified for INT4 or INTS together with in port 7 the signal from port 7 is ignored 3 5 4 Options There is no user option for port 7 3 5 5 HALT and HOLD Mode Operation The pull up resistor to P70 is turned off P71 to P73 retain their state that 1s established when the HALT or HOLD mode is entered 3 22 3 6 3 6 1 1 2 3 4 3 6 2 2 3 LC871A00 Chapter 3 Timer Counter 0 TO Overview The timer counter 0 TO incorporated in this series of microcontrollers is a 16 bit timer counter that provides the following four functions Mode 0 Two channels of 8 bit programmable timer with a programmable prescaler equipped with an 8 bit capture register Mode 1 8 bit programmable timer with a programmable prescaler equipped with an 8 bit capture register 8 bit programmable counter equipped with an 8 bit capture register Mode 2 16 bit programmable timer with a programmable prescaler equipped with a 16 bit capture register Mode 3 16 bit programmable counter equipped with a 16 bit capture register Functions Mode 0 Two channels of 8 bit programmable timer with a programmable prescaler equipped with an 8 bit capture register Two independent 8 bit programmable timers TOL and run on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler Mode
166. e 1 UART1 mH 3 92 3151 3 92 3 15 2 Functions mmm mmm 3 92 3 15 3 Circuit Configuration mener 3 93 3 15 4 Related Registers nnne 3 95 3 15 5 UART1 Continuous Communication Processing Examples strstr 3 99 3 15 6 UART1 HALT Mode Operation mme 3 101 PWMO emm nnne 3 102 3 16 1 3 102 3 16 2 FUNCTIONS mm 3 102 iii Contents 3 16 3 Circuit Configuration Peete eee treet ree treet rere rere eee PAG 3 103 3 1 6 4 Related Registers Peete etree treet rere reer 9 C F 9 F 9 3 1 04 3 1 7 AD Converter ADC1 2 3 1 09 3 17 1 Overview eee eee eee eee eer eee tree treet reer errr errr errr errr errr errr eter rere rrr 3 1 09 3 1 7 2 Functions Peete etree treet reer etter rere etree tre ttre tree errr rere retire terete retire teeter etree AP 3 1 09 3 17 3 Circuit Configuration Peete eer eee etre etre 3 1 10 3 1 7 4 Related Registers Peete etre et
167. e R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE78 0000 0000 R W T67CNT 7 T7CO 6 0 T7IE T60V T7C1 bit 7 T7 count clock control T7CO bit 6 T7 count clock control T7C1 T7CO T7 Count Clock Timer 7 prescaler and timer counter are stopped in the reset state o RN T6C1 bit 5 T6 count clock control T6CO bit 4 count clock control T6C1 T6CO T6 Count Clock Timer 6 prescaler and timer counter are stopped in the reset state T7OV bit 3 7 overflow This flag is set at the interval of timer 7 s period when timer 7 is running This flag must be cleared with an instruction bit 2 T7 interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and T7OV are set to 1 T6OV bit 1 T6 overflow flag This flag is set at the interval of timer 6 s period when timer 6 is running This flag must be cleared with an instruction T6IE bit 0 T6 interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and T6OV are set to 1 3 9 4 2 Timer 6 period setting register T6R 1 This register is an 8 bit register for defining the period of timer 6 Timer 6 period T6R value 1 x Timer 6 prescaler value 4 16 or 64 Tcyc 2 When data is written into T6R while timer 6 is running both the timer 6 s prescaler and counter are temporarily cleare
168. e counter counts up on the RM2CK that is selected by the value of RM2CK2 through RM2CKO RM2CNT bits 2 through 0 The RM2CKPR uses different count setup registers when receiving the guide pulse and the data pulse The count is set up by RM2GPRI RM2GPRO RM2CTPR bits 7 and 6 or RM2DPRI and RM2DPRO RM2CTPR bits 5 and 4 A count clock to RM2MJCT is generated every one of the counts listed below 3 147 REMOREC2 3 19 3 8 1 3 19 3 9 1 3 19 3 10 1 3 19 3 11 1 2 Count clock to the RM2MJCT the guide pulse or data pulse receive mode When RM2FMT2 through RM2FMTO 0 to 2 is selected RM2GPR1 RM2GPRO RM2DPR1 RM2DPRO RM2CKPR Count Value Remote control receive guide pulse width setup register RM2GPW 8 bit register The remote control receive guide pulse width setup register is an 8 bit register that defines the width of the guide pulse The values of this register exerts no influence on the receive operation when RM2FMT2 through RM2FMTO are set to give a value of 2 or 3 Remote control receive data 0 pulse width setup register RM2DTOW 8 bit register The remote control receive data 0 pulse width setup register is an 8 bit register that defines the width of the data 0 pulse and timings 1 and 2 Remote control receive data 1 pulse width setup register RM2DT1W 8 bit register The remote control receive data 1 pulse width setup register is an 8 bit register that defines the width of th
169. e data 1 pulse and timings 3 and 4 Remote control receive guide pulse amp data pulse width high byte setup register RM2XHW 7 bit register The remote control receive guide pulse amp data pulse width high byte setup register is a 7 bit register that defines the width of the guide pulse and data pulse and sets the highest bit of timings 1 through 4 It is also used to control the direction in which data is loaded in RM2SFT Remote control receive pulse width measurement counter RM2MJCT 5 bit counter The remote control receive pulse width counter is a 5 bit up counter used to measure the pulse width of the remote control input signal and to generate timing signals It counts up on the count clock output from the RM2CKPR Note See the subsection entitled Operation of the remote control receiver circuit for the operation of the REMOREC2 in various receive format mode 3 148 LC871A00 Chapter 3 3 19 3 12 Remote control receive noise filter RM2NFLT 1 remote control receive noise filter rejects occurrences of the remote control input signals whose width is less than a predetermined duration as noises 2 When the REMOREC2 is running RM2RUN set to 1 the remote control input signal is always sampled at RM2CK The input signal is processed by the circuit as a valid signal if its signal levels remain the same while four samples are obtained If the input signal width is less than RM2CK 4 the remote control input signa
170. e instruction for one cycle during which transfers the required data This is called a wait sequence The peripheral circuits such as timers and PWM continue processing during the wait sequence A wait sequence extends over no more than two cycles The microprocessor performs no wait sequence when it is in the HALT or HOLD mode Note that one cycle of discrepancy is introduced between the progresses of the program counter and time once a wait sequence occurs 2 10 Table 2 12 1 Chart of State Transitions of Bit 8 RAM SFR and P1 Instruction BIT8 RAM SFR P1 PSW BIT 1 LC871A00 Chapter 2 Remarks LD LDW up p o o o Po PLCREGS B 8 lt 8 1 lt 8 POPW REGH8 lt RAMH8 REGL8 lt RAML8 lt 8 lt gt 1 Same as left INC INC 9 bits P1 lt REG8 after computation INCW INC 17 bits REGL8 lt lower byte of CY P1 lt REGH8 after computation DEC DEC 9 bits P1 REGS after computation DECW DEC 17 bits REGL8 lt lower byte of CY P1 REGHS after inverted computation DBNZ DEC 9 bits P1 lt REG8 DEC 9 bits P1 lt REG8 sf SS Nom S S 22 __ _ MUL24 8 lt 1 DIV24 Note 115 read if the processing target is 8 bit register no bit 8 Legends REGS Bit 8 of a RAM or SFR location P1 lt bitl when PSW is popped P1 lt bit1 when higher order address of PS
171. e timer 7 s prescaler and counter are temporarily cleared then restart counting 3 9 4 2 Timer 7 prescaler T7PR 6 bit counter 1 This prescaler is used to define the clock period the timer 7 determined by T7CO and T7C1 T67CNT FE78 bits 6 and 7 Table 3 9 2 Timer 7 Count Clocks T7 Count Clock Timer 7 prescaler and timer counter are reset 3 9 4 2 Timer 7 period setting register T7R 8 bit register 1 Thisregister defines the period of timer 7 2 When data is written into T7R while timer 7 is running both the timer 7 s prescaler and counter are temporarily cleared then restart counting 3 48 LC871A00 Chapter 3 Timer 6 period register T6R FE7Ah Timer 6 7 control register T67CNT FE78h T6 overflow T6R 1 x count clock lied Set prescaler count 1 Tove Clock Timer 6 prescaler Clock Timer 6 counter 6 Clear Timer 6 7 control register T67CNT FE78h Set Set 6 interrupt E T7 interrupt Clear Clear Timer 7 counter T7PR T7CTR Set prescaler count T7 overflow Timer 6 7 control register T7R 1 x count clock 1 Timer 7 prescaler T67CNT FE78h Timer 7 period register T7R FE7Bh Figure 3 9 1 Timer 6 7 Block Diagram 3 49 3 9 4 Related Registers 3 9 4 1 Timer 6 7 control register T67CNT 1 The timer 6 7 control register is an 8 bit register that controls the operation and interrupts of T6 and T7 Address Initial Valu
172. ecified bit length to data RAM at the specified address in the data transmission or data transmission reception mode RAM addresses 01CO H to 01DF H when SIOBNK 0 RAM addresses 01E0 H to OLFF H when SIOBNK 1 Data transmission and reception processing is started after the operation flag is set and the contents of RAM and SBUFO are exchanged Consequently there is no need to transfer data to SBUFO 6 Starting operation Set SIOCTR Set Suspending continuous data transmission processing Set SOWSTP Resuming continuous data transmission processing Clear SOWSTP Checking the number of bytes transferred during continuous data transmission processing Read SOXBYTA to SOXBYTO 7 Reading data after an interrupt Received data has been stored in data RAM at the specified address and SBUFO RAM addresses 01C1 H to 01DF H when SIOBNK 0 RAM addresses 01 E1 H to 01FF H when SIOBNK 1 The last 8 bits or less of received data is left in SBUFO and not present in RAM Clear SIOEND Return to step 5 when repeating transmission reception processing 3 63 3 11 6 3 11 6 1 2 3 11 6 2 1 2 100 HALT Mode Operation Synchronous 8 bit mode SIOO s synchronous 8 bit mode processing is enabled in the HALT mode The HALT mode can be reset by an interrupt that is generated during SIOO synchronous 8 bit mode processing Continuous data transmission reception mode S
173. en it is read 3 When PWMI control bit PWMOC FE24 bit 3 is set to 0 the output of ternary can be controlled using bits 7 to 4 of PWMIL 3 16 3 5 PWM 1 compare register PWM1H 8 bit register 1 The compare register controls the fundamental pulse width of PWMI 2 When bits 7 to 4 of PWMIL are all fixed at 0 PWMI can serve as period programmable 8 bit PWM that is controlled by PWM1H 3 16 3 6 PWMO01 port input register PWMO1P 2 bit register 1 PWMO data can be read into this register as bit 0 2 PWMI data can be read into this register as bit 1 3 103 PWM 3 16 4 Related Registers 3 1641 PWMO PWM control register PWMOC 8 bit register 1 control register controls the operation and interrupts of PWMO and PWM 1 Address Initial Value R W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE24 0000 0000 R W PWMOC PWMOC7 PNMOC6 PWMOCS ENPWM1 PWMOOV PWMOIE PWMOC7 to PWMOCA bits 7 to 4 PWMO PWM f period control e Fundamental wave period Value represented by PWMOC7 to PWMOCA 1 x 1 Overall period Fundamental wave period x 16 ENPWM bit 3 PWM1 operation control e When this bit is set to 1 is active e When this bit is set to 0 the PWM1 output ternary can be controlled using bits 7 to 4 of PWMIL bit 2 PWMO operation control When this bi
174. ence clock frequency select SELREF1 bit 6 PLL reference clock frequency select SELREFO bit 5 PLL reference clock frequency select 1 These bits are used to select the frequency of the ceramic oscillator element connected to the CF pins CF1 and CF2 Table 3 18 4 Ceramic Oscillator Frequencies SELREF 2 0 Frequency MHz 000 8 001 9 010 10 011 11 100 12 101 2 110 3 111 16 PLLTEST bit 4 Test bit for the PLL circuit Must always set to 0 VCOSTP bit 3 PLLVCO operation control flag CMPSTP bit 2 PLL phase comparator operation control flag 1 Must be set to 0 together with VCOSTP and CMPSTP to generate the USB 48 MHz clock from the internal PLL circuit In this case FE4DH bit 4 P34DDR and P3 FE4CH bit 4 P34 must be set to 0 In addition it is necessary to connect an external filter to the P34 UFILT pin as shown in Figure 3 18 3 2 Must be set to if the internal PLL circuit is not to be used LOWVDEC bit 1 Reserved bit Must always be set to 0 PWONRES bit 0 Reserved bit Must always be set to 0 3 18 4 3 USB operation control register USCTRL 1 USB operation control register is used to turn on and off the USB clock 3 124 LC871A00 Chapter 3 Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE80 00000000 USCTRL USBON USBRUN VD3KIL IDLFG IDLEN DPIEZ DMIEZ USBO
175. er RM2SFT 8 bit shift register 1 The RM2SFT is an 8 bit shift register used for storing remote control receive data 2 The direction in which receive data is stored LSB first or MSB first is determined by the value of RM2RDIR RM2XHW bit 7 3 Data is transferred from RM2SFT to RM2RDT each time this register is loaded with 8 bits of receive data This register is also used to read the last less than 8 bit receive data 3 146 4 3 19 3 4 2 3 19 3 5 2 3 3 19 3 6 2 3 LC871A00 Chapter 3 RM2SFT is reset when one of the following conditions occurs 1 The receive operation is stopped RM2RUN 0 2 A guide pulse is received normally after the beginning or resumption of a receive operation when RM2FMT2 through RM2FMTO RM2CNT bits 6 to 4 are set to give a value of 0 1 or 4 3 The first rising edge assuming that the input polarity is set to positive phase is detected after the beginning or resumption of a receive operation when RM2FMT2 through RM2FMTO are set to 2 or 3 4 A RM2SFT to RM2RDT data transfer occurs Remote control receive data register RM2RDT 8 bit register The remote control receive data register is an 8 bit register that holds the data received from the remote control The initial value of this register is unpredictable The contents of the RM2SFT are transferred to this register each time 8 bits of receive data are loaded in the RM2SFT Remote control receive bit co
176. er Circuit 2 Block Diagram RM2FMT2 0 0 2 3 149 REMOREC2 3 19 4 Related Registers 3 19 4 1 Remote control receive control register RM2CNT 1 The remote control receive control register is an 8 bit register that controls the operation of the remote control receiver circuit Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE27 0000 0000 R W RM2CNT RM2RUN RM2FMT2 RM2FMTI RM2FMTO RM2DINV RM2CK2 RM2CK1 RM2CKO RM2RUN bit 7 REMOREC2 receive control Setting this bit to O stops the operation of the remote control receiver circuit When this bit is set to 1 the remote control receiver circuit starts operation and waits for the remote control input signal RM2FMT2 bit 6 RM2FMT1 bit 5 REMOREC2 receive format select RM2FMTO0 bit 4 Receive format A Guide pulse Half clock Data encoding system PPM Stop bits None Receive format B Guide pulse Clock Data encoding system PPM Stop bits Yes Receive format C Guide pulse None Data encoding system PPM Stop bits Yes Receive format D Guide pulse None Data encoding system Manchester coding Stop bits None Receive format E Guide pulse Clock Data encoding system Manchester coding Stop bits None Any values other than those listed above are inhibited See the subsection entitled Operation of the remote control receiver circuit for the operation of the REMOREC2 in v
177. eration flag RECRUN before this bit is set bit 0 UART1 receive interrupt request enable control 1 When this bit and RECEND are set to 1 an interrupt request to vector address 0033H is generated 3 15 4 2 UART1 control register 1 1 The UARTI control register 1 is an 8 bit register that controls the transmission processing data length and interrupts of and for UARTI Address Initial Value R W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FED1 0000 0000 TRUN 8 9BIT TDDR TCMOS 8 7 TBIT8 TEPTY TRNSIE TRUN bit 7 UART1 transmission control 1 When this bit is set to 1 the UARTI starts a transmit operation 2 This bit is automatically cleared at the end of the transmit operation If this bit is cleared in the middle of a transmit operation the operation is aborted immediately 3 06 LC871A00 Chapter 3 In the continuous transmission mode this bit is cleared at the end of a transmit operation but is automatically set within the same cycle Tcyc Consequently transmit operations occur with intervening 1 Tcyc waits In the continuous transmission mode TRUN will not be set automatically if a bit manipulation instruction NOTI CLRI or SET1 is executed on the UCONI register in the same cycle in which TRUN is to be automatically cleared 8 9BIT bit6 UART1 transmit data length control 1 2 3 When this bit is set to 1 the data length of UARTI
178. ernal RC circuit connected to the P70 INTO TOLCP pin is charged When voltage at this pin reaches the high level a reset or interrupt is generated as specified in the watchdog timer control register WDT To run the program in the normal mode it is necessary to periodically discharge the RC circuit before the voltage at the P70 INTO TOLCP pin reaches the high level clearing the watchdog timer Execute the following instruction to clear the watchdog timer while it is running MOV 55H WDT This instruction turns on the N channel transistor at the P70 INTO TOLCP pin Owing to the pulse stretcher function keeps the transistor on after the MOV instruction is executed the capacitor keeps discharging for a period from a minimum of 1 920 cycle times to a maximum of 2 048 cycle times Detecting a runaway condition Unless the above mentioned instruction is executed the RC circuit keeps charging because the watchdog timer is not cleared As charging proceeds and the voltage at the P70 INTO TOLCP pin reaches the high level the watchdog timer considers that a program hangup has occurred and triggers a reset or interrupt In this case the runaway detection flag WDTFLG is set Only when WDTRST 1 If WDTRST is found to be 1 in this case a reset occurs and execution restarts at address OOOOH If WDTRST is 0 an external interrupt INTO is generated and control is transferred to vector address 0003H e Hints on Use 1 2 To realize ultra
179. errupt flag is set is input to P70 or P71 in the HOLD mode the interrupt flag is set In this case the HOLD mode is released if the corresponding interrupt enable flag is set When a signal change such that the interrupt flag is set is input to P72 in the HOLD mode the interrupt flag is set In this case the HOLD mode is released if the corresponding interrupt enable flag is set The interrupt flag however cannot be set by a rising edge occurring when P72 data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when P72 data which is established when the HOLD mode is entered is in the low state Consequently to release the HOLD mode with P72 it is recommended that P72 be used in the double edge interrupt mode Interrupt Input Input Output Signal Detection Input Release Timer OL Enabled pull up resistor L edge H edge Available Enabled both edges Available Timr0H Note P70 and P71 HOLD mode release is available only when level detection is set N channel open drain L level H level 7 Analog voltage input function P70 and P71 are used to receive the analog voltage inputs to the AD converter 3 5 3 Related Registers 3 5 3 1 Port 7 control register P7 1 The port 7 control register is an 8 bit register for controlling the I O of port 7 data and pull up resistors 2 When this register is read with an instruction data at pins P70 to P7
180. etection control INT5LEG bit 6 INT5 falling edge detection control INT5HEG INT5LEG INT5 Interrupt Conditions Pin Data No edge detection Falling edge detection 0 0 a Rising edge seecion INTSIF bit 5 INT5 interrupt source flag This bit is set when the conditions specified by INTSHEG and INTSLEG are satisfied When this bit and the INT5 interrupt request enable bit INTSIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 001BH are generated The interrupt flag however cannot be set by a rising edge occurring when 5 data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when 5 data which is established when the HOLD mode is entered is in the low state Consequently to release the HOLD mode with INTS it is recommended that INTS be used in the double edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INTSIE bit 4 INT5 interrupt request enable When this bit and INTSIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 001BH are generated INT4HEG bit 3 INT4 rising edge detection control INT4LEG bit 2 INT4 falling edge detection control INTAHEG INTALEG INT4 Interrupt Conditions Pin Data No edge detection Falling edge detection 0 0 Rising ease de
181. f releasing the X tal HOLD mode 1 4 LC871A00 Chapter 1 1 Setting the reset pin to the low level 2 Setting at least one of the INTO INT1 INT2 INT4 and 5 pins to the specified level 3 Having an interrupt source established at port 0 4 Having an interrupt source established in the base timer circuit 5 Having a bus active interrupt source established in the USB interface circuit 6 Having an interrupt source established in the infrared remote control receiver circuit Package form e SQFP48 lead free type Development tools e On chip debugger TCB87 LC87F1A32A 1 5 Pinout 1 3 SQFP48 TOS Id OMOS CId OdS OIS TId OOS 0Id TIO 140 ISSA TINW CLX OINV LLX 5844 5 TA 22 5 CA o o AMS lt lt gt AANA lt lt co N N ST TI OSDO SNV S0d 97 09 1 9 90 C3 LC OI OLLI LNV L0d 87 6 F LNI OCd C43 67 8 0 L SON FOS FLNI CCd TE 9 UM PIS PLNI ETd VMOS SLNI pZd E SLNI SCd vE 9 SE T SINI LZd lt 9 00 ON CI ceo t v S SEE SB GF GF
182. g up the clock SIACNO S4CKPL 1 0 SIACN1 PARA 0 P1 PO 1 4 Setting up ports SIACNI For data transmission from 22 gt P22 P23 1 P240UT 1 P230UT 0 P22MOS 1 P220UT 1 For data transmission from 23 gt e 22 23 0 P240UT 1 P23MOS 1 P230UT 1 P220UT 0 5 Setting the baudrate SABAUD Set the period of the 5104 serial clock internal clock to a value from 4 3 to 1020 3 Tcyc ON Setting the byte count S4BYTH S4BYTE Specify the number of bytes to be transmitted continuously Setting up 5104 data transfer RAM address offset register S4ADDR S4ADRL Load the SIO4 RAM address register with the starting address of the RAM data area to be used for continuous serial data transmission 8 Setting up output data Transfer the number of data bytes specified in step 6 to the RAM area specified in step 7 9 Starting data transfer Set SIARUN SIACNO bit 7 to 1 to start data transfer 10 End of transfer processing When the number of data bytes specified in 6 have been output SIRUN SIACNO bit 7 is automatically cleared SI4END SIACNO bit 1 is set and an interrupt request to vector address 003B H is generated 3 85 5104 Example 2 Receiving data bytes continuously on the external clock 1 Setting up the transmission ports P15 P14 and P13 PIDDR P15DDR 0 P14DDR 0 P13DDR 0 P1 P15 0 P1420 P1320 e S4ADDR S4PTSEL 1 2
183. ggle output 8 bit programmable timer counter with toggle output Mode 1 Two channels of 8 bit PWM with an 8 bit prescaler Mode 2 16 bit programmable timer counter with an 8 bit prescaler with toggle output the lower order 8 bits may be used as a timer counter with toggle output Mode 3 16 bit programmable timer with an 8 bit prescaler with toggle output the lower order 8 bits may be used as a PWM Functions Mode 0 Two channels of 8 bit programmable timer with an 8 bit prescaler with toggle output 8 bit programmable timer counter with toggle output TIL functions as an 8 bit programmable timer counter that counts the number of signals obtained by dividing the cycle clock by 2 or external events while T1H functions as an 8 bit programmable timer that counts the number of signals obtained by dividing the cycle clock by 2 TIPWML and TIPWMH generate a signal that toggles at the interval of TIL and TIH period respectively Note 1 TIL period TILR 1 x TILPRC count x 2 TILR 1 x TILPRC count events detected TIPWML period TIL period x 2 period T1HR 1 x TIHPRC count x 2Tcyc TIPWMH period period x 2 Period of cycle clock Mode 1 Two channels of 8 bit PWM with an 8 bit prescaler Two independent 8 bit PWMs TIPWML and TIPWMH run on the cycle clock TIPWML period 256 x TILPRC count x Tcyc TIPWML low period T1LR 1 x TILPRC count x Tcyc TIPWMH period
184. gister 0 UCONO 1 The UARTI control register O is an 8 bit register that controls the receive operation and interrupts of UARTI Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEDO 0000 0000 UCONO UBRSEL STRDET STPERR UOB3 RBIT8 RECEND UBRSEL bit 7 UART1 baudrate generator period control 1 When this bit is set to 1 the UARTI s legitimate clock rate range is set to 2 When this bit is set to 0 the UARTI s legitimate clock rate range is set to ee to 7 Tcyc 3 95 UART STRDET bit 6 UART1 start bit detection control 1 When this bit is set to 1 the start bit detection falling edge detection function is enabled 2 When this bit is set to 0 the start bit detection falling edge detection function is disabled This bit must be set to 1 to enable the start bit detection function when UART1 is to be used in the continuous receive mode Tf this bit is set to 1 when the receive port P21 is held at the low level RECRUN is automatically set to start UART receive RECRUN bit 5 UART1 start of receive operation flag 1 This bit is set and a receive operation starts if a falling edge of the signal at receive port P21 is detected when the start bit detection function is enabled STRDET 1 2 This bit is automatically cleared at the end of the receive operation clearing this bit during a receive operation will a
185. gister is used to select the frequency of the frequency divided clock that is derived from the USB 48 MHz clock Address Initial Value R W BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE04 0000 0000 R W USBDIV CF480N DVCKON DVCKDR P73NDL 12 UDVSEL2 UDVSELI UDVSELO 4 bit 7 Reserved bit Must always be set to 0 DVCKON bit 6 Frequency divided clock select flag 1 Must be set to 1 to select the frequency divided clock derived from the USB 48 MHz clock as the main clock When the OCR register is configured to select the main clock CLKCB4 set to 1 in this case the frequency divided clock is supplied as the system clock 2 Must be set to 0 to select the CF clock as the main clock 3 When changing the state of this bit make sure that the system clock selection setting of OCR register is set to a value other than main clock CLKCBA 0 DVCKDR bit 5 Frequency divided clock external output control flag 1 Must be set to 1 to generate the frequency divided clock derived from the USB 48 MHz clock from pin P73 The frequency divided clock is transmitted from pin P73 when the P73 output enable bit P7 register bit 7 is set to 1 and the P73 data latch P7 register bit 3 is set to 0 in this case 2 Must be set to 0 to suppress the generation of the frequency divided clock to the external circuitry P73NDL bit 4 Reserved bit Must always be set to 0 CF12BOFF bit 3 Reserved bit Mu
186. gth control 1 See the bit description on 8 9BIT bit 6 TBITS8 bit 2 UART1 transmit data bit 8 storage 1 This bit carries bit 8 of the transmit data when the data length is set to 9 bits 8 9 1 bit 1 UART1 transmit shift register transfer flag D 2 This bit is set when the data transfer from the transmit data register TBUF to the transmit shift register TSFT ends at the beginning of a transmit operation This bit is set in the cycle Tcyc following the one in which the transmit control bit TRUN is set to 1 This bit must be cleared with an instruction When performing continuous mode transmission processing make sure that this bit is set before each loading of the next transmit data into the transmit data register TBUF When this bit is subsequently cleared the transmit control bit TRUN is automatically set at the end of the transmit operation TRNSIE bit 0 UART1 transmit interrupt request enable disable control D An interrupt request to vector address 003BH is generated when this bit and TEPTY are set to 1 3 07 UART 3 15 4 3 UART1 baudrate generator UBR 1 The UARTI baudrate generator is an 8 bit register that defines the baudrate of the UARTI 2 counter for the baudrate generator is initialized when a UARTI serial transmit operation is stopped or terminated RECRUN 0 UCONI TRUN 0 3 Thelegitimate clock rate value can be deter
187. gure 2 4 1 the usable instructions vary depending on the address of RAM The efficiency improvement of use ROM and execution speed can be attempted by using these instructions properly 2 2 FFOOH FEFFH FEOOH FDFFH 2000H 1FFFH 0200H O1FFH 0100H 0000H Reserved for system SFR space 8 bit long Stack space 9 bit long LC871A00 Chapter 2 Note Some registers are 9 bit long Bit instruction direct long Bit instruction direct short Non bit instruction direct long indirect 16 bit operation instruction direct indirect Non bit instruction direct short Fig 2 4 1 RAM Addressing Map When the value of the PC is stored in RAM during the execution of a subroutine call instruction or interrupt assuming that SP represents the current value of the stack pointer the value of BNK and the lower order 8 bits of the 17 bit PC are stored in RAM address SP 1 and the higher order 9 bits in SP 2 after which SP is set to SP 2 2 5 Accumulator A Register ACC A The accumulator ACC also called the register is an 8 bit register that is used for data computation transfer and I O processing It is allocated to address in the internal data memory space and initialized to on a reset Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FE00 0000 0000 R W 2 6 B Register B AREG7 AREG6 AREG5 AREG4 AR
188. hapter 3 Circuit Configuration UART1 control register 0 UCONO 8 bit register The UARTI control register 0 controls the receive operation and interrupts of the UARTI UART1 control register 1 UCON1 8 bit register The UARTI control register 1 controls the transmit operation data length and interrupts of the UARTI UART1 baudrate generator UBR 8 bit reload counter The UART1 baudrate generator is a reload counter for generating internal clocks It can generate clocks at intervals of n 1 x Tcyc 1 1 x Tcyc n 1 to 255 Note 0 is inhibited UART1 transmit data register 8 bit register The UARTI transmit data register is an 8 bit register for storing the data to be transmitted UART1 transmit shift register TSFT 11 bit shift register The UARTI transmit shift register is used to send transmit data via UARTI This register cannot be accessed directly with an instruction It must be accessed through the transmit data register TBUF UART1 receive data register RBUF 8 bit register The UARTI receive data register is an 8 bit register for storing received data UARTI receive shift register RSFT 11 bit shift register The UARTI receive shift register is used to receive serial data via UARTI This register cannot be accessed directly with an instruction It must be accessed through the receive data register RBUF 3 03 UART Data input LSB first Start bit Note The number
189. he following special function registers PWMOL PWMOH PWMIL PWMIH PWMOC PWMOIP Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE20 0000 HHHH R W PWMOL PWMOL3 PWMOL2 PWMOLI PWMOLO e wow ms mw rwv 3 16 3 Circuit Configuration 3 16 31 PWMO PWM control register PWMOC 8 bit register 1 control register controls the operation and interrupts of PWMO and PWMI 3 16 3 2 PWMO compare register L PWMOL 4 bit register 1 PWMO compare register L controls the additional pulses of PWMO 2 PWMOL is assigned bits 7 to 4 and all of its lower order 4 bits are apparently set to 1 when it is read 3 When the PWMO control bit PWMOC FE24 bit 2 is set to 0 the output of PWMO ternary be controlled using bits 7 to 4 of PWMOL 3 16 3 3 PWMO compare register PWMOH 8 bit register 1 ThePWMO compare register H controls the fundamental pulse width of PWMO 2 When bits 7 to 4 of PWMOL are all fixed at 0 PVMO can serve as period programmable 8 bit PWM that is controlled by PWMOH 3 16 3 4 PWM 1 compare register L PWM1L 4 bit register 1 The compare register L controls the additional pulses of PWM1 2 PWMIL is assigned bits 7 to 4 and all of its lower order 4 bits are apparently set to 1 wh
190. igh byte T1H 8 bit counter 1 Start stop The start stop of the timer 1 high byte is controlled by the 0 1 value of TIHRUN timer 1 control register bit 7 2 Countclock T1H prescaler output clock 3 Match signal A match signal is generated when the count value matches the value of the match buffer register 4 Reset The timer 1 high byte is reset when it stops operation or a match signal occurs on the mode 0 2 or 3 condition Ti 3 8 3 7 1 2 3 8 3 8 2 3 8 3 9 1 2 3 3 8 3 10 D 2 3 Timer 1 match data register low byte T1LR 8 bit register with match buffer register This register is used to store the match data for TIL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with that of timer 1 low byte TIL The match buffer register 1s updated as follows TILR and the match register has the same value when in inactive state TILRUN 0 If active TILRUN 1 the match buffer register is loaded with the contents of T1LR when the value of TIL reaches 0 Timer 1 match data register high byte T1HR 8 bit register with a match buffer register This register is used to store the match data for T1H It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with that of timer 1 high byte T1H The match buffer register 1s updated as follows
191. ignal is identified as 0 or 1 When the receive operation is completed the number of last less than 8 bit data bits can be obtained by reading the value of RM2BCT The RM2BCT 1 reset when 1 The remote control receive operation is stopped RM2RUN set to 0 2 RM2FMT2 through RM2FMTO are set to give a value of 0 1 or 4 and a guide pulse is received normally following the initiation or resumption of a receive operation 3 RM2FMT2 through RM2FMTO are set to give a value of 2 or 3 and the first rising edge is detected assuming that the input polarity is set to positive phase following the initiation or resumption of a receive operation 3 Bits 3 to 0 of this register is read only FE2B 0000 0000 R W RM2CTPR RM2GPRI RM2GPRO RM2DPRI RM2DPRO RM2HOLD RM2BCT2 RM2BCTI RM2BCTO RM2GPR1 bit 7 Guide pulse receive mode RM2CKPR count select RM2GPRO bit 6 RM2DPR1 bit 5 RM2DPRO bit 4 Data pulse receive mode RM2CKPR count select When RM2FMT2 through RM2FMTO 0 to 2 is selected RM2GPR1 RM2GPRO RM2DPR1 RM2DPRO RM2CKPR Count Value RM2HOLD bit 3 Receive operation suspend resume flag This bit is set and the REMOREC2 suspends the receive operation at the end of a receive operation Then the REMOREC2 does not perform another receive operation even when a next remote control signal is input This bit is cleared and the REMOREC2 resumes the receive operation when the RM2SFT is read This
192. illator control register PLLCNT 8 bit register 1 The USB dedicated PLL oscillator control register is an 8 bit register that controls the operation of the USB dedicated PLL oscillation circuit Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEOD 0000 0000 R W PLLCNT SELREF2 SELREFI SELREFO PLLTEST VCOSTP CMPSTP ILOWVDEC PONRES SELREF2 bit 7 PLL reference clock frequency select SELREF1 bit 6 PLL reference clock frequency select SELREFO bit 5 PLL reference clock frequency select Theses bits are used to select the frequency of the ceramic oscillator element connected across the CF pins CF1 and CF2 1 4 10 LC871A00 Ceramic Oscillator Frequencies SELREF 2 0 Frequency MHz 000 8 001 9 010 10 011 11 100 12 101 2 110 111 16 PLLTEST bit 4 Test bit for the PLL circuit Must always set to 0 VCOSTP bit 3 PLLVCO operation control flag CMPSTP bit 2 PLL phase comparator operation control flag 1 Must be set to 0 together with VCOSTP and CMPSTP to generate the USB 48 MHz clock from the internal PLL circuit In this case PSDDR FE4DH bit 4 P34DDR and FE4CH bit 4 P34 must be set to 0 In addition it is necessary to connect an external filter circuit to the P34 UFILT pin as shown in Figure 3 18 3 2 Must be set to 1 if the internal PLL circuit 1s not to be used LOWVDEC bit 1 Reserved bit PONRES b
193. ime HOLD 00 to PO7 eInput mode Input output pull up lt P10 to P17 e Pull up resistor controlled by P20 P27 resistor off a program P30 P34 P70 Input mode Input output pull up Input mode Same as in e Pull up resistor controlled by a e Pull up resistor off normal mode resistor off program e N channel output e N channel output transistor for transistor for watchdog timer is watchdog timer off automatic controlled by a on time extension program on time is function reset automatic P71 to P73 Input mode Input output pull up Pull up resistor controlled by resistor off a program 4 17 Standby All modes Reset state entry conditions Low level applied to RES pin Reset Main clock started Subclock stopped RC oscillator started USB dedicated PLL oscillator started All registers initialized Reset signal generated by watchdog timer HOLD mode entry conditions PCON register 07 bit 2 set to 0 and bit 1 to 1 Normal operating mode Start stop of oscillators programmable CPU and peripheral modules run normally HOLD mode All oscillators stopped Since OCR register bits 0 1 4 and 5 are cleared the main clock and RC oscillator are started and RC oscillator is designated as System clock source when HOLD mode is reset CPU and peripheral modules are stopped HALT
194. instruction NOTI CLR1 SETI DBZ DBNZ INC or DEC the contents of the register are referenced instead of the data at port pins 3 Port 2 data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE48 0000 0000 R W P2 P27 P26 P25 P24 P23 P22 P21 P20 3 3 3 2 Port 2 data direction register P2DDR 1 The port 2 data direction register is an 8 bit register that controls the I O direction of port 2 data on a bit basis Port P2n are placed in the output mode when bit P2nDDR is set to 1 and in the input mode when bit P2nDDR is set to 0 2 When bit P2nDDR is set to 0 and the bit P2n of the port 2 data latch is set to 1 port P2n becomes an input with a pull up resistor Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BITO FE49 0000 0000 R W P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Register Data Port P2n State Built in Pull up Input Resistor 0 0 Enabled OFF Buien mem tw 3 3 3 3 External interrupt 4 5 control register 145 1 This register is an 8 bit register for controlling external interrupts 4 and 5 Address Initial Value R W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE4A 0000 0000 R W 145 INTSHEG INTSLEG INTSIF INTSIE INTALEG INTAIF INT4IE INT5HEG bit 7 INT5 rising edge d
195. ion of the built in RC oscillation circuit When a reset occurs or when the HOLD mode is entered this bit is cleared and the built in RC oscillation circuit is enabled for oscillation CFSTOP bit 0 Main clock oscillator control Setting this bit to 1 stops the oscillation of the main clock oscillation circuit 1 2 3 4 2 4 3 1 Setting this bit to 0 starts the oscillation of the main clock oscillation circuit On a reset or when the HOLD mode is entered this bit is cleared and the main clock oscillation circuit is enabled for oscillation XT2 general purpose port output control register XT2PC 8 bit register The XT2 general purpose output control register is an 8 bit register that controls the general purpose output N channel open drain type at the XT2 pin XT2PCB7 XT2PCB2 bits 7 to 2 General purpose flags These bits can be used as general purpose flag bits Any manipulations of these bits exert no influence on the operation of this function block XT2DR bit1 XT2 input output control XT2DT bit 0 XT2 output data Register Data Port XT2 State XT2DT XT2DR Input Output 0 0 Enabled Open 1 0 Enabled Open 0 1 Enabled Low 1 1 Enabled Open Note The XT2 general purpose output port function is disabled when EXTOSC OCR register bit 6 is set to 1 To enable this port as a general purpose output port set EXTOSC to 0 4 2 4 4 USB dedicated PLL osc
196. ircuit and a watchdog timer control register Its configuration diagram 1 shown in Figure 4 5 1 High threshold buffer The high threshold buffer detects the charging voltage of the external capacitor Pulse stretcher circuit The pulse stretcher circuit discharges the external capacitor for longer than the specified time to ensure reliable discharging The stretching time is from 1 920 to 2 048 Tcyc 4 21 Watchdog Timer Watchdog timer control register WDT The watchdog timer control register controls the operation of the watchdog timer R INTO interrupt P70 INTO TOLCP gt Interrupt control circuit Pulse stretcher circuit 7 5 4 2 1 0 WDT FEOF Reset MOV 55H WDT instruction Fig 4 5 1 Watchdog Timer Circuit 4 5 4 Related Registers 1 Watchdog timer control register WDT Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT2 BIT1 BITO FEOF 000 R W WDT WDTFLG WDTBS WDTHLT WDTCLR WDTRST WDTRUN Bit Name Function WDTFLG bit 7 Runaway detection flag 0 No runaway 1 runaway WDTBS bit 5 General purpose flag Can be used as a general purpose flag WDTHLT bit 4 HALT HOLD mode function control 0 Enables the watchdog timer 1 Disables the watchdog timer WDTCLR bit 2 Watchdog timer clear control 0 Disables the watchdog timer for clearing 1 Enables the watchdog timer for clearing WDTRUN bit 0 Watchdog timer
197. is bit must be set to 0 to perform normal USB communication DDRDM bit 2 D pin general purpose output control 1 115 bit is set to 1 PORTDM data is generated of the D pin 2 This bit must be set to 0 to perform normal USB communication PORTDP bit 1 D port data latch 1 PORTDP data is generated from the D pin when DDRDP is set to 1 2 Reading this bit with an instruction causes the data at the D pin to be read in If USPORT is manipulated using a NOTI CLR1 SETI DBZ DBNZ INC or DEC instruction however not the data at the D pin but the register contents are referenced PORTDM bit 0 D port data latch 1 PORTDP data is generated from the D pin when DDRDM is set to 1 2 Reading this bit with an instruction causes the data at the D pin to be read in If USPORT is manipulated using a NOTI CLR1 SETI DBZ DBNZ INC or DEC instruction however not the data at the D pin but the register contents are referenced 3 18 4 5 USB interrupt control register USBINT 1 USB interrupt control register controls USB interrupts Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE82 00000000 USBINT BRSFG BRSEN BACFG BACEN SOFFG SOFEN USBINTI BRSFG bit 7 Bus reset detect flag 1 This flag is set when a USB bus reset state SEO state continuing for 2 5 s or longer is detected 2 Thebit remains set until the bus reset state is released 3 This
198. is set to 9 bits When this bit is set to 0 and 8 7BIT bit 3 is set to 0 the data length of UARTI is set to 8 bits When this bit is set to 0 and 8 7BIT bit 3 is set to 1 the data length of UARTI is set to 7 bits The UARTI will not run normally if the data length is changed in the middle of a transmit operation Be sure to manipulate this bit after confirming the completion of a transmit operation The same data length is used when both transmission and receive operations are to be performed at the same time 8 9 BIT 8 7 BIT Data Length in bits 0 0 8 0 1 7 1 X 9 TDDR bit 5 UART1 transmit port output control D 2 When this bit is set to 1 the transmit data is placed at the transmit port P20 No transmit data is generated if bit 0 of P2DDR at FE49 is set to 1 When this bit is set to 0 no transmit data is placed at the transmit port P20 The transmit port is placed in the HIGH open CMOS N channel open drain mode if this bit is set to 1 when the UARTI has stopped a transmit operation TRUN 0 This bit must always be set to 0 when the UARTI transmission function is not to be used TCMOS bit 4 UART1 transmit port output type control D 2 When this bit is set to 1 the output type of the transmit port P20 is set to CMOS When this bit is set to 0 the output type of the transmit port P20 is set to N channel open drain 8 7BIT bit3 UART1 transmit data len
199. it 0 Reserved bit 4 2 4 5 USB frequency divided clock control register USBDIV 8 bit register 1 The USB frequency divided clock control register is used to select the frequency of the frequency divided clock that is derived from the USB 48 MHz clock Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE04 0000 0000 R W USBDIV CF480N DVCKON DVCKDR P73NDL 12 UDVSEL2 UDVSELI UDVSELO 4 bit 7 Reserved bit Must always be set to 0 DVCKON bit 6 Frequency divided clock select flag 1 Must be set to 1 to select the frequency divided clock derived from the USB 48 MHz clock as the main clock When the OCR register is configured to select the main clock CLKCBA set to 1 in this case the frequency divided clock 1 supplied as the system clock 2 Must be set to 0 to select the CF clock as the main clock 3 When changing the state of this flag make sure that the OCR register s system clock select bit is set to a setting other than main clock CLKCBA set to 0 DVCKDR bit 5 Frequency divided clock external output control flag 1 Must be set to 1 to generate the frequency divided clock derived from the USB 48 MHz clock from pin P73 The frequency divided clock is transmitted from pin P73 when the P73 output enable bit P7 register bit 7 is set to 1 and the P73 data latch P7 register bit 3 is set to 0 in this case 2 Must be set to 0 to suppress the generation of the frequenc
200. its Pull up resistors can be turned on and off in 1 bit units Pin functions P34 USB interface PLL filter circuit pin On chip debugger pins DBGPO to DBGP2 P30 to P32 P30 to P34 4 bit I O port P70 to P73 specifiable in 1 bit units 222 Pull up resistors can be turned on and off in 1 bit units Pin functions P70 INTO input HOLD release input timer OL capture input watchdog timer output D 1 5k pull up resistor pin P71 INTI input HOLD release input timer OH capture input P72 INT2 input HOLD release input timer 0 event input timer OL capture input high speed clock counter input P73 INT3 input with noise filter timer 0 event input timer OH capture input infrared remote control receiver input AD converter input port pins AN8 P70 AN9 P71 Interrupt acknowledge type re t Y Y N Y Y Y Y N Y Y Y Y Y N N Y Y Y N N PWMO output ports General purpose input port USB data I O pin D general purpose I O port USB data I O pin D general purpose I O port Reset pin 32 768 kHz crystal oscillator input pin Pin functions General purpose input port AD converter input port AN10 Must be connected to VDDI if not to be used 32 768 kHz crystal oscillator output pin Pin functions General purpose input port AD converter input port AN11 Must be set to oscillation specification and kept open if not to be used Ceramic oscillator input pin Output Ceramic oscillator output pin
201. its do not exist 1 is always read when these bits are read CLKDV2 bit 2 CLKDV1 bit 1 Define the division ratio of the system clock CLKDVO bit 0 CLKDV2 CLKDV1 CLKDVO Division Ratio 5 1 pom dox cq Jt 5 WS _ ow 16 4 5 4 12 LC871A00 4 3 Standby Function 4 3 1 Overview This series of microcontrollers supports three standby modes called the HALT HOLD and X tal HOLD modes that are used to reduce current consumption at power failure time or in program standby mode In a standby mode the execution of all instructions is suspended 4 3 2 Functions 1 HALT mode The microcontroller suspends the execution of instructions but its peripheral circuits continue processing The HALT mode is entered by setting bit 0 of the PCON register to 1 when bit 1 is set to 0 Bit 0 of the PCON register is cleared and the microcontroller returns to the normal operating mode when a reset occurs or an interrupt request is accepted 2 HOLD mode All oscillations are suspended The microcontroller suspends the execution of instructions and its peripheral circuits stop processing The HOLD mode is entered by setting bit 1 of the PCON register to 1 when bit 2 is set to 0 In this case bit 0 of the PCON register HALT mode flag is automatically set When a reset occurs or a HOLD mode resetting signal INTO INT1 INT2 INT4 INTS POINT
202. iven in the paragraph entitled How to calculate 7 8 9 the conversion time is taken in the second and subsequent conversions or in the AD conversions that are carried out in the 8 bit AD conversion mode The conversion results data contains some errors quantization error combination error Be sure to use only valid conversion results while referring to the latest Semiconductor News bulletin Make sure that only input voltages that fall within the specified range are supplied to pins P00 ANO to PO7 AN7 and pins P70 AN8 and P71 AN9 XTI ANIO XT2 A11 Application of a voltage greater than VDD or lower than VSS to an input pin may exert adverse influences on the converted value of the channel in question or other channels Take the following measures to prevent reduction in conversion accuracy due to noise interferences Add external bypass capacitors of several to 1000 pF near the VDD1 and VSS1 pins as close as possible 5 mm or less is desirable Add an appropriate external low pass filter RC which is appropriated to reject noise interferences or capacitors close to each analog input pin To preclude adverse coupling influences use a ground that is free of noise interferences as a guideline R approx 5kQ or less 1000 pF to 0 1 u Do not lay analog signal lines close to in parallel with or in a crossed arrangement with digital pulse signal lines or signal lines in which large current changes
203. l is rejected as noise and the REMOREC continues operation while preserving the state of the old signal in the circuit Noise cancellation width Less than RM2CKx4 Note The noise cancellation width may vary by a maximum factor of RM2CKxl depending on the timing at which the remote control input signal is sampled in the circuit Input polarity control bit RM2DINV Receive Input P73 RMIN polarity Noise filter Edge operation control selector RM2NFLT detect creuit Guide data pulse select signal Reset or start Receive format select bit signal generator RM2FMT2 0 Reset or start signal Base clock select bit 2 2 0 Subclock source oscillator Pulse counter RM2GPOK set signal D 1 RM2MJCT RM2DERR set signal divider RM2REND set signal Prescaler D RM2CKPR Count clock Guide pulse test data Storage direction control bit RM2RDIR Receive format select bit RM2GPHn RM2FMT2 0 RM2GPLn Receive shift Receive data Guide data pulse select signal Data pulse register register RM2SFT RM2RDT test data RM2DOHn Guide pulse Data pulse RM2DOLn match data match data RM2D1Hn RM2GPRn RM2DPRn RM2D1Ln Z Transferred on each reception of 8 bits of data Receive bit D counter RM2BCT RM2SFUL set signal Figure 3 19 1 Infrared Remote Control Receiv
204. l register SWCONO 8 bit register The continuous data transfer control register controls the suspension and resumption of serial transmission in byte units in the continuous data transmission reception mode It allows the application program to read the number of bytes transmitted in the continuous data transmission reception mode 3 57 Data input 8 bit shift register Data LSB first output 1 5100 output control P10 Bele noe e Clock 1 P10 output control 1 lt MSB first SBUFO FE31h 5100 output control P11 P11 port latch P11 output control Clock generation circuit MSB LSB first control P12 port latch P12 output control Baud rate generator Serial transfer end flag SBRO FE32h 6100 overrun flag SCONO FE30h Interrupt request Figure 3 11 1 100 Synchronous 8 bit Serial I O Block Diagram SIOCTR 0 3 58 LC871A00 Chapter 3 Data input 8 bit shift reaister LSB first ________ D SCTRO FE33h gt 1 1 Clock MSB 1 SIOO output control P10 SBUFO FE31h P10 port latch P10 output control at the end of 8 bit data transmission Number of 100 output control P11 P11 port latch P11 output control SWCONO FE37h Clock generation circuit 100 output contro 12 MSB LSB first control P12 port lat
205. llocated see Appendixes 1 Fig 2 1 1 Types of Memory Space 2 2 Program Counter PC The program counter PC is made up of 17 bits and a bank flag BNK The value of BNK determines the bank The lower order 17 bits of the PC allows linear access to the 128K ROM space in the current bank Normally the PC advances automatically in the current bank on each execution of an instruction Bank switching is accomplished by executing a Return instruction after pushing necessary addresses onto the stack When executing a branch or subroutine instruction when accepting an interrupt or when a reset is generated the value corresponding to each operation is loaded into the PC Table 2 2 1 lists the values that are loaded into the PC when the respective operations are performed 2 1 Table 2 2 1 Values Loaded the PC Operation PC value BNK value 00000H INTO 00003H INTI 0000BH INT2 TOL INTA USB bus active Remote controller 00013H reception emu 9 oosa o SIOVUSBemdpenwUSESOFSIONUARTIWamwi wmm o mma mamma 2 800 instructions BZW BNZW BP BN nb of i instruction Call instructions 7 Unchanged Return instructions RET RETI PC16 to 08 SP BNK is set PC07 to 00 SP 1 to bit 8 of SP denotes the contents of RAM SP 1 address designated by the value of the stack pointer SP Standard instructio
206. mal operating mode Active Active Active Inactive voltage circuit HOLD mode Active Inactive Inactive Inactive operation HALT mode Active Inactive Active Inactive 1 2 3 4 The USB port output reference voltage will be the same voltage level as the one at VDD1 if the reference voltage generator circuit is stopped The option settings 2 and 3 must be used to stop the reference voltage generator circuit in the HALT and HOLD modes respectively The power dissipation consumed when the reference voltage generator circuit is active is increased by 100A than the one that is consumed when it is held inactive LC871A00 Chapter 2 2 Internal Configuration 2 1 Memory Space The LC870000 series microcontrollers have the following three types of memory space 1 Program memory space 256K bytes 128K bytes x 2 banks 2 Internal data memory space 64K bytes 0000H to FDFFH out of 0000H to FFFFH is shared with the stack area 3 External data memory space 16M bytes External data memory Address Space Program memory Address space FFFFFFH 3FFFFH 1 Internal data Address i RAM ROM bank 1 FFFFH 16 1 1 FFOOH eserved for FEFFH 1 1FFFFH i SFR 8 bit some 9 bit 1 1 FDFFH bey RAM Stack 64 9 bit config 00000H 0000H 000000H Note SFR is the area in which special registers such as the accumulator are a
207. mber when SOF data is received Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE8A 0000 0000 7 FRM06 FRM05 4 FRMO3 FRMO2 1 FRAMEH FRMIO FRMOS 3 18 4 12 USB address register USBADR 1 The USB address register stores the address of the USB device Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE8C 00000000 USBADR ADREN ADDR6 ADDRS ADDR4 ADDR3 ADDR2 ADDRI ADDRO ADREN bit 7 Device address enable flag 1 A 1 in this bit enables ADDR 6 0 Of the tokens sent from the host only the tokens whose device address matches the contents of ADDR 6 0 are processed 2 0 in this bit disables ADDR 6 0 Of the tokens sent from the host only the tokens whose device address is 0 are processed 3 131 USB ADDRS6 bit 6 Device address ADDR5 bit 5 Device address ADDRA bit 4 Device address ADDR3 bit 3 Device address ADDR2 bit 2 Device address ADDR bit 1 Device address ADDRO bit 0 Device address 1 These bits designate the device address assigned by the host 3 18 4 13 Endpoint information register EPINFO The endpoint information register contains information about the endpoint number and token type Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT2 BIT1 BITO FE8D 0000 0000 R EPINFO E
208. me BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE16 XXXX XXXX R TOCAL TOCAL7 TOCAL6 TOCALS TOCAL4 TOCAL3 TOCAL2 TOCALO 3 6 48 Timer counter 0 capture register high byte TOCAH 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 high byte TOH on an external input detection signal Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEI7 XXXX XXXX R TOCAH TOCAH7 TOCAH6 5 TOCAH3 TOCAH2 TOCAHI TOCAHO 3 31 3 7 High speed Clock Counter 3 7 1 Overview The high speed clock counter is a 3 bit counter that is provided with a realtime output capability It is coupled with timer counter 0 to form a 11 or 19 bit high speed counter It can accept clocks with periods of as short as the cycle time The high speed clock counter is also equipped with 4 bit capture register incorporating a carry bit 3 7 2 Functions 1 11 bit or 19 bit programmable high speed counter The 11 bit or 19 bit timer counter in conjunction with the timer counter 0 low byte TOL and timer counter 0 high byte TOH functions as a 11 or 19 bit programmable high speed counter that counts up the external input signals from the P72 INT2 TOIN NKIN pin The coupled timer counter 0 counts the number of overflows occurring in the 3 bit counter In this case timer 0 functions as a free running counter 2
209. mined by the value of UBRSEL UBRSEL TUBR1 Value Range 0 UBR value 1 x 8 8 10 Tcyc 1 UBR value 1 x to Tcyc Do not change the baudrate in the middle of UARTI serial transmission processing The UARTI will not function normally if the baudrate is changed during UARTI serial transmission processing Always make sure that the UARTI has finished serial transmission processing before changing the baudrate The same baudrate is used when both transmit and receive operations are to be performed at the same time this holds also true when the transmit and receive operations are to be performed in the continuous transmission mode Setting UBR to 00 H is inhibited Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FED2 0000 0000 R W UBR UBRG7 UBRG6 UBRGS UBRG4 UBRG3 UBRG2 UBRGI UBRGO 3 15 4 4 UARTI1 transmit data register 1 UARTI transmit data register is an 8 bit register that stores the data to be transmitted through the UARTI 2 Data the is transferred to the transmit shift register TSFT at the beginning of a transmit operation Load the next data after checking the transmit shift register transfer flag UCONI TEPTY Bit 8 of the transmit data must be loaded into the transmit data bit 8 storage bit UCONI TBITS Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO F
210. mode All oscillators retain the state established when the HALT mode is entered CPU stopped Peripheral Reset state cancellation conditions Lapse of predetermined time after resetting conditions are set X tal HOLD mode entry conditions PCON register FEO7 bit 2 set to 1 and bit 1 to 1 HOLD Main clock and RC and USB dedicated PLL oscillators stopped Subclock retains the state established when X tal HOLD mode is entered Contents of OCR register remain unchanged Contents of PLLCNT and USBDIV registers remain unchanged CPU enters this mode after selecting subclock or RC oscillator clock as system clock and stopping main clock CPU and all peripheral modules except base timer stop operation and base timer retains the state HOLD mode resetting conditions modules keep running established when X tal HOLD INTO or INT1 level interrupt request generated Request for INT2 INT4 INT5 USB bus active or port 0 interrupt generated Resetting conditions established Note 1 HALT mode entry conditions mode is entered When X tal HOLD mode is exited the oscillators return to the state established when the mode is entered X tal HOLD mode resetting PCON register 07 bit 1 set to 0 and bit 0 to 1 conditions HALT mode resetting conditions d 22 inte
211. n 3 Tcyc nz 1 to 255 Note that 0 is inhibited Transmits and receives 1 to 2 048 bytes of data automatically and continuously Transmit data is automatically transferred from RAM to a shift register SIABUF while receive data is automatically transferred from the shift register SIBUF to RAM The RAM area to be used for continuous transmission and reception can be allocated to any addresses in 1 byte units When the internal clock is used suspension and resumption of continuous mode data transfer can be controlled in 1 or 2 byte units Datacan be transferred either on an MSB or LSB first basis 16 bit CRC code calculation can be performed on serial transfer data Related ports Either port pin group P22 to P24 or P13 to P15 can be selected for serial communication Port Pin Name Function P22 P13 IO 04 Serial input output pin P23 P14 IO 514 Serial input output pin P24 P15 IO SCK4 Synchronous clock input output pin 2 Interrupt generation An interrupt request is generated at the end of transfer when the interrupt request enable bit is set 3 control serial interface 4 5104 it is necessary to manipulate the following special function registers e S4ADRL 54 CRCL CRCH CRCCNT SI4CNO SI4CN1 SI4BUF SABAUD S4ADDR S4BYTE PI PIDDR P2 P2DDR 3 76 LC871A00 Chapter 3 Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO
212. n erroneous count from the base timer When entering the hold mode therefore it is recommended that the base timer be stopped This series of microcontrollers supports the X tal HOLD mode that enables low current intermittent operation In this mode only the base timer is allowed for operation 3 10 4 2 Input signal select register ISL 1 This register is an 8 bit register that controls the timer 0 input noise filter time constant buzzer output and base timer clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESF 0000 0000 R W ISL STOHCP STOLCP BTIMCI BTIMCO BUZON NFSEL NFON STOIN STOHCP bit 7 Timer capture signal input port select STOLCP bit 6 Timer OL capture signal input port select These 2 bits have nothing to do with the control function on the base timer bit 5 Base timer clock select BTIMCO bit 4 Base timer clock select BTIMC1 BTIMCO Base Timer Input Clock 0 0 Subclock 1 __ 0 Subclock Timer counter 0 prescaler output BUZON bit 3 Buzzer output select This bit enables the buzzer output 1851 When set to 1 a signal that is obtained by dividing the base timer clock by 16 is sent to port P17 as buzzer output When this bit is set to 0 the buzzer output becomes fixed high fBST Is the period of the input clock to the base timer that is selected by the input signal select register ISL bits
213. nary up counter can be constructed using an 8 bit binary up counter and a 6 bit binary up counter These counters can be cleared under program control High speed mode when used as a 6 bit base timer When the base timer is used as a 6 bit timer it can clock at intervals of approximately 2 ms if the 32 768 kHz subclock is used as the count clock The bit length of the base timer can be specified using the base timer control register BTCR Buzzer output function The base timer can generate 2kHz beeps when the 32 768 kHz subclock is used as the count clock The buzzer output can be controlled using the input signal select register ISL The buzzer output is ANDed with the PWMH output from timer 1 and can be transmitted via pin P17 Interrupt generation An interrupt request to vector address 001BH is generated if an interrupt request is generated by the base timer when the interrupt request enable bit is set The base timer can generate two types of interrupt requests base timer interrupt 0 and base timer interrupt 1 HOLD mode operation and HOLD mode resetting The base timer is enabled for operation in the HOLD mode when bit 2 of the power control register PCON is set The HOLD mode can be reset by an interrupt from the base timer This function allows the microcontroller to perform low current intermittent operations To control the base timer it is necessary to manipulate the following special function registers BTCR ISL
214. ndamental wave period is represented by 8 bit PWM PWM compare register PWMH 4 bits are used to designate the fundamental wave period to which additional pulses are to be added PWM compare match register L PWML 12 bit register structure gt PWMH PWML XXXX XXXX XXXX 12BIT How pulses are added to the fundamental wave periods Example 1 PWM compare register H PWMH 00 H PWM compare register L PWML Oto F H Overall period l Fundamental Fundamental Fundamental Fundamental Fundamental Fundamental wave period wave period 1 wave period 2 wave period 13 wave period 14 wave period 15 Fundamental period 0 1 2 3 3 4 signal PWMH PWML 000 PWMH PWML 001 PWMH PWML 002 PWMH PWML 003 PWMH PWML 004 PWMH PWML 005 PWMH PWML 006 PWMH PWML 007 PWMH PWML 008 PWMH PWML 009 PWMH PWML 00A PWMH PWML 00B PWMH PWML 00C PWMH PWML 00D PWMH PWML 00E O MR ME IA a ANR ix Ns Wu UN EE E i MEE PWML 00F LL IL JL JL 3 106 Overall period LC871A00 Chapter 3 How pulses are added to fundamental wave periods PWM compare register PWMH 01 PWM compare register L PWML Oto H Fundamental wave period wave period 1 wave period 2 Fundamental Fundamental Fundamental wave period 13 wave
215. nes the lowest order 8 bits of the start address of the RAM area to be used for data transfer Address Initial Value R W Name BIT7 BIT6 BITS BIT4 2 BIT1 BITO FED6 0000 0000 R W S4ADRL S4ADL7 SAADL6 S4ADLS S4ADL4 S4ADL3 S4ADL2 S4ADL1 S4ADLO 3 13 4 8 04 RAM address register high byte S4ADDR 1 The S4ADRL register is used to control the suspension of continuous data transfer processing 2 Theregister is also used to select the ports for serial communication 3 The SAADRL register defines the highest order 6 bits of the start address of the RAM area to be used for data transfer Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO i FEDF 0000 0000 S4ADDR SAWSTP SAPTSEL S4ADR5 S4ADR4 S4ADR3 S4ADR2 S4ADRI S4ADRO SAWSTP bit 7 Continuous data transfer mode suspension control flag 1 Disables automatic data transfer between the RAM and shift register Continuous data transfer processing is suspended when the current transfer of the data to or from the shift register is finished If S4STPWD S4BYTH bit 7 is set to 1 however data transfer processing is suspended after the transfer of an even byte data is finished Control of data transfer cannot be exercised when the SIO4 is running on an external clock 0 The suspension mode is canceled SAPTSEL bit 6 Serial communication port select Pin Name S4PTSEL 0 S4
216. ng of the X level interrupt This bit is read only No instruction can rewrite the value of this bit directly HFLG bit 5 H level interrupt flag R O This bit is set when an H level interrupt 15 accepted and reset when execution returns from the processing of the H level interrupt This bit is read only No instruction can rewrite the value of this bit directly LFLG bit 4 L level interrupt flag R O This bit is set when an L level interrupt is accepted and reset when execution returns from the processing of the L level interrupt This bit is read only No instruction can rewrite the value of this bit directly Bits 3 2 These bits do not exist They are always read as 1 XCNT1 bit 1 0000BH Interrupt level control flag e A 1 in this bit sets all interrupts to vector address 0000BH to the L level e 0 in this bit sets all interrupts to vector address 0000BH to the X level XCNTO bit 0 00003H Interrupt level control flag e A in this bit sets all interrupts to vector address 00003H to the L level e this bit sets all interrupts to vector address 00003H to the X level 4 3 Interrupt 4 1 4 2 Interrupt priority control register IP 1 The interrupt priority control register is 8 bit register that selects the interrupt level H L of interrupts to vector addresses 00013H to 0004BH Address Initial value R W Name BIT7 6 5 4 2 BITO FE09 00000
217. nge is from 00 H to 40 H Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE9E H000 0000 R W EPACNT E4CN6 EACNS E4CN4 E4CN3 E4CN2 E4CNI E4CNO 3 18 4 29 EP4 receive data count register EP4RX 1 receive data count register indicates the number of data bytes received at endpoint 4 2 The contents of this register are updated when an OUT transaction for endpoint 4 terminates normally with an ACK 000000 rw EP4RX 5 3 18 4 30 Test register 0 TESTRO 1 TESTROis a test register Address Initial Value Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FEAC 00000000 R W TESTRO DPLTST CMPTST CMPKIL TTXCLK TTXREQ TADR2 TADRI P71NDL DPLTST bit 7 Test bit Must always be set to 0 CMPTST bit 6 Test bit Must always be set to 0 CMPKIL bit 5 Test bit Must always be set to 0 TTXCLK bit 4 Test bit Must always be set to 0 TTXREQ bit 3 Test bit Must always be set to 0 TADR2 bit 2 Test bit Must always be set to 0 TADR bit 1 Test bit Must always be set to O P71NDL bit 0 Test bit Must always be set to 0 3 139 USB 3 18 4 31 Test register 1 TESTR1 1 TESTRI is a test register Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEAD 0000 0000 TESTRI TDAT7 TDAT6 TDATS TDAT4 TDA
218. ns a 12 bit 12 channel AD converter with 12 8 bit resolution selector two channels of 12 bit PWMs a system clock divider an infrared remote control receiver function and a 28 source 10 vector address interrupt feature 1 2 Features Flash ROM Onboard programmable over a wide power voltage range of 3 0V to 5 5V Erasable in 128 byte block increments Write operation in 2 byte units 32768 x 8 bits RAM 2048 x 9 bits Bus cycle time 83 3 ns when 12 MHz Note The bus cycle time here refers to the ROM read speed e Minimum instruction cycle time Tcyc 250 ns when 12 MHz e Ports I O ports Ports whose I O direction can be designated in 1 bit units 28 P10 to P17 P20 to P27 P30 to P34 P70 to P73 PWMI XT2 Ports whose I O direction can be designated in 4 bit units 8 to P07 USB ports 2 D Dedicated oscillation ports 2 CF1 CF2 Input only ports can also be used for oscillation 2 XT1 Reset pin 1 RES Power pins 6 VSSI to VSS3 VDDI to VDD3 1 1 Timers Timer 0 16 bit timer counter with a capture register Mode 0 8 bit timer with an 8 bit programmable prescaler with an 8 bit capture register x 2 channels Mode 1 8 bit timer with an 8 bit programmable prescaler with an 8 bit capture register 8 bit counter with an 8 bit capture register Mode 2 16 bit timer with an 8 bit programmable prescaler with a 16 bit capture register
219. ns NOP MOV ADD PC PC nb Unchanged nb Number of instruction bytes 2 3 Program Memory ROM The LC870000 series microcontrollers have a program memory space of 256K bytes but the size of the ROM that is actually incorporated in the microcontroller varies with the CPU type of the microcontroller The ROM table lookup instruction LDC can be used to reference all ROM data within the bank Of the ROM space the 256 bytes in ROM bank 0 1FFOOH 1FFFFH for ROM sizes of 64K and above and OFFOOH OFFFFH for ROM sizes of 64K and below is reserved as the option area Consequently this area is not available as a program area 2 4 Internal Data Memory RAM The LC870000 series microcontrollers have an internal data memory space of 64K bytes but the size of the RAM that is actually incorporated in the microcontroller varies with the series of the microcontroller 9 bits are used to access addresses 0000 to FDFFH of the 128K ROM space and 8 or 9 bits are used to access addresses to FFFFH The 9th bit of RAM is implemented by bit 1 of the PSW and can be read and written The 128 bytes of RAM from 0000H to 007FH are paired to form 64 2 byte and can also be used as 64 indirect address registers The bit length of these indirect registers is normally 16 bits 8 bits x 2 When they are used by the ROM table lookup instruction LDC however their bit length is set to 17 bits 9 higher order bits 8 lower order bits As shown in Fi
220. nsaction terminates with an error See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction ER2EN bit 2 EP2 error interrupt request enable flag 1 interrupt to vector address 003BH is generated when this bit ER2FG and ENPEN are all set to 1 ST2FG bit 1 EP2 stall end flag 1 Set to 1 when the endpoint 2 transaction terminates with a stall See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction ST2EN bit 0 EP2 stall interrupt request enable flag 1 interrupt to vector address 003BH is generated when this bit ST2FG and ENPEN are all set to 1 3 129 USB 3 18 4 9 interrupt control register EP3INT 1 EP3 interrupt control register controls endpoint 3 interrupts Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT2 BIT1 BITO FE86 0000 0000 R W EP3INT AK3FG AK3EN NK3FG NK3EN ER3FG ER3EN ST3FG ST3EN AK3FG bit 7 EP3 ACK end flag 1 Set to 1 when the endpoint 3 transaction terminates normally with an ACK See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction AK3EN bit 6 EP3 ACK interrupt request enable flag 1 interrupt to vector address 003BH is generated when this bit AK3FG ENPEN are all set to 1 NK3FG bit 5 EP3 end flag 1 Set to when the endpoint 3 transaction terminates with
221. nssasusasssasusasssasusasuen 3 6 3 2 4 Options 3 9 3 2 5 HALT and HOLD Mode Operation 3 9 Port 2 3 1 0 3 3 1 3 10 3 3 2 Functions shsssususnsusnsuunsuunassnansnassnansnanunanunanunanunanssanusanusanusanusanusanusanusanusasusasusae 3 10 3 3 3 Related Registers 3 1 1 3 3 4 Options 3 14 3 3 5 HALT and HOLD Mode Operation
222. nterface transmits a data packet for an IN transaction and an handshake for an OUT transaction 2 If this bit is set to 0 the USB interface returns handshake for IN and OUT transactions 3 See Table 3 18 11 EOCSU bit 2 EPO complete setup stage flag 1 This bit is automatically set to 1 when a SETUP transaction terminates normally with an ACK 2 This bit is automatically cleared to 0 when an IN transaction in the status stage terminates normally with an ACK 3 See Table 3 18 11 EOCST bit 1 EPO status stage flag 1 Alinthis bit indicates that the USB interface 15 in the control transfer status stage 2 This bit is automatically cleared to 0 when a SETUP transaction terminates normally with an ACK 3 This bit is automatically set to 1 when an OUT transaction in the status stage terminates normally with an ACK 4 See Table 3 18 11 EOCRW bit 0 EPO transfer direction flag 1 Alinthis bit identifies a control read transfer 2 A 0 in this bit identifies a control write transfer 3 This bit is automatically cleared to 0 when a SETUP transaction terminates normally with an ACK 4 See Table 3 18 11 3 18 4 15 EPO maximum payload register EPOMP 1 EPO maximum payload register defines the maximum payload size of endpoint 0 2 legitimate values are 08 H 10 H 20 H and 40 H Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE8F 000 0000 R W EPO
223. nterrupt Read SBUFI Return to step 8 to continue reception of data Go to in step 10 to terminate processing At this moment SBUFI bit 8 data has already been presented as acknowledge data and the clock for the master side has been released Terminating communication Manipulate the clock output port PISFCR 0 PISDDR 1 P15 0 and set the clock output to 0 Manipulate the data output port P14FCR 0 P14DDR 1 P14 0 and set the data output to 0 Restore the clock output port into the original state PISFCR 1 PISDDR 1 P15 0 and release the clock output Wait for all slaves to release the clock and the clock to be set to 1 Allow for a data setup time then manipulate the data output port P14FCR 0 P14DDR 1 P14 1 and set the data output to 1 In this case the 5101 overrun flag SILOVR SCONI FE24 bit 2 is set but this will exert no influence on the operation of 5101 Restore the data output port into the original state set P14FCR to 1 then PIADDR to 1 and P14 to 0 Clear and 5 then exit interrupt processing Return to step 4 to repeat processing Bus slave mode mode 3 Setting the clock Set up SBRI to set the acknowledge data setup time Setting the transmission mode Set as follows SIIMO 1 SI1M1 1 SIIDIR 1 0 Setting up ports Designate the clock and data ports as N channel open drain output ports 3 72 4 5 7 LC871A00 Chapter 3 S
224. o 2 or 3 4 A RM2SFT to RM2RDT data transfer occurs Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE29 0000 0000 R RM2SFT RM2SFT7 RM2SFT6 RM2SFTS RM2SFT4 RM2SFT3 RM2SFT2 RM2SFTI RM2SFTO Note Before reading this register make sure that the value of RM2REND is set to 1 End of reception 3 19 4 4 Remote control receive data register RM2RDT 1 The remote control receive data register is an 8 bit register that holds the data received from the remote control 2 The initial value of this register is unpredictable Each received data block of 8 bits is transferred from RM2SFT to RM2RDT Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE2A XXXX XXXX R RM2RDT RM2RDT7 RM2RDT6 RM2RDT5 RM2RDT4 RM2RDT3 RM2RDT2 RM2RDTI RM2RDTO Note Before reading this register make sure that the value of RM2SFUL is set to 1 Data transfer detected 3 152 LC871A00 Chapter 3 3 19 4 5 Remote control receive bit counter amp prescaler setup register RM2CTPR 1 This register consists of a 3 bit up counter RM2BCT that counts the number of data bits received from the remote control a flag RM2HOLD that signals the suspension and resumption of the next receive operation and the bits that defines the count value RM2GPRI1 0 RM2DPRI1 0 of RM2CKPR in the guide pulse or data pulse receive mode 2 RM2BCT starts counting up when the remote control input s
225. of the PLL reference clock the oscillator element connected across the CF pins USB frequency divided clock control register USBDIV 8 bit register The USB frequency divided clock control register is used to select the frequency out of 4 4 8 6 8 12 and 16 MHz that is obtained by dividing the 48 MHz clock for the USB It is also used to select either CF or USB frequency divided clock as the main clock System clock division control register CLKDIV 3 bit register 1 The system clock division control register controls the operation of the system clock divider circuit 1 1 1 1 1 1 at al 1 1 The division ratios of gt gt and are allowed 1 2 4 8 16 32 64 128 4 7 System Clock DVCKON CLKCBS 4 UDVSEL 2 CLKSGL CLKDV CF clock CFSTOP CF oscillator 5 Main clock Frequency 8 i 3 divided m System clock clock SCLK VCOSTP PLL oscillator gt CMPSTP 3 50 SELREF gt 8 CF oscillator frequency selected 48MHZ To USB 2 AC RC clock RCSTOP gt oscillator fSCLK System clock frequency To base timer fCYC Cycle clock frequency Minimum instruction cycle Agee Subclock Subclock oscillator fCYC fSCLK 3 Fig 4 1 System Clock Generator Block Diagram 4 2 4 Related Registers 4 2 4 1 Power Control Register PCON 3 bit register 1 The power control register is 3 bit register used to specify the operating mode normal HALT
226. oints including the control endpoint The endpoint buffer for data transmission and reception 64 bytes maximum is mapped into RAM The USB data sampling clock 48 MHz can be derived from a clock that is generated by the internal PLL circuit 2 Interrupt generation An interrupt is generated at the end of a USB transaction or on detection of a bus reset signal a suspend condition an SOF packet or resume signal if the corresponding interrupt request enable bit is set 3 To control the USB interface it is necessary to manipulate the following special function registers USBDIV PLLCNT USCTRL USPORT USBINT EPOINT EP2INT EP3INT EPAINT FRAMEL FRAMEH USBADR EPINFO EPOSTA EPOMP EPORX EPOTX EPISTA EP2STA EP3STA EP4STA EPICNT EPIRX EP2CNT EP2RX EP3CNT EP3RX EP4CNT TESTRO TESTR1 EPADOF P3 P3DDR Address Initial Value BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 4 0000 0000 R W USBDIV CF480N DVCKDR P73NDL 12 UDVSEL2 UDVSEL1 UDVSELO 3 117 U Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FESB H000 FRAMEH FRMIO 09 08 FEsF rw EPOMP EOMPS EOMP4 EOMPI EOMPO H000 0000 R W EPORX FE EPOTX EOTX6
227. on Output type CMOS or N channel OD selectable on a bit basis 5 Port Block Diagrams sng P7 FE5C W P7 P73 P71 S lt AD input 71 L P7 bits 7 5 HALT HOLD T D P7 FE5C bit 0 Q 4 5 5 E AD input P70 L INTO P7 bit 4 D INTS INT1 From watchdog timer Port 7 Pin Block Diagram Option None 6 LC871A00 APPENDIX II ISL FE5F Noise fitter filter D B Timer OH capture signal gt Timer 0 clock input Int request to L address 00013 I23CR FESE CELERE Int request to address 0001B E L INT2 _ e Timer OL capture signal E INT1 L level Int request to address 00003 Int request to address 0000B INTO 2 ee L level Port 7 Interrupt Block Diagram 7 Port Block Diagrams PWM1 output data Pin d PWM1 PWM1L FE22 bit 6 L D W PWM1L C R PWM1L PWMOC FE24 bit 3 L W PWMOC C E R PWMOC PWMO output data Pi in PWMO PWMOL FE20 bit 6 W PWMOL R PWMOL R PWMO1P PWM0 PWM1 Block Diagram Option None 8 Important Note This document is designed to provide the reader with accurate information in easily understandable form regarding the device features and the correct device implementation procedures The sample configurations included in the various descri
228. on mode e Set as follows SIOCTR 0 SIODIR SIOIE 1 Setting up the ports Clock Port P12 Internal clock Output Data Output Port Data I O Port P10 P11 Data transmission only Output Data transmission reception 3 wire Output Input Data transmission reception 2 wire EE N channel open drain output Setting up output data Write the output data into SBUFO in the data transmission or data transmission reception mode Starting operation Set Reading data after an interrupt Read SBUFO SBUFO has been loaded with serial data from the data I O port even in the transmission mode Clear SIOEND Return to step 4 when repeating transmission reception processing 3 62 LC871A00 Chapter 3 3 11 5 2 Continuous data transmission reception mode 1 Setting the clock Setup SBRO when using an internal clock 2 Setting the transmission mode Setas follows SIOBNK 7 SIOWRT 1 SIODIR SIOIE 1 3 Setting up the ports Clock Port P12 Internal clock Output Data Output Port Data Port P10 P11 Data transmission only Output Data transmission reception 3 wire Output Data transmission reception 2 wire _____ ____ N channel open drain output 4 Setting up the continuous data bit register Specify the number of bits to be subject to continuous transmission reception processing 5 Setting up output data Transfer the output data of the sp
229. on occurs see Note 1 in Table 3 12 1 interrupt will be generated as is cleared in that case If there is a possibility of a condition for losing the bus contention such as the presence of a separate master mode device find out such condition by for example performing timeout processing using a timer module 6 Sending data Load SBUFI with output data Clear SIIEND and exit interrupt processing transfer SBUFI 8 bits stop bit H 3 71 5101 7 8 9 10 3 12 4 4 2 3 Checking sent data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in the transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW If a condition for losing the bus contention occurs see Note 1 in Table 3 12 1 no interrupt will be generated as SITRUN is cleared in that case If there is a possibility of a condition for losing the bus contention such as the presence of a separate master mode device find out such condition by for example performing timeout processing using a timer module Return to step 6 when continuing data transmission Go to step 10 to terminate communication Receiving data Set to 1 Clear SIIEND and exit interrupt processing receive 8 bits SBUFI bit 8 acknowledge output Reading received data after an i
230. one p p p T E iem pe Se 4 s AI 9 LC871A00 APPENDIX II E T7OUT P07 T6OUT P06 CLKOUT P05 SW PO FE40 bits 7 5 D CMOS W PO Q Nch OD s P07 P05 S lt E L R PO E 5 PO FE40 bit 4 D CMOS Q or Pin Nch OD P04 S lt L SW PO FE40 d sw bits 3 2 1 0 D CMOS Q or Pin Nch OD S lt E i PODDR FE41 5 4 3 2 9 PO FE40 bit 7 07 pin input data Int request to PO FE40 bit 6 address 00048 pin input data PO FEAO bit 5 P05 pin input data PO FEAO bit 4 P04 pin input data PODDR FE41 bit 1 PO interrupt detected 40 bit 3 Pull up resistor is pin input data Not attached if Nch OD option is selected PO FE40 bit 2 Programmable if CMOS option is selected P02 pin input data 40 bit 1 pin input data PO FE40 bit 0 Shared port pin function POO pin input data Timer 7 toggle output PODDR FE41 bit 0 Timer 6 toggle output 5 Clock output system subclock selectable Port 0 Block Diagram Option Output type CMOS or N channel OD selectable on a bit basis 1 Port Block Diagrams FUNCTION output 7 6 P1FCR FE46 bits 7 6 W P1FCR E o R P1FCR 1 FE44 bits 7 6 cmos D Pin W P1 Nch OD XOR P17 P16 S E L R P1 P1DDR FE45 bits 7 6 D Q W P1DDR R
231. ons for receive format B as for receive format A Refer to Receive format receive operation 3 157 REMOREC2 3 19 5 3 Receive operation when receive format C is specified Receive format C outline Guide pulse None Data encoding system PPM Stop bits Yes Example of a receive format C receive operation positive phase input RM2RUN set to 1 V P73 RMIN Data Data Data 0 1 i Check end of reception i Data 1 pulse criterion Data 1 pulse criterion Overflow detected value low side value high side RM2MJCT count value Edge detected Edge detected Data 0 pulse Data 0 pulse End of Count start Count reset amp criterion value criterion value reception start low side high side Setting up the receive format C criterion values 2 3 Check the pulse width from rising edge to rising edge of data 0 and 1 4 Detect an end of reception condition from rising edge to overflow of data criterion value The criterion values are the same as those for the receive format A Receive format C receive operation 1 When the REMOREC2 detects the first rising edge of the remote control signal at the beginning or resumption of a receive operation it resets the RM2SFT and RM2BCT 2 When the data pulse falls within the valid criterion value range the REMOREC2 resets the RM2MJCT and loads the data 0 1 into the RM2SFT The data from the RM2SFT is transferred to the RM2RDT ever
232. or 2 byte basis according to the level H or L level of a port P70 to P73 0 Disables suspension port control in the continuous transfer mode S4STPCHI bit 2 Suspension port control polarity select 1 Transfer is suspended when a port P70 to P73 is set to the high level and resumed when the port is set to the low level 0 Transfer is suspended when the ports P70 to P73 are set to the low level and resumed when the ports are set to high level S4STPSL1 bit 1 Suspension control port select S4STPSLO bit 0 Suspension control port select These bits are used to select the ports to be used to control continuous transfer mode suspension S4STPSL 1 0 Suspension control port 00 P70 01 71 10 P72 11 P73 S4STPSL1 0 Number of bytes transferred S4STPWD Selector Transfer suspension resumption control S4STPCHI S4STPCEN S4WSTP 3 79 5104 3 13 4 3 5104 control register 0 SI4CNO Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEDB 0000 0000 R W SI4CNO SI4RUN SBITON MSBSEL SARAM S4CKPL SIAWRT SI4END SI4TE SI4RUN bit 7 104 operation control flag 1 Starts transfer This bit is automatically cleared at the end of transfer e When SIARUN is set to 1 in the internal clock operating mode master operation the transmission of the clock from the SCK4 pin and the loading of the input serial data into the shift
233. or USB bus active occurs bit 1 of the PCON register is cleared and the microcontroller switches into the HALT mode 3 X tal HOLD mode All oscillations except the subclock oscillation are suspended The microcontroller suspends the execution of instructions and all the peripheral circuits except the base timer stop processing The X tal HOLD mode is entered by setting bit 1 of the PCON register to 1 when bit 2 is set to 1 In this case bit 0 of the PCON register HALT mode flag is automatically set When a reset occurs or a HOLD mode resetting signal base timer interrupt INTO INTI INT2 INT4 5 POINT USB bus active or remote controller reception occurs bit 1 of the PCON register is cleared and the microcontroller switches into the HALT mode 4 3 3 Related Registers 4 3 3 1 Power Control Register PCON 3 bit register 1 The power control register is a 3 bit register that specifies the operating mode normal HALT HOLD X tal HOLD Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH H000 R W PCON XTIDLE PDN IDLE bits 7 to 3 These bits do not exist They are always read as 1 4 13 Standby XTIDLE bit 2 X tal HOLD mode setting flag PDN bit 1 HOLD mode setting flag XTIDLE Operating mode Normal or HALT mode 0 sent dee am n HOLD mode X tal HOLD mode 1 These bits must be set with an instruction If microcontroller enters
234. ot transferred to RAM e For example when data is received with S4ADDR set to 04 and S4ADRL to 00 SABYTH to 00 H SABYTE to 1F H 32 bytes of received data are stored in the RAM address area 0400 H through 041E H and the shift buffer SI4BUF 3 86 LC871A00 Chapter 3 Shift buffer SI4BUF FEDD H 32 RAM Example 3 CRC cyclic redundancy checking calculation 1 Setting up CRC related registers Set the SIO4 registers as follows i CRCCNT CRCON 0 CRCLRZ 0 CRCRD 0 I OSEL 0 ii Define the generator polynomial CRCH CRCL CRCH 10 H CRCL 21 H CRCCNT CRCON 0 CRCLRZ 1 CRCRD 1 1 05 1 Step ii may be skipped if one is already defined For 2 to 9 set the SIO4 registers in the same way as in 1 through 8 in example 2 10 Reading received data Received data is stored in RAM sequentially starting at the specified RAM starting address The last data byte is held in the shift buffer and not transferred to RAM For example when the byte data stream 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff H is received with S4ADDR set to 05 S4ADRL set to 00 S4BYTH to and SABYTE to OF H 16 bytes of receive data are stored in the RAM address area 0500 H through OSOE H and the shift buffer SI4BUF 11 Reading CRC results The results of CRC calculated on the received data are as follows CRCH 12 H CRCL 48 H Shift buffer SI4B
235. ow power intermittent current operation 4 Itis necessary to manipulate the following special function registers to control the infrared remote control receiver circuit 2 REMOREC2 e RM2CNT RM2INT RM2SFT RM2RDT RM2CTPR RM2GPW RM2DTOW RM2DTI W RM2XHW P7 FE27 0000 0000 R W RM2CNT RM2RUN RM2FMT2 RM2FMTI RM2FMTO 2 RM2CK2 RM2CKI RM2CKO sooo nwcsre nwcsrrz rx RVARDTS rer woe _ 3 19 3 Circuit Configuration 3 19 31 Remote control receive control register RM2CNT 8 bit register 1 remote control receive control register controls the remote control s receive operation 3 19 3 2 Remote control receive interrupt control register RM2INT 8 bit register 1 The remote control receive interrupt control register controls the processing of remote control receive interrupts 2 When the REMOREC2 starts receive operation with RM2CK selected as the subclock oscillation source the X tal HOLD mode of the microcontroller can be released using the interrupt occurring in the REMOREC2 circuit 3 19 3 3 Remote control receive shift regist
236. point 0 2 Ifthis bit is set to 0 the USB interface does not process the token at endpoint 0 EOTGL bit 6 EPO data toggle 1 This bit is automatically set to 1 when a SETUP transaction terminates normally with an ACK 3 132 LC871A00 Chapter 3 2 Onan OUT transaction the receive data is transferred to RAM only when the packet ID in the data packet from the host matches EOTGL The state of EOTGL is automatically inverted when the transaction terminates normally with an ACK 3 Onan IN transaction the USB interface transmits the data packet with a packet ID matching EOTGL The state of EOTGL is automatically inverted when the USB interface receives an ACK from the host 4 This bit is automatically cleared to 0 when an OUT transaction or IN transaction in the status stage terminates normally with an ACK EOOVR bit 5 EPO payload over flag 1 This bit is automatically set to when the USB interface receives a volume of data exceeding the maximum payload size defined in EPOMP 2 This flag must be cleared with an instruction EOSTL bit 4 EPO stall flag 1 If this bit is set to 1 the USB interface returns a STALL handshake for IN and OUT transactions 2 This bit is automatically set to 1 when a STALL handshake is returned due to a protocol violation 3 This bit is automatically cleared to 0 when a SETUP transaction terminates normally with ACK EOACK bit 3 EPO ACK flag 1 this bit is set to 1 the USB i
237. pt requests nterrupt requests of the X level cannot be disabled 5 Interrupt disable period Interrupts are held disabled for a period of 2Tcyc after a write is made to the IE FE08H or IP register or the HOLD mode is reset No interrupt can occur during the interval between the execution of an instruction that loads the PCON FE07H register and the execution of the next instruction No interrupt can occur during the interval between the execution of a RETI instruction and the execution of the next instruction 4 1 Interrupt 6 Interrupt level control Interrupt levels can be selected on a vector address basis Table of Interrupts No Vector Selectable Level Interrupt Sources 00003H XorL INTO 00013H HorL INT2 TOL INT4 USB bus active Remote controller reception 0001BH INT3 5 timer MN Eus Ls We eet eet ES 00033 HorL SIO0 USB bus reset USB suspend UARTI receive 0003BH HorL SIOI USB endpoint USB SOF SIO4 UARTI transmit was Por PME e Priority levels X gt H gt L 1 2 3 4 5 7 10 Of interrupts of the same level the one with the smallest vector address takes precedence 7 To enable and disable interrupts and specify their priority it is necessary to manipulate the following special function registers IE IP Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT2 BIT1 BITO 08 0
238. ptions are intended for reference only and should not be directly incorporated in user product configurations ON Semiconductor shall bear no responsibility for obligations concerning patent infringements safety or other legal disputes arising from prototypes or actual products created using the information contained herein LC871A00 SERIES USER S MANUAL Rev 1 02 March 1 2010 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit
239. r stopped by a reset Caution If WDTRST is set to 1 a reset is triggered when P70 INTO TOLCP pin is H level even if the watchdog timer is inactive The N channel transistor at pin P70 INTO TOLCP is turned on if the watchdog timer is stopped WDTRUN 0 and watchdog timer clear control WDTCLR is set to 1 Keep this in mind when programming if the watchdog timer function is not to be used current than usual may be consumed depending on the program or application circuit 2 Master interrupt enable control register IE See subsubsection 4 1 4 1 Master interrupt Enable Control Register for details 3 Port 7 control register P7 See subsubsection 3 5 3 1 Port 7 Control Register for details 4 23 Watchdog Timer 4 5 5 Using the Watchdog Timer Code a program so that instructions for clearing the watchdog timer periodically are executed Select the resistance R and the capacitance C such that the time constant of the external RC circuit is greater than the time interval required to clear the watchdog timer 1 2 Initializing the watchdog timer All bits of the watchdog timer control register WDT are reset when a reset occurs by the external RES pin If the P70 INTO TOLCP pin has been charged up to the high level discharge it down to the low level before starting the watchdog timer The built in N channel transistor is used for discharging Since it has an on resistance a discharging time equal
240. r counter 0 16 bits of data need match in the 16 bit mode 2 The match buffer register is updated as follows The match register matches TOLR when it is inactive TOLRUN 0 When the match register is running TOLRUN 1 it is loaded with the contents of TOLR when a match signal is generated Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 14 0000 0000 R W TOLR TOLR7 TOLR6 TOLRS TOLR4 TOLR3 TOLR2 TOLR1 TOLRO 3 30 LC871A00 Chapter 3 3 6 4 6 Timer counter 0 match data register high byte 1 This register is used to store the match data for TOH It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the higher order byte of timer counter 0 16 bits of data need match in the 16 bit mode 2 The match buffer register is updated as follows The match register matches TOHR when it is inactive TOHRUN 0 When the match register is running TOHRUN 1 it is loaded with the contents of when a match signal is generated Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE15 0000 0000 R W TOHR TOHR7 TOHR6 5 TOHR4 TOHR3 TOHR2 TOHRI TOHRO 3 6 4 7 Timer counter 0 capture register low byte TOCAL 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 low byte TOL on an external input detection signal Address Initial Value R W Na
241. re 16 bit programmable timer with a programmable prescaler equipped with a 16 bit n this mode timer counter 0 serves as 16 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL and are captured into the capture registers and TOCAH at the same time on external input detection signals from the P71 INTI TOHCP and P73 INT3 TOIN and P20 to P27 timer OH capture input pins TO period TOHR TOLR 1 x TOPRR 1 x Tcyc 16 bits 4 Mode 3 16 bit programmable counter equipped with a 16 bit capture register n this mode timer counter serves as a 16 bit programmable counter that counts the number of external input detection signals from the P72 INT2 TOIN and P73 INT3 TOIN pins The contents of TOL and are captured into the capture registers and TOCAH at the same time on external input detection signals from the P71 INTI TOHCP and P73 INT3 TOIN and P20 to P27 timer OH capture input pins TO period TOHR 1 16 bits 5 Interrupt generation TOL or TOH interrupt requests are generated at the counter interval for timer counter TOL or TOH if the interrupt request enable bit is set 6 To control timer counter 0 TO it is necessary to manipulate the following special function registers TOCNT TOL TOLR P7 ISL 0 D3CR P2 P2DDR 145 I45SL
242. re 3 13 1 CRC Encoding Decoding Circuit In this example the CRC register CRCH and CRCL must be set up as follows CRCH 10 H CRCL 21 H 3 The results of CRC calculation can be read from the CRC register CRCH and CRCL when the CRC control register CRCCNT bit 5 CRCRD is set to 1 3 78 LC871A00 Chapter 3 3 13 4 2 Cyclic redundancy check CRC control register CRCCNT 1 CRCCNT register controls cyclic redundancy check CRC processing 2 The register exercises suspension port control in the continuous data transfer mode Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO 00000000 CRCON CRCLRZ CRCRD 1 0SEL S4STPCEN S4STPCHI S4STPSL1 S4STPSLO CRCON bit 7 CRC calculation control flag 1 Starts operation 0 Stops operation CRCLRZ bit 6 CRC register control flag 1 The contents of the CRC results register are preserved 0 The CRC results register is initialized CRCRD bit 5 CRC results read control flag 1 The CRC results are read out of the CRC results register 0 The generator polynomial is read out of the CRC results register 1 0SEL bit 4 CRC results register initialization control flag 1 All CRC results register bits are initialized to 1 0 All CRC results register bits are initialized to 0 S4STPCEN bit 3 Suspension port control enable flag 1 Enables continuous transfer mode suspension control on a 1
243. reaches the count value TOLR 1 x 8 value of NKCMP2 to NKCMPO the realtime output turns to the required value Subsequently the realtime output port relinquishes the realtime output capability and synchronizes itself with the data in the port latch To restore the realtime output capability a value that will result in NKEN 1 must be written into NKREG 5 Capture clock Generated in synchronization with the capture clock for TOL timer 0 low byte 3 7 3 2 P1TST Register 1 The realtime output function is enabled when DSNKOT PITST register bit 2 is set to 0 2 The realtime output function is disabled when DSNKOT PITST register bit 2 is set to 1 In this case the realtime output pin functions as an ordinary port pin 3 33 3 7 3 3 Timer counter 0 operation TOEXT TOCNT bit4 must be set to 1 when a high speed clock counter is to be used When NKEN 1 and TOCNT bit5 0 timer OH runs in the normal mode and timer OL is coupled with the high speed clock counter to form a 11 bit free running counter When NKEN 1 and TOLONG TOCNT bit5 1 timer 0 is coupled with the NK counter to form a 19 bit free running counter When a free running counter reaches the count value timer 0 match register value 1 x 8 value of NKCMP2 to a match detection signal occurs generating the realtime output of the required value and setting the match flag of timer 0 No new match signal is detected un
244. ree FUE 3 1 10 3 1 7 5 AD Conversion Examples eee eee eee eee 3 1 14 3 17 6 Hints on the Use of the ADC 3 115 3 18 USB 3 117 3 18 1 Overview eee eee eee eee eee ere eter etree treet FC C nwE0nE0nE00LLGBLB PE 3 1 17 3 18 2 Functions tree rere rere rer tree reer treet reer rere terete rere rere retire 3 1 17 3 1 8 3 Circuit Configuration Prete eer eee ree treet rere rere eet rere reer errr rer CCFCCTFC L A r ire 3 1 19 3 1 8 4 Related Registers Petree etree treet eet rere rere e etre rere errr rr rer reer reer eter eter errr errr erie 3 1 23 3 1 8 5 USB Communication Examples eee eee eer eee etree teeter etree reer rere errr ee 3 144 3 18 6 USB Interface HALT Mode Operation 3 144 3 19 Infrared Remote Control Receiver Circuit 2 REMOREC2 m 3 145 3 19 1 Overview eee eee eee eee eer eee eet ree errr C CCCC A A L A o e n 3 145 3 1 9 2 Functions Perret eee eee treet rere rere rere rere reer rer r rer r rer r rere terete rere rere r etree teeter etree treet t es 3 1 45 3 19 3 Circuit Configuration Peete etre
245. register TI CNT 8 bit register 1 The timer 1 control register controls the operation and interrupts of the TIL and 3 8 3 2 Timer 1 prescaler control register TIPRR 8 bit counter 1 Thisregister sets the clocks for TIL and T1H 3 8 3 3 Timer 1 prescaler low byte 8 bit counter 1 Start stop The start stop of timer 1 prescaler low byte is controlled by the 0 1 value of TILRUN timer 1 control register bit 6 2 Count clock Varies with the operating mode Mode T1LONG T1PWM T1L Prescaler Count Clock 0 0 0 2 Tcyc events Note 2 1 0 1 1 Note 3 2 1 0 2 Tcyc events Note 2 3 1 1 1 Tcyc Note 3 Note 2 TIL serves as an event counter when INT4 INTS is specified as the timer 1 count clock input in the external interrupt 4 5 pin select register I45SL It serves as a timer that runs using 2Tcyc as its count clock if neither INT4 nor 5 are specified as the timer 1 count clock input Note 3 TIL will not run normally if INT4 or INTS is specified as the timer 1 count clock input when T1PWM 1 When TIPWM 1 do not specify INT4 or INT5 as the timer 1 count clock input 3 Prescaler count Determined by the TIPRC value The count clock for is generated at the intervals determined by the prescaler count T1LPRE TILPRC2 TILPRC1 TILPRCO T1L Prescaler Count 0 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0
246. register are started regardless of the setting of SBITON 0 Stops transfer SBTION bit 6 Automatic transfer on start bit detection control flag 1 Sets the serial data transfer control flag SI4RUN automatically on detection of the falling edge of the serial input data Even when SBITON is set to 1 with SIARUN set to 0 in the internal clock operating mode master operation no clock is transmitted out of the SCK4 pin until a falling edge of input serial data is detected and SIARUN is automatically set 0 Does nothing on the automatic transfer setting MSBSEL bit 5 MSB LSB transfer direction control flag 1 MSB transfer 0 LSB transfer S4RAM bit 4 Selects the start time RAM address 1 The RAM address 00 is selected first followed by RAM address 01 and so on on output On input the RAM address 01 is selected first followed by RAM address 02 and so on 0 The serial shift register is selected first followed by RAM address 00 and so on on output On input the RAM address 00 is selected first followed by RAM address 01 and so on S4CKPL bit 3 104 clock polarity control flag 1 Data is output on detection of the rising edge of a clock and input on detection of the falling edge of a clock 0 Data is output on detection of the falling edge of a clock and input on detection of the rising edge of a clock SIAWRT bit 2 104 transmission reception mode setting flag 1 Transmission and reception the contents of R
247. requency of source clock to be placed at 5 100 1 16 of frequency of source clock to be placed at POS 101 1 32 of frequency of source clock to be placed at POS 110 1 64 of frequency of source clock to be placed at POS 111 Frequency of source oscillator clock selected as subclock 3 3 Notes on the use of the clock output feature gt Take notes 1 to 4 given below when using the clock output feature Anomalies may be observed in the waveform of the port clock output if these notes are violated 1 Donotchange the frequency of the clock output when CLKOEN bit 3 is set to 1 gt Do not change the settings of CKODV2 to CKODVO bits 2 to 0 2 Do not change the output clock source selection when CLKOEN bit 3 is set to 1 gt Do not change the settings of SCKOSLS and SCKOSL4 bits 5 and 4 3 not change the system clock selection when CLKOEN 3 is set to 1 Do not change the settings of CLKCB5 and CLKCBA bits 5 and 4 of the OCR register 4 CLKOEN will not go to 0 immediately even when the user executes an instruction that loads the POFCRU register with such data that sets the state of CLKOEN from 1 to 0 CLKOEN is set to 0 at the end of the clock that is being output on detection of a falling edge of the clock Accordingly when changing the clock divider setting or changing the system clock selection after setting CLKOEN to 0 with an instruction be sure to read the CLKOEN value in advance and make sure
248. rol signal If the REMOREC2 detects an edge after starting the detection of an edge at this timing and before timing 3 it resets the 2 and proceeds with the next step data error is identified if no edge is detected At timingl in step 6 the REMOREC2 samples the remote control signal At timing 2 in step 6 REMOREC tests the data that is sampled in step 11 12 If the data is identified as 0 or 1 the REMOREC2 performs the step similar to step 5 It also resets the RM2MJCT and resets RM2CK to the frequency If the data is identified as error the REMOREC2 performs the step similar to step 6 At timing in step 7 REMOREC2 samples the remote control signal If the REMOREC2 detects an edge after starting the detection of an edge at this timing and before timing 3 it resets the 2 and proceeds with the next step a data error is identified if no edge is detected In subsequent step 8 the REMOREC2 repeats steps 3 to 7 It performs step 8 when it detects the end of reception condition 3 161 REMOREC2 3 162 LC871A00 4 Control Functions 4 1 Interrupt Function 4 1 1 Overview This series of microcontrollers has the capabilities to control three levels of multiple interrupts 1 e low level L high level H and highest level X The master interrupt enable and interrupt priority control registers are used to enable or disable interrupts and determine the priority of in
249. rrupt request Interrupt request accepted Note 2 E Resetting conditions established Note 1 INTO or INT1 level interrupt request generated Request for INT2 INT4 INT5 USB bus active port 0 interrupt or remote controller reception generated Resetting condition established Note 1 Note 1 The CPU enters the reset state when the resetting conditions are established Note 2 The CPU cannot return from the HALT mode since no interrupt request can be accepted unless its interrupt level is higher than the interrupt level t hat placed the CPU into the HALT HOLD or X tal HOLD mode Interrupt level at which the CPU entered HALT HOLD or X tal HOLD mode No interrupt request present Interrupt request level that can reset HALT mode X H and L levels L level X and H levels H level X level X level None unable to reset with interrupt Fig 4 3 1 Standby Mode State Transition Diagram 4 18 LC871A00 4 4 Reset Function 4 4 1 Overview The reset function initializes the microcontroller when it is powered on or while it is running 4 4 2 Functions This series of microcontrollers provides the following two modes of resetting function External reset via the RES pin The microcontroller is reset without fail by applying and holding a low level to the RES pin for 200 ws or longer Note however that a low level of a small duration less than 200 ws 15 likely to
250. rsion interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and ADENDF are set to 1 Notes No correct conversion results can be obtained if both ADCHSEL3 and ADCHSEL2 are set to 1 Setting ADCHSEL3 and ADCHSEL2 to 1 is inhibited Do not place the microcontroller in the HALT or HOLD mode with ADSTART set to Make sure that ADSTART is set to 0 before putting the microcontroller in the HALT or HOLD mode 3 111 ADC12 3 17 4 2 AD mode register ADMRC 1 The AD mode register is an 8 bit register for controlling the operation mode of the AD converter 4 bit 7 Fixed bit This bit must always be set to 0 bit 6 AD conversion mode control resolution select This bit selects the AD converter s resolution between 12 bit AD conversion mode 0 and 8 bit AD conversion mode 1 When this bit is set to 1 the AD converter serves as an 8 bit AD converter The conversion results are placed in the AD conversion results register high byte ADRHC the contents of the AD conversion results register low byte ADRLC remain unchanged When this bit is set to 0 the AD converter serves as a 12 bit AD converter The conversion results are placed in the AD conversion results register high byte ADRHC and the higher order 4 bits of the AD conversion results register low byte ADRLC ADMD2 bit 5 Fixed bit This bit must always be set to 0 ADMD1 bit
251. rt and interrupts Setup the transmit control register UCONI 31H Set P20DDR P2DDR BITO to 0 and P20 P2 BITO to 0 2 Starting a transmit operation Set UCON1 TRUN 3 Transmit interrupt processing Load the next transmit data xxH Clear UCONI TEPTY and exit the interrupt processing routine 4 End of transmit operation e When the transmit operation ends UCONI TRUN is automatically cleared automatically set in the same cycle Tcyc at the continuous data transmission mode only this processing takes 1 Tcyc of time The UARTI then starts the transmission of the next transmit data 5 Next transmit data processing e Subsequently repeat steps 3 and 4 shown above To terminate continuous mode transmit processing clear UCONI TRNSIE while not clearing UCONI TEPTY and exit the interrupt in the step 3 processing and the transmit operation that is being performed at that time will be the last transmit operation that the UARTI executes 3 100 3 15 5 3 2 3 15 6 3 15 6 1 1 2 3 15 6 2 2 LC871A00 Chapter 3 Setting Up the UART1 communications ports Setting up the receive port P21 Register Data Receive Port P21 Internal Pull up P21 P21DDR State Resistor 0 0 Input Off 1 0 Input On The UARTI can receive no data normally if P21DDR is set to 1 Setting up the transmit port P20 Register Data Transmit Port P20 State
252. rt 0 output data and port 0 interrupts 2 When this register is read with an instruction data at pins POO to 7 is read in If PO FE40 is manipulated with an instruction NOTI CLR1 SETI DBZ DBNZ INC or DEC the contents of the register are referenced instead of the data at port pins 3 Port 0 data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE40 0000 0000 R W PO P07 P06 P05 P04 P03 P02 1 POO 3 1 3 2 Port 0 data direction register PODDR 1 The port 0 data direction register is a 6 bit register that controls the I O direction of port 0 data in 4 bit units the pull up resistors in 4 bit units and port 0 interrupts Address Initial Value R W Name BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 41 HH00 0000 R W PODDR POFLG POIE POHPU POLPU POHDDR POLDDR POFLG bit 5 PO interrupt source flag This flag is set when a low level is applied to a port 0 pin that is set up for input and the corresponding PO FE40 bit is set A HOLD mode release signal and an interrupt request to vector address 004BH are generated when both this bit and the interrupt request enable bit POIE are set to 1 This bit must be cleared with an instruction as it is not cleared automatically POIE bit 4 PO interrupt request enable Setting this bit and POFLG to 1 generates a HOLD mode release signal and an interrupt request to vector
253. ry SABYTRD bit 6 Transferred byte count read control flag 1 The number of transferred data bytes can be read from the lowest order 4 bits of SABYTH and SABYTE If continuous mode data transfer is suspended with SARAM SI4CNO bit 4 set to 0 however the byte count that is read is number of data bytes that are transferred minus 1 A 0 is read as the transferred byte count after the continuous mode data transfer processing is finished 0 The readout of transferred byte count is disabled 4 5 bit 5 Reserved Must always be set to 0 SABYTHA bit 4 Reserved Must always be set to 0 SABYTHS to 0 bit 3 to 0 Highest order 4 bits of transferred data byte count See the next subsubsection 3 13 4 10 5104 transfer data byte register low byte S4BYTE 1 The SABYTE register is used to define the lowest order 8 bits of the number of data bytes to be transferred in the continuous data transfer mode FEEO 0000 0000 R W S4BYTE S4BYT7 54 6 54 5 54 4 S4BYT3 S4BYT2 SABYTI SABYTO The lowest order 4 bits of SABYTH and 8 bits of S4BYTE are used to define the number of data bytes to be transferred SABYTH lowest order 4 bits SABYTE Transfer data byte count H H 0 00 1 0 01 2 7 2048 3 83 When S4CKPL 0 SCKA is held high when the clock is stopped the data state is changed on the falling edge of a clock and data is taken in on the rising edge
254. s handshake for IN and OUT transactions 3 See Table 3 18 12 E4DIR bit 2 EPA transfer direction flag 1 If this bit is set to 1 the USB interface processes only IN tokens at endpoint 4 2 If this bit is set to 0 the USB interface processes only OUT tokens at endpoint 4 3 See Table 3 18 12 EAISO bit 1 EP4 isochronous transfer 1 Setting this bit to 1 sets the transfer type of endpoint 4 to isochronous 2 If this bit is set to 0 the transfer type of endpoint 4 is either bulk transfer or interrupt transfer 3 See Table 3 18 12 3 137 USB E4BNK bit 0 EP4 transfer RAM address control flag 1 Setting this bit and E4OF 1 0 EPADOF bits7 and 6 allocates the data transmit receive buffer areas for endpoint 4 Table 3 18 10 EP4 buffer areas E4BNK 4 1 4 RAM address 0 0 0 0380H to 0 0 1 0390H to 03 0 1 0 to 0 1 1 03BOH to 1 0 0 03COH to 1 0 1 03D0H to 040 1 1 0 03 to 041FH 1 1 1 03F0H to 042FH 3 18 4 22 count register EP1CNT 1 The count register must be loaded with the number of transmit data bytes for endpoint 1 if the transfer direction of endpoint 1 is IN EIDIR 1 2 If the transfer direction of endpoint 1 is OUT E1DIR 0 this register must be loaded with the maximum payload size of endpoint 1 3 The legitimate value range is from 00 H to
255. s controlled by PWMOH FE21 0000 0000 PWMOH PWMO0OH7 6 PWMOH3 PWMOH2 PWMOH 1 PWMOHO 3 16 4 4 PWM 1 compare register L PWM1L 4 bit register 1 The compare register L controls the additional pulses of PWMI 2 PWMIL is assigned bits 7 to 4 and all of its lower order 4 bits are apparently set to 1 when it is read 3 When the PWMI control bit PWMOC FE24 bit 3 is set to 0 the output of ternary can be controlled using bits 7 to 4 of PWMIL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE22 0000 HHHH R W PWMIL PWMIL3 PWMIL2 PWMILI PWMILO PWM1L1 ENPWM1 PWM1L3 PWM1L2 PWM1 Output PWM1L0 FE24 bit 3 FE22 bit 7 FE22 bit 6 FE22 bits 5 amp 4 3 16 4 5 PWM1 compare register PWM1H 8 bit register 1 The PWMI compare register H controls the fundamental pulse width of PWMI Fundamental pulse width Value represented by PWM1H7 to PWMIHO 4 Teye 2 When bits 7 to 4 of PWMIL are all fixed at 0 can serve as period programmable 8 bit PWM that is controlled by PWM1H Os ele Additional pulses PWMOH PWMIH setting value Fundamental pulse counter Fundamental PVM waveform PWM output waveform 3 105 PWM 12 bit PWM has the following waveform structure The overall period consists of 16 fundamental wave periods A fu
256. s generated releasing the HOLD mode The CPU then enters the HALT mode main oscillation by CR When the interrupt is accepted the CPU switches from the HALT mode to normal operating mode e When signal change such that the interrupt flag is set is input to INT4 or INT5 in the HOLD mode the interrupt flag is set In this case the HOLD mode is released if the corresponding interrupt enable flag is set The interrupt flag however cannot be set by a rising edge occurring when INT4 or INT5 data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when INT4 or INTS data which is established when the HOLD mode is entered is in the low state Consequently to release the HOLD mode with INT4 or 5 it is recommended that INT4 or INT5 be used in the double edge interrupt mode LC871A00 Chapter 3 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE48 0000 0000 R W P2 P27 P26 P25 P24 P23 P22 P21 P20 FE49 0000 0000 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR rox Paspor respon pp m 3 3 8 Related Registers 3 3 3 1 Port 2 data latch P2 1 The port 2 data latch is an 8 bit register for controlling port 2 output data and pull up resistors 2 When this register is read with an instruction data at pins P20 to P27 is read in If P2 FE48 is manipulated with an
257. s of RAM are unpredictable at power on time Be sure to set the RES pin to the low level when turning on the CPU Otherwise the CPU will be out of control during the period from power on till the time the RES pin goes to the low level 4 20 LC871A00 4 5 Watchdog Timer Function 451 X Overview This series of microcontrollers incorporates a watchdog timer that with an external RC circuit detects program runaway conditions The watchdog timer charges the external RC circuit that is connected to the P70 INTO TOLCP pin and when the level at the pin reaches the high level triggers a reset or interrupt regarding that a program runaway occurred 4 5 2 Functions 1 Detection of a runaway condition A program that discharges the RC circuit periodically needs to be prepared If such a program hangs it will not execute instructions that discharge the RC circuit This causes the P70 INTO TOLCP pin to the high level watchdog timer detects the runaway 2 Actions to be taken following the detection of a runaway condition The microcontroller can take one of the following actions when the watchdog timer detects a program runaway condition Reset program reexecution External interrupt INTO program continuation The priority of the external interrupt INTO can be changed using the master interrupt enable control register IE 4 5 3 Circuit Configuration The watchdog timer is made up of a high threshold buffer a pulse stretcher c
258. s set Detect the falling edge of receive data 6 Reading data after an interrupt Read SBUFI SBUFI has been loaded with serial data read from the data I O port even in the transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW e Clear and exit interrupt processing Return to step 4 when repeating processing Note Make sure that the following conditions are met when performing continuous mode reception processing with SIO1 in mode 1 UART The number of stop bits is set to 2 or greater e Clearing of SIIEND during interrupt processing terminates before the next start bit arrives 3 12 4 3 Bus master mode mode 2 1 Setting the clock e Setup SBRI 2 Setting the mode Set as follows 0 SIIM1 1 SIIDIR 5 1 0 3 Setting up the ports Designate the clock and data ports as N channel open drain output ports 4 Starting communication sending an address Load SBUFI with address data Set SIIRUN transfer a start bit SBUFI 8 bits stop bit H 5 Checking for address data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in the transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW condition for losing the bus contenti
259. s that indicate the status of computation results a flag to access the 9th bit of RAM and a flag to designate the bank during the LDCW instruction The PSW is allocated to address FEO6H of the internal data memory space and initialized to on a reset Address Initial value R W Name BIT7 BIT6 BITS BIT4 2 BIT1 BITO FE06 0000 0000 R W PSW PSWBS5 PSWB4 LDCBNK OV bit 7 Carry flag CY is set to 1 when a carry occurs as the result of a computation and cleared to 0 when no carry occurs There are the following types of carries 1 Carry resulting from an addition 2 Borrow resulting from a subtraction 3 Borrow resulting from a comparison 4 Carry resulting from a rotation There are some instructions that do not affect this flag at all AC bit 6 Auxiliary carry flag AC is set to 1 when a carry or borrow occurs in bit 3 bit 3 of the higher order byte during a 16 bit computation as the result of an addition or subtraction and cleared to 0 otherwise There are some instructions that do not affect this flag at all PSWB5 PSWBA bits 5 and 4 User bits These bits can be read and written through instructions They can be used by the user freely LDCBNK bit 3 Bank flag for the table lookup instruction LDCW This bit designates the ROM bank to be specified when reading the program ROM with a table lookup instruction 0 ROM ADR 0 to IFFFF 1 ROM ADR 200
260. saevis mu wwws wwe mg mwmm ww LL LE mu wem wwe LLLI mu mumm ww LL 7 me www wwe mms ww L EL PE xL mu pre HHHH HHHH HORE ee ma mwmm ww L LLL mms wwmm wwe SSCS me ww LE ILL me mg ww ILL me wem wwe SS mo ww oe HHHH HHHH E E A E ma mwmm ww L E we we me ww L ERE E FEF8 HHHH HHHH None rro mmm noe p gd T 1 f 1 AI 8 LC871A00 APPENDIX I Address Initial value R W LC871A00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FEFA HHHH HHHH None FEFB HHHH HHHH None FERC Wu Wm FEFD None PO ree N
261. se 4 bits are used to select the signal to be subject to AD conversion 3 110 LC871A00 Chapter 3 AD AD AD AD CHSEL3 CHSEL2 CHSEL1 CHSELO 0 0 0 0 o o o o 9 1 o ww o o oum Signal Input Pin o s o Prans ____ FANS ADCRCS bit 3 Fixed bit This bit must always be set to 0 ADSTART bit 2 AD converter operation control This bit starts 1 and stops 0 AD conversion processing AD conversion starts when this bit is set to 1 This bit is automatically reset when AD conversion terminates The conversion time is defined using the ADTM2 bit of the AD conversion results register low byte ADRLC and bits ADTMI and ADTMO of the AD mode register ADMRC AD conversion stops when this bit is set to 0 Correct conversion results cannot be obtained if this bit is cleared during AD conversion processing This bit must never be cleared or the microcontroller must never be placed in the HALT or HOLD mode while AD conversion processing is in progress ADENDF bit 1 End of AD conversion flag This bit identifies the end of AD conversion It is set when AD conversion is finished Then an interrupt request to vector address 0043H is generated if ADIE is set to 1 If ADENDF is set to 0 it indicates that no AD conversion is in progress This flag must be cleared with an instruction ADIE bit 0 AD conve
262. shift register 1 The SI4BUF register is an 8 bit shift register used for 5104 serial transfer 3 77 5104 3 13 3 9 04 baudrate generator S4BAUD 8 bit reload register 1 The S4BAUD register is a reload counter for generating internal clocks 2 It can generate clocks at intervals of 4n 3 Tcyc n 1 255 Note n 0 is inhibited 3 13 3 10 04 RAM address register high byte S4ADDR 8 bit register 1 The S4ADDR register is used to define the starting address of the RAM area to be used for data transfer 3 13 311 6104 data byte register low byte SABYTE 8 bit register 1 The S4BYTE register is used to define the number of data bytes to be transferred via the 5104 in the continuous data transmission reception mode 3 13 4 Related Registers 3 13 4 1 Cyclic redundancy check register CRCL CRCH Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FED8 0000 0000 R W CRCL CRC7 CRC6 5 4 CRC3 CRC2 1 1 The CRC register for setting up the generator polynomial is 16 bits long and is made up of two registers CRCL and CRCH 2 This register is loaded with the data for setting up the generator polynomial when the CRC control register CRCCNT bit 5 CRCRD is set to 0 This register must be set up only once at the beginning Example The CRC encoding decoding circuit for the 16 bit generator polynomial G x X X 1 is shown below Data out Data in Figu
263. ss 6 23H RAM address 7 01H LD R3 Transfers the contents of RAM address 123H to the accumulator Li STW R3 Transfers the contents of BA register pair to RAM address 123H PUSH R3 Saves the contents of RAM address123H in the stack SUB R3 Subtracts the contents of RAM address 123H from the accumulator DBZ R3 L1 Decrements the contents of RAM address 123H by 1 and causes a branch if Zero 2 11 3 Indirect Register C Register Indirect Addressing Rn C In the indirect register C register indirect addressing mode the result of adding the contents of one of the indirect registers RO to R63 to the contents of the C register 128 to 127 with MSB being the sign bit designates an address in RAM or SFR For example if the selected indirect register contains FE02H and the C register contains 1 the address B register FE02H 1 FEO1H is designated Examples When R3 contains 123 and the C register contains 02H LD R3 C Transfers the contents of RAM address 125H to the accumulator 11 STW R3 C Transfers the contents of the BA register pair to RAM address 125H PUSH 3 Saves the contents of 125 in the stack SUB R3 C Subtracts the contents of RAM address 125H from the accumulator DBZ R3 C L1 Decrements the contents of RAM address 125H by 1 and causes a branch if Zero lt Notes on this addressing mode gt The internal data memory space is divided into three closed
264. st always be set to 0 UDVSEL2 bit 2 Frequency divided clock frequency select UDVSEL1 bit 1 Frequency divided clock frequency select UDVSELO bit 0 Frequency divided clock frequency select 1 These bits are used to select the frequency of the frequency divided clock derived from the USB 48 MHz clock 2 The bits must be set to select a frequency divided clock frequency of 8 to 12 MHz when the frequency divided clock is to be supplied as the system clock to drive the USB interface control circuit 3 When making an attempt to change the frequency divided clock frequency setting to any value other than the initial value UDVSEL 000 reset it to the clock stopped state value UDVSEL 110 before setting up a new value Example Changing the frequency divided clock frequency from 12 MHz to 8 MHz UDVSEL 100 gt 10 gt 011 3 123 U Table 3 18 3 Frequency Divided Clock Frequencies UDVSEL 2 0 Frequency MHz 000 4 001 4 8 010 6 011 8 100 12 101 Inhibited 110 Frequency divided clock stopped 111 16 3 18 42 USB PLL control register PLLCNT 1 The USB PLL control register is 8 bit register that controls the operation of the PLL oscillation circuit for the USB Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT2 BIT1 BITO FEOD 0000 0000 PLLCNT SELREF2 SELREFI PLLTEST VCOSTP CMPSTP LOVDEC PONRES SELREF2 bit 7 PLL refer
265. st order byte of the address and the contents 16 bits of Rn Rn C or RO off either one as the lower order bytes of the address Examples LDW 3456H Sets up the lower order 16 bits STW R5 Loads the indirect register R5 with the lower order 16 bits of the address MOV 12H B Sets up the higher order 8 bits of the address R5 Transfers the contents of external data memory address 123456H to the accumulator 2 9 2 12 2 12 1 Wait Sequence Wait Sequence Occurrence This series of microcontrollers performs wait sequences that suspend the execution of instructions in the following cases 1 2 3 2 12 2 1 2 3 4 5 When continuous data transmission is performed over 5100 with SIOCTR SCONO bit 4 set a wait request is generated ahead of each transfer of 8 bit data in which case a 1 cycle wait sequence RAM data transfer is performed When continuous data transmission is performed over the SIO4 a wait request is generated for each transfer of 8 bit data in which case a 1 1 wait sequence RAM data transfer is performed When data packet transmission reception is performed by the USB interface circuit a wait request is generated for each transfer of 4 bytes in which case a 1 wait sequence RAM data transfer is performed What is a Wait Sequence When a wait request occurs out of a factor explained in Subsection 2 12 1 the CPU suspends the execution of th
266. t 8192 3 The clock rate of the UARTI is programmable within the range of E to Tcyc 2 Continuous data transmission reception Performs continuous transmission of serial data whose data length and clock rate are fixed the data length and clock rate that are identified at the beginning of transmission are used The number of stop bits used in the continuous transmission mode is 2 See Figure 3 15 4 Performs continuous reception of serial data whose data length and clock rate vary on each receive operation 8192 3 The transmit data is read from the transmit data register TBUF and the received data is stored in the receive data register RBUF Theclock rate of the UARTI is programmable within the range of 5 to 3 Interrupt generation Interrupt requests are generated at the beginning of each transmission and at the end of each reception if the interrupt request enable bit is set 4 control the asynchronous serial interface 1 UART1 it is necessary to manipulate the following special function registers UCONO UCONI UBR TBUF RBUF P2 P2DDR Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEDO 0000 0000 R W UCONO UBRSEL STRDET RECRUN STPERR RBIT8 RECEND UCONI 3 02 3 15 3 3 15 3 1 1 3 15 3 2 1 3 15 3 3 1 2 3 15 3 4 1 3 15 3 5 1 2 3 15 3 6 1 3 15 3 7 1 2 LC871A00 C
267. t to vector address 0013H are generated RM2REND bit 1 End of reception flag This bit is set when the end of the receive format conditions are detected This flag must be cleared with an instruction 2 bit 0 End of reception interrupt request enable control When this bit and RM2REND are set to 1 an X tal HOLD mode release signal and an interrupt request to vector address 0013H are generated Notes RM2GPOK is not set when RM2FMT2 through RM2FMTO are set to give a value of 2 or 3 3 19 4 3 Remote control receive shift register 2 RM2SFT 1 The remote control receive shift register 2 is an 8 bit shift register used to receive data from the remote control 2 The data loading direction LSB first or MSB first is determined by the value of RM2RDIR 3 Since the contents of this register are transferred to RM2RDT from RM2SFT each time 8 bits of receive data are loaded in the RM2SFT this register is also used to read the last less than 8 bit receive data 4 RMGSFT is reset when one of the following conditions occurs 1 The receive operation is stopped RM2RUN 0 2 A guide pulse is received normally after the beginning or resumption of a receive operation when RM2FMT2 through RM2FMTO are set to 0 1 or 4 3 The first rising edge assuming that the input polarity is set to positive phase is detected after the beginning or resumption of a receive operation when RM2FMT2 through RM2FMTO set t
268. t after the contents of data RAM is transferred to SBUFO after the contents of RAM and SBUFO are exchanged when SIOWRT 1 Number of bits transferred SCTRO value 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE33 0000 0000 R W SCTRO SCTRO7 SCTRO6 SCTROS SCTR04 SCTRO3 SCTRO2 SCTRO1 SCTROO 3 11 4 5 Continuous data transfer control register SWCONO 1 continuous data transfer control register is used to suspend or resume the operation of 5100 in byte units in the continuous data transmission reception mode and to read the number of transmitted bytes bits 4 to O are read only Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE37 0000 0000 SWCONO SOWSTP SWCONB6SWCONBS SOXBYT4 SOXBYT3 SOXBYT2 SOXBYT1 SOXBYTO SOWSTP bit 7 When this bit is set to 1 SIOO stops operation after completing the transmission of 1 byte data in the continuous transfer mode 1 byte of serial data separated at the beginning of serial transfer Serial transfer resumes when this bit is subsequently set to 0 SWCONB6 SWCONBS bits 6 and 5 These bits can be read and written with instructions The user can use these bits freely SOXBYT4 SOXBYTO bits 4 to 0 These bits can be read to determine the number of bytes transmitted in the continuous data transfer mode 3 61 00 3 11 4 6 RAM used continuous data transmission reception mode SIOO c
269. t data into SBUFI in the data transmission mode SII REC 0 5 Starting operation e Set SIITRUN 6 Reading data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in the transmission mode e Clear SIIEND and exit interrupt processing Return to step 4 when repeating processing 3 12 4 2 Asynchronous serial transmission Mode 1 1 Setting the baudrate Setup SBRI 2 Setting the transmission mode e Set as follows 511 0 1 1 0 SIIDIR SI1IE 1 3 Setting up the ports Data Output Port Data I O Port P13 P14 Data transmission reception 2 wire Output Input Data transmission reception 1 wire N channel open drain output 3 70 LC871A00 Chapter 3 4 Starting transmission Set SIIREC to 0 and write output data into SBUFI e Set SIIRUN Note Use the 5101 data I O port when using the 8101 transmission only in mode 1 In mode 1 transmission is automatically started when a falling edge of receive data is detected While mode 1 is on the falling edge of data is always sensed at the data I O port P14 Consequently if the transmit port is assigned to the data output port P13 it is likely that data transmissions are started unexpectedly according to the changes in the state of P14 5 Starting receive operation Set SIIREC to 1 Once SIIREC is set to 1 do not attempt to write data to the SCONI register until the flag i
270. t is set to 1 PWMO is active When this bit is set to 0 the PWMO output ternary can be controlled using bits 7 to 4 of PWMOL PWMOOV bit 1 PWM0 PWM1 overflow flag This bit is set at the interval equal to the overall period of PWM This flag must be cleared with an instruction PWMOIE bit 0 PWMO PWM interrupt request enable control An interrupt to vector addresses 004BH is generated when this bit and PWMOOV are both set to 1 3 16 4 2 PWMO compare register L PWMOL 4 bit register 1 compare register L controls the additional pulses of PWMO 2 PWMOL is assigned bits 7 to 4 and all of its lower order 4 bits are apparently set to 1 when it is read 3 When the PWMO control bit PWMOC FE24 bit 2 is set to 0 the output of PWMO ternary can be controlled using bits 7 to 4 of PWMOL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE20 0000 HHHH PWMOL PWMOL3 PWMOL2 PWMOL1 PWMOLO ENPWMO PWMOL3 PWMOL2 PWMOL1 0 FE24 bit2 FE20 bit7 FE20 bit6 FE20 bits 5 4 PWMO Output HI Z 3 104 LC871A00 Chapter 3 3 16 4 3 PWMO compare register PWMOH 8 bit register 1 compare register controls the fundamental pulse width of PWMO Fundamental pulse width Value represented by to PWMOH 0 x 1 Teye 2 When bits 7 to 4 of PWMOL are all fixed at 0 PWMO can serve as period programmable 8 bit PWM that i
271. t to 1 when the endpoint 1 transaction terminates with a stall See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction 3 128 LC871A00 Chapter 3 ST1EN bit 0 EP1 stall interrupt request enable flag 1 An interrupt to vector address 003BH is generated when this bit STI FG and ENPEN are all set to 1 3 18 4 8 EP2interrupt control register EP2INT 1 The EP2 interrupt control register controls endpoint 2 interrupts Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT2 BIT1 BITO FE85 0000 0000 R W EP2INT AK2FG AK2EN NK2FG NK2EN ER2FG ER2EN ST2FG ST2EN AK2FG bit 7 EP2 ACK end flag 1 Set to 1 when the endpoint 2 transaction terminates normally with an ACK See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction AK2EN bit 6 EP2 ACK interrupt request enable flag 1 interrupt to vector address 003BH is generated when this bit AK2FG and ENPEN are all set to 1 NK2FG bit 5 EP2 NAK end flag 1 Set to 1 when the endpoint 2 transaction terminates with See the column entitled End Flags in Table 3 18 12 2 This flag must be cleared with an instruction NK2EN bit 4 EP2 NAK interrupt request enable flag 1 interrupt to vector address 003BH is generated when this bit NK2FG and ENPEN are all set to 1 ER2FG bit 3 EP2 error end flag 1 Set to 1 when the endpoint 2 tra
272. tarting communication waiting for an address Set SIIRUN is automatically set on detection of a start bit Perform receive processing 8 bits and set the clock output to 0 on the falling edge of the 8th clock which generates an interrupt Checking address data after an interrupt Detecting a start condition sets SILOVR Check SIIRUN 1 and SIIOVR 1 to determine if the address has been received is not automatically cleared Clear it by instruction Read SBUF1 and check the address If no address match occurs clear SILRUN and SIIEND and exit interrupt processing then wait for a stop condition detection at of step 8 Receiving data Clear and exit interrupt processing If a receive sequence has been performed send an acknowledge and release the clock port after the lapse of SBRI value 1 x Tcyc When a stop condition is detected SITRUN is automatically cleared and an interrupt is generated Then clear to exit interrupt processing and return to 2 in step 4 Perform a receive operation 8 bits then set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs The clock counter will be cleared if a start condition is detected in the middle of receive processing In such a case another 8 clocks are required to generate an interrupt Read SBUF1 and store the read data Note Bit 8 of SBUF is not yet updated beca
273. tch buffer register A match signal 15 generated when the value of this match buffer register coincides with the value of timer 1 high byte 2 The match buffer register is updated as follows and the match register has the same value when in inactive TIHRUN 0 If active TIHRUN 1 the match buffer register is loaded with the contents of TIHR when the value of T1H reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FEID 0000 0000 R W TIHR TIHR7 TIHR6 TIHRS TIHR4 TIHR3 TIHR2 TIHRI TIHRO 3 45 Match buffer register value Mode 0 2 Match signal Interrupt flag set T1PWML T1PWM FFH Counter value Mode 1 T1H Match signal FFH Counter value Interrupt flag set T1PWML T1PWMH Match buffer register value Mode 3 E Match sianal Interrupt flag set T1PWMH FFH Counter value I ir 3 o c 2 5 8 gt 5 5 gt 3 46 LC871A00 Chapter 3 3 9 Timers 6 and 7 T6 T7 3 9 1 Overview The timer 6 T6 and timer 7 T7 incorporated in this series of microcontrollers are 8 bit timers with two independently controlled 6 bit prescalers 3 9 2 Functions 1 Timer 6 Timer 6 is an 8 bit timer that runs on either 4Tcyc 16Tcyc or 64Tcyc clock It can generate at pin P06 toggle waveforms whose freq
274. tection INT4IF bit 1 INT4 interrupt source flag This bit is set when the conditions specified by INTAHEG and INT4LEG are satisfied When this bit and the INT4 interrupt request enable bit INT4IE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated The interrupt flag however cannot be set by a rising edge occurring when INT4 data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when INT4 data which is established when the HOLD mode is entered is in the low state Consequently to release the HOLD mode with INT4 it is recommended that INT4 be used in the double edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INT4IE bit 0 INT4 interrupt request enable When this bit and INTAIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 3 3 4 External interrupt 4 5 pin select register I45SL 1 This register is an 8 bit register used to select pins for the external interrupts 4 and 5 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE4B 0000 0000 R W I45SL 15813 15512 15511 15510 14513 14512 14511 14510 LC871A00 Chapter 3 15513 bit 7 INT5 pin select 15512 bit 6 INT5 pin select 15513 15512 Pin Assigned to INT5 Port P24 Port P25 0 0 o
275. terrupts 4 1 2 Functions 1 Interrupt processing Peripheral modules generate an interrupt request to the predetermined vector address when the interrupt request and interrupt request enable flags are set to 1 When the microcontroller receives an interrupt request from a peripheral module it determines the interrupt level priority and interrupt enable status of the interrupt If the interrupt request is legitimate for processing the microcontroller saves the value of PC in the stack and causes a branch to the predetermined vector address The return from the interrupt routine 1s accomplished by the RETI instruction which restores the old state of the PC and interrupt level 2 Multilevel interrupt control The interrupt function supports three levels of interrupts that is the low level L high level H and highest level X The interrupt function will not accept any interrupt requests of the same level or lower than that of the interrupt that is currently being processed 3 Interrupt priority When interrupt requests to two or more vector addresses occur at the same time the interrupt request of the highest level takes precedence over the other interrupt requests Among the interrupt requests of the same level the one whose vector address is the smallest has priority 4 Interrupt request enable control The master interrupt enable register can be used to control the enabling disabling of H and L level interru
276. the AD conversion mode 3 12 channel analog input The signal to be converted is selected using the AD converter control register ADCRC out of 12 types of analog signals that are supplied from port 0 pins and pins P70 P71 XTI and XT2 4 Conversion time select The AD conversion time can be set to 1 1 to 1 128 frequency division ratio The AD mode register ADMRC and AD conversion results register low byte ADRLC are used to select the conversion time for appropriate AD conversion 5 Automatic reference voltage generation control The ADC incorporates a reference voltage generator that automatically generates the reference voltage when the AD converter is started Generation of the reference voltage stops automatically at the end of AD conversion which dispenses with the deed to manually provide on off control of the reference voltage There is also no need to supply the reference voltage externally 3 109 ADC12 6 Itis necessary to manipulate the following special control registers to control the AD converter ADCRC ADMRC ADRLC ADRHC Address Initial value BIT5 AD CHSEL3 CHSEL2 CHSELI FES8 0000 0000 3 17 3 Circuit Configuration 3 17 3 1 conversion control circuit 1 The AD conversion control circuit runs in two modes 12 and 8 bit AD conversion modes 3 17 3 2 Comparator circuit 1 The comparator circuit consists of a comparator that compares the analog input with the reference volt
277. the HOLD mode all oscillations main clock subclock RC and PLL are suspended and bits 0 1 4 and 5 of the OCR are set to 0 When the microcontroller returns from the HOLD mode the main clock and RC oscillators resume oscillation The subclock and PLL oscillators restore the state that 1s established before the HOLD mode is entered and the system clock is set to RC Ifthe microcontroller enters the X tal HOLD mode all oscillations except XT main clock RC and PLL are suspended but the contents of the OCR register remain unchanged When the microcontroller returns from the X tal HOLD mode the system clock to be used when the X tal HOLD mode is entered needs to be set to either subclock or RC because it is impossible to reserve the oscillation stabilization time for the main clock Since the X tal HOLD mode is used usually for low current clock counting less current will be consumed if the system clock is switched to the subclock and the main clock and RC oscillations are suspended before the X tal HOLD mode is entered 2 XTIDLE must be cleared with an instruction 3 is cleared when a HOLD mode resetting signal INTO INT1 INT2 INT4 5 POINT USB bus active or remote controller reception or a reset occurs IDLE bit 0 HALT mode setting flag 1 Setting this bit places the microcontroller into the HALT mode 2 This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal
278. this bit indicates that 5100 is running 2 This bit must be set with an instruction 3 This bit is automatically cleared at the end of serial transmission on the rising edge of the last clock involved in the transfer SIOCTR bit 4 5100 continuous data transmission synchronous 8 bit control 1 Alinthis bit places SIOO into the continuous data transmission reception mode 2 this bit places SIOO into the synchronous 8 bit mode 3 This bit is automatically cleared at the end of serial transmission on the rising edge of the last clock involved in the transfer SIODIR bit 3 MSB LSB first select 1 A 1 in this bit places SIOO into MSB first mode 2 0 in this bit places SIOO into the LSB first mode SIOOVR bit 2 SIOO overrun flag 1 This bit is set when a falling edge of the input clock is detected with SIORUN 0 2 This bit is set when a falling edge of the input clock is detected during internal data communication between SBUFO and RAM with each 8 bit transfer 3 Read this bit and judge if the communication is performed normally at the end of the communication 4 This bit must be cleared with an instruction SIOEND bit 1 End of serial transmission flag 1 This bit is set at the end of serial transmission on the rising edge of the last clock involved in the transfer 2 Thisbit must be cleared with an instruction SIOIE bit 0 SIOO interrupt request enable control 1 When this bit and SIOEN
279. til the next NKREG write operation is performed The match data for these free running counters must always be greater than the current counter value When updating the match data the match register for timer 0 must be set up before loading the match register for NKREG NKCMP2 to with data Even if the same value is loaded it must be written into NKREG to start a search for a match 3 7 4 Related registers 1 This register is an 8 bit register that controls the operation of the high speed clock counter Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7D 0000 0000 R W NKREG 2 NKCAP2 NKCAPO NKEN bit 7 Counter conirol When set to 0 the NK control circuit is inactive When set to 1 the NK control circuit is active The timer 0 operation is switched to make up an asynchronous high speed counter with timer 0 being the higher order counter Counting is started by setting this bit to 1 and starting timer 0 in the external clock mode 2 bits 6 4 Match register Immediately when the counter reaches the value equivalent to timer O s match register 1 x 8 value of NKCMP2 to NKCMPO 8 a match detected signal occurs generating the realtime output of the required value and setting the timer 05 match flag Subsequently the realtime output port relinquishes the realtime output cap
280. tion capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P70 When this bit is set to 0 a timer OL capture signal is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P72 3 21 bit 5 Base timer clock select BTIMCO bit 4 Base timer clock select BTIMC1 BTIMCO Base Timer Input Clock 0 Subclock Cycle clock Timer counter 0 prescaler output 0 1 9 sek BUZON bit 3 Buzzer output select This bit enables the buzzer output fBST 16 When set to 1 a signal that is obtained by dividing the base timer clock by 16 is sent to port P17 as buzzer output When this bit is set to 0 the buzzer output is fixed at the high level fBST frequency of the input clock to the base timer that is selected through the input signal select register ISL bits 5 and 4 NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select NFSEL Noise Filter Time Constant 1 TOIN bit 0 Timer 0 counter clock input port select This bit selects the timer 0 counter clock signal input port When set to 1 a timer 0 count clock is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P73 When this bit is set to 0 a timer 0 count clock is generated when an input that satisfies the INT2 interrupt
281. to the time constant of the external capacitance 1 required Set bits 0 and 4 of the port7 control register P7 FESC to 0 0 or 1 1 to make the P70 port output open Starting discharge Load WDT with 04H to turn on the N channel transistor at the P70 INTO TOLCP pin to start discharging the capacitor Checking the low level Checking for data at the P70 INTO TOLCP pin Read the data at the P70 INTO TOLCP pin with a LD or similar instruction A 0 indicates that the P70 INTO TOLCP pin is at the low level Starting the watchdog timer 1 Set bit 2WDTCLR and bit 0 WDTRUN to 1 2 Also set bit 1 WDTRST to 1 when a reset is to be triggered when a runaway condition 1s detected 3 To suspend the operation of the watchdog timer in the HOLD or HALT mode set bit 4 WDTHLT at the same time The watchdog timer starts functioning when bit 0 WDTRUN is set to 1 Once the watchdog timer starts operation watchdog timer control register WDT is disabled for write it is allowed only to clear the watchdog timer and read watchdog timer control register WDT Consequently the watchdog timer can never be stopped with an instruction The function of the watchdog timer is stopped only when a reset occurs or when the microcontroller enters the HALT or HOLD mode with WDTHLT being set In this case bits WDTCLR WDTRST and WDTCRUN are reset 4 24 3 4 LC871A00 Clearing the watchdog timer When the power is supplied the ext
282. to vector address 000BH are generated INTOLH bit 3 INTO detection polarity select INTOLV bit 2 INTO detection level edge select INTOLH INTOLV INTO Interrupt Conditions P70 Pin Data 0 Falling edge detection Low level detection 0 1 o rising edge detecson ____________ INTOIF bit 1 INTO interrupt source flag This bit is set when the conditions specified by INTOLH and INTOLV are satisfied When this bit and the INTO interrupt request enable bit INTOIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated This bit must be cleared with an instruction as it is not cleared automatically INTOIE bit 0 INTO interrupt request enable When this bit and INTOIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated 3 5 3 3 External interrupt 2 3 control register I23CR 1 This register is an 8 bit register for controlling external interrupts 2 and 3 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESE 0000 0000 R W D3CR INT3HEG INT3LEG INT3IF INT3IE INT2HEG INT2LEG INT2IF INT2IE INT3HEG bit 7 INT3 rising edge detection control INT3LEG bit 6 falling edge detection control INT3HEG INT3LEG Interrupt Conditions P73 Pin Data No edge detection Falling edge detection 0 0 MEL 1
283. tted 3 142 The number of bytes specified in EPOTX are transmitted If the reception of an ACK packet from host fails the error end flag bit 3 in EPOINT is automatically set to 1 but the ACK flag bit 3 in EPOSTA is not cleared automatically LC871A00 Chapter 3 Table 3 18 12 Endpoint n n 1 to 4 Status Register Transition Chart EPnSTA A 1 Receive Receive Receive EPnSTA A 1 Token Response End flag STL ACK DIR ISO toggle data buffer STL ACK DIR ISO OUT Invalid 0 0 0 0 Error 0 0 0 0 Valid NAK 0 0 0 0 NAK IN 0 0 0 0 Invalid 0 0 0 1 Error 0 0 0 1 Valid 0 0 0 1 IN 0 0 0 1 4 0 0 0 0 1 0 IN NAK 0 0 1 0 NAK t 0 1 1 OUT 0 0 1 1 IN Tx 0 1 0 0 1 1 Mis Invalid 0 1 0 0 Error OUT match Valid ACK 0 1 0 0 0 1 0 0 Match Invalid Update 0 1 0 0 Error Valid Update ACK 0 0 0 0 ACK IN 0 1 0 0 OUT Invalid Update 0 1 0 1 Error 0 1 0 1 Valid Update 0 0 0 1 IN 0 1 0 1 0 1 1 0 0 1 1 0 Tx Data IN ED 0 0 1 0 ACK OUT 0 1 1 1 0 IN Bu 0 0 1 1 OUT _ Invalid 1 0 0 0 Error 1 0 0 0 Valid STALL 1 0 0 0 STALL IN 1 0 0 0 Invalid 1 0 0 1 Error 1 0 0 1 oe 4
284. uency is equal to the period of timer 6 T6 period 6 1 x 4 Tcyc n 1 2 3 Period of cycle clock 2 Timer 7 T7 Timer 7 is 8 bit timer that runs on either 4Tcyc 16Tcyc or 64 clock It can generate at pin P07 toggle waveforms whose frequency is equal to the period of timer 7 T7 period T7R 1 x 4 Tcyc n 1 2 3 Period of cycle clock 3 Interrupt generation Interrupt requests to vector address 0043H are generated when the overflow flag is set at the interval of timer 6 or timer 7 period and the corresponding interrupt request enable bit is set 4 To control the timer 6 T6 and timer 7 T7 it is necessary to manipulate the following special function registers T67CNT T6R T7R PO PODDR POFCRU Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE78 0000 0000 R W T67CNT 7 T7CO 6 0 T7IE 3 9 3 Circuit Configuration 3 9 4 2 Timer 6 7 control register 8 bit register 1 timer 6 7 control register controls the operation and interrupts of and T7 3 9 4 2 Timer 6 counter T6CTR 8 bit counter 1 The timer 6 counter counts the number of clocks from the timer 6 prescaler T6PR The value of timer 6 counter T6CTR reaches 0 on the clock following the clock that brought about the value specified in the timer 6 period register when the interrupt flag T6OV is set 2
285. uit 2 This register allows the X tal HOLD mode to be reset by an interrupt occurring in the remote control receiver circuit provided that the REMOREC2 is started for receive processing with the RM2CK set to subclock source oscillation RM2GPOK bit 7 Guide pulse receive flag This bit is set when REMOREC2 receives guide pulse normally in a receive format that is specified by setting RM2FMT2 through RM2FMTO to O 1 or 4 This flag must be cleared with an instruction RM2GPIE bit 6 Guide pulse receive interrupt request enable control When this bit and RM2GPOK are set to 1 an X tal HOLD mode release signal and an interrupt request to vector address 0013H are generated RM2DERR bit 5 Receive data error This bit is set when an error is detected while testing the received data This flag must be cleared with an instruction RM2ERIE bit 4 Receive data error interrupt request enable control When this bit and RM2DERR are set to 1 an X tal HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 151 REMOREC2 RM2SFUL bit 3 Receive shift register FULL flag This bit is set when the 8 data bits loaded in RM2SFT are transferred from RM2SFT to RM2RDT This flag must be cleared with an instruction RM2SFIE bit 2 Receive shift register FULL interrupt request enable control When this bit and RM2SFUL are set to 1 an X tal HOLD mode release signal and an interrupt reques
286. unt clock input timer 1L functions as an event counter If neither INT4 nor INT5 are specified for timer 1 count clock input the timer 1L counter counts on every 2Tcyc 3 3 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 3 5 HALT and HOLD Mode Operation When in the HALT or HOLD mode port 2 retains the state that is established when the HALT or HOLD mode is entered LC871A00 Chapter 3 3 4 Port 3 3 4 1 Overview Port 3 is a 5 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register and a control circuit Control of the input output signal direction is accomplished by the data direction register on a bit basis As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type on a bit basis Note Port 30 is temporally set low when the microcontroller is released 3 4 2 Functions 1 Input output port 5 bits P30 to P34 The port 3 data latch FE4C is used to control the port output data and the port 3 data direction register P3DDR FE4D to control the I O direction of port data Each port bit is provided with a programmable pull up resistor Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2
287. unter 4 prescaler setup register RM2CTPR 3 bit counter 5 bit register This register consists of a 3 bit up counter RM2BCT that counts the number of data bits received from the remote control a flag RM2HOLD that signals the suspension and resumption of the next receive operation and the bits that defines the count value RM2GPRI1 0 RM2DPRI1 0 of RM2CKPR in the guide pulse or data pulse receive mode The RM2BCT starts counting up when the remote control input signal is identified 0 or 1 When the receive operation is completed the number of last less than 8 bit data bits can be obtained by reading the value of RM2BCT The RM2BCT is reset when 1 The remote control receive operation is stopped RM2RUN set to 0 2 RM2FMT2 through RM2FMTO are set to give a value of 0 1 or 4 and a guide pulse is received normally following the initiation or resumption of a receive operation 3 RM2FMT2 through RM2FMTO are set to give a value of 2 or 3 and the first rising edge is detected assuming that the input polarity is set to positive phase following the initiation or resumption of a receive operation The value of RM2GPRI and RM2GPRO exert no influence on the receive operation if RM2FMT2 through are set to 2 or 3 Remote control receive prescaler RM2CKPR 5 bit counter The remote control receive prescaler is a 5 bit up counter that generates a count clock to the pulse width measuring counter RM2MJCT Th
288. use the rising edge of 9th clock has not yet occurred Return to in step 6 to continue receive processing Sending data o 3e 4 o Clear SII REC Load SBUFI with output data Clear and exit interrupt processing Send an acknowledge for the preceding reception operation and release the clock port after the lapse of SBR1 value 1 x Tcyc Perform a send operation 8 bits and set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs Go to 3 in step 7 if SITRUN is set to 1 If SILRUN is set to 0 implying an interrupt from 4 in step 7 clear SILEND and SILOVR and return to 1 in step 4 Read SBUF1 and check send data as required Note Bit 8 of SBUF is not yet updated because the rising edge of 9th clock has not yet occurred Load SBUFI with the next output data Clear and exit interrupt processing Release the clock port after the lapse of SBRI value 1 x Tcyc Return to 1 in step7 if an acknowledge from the master is present L If there is no acknowledge presented from the master 5101 recognizing the end of data transmission automatically clears SIIRUN and release the data port However a case that restart condition comes just after the event must be set to 1 before exiting the interrupt 5 is for detecting a start condition and is not set automatically It may disturb the transmission of
289. ut data of pin P07 This bit is disabled when 07 is in the input mode When P07 is in the output mode 0 Carries the value of the port data latch 1 Carries the OR of the waveform that toggles at the interval determined by timer 7 and the value of the port data latch T6OE bit 6 Controls the output data of pin P06 This bit is disabled when P06 is in the input mode When P06 is in the output mode 0 Carries the value of the port data latch 1 Carries the OR of the waveform that toggles at the interval determined by timer 6 and the value of the port data latch SCKOSLS5 bit 5 SCKOSLA bit 4 These bits are used to select the clock source that is to be sent to PO5 SCKOSL5 SCKOSL4 P05 Output Clock Source 0 0 Source oscillator clock selected as the system clock 0 1 Internal RC clock 1 0 USB frequency divided clock 1 1 CF clock CLKOEN bit 3 Controls the output data of pin POS This bit is disabled when PO5 is in the input mode When P05 is in the output mode 0 Carries the value of the port data latch 1 Carries the OR of the system clock output and the value of the port data latch CKODV2 bit 2 CKODV1 bit 1 CKODVO bit 0 Define the frequency of the clock to be placed at P05 000 Frequency of source oscillator clock to be placed at 5 001 1 2 of frequency of source clock to be placed at 5 010 1 4 of frequency of source clock to be placed at 5 011 1 8 of f
290. ut from pin P71 when P71DDR is set to 1 A 1 or 0 in this bit turns on and off the built in pull up resistor for pin P71 P70DT bit 0 P70 data The value of this bit is output from pin P70 when P70DDR is set to 1 Since this bit is of N channel open drain output type however it is placed in the high impedance state when P70DT is set to 1 A 1 or 0 in this bit turns on and off the built in pull up resistor for pin P70 3 5 3 2 External interrupt 0 1 control register 101 1 This register is an 8 bit register for controlling external interrupts 0 and 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESD 0000 0000 R W IOICR INTILH INTILV INTIIF INTHE INTOLH INTOLV INTOIF INTOIE INT1LH bit 7 INT1 detection polarity select INT1LV bit 6 INT1 detection level edge select INT1LH INT1LV INT1 Interrupt Conditions P71 Pin Data 0 0 Falling edge detection INT1IF bit 5 INT1 interrupt source flag This bit is set when the conditions specified by INTILH and INTILV are satisfied When this bit and the INTI interrupt request enable bit are set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated This bit must be cleared with an instruction as it is not cleared automatically INT1IE bit 4 INT1 interrupt request enable When this bit and INTIIF are set to 1 a HOLD mode release signal and an interrupt request
291. value matches the value of register TOPRR period 1 to 256 Tcyc Reset The counter starts counting from 0 when a match signal occurs or when data is written into TOPRR Timer counter 0 low byte TOL 8 bit counter Start stop This counter is started and stopped by the 0 1 value of TOLRUN timer 0 control register bit 6 Count clock Either prescaler s match signal or external signal must be selected through the 0 1 value of TOLEXT timer 0 control register bit 4 Match signal match signal is generated when the count value matches the value of the match buffer register 16 bits of data needs to match in the 16 bit mode Reset This counter is reset when it stops operation or a match signal is generated Timer counter 0 high byte 8 bit counter Start stop This counter is started and stopped by the 0 1 value of TOHRUN timer 0 control register bit 7 Count clock Either prescaler s match signal TOL match signal must be selected through the 0 1 value of TOLONG timer 0 control register bit 5 Match signal match signal is generated when the count value matches the value of the match buffer register 16 bits of data need to match in the 16 bit mode Reset This counter is reset when it stops operation or a match signal is generated Timer counter 0 match data register low byte TOLR 8 bit register with a match buffer register This register is used to store the match data for TOL It has an 8 bit mat
292. w wwe msg ww L mm wwmm wwe SSCS E ww E mm www wwe me ww LE me wem we SSS mwmm ww LLLI me wmm we m mmmm ww 1 LL LLLI m www we mn mwmm ww 1 L LL 7 um wwe S Qm ww Exe i ee VE s ww e mwmm wwe S mn mwmm ww L eo torr SSS me me mw mm mwmm ww m 000 0000 ww m S e we Ter mm 0000 0000 S me me vm mm rm rm c ww LLL lI I LL 1 4 LC871A00 APPENDIX I Address Initial value R W LC871A00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE7D 0000 0000 R W NKREG NKEN NKCMP2 NKCMP1 NKCMPO NKCOV NKCAP2 NKCAP1 NKCAPO FETE 0000 0000 R W FSRO eee EE FSROB7 FSROB6 FSAERR FSWOK INTHIGH FSLDAT FSPGL FSWREQ Fix to 0 Fi
293. w byte T1L 1 This is a read only 8 bit timer It counts up on every TIL prescaler output clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FEIA 0000 0000 R TIL TIL7 TIL6 115 TIL4 TIL3 TIL2 TILO 3 8 4 4 Timer 1 high byte T1H 1 This is a read only 8 bit timer It counts up on every prescaler output clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FEIB 0000 0000 R TIH T1H7 T1H6 1 5 4 2 0 3 8 4 5 Timer 1 match data register low byte T1LR 1 This register is used to store the match data for TIL It has 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the value of timer 1 low byte 2 Match buffer register is updated as follows and the match register has the same value when in inactive TILRUN 0 If active TILRUN 1 the match buffer register is loaded with the contents of TILR when the value of TIL reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FEIC 0000 0000 R W TILR TILR7 TILR6 TILRS TILR4 TILR3 TILR2 TILRI TILRO 3 8 4 6 Timer 1 match data register high byte T1HR 1 This register 1s used to store the match data for T1H It has an 8 bit ma
294. when SIIEND 1 when SIIRUN 0 SILRUN 0 SIIRUN 0 2 2 SIITEND 2 set set set conditions conditions conditions met when met when met when SHEND 1 SIIEND 1 SHEND 1 3 Start bit detected Ce 0 e Shifter data SBUFI SBUFI update Shifter at Shifter at Shifter at Shifter at beginning beginning beginning of beginning of of of operation operation operation operation Shifter gt Rising edge lt When 8 bit When 8 bit Rising edge lt Rising edge SBUFI of 8th clock of 8th clock of 8th clock bits 0 to 7 transferred received Automatic Input data Input data Input data update of read in on read in on read in on SBUFI bit 8 stop bit rising edge rising edge of 9th clock of 9th clock Note 1 If internal data output state H and data port state L conditions are detected at the rising edges of the first to 8th clocks the microcontroller recognizes a bus contention loss and clears SIIRUN and also stops the generation of the clock immediately Data input operation SIO1 It cont iv eoe perpe aro t3 P13 SBUF1 FE35h lt 101 output control P14 P14 port latch D T Clock P14 output contol lt Glock generation ee circuit 8101 output contro e gt P15 15 port latch MSB LSB first control P1 Baud rate 5 output control generator Serial transfer end flag SBR1 FE36h Overrun flag gt SCON1 FE34h
295. x to 0 rc 00000000 Rw to rur woo mae toes twez tower wooo ww tm Bw tw tono tomi rw ww 0000 tox mme tens tons tome toni tomo rw O Ee tw tm FE93 0000 0000 R W EP2STA E2EN E2TGL E20VR E2STL E2ACK E2DIR E2180 E2BNK ee rus 0000 o000 Ee tex Tm Wwe LL LL LL rw www we ru woo tiw rw 0000 tmm me tme tmu emo tme 0000 ww tmor o Ee ee Exo re woo ww tm oo Eme ems exo 1 5 LC871A00 APPENDIX I Address Initial value LC871A00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO FE9C H000 0000 R W EP3CNT z E3CN6 E3CN5 E3CN4 E3CN2 E3CN1 E3CNO ww ew emus Eo ms mar tex
296. y divided clock to the external circuitry 73NDL bit 4 Reserved bit Must always be set to 0 CF12BOFF bit 3 Reserved bit Must always be set to 0 System Clock UDVSEL2 bit 2 Frequency divided clock frequency select UDVSEL1 bit 1 Frequency divided clock frequency select UDVSELO bit 0 Frequency divided clock frequency select 1 These bits are used to select the frequency of the frequency divided clock derived from the USB 48 MHz clock 2 The bits must be set to a value between 8 to 16 MHz when the frequency divided clock is to be supplied as the system clock 3 When changing the frequency divided clock setting from a value other than its initial value UDVSEL 000 temporarily turn on the frequency clock suspended state UDVSEL 110 then set a new value Example Changing the frequency divided clock frequency from 12 MHz to 8 MHz UDVSEL 100 110 011 Frequency Divided Clock Frequencies UDVSEL 2 0 Frequency MHz 000 4 001 4 8 010 6 011 8 100 12 101 Inhibited 110 Frequency divided clock suspended 111 16 4 2 4 6 System clock divider control register CLKDIV 3 bit register 1 The system clock divider control register controls the frequency division processing of the system clock Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO HHHH H000 CLKDIV t CLKDV2 CLKDV1 CLKDVO bits 7 to 3 These b
297. y for low current clock counting less current will be consumed if the system clock is switched to the subclock and the main clock and RC oscillations are suspended before the X tal HOLD mode is entered 2 XTIDLE must be cleared with an instruction 3 is cleared when a HOLD mode resetting signal INTO INT2 INT4 INT5 POINT USB bus active or remote controller reception or a reset occurs 4 BitO is automatically set when PDN is set IDLE bit 0 HALT mode setting flag 1 Setting this bit places the microcontroller into the HALT mode 2 Thisbit is automatically set whenever bit 1 1 set 3 Thisbit is cleared on acceptance of an interrupt request or on receipt of a reset signal 4 2 4 2 Oscillation Control Register OCR 8 bit register 1 oscillation control register is an 8 bit register that controls the operation of the oscillation circuits selects the system clock and read data from the and XT2 pins Except for read only bits 3 and 2 all bits of this register can be read or written Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FEOE 0000 XX00 R W OCR CLKSGL EXTOSC CLKCB5 CLKCB4 XT2IN XTIIN RCSTOP CFSTOP CLKSGL bit 7 Clock division ratio select 1 When this bit is set to 1 the clock selected by bits 4 and 5 is used as the system clock as is 2 When this bit is set to 0 the clock having a clock rate of 2 of the clock selected by
298. y time the REMOREC2 receives 8 bits of data At this moment the REMOREC2 sets the RM2SFUL flag and resets the RM2SFT 3 If the data pulse goes out of the valid criterion value range the REMOREC2 sets the RM2DERR flag and returns into the idle state waiting for a next rising edge 4 The number of received data bits is counted by the RM2BCT When receiving the number of data bits that is not an integral multiple of 8 the REMOREC2 references this value at the end of reception to determine the number of valid data bits in the RM2SFT 5 When the REMOREC2 detects the end of reception condition it sets the RM2REND and RM2HOLD flags and suspends operation Subsequently when the RM2SFT is read the REMOREC2 clears the RM2HOLD flag and enters the idle state waiting for a next rising edge resuming the receive operation 3 19 5 4 Receive operation when receive format D is specified Receive format D outline Guide pulse None Data encoding system Manchester Stop bits No 3 158 LC871A00 Chapter 3 Example of a receive format D receive operation positive phase input RM2RUN set to 1 P73 RMIN Data Data Data i Data i un d Poco Pot Poco Poco Check end of reception Timing 3 Timing 4 sampling End of reception detected Overflow detected RM2MJCT count value Edge detected Edge detected Timing 1 Timing 2 End of Count start Count reset amp sampling Judge reception start

LC871A00 SERIES USER`S MANUAL

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