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1. VERSION 1 3 X REV MODIFIED BY DATE DESCRIPTION x A DAVID M SENDEK 29 SEPT 87 INCLUDE A MONITOR PROMPT INCLUDE BUFFER FULL m CONDITION DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES ECHO1 CONSOLE ASM x K kk k K k k Kk K kk KKK KKK KKK KKK KKK K KKK KKK KKK XK xxx xxx xxx xx xxx xxx KKK KK GLOBAL BKPTMSG EPROMSG ERRMSG HEXMSG ILLMSG GLOBAL MONMSG REGERR REGMSG SREC_ERR USEMSG GLOBAL MESSAGE PROMPT BUFFULLMSG SPCE EXTERNAL ECHO1 CR EQU 50 ASCII CODE FOR RETURN LF EQU SOA ASCII CODE FOR LINEFEED NULL EQU 00 ASCII CODE FOR NUL MESSAGE MOVE B A5 D0 MESSAGE CHAR INCREMENT POINTER BEQ S MSGRET IF CHAR NULL THEN EXIT BSR OUTPUT CHAR TO CONSOLE BRA S MESSAGE GET ANOTHER CHARACTER MSGRET RTS BKPTMSG BYTE BREAKPOINT TRAP AT BYTE NULL ERRMSG BYTE ERROR RE ENTER CR LF BYTE NULL EPROMSG BYTE ATTEMPTED WRITE TO EPROM CR LF BYTE NULL HEXMSG BYTE CONVERSION ERROR RE ENTER CR LF BYTE NULL ILLMSG BYTE ILLEGAL INSTRUCTION TRAP CR LF BYTE NULL MONMSG BYTE 68010 MONITOR V1 3 CR LF BYTE WRITTEN BY DR LARRY ABBOTT CR LF BYTE 8 COPYRIGHT 1986 CR LF BYTE NULL REGERR BYTE REG
2. FILENAME 5 Kk xxx xk KKK KKK xx kx xx xk xxx xxx xk KKK KKK KK xxx xxx xxx xxx xxx xxx xxx VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION DAVID M SENDEK 1 87 DOCUMENTATION UPGRADE K Kk k K K K k 7 k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES HEX ERR MAIN ASM MONSTAT MAIN ASM kk Kk K kx XK xxx xxx xxx Kx xk xxx xxx xxx xxx xx KKK KKK KK KK xxx Kx xk xxx KKK GLOBAL HEX CONV EXTERNAL ERR MONSTAT HEX CONV 508 8 30 D0 ADJUST ASCII TO HEX BASE CMPI B 9 00 IS CHARACTER lt 9 BLS S ZERO CHECK YES CHECK gt 0 SUB B 7 D0 ADJUST FOR A F CMPI B A D0 1 gt BCS S HEXERR HEX ERROR 0 IS CHARACTER lt F BHI S HEXERR NO HEX ERROR ZERO CHECK CMPI B 0 D0 IS CHARACTER 0 BMI S HEXERR NO HEX ERROR BSR HEX SHIFT HEX INTO HEX BUFFER BCLR B ERR MONSTAT CLR HEX CONVERSION ERROR STATUS BIT BRA S EXIT EXIT HEX CONVERSION HEXERR BSET B ERR MONSTAT SET HEX CONVERSION ERROR STATUS BIT HEX EXIT RTS HEX SHIFT LSL B 84 00 SHIFT L S NIBBLE TO M S NIBBLE MOVE W 3 D1 SET FOR INDEX TO 4 SHIFTS NIBBLE SHF LSL B 1 00 SHIFT HEX CHARACTER OUT ROXL L 1 D2 SHIFT INTO HEX BUFF
3. WRITTEN DR LARRY ABBOTT APRIL 24 1986 x x x x x FILENAME DOWNLOAD ASM VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION LARRY ABBOTT 12 18 86 INIT DEBUG PROCESS DAVID SENDEK 1 OCT 87 DOCUMENTATION UPGRADE CORRECT FOR MC68681 DAVID M SENDEK 5 OCT 87 BCLR BSET ASSEMBLY LANGUAGE CORRECTION D DAVID M SENDEK 4 JAN 88 CORRECT DOWNLOADING OF 51 59 FORMAT RECORDS NOTE FINAL 9 RECORD WILL HAVE AFTER LAST CHARACTER IN THE RECORD Kk k k k Kk k k k k k k k k k k k k k k Kk k k k Kk k k k k k k k k k Kk K k k k k k k k k k k k k k k k k k K k k k k k k DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES CHECKSUM MAIN ASM CK SUM MAIN ASM 1 CONSOLE ASM 2 CONSOLE ASM EPROMRNG MAIN ASM EPROMSG MESSAGE ASM EPROMWR MAIN ASM HEXCONV ASM IO UTIL ASM ERR MAIN ASM SREC ERR MESSAGE ASM 5 MESSAGE ASM 5 2 501 5 MESSAGE MESSAGE ASM SPACES IO UTIL ASM MONSTAT MAIN ASM SRB MAIN ASM RECFULL MAI
4. OL OL Z SNQGWA 1 SLNINWNOD aNd 26189825 3534 D 114538 S NA 2 ES 4104 T e 50714 8 Sana 8 MEV 8 NN3G C TOTT C 9100 09M0 L NNZIWA MM M MM315VM KUUIGT 99 NN3SO N32VIGOT1 6 NTISATS KATS pe32euuo JON 2439 OL ON ZT 12 3 SinBra epooeg 55 247111 Wwud 3104 1904 OL p9LAbL JO 2 BUTT ASanbay L 2 WO13 SLNSWINOO 0 ANANI LNANI TAANI 1 MI 1 M1 xCOTHP9LSO LhdNI indNI ANANI Em ER 2 X12 1 4M1 ZG d JO abeg 5 5 5 ATLIL Wwud IJTNDITD 4L18S3H LIVH OL 1 cy 5 OL 55 5 OL IJTNDITD ABT TOAAW OD OL
5. MOVE L ADDRESS MOVE W 16 A0 RESTORE INSTRUCTION LEA BKPTMSG A5 SET BREAKPOINT MESSAGE BADINST BSR MESSAGE PRINT MESSAGE MOVE L A3 D0 GET BKPT ADDRESS MOVE W 3 D3 SET BYTE INDEX ADDROUT ROL L 8 00 ROTATE DO BY 1 BYTE BSR OUTPUT BYTE CRT D0 lt 0 7 gt DBF D3 ADDROUT MORE ADDRESS THE LOOP BSR SCRLF MOV CURSOR TO STRT OF LINE SUBQ L 42 2 SP ADJUST RETURN ADDRESS MOVE L SP SYSTAX SAVE POINTER TO RETURN ADDR EXAMINE BSR GETSTRING ALLOWS EXAM AT BKPT BCLR B STRINGEND MONSTAT END OF STRING BEQ EXAMINE NO SO LOOP BCLR B STRING MONSTAT CLEAR NEW STRING FLAG BSR CMD_DECODE IF END THEN DECODE BCLR B CONTINUE MONSTAT IS THIS A CONTINUATION BEQ EXAMINE YES LOOP AGAIN RTE END K k k e code k oko oe oe oe oe ode oe oe oe oe eoe oe eoe eoe eode obe eee oe e ke ke oe oe eoe oe e eee ek e e n x x Xx X xx THIS FILE CONTAINS PROGRAMMING STUBS TO COMPLETE THE LINKING PROCESS WHILE BUILDING AND TESTING HIGHER LEVEL MODULES WRITTEN BY DR LARRY ABBOTT K k kk X oe oe X XX XXXXXXXXX X X XXXXXX X X XXXX XX X X X X XXX XXX X X X XX XX FILENAME STUB ASM KKK X X XXX oe eoe dee KKK oe oe oe oe oe eoe oe oe ok coe oe oe c0 oe 0e e ce e 0x eG e x e Xx xx kx x kx x kx ox kx kk kx kk VERSION 1 3
6. 013 5 SINAWWOO OT 6 8 L 9 5 2 1 v 14 12 179 1 9 S 27417 IV 91 81 144 t JOIE 251 5t post 1 AGS x A40 LG ez a 8306143 JO 2 IJINIITD 5 2 5 ATNOATO 2 3 AILIL MOM 14 1 AS XGQLSAS 1041 2081 EOHI P HI 5031 9081 1 ano LVONIS 27208 scua 100608 100294 NIZDA NII5G8 110078 NI058 TIV32V eW 128 vASGA N P EN ES ES gt x LNOXDG x IIVdJOV 9 410 154 JO 5 5 3 1995 2N 41111 12411 19 VV25 IV 2 14 1 ER A EN TERE 2222 RRR 913534545 4438 91143535 ANI sta vita C10 110 010 60a 900 SIVD 849 6179 x NIINA 8Wd 9 6140 9IV 9145 14548515 x Vida 6073 T 5 4 614 ON ON ON ON NI AJ NJ CV 83051L4
7. 30us eugo 119 O 5 3SILIL JON ON PUB OL Z OL gt S AS 5595 V67LI ANI 5025 0 2 19151391 2032111550 5295 0006 THW 9T ON 120 bp oanbtg SSIIPPY 5 41114 JON pue 4 WVuS OL OL LUVNG 189899 V 0 pue IJINDITD WOW OL uoi 01643 SV 1 0 1 C7V 0 1 L M1 ANANI 1 M1 ANANI 1 M1 x NHIWOMH 1 M1 LOGNI ANANI 312 1naNT ON b 2 T gt SLNSNWNWOO 121 679 eunbtd pue u 3s S 1114 9013 55 Aiijrno4TO Z OL 1 SLNSWWOO s 500 0 AS VIISTIL SOSTPL XC snz Aetea 999
8. 134 4d TOINDU P 5 pue LASTA PUB 3414211 OL OL 2 1 SLNIWNWOD x LISJASAS CF 3 1 5051V 19539 lt 79534 azz 9 T Hhutounogsgq 2858 ANI uorqo uuoo 30us euo 37111 JON ON IJTNDITD PUB VL 0 OL 2 pue 110d Tend OL 1 SLNHNWOO AS Az 1 5585 lt ZHW 8 ANI 2 5595 4066 lt ZHN 1915174 T ZHN 91 203111250 5095 U00S lt ZHN C 29 91 i 5 771 ON 595 01 lt ZHW 1 ui oec 91 1 I6 7 ON 136 974 8X C6 6LI 3 sng 001 ILIL JON pue 5 OL 91498034 wwus
9. OL 56189 26 3929735 NWW OL TSPB89DW 199795 4142 OL LYWNG I1898920W A131024110 2 1 PU WONHdH OL WOU KAT LADITD MAAG pue IJTNDITD 1977013U0D9 OL 785210059 330 OL 1 9 JO BUTT 3senbey 399795 01643 01643 ot 4 xSVd 0 1 0 1 O I O I INANI 1 MI 1 M1 0 1 1 M1 ON 9 ON O I 1 MI C 16759 81 0 1 1 M1 ON 0 1 1 M1 E 18955 0 1 1 M1 0 1 1 4 M1 0 1 10481 x 09V099930 L T 1034791595 O I 10401 0 1 IndNI ANANI 10481 INANI 10481 M1 273 LNGNI M15 1 4M1 122222072720 22272722200 gt SLNGWWOD ON 8 L 9 8 L 2 T 134 AGt JO atun 2 ATLIL D SY 2 5051V x UO gt SV i O a C t id 21 lt 5 1 21744 1959 M D LdSdH L M a 57 LM 7 6 V 224 2 454 094 151 2 98 2 024 21 gave
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11. 103 ST 340d 202 ST 13104 ON m x 53544 JON ON 18959 OL ON x LESAN word OT ON ER LW 1X uoad 6 ON Teuruz r 8 ON uo3sAg LV LX OL 4 pe oL 9 ON EE 34 OL 6 ON CJ KIITADITD xMOVLG OL 6 ON ON 2 ON 5 x T89HOWI T ON 189041 SINSWWOO M u se 8945 10 L z m I 2 6 teri ER 9 a A 8 gt 68 were X 0L TW ang 3401 lt ol APPENDIX D MINIMAL SYSTEM S PROGRAMMABLE LOGIC DEVICE SOURCE CODE In order to reduce the chip count Altera EP310 erasable programmable logic devices EPLDs were used within the minimal system Abel a logic software design tool by Data 1 0 Corporation was used to program Altera EP310 EPLDs Ref 16 pp 2 57 2 62 Abel files provides a high level representation of the logic to be implemented on the EP310s The EP310 comes in a 20 pin package Nine pins are used strictly for input logic one pin can be used for input
12. ERR MONSTAT SN EXIT MOVE W D2 D4 SUB W D3 D4 SUBQ W 2 04 MOVE W D3 D6 IS CHARACTER S NO SEARCH FOR A S ECHO S TO CONSOLE SET FOR 16 BIT ADDR GET A CHAR FROM DWNLNK PORT ECHO DWNLNK CHAR TO CONSOLE IS THIS A 0 RECORD YES GO TO S RECORD IS THIS S1 RECORD YES GO TO S RECORD IS THIS S9 RECORD YES GO TO S9 RECORD SET FOR 24 BIT ADDR IS THIS A S2 RECORD YES GO TO S RECORD SET FOR A 32 BIT ADDRESS IS THIS S3 RECORD YES GO TO S RECORD IF NO Sxx RECORD THEN S RECORD ERROR MSG ECHO CR amp LF SET UP ATTEMPTED WRITE TO EPROM WAS THERE A WRITE TO EPROM YES PRINT ERROR MESSAGE PRINT ERROR MESSAGE PROCESS S RECORD IF NOT HEX CONVERSION ERR THEN GET NEXT RECORD ELSE HEX CONV ERROR MSG PRINT ERROR MSG PROCESS S RECORD IF HEX CONVERSION ERROR THEN TERMINATE XMISSION SET FOR 1 BYTE CLEAR CHECK SUM GET DOWNLOAD FIELD IF HEX CONVERSION ERROR THEN EXIT SN RECORD D4 HEXBUFFER S REC LEN LEN S REC LEN ADDR ADJST FOR DBF INST amp ADDR SET ADDRESS SIZE BSR GETFIELD GET ADDRESS FIELD BTST B HEX_ERR MONSTAT IF HEX CONVERSION ERROR BNE S 5 EXIT THEN EXIT SN RECORD MOVE L D2 A0 A0 LOAD ADDRESS BSR DOWN DATA GET DOWN LOAD DATA SN EXIT RTS DOWN DATA BSR GETCHR2 GET FIRST CHARACTER BSR ECHO2 ECHO DWNLD CHARACTER TO CONSOLE CLR L 02 BSR HEX CONV CONVERT CHAR TO HEX BTST B HEX_ERR MONSTAT IF HEX CONVERSION E
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14. 20 Mapping Mechanism esee emolumenti etenim 21 Dyal ported Memory 22 System BIOGK 25 Minimal System 31 MC68010 Signal Groups vene epe Eco decem gres 70 Minimal System MC68010 Microprocessor Circuitry 118 Minimal System HALT and RESET Generation Circuitry 119 Minimal System Clock Generation Circuitry 120 Minimal System Address Decode Circuitry 121 Minimal System DTACK and BERR Generation Circuitry 122 Minimal System EPROM and SRAM Circuitry 123 Minimal System Interrupt Request and interrupt Acknowledge Circuitry mee ost mee 124 Minimal System Dual port Receiver Transmitter Serial POLE Circuitry e eem eee 125 Master Circuit Board Functional Block Diagram 132 System Controller Circuit Board Functional Block Diagram 7 10 Ll 12 13 14 15 6 17 18 19 20 21 22 23 24 MC68010 Microprocessor Circuitry 57 RESET Generation Circuitry 135 Clock Generation Circuitry 136 Local Bus Address Decode Circuitry 137 Memory Management Unit Circuitry Page 1 of 2 138 Memory Management Unit Circuitry Page 2 of 2 139 Dual port DRAM Controller Circuitry Page 1 of 3 140 Dual p
15. 5 uopuey TTLIL t JO Z OL Z 181 I9 0 0 1 TT gt SLNAWWOD CTAS 251IVL yyzSTpL eSVITET SVIIGA 5 8VN 2 SWOTEN 2 SWA Ld 04 2 M x SVO IH I 143 8VN OV x SVOTIN x SWA La 00 JM x SVO IA I CT a Jo 2 wopuey oTweudq ATLIL JO gt LNSWWOD 144 Pla oanbtg JON ON P JO 1013 400 oj ssoooy orueuAG wTLII JO abeg OL Z AIYIMIATD 1 TSS Tt gt SLNAWWOD TAS bb S IvL 145 2 8 c Sonan 2 5V c 518 2 SONET OWN xSVOnan x SWYN SIG 80 x SVO Gl a 6 JO sTLIL H e e JO 1 LN3NWOD n ne lt lt 8 24 y 146 9174 oJunbrJ WWUS pue ITLIL
16. the EPLDs were programmed EPLDS were bread boarded while determining with reasonable certainty that the devices were actually implementing the desired logic The ultimate goal in this thesis was to implement the master circuit board subsystem design One of the steps to achieve this goal requires the memory management unit MMU to translate a virtual address to a physical address To avoid significant wiring 60 modifications to the minimal system to build up to the master subsystem the MMU was wire wrapped into the minimal system design However the MMU was not programmed at the minimal system stage The MMU translates a virtual address to the same physical address when the MMU is not programmed after being reset The MMU was configured to accommodate an automatic manual and programmed CPU reset instruction reset SUMMARY AND CONCLUSIONS A SUMMARY The goal of this thesis was two fold first to explore hardware ramifications of designing a microprocessor system for a multi processor environment and secondly to implement the minimal system design 1 Design Concepts In exploring hardware ramifications the scope was limited to features of the VMEbus structure in memory management and interrupt control The memory management features included memory protection dual ported memory and virtual memory a VMEbus Structure The VMEbus permits an exchange of data and control beyond the bound
17. sng Z 8 TSSS5VT t Nag WAIS P 1880HI 5 5SLNSWWOO ON 178 i I 18932410 9 seri EA gt 8174 21NPT4 340119301 AILIL oe 41141 ce 29081 40141 S0u1 SONDVI A 9t OI xISPOMNI L 89 vOuT s Ou1 90 cout sa 10811 gt SASI ta 8 451509 HOWId 32VI8 eLOUl 90u1 0d II x GG INOVLG xL 3544 ZHW 8 Vd 5 2 35 2 P HI LISIN E HI 315 I0 I CV LOYI IONI 9 IHN ev eNOVIT 1 OL 21 55359 39 0L LI IJTNDITD NWA uoi OT LYWNA OL 6 800280 55 sng 8 L V L snqgwA 9 pue OL S xMOVLG OL t IJTNDITO 14544 wow 2 1 SLNINNOI ZI TSpHOW VI 6L 4 1971 1013400 6 L 8
18. 3 System Controller Circuit Board a Bus Arbiter The VMEbus arbitration circuitry Fig E 25 provides the logic to arbitrate prioritized bus requests in parallel Each bus request is then daisy chained down to the requesting device Each subsystem capable of VMEbus access must have the ability to provide a bus request at one of four priority levels The highest priority signal used is DBG7 while the lowest priority level Signal used is DBG4 The process of resolving the VMEbus requests was described in Chapter II Since the MC68452 bus arbitration module BAM Ref 8 is an asynchronous device the bus grant Signals DBGx are not guaranteed to be spike free Consequently a 50 nanosecond delay circuit is used to disable the DBGx signals during the parallel arbitration process b System Reset The system reset circuitry Fig E 26 provides a system wide master reset This signal is sent on the VMEbus to all Circuit boards and it is used to reset the entire system much like the local reset discussed earlier in this chapter c VMEbus Drivers The circuitry for the system controller drivers Fig E 27 provides the drive capability for signals to from the VMEbus Since circuitry was not designed to detect an AC power failure the ACFAIL signai is never asserted This signal is input to the non maskable interrupt of the interrupt handler Fig E 17 The bus Clear BCLR signal informs the current bus master that there is 57
19. REV MODIFIED BY DATE DESCRIPTION A DAVID SENDEK 1 OCT 87 DOCUMENTATION UPGRADE INCORPORATE PROMPT MSG Kk k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k X k X DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES PROMPT MESSAGE ASM MESSAGE MESSAGE ASM MX X X eoe oe eoe e o0 eoe oe e oe 00 eee oe o ok ko k kk kXkkk GLOBAL BKPT LIST NO BKPT EXTERNAL PROMPT MESSAGE BKPT_LIST LEA PROMPT AS BSR MESSAGE RTS NO_BKPT LEA PROMPT AS BSR MESSAGE RTS END KKK THIS ROUTINE PRINTS OUT THE CONTENTS OF THE REGISTERS x kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkxkkkk kk WRITTEN DR LARRY ABBOTT X X X X X X X X X XX XXX XX X X XXX X X SS SSS FILENAME REG ASM x K K X X k k k X k k k k X K k k X XX K XX k XX XX XX K k K k K K K K K K K k k K K K K K K K K K K K K K K K K K VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION DAVID SENDEK 1 OCT 87 DOCUMENTATION UPGRADE x DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES MESSAGE MESSAGE ASM SCRLF IO UTIL ASM OUTPUT BYTE BYTEOUT ASM
20. Figure 2 3 Master Slave Subsystem they also prevent access from the VMEbus to shared slave devices when the appropriate control signal is asserted by the bus 13 controller Whenever the local master in this case the CPU is accessing the shared slave devices these devices become a local asset As discussed in the master only application the bus controller preserves the VMEbus protocol 4 Arbitration Protocols Arbitration protocols ensure conflict free access to the system bus from all subsystems and are crucial in a multi processor environment Ref 6 p 100 An arbitration protocol ensures that only one bus master has access to the bus at a time thus safeguarding the bus from collisions in which information is transferred on the bus by multiple sources The VMEbus supports both serial and parallel arbitration schemes or a combination of both methods These two method are described in the following paragraphs Daisy chaining is a method of arbitrating a shared communication bus by serial prioritization Figure 2 4 illustrates daisy chain arbitration If the bus is in use any subsystem requesting ownership must wait till the present bus master relinquishes control of the bus A Subsystem requests access to the bus by asserting the bus request BR signal The bus arbiter or other controlling device acknowledges the bus request by asserting a bus grant BG signal to the bus grant input BGIN of SUBSYSTEM1 the first sub
21. INITIAL STACK POINTER DEFINITION OF MONSTAT MONITOR STATUS WORD EPROMWR EQU 0 WRITE TO EPROM FLAG ESCAPE EQU 1 ESCAPE FLAG CONTINUE EQU 2 CONTINUATION FLAG FOUND EQU 3 CMD FOUND FLAG ERR EQU 4 HEX CONVERSION ERROR MODIFY EQU 5 MEMORY MODIFY FLAG STRING EQU 6 STRING BUILDING IN PROGRESS STRINGEND EQU 7 END OF STRING BUILDING CHECKSUM EQU 8 CHECKSUM ERROR FLAG X 68681 EQUATES x RECFULL EOU 00 SRA 0 1 gt RECEIVE FIFO A CHAR XEMPTY EQU 02 SRA 2 1 gt XMIT HOLDING REG EMPTY MR1RFSET EQU 1 RESET REG PTR amp DISABLE XMIT RECV CLK_SRC EQU 30 XTAL 16 CLOCK CONF_1AB EQU 13 8 DATA NO PARITY CONF 2A EQU 07 1 STOP BIT CONF 28 EQU 0F 2 STOP BITS BAUD2400 EQU 88 2400 BAUD BAUD9600 EQU BB 9600 BAUD EN_PORT EQU 45 RESET ERROR ENABLE XMIT amp RUPTMASK EOU 02 ENABLE READY RUPTVECT EQU 40 USER INTERRUPT 0 VECTOR x 68681 REGISTZRS CRT lt PORT A 9600 BAUD 8 DATA BITS NO PARITY 1 STOP BIT DOWNLOAD lt PORT B 2400 BAUD 8 DATA BITS NO PARITY 2 STOP BITS OPCR INIT EQU EQU EQU EQU EQU EQU EQU EOU EOU EOU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU CODE LEA CLR W MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B 57 7000 DUART DUART 10 DUART A4 MONSTAT BASE ADD
22. a higher pending bus request Burden is placed upon the current bus master to either relinquish control of the bus or to continue control until its task is completed For the sake of simplicity the master circuit board subsystem was designed to relinquish control upon the completion of its task Finally an IACK daisy chain driver is provided for VMEbus interrupts RESULTS Once the minimal system and fully integrated system hardware was designed the schematic drawings drafted and the pin out list implemented software support was required to implement the minimal system The monitor debugger program required a thorough check of all its software features These software features include the capability to set and remove a breakpoint to display and modify memory to display and change registers to start program execution and to down load software from a development system It was discovered while debugging the down load portion of the monitor debugger program that the 2500AD 68010 cross assembler s linking process incorrectly resolved external references The lirking process generates a file in the Motorola S record format The problem was isolated only after comparing the Motorola S record to Motorola s instruction format It was identified that the 2500AD cross assembler was improperly resolving external references A corrected version of the 2500AD cross assembler was obtained from the vendor that resolved this problem With
23. 294 004 4 27 vavd Uv etw 138 u E 11111111 4 z bt tc Std TT M gt EA ER BA CU ted 944 T 815953 9 2 8 14 1 V IL5VX5VL0 en San esu i 8 S ER 8 819 541 154 i 4 tw CV 8 oanbtg OL 91 2 30 355 OL GT t 30 7 atun aueuefeuew 47111 OL PT s urT ss appv burairnbey OL sago13S OL 71 135 5 ue OL TT Z JO 01 2 JO 01 6 4 JO z abeg 1 8 4 13534 L 4 9 G y IJINDITD 0 14 OL i 9 OL G Z f 55 sng T SLNSJWWOO xSWW OT 107 19499 240175 Ssedppv post xSQI 2 23 21
24. VOTJILIJIGIV SNGINA 371111 5105 eee ene OT dr mCE xL 9d x99ad G9dG xb odd ZS 8924 9 tz pe32euuoj3 JON 5 OL uoi 9 x Saga VAGA H Al NT 5 AS xWIOd 7 ON 2 gt SLNAWWNOD 156 9 uorqez u 5 4 LSSSHSAS 1111 OL LNSWHWOO Oe IT 5051V NET AG ANI peu U231AS 32594 L SJUSAS 157 AS 1274 eanbrd 19710134U09 5 5 41114 2 8 MOM 14 1 AS KAALSAS 21 TOHI scout Tov EOHI tov vov 6081 504 9081 90V L HI LOV ANI V0VM3 100X5VI sNIWOVI AIVI 5 ano NIVLA 158 135385 6 s MH3H LAOCIA IIV3SAS NISA 100299 510 NIZD8 via 100194 oNITOS 210 100058 TG 61028 010 11 32 60a W128 800 15998 WWA OL 5 AAAINIATD 1 5 5 314 Z SLNGWNOD N I 10 11 12 13 14 LIST OF REFERENCES Stone H S High Performance Computer Architecture Addison Wesley Publishin
25. indicates that the data being transferred is on an odd byte boundary When UDS and LDS are both asserted a word 16 bits of data is being transferred The UDS and LDS 70 signals together determine address bit A0 thus giving an address range of 16 megabytes for the CPU The UDS LDS and R W signals control the flow of the data on the data bus as illustrated in Table III Ref 18 p 4 2 Finally the data transfer acknowledge DTACK signal informs the CPU that the current data transfer has been completed by the peripheral device or memory location addressed TABLE III DATA STROBE CONTROL OF THE DATA BUS UDS LDS 10X0 0 VALID DATA BITS NO VALID DATA BITS VALID DATA BITS VALID DATA BITS NO VALID DATA BITS VALID DATA BITS VALID DATA BITS NO VALID DATA BITS VALID DATA BITS VALID DATA BITS VALID DATA BITS 0 7 VALID DATA BITS VALID DATA BITS VALID DATA BITS 8 15 These conditions are a result of current implementation and may not appear on future devices 4 Bus Arbitration Control As a group the bus arbitration control signals provide a mechanism for the CPU to give up control of the bus However these signals do not determine directly which alternate bus master gets control The bus request BR signal is a Signal generated by a device or devices requesting access to the bus The bus grant BG is a signal from the CPU indicating that it will release the bus at the end of the current
26. 6 251 215190 TT NOVLVG TT 9 6 2145 6 LL TT 1173 JO ATLIL SVO etTqeug 549 atqeug SVO SVO pejoeuuo JON a1addn xueg XU H I9MOT xueg xueg 05754 Jo Z OL 4MOVLO OL 8 8 8 xSWOTEN 8 AS xSWOTET xSWONdT STONEN et 21 et et Wd ndo OL 19717013U09 SnqgwA OL JO uoa OL WO13 Jo ebed OL 5 SnqdWA xSWOTET 800280 xSWondn 5531 9 sng xSVO Idn 0014 ANN C Fr C eid 6 a PT xS nd 6 ST pT T ZT LL 00 6 8 L 9 6 5 2 S LNAWNOD 214 oanbtg JON ON JO t AST Tor uoD OL
27. INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT 1 INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTCR VECTOR VECTOR VECTOR VECTOR VECTOR LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG END UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UN
28. Ref 2 pp 220 223 When it is ready to service interrupting device the processor saves its current state and then performs the servicing tasks When the servicing tasks are completed the saved state of the processor is restored and the operation prior to the interrupt is resumed Consequently the processing power of the processor is increased because the overhead from polling peripheral devices for a service request is eliminated In a general sense a generic multi processor system can be viewed as illustrated in Figure 1 1 Various subsystems such as data processing storage and data communications are integrated along a system bus to make up a complete system Each subsystem is comprised of memory I O and processor modules configured to accommodate the unique requirements of the users of the multi processor system A system controller acts as the arbiter for the entire system The system controller directs the information flow much as a traffic policeman directs traffic between the various subsystems along the system bus to ensure that the system is properly coordinated In order for each subsystem to have access to the system bus logic must be incorporated within each subsystem to allow it to interface to the system bus The main thrust of this thesis is to explore the concepts of bus structure memory management and interrupt control These concepts are addressed in a greater depth than would be possible in a classr
29. bus arbiter interrupt handler hardware and dual port dynamic random access memory DRA controller The following discussion presents a broad overview of the VMEbus structure and memory management This should facilitate understanding of the concepts that are incorporated into the final system master circuit board design A VMEbus SPECIFICATION 1 Background The VMEbus specification originated with Motorola s 68000 microprocessor products The 68000 series was introduced to the marketplace in the late 1970s using the VERSAbus specification In the early 1980s Motorola s European Microsystems group in Munich Germany introduced the Eurocard version of the VERSAbus referred to as the VERSAbus E specification A joint agreement was reached to adopt the VERSAbus E as the baseline bus specification for Motorola 68xxx devices with Mostek and Signetics as second source suppliers of the 68xxx family of devices The VERSAbus E was renamed the VMEbus The VMEbus specification Ref 4 delineates the mechanical and electrical characteristics of the bus and the protocols to interface devices on the VMEbus 2 VMEbus Description The VMEbus offers a versatile combination of timing strategies and support features It also offers several data transfer sizes several addressing modes and several arbitration methods The VMEbus is an asynchronous non multiplexed bus that accommodates 8 16 and 32 bit data transfers Ref 5 Asynchronou
30. gt gt 0 2 5 x Gt 21 Z L3 34 NIM OT 91 entre AIITNDITD 10321343 2901935 5 139 674 DINDTA JO ebeg IJTNIITD 2371111 ON 9 NASVI L ZHW 8 P 9 50 x 145 S1 8 9 9 5414 9 5404 9 AS Sam S 5009 S 9 6 6149 8IND LIV SSS SSS SS 9 IV KD t 5t CI ptt 229221 EE 23 asa im ass 11 6 9 AKI t 8 9 I IND N3SV2 459 2034 2135 R 8 te 8 8 8 8 9 8 0 z 1 9 t t t 6 8 t 9 v v v v v v 5 lt 5 X 42 135 2 1 V v x 9 SV ZHW 8 Y 1039379155 1135 61 PT 8 hi D KID E 75 f 5414 T H 5404 T xM H 2 N 6 T 8tVd LlVd 1 LEN SEN T EN 8 9 6 gt LL 140 0 TA z Wwud 72517
31. 13 14 15 16 17 18 19 ASSIGNMENT STATEMENTS h 1 x H H I 1 HIGH 0 LOW DONT CARE DEFINE ESET TONS NOTE amp rw rw EQUATIONS weu34 rw weu35 rw oehb rw toelb rw amp END output enable write enable INVERSION Abel V2 must be used for this device THIS FILE USES DATA I O S ABEL DESIGN LANGUAGE TO GENERATE A JEDEC FILE TO PROGRAM AN ALTERA EP310 ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD MODULE interrupt controller FLAG 1 TITLE INTERRUPT CONTROLLER FOR THE MINIMAL SYSTEM THIS IS NOT UPWARDS COMPATIBLE FOR THE FULLY INTEGKATED SYSTEM 100 DEVICE E0310 Abel V2 must be used for this device DEFINE LABELS ASSOCIATED WITH INPUT AND OUTPUT PINS FOR THE EP310 INPUT PINS al a2 a3 as irq681 fcl fc2 fc3 PIN 1 2 3 4 5 6 7 8 OUTPUT PINS iplO ipll ipl2 irack681 PIN 16 17 18 19 ASSIGNMENT STATEMENTS h 1 HIGH l 0 LOW X Kot DONT CARE DEFINE EQUATIONS NOTE INVERSION amp AND OR EQUATIONS tirack681 al amp 2 a3 8 4 fc2 amp c3 1 10 1 11 1012 irg681 END interrupt controller APPENDIX SYSTEM DIAGRAMS In this appendix are the wiring diagrams which implement the Master circuit board subsystem and system controller subsystem which are discussed in Chapter IV These diagrams were produced by the OrCAD SDT III computer aided design CAD tool It is however t
32. 232 PORT 2 BTST B RECFULL SRB A4 DOES PORT 2 HAVE A CHAR BEQ S SCAN2 EX NO EXIT MOVE B RBB 24 DO YES GET CHAR SCAN2 EX RTS WHILE DOWNLOADING CHARACTERS FROM PORT 2 THIS PROCESS CAN BE HALTED BY SENDING AN ESC CHARACTER FROM THE KEYBCARD TO PORT 1 GETCHR2 BSR 5 1 CHAR FROM PORT 1 IF PRESENT ESC DO IS THE CHAR AN ESCAPE BEQ GC2_EXIT YES SO EXIT BSR GETCHAR2 NO GET DOWNLOAD CHAR BRA S EXIT GC2 GC2 EXIT BSET B ESCAPE MONSTAT IF ESC CHAR SET MONSTAT BIT EXIT GC2 RTS ECHO2 LEA PORT2 A4 POINTS TO RS 232 PORT 2 BTST B XEMPTY SRB A4 IS CONSOLE XMIT RDY BEQ ECHO2 CHECK AGAIN MOVE B TBA A4 YES OUTPUT CHAR PORT 1 RTS LEA PORT1 A4 POINTS TO RS 232 PORT 1 BTST B XEMPTY SRA A4 IS CONSOLE XMIT RDY BEQ MOVE B DO 4 YES OUTPUT CHAR PORT 1 RTS END 91 THIS PROGRAM BUILDS THE CMD STRING INPUT FROM THE KEYBOARD Kk K k K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k K k k k K k k k k k k k k k k WRITTEN BY DR LARRY ABBOTT K X X X K k K X X K k k k k X X K K k k X XX k K k k k k K k k k k k k k k k k k k k k k k k K k k k k k k k k k k k K FILENAME GETSTRIN ASM K X X NX k K
33. 9 a Slave Only Application 9 b Master Only Application 10 c Master Slave Application 12 JuDibration Protocols s 14 MEMORY MANAGEMENT 18 l Memory Protection eesece eemper 18 24 WVirtusleMemoky sore sees 19 3 tDuslsported Memory eoe Rose s ni 22 SYSTEM OVERVIEW 24 A SYSTEM CONTROLLER CIRCUIT BOARD 24 1 Priority Bus ALPDILtabION et 59 9 cene 24 2 Manuel 25 Jc Interrupt Driver reese 26 MASTER CIRCUIT BOARD 26 Central Processor 26 2 Dual Universal Asynchronous Receiver TABLE OF CONTENTS Transmitter 27 Erasable Programmable Read Only Memory 27 iv 4 Random Access Memory 28 5 Memory Management Unit 28 6 Dual port DRAM Controller 28 WMBb us Controller Sest ennnen 29 8 Interrupt Handler 29 DESIGN IMPLEMENTATION 31 A MINIMAL SYSTEM 32 1 Memory Map 32 2 Hardware Interface 35 3 Software Support 38 a Exception Vector Table and Monitor Debugger Program 38
34. CHECK SUM D6 LOOPINIT IF MORE CHARS THEN LOOP ELSE EXIT K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k K k k k k k K k K k k k k k k k k k k THIS ROUTINE IS VECTORED TO BY ALL EXCEPTIONS THAT LACK DEFINITE EXCEPTION SERVICE ROUTINE Kk k k k k oe oe eoe oe oe oe ck ode oo oko oe oe oe ce 0 oe oe oe oe oe coke oe ox oe xK 0e c oe de ok xoxo ko koX ko ck k k k kk WRITTEN DR LARRY ABBOTT FILENAME UNUSED ASM K k k k k kk k k eoe oe oe e e eoe che de eoe eoe oe oe eoe e oe oe oe oe oe eoe e ook oce oe e eoe e KKK x X ox e X x kx x x VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION DAVID M SENDEK 1 OCT 87 DOCUMENTATION UPGRADE INCORPORATE PROMPT K k k k k k k k k k k K k k k k k k k k k k k k k k k k k k k k k k k K k k k k k k k k k k K k k K k k K k k k k k k K DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES OUTPUT BYTE BYTEOUT ASM MESSAGE MESSAGE ASM REG REG ASM SCRLF IO UTIL ASM SYSTAX MAIN ASM USEMSG MESSAGE ASM PROMPT MESSAGE ASM GLOBAL UNUSED EXTERNAL OUTPUT_BYTE MESSAGE REG SCRLF SYSTAX USEMSG EXTERNAL PROMPT UNUSED MOVEM L SP SYSTAX SAVE POINTER TO APP
35. DUART A chip select signal will be generated for the DUART when a physical address is in the range 7F7000 through 7 The physical addresses in the range 34 7F7010 through 7F7FFF are multiple maps for the DUART Multiple maps provide valid addresses to chip select the DUART They also permit address decoding logic to be simplified However to avoid ambiguity only the physical addresses 7F7000 through 7F700F are used to address the DUART 2 Hardware Interface Appendix illustrates the circuitry involved in the minimal system Figures C 1 through C 8 illustrate the minimum system in its entirety Figure C 1 illustrates the MC68010 microprocessor used in the minimal system design Figure C 2 illustrates the HALT and RESET generation circuitry The NE555 timer provides an automatic system reset when the system is powered up There is also a manual system reset switch push button Resetting the system initializes the internal circuitry of the CPU and DUART A two input OR gate in the reset circuitry has one input grounded so it acts as unneeded buffer However in the fully integrated system discussed later in this chapter this input is tied to the VMEbus system reset SYSRESET line This permits a system wide reset to the master circuit board illustrated in Figure 3 1 Figure C 3 illustrates the clock generation circuitry The 8 MHz CPU clock signal is produced by using a 7415161 binary counter to
36. KKK KKK KKK KKK KKK KKK KK KK KKK WRITTEN BY DR LARRY ABBOTT MX MX MX X X X MXXXXX XX XXXXXX XMXXXXXX X X X X MXX X XXXXXX XX X XX XX X FILENAME REGCHANG ASM kk kk kx xx xk xk k kk VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION A DAVID SENDEK 1 OCT 87 DOCUMENTATION UPGRADE DEFINING MODULES EXTERNALLY DECLARED VARTABLES BUFFIN MAIN ASM MONSTAT MAIN ASM GET ADDR GET_ADDR ASM REG REG ASM REGERR MESSAGE ASM HEX CONV HEXCONV ASM SPACE MAIN ASM HEX ERR MAIN ASM SYSTAX MAIN ASM MESSAGE MESSAGE ASM SCRLF IO UTIL ASM GLOBAL REGCHANG EXTERNAL BUFFIN GET ADDR HEX CONV HEX ERR EXTERNAL MESSAGE MONSTAT REG REGERR SPACE SYSTAX SCRLF ESC EQU 1B BSR DISPLAY REGISTERS CRT BLANKSCAN MOVE B 0 00 SUBQ B 1 BUFFIN LENGTH SPACE D0 DOES BUFFIN I CHAR SPACE 2 BNE START_REG NO GET START AND END ADDR BRA BLANKSCAN CONTINUE SCANNING BUFFIN START REG CMPI B 5 00 DOES DO ESC ASCII BEQ REG DONE YES R
37. LINE ADDRESS 101 WORD_SPACE MOVE W 2 D2 L L MD_EXIT MOVE B A2 D0 BSR BTST BEQ MOVE SUB L BLT OUTPUT BYTE MODIFY MONSTAT WORD_SPACE CHANGE HEX_ERR MONSTAT MD_EXIT SPACES END ADDRESS D1 A2 D0 D0 D1 MD_EXIT ANDI B 50L 00 BNE BSR CMP B BEQ BRA BSR RTS LINE NUMBER MOVE CHANGE CHGAGIN MORE CHAR ROR L BSR ROR L BSR ROR L BSR ROR L BSR MOVE BSR RTS MOVE W BCLR B BSR BSR BCLR B BEQ MOVE B BEQ CMPI B BNE BSR BTST B BNE MOVE B ADDQ W DO START ADDRESS OUTPUT BYTE TO CRT IS MEMORY MODIFY STATUS BIT SET NO SKIP CHANGE YES MODIFY MEMORY CLR HEX STATUS BIT ERROR IF ERROR EXIT SETUP FOR 2 SPACES OUTPUT 2 SPACES TO CRT GET END ADDRESS 00 START ADDRESS D1 END ADDR START ADDR IF START END THEN EXIT DOES L S NIBBLE 0 GETABYTE NO GET ANOTHER BYTE SCROLL SCROLL PAUSE CHECK ESC DO ABORT SCROLL MD_EXIT YES SO EXIT NEWLINE NO START A NEW LINE SCRLF MOVE CURSOR TO NEXT LINE L A2 D0 GET CURRENT ADDRESS 8 D0 MOVE M S BYTE TO L S BYTE OUTPUT BYTE DISPLAY BYTE ON CRT 8 D0 MOVE M S BYTE TO L S BYTE OUTPUT BYTE DISPLAY BYTE ON CRT 8 D0 MOVE M S BYTE TO L S BYTE OUTPUT BYTE DISPLAY BYTE ON CRT 8 D0 MOVE M S BYTE TO L S BYTE OUTPUT_BYTE DISPLAY BYTE ON CRT 4 D2 SETUP FOR 4 SPACES SPACES OUTPUT 4 SPACES TO CRT 2 D2 SETUP FOR 2 BCKS
38. SPACES IO UTIL ASM REGMSG MESSAGE ASM SYSTAX MAIN ASM LESEREREZERSSREERRRERERRSSSERERERERERREERRSRSSSERSSERREREREERERERERRRE GLOBAL REG EXTERNAL MESSAGE OUTPUT BYTE REGMSG EXTERNAL SCRLF SPACES SYSTAX REG BSR SCRLF LEA KEGMSG AS GET POINTER TO MESSAGE MOVEA L SYSTAX A2 GET STACK POINTER AT MONITOR bi ENTRY SUB L 540 2 OFFSET OF THE STACK MOVE W 15 D3 SET REGS CNTR FOR 16 REGS REGLIST BSR MESSAGE PRINT PART OF REGISTER MESSAGE MOVE W 3 D4 SET FOR 32 BIT REGISTER BSR REG_DUMP PRINT CONTENTS OF A REGISTER DBF D3 REGLIST IF MORE REGS THEN GO TO REGLIST BSR MESSAGE PRINT SR MOVE W 1 D4 SET FOR 16 BIT REGISTER BSR REG DUMP PR CONTENTS OF STAT REG SR MOVE W 4 D2 SET FOR 4 SPACES BSR SPACES PRINT 4 SPACES BSR MESSAGE PRINT PC MOVE W 3 D4 SET FOR 32 BIT PC REGISTER BSR REG_DUMP PRINT CONTENTS OF PC REGISTER MOVE W 1 D2 SET FOR 1 SPACES BSR SPACES PRINT 1 SPACES BSR MESSAGE PRINT PC SUBQ L 4 A2 MOVE L A2 A2 MOVE W 1 D4 SET FOR WORD POINTED TO BY PC BSR REG_DUMP PRINT CONTENTS OF WD PNTD BY PC BSR SCRLF FORMAT DISPLAY RTS 108 REG DUMP MOVE B A2 D0 GET A BYTE OF THE REG FROM APPLICATION PSW BSR OUTPUT_BYTE OUTPUT BYTE TO CONSOLE DBF D4 REG DUMP IF MORE BYTES THEN REG DUMP RTS ELSE EXIT END 109 X kk X X X XX X XXX X X X X XXXX X 2XXX XXX XX XXXX X X XX X X THIS ROUTINE CHANGES THE CONTENTS OF DESIRED REGISTERS 5 LC XXI KKK KKK KKK KKK
39. Virtual Memory Virtual memory allows programs to be executed which require more memory space than is physically resident Therefore the maximum program size is not limited by the size of physical memory Originally this method was designed to reduce and more effectively use memory A virtual address is an address located within the address space of the microprocessor Consequently with the MC68010 microprocessor there exists 16 megabytes of virtual memory A virtual memory implementation groups the virtual addresses into blocks called pages Figure 2 6 shows such a grouping with zero through N pages of virtual memory but with only enough physical memory to accommodate two virtual pages in physical memory In Figure 2 6 virtual PAGE 1 and virtual PAGE N are mapped into separate physical pages When the CPU generates a virtual address the virtual address is translated into a physical address The address translation process includes fairly sophisticated memory protection so that tasks cannot interfere with each other or access resources 19 not allocated to them Figure 2 7 illustrates simplified memory mapping mechanism The high order virtual address bits are referred to as a virtual page number The virtual page number referenc gt s a location of the translation table The translation table has as its contents a physical page number which references the starting location of the physical memory s page address The low or
40. arbiter VMEbus arbitration uses a scheme with four parallel priority levels similar to Figure 2 5 Each priority level however can have subsystems daisy chained as illustrated in Figure 2 4 In other words the bus arbiter grants bus access to a given level and then the daisy chain at that level determines which subsystem actually gets the bus The VMEbus arbitration process includes the BBSY signal as shown in Figure 2 4 and the bus clear BCLR signal The BBSY and BCLR lines are added to the bus arbiter and all subsystems on the VMEbus The VMEbus BBSY signal is asserted by the subsystem which is granted bus access The BCLR output signal informs all subsystems on all priority levels that a subsystem on a higher priority level than the current bus master has requested access to the VMEbus As mentioned earlier the requesting subsystem should accommodate a release when done or release on request strategy to resolve pending higher priority requests for bus access 17 MEMORY MANAGEMENT Memory management can employ a combination of methods to organize the physical memory associated with a microprocessor or system These methods effectively free the programmer using the system from being concerned where the program code and program data will reside in memory This thesis addresses the memory Management concepts of memory protection virtual memory and dual ported memory 1 Memory Protection One method used to organi
41. are incorporated to meet the specified signal drive capability and isolation requirements b Erasable Programmable Logic Devices The erasable programmable logic device EPLD used in the minimal system s address decoding must be modified to include the additional memory mapped devices cf the master circuit board subsystem The EPLD used for interrupt handling in the minimal system is replace by the interrupt handler hardware in the master circuit board subsystem design The master circuit board subsystem design is an upgraded version of the minimal system A pin out list for all wiring connections was developed in order to reduce wire wrap errors but it is not included as part of this thesis The small scale integrated circuit SSI logic shown for the generation of the data transfer acknowledge DTACK bus error BERR physical upper data strobe PUDS physical lower data strobe PLDS and 66 physical address strobe PAS Signals was actually implemented with EPLDs to reduce the chip count CONCLUSIONS Meeting all the goals set in this thesis made this thesis an ambitious undertaking The major integrated circuit IC chips included the CPU DUART interrupt handler hardware dual port DRAM controller MMU VMEbus controller and BAM These IC chips required an extensive study of product specification and application notes to understand the wiring configurations and programming of the devices Study of the spe
42. b Monitor Debugger Commands 38 C Programmable Logic Device Programming 40 B FULLY INTEGRATED SYSTEM 41 1 Memory 41 2 Master Circuit Board 44 a MiCroprocesson SSi 44 b Halt and Reset Generation 45 gu Clock Generation 5 ress liga 46 d Local Bus Address Decoding 46 e Memory Management Unit 46 f Dual port DRAM Controller 48 g Dynamic Random Access Memory 50 h EPROM SRAM 51 i Dual Serial Port 51 j Interrupt Handler 51 Data Transfer Acknowledge and Bus Error Generation 53 1 VMEbus Controller 55 m VMEbus Address Decoding 56 n VMEbus Drivers 56 System Controller Circuit Board 57 Bus Arbiter 57 b System Reset 57 VMEbus Drivers 57 V RESULTS 2 92 9 2 24 9 220252 5 25 2 22525 59 VI SUMMARY AND CONCLUSIONS 62 A SUMMARY 2 95 9 22 4 62 Design Concepts 62 a VMEbus Structure
43. be performed successfully The write violation occurs if an attempt is made to write to a write protected portion of physical memory If address translation cannot be performed this denotes to the operating system that a new memory page may need to be brought into memory from a hard disk or that there is a system error The operating system configures the MMU to write protect memory segments and to implement virtual memory mapping by the MMU The circuitry to inhibit virtual address to physical address translation during an interrupt cycle is illustrated in Figure E 7 The mapped address strobe MAS and ALL input signals to the MMU are generated during an interrupt acknowledge cycle The physical data strobe generation circuitry Fig E 8 is used to generate the physical upper data strobe PUDS and the physical lower data strobe PLDS signals The PUDS and PLDS signals are generated during normal virtual address to physical address translation Normal address translation is the mapping of a virtual address to a physical address without a page fault occurring The physical data strobes will not be generated if there is a write cycle for a write protected segment This is accomplished by the write inhibit WIN signal generated by the MMU 47 The physical address strobe circuitry Fig E 8 generates a physical address strobe PAS signal to denote that the address translation has taken place and the physical address is
44. bus cycle The bus grant acknowledge BGACK is signal asserted by alternate bus master while it has control of the bus 5 Interrupt Control The interrupt priority levels IPLO through IPL2 are signals which represent the encoded priority level for the highest priority device desiring interrupt service The signal IPLO is the least significant bit and the signal IPL2 is the most significant bit of the group A level zero interrupt all signals are asserted high indicates there is no interrupt request pending A level seven interrupt all IPLx signals are asserted low has the highest priority and is non maskable This implies that level seven is not an ordinary interrupt level for requesting routine interrupt service Rather a level seven interrupt should be reserved for catastrophic events such as alternating current AC power failure where the non maskable property is essential 6 System Control The system control group is used to reset the CPU and to indicate to the CPU that a bus error has occurred It is also used to reset peripheral devices and to generate a bus error exception The halt signal HALT active low is a bi directional signal As an input it is used to stop the CPU at the completion of the current bus cycle As an output HALT is asserted only when double bus error or address error exception has caused the MC68010 to enter a halt state The reset signal RESET active low is also a
45. cannot generate their own DTACK signals so external circuitry must do it for them The DTACK generation circuitry for the SRAM and ROM must allow adequate time for the data transfer All these DTACK signals are ORed together to produce the MC68010 DTACK input If the CPU on the master circuit board makes an off board access using the off board OFFBOARD signal to the VMEbus controller the DTACK signal DTACK172 is generated from the VMEbus controller The off board device provides a global DTACK Signal GDTACK to the VMEbus controller Fig E 20 via the VMEbus DTACK line In turn the VMEbus controller would provide the DTACK172 signal for the DTACK circuitry This arrangement permits long access times on the VMEbus If the master circuit board s DRAM is being accessed as a global asset the GDTACK signal is generated by the SEL2 and DTACK764 signals as illustrated in Figure 11 The BERR signal is generated under one of three conditions First the BERR signal is generated when the maximum allowable SRAM and ROM data transfer time has been reached and a DTACK signal has not been received by the CPU Secondly a global bus error BERR172 signal can be received from a VMEbus watchdog timer if the master circuit board subsystem has control of the VMEbus Finally if a page fault signal FAULT is generated by the MMU this also causes a bus error condition 54 The bus error condition causes exception p
46. code listing of the exception 33 vector table and the monitor debugger program The 2500AD MC68010 cross assembler Ref 9 running on an IBM XT AT compatible computer was used to cross assemble the monitor debugger source code into a Motorola S record format Ref 10 pp A 1 A 4 order to program the S record code into the EPROM a Data 1 0 System 29 Universal Programmer was configured to accept Motorola S records The S record file was then sent from the IBM XT AT to the Data I O System 29 via an RS 232 interface Finally the EPROM programming process was initiated on the Data I O System 29 The 16K bytes of SRAM are used to test development software Files can be down loaded to the SRAM for debugging SRAM is used in the minimal system design instead of DRAM to avoid the additional logic necessary to generate refresh cycles for the DRAM MC68681 dual universal asynchronous receiver transmitter DUART is a communications peripheral device that can accommodate two independent full duplex receiver transmitter ports The operating mode and data format of each port can be programmed independently One port of the DUART is configured by the monitor debugger program to accommodate the down loading of files from an IBM XT AT compatible computer The other port of the DUART is configured to communicate with the terminal The memory map Table I delineates a physical address range of 7 7000 through S 7F7FFF for the
47. divide a 16 MHz signal from a crystal controlled oscillator A 4 MHz signal from the 74LS161 provides the clock 35 input for the shift register which is used to help generate the data transfer acknowledge DTACK and bus error BERR signals Erasable programmable logic devices EPLDs specifically Altera EP310s were used to reduce the chip count in the minimal system EPLDs were used for address decoding generating DTACK and BERR signals performing interrupt control and generating SRAM write enable and RAM and ROM output enables Figure C 4 shows the EPLD implementation for the minimal system address decoder The minimal system address decoder implements the memory map of Table I Listing D 1 in Appendix D presents the Abel software program for the address decoder Abel software will be discussed in the next section Figure C 5 shows the logic of the circuitry which generates the DTACK and BERR signals to the CPU The circuitry prior to the 741505 open collector inverters is implemented by an EPLD The DTACK and BERR signals are passed through the 7415055 to give the open collector outputs and the proper assertion levels DTACK and BERR In the event that the MC68010 microprocessor tries to address a location not supported by the design a bus error BERR time out signal is generated after two microseconds The BERR signal causes the CPU to begin bus error exception processing This invokes the routine whose address is in th
48. logic or as a clocked input eight pins can be used for input logic or output logic the remaining two pins are used for Vcc input and ground input The following Abel modules were implemented minimal system address decoder dtack and bus error generation output enable write enable interrupt controller 126 THIS FILE USES DATA I 0 S ABEL DESIGN LANGUAGE bi TO GENERATE A JEDEC FILE TO PROGRAM AN ALTERA EP310 ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD MODULE minimal system address decoder FLAG X0 TITLE 768010 ADDRESS DECODER FOR THE MINIMAL SYSTEM 161 DEVICE 0310 Abel V2 must be used for this device DEFINE LABELS ASSOCIATED WITH INPUT AND OUTPUT PINS FOR THE EP310 INPUT PINS 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 11 12 13 15 5 OUTPUT PINS cs681 romen sramen PIN 16 18 19 ASSIGNMENT STATEMENTS h 1 HIGH l 0 LOW x X DONT CARE ramaddr 23 22 21 20 19 18 17 16 15 14 X X X X X X X X X X X X X X romaddr 23 22 21 20 19 18 17 16 X X X X X X X X X X XI duartaddr a23 a22 821 a20 a19 a18 a17 a16 a15 a14 al3 al2 X X X X X X X X X X X X 000010086 EQUATIONS AS PER MEMORY INVERSION i amp AND OR EQUATIONS Sramen ramaddr gt h010000 amp ramaddr lt h013FFF amp as 5681 duartaddr gt h7F7000 amp duartaddr lt h7F
49. or a range of addresses if desired The change register command RCH is used to modify the contents of an address register Axx a data register Dxx the program counter PC the user stack pointer US the system stack 39 pointer SP the status register SR One of these options must be specified with the RCH command The display register command REG displays the contents of the address registers data registers program counter user Stack pointer system stack pointer and status register This information gives the state of the MC68010 This command is particularly useful when a breakpoint is reached in the debugging process The down load command LOAD permits the minimal system to receive software that was developed on an IBM XT AT compatible computer After code has been assembled and linked using software such as the 2500AD MC68010 cross assembler it can be down loaded to the absolute address or addresses specified during the linking process c Programmable Logic Device Programming As already mentioned EPLDs are used to reduce the chip count on the printed circuit board The Data I O Abel Ref 11 program was used to compile a high level language representation of desired digital logic The output of Abel is a joint electron device engineering council JEDEC standard file for programming the EPLDs This file is then down loaded to the Data I O System 29 Universal Programmer to program the EPLDs App
50. port DRAM controller VMEbus controller and interrupt handler The master circuit board is configured in a master only role as discussed in Chapter II 1 Central Processor Unit The Motorola MC68010 16 bit CPU was selected to be the processing element because it has the necessary features to support virtual memory but lacks the 24023 complanity of 32 bit architecture It also affords easier wire wrap assembly than the other Motorola CPUs supporting virtual memory because wire wrap is better supported for a dual in line package DIP and there are fewer data and address signals The signals and programming capabilities of the MC68010 microprocessor are discussed in further detail in Appendix A 2 Dual Universal Asynchronous Receiver Transmitter Two asynchronous serial RS 232 ports are implemented with the Motorola MC68681 DUART One serial port is configured to drive a terminal while the second serial port is used to down load files from an IBM XT AT compatible computer The first serial port is used to permit a human interface to the system The intent of the second serial port is to provide the ability to develop software on an IBM XT AT compatible computer with a cross assembler and then to down load the software through the second serial port to the master circuit board s random access memory RAM for testing debugging and execution 3 Erasable Programmable Read Only Memory The EPROM in this thesis design contains
51. the exception vector table and the monitor debugger program The exception vector table contains the addresses of the routines to be executed as a result of an interrupt or other exception The monitor program configures the subsystem when it is powered up and handles communications with the terminal for interaction between the microprocessor and the user It also provides debugging commands and coordinates the previously mentioned down loading of files Sixty four kilobytes of EPROM are provided in the master circuit board Once an operating system is developed it would not be desirable to freeze the interrupt part of the exception vector table into read only memory ROM It should be noted that the 27 design of operating system to take advantage of the system s hardware features is beyond the scope of this thesis 4 Random Access Memory Sixteen kilobytes of SRAM and one megabyte of DRAM are provided on the master circuit board 5 Memory Management Unit The use of the Motorola MC68451 MMU affords several advantages to the microprocessor system The MMU provides the advantages of virtual memory and a sophisticated memory protection scheme both previously discussed in Chapters I and II The MC68451 provides the capability to Translate logical addresses to physical addresses Provide segment descriptors to implement memory protection Detect page faults and other situations requiring operating system interven
52. 62 b Memory Management 62 Interrupt Control 64 Design Implementation 65 a Hardware Configurations 65 b Erasable Programmable Logic Devices 66 B CONCLUSIONS 67 APPENDIX A MC68010 16 BIT MICROPROCESSOR 69 APPENDIX B MINIMAL SYSTEM EXCEPTION VECTOR TABLE AND MONITOR DEBUGGER PROGRAM 77 APPENDIX C MINIMAL SYSTEM DIAGRAMS 117 APPENDIX D MINIMAL SYSTEM S PROGRAMMABLE LOGIC DEVICE SOURCE CODE 126 APPENDIX E SYSTEM DIAGRAMS 131 LIST OF REFERENCES BIBLIOGRAPHY INITIAL DISTRIBUTION LIST vii LIST OF TABLES Minimal System Memory System Memory nS SSS Sete eee Data Strobe Control of tne Data Bus State and Address Space Q LIST OF FIGURES Generic M lti sProcessor System ssp Ata ia 5 Slave Only 10 Mastes Only Subsystem malm 11 Master 5lave Subsystem iie 13 Daisy Chain Arbitration 15 Paraller Arbitration s 16 Virtual Memory Mapping Sessa Sst
53. 7FFF amp as romen romaddr lt hn00FFFF amp as END minimal_system_address decoder THIS FILE USES DATA I O S ABEL DESIGN LANGUAGE GENERATE JEDEC FILE TO PROGRAM ALTERA EP310 ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD MODULE dtack and bus error generation FLAG 0 TITLE AND BUS ERROR GENERATION FOR THE MINIMAL SYSTEM u64 DEVICE E0310 Abel V2 must be used for this device DEFINE LABELS ASSOCIATED WITH INPUT AND OUTPUT PINS FOR THE EP310 INPUT PINS berr delay rom delay sram delay romen dtack681 sramen PIN 1 8 9 11 13 16 OUTPUT PINS dtack berr PIN 18 19 ASSIGNMENT STATEMENTS h 1 HIGH 1 0 LOW x X DONT CARE DEFINE EQUATIONS NOTE INVERSION amp AND OR EQUATIONS dtack dtack681 sramen amp sram_delay romen amp rom_delay berr berr delay END dtack and bus error generation MODULE output enable write enable FLAG X1 TITLE SRAM WRITE ENABLE AND SRAM AND ROM OUTPUT ENABLES FOR THE MINIMAL SYSTEM u63 DEVICE E0310 DEFINE LABELS ASSOCIATED WITH INPUT AND OUTPUT PINS THIS FILE USES DATA I 0 S ABEL DESIGN LANGUAGE GENERATE JEDEC FILE TO PROGRAM ALTERA EP310 ERASABLE PROGRAMMABLE LOGIC DEVICE FOR THE EP310 INPUT PINS rw win uds lds mas as pudsi pldsi PIN 1 2 3 4 5 6 8 9 OUTPUT PINS oelb weu34 weu35 oehb pudso pldso pas PIN
54. 9 CI 5 006 WOU lt 505194 T S lt lt lt lt 89 14 Z 975 toinbtd pue 5 47111 6141 27144 PER 7 aqAq 311XM cd aj g atgeug andano vik 3 MOT 304100 Gua 55 oiv 2 P ES i a oa gTM 8730 2 T SLNIWWOO 2 I xNJWOY NINVAS IV T 2 L M W xSGn I SAI I AE EE ma p 279 pue 3as nb w 5 TILIJL O IAI 957 319 aue2rjrubrtS 45 957 174 ISON 95 KIJTNDITD Luvnd OL LUNG 6 OL 1 2 TIdI L897 VI 95 SLNSWWOD 16 5 SV I n i 2 ew LL A en s t z CV 1 1 TV T 253 11 Toa T 003 1 124 2204 WIIS S TEUTUTH 181211
55. AD A232 554 2 NAVAL POSTGRADUATE SCHOOL Monterey California DTIC ELECTE 6 1991 THESIS DESIGNING A VIRTUAL MEMORY IMPLEMENTATION USING THE MOTOROLA MC68010 16 BIT MICROPROCESSOR WITH MULTI PROCESSOR CAPABILITY INTERFACED TO THE VMEbus by David M Sendek June 1990 Thesis Advisor Larry W Abbott Approved for public release distribution is unlimited 91 3 04 004 Unclassified SECULA LASSE ON OF 45 PAGE REPORT DOCUMENTATION PAGE REPORT SECURITY C ASS F CATION SECURITY CLASS FE CAT ON AUTHOR TY 20 DECLASSIFICATION DOWNGRADING SCHEDULE 4 PERFORMING ORGAN ZAT ON REPORT NUMBER S OFF SYMBOL If applicable Naval Postgraduate School FC 6c ADDRESS City State and ZIP Code NAME OF PERFORMING ORGAN ZATION Monterey California 93943 5000 Bo Or 72 5 If applicable 8a NAME OF FUNDING SPONSOR NG ORGANIZATION 8 ADDRESS City State and ZIP Code 71 TITLE Include Security Classification 13a OF RESORT COVERED Master s Thesis FROM 16 SUPPLEMENTARY NOTATION Form Approved OMB No 0704 0188 Approved for public release distribution is unlimited 5 MON TORING ORGAN ZAT ON REPORT hu VRERIS 15 RESTRICTIVE VARY NGS 3 DISTR 7 NAME OF SON TORING ORGAN ZATON Naval Postgraduate School 76 ADDRESS City State and ZIP Code 93943 5000 Monterey California 9 PROCUREME
56. ED UNUSED TRAP 0 VECTOR USED AS MONITOR BRKPT TRAP TRAP TRAP TRAP TRAP TRAP TRAP NOTE USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER 80 1 VECTOR 2 VECTOR 3 VECTOR 4 VECTOR 5 VECTOR 6 VECTOR 7 VECTOR VECTOR NUMBERS 48 63 ARE UNASSIGNED RESERVED INTERRUPT 0 VECTOR DEFINED FOR MONITOR INTERRUPT 1 VECTOR INTERRUPT 2 VECTOR INTERRUPT 3 VECTOR INTERRUPT 4 VECTOR INTERRUPT 5 VECTOR INTERRUPT 6 VECTOR INTERRUPT 7 VECTOR INTERRUPT 8 VECTOR INTERRUPT 9 VECTOR INTERRUPT 10 VECTOR INTERRUPT 11 VECTOR INTERRUPT 12 VECTOR INTERRUPT 13 VECTOR INTERRUPT 14 VECTOR INTERRUPT 15 VECTOR INTERRUPT 16 VECTOR INTERRUPT 17 VECTOR INTERRUPT 18 VECTOR INTERRUPT 19 VECTOR INTERRUPT 20 VECTOR INTERRUPT 21 VECTOR INTERRUPT 22 VECTOR INTERRUPT 23 VECTOR INTERRUPT 24 VECTOR INTERRUPT 25 VECTOR INTERRUPT 26 VECTOR INTERRUPT 27 VECTOR INTERRUPT 28 VECTOR INTERRUPT 29 VECTOR INTERRUPT 30 VECTOR INTERRUPT 31 VECTOR INTERRUPT 32 VECTOR INTERRUPT 33 VECTOR INTERRUPT 34 VECTOR INTERRUPT 35 VECTOR INTERRUPT 36 VECTOR INTERRUPT 37 VECTOR INTERRUPT 38 VECTOR INTERRUPT 39 VECTOR LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG L
57. END A0 D0 DO lt BUFFIN I amp I lt 1 1 HEX CONV CONVERT 1 CHAR OF END ADDR TO HEX ERR MONSTAT WAS THERE AN HEX CONVERSION ERROR ADDR ERR YES EXIT ROUTINE D3 END ADDR IF MORE CHARS CONTINUE D2 A3 ELSE STR END ADDR IN A3 A3 END ADDRESS SAV END ADR IN MEM EXIT HEXMSG A5 MESSAGE X X kk X X KKK KKK KKK KKK KEK KKK KEK KKK k kk THIS PROGRAM CONTAINS A GROUP OF CONSOLE UTILITIES WRITTEN BY LARRY ABBOTT JAN 1986 K kk k k k Kk k k k k k k K k k k k k K k k Kk k k k k k k Kk k k k lt k k k k k k k k k k k k k k K k Kk k k k k k X k x FILENAME IO UTIL ASM K X KK KIK xk xx kx KK KKK KKK KKK KKK KEK KKK KK KKK KEKE KK KEKE KKK X Kok k k k k k kk VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION DAVID SENDEK 30 SEPT 87 UPGRADE CORRECT FOR 68681 K kk Kx xx xxx xk xxx xk x Kx kx xxx xk xxx xxx kx xxx x K xxx x xxx xxx XK x Kk XK xxx xk xk x xxx DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES BS MAIN ASM PORTI MAIN ASM CR MAIN ASM ECHO1 CONSOLE ASM ESC CONSOLE ASM FWDARW MAIN ASM GETCHAR1 CONSOLE ASM LF MAIN ASM RECFULL MAIN ASM SRA MAIN ASM MAIN ASM k kX x x XK x XK XK k XK x Kx xk x xk xx xk xx
58. ER DBF D1 NIBBLE SHF BRANCH IF MORE BITS RTS END 104 K k k k k Kk k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k THE GO ROUTINE EXECUTES A PROGRAM FROM THE MONITOR THE FORMAT IS GO start address gt optional breakpoint WRITTEN DR LARRY ABBOTT Ok k Kk K KK xxx xxx xxx xxx xxx xxx xxx xx xxx 0e KKK KKK e e e kx kk kk KKK xxx FILENAME GO ASM K K K k k amp amp k k amp k k k k k K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION A DAVID M SENDEK 1 OCT 87 DOCUMENTATION UPGRADE B DAVID M SENDEK 5 OCT 87 BSET BCLR ASSEMBLY LANGUAGE CORRECTION Kx Kk k k X k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k K k k k DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES x MAIN ASM ILLMSG MESSAGE ASM 5 5 MESSAGE ASM MESSAGE MESSAGE ASM MAIN ASM MONSTAT MAIN ASM BUFFIN MAIN ASM OUTPUT_BYTE BYTEOUT ASM CONTINUE MAIN ASM SCRLF 10 UTIL ASM X CMD DECODE DECODER ASM SPACE MAIN ASM GET ADDR GET ADDR ASM STRING MAIN ASM hi GETSTRING GETSTRIN ASM STRINGEND MAI
59. ERRS amp ENABLE XMIT RCV RUPTMASK IMR A4 WHEN PORT RCVS CHAR 86 BANNER BSR SCRLF MOVE CURSOR TO NEXT LINE LEA MONMSG A5 SET MESSAGE POINTER TO MONMSG BSR MESSAGE CRT lt 68010 MONITOR V1 3 BSR SCRLF MOVE CURSOR TO NEXT LINE LEA PROMPT 25 SET UP FOR A PROMPT TO THE CRT BSR MESSAGE SEND PROMPT TO CRT LOOP BRA S LOOP WAIT FOR AN INTERRUPT MONITOR MOVE L SP SYSTAX SAVE PTR APPL REGS MOVEM L A0 A7 D0 D7 SP SAVE ALL REGISTERS LEA STAX A6 SET MONITOR STATE PTR MOVEM L A6 A0 A5 D0 D7 LAST MONITOR STATE BSR GETSTRING ENTER MONITOR BCLR B STRINGEND MONSTAT CHECK FOR END OF STRING BEQ RESTORE NOT THE END SO EXIT BCLR B STRING MONSTAT CLEAR NEW STRING FLAG BSR CMD DECODE IF END THEN DECODE LEA PROMPT A5 SET MSG PNTR TO PROMPT BSR MESSAGE CRT lt 7 gt CRT PROMPT RESTORE MOVEM L A0 A5 D0 D7 A6 SAVE MONITOR STATE MOVEM L SP A0 A7 D0 D7 RESTORE ALL REGISTERS RTE END K k k k k k K k k k k k k k k k k k k k k k Kk k k k k k k K k k X k k K k k k k k k Kk k k k k k k k k k k k k k k k k k k THIS PROGRAM OUTPUTS MESSAGES TO THE CRT SCREEN K kx xk X xk KKK KKK xk xk kx xk xk xk xxx xk x xk xk KKK xk xx xxx xxx xx xxx xxx xk xk x xxx xk xxx xxx WRITTEN BY DR LARRY ABBOTT FILENAME 55 5
60. H An Evaluation Tool For The MC68451 MMU Motorola Inc 1982 Scales H Virtual Memory Using The MC68000 And The MC68451 MMU Motorola Inc 1982 West T Dual Ported RAM For The MC68000 Microprocessor Motorola Inc 1982 161 INITIAL DISTRIBUTION LIST No Library Code 0142 Naval Postgraduate School Monterey California 93943 5002 Chairman Department of Electrical and Computer Engineering Code EC Naval Postgraduate School Monterey California 93943 5000 Dr Larry Abbott 16047 Arborlea Dr Friendswood Texas 77546 Professor Mitchell Cotton Code EC CO Department of Electrical and Computer Engineering Naval Postgraduate School Monterey California 93943 5000 Professor Frederick Terman Code 2 Department of Electrical and Computer Engineering Naval Postgraduate School Monterey California 93943 5000 Commanding Officer Attn Lieutenant David M Sendek USN Naval Oceans Systems Center NOSC Code 845 271 Catalina Blvd San Diego California 92152 5000 Roberto Ventura Crispino LT CN Apartado Aero 2845 Cartagena Colombia Defense Technical Information Center Cameron Station Alexandria Virginia 22304 6145 162 Copies
61. ION VECTOR LONG UNUSED ZERO DIVIDE VECTOR LONG UNUSED CHK INSTRUCTION VECTOR LONG UNUSED TRAPV INSTRUCTION VECTOR LONG UNUSED PRIVILEGE VIOLATION VECTOR LONG UNUSED TRACE VECTOR LONG UNUSED LINE 1010 EMULATION VECTOR LONG UNUSED LINE 1111 EMULATION VECTOR ORG 38 NOTE VECTOR NUMBERS 12 AND 13 ARE UNASSIGNED RESERVED LONG UNUSED FORMAT ERROR VECTOR LONG UNUSED UNINITIALIZED INTERRUPT VECTOR ORG 60 NOTE VECTOR NUMBERS 16 23 ARE UNASSIGNED RESERVED LONG UNUSED SPURIOUS INTERRUPT VECTOR LONG UNUSED LEVEL 1 AUTOVECTOR VECTOR LONG UNUSED LEVEL 2 AUTOVECTOR VECTOR LONG UNUSED LEVEL 3 AUTOVECTOR VECTOR LONG UNUSED LEVEL 4 AUTOVECTOR VECTOR LONG UNUSED LEVEL 5 AUTOVECTOR VECTOR LONG UNUSED LEVEL 6 AUTOVECTOR VECTOR LONG UNUSED LEVEL 7 AUTOVECTOR VECTOR 79 LONG LONG LONG LONG LONG LONG LONG LONG ORG 100 LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG BKPT UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED MONITOR UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUS
62. IPTION LARRY ABBOTT 6 6 87 ADAPT TO 68681 DAVID SENDEK 30 SEPT 87 DOCUMENTATION UPGRADE K k k k K X k Kk k Kk K X K k K Kk X X Kk XX X XX XX k XX k XX k k k k k k K k k k K k K k k k k k K k K k k k K k k k K DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES 5 ESCAPE MAIN ASM MONSTAT MAIN ASM 1 MAIN ASM PORT2 MAIN ASM A X RECFULL MAIN ASM x RBA RBB MAIN ASM SRA SRB MAIN ASM TBA TBB MAIN ASM K kk k kx ec oe XXX KKK KK KKK KKK KKK KEK KKK KKK KKK KK xK Kx o koX k k kk GLOBAL ECHO1 ECHO2 GLOBAL GETCHAR1 GETCHR2 GLOBAL SCANCHR2 EXTERNAL ESCAPE MONSTAT PORT1 PORT2 EXTERNAL RECFULL RBA SRA TBA TBB SRB EXTERNAL XEMPTY RBB ESC EQU 1B ASCII CODE FOR ESCAPE 1 LEA 4 POINT RS_ 232 PORT 1 BTST B RECFULL SRA A4 CONSOLE CHAR READY BEQ GETCHAR1 NO CHECK AGAIN MOVE B RBA A4 00 YES GET CHAR RTS GETCHAR2 LEA 2 4 POINT RS 232 PORT 2 BTST B RECFULL SRB A4 CONSOLE CHAR READY BEQ GETCHAR2 NO CHECK AGAIN MOVE B RBB A4 D0 YES GET CHAR RTS SCANCHAR GETS A CHARACTER FROM A PORT IF IT IS THERE OTHERWISE SCANCHAR RETURNS TO THE CALLING ROUTINE SCANCHR1 LEA PORT1 A4 POINTS TO RS 232 PORT 1 BTST B RECFULL SRA A4 DOES PORT 1 HAVE A CHAR BEQ S SCAN1 EX NO EXIT MOVE B RBA A4 DO YES GET CHAR SCAN1 EX RTS 90 SCANCHR2 LEA PORT2 A4 POINTS TO RS
63. ISTER CONTENTS ERROR RE ENTER CR LF BYTE NULL REGMSG BYTE BYTE BYTE BYTE BYTE BYTE BYTE SREC_ERR BYTE BYTE USEMSG BYTE BYTE BYTE PROMPT BYTE BYTE SPCE BYTE BYTE BUFFULLMSG BYTE BYTE END DO NULL D1 NULL D2 NULL D3 NULL CR LF D4 NULL D5 NULL D6 NULL D7 NULL CR LF AQ NULL Al NULL A2 NULL A3 NULL CR LF A4 NULL A5 NULL A6 NULL 7 CR LF SR NULL PC NULL PC NULL CR LF US NULL SS NULL CR LF NULL S RECORD ERROR MESSAGE LF CR NULL UNUSED EXCEPTION ENCOUNTERED LF CR WITH FORMAT WORD NULL 15 NULL NULL LF CR INPUT BUFFER IS FULL TRY NULL 89 K Kk k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k THIS MODULE INPUTS FROM THE KEYBOARD AND DOWNLOAD PORT AND OUTPUTS CHARACTERS TO THE CRT K K k k k k k Kk k k k Kk k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k X k k k k NEW CONSOLE WRITTEN DEC 19 1986 BY DR LARRY ABBOTT x X MX X X X X X X XX XX XX XX XX XX XX XX XX XX X X XX M M X X XXX FILENAME CONSOLE ASM K X K k X X X X X X X X X X X X X X X XX X XX X XX X XXX XX X X X XX XX XXX X X XX X VERSION 1 3 REV MODIFIED DATE DESCR
64. LICATION REGISTERS MOVEM L A0 A7 D0 D7 SP SAVE ALL REGISTERS BSR SCRLF MOVE CURSOR TO NEXT LINE LEA USEMSG A5 SET MSG POINTER TO MONMSG BSR MESSAGE CRT UNUSED EXCEPTION MSG MOVE L SYSTAX A5 GET TOP OF STACK AT ENTRY ADDQ L 6 5 POINT TO STACK FORMAT WORD MOVE B A5 D0 GET FORMAT HIGH BSR OUTPUT BYTE OUTPUT FORMAT HIG MOVE B 5 00 GET FORMAT LOW BSR OUTPUT BYTE OUTPUT FORMAT LOW BSR SCRLF MOVE CURSOR TO NEXT LINE BSR REG DISPLAY REGISTERS MOVEM L SP A0 A7 D0 D7 RESTORE ALL REGISTERS RTE END 116 APPENDIX MINIMAL SYSTEM DIAGRAMS The figures Figs C 1 through C 8 contained in this appendix are discussed in Chapter IV These figures were created using the OrCAD SDT III computer aided design CAD tool Each signal s source s and or destination s are noted on the diagrams It is however the integration of these various components into a minimal system that comprises the work that is original to this thesis 117 1 3 830 0614 OTOS9OW 3 ATLIL 0108924 AS we AG AS AGH sioqjstsey 40 1104 AS AS 118 7 3 eanbr4 9 1959 PUB 3 ATLIL L V PU OL Z OL LNIWWOD 505190 Z 544 z ANI YDITMS qesoy 3 5
65. N ASM HEX ERR MAIN ASM SYSTAX MAIN ASM x K Kk k Kk Kk k k k k k k k k k k k K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k K k GLOBAL GO EXTERNAL BKPTAB BKPTMSG BUFFIN CONTINUE EXTERNAL ADDR GETSTRING ERR ILLMSG MESSAGE EXTERNAL OUTPUT SCRLF SPACE STRING STRINGEND EXTERNAL MONSTAT SYSTAX DECODE TRAPO EQU 4 40 OP CODE FOR TRAP 0 GO CMPI B SPACE 0 IS BUFFIN X A SPACE BNE GO_ADDR GET GO ADDRESS SUBQ B 1 BUFFIN YES ADJUST BUFFIN LENGTH BRA GO YES SCAN FOR NEXT SPACE GO_ADDR SUBQ 1 A0 ADJUST FOR POST INCREMENT BSR GET ADDR A2 lt GO ADDR A3 lt BREAKPOINT CMPA 0 A2 IS THERE A START ADDRESS BEQ CONTINU NO THIS IS A CONTINUATION BCLR B 4 MONSTAT CHECK FOR HEXCONV ERROR BNE GO_EXIT IF HEX ERROR THEN EXIT MOVEA L SYSTAX ELSE GET SYSTAX POINTER MOVE L 72 SYSTAX PC lt GO ADDRESS CMPA 0 A3 IS THERE A BREAKPOINT BEQ GO_EXIT NO SO EXIT LEA BKPTAB SET BREAK TAB POINTER MOVEA L 0 STORE BREAKPOINT IN TABLE MOVE W A3 BTLEN AO STORE INSTRUCTION AT BKPT 105 MOVE W TRAPO STORE ILL INSTRUCT AT BKPT CONTINU BSET B MONSTAT SET CONTINUE FLAG GO EXIT RTS THE BREAKPOINT ROUTINE RESTORES THE INSTRUCTION AT THE BREAKPOINT k BKPT CONTINUE MONSTAT INIT CONTINUATION FLAG LEA
66. N ASM GETCHR2 CONSOLE ASM K kk xx xk xk x xk xk xx kx kk kk xk XK kk kk kk kX xx xk k kx xk kx xk kx xxx xxx xk xxx xxx xk xxx xx GLOBAL DOWNLOAD EXTERNAL CHECKSUM CK SUM ECHO1 ECHO2 EPROMRNG EPROMSG EXTERNAL EPROMWR ESCAPE EXTERNAL HEX_CONV HEX_ERR HEXMSG MESSAGE MONSTAT EXTERNAL RECFULL SCRLF SREC ERR EXTERNAL SCANCHR2 SPACES EXTERNAL SRB GETCHR2 DOWNLOAD BSR SCANCHR2 DO DUMMY RD TO CLR CHAN B 2 RECFULL SRB ANY THING ELSE IN CHAN B BNE S DOWNLOAD YES SCAN CHANNEL AGAIN BSR SCRLF ECHO CR amp LF TO CRT DOWNLOOP BCLR B HEX_ERR MONSTAT CLEAR HEX ERROR FLAG S_LOOP BSR GETCHR2 GET A CHAR FROM DWNLNK PORT BTST B ESCAPE MONSTAT ESC THE DOWNLOAD PROCESS BNE DOWNEXIT YES EXIT 112 BNE BSR MOVE W BSR BSR CMPI B BEQ CMPI BEQ CMPI BEQ ADDQ CMPI BEQ ADDO CMPI BEO LOADERR LEA wz BSR DOWNEXIT BSR LEA BCLR B BEQ S RTS ERRMSG BSR RTS S RECORD BSR BCLR B BEO LEA BRA 59 RECORD BSR BTST B BEQ RTS SN RECORD CLR W CLR B BSR BTST B BNE S 757 00 S LOOP ECHO2 1 D3 GETCHR2 ECHO2 7 07 00 S RECORD 17 00 S RECORD 797 00 9 RECORD 1 03 7 2 D0 S RECORD 1 D3 737 00 S RECORD SREC ERR A5 ERRMSG SCRLF EPROMSG A5 EPROMWR MONSTAT ERRMSG MESSAGE SN RECORD HEX ERR MONSTAT DOWNLOOP HEXMSG A5 ERRMSG SN RECORD amp HEX ERR MONSTAT DOWNEXIT D6 CK SUM GETFIELD
67. NT INSTRUMENT IDENT FICATION NUMBER TO SOL POE 74 NUNBERS PROJECT ELEMENT NO WORs UNT ACCESSION NO DESIGNING A VIRTUAL MEMORY IMPLEMENTATION USING THE MOTOROLA 195013 16 BIT MICROPROCESSOR WITH MULTI PROCESSOR CAPABILITY INTERFACED THE DUS 12 PERSONA AUTHOR S DATE OF REPORT Y gt ar Month Day June 1990 5 PAGE COUNT 175 The views expressed in this thesis are those of the author and do not reflect the official policy or position of the Department of Defense or the U S 17 5 7 CODES 18 SUBJECT TERVS Continue reverse if necessary and identify by block number MC68010 Microprocessor VMEbus Virtuai Memory Dual port Memory Mul ti processor Oe Sees 19 ABSTRACT Continue on reverse if necessary and identify by block number The primary purpose of this thesis is to explore and discuss the hardware design of a bus oriented microprocessor system be expanded to a multi processor system A bus oriented microprocessor system permits it to Through the use of a bus controller and bus arbiter as discussed in this thesis the necessary logic is in place to control bus access by system users resource such as memory Bus access may be initiated to share another sub svstem s To accommodate memory sharing between two systems a dua port memory controller can be used to resolve memory access between the two systems This thesis discusses the d
68. O ECHO CHAR TO CRT BSR CONCAT ADD CHAR TO END OF STRG STRING EXIT RTS 92 CONCATENATES THE CHAR ONTO THE END OF THE STRING CMP B BS DO IS INPUT CHAR A BACKSPACE BEQ BKSPACE YES GOT BACKSPACE CMPA L BUFFIN 63 A0 IS BUFFIN FULL BNE ADD TO STRING NO ADD BYTE TO STRING LEA BUFFULLMSG A5 YES SET UP POINTER FOR MESSAGE BSR MESSAGE YES SEND MSG TO CRT BRA CONCAT EXIT YES NOW EXIT ADD TO STRING MOVE B DO 20 ADD BYTE TO STRING BRA CONCAT_EXIT BKSPACE CMPA L 20 IS BUFFIN PTR POINTING TO lst BYTE BEQ CONCAT EXIT YES EXIT SUBQ W 1 A0 NO BACKUP BUFFIN PNTR LEA SPCE A5 BSR MESSAGE CONCAT EXIT RTS END k k K k kk xk xxx xx xxx xx xx ce oe C0 o eoe CU e e c Ck A A x x ko oko ko oko X k X k Xx GET ADDRESS CONVERTS THE START AND END ADDRESS TO HEX KKK KK WRITTEN BY DR LARRY ABBOTT XX X X XX FILENAME GET ADDR ASM X X X X X X X X X X X KK XX X X X X XX XXX XX X XX X XXX XXX XXX ck IK IK ko X ok KK ok ok ck ok ok VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION DAVID SENDEK 30 SEPT 87 DOCUMENTATION UPGRADE MX MX k X XX X XX X XX X XX XX XX X X KKK xk xxx xxx xxx K
69. ONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT VECTOR VECTOR VECTOR VECT
70. OR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LUNG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG LONG UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER 82 INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT
71. PCES STRING MONSTAT SET FOR NEW STRING BACKSPACES MOVE 2 SP TO THE LEFT GETSTRING GET ANY NEW CHARACTERS STRINGEND MONSTAT CHECK FOR END OF STR MORE_CHAR IF MORE STRING BRANCH BUFFIN D3 GET STRING LENGTH NO_ENTRY IF STR LEN 0 THEN NO ENTRY 2 D3 DOES STRING LEN 2 CHGAGIN NO THEN RE ENTER GET_DATA CONVERT BYTE TO HEX HEX_ERR MONSTAT IS THERE A HEX ERROR CHG_EXIT D2 A2 1 A2 YES EXIT BUFFIN I HEX NO ENTRY CHG EXIT GET_DATA DATALOOP DATAEXIT CLR W MOVE B NEG W ADDQ W BSR RTS CLR L CLR SUBQ LEA MOVE B BSR BTST B DBNE RTS END D2 D3 D2 D2 4 D2 SPACES D2 D4 BUFFIN D4 1 D4 BUFFIN 1 0 A0 DO HEX CONV ERR MONSTAT DATALOOP 103 GET STRING LENGTH 21 lt STRING LENGTH ADJUST SPACE COUNT SPACE TO END OF BYTE CLEAR HEXBUF CLR WORD FOR DBCC INDEX GET BUFFIN LENGTH ADJUST FOR DBCC INST INITIALIZE BUFFING PNTR GET CHAR FROM BUFFIN CONV ASCII CHAR TO HEX IS THERE A HEX ERR IF MORE CHARS THEN LOOP AGAIN KK X X XX XX M V XX X X XX XX X X X XXXXX X XX XX X X XXXXX X XX XX X X X XXX THIS PROGRAM CONVERTS THE CONTENTS OF 00 lt 7 0 gt FROM ASCII TO HEX AND STORES THE RESULT IN REG D2 K Kk x k k K k k K Kk k k K k k k k Kk k k K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k x K WRITTEN BY DR LARRY ABBOTT
72. RESS FOR MC68681 PORT A PORT B R W R W R DB DD DW MSS zzz zx DW zzz MODE REG 1 FOR PORT A MODE REG 2 FOR PORT A STATUS REGISTER FOR PORT A CLOCK SELECT REGISTER A COMMAND REGISTER FOR PORT A RECEIVER BUFFER FOR PORT TRANSMITTER BUFFER FOR PORT A INPUT PORT CHANGE REGISTER AUXILIARY CONTROL REGISTER INTERRUPT STATUS INTERRUPT MASK REGISTER COUNTER MODE CURRENT CNTR MSB COUNTER TIMER UPPER REGISTER COUNTER MODE CURRENT CNTR LSB COUNTER TIMER LOWER REGISTER MODE REG 1 FOR PORT B MODE REG 2 FOR PORT B STATUS REGISTER FOR PORT B CLOCK SELECT REGISTER B COMMAND REGISTER FOR PORT B RECEIVER BUFFER FOR PORT B TRANSMITTER BUFFER FOR PORT B INTERRUPT VECTOR REGISTER OUTPUT PORT CONFIGURATION REG A4 PTR TO DUART CLR MONITOR STATUS WORD MRIRESET CRA A4 RESET PORT PTR DISABLE XMIT amp RECV MRIRESET CRB A4 PORT B PTR DISABLE XMIT amp RECV CLK_SRC ACR 4 CNTK TMR CLK FROM CRYSTAL 16 CONF_1AB MR1A A4 PORT A 8 DATA BITS 6 NO PARITY CONF 2A MR2A A4 PORT A 1 STOP BIT BAUD9600 CSRA A4 PORT A 9600 BAUD CONF_1AB MR1B A4 PORT B 8 DATA BITS amp NO PARITY CONF_2B MR2B A4 PORT 2 STOP BITS BAUD2400 CSRB A4 PORT B 2400 BAUD RUPTVECT IVR A4 SET DUART INTERRUPT SERVICE AT USER INTERRUPT 0 PORT A4 RESET ERRS amp ENABLE XMIT RCV PORT CRB A4 RESET
73. RROR BNE S DD EXIT THEN EXIT DOWN DATA BSR GETCHR2 GET SECOND CHARACTER BSR ECHO2 ECHO DWNLD CHAR TO CONSOLE CMPA L EPROMRNG IS THIS A WRITE TO EPROM BLS S EPROMERR YES GO TO EPROMERR BSR HEX_CONV CONVERT CHARACTER TO HEX MOVE B D2 A0 LOAD BYTE INTO MEMORY BRA S 50 EPROMERR BSET B EPROMWR MONSTAT FLAG EPROM WRITE SUM ADDQ L 1 A0 INCREMENT MEM LOAD ADDR TST W D4 ARE NXT CHARS CHECK SUM BEO S LOOP END YES DONT ADD TO SUM ADD B D2 CK SUM ADD THIS BYTE TC CHK SUM LOOP_END DBF D4 DOWN DATA IF MORE DATA THEN LOOP NOT B CK SUM COMPLEMENT CHECK SUM MOVE B A0 D2 GET COMPUTED CHECK SUM CMP B CK SUM D2 COMP CALC S AND XMIT CHK SUMS 5 ERRCHECK IF CHECK SUMS AGREE THEN EXIT DOWNLOAD MOVE L MONSTAT D3 BSET L CHECKSUM D3 SET FLAG IF CHECK SUM ERR MOVE L D3 MONSTAT BRA S ERR MARK BTST B EPROMWR MONSTAT A WRITE TO EPROM BEO S DD EXIT EXIT ERR MARK MOVE W D0 YES MARK ERROR WITH BSR ECHC1 DD EXIT BSR SCRLF ECHO CR amp LF RTS GETFIELD CLR L 02 CLEAR HEX BUFFER LOOPINIT MOVE W 1 D5 SET COUNT TO PACK 2 NIBBLES GF LOOP BSR GETCHR2 GET DOWNLOAD CHARACTER BSR ECHO2 ECHO DOWNLOAD CHARACTER TO CONSOLE BSR HEX CONV CONVERT ASCII CHAR TO HEX BTST B ERR MONSTAT IF HEX CONVERSION ERROR 114 GF_EXIT 5 DBF ADD B DBF RTS END GF_EXIT THEN EXIT GET FIELD D5 GF LOOP GET SECOND NIBBLE D2 CK SUM COMPUTE
74. TAT CLEAR COM FOUND STATUS BIT BEQ DECODE_INIT CHECK NEXT CMD SUB L 5 D1 ADD B D1 BUFFIN ADJUST BUFFIN LENGTH SUBQ L 2 1 ADJUST ADDRESS FOR JUMP CMD FOUND MOVE W 1 1 GET JUMP ADDRESS JSR A1 JUMP TO COMMAND BRA DECODEXT EXIT DECODER NO CMD BSR SCRLF MOVE W ERRMSG A5 SET MESSAGE POINTER BSR MESSAGE PRINT ERROR MESSAGE TO CRT DECODEXT RTS EVEN ON COMMANDS BYTE WORD BKPT_LIST BYTE LOAD WORD DOWNLOAD BYTE GO WORD GO BYTE WORD MEM DISPLAY BYTE WORD MODIFY BYTE WORD NO_BKPT BYTE WORD REGCHANG BYTE WORD REG BYTE NULL NULL NULL NULL EVEN OFF END 99 K K k k k kk KKK KKK KKK XK x KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KEKKKKKKKK KKK KK THIS PROGRAM CONVERTS A BYTE INTO 2 ASCII CHARACTERS AND IT SENDS THE CHARACTERS TO THE CRT DISPLAY K k X XXX X M X XX M MX X M MXXXXX X XX XXX X XXX X X X X X XXXXX X X XX X XXX WRITTEN BY DR LARRY ABBOTT K k K Kx xxx xxx xxx xxx xx KKK KKK KEKE KEK KKK xxx xxx xxx xx xxx xxx xx xxx FILENAME BYTEOUT ASM k k k kk kk xk KK KKK KKK KKK KKK KK KKK kx xk KKK x KKK KKK KKK kx xk xk xk KKK xxx xxx VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION A DAVID M SENDEK 1 OCT 87 DOCUMENTATION UPGRADE Kk k kk kk kk IKK KK KEK KKK KEK KKK KKK KKK KKK XXX KKK xxx xxx xxx xxx xxx KKK DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES 1 CONSOLE ASM XX MX M X
75. TS amp A DO DOES DO A 2 BEQ REGA YES ADJUST POINTER 0 00 DOES DO D BEQ REGD YES ADJUST POINTER CMPI B P D0 DOES DO P BEQ REGP YES CK FOR 6 ADJUST PNTR U DO DOES DO U 2 BEQ REGU YES CHECK FOR S CMPI B 5 00 DOES DO 5 2 BNE PRINTERR NO PRINT ERR DO lt gt A D P U S MOVE B A0 D0 GET SECOND CHAR OF CCMMAND LINE SUBQ B 1 BUFFIN SUBTRACT 1 FROM BUFFIN CMPI B 00 BEQ REGSP CMPI B R 4 DO BEQ REGREP S D0 REGD REGP REGU REGSP PRINTERR FFF REG_DONE BTST B LSL L ADD L LEA MOVE L ADD L CMPI B BNE ADDQ W SUBQ B BSR MOVE L BSR RTS PRINTERR 4 D3 REGREP 32 D3 REGFIN 64 D3 REGFIN A0 DO 1 BUFFIN C 00 PRINTERR 2 D3 REGREP A0 DO 1 BUFFIN 5 00 4 D3 REGREP 8 4 00 REGERR AS MESSAGE REG DONE A0 DO 1 BUFEZN D2 HEX CONV ERR MONSTAT PRINTERR 2 D2 D2 D3 SYSTAX Al Al Al D3 Al SPACE A0 FFF 1 A0 41 BUFFIN RCA GET ADDR A2 Al REG 111 X X XXXXXXXXXXX XXXXX XXXXXXX XXXXXX XXX XXXXXXX X XXX X X X XXXX X X X XX X DOWNLOAD ALLOWS THE MONITOR TO DOWNLOAD Sxx RECORDS ITS RESIDENT 680XX MICROCOMPUTER OVER A SECOND RS 232 PORT
76. The global interrupt signal IRQ7 has the highest priority while global interrupt signal IRQ1 has the lowest priority The NMI signal has priority over local and global interrupts and it is provided for a catastrophic occurrence such as an alternating current AC power failure Local interrupts are generated by the DUART and the MMU The DUART is programmed to provide an interrupt request when port buffer full condition is met buffer full condition of the MC68681 DUART occurs whenever a character is received from the terminal keyboard or from the IBM XT AT The local interrupt generated by the MC68451 MMU occurs when the interrupt bit of the page status register is set during normal address translation When a local or global interrupt occurs the interrupt handler hardware generates an interrupt priority level output on lines IPLO through IPL2 to the CPU The CPU responds by acknowledging the interrupt with the interrupt acknowledge signal IACK and places the interrupt level on address lines Al through A3 The interrupt handler hardware reads the interrupt level on address lines Al through A3 to determine which level is being acknowledged If the interrupt was from a local device the 52 interrupting device provides the vector number the local data bus If the interrupt was from another subsystem on the VMEbus the interrupt handler hardware generates bus interrupt acknowledge BIACK signal to the VMEbus contro
77. USED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER USER INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT 145 146 147 148 149 150 151 152 153 154 155 156 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR
78. VALUES IN HEX BREAK POINT BR NOT IMPLEMENTED NO BREAKPOINT NOBR NOT IMPLEMENTED DOWNLOAD LOAD GO GO address lt break point address gt a MEMORY MODIFY MM start address end address MEMORY DISPLAY MD start address lt end address gt REGISTER CHANGE RCH Axx Dxx PC US SP SR value DISPLAY REGISTERS REG 2 k KK xxx xxx xx xx XK x x x kx x xxx Kx xxx x xk xxx xx xxx Kx xxx xxx xxx xk xx xxx x xxx GLOBAL CMD_DECODE EXTERNAL BUFFIN ERRMSG FOUND MESSAGE MONSTAT NULL EXTERNAL SPACE SCRLF EXTERNAL BKPT_LIST DOWNLOAD GO EXTERNAL MEM DISPLAY MEM MODIFY NO_BKPT REG REGCHANG CMD DECODE LEA COMMANDS Al INITIALIZE COMMAND POINTER BCLR FOUND MONSTAT DECODE INIT LEA BUFFIN 1 A0 INITIALIZE BUFFIN POINTER MOVE L 3 1 INIT INDEX FOR 4 CHARS SCAN MOVE B A1 D0 GET COMMAND TABLE I 6 1 lt 1 1 SPACE D0 IS CHARACTER SPACE BEQ FOUND_CMD YES FOUND COMMAND CMP B NULL DO IS CHARACTER A NULL BEQ NO_CMD YES EXHAUSTED COM TABLE CMP B 00 IS BUFFIN COMMAND TABLE DBNE D1 YES amp MORE CHAR CONT BNE ADDR_FIELD NO ADJUST ADDR FOR NEXT COMMAND FOUND CMD BSET FOUND MONSTAT SET COMMAND FND STATUS CMPI W 0 D1 IS COMMAND A 4 CHAR COM BMI CMD FOUND YES SKIP JUMP ADDRESS ADJUST ADDR_FIELD ADDQ L 2 D1 ADJUST INDEX FOR NEXT COM ADD L D1 Al1 ADD INDEX TO COMMAND PNTR BCLR FOUND MONS
79. VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR MAIN IS THE ENTRY POINT INTO THE MONITOR MAIN INITIALIZES THE RS 232 PORT BEFORE ENTERING THE MONITOR ALSO MAIN CONTAINS THE MEMORY MAPS EQUATES AND MEMORY ALLOCATIONS k kk kx xxx x xxx xk xxx xk xk xk xk kk xk kx xx kx kx xk xk x KX Xx xk xxx xk xx kx xk xxx xx 68K MONITOR VERSION V1 3 AN ACCUMULATION OF ALL PRIOR VERSIONS COPYRIGHT AUG 1986 DR LARRY ABBOTT Kx k k K kk xxx kx x kx xxx xk Kx xxx xxx xx xxx xxx xxx xx xxx xxx xxx kx xxx xxx xxx FILENAME MAIN ASM k k k Kk k k k k k k k k k k k k k k k k k kk k k k KKK IK xxx KKK KKK KKK KKK kx x xxx xxx xx X k kk VERSION 1 3 REV MODIEIED BY DATE DESCRIPTION A LARRY 11 7 86 LARRY ABBOTT 12 14 86 MONSTAT ESCAPE LC LARRY ABBOTT 6 6 87 ADAPT TO MC68681 D DAVID M SENDEK 29 SEPT 7 INCLUDE VECTOR TABLE INCLUDE MONITOR PROMPT 68681 X X X X X X X X X X X X X X X X X XX X XX XX X XXX XX X X XX XX X X XX X DEFINING MODULES OF EXTERNALLY DECLARED V7RIABLES x CMD DECODE DECODER ASM GETSTRING GETSTRIN ASM MESSAGE MESSAGE ASM X MONMSG MESSAGE ASM SCRLF UTIL ASM K K X x Kk k X X
80. X X X X X X X X X X X XX X X X XX X X X XX X SCS ee See ee ee ee ee X X X X X X GLOBAL BKPTAB BS BTLEN BUFFIN CHECKSUM CK_SUM C LOBAL CONTINUE CR GLOBAL END ADDRESS EPROMRNG EPROMWR ESC ESCAPE GLOBAL FOUND FWDARW HEX ERR LF MODIFY MONSTAT GLOBAL NULL PORT1 PORT2 RBA RECFULL GLOBAL SPACE SRA SRAM SRAMSIZE STRING STRINGEND GLOBAL SYSTAX SRB TBA TBB RBB GLOBAL TBA XEMPTY GLOBAL INIT SP INIT MONITOR EXTERNAL CMD DECODE GETSTRING MESSAGE MONMSG SCRLF EXTERNAL PROMPT DATA ALL R W DATA IS STORED IN SRAM AT ADDRESS 010000 EQUATES BS EQU 08 ASCII CODE FOR BACKSPACE CR EQU 0D ASCII CODE FOR RETURN EPROMRNG EQU 3FF EPROM RNG 0 gt 3FF EXCEPTION TBL ESC EQU 1B ASCII CODE FOR ESCAPE FWDARW EQU 3E ASCII CODE FOR FORWARD ARROW LF EQU 0A ASCII CODE FOR LINEFEED 84 NULL EQU 00 ASCII CODE FOR NUL SPACE EQU 20 ASCII CODE FOR SPACE BTLEN EQU 10 BREAKPOINT TABLE LENGTH IN WORDS X MEMORY ALLOCATIONS BKPTAB BLKW 3 2 BTLEN RESERVE BTLEN 2 32 BIT BKPT s BUFFIN BLKB 3F RESERVE 63 BYTE INPUT BUFFER END_ADDRESS BLKW 2 RESERVE WORD FOR END ADDRESS MONSTAT BLKW 1 RESERVE A WORD FOR MONITOR STATUS STAX BLKW 36 SAVE AREA FOR APPLICATION 5 SYSTAX BLKW 2 RESERVE MEMORY FOR STACK POINTER CK_SUM BLKW 1 CHECK SUM STORAGE SRAM EQU DATA BEGINS AT LOW ADDR OF SRAM SRAMSIZE EQU 3FFF 16K BYTES OF STATIC RAM INIT SP EQU 5013
81. X X KK X X X ck X X X X X X X X XX XXX X XX XX XXX IOI IOI II XX XX XXXXXXXX x VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION x X YA DAVID M SENDEK 2 OCT 87 DOCUMENTATION UPGRADE K K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES 5 MAIN ASM MESSAGE MESSAGE ASM BUFFIN MAIN ASM SPCE MESSAGE ASM CR MAIN ASM CMD DECODE DECODER ASM x CONSOLE ASM GETCHAR1 CONSOLE ASM MONSTAT MAIN ASM STRING MAIN ASM 5 id STRINGEND MAIN ASM x BUFFULLMSG MESSAGE ASM K K X X X X X X X X X X X X X X XX X XX XX X X XX X XX X OK XXX TOR IO OR OR IK KO IK KK KK GLOBAL GETSTRING EXTERNAL BS BUFFIN CR CMD_DECODE ECHO1 GETCHAR1 EXTERNAL MONSTAT STRING STRINGEND EXTERNAL BUFFULLMSG SPCE EXTERNAL MESSAGE GETSTRING BSET B STRING MONSTAT IS THIS A NEW STRING BNE BUILD NO SKIP PTR INIT BCLR B STRINGEND MONSTAT YES CLR STRG END BIT LEA BUFFIN 1 A0 YES INIT STRING PTR BUILD BSR 1 00 CHR FROM CRT CMP B CR DO 1S CHAR A CR BNE ADD STRING NO ADD CHAR TO STRG BSET B STRINGEND MONSTAT YES SET STRG END MOVE W A0 D0 YES 00 CURRENT BUFFIN SUB W BUFFIN 1 D0 YES CALC BUFFIN LEN MOVE B DO BUFFIN YES BUFFIN 0 lt BUFFIN LENGTH BRA STRING EXIT YES EXIT ADD_STRING BSR ECH
82. XMX XXX XM X X XX XX X M XX M XXXX XXXM XXX XXX XXXXXXX GLOBAL OUTPUT BYTE EXTERNAL 1 OUTPUT BYTE MOVE B D0 D2 MAKE A TEMPORARY COPY OF BYTE LSR B 4 0 SHIFT M S NIBBLE TO L S NIBBLE BSR ASCONV CONVERT M S NIBBLE TO ASCII MOVE B D2 D0 20 lt TEMPORARY COPY OF BYTE ANDI B 0F D0 MASK OFF M S NIBBLE BSR ASCONV CONVERT L S NIBBLE TO ASCII RTS ASCONV ADDI B 30 D0 ADD ASCII BASE 532 00 IS NUMBER 0 9 BLT ASCOUT YES OUTPUT TO CONSOLE ADDO B 7 D0 ADJUST FOR A F HEX ASCOUT BSR ECHO1 OUTPUT TO CONSOLE RTS END K K k k k k k K Kk k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k THIS PROGRAM MODIFIES OR LISTS THE CONTENTS OF THE SPECIFIED MEMORY LOCATIONS WRITTEN BY DR LARRY ABBOTT K K k Kk k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k K k k k k k k k k k K FILENAME MEM LIST ASM VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION A DAVID SENDEK 1 87 DOCUMENTATION UPGRADE K K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k
83. ansfer synchronized with the E signal The valid memory address VMA signal from the CPU indicates to a 73 M6800 device that there is a valid address on the address bus and that the MC68010 is synchronized with the E signal 8 Processor Status The MC68010 has three function code lines FCO through FC2 which delineate the current processor state user or supervisor and the address space program or data being accessed as defined by Table IV Ref 18 p 5 3 The address strobe AS signal from the CPU indicates that a valid address and function code are available from the CPU TABLE IV STATE AND ADDRESS SPACE FUNCTION CODE OUTPUT ADDRESS SPACE UNDEFINED RESERVED FOR FUTURE USE USER DATA SPACE USER PROGRAM SPACE UNDEFINED RESERVED FOR FUTURE USE UNDEFINED RESERVED FOR FUTURE USE SUPERVISOR DATA SPACE SUPERVISOR PROGRAM SPACE CPU SPACE INTERRUPT ACKNOWLEDGE 0 0 0 0 1 1 1 1 O O i O O O O O F O 9 Miscellaneous Both Vcc pins and both GND pins must be connected in order to power the CPU The clock CLK input signal is used to develop all the synchronizing signals required within the CPU 74 PROGRAMMING Motorola provides programming information in its reference manual Ref 7 The MC68010 s instruction set includes the following operations Data Movement Bit Manipulation Integer Arithmetic Binary Coded Decimal BCD Arithmeti
84. ards to communicate with each other and to share r2sources However a strict adherence to protocols must be maintained so the integrity of information and control is preserved Memory management features include memory protection and virtual memory Special memory schemes have been used to protect a system s integrity to make more effective use of its physical memory s address range and to permit multi ported memory so that the memory resource can be shared in a multi processor system A memory protection scheme prevents users from inadvertently or maliciously tampering with the operating system its associated memory mapped hardware or other users TO accomplish this a portion of the processor s address range can be reserved for the operating system while the remaining portion is allocated to system users The operating system is protected because the user is not permitted to cross into the operating system s memory The virtual memory aspect of memory management permits a greater dynamic range and flexibility for user memory than actually exists with the system s physical memory Virtual memory allows each user to run programs as if he or she has full use of the processor s address range independent of the memory used by the operating system or the other users The user is unaware of how the physical memory in the system is allocated Therefore memory resources can be allocated automatically and respond to the dynamic nee
85. aries of a single circuit board Other subsystems or circuit boards which may include processing elements memory and or input output 1 0 devices can be integrated to the VMEbus A strict adherence to data transfer protocols over the VMEbus ensures the reliability and integrity of the system The ability to integrate various subsystems along the VMEbus supports a multi processor environment b Memory Management The Motorola MC68010 central processor unit CPU generates function codes which can be used by the memory management unit MMU to partition memory into supervisor and user portions 62 An operating system would manage memory partitioning Normally systems are designed so that the supervisor memory portion contains the memory mapped I O devices and the read only memory ROM and some random access memory RAM The ROM is mapped to the supervisor portion of memory since it provides the exception vector table and start up program The function codes reflect the CPU s two modes of operation the supervisor and user The supervisor mode is a privileged mode which permits access to all instructions and the full range of memory supervisor and user memory The user mode permits access to only user instructions and the user memory Typically in the user mode permission must be granted through the operating system to use system resources The separation of supervisor memory from user memory prevents the user from tampering
86. bi directional signal It can be used as an input to reset the internal microcircuitry within the When reset instruction is executed by the CPU it can be used to reset system devices Typically a maximum time is allotted for data transfer If the data transfer is not completed within the allotted time bus error BERR is asserted by a time out circuit called a watchdog timer Often the BERR signal is used to inform the CPU that the current address on the address bus is invalid because no physical memory or peripheral device is mapped at that address The BERR signal can also be used to flag the condition that the CPU is making an attempt to write to read only memory ROM In a virtual memory system BERR is asserted by the memory management unit MMU when a page fault occurs 7 M6800 Peripheral Control The M6800 peripheral control group is a group of signals which are used to interface the MC68010 s 16 bit asynchronous data bus to synchronous peripheral devices in the Motorola M6800 eight bit family The enable E signal which acts as the 6800 phase two clock is used to synchronize data transfer between the MC68010 CPU and M6800 peripheral device The E signal s period is ten clock periods of the MC68010 s clock input The valid peripheral address VPA signal denotes to the CPU that the device selected is a M6800 peripheral device The VPA signal indicates to the CPU that it should initiate a data tr
87. c Logical Program Control Shift and Rotate System Control Bit Manipulation Multi processor Communications supporting the following data types Bit BCD Four bits Byte Eight bits Word 16 bits Long Word 32 bits Fourteen addressing modes that are available to the assembly language programmer The addressing modes available include Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Offset Address Register Indirect with Index and Offset Absolute Short Absolute Long Program Counter with Offset Program Counter with Index and Offset Immediate Data Quick Immediate Implied Register 75 The following assets are available Eight Data Registers Seven Address Registers User Stack Pointer User Mode Supervisor Stack Pointer Supervisor Mode Program Counter Status Register Supervisor mode Vector Base Register Supervisor Mode Alternate Function Code Registers Supervisor Mode The condition code register is the lower byte of the status register and it is accessible in the user mode To support virtual memory the MC68010 microprocessor allows an interrupted bus cycle to be re run after a bus error exception The return from exception RTE instruction uses the format field of the exception stack to determine whether the exception was
88. caused by bus or address error After a bus or address error caused the exception the CPU continues the interrupted instruction after completion of the exception routine Ref 19 APPENDIX MINIMAL SYSTEM EXCEPTION VECTOR TABLE AND MONITOR DEBUGGER PROGRAM This appendix contains the source listings of the exception vector table and monitor debugger program The separate file names are as follows VECTABLE ASM MAIN ASM MESSAGE ASM CONSOLE ASM GETSTRIN ASM GET ADDR ASM IO UTIL ASM DECODER ASM BYTEOUT ASM MEM LIST ASM HEXCONV ASM GO ASM STUB ASM REG ASM REGCHANG ASM DOWNLOAD ASM UNUSED ASM Using the 2500AD 68010 cross assembler and linker a Motorola S record format file was generated as a load module The load module was loaded as a ASCII file into a Data I O System 29 Universal Programmer Once resident in the programmer the load module was programmed to erasable programmable read only memory EPROM It should be noted that the data section as contained in MAIN ASM was not programmed on EPROM but rather it resides in random access memory RAM The first two entries in the exception vector table are used during the system boot up to provide the initial contents for the stack pointer and the program counter The exception vector table contains the addresses of exception routines The monitor debugger 77 program initializes the MC68681 peripheral device and provides facil
89. cess to the desired one megabyte of RAM When the row address strobe RAS signal becomes inactive the data transfer acknowledge output from the 74F764 DTACK764 is asserted The DTACK signal of the 74F764 signals that data has been transferred to or from memory g Dynamic Random Access Memory The dynamic random access memory circuitry Figs 12 13 E 14 and E 15 provides one megabyte of DRAM for the master circuit board subsystem The DRAM is divided into two 512k byte blocks The odd bytes are stored in one 512k byte block Figs E 12 and E 13 while the even bytes are stored in the other 512k byte block Figs E 14 and E 15 The DRAM receives refresh cycles from the dual port DRAM controller Although the 74F764 dual port DRAM controller seizes control of the DRAM during refresh cycles a bus arbitration process is not needed An 8 MHz clock pulse RCP is divided by 64 to produce a refresh request internal to the 74F764 If no request signal REQ1 or REQ2 is asserted on the 74F764 a nine bit counter internal to the 74F764 is incremented The counter value which represents the row in memory to be refreshed is then placed on output lines MAO through MA8 of the 74F764 The RAS signal is then asserted for four clock cycles to refresh a row in memory Finally the RAS signal is released and the refresh cycle is complete h EPROM and SRAM The EPROM and SRAM circuitry Fig E 16 provide 64k bytes of ROM and 16k bytes o
90. cification notes invoked support ideas in the design that required further investigation These support ideas included DRAM memory refresh accommodations driver characteristics noise reduction and virtual memory Once each device was reasonably understood the problem of integrating the devices into a single system remained Care was exercised to ensure that control signals were properly integrated to the devices Consequently a major portion of this thesis was spent in the research and design process without the assistance of CAD tools The design and implementation work of this thesis spanned almost two years A major problem encountered was the inability to Simulate the system designs Hence the system s validity could only be verified by actual design implementation The design phase took a considerable length of time because the inter relationships between the devices to support a multi processor environment dual port memory virtual memory memory 67 protection dual serial ports and interrupt control features were not trivial Some of these features should have been eliminated so that a simpler design could have been implemented However using the approach of building a complex subsystem from a minimal system is an important technique For a growing number of new application Ic chips facilities to simulate designs using these chips do not yet exist Thus there is a strong need for advanced design tools and engineeri
91. cuit board subsystem The operating system would manage this resource by assigning virtual pages to physical memory It is intended that a portion of the DRAM s physical address range map to the same virtual address range This will permit global memory access to pass semaphores and messages between the master circuit board and other subsystems as discussed in Chapter I It is important c note that if an address falls into the ranges of 5014000 through S 7F4FFF 7F8000 through 57 or 5900000 through SFFFFFF the CPU is accessing an off board device 2 Master Circuit Board a Microprocessor The MC68010 CPU Fig E 3 is the processing element of the master circuit board subsystem The signals of the CPU can be organized into functional groups see Appendix A which describe the role of the signals within the subsystem The CPU has two bi directional open collector pins HALT and RESET which require pull up resistors to ensure that the signals are not asserted until the appropriate events occur The only bus master on the subsystem is the MC68010 Hence the bus request BR and the bus grant acknowledge BGACK 44 signals require pull up resistor to ensure that the CPU does not perform bus arbitration No Motorola M6800 peripherals are used in the master circuit board design Hence the valid peripheral address VPA signal is tied to a logical one The circuitry to generate the DTACK and BERR signals discu
92. d into groups and the direction of the signal flow is denoted by the arrows To avoid any confusion over logic assertion levels the asterisk at the end of a signal name is used to denote an active low assertion level 1 Address Bus The address bus consists of 23 address lines giving an eight megaword address range for the CPU 69 2 gt gt ADDRESS BUS Al A23 MISCELLANEOUS ew lt gt DATA BUS DO D15 CLK gt AS FCO lt gt R W ASYNCHRONOUS PROCESSOR lt gt UDS BUS STATUS FC2 lt gt LDS CONTROL DTACK M6800 E lt MC68010 PERIPHERAL VMA lt BR BUS CONTROL VPA gt BG ARBITRATION lt BGACK CONTROL BERR gt SYSTEM RESET lt gt lt IPLO CONTROL HALT lt gt IPL1 INTERRUPT lt IPL2 CONTROL Figure A 1 MC68010 Signal Groups 2 Data Bus The data bus is a 16 bit bi directional bus used for transferring byte or word length data 3 Asynchronous Bus Control The asynchronous bus control group provides information about the data that is being transferred The address strobe AS signal signifies that valid address signals are being gated from the CPU The read write R W line denotes that the CPU is reading from a device active high or that the CPU is writing to the device active low The upper data strobe UDS indicates that the data being transferred is on an even byte boundary The lower data strobe LDS
93. der virtual address bits give the relative address offset of the desired address within the physical page selected PAGE 0 PAGE 1 PAGE N 1 PAGE N VIRTUAL ADDRESS PHYSICAL ADDRESS gt gt lt Figure 2 6 Virtual Memory Mapping Generally each processing task has its own translation table similar to Figure 2 7 These tables are switched whenever the active task changes which avoids interference between processing tasks 20 VIRTUAL ADDRESS HIGH ORDER BITS LOW ORDER BITS VIRTUAL PAGE NUMBER TRANSLATION TABLE ADDRESS PHYSICAL PAGE PAGE 1 PAGE ADDRESS gt lt SELECTED PHYSICAL ADDRESS Figure 2 7 Mapping Mechanism When the CPU generates a virtual address in page that is not present in physical memory for instance PAGE 2 as in Figure 2 7 the memory manager senses that fact and generates a page fault The page fault triggers a chain of events which ultimateiy retrieves the desired page of the program from secondary storage and places it in physical memory The instruction which caused the page fault is then continued or restarted Ref 2 pp 326 330 21 3 Dual ported Memory Dual ported memory permits two nearly simultaneous accesses to the memory resource without conflict Figure 2 8 illustrates a typical configuration of a dual port memory device One approach to arbitrating concurrent memory requests in a dual ported rand
94. ds of the operating system and the users In a system without virtual memory programs must be executed in a specific memory space and for large programs the user must provide complex overlay schemes to circumvent the fixed user memory allocation It is difficult for such a system to support several large programs concurrently In a virtual memory system the operating system breaks up the user s program into segments called pages and moves these pages as needed between physical memory and a secondary storage device such as a hard disk Thus a virtual memory system can easily support several large programs concurrently as long as each program only requires a modest amount of memory at any given time Multi ported memory such as dual ported memory allows a common memory resource to be shared between two or more processors peripheral devices Thus different processes or different processors can communicate with each other via a multi ported memory mailbox equipped with an accompanying semaphore to maintain access control and data integrity Also multi porting provides a communication link between tightly coupled systems where there is a high degree of interaction Interrupts optimize the performance of processor An interrupt is a control signal generated asynchronously by a device such as a serial port requesting service from the processor The processor is free to process other tasks between interrupts from devices requiring service
95. e VMEbus controller provides the necessary logic to interface the master circuit board subsystem to the VMEbus 8 Interrupt Handler The Signetics SCB68155 interrupt handler is used in the master subsystem design to assist the CPU with interrupt processing The interrupt handler receives global and local interrupt requests and arbitrates their priority The arbitration priority is non maskable interrupts first then local interrupts and finally global interrupts The interrupt handler acts as a mediator between the CPU and the interrupting device or between the CPU and the interrupting subsystem Once a local interrupt is generated by the DUART or MMU control signals are sent between the interrupting device and 29 the interrupt handler as well as between the interrupt handler and the CPU The DUART or the MMU responds with a pre programmed Status ID vector as an interrupt response A subsystem can request an interrupt at any time by asserting the appropriate interrupt request line On detecting an interrupt request the interrupt handler sends a control signal to the VMEbus controller to request the VMEbus during the interrupt acknowledge cycle The subsystem making the request then sends the status ID vector to the master circuit board s CPU 30 DESIGN IMPLEMENTATION This chapter discusses the design of the minimal system and of the fully integrated system master circuit board and system controller circuit b
96. e longword at address 000008 The circuit which generates the delay time for BERR is referred as a watchdog timer Listing D 2 in Appendix D presents the Abel description of the DTACK and BERR signals The circuitry for EPROM and SRAM is illustrated in Figure C 6 Since random access memory RAM and ROM cannot generate a DTACK signal to the CPU additional circuitry is required The DTACK signal informs the CPU that the data transfer has been completed by the slave device The 7415164 shift register generates the data transfer delay times for the RAM and the ROM and the bus time out delay for bus error condition Fig C 5 250 nanosecond delay is provided to ensure an adequate time for data transfer between the CPU and the RAM A 500 nanosecond delay is provided for data transfer between the CPU and the ROM These transfer times accommodate the data propagation delay the system address decoding delay and the internal address decoding delay of the RAM and the ROM The logic for the output enable and the write enable signals are implemented on an EPLD Listing D 3 in Appendix D presents the Abel description of the SRAM write enable and RAM and ROM output enable signals Figure C 7 shows the logic for the interrupt priority level IPLO through IPL2 and the interrupt acknowledge IACK681 Signal A level one interrupt request HHL is sent to the MC68010 CPU when the MC68681 DUART asserts its interrupt request output low A
97. e pathways for the data signals the address signals and their associated control signals The process of resolving bus ownership takes place on the data transfer arbitration bus The priority interrupt bus is used to accommodate processes which request servicing from another subsystem An interrupt stops normal bus activity until the interrupt is serviced The utilities bus is sometimes referred to as a miscellaneous functions bus It includes a system reset line an alternating current AC power failure line a system failure line and a system clock Ref 2 p 475 The design in this thesis uses the VMEbus controller and the interrupt handler hardware devices which are designed for use with the VMEbus 3 Configurations In a multi processor VMEbus based system with a variety of peripheral devices each subsystem can fulfill one of three primary roles The subsystem can serve as a slave only as a master only or aS a master slave combination A subsystem can also have the role of direct memory access DMA in a master slave configuration To limit the size and complexity of this thesis the DMA master Slave configuration is not discussed These roles determine the way the subsystem is integrated to the system bus a Slave Only Application In the slave only configuration the subsystem is Slaved to the VMEbus In other words this subsystem is incapable of making a request to obtain access and control of the VMEbus The slave s
98. endix D shows the Abel source code that generates the logic implementations discussed in this chapter and illustrated in Figures 4 5 C 6 and C 7 40 FULLY INTEGRATED SYSTEM The intent of this thesis is to design a hardware system so that at some future date an operating system could be developed to control its hardware facilities These facilities accommodate virtual memory protected memory serial communications interrupt control and multi processor abilities interfaced to the VMEbus A hard disk controlled by a direct memory access DMA controller would be needed to implement the paging function required to support virtual memory The operating system would use the memory management unit MMU to implement user supervisor memory allocations protected memory and virtual memory Considerations for a future operating system will be discussed throughout the following sections The fully integrated system is composed of the master circuit board subsystem and the system controller subsystem Fig 3 1 Each subsystem is decomposed into functional units The functional units for the master circuit board subsystem are shown in Figure E 1 and the functional units for the system controller subsystem are shown in Figure E 2 Each of the functional units for the subsystems is discussed in the following sections 1 Memory Map The memory map Table II of the master circuit board s physical address space contains the memory ma
99. ering operating cost through increased speed and power and by lowering design maintenance and upgrade costs through modular design techniques Architectural innovations can accelerate this process Hence new innovations in system architecture are constantly sought after Architecture is used here to mean the structuring of the modules which are organized into a computer system Ref l p 1 These modules include processors memory and input output 1 0 devices A uni processor system consists of a single processor subsystem and various supporting modules integratei to form a system In contrast a multi processor system is comprised of two or more processor subsystems connected into one interrelated functional system In a multi processor system the interconnection of the processor subsystems must be done in such a way as to maintain control and manage the data flow of the entire system This may be accomplished through multi ported memory a serial link or as in this thesis by a system bus A number of computer architectural designs that accommodate growing needs are examined in this thesis Key architectural features of bus structures memory management and interrupt control are described in this chapter Bus structures allow for the integration of peripherals memory and application specific boards into one coherent system Bus structures permit the exchange of data and control signals between circuit boards This allows circuit bo
100. esign of a MC68010 microprocessor system integrated on the VMEbus with dual ported memory capability Additional features of the MC68010 microprocessor system include memory management and interrupt control memory management features permit protected memory and virtual memory to be implemented on the system while an interrupt nandler is used to assist the MC68010 microprocessor in exception processing 20 OSTRIBITION AVALAR Y OF ABSTRACT oNciassittD DI save as cia OF RESPONSIBLE INDIVID GAL Larry W Abbott DD Form 1473 JUN 86 1 one 95685 Previous editions are obsolete S N 0102 LF 01 6603 21 ABSTRACT SECUR TY CL ASS CATION i find 22b TELEPHONE Include Area Code 2206 OFFICE SV VRO 483 8 CLASSE CATON U classified Approved for public release distribution is unlimited DESIGNING VIRTUAL MEMORY IMPLEMENTATION USING THE MOTOROLA MC68010 16 BIT MICROPROCESSOR WITH MULTI PROCESSOR CAPABILITY INTERFACED TO THE VMEbus by David M Sendek Lieutenant United States Navy B S The College of Charleston 1981 Submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING from the NAVAL POSTGRADUATE SCHOOL Author David M Sendek Approved by W Abbott Thesis Advisor Electrical and Computer Engineering 11 ABSTRACT The p
101. f SRAM The EPROM contains the resident exception vector table and the monitor debugger program The SRAM is upward compatible from the minimum system If additional memory is required by a resident operating system a modification to the local bus address decoding logic would permit the size of ROM or RAM to be increased 1 Dual Serial Port The MC68681 dual universal asynchronous receiver transmitter serial port circuitry Fig E 17 is used to provide serial communications with the terminal and the IBM XT AT computer Port A is dedicated to the terminal and Port B is dedicated to the XT AT computer The 3 6864 MHz crystal is used to generate the baud rates for data transmission for both ports The terminal provides an interface to the system for the user The IBM XT AT is used to down load files into the master circuit board subsystem s memory j Interrupt Handler The interrupt handler circuitry Fig E 18 provides the necessary logic to accomnodate interrupts from devices residing on the master circuit board subsystem and global devices residing on other subsystems The SCB68155 interrupt handler can 51 accommodate six local interrupts seven global interrupts and a non maskable interrupt NMI Local interrupts LRQ1 through LRQ6 have a higher precedence than the global interrupts 01 through IRQ7 The local interrupt signal LRQ6 has the highest priority while local interrupt signal LRQ1 has the lowest priority
102. g Company Reading Ma 1987 Clements A Microprocessor System Design 68000 Hardware Software and Interfacing PWS Publishers Boston Ma 1987 Borrill P L Microstandards Special Feature A Comparison of 32 Bit Buses IEEE MICRO Vol 5 No 6 pp 71 79 December 1985 The VMEbus Specification Printex Publishing Inc Tempe Az 1985 Pri Tal S and MacKenna C Understanding VMEbus Architecture Electronic Products Vol 27 No 19 pp 103 110 15 March 1985 Stone H S Microcomputer Interfacing Addison Wesley Publishing Company Reading Ma 1983 68000 8 16 32 Bit Microprocessors Programmer s Reference Manual Prentice Hall Englecliffs N J 1986 MC68452 Bus Arbitration Module Advance Information Motorola Semiconductors Phoenix Az 1985 68000 08 10 Cross Assembler 2500AD Software Inc Aurora Co 1987 MC68000 Educational Computer Board User s Manual Motorola Inc Tempe Az 1982 ABEL 2 0 Data I O Corp Santa Clara Ca 1986 Brooks S L The Design of an Intelligent Multidisk Control Module for VME bus Based Systems Master s Thesis Naval Postgraduate School Monterey Ca December 1987 Memory Management Unit Advance Information Motorola Semiconductors Phoenix Az 1983 Microprocessor Data Manual Signetics Corp Sunnyvale Ca 1986 159 15 16 17 18 19 MC68681 Dual Asynchronous Receiver Transmitter DUART Advance Informat
103. he Motorola MC68010 microprocessor has 23 address lines Al through A23 The upper data strobe UDS and lower data strobe LDS lines collectively determine address bit Effectively there are 24 address lines giving an virtual address range of 16 megabytes Physical memory elements such as static random access memory SRAM dynamic random access memory DRAM and read only memory ROM are mapped into this 16 megabyte range as are the memory mapped peripherals 32 The memory mapped peripheral devices have multiple internal registers The high order physical address bits are used to select a particular peripheral device The low order physical address bits are decoded inside the peripheral device and subsequently select one of the internal registers These registers are programmed to configure the device to meet desired performance specifications Table I displays the specific locations of the minimal system s memory mapped devices and the physical memory components within the address space of the MC68010 central processor unit TABLE I MINIMAL SYSTEM MEMORY MAP PHYSICAL ADDRESS 000000 64K BYTES OF EPROM SOOFFFF 010000 16K BYTES OF STATIC RAM 013FFF 014000 NOT USED 57L6LLL 57 7000 68681 DUART S7F7FFF 7 8 000 NOT USED SFFFFFF The 64k bytes of erasable programmable read only memory EPROM contain the exception vector table and the monitor debugger program Appendix B gives the source
104. he global bus side In each case the select line is released after the request signal is no longer asserted If both request lines are asserted and neither select line is asserted on the next rising or falling clock edge the select signal will be generated for the appropriate port access The request that is locked out cannot gain access to the dual port DRAM controller until the other port has completed its task and is no longer asserting its request signal 74152455 octal bus transceivers with 3 state outputs illustrated in Figure E 10 are used to buffer the data Signals Data can be sent between the CPU and the VMEbus between the CPU and the DRAM or between the DRAM and the VMEbus The data enable signal DATAEN enables data to flow between the CPU and the VMEbus The select port one SEL1 signal enables data to flow between the CPU and the DRAM while the SEL2 signal enables data to flow between the DRAM and the VMEbus The data flow direction to the 74152455 is controlled by the read write R W signal during local DRAM accesses while the global R W signal GR W controls the direction for global DRAM accesses The data direction enable DDEN signal controls the data direction flow between the CPU and the VMEbus The 74F764 can only effectively accommodate 18 address lines Consequently additional logic illustrated in Figure 11 must be incorporated to handle address bit 19 which is required to give ac
105. he integration of these various components into a multi processor system that comprises the work that is original to this thesis 131 174 oanbtg xoorg Teuot young 03509 199SPW 1111 pu MOYLG uOor32euuo 5 CL 800580 5 ss rzppv TC sng WWus pu 2 210d Teng IJTNDITD 2204 Teng NOOTI x LASTA pue LIYH 53104 2C2 59 Z 132 1032104 usnd 79534 2714 soinbta xoord we AsdAS HTLIL uorqo uuoo CC SI9AIJQ 5 TC UOTIBIIJTAIV x LASAYSAS uo j 4ng usnd 79594 lt H ounbrt4 0558 019 012LVI 010890 1111 010892N AS AGt 6 486 19 AG t szojstsay
106. ighest priority bus request The bus grant signal is then daisy chained down on the level of the highest 24 priority bus request This VMEbus arbitration method combines the advantages of both the daisy chain arbitration and parallel arbitration methods discussed in Chapter II DEVELOPMENT SYSTEM TERMINAL CRT and KEYBOARD DUAL PORT DRAM CONTROLLER IACK DAISY CHAIN DRIVER VMEbus INTERRUPT CONTROLLER HANDLER MASTER CIRCUIT BOARD SYSTEM CONTROLLER CIRCUIT BOARD VMEbus Figure 3 1 System Block Diagram 2 Manual Reset The manual system reset provides a system wide master reset of all devices within all subsystems Resetting the system re initializes various devices within it This is necessary in order to restart the system after system failure 25 3 Interrupt Driver The VMEbus structure provides the IACK signal daisy chain However a driver is provided on the system controller circuit board to drive the IACK signal onto the VMEbus B MASTER CIRCUIT BOARD The master circuit board is the primary design focus of this thesis As shown in Figure 3 1 the master circuit board subsystem is composed of nine functional blocks These functional blocks are the central processor unit CPU dual universal asynchronous receiver transmitter DUART dynamic random access memory DRAM Static random access memory SRAM erasable programmable read only memory EPROM memory management unit MMU dual
107. ion Motorola Semiconductors Phoenix Az 1985 Altera Data Book Altera Corporation Santa Clara Ca 1987 DRAM Dual Ported Controllers Product Specification Signetics Corp Sunnyvale Ca 1987 MC68010 MC68012 16 32 Bit Virtual Memory Microprocessors Advance Information Motorola Semiconductors Phoenix Az 1985 MacGregor D and Mothersole D S Virtual Memory and the MC68010 IEEE Micro Vol 3 No 3 pp 24 39 June 1983 160 10 11 12 BIBLIOGRAPHY 74LS764 DRAM Controller Product Specification Signetics Corp Sunnyvale Ca 1986 Baliga S Simplifying VMEbus System Design VMEbus System Magazine pp 23 25 Fall Winter 1986 Baliga S Three Chip Control Set Trims VMEbus Logic For Asynchronous Systems Electronic Design Vol 33 No 2 pp 207 214 24 January 85 Brown G and Harper K MC68008 Minimum Configuration System Motorola Inc 1984 Harper K Terminal Interface Printer Interface And Background Printing For An MC68000 Based System Using The MC68681 DUART Motorola Inc 1984 MacKenna C Bus Controller Chip Lets Processor Board Switch Master And Slave Roles Electronic Design Vol 32 No 13 pp 243 254 28 June 1984 MC68000 Educational Computer Board User s Manual Motorola Inc Tempe Az 1982 MTT8 Course Notes Motorola Semiconductors Phoenix Az 1986 Reddy A Dynamic Memory Refresh Considerations Motorola Inc 1983 Scales
108. ircuit board subsystem However if an operating system requires more that the 64K byte size of ROM which is a likely possibility any range spanning the physical addresses 5010000 through S7F4FFF could be allocated for more ROM or RAM This would require changing the address decoding logic and adding or RAM chips to the master circuit board subsystem design The MC68451 Ref 13 is memory mapped because its internal registers must be programmed for the desired virtual memory configuratior and address translation By using the MC68010 s function codes see Appendix A along with the desired address translation scheme an operating system can separate the supervisor s address space from the user s address space thus implementing a memory protection scheme The SCB68155 interrupt handler hardware Ref 14 pp 2 369 2 385 is memory mapped so that it can be initialized for the desired mode of operation The interrupt handler can accommodate local interrupts from the DUART and the MMU as well as interrupts from global bus masters The MC68681 DUART Ref 15 provides the interface to two RS 232 serial links One link is used for communications with the 43 terminal while the other link is used for communications with IBM XT AT computer The DUART is configured to provide the desired serial communications characteristics such as baud rate parity and stop bits One megabyte of DRAM is provided for the master cir
109. ities for performing software debugging and the down loading of files from an IBM XT AT compatible computer 78 EXCEPTION VECTOR TABLE K K X Kk K XX XX KKK KKT KKK XX XX XK x xk xxx xxx xx xxx xxx X XXXX XX XXX XXXXX X XX WRITTEN BY LARRY ABBUTT JUNE 5 1987 K k K Kx xxx xxx xk xxx xx xxx xx XK xxx KKK xk xx xxx e KKK KKK KKK k kk FILENAME VECTABLE ASM kk KK Xxx xxx kx x xk xk xxx xxx xk xxx xxx xk KKK xk xxx xxx xx x xe koe k ke ko ko ko k k k k kk xk xxx VERSION 1 3 REV DATE NAME DESCRIPTION A 29 SEPT 87 DAVID M SENDEK ADDITIONAL DOCUMENTATION DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES GO ASM INIT MAIN ASM INIT SP MAIN ASM MESSAGE MESSAGE ASM MONITOR MAIN ASM UNUSED UNUSED ASM X X koe X XX XX xxx xxx XXX X XX X xxx X xk x KKK xk xxx xx xk xx xxx kx X XX x x kx kk ko xxx xxx EXTERNAL BKPT INIT INIT SP MESSAGE MONITOR EXTERNAL UNUSED ORG 0 VECTOR TABLE STARTS AT ABSOLUTE ADDRESS 000000 LONG INIT_SP INITIAL STACK POINTER VECTOR LONG INIT INITIAL PROGRAM COUNTER PC VECTOR LONG UNUSED Bus ERROR VECTOR LONG UNUSED ADDRESS ERROR VECTOR LONG UNUSED ILLEGAL INSTRUCT
110. k k X k k k k k k k k k k Xk DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES BUFFIN MAIN ASM MONSTAT MAIN ASM BACKSPACES UTIL ASM OUTPUT BYTE BYTEOUT ASM END ADDRESS MAIN ASM SCRLF IO UTIL ASM ESC MAIN ASM SCROLL IO UTIL ASM GET ADDR ADDR ASM SPACE MAIN ASM GETSTRING GETSTRIN ASM SPACES IO UTIL ASM HEX CONV 5 STRINGEND MAIN ASM ERR MAIN ASM STRING MAIN ASM MODIFY MAIN ASM GLOBAL MEM_DISPLAY MEM MODIFY EXTERNAL BUFFIN BACKSPACES END ADDRESS ESC EXTERNAL GET_ADDR GETSTRING HEX_CONV HEX_ERR MODIFY EXTERNAL MONSTAT OUTPUT_BYTE SCRLF SCROLL SPACE SPACES EXTERNAL STRINGEND STRING MEM MODIFY BSET B MODIFY MONSTAT SET MODIFY FLAG BSR MEM DISPLAY DISPLAY MEMORY BCLR B MODIFY MONSTAT CLEAR MODIFY FLAG RTS THIS PROGRAM LIST THE CONTENTS OF THE SPECIFIED MEM DISPLAY CMPI B SPACE 0 DOES BUFFIN I CHAR SPACE BNE START_ADDR NO GET START amp END ADDRESS ADDQ W 1 A0 YES SO I lt 1 1 SUBQ B 1 BUFFIN DECREMENT BUFFIN LENGTH BRA MEM DISPLAY CONT SCANNING BUFFIN START_ADDR BSR GET_ADDR CONVERT ADDRS TO HEX BCLR B HEX_ERR MONSTAT WAS THERE AN HEX ERROR BNE MD_EXIT YES SO EXIT NEWLINE BSR SCRLF MOVE CURSOR TO NEXT LINE BSR LINE NUMBER DISPLAY
111. k k k k k k k k k k k k k k kk X X XX XX X XX X M X XXXX X X X X X X X THIS PROGRAM DECODES COMMANDS FROM THE COMMAND LINE MX X XX XX xk xx xk x xk xx XK xxx xk x xxx xx xxx xx XK x XK Xk XK XK XK KKK xk xxx xxx xxx xxx xxx xxx xxx 68K MONITOR VERSION 1 3 WRITTEN BY DR LARRY ABBOTT NOV 7 1986 k Kk k Kk k k k k k k k k k k f K K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k FILENAME DECODER ASM K Kk xxx xxx xxx wKx xk xxx X XX X XX XX XXX X X X x xk xxx xxx xxx xx VERSION 1 3 REV MODIFIED BY DATE DESCRIPTION DAVID SENDEK 1 87 DOCUMENTATION UPGRADE Kk K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k K k k k k k k Kk k k k k k k k k k k k k k DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES BUFFIN MAIN ASM BKPT_LIST STUB ASM ERRMSG MESSAGE ASM DOWNLOAD DOWNLOAD ASM FOUND MAIN ASM GO GO ASM MESSAGE MESSAGE ASM MEM DISPLAY MEM LIST ASM 5 MAIN ASM MEM MODIFY MEM LIST ASM NULL MAIN ASM NO_BKPT STUB ASM SPACE MAIN ASM REG REG ASM SCRLF 10 UTIL ASM REGCHANG REGCHANG ASM GO ASM MX X Ok ok oe XX XX KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK KE KKK KE KEK KKK kXk k COMMAND FORMATS LEGEND lt gt OPTIONAL SELECT ONE ITEM X X NUMBER 0 gt 15 id NOTE ALL ADDRESSES AND
112. ller and the VMEbus The VMEbus controller obtains control of the data transfer bus DTB so that an interrupt vector can be obtained from the interrupting subsystem The BIACK signal is only generated if the bus interrupt level is not masked within the interrupt handler and a local interrupt is not pending Once the local CPU has acknowledged the local or global interrupt request and has obtained an interrupt vector the local CPU saves the state of the machine and transfers control to the appropriate interrupt handling routine This prepares the CPU to perform an interrupt handling routine After completion of the interrupt handling routine the stored state of the machine is restored and the CPU resumes processing where it left off at the interrupt Ref 7 4 3 4 16 Ref 18 5 1 5 15 k Data Transfer Acknowledge aud Bus Error Generation The data transfer acknowledge and bus error generation circuitry Fig E 19 provides control signals to the CPU This circuitry physically resides within a Altera EP310 EPID The DTACK signal denotes that a data transfer has been completed by the slave device addressed The MC68681 DUART C68451 MMU SCB68172 VMEbus controller SCB68155 interrupt handler and 74F764 dual port DRAM controller peripheral devices possess the necessary logic to generate their own DTACK signal to acknowledge receipt or availability of data The master circuit board s RAM and ROM chips
113. m reset the microprocessor s program counter is initially loaded with address 002000 to start the monitor debugger program b Monitor Debugger Commands The monitor debugger program provides a user with six commands These commands are not intended to be comprehensive but 38 they do provide assistance in program development and debugging The user commands are as follows GO address lt break point address gt MM start address lt end address gt MD start address lt end address gt RCH Axx PC US SP SR REG LOAD where lt gt implies optional implies select one entry The GO command is used to execute a program that resides in the system s memory The program can be placed in memory by using the memory modify command or by down loading a program from an IBM XT AT compatible computer The address in the GO command gives the location where program execution will begin An optional break point address can be added within the GO command The break point will stop program execution at the address specified This is particularly useful if one desires o know the state of the machine i e memory contents or register contents at that point The memory modify command MM is used to modify the contents of an address or if desired a range of addresses This command can modify code or data residing in RAM The memory display command MD is used to display the contents of an address
114. n IACK681 signal is sent to the DUART when a level one interrupt acknowledge is output by the CPU The logic for the IACK681 and the IPLO through IPL2 signals are actually implemented with an EPLD Listing D 4 in Appendix D presents the Abel description of the IACK681 and IPLO through IPL2 signals 37 Figure C 8 illustrates the circuitry which supports the dual serial ports As mentioned earlier one port Port A of the DUART is configured to communicate with the terminal The other port Port B is configured by the monitor debugger program to accommodate the down loading of files from an IBM XT AT compatible computer 3 Software Support a Exception Vector Table and Monitor Debugger Program The exception vector table contains the addresses of routines to be executed when an exception trap or interrupt is detected The monitor program sets up communications with the terminal provides debugging commands as well as down load command The exception vector table and the monitor debugger program Appendix B reside in the EPROM starting at physical address 000000 The exception vector table occupies physical addresses 5000000 through 0003FF Ref 7 4 5 Physical addresses 5000400 through 001FFF are not used the monitor debugger program begins at the arbitrarily selected physical address 002000 The monitor debugger program was developed on the Motorola Educational Computer Board ECB Ref 10 After a syste
115. n the falling clock edge The other request is locked out until the request line of the recognized port is no longer asserted The other port will then gain access on the appropriate clock edge 23 III SYSTEM OVERVIEW This thesis seeks to design a system that satisfies the design requirements for a system that can be expanded to a multi processor system Additionally the subsystem design is interrupt controlled with both virtual memory and dual ported memory support This chapter gives a system perspective on the hardware associated with the system controller circuit board and master circuit board Fig 3 1 integrated to the VMEbus A SYSTEM CONTROLLER CIRCUIT BOARD The VMEbus specification describes the system controller as a board which resides in slot one of the VMEbus back plane Ref 4 5 The system controller circuit board design provides priority bus access arbitration a manual system reset and a interrupt acknowledge IACK daisy chain driver The system controller subsystem uses line drivers to buffer the arbitration signals and IACK signal on the VMEbus 1 Priority Bus Arbitration The Motorola MC68452 bus arbitration module BAM peripheral device Ref 8 was selected to perform the VMEbus access arbitration The BAM is configured to accommodate four bus request BRx inputs and four bus grant BGx outputs After parallel arbitration a bus grant signal is generated by the BAM at the level of the h
116. ng practices to support complex designs An important restriction of the master circuit board subsystem design is the lack of an operating system The capability provided in this thesis could not be fully utilized without an operating system and a mass storage device such as a hard disk Managing the virtual memory and protected memory requirements would require a tremendous amount of code which is beyond the scope of this thesis However while designing the master circuit board subsystem foresight was exercised to consider the requirements of an operating system This confirms the need for a dialogue between system designers and operating system designers to communicate the system requirements 68 APPENDIX MC68010 16 BIT MICROPROCESSOR Since the entire hardware system design revolves about the MC68010 microprocessor a description of the microprocessor its external signals and its programming is appropriate A MC68010 DESCRIPTION The 68010 has seventeen 32 bit general purpose registers a 16 megabyte address space virtual memory machine support 57 instructions with 14 addressing modes using five main data types and memory mapped input output 1 0 Ref 7 p 1 1 Motorola provides a complete signal description and timing analysis of the MC68010 microprocessor Ref 18 B MC68010 SIGNALS The MC68010 central processing unit CPU comes in a 64 pin package As shown in Figure A 1 the signals are organize
117. oard The minimal system provides the foundation of core resources necessary to construct a computer system The fully integrated system design can be implemented by integrating additional resources to the minimal system For comparison the fully integrated system is illustrated in Figure 3 1 while the minimal system is illustrated in Figure 4 1 DEVELOPMENT SYSTEM TERMINAL CRT and KEYBOARD MINIMAL SYSTEM Figure 4 1 Minimal System 31 MINIMAL SYSTEM Currently at the Naval Postgraduate School NPS there exists no computer aided design CAD tools which can simulate the fully integrated system designed in this thesis This is in part due to the inability of the CAD vendors to keep with the profusion of extremely complex very large scale integrated VLSI circuit chips The CAD systems at NPS Valid Inc s SCALD and Futurenet s CAD50 do not support all the peripheral devices incorporated within this thesis Consequently a step by step progression was made to fully integrate the system The first stage referred to as the minimal system includes the core resources which form the foundation to which more complex devices can be added When more complexity is added to the minimal system operational testing can be conducted to insure proper integration of the new devices into the system 1 Memory Map Memory mapping determines how the microprocessor accesses physical memory and peripheral devices T
118. om access memory RAM is to sample one request line on the rising clock edge and the other on the falling clock edge A PORT 1 REQUEST is assumed to be sampled on the rising clock edge PORT 1 PORT 2 ADDRESS BUS 74152445 74152445 ADDRESS BUS DATA BUS 741 52455 74152455 DATA BUS CONTROL BUS 74LS244s 74LS244s CONTROL BUS PORT 1 GRANT PORT 2 GRANT PORT 1 REQUEST DUAL PORT MEMORY DEVICE PORT 2 REQUEST CLOCK ADDRESS BUS MEMORY Figure 2 8 Dual ported Memory DATA BUS If a PORT 1 REQUEST is asserted PORT 1 GRANT is generated which gates the PORT 1 address data and control lines through the left hand 74152445 and 74152455 in Figure 2 8 The address and control signals are sent to the dual port memory device and the data 22 Signals are sent directly to memory The dual port memory device then gates the address lines to memory While the PORT 1 GRANT is active the PORT 2 GRANT cannot be asserted PORT 2 is thus locked out from gaining access to memory In contrast if a PORT 2 REQUEST is asserted and PORT 1 is inactive a PORT 2 GRANT is generated This causes PORT 2 to gate the control and address lines through the other 74152445 to the dual port memory device and to gate the data lines directly to memory via the 74LS245s In the event that both request lines are active a PORT 1 GRANT will be generated on the rising clock edge or a PORT 2 GRANT will be generated o
119. om the crystal oscillator into rates that accommodate the CPU the MMU the dual port DRAM controller and the interrupt handler hardware A 4 MHz signal is sent to additional circuitry to help generate the DTACK and BERR signals d Local Bus Address Decoding Once a virtual address is mapped to a physical address the local bus address decode circuitry Fig E 6 is used to generate chip select signals for RAM ROM or a peripheral device based upon the system memory map Table II Two Altera EP310 EPLDs Ref 16 2 57 2 62 were used in the design to be programmed via Abel software Ref 11 As mentioned earlier Abel is software developed by Data I O Corporation that permits a high level language description of the logic function to be programmed on a EPLD programmable array logic PAL or similar logic device e Memory Management Unit The MMU circuitry Figs E 7 and E 8 provides the subsystem with virtual memory support and memory protection The address translation from a virtual address to physical address is done by this device Once the MC68451 MMU has been configured by the operating system the address translation is performed 46 internally within the MMU and is thus hidden from the subsystem unless a page fault occurs The internal details of the MMU are given in its reference manual Ref 13 A page fault FAULT signal is generated if the MMU detects a write violation or if address translation cannot
120. onents into a system care was taken to ensure that the control signals were interfaced properly Since no computer aided design CAD tools existed at the Naval Postgraduate School NPS to fully simulate even the minimal system design prototyping the minimal system was necessary The minimal system has a foundation of core resources The intent was to prove the system design by building up a master circuit board subsystem from the minimal system The system controller subsystem provides a bus arbiter interrupt acknowledge IACK daisy chain driver and system wide reset The bus arbiter determines bus ownership between subsystems that make bus requests and it grants bus ownership to the subsystem with the highest priority An IACK daisy chain driver sends the IACK signal on to the bus during an interrupt acknowledge cycle 65 The system reset is used to reset all devices all subsystems after a system failure The master circuit board subsystem accommodates the VMEbus structure virtual memory mapping facilities a protected memory scheme dual ported memory and interrupt handling hardware The master circuit board subsystem design is an extension of the minimal system and should not be implemented until the minimal system is operational In the master circuit board subsystem the VMEbus controller provides the necessary logic to meet the VMEbus specification for setting up the baseline bus structure Drivers and transceivers
121. oom environment SYSTEM CONTROLLER DATA COMMUNICATIONS STORAGE LOGIC LOGIC DEFINED BY THE BUS DEFINED BY THE BUS SYSTEM BUS LOGIC DEFINED BY THE BUS PROCESSOR PROCESSOR Figure 1 1 Generic Multi Processor System II DESIGN CONCEPTS The concepts addressed in this thesis are limited to bus structure organization memory management and interrupt control These features are commonly used in today s processor systems However many options are available within each area This thesis design is a virtual memory implementation of a MC68010 based microprocessor system integrated on the VMEbus with dual ported memory Capability Borrill Ref 3 highlights several advantages of the VMEbus The VMEbus through its non multiplexed address lines and data lines does not have multiplexing delays as do other buses nor does it have the transactional protocol overheads as do some other buses In addition the non multiplexed address lines will support address pipelining For interested readers Borrill has made a detailed comparison of the features and performance of the VMEbus Futurebus Multibus II Nubus Fastbus Ref 3 In addition to the advantages that Borrill highlights the VMEbus structure was selected because of the relative ease of integrating Motorola and Signetics peripheral hardware devices These hardware devices include a memory management unit VMEbus controller
122. ort DRAM Controller Circuitry Page 2 of 3 141 Dual port DRAM Controller Circuitry Page 3 of 3 142 Dynamic Random Access Memory Circuitry Page 1 143 Dynamic Random Access Memory Circuitry Page 2 GL Se ae eae 144 Dynamic Random Access Memory Circuitry Page evene testo 145 Dynamic Random Access Memory Circuitry Page 4 Of 4 SSS Seer eee eer 146 EPROM SRAM CE LTCULE IV soso eee 147 Dual port Asynchronous Receiver Transmitter Serial P rt Circuitry 148 Interrupt Handler Circuitry 149 DTACK and BERR Generation Circuitry 150 VMEbus Controller Circuitry 151 VMEbus Address Decode Circuitry 152 Master Circuit Board VMEbus Drivers Circuitry Page I Of ASR ESSEN See s 153 Master Circuit Board VMEbus Drivers Circuitry Page 2 0 154 Master Circuit Board VMEbus Drivers Circuitry Page 3 0 3 siiski eee 155 E 25 VMEbus Arbitration Circuitry 156 E 26 SYSRESET Generation Circuitry 157 E 27 System Controller VMEbus Drivers Circuitry 158 1 INTRODUCTION Economic pressure constantly forces computer design and technology to produce more cost effective system implementations Computers are made more cost effective by low
123. pped peripheral devices and the physical memory This mapping is an enhanced version of the minimal system s physical memory map Table I 41 TABLE II SYSTEM MEMORY MAP PHYSICAL ADDRESS 000000 64K BYTES OF EPROM SOOFFFF 010000 16K BYTES OF SRAM 013FFF 014000 OFF BOARD RESOURCE S7F4FFE 7F5000 MC68451 MMU 7 5 7 6000 SCB68155 INTERRUPT HANDLER S7F6FFF 7F7000 MC68681 DUART 57 7 57 8000 OFF BOARD RESOURCE 57 5800000 ONE MEGABYTE OF DRAM S8FFFFF 900000 OFF BOARD RESOURCE SFFFFFF The memory map allocates 64K bytes of ROM to include the interrupt vector table monitor debugger program and operating System The interrupt vector table and monitor debugger program perform the same roles as described in the minimal system However an operating system would have to be incorporated to handle the enormous code requirements to manage user supervisor memory allocations protected memory page faults for virtual memory and an operating system kernel The intent is for the core of the operating system to reside in ROM since a mass storage 42 device is not incorporated in this subsystem design A design of a multi disk control module for VMEbus based system was presented in an earlier thesis Ref 12 The 16k bytes of SRAM retains upward compatibility with the minimal system The SRAM will be used until the DRAM can be incorporated into the master c
124. ress which is not currently present in physical memory When such an attempt is detected the MMU generates a page fault This page fault causes the page fault exception routine to be invoked The exception routine reads a page of information from secondary storage into RAM The MMU maps the virtual addresses associated with the page into addresses in the physical RAM After completion of the exception routine program execution resumes with the completion of the instruction that caused the page fault C Interrupt Control Using interrupts results in more effective use of the microprocessor because the microprocessor is not kept waiting for a device to respond The devices requesting interrupts in this thesis are programmed to provide an interrupt vector number during an interrupt acknowledge cycle for local interrupts The interrupt 64 vector number causes the address of the exception routine to be obtained from the exception vector table by the CPU so that it can be executed 2 Design Implementation a Hardware Configurations The recommended wiring configurations that accompanied the product specifications for the MMU VMEbus controller dual universal asynchronous receiver transmitter DUART dual port DRAM controller interrupt handler hardware and bus arbitration module BAM greatly assisted in the designs of the minimal system system controller subsystem and master circuit board subsystem However in order to integrate these comp
125. rimary purpose of this thesis is to explore and discuss the hardware design of a bus oriented microprocessor system A bus oriented microprocessor system permits it to be expanded to a multi processor system Through the use of a bus controller and bus arbiter as discussed in this thesis the necessary logic is in place to control bus access by system users Bus access may be initiated to share another sub system s resource such as memory To accommodate memory sharing between two systems dual rort memory controller can be used to resolve memory access between the two systems This thesis discusses the design of a MC68010 microprocessor system integrated on the VMEbus with dual ported memory capability Additional features of the 68010 microprocessor system include memory management and interrupt control The memory management features permit protected memory and virtual memory to be implemented on the system while an interrupt handler is used to assist the MC68010 microprocessor in exception processing Accession For NTIS GRA amp I DTIC TAB o Unannounced a 2 and or Special II III INTRODUCTION 1 DESIGN CONCEPTS 6 A VMEbus SPECIFICATION 7 Pa Background FASE vas 7 2 VMEbus Description _ ss 7 je C nfig rations c SASi
126. rocessing to occur The current state of the machine is saved Information from the saved state of the machine can be used to determine the cause of the bus error This is handled by the bus error exception routine as part of an operating system If the first port of the dual port DRAM controller is not active and a refresh cycle is not taking place a global bus master can have access to the DRAM The master circuit board s CPU is unaware of the access to the DRAM through the second port Consequently the burden is placed upon a global master or a VMEbus watchdog timer to provide a global BERR signal GBERR on the VMEbus BERR line when appropriate to the VMEbus controller The GBERR signal is sent to the BERR circuitry Fig E 19 via the BERR172 signal 1 VMEbus Controller The VMEbus controller circuitry Fig E 20 provides the necessary logic for the master circuit board subsystem to gain access to the VMEbus The SCB68172 VMEbus controller provides contrel signals VMEEN DATAEN and DDEN to the master circuit board subsystem s drivers and transceivers purpose of the VMEbus enable VMEEN signal is to enable the bus drivers only when there is an off board OFFBOARD access In addition the data flow DATAEN and its direction DDEN are controlled Parallel jacks are provided which permit jumper selection of the master circuit board subsystem s priority on the VMEbus 55 m VMEbus Address Decoding The VMEbu
127. s In this parallel arbitration scheme the subsystems desiring use of the bus make bus requests BRx through the bus arbiter The bus arbiter or other controlling device then sends out a bus grant BGx onto the bus to the highest priority subsystem with a pending bus request BUS ARBITER SUBSYSTEM2 SUBSYSTEM1 SUBSYSTEMO Figure 2 5 Parallel Arbitration The main advantage of the daisy chain arbitration scheme over the parallel arbitration scheme is that subsystems can be inserted sequentially one after the other Consequently new subsystems are easily added to the system The main advantage of the parallel arbitration scheme over the daisy chain arbitration scheme is that arbitration can be performed faster Parallel arbitration does not propagate a bus grant signal down a chain but rather the bus grant signal is sent 16 directly to the highest priority subsystem requesting service However the parallel arbitration scheme limits the number of subsystems that the bus arbiter can accommodate Any fixed priority arbitration cannot ensure that the subsystem with the lowest priority level will be serviced if higher priority subsystems make frequent requests The daisy chain arbitration and parallel arbitration methods may need to be modified or a controller may need to be incorporated to ensure each subsystem can be serviced fairly The VMEbus uses serial parallel combination for bus arbitration with only one bus
128. s address decode circuitry Fig E 21 permits access of a global bus master to the second port of the dual port DRAM controller and ultimately into DRAM Any subsystem which has gained control of the VMEbus has the ability to access the designated by the operating system area of DRAM for semaphore passing The VMEbus address decoder provides the chip select Signal CS764REQ2 to the dual port DRAM controller Fig E 9 If the CS764REQ2 is asserted when clock edge falls and SEL1 signal of the 74F764 is not asserted the isolation drivers are enabled to permit the flow of data and addresses from the global resource to the DRAM n VMEbus Drivers The circuitry for the master circuit board s VMEbus drivers Figs E 22 E 23 and E 24 provides control of signals from the local bus to the VMEbus and from the VMEbus to the local bus The VMEbus controller controls the direction of the signal flow as requested by the CPU Whenever the local bus master the CPU is not in control of the VMEbus all signals from the local bus are isolated at the drivers by the VMEbus controller Thus in this case no signals are gated onto the VMEbus from the local bus However another subsystem if in control of the VMEbus has direct access to the DRAM through the dual port DRAM controller The global addresses on the VMEbus fall into the range of the one megabyte of user DRAM in the master circuit board subsystem s memory map Table II 56
129. s data transfers are flexible and do not impose timing control signals Completion signals from the asynchronous devices ensure that adequate time is allowed for the data transfer In contrast synchronous data transfers impose a timing constraint 7 on the data transfer which must accommodate the slowest device attached to the bus non multiplexed bus is one that accommodates data transfers and address transfers as separate signals on separate lines of the bus This contrasts with the multiplexing strategy where data signals and address signals share the same set of lines As a simple description during a write cycle multiplexing address Signals are gated on one clock cycle and data signals are gated on the same lines during a subsequent clock cycle The non multiplexing strategy speeds up data transfer by eliminating the second clock cycle The VMEbus can be used with 24 or 32 address lines depending on the microprocessor s requirements and it is easily adaptable to the entire family of Motorola 68xxx microprocessors and peripherals The VMEbus is composed of four sub buses that play unique roles within the overall VMEbus functional structure These include the data transfer bus DTB the data transfer arbitration bus the priority interrupt bus and the utility bus The VMEbus functional specification describes how each sub bus interacts and the rules which govern the behavior of each sub bus Ref 4 pp 15 194 The DTB provides th
130. ssed later are open collector signals Hence pull up resistors are used to ensure that these signals are not inappropriately asserted b Halt and Reset Generation The HALT and RESET generation circuitry Fig E 4 provides manual and automatic power on subsystem reset to the CPU and peripheral devices The NE555 timer provides an automatic power on reset to the subsystem The NE555 timer is configured as a one shot to generate the power on reset signal This automatic reset occurs within the first few tenths of a second after the subsystem is powered on An external system reset can also reset the subsystem This system reset is generated from the system controller subsystem via the VMEbus A debounced switch is used to cause a manual reset of the subsystem A reset causes the CPU to read into the SP register and PC register the longword 32 bits contents of physical addresses 000000 and 000004 respectively Recall that ROM begins at physical address 000000 Consequently the two longwords beginning at physical address 000000 are retrieved from non volatile memory The initial PC vector at physical address 000004 contains the 45 value 002000 so when this value is read into the PC execution of the monitor debugger program is started Clock Generation The clock generation circuitry Fig E 5 provides clocking signals to the CPU and to the peripheral devices A 74LS161 binary counter is used to divide the 16 MHz signal fr
131. subsystem If the bus is in use and a higher priority bus request is asserted the bus arbiter asserts the bus clear line The bus clear signal informs the current bus master that another subsystem with a higher priority is requesting bus ownership Each potential bus master should accommodate either a release when done or a release on request strategy to resolve pending higher priority requests for bus access c Master Slave Application A master slave configuration combines the master only and slave only capabilities into a single subsystem As illustrateu in Figure 2 3 the CPU residing on the master slave subsystem has the ability to gain control of the VMEbus The system controller and bus arbiter perform the same roles as described in the master only subsystem 12 Shared slave devices are onboard the master slave subsystem These devices can be accessed by another subsystem when it has control of the VMEbus Fig 2 3 The bus controller isolates the shared slave devices from the CPU by putting the 74LS244s outputs into a high impedance state whenever another subsystem accesses the shared slave devices When this happens the shared slave devices become a global asset to the system The 74LS245s not only act as line drivers and receivers SYSTEM CONTROLLER MASTER SLAVE SUBSYSTEM LOCAL DEVICES 74LS244s SHARED SLAVE DEVICES L 74LS245s VMEbus BUS ARBITER BUS CONTROLLER 74152445
132. system in the daisy chain If SUBSYSTEM is requesting the bus it asserts the bus busy BBSY signal and it continues to negate its bus grant output BGOUT signal SUBSYSTEM1 can now begin data transfer If the bus request was 14 made by any subsystem other than SUBSYSTEM1 the BG signal is passed by SUBSYSTEM to the next subsystem the chain SUBSYSTEM2 BGOUT signal from SUBSYSTEM1 becomes the BGIN signal to the next subsystem in the chain SUBSYSTEM2 This process is repeated until the highest priority requesting subsystem receives the BGIN signal SUBSYSTEM1 has a higher priority than SUBSYSTEM2 The last subsystem in the chain SUBSYSTEMn has the lowest priority BUS ARBITER SUBSYSTEMn SUBSYSTEM1 SUBSYSTEM2 BGOUT Figure 2 4 Daisy Chain Arbitration The BR and BBSY signals are wire ORed open collector active low i e the logic is tied together at a wire connection Consequently the BR signal will cause the BBSY signal to be asserted once the BGIN signal is received through the daisy chain Parallel arbitration is a method of arbitrating a shared communication bus by priority levels An example of a three level parallel arbitration scheme is shown in Figure 2 5 In Figure 2 5 15 bus request zero BRO has the lowest priority level while bus request two BR2 has the highest priority level The highest priority subsystem with a pending request is granted access to the bu
133. the monitor debugger software developed the minimal system design was complete The monitor dekugger and vector table were programmed in the erasable programmable read only memory EPROM with the Data 1 0 System 29 Universal Programmer Data I O System 29 segregated the even bytes and odd bytes into separate EPROMs as required by the Motorola MC68010 central processor unit CPU Erasable programmable logic devices EPLDs were used to reduce the chip count in the minimal system design The minimal system used EPLD to perform the interrupt request 0681 and the interrupt acknowledge IACK681 logic Also EPLDs were used to implement the circuit logic required for the generation of the data transfer acknowledge DTACK and the bus error BERR signals and for address decoding In order to program the EPLDs Abel software was used to compile the source code representation of the logic to be implemented with the EPLD Once all of the source code for the EPLDs had been written compiled and software tested the EPLDs were programmed On the Data I O System 29 once the EPLD is programmed the test vectors are again tested against the programmed EPLD During this test run the System 29 failed for every EPLD that was programmed even though they passed the software tests On the advice of an applications engineer at Data 1 0 Corporation the test vectors were removed from the source code This code was
134. tion Aid the operating system in managing the virtual memory system efficiently by use of the segment status registers 6 Dual port DRAM Controller The Signetics 74F765 dual port DRAM controller provides access to the DRAM by either a local bus master or a global bus master If DRAM is accessed by the local bus master i e the CPU on the master circuit board subsystem it becomes a local asset It is not desirable for the local CPU to access DRAM via the VMEbus because long access times would be the result If DRAM is accessed by a global bus master i e another subsystem controlling the VMEbus it becomes a global asset The ability to access DRAM locally or globally is desirable for a system that includes 28 subsystems that interact closely with one another In addition the dual port DRAM controller provides refresh cycles to the dynamic memory integrated circuit chips The global memory accesses in this master circuit board subsystem design use physical addresses to permit the implementation of mailboxes with attached semaphores as discussed in Chapter I An operating system needs to lock the mailbox page in physical memory at a specified physical address 7 VMEbus Controller The Signetics SCB68172 VMEbus controller preserves the VMEbus data transfer and VMEbus access protocols The VMEbus controller and the MC68010 CPU are configured in a master only role as illustrated in Figure 2 2 and discussed in Chapter II Th
135. to control bus accesses SYSTEM CONTROLLER MASTER SUBSYSTEM LOCAL DEVICES BUS BUS ARBITER CONTROLLER 74152445 741 52455 VMEbus Figure 2 2 Master Only Subsystem Given a request by the CPU the bus controller generates a bus request signal through 7415245 to the system controller s bus arbiter The abilities of the 7415245 were described in the slave only subsystem The bus arbiter receives requests from subsystems on the VMEbus through the 74LS244 octal buffers and line drivers with 3 state outputs The function of the bus arbiter is to resolve prioritized requests from the subsystems and to generate bus grant signal through the 7415244 to the 11 highest priority requesting subsystem The subsystem s bus controller maintains system integrity by ensuring that a bus grant Signal is received prior to permitting a data transfer The requesting subsystem after receiving the bus grant signal negates its bus request and asserts the bus busy signal so that other subsystems cannot gain control of the bus while the data exchange is in process Also the bus busy signal informs the bus arbiter that a data exchange is currently in progress and that the bus arbiter can release the bus grant signal The requesting device is now the bus master When the data exchange is complete the requesting device releases the bus busy signal to allow the bus arbiter the opportunity to grant the bus to another
136. ubsystem is a device which other subsystems utilize Examples of slave subsystems include communication ports and stand alone memory boards If intelligence logic is added the subsystem can evolve into an input output I O channel or a mass storage subsystem Figure 2 1 shows the simplicity of a slave subsystem interfaced to the VMEbus The 74152455 octal bus transc vers with 3 state outputs provide the drive capability for transmitting signals onto the VMEbus and the receiver capability for receiving signals from the VMEbus If desired the 74LS245s can also be disabled to isolate the slave subsystem from the VMEbus SLAVE SUBSYSTEM SLAVE DEVICE S 74LS245s VMEbus Figure 2 1 Slave Only Subsystem Master Only Application In the master only configuration the subsystem has the ability to gain control of the VMEbus A master only subsystem has an onboard central processor unit CPU with or without local slave devices It is interfaced to the VMEbus with a bus controller When the subsystem has gained control of the VMEbus this subsystem is said to be in a master role Figure 2 2 gives a simplified illustration of a VMEbus system with a master only subsystem 10 attached to it Comparison of Figures 2 1 and 2 2 shows the added complexity required in a subsystem which can gain control of the VMEbus In addition a system controller is included in Figure 2 2 to illustrate the added system complexity required
137. valid and stable f Dual port DRAM Controller The dual port DRAM controller circuitry Figs E 9 E 10 and E 11 provides two paths into RAM Ref 17 The local bus master the CPU can be ported to the RAM or a global bus master can be ported to the RAM via the VMEbus Two paths into RAM are especially useful because processor subsystems can pass information carrying semaphores Also The 74F764 dual port DRAM controller provides DRAM refresh The 3 state capability of the 74152445 Fig E 9 octal buffers and line drivers with 3 state outputs are used to isolate one port access to the dual port DRAM controller from the other port The port is selected by the appropriate clock edge and control signal to the request input REO1 or REQ2 of the 74 764 dual port DRAM controller The control signal for RE01 of the 74F764 CS764REQ1 is generated by the local bus address decoder and the control signal for REQ2 of the 74F764 CS764REQ2 is generated by the VMEbus address decoder If CS764REQ1 is active on a rising clock edge and SEL2 is not asserted the local master is granted access to the 74F764 The dual port DRAM controller then asserts SEL1 to enable the 74LS244s and 74LS245s on the local bus side CS764REQ2 is active on falling clock edge and SEL1 is not asserted the global bus master is granted access into the 74F764 The dual port DRAM controller then asserts SEL2 to enable the 74152445 and 74152455 for t
138. with the system assets or gaining supervisor privileges Dual ported memory permits two separate sources to access the same memory block and provides the refresh signals for the dynamic random access memory DRAM Dual ported memory permits RAM to be used as a shared asset It is especially useful when a portion of the physical RAM is dedicated to passing parameters between microprocessor subsystems Dedicating a portion of RAM for parameters is analogous to a mailbox delivery system The mail courier subsystem 1 delivers mail parameters to the mailbox RAM The addressee subsystem 2 picks up the mail parameters and responds as required If appropriate the occupant subsystem 2 places mail parameters in the mailbox 63 RAM to be delivered to subsystem 1 These parameters can be used in managing a multi processor operating system A MC68010 based system typically has memory mapped I 0 devices RAM and ROM DRAM is added the master circuit board subsystem to supplement the minimal system s static random access memory SRAM The MC68010 CPU has a virtual address range of 16 megabytes However the physical RAM s size 15 usually considerably less than the size of the virtual address space Virtual memory is used to extend the range of programming beyond the range of physical RAM An MMU is used to map virtual addresses into RAM physical addresses Also the MMU detects an attempt by the CPU to access a virtual memory add
139. x xxx xx KKK KKK X XX XXX DEFINING MODULES OF EXTERNALLY DECLARED VARIABLES BUFFIN MAIN ASM END_ADDRESS MAIN ASM HEX CONV HEXCONV ASM ERR MAIN ASM MONSTAT MAIN ASM 5 MESSAGE ASM MESSAGE MESSAGE ASM X X MX X ke XK x XX XK XK XX X X XX X X xx XX X X X X XX XX XX X X X X X X XX X X kk xk GLOBAL GET ADDR EXTERNAL BUFFIN END ADDRESS HEX HEX ERR EXTERNAL MONSTAT HEXMSG MESSAGE GET_ADDR CLR L D2 CLEAR HEX BUFFER LEA 0 A2 CLEAR START ADDRESS LEA 0 CLEAR END ADDRESS CLR D3 MOVE B BUFFIN D3 D3 lt BUFFIN LENGTH BLE EXIT EXIT IF NULL CMD STRING SUBQ W 1 D3 ADJUST FOR DBCC INST START ADDR MOVE B A0 D0 20 lt BUFFIN I amp I lt 1 4 DO IS CHAR IN DO A COMMA BEQ STORE START YES INDICATE END OF START ADDRESS BSR HEX CONV CONVERT 1 CHAR OF START ADDR TO BTST B HEX_ERR MONSTAT WAS THERE AN HEX CONVERSION ERROR 2 BNE ADDR_ERR YES EXIT ROUTINE DBF D3 START_ADDR IF MORE CHARACTERS CONT STORE_START SUBQ W 1 D3 ADJUST LENGTH FOR COMMA MOVE L D2 A2 STORE START ADDRESS IN A2 CLR L D2 CLEAR HEX BUFFER D3 CONTAINS THE LENGTH OF THE REMAINING COMMAND LINE TST W D3 IS BUFFIN LENGTH lt 0 BMI ADDREXIT YES EXIT WITH END ADDR 0 94 END_ADDR ADDREXIT ADDR ERR EXIT MOVE B BSR BTST B BNE DBF MOVE L MOVE L BRA LEA BSR RTS
140. x xxx xxx xxx xx xxx xxx xx xx xxx xx xxx xxx xx xxx GLOBAL BACKSPACES SCROLL SCRLF SPACES EXTERNAL BS CR ECHO1 ESC FWDARW GETCHAR1 LF EXTERNAL RECFULL SPACE EXTERNAL SRA PORT1 BACKSPACES MOVES THE CURSOR ON THE CRT TO THE LEFT TIMES BACKSPACES SUBQ W 1 D2 ADJ INDEX FOR THE OF BK_SP BK SPACE MOVE B 85 00 DO lt ASCII CODE FOR BACKSPACE BSR ECHO1 OUTPUT BACKSPACE TO CONSOLE DBF D2 BK_SPACE IF MORE BCKSP LOOP TO BK_SPACE RTS SCRLF SEND A CARRIAGE RETURN AND LINEFEED TO THE CONSOLE SCRLF MOVE B CR DO DO ASCII CODE FOR CR BSR ECHO1 OUTPUT CR TO CONSOLE MOVE B LF DO DO lt ASCII CODE FOR LF BSR ECHO1 OUTPUT LF TO CONSOLE RTS 96 i SPACES MOVE THE CURSOR ON THE CRT TO THE RIGHT N TIMES SPACES SUBQ W 1 D2 ADJUST INDEX FOR THE OF SP SPACE LOOP MOVE B 5 0 ASCII CODE FOR BSR ECHO1 OUTPUT SPACE TO CONSOLE DBF D2 SPACE_LOOP IF MORE SPACES LOOP TO SPACE RTS SCROLL ALLOWS THE SCREEN SCROLL TO BE ABORTED BY AN ESC OR STOPPED AND STARTED BY ANY OTHER KEY SCROLL LEA PORT1 A4 BTST B RECFULL SRA A4 GET CONSOLE STATUS BEQ S SCROLL EXIT IF NO CHAR FROM 5 CONSOLE EXIT BSR GETCHAR1 ELSE GET CHAR L5C 00 IS THE CHAR AN ESC 5 5060LL YES ABORT PAUSE CHK LEA PORT1 A4 BTST B RECFULL SRA A4 GET CONSOLE STATUS BEQ S PAUSE IF NO NEW KEY STROKE WAIT BSR 1 ELSE GET CHAR SCROLL_EXIT RTS END 97 Kk X K k k k k
141. ze the address range of a microprocessor is to divide its address space into two or more blocks Each block of the address space can be designated for a specific purpose such as supervisor memory or user memory The MC68010 microprocessor has two modes of operation These modes are the user mode and the supervisor mode The user mode provides an instruction set for the programmer to accommodate a majority of applications The supervisor mode provides additional instructions and privileges for use by the operating system and other system related software Ref 7 p 1 1 The user memory is the area designated for non privileged individuals to use Such an individual executes programs in the user mode The address range for the user is normally limited because it does not include the addresses associated with the operating system and the memory mapped peripherals Additionally the user is restricted from executing privileged supervisor instructions In contrast the operating system executes programs 18 in supervisor mode and can address supervisory memory and memory mapped peripherals as well as user memory This segregation of the supervisor and the user precludes the user from reconfiguring the system but still allows the user access to part of the physical memory and to the computational power of the microprocessor Typically the user must request the operating system to perform operations which the user is not allowed to perform 2

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