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Arria V GT FPGA Development Board Reference Manual

1. Chapter 1 Overview 1 5 Development Board Block Diagram m General user I O m LEDs and displays m Eight dual color user LEDs Two HSMC interface transmit receive TX RX LEDs m Pushbuttons m OneCDU reset push button m Three general user push buttons m Eight user control DIP switches Figure 1 1 shows a block diagram of the Arria V GT FPGA development board Figure 1 1 Arria V GT FPGA Development Board Block Diagram Cie 6 Port A 2x16 LCD Port B On Board Min USB 2 2 2 USB Interface g 3 5 4 S 8 i d 3 x o JTAG Chain x72 1152 USB Interface x19 3 SDI 32 Hard IP DDR3 x36 72 Mb _ Soft 06 3 gt ERE Bul Eye p QDRI Chip to Chip FH o LVDS x29 Chip to Chip 1 Clock Input 4 Suis XCVR x1 Arria V p LVDS x29 Chip to Chip 1 Clock Input Arria V 106 4 BursEe XCVRxI Fa Push buttons 10G DIP Switches Gigabit Ethernet 746 BAGTFD7K3F40 x XCVR 1 5AGTFD7K3F40 PHY RGMII Bulls Eye SS XCVR x2 FPGA 1 t XCVR 1 L Y gt 8 bi color LEDs SFP lt L 8 bi color LEDs E E e E 8 I bl PCI MAX Programmable Ostilators i EXPRESS TI 1 Gb Ostilators FMC 50 M 100 M x8 Edge CPLD Flash 50M 100 M
2. J4 Schematic Signal Name 1 0 Standard Description B20 PCIE N1 AT38 1 4 V PCML Receive bus B24 PCIE RX N2 AP38 1 4 V PCML Receive bus B28 PCIE RX AM38 1 4 V PCML Receive bus B34 PCIE RX AH38 1 4 V PCML Receive bus B38 PCIE RX 5 AF38 1 4 V PCML Receive bus B42 PCIE RX 6 AD38 1 4 V PCML Receive bus B46 PCIE RX N7 4838 1 4 V PCML Receive bus B14 PCIE RX AW37 1 4 V PCML Receive bus 819 PCIE RX P1 AT39 1 4 V PCML Receive bus B23 PCIE RX P2 AP39 1 4 V PCML Receive bus B27 PCIE RX P3 AM39 1 4 V PCML Receive bus B33 4 AH39 1 4 V PCML Receive bus B37 PCIE RX P5 AF39 1 4 V PCML Receive bus B41 PCIE RX P6 AD39 1 4 V PCML Receive bus B45 PCIE RX P7 4839 1 4 V PCML Receive bus B5 PCIE SMBCLK AV18 1 4 V PCML SMB clock B6 PCIE SMBDAT 16 1 4 V PCML SMB data 17 PCIE TX CNO AU36 1 4 V PCML Transmit bus A22 PCIE TX CN1 AR36 1 4 V PCML Transmit bus A26 PCIE TX CN2 AN36 1 4 V PCML Transmit bus A30 PCIE TX CN3 AL36 1 4 V PCML Transmit bus A36 PCIE 6114 AG36 1 4 V PCML Transmit bus A40 PCIE TX CN5 AE36 1 4 V PCML Transmit bus 44 CN6 AC36 1 4 V PCML Transmit bus A48 PCIE TX CN7 AA36 1 4 V PCML Transmit bus A16 PCIE TX CPO AU37 1 4 V PCML Transmit bus 21 PCIE TX 1 AR37 1 4 V PCML Transmit bus A25 PCIE TX CP2 AN37 1 4 V PCML Transmit bus A29 PCIE TX C
3. 1 2 Dual Em 1 3 FREGAT EE Go eRe CM NE 1 3 PPGA2 1 4 Development Board Block Diagram 1 5 Handling the Board oui eed ka f ie a et rp sex vate ba ie V eroe Va qa nd 1 5 Chapter 2 Board Components rto MC Em 2 1 Board Overview aet ae eee tee eure ee ad ue ard are D dee eiue 2 2 Featured Device Arria V GI FPGA eee bn sa 2 6 T O Resources e ced etc d ten e E Ee dee 2 6 MAX II CPLD EPM2210 System Controller 2 8 Configuration Status and Setup 2 14 Configuration ER 2 14 FPGA Programming over On Board USB Blaster 2 14 FPGA Programming from Flash Memory 1 2 16 FPGA Programming over External USB Blaster 2 18 Status Blements esas angela e buna cole 2 18 Sel p Elements e do n de e Has eed He He hua ede dete een 2 20 Board Settings Switch 5 ecer nenne ere 2 20 JT AG Settin
4. 2 33 PCI 2454 ee xe Paderb Pee Eo de ove a tele 2 33 10 00 1000 Ethernet Je teet eese Ep opted eren hog ne Pepe E c e eges 2 36 rt eese Ee ne 2 37 Modules ote et lah ay E a dts 2 45 FMCG Connector s aed ie etae be re d hne hu bea deiode te ie e Pedes 2 46 Bull s Bye ConnectoE e an pe kid ke ue Ree pr pee e don ete aed lect de 2 52 25550590 aote eed Ee doo do equ 2 54 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual iv ContentsContents DDR9 2 54 DDRSATOFIPDGA Lu pue saya 2 54 DDKSB C f r FPGA 2 swe kon Mak iet kad XE ER oe bebe Eb 2 59 ODRU ioc baa saa aaa sa LU UM 2 64 PIAS c Rb aap 2 67 Power teni ti at bet stint 2 68 Power Distribution System coss Ha e a ee ach vy a Pa n rex 2 69 Power Measurement oen re PI ee CD cerae p een 2 70 Statement of China RoHS Compliance 2 72 Chapter 3 Board Components Reference Additio
5. Board Reference 2 1 0 Standard Description L7 DDR3B A10 032 1 5 V SSTL Class Address bus R7 DDR3B_A11 D32 1 5 V SSTL Class Address bus N7 DDR3B A12 N31 1 5 V SSTL Class Address bus T3 DDR3B A13 P31 1 5 V SSTL Class Address bus M2 DDR3B 0 M32 1 5 V SSTL Class Bank address bus N8 DDR3B N32 1 5 V SSTL Class Bank address bus M3 DDR3B_BA2 J34 1 5 V SSTL Class Bank address bus K3 DDR3B CASN L33 1 5 V SSTL Class Row address select K9 DDR3B CKE E31 1 5 V SSTL Class Column address select K7 DDR3B CLK N C30 1 5 V SSTL Class Differential output clock J7 DDR3B CLK P B30 1 5 V SSTL Class Differential output clock L2 DDR3B CSN L34 1 5 V SSTL Class Chip select Ki DDR3B ODT L31 1 5 V SSTL Class On die termination enable J3 DDR3B RASN K34 1 5 V SSTL Class Row address select T2 DDR3B RESETN G30 1 5 V SSTL Class Reset L3 DDR3B_WEN M33 1 5 V SSTL Class Write enable DDR3C 019 E7 DDR3C M21 1 5 V SSTL Class Write mask byte lane D3 DDR3C_DM1 B22 1 5 V SSTL Class Write mask byte lane E3 DDR3C_DQO D20 1 5 V SSTL Class Data bus byte lane F7 DDR3C_DQ1 H21 1 5 V SSTL Class Data bus byte lane F2 DDR3C DQ2 021 1 5 V SSTL Class Data bus byte lane F8 DDR3C DQ3 J21 1 5 V SSTL Class Data bus byte lane H3 DDR3C DQ4 A21 1 5 V SSTL Class Data bus byte lane H8 DDR3C DQ5 G21 1 5 V SSTL Class Data bus byte lane G2 DDR3C DQ6
6. Handling the Board When handling the board it is important to observe the following static discharge precaution CAUTION anti static handling precautions when touching the board December 2014 Altera Corporation Without proper anti static handling the board can be damaged Therefore use Arria V GT FPGA Development Board Reference Manual 1 6 Chapter 1 Overview Handling the Board Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual YAN 2 Board Components Introduction This chapter introduces the major components on the Arria V GT FPGA development board Figure 2 1 illustrates the component locations and Table 2 1 provides a brief description of all component features of the board a complete set of schematics a physical layout database and GERBER files for the development board reside in the Arria V GT FPGA development kit documents directory For information about powering up the board and installing the demonstration software refer to the Arria V GT FPGA Development Kit User Guide This chapter consists of the following sections Board Overview Featured Device Arria V GT FPGA on page 2 6 MAX II CPLD EPM2210 System Controller on page 2 8 Configuration Status and Setup Elements on page 2 14 Clock Circuitry on page 2 22 General User Input Output on page 2 27 Components and Interfaces on page 2 33 Memory
7. RYAN 101 Innovation Drive San Jose CA 95134 www altera com MNL 01074 1 2 Arria V GT FPGA Development Board Reference Manual A Feedback Subscribe 2014 Altera Corporation rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual AHERN Contents Chapter 1 Overview General Description uyu ex teg boo dee deb gt 1 1 Board Component
8. 2 B QR2 P N 4 41 8 Tou 100 MHz 125 MHz ai a o E o Arria V GT FPGA Development Board Reference Manual 2 24 Chapter 2 Board Components Clock Circuitry Table 2 11 lists the oscillators its I O standard and voltages required for the development board Table 2 11 On Board Oscillators Arria V GT Source ano Signal Frequency 1 0 Standard FPGA Pin Application ame N umber CLKIN MAX 50 1 8 V X6 to U51 1 3 clock buffer CLKINA 50 50 000 MHz 1 8 V AF21 Nios and MAX II CPLD CLKINB 50 1 8 V AP34 X3 CLK CONFIG 100 000 MHz 2 5 V CMOS Fast FPGA configuration REFCLK1 A QLO P 1 PCI Express host dual XTL REFCLK1_A_QL0_N AE32 CLKINBOTA AD20 Bottom edge FPGA 1 QDRII CLKINBOTA NO 21 6 CLKINTOPA LVDS C20 100 000 MHz Top edge FPGA 1 0083 clock buffer CLKINTOPA fanout buffer D20 CLKINBOTB AK7 gt Bottom edge FPGA 2 CLKINBOTB NO AJ7 CLKINTOPB C34 FPGA 2 DDR3 CLKINTOPB NO D34 CLKA 125 P LVDS Fixed clock at 125 MHz for X1 125 000 MHz CLKA 125 N LVDS AN34 FPGA 1 bank CLKB 125 P LVDS AD20 Fixed clock at 125 MHz for X4 125 000 MHz CLKB 125 N LVDS
9. Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Power Supply Table 2 36 Power Measurement Rails Part 2 of 3 2 71 Switch Schematic Signal Name GUI Name Voltage Device Pin Description 2 5V VCCPD pre drivers 2 5V VCCPGM Configuration 1 0 VCCIO_4A VCCIO_4B 3 PGM 10 2 5V VCCPD PGM VCCIO 4C VCCIO 4D 25V VCCIO VCC 1 0 banks 4 and 7 VCCIO 7B VCCIO 7C VCCIO 7D 4 1 15V VCC VCCP FPGA core and periphery power VCCIO 8A 5 VCCIO 1 5V VCCIO 1 5V 15V YCCIO8B 0010 bank 8 DDR3A _ a d VCCIO 8C VCCIO 8D 15V VCCD PLL digital power 6 VCCD PLL 1 5V A5A VCCD PLL i 2 FLL _ S 15V XCVR block level transmit buffers VCCIO VCCIO 3B 7 A5A VCCIO 1 8V VCCIO 1 8V 1 8 V VCCIO 3C VCC bank QDRII VCCIO 3D VCCR_GXB XCVR analog receive and clock 8 A5B_VCCR_VCCL_GXB XCVR GXB 1 2V VCCL GXB network A5B_VCCT_GXB 1 2 V VCCT_GXB XCVR transmitter power 25V VCCA FPLL PLL analog power 9 VCCA 2 5V 25V AUX Auxiliary 25V VCCPD 1 0 pre drivers 25V VCCPGM Configuration 1 0 VCCIO 10 VCCPD PGM 10 2 5V VCCPD PGM VCCIO 3B VCCIO 25V VCCIO 7B VCC 1 0 banks 3B and 7 VCCI0_7C VCCIO 7D 11
10. Package Type 1517 pin FBGA 1 0 Resources Figure 2 2 illustrates the bank organization and I O count for the Arria V GT FPGA SAGTFEDZK3F40I3N device in the 1517 pin FBGA package Figure 2 2 Arria V GT FPGA Device 1 0 Bank Diagrams AWI Ai 25V 48 Bank4A C2C HSMA SMA HSMA SMA Bank7A 48 25V x8 x4 66 x8 100 HSMA SFP 48 Bank4B GXB R Bank7B 48 ip to Chi XCVBs Chip to Chip USER LCD 32 Bank4C Bank7C 32 USER ENET PCle 25V 48 Bank4D Bank7D 48 SFP B5AGTFD7K3F40I3N 18V Bank3D Device 1 Bank 8D 48 15V 48 Bank3C 8 48 DDR3 x72 Flash MAX GXB L USB 32 Bank3B XCVRs Bank8B 32 PCle SMA SMA SFP 48 Bankoa d xi 06 SEPH Banksa 48 SMA BP BP C2C 25V 15V Banksa Goa 1 BE 20 Bank3A 48 HSMB L 32 Bank8B Bank3B 32 D DDR3 x72 USER 48 Bank 8C Bank3C 48 48 Bank8D Bank3D 48 25V 7 4 25V 48 Bank7D Device 2 Bank4D 48 FMC Chip to Chip 92 Bank 70 Bank 46 32 LCD GXB_R 48 Bank 78 XCVRs Bank4B 48 SMA SMA SDI HSMB P Bank 7A x6 x4 6G 10G 1 4 Bank 4 48 Arria V FPGA Development Board Reference Manual December 2014 Altera Corporation C
11. Table 2 6 PGM1 LED Settings PGM1 LEDO PGM1 LED1 PGM1 LED2 Design ON OFF OFF Factory hardware OFF ON OFF User design 1 OFF OFF ON User design 2 FPGA Programming over External USB Blaster The JTAG programming header provides another method for configuring the using an external USB Blaster device with the Quartus II Programmer running on a PC The external USB Blaster connects to the board through the JTAG connector J5 Both FPGAs and the MAX II devices are always in the JTAG chain Ta For more information on the following topics refer to the respective documents m Board Update Portal and PFL design refer to the Arria V GI FPGA Development Kit User Guide m PFL megafunction refer to Parallel Flash Loader Megafunction User Guide Status Elements The development board includes status LEDs This section describes the status elements Table 2 7 lists the LED board references names and functional descriptions Table 2 7 Board Specific LEDs Part 1 of 2 Board Schematic Signal Arria V GT FPGA 1 0 Reference Name Pin Number Standard Description D1 Power 5 0 Blue LED Illuminates when 5 0 V power is active Green LED when the MAX II CPLD D16 CONF 25 2210 System Controller is successfully configured Driven by the MAX II CPLD EPM2210 System Controller Green LED when the MAX II CPLD 2210 System Con
12. Address bus N2 DDR3A A3 P28 1 5 V SSTL Class Address bus P8 DDR3A A4 L24 1 5 V SSTL Class Address bus P2 DDR3A A5 632 1 5 V SSTL Class Address bus R8 DDR3A A6 R21 1 5 V SSTL Class Address bus R2 DDR3A A7 K30 1 5 V SSTL Class Address bus T8 DDR3A_A8 D21 1 5 V SSTL Class Address bus R3 DDR3A_A9 M30 1 5 V SSTL Class Address bus L7 DDR3A A10 J28 1 5 V SSTL Class Address bus R7 DDR3A A11 M21 1 5 V SSTL Class Address bus N7 DDR3A A12 G28 1 5 V SSTL Class Address bus T3 DDR3A A13 M31 1 5 V SSTL Class Address bus M2 DDR3A_BAO G30 1 5 V SSTL Class Bank address bus N8 DDR3A_BA1 T24 1 5 V SSTL Class Bank address bus M3 DDR3A_BA2 K34 1 5 V SSTL Class Bank address bus K3 DDR3A CASN D32 1 5 V SSTL Class Row address select K9 DDR3A CKE K29 1 5 V SSTL Class Column address select K7 DDR3A CLK N F34 1 5 V SSTL Class I Differential output clock J7 DDR3A CLK P E34 1 5 V SSTL Class Differential output clock L2 DDR3A CSN F31 1 5 V SSTL Class Chip select Ki DDR3A ODT E33 1 5 V SSTL Class On die termination enable J3 DDR3A RASN A32 1 5 V SSTL Class Row address select T2 DDR3A RESETN J31 1 5 V SSTL Class Reset L3 DDR3A WEN G29 1 5 V SSTL Class Write enable DDR3A U7 K3 DDR3A A0 M34 1 5 V SSTL Class Address bus L7 DDR3A A1 H25 1 5 V SSTL Class Address bus L3 DDR3A A2 F32 1 5 V SSTL Class Address bus K2 DDR3A A3 P28 1 5 V SSTL Class Address bus L8 DDR3A A4 L24 1 5
13. 5 CLK sg DONE lt gt CONE DONE MSELO ENABLE a FACTORY V CONF DONE LED A Les FACTORY2 CONF DONE L PS Port FPGA DATA 7 0 gt DATA 7 0 1 FPGA_DCLK gt DCLK Flash Interface 25V gt RESETn 5620 FLASH_A 26 1 e J gt PGM1_CONFIG FLASH D 15 0 a i FLASH CEn FLASH_OEn PGM1_SEL FLASH_WEn FLASH_RYBSYn Pami LEDO FLASH CLK gt gt PGM1_LED1 FLASH_RSTn LED2 FLASH ADVn CFI Flash 18V FLASH A 26 0 lt 10 FLASH D 15 0 lt FLASH CEn lt FLASH OEn a FLASH WEn e FLASH RYBSYn lt FLASH FLASH RESETn L FLASH WPn FLASH ADVn lt b For information on flash memory map storage refer to the Arria V GT FPGA Development Kit User Guide There are two pages reserved for the FPGA configuration data The factory hardware page page 0 loads upon power up when Factory1 DIP switch SW5 3 is set to 1 Otherwise the user hardware page 1 loads Pressing the PGM1 CONFIG push button 53 loads the FPGA with a hardware page based on which PGM1 LED 2 0 LED D12 D13 D14 illuminates December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 18 Chapter 2 Board Components Configuration Status and Setup Elements Table 2 6 defines the hardware page that loads when you press the PGM1_CONFIG push button S3
14. RXD 3 0 Marvell 88E1111 POE e eme Interface Table 2 25 lists the Ethernet PHY interface pin assignments Table 2 25 Ethernet PHY Pin Assignments Signal Names and Functions Part 1 of 2 Board E des Schematic Signal Arria V GT FPGA Reference Name Pin Number 1 0 Standard Description U14 8 GTX CLK AN16 2 5 V CMOS RGMII transmit clock 23 ENET INTN AP16 2 5 V CMOS Management bus interrupt 60 ENET LED DUPLEX 2 5 V CMOS Duplex link LED 70 ENET LED DUPLEX 2 5 V CMOS Duplex link LED 76 ENET LED LINK10 2 5 V CMOS 10 Mb link LED 74 ENET LED LINK100 2 5 V CMOS 100 Mb link LED 73 ENET LED LINK1000 AN17 2 5 V CM0S 1000 Mb link LED 58 ENET LED RX 2 5 V CMOS RX data active LED 69 ENET LED RX 2 5 V CMOS RX data active LED 68 ENET LED TX 2 5 V CMOS TX data active LED 25 ENET MDC AJ18 2 5 V CMOS Management bus data clock 24 ENET MDIO AL17 2 5 V CMOS Management bus data 28 ENET RESETN AK17 2 5 V CMOS Device reset Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Components and Interfaces 2 31 Table 2 25 Ethernet PHY Pin Assignments Signal Names and Functions Part 2 of 2 Reference Schematic Signal Aria V GT FPGA jo standard Description U14 0
15. VCCINT VCCINT 1 15 V FPGA core and periphery power VCCIO 8A 12 5 1 5V A5B VCCIO 15V 15V 000 88 0010 bank 8 DDR3A m VCCIO 8C VCCIO 8D December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 12 Chapter 2 Board Components Statement of China RoHS Compliance Tahle 2 36 Power Measurement Rails Part 3 of 3 Switch Schematic Signal Name GUI Name Voltage Device Pin Description 15V VCCD_FPLL digital power 13 VCCD PLL 1 5V VCCD PLL i 5 PLL E 15V VCCH XCVR block level transmit buffers 15 V VCCIO_3C 18 V VCCIO 3D 14 5 VCCIO 5 VCCIO FMC VCCIO 4A 1 0 supply bank FMC port 2 5 V 33V VCCIO 4C VCCIO 4D of China RoHS Compliance Table 2 37 lists hazardous substances included with the kit Table 2 37 Table of Hazardous Substances Name and Concentration Notes 1 2 Hexavalent Polybrominated Lead Cadmium Mercury Polybrominated Part Pb Cd T biphenyls PBB E Arria V development board X 0 0 0 0 0 12 V power supply 0 0 0 0 0 0 Type A B USB cable 0 0 0 0 0 0 User guide 0 0 0 0 0 0 Notes to Table 2 37 1 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the SJ
16. m External USB Blaster for configuring the FPGA using an external USB Blaster that connects to the JTAG programming header J1 m Flash memory download for configuring the FPGA using stored images from the flash memory on either power up or pressing the program configuration push button PGM1 CONFIG S3 FPGA Programming over USB Blaster This configuration method implements a USB Type AB connector J7 a FTDI USB 2 0 PHY device U5 and an Altera MAX II CPLD U2 to allow the FPGA configuration using a USB cable that connects directly between the USB port on the board and a USB port of a PC running the Quartus II software The on board USB Blaster II in the MAX II CPLD EPM570GM100 normally masters the JTAG chain To prevent contention between the JTAG masters the on board USB Blaster II is automatically disabled when you connect an external USB Blaster to the JTAG chain through the JTAG connector If the USB Blaster II is detected but no hardware is found in the chain try reducing the clock frequency of the JTAG chain using these commands m Tocheck the current setting jtagconfig getparam cable no JtagClock m Tosetanew setting example clock frequency 16 M jtagconfig setparam cable no JtagClock 16M The USB Blaster II needs to be 16 M or slower in this case Only 6 M 16 M and 24 clock frequency options are available Insert a value of 1 for the lt cable no gt if this is the only JTAG cable
17. 21 FPGA 1 bank 3D REFCLKO QRO P LVDS 2 148 500 MHz HD SDI video 012 LVDS REFCLK4 A QL2 P LVDS W31 625 000 MHz SFP REFCLK4 012 LVDS W32 REFCLK3 A BUF P LVDS 156 250 MHz U53 REFCLK3 A BUF N LVDS SFP Bull s Eye connector REFCLK2 A QL1 P LVDS U31 1 2 clock to REFCLK3 on FPGA 1 125 000 MHz REFCLK2 A QL1 N LVDS U32 CLKINBOTA P1 LVDS AL20 125 000 MHz Bottom edge FPGA 1 memory CLKINBOTA N1 LVDS AK20 REFCLK4 A QR2 P LVDS T9 125 000 MHz REFCLK4 A QR2 N LVDS T8 HSMC port A 2 REFCLK2 A QR1 P LVDS AB9 lt 100 000 MHz U48 REFCLK2 QR1 N LVDS AB8 REFCLKO A QRO P LVDS AF8 625 000 MHz C2C REFCLKO A QRO N LVDS AF7 CLKINTOPA P1 LVDS A22 gt 125 000 MHz FPGA 1 memory CLKINTOPA 111 LVDS A21 Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Clock Circuitry Table 2 11 On Board Oscillators 2 25 Arria V GT Source dba Frequency 1 0 Standard FPGA Pin Application Number REFCLK4 B QL2 P LVDS U31 625 000 MHz C2C REFCLK4 B 012 N LVDS U32 REFCLK2 011 P LVDS AC31 100 000 MHz C2C U34 REFCLK2 B QLI N LVDS AC32 REFCLKO B QLO P LVDS AG32 625 000 MHz C2C REFCLK0 B QLO LVDS AG33 CLKINBOTB P1 LVDS AL20 125 000 2 Bottom edge FPGA 2 memory CLKINBOTB N
18. Reserved 9 SFP TX RS11 AE15 3 3 V LVTTL Reserved Module J15 6 SFP MOD ABS2 AT16 3 3 V LVTTL Module present indicator 8 SFP OP RX LOS2 AH17 3 3 V LVTTL Signal present indicator 2 SFP OP TX FLT2 AM18 3 3 V LVTTL Transmitter fault indicator 12 SFP RX N2 K38 3 3 V LVTTL Receiver data 13 SFP RX P2 K39 3 3 V LVTTL Receiver data 5 SFP SCL2 AD16 3 3 V LVTTL Serial 2 wire clock 4 SFP SDA2 AP15 3 3 V LVTTL Serial 2 wire data 3 SFP TX DIS2 AD15 3 3 V LVTTL Drive low to disable transmitter December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 46 Chapter 2 Board Components Components and Interfaces Table 2 28 SFP Modules Pin Assignments Schematic Signal Names and Functions Part 2 of 2 rie Signal Name _ Pin Number VO Standard Description 19 SFP TX N2 J36 3 3 V LVTTL Transmitter data 18 SFP_TX_P2 J37 3 3 V LVTTL Transmitter data 7 SFP TX RS02 AP14 3 3 V LVTTL Reserved 9 SFP 1512 7 3 3 V LVTTL Reserved FMC Connector The development board contains a high pin count HPC FPGA mezzanine card FMC connector that functions with a quadrature amplitude modulation OAM digital to analog converter DAC FMC module or daughter card This pinout satisfies a OAM DAC that requires 58 LVDS data output pairs one LVDS input clock pair and three low voltage differential signaling LVDS control pairs from the Arria V These pins also have the opt
19. Reset L3 DDR3B_WEN M33 1 5 V SSTL Class Write enable L8 DDR3B ZQ2 1 5 V SSTL Class 20 impedance calibration DDR3B U6 E7 DDR3B DMO J30 1 5 V SSTL Class Write mask byte lane D3 DDR3B DMI J29 1 5 V SSTL Class Write mask byte lane E3 DDR3B 100 B28 1 5 V SSTL Class Data bus byte lane F7 DDR3B 001 C29 1 5 V SSTL Class Data bus byte lane F2 DDR3B DQ2 R30 1 5 V SSTL Class Data bus byte lane F8 DDR3B DQ3 A29 1 5 V SSTL Class Data bus byte lane H3 DDR3B 104 A28 1 5 V SSTL Class Data bus byte lane H8 DDR3B 105 L30 1 5 V SSTL Class Data bus byte lane G2 DDR3B_DQ6 D30 1 5 V SSTL Class Data bus byte lane H7 DDR3B DQ7 D29 1 5 V SSTL Class Data bus byte lane 07 DDR3B_DQ8 L28 1 5 V SSTL Class Data bus byte lane C3 DDR3B DQ9 M28 1 5 V SSTL Class Data bus byte lane C8 DDR3B DQ10 H28 1 5 V SSTL Class Data bus byte lane C2 DDR3B_DQ11 C28 1 5 V SSTL Class Data bus byte lane DDR3B DQ12 D28 1 5 V SSTL Class Data bus byte lane A2 DDR3B DQ13 F28 1 5 V SSTL Class Data bus byte lane B8 DDR3B 0014 M29 1 5 V SSTL Class Data bus byte lane A3 DDR3B 0015 N29 1 5 V SSTL Class Data bus byte lane G3 DDR3B DQS NO P30 1 5 V SSTL Class Data strobe N byte lane B7 DDR3B 008 NI T29 1 5 V SSTL Class Data strobe N byte lane F3 DDR3B N30 1 5 V SSTL Class Data strobe P byte lane C7 DDR3B DQS PI R29 1 5 V SSTL Class Data strobe P byte lane DDR3B 012 E
20. on page 2 54 Power Supply on page 2 68 Statement of China RoHS Compliance on page 2 72 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 2 Chapter 2 Board Components Board Overview Board Overview This section provides an overview of the Arria V GT FPGA development board including an annotated board image and component descriptions Figure 2 1 shows an overview of the available components Figure 2 1 Overview of the Arria V GT FPGA Development Board Features User LEDs D18 D25 Configuration LEDs D12 D17 DDR3B U6 U12 FMC VCCPD B4 Select J5 User DIP Switch SW3 CPU Reset User Push Configuration User Push Buttons 59 511 Push HSMC User DIP Buttons Push Buttons CPU Reset HSMC User LEDs D26 D33 Flash Button S4 Port A J2 Switch SW2 85 87 51 93 Push Button S8 Port B J3 Board Power Switch SW1 ATX Power Connector MAX II CPLD gt 2210 System i AET Controller U2 pi m USD Bister Character Circuitry J7 LCD J29 Memory U4 JTAG Connector 1 Gigabit Ethernet Port J8 Connector Port 210 Port J15 Available in Arria V GT Development Board Only Arria V FPGA U13 FMC Bank B Voltage Select J11 FMC Bank B Power Source Select J28 DDR3C Fan Power 019 U22 014 Arria V FPGA Clock Input PCI Tx Rx DDR3A Buliseye T
21. 050 A TPS51200 gt VTT DDR3A gt VREF DDR3B 0 75 V 0 050 A TPS51200 VTT DDR3B 1 345 A LTM4618 ANN 1 8 3 3V 4 500 A A5 VCCIO FMC Switching Regulator gt VCCIO_FMC 1 15 V 29 902 A A5 VCCINT FPGA VCC Rense 3 426 A LTC3880 Switching gt A5 VCCP Regulator 396 BEAD FPGA VCCP 5 0V T 0 018 A 0018 gt Character LCD MAX3378 a Channel 1 LDO PCle Motherboard deal Diode Regulator Bias 12 V 5 5 A Maximum Multiplexer 12V 8 651A 0 220 LT3029 5 37 V 0 220 A ADC MONITOR DCINPUT19V aera Channel 2 LDO LT2418 x2 1103855 Dual Multiplexer Channel Controller 73 3 3V 2 451 A 3 3V 2 198 3 3V gt 1398543 CLK Buffer EZ USB V SDI OSC Display Port PCle Motherboard 3 3 V 3 0 A Maximum LTC3025 1 0 5 A 1 0 V 0 253 A 1 0V Ideal Diode Linear Regulator ENET DVDD Multiplexer I 124804 12 12V 11 HSMA HSMB 12V 5 971 A LTM4601 3 3 3 3V_ATX 12V 2 971 A Switching Regulator HSMA HSMB SFP FMC December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 10 Power Measurement There are 16 power supply rails that have on board voltage current and wattage sense capabilities using 24 bit differential ADC devices Precision sense resistors split the ADC devices and rails from the primary supply plane for the ADC to
22. 2 Board Components Components and Interfaces 2 39 Table 2 26 HSMC Port A Pin Assignments Schematic Signal Names and Functions Part 2 of 5 Board 2 Reference J1 Schematic Signal Name M Maks 1 0 Standard Description 4 HSMA RX N7 E2 1 5 V PCML Transceiver RX bit 7n 5 HSMA TX P6 H3 1 5 V PCML Transceiver TX bit 6 6 HSMA RX P6 J1 1 5 V PCML Transceiver RX bit 6 7 HSMA TX N6 H4 1 5 V PCML Transceiver TX bit 6n 8 HSMA RX N6 J2 1 5 V PCML Transceiver RX bit 6n 9 HSMA TX P5 K3 1 5 V PCML Transceiver TX bit 5 10 HSMA RX P5 L1 1 5 V PCML Transceiver RX bit 5 11 HSMA TX N5 K4 1 5 V PCML Transceiver TX bit 5n 12 HSMA RX N5 L2 1 5 V PCML Transceiver RX bit 5n 13 HSMA TX P4 1 5 V PCML Transceiver TX bit 4 14 HSMA P4 N1 1 5 V PCML Transceiver RX bit 4 15 HSMA TX N4 M4 1 5 V PCML Transceiver TX bit 4n 16 HSMA N4 N2 1 5 V PCML Transceiver RX bit 4n 17 HSMA TX P3 AH3 1 5 V PCML Transceiver TX bit 3 18 HSMA RX P3 AJ1 1 5 V PCML Transceiver RX bit 3 19 HSMA TX N3 4 1 5 V PCML Transceiver TX bit 3n 20 HSMA RX N3 AJ2 1 5 V PCML Transceiver RX bit 3n 21 HSMA TX P2 V3 1 5 V PCML Transceiver TX bit 2 22 HSMA RX P2 1 5 V PCML Transceiver RX bit 2 23 HSMA TX N2 V4 1 5 V PCML Transceiver TX bit 2n 24 HSMA RX N2 W2 1 5 V PCML Transceiver RX bit 2n 25 HSMA TX PI
23. 2 5 V CMOS FMC data bus HPC bank A J9 FMC HA P7 AH14 2 5 V CMOS FMC data bus bank A F10 FMC HA P8 AD19 2 5 V CMOS FMC data bus bank A E9 FMC HA P9 7 2 5 V CMOS data bus HPC bank A K13 FMC HA P10 F6 2 5 V CMOS FMC data bus HPC bank A J12 FMC HA P11 AC18 2 5 V CMOS FMC data bus bank A F13 FMC HA P12 AJ18 2 5 V CMOS FMC data bus bank A Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Components and Interfaces Table 2 29 FMC Connector Pin Assignments Schematic Signal Names and Functions Part 4 of 7 2 49 kita 2 uw 1 0 Standard Description J10 Pin Numher E12 FMC HA P13 AF19 2 5 V CMOS FMC data bus bank A J15 FMC HA 14 AD14 2 5 V CMOS FMC data bus bank A F16 FMC HA 15 AH20 2 5 V CMOS FMC data bus HPC bank A E15 FMC HA 16 AL17 2 5 V CMOS FMC data bus HPC bank A K16 FMC HA P17 AT25 2 5 V CMOS FMC data bus bank A J18 FMC HA P18 AP20 2 5 V CMOS FMC data bus bank A F19 FMC HA P19 AP19 2 5 V CMOS FMC data bus HPC bank A E18 FMC HA P20 21 2 5 V CMOS FMC data bus bank A K19 _ 21 23 2 5 V CMOS FMC data bus bank A J21 FMC HA P22 AP22 2 5 V CMOS FMC data bus bank A K22 FMC HA P23 AP24 2 5 V CMOS FMC data bus bank A K26 FMC HB
24. 2 5 V CMOS FMC data bus LPC bank A D26 FMC LA P26 AL22 2 5 V CMOS FMC data bus LPC bank A C26 FMC LA P27 AH23 2 5 V CMOS FMC data bus LPC bank A H31 FMC LA P28 AH24 2 5 V CMOS FMC data bus LPC bank A G30 FMC LA P29 AP26 2 5 V CMOS FMC data bus LPC bank A H34 FMC LA P30 AF27 2 5 V CMOS FMC data bus LPC bank A 033 LA P31 AH27 2 5 V CM0S FMC data bus LPC bank A H37 FMC LA P32 AD24 2 5 V CM0S FMC data bus LPC bank A G36 FMC_LA P33 AD25 2 5 V CMOS FMC data bus LPC bank A F1 M2C PG 2 5 V CMOS Power good input H2 PRSNT 2 5 V CMOS FMC module present C30 FMC SCL 2 5 V CMOS Management serial clock line C31 FMC SDA 2 5 V CMOS Management serial data line Bull s Eye Connector The development board comes with Samtec s Bull s Eye system which includes four SMA cables along with the insertion tool to insert the cables into the connector Arria V GT FPGA Development Board The Bull s Eye high density RF interconnect system allows many channels to be compacted into a small area on a printed circuit board at a comparable performance to SMA connectors The cables allow you to monitor only two differential signals at a time You can move the cables from one channel to another using the tool included with this board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components 2 53 Components and Interfaces Figure 2 11 shows a diagram of the color coded Bull s Eye conne
25. 42 104 HSMB RX D N8 AT29 LVDS or 2 5 V LVDS RX bit 8n or CMOS bit 43 107 HSMB TX D P9 AP30 LVDS or 2 5 V LVDS TX bit 9 or CMOS bit 44 108 HSMB RX D P9 AW31 LVDS or 2 5 V LVDS RX bit 9 or CM0S bit 45 109 HSMB TX D N9 AN30 LVDS or 2 5 V LVDS TX bit 9n or CMOS bit 46 110 HSMB RX D N9 AW30 LVDS or 2 5 V LVDS RX bit 9n or CMOS bit 47 113 HSMB TX D P10 AR28 LVDS or 2 5 V LVDS TX bit 10 or CMOS bit 48 114 HSMB RX D P10 AW28 LVDS or 2 5 V LVDS RX bit 10 or CMOS bit 49 115 HSMB TX D N10 AP28 LVDS or 2 5 V LVDS TX bit 10n or CMOS bit 50 116 HSMB RX D N10 AW29 LVDS or 2 5 V LVDS RX bit 10n or CMOS bit 51 119 HSMB TX D P11 AV30 LVDS or 2 5 V LVDS TX bit 11 or CMOS bit 52 120 HSMB RX D P11 AU27 LVDS or 2 5 V LVDS RX bit 11 or CMOS bit 53 121 HSMB TX D N11 AU30 LVDS or 2 5 V LVDS TX bit 11n or CMOS bit 54 122 HSMB RX D N11 AT27 LVDS or 2 5 V LVDS RX bit 11n or CMOS bit 55 125 HSMB TX D P12 AV31 LVDS or 2 5 V LVDS TX bit 12 or CMOS bit 56 126 HSMB RX D P12 AW27 LVDS or 2 5 V LVDS RX bit 12 or CMOS bit 57 127 HSMB TX D N12 AU31 LVDS or 2 5 V LVDS TX bit 12n or CMOS bit 58 128 HSMB RX D N12 AV27 LVDS or 2 5 V LVDS RX bit 12n or CMOS bit 59 131 HSMB TX D P13 AR27 LVDS or 2 5 V LVDS TX bit 13 or CMOS bit 60 132 HSMB RX D P13 AW32 LVDS or 2 5 V LVDS RX bit 13 or CMOS bit 61 133 HSMB TX D N13 AP27 LVDS or 2 5 V LVDS TX bit 13n or CMOS bit 62 134 HSMB RX D N13 AW33 LVDS or 2 5 V LVDS RX bit 13n or CMOS bit 63 137 HSMB TX D P14 AP31 L
26. 5 V USER1 LED RO U16 AL15 2 5 V D24 USER1 LED G1 U16 R18 2 5 V USER1 LED R1 U16 AC15 2 5 V D23 USER1 LED G2 U16 F11 2 5 V USER1 LED R2 U16 AD14 2 5 V 029 USER1 LED G3 U16 AP11 2 5 V USER1 LED R3 U16 AN8 2 5 V USER1 LED G4 U16 AU14 2 5 V USER1 LED R4 U16 AP8 2 5 V D20 USER1 LED G5 U16 AE16 2 5 V USER1 LED R5 U16 AK14 2 5 V D19 USER1 LED G6 U16 AF15 2 5 V USER1 LED R6 U16 AG14 2 5 V D18 USER1_LED_G7 U16 AK15 2 5 V USER1_LED_R7 U16 AH15 2 5 V D33 USER2_LED_G0 U13 M19 2 5 V USER2 LED RO U13 N20 2 5 V USER2 LED G1 U13 L19 2 5 V USER2_LED_R1 U13 C15 2 5 V USER2 LED G2 U13 K19 2 5 V a USER2 LED R2 U13 AL28 2 5 V USER2 LED G3 U13 J19 2 5 V idi USER2 LED R3 U13 F11 2 5 V D29 USER2 LED G4 U13 K20 2 5 V USER2 LED R4 U13 AJ31 2 5 V D28 USER2 LED G5 U13 J20 2 5 V USER2 LED R5 U13 AN34 2 5 V 027 USER2 LED G6 U13 T20 2 5 V USER2 LED R6 U13 AJ34 2 5 V D26 USER2 LED G7 U13 R20 2 5 V USER2 LED R7 U13 AK33 2 5 V Description User defined LEDs for FPGA 1 User defined LEDs for FPGA 2 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 30 HSMC User Defined LEDs Each HSMC port has two LEDs located nearby There are no board specific functions for the HSMC LEDs The LEDs are labeled TX and RX and are intended to display data flow to and from the connected HSMC daughtercards The LEDs are driven by the Arria V GT FPGA Chapter 2 Board Components General Us
27. 50 ppm using the UP and DN voltage control lines to the VCXO Table 2 20 lists the supported output standards for the SD and HD input Table 2 20 Supported Output Standards for SD and HD Input SD HD Input Supported Output Standards Rise Tlme 0 SMPTE 424M SMPTE 292M Faster 1 SMPTE 259M Slower St For more information about the application circuit of the LMH0303SQx cable driver refer to the cable driver data sheet at www national com December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 32 Chapter 2 Board Components General User Input Output Table 2 21 summarizes the SDI video output interface pin assignments signal names and functions Table 2 21 SDI Video Output Interface Pin Assignments Schematic Signal Names and Functions Reference U24 Signal Name pin Number VO Standard Description 1 SDI A TX P 1 4 V PCML SDI video input P 2 SDI A TX N 4 1 4 V PCML SDI video input N 4 SDI A TX RSET 3 3 V Device reset pull up register 6 SDI A TX EN AK31 2 5 Device enable 10 SDI A TX SD HDN M20 2 5 V High definition select 11 SDI A TXDRV N 3 3 V SDI video output from cable driver N 12 SDI A TXDRV P 3 3 V SDI video output from cable driver P The cable equalizer supports operation at 270 Mbit SD 1 5 Gbit HD and 3 0 Gbit dual link HD modes Control signals are allowed for bypassing or disabli
28. A TX R16 P F3 LVDS or 2 5 V Transceiver channel 8 SMA A TX R17 N B4 LVDS or 2 5 V Transceiver channel 9 SMA A TX R17 P B3 LVDS or 2 5 V Transceiver channel 15 SMA 10G RX N1 H38 LVDS or 2 5 V Transceiver channel December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 54 Chapter 2 Board Components Table 2 30 Bull s Eye Connector Pin Assignments Schematic Signal Names and Functions Memory Board Arria V GT FPGA m Reference J16 Schematic Signal Name Pin Number 1 0 Standard Description 16 SMA B 10G RX P1 H39 LVDS or 2 5 V Transceiver channel 5 SMA B 6G NO AC2 LVDS or 2 5 V Transceiver channel 6 SMA B 6G 1 LVDS or 2 5 V Transceiver channel 19 SMA B 115 N G36 LVDS or 2 5 V Transceiver channel 20 SMA B TX L15 P 037 LVDS or 2 5 V Transceiver channel 10 SMA B TX R6 N 4 LVDS or 2 5 V Transceiver channel 14 SMA B TX R6 P LVDS or 2 5 V Transceiver channel Memory This section describes the development board s memory interface support and also their signal names types and connectivity relative to the Arria V GT FPGA The development board has the following memory interfaces m DDR3 m QDRII m Flash Te For more information about the memory interfaces refer to the following documents m Timing Analysis section in volume 4 of the External Memory Interface Handbook m DDR DDR2 and DDR3 SDRAM Des
29. Address bus A2 QDRII A20 AU32 1 8 V HSTL Address bus B7 QDRII BWSNO AK27 1 8 V HSTL Write byte write select 0 QDRII_BWSN1 AB25 1 8 V HSTL Write byte write select 1 A5 QDRII BWSN2 AM25 1 8 V HSTL Write byte write select 2 5 QDRII BWSN3 AV24 1 8 V HSTL Write byte write select 3 R6 QDRII C N AG24 1 8 V HSTL Clock N P6 QDRII C P 023 1 8 VHSTL Clock P A1 QDRII N AR21 1 8 VHSTL Echo clock 11 QDRII CQ P AT21 1 8 V HSTL Echo clock P P10 QDRII DO AE28 1 8 V HSTL Write data bus Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual Chapter 2 Board Components Memory Table 2 34 QDRII Pin Assignments Schematic Signal Names and Functions Part 2 of 3 2 65 Reference U8 Signal Name Pin Number VO Standard Description N11 QDRII 01 27 1 8 V HSTL Write data bus M11 QDRII D2 AB28 1 8 V HSTL Write data bus K10 QDRII D3 AM28 1 8 V HSTL Write data bus J11 QDRII 04 AC27 1 8 V HSTL Write data bus 611 QDRII_D5 AD27 1 8 V HSTL Write data bus E10 QDRII D6 AR28 1 8 VHSTL Write data bus D11 QDRII D7 AU28 1 8 VHSTL Write data bus C11 QDRII D8 AV28 1 8 V HSTL Write data bus N10 QDRII D9 AW29 1 8 V HSTL Write data bus M9 QDRII D10 AW28 1 8 V HSTL Write data bus L9 QDRII 11 AR27 1 8 V HSTL Write data bus J9 QDRII D12 AT27 1 8 V HSTL Wri
30. FPGA 1 reset push button CPU2 RESETN E6 2 5 V FPGA 2 reset push button DEVICE1 LED D13 2 5 V FPGA 1 configuration done LED DEVICE2 LED C15 2 5 V FPGA 2 configuration done LED EXTRA SIGO B10 2 5 V Reserved for future use EXTRA SIGI F16 1 8 V Reserved for future use EXTRA SIG2 J16 1 8 V Reserved for future use FACTORY USER1 A5 2 5 V Load factory or user design at power up FACTORY USER2 C4 2 5 V Load factory or user design at power up FACTORY REQUEST B9 2 5 V On Board USB Blaster request to send FACTORY command FACTORY STATUS F10 2 5 V On Board USB Blaster FACTORY command status FLASH ACCESSN B12 1 8 V FM bus flash memory access indication FLASH ADVN 615 1 8 V FM bus flash memory address valid FLASH CEN E16 1 8 bus flash memory enable FLASH CLK E17 1 8 V FM bus flash memory clock FLASH OEN F14 1 8 bus flash memory output enable FLASH RDYBSYN D18 1 8 V FM bus flash memory ready FLASH_RESETN F13 1 8 V FM bus flash memory reset FLASH WEN D17 1 8 V FM bus flash memory write enable FM 0 17 1 8 V FM bus address FM Al R15 1 8 V FM bus address FM A2 T16 1 8 V FM bus address FM A3 F15 1 8 V FM bus address FM A4 R16 1 8 V FM bus address FM A5 P15 1 8 V FM bus address FM A6 R17 1 8 V FM bus address FM A7 P14 1 8 V FM bus address December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 10 Table 2 5 MAX II CPLD EPM2210 System Controller Device Pin Out Part 2 of 5 Chap
31. HPC bank B E36 FMC HB P21 AM13 2 5 V CMOS FMC data bus HPC bank B D30 FMC JTAG TDI 2 5 V CMOS JTAG data in D31 FMC JTAG TDO 2 5 V CMOS JTAG data out D33 FMC JTAG TMS m 2 5 V CMOS JTAG mode select G7 FMC LA NO AN16 2 5 V CMOS FMC data bus LPC bank A D9 FMC LA N1 AV13 2 5 V CMOS FMC data bus LPC bank A H8 FMC LA N2 15 2 5 V CMOS FMC data bus LPC bank A G10 FMC LA N3 AW14 2 5 V CMOS FMC data bus LPC bank A H11 FMC LA N4 AK8 2 5 V CMOS FMC data bus LPC bank A D12 FMC LA N5 7 2 5 V CMOS data bus LPC bank A C11 FMC LA N6 AL9 2 5 V CMOS FMC data bus LPC bank A H14 FMC LA N7 AUG 2 5 V CMOS FMC data bus LPC bank A 613 FMC LA N8 AN9 2 5 V CMOS FMC data bus LPC bank A D15 FMC LA N9 AG17 2 5 V CMOS FMC data bus LPC bank A C15 FMC LA N10 7 2 5 V CMOS data bus LPC bank A H17 FMC LA N11 AK15 2 5 V CMOS FMC data bus LPC bank A 516 LA N12 AJ16 2 5 V CM0S FMC data bus LPC bank A D18 FMC LA N13 AK14 2 5 V CMOS FMC data bus LPC bank A C19 FMC LA N14 2 5 V CMOS data bus LPC bank A H20 FMC LA N15 AL16 2 5 V CMOS FMC data bus LPC bank A 519 LA N16 AK24 2 5 V CM0S FMC data bus LPC bank A D21 FMC LA N17 AN15 2 5 V CMOS FMC data bus LPC bank A Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Components and Interfaces Table 2 29 FMC Connector Pin Assignments Schematic Signal Names and Funct
32. M23 1 5 V SSTL Class Data bus byte lane F2 DDR3C DQ18 B24 1 5 V SSTL Class Data bus byte lane F8 DDR3C 0019 R23 1 5 V SSTL Class Data bus byte lane H3 DDR3C DQ20 G24 1 5 V SSTL Class Data bus byte lane H8 DDR3C DQ21 G23 1 5 V SSTL Class Data bus byte lane G2 DDR3C DQ22 F24 1 5 V SSTL Class Data bus byte lane H7 DDR3C DQ23 F23 1 5 V SSTL Class Data bus byte lane 07 DDR3C 0024 R24 1 5 V SSTL Class Data bus byte lane C3 DDR3C DQ25 G25 1 5 V SSTL Class Data bus byte lane C8 DDR3C DQ26 T26 1 5 V SSTL Class Data bus byte lane C2 DDR3C DQ27 E25 1 5 V SSTL Class Data bus byte lane DDR3C DQ28 N24 1 5 V SSTL Class Data bus byte lane A2 DDR3C DQ29 K24 1 5 V SSTL Class Data bus byte lane B8 DDR3C DQ30 T25 1 5 V SSTL Class Data bus byte lane A3 DDR3C DQ31 P24 1 5 V SSTL Class Data bus byte lane G3 DDR3C DQS N2 E24 1 5 V SSTL Class Data strobe N byte lane B7 DDR3C DQS N3 B25 1 5 V SSTL Class Data strobe N byte lane F3 DDR3C DQS P2 D24 1 5 V SSTL Class Data strobe P byte lane C7 DDR3C DQS P3 A25 1 5 V SSTL Class Data strobe P byte lane L8 DDR3B 203 1 5 V SSTL Class ZQ impedance calibration December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 64 QDRII Chapter 2 Board Components Memory The development board supports a burst of 4 QDRII SRAM memory device for very high speed low latency memory access The QDRII has a x36 int
33. NO AH13 2 5 V CMOS FMC data bus HPC bank B J25 FMC HB N1 AV12 2 5 V CMOS FMC data bus HPC bank B F23 FMC HB N2 11 2 5 V CMOS FMC data bus bank B E22 FMC HB N3 AW10 2 5 V CMOS FMC data bus HPC bank B F26 HB N4 AF13 2 5 V CMOS FMC data bus HPC bank B E25 FMC HB N5 AE14 2 5 V CMOS FMC data bus bank B K29 FMC HB N6 AF12 2 5 V CMOS FMC data bus bank B J28 FMC HB N7 AG11 2 5 V CMOS FMC data bus bank B F29 FMC HB N8 AP10 2 5 V CMOS FMC data bus HPC bank B E28 FMC HB N9 AL10 2 5 V CMOS FMC data bus HPC bank B K32 FMC HB N10 AC13 2 5 V CMOS FMC data bus HPC bank B J31 FMC HB N11 AV9 2 5 V CMOS FMC data bus HPC bank B F32 FMC HB N12 AU10 2 5 V CMOS FMC data bus HPC bank B E31 FMC HB N13 AT9 2 5 V CMOS FMC data bus HPC bank B K35 FMC HB N14 AP13 2 5 V CMOS FMC data bus HPC bank B J34 FMC HB N15 AH12 2 5 V CMOS FMC data bus HPC bank B F35 FMC HB N16 AN12 2 5 V CMOS FMC data bus HPC bank B K38 FMC HB N17 AC12 2 5 V CMOS FMC data bus HPC bank B J37 FMC HB N18 AD12 2 5 V CMOS FMC data bus HPC bank B E34 FMC HB N19 AT12 2 5 V CMOS FMC data bus HPC bank B F38 FMC_HB N20 AK12 2 5 V CMOS FMC data bus HPC bank B E37 FMC HB N21 AL13 2 5 V CMOS FMC data bus HPC bank B K25 HB PO AJ13 2 5 V CMOS FMC data bus HPC bank B J24 FMC HB P1 AW12 2 5 V CMOS FMC data bus HPC bank B F22 FMC HB P2 AU11 2 5 V CMOS FMC data bus HPC bank B E21 FMC HB P3 AW11 2 5 V CMOS data bus HPC ban
34. P19 2 5 V Equalizer bypass enable 11 SDI A RX P 1 4 VPCML SDI video output P 10 SDI A RX N AJ2 1 4 VPCML SDI video output 14 SDI EN AK34 2 5 V Device enable 15 SDI A RX CDN _ 3 3 V 1 s input carrier Components and Interfaces This section describes the development board s communication ports and interface cards relative to the Arria V GT FPGA The development board supports the following communication ports m PCIExpress 10 100 1000 Ethernet HSMC SFP modules FMC connector Bull s Eye connector PCI Express The Arria V GT FPGA development board is designed to fit entirely into a PC motherboard with a x8 PCI Express slot that can accommodate a full height long form factor add in card This interface uses the Arria V GT FPGA s PCI Express hard IP block saving logic resources for the user logic application The PCI express edge connector has a presence detect feature to allow the motherboard to determine if a card is installed For more information on using the PCI Express hard IP block refer to the PCI Express Compiler User Guide The PCI Express interface supports auto negotiating channel width from x1 to x4 to x8 by using Altera s PCIe MegaCore IP You can also configure this board to a x1 x4 or x8 interface through a DIP switch that connects the PRSNTn pins for each bus width The PCI Express edge connector has a connection speed of 2 5 Gbps lane for a maximum of 20 Gbps full duplex G
35. P3 P3 2 5 V CMOS Transmit channel A34 FMC DP C2M P4 H3 2 5 V CMOS Transmit channel A38 FMC DP C2M P5 M3 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B36 FMC DP C2M P6 K3 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B32 FMC DP C2M P7 F3 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B28 FMC DP C2M P8 D3 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B24 FMC DP C2M P9 B3 2 5 V CMOS Transmit channel available in Arria V GT FPGA device C7 FMC DP M2C NO AE2 2 5 V CMOS Transmit channel A3 FMC DP M2C N1 AA2 2 5 V CMOS Transmit channel DP M2C N2 U2 2 5 V CMOS Transmit channel A11 FMC DP M2C N3 R2 2 5 V CMOS Transmit channel A15 FMC DP M2C 114 J2 2 5 V CMOS Transmit channel A19 FMC DP M2C N5 N2 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B17 FMC DP M2C N6 L2 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B13 FMC DP M2C N7 G2 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B9 FMC DP M2C N8 E2 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B5 FMC DP M2C N9 C2 2 5 V CMOS Transmit channel available in Arria V GT FPGA device C6 FMC DP M2C PO 1 2 5 V CMOS Transmit channel A2 FMC DP M2C P1 AAI 2 5 V CMOS Transmit channel A6 FMC DP M2C P2 U1 2 5 V CMOS Transmit channel A10 FMC DP M2C P3 R1 2 5 V CMOS Transmit channel A14 FMC DP M2C P4 Ji 2 5 V CMOS Trans
36. T11363 2006 standard 2 X indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant threshold of the SJ T11363 2006 standard but it is exempted by EU RoHS Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation 3 Board Components Reference This chapter lists the component reference and manufacturing information of all the components on the Arria V GT FPGA FPGA development board Table 3 1 Component Reference and Manufacturing Information Part 1 of 2 Board Manufacturing Manufacturer Reference Component Manufacturer Part Number Website FPGAs Arria V GT F1517 504K U13 U16 LEs lead free Altera Corporation 5AGTFD7K3F4013N www altera com IC MAX CPLD EPM2210 U2 324FBGA 3 LF 1 8V VCCINT Altera Corporation EPM2210GF324 www altera com D2 D12 Green LEDs Lumex Inc SML LXT0805GW TR www lumex com 034 040 D45 Yellow LEDs Lumexinc SML LXTOBOSYW TR www umex com D18 D33 Bi color Red Green LEDs Lite On LTST C195KGJRKT www lite on com D13 Red LED Lumex Inc SML LXT0805IW TR www lumex com D1 Blue LED Lumex Inc SML LX0805USBC TR www lumex com 5 C amp K Components SW5 SW7 Four position DIP switches ITT Industrias TDAO4HOSB1 www ittcannon com S1 S4 S8 Reset push buttons TS A02SA 2 S10
37. T3 1 5 V PCML Transceiver TX bit 1 26 HSMA Pl U1 1 5 V PCML Transceiver RX bit 1 27 HSMA TX NI 14 1 5 V PCML Transceiver TX bit 1n 28 HSMA NI U2 1 5 V PCML Transceiver RX bit 1n 29 HSMA TX P3 1 5 V PCML Transceiver TX bit 0 30 HSMA RX R1 1 5 V PCML Transceiver RX bit 0 31 HSMA TX NO P4 1 5 V PCML Transceiver TX bit On 32 HSMA_RX_NO R2 1 5 V PCML Transceiver RX bit On 33 HSMA SDA 14 2 5 V CMOS Management serial data 34 HSMA SCL AU15 2 5 V CMOS Management serial clock 35 JTAG TCK AV34 2 5 V CMOS JTAG clock signal 36 HSMA JTAG TMS 2 5 V CMOS JTAG mode select signal 37 HSMA JTAG TDO 2 5 V CMOS JTAG data output 38 AVB JTAG TDO AT34 2 5 V CMOS JTAG data output 39 HSMA CLK OUTO AL14 LVDS or 2 5 V Dedicated CMOS clock out 40 HSMA CLK INO LVDS or 2 5 V Dedicated CMOS clock in 41 HSMA DO AG16 2 5 V CMOS Dedicated CMOS 1 0 bit 0 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 40 Chapter 2 Board Components Components and Interfaces Table 2 26 HSMC Port A Pin Assignments Schematic Signal Names and Functions Part 3 of 5 Board kou Arria V GT t Reference J1 Schematic Signal Name M 1 0 Standard Description 42 HSMA D1 AH16 2 5 V CMOS Dedicated CMOS bit 1 43 H
38. Usage Part 1 of 2 Function 1 0 Standard 1 0 Count Special Pins DDR3 x64 device 1 5 V SSTL 156 1 differential x9 differential DQS HSMC port B 2 5 V CMOS LVDS 84 1 reference clock FMC 2 5 V 178 1 reference clock SDI 2 5 V CMOS 8 1 reference clock Chip to chip bridge 2 5 V 120 1 reference clock Buttons 2 5 V CMOS 4 Switches 2 5 V CMOS 8 LEDs 2 5 V CMOS 16 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 8 Chapter 2 Board Components MAX II CPLD EPM2210 System Controller Tahle 2 4 Arria V GT FPGA 2 Pin Count and Usage Part 2 of 2 Function 1 0 Standard 1 0 Count Special Pins Clocks or Oscillators 1 8 V CMOS LVDS 5 differential clocks 1 single ended Total 1 0 Used 584 Transceivers SMAs or Bull s Eye 12 HSMC port B 16 FMC 40 Chip to chip bridge 32 Total Transceivers 116 MAX 11 CPLD EPM2210 System Controller The board utilizes the EPM2210 System Controller an Altera MAXII CPLD for the following purposes m FPGA configuration from flash m Power consumption monitoring m Virtual JTAG interface for PC based GUI m Control registers for clocks m Control registers for remote system update Figure 2 3 illustrates the MAX II CPLD EPM2210 System Controller s functionality and external circuit connections as a block diagram Figure 2 3 M
39. V Address bus G1 FM A23 1 8 Address bus H8 24 AN29 1 8 V Address bus B6 25 AL32 1 8 V Address bus B8 26 1 1 8 Address bus F2 FM DO 22 1 8 Data bus 2 FM DI AH20 1 8 Data bus G3 FM D2 AG22 1 8 V Data bus E4 FM D3 AN20 1 8 Data bus E5 FM D4 AP20 1 8 V Data bus G5 FM D5 AV22 1 8 V Data bus G6 FM D6 AG23 1 8 V Data bus H7 FM D7 AN22 1 8 Data bus 51 FM 18 21 1 8 Data bus E3 FM D9 AD21 1 8 V Data bus F3 FM D10 AN23 1 8 V Data bus F4 FM 011 21 1 8 V Data bus F5 FM D12 AL22 1 8 Data bus H5 FM D13 AG20 1 8 V Data bus G7 FM 114 AK22 1 8 V Data bus E7 FM 015 AK23 1 8 V Data bus Power Supply A laptop style DC power input provides power to the development board The input voltage must be in the range of 14 V to 20 V The DC voltage is then stepped down to various power rails used by the board components and installed into the HSMC connectors An on board multi channel analog to digital converter ADC measures both the voltage and current for several specific board rails The power utilization is displayed on a graphical user interface GUI that can graph power consumption versus time Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Power Supply Power Distribution System Figure 2 12 shows the power distribution system on the development board Regulator efficiencies and sharing are reflected in t
40. bus byte lane C7 DDR3A DQ65 L22 1 5 V SSTL Class Data bus byte lane C2 DDR3A DQ66 C22 1 5 V SSTL Class Data bus byte lane C8 DDR3A DQ67 N22 1 5 V SSTL Class Data bus byte lane DDR3A DQ68 E22 1 5 V SSTL Class Data bus byte lane E8 DDR3A DQ69 J22 1 5 V SSTL Class Data bus byte lane D2 DDR3A DQ70 A23 1 5 V SSTL Class Data bus byte lane E7 DDR3A DQ71 F22 1 5 V SSTL Class Data bus byte lane D3 DDR3A DQS N8 D23 1 5 V SSTL Class Data strobe N byte lane C3 DDR3A DQS P8 C23 1 5 V SSTL Class Data strobe P byte lane G1 DDR3A ODT E33 1 5 V SSTL Class On die termination enable F3 DDR3A RASN A32 1 5 V SSTL Class Row address select N2 DDR3A RESETN J31 1 5 V SSTL Class Reset H3 DDR3A WEN G29 1 5 V SSTL Class Write enable H8 DDR3A ZQ05 1 5 V SSTL Class ZQ impedance calibration DDR3A U11 E7 DDR3A DM6 M32 1 5 SSTL Class Write mask byte lane D3 DDR3A DM7 D31 1 5 V SSTL Class Write mask byte lane DDR3A DQ48 T26 1 5 V SSTL Class Data bus byte lane F DDR3A DQ49 R24 1 5 V SSTL Class Data bus byte lane F2 DDR3A DQ50 D25 1 5 V SSTL Class Data bus byte lane F8 DDR3A DQ51 T25 1 5 V SSTL Class Data bus byte lane H3 DDR3A DQ52 E25 1 5 V SSTL Class Data bus byte lane Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Memory Table 2 31 DDR3A Devices Pin Assignments Schematic Signal Names and Functio
41. depends on the switch settings but the FPGAs and MAX II devices are always in the JTAG chain December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 16 Chapter 2 Board Components Configuration Status and Setup Elements Flash Memory Programming Flash memory programming is possible through a variety of methods The default method is to use the factory design Board Update Portal BUP This design is an embedded webserver which serves the BUP web page The web page allows you to select new FPGA designs including hardware software or both in an industry standard S Record File flash and write the design to the user hardware page page 1 of the flash memory over the network The secondary method is to use the pre built parallel flash loader PFL design included in the development kit The development board implements the Altera PFL megafunction for flash memory programming The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device FPGA or CPLD The PFL functions as a utility for writing to a compatible flash memory device This pre built design contains the PFL megafunction that allows you to write either page 0 page 1 or other areas of flash memory over the USB interface using the Quartus II software This method is used to restore the development board to its factory default settings Other methods to program the flash memory can be used as well includi
42. designs implemented in the Arria V GT FPGAs operate faster with lower power and have a faster time to market than previous FPGA families For more information on the following topics refer to the respective documents W Arria V device family refer to the Arria V Device Handbook m PCIExpress MegaCore function refer to the PCI Express Compiler User Guide m HSMC Specification refer to the High Speed Mezzanine Card HSMC Specification December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual Chapter 1 Overview Board Component Blocks Board Component Blocks The development board features the following major component blocks Two Arria GT FPGA 5AGTFD7KS3FAOI3N in the 1517 pin FineLine BGA FBGA package m 504K LEs m 190 240 adaptive logic modules ALMs 24 140 Kbit Kb M10K on die memory 2 906 Kb MLAB memory 36 transceivers m 16 phase locked loops PLLs 2 312 18x18 multipliers m 1 15 V core voltage MAX II CPLD EPM2210GF324 System Controller in the 324 pin FBGA package FPGA configuration circuitry m MAXII CPLD EPM570GM100 and flash fast passive parallel FPP configuration m On board USB Blaster II for use with the Quartus II Programmer Clocking circuitry m Nine on board oscillators m One 50 MHz oscillator m Two 125 MHz oscillators m Clock buffer with six outputs sourced by SMA or programmable oscillator with a default frequency of 100 MHz m One programmab
43. mer 25V CMOS fo ground through a 439 Ka resistor 2 AK7 2 5 V CMOS RGMII receive clock 95 ENET RX DO AU17 2 5 V CMOS RGMII receive data 92 DI 17 2 5 V CMOS RGMII receive data 93 ENET RX D2 AW16 2 5 V CMOS RGMII receive data 91 RX 18 2 5 V CMOS RGMII receive data 94 RX DV AW17 2 5 V CM0S RGMII receive data valid 15 ENET RX N AK19 2 5 V CMOS RGMII receive channel 77 ENET_RX P AL19 2 5 V CMOS RGMII receive channel 11 ENET TX DO AT19 2 5 V CMOS RGMII transmit data 12 TX DI AU18 2 5 V CMOS RGMII transmit data 14 ENET TX D2 AH19 2 5 V CMOS RGMII transmit data 16 ENET TX D3 AG19 2 5 V CMOS RGMII transmit data 9 ENET TX EN AP19 2 5 V CMOS RGMII transmit enable 81 ENET TX N AE19 2 5 V CMOS RGMII transmit channel 82 ENET TX P AF19 2 5 V CMOS RGMII transmit channel 55 ENET XTAL 25MHZ 2 5 V CMOS 25 MHz clock 29 MDI PO 2 5 V CMOS Media dependent interface 0 31 MDI NO 2 5 V CMOS Media dependent interface 0 33 MDI P1 2 5 V CMOS Media dependent interface 1 34 MDI N1 2 5 V CMOS Media dependent interface 1 39 MDI P2 2 5 V CMOS Media dependent interface 2 41 MDI_N2 2 5 V CM0S Media dependent interface 2 42 MDI P3 2 5 V CMOS Media dependent interface 3 43 MDI N3 2 5 V CMOS Media dependent interface HSMC The development board contains two HSMC interfaces port A on device 1 and por
44. or command select 5 LCD1_WEn M20 2 5 V LCD write enable 6 LCD1 CSn E18 2 5 V LCD chip select Arria FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components 2 31 General User Input Output Table 2 19 lists the LCD pin definitions and is an excerpt from Lumex data sheet Table 2 19 LCD Pin Definitions and Functions s Symbol Level Function 1 Vpp 5V 2 Vss Power supply GND 0 V 3 Vo For LCD drive Register select signal 4 RS H L H Data input L Instruction input H Data read module to MPU 5 R W H L L Data write MPU to module 6 E H H to L Enable 7 14 DBO DB7 H L Data bus software selectable 4 bit or 8 bit mode gt For more information such as timing character maps interface guidelines and other related documentation visit www lumex com SDI Video Output Input The SDI video port consists of a LMH0303SQx cable driver and a LMHO3845Q cable equalizer The PHY devices from National Semiconductor interface to single ended 75 O SMB connectors The cable driver supports operation at 270 Mbit standard definition SD 1 5 Gbit high definition HD and 3 0 Gbit dual link HD modes Control signals are allowed for SD and HD modes selections as well as device enable The device can be clocked by the 148 5 MHz voltage controlled crystal oscillator VCXO and matched to incoming signals within
45. the PCI Express link width x8 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 20 Chapter 2 Board Components Configuration Status and Setup Elements Setup Elements The development board includes several different kinds of setup elements This section describes the following setup elements Board settings DIP switch chain header switch PCI Express control DIP switch CPU reset push button MAX II reset push button Configuration push button m Image select push button a For more information about the default settings of the DIP switches refer to the Arria V GI FPGA Development Kit User Guide Board Settings DIP Switch The board settings DIP switch SW5 controls various features specific to the board and the MAX II CPLD EPM2210 System Controller logic design Table 2 8 lists the switch controls and descriptions Table 2 8 Board Settings DIP Switch Controls Schematic Switch Signal Name Description ON 100 MHz clock select 1 CLK SEL OFF SMA input clock select ON Enable on board oscillators OFF Disable on board oscillators ON Load the factory design from flash for Arria V FPGA 1 at power up OFF Load the user design from flash at power up 4 FACTORY USER2 Unused 2 CLK ENABLE 3 FACTORY USER1 JTAG Settings DIP Switch The JTAG settings DIP switch SW6 either remove or include devices in the acti
46. you attach to the board Installing daughtercards such as HSMC or FMC can affect performance and requires lower speed Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual Chapter 2 Board Components 2 15 Configuration Status and Setup Elements Figure 2 4 illustrates the JTAG chain Figure 2 4 JTAG Chain 10 pin DISABLE JTAG Header gt TCK Cypress TDO 5 On Board GPIO Di l TDI FPGA 1 in chain USB Blaster 4 100 JTAG Slave JTAG Master e TCK ALWAYS 3 IMS E 4 ENABLED gt in chain gt TDO JTAG Slave gt TCK TMS HSMC Installed Tpi Port A n Analo TDO Switc 25V ENABLE JTAG Slave TCK TMS Installed TDI PortB sme ENABLE JTAG Slave DIP switch CK Installed TMS EMC Port EMC gt gt TDI Card Analog TDO k ENABLE Switc JTAG Slave DIP switch K rus MAX II CPLD ALWAYS System 4 ENABLED Le Controller in chain JTAG Slave Each jumper shown in Figure 2 4 is located in the JTAG chain DIP switch SW6 on the back of the board To connect a device or interface in the chain you must set the corresponding switch from the JTAG chain DIP switch SW6 The interface in the JTAG chain
47. 0 www dawning2 com tw S3 Configuration push button uis Aa 15 025 2 5100 www dawning2 com tw S2 _ Image select push button 15 025 2 5100 www dawning2 com tw 125 000 MHz LVDS saw clock EG 2121CA 125 0000 X1 X4 oscillator Epson LGPNL3 www eea epson com X5 25 MHz oscillator Epson ien www eea epson com Y3 24 MHz crystal oscillator Epson FA 128 24 0000MB W www eea epson com a 5 25 MHz crystal oscillator Epson FA 128 25 0000MB C www eea epson com X6 50 MHz oscillator ECS Inc 5 3518 500 www ecsxtal com Si5338A A01316 GM U34 U48 Quad output programmable clock T 515338 01317 0 A U53 052 generator aligon Labs Ine Si5338A A01319 GM 100 MHz single output m X7 programmable oscillator Silicon Labs Inc 570FAB000433DG www silabs com 148 5 MHz single output X2 programmable Silicon Labs Inc 571FDB000159DG www silabs com December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual Chapter 3 Board Components Reference Table 3 1 Gomponent Reference and Manufacturing Information Part 2 of 2 Board Manufacturing Manufacturer Reference Component Manufacturer Part Number Website X7 100 MHz crystal oscillator ECS Inc ECS 3525 1000 B TR www ecsxtal com So STI User defined push button Dawning Precision Ts a02SA 2 S100 www dawnin
48. 1 1 5 V PCML Transceiver RX bit 0 31 HSMB TX NO 4 1 5 V PCML Transceiver TX bit On 32 HSMB RX NO AL2 1 5 V PCML Transceiver RX bit 33 HSMB SDA AG25 2 5 V CMOS Management serial data 34 HSMB SCL AH26 2 5 CMOS Management serial clock 35 JTAG TCK AV34 2 5 V CMOS JTAG clock signal 36 HSMB JTAG TMS 2 5 V CMOS JTAG mode select signal 37 HSMB JTAG TDO 2 5 V CMOS JTAG data output 38 HSMB JTAG TDI 2 5 V CMOS JTAG data input 39 HSMB CLK OUTO AJ33 LVDS or 2 5 V Dedicated CMOS clock out 40 HSMB CLK INO AR6 LVDS or 2 5 V Dedicated CMOS clock in 41 HSMB DO AW25 2 5 V CMOS Dedicated CMOS I 0 bit 0 42 HSMB 01 AW26 2 5 V CMOS Dedicated CMOS I 0 bit 1 43 HSMB D2 AV25 2 5 V CMOS Dedicated CMOS I 0 bit 2 44 HSMB D3 AV24 2 5 V CMOS Dedicated CMOS I 0 bit 3 Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Components and Interfaces 2 43 Table 2 27 HSMC Port B Pin Assignments Schematic Signal Names and Functions Part 2 of 4 1 0 Standard Description Reference J2 Schematic Signal Name Pin Number p 47 HSMB TX D PO AC29 LVDS or 2 5 V LVDS TX bit 0 or CMOS bit 4 48 HSMB RX D PO AC25 LVDS or 2 5 V LVDS RX bit 0 or CMOS bit 5 49 HSMB TX D NO AB29 LVDS or 2 5 V LVDS TX bi
49. 1 LVDS AK20 REFCLK3 B QR2 P LVDS T9 125 000 MHz FMC REFCLK3 B QR2 N LVDS T8 REFCLK2 B QR1 P LVDS Y9 100 000 MHz FMC REFCLK2 QR1 N LVDS Y8 REFCLK1 B P LVDS AD9 156 250 MHz HSMC port B SDI LVDS AD8 CLKINTOPB P1 LVDS H6 125 000 MHz Top edge FPGA 2 CLKINTOPB N1 LVDS J6 Off Board Clock Input Output The development board has input and output clocks which can be driven onto the board The output clocks can be programmed to different levels and I O standards according to the FPGA device s specification Table 2 12 lists the clock inputs for the development board Table 2 12 Off Board Clock Inputs m Arria V GT Source 1 0 Standard FPGA Pin Description Number CLKIN SMA P LVPECL Input to LVDS fan out buffer drives one REFCLK SMA one clock on the top edge and one on the bottom CLKIN SMA N LVPECL of each FPGA HSMC Hum Gee 2 5 V NT Single ended input from the installed HSMC cable or board HSMC HSMA CLK IN P1 LVDS 2 5 V AWA LVDS input from the installed HSMC cable or HSMA IN N1 LVDS LVTTL AV4 board Can also support 2x LVTTL inputs HSMC HSMA CLK IN_P2 LVDS LVTTL AR6 LVDS input from the installed HSMC cable or HSMA CLK IN N2 LVDS LVTTL AP6 board Can also support 2x LVTTL inputs HSMC GLE TNO 2 5 V AR6 Single ended input from the installed HSMC cable or board HSMC HSMB CLK IN P1 LVDS LVTTL AM33 LV
50. 3B A6 H31 1 5 V SSTL Class Address bus R2 DDR3B A7 J31 1 5 V SSTL Class Address bus T8 DDR3B A8 C31 1 5 V SSTL Class Address bus R3 DDR3B A9 D31 1 5 V SSTL Class Address bus L7 DDR3B A10 C32 1 5 V SSTL Class Address bus R7 DDR3B_A11 D32 1 5 V SSTL Class Address bus N7 DDR3B_A12 N31 1 5 V SSTL Class Address bus December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 60 Chapter 2 Board Components Memory Table 2 32 DDR3 x32 Devices Pin Assignments Schematic Signal Names and Functions Part 2 of 3 Board Reference ME 1 0 Standard Description T3 DDR3B A13 P31 1 5 V SSTL Class Address bus M2 DDR3B 0 M32 1 5 V SSTL Class Bank address bus N8 DDR3B 1 N32 1 5 V SSTL Class Bank address bus DDR3B_BA2 J34 1 5 V SSTL Class Bank address bus K3 DDR3B CASN L33 1 5 V SSTL Class Row address select K9 DDR3B CKE 1 1 5 V SSTL Class Column address select K7 DDR3B CLK N C30 1 5 V SSTL Class Differential output clock J7 DDR3B CLK P B30 1 5 V SSTL Class Differential output clock L2 DDR3B CSN L34 1 5 V SSTL Class Chip select Ki DDR3B ODT L31 1 5 V SSTL Class On die termination enable J3 DDR3B RASN K34 1 5 V SSTL Class Row address select T2 DDR3B RESETN G30 1 5 V SSTL Class
51. 4 Signal Name A pin Number VO Standard F6 FLASH_ADVN AK30 1 8 V Address valid B4 FLASH_CEN AU30 1 8 V Chip enable E6 FLASH CLK AL31 1 8 V Clock F8 FLASH OEN 1 8 Output enable F7 FLASH RDYBSYN 2 1 8 V Ready D4 FLASH RESETN AL34 1 8 Reset G8 FLASH WEN AN32 1 8 Write enable C6 FLASH WPN 1 8 V Write protect A1 FM Al AT30 1 8 Address bus B1 FM A2 AL30 1 8 V Address bus C1 FM A3 AP32 1 8 Address bus D1 FM A4 AM34 1 8 V Address bus D2 FM A5 AJ33 1 8 V Address bus A2 FM A6 1 8 Address bus C2 FM A7 AW33 1 8 V Address bus A3 FM A8 1 8 Address bus B3 FM A9 1 8 Address bus C3 FM A10 1 8 Address bus D3 11 AM31 1 8 V Address bus C4 FM A12 AP31 1 8 V Address bus A5 FM A13 AR31 1 8 V Address bus B5 FM A14 AT31 1 8 Address bus C5 FM A15 AE29 1 8 V Address bus 07 16 AG30 1 8 V Address bus D8 17 AV31 1 8 V Address bus 7 18 AW30 1 8 V Address bus B7 19 AW31 1 8 V Address bus C7 FM_A20 AV30 1 8 V Address bus December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 68 Chapter 2 Board Components Power Supply Table 2 35 Flash Pin Assignments Schematic Signal Names and Functions Part 2 of 2 Reference SignalName Pin Number VO Standard Description C8 FM A21 AT29 1 8 Address bus A8 22 AU29 1 8
52. 7 DDR3B DM2 J30 1 5 V SSTL Class Write mask byte lane Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Memory Table 2 32 DDR3 x32 Devices Pin Assignments Schematic Signal Names and Functions Part 3 of 3 2 61 Board Reference NEN 1 0 Standard Description D3 DDR3B DM3 J29 1 5 V SSTL Class Write mask byte lane E3 DDR3B DQ16 P27 1 5 V SSTL Class Data bus byte lane F7 DDR3B 1017 R27 1 5 V SSTL Class Data bus byte lane F2 DDR3B DQ18 H27 1 5 V SSTL Class Data bus byte lane F8 DDR3B DQ19 B27 1 5 V SSTL Class Data bus byte lane H3 DDR3B DQ20 C27 1 5 V SSTL Class Data bus byte lane H8 DDR3B DQ21 E27 1 5 V SSTL Class Data bus byte lane G2 DDR3B DQ22 M27 1 5 V SSTL Class Data bus byte lane H7 DDR3B_DQ23 N27 1 5 V SSTL Class Data bus byte lane D7 DDR3B_DQ24 C26 1 5 V SSTL Class Data bus byte lane C3 DDR3B DQ25 D26 1 5 V SSTL Class Data bus byte lane C8 DDR3B DQ26 K25 1 5 V SSTL Class Data bus byte lane C2 DDR3B DQ27 R26 1 5 V SSTL Class Data bus byte lane DDR3B 0028 27 1 5 V SSTL Class Data bus byte lane A2 DDR3B DQ29 A26 1 5 V SSTL Class Data bus byte lane B8 DDR3B DQ30 F26 1 5 V SSTL Class Data bus byte lane A3 DDR3B DQ31 G26 1 5 V SSTL Class Data bus byte lane G3 DDR3B DQS N2 T28 1 5 V SSTL Class Data strobe N byte lane B7 DDR3B 105 113
53. A22 1 5 V SSTL Class Data bus byte lane H7 DDR3C DQ7 C20 1 5 V SSTL Class Data bus byte lane 07 DDR3C 108 A23 1 5 V SSTL Class Data bus byte lane C3 DDR3C DQ9 E22 1 5 V SSTL Class Data bus byte lane C8 DDR3C DQ10 L22 1 5 V SSTL Class Data bus byte lane C2 DDR3C 0011 C22 1 5 V SSTL Class Data bus byte lane DDR3C 0012 N22 1 5 V SSTL Class Data bus byte lane A2 DDR3C 0013 F22 1 5 V SSTL Class Data bus byte lane B8 DDR3C 0014 P22 1 5 V SSTL Class Data bus byte lane A3 DDR3C 0015 J22 1 5 V SSTL Class Data bus byte lane G3 DDR3C DQS NO 21 1 5 V SSTL Class Data strobe N byte lane B7 DDR3C DQS 1 D23 1 5 V SSTL Class Data strobe N byte lane F3 DDR3C DQS A20 1 5 V SSTL Class Data strobe P byte lane C7 DDR3C DQS P1 C23 1 5 V SSTL Class Data strobe P byte lane Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Memory Table 2 33 DDR3 x64 Devices Pin Assignments Schematic Signal Names and Functions Part 3 of 3 2 63 Board Reference 2 1 0 Standard Description L8 DDR3B 704 1 5 V SSTL Class 20 impedance calibration DDR3C 022 E7 DDR3C DM2 J23 1 5 V SSTL Class Write mask byte lane D3 DDR3C DM3 D25 1 5 V SSTL Class Write mask byte lane DDR3C 0016 C24 1 5 V SSTL Class Data bus byte lane F DDR3C DQ17
54. AX li CPLD EPM2210 System Controller Block Diagram MAX II CPLD PC JTAG Control 1 Embedded lt SLD HUB Blaster Y Information Register Arria V Virtual JTAG ie 1 1 n Control Flash Register Power Measurement I 8 Results ontroller Power Calculations Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components MAX CPLD EPM2210 System Controller 2 9 Table 2 5 lists the I O signals present on the MAXII CPLD EPM2210 System Controller The signal names and functions are relative to the MAXII device U2 Table 2 5 MAX II CPLD EPM2210 System Controller Device Pin Out Part 1 of 5 Schematic Signal Name 1 0 Standard Description CLK125A EN B13 2 5 V 125 MHz oscillator enable CLK125B EN 07 2 5 125 MHz oscillator enable CLK50_EN D11 2 5 V 50 MHz oscillator enable CLK CONFIG K6 2 5 V 100 MHz configuration clock input CLK ENABLE B5 2 5 V DIP switch for clock oscillator enable CLK SEL E7 2 5 V DIP switch for clock select SMA or oscillator CLKIN MAX 50 K13 2 5 V 50 MHz clock input CLOCK SCL C14 2 5 V Programmable oscillator 126 clock CLOCK SDA 14 2 5 Programmable oscillator 120 data CPU1 RESETN B8 2 5 V
55. Bank 2 and bank 3 have all the pins populated as done in the QSH QTH series Figure 2 10 shows the bank arrangement of signals with respect to the Samtec connector s three banks Figure 2 10 HSMC Signal and Bank Diagram Bank 3 Power D 79 40 or CLKIN2 CLKOUT2 Bank 2 Power 013 0 LVDS CLKIN1 CLKOUT1 8 RX Channels JTAG SMB CLKINO CLKOUTO The HSMC interface has programmable bi directional I O pins that can be used as 2 5 V LVCMOS which is 3 3 V LVTTL compatible These pins can also be used as various differential I O standards including but not limited to LVDS mini LVDS and RSDS with up to 17 full duplex channels As noted in the High Speed Mezzanine Card HSMC Specification manual LVDS and single ended I O standards are only guaranteed to function when mixed according to either the generic single ended pin out or generic differential pin out Table 2 26 lists the HSMC port A interface pin assignments signal names and functions Table 2 26 HSMC Port A Pin Assignments Schematic Signal Names and Functions Part 1 of 5 Board Reference J1 Schematic Signal 1 0 Standard Description 1 HSMA TX P7 D3 1 5 V PCML Transceiver TX bit 7 HSMA P7 E1 1 5 V PCML Transceiver RX bit 7 3 HSMA TX N7 04 1 5 V PCML Transceiver TX bit 7n Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter
56. C SCL R5 2 5 V FMC module clock Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components MAX CPLD EPM2210 System Controller 2 11 Table 2 5 MAX II CPLD EPM2210 System Controller Device Pin Out Part 3 of 5 Schematic Signal Name 1 0 Standard Description FMC_SDA V2 2 5 V FMC module data FPGA1 CEN L1 2 5 V FPGA 1 chip enable FPGA1 CEON F11 2 5 V FPGA 1 chip output enable FPGA1 CONF DONE 4 2 5 FPGA 1 configuration done FPGA1 CONFIG DO D1 2 5 V FPGA configuration data FPGA1 CONFIG DI D3 2 5 V FPGA configuration data FPGA1 CONFIG 02 E2 2 5 V FPGA configuration data FPGA1 CONFIG 03 D4 2 5 V FPGA configuration data FPGA1 CONFIG 04 E1 2 5 V FPGA configuration data FPGA1_CONFIG_D5 E3 2 5 V FPGA configuration data FPGA1_CONFIG_D6 F3 2 5 V FPGA configuration data FPGA1_CONFIG_D7 E4 2 5 V FPGA configuration data FPGA1_CONFIG_D8 F2 2 5 V FPGA configuration data FPGA1_CONFIG_D9 E5 2 5 V FPGA configuration data FPGA1_CONFIG_D10 Fi 2 5 V FPGA configuration data FPGA1 CONFIG 011 F4 2 5 V FPGA configuration data FPGA1 CONFIG D12 G3 2 5 V FPGA configuration data FPGA1 CONFIG 013 F5 2 5 V FPGA configuration data FPGA1 CONFIG D14 G2 2 5 FPGA configuration data FPGA1 CONFIG 015 F6 2 5 V FPGA configuration data FPGA1 CVP CONFDONE 1 2 5 FPGA 1 confi
57. C data bus HPC bank A E7 FMC HA N5 AK11 2 5 V CMOS FMC data bus HPC bank A K11 FMC HA N6 K8 2 5 V CMOS FMC data bus HPC bank A J10 FMC HA N7 AG14 2 5 V CMOS FMC data bus HPC bank A F11 FMC HA N8 AC19 2 5 V CMOS FMC data bus HPC bank A E10 FMC HA N9 AL7 2 5 V CMOS FMC data bus HPC bank A K14 FMC HA N10 G6 2 5 V CMOS FMC data bus HPC bank A J13 FMC HA N11 AD17 2 5 V CMOS FMC data bus HPC bank A F14 FMC HA N12 AH18 2 5 V CMOS FMC data bus bank A E13 FMC HA N13 AE19 2 5 V CMOS FMC data bus HPC bank A J16 FMC HA N14 AC15 2 5 V CMOS FMC data bus HPC bank A F17 HA N15 AG20 2 5 V CMOS FMC data bus HPC bank A E16 FMC HA N16 AK17 2 5 V CMOS FMC data bus HPC bank A K17 FMC HA N17 AR25 2 5 V CMOS data bus bank A J19 FMC HA N18 AN20 2 5 V CMOS FMC data bus HPC bank A F20 FMC HA N19 AN19 2 5 V CMOS FMC data bus bank A E19 FMC HA N20 21 2 5 V CMOS FMC data bus bank A 20 FMC HA N21 AN23 2 5 V CMOS FMC data bus HPC bank A J22 FMC HA N22 AN22 2 5 V CMOS FMC data bus HPC bank A K23 FMC HA N23 AN24 2 5 V CMOS FMC data bus HPC bank A FMC HA 16 2 5 V CMOS FMC data bus bank A 2 FMC HA 1 AF16 2 5 V CMOS FMC data bus HPC bank A K7 FMC HA P2 AV16 2 5 V CMOS FMC data bus HPC bank A J6 FMC HA P3 AP17 2 5 V CMOS FMC data bus HPC bank A F7 FMC HA P4 AK10 2 5 V CMOS FMC data bus HPC bank A E6 FMC P5 AL11 2 5 V CMOS FMC data bus HPC bank A K10 FMC HA P6 J8
58. DR3A DQ35 C27 1 5 V SSTL Class Data bus byte lane H3 DDR3A DQ36 M27 1 5 V SSTL Class Data bus byte lane H8 DDR3A DQ37 H27 1 5 V SSTL Class Data bus byte lane G2 DDR3A DQ38 N27 1 5 V SSTL Class Data bus byte lane H7 DDR3A DQ39 K27 1 5 V SSTL Class Data bus byte lane 07 DDR3A 0040 426 1 5 V SSTL Class Data bus byte lane C3 DDR3A 0041 D26 1 5 V SSTL Class Data bus byte lane C8 DDR3A DQ42 K25 1 5 V SSTL Class Data bus byte lane C2 DDR3A DQ43 G26 1 5 V SSTL Class Data bus byte lane DDR3A 0044 T27 1 5 V SSTL Class Data bus byte lane A2 DDR3A DQ45 F26 1 5 V SSTL Class Data bus byte lane B8 DDR3A DQ46 R26 1 5 V SSTL Class Data bus byte lane A3 DDR3A DQ47 C26 1 5 V SSTL Class Data bus byte lane G3 DDR3A DQS 4 T28 1 5 V SSTL Class Data strobe N byte lane B7 DDR3A DQS N5 N26 1 5 V SSTL Class Data strobe N byte lane F3 DDR3A DQS P4 R28 1 5 V SSTL Class Data strobe P byte lane C7 DDR3A DQS P5 M26 1 5 V SSTL Class Data strobe P byte lane December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 58 Chapter 2 Board Components Table 2 31 DDR3A Devices Pin Assignments Schematic Signal Names and Functions Part 4 of 5 Memory Board Reference erasa ET 1 0 Standard Description L8 DDR3A 2003 1 5 V SSTL Class
59. DS input from the installed HSMC cable or HSMB CLK IN N1 LVDS LVTTL AL33 board Can also support 2x LVTTL inputs December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 26 Table 2 12 Off Board Clock Inputs Chapter 2 Board Components Clock Circuitry Arria V GT Source ir 1 0 Standard FPGA Pin Description Number USMC HSMB_CLK_IN_P2 LVDS LVTTL AU32 LVDS input from the installed HSMC cable or HSMB CLK IN N2 LVDS LVTTL AT32 board Can also support 2x LVTTL inputs PCIE REFCLK P LVDS LVTTL AG32 LVDS input from the PCI Express edge connector Edge PCIE REFCLK N HCSL AG33 REFCLK LVDS AB9 REFCLK PI LVDS V9 LVDS input from the FMC board drives two FMC REFCLK NO LVDS AB8 REFCLKs on FPGA 2 FMC REFCLK N1 LVDS V8 FMC gt gt 1420 PO LVDS AV19 FMC CLK M2C P1 LVDS AF21 LVDS input from the FMC board FMC CLK M2C LVDS AU19 FMC CLK M2C LVDS 21 Table 2 13 lists the clock outputs for the development board Table 2 13 Off Board Clock Outputs ne Arria V GT Source Schematic Signal yo Standard FPGA Pin Description Number HSMC HSMA CLK OUTO 2 5V CMOS AL14 FPGA CMOS output or GPIO HSMC HSMA CLK OUT P1 LVDS 2 5V CMOS AU13 LVDS output Can also support 2x CMOS CLK OUT N
60. Development Board Components Part 3 of 4 Board Reference Type Description Programmable oscillator with default frequencies of CLKO 125 MHz CLK1 100 MHz CLK2 156 25 MHz CLK3 125 MHz at 12C address U52 73 HEX The frequency is programmable using the clock GUI with the default MAX CPLD EPM2210 System Controller design programmed into the MAX II EPM2210 Programmable oscillator with default frequencies of CLK0 625 MHz CLK1 100 MHz CLK2 625 MHz CLK3 125 MHz at I C address U34 72 frequency is programmable using the clock GUI with the default MAX CPLD EPM2210 System Controller design programmed into the MAX II EPM2210 X1 125 MHz oscillator 125 000 MHz crystal oscillator for general purpose logic to FPGA 1 X4 125 MHz oscillator 125 000 MHz crystal oscillator for general purpose logic to FPGA 2 Programmable oscillator for SDI or REFCLKORP N with default YO Si571 programmable frequencies at 12C address 55 HEX The frequency is programmable Oscillator 148 5 MHz default using the clock GUI with the default MAX EPM2210 System Controller design programmed into the MAX EPM2210 X7 or J17 and J18 to U56 buffer X6 to U51 1 3 zero delay clock buffer Programmable oscillator 100 MHz default 50 000 MHz crystal oscillator for general purpose logic Three outputs 50 MHz oscillator Programmable oscillator with a default frequency of 100 00 MHz The frequency is programmable using the clo
61. EL4 U6 2 5 V FPGA 2 mode select 4 FPGA2 NCONFIG M2 2 5 V FPGA 2 configuration active FPGA2 NSTATUS M6 2 5 V FPGA 2 configuration ready FPGA2 PR DONE B16 2 5 V FPGA 2 partial reconfiguration done FPGA2 PR ERROR D14 2 5 V FPGA 2 partial reconfiguration error FPGA2 PR READY A17 2 5 V FPGA 2 partial reconfiguration ready FPGA2 PR REQUEST E13 2 5 V FPGA 2 partial reconfiguration request FPGA DCLK N2 2 5 V FPGA configuration clock HSMA PRSNTN A14 2 5 V HSMC port A present HSMB PRSNTN E11 2 5 V HSMC port B present INIT DONE1 T6 2 5 V FPGA initialization done INIT DONE2 V4 2 5 V FPGA initialization done JTAG EPM2210 TDI M7 2 5 V CPLD on board JTAG chain data in JTAG BLASTER TDI N6 2 5 V II CPLD on board JTAG chain data out JTAG TCK R4 2 5 V JTAG chain clock JTAG TMS P5 2 5 V JTAG mode select M570 CLOCK 10 1 8 V 2 on board USB Blaster for sending 09 1 8 V Low signal to disable the on board USB Blaster II when the Express acts as master to the JTAG chain MAX BENO B11 2 5 V FM bus MAX II byte enable 0 MAX BENI C10 2 5 V FM bus MAX II byte enable 1 MAX BEN2 A11 2 5 V FM bus MAX II byte enable 2 MAX BEN3 C9 2 5 V FM bus MAX II byte enable 3 MAX CLK J18 1 8 FM bus II clock MAX CSN J17 1 8 V FM bus MAX II chip select MAX OEN J15 1 8 V FM bus MAX II output enable MAX WEN J14 1 8 FM bus II write enable CONF DONEl B3 2 5 V FPGA configuration done LED MAX CTLO E10 2 5 V FPGA 1 to MAX op
62. EX SCC 01 U6 U11 U12 U18 A MT41J128M16HA 019 21 32Mx16x8 2 Gb DDR3 memory Micron 125 www micron com U22 U28 U7 16Mx8x8 1 Gb DDR3 memory Micron MT41J128M8JP 125 G www micron com QDRII SRAM 72 Mb 4 word burst Renesas U8 2Mx36 533 MHz Technology Corp R10DA7236ABG 19 80 www am renesas com U4 1 Gb synchronous flash Numonyx PC28F512P30BF www numonyx com U29 U31 8 channel differential 24 bit Linear Technology LTC2418CGNZPBF www linear com Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table lists the revision history for this document Date Version Changes December 2014 1 2 Corrected FPGA pin numbers for user defined LEDs for FPGA 1 Table 2 16 May 2013 1 1 Revised the FPGA core voltage to 1 15 V in Figure 2 12 and Table 2 36 November 2012 1 0 Initial release How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact 7 Contact Method Address Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com
63. MOS bit 28 84 HSMB RX D P6 AH30 LVDS or 2 5 V LVDS RX bit 6 or CMOS bit 29 85 HSMB TX D N6 AK32 LVDS or 2 5 V LVDS TX bit 6n or CMOS bit 30 86 HSMB RX D N6 AG30 LVDS or 2 5 V LVDS RX bit 6n or CMOS bit 31 89 HSMB TX D P7 AM31 LVDS or 2 5 V LVDS TX bit 7 or CMOS bit 32 90 HSMB RX D P7 AP29 LVDS or 2 5 V LVDS RX bit 7 or CMOS bit 33 91 HSMB TX D N7 AL31 LVDS or 2 5 V LVDS TX bit 7n or CMOS bit 34 92 HSMB RX D N7 AN29 LVDS or 2 5 V LVDS RX bit 7n or CMOS bit 35 95 OUT P1 AM34 LVDS or 2 5 V LVDS or CMOS clock out 1 or CMOS bit 36 96 HSMB IN PI AM33 LVDS or 2 5 V LVDS or CMOS clock in 1 or CMOS bit 37 97 HSMB CLK OUT NI AL34 LVDS or 2 5 V LVDS or CMOS clock out 1 or CMOS bit 38 98 HSMB CLK IN N1 AL33 LVDS or 2 5 V LVDS or CMOS clock in 1 or CMOS bit 39 101 HSMB TX D P8 AN27 LVDS or 2 5 V LVDS TX bit 8 or CMOS bit 40 102 HSMB RX D P8 AU29 LVDS or 2 5 V LVDS RX bit 8 or CMOS bit 41 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 44 Chapter 2 Board Components Components and Interfaces Tahle 2 27 HSMC Port B Pin Assignments Schematic Signal Names and Functions Part 3 of 4 Baard EA 1 0 Standard Description Reference J2 Schematic Signal Name Pin Number p 103 HSMB TX D N8 AM27 LVDS or 2 5 V LVDS TX bit 8n or CMOS bit
64. N26 1 5 V SSTL Class Data strobe N byte lane F3 DDR3B DQS P2 R28 1 5 V SSTL Class Data strobe P byte lane C7 DDR3B DQS P3 M26 1 5 V SSTL Class Data strobe P byte lane Table 2 33 lists the DDR3C x64 soft controller pin assignments signal names and functions The signal names and types are relative to the Arria V GT FPGA in terms of I O setting and direction Table 2 33 0083 x64 Devices Pin Assignments Schematic Signal Names and Functions Part 1 of 3 Board Reference P ms ges 1 0 Standard Description DDR3C U19 U22 N3 DDR3B A0 B31 1 5 V SSTL Class Address bus P7 DDR3B 11 A30 1 5 V SSTL Class Address bus P3 DDR3B A2 A31 1 5 V SSTL Class Address bus N2 DDR3B A3 A32 1 5 V SSTL Class Address bus P8 DDR3B A4 A33 1 5 V SSTL Class Address bus P2 DDR3B 5 B33 1 5 V SSTL Class Address bus R8 DDR3B A6 H31 1 5 V SSTL Class Address bus R2 DDR3B A7 J31 1 5 V SSTL Class Address bus T8 DDR3B A8 C31 1 5 V SSTL Class Address bus R3 DDR3B A9 D31 1 5 V SSTL Class Address bus December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 62 Chapter 2 Board Components Table 2 33 DDR3 x64 Devices Pin Assignments Schematic Signal Names and Functions Part 2 of 3 Memory
65. NI AV4 LVDS or 2 5 V LVDS or CMOS clock in 1 or CMOS bit 39 101 HSMA TX D P8 AL8 LVDS or 2 5 V LVDS TX bit 8 or CMOS bit 40 102 HSMA RX D P8 AW11 LVDS or 2 5 V LVDS RX bit 8 or CMOS bit 41 103 HSMA TX D N8 AK8 LVDS or 2 5 V LVDS TX bit 8n or CMOS bit 42 104 HSMA RX D N8 AW10 LVDS or 2 5 V LVDS RX bit 8n or CMOS bit 43 107 HSMA TX D P9 AK10 LVDS or 2 5 V LVDS TX bit 9 or CMOS bit 44 108 HSMA RX D P9 AR10 LVDS or 2 5 V LVDS RX bit 9 or CMOS bit 45 109 HSMA TX D N9 AK9 LVDS or 2 5 V LVDS TX bit 9n or CMOS bit 46 110 HSMA RX D N9 AP10 LVDS or 2 5 V LVDS RX bit 9n or CMOS bit 47 113 HSMA TX D P10 AL11 LVDS or 2 5 V LVDS TX bit 10 or CMOS bit 48 114 HSMA RX D P10 AM10 LVDS or 2 5 V LVDS RX bit 10 or CMOS bit 49 115 HSMA TX D N10 AK11 LVDS or 2 5 V LVDS TX bit 10n or CMOS bit 50 116 HSMA RX D N10 AL10 LVDS or 2 5 V LVDS RX bit 10n or CMOS bit 51 119 HSMA TX D 11 AL12 LVDS or 2 5 V LVDS TX bit 11 or CMOS bit 52 120 HSMA RX D P11 AJ13 LVDS or 2 5 V LVDS RX bit 11 or CMOS bit 53 121 HSMA TX D N11 AK12 LVDS or 2 5 V LVDS TX bit 11n or CMOS bit 54 122 HSMA RX D N11 AH13 LVDS or 2 5 V LVDS RX bit 11n or CMOS bit 55 125 HSMA TX D P12 AM13 LVDS or 2 5 V LVDS TX bit 12 or CMOS bit 56 126 HSMA RX D P12 AH11 LVDS or 2 5 V LVDS RX bit 12 or CMOS bit 57 127 HSMA TX D N12 AL13 LVDS or 2 5 V LVDS TX bit 12n or CMOS bit 58 128 HSMA RX D N12 AG11 LVDS or 2 5 V LVDS RX bit 12n or CMOS bit 59 131 HSMA TX D P13 AE12 LVDS or 2 5 V LVDS T
66. P3 AL37 1 4 V PCML Transmit bus A35 PCIE TX CP4 AG37 1 4 V PCML Transmit bus A39 PCIE TX CP5 AE37 1 4 V PCML Transmit bus A43 PCIE TX CP6 AC37 1 4 V PCML Transmit bus A47 PCIE TX CP7 AA37 1 4 V PCML Transmit bus 11 PCIE R AL16 1 4 V PCML Wake signal December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 36 10 100 1000 Ethernet This development board supports 10 100 1000 base T Ethernet using an external Marvell 88E1111 PHY and Altera Triple Speed Ethernet MegaCore MAC function The PHY to MAC interface employs RGMII using the Arria V GT FPGA LVDS pins in Soft CDR mode at 1 25 Gbps transmit and receive In 10 Mb or 100 Mb mode the RGMII interface still runs at 1 25 GHz but the packet data is repeated 10 or 100 times The MAC function must be provided in the FPGA for typical networking applications Chapter 2 Board Components Components and Interfaces The Marvell 88E1111 PHY uses 2 5 V and 1 0 V power rails and requires a 25 MHz reference clock driven from a dedicated oscillator The PHY interfaces to a HALO HFJ11 1G02E model RJ45 with internal magnetics that can be used for driving copper lines with Ethernet traffic Figure 2 9 shows the RGMII interface between the FPGA MAC and Marvell 88E1111 PHY Figure 2 9 RGMII Interface between FPGA MAC and Marvell 88E1111 PHY
67. S Y lt lt 1 5 lt zz s og 8 125 MHz Pos v 100 MHz oo 8 us YY Y Y T REFCLK1A 010 P N 125 MHz PCIe 010 _ REFCLKO A QRO PIN 48 cua 125 MH PCIE REF CLK P N 620 z uo 125 MHz B3 625 MHz 95300 15625 REFCLK3_A_QL1_P N 25 MHz gt LA QLI PIN _ 100 Sis388 SFP REFCLK2_A_QR1_P N 825 MHz lt C2C HSMA gt REFCLK2 A QL1 P N xi REFCLK4 A QR2 P N gt REFCLK4 QL2 PIN QL QR2 lt HSMA a SFP ZE 025 J16 7 Lge Clock Buffer Bullseye S gt 12 156 25 MHz Connector c a lt lt a 775 A 100 MHz 100 MHz 125 MHz 125MHz B eal 2 8 50 2 x m z E o o o di Ie 1 U53 801 148 5 M 148 35 oon 100 MHz x x Si571 o o 148 5 MHz vus Y Y Y Y Default vas REFCLK1 B QLO PIN 4 REFCLKO QRO P N CLK3 125 MHz 010 5 501 128MHz 625 MHz REFCLKO QLO PJ 4 It REFCLK1 8 080 P N HSMB 501 156 25 MHz Si5388 400 MHz eue REFCLK2 0 PIN m Si5388 COO T REFCLK2_B_QR1 PIN lt OM 625 MHz 20 QL1 4 FMC 125 MH 2 CLKO B8 B7 REFCLK4 B QL2 P N REFCLK3 B QR2 P N gt B QL2 PN
68. SMA D2 AV13 2 5 V CMOS Dedicated CMOS 1 0 bit 2 44 HSMA D3 AW13 2 5 V CMOS Dedicated CMOS 1 0 bit 3 47 HSMA TX D PO AV6 LVDS or 2 5 V LVDS TX bit 0 or CMOS bit 4 48 HSMA RX D PO AW12 LVDS or 2 5 V LVDS RX bit 0 or CMOS bit 5 49 HSMA TX D NO AW LVDS or 2 5 V LVDS TX bit On or CMOS bit 6 50 HSMA RX D NO AV12 LVDS or 2 5 V LVDS RX bit On or CMOS bit 7 53 HSMA TX D P1 AUG LVDS or 2 5 V LVDS TX bit 1 or CMOS bit 8 54 HSMA RX D P1 AR18 LVDS or 2 5 V LVDS RX bit 1 or CMOS bit 9 95 HSMA TX D NI AT6 LVDS or 2 5 V LVDS TX bit 1n or CMOS bit 10 56 HSMA D NI AP18 LVDS or 2 5 V LVDS RX bit 1n or CMOS bit 11 59 HSMA TX D P2 AUS LVDS or 2 5 V LVDS TX bit 2 or CMOS bit 12 60 HSMA RX D P2 AU8 LVDS or 2 5 V LVDS RX bit 2 or CM0S bit 13 61 HSMA TX D N2 AT9 LVDS or 2 5 V LVDS TX bit 2n or CMOS bit 14 62 HSMA RX D N2 AU LVDS or 2 5 V LVDS RX bit 2n or CMOS bit 15 65 HSMA TX D P3 AV10 LVDS or 2 5 V LVDS TX bit 3 or CMOS bit 16 66 HSMA RX D P3 AW8 LVDS or 2 5 V LVDS RX bit 3 or CMOS bit 17 67 HSMA TX D N3 AU10 LVDS or 2 5 V LVDS TX bit 3n or CMOS bit 18 68 HSMA RX D N3 AW7 LVDS or 2 5 V LVDS RX bit 3n or CMOS bit 19 71 HSMA TX D P4 AU12 LVDS or 2 5 V LVDS TX bit 4 or CMOS bit 20 72 HSMA D P4 AW9 LVDS or 2 5 V LVDS RX bit 4 or CMOS bit 21 73 HSMA TX D N4 AT12 LVDS or 2 5 V LVDS TX bit 4n or CMOS bit 22 74 HSMA RX D AV9 LVDS or 2 5 V LVDS RX bit 4n or CMOS bit 23 77 HSMA TX D P5 AP9 LVDS or 2 5 V LVDS TX bit 5 or CMOS
69. STL Class Data strobe N byte lane F3 DDR3A DQS L33 1 5 V SSTL Class Data strobe P byte lane C7 DDR3A PI N30 1 5 V SSTL Class Data strobe P byte lane L8 DDR3A 2001 1 5 V SSTL Class ZQ impedance calibration DDR3B C for FPGA 2 The development board supports a 16Mx64x8 bank DDR3 SDRAM interface on FPGA 2 for very high speed sequential memory access The 64 bit data bus consists of four x16 devices with a single address or command bus This interface connects to the vertical I O banks on the top edge of the FPGA This DDR3 SDRAM has two interface options The first option is a x32 interface using a memory hard controller The second option is a x64 interface using a memory soft controller Table 2 32 lists the DDR3B x32 hard controller pin assignments signal names and functions The signal names and types are relative to the Arria V GT FPGA in terms of I O setting and direction Table 2 32 DDR3 x32 Devices Pin Assignments Schematic Signal Names and Functions Part 1 of 3 Board Reference b ga 1 0 Standard Description DDR3B U6 U12 N3 DDR3B A0 B31 1 5 V SSTL Class Address bus P7 DDR3B A1 A30 1 5 V SSTL Class Address bus P3 DDR3B A2 A31 1 5 V SSTL Class Address bus N2 DDR3B A3 A32 1 5 V SSTL Class Address bus P8 DDR3B A4 A33 1 5 V SSTL Class Address bus P2 DDR3B A5 B33 1 5 V SSTL Class Address bus R8 DDR
70. V SSTL Class Address bus L2 DDR3A A5 G32 1 5 V SSTL Class Address bus M8 DDR3A_A6 R21 1 5 V SSTL Class Address bus December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 56 Chapter 2 Board Components Memory Table 2 31 DDR3A Devices Pin Assignments Schematic Signal Names and Functions Part 2 of 5 Board Reference siyasi n 1 0 Standard Description M2 DDR3A A7 K30 1 5 V SSTL Class Address bus N8 DDR3A A8 021 1 5 V SSTL Class Address bus M3 DDR3A A9 M30 1 5 V SSTL Class Address bus H7 DDR3A A10 J28 1 5 V SSTL Class Address bus M7 DDR3A A11 M21 1 5 V SSTL Class Address bus K7 DDR3A A12 G28 1 5 V SSTL Class Address bus N3 DDR3A A13 M31 1 5 V SSTL Class Address bus J2 DDR3A_BAO G30 1 5 V SSTL Class Bank address bus K8 DDR3A T24 1 5 V SSTL Class Bank address bus J3 DDR3A BA2 K34 1 5 V SSTL Class Bank address bus G3 DDR3A_CASN D32 1 5 V SSTL Class Row address select G9 DDR3A_CKE K29 1 5 V SSTL Class Column address select G7 DDR3A CLK N F34 1 5 V SSTL Class Differential output clock F7 DDR3A CLK P E34 1 5 V SSTL Class Differential output clock H2 DDR3A CSN F31 1 5 V SSTL Class Chip select B7 DDR3A DM8 P22 1 5 V SSTL Class Write mask byte lane B3 DDR3A DQ64 B22 1 5 V SSTL Class Data
71. VDS or 2 5 V LVDS TX bit 14 or CMOS bit 64 138 HSMB RX D P14 AT31 LVDS or 2 5 V LVDS RX bit 14 or CMOS bit 65 139 HSMB TX D N14 AN31 LVDS or 2 5 V LVDS TX bit 14n or CMOS bit 66 140 HSMB RX D N14 AR31 LVDS or 2 5 V LVDS RX bit 14n or CMOS bit 67 143 HSMB TX D 15 AP32 LVDS or 2 5 V LVDS TX bit 15 or CMOS bit 68 144 HSMB RX D 15 AV28 LVDS 2 5 V LVDS RX bit 15 or CMOS bit 69 145 HSMB TX D N15 AN32 LVDS or 2 5 V LVDS TX bit 15n or CMOS bit 70 146 HSMB RX D N15 AU28 LVDS or 2 5 V LVDS RX bit 15n or CMOS bit 71 149 HSMB TX D 16 AP33 LVDS or 2 5 V LVDS TX bit 16 or CMOS bit 72 150 HSMB RX D P16 AT30 LVDS or 2 5 V LVDS RX bit 16 or CMOS bit 73 151 HSMB TX D N16 AN33 LVDS or 2 5 V LVDS TX bit 16n or CMOS bit 74 152 HSMB RX D N16 AR30 LVDS or 2 5 V LVDS RX bit 16n or CMOS bit 75 155 HSMB CLK OUT P2 AE26 LVDS or 2 5 V LVDS or CMOS clock out 2 or CMOS bit 76 156 HSMB IN P2 AU32 LVDS or 2 5 V LVDS or CMOS clock in 2 or CMOS bit 77 157 HSMB CLK OUT N2 AD26 LVDS or 2 5 V LVDS or CMOS clock out 2 or CMOS bit 78 Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components 2 45 Components and Interfaces Table 2 27 HSMC Port B Pin Assignments Schematic Signal Names and Functions Part 4 of 4 Paang AROA VO Standard D T tandar escription Reference J2 Schematic Signal Name Pin Number 158 HSMB CLK N2 AT32 LVDS or 2 5 V LVDS or 5 cl
72. X bit 13 or CMOS bit 60 132 HSMA RX D P13 AG12 LVDS or 2 5 V LVDS RX bit 13 or CMOS bit 61 133 HSMA TX D N13 AD12 LVDS or 2 5 V LVDS TX bit 13n or CMOS bit 62 134 HSMA RX D N13 AF12 LVDS or 2 5 V LVDS RX bit 13n or CMOS bit 63 137 HSMA TX D 14 AD11 LVDS or 2 5 V LVDS TX bit 14 or CMOS bit 64 138 HSMA RX D P14 AD13 LVDS or 2 5 V LVDS RX bit 14 or CMOS bit 65 139 HSMA TX D N14 AC12 LVDS or 2 5 V LVDS TX bit 14n or CMOS bit 66 140 HSMA RX D N14 AC13 LVDS or 2 5 V LVDS RX bit 14n or CMOS bit 67 143 HSMA TX D 15 AR13 LVDS or 2 5 V LVDS TX bit 15 or CMOS bit 68 144 HSMA D P15 AE13 LVDS or 2 5 V LVDS RX bit 15 or CMOS bit 69 145 HSMA TX D N15 AP13 LVDS or 2 5 V LVDS TX bit 15n or CMOS bit 70 146 HSMA RX D N15 AE14 LVDS or 2 5 V LVDS RX bit 15n or CMOS bit 71 149 HSMA TX D 16 AJ12 LVDS or 2 5 V LVDS TX bit 16 or CMOS bit 72 150 HSMA D P16 AG13 LVDS or 2 5 V LVDS RX bit 16 or CMOS bit 73 151 HSMA TX D N16 AH12 LVDS or 2 5 V LVDS TX bit 16n or CMOS bit 74 152 HSMA RX D N16 AF13 LVDS or 2 5 V LVDS RX bit 16n or CMOS bit 75 155 HSMA CLK OUT P2 LVDS or 2 5 V LVDS or CMOS clock out 2 or CMOS bit 76 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 42 Chapter 2 Board Components Components and Interfaces Table 2 26 HSMC Port A Pin Assignments Schematic Signal Names and Functions Part 5 of 5 Board v Reference J1 Sche
73. ZQ impedance calibration DDR3A U21 E7 DDR3A DM2 M32 1 5 V SSTL Class Write mask byte lane D3 DDR3A DM3 D31 1 5 V SSTL Class Write mask byte lane DDR3A DQ16 D30 1 5 V SSTL Class Data bus byte lane F DDR3A DQ17 C29 1 5 V SSTL Class Data bus byte lane F2 DDR3A DQ18 R30 1 5 V SSTL Class Data bus byte lane F8 DDR3A 0019 A29 1 5 V SSTL Class Data bus byte lane H3 DDR3A DQ20 L30 1 5 V SSTL Class Data bus byte lane H8 DDR3A DQ21 A28 1 5 V SSTL Class Data bus byte lane G2 DDR3A DQ22 J30 1 5 V SSTL Class Data bus byte lane H7 DDR3A DQ23 B28 1 5 V SSTL Class Data bus byte lane 07 DDR3A 0024 J29 1 5 V SSTL Class Data bus byte lane C3 DDR3A DQ25 C28 1 5 V SSTL Class Data bus byte lane C8 DDR3A DQ26 L28 1 5 V SSTL Class Data bus byte lane C2 DDR3A DQ27 F28 1 5 V SSTL Class Data bus byte lane AT DDR3A DQ28 N29 1 5 V SSTL Class Data bus byte lane A2 DDR3A DQ29 D28 1 5 V SSTL Class Data bus byte lane B8 DDR3A DQ30 M29 1 5 V SSTL Class Data bus byte lane A3 DDR3A DQ31 M28 1 5 V SSTL Class Data bus byte lane G3 DDR3A DQS N2 P30 1 5 V SSTL Class Data strobe N byte lane B7 DDR3A DQS N3 T29 1 5 V SSTL Class Data strobe N byte lane F3 DDR3A DQS P2 N30 1 5 V SSTL Class Data strobe P byte lane C7 DDR3A DQS P3 R29 1 5 V SSTL Class Data strobe P byte lane L8 DDR3A ZQ01 1 5 V SSTL Class ZQ impedance calibration DDR3A U28 E7 DDR3A 1140 M32 1 5 V SSTL C
74. a website where you can sign up to receive update notifications for Altera documents The feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation
75. a bus C2 QDRII Q28 AT20 1 8 V HSTL Read data bus 51 QDRII 029 020 1 8 V HSTL Read data bus Fi QDRII Q30 21 1 8 V HSTL Read data bus J2 QDRII Q31 AU19 1 8 V HSTL Read data bus K1 QDRII Q32 AV19 1 8 V HSTL Read data bus L1 QDRII Q33 AN21 1 8 V HSTL Read data bus M2 QDRII Q34 21 1 8 VHSTL Read data bus P1 QDRII Q35 21 1 8 V HSTL Read data bus A8 QDRII RPSN AR25 1 8 V HSTL Read port select A4 QDRII WPSN AK24 1 8 V HSTL Write port select December 2014 Altera Corporation Chapter 2 Board Components 2 67 Memory Flash The development board supports a 1 Gb CFI compatible synchronous flash device for non volatile storage of FPGA configuration data board information test application data and user code space This device is part of the shared FM bus that connects to the flash memory and MAX II CPLD EPM2210 System Controller This 16 bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps The write performance is 270 us for a single word while the erase time is 800 ms for a 128 K main block Table 2 35 lists the flash pin assignments signal names and functions The signal names and types are relative to the Arria V GT FPGA in terms of I O setting and direction Table 2 35 Flash Pin Assignments Schematic Signal Names and Functions Part 1 of 2 Reference U
76. back from PCI Express TDI to PCI Express TDO and are not used on this board The SMB signals are wired to the Arria V GT FPGA but are not required for normal operation Table 2 24 summarizes the PCI Express pin assignments The signal names and directions are relative to the Arria V GT FPGA Table 2 24 PCI Express Pin Assignments Schematic Signal Names and Functions B J4 Schematic Signal Name a an 1 0 Standard Description A5 PCIE JTAG TCK 1 4 V PCML JTAG chain clock A6 PCIE JTAG TDI 1 4 V PCML JTAG chain data in 7 PCIE JTAG 1 4 V PCML JTAG chain data out A8 PCIE JTAG TMS 1 4 V PCML JTAG chain mode select A11 PCIE PERSTN N9 1 4 V PCML Presence detect DIP switch A1 PCIE PRSNTIN 1 4 V PCML Presence detect DIP switch B17 PCIE PRSNT2N X1 1 4 V PCML Presence detect DIP switch B31 PCIE PRSNT2N X4 1 4 V PCML Presence detect DIP switch B48 PCIE PRSNT2N X8 1 4 V PCML Presence detect DIP switch A14 PCIE REFCLK N AG33 1 4 V PCML Motherboard reference clock A13 PCIE REFCLK P AG32 1 4 V PCML Motherboard reference clock B15 PCIE RX NO AW36 1 4 V PCML Receive bus Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual Chapter 2 Board Components 2 35 Components and Interfaces Table 2 24 PCI Express Pin Assignments Schematic Signal Names and Functions
77. bit 24 78 HSMA RX D P5 AU11 LVDS or 2 5 V LVDS RX bit 5 or CMOS bit 25 79 HSMA TX D N5 AN9 LVDS or 2 5 V LVDS TX bit 5n or CMOS bit 26 80 HSMA RX D N5 AT11 LVDS or 2 5 V LVDS RX bit 5n or CMOS bit 27 83 HSMA TX D P6 AP12 LVDS or 2 5 V LVDS TX bit 6 or CMOS bit 28 84 HSMA RX D P6 ARQ LVDS or 2 5 V LVDS RX bit 6 or CMOS bit 29 85 HSMA TX D_N6 AN12 LVDS or 2 5 V LVDS TX bit 6n or CMOS bit 30 86 HSMA RX D_N6 AT8 LVDS or 2 5 V LVDS RX bit 6n or CM0S bit 31 89 HSMA TX D P7 9 LVDS or 2 5 V LVDS TX bit 7 or CMOS bit 32 90 HSMA RX D P7 5 LVDS or 2 5 V LVDS RX bit 7 or CMOS bit 33 91 HSMA TX D N7 AL9 LVDS or 2 5 V LVDS TX bit 7n or CMOS bit 34 92 HSMA RX D N7 AW6 LVDS or 2 5 V LVDS RX bit 7n or CMOS bit 35 95 HSMA CLK OUT P1 AU13 LVDS or 2 5 V LVDS or CMOS clock out 1 or CMOS bit 36 96 HSMA CLK IN P1 AW4 LVDS or 2 5 V LVDS or CMOS clock in 1 or CMOS bit 37 97 HSMA CLK OUT N1 AT13 LVDS or 2 5 V LVDS or CMOS clock out 1 or CMOS bit 38 Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Components and Interfaces 2 41 Table 2 26 HSMC Port A Pin Assignments Schematic Signal Names and Functions Part 4 of 5 Board 2 Reference J1 Schematic Signal Name PR 1 0 Standard Description 98 HSMA
78. ck GUI with the default MAX II CPLD EPM2210 System Controller design programmed into the MAX II EPM2210 Multiplex with CLKIN SMA P N based CLK SEL switch value connect to the FPGA 1 FPGA 2 and MAX II devices J17 J18 Clock input SMAs Drive LVPECL compatible clock inputs into the clock multiplexer buffer U56 General User Input Output SW2 FPGA 1 user DIP switch Octal user DIP switches When the switch is ON a logic 0 is selected SW3 FPGA 2 user DIP switch Octal user DIP switches When the switch is ON a logic 0 is selected 1 reset push button Resets the MAX II CPLD EPM2210 System Controller 54 FPGA 1 CPU reset push button Resets the FPGA 1 logic S8 FPGA 2 CPU reset push button Resets the FPGA 2 logic 55 57 FPGA 1 general user push Three user push buttons Driven low when pressed buttons 59 511 diua general user push Three user push buttons Driven low when pressed D18 D25 FPGA 1 user LEDs Eight bi color user LEDs Illuminates when driven low D26 D33 FPGA 2 user LEDs Eight bi color user LEDs Illuminates when driven low D35 FPGA 1 LED LED indicator for FPGA 1 D32 FPGA 2 LED LED indicator for FPGA 2 Memory Devices U4 Flash x16 memory Synchronous burst mode flash device that provides a 16 bit 125 MB non volatile memory port Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Compone
79. ctions Follow the color code to make loopback connections For example connect purple to purple pins 17 to 21 for RX to TX loopback The only pins not connected are pins 3 and 4 Figure 2 11 Bull s Eye Connections 5 You can order more cables from www samtec com and these cable systems can be reused on other boards For specific instructions on how to install the connector to the board and insert the cables into the connector refer to Samtec s web page regarding this system Table 2 30 lists the Bull s eye connector pin assignments signal names and functions Table 2 30 Bull s Eye Connector Pin Assignments Schematic Signal Names and Functions Men J16 Schematic Signal Name lie eta 1 0 Standard Description 4 BULLSEYE SMA CLKN LVDS or 2 5 V Clock buffer 3 BULLSEYE SMA CLKP LVDS or 2 5 V Clock buffer 21 SMA A 10G RX NO G2 LVDS or 2 5 V Transceiver channel 2 SMA 10G RX NI H38 LVDS or 2 5 V Transceiver channel 22 SMA A 10G G1 LVDS or 2 5 V Transceiver channel 1 SMA 106 RX H39 LVDS or 2 5 V Transceiver channel 7 SMA A 6G N2 C2 LVDS or 2 5 V Transceiver channel 11 SMA A 6G RX P2 C1 LVDS or 2 5 V Transceiver channel 13 SMA A TX L15 N G36 LVDS or 2 5 V Transceiver channel 12 SMA A TX L15 P G37 LVDS or 2 5 V Transceiver channel 17 SMA A TX R16 F4 LVDS or 2 5 V Transceiver channel 18 SMA
80. des a 10 100 1000 Ethernet connection J8 Gigabit Ethernet via a Marvell 88E1111 PHY and the FPGA based Altera Triple Speed Ethernet MegaCore function in RGMII mode Display Ports Connector which interfaces to the provided 16 character x 2 line LCD ic POIG Or module along with two standoffs at MTH7 and MTH8 Power Supply Accepts a 19 V DC power supply Do not use this input jack while the J6 DC input jack board is plugged into a PCI Express slot J4 ATX power connector PCI Express auxiliary power source option Interfaces to a PCI Express root port such as an appropriate PC J30 PCI Express edge connector motharboard sw1 Switch to power or off the board when power is supplied from the DC input jack December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual Featured Device Arria V GT FPGA Chapter 2 Board Components Featured Device Arria V GT FPGA The Arria V GT FPGA development board features two Arria V GT FPGA 5AGTFD7K3F40I3N device 013 and 016 in a 1517 pin FBGA package Handbook For more information about Arria V device family refer to the Arria V Device Table 2 2 describes the features of the Arria V GT FPGA 5AGTFD7K3FAOI3N device Table 2 2 Arria V GT FPGA Features Equivalent M10K RAM ALMs LEs Blocks 190 240 504 000 24 140 Total RAM Kbits 27 046 18 bit x 18 bit Multipliers 2 312 PLLs 16 Transceivers 36
81. elect for CLK BIDIR H4 FMC CLK M2C PO AV19 2 5 V CMOS Clock input 0 H5 FMC CLK M2C NO AU19 2 5 V CMOS Clock input 0 G2 M2C PI AF21 2 5 V CMOS Clock input 1 G3 CLK M2C NI 21 2 5 V CMOS Clock input 1 C3 FMC DP C2M NO AD4 2 5 V CMOS Transmit channel A23 FMC DP C2M 111 Y4 2 5 V CMOS Transmit channel A27 FMC DP C2M N2 T4 2 5 V CMOS Transmit channel A31 FMC DP C2M N3 P4 2 5 V CMOS Transmit channel A35 FMC DP C2M 114 H4 2 5 V CMOS Transmit channel December 2014 Altera Corporation Chapter 2 Board Components Components and Interfaces 2 41 Table 2 29 FMC Connector Pin Assignments Schematic Signal Names and Functions Part 2 of 7 2 PA 1 0 Standard Description J10 Pin Number A39 FMC DP C2M N5 M4 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B37 FMC DP C2M N6 K4 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B33 FMC DP C2M N7 F4 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B29 FMC DP C2M N8 D4 2 5 V CMOS Transmit channel available in Arria V FPGA device B25 FMC DP C2M N9 B4 2 5 V CMOS Transmit channel available in Arria V GT FPGA device C2 FMC DP C2M PO AD3 2 5 V CMOS Transmit channel A22 FMC DP C2M P1 2 5 V CMOS Transmit channel A26 FMC DP C2M P2 T3 2 5 V CMOS Transmit channel A30 FMC DP C2M
82. en not in use and on when in use or idle Illuminates to show the LED sequence that determines which flash D12 D13 D14 Configuration LEDs memory image loads to the FPGA when you press the SEL push button D15 Error LED Illuminates when the FPGA configuration from flash memory fails D16 Configuration done LED when the FPGA is configured Illuminates when the MAX II CPLD EPM2210 System Controller is BU actively configuring the a A Da0 Ethernet LEDs Shows the connection speed as well as transmit or receive activity D42 D43 D44 PCI Express link LEDs You can configure these LEDs to display the PCI Express link width x1 x4 x8 Clock Circuitry Programmable oscillator with default frequencies of CLK0 125 MHz CLK1 100 MHz CLK2 625 MHz CLK3 125 MHz at I C address U48 TANE 71 HEX The frequency is programmable using the clock GUI with the default MAX CPLD EPM2210 System Controller design programmed into the MAX EPM2210 Programmable oscillator with default frequencies of CLKO 625 MHz CLK1 156 25 MHz CLK2 125 MHz CLK3 125 MHz 126 address U53 70 HEX The frequency is programmable using the clock GUI with the default MAX CPLD EPM2210 System Controller design programmed into the MAX EPM2210 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 4 Chapter 2 Board Components Board Overview Table 2 1 Arria V GT FPGA
83. en1 or 5 0 Gbps lane for a maximum of 40 Gbps full duplex Gen2 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 34 Chapter 2 Board Components Components and Interfaces The power for the board can be sourced entirely from the PCI Express edge connector when installed into a PC motherboard Although the board can also be powered by a laptop power supply for use on a lab bench Altera recommends that you do not power up from both supplies at the same time Ideal diode power sharing devices have been designed into this board to prevent damages or back current from one supply to the other The PCIE REFCLK P signalis a 100 MHz differential input that is driven from the PC motherboard on to this board through the edge connector This signal connects directly to a Arria V GT FPGA REFCLK input pin pair using DC coupling This clock is terminated on the motherboard and therefore no on board termination is required This clock can have spread spectrum properties that change its period between 9 847 ps to 10 203 ps The I O standard is High Speed Current Steering Logic HCSL Figure 2 8 shows the PCI Express reference clock levels Figure 2 8 PCI Express Reference Clock Levels VMAX 1 15 V REFCLK VCROSS MAX 550 mV VCROSS MIN 250 mV REFCLK 0 30 V The JTAG and SMB are optional signals in the PCI Express specification Therefore the JTAG signal loop
84. ents Memory Arria V GT FPGA Development Board Reference Manual Reference UB Signal Name pin Number VO Standard 10 QDRII 01 24 1 8 VHSTL Read data bus L11 QDRII Q2 AU24 1 8 V HSTL Read data bus K11 QDRII Q3 AL24 1 8 V HSTL Read data bus J10 QDRII Q4 AE24 1 8 V HSTL Read data bus F11 QDRII Q5 AF24 1 8 V HSTL Read data bus E11 QDRII Q6 AH24 1 8 V HSTL Read data bus C10 QDRII Q7 AW23 1 8 HSTL Read data bus 811 QDRII Q8 AW24 1 8 V HSTL Read data bus P9 QDRII Q9 AP24 1 8 V HSTL Read data bus N9 QDRII Q10 AT23 1 8 V HSTL Read data bus L10 QDRII 011 AU23 1 8 V HSTL Read data bus K9 QDRII 012 AP23 1 8 V HSTL Read data bus G9 QDRII Q13 AD22 1 8 V HSTL Read data bus F10 QDRII Q14 AE23 1 8 V HSTL Read data bus E9 QDRII Q15 AL23 1 8 V HSTL Read data bus D9 QDRII Q16 AT22 1 8 V HSTL Read data bus B10 QDRII Q17 AU22 1 8 V HSTL Read data bus B2 QDRII Q18 AW22 1 8 V HSTL Read data bus D3 QDRII Q19 21 1 8 VHSTL Read data bus E3 QDRII Q20 AW 1 1 8 V HSTL Read data bus F2 QDRII Q21 AH23 1 8 V HSTL Read data bus G3 QDRII Q22 AE22 1 8 V HSTL Read data bus K3 QDRII Q23 AF22 1 8 V HSTL Read data bus L2 QDRII Q24 AP22 1 8 V HSTL Read data bus N3 QDRII Q25 AW19 1 8 V HSTL Read data bus P3 QDRII Q26 AW20 1 8 V HSTL Read data bus B1 QDRII Q27 AH22 1 8 V HSTL Read dat
85. er Input Output Table 2 17 lists the HSMC user defined LED schematic signal names and their corresponding Arria V GT FPGA pin numbers Table 2 17 HSMC User Defined LED Schematic Signal Names and Functions Jm mem D5 HSMA TX LED U16 AH14 2 5 04 HSMA RX LED U16 AT15 a port A D8 HSMB TX LED U13 AM28 2 5 V CUBE AN port B 07 HSMB RX LED U13 AG26 nd port B LCD The development board includes a single 14 pin 0 1 pitch dual row header that interfaces to a 16 character x 2 line Lumex LCD display The LCD has a 14 pin receptacle that mounts directly to the board s 14 pin header so it can be easily removed for access to components under the display You can also use the header for debugging or other purposes Table 2 18 summarizes the LCD pin assignments The signal names and directions are relative to the Arria V GT FPGA Table 2 18 LCD Pin Assignments Schematic Signal Names and Functions 130 Schematic Signal Name 1 0 Standard Description 7 LCD1 DATAO N20 2 5 V LCD data bus 8 LCD1 DATAI R20 2 5 V LCD data bus 9 LCD1 DATA2 T20 2 5 V LCD data bus 10 LCD1 DATA3 J20 2 5 V LCD data bus 11 LCD1 DATA4 K20 2 5 V LCD data bus 12 LCD1 DATAS J19 2 5 V LCD data bus 13 LCD1 DATA6 K19 2 5 V LCD data bus 14 LCD1 L19 2 5 V LCD data bus 4 LCDI D Cn M19 2 5 V LCD data
86. erface providing device addressing of up to a 36 Mb The QDRII has separate read and write data ports with DDR signaling at up to 550 MHz The pinout and footprint is compatible with a burst of 2 SSRAM memory device The FPGA can support up to 400 MHz ODRII data Table 2 34 lists the QDRII pin assignments signal names and functions Table 2 34 QDRII Pin Assignments Schematic Signal Names and Functions Part 1 of 3 Reference U8 Signal Name Number VO Standard Description R9 QDRII 0 AB29 1 8 V HSTL Address bus R8 QDRII A1 AC29 1 8 V HSTL Address bus B4 QDRII A2 AF28 1 8 V HSTL Address bus B8 QDRII A3 AG28 1 8 V HSTL Address bus C5 QDRII A4 AK29 1 8 V HSTL Address bus C7 QDRII A5 AL29 1 8 V HSTL Address bus N5 QDRII A6 AH28 1 8 V HSTL Address bus N6 QDRII A7 AJ28 1 8 V HSTL Address bus 7 QDRII_A8 AD28 1 8 V HSTL Address bus P4 QDRII A9 AP28 1 8 V HSTL Address bus P5 QDRII A10 AJ27 1 8 V HSTL Address bus P7 QDRII All AP27 1 8 V HSTL Address bus P8 QDRII A12 27 1 8 V HSTL Address bus R3 QDRII A13 AG27 1 8 V HSTL Address bus R4 QDRII A14 AE27 1 8 V HSTL Address bus R5 QDRII A15 AC24 1 8 V HSTL Address bus R7 QDRII A16 AD26 1 8 V HSTL Address bus A9 QDRII A17 AN26 1 8 V HSTL Address bus A3 QDRII A18 AJ25 1 8 V HSTL Address bus A10 QDRII A19 AT32 1 8 V HSTL
87. g2 com tw User defined eight position DIP C amp K Components SW2 SW3 switch ITT Industries TDA08H0SB1 www ittcannon com D18 D25 User defined bi color red and green www us liteon com opto D26 D33 LEDs Lite On index html HSMC Green LEDs Lumex Inc SML LXTO805GW TR www lumex com 2x7 pin 100 mil vertical header LCD socket strip Samtec TSM 107 01 G DV www samtec com qepa xerunt Lumex Inc LCM S01602DSR C www lumex com 3 Gbps HD SD SDI cable driver National U24 with cable detect Semiconductor LMH0303SQx www national com 3 Gbps HD SD SDI adaptive cable National 023 equalizer Semiconductor LMH0384S0 www national com PCI Express 4 20 mm pitch header J4 13 A per pin dual row right angle Molex 50 34 8571 www molex com with PCB mounting flanges 2 Marvell U14 Ethernet PHY BASE T device Samicondu tor 88E1111 B2 CAA1C000 www marvell com RJ 45 connector J8 10 100 1000 Mbps Wurth Elektronik 7499111001A www we online com HSMC custom version of QSH DP _ _ J1 J2 family high speed socket Samtec ASP 122953 01 www samtec com B2 SFP right angle press fit cage Molex 74754 0101 www molex com SFP right angle 20 pin SMT qp J10 J15 connector Samtec MECT 110 01 M D RA1 www samtec com FMC pitch socket array assembly 1 J10 Samtec ASP 134486 01 www samtec com Bull s Eye test point receptacle BAR J 22 J16 Four CCA 25M cable assemblies Samtec don Ok www samtec com Insertion Extraction tool CAT
88. gs Switch Eae bee aa ra antes 2 20 PCI Express Control DIP ker 2 21 CPU Reset Push der Ded 2 21 MAX II Reset Push Button 2 21 Configuration Push Button 2 21 Image Select Push 2 22 Clock Circuitry fe Hone kk dik ei e e AGE dde Ete qia 2 22 On Board Oscillatots er ter Dex eer pac dottore edet 2 22 Off Board Clock Input Output 2 25 General User Output uu ete dene eter pe i digits 2 27 User Defined Push 2 2 27 User Defined DIP Switches o 2 27 User Defined LEDS u e Revo eee haee r eie e ree oe a qose ao 2 28 General User Defined LEIS w eee er Peter ee ao ee x e e Re P hia 2 28 HSMC User Defined LEDS J tee Hte e ORE ORE EHE RR HR be ee oe 2 30 DEPI 2 30 SDI Video Output Input uuu y kdk ae ma Ede ee ea 2 31 Components Interfaces ego
89. guration via protocol done 1 MSELO F8 2 5 V FPGA 1 mode select 0 1 MSELI A6 2 5 V FPGA 1 mode select 1 1 MSEL2 E8 2 5 V FPGA 1 mode select 2 1 MSEL3 B7 2 5 V FPGA 1 mode select 3 1 MSEL4 D8 2 5 V FPGA 1 mode select 4 FPGA1 NCONFIG M5 2 5 V FPGA 1 configuration active FPGA1 NSTATUS N1 2 5 V FPGA 1 configuration ready FPGA1 PR DONE K4 2 5 V FPGA 1 partial reconfiguration done FPGA1 PR ERROR L5 2 5 V FPGA 1 partial reconfiguration error FPGA1 PR READY L6 2 5 V FPGA 1 partial reconfiguration ready FPGA1 PR REQUEST L2 2 5 V FPGA 1 partial reconfiguration request FPGA2 CEN K5 2 5 FPGA 2 chip enable FPGA2 CEON C11 2 5 V FPGA 2 chip output enable FPGA2 CONF DONE M3 2 5 FPGA 2 configuration done FPGA2_CVP_CONFDONE B18 2 5 V FPGA 2 configuration via protocol done FPGA2 MSELO U5 2 5 V FPGA 2 mode select 0 FPGA2 MSELI 87 2 5 V FPGA 2 mode select 1 FPGA2 MSEL2 V5 2 5 V FPGA 2 mode select 2 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 12 Chapter 2 Board Components MAX II CPLD EPM2210 System Controller Table 2 5 MAX Il CPLD EPM2210 System Controller Device Pin Out Part 4 of 5 Arria V GT FPGA Development Board Reference Manual Schematic Signal Name 1 0 Standard Description FPGA2 MSEL3 T7 2 5 V FPGA 2 mode select 3 FPGA2 MS
90. hapter 2 Board Components Featured Device Arria V GT FPGA Table 2 3 lists the Arria V GT FPGA 1 pin count and usage by function on the development board Clocks are listed under special pins as it uses dedicated I O pins Tahle 2 3 Arria V GT FPGA 1 Pin Count and Usage 2 1 Function 1 0 Standard 1 0 Count Special Pins DDR3 x72 interface 1 5 V SSTL 125 1 differential x9 differential DQS QDRII x36 interface 1 8 V HSTL 103 1 differential x36 differential 005 MAX II System Controller 1 8 V CMOS 8 Flash 1 8 V CMOS 49 PCI Express 2 5 V CMOS 10 1 reference clock HSMC port A 2 5 V CMOS LVDS 84 1 reference clock Gigabit Ethernet 2 5 V CMOS LVDS 16 On Board USB Blaster 1 5 V 2 5 V CMOS 19 SFP 2 5 V CM0S 16 2 reference clocks Chip to chip bridge 2 5 V 120 2 reference clocks Buttons 2 5 V CMOS 3 Switches 2 5 V CMOS 4 LCD 2 5 V CMOS 11 LEDs 2 5 V CMOS 16 Clocks or Oscillators 1 8 V CMOS LVDS 10 5 differential clocks 1 single ended Total 1 0 Used 625 Transceivers SMA or Bull s Eye 16 HSMC port A 32 PCI Express 32 Chip to chip bridge 32 SFP 8 Total Transceiver Used 120 Table 2 4 lists the Arria V GT FPGA 2 pin count and usage by function on the development board Clocks are listed under special pins as it uses dedicated I O pins Table 2 4 Arria V GT FPGA 2 Pin Count and
91. he currents shown which are conservative absolute maximum levels Figure 2 12 Power Distribution System 2 69 1 2V 4512A A5 VCCR GXB Power Sequencing VCCR GXB VCCL GXB R VCCNCCPIVCCR GXB VCCT GXB VCCL GXB 1225 LTM4628 Dual 84 24 6592A n 12V 2 070 A A5_VCCT GXB gt Switching Regulator BEAD VCCR GXB VCCPD CCPGMIVCCAUXIVCCA VCCA GXB 300 NEN 5V 0 2 VCCA VCCAUX VCCH_GXB VCCD_FPLL 2 AAA 2 5 V 0 704 A 5_ BEAD VCCA GXB 2 5 V 2542 A5 VCCPD PGM 10 VCCPD VCCPGM Rosense L MA 42 51 1 226 A5 VCCPD 10 FPGA VCCIO 2 5 V Banks 2 5V 25 1249A Flash VDDQ ENET VDD 2210 VCCIO2 NB6L118 6 Oscillators R LT3026 SENSE 1 5 A LDO LAW 3 R SE 18V0693A A5 VCCIO 1 8V ANN FPGA VCCIO 1 8 V Banks 1 8V 8V 1 688 LEN SOILA gt Flash QDR_VDD 12V 1 466A LTM4628 Dual 8A EPM2210 EPCQ gt Switching Regulator 1 3 1 5 V 5 864 A 5V 1 080 A A5 VCCIO 1 5V ANN FPGA VCCIO 1 5 V Bank 8 5 4794 A 1 5V gt VREF_DDR3A DDR3 VDD EZ USB 0 75 V 0
92. ign Tutorials section in volume 6 of the External Memory Interface Handbook DDR3 Arria V GT FPGA Development Board Reference Manual DDR3A for FPGA 1 The development board supports a 16Mx72x8 bank DDR3 SDRAM interface on FPGA 1 for very high speed sequential memory access The 72 bit data bus consists of four x16 devices and one x8 device with a single address or command bus This interface connects to the vertical I O banks the top edge of the FPGA and utilizes the memory soft controller This memory interface is designed to run at a target frequency of 667 MHz for a maximum theoretical bandwidth of over 115 2 Gbps The minimum frequency for this device is 667 MHz The target Micron device is rated at 800 MHz with a CAS latency of 11 December 2014 Altera Corporation Chapter 2 Board Components Memory 2 55 Table 2 31 lists the DDR3A x72 soft controller pin assignments signal names and functions The signal names and types are relative to the Arria V GT FPGA in terms of I O setting and direction Table 2 31 DDR3A Devices Pin Assignments Schematic Signal Names and Functions Part 1 of 5 Board Reference men EET 1 0 Standard Description DDR3A 011 U18 021 028 N3 DDR3A A0 M34 1 5 V SSTL Class Address bus P7 DDR3A A1 H25 1 5 V SSTL Class Address bus P3 DDR3A A2 F32 1 5 V SSTL Class
93. ion to be used as single ended I O pins The VCCIO supply for the FMC A banks in the low pin count LPC and HPC provide a variable voltage of 1 5 V 1 8 V 2 5 V default or 3 3 V The VCCIO supply for the FMC B bank in the HPC provides a variable voltage from 1 2 V to 3 3 V which can be supplied by the FMC module However for the sake of device safety concerns a jumper is available for you to connect this bank to the same VCCIO used for the FMC A banks This allows the VCCIO pins on the FPGA to be tied to a known power The VCCIO pins also allows you the option to perform a manual check for the module s input voltage before connecting to the FPGA This is to ensure that the module does not exceed the power supply maximum voltage rating Table 2 29 lists the FMC connector pin assignments signal names and functions Table 2 29 FMC Connector Pin Assignments Schematic Signal Names and Functions Part 1 of 7 Arria V GT FPGA Development Board Reference Manual eee Kou 1 0 Standard Description J10 Pin Number D1 FMC C2M PG 2 5 V CMOS Power good output K4 FMC CLK BIDIR P2 AE23 2 5 V CMOS Clock input or output 2 K5 FMC CLK BIDIR N2 AD22 2 5 V CMOS Clock input or output 2 J2 FMC CLK BIDIR P3 AU22 2 5 V CMOS Clock input or output 3 J3 FMC CLK BIDIR N3 AT22 2 5 V CMOS Clock input or output 3 B1 FMC CLK DIR AW 1 2 5 V CMOS Clock direction s
94. ions Part 6 of 7 2 51 kita 2 PA 1 0 Standard Description J10 Pin Numher C23 FMC LA N18 AC16 2 5 V CMOS FMC data bus LPC bank A H23 FMC LA N19 AV22 2 5 V CMOS FMC data bus LPC bank A G22 FMC LA N20 AR16 2 5 V CMOS FMC data bus LPC bank A H26 FMC LA N21 AG22 2 5 V CMOS FMC data bus LPC bank A G25 FMC_LA N22 AD21 2 5 V CMOS FMC data bus LPC bank A D24 FMC LA N23 AV18 2 5 V CMOS FMC data bus LPC bank A H29 FMC LA N24 AJ25 2 5 V CMOS FMC data bus LPC bank A G28 FMC LA N25 AK23 2 5 V CMOS FMC data bus LPC bank A D27 FMC LA N26 AK22 2 5 V CMOS FMC data bus LPC bank A C27 FMC LA N27 AG23 2 5 V CMOS FMC data bus LPC bank A H32 FMC LA N28 AG24 2 5 V CMOS FMC data bus LPC bank A G31 FMC LA N29 AN26 2 5 V CMOS FMC data bus LPC bank A H35 FMC LA N30 AE27 2 5 V CMOS FMC data bus LPC bank A 034 LA N31 AG27 2 5 V CM0S FMC data bus LPC bank A H38 FMC_LA N32 AD23 2 5 V CM0S FMC data bus LPC bank A G37 FMC LA N33 AC24 2 5 V CMOS FMC data bus LPC bank A G6 LA 16 2 5 V CMOS data bus LPC bank A D8 FMC LA P1 AW13 2 5 V CMOS FMC data bus LPC bank A H7 FMC_LA P2 AU15 2 5 V CMOS FMC data bus LPC bank A G9 FMC LA P3 AW15 2 5 V CMOS FMC data bus LPC bank A H10 FMC LA P4 AL8 2 5 V CMOS FMC data bus LPC bank A D11 FMC LA P5 7 2 5 V CMOS data bus LPC bank A C10 FMC LA P6 AM9 2 5 V CMOS FMC da
95. ity Driven by the Marvell 88E1111 PHY Green LED Illuminates to indicate Ethernet linked D40 ENET LED LINK10 2 5 V at 10 Mbps connection speed Driven by the Marvell 88E1111 PHY Green LED Illuminates to indicate Ethernet linked D38 ENET LED LINK100 2 5 V at 100 Mbps connection speed Driven by the Marvell 88E1111 PHY Green LED Illuminates to indicate Ethernet linked D39 ENET LED LINK1000 AN17 2 5 V at 1000 Mbps connection speed Driven by the Marvell 88E1111 PHY D4 HSMA RX LED 15 2 5 V Green LED Illuminates to indicate 5 port receive data activity D5 HSMA TX LED 14 2 5 V Green LED Illuminates to indicate HSMA port A transmit data activity Green LED Illuminates when HSMC port A has a D6 HSMA PRSNTn AW15 3 3 V board or cable plugged in such that pin 160 becomes grounded Driven by the add in card D7 HSMB RX LED AG26 254 Green LED Iiluminates to indicate HSMA port receive data activity I Green LED Illuminates to indicate HSMA port B 8 HSMB TX LED AMER ean transmit data activity Green LED Illuminates when HSMC port B has D9 HSMB_PRSNTn AT24 3 3 V board or cable plugged in such that pin 160 becomes grounded Driven by the add in card 1 Yellow LED Configure this LED to display the PCI D44 PCIE LED X1 AC18 2 5 V Express link width x1 Yellow LED Configure this LED to display the PCI D43 PCIE LED X4 AD17 2 5 V Express link width x4 D42 PCIE LED X8 AT16 2 5 V Yellow LED Configure this LED to display
96. k B F25 FMC HB P4 AG13 2 5 V CMOS FMC data bus bank B December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 50 Chapter 2 Board Components Components and Interfaces Table 2 29 FMC Connector Pin Assignments Schematic Signal Names and Functions Part 5 of 7 2 uw 1 0 Standard Description J10 Pin Number E24 FMC HB P5 AE13 2 5 V CMOS FMC data bus HPC bank B K28 FMC HB P6 AG12 2 5 V CMOS FMC data bus bank B J27 FMC HB P7 AH11 2 5 V CMOS FMC data bus HPC bank B F28 HB P8 AR10 2 5 V CMOS FMC data bus bank B E27 FMC HB P9 10 2 5 V CMOS FMC data bus bank K31 FMC_HB_P10 AD13 2 5 V CMOS FMC data bus bank B J30 FMC HB P11 AW9 2 5 V CMOS FMC data bus HPC bank B F31 FMC HB P12 AV10 2 5 V CMOS FMC data bus HPC bank B E30 FMC HB P13 AUS 2 5 V CMOS FMC data bus bank K34 FMC HB 14 AR13 2 5 V CMOS FMC data bus HPC bank B J33 FMC HB 15 AJ12 2 5 V CMOS FMC data bus bank B F34 FMC HB 16 AP12 2 5 V CMOS FMC data bus HPC bank B K37 FMC HB P17 AD11 2 5 V CMOS FMC data bus HPC bank B J36 FMC HB P18 AE12 2 5 V CMOS FMC data bus HPC bank B E33 FMC HB 19 AU12 2 5 V CMOS FMC data bus bank B F37 FMC HB P20 AL12 2 5 V CMOS FMC data bus
97. l LVDS 2 5V CMOS AT13 outputs HSMC HSMA CLK OUT P2 LVDS 2 5V CMOS 7 LVDS output Can also support 2x CMOS CLK OUT N2 LVDS 2 5V CMOS AL7 outputs HSMC HSMB CLK OUTO 2 5V CMOS AJ33 FPGA CMOS output or GPIO HSMC HSMB CLK OUT P1 LVDS 2 5V CMOS AM33 LVDS output Can also support 2x CMOS HSMB CLK OUT Ni LVDS 2 5V CMOS AL34 outputs HSMC HSMB CLK OUT P2 LVDS 2 5V CMOS AU32 LVDS output Can also support 2x CMOS CLK OUT 2 LVDS 2 5V CMOS AD26 outputs Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components 2 21 General User Input Output General User Input Output This section describes the user I O interface to the FPGA including the push buttons DIP switches status LEDs character LCD and SDI video output input port User Defined Push Buttons The development board includes three user defined push buttons for each FPGA device For information on the system and safe reset push buttons refer to Setup Elements on page 2 20 Board references 55 96 and 57 are push buttons that allow you to interact with Arria V GT FPGA 1 while S9 S10 and S11 are for use with the Arria V GT FPGA 2 When you press and hold down the button the device pin is set to logic 0 when you release the button the device pin is set to logic 1 There are no board specific functions for these general user push buttons Table 2 14 lists the user defined push b
98. lass Write mask byte lane D3 DDR3A DM1 D31 1 5 V SSTL Class Write mask byte lane DDR3A 000 N33 1 5 V SSTL Class Data bus byte lane F7 DDR3A 001 N31 1 5 V SSTL Class Data bus byte lane F2 DDR3A DQ2 N34 1 5 V SSTL Class Data bus byte lane F8 DDR3A DQ3 L31 1 5 V SSTL Class Data bus byte lane H3 DDR3A DQ4 N32 1 5 V SSTL Class Data bus byte lane H8 DDR3A DQ5 J34 1 5 V SSTL Class Data bus byte lane G2 DDR3A DQ6 P31 1 5 V SSTL Class Data bus byte lane H7 DDR3A DQ7 J32 1 5 V SSTL Class Data bus byte lane 07 DDR3A 008 A30 1 5 V SSTL Class Data bus byte lane C3 DDR3A DQ9 C30 1 5 V SSTL Class Data bus byte lane C8 DDR3A DQ10 B30 1 5 V SSTL Class Data bus byte lane Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components Memory Table 2 31 DDR3A Devices Pin Assignments Schematic Signal Names and Functions Part 5 of 5 2 59 Board Reference erasa 1 0 Standard Description C2 DDR3A 0011 H31 1 5 V SSTL Class Data bus byte lane DDR3A 0012 831 1 5 SSTL Class Data bus byte lane A2 DDR3A DQ13 E31 1 5 V SSTL Class Data bus byte lane B8 DDR3A 0014 1 1 5 V SSTL Class Data bus byte lane DDR3A 0015 C31 1 5 V SSTL Class Data bus byte lane G3 DDR3A DQS NO M33 1 5 V SSTL Class Data strobe N byte lane B7 DDR3A DQS 1 B33 1 5 V S
99. le oscillator with a default frequency of 148 5 MHz m Four programmable oscillators with four outputs each of various default frequencies m Clock buffer with two outputs sourced by one of the above four programmable oscillators with one output to the FPGA reference clock and Bull s Eye SMA m SMA connectors for external LVPECL clock input Power supply m 14 20 V DC input m PCI Express edge connector power m 12 PCI Express ATX supply m On board power measurement circuitry Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual Chapter 1 Overview Board Component Blocks m Mechanical Dual FPGA PCI Express long form factor 4 376 x 10 45 PCI Express chassis or bench top operation The development board includes two Arria V GT FPGAs that connect to other components on the board to provide a better transceiver and bandwidth design solution FPGA 1 The first FPGA device FPGA 1 connects to the following components m Communication ports One PCI Express x8 edge connector One universal HSMC expansion port port A One USB 2 0 connector One gigabit Ethernet port Chip to Chip C2C bridge with 29 LVDS inputs and 29 LVDS outputs and x8 transceivers Two small form factor pluggable plus SFP channels One SMA 10 Gbps transceiver channel Three Bull s Eye 10 Gbps transceiver channels m Memory December 2014 Altera Corporation 1152 Mbyte MB DDR3 SDRAM with a 72 bit data bu
100. matic Signal Name POR 1 0 Standard Description 156 HSMA CLK IN P2 AR6 LVDS or 2 5 V LVDS or CMOS clock in 2 or CMOS bit 77 157 HSMA CLK OUT N2 AL7 LVDS or 2 5 V LVDS or CMOS clock out 2 or CMOS bit 78 158 HSMA CLK IN N2 AP6 LVDS or 2 5 V LVDS or CMOS clock in 2 or CMOS bit 79 160 HSMA PSNTN AW15 2 5 V CMOS HSMC port A presence detect Table 2 27 lists the HSMC port B interface pin assignments signal names and functions Table 2 27 HSMC Port B Pin Assignments Schematic Signal Names and Functions Part 1 of 4 Beard 1 0 Standard Description Reference J2 Schematic Signal Name Pin Number p 17 HSMB TX P3 AT3 1 5 V PCML Transceiver TX bit 3 18 HSMB RX P3 1 5 V PCML Transceiver RX bit 3 19 HSMB TX N3 1 5 PCML Transceiver TX bit 20 HSMB RX N3 AU2 1 5 V PCML Transceiver RX bit 3n 21 HSMB TX P2 AP3 1 5 V PCML Transceiver TX bit 2 22 HSMB_RX_P2 1 1 5 V PCML Transceiver RX bit 2 23 HSMB TX N2 4 1 5 V PCML Transceiver TX bit 2n 24 HSMB RX N2 AR2 1 5 V PCML Transceiver RX bit 2n 25 HSMB TX Pl 1 5 V PCML Transceiver TX bit 1 26 HSMB Pl 1 5 V PCML Transceiver RX bit 1 27 HSMB TX NI 1 5 V PCML Transceiver TX bit 1n 28 HSMB NI AN2 1 5 V PCML Transceiver RX bit 1n 29 HSMB_TX PO AK3 1 5 V PCML Transceiver TX bit 0 30 HSMB RX PO AL
101. measure voltage and current A SPI bus connects these ADC devices to the MAX II CPLD EPM2210 System Controller as well as the Arria V GT FPGA Chapter 2 Board Components Power Supply Figure 2 13 shows the block diagram for the power measurement circuitry Figure 2 13 Power Measurement Feedback R SENSE A Supply Power Supply Load 0 14 10 14 SCK DSO CSn LTC2418 SCK DSI 8 DSO CSn DSI ft Embedded USB Blaster To User PC Power GUI 570 UB _ mE JTAG Chain RW 14 pin RS 2x16 LCD D 0 7 Arria V EPM2210 gt FPGA 4 Table 2 36 lists targeted rails The schematic signal name column specifies the name of the rail being measured while the device pin column specifies the devices attached to the rail If no subnet is named the power is the total output power for that voltage Table 2 36 Power Measurement Rails Part 1 of 3 Switch Schematic Signal Name GUI Name Voltage Device Pin Description VCCR GXB XCVR analog receive and clock 1 VCCR VCCL GXB XCVR GXB 1 2V VCCL GXB A5A_VCCT_GXB 1 2V VCCT_GXB XCVR transmitter power 2 5V VCCA PLL analog power 2 2 5V VCC AUX 23 2 5V VCCA GXB Auxiliary
102. mit channel A18 FMC DP M2C P5 N1 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B16 FMC DP M2C P6 L1 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B12 FMC DP M2C P7 G1 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B8 FMC DP M2C P8 E1 2 5 V CMOS Transmit channel available in Arria V GT FPGA device B4 DP M2C P9 C1 2 5 V CMOS Transmit channel available in Arria V GT FPGA device 04 GBTCLK M2C AB9 2 5 V CMOS Transceiver reference clock 0 D5 FMC M2C AB8 2 5 V CMOS Transceiver reference clock 0 B20 GBTCLK M2C PI 2 5 V CMOS Transceiver reference clock 1 December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 48 Chapter 2 Board Components Components and Interfaces Table 2 29 FMC Connector Pin Assignments Schematic Signal Names and Functions Part 3 of 7 oie uw 1 0 Standard Description J10 Pin Number B21 FMC M2C 1 2 5 V CMOS Transceiver reference clock 1 F5 FMC HA NO AG16 2 5 V CMOS FMC data bus HPC bank A E3 FMC HA N1 AE17 2 5 V CMOS FMC data bus HPC bank A K8 FMC HA N2 AU16 2 5 V CMOS FMC data bus HPC bank A J7 FMC HA N3 AN17 2 5 V CMOS FMC data bus HPC bank A F8 HA N4 AK9 2 5 V CMOS FM
103. mmable VCXO enable USB CFGO H14 1 8 V On board USB Blaster data USB H13 1 8 V On board USB Blaster data USB CFG2 613 1 8 V On board USB Blaster data USB CFG3 F17 1 8 V On board USB Blaster data USB CFG4 612 1 8 V On board USB Blaster data USB CFG5 F18 1 8 On board USB Blaster data USB CFG6 H16 1 8 V On board USB Blaster data USB CFG7 516 1 8 On board USB Blaster data USB CFG8 H15 1 8 V On board USB Blaster data USB CFG9 G17 1 8 V On board USB Blaster data USB_CFG10 G14 1 8 V On board USB Blaster data USB_CFG11 G18 1 8 V On board USB Blaster data USB_CLK J6 2 5 V On board USB Blaster II clock VCCINT SCL R3 2 5 V LTC3880 serial clock VCCINT SDA R2 2 5 V LTC3880 serial data December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 14 Chapter 2 Board Components Configuration Status and Setup Elements Configuration Status and Setup Elements This section describes the board s configuration status and setup elements Configuration This section describes the FPGA flash memory and MAXII CPLD EPM2210 System Controller device programming methods supported by the Arria V GT FPGA development board The Arria V GT FPGA development board supports the following three configuration methods m On board USB Blaster II is the default method for configuring the FPGA at any time using the Quartus II Programmer in JTAG mode with the supplied USB cable
104. nal Information Document Revision History Info 1 How to Contact Altera ul dee Dee te vdd aes Info 1 Typographic Conventions Info 1 Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual 1 Overview This document describes the hardware features of the Arria9 development board including the detailed pin out and component reference information required to create custom FPGA designs that interface with all components of the board General Description The Arria V GT FPGA development board provides a hardware platform for developing and prototyping low power high performance and logic intensive designs using Altera s Arria V GT FPGA device The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V GT FPGA designs Two high speed mezzanine card HSMC connectors are available to add additional functionality via a variety of HSMCs available from Altera and various partners To see a list of the latest HSMCs available to download a copy of the HSMC specification refer to the Development Board Daughtercards page of the Altera website Design advancements and innovations such as the PCI Express hard IP implementation and programmable power technology ensure that
105. ng the Nios II processor St For more information on the Nios II processor refer to the Nios II Processor page of the Altera website FPGA Programming from Flash Memory On either power up or by pressing the program configuration push button PGM1 CONFIG S3 MAX II CPLD EPM2210 System Controller s PFL configures the FPGA from the flash memory when the PGM1_LED 2 0 are ON PFL megafunction reads 16 bit data from the flash memory and converts it to fast passive parallel FPP format This 8 bit data is then written to the FPGA s dedicated configuration pins during configuration Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual Chapter 2 Board Components Configuration Status and Setup Elements Figure 2 5 shows the PFL configuration Figure 2 5 PFL Configuration 2 17 251 25 25V 25V 5620 gt 1000 c MAX II CPLD 2210 System Controller gt MAX ERRORI 50 MHz 5232 gt MAX LOAD1 I CONF DONE1 MSEL 4 0 also 100 Mit goes to MAX II CPLD z 5 FPGA INIT DONE lt INIT DONE FPGA nSTATUS lt nSTATUS MSELT FPGA nCONFIG lt gt nCONFIG MSEL3 a
106. ng the device as well as a carrier detect or auto mute signal interface Table 2 22 lists the cable equalizer lengths Table 2 22 SDI Cable Equalizer Lengths Data Rate Mbps 270 1485 Cable Type Belden 1694A 2970 Maximum Cable Length m 400 140 120 Figure 2 7 is an excerpt from the LMH0384SQ cable equalizer data sheet that shows the SDI cable equalizer On this development board the output is a single ended output with the negative channel driving a load local to the board Figure 2 7 SDI Cable Equalizer SDI Adaptive Cable Equalizer Coaxial Cable 750 1 0 uF Q 2 ANN SDI SDO gt 1 0 uF M To FPGA SDI SDO 3 9 nH 750 3740 MUTE l 55 l MUTE gt gt n gt gt BYPASS gt gt CD 1 0 uF Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation Chapter 2 Board Components 2 33 Components and Interfaces Table 2 23 summarizes the SDI video input interface pin assignments signal names and functions Table 2 23 SDI Video Input Interface Pin Assignments Schematic Signal Names and Functions Board Reference Schematic Aria VGT FPGA yo standard Description 2 SDI A EQIN P1 3 3 V SDI video cable equalizer input P 3 SDI A EQIN N1 3 3 V SDI video cable equalizer input N 7 SDI_A RX BYPASS
107. ns Courier type Indicates signal port register bit block and primitive names For example datal tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI lt angled arrow instructs you to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b c and so on such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 57 The hand points information that requires special attention The question mark directs you to a software help system with related information The feet direct you to another document or website with related information The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Alter
108. ns Part 3 of 5 2 57 Board Reference A E 1 0 Standard Description H8 DDR3A DQ53 N24 1 5 V SSTL Class Data bus byte lane G2 DDR3A DQ54 G25 1 5 V SSTL Class Data bus byte lane H7 DDR3A_DQ55 K24 1 5 V SSTL Class Data bus byte lane D7 DDR3A DQ56 F23 1 5 V SSTL Class Data bus byte lane C3 DDR3A DQ57 J23 1 5 V SSTL Class Data bus byte lane C8 DDR3A DQ58 G23 1 5 V SSTL Class Data bus byte lane C2 DDR3A DQ59 C24 1 5 V SSTL Class Data bus byte lane AT DDR3A DQ60 F24 1 5 V SSTL Class Data bus byte lane A2 DDR3A DQ61 R23 1 5 V SSTL Class Data bus byte lane B8 DDR3A DQ62 G24 1 5 V SSTL Class Data bus byte lane A3 DDR3A DQ63 M23 1 5 V SSTL Class Data bus byte lane G3 DDR3A DQS N6 B25 1 5 V SSTL Class Data strobe N byte lane B7 DDR3A DQS N7 E24 1 5 V SSTL Class Data strobe N byte lane F3 DDR3A DQS P6 A25 1 5 V SSTL Class Data strobe P byte lane C7 DDR3A DQS P7 D24 1 5 V SSTL Class Data strobe P byte lane L8 DDR3A ZQ04 1 5 V SSTL Class ZQ impedance calibration DDR3A U18 E7 DDR3A DM4 E27 1 5 V SSTL Class Write mask byte lane D3 DDR3A DM5 A26 1 5 V SSTL Class Write mask byte lane E3 DDR3A DQ32 P27 1 5 V SSTL Class Data bus byte lane F DDR3A DQ33 B27 1 5 V SSTL Class Data bus byte lane F2 DDR3A DQ34 R27 1 5 V SSTL Class Data bus byte lane F8 D
109. nts Board Overview 2 5 Table 2 1 Arria V GT FPGA Development Board Components Part 4 of 4 Board Reference Type Description 9 MB QDRII SRAM with 36 bit data bus The device has a separate 08 36 bit read and 36 bit write port with DDR signalling at up to 400 MHz U7 U11 U18 DDR3 SDRAM interface on FPGA 1 This 1152 MB DDR3 x72 bit data DDR3A memory bus consists of four x16 devices and one x8 device with a single U21 U28 address or command bus DDR3 SDRAM interface on FPGA 2 There are two interface options m Option 1 512 MB interface with a 32 bit data bus This DDR3 U6 U12 U19 x32 bit data bus consists of two x16 devices with a single shared U22 DDR3B C memory address m Option 2 1024 MB interface with a 64 bit data bus This DDR3 x64 bit data bus consists of four x16 devices with a single shared address Communication Ports Gold plated edge fingers connector for up to x8 signaling in Gen1 and J30 PCI Express edge connector xA modes Provides four transceiver channels and 80 CMOS or 17 LVDS channels d per the HSMC specification Provides four transceiver channels and 80 CMOS or 17 LVDS channels J the 5 specification USB interface for programming the FPGA through on board saj Mini USB type AB connector reb Blaster II JTAG a type AB Mini USB cable RJ 45 connector which provi
110. ock in 2 or CMOS bit 79 160 HSMB PRSNTN AT24 2 5 V CMOS HSMC port B presence detect Modules The development board include two SFP modules that use transceiver channels from the FPGA These modules takes in serial data from the FPGA and transform them into optical signals Both SFP ports are active and include the SFP cage assembly only when the Arria V GT FPGA device is installed The Arria V GX FPGA development board includes only one SFP cage assembly for the SFP port used by the device Table 2 28 list the SFP modules interface pin assignments signal names and functions Table 2 28 SFP Modules Pin Assignments Schematic Signal Names and Functions Part 1 of 2 Reference Signal Name Number VO Standard Description SFP Module J10 6 SFP_MOD_ABS1 AK16 3 3 V LVTTL Module present indicator 8 SFP OP RX 1051 AN19 3 3 V LVTTL Signal present indicator 2 SFP OP TX FLT1 AG17 3 3 V LVTTL Transmitter fault indicator 12 SFP Nl Y38 3 3 V LVTTL Receiver data 13 SFP RX P1 Y39 3 3 V LVTTL Receiver data 5 SFP SCL1 AL18 3 3 V LVTTL Serial 2 wire clock 4 SFP 8111 AC16 3 3 V LVTTL Serial 2 wire data 3 SFP TX DIS1 AN15 3 3 V LVTTL Drive low to disable transmitter 19 SFP TX NI W36 3 3 V LVTTL Transmitter data 18 SFP TX W37 3 3 V LVTTL Transmitter data 7 SFP TX RS01 AN14 3 3 V LVTTL
111. on The program select push button PGM1 SEL 52 is an input to the MAX II CPLD System Controller The push button toggles the PGM1 LED 2 0 sequence that selects which location in the flash memory is used to configure the FPGA Refer to Table 2 6 for the PGM1 LED 2 0 sequence definitions Clock Circuitry This section describes the board s clock inputs and outputs On Board Oscillators The development board includes fixed and programmable oscillators with a frequency of 50 MHz 100 MHz 125 MHz 148 5 MHz 156 25 MHz and 625 MHz Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual Chapter 2 Board Components Clock Circuitry 2 23 Figure 2 6 shows the default frequencies of all external clocks going to the Arria V GT FPGA development board Figure 2 6 Arria V GT FPGA Development Board Clocks December 2014 Altera Corporation U51 2 50 Buffer SOM MAX 50 50 MHz 50 MHz 10 35 100 MHz 5 gt Buffer x gt 100 Default Si570 100 MHz gt Default g 125MHz zz
112. push button CPU1_RESETn 54 for FPGA 1 and CPU2_RESETn S8 for FPGA 2 Both these push buttons are inputs to the Arria V GT FPGA DEV CLRn pin and are open drain I Os from the MAX II CPLD System Controller The push button is the default reset for both the FPGA and CPLD logic The MAX II System Controller also drives these push button during POR 57 You must enable the RESETn signal within the Quartus II software for this reset function to work Otherwise the CPU RESETn acts as a regular I O pin When you enable the signal in the Quartus II software and then pull high on the board every register within the FPGA resets to a low signal II Reset Push Button The MAX II reset push button MAX RESETn is an input to the MAX II CPLD System Controller This push button is the default reset for the CPLD logic Configuration Push Button The configuration push button PGM1 CONFIG S3 is an input to the MAXII CPLD EPM2210 System Controller The push button forces a reconfiguration of the FPGA from flash memory The location in the flash memory is based on the settings of the PGM1 LED 2 0 which is controlled by the image select push button PGM1 SEL 52 Valid settings include PGM1_LED0 PGM1_LED1 or PGM1_LED2 on the three pages in flash memory reserved for FPGA designs December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 22 Chapter 2 Board Components Clock Circuitry Image Select Push Butt
113. s 72 Mbit Mb QDRII SRAM 1 Gbit Gb synchronous flash with a 16 bit data bus Arria V GT FPGA Development Board Reference Manual 1 4 Chapter 1 Overview Board Component Blocks m General user I O LEDs and displays Eight dual color user LEDs Two line character LCD display Three configuration select LEDs One configuration done LED Two HSMC interface transmit receive TX RX LEDs Three PCI Express LEDs Five Ethernet LEDs Push buttons One CPU reset push button One Max II CPLD EPM2210 System Controller configuration reset push button One load image push button to program the FPGA from flash memory One image select push button select an image to load from flash memory Three general user push buttons Eight user control DIP switches FPGA 2 The second FPGA device FPGA 2 connects to the following components m Communication ports One universal HSMC expansion port port B One FMC port C2C bridge with 29 LVDS inputs and 29 LVDS outputs and x8 transceivers One serial digital interface SDI channel One SMA 10 Gbps transceiver channel One Bull s Eye 6 Gbps transceiver channel One Bull s Eye 10 Gbps transceiver channel m Memory m 1024 MB DDR3 SDRAM with a 64 bit data bus soft controller m 512 MB DDR3 SDRAM with a 32 bit data bus hard IP controller Arria V GT FPGA Development Board Reference Manual December 2014 Altera Corporation
114. software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Meaning Indicate command names dialog box titles dialog box options and other GUI Bold Type with Initial Capital labels For example Save As dialog box For GUI elements capitalization matches Letters the GUI Indicates directory names project names disk drive names file names file name bold type extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines Indicates variables For example 1 italic type Variable names are enclosed in angle brackets lt gt For example file name and lt project name pot file December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual Info 2 Additional InformationAdditional Information Typographic Conventions Visual Cue Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus II Help topics For example Typographic Conventio
115. t B on device 2 HSMC port A and port B interfaces support both single ended and differential signaling This physical interface provides eight channels of 6 5536 Gbps capable transceivers for the GT version of this board The HSMC interface also supports a full 5 14 2 interface 17 LVDS channels three input and output clocks JTAG and SMB signals as well as power for compatible HSMC cards The LVDS channels can be used for CMOS signaling as well as LVDS The HSMC is an Altera developed open specification which allows you to expand the functionality of the development board through the addition of daughtercards HSMCs December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 38 Chapter 2 Board Components Components and Interfaces For more information about the HSMC specification such as signaling standards signal integrity compatible connectors and mechanical information refer to the High Speed Mezzanine Card HSMC Specification manual The HSMC connector has a total of 172 pins including 120 signal pins 39 power pins and 13 ground pins The ground pins are located between the two rows of signal and power pins acting both as a shield and a reference The HSMC host connector is based on the 0 5 mm pitch family of high speed board to board connectors from Samtec There are three banks in this connector Bank 1 has every third pin removed as done in the QSH DP QTH DP series
116. t On or CMOS bit 6 50 HSMB RX D NO AB25 LVDS or 2 5 V LVDS RX bit On or CMOS bit 7 53 HSMB TX D P1 AE28 LVDS or 2 5 V LVDS TX bit 1 or CMOS bit 8 54 HSMB RX D Pl AF25 LVDS or 2 5 V LVDS RX bit 1 or CMOS bit 9 55 HSMB TX D NI AD28 LVDS or 2 5 V LVDS TX bit 1n or CMOS bit 10 56 HSMB RX D N1 AE25 LVDS or 2 5 V LVDS RX bit 1n or CMOS bit 11 59 HSMB TX D P2 AE29 LVDS or 2 5 V LVDS TX bit 2 or CMOS bit 12 60 HSMB RX D P2 AD27 LVDS or 2 5 V LVDS RX bit 2 or CMOS bit 13 61 HSMB TX D N2 AD29 LVDS or 2 5 V LVDS TX bit 2n or CMOS bit 14 62 HSMB RX D N2 AC27 LVDS or 2 5 V LVDS RX bit 2n or CMOS bit 15 65 HSMB TX D P3 AK27 LVDS or 2 5 V LVDS TX bit 3 or CMOS bit 16 66 HSMB RX D P3 AB28 LVDS or 2 5 V LVDS RX bit 3 or CMOS bit 17 67 HSMB TX D N3 AJ27 LVDS or 2 5 V LVDS TX bit 3n or CMOS bit 18 68 HSMB RX D N3 AB27 LVDS or 2 5 V LVDS RX bit 3n or CMOS bit 19 71 HSMB TX D P4 AL29 LVDS or 2 5 V LVDS TX bit 4 or CMOS bit 20 72 HSMB RX D P4 AJ28 LVDS or 2 5 V LVDS RX bit 4 or CMOS bit 21 73 HSMB TX D N4 AK29 LVDS or 2 5 V LVDS TX bit 4n or CMOS bit 22 74 HSMB RX D AH28 LVDS or 2 5 V LVDS RX bit 4n or CMOS bit 23 77 HSMB TX D P5 AL30 LVDS or 2 5 V LVDS TX bit 5 or CMOS bit 24 78 RX D P5 AG28 LVDS or 2 5 V LVDS RX bit 5 or CMOS bit 25 79 HSMB TX D N5 LVDS or 2 5 V LVDS TX bit 5n CMOS bit 26 80 HSMB RX D N5 AF28 LVDS or 2 5 V LVDS RX bit 5n or CMOS bit 27 83 HSMB TX D P6 AL32 LVDS or 2 5 V LVDS TX bit 6 or C
117. ta bus LPC bank A H13 FMC LA P7 AT6 2 5 V CMOS FMC data bus LPC bank A G12 FMC_LA P8 AP9 2 5 V CMOS FMC data bus LPC bank A D14 FMC LA P9 AH17 2 5 V CMOS FMC data bus LPC bank A C14 FMC LA P10 AV6 2 5 V CMOS FMC data bus LPC bank A H16 FMC LA P11 AL15 2 5 V CMOS FMC data bus LPC bank A 615 FMC LA P12 AK16 2 5 V CMOS FMC data bus LPC bank A D17 FMC LA P13 AL14 2 5 V CMOS FMC data bus LPC bank A C18 FMC LA P14 AU13 2 5 V CMOS FMC data bus LPC bank A H19 FMC LA P15 AM16 2 5 V CMOS FMC data bus LPC bank A G18 FMC_LA P16 AL24 2 5 V CMOS FMC data bus LPC bank A D20 FMC_LA P17 AP15 2 5 V CMOS FMC data bus LPC bank A 022 LA P18 AD16 2 5 V CMOS FMC data bus LPC bank A H22 FMC LA P19 AW22 2 5 V CMOS FMC data bus LPC bank A G21 FMC_LA P20 AT16 2 5 V CMOS FMC data bus LPC bank A H25 FMC_LA P21 AH22 2 5 V CMOS FMC data bus LPC bank A December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 52 Chapter 2 Board Components Components and Interfaces Table 2 29 FMC Connector Pin Assignments Schematic Signal Names and Functions Part 7 of 7 2 Kou 1 0 Standard Description J10 Pin Number G24 FMC LA P22 22 2 5 V CM0S FMC data bus LPC bank A D23 FMC LA P23 AW18 2 5 V CM0S FMC data bus LPC bank A H28 FMC LA P24 AK25 2 5 V CMOS FMC data bus LPC bank A G27 FMC LA P25 AL23
118. te data bus G10 QDRII D13 AU27 1 8 V HSTL Write data bus F9 QDRII 014 AN27 1 8 V HSTL Write data bus D10 QDRII 015 AV27 1 8 V HSTL Write data bus C9 QDRII D16 AW27 1 8 V HSTL Write data bus B9 QDRII D17 AH27 1 8 V HSTL Write data bus B3 QDRII D18 AC25 1 8 V HSTL Write data bus C3 QDRII D19 AF27 1 8 V HSTL Write data bus D2 QDRII D20 AD25 1 8 V HSTL Write data bus F3 QDRII D21 AG26 1 8 VHSTL Write data bus G2 QDRII D22 AH26 1 8 V HSTL Write data bus J3 QDRII D23 AE26 1 8 V HSTL Write data bus L3 QDRII D24 AG25 1 8 V HSTL Write data bus M3 QDRII D25 AH25 1 8 V HSTL Write data bus N2 QDRII D26 AP26 1 8 V HSTL Write data bus C1 QDRII D27 AN25 1 8 VHSTL Write data bus D1 QDRII D28 AK25 1 8 V HSTL Write data bus E2 QDRII D29 AT26 1 8 V HSTL Write data bus G1 QDRII D30 AU26 1 8 V HSTL Write data bus QDRII D31 AT25 1 8 V HSTL Write data bus K2 QDRII D32 AW25 1 8 V HSTL Write data bus M1 QDRII D33 AW26 1 8 V HSTL Write data bus N1 QDRII D34 AL26 1 8 V HSTL Write data bus P2 QDRII D35 AV25 1 8 V HSTL Write data bus H1 QDRII DOFFN AN24 1 8 V HSTL DLL enable A6 QDRII K N AE25 1 8 V HSTL Write clock N B6 QDRII K P AF25 1 8 V HSTL Write clock P P11 QDRII 00 AD24 1 8 V HSTL Read data bus December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 66 Table 2 34 QDRII Pin Assignments Schematic Signal Names and Functions Part 3 of 3 Chapter 2 Board Compon
119. ter 2 Board Components MAX II CPLD EPM2210 System Controller Schematic Signal Name 22 1 0 Standard Description FM A8 R18 1 8 V FM bus address FM A9 N15 1 8 V FM bus address FM A10 P16 1 8 V FM bus address FM A11 N14 1 8 V FM bus address FM A12 P18 1 8 V FM bus address FM A13 M15 1 8 V FM bus address FM 14 N16 1 8 V FM bus address FM A15 P17 1 8 V FM bus address FM A16 N13 1 8 V FM bus address FM A17 M14 1 8 V FM bus address FM A18 N17 1 8 V FM bus address FM A19 M13 1 8 V FM bus address FM A20 N18 1 8 V FM bus address FM A21 M12 1 8 V FM bus address FM A22 M16 1 8 V FM bus address FM A23 K14 1 8 V FM bus address FM A24 K18 1 8 V FM bus address FM A25 K15 1 8 V FM bus address FM A26 H17 1 8 V FM bus address FM DO L16 1 8 V FM data bus FM DI M18 1 8 V FM data bus FM D2 L14 1 8 V FM data bus FM D3 L17 1 8 V FM data bus FM 14 L13 1 8 V FM data bus FM D5 L18 1 8 V FM data bus FM D6 M17 1 8 V FM data bus FM D7 L15 1 8 V FM data bus D8 K16 1 8 V FM data bus FM D9 17 1 8 V FM data bus FM D10 D15 1 8 bus FM D11 C17 1 8 V FM data bus FM D12 E15 1 8 V FM data bus FM D13 C16 1 8 V FM data bus FM D14 D16 1 8 bus D15 14 1 8 data bus FMC_C2M PG P6 2 5 V FMC card to module power good FMC M2C PG T4 2 5 V FMC module to card power good FMC PRSNT U3 2 5 V FMC module present FM
120. that SW2 5 USER1 DIPSWA G17 2 5 V connects to FPGA 1 SW2 6 USER1 DIPSW5 F17 2 5 V SW2 7 USER1_DIPSW6 D17 2 5 V SW2 8 USER1_DIPSW7 C17 2 5 V SW3 1 USER2 DIPSWO C8 2 5 V SW3 2 USER2 DIPSW1 D8 2 5 V SW3 3 USER2 DIPSW2 E7 2 5 V SW3 4 USER2_DIPSW3 E6 2 5 V User defined DIP switch that SW3 5 USER2_DIPSW4 G8 2 5 V connects to FPGA 2 SW3 6 USER2 DIPSWS F8 2 5 V SW3 7 USER2 DIPSW6 D15 2 5 V SW3 8 USER2 DIPSW7 G11 2 5 User Defined LEDs The development board includes general and user defined LEDs This section describes all user defined LEDs For information on board specific or status LEDs refer to Status Elements on page 2 18 General User Defined LEDs Board references D18 through D25 and D26 through D33 are two sets of eight pairs user defined LEDs Each of the Arria V GT FPGA have a set of user defined LEDs The LEDs illuminate when a logic 0 is driven and turns off when a logic 1 is driven There are no board specific functions for these LEDs Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual Chapter 2 Board Components General User Input Output 2 29 Table 2 16 lists the user defined LED schematic signal names and their corresponding Arria V GT FPGA pin numbers Tahle 2 16 User Defined LED Schematic Signal Names and Functions Board Reference ena 1 0 Standard 025 USER1 LED GO U16 C15 2
121. tion MAX 0111 A12 2 5 V FPGA 1 to MAX II option MAX CTL2 D10 2 5 V FPGA 1 to MAX II option MAX ERRORI C7 2 5 V FPGA 1 configuration error LED MAX LOAD1 B6 2 5 V FPGA 1 configuration active LED MAX RESETN E18 1 8 V II reset push button OVERTEMP1 B14 2 5 V FPGA 1 fan RPM control OVERTEMP2 C12 2 5 V FPGA 2 fan RPM control CONFIG B4 2 5 V Load the flash memory image identified by the PGM LEDs December 2014 Altera Corporation Chapter 2 Board Components MAX CPLD EPM2210 System Controller 2 13 Table 2 5 MAX Il CPLD EPM2210 System Controller Device Pin Out Part 5 of 5 Schematic Signal Name reris 1 0 Standard Description PGM1_LEDO A4 2 5 V Flash memory PGM select indicator 0 PGM1 LED1 F7 2 5 V Flash memory PGM select indicator 1 PGM1 LED2 C5 2 5 V Flash memory PGM select indicator 2 SEL D6 2 5 V Toggles the LED 0 2 LED sequence PHASEO P8 2 5 V LTM4601 phase control SDI A RX BYPASS A8 2 5 V SDI equalization bypass SDI A RX EN E9 2 5 V SDI receive enable SDI A TX EN F9 2 5 V SDI transmit enable SENSE CSON F12 2 5 V Power monitor chip select SENSE CSIN B15 2 5 V Power monitor chip select SENSE SCK E12 2 5 V Power monitor SPI clock SENSE SDI A15 2 5 V Power monitor SPI data in SENSE SDO 012 2 5 Power monitor SPI data out SI570 EN A13 2 5 V 51570 programmable oscillator enable SI571 EN C13 2 5 V 51571 progra
122. troller is actively configuring D17 MAX LOAD1 2 5 V the FPGA Driven by the MAX II CPLD EPM2210 System Controller wire OR d with the on board USB Blaster CPLD Red LED when the MAX II CPLD 2210 System Controller fails to configure the Dio MAA ERRORI 2 5 V FPGA Driven by the MAX II CPLD 2210 System Controller Green LEDs Illuminates to indicate which hardware D12 D13 _ _ page loads from flash memory when you press the D14 PGM1 LED 2 0 2 3 V PGMi SEL push button or when you power on the board Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual Chapter 2 Board Components Configuration Status and Setup Elements Table 2 7 Board Specific LEDs Part 2 of 2 2 19 Schematic Signal Arria V GT FPGA 1 0 Reference Name Pin Numher Standard Description Green LED when FPGA 1 is D34 DEVICE1 LED 2 5 V successfully configured Driven by the MAX II CPLD EPM2210 System Controller Green LED when FPGA 2 is D35 DEVICE2 LED 2 5 V successfully configured Driven by the MAX II CPLD EPM2210 System Controller Green LED Illuminates to indicate Ethernet PHY D36 LED TX 2 5 V transmit activity Driven by the Marvell 88E1111 PHY Green LED Illuminates to indicate Ethernet PHY D37 ENET LED RX 2 5 V receive activ
123. trols the PCI Express lane width by connecting prsnt pins SW7 PCI Express DIP switch together on the PCI Express edge connector This switch is located on the bottom of the board SW8 FPGA 1 mode select DIP Sets the Arria V MSEL 4 2 1 pins This switch is located on the switch bottom of the board FPGA 2 mode select DIP Sets the Arria V MSEL 4 2 1 pins This switch is located on the 5 4 switch bottom of the board Toggles the configuration LEDs which selects the program image that loads from flash memory to the FPGA 53 Program configuration push Configures the FPGA from flash memory image based on the program button LEDs D1 Power LED Illuminates when 5 0 V power is present Indicate the transmit or receive activity of the JTAG chain The Tx and D2 D3 JTAG Tx Rx LEDs Rx LEDs blink when the link is in use and active The LEDs are off when not in use and on when in use or idle 04 05 HSMC port LEDs You can configure these LEDs to indicate transmit or receive activity D6 HSMC port A present LED Illuminates when a daughtercard is plugged into the HSMC port A D7 D8 HSMC port B LEDs You can configure these LEDs to indicate transmit or receive activity D9 HSMC port B present LED Illuminates when daughtercard is plugged into the HSMC port B Indicate the transmit or receive activity of the System Console USB D10 D11 System Console Tx Rx LEDs interface The Tx and Rx LEDs blink when the link is in use and active The LEDs are off wh
124. utton schematic signal names and their corresponding Arria V GT FPGA device pin numbers Table 2 14 User Defined Push Button Schematic Signal Names and Functions Board Reference Pale Pu 1 0 Standard Description S6 USER1 U16 T19 2 5 V 55 USER PBl U16 R19 T NE 54 USER1 PB2 U16 F18 2 5 V 511 USER2 U13 D6 2 5 V 510 USER2 PBl U13 C6 59 USER2 2 U13 K7 2 5 V User Defined DIP Switches Board references SW2 and SW3 are two sets of eight pin DIP switches There are no board specific functions for these switches Each of the Arria V GT FPGA have a set of user defined DIP switch When the switch is in the OFF position a logic 1 is selected When the switch is in the ON position a logic 0 is selected December 2014 Altera Corporation Arria V GT FPGA Development Board Reference Manual 2 28 Chapter 2 Board Components General User Input Output Table 2 15 lists the user defined DIP switch schematic signal names and their corresponding Arria V GT FPGA pin numbers Table 2 15 User defined DIP Switch Schematic Signal Names and Functions Schematic Arria V GT FPGA 2242 Board Reference Signal Name Pin Number 1 0 Standard Description SW2 1 USER1 DIPSWO P18 2 5 V SW2 2 USER1_DIPSW1 N18 2 5 SW2 3 USER1 DIPSW2 C16 2 5 V SW2 4 USER1 DIPSW3 B16 2 5 V User defined DIP switch
125. ve chain However the Arria V GT FPGAs and MAXII CPLD EPM2210 System Controller are always in the JTAG chain Table 2 9 lists the switch controls and its descriptions Table 2 9 JTAG Chain Header Switch Controls Part 1 of 2 Switch Schematic Signal Name Description ON Bypass HSMA 1 HSMA JTAG EN OFF HSMA in chain ON Bypass HSMB 2 HSMB JTAG EN OFF in chain Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual Chapter 2 Board Components 2 21 Configuration Status and Setup Elements Tahle 2 9 JTAG Chain Header Switch Controls Part 2 of 2 Switch Schematic Signal Name Description ON Bypass FMC connector 3 FMC JTAG EN OFF FMC connector in chain 4 NC Unused PCI Express Control DIP Switch The PCI Express control DIP switch SW7 is provided to enable or disable different configurations Table 2 10 lists the switch controls and descriptions Table 2 10 PCI Express Control DIP Switch Controls Switch Schematic Signal Name Description ON Enable x1 presence detect 1 PCIE PRSNT2n xl m E OFF Disable x1 presence detect ON Enable x4 presence detect 2 PCIE PRSNT2n x4 OFF Disable x4 presence detect ON Enable x8 presence detect 3 PCIE PRSNT2n 8 OFF Disable x8 presence detect 4 NC Unused CPU Reset Push Button Each Arria V GT FPGA has a CPU reset
126. x Rx SDI Video U16 SMA Express Edge Transceivers 07 U11 U18 SMA Transceivers Port J12 J13 J26 J27 J24 J25 Connector Connector J19 J22 U21 U28 Connector J10 J11 J14 J16 Table 2 1 describes the components and lists their corresponding board references Table 2 1 Arria V GT FPGA Development Board Components Part 1 of 4 Board Reference Type Description Featured Devices U13 U16 FPGA Two Arria V GT FPGA 5AGTFD7K3F4013N 1517 pin FBGA U2 CPLD CPLD EPM2210GF324 324 pin uBGA Configuration Status and Setup Elements Disables the on board USB Blaster for use with external USB Blasters J7 On Board USB Blaster Mini USB 2 0 connector for programming and debugging the FPGA Controls the MAX II CPLD EPM2210 System Controller functions such as clock enable SMA clock input control and which image to load J1 JTAG connector owe from flash memory at power up This switch is located on the bottom of the board Enables and disables devices in the JTAG chain This switch is located SW6 JTAG chain DIP switch on the bottom of the board Arria V GT FPGA Development Board December 2014 Altera Corporation Reference Manual Chapter 2 Board Components 2 3 Board Overview Table 2 1 Arria V GT FPGA Development Board Components Part 2 of 4 Board Reference Type Description Con

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