UM10120 Volume 1: LPC213x User Manual
Contents
1. above the level of V3 at any time Otherwise A D converter readings will be invalid If the A D converter is not used in an application then the pins associated with A D inputs can be used as 5 V tolerant digital IO pins Warning while the ADC pins are specified as 5 V tolerant see Table 56 Pin description on page 67 the analog multiplexing in the ADC block is not More than 3 3 V Vppa 10 should not be applied to any pin that is selected as an ADC input or the ADC reading will be incorrect If for example ADO 0 and ADO 1 are used as the ADCO inputs and voltage on ADO 0 4 5 V while ADO 1 2 5 V an excessive voltage on the ADO 0 can cause an incorrect reading of the ADO 1 although the ADO 1 input voltage is within the right range Vref Reference Voltage Reference This pin is provides a voltage reference level for the A D converter s Vpopa Vssa Power Analog Power and Ground These should be nominally the same voltages as Vpp and Vss but should be isolated to minimize noise and error Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 193 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 16 A D Converter 16 4 Register description The A D Converter registers are shown in Table 162 Table 162 ADC registers Generic Description Access Reset ADO AD1 Name valuel Address Address amp Name amp Name ADCR A D Cont2. Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 21 PDN 1 The A D converter is operational 0 0 The A D converter is in power down mode 23 22 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 26 24 START When the BURST bit is 0 these bits control whether and when an A D conversion is 0 started 000 No start this value should be used when clearing PDN to 0 001 Start conversion now 010 Start conversion when the edge selected by bit 27 occurs on P0O 16 EINTO MAT0 2 CAP0 2 pin 011 Start conversion when the edge selected by bit 27 occurs on P0 22 TD3 CAP0 0 MATO 0 pin 100 Start conversion when the edge selected by bit 27 occurs on MATO 1 101 Start conversion when the edge selected by bit 27 occurs on MATO 3 110 Start conversion when the edge selected by bit 27 occurs on MAT1 0 111 Start conversion when the edge selected by bit 27 occurs on MAT1 1 27 EDGE This bit is significant only when the START field contains 010 111 In these cases 0 Start conversion on a falling edge on the selected CAP MAT signa 0 Start conversion on a rising edge on the selected CAP MAT signal 31 28 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights rese
3. UM10120 Chapter 16 Analog to Digital Converter ADC Semiconductors 16 1 Features Rev 01 24 June 2005 User manual E e 10 bit successive approximation analog to digital converter one in LPC2131 2 and two in LPC2134 6 8 Input multiplexing among 8 pins e Power down mode e Measurement range 0 to 3 V e 10 bit conversion time gt 2 44 us e Burst conversion mode for single or multiple inputs e Optional conversion on transition on input pin or Timer Match signal e Global Start command for both converters LPC2134 6 8 only 16 2 Description Basic clocking for the A D converters is provided by the VPB clock A programmable divider is included in each converter to scale this clock to the 4 5 MHz max clock needed by the successive approximation process A fully accurate conversion requires 11 of these clocks 16 3 Pin description Table 161 gives a brief summary of each of ADC related pins Table 161 ADC pin description Pin Type ADO 7 0 Input amp AD1 7 0 LPC2134 6 8 Description Analog Inputs The A D converter cell can measure the voltage on any of these input signals Note that these analog inputs are always connected to their pins even if the Pin Multiplexing Register assigns them to port pins A simple self test of the A D Converter can be done by driving these pins as port outputs Note if the A D converter is used signal levels on analog input pins must not be
4. ardware triggered conversion If the BURST bit in the ADCR is 0 and the START field contains 010 111 the A D converter will start a conversion when a transition occurs on a selected pin or Timer Match signal The choices include conversion on a specified edge of any of 4 Match signals or conversion on a specified edge of either of 2 Capture Match pins The pin state from the selected pad or the selected Match signal XORed with ADCR bit 27 is used in the edge detection logic 16 5 2 Interrupts An interrupt request is asserted to the Vectored Interrupt Controller VIC when the DONE bit is 1 Software can use the Interrupt Enable bit for the A D Converter in the VIC to control whether this assertion results in an interrupt DONE is negated when the ADDR is read 16 5 3 Accuracy vs digital receiver The AIN function must be selected in corresponding Pin Select register see Pin Connect Block on page 73 in order to get accurate voltage readings on the monitored pin For pin hosting an ADC input it is not possible to have a have a digital function selected and yet get valid ADC readings An inside circuit disconnects ADC hardware from the associated pin whenever a digital function is selected on that pin Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 197
5. as a high impedance analog source a slower clock may be desirable 16 BURST 1 The AD converter does repeated conversions at the rate selected by the CLKS field 0 scanning if necessary through the pins selected by 1s in the SEL field The first conversion after the start corresponds to the least significant 1 in the SEL field then higher numbered 1 bits pins if applicable Repeated conversions can be terminated by clearing this bit but the conversion that s in progress when this bit is cleared will be completed Important START bits must be 000 when BURST 1 or conversons will not start 0 Conversions are software controlled and require 11 clocks Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 194 Philips Semiconductors UM10120 ja Volume 1 Chapter 16 A D Converter Table 163 A D Control Register ADOCR address 0xE003 4000 and AD1CR address 0xE006 0000 bit description Bit Symbol Value Description Reset value 19 17 CLKS This field selects the number of clocks used for each conversion in Burst mode and the 000 number of bits of accuracy of the result in the LS bits of ADDR between 11 clocks 10 bits and 4 clocks 3 bits 000 11 clocks 10 bits 001 10 clocks 9bits 010 9 clocks 8 bits 011 8 clocks 7 bits 100 7 clocks 6 bits 101 6 clocks 5 bits 110 5 clocks 4 bits 111 4 clocks 3 bits 20
6. rol Register The ADCR register must be written R W 0x0000 0001 OxE003 4000 OxE006 0000 to select the operating mode before A D conversion can ADOCR AD1CR occur ADDR A D Data Register This register contains the ADC s R W undefined OxE003 4004 OxE006 0004 DONE bit and when DONE is 1 the 10 bit result of the ADODR AD1DR conversion ADGSR_ A D Global Start Register This address can be written in WO 0x00 OxE003 4008 the ADO address range to start conversions in both A D ADGSR converters simultaneously 1 Reset value relects the data stored in used bits only It does not include reserved bits content 16 4 1 A D Control Register ADOCR 0xE003 4000 and AD1CR 0xE006 0000 Table 163 A D Control Register ADOCR address 0xE003 4000 and AD1CR address 0xE006 0000 bit description Bit Symbol Value Description Reset value 7 0 SEL Selects which of the ADO 7 0 AD1 7 0 pins is are to be sampled and converted For 0x01 ADO bit 0 selects Pin ADO 0 and bit 7 selects pin ADO 7 In software controlled mode only one of these bits should be 1 In hardware scan mode any value containing 1 to 8 ones All zeroes is equivalent to 0x01 15 8 CLKDIV The VPB clock PCLK is divided by this value plus one to produce the clock for the 0 A D converter which should be less than or equal to 4 5 MHz Typically software should program the smallest value in this field that yields a clock of 4 5 MHz or slightly less but in certain cases such
7. roma NA reserved bit is not defined Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 196 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 16 A D Converter Table 165 A D Global Start Register ADGSR address 0xE003 4008 bit description Bit Symbol Value Description Reset value 26 24 START When the BURST bit is 0 these bits control whether and when an A D conversion is 0 started 000 No start this value should be used when clearing PDN to 0 001 Start conversion now 010 Start conversion when the edge selected by bit 27 occurs on P0 16 EINTO MATO0 2 CAP0 2 pin 011 Start conversion when the edge selected by bit 27 occurs on P0 22 TD3 CAP0 0 MATO 0 pin 100 Start conversion when the edge selected by bit 27 occurs on MATO 1 101 Start conversion when the edge selected by bit 27 occurs on MATO 3 110 Start conversion when the edge selected by bit 27 occurs on MAT1 0 111 Start conversion when the edge selected by bit 27 occurs on MAT1 1 27 EDGE This bit is significant only when the START field contains 010 111 In these cases 0 1 Start conversion on a falling edge on the selected CAP MAT signal 0 Start conversion on a rising edge on the selected CAP MAT signal 31 28 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 16 5 Operation 16 5 1 H
8. rved User manual Rev 01 24 June 2005 195 Philips Semiconductors UM1 01 20 ja Volume 1 Chapter 16 A D Converter 16 4 2 A D Data Register ADODR 0xE003 4004 and AD1DR 0xE006 0004 Table 164 A D Data Register ADODR address 0xE003 4004 and AD1DR address 0xE006 0004 bit description Bit Symbol Description Reset value 5 0 Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined 15 6 V VREF When DONE is 1 this field contains a binary fraction representing the voltage on NA the Ain pin selected by the SEL field divided by the voltage on the Vppa pin Zero in the field indicates that the voltage on the Ain pin was less than equal to or close to that on Vssa while 0x3FF indicates that the voltage on Ain was close to equal to or greater than that on Vpr_er 23 16 Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined 26 24 CHN These bits contain the channel from which the LS bits were converted e g 000 NA identifies channel 0 001 channel 1 29 27 Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined 30 OVERUN This bit is 1 in burst mode if the results of one or more conversions was were lost 0 and overwritten before the conversion that produced the result in the LS bits In non FIFO operation
9. this bit is cleared by reading this register 31 DONE This bit is set to 1 when an A D conversion completes It is cleared when this 0 register is read and when the ADCR is written If the ADCR is written while a conversion is still in progress this bit is set and a new conversion is started 16 4 3 A D Global Start Register ADGSR 0xE003 4008 Software can write this register to simultaneously initiate conversions on both A D controllers This register is available in LPC2134 6 8 devices only Table 165 A D Global Start Register ADGSR address 0xE003 4008 bit description Bit Symbol Value Description Reset value 15 0 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 16 BURST 1 The AD converters do repeated conversions at the rate selected by their CLKS fields 0 scanning if necessary through the pins selected by 1s in their SEL field The first conversion after the start corresponds to the least significant 1 in the SEL field then higher numbered 1 bits pins if applicable Repeated conversions can be terminated by clearing this bit but the conversion that s in progress when this bit is cleared will be completed Important START bits must be 000 when BURST 1 or conversons will not start 0 Conversions are software controlled and require 11 clocks 23 17 Reserved user software should not write ones to reserved bits The value read f
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