FRS-HD-CHO / FRS-HD-CHO-ASI / ASI-CHO-2x1
Contents
1. sets the minimum frames delay Without a sync input present this sets the no of frames delay relative to the input nevion com 9 FRS HD CHO Rev K Switch Function Function DIPs Comment name 12 SDI OUT 1 Off through mode In through mode the video only On processed mode goes through a re clocker 13 SDI OUT 2 Off through mode In through mode the video only On processed mode goes through a re clocker 14 Video Generator Off Color bar This is the video generator signal On Black field that is shown when video is detected lost according to the fallback rule set in GYDA 15 RESET Off Use values preset by GYDA To reset both DIP 15 and DIP16 On RESET to factory defaults must be set on before powering on DIP 15 and 16 is read at power up The reset is not done until DIP 15 is set back to off and re powered 16 OVR Off GYDA mode This DIP is only read at power On Manual mode up OVR is short term for GYDA override Table 1 DIP SWITCH FUNCTIONS For the ASI CHO 2x1 PB only DIPs number 2 4 5 and 8 and 15 16 will have any effect The rest will be ignored and can be set to any position 3 2 Gyda mode All functions of the card can be controlled by the Multicon Gyda control system In Multicon Gyda the module has an information page and a configuration page 3 2 1 Information page The information page for ASI CHO 2x1 PB is a subset of the information page for FRS HD CH2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 kHz Mute c Ca a ICI F C CINC CN IN 3 All outputs have a common fallback option that can be set in Gyda The priorities can be selected between matrix being the choice in the cross point matrix sine mute or delete Mute is merely silence while Delete deletes any audio content and set the audio control package to channel delete for its respective channels Emb audio fallback 5 15 Audio generator Main Matrix Backup 1 Mute X C Sine C Mute C Delete The stereo audio generator is available in the audio cross point matrix as a source It is a high purity 1 kHz sine wave with a 250ms interruption on the left channel every 3 seconds The audio level may be set to one of two standards The two levels are 18 dBFS and 20 dBFS These two levels correspond to EBU R68 and SMPTE RP 155 5 16 Audio processing block The output of each stereo signal from the audio cross point matrix may be processed in the audio processing block This is controlled with the Gyda controller The processing includes channel L R manipulation and audio gain Audio processing ch 1 2 Audio processing ch 34 Audio processing ch 5 6 Audio processing ch 7 8 Audio processing ch 9 10 Audio processing ch 11 12 Audio processing ch 13 14 Audio processing ch 15 16 Mode LR y Level Level Level Level Level Level Level Level 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dB
3. 270Mbps w Belden 8281 with BER lt 10E 12 gt 130m 1485Mbps w Belden 1694A with BER lt 10E 12 gt 15dB 5MHz 1 485GHz gt 15dB 5MHz 742 5MHz gt 10dB 742 5MHz 1 485GHz SD limit 10Hz 1kHz gt 1 Ul 10kHz 5MHz gt 0 2 Ul HD limit 10Hz 100kHz gt 1 UI 100kHz 10MHz gt 0 2 Ul 75 Ohm BNC Black amp Burst Tri level gt 35dB O lt 10MHz 30dB lt 30MHz 4 75 Ohm BNC gt 15dB 5MHz 1 485GHz gt 15dB 5MHz 742 5MHz gt 100B 742 5MHz 1 485GHz gt 15dB 5MHz 742 5MHz gt 10d0B 742 5MHz 1 485GHz 800mV 10 SD limit 0 4ns 1 5ns lt 0 5ns rise fall var HD limit lt 270ps lt 100ps rise fall var lt 10 SD lt 0 2 Ul HD lt 1 Ul SD lt 0 15 Ul HD lt 0 2 Ul nevion com 6 FRS HD CHO Supported standards SD 270 Mbps HD 1485 Mbps DVB ASI Video switch point definition and sync EDH Video Payload Identification Other Power consumption Rev K SMPTE 259M SMPTE 272M AC SMPTE 292M SMPTE 274M SMPTE 291M SMPTE 296M SMPTE 299M 50083 9 error detection according to ETR290 1 1 and 1 2 SMPTE RP168 tri level SMPTE 170m ITU R BT 470 Compliant to SMPTE RP165 SMPTE 352M 2002 3 5W O 5V 1 2W 15V 1 The ASI support can be purchased as an optional upgrade nevion com 7 FRS HD CHO Rev K 3 Configuration The board can be configured both manually and through the system controller Multicon Gyda However only a few of the confi
4. APVF Active picture video freeze detected TCF Time code freeze detected BLK Black video detected below set threshold The black detect threshold is an integer between 0 and 255 Selecting a threshold of 10 will accept everything below 74 04Ah luma and between 10 and 10 1F6h and 206h chroma as black The silence threshold can be adjusted in 6dB steps from 90aB to 18dB Audio in silence trigger and APVF and silence trigger share the same silence threshold setting It can only be adjusted from the Audio in silence trigger The threshold value in APVF and silence trigger will always display as 0 and the threshold value in Audio in silence trigger is always the one used by the module 5 4 De glitcher The de glitcher corrects timing errors within a line The de glitcher has a 2048 samples buffer When the first signal is present we call it the initial phase signal data is taken from the centre of this buffer If the timing reference of the video signal changes when for instance a new source being switched into the signal path the timing errors occurring by this change will be corrected if the new timing reference is within 1024 samples of the initial phase signal This also goes for all consecutive timing references nevion com 18 FRS HD CHO Rev K If a signal is more than 1024 samples off relative to the initial phase signal the output will repeat the last fra
5. DIP switch of the vertical DIP package is number 9 Switch Function Function DIPs Comment name 1 ASI SDI input Off input is SDI FRS HD CHO ASI only mode On input is ASI Note Firmware older than ver FRS HD CHO For valid ASI output DIP12 and or 1 10 use this DIP for a latch ASI only DIP13 must also be set to the on off input setting Through position 2 CHO priority Off In1 On In2 3 Reserved Note Firmware older than ver 1 10 use this DIP for selection between Loss Of Signal and Loss Of Lock 4 5 Lock amp Hold time DIP 5 6 Off Off gt Only valid if latch is on Minimum DIP 5 6 Off On gt 1s DIP 5 6 On Off gt 4s DIP 5 6 On On gt Reserved 6 Audio gen Off 1kHz Sine On Black sound T Emb enable Off No audio embedded When off the audio is left un On Audio embedded touched on the SDI stream When on the audio configured to be embedded is embedded into the SDI 8 GPIO setup Off SDI CHO 2x1 mode See the GPI input output On FRS HD SDI mode description below 9 11 Frame delay DIP 9 10 11 Off Off Off gt 0 With a sync input present this frms DIP 9 10 11 Off Off On gt 1 frms DIP 9 10 11 Off On Off gt 2 frms DIP 9 10 11 Off On On gt 3 frms DIP 9 10 11 On Off Off gt 4 frms DIP 9 10 11 On Off On gt 5 frms DIP 9 10 11 On On Off gt 6 frms DIP 9 10 11 On On On gt 7 frms
6. card is freshly ONLY FOUND in ovr programmed by the bootloader Conf 0 and the program is still un finalized fin is the normal condition ovr if DIP switch 16 is set to the ON position and the card is under DIP switch control Note 1 The info part of misc has additional functionality when locate is used locating lt remaining seconds gt This enables a visible countdown clock in Gyda but is not a required part of FLP400 6 2 Normal control blocks Blo Bik Commands Example Response Control ck ceq 0 l ceq 0 cd ncd cable equalizer for electrical input 1 No control only used to report carry detect or not carry detect ceq 1 l ceq 0 cd ncd cable equalizer for electrical input 2 No control only used to report carry detect or not carry detect cho O pri lt k gt cho 0 pri 0 size 5 pri k m auto t1 Video input select pri lt k gt lt l gt cho pri 0 1 lt hold time gt t2 lt lock pri lt k gt lt l gt lt m gt cho pri 10 2 time gt pri a prioritized list of inputs used when pos man lt k gt pos auto latch reset t1 lt hold_time gt t2 lt lock_time gt cho 0 pos man 1 cho 0 pos auto cho 0 latch reset cho 0 t1 1000 cho 0 t2 1000 size 5 pri k m man m t1 lt hold time gt t2 lt lock time gt change over is automatic The list can have 1 2 or 3 entries or levels Manual mode is effectively the same as automatic mode
7. diagram ch 1 1 replaced kill with mute as audio fallback ch 5 13 replaced misleading figures on sync ch 5 4 1 3 2 2009 05 12 RS Corrected cable equalization spec on inputs Added a requirement of termination of unused 2 1 05 SHH AS SDI inputs outputs in chapter 3 3 Updated document with Label generator and 1 03 HH A 2009 03 03 corrected an error in the mtx 0 description 0 B 2008 12 15 NBS First release of product B A 2008 12 04 SHH Re written and new Gyda features included A 2008 10 17 SHH Initial release nevion com 2 FRS HD CHO Rev K Contents POUM caeeyaara ade EE T ATE EE 4 151 Product descripto n rena e eae e a aE E AE ee a lcd al ci 4 2 SPOON GANONG irea O 6 3 Configuratio N e e e aude EE EE eE RE R AE OE E E EER abet pba ae 8 3 1 Manual moden asii let 8 E O 10 30 GOMMOGIONS estoi 12 SAS MIN PU tn A td e o a 12 O beta da seh acadee ule sib E EE A EER ead EEE seen E aiden phen EER E 13 4 1 Front panel LED ICA di iii 13 42 GIP VALAIS tna a aE E a A E AE E E E E 13 5F rnct nal descripti OMe ida oia 15 5 1 Selection of input signal type FRS HD CHO ASI only cooocconcccccoccccncncnonanananancnonannnnnannns 15 52 Socia Pal setas stand taa atada 15 A O ee ee dase 15 54 DS CNC GT caret ces tia E S 18 So Frame SYNC ON Z ON ae aa deh recs olor a aa 19 5 6 Video gengratOr cocida 23 5 7 Label GenGraion a a a a a aE 24 5 8 Video OI as 24 SQ ED
8. effect one moves the delay window start this is equivalent with setting of the video delay to a larger value Let us assume that the video delay is set to 2 frames 200 lines In that case the outgoing video will be between 2 frames 200 lines and 3 frames 200 lines delayed with respect to the incoming video For convenience let us assume that the incoming video is iso synchronous but that it lags 25 lines after the sync Let us also assume that the phase delay is set to 60 samples We will then have the situation shown in Figure 14 3 Frames 25 lines i 60 samples i l Outgoing video I l l l l l l Incoming video A 2 19 l l l l I I l I sync 1 1 l l isync I tot l I Ko oo 60 t mis 25 lines Figure 14 Another example of delayed outgoing video nevion com 21 FRS HD CHO Rev K To reiterate The phase delay can be both positive and negative and sets the difference between the phase of the sync input and the video output The video delay sets the delay between video output and video input However the actual delay might be longer as it also needs to phase up to the sync input The actual delay may be up to 1 frame longer than the minimum video delay The user may specify a video delay between 2 lines min and 7 frames max The two parameters allow a user to delay the incoming video and refere
9. lt threshold gt trig 3 msk 0x13 trig O dis trig 2 t1 1000 trig 6 Ivl O 65 en msk 0x0 t1 0x2710 lvl O 66 Triggers for synchronous switching The trig blocks responsible for the synchronous switching between the electrical inputs Each trig block has it s own hold time and a mask that select which bits should be taken into account and if these bits should be or ed or and ed together Some bits may have a user selectable threshold values In the case that one threshold is valid for several bits the lowest bit number is used For instance silence threshold in Audio in silence trigger is valid for all 8 bits but the command targets bit 0 only For bit masks see chapter 5 3 on input selection and triggers supr en dis auto lb lt page gt lt L1 gt lt L2 gt lt L16 gt font lt tag gt supr 0 auto supr 0 Ibl 0 65 66 67 0 supr 0 font 1252 Supr 0 en font 0x4e4 lb 0 86 73 68 69 79 10 76 65 66 69 76 Label generator A label generator can be superimposed on the video The setting en means it is always superimposed dis means it is nevion com 33 FRS HD CHO Rev K never superimposed and auto means it is superimposed on the internal video generator only The text in the label can be set or modified by the lb lt page gt sub command where page is 0 to operate on letters 1 16 or 1 to operate on the letters 17 32 The
10. not status absent present but signal in lock been card not able to programmed lock VCXO Sync input Sync signal Sync signal B amp B or Tri Module has not status absent present but level sync in been card unable to lock programmed lock VCXO Audio input No audio One two or 4 audio groups Module has not status embedded in three audio embedded in been incoming video groups incoming video programmed embedded in incoming video A few special conditions exist for the LEDs When upgrading the module s FPGA software there a transfer stage followed by an unpacking stage During the unpacking the LEDs will display a running lights pattern three orange LEDs and one unlit LED When running a Locate command all four LEDs will flash slowly between orange and unlit When running the module in manual mode the two push buttons can be used to set the sample part of the phase delay When the end of the adjustment range is reached the closest LED will flicker briefly Returning to O samples by pressing both push buttons simultaneously will be acknowledged by the two middle LEDs flickering briefly 4 2 GPI alarms The FRS HD CHO can have the GPI outputs to be setup as change over style or frame sync style either by DIP8 or by Multicon Gyda control In the graphical user interface of Multicon Gyda the selector looks like this GPIO mode C FRS HD DMUX compatible SDI CHO 2x1 compatible The selecti
11. of the group into the ancillary area acp on off This is valid only for SD and enables the audio control package use24 on off This is only valid for SD and selects between 24bit and 20bit sound del off on delay12 delay34 For each of the embedder groups the delay bits for ch1 2 and for ch3 4 can be inserted into the ACP The delay value can be positive and negative and is put directly into the ACP as it is written Note To set both delays to 0 would be the same as turning the delays off The response reflects this nevion com 31 FRS HD CHO Rev K dem 0 3 demb 0 grp ken Audio de embedders b demb 2 one permanently assigned to each incoming group always enabled No control available vprc O Iglz on vprc 0 lglz on Video processing block lglz off vprc 0 lgliz off Gain and offset are both signed fixed vprc 0 y 8192 0 point numbers Gain is in 2 13 format y cb cr lt gain gt vprc 0 cb 2000 0 while offset for Y and the chroma lt offset gt vpre O cr 1000 1000 channels are given in 10 2 and 9 2 respectively Gain range is 0 32767 Gain ox 0 Gain 1x 8192 Gain 4x 32767 Luma Offset range is 4095 4095 Offset o 0 Chroma Offset range is 2047 2047 Offset o 0 sync 0 sync 0 lol lock trilvl bb Frequency reference for video output sdi Status only no commands available dly 0 lt frames gt frms dly 0 2frms tgt lt fram
12. setting A short cut to set change overs 2 11 all at once Will of course not report anything in info that s left to the individual cho blocks gpi O act inact gpi O act gpi 0 inact EDH insert select This gpi works as a simple 2 1 switch inact EDH off act EDHon gpi 1 act inact gpi 1 act gpi 1 inact GPO compatibility modus This gpi works as a simple 2 1 switch inact GPOs are pin compatible with the FRS HD DMUX range act GPOs are pin compatible with the earlier SDI CHO 2X1 range gpi 2 lact inact gpi 1 act gpi 1 inact Input signal type Available from MCU firmware 1 10 and then only for FRS HD CHO ASI i e if the optional ASI functionality has been purchased This gpi works as a simple 2 1 switch inact The module expects SDI input and behaves just like the FRS HD CHO act The module expects ASI input SDI input will still be accepted but all SDI processing blocks will be bypassed rel 0 rcl O lock lol Reclocker No control only used to report lock status emb 0 3 en dis del off on acp on off use24 on off lt del12 gt lt del34 gt emb 0 en emb 2 dis emb 1 acp on emb 3 acp off emb 1 use24 on emb 2 use24 off emb 0 del off emb 2 del on 54 432 en dis use24 on off acp on off del off on lt del12 gt lt del34 gt Audio embedder block en dis Enables or disables the embedding
13. the sync signal The parameter really determines a delay on an internal sync signal isync The output is synchronous with isync see Figure 11 Positive output t le phase delay gt Figure 11 Positive phase delay Figure 11 show how the sync signal and the isync signal would look on an oscilloscope if converted to analogue signals The delay of isync can be given in frames lines and samples The delay can be negative see Figure 12 5 Note that isync is not a physical entity but a term used in this context to explain the delay process and the use of the configurable parameters related to this process nevion com 19 FRS HD CHO Rev K Negative output t le phase delay gt Figure 12 Negative phase delay The phase delay can thus be written in several ways a large positive delay will equal a small negative delay because there is wrap around on a frame basis lt follows that it is not useful to specify a phase delay larger than 1 frame Strictly speaking the range could have been limited to 1 2 frame to 1 2 frame For convenience the delay range is allowed to be from 1 frame 1100 samples to 1 frame 1100 samples In order for FRS HD DMUX to honor the phase delay setting it should ideally delay the incoming video between 0 to 1 frames Because the processing delay through the card is 2 lines minimum the actual window is between 2 lines and 1 frame 2 lines Hence with the parameter minimum video de
14. 9 The available triggers and their masks nevion com 17 FRS HD CHO Rev K Term Description Term Description Video error trigger Audio error trigger group 1 4 APV Active picture CRC invalid Ch 1 Channel 1 set inactive in audio control 2 3 4 package FFV Full frame CRC invalid Group Audio group missing in audio trigger 1 2 3 4 group group 1 2 3 4 EDH EDH package missing SD only ACP Audio control package missing VSTD Video standard error U O Audio underflow overflow ch 1 4 FFCRC Full frame CRC error SD only BCH Audio CRC error APCRC Active picture CRC error SD only 48kHz Sampling rate different from 48kHz detected LOCK Loss of re clocker lock Audio in silence trigger CCS Chroma checksum error Ch1 2 3 Audio level received in channel 1 and 2 4 15 16 below set silence threshold YCS Luma checksum error Audio out clipping trigger CCRC Chroma CRC HD only Ch1 2 3 Audio out after audio processing gain 4 15 16 is clipped YCRC Luma CRC HD only APVF and silence trigger LNUM Line numbering error HD only Ch1 2 3 Audio level received in channel 1 and 2 4 15 16 below set silence threshold while active picture video freeze is also detected SAV Start of active video error EAV End of active video error Video content trigger VCLP Video clipping detected by legalizer FFVF Full frame video freeze detected
15. CHO Rev K Product Warranty The warranty terms and conditions for the product s covered by this manual follow the General Sales Conditions by Nevion which are available on the company web site www nevion com nevion com 37 FRS HD CHO Rev K Appendix A Materials declaration and recycling information A 1 Materials declaration For product sold into China after 1st March 2007 we comply with the Administrative Measure on the Control of Pollution by Electronic Information Products In the first stage of this legislation content of six hazardous materials has to be declared The table below shows the required information Toxic or hazardous substances and elements RAB a R B ASME SRK 2R Part Name Lead Mercury Cadmium Hexavalent Polybrominated Polybrominated Pb Hg Cd Chromium biphenyls diphenyl ethers Cr VI PBB PBDE FRS HD CHO FRS HD CHO ASI O O O O O O ASI CHO 2x1 PB O Indicates that this toxic or hazardous substance contained in all of the homogeneous materials for this part is below the limit requirement in SJ T1 1363 2006 X Indicates that this toxic or hazardous substance contained in at least one of the homogeneous materials used for this part is above the limit requirement in SJU T 11363 2006 This is indicated by the product marking A 2 Recycling information Nevion provides assistance to customers and recyclers through our web site htt
16. H processing DIO de De ee da 25 5 10 Video output selection esla 25 5 1T A dio blocks ONIS W ica id ll 25 5 12 Audio de embedder acota 26 5 13 Au dio delay coins 26 5 14 Audio cross Poma Edi 27 Bel AUGIO generato rnt tdi 27 5 16 A dio Processind Block aktrisa Aaa 27 5 17 ARAUCO MOSS k ers a raaraa A aE E aara i EEA e aan 28 6 R8422 COIN AS e a aa eee teh 29 6 1 FLPA O required COMMAS css artis at vevtowndi vreecarncwecuntiun ee 29 6 2 Normal control IOC KS atacarlo rte 30 6 3 Commands intended for debug lab use ONly ooononnooccccnnnccccnnonanaccncnonnncnnnannnncnnnonancnnnnnos 35 General environmental requirements for Nevion equipMeMt oocccconncnccccccnncccnnnnanancccnoncnnnnnnnns 36 Pr d ct Wars tit 37 Appendix A Materials declaration and recycling information ooocconnnncnncccccnnnccnnnncanaccccnnnnnns 38 nevion com 3 FRS HD CHO Rev K 1 Product overview lr HD SD 7 A l SDI eq 2x1 Reclocker switch deserializer D Electrical input 1 IN SDI out1 01 SDI out2 Electrical input 2 IN2 02 Deserializer reclocker pen SDI out2 FRS HD CHO C1 02 FRS HD CHO C1 backplane Audio deembedder and reembedder backplane Sync in Sync out Remote control GPI VO Microcontroller Figure 1 Simplified block diagram of the FRS HD CHO card 1 1 Product description The base version of the Flashlink FRS HD CHO is a 2x1 HD SD change over module with a frame synchronizer
17. O which in turn is a subset of the information page for FRS HD CHO ASI While the FRS HD CHO and FRS HD CHO ASI only differ in that the latter has an extra line for Input signal type the ASI CHO 2x1 PB information page is quite reduced because the frame synchronizer and audio embedder d embedder functionality quite simply isn t included The difference between Figure 3 and Figure 4 should make this clear The following paragraphs will describe the information page for FRS HD CHO ASI but as far the mentioned items are also present in the ASI CHO 2x1 PB information page the description will apply for that product version as well The information page shows a dynamic block diagram of the board and some additional information in textual form The block diagram updates with the boards status showing input signal selected signals missing by red crosses over signal lines and routing through switches It also shows the audio matrix selections that have been made on the configuration page Note that if embedded audio is missing from a group the user will still be allowed to select those inputs in the matrix but the output will go to a fallback position Missing audio channels will be shown in the block diagram with a red cross over the matrix input line The text on the information page gives information about functionality not displayed on the dynamic block diagram The video delay represents the actual delay between input and o
18. ality with switching criteria Video integrity check Audio integrity check Video freeze detect full frame or active area Video black detect with adjustable black threshold Time code freeze Audio silence detect with adjustable silence threshold Latched switching Ripple rejection latching with adjustable hold times Switching between inputs on switching line GPI inputs for external control of switch Individual detection timings for video signal integrity audio signal integrity video content and audio content HD SD frame sync delay 8 frames max luma chroma gain and level adjustment Audio delay enabling Dolby E processing delay correction Audio router for embedded audio Embedded audio gain adjustment Audio fade out fade in at switching or frame wrap SDI Label inserter EDH processing nevion com 5 FRS HD CHO 2 Specifications Electrical SDI input Number of inputs Connectors Equalization Input Return loss Active input Input Return loss passive bypass Jitter tolerance Electrical Sync input Connector Format Input Return loss Electrical SDI outputs Number of outputs Connectors Return Loss 01 O2 Active output Output Return loss 01 O2 Passive bypass Return loss 01 102 Output signal level Output signal rise fall time 20 80 Amplitude overshoot Output timing jitter Output alignment jitter Rev K 2 75 Ohm BNG Automatic gt 300m
19. c signal reappears the delay mode will change back to Frame Sync mode Hence the internal clock will be locked to the sync signal and the delay will again change NOTE This will result in a frame roll as the delay changes If both signals disappears The picture will first freeze for lt hold time gt and then go to video generator The output is now referenced to the local clock source However this clock source will be kept within 1 ppm of the last sync source 5 5 2 Frame delay mode In this mode a sync signal is not present The delay set is then directly related to the incoming video 1 frame and 1 line delay means that the output will be 1 frame and 1 line delayed version of the input If video signal disappears The picture will first freeze lt hold time gt and then go to video generator The output is now referenced to the local clock source However this clock source will be kept within 1 ppm of the last video source If video signal reappears If the input video signal reappears the video will reappear on the output lt ock time gt after stable input video The delay will be set to the same delay as before loosing input NOTE This may cause a frame roll If a sync input appears Given that a stable SDI input exists If a sync signal appears the delay mode will change to Frame Sync mode see Chapter 5 5 1 Hence the internal clock will be locked to the sync signal and the delay will again change NOTE This will result
20. d is 1080i25 a delay of one line is equal to 35 5us If the output SDI standard is 720p50 a delay of one line is equal to 26 6us If the output SDI standard is 625i25 a delay of one line is equal to 64us For a scenario where the card receives different HD video standards e g 1080125 and 720p50 the user may want to conserve a specific delay in microseconds for all HD video standards This is accomplished by specifying the delay in number of samples instead of frames and lines For HD video standards the sample frequency is equal over standards but the line and frame frequencies are different for the different standards If video input disappears Given that stable SDI input and sync input exists If the SDI input disappears the picture will freeze for lt hold time gt and then go to video generator if the card is in default configuration When the SDI input disappears the Frame Delay pulses at the back plane will also disappear If video input reappears Given stable sync input the video will reappear after lt ock time gt of locked video input if card is in default settings If sync input disappears nevion com 22 FRS HD CHO Rev K Given that stable SDI input and sync input exists If the sync signal disappears the card will act as in frame delay mode see Chapter 5 5 2 NOTE This will result in a frame roll as the delay changes If sync input reappears Given that a stable SDI input exists If the syn
21. dB dB Feo dB dB dB dB dB Figure 24 The figure shows the Gyda configuration view of the audio processing block nevion com 27 FRS HD CHO Rev K Channel L R manipulation The stereo signals may be output in one of the following ways LR Left Right No change RL Right Left Channels are swapped LL Left Left Left channel is copied into the right channel RR Right Right Right channel is copied into the left channel NLR VLeft Right The left channel is phase inverted LnR Left VRight The right channel is phase inverted MM Left Right 2 The left and right channels are summed MS MS AB The left and right channels are converted from AB stereo to MS stereo The sum products L R 2 and MS are reduced in level by 6 dB to avoid any possibility of clipping Audio gain Audio gain is a 16 bit value that can be set for each stereo pair going into the audio processing block The actual gain is the 16bit value 100dB The gain range is set to 96dB 96dB with a gain step of 0 1dB Note that non audio data is ignored and left unchanged by the gain function 5 17 Audio embedder Audio emb ch 14 Enable Disable Acp On Off 24 bit 20 bit Audio emb ch 58 Enable Disable Acp On Off 24 bit 20 bit Audio emb ch 9 12 Enable Disable Acp On Off 24 bit 20 bit Audio emb ch 13 16 Enable Disable Acp On Off 24 bit 20 bit Fig
22. deo standard seen by the module 3 1 2 Slide switch The slide switch on the lower right side of the card selects between backplane sync input BP and Flashlink rack distributed sync RACK The rack distributed sync is a future feature upgrade of the Flashlink frame and at present the switch should always be set to its lower position to BP 3 1 3 Factory reset function The factory reset function restores the module to its default settings These settings are just a start condition for the board and changes done by the user will still take effect and be stored nevion com 8 FRS HD CHO Rev K The factory reset is initiated by setting DIPs 15 and 16 to the On position and booting the module All inputs signals should be removed The status LED will stay permanently orange and the module will not complete its start up DIP 15 should then be returned to the Off position while DIP 16 should be set to the desired mode of operation before the module is booted again This starts the actual internal reset process and the module should now be left powered for at least 10 seconds or the complete set of default setting may not be stored properly If necessary the reset operation can be performed multiple times 3 1 4 DIP switch functions The two sets of DIP switches are labeled with a number running from 1 to 15 The 16 DIP is labeled OVR Note that the left DIP switch of the horizontal DIP package is number 1 The top
23. es gt frms Video delay lt lines gt lines dly 0 2lines 30sps lt lines gt lines This sets the minimum video delay of lt samples gt sps dly 0 Ofrms 50sps lt samples gt sps the card dly 0 Ofrms 3lines In info this block reports back the current 50sps delay in nanoseconds This will vary with the incoming video standard dly 1 lt audio_samples gt s dly 1 30sps tgt lt audio_samples gt audio delay ps sps The audio delay is given in audio samples Audio delay is always given relative to video dly 2 lt lines gt lines dly 2 1lines 30sps phase lt lines gt lines Video phase lt samples gt sps lt samples gt sps If lines 0 the resulting phase will vary with incoming video standard see dly 0 above vge O cbar vgen 0 cbar video Internal video generator n chkfield lt Ins gt lt rate gt lt scan gt The video generator will be activated in white wss auto off on two different ways If selected as a yellow lt wss_value gt cbar fallback option the generator will cyan chkfield white yellow generate the selected pattern when the green cyan green other input s are missing and then use magenta vgen 0 flat 200 0 100 magenta red blue the video settings from the last external red vgen 0 video black flat lt Y gt lt Cb gt source present lt can also be selected blue 1080 24p lt Cr gt as the main input in cho 1 in which case black vgen 0 video its own video settin
24. es lo samples Relative audio delay 960 samples Figure 21 Gyda view of the delay settings The video is delayed 1 frames compared with the audio for a 50Hz signal Audio embedder bypass C Enable Disable Audio emb ch 14 Enable Disable Acp COn Of 24bit 20 bit Audio emb ch 54 Enable Disable Acp On Of 24bit C20bit Audio emb ch 9 12 Enable Disable Acp On Off 24bit 20 bit Audio emb ch 13 16 Enable Disable Acp On Off 24bit 20 bit Figure 22 Gyda view of the audio embedder settings To calculate number of audio samples frame simply divide 48000 with frame rate 24Hz 25Hz 29 97Hz 30Hz 50Hz 59 94Hz or 60Hz nevion com 26 FRS HD CHO 5 14 Audio cross point matrix Rev K The audio cross point matrix is an 8x10 cross point with inputs and outputs as shown in Figure 20 The 8 de embedded channels a 1 kHz sine and black sound are selectable inputs Black sound is explained in Chapter 5 2 The outputs of the cross points are 8 stereo channels for re embedding Audio matrix Group 1 Group 2 Group 3 Emb ch 1 2 o e Emb ch 3 4 CI Emb ch 5 6 Cos Emb ch 7 8 ees Embch9 10 COC Ember 20 eat ee Embch13 14 C Emb ch 15 16 Figure 23 Gyda configuration view of the audio cross point matrix C O e e e c o e o 9 ee ce e Group 4 IN ICI II e eeeereee gt Generator
25. ew of input 1 selected in manual mode Automatic selection mode Main input Electrical 1 vj Video in Mode Auto Backup 1 Electrical 2 Backup 2 Video gen Latch Reset Hold time 3000 ms Lock time 3000 ms Figure 8 Gyda view of the input selection If in Gyda the video in mode choice is set to auto three input choices can be made for three priorities electrical 1 electrical 2 or mute generator When signal is missing on one priority the change over will switch to the next priority and look for signal If only two priorities are needed i e one main and a fallback the third priority can be disabled by setting it to Note that the ASI CHO 2x1 PB product version does not have the Video gen and Mute choices Because no version of the FRS HD CHO has a built in ASI generator no fallback is available when using ASI input signals This is also true for the FRS HD CHO ASI Even though the Video gen and Mute choices are available regardless of the selected mode SDI or ASI no actual fallback will be available for lost ASI sources Hold time and lock time controls how long a signal can be missing before the next priority is used and how long a signal has to be present before it is considered to be OK again This module is always latching which means that is doesn t switch from a fallback back to the main input unless it is either ordered to do so the latch reset button or if the fallback signal also d
26. gs will also be used 1080 25p flat lt Y gt lt Cb gt lt Cr gt vgen 0 video 1080 25i video vgen 0 video lt Ins gt lt rate gt lt scan gt 1080 29i vgen 0 video wss autoloff on 1080 30i lt wss_val gt vgen 0 video 720 24p vgen 0 video 720 25p vgen 0 video 720 29p vgen 0 video 720 30p vgen 0 wss auto vgen 0 wss on 7 edh O msk lt 24b _mask gt edh 0 msk OxFE0005 msk lt 24b_mask gt Error detection and handling reset edh 0 reset Error counting The count itself is reported in info Errors can be masked off and not counted this is the purpose of the mask The counter itself is 16b and will wrap around but can also be reset by issuing reset nevion com 32 FRS HD CHO mtx lt i1 gt lt 01 gt lt iN gt lt oN gt lt i1 gt lt 01 gt lt 02 gt lt oN gt lt i1 gt lt 01 gt lt 02 gt or the above combined mix0021455 mtx000 11 22 mtx 0 0 0 9 mtx 0 0 0 1 122 7 size M N i1 i2 i3 iN Rev K Audio matrix mtx 0 size 10 8 controls the audio matrix outputs 0 7 are embedded sound inputs 0 7 are de embedded audio 8 1kHz sine 9 Black silence Note Any combination of the three basic commands are allowed for instance the following command to set up a 10x10 audio matrix in a single line mtx0112230 3 7 gt mtx 0 size 10 103 12333333 mtx lt i1 gt lt 01 gt lt i2 gt lt 02 gt lt i1 gt lt 01 gt lt 02 gt mi
27. gurable parameters are available when operating in manual mode 3 1 Manual mode To reach manual mode DIP16 labeled OVR on the board must be switched on to the right and the board must be re booted This takes the board out of Multicon Gyda control if it was previously set to off and a number of the module s features will be controlled directly by the other DIP switches the rotary switch and the two pushbuttons Settings not controlled by any of these switches are kept unchanged from previous session factory setup or Gyda setup The Manual Mode configuration controls are all found on the front side of the board There are two sets of DIP switches one rotary switch and two push buttons The slide switch on the lower right is used to select sync source for both modes of operation see 3 1 2 below JJLLLLLL muy metwork 20 o e e les O88 OC vel oo e f Figure 2 The figure shows a top view component printout of the board LEDs push buttons the rotary switch and the 2 sets of DIP switches are colorized 3 1 1 Rotary switch and push buttons The rotary switch labeled DLY adjusts the phase delay by 5 to 4 video lines It is only functional when a sync signal black amp burst or tri level is present at the sync input The rotary switch is accessible from the front of the rack The push buttons labeled INC and DEC are used to fine adjust the phase delay by samples It can adjust within video line for the vi
28. her routed directly from the re clocker or routed through the processing unit SDI outputs Input Through Processed SDI out 1 SDI out 2 Figure 18 Gyda view of SDI output selection block When processed is selected it is possible to either output video generator or mute the output This is done at the video in mode by selecting Video gen or Mute This will not have any effect on outputs set in through mode x Video in Latch Reset Figure 19 Gyda view of video input mode 5 11 Audio blocks overview To audio em bedder Audio Processing Audio De em bedder Gain LR RL swap Figure 20 Audio function blocks nevion com 25 FRS HD CHO Rev K 5 12 Audio de embedder The Audio de embedder extracts all audio embedded in the video stream The de embedder is always enabled 5 13 Audio delay An audio delay relative to the video output can be specified commonly for all de embedded channels This is done in Gyda The audio delay is specified in audio samples relative to the output video and can be both positive and negative Note that as the audio delay is relative to the video output it is possible to specify an audio delay that will be an actual negative delay This will cause audio errors The negative audio delay is limited by the positive video delay Since the audio delay is always relative to the video the only way to give the audio a negative delay is to delay the video by a posi
29. ic settings only will usually not be included see conf above chk off chk off ok Checksum off If issued twice in succession this command will disable checksums Note Responses will still have the checksums appended NOTE1 command turns the checksum back on locate on lt seconds gt locate off locate on 3 locate off ok Card locator This command will cause all the LEDs to flash for a user specified number of seconds If omitted the value lt seconds gt will be set to a default of 120 seconds The flashing can be terminated at any time with locate off address address address lt address gt Card address This command will check and update the card s current rack and slot address which is normally only done at start up filename filename frshdcho 0 105 ffw filename frshdcho 0 100 mfw lt name gt lt extension gt Firmware upgrades The lt name gt part must match the card s hardware and include a revision number and the extension must be either ffw for FPGA firmware or mfw for microcontroller firmware After running this command the board will wait for the firmware in Intel hex format nevion com 29 FRS HD CHO Rev K fin fin ok Finalize Finalize the programming of the microcontroller See description of the uC bootloader separate document misc 0 NOT AVAILABLE prog fin Misc info BY COMMAND prog if the
30. in a frame roll as the delay changes 5 6 Video generator The video generator can produce several simple signals Color bar Check field and flat field The flat field is possible to set up with 10bit 0 1023 luma and chroma values or by selecting a color The generator may be used as the video source if there is no video signal present at either of the video inputs The generator may also be switched on with Gyda This will override video input but the generator signal will be locked to the input nevion com 23 FRS HD CHO Rev K Wideo format 576 251 y Pattern C Flat 0 Cho ero Select pattern Video generator Colorbar motion Chkfield Figure 15 Gyda view of the video generator 5 7 Label generator The label generator consist of 2 lines of 16 characters each that are placed at the lower left corner of the active area Its main function enables the user to automatically add a label to the internal generator at loss of input signal It is done by selecting the auto tick box on the Label gen block in the Gyda configuration It is also possible to insert the label to the incoming SDI by ticking on the On tick box Note that to see the label on an output the video output selection must be set to processed for this specific output C Enable Disable Auto Label generator VIDEO LABEL Figure 16 Gyda view of label generator 4 5 8 Video processing block The video p
31. isappears Triggers In addition to the loss of signal and lock detect there are a set of triggers that can force the switching to next priority Equal types of triggers are grouped together in a trigger block A trigger block consists of a switching enable signal a trigger selection mask a Boolean operator a hold time and a threshold The trigger block always report status of all triggers inside the trigger block The switching enable signal enable disable radio button enables the trigger to do a switch between the inputs after detecting a continuously present error over a hold time The trigger selection mask selects which detections are enabled to do switching The Boolean operator is either and or or It controls whether the switching should be based on either or or all and of the selected triggers in the trigger selection mask The trigger to switch time is the time that a trigger must be continuously present before a switching of the inputs will happen 4 The processed video out block selects whether the output goes to mute or generator at loss of signal nevion com 16 FRS HD CHO Rev K Level is number to set a threshold for a content check The format of the levels will differ between trigger blocks Not all trigger blocks have a threshold The trigger blocks for the FRS HD CHO are video error trigger block video content trigger block audio error trigger block 1 4 audio i
32. lay set to 2 lines the least number possible for the parameter the output video will be between 2 lines and 1 frame 2 lines delayed with respect to the incoming video A common occurrence in practical use is to synchronize an incoming video with a sync but to let the outgoing video lead some samples or lines to the sync This can easily be accomplished Say that we want the outgoing video to occur 50 samples before the sync We will then set the phase delay to 50 samples and the v deo delay parameter to 2 lines For convenience let us assume that the incoming video is iso synchronous but that it lags 20 lines after the sync We will then have the situation shown in Figure 13 Note that the numbers in circles in the next figures are visualizing the video frames nevion com 20 FRS HD CHO Rev K 1 Frame Delay of outgoing video with respect to incoming video 20 lines E 50 samples i Outgoing video 2 ZO 9 Incoming video sync isync 50 t le gt k20 lines gt samples Figure 13 Example of delayed outgoing video To match larger processing delays one will want to first delay the incoming video and then synchronize the video This is equivalent to introducing a delay line for the incoming video and then synchronizing the output of the delay line to the sync In
33. letters follow as a string of ASCII numbers To write more than 16 letters two commands must be issued A string is always terminated at an ASCII 0 and ASCII 10 is linefeed new line Only the first ASCII 10 will be honored In the second example command the label string is set to ABC and terminated with ASCII 0 If not terminated the command would ve modified the first 3 letters of the string but any remains of a previous string would still be present until ASCII O or 33 letter encountered Note 1 When the flash is busy programming the FPGA or is being programmed with new FPGA code label information can not be updated Note 2 At the present only one font codepage codepage 1252 is included in the module nevion com 34 FRS HD CHO Rev K 6 3 Commands intended for debug lab use only Block BIk Commands example Response Control spi on off spi on spi off used to isolate the uC spi off from the SPI lines during programming of the flash by external programmer spi on must be issued in order to re enable normal card operation with the uC as the SPI master spir lt address gt spir 0x0004 Read a single word or byte from a SPI registers Addressing is 16b and most significant nibble determines which chip These are the address ranges 0x0000 OxOfff Reserved audio DAC not present in FRS HD CHO 0x1000 Ox1fff FPGA 0x2000 0x2fff flash 0x3000 OxSfff dese
34. me refill the 2048 samples buffer and take out data from the centre of the buffer This new signal is now considered the initial phase signal Audio will fade out when a frame repeat is being done and fade in at the new frame Hence it produces an error free video output without frame wrapping when the video input comes from a router with synchronous input video signals that all lies within 1024 samples of each other The de glitcher output is always seamless When a signal is repeated the audio is faded out It fades in at the new frame 5 5 Frame synchronizer The frame synchronizer consists of a frame store buffer and some control logic The frame store buffer can store up to 8 full HD frames Data is fetched from this buffer according to the user settings by force of the control logic The control logic sets the frame synchronizer into different modes dependent on the presence of a sync input 5 5 1 Frame sync mode If a sync input B amp B or Tri level is present the frame synchronizer will output a signal that has a delay relative to this signal Two parameters can be set Phase delay and Video delay Phase delay lo lines 0 samples Video delay 2 frames 0 lines lo samples Figure 10 Gyda view of the video delay settings Let us first focus on the phase delay which also may be called output phase delay This parameter can be positive or negative and determines the relationship between the outgoing video and
35. n 5 1 Selection of input signal type FRS HD CHO ASI only If the optional ASI upgrade has been purchased the top of the configuration page will be a selector between SDI input mode and ASI input mode In ASI mode the module will not lock to a non ASI SDI signal The ASI signal will not pass through the FPGA it will only be passed to the FPGA enabling the FPGA to look for valid ASI data In order to get an output in ASI mode the video output must also be taken from the Pass through position see 5 10 Video output selection meaning that the video output is re clocked only Input signal type CASI SDI Figure 6 Gyda view of the input signal type selector 5 2 SDI data path HD SD SDI input is selected from input 1 or 2 equalized re clocked and transferred to a processing unit Here the signal is first sent through a de glitcher that cleans up errors that might appear on input signal for instance due to switching After the de glitcher the parallel video is split in two paths one going directly to a frame store buffer the other sent to the audio de embedder The 16 audio channels coming from the de embedder are bundled in pairs and sent to an audio store buffer being the same as the frame store buffer The audio is fetched from the audio store buffer according to a user specified delay and sent to an Audio Cross Point The output of the Audio Cross Point can be any pair of audio channels de embedded from the incoming vide
36. n silence trigger audio out clipping trigger active picture video freeze and silence trigger The different trigger blocks with their respective trigger masks are shown in Figure 9 C Enable Disable Hold time 10000 ms v Bit T AN ERA EDO ein rire TAPCRE Video error trigger ee ue E L E C C G a LOCK CCS YCS CCRC YCRC LNUM SAV EAV z E E E a E mn C Enable Disable Hold time fio000 ms v eee VCLP FFVF TCF BLK Video content trigger And 7 E B T e Or Black threshold luma fo C Enable Disable Hold time fi 0000 ms v Bit tor 48kHz Audio error trigger gr 1 A Te 2 m e E Ch4 Ch3 Ch2 Chi Group U O BCH T a a a E mn Audio error trigger gr 2 C Enable Disable Hold time fi 0000 ms v Audio error trigger gr 3 C Enable Disable Hold time fi 0000 ms vj Audio error trigger gr 4 C Enable Disable Hold time fi 0000 ms v C Enable Disable Hold time fioooo ms v Bit operator Ch15 16 Ch13 14 Ch11 12 Ch9 10 Ch 8 Ch5 6 Ch3 4 Ch1 2 Audio in silence trigger C And r F Fr r m al el e Or Silence threshold 60 dBFS Enable Disable Hold time 10000 ms v Audio out clipping trigger Pl operator Ch15 16 Ch13 14 Ch11 12 Ch9 10 Ch 8 Ch5 b Ch3 4 Ch1 2 r els F um e Or C Enable Disable Hold time 0000 ms v Bit operator APVF and silence trigger C And r r e Or Ch15 16 Ch13 14 Ch11 12 Ch9 10 Ch 8 Ch5 6 Ch3 4 Ch1 2 a z E Silence threshold in Audio in silence trigger 0 Figure
37. nce it to the sync input By this mechanism the user can precompensate processing delay in other equipment The video delay setting simply determines a lower limit to a 1 frame wide window into a long delay line The phase delay may be seen as a specification of the delay between the sync input and a signal isync The output video is always synchronized to isync A few more examples Example 1 The SDI input signal is isosynchronous to a sync signal but 12 lines O samples delayed The video delay is set to 1 frame 0 lines and 0 samples The phase delay is set to 65 samples The actual delay between the input video and the output video will be 2 frames 12 lines 65 samples Example 2 The SDI input signal is asynchronous to the sync signal the frame frequency is slightly different The video delay is set to 1 frame 13 lines and 0 samples The phase delay is set to 1 line The actual delay will gradually change between 1 frame and 13 lines to 2 frames and 13 lines The output will appear 1 line in the output video format ahead of the sync signal Example 3 The SDI input signal is isosynchronous to the sync signal but 12 lines ahead of the sync signal The video delay is set to 1 frame O lines and O samples The phase delay is set to 2 lines The actual delay between the input video and the output video will be 1 frame 10 lines The frames and lines are measured in units of the output SDI video standard If the output SDI standar
38. nevicn FRS HD CHO FRS HD CHO ASI ASI CHO 2x1 PB HD SD SDI 2x1 Change Over with Frame Synchronizer and or ASI 2x1 Change Over User manual Rev K FRS HD CHO Rev K Nevion Support Nevion Europe Nevion USA P O Box 1020 1600 Emerson Avenue 3204 Sandefjord Norway Oxnard CA 93033 USA Support phone 1 47 33 48 99 97 Toll free North America 866 515 0811 Support phone 2 47 90 60 99 99 Outside North America 1 805 247 8560 E mail supportOnevion com See http www nevion com support for service hours for customer support globally Revision history Current revision of this document is the uppermost in the table below Rev Repl Date Sign Change description Cover page update DoC removed no other K 9 2015 05 14 MB changes to content Corrected DIP switch description for ASI CHO 9 8 2012 08 10 TB 2x1 Added min max audio delay Corrected table 2 Connections Added 8 7 2012 05 04 TB description of the GPIO mode selector under GPI alarms Added the ASI only variant ASI CHO 2x1 PB 7 6 2012 02 22 TB Updated several screen shots to current look Multicon 3 6 0 Added clarification about ASI upgrade and HW 6 5 2011 08 15 TB versions Added description for the ASI variant Some 5 4 2011 05 19 TB changes to DIPs and the list of commands Added Declaration of Conformity Added APVF and silence trigger ch 5 2 4 3 2010 02 24 TB updated block
39. o stream an internal 1 KHz sine or an internal black sound Black sound is in function mute but it produces a waveform pattern which is different from mute Each channel pair from the cross point outputs enters an Audio Processing Block where the paired channels may be level adjusted and shuffled After the audio processing block the audio enters the Audio Embedder The video with audio still inserted is fetched from the frame buffer with the user specified delay and sent to a Video processing block gain offset and hard clip legalizing followed by an EDH processing block After the EDH block the video and audio is embedded according to the user settings and the video is sent from the processing unit to a re clocker Here the signal is converted back to SDI and sent to a 2x2 output switch The buffered output switch is a 2x2 cross point switching between an equalized and re clocked input through and a video processed input processed The two outputs are sent to two paired non inverting and inverting outputs 5 3 Video input selection The FRS HD CHO has two electrical inputs The input can be chosen either by an automatic selection with priorities and rule of switching or by manual selection If there is a sync input connected the board will switch the signals on the switching line of the present format nevion com 15 FRS HD CHO Rev K Manual selection mode v Latch Reset Video in Figure 7 Gyda vi
40. on FRS HD DMUX compatible is equal to what the table on the next page refers to as frame synch style while SDI CHO 2x1 compatible is equal to the change over style of the GPIO lines As the table on the next page shows the difference lies in the behavior of pins 3 4 and 7 nevion com 13 FRS HD CHO 4 2 1 Functions of 8pin modular jack Rev K GPI name Function Pin Mode change change over style over style frame synch style frame synch style Status General error status Pin Inverted for the module 1 Open Collector open is alarm LOS Loss of signal or lock Pin at selected input 2 Input 1 Input 1 selected IN1 Pin Open Sync loss Sync input loss of Collector signal or lock Input 2 Input 2 selected IN2 Open Framedelay Outputs a pulse with Collector length equal to frame delay Reset selected input Pin to main Set Set selected input to in standby Reset TTL OV active level Input 2 Connected to pin 4 on Open Frame backplane Collector delay Ground 0 volt pin Pin OV 8 Open Output Collector Direction a E e E aly lalslalo aa TTL OV Input active level 2 EDH errors will not be shown at GPI output 3 Pin 4 and 7 are connected on TP45 connector to be compatible with both FRS HD SDI and SDI CHO 2x1 nevion com 14 FRS HD CHO Rev K 5 Functional descriptio
41. or a nominal fee These modules can be recognized by the way they respond to a command on the serial communication bus and the way they present themselves in the Multicon Gyda configuration page If the reply to the command contains a line that says Serial rev 1728201000000001 the actual 16 digit number will be different and a line that says HW rev 1 1 or there are two lines at the very bottom of the Multicon configuration page that looks like below the module can be upgraded to the ASI version with a software key nevion com 4 FRS HD CHO Rev K HW 1 1 Serial 1728201000000001 If one or both of these two lines is not present or the HW version is reported as 1 0 or the serial number reported is XXXXXXXXXXXXXXXX literally sixteen X characters the module cannot be field upgraded from the FRS HD CHO to the FRS HD CHO ASI version Of course the module can still be upgraded with the latest firmware and continue to work as an FRS HD CHO 1 1 2 Key features Passive bypass from both inputs to non inverted outputs with less than 25m loss of cable length enables full redundancy see app note in appendix HD SD video support including DVB ASI in through mode Separate ASI mode available as an upgrade from the normal FRS HD CHO Separate ASI only version available with a much simplified user interface De glitching of input video signal always seamless output Intelligent change over function
42. p www nevion com Please contact Nevion Customer Support for assistance with recycling if this site does not show the information you require Where it is not possible to return the product to Nevion or its agents for recycling the following general information may be of assistance Before attempting disassembly ensure the product is completely disconnected from power and signal connections All major parts are marked or labeled to show their material content Depending on the date of manufacture this product may contain lead in solder Some circuit boards may contain battery backed memory devices nevion com 38
43. rializer 0x4000 Ox4fff serializer 0x5000 Ox5fff shift register for LEDs spiw lt address gt spiw 0x0004 Ox2c With the same address ranges lt data gt as for spir above this command allows the user to modify SPI registers thebug thebug A collection of debug information that is presented in a Gyda block like format First line tells which image is currently loaded Second line contains the filename and version of the uC software including the AVR controller it was compiled for The third line contains the SW flags in uC the number of times the watchdog timer has kicked in readout of dip switches input select for deserializer SDOn on off slew rates and status for the video changeovers The next two lines contain raster information from the deserializer and serializer respectively while the next two lines contain sample values for mlines and VCXO nevion com 35 FRS HD CHO Rev K General environmental requirements for Nevion equipment 1 The equipment will meet the guaranteed performance specification under the following environmental conditions Operating room temperature 0 C to 45 C range Operating relative humidity range lt 90 non condensing 2 The equipment will operate without damage under the following environmental conditions Temperature range 10 C to 55 C Relative humidity range lt 95 non condensing nevion com 36 FRS HD
44. rocessing block consists of a gain and offset adjustment and a video payload legalizer Legalize On Off vj Y Cb Cr era Gain 1 0000 1 0000 1 0000 Offset 0 0000 0 0000 0 0000 Figure 17 Gyda view of the video processing block 5 8 1 Gain and offset The gain and offset adjustment is done separately on the Y Cb and Cr samples Range in Multicon Gyda Luma gain 0 4x Chroma gain 0 4x Luma offset gain 1 511 75 511 75 in sample values Chroma offset gain 1 255 75 255 75 in sample values 5 8 2 Video payload legalizer The legalizer hard clips the upper and lower limit of the video payload With the legalizer enabled these limits are nevion com 24 FRS HD CHO Rev K Upper limit Luma 3ACh Chroma 3C0h Lower limit Luma 040h Chroma 040h With the legalizer disabled the video processing block hard clips both luma and chroma to 3FBh and 004h Note that the payload legalizer gives out a trigger to the video content trigger block when output has been clipped 5 9 EDH processing block If enabled the EDH processing block extracts the EDH package from the video updates the EDH flags according to SMPTE RP165 and inserts the EDH package into the ancillary data of the video If disabled The EDH processing block only reads process and report the EDH package without changing it in video stream 5 10 Video output selection The board has four outputs where two and two can be eit
45. that can lock an HD SDI or SD SDI input to a black amp burst or tri level reference signal A de glitcher ensures an always error free output The change over functionality covers numerous switching criteria that analyses video and audio integrity and content The switching criteria are placed into several logical groups each of which can have their own timing The FRS HD CHO has an extensive audio functionality including audio cross point matrix channel swapping relative audio delay and audio gain The module is also well suited for Dolby E An extension and even a separate version exists that will also handle change over switching on ASI inputs but then without the frame synchronizer de glitcher and audio functionality The user parameters of the card can either be changed by switches on the board or by the Multicon Gyda system controller 1 1 1 Product versions This product comes in three versions The base model FRS HD CHO for HD SD SDI the FRS HD CHO ASI with a selectable SDI or ASI mode and an ASI only version called ASI CHO 2x1 PB The ASI CHO 2x1 PB is not designed to be upgradable to an FRS HD CHO or an FRS HD CHO ASI The user interface for ASI only is however much reduced compared to the SDI capable versions with frame synchronizer and audio embedding de embedding making the ASI CHO 2x1 PB very easy to understand set up and use Some FRS HD CHO modules can be upgraded to FRS HD CHO ASI with a software key f
46. tive amount To go beyond this limit would require the audio to be re embedded before it had even been de embedded from the incoming video and that is of course impossible The positive audio delay is limited by the fact that the sum of the video delay and the relative audio delay cannot be larger than 32000 audio samples approx 0 67 ms with 48 kHz audio If the video delay is set to minimum the full 32000 audio samples will be available but if the video delay is set to say 5 frames the maximum relative audio delay is reduced to 20000 audio samples assuming 25 frames per second 5 frames equals 0 2 seconds which in turn equals 12000 audio samples and 32000 12000 20000 When doing these calculations remember that if a sync reference is present a video delay setting of N frames means that the actual video delay can vary continuously between N and N 1 frames The calculations should therefore be based on N 1 frames Dolby E delay handling The FRS HD CHO can re align Dolby E with video Dolby E processing equipment typically causes one frame delay for the audio The positive video delay needs to be set higher than the desired negative relative audio delay Then set a negative relative audio delay that corresponds to a whole number of full frames of audio samples A delay example setting is shown in Figure 21 The audio embedder settings should be as in Figure 22 Phase delay lo lines lo samples Video delay 2 frames lo lin
47. ure 25 Gyda view of the audio embedders The audio embedder can be enabled per group in Gyda When a group is disabled the audio inside that group is removed When in SD mode a 24bit sound signal can be changed to 20bit through Gyda control This removes the upper 4 bits of the signal The audio control package is left unchanged as the bit range is still present The audio control package can also be switched on and off in SD mode through Gyda control The audio embedder can be switched off all together In this state the audio embedded on the input signal is left unchanged nevion com 28 FRS HD CHO 6 RS422 commands 6 1 FLP4 0 required commands Rev K Block Bik Commands Example Response Control product name SW rev n m FW rev r s protocol ver 4 0 Hello command Note 1 No other commands will be available until the card has received this hello Note 2 This command will also enable checksums Note 3 Cards are designed to be hot swappable To sync with the start of anew command the cards will wait for a lt lf gt character before looking for a valid command conf conf 0 too long to list Configuration settings Retrieves the card s configurable settings Each addressable block is represented by a single line Dynamic status may be included in response but is usually reported in info only info info too long to list Dynamic status info Blocks with stat
48. utput video nevion com 10 FRS HD CHO Rev K If the ASI option has been purchased the name of the module will have ASI appended In addition a line Input signal type followed by SDI or ASI will appear as a reminder of the selected mode ASI or SDI w EAN FRS HD CHO ASI Input signal type SDI Phase delay D samples Electrical input 1 Loss of signal Electrical input 2 Loss of signal Reclocker Loss of lock Sync source Missing Video delay Ons 0 samples Relative audio delay 0 samples 10807251 Error counter 0 Reset Signal integrity O NOEDH V8 FFORC APRC LOCK lecs YCS CCRC YCRC NUM SAV EAV Figure 3 Gyda information page for FRS HD CHO ASI ASI CHO 2x1 PB Ingut 1 ASI out1 ASI out2 Electrical input 1 Loss of signal Electrical input 2 Loss of signal Reclocker Loss of lock Figure 4 Gyda information page for ASI CHO 2x1 PB 3 2 2 Configuration page The different configuration possibilities are explained in detail in Chapter 5 under the corresponding functions nevion com 11 FRS HD CHO 3 3 Connections iada in Naa ve 02 metworl Rev K Figure 5 FRS HD CHO C1 backplane left component side right connection side The backplane for the FRS HD CHO is labeled FRS HD CHO C1 The table below shows the connectors and their functions Function Label Connector t
49. with one priority level only but has its own command 0 from electrical input 1 1 from electrical input 2 2 mute 3 internal video generator 4 none The module will always respond with 3 levels filling in 4 none for the levels not used t1 and t2 change over doesn t happen immediately as a precaution against glitches and unstable signals The timers t1 and t2 let the user decide how long in ms we will cling on to a missing input before we consider it gone and move on to the next pri level and how long an input with a higher priority should be present before we consider it repaired and switch back respectively Note MCU firmware before ver 1 10 also have latch and rule settings These are deprecated nevion com 30 FRS HD CHO cho 1 size 3 pri k auto size 3 pri k man m Rev K No commands available Included to show internal status and to update Gyda graphics cho 2 9 pri lt k gt pri lt k gt lt l gt cho 2 pri 1 cho 5 pri 0 2 size 4 pri k Audio fallback setting Audio change over blocks one cho per audio output from the audio matrix mtx 0 No other settings but the priority list 0 from audio matrix 1 sine 2 black sound 3 mute Note Only generators pri 1 2 or 3 are allowed to be set as first and only priority cho 10 pri lt k gt pri lt k gt lt l gt cho 12 pri 1 cho 12 pri O0 2 size 4 pri k Audio common fallback
50. x10011 mtx 100 1 size M N i1 12 13 iN Video output matrix mtx 1 size 2 2 controls the video output switches 0 Through mode re clocked only 1 Processed mode SDI from FPGA mtx lt i1 gt lt 01 gt mtx 200 mix210 size M N i1 12 13 iN Audio embedder bypass 0 Embedding disabled 1 Embedding enabled age lvl lt sine_level gt cBFS agen lvl 180 agen lvl 200 sine 1kHz lvl lt sine_level gt cBFS Audio generator The amplitude of the generated sine that can be chosen as fallback in audio change overs Legal values are 180cBFS or 200cBFS centiBel referred to full scale output Units are optional but if included must be written as cBFS case sensitive apre Ir rl ll rr nir Inr mm ms lvl lt gain gt aprc 0 Ir aprc 3 ll aprc 6 mm apre 7 lvl 400 Ir rl I rr nlr Inr mm ms Audio processing one block for each output from cho 2 9 that is routed to the embedder The meaning of the commands are as follows Ir Normal rl Channel swapped ll Left channel to both output channels rr Right channel to both output channels nlr Left channel phase inverted Inr Right channel phase inverted mm Mono both channels r l 2 ms Mono stereo m I r 2 s I r 2 Ivl means level and is the gain setting trig 0 8 msk lt mask gt amp 1 en dis t1 lt hold_time gt lvl lt bitnr gt
51. ype HD SD SDI or ASI input 1 IN1 BNC HD SD SDI or ASI input 2 IN2 BNC HD SD SDI or ASI output 1 O1 BNC HD SD SDI output 1 inverted ASI is a __ BNC polarized signal i e the inverted signal is not O1 valid ASI unless inverted a second time HD SD SDI or ASI output 2 O2 BNC HD SD SDI output 2 inverted ASI is a __ BNC polarized signal i e the inverted signal is not 02 valid ASI unless inverted a second time Black amp Burst tri level input SYNC BNC Black amp Burst tri level input SYNC BNC GPI in GPI TP45 pin 5 8 6 GPI out GPI TP45 pin 1 2 3 4 7 pin 8 GND Table 2 Connector functions Unused SDI ASI inputs outputs must be terminated with 75 Ohm 3 4 Sync input The two sync inputs on the backplane are internally connected It is possible to use one as input and the other as a looped output The backplane also features a switchable termination By setting the red switch in the upper right of Figure 5 to the On position the sync input will be terminated to 75 Ohms nevion com 12 FRS HD CHO 4 Operation 4 1 Front panel LED indicators Rev K Diode 1 state Red LED Orange LED Green LED No light Card status PTC fuse has Module has not Module is OK Module has no been triggered been power or FPGA programmed programming RESET and has failed OVR DIPS are on or module is updating firmware SDI input Video signal Video signal Video input Module has
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