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NuDAQ® PCI-7442/7443/7444

1. CLRO Bit 5 Bit2 EAO Biti5 Bit13 Bit12 Bit11 Bit9 Bits Bit15 9 Not used Bit7 1 Not used Bito CLRO COS 0 interrupt clear 1 Clear 0 No effect Bit8 COS 0 interrupt enable disable 1 Enabled 0 Disabled 34 Register Format Address BASE 0x46h Reset Value 0x0000h Read Write W A ADLINK BA TECHNOLOGY INC CLR1 Bit7 Bit Bits Bit2 Bito EA1 Bit15 Bit14 Bit13 Bit12 Bit9 Bit15 9 Not used Bit7 1 Not used BitO CLR1 COS 1 interrupt clear 1 Clear 0 No effect Bit8 EA1 COS 1 interrupt enable disable Register Format 1 Enabled 0 Disabled 35 E A ADLINK TECHNOLOGY Interrupt Status COS INT Control Read Back Registers When any COS interrupts occur these registers provide informa tion for you to recognize the interrupt status and the interrupt setup condition read back Address BASE 0x06h Reset Value 0x0000h Read Write R CIS1 CISO Bit 5 Bit2 Bito COSOE Biti5 14 Bit13 Bit12 Bit11 Bit1O Bit9 Bits Bit14 12 Not used Bi
2. 29 Common Ground Connection of Isolated Digital Output 30 List of Figures 1 ADLINIC Introduction The ADLINK PCI 7442 PCI 7443 and PCI 7444 cards are high density isolated digital cards featuring 128 or 64 channels of digital input 128 or 64 channels of digital output and up to 32 TTL channels for a wide range of PCI bus based industrial applica tions gt 7442 Isolated 64 CH DI and 64 CH DO card gt 7443 Isolated 128 CH DI card gt 7444 Isolated 128 CH DO The card series provide a robust 1 250 Vans isolation protection which is suitable for most industrial applications For PCI chassis with multiple PCI 7442 7443 7444 installed the board ID design feature enables convenient identification of the cards through a switch jumper allowing quick troubleshooting and maintenance Introduction ADLINIC 1 1 Features Refer to the comparison table below for the card series features Features PCI 7442 PCI 7443 7444 32 bit 3 3 V 5 V PCI bus PnP Yes Yes Yes Isolated digital input channels 64 128 Isolated digital output channels 64 128 Change of state COS detection 64 128 Channels with 28 V voltage protection 64 128 Channels with 250 mA sink current 64 128 on with digital output status read 64 _ 128 DO value reta
3. V5V Onboard un regulated 5V power supply output N C No Connect 22 Hardware Information ADLINK pw TECHNOLOGY INC CN1 Connector CN1B CN1A N C B68 34 IDO 0 1 A35 IDO 8 IGND B67 B33 IGND IDO 1 A2 A36 IDO 9 IGND B66 B32 IGND IDO 2 A37 IDO 10 IGND B65 31 IGND IDO 3 A4 A38 IDO 11 IGND B64 B30 IGND IDO 4 A5 A39 IDO 12 IGND B63 B29 IGND IDO 5 A6 A40 IDO 13 IGND B62 B28 IGND IDO 6 A7 A41 DO 14 IGND B61 B27 IGND IDO 7 A8 A42 IDO 15 VDD8 B60 B26 VDD7 VDD1 AQ A43 VDD2 DO 63 B59 25 00_55 A10 A44 1 DO 62 B58 B24 1 54 A11 45 IGND DO 61 B57 B23 IDO 53 GND A12 A46 IGND DO 60 B56 B22 IDO 52 A13 47 IGND DO 59 B55 B21 1 51 GND A14 A48 IGND DO 58 B54 B20 1 50 15 49 DO 57 53 B19 IDO_49 A16 50 IGND DO 56 52 B18 IDO_48 N C A17 51 B51 B17 IDO_16 A18 A52 IDO 24 IGND B50 B16 IGND IDO 17 A19 A53 IDO 25 IGND B49 B15 IGND IDO 18 20 A54 IDO 26 IGND B48 B14 IGND IDO 19 21 A55 IDO 27 IGND B47 B13 IGND IDO 20 22 56 IDO 28 IGND B46 B12 IGND IDO 21 A23 A57 IDO 29 IGND B45 B11 IGND IDO 22 A
4. Address R W Value Mapping MSB LSB BASE 0x00h IDO 15 0 BASE 0x02h W IDO 31 16 BASE 0x04h W IDO 47 32 BASE 0x06h W IDO 63 48 BASE 0x0Ah W IDO 79 64 BASE 0x0Ch IDO 95 80 BASE 0x0Eh IDO 111 96 BASE 0x10h IDO 127 112 BASE 0x08h Port 0 Send Out Start BASE 0x12h W Port 1 Send Out Start BASE 0x14h All Ch Send Out Start Bit value 0 Output PowerMOSFET is OFF Initial value 1 Output PowerMOSFET is ON Register Format 57 p TECHNOLOGY INC ADLINK Isolated digital output channel range from bitO to 6163 Isolated digital output channel range from bit64 to bit127 All Ch Isolated digital output channel range from bitO to bit127 58 You may read the isolated DO statuses from the registers To read the 128 bit DO statuses you must first send the Read Back Start All Ch Port1 command You can then read back isolated DO Read Back Register offset in turn if DO read back procedure is standby Address R W Value Mapping MSB LSB BASE 0x00h R All CH Read Back Start BASE 0x02h R Port 0 Read Back Start BASE 0x0Ch R Port 1 Read Back Start BASE 0x04h R IDO 15 0 BASE 0x06h R IDO 31 16 BASE 0x08h R IDO 47 32 BASE 0x0Ah R IDO 63 48 BASE 0x0Eh R IDO 79 64 BASE 0x10h R IDO 95 80 BASE 0x12h R IDO 111 96 BASE 0x14h R IDO 127 112 Bit value 0 Output Pow
5. 14 Hardware Information ADLINK BA TECHNOLOGY INC CN1 Connector CN1B B68 B34 IDI 0 1 A35 101 8 B67 833 COM7 IDI 1 A2 A36 IDI 9 8 B66 B32 COM7 IDI 2 A37 IDI 10 8 B65 B31 COM7 IDI 3 A4 A38 IDI 11 8 B64 B30 COM7 IDI 4 A5 A39 IDI 12 8 B63 29 COM7 101 5 A40 101 13 8 B62 28 COM7 1016 41 DI 14 61 27 COM7 IDI 7 A42 IDI 15 8 B60 26 7 1 9 4 2 1021 63 B59 25 IDI 55 COM1 A10 A44 COM2 IDI 62 B58 24 IDI 54 1 A11 45 2 IDI 61 B57 B23 IDI 53 1 A12 46 2 12160 B56 22 IDI 52 1 A13 A47 COM2 IDI 59 B55 B21 IDI 51 1 14 48 2 10158 B54 20 IDI 50 1 A15 49 2 101 57 B53 B19 IDI 49 1 A16 A50 2 10156 B52 B18 101 48 N C A17 A51 N C N C B51 B17 IDI 16 A18 A52 IDI 24 COM6 B50 B16 5 DI 17 A19 53 IDI 25 6 B49 15 5 DI 18 A20 A54 IDI 26 6 B48 14 5 DI 19 21 55 101 27 6 B47 13 5 DI 20 22 56 101 28 6 B46 B12 5 DI 21 23 A57 IDI 29 6 B45 11 5 DI
6. ADLINK TECHNOLOGY INC Bit3 Address BASE 0x8Ah Reset Value 0x0000h Read Write 1 Clear WDT interrupt 0 No effect WSOE WDT Safety DO Send Out Enable 1 Enabled 0 Disabled ARDYS SRDYS RBRDYS SOES WIS WDTES HRHES Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit BitO Biti5 4 Bit12 Bit10 Bit9 Bit8 Bit15 7 Not used Bito HRHES Hot Reset Hold Enable Status 1 Enabled 0 Disabled Biti WDTES WDT Interrupt Enable Status 1 Enabled 0 Disabled Bit2 WIS WDT interrupt status 1 WDT interrupt does not assert 0 WDT interrupt asserts Bit3 SOES Safety Out Enable Status 1 Enabled 0 Disabled Bit4 RBRDYS DO Read Back Data Ready Status 1 Not ready 0 Ready Bit5 SRDYS DO Data Sending Finished Status 1 Not finished 0 Finished Bit6 ARDYS Flash Data Read Write Finished Status 46 1 Not finished 0 Finished Register Format ADLINK BA TECHNOLOGY INC 4 2 7443 I O Registers Isolated Digital Input Registers There are 128 isolated digital inputs on the PCI 7443 card The statuses of the 128 lines can be read from the registers listed below Each bit corresponds to each channel Address R W Value Mapping MSB LSB BASE 0x02h R IDI 15 0 BASE 0x04h R IDI 31 16 BASE 0x42h R IDI 47 32 BASE 0x44h R IDI 63 48 BASE 0x82h R IDI 79 64 BASE 0x84h R IDI 95 80 BASE 0xC2h
7. ADLINK p NuDAQ PCI 7442 7443 7444 128 CH 64 CH Isolated Digital 1 0 Cards User s Manual Manual Rev 2 01 Revision Date March 12 2007 Part No 50 11218 2000 Recycled Paper Advance Technologies Automate the World E A ADLINK TECHNOLOGY INC Copyright 2007 ADLINK TECHNOLOGY INC All Rights Reserved The information in this document is subject to change without prior notice in order to improve reliability design and function and does not represent a commitment on the part of the manufacturer In no event will the manufacturer be liable for direct indirect spe cial incidental or consequential damages arising out of the use or inability to use the product or documentation even if advised of the possibility of such damages This document contains proprietary information protected by copy right All rights are reserved No part of this manual may be repro duced by any mechanical electronic or other means in any form without prior written permission of the manufacturer Trademarks NuDAQ NulPC DAQBench are registered trademarks of ADLINK TECHNOLOGY INC Product names mentioned herein are used for identification pur poses only and may be trademarks and or registered trademarks of their respective companies ADLINK BA TECHNOLOGY INC Getting service Customer satisfaction is our top priority Contact us should you require any service or assistance ADLINK TECHNOLOGY INC Web
8. Bit9 Bit8 Bit15 7 Not used Bit6 ARDYS Flash Data Read Write Finished Status 1 Process is not finished 0 Process is finished Bit5 SRDYS DO Data Sending Finishes Status 1 Process is not finished 0 Process is finished Bit4 RBRDYS DO Read Back Data Ready Status 1 DO read back data is not ready 0 DO read back data is ready Bit3 SOES Safety Out Enable Status 1 Function is enabled 0 Function is disabled Bit2 WIS WDT Interrupt Status 1 The WDT interrupt has asserted 0 The WDT interrupt did not assert WDTES WDT Interrupt Enable Status 1 Function is enabled 0 Function is disabled Bito HRHES Hot Reset Hold Enable Status 1 Function is disabled 0 Function is enabled Register Format ADLINK BA TECHNOLOGY INC TTL IO Setup Status DO and DI Registers The PCI 7444 provides an extra 32 CH TTL function for optional applications These TTL I O channels are divided into two 16 bit banks These channels are divided between two connec tors JP3 and JP4 You can choose the direction of each TTL channel any time by setting up the two bank TTL IO setup register Address R W Value Mapping MSB LSB BASE 0x3C TTL IO SETUPT 15 0 BASE 0x3E W TTL IO SETUPT S1 16 Bit value 0 direction is input Default 1 direction is output When you set up the direction of TTL I O channels the statuses of setting can be read back through TTL IO Status Re
9. Number of I O channels 32 Digital logic level 3 3 TTL Current rating 4 mA max per channel Data transfer Programmed I O Watchdog timer PCI 7442 PCI 7444 only Base clock available 10 MHz fixed Counter width 32 bit Continued on next page Introduction 3 ADLINIC Safety functions 7442 7444 only Programmable power up DO initial status Programmable safety DO status function even during WDT interruption Digital output value retention after hot system reset General specifications Dimensions 174 7 mm L x 106 7 mm W standard PCI Bus 32 bit PCI bus Operating temperature 0 C 60 Storage temperature 40 80 596 to 85 non condensing Power Power consumption PCI 7442 5 V at 800 mA typical PCI 7443 5 V at 550 mA typical PCI 7444 5 at 800 mA typical Specifications are subject to change without notice 4 Introduction ADLINIC 1 4 Unpacking Checklist Before unpacking check the shipping carton for any damage If the shipping carton and or contents are damaged inform your dealer immediately Retain the shipping carton and packing mate rials for inspection Obtain authorization from your dealer before returning any product to ADLINK Check if the following items are included in the package gt PCI 7442 PCI 7443 PCI 7444 card gt ACL 10337 DB37F br
10. ADLINK is not responsible for any loss of data gt Please ensure the use of properly licensed software with our systems ADLINK does not condone the use of pirated software and will not service systems using such software ADLINK will not be held legally responsible for products shipped with unlicensed software installed by the user Forgeneral repairs please do not include peripheral accessories If peripherals need to be included be cer tain to specify which items you sent on the RMA Request amp Confirmation Form ADLINK is not responsible for items not listed on the RMA Request amp Confirmation Form Warranty Policy 69 E A ADLINK TECHNOLOGY INC 3 Our repair service is not covered by ADLINK s guarantee in the following situations gt gt gt gt Damage caused by not following instructions in the User s Manual Damage caused by carelessness on the user s part dur ing product transportation Damage caused by fire earthquakes floods lightening pollution other acts of God and or incorrect usage of voltage transformers Damage caused by unsuitable storage environments i e high temperatures high humidity or volatile chemi cals Damage caused by leakage of battery fluid during or after change of batteries by customer user Damage from improper repair by unauthorized ADLINK technicians Products with altered and or damaged serial numbers are not entitled to our service This war
11. Table of Contents ADLINK BA TECHNOLOGY INC Programmable TTL Input Output 31 4 Register Format 33 PCI 7442 I O 5 33 Isolated Digital Input Register 33 COS Interrupt Control Registers 34 Interrupt Status COS INT Control Read Back Registers 36 COS Setup Latch Registers 37 TTL IO Setup Status DO and DI Registers 38 Isolated Digital Output and Read Back Registers 40 Power up DO Setup Read Register 42 Watchdog Timer Load Safety DO Setup Read Back Registers 43 WDT INT Control Hot Reset and Hold Control Register 45 PCI 7443 I O 5 47 Isolated Digital Input Registers 47 COS Interrupt Control Registers 48 Interrupt Status COS INT Control Read Back Registers 51 COS Setup Latch Registers 53 TTL IO Setup Status DO and DI Register
12. 0x1Eh IDO 79 64 BASE 0x20h IDO 95 80 BASE 0x22h W IDO 111 96 BASE 0x24h IDO 127 112 Bit value 0 Output PowerMOSFET is OFF Initial value 1 Output PowerMOSFET is ON Register Format 59 E A aos Address R W Value Mapping MSB LSB BASE 0x16h R Read Back Start BASE 0x18h R IDO 15 0 BASE 0x1Ah R IDO 31 16 BASE 0x1Ch R IDO 47 32 BASE 0x1Eh R IDO 63 48 BASE 0x20h R IDO 79 64 BASE 0x22h R IDO 95 80 BASE 0x24h R IDO 111 96 BASE 0x26h R IDO 127 112 Bit value 0 Output PowerMOSFET is OFF Initial value 60 1 Output PowerMOSFET is ON You need not assign a register value for the Power Up Initial DO All Ch Status Read Back Start You only need to send out the address BASE 0x16h in Read mode before reading back all inital 128 bit channel output data When the DO bank receives the Start command the flash reading procedure starts in 100 ms You can check if the procedure is finished by get nAction_Ready flag status Register Format ADLINK BA TECHNOLOGY INC WDT Load Config Safety DO Setup Read Back Registers The PCI 7444 provides a 32 bit watch dog timer WDT with 10 MHz clock The WDT counter loads the 32 bit value of two 16 bit WDT LOAD CONFIG Registers turn The corresponding hexa decimal value you set determines the overflow time of WDT counter The overflow time is calculated by the value that you se
13. 22 24 58 101 30 6 B44 10 5 DI 23 25 59 101 31 6 B43 5 26 A60 COM4 IDI 47 B42 B8 IDI 39 A27 61 4 10146 B41 B7 IDI 38 A28 A62 COM4 IDI 45 B40 B6 IDI 37 A29 A63 COM4 10144 B39 5 IDI 36 A30 64 4 10143 B38 B4 101 35 A31 65 4 10142 B37 B3 IDI 34 A32 66 4 10141 B36 2 IDI 33 A33 67 4 10140 B35 1 IDI 32 A34 A68 N C Hardware Information 15 ADLINIC p Pin Definition Pin Definition IDI n Isolated digital input channel n common junction for input channel 0 7 COM2 common junction for input channel 8 15 COM3 common junction for input channel 16 23 COM4 common junction for input channel 24 31 COM5 common junction for input channel 32 39 COM6 common junction for input channel 40 47 COM7 common junction for input channel 48 55 COM8 common junction for input channel 56 63 16 Hardware Information ADLINK BA TECHNOLOGY INC 2 3 PCI 7443 Pin Assignments CN2 Connector CN2B CN2A N C B68 B34 IDI 64 1 A3
14. 55 PCI 7444 I O 5 57 Isolated Digital Output Read Back Registers 57 Power up DO Setup Read Back Register 59 WDT Load Config Safety DO Setup Read Back Registers 61 WDT INT Control Hot Reset Hold Control Register 63 TTL IO Setup Status DO and DI Registers 65 Handling PCI Controller Registers 67 Warranty Policy 69 Table of Contents ADLINK Y INC List of Tables Table 2 1 TTL IO Connector Pin Assignments 25 Table 2 2 TTL IO JP4 Connector Pin Assignments 25 Table 2 3 Board ID Settings 26 List of Tables iii ADLINIC Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 List of Figures PCI 7442 9 PCI 7443 10 PCI 7444 11 PCI 7440 Series Card Bracket 12 PCI 7440 Series Connector Pin Reference 12 Photo Coupler essen 27 COS TIMING 28 COS Detection
15. 63 48 Bit value 0 Output Power MOSFET is OFF Initial value 1 Output Power MOSFET is ON Register Format 41 E FA ADLINK TECHNOLOGY INC 42 Power up DO Setup Read Register When the system enters the power up status PCI 7442 can enter the initial procedure which sends out the default initial value to 64 CH digital outputs You can configure the power up default DO values and store them in the flash memory With this the DO goes to a definite status when the system turns on You can program the 64 CH power up default DO values by accessing the Power up DO Setup Register in turn After access ing the last Power up DO Setup Register BASE 0x92h it could take up to 0 5s to finish writing the procedure to the flash memory You may check if the procedure is finish or not by nAction_Ready flag Address R W Value Mapping MSB LSB BASE 0x8Ch W IDO 15 0 BASE 0x8Eh 100 31 16 BASE 0x90h W IDO 47 32 BASE 0x92h W IDO 63 48 Bit value 0 Output Power MOSFET is OFF Initial value 1 Output Power MOSFET is ON You can read the configured power up initial DO values stored in the flash memory by sending out the Read Start command BASE 0x8Ch The read procedure starts in 50 ms When the Read Back procedure is ready nAction_Ready flag you can read back the 64 bit Power up DO Read Back Register in turn Address R W Value Mapping
16. Controls 7 2 Hardware Information 9 21 Layout hei dee rer ene cu tret nene 9 Bracket Layout 12 2 2 7442 Pin 5 13 CN2 Connector 13 Connector 15 2 3 7443 Pin 5 17 CN2 Connector nennt 17 Connector 19 2 4 PCI 7444 Pin 21 CN2 Connector sse 21 CN1 Connector 23 25 TTLI O Connector Pin Assignments 25 ES 25 25 2 5 Board ID 26 Operation theory nnn inre ak 27 3 1 Isolated digital input 27 3 2 Change of State COS interrupt 28 28 GOS detection 28 COS detection architecture 29 3 3 Isolated digital output channels 30 3 4 Watchdog timer WDT 31
17. Detection Architecture Operation theory 29 E FA ADLINK TECHNOLOGY INC 30 controller ADuM DO ouput 3 3 Isolated digital output channels The common ground connection of isolated digital output is shown in the figure below When the isolated digital output goes ON the sink current will be conducted through the power MOSFETs When the isolated digital output goes OFF no current is con ducted to flow through the power MOSFETS Take note that when the load is of an inductance nature such as a relay coil or motor the VDD pin must be connected to an external power source The extra connection is utilized for the fly wheel diode to form a cur rent release closed loop so that the MOSFETS are protected from any high reverse voltage which can be generated by the induc tance load when the output is switched from ON to OFF In addi tion you can read back the 64 128 CH IDO statuses to check if the statuses meet your purpose DC to DC VDD n 1 8 x _ E gt Coad _ IE x 0 63 CPLD ES o Ko Milij Isolation es Isolator IGND Figure 3 4 Common Ground Connection of Isolated Digital Output The PCI 7442 PCI 7444 provides three special functions for safety measures First the PCI 7442 PCI 7444 could automatically con figure the 64 128 CH DO initial statuses when powering up Sec ond you
18. can direct the PCI 7442 PCI 7444 to hold the DO statuses and avoid its power up initial configuration state after a hot system reset Third you can direct the PCI 7442 PCI 7444 to automatically configure the 64 128 CH DO safety statuses when a WDT interruption asserts Operation theory ADLINK BA TECHNOLOGY INC 3 4 Watchdog timer WDT In safety critical applications you can enable the watchdog timer WDT function to automatically generate an interrupt signal in case the operating system or the PCI 7442 PCI 7444 crashes To access this function you must first configure the watchdog timer overflow counter by windows API Generally the trigger source would come from the onboard 32 bit watchdog timer The WDT overflow interval can be programmed through API You must reload the WDT counter value before enabling the WDT After enabling the watchdog timer you must periodically reload the timer value by software command If the timer is not being reloaded within the specified interval the WDT module generates an overflow interruption signal When you enable the SafetyOut Enable bit the PCI 7442 PCI 7444 would automati cally configure the 64 CH 128 CH DO safety statuses This WDT function is disabled by default 3 5 Programmable TTL Input Output The PCI 7442 7443 7444 card provides a 32 CH programmable TTL input output These channels are divided between two con nectors JP3 and JP4 You can change the direction of e
19. 0 1 0 1 0 11 0 0 1 0 12 1 1 0 0 13 0 1 0 0 14 1 0 0 0 15 0 0 0 0 Table 2 3 Board ID Settings 26 Hardware Information ADLINK 3 Operation theory 3 1 Isolated digital input The PCI 7442 7443 card comes with 64 128 opto isolated digital input channels The circuit diagram of the isolated input channel is shown in Figure 3 1 DIn DICOM Photo Coupler Figure 3 1 Photo Coupler The digital input is routed first through a photo coupler so that the connection are not polarly sensitive whether using positive or negative voltage The normal input voltage range for high state is from 5 V to 28 V Operation theory 27 ADLINIC 3 2 Change State COS interrupt Overview The COS Change of State means either the input state logic level changes from low to high or from high to low The COS detection circuit will detect the edge of level change In the PCI 7442 7443 card the COS detection circuit is applied to all the input channels When any channel changes its logic level the COS detection circuit generates an interrupt request to PCI con troller COS detection Figure 3 2 is an example of an 8 CH COS operation All of the enabled DI channels signal level change will be detected to gen erate the interrupt request While the interrupt request generates the corresponding DI data will also be latched into the COS latch register In our COS archi tecture the DI data
20. 11 64 12 01107 B38 4 IDI 99 11 A65 COM12 01106 B37 B3 IDI 98 11 A32 A66 COM12 01105 B36 2 IDI 97 11 A33 67 12 01104 B35 B1 IDI 96 N C A34 A68 N C Hardware Information 17 ADLINIC p Pin Definition Pin Definition IDI n Isolated digital input channel n COM9 common junction for input channel 64 71 COM10 common junction for input channel 72 79 COM11 common junction for input channel 80 87 COM12 common junction for input channel 88 95 COM13 common junction for input channel 96 103 COM14 common junction for input channel 104 111 COM15 common junction for input channel 112 119 COM16 common junction for input channel 120 127 18 Hardware Information ADLINK BA TECHNOLOGY INC CN1 Connector CN1B B68 B34 IDI 0 1 A35 101 8 B67 833 COM7 IDI 1 A2 A36 IDI 9 8 B66 B32 COM7 IDI 2 A37 IDI 10 8 B65 B31 COM7 IDI 3 A4 A38 IDI 11 8 B64 B30 COM7 IDI 4 A5 A39 IDI 12 8 B63 29 COM7 101 5 A40 101 13 8 B62 28 COM7 1016 41 DI 14 61 27 COM7 ID
21. 2 TTLIO 12 13 TTLIO 5 14 TTLIO 13 BR 15 TTLIO 6 16 TTLIO 14 17 TTLIO_7 18 TTLIO 15 19 SGND 20 SGND Table 2 1 TTL IO JP3 Connector Pin Assignments JP4 Pin Function Pin Function 1 TTLIO_16 2 TTLIO 24 3 TTLIO 17 4 TTLIO 25 5 TTLIO 18 6 TTLIO 26 7 9 TTLIO 19 8 TTLIO 27 SGND 10 SGND 11 TTLIO 20 12 TTLIO 28 13 TTLIO 21 14 TTLIO 29 15 TTLIO 22 16 TTLIO 30 17 TTLIO 23 18 TTLIO 31 19 SGND 20 SGND Table 2 2 TTL IO JP4 Connector Pin Assignments TTLIO TTL channel SGND System ground for PCI 7440 card series H OD ED BI m Hardware Information 25 ADLINIC 2 6 Board ID S1 The Board ID feature helps you identify the modules when two or more PCI 7440 Series cards are installed in one system Accord ing to a DIP switch configuration located in the S1 you can assign a specific board ID to a designated card and access it correctly through simple software programming The table below shows all the switch settings 1 means DIP is at ON position 0 means that the DIP is OFF Switch No Board ID 1 2 3 4 0 1 1 1 1 1 0 1 1 1 2 1 0 1 1 3 0 0 1 1 4 1 1 0 1 ON 5 0 1 0 1 6 1 0 0 1 1 2 3 4 7 0 0 0 1 Note 1 ON 0 OFF 8 1 1 1 0 Default setting is 1111 or Board ID 0 0 1 1 1
22. 24 A58 IDO 30 IGND B44 B10 IGND IDO 23 A25 A59 IDO 31 VDD6 B43 B9 VDD5 003 A26 A60 VDD4 DO 47 B42 B8 IDO 39 A27 A61 GND 46 B41 B7 IDO 38 GND A28 A62 IGND DO 45 B40 B6 IDO 37 GND A29 A63 IGND DO 44 39 B5 IDO 36 GND A30 A64 IGND DO 43 38 B4 IDO 35 GND A31 A65 IGND DO 42 B37 B3 IDO 34 GND A32 A66 IGND 41 B36 2 IDO 33 GND A33 A67 IGND DO 40 B35 B1 IDO 32 A34 A68 N C Hardware Information 23 ADLINK Lam Pin Definition Pin Definition IDO n Isolated digital output channel n VDD1 common VDD junction for input channel 0 7 VDD2 common VDD junction for input channel 8 15 VDD3 common VDD junction for input channel 16 23 VDD4 common VDD junction for input channel 24 31 VDD5 common VDD junction for input channel 32 39 VDD6 common VDD junction for input channel 40 47 VDD7 common VDD junction for input channel 48 55 VDD8 common VDD junction for input channel 56 63 IGND Ground return path for isolated output channels N C No Connect 24 Hardware Information ADLINK BA TECHNOLOGY INC 25 TTL I O Connector Pin Assignments JP3 Pin Function Pin Function 1 TTLIO 0 2 TTLIO 8 gH 3 TTLIO 1 4 9 qe 5 TTLIO 2 6 TTLIO 10 E 7 TTLIO 3 8 TTLIO 11 9 SGND 10 SGND E 11 TTLIO 4 1
23. 5 101 72 COM16 B67 B33 COM15 101 65 A36 101 73 COM16 B66 B32 15 IDI 66 A37 101 74 COM16 B65 B31 15 101 67 A4 A38 101 75 COM16 B64 B30 COM15 IDI 68 5 A39 IDI 76 COM16 B63 29 15 IDI 69 A40 101 77 COM16 B62 28 COM15 IDI 70 A7 A41 DI 78 COM16 B61 27 5 10171 8 A42 101 79 COM16 B60 B26 COM15 9 A9 43 COM10 01127 B59 25 IDI 119 9 A10 44 COM10 DI 126 58 24 IDI 118 COM9 A11 A45 COM10 DI 125 B57 IDI 117 9 A12 A46 COM10 DI 124 B56 22 IDI 116 9 A13 47 COM10 DI 123 B55 21 IDI 115 COM9 14 A48 COM10 DI 122 B54 B20 IDI 114 COM9 A15 A49 COM10 DI 121 B53 B19 101 113 9 16 A50 COM10 DI 120 B52 B18 IDI 112 N C A17 A51 N C N C B51 B17 IDI 80 A18 A52 IDI 88 COM14 B50 B16 10181 A19 53 101 89 14 B49 815 IDI 82 20 A54 IDI 90 14 B48 814 101 83 21 A55 101 91 14 B47 B13 1 101 84 22 56 101 92 14 B46 B12 COM13 101 85 A23 57 101 93 14 B45 B11 1 101 86 24 58 101 94 14 B44 10 1 10187 25 59 101 95 14 B43 B9 COM13 11 A26 A60 12 DI 111 B42 B8 IDI 103 11 A27 A61 12 01110 B41 B7 IDI 102 11 A28 62 12 01109 B40 B6 IDI 101 11 A29 A63 COM12 DI_108 B39 5 IDI 100
24. 5 or any Windows programming language that allows calls to DLL The user s guide and function reference manual of PCIS DASK are in the CD Refer to the manual files in the All in One CD Manual_PDF Software PCIS DASKk These software drivers are shipped with the board Refer to the Software Installation Guide for installation procedures DAQ LVIEW PnP LabVIEW Driver DAQ LVIEW PnP contains VIs that are used to interface with the LabVIEW software package DAQ LVIEW PnP supports Win dows 95 98 NT 2000 XP The LabVIEW drivers are shipped free with the board You can install and use them without a license For more information about DAQ LVIEW PnP refer to the user s guide in the All in One CD 6 Introduction ADLINIC DAQBenchTM ActiveX Controls It is recommended for programmers familiar with ActiveX controls and VB VC programming to use the DAQBench ActiveX Con trol component library for developing applications The DAQBench is designed under Windows NT 98 environment For more information about DAQBench refer to the user s guide in the All in One CD Introduction 7 ADLINIC 8 Introduction ADLINK 2 Hardware Information This chapter provides information on the PCI 7442 7443 7444 card layout connectors and pin assignments 2 1 Card Layout Figure 2 1 shows the location of the PCI 7442 connectors switch and jumpers at gt at Figure 2 1 PCI 7442 Layo
25. 53 B19 IDO 113 GND A16 A50 IGND IDO 120 B52 B18 IDO 112 N C A17 A51 N C B51 B17 IDO 80 A18 A52 IDO 88 IGND B50 B16 IGND IDO 81 A19 A53 IDO 89 IGND B49 B15 IGND IDO 82 20 A54 IDO 90 IGND 48 B14 IGND IDO 83 21 A55 IDO 91 IGND B47 B13 IGND IDO 84 A22 A56 IDO 92 IGND B46 B12 IGND IDO 85 A23 A57 IDO 93 IGND 45 B11 IGND IDO 86 A24 A58 IDO 94 IGND B44 B10 IGND IDO 87 A25 A59 IDO 95 0014 B43 B9 0013 0011 26 A60 VDD12 IDO 111 B42 B8 IDO 103 A27 61 GND IDO 110 B41 B7 IDO 102 GND A28 A62 IGND IDO 109 B40 B6 IDO 101 A29 A63 IGND IDO 108 B39 B5 IDO 100 GND A30 A64 IDO_107 B38 B4 IDO_99 GND A31 A65 IGND IDO 106 B37 B3 IDO 98 GND A32 66 IDO 105 B36 2 IDO 97 GND A33 A67 IGND IDO 104 B35 B1 IDO 96 N C A34 A68 N C Hardware Information 21 ADLINIC p Pin Definition Pin Definition IDO n Isolated digital output channel n VDD9 common VDD junction for input channel 64 71 VDD10 common VDD junction for input channel 72 79 VDD11 common VDD junction for input channel 80 87 VDD12 common VDD junction for input channel 88 95 VDD13 common VDD junction for input channel 96 103 VDD14 common VDD junction for input channel 104 111 VDD15 common VDD junction for input channel 112 119 VDD16 common VDD junction for input channel 120 127 IGND Ground return path for isolated output channels
26. 7 A51 N C B51 B17 IDO 16 A18 A52 IDO 24 IGND B50 B16 IGND IDO 17 A19 A53 IDO 25 IGND B49 B15 IGND IDO 18 20 A54 IDO 26 IGND 48 B14 IGND IDO 19 21 A55 IDO 27 IGND B47 B13 IGND IDO 20 22 A56 IDO 28 IGND B46 B12 IGND IDO 21 A23 A57 IDO 29 IGND 45 B11 IGND IDO 22 A24 A58 IDO 30 IGND B44 B10 IGND IDO 23 25 A59 IDO 31 VDD6 B43 B9 005 003 26 A60 VDD4 DO 47 B42 B8 IDO 39 GND A27 A61 GND DO 46 B41 B7 IDO 38 GND A28 A62 IGND DO 45 B40 B6 IDO 37 A29 A63 IGND DO 44 39 B5 IDO 36 GND A30 A64 43 B38 4 IDO 35 GND A31 A65 IGND DO 42 B37 B3 IDO 34 GND A32 66 41 B36 2 IDO 33 GND A33 A67 IGND DO 40 B35 B1 IDO 32 N C A34 A68 N C Hardware Information 13 ADLINIC Pin Definition Pin Definition IDO n Isolated digital output channel n VDD1 common VDD junction for input channel 0 7 VDD2 common VDD junction for input channel 8 15 VDD3 common VDD junction for input channel 16 23 VDD4 common VDD junction for input channel 24 31 VDD5 common VDD junction for input channel 32 39 VDD6 common VDD junction for input channel 40 47 VDD7 common VDD junction for input channel 48 55 VDD8 common VDD junction for input channel 56 63 IGND Ground return path for isolated output channels V5V Onboard un regulated 5V power supply output N C No Connect
27. I 7 A42 IDI 15 8 B60 26 7 1 9 4 2 1021 63 B59 25 IDI 55 COM1 A10 A44 COM2 IDI 62 B58 24 IDI 54 1 A11 45 2 IDI 61 B57 B23 IDI 53 1 A12 46 2 12160 B56 22 IDI 52 1 A13 A47 COM2 IDI 59 B55 B21 IDI 51 1 14 48 2 10158 B54 20 IDI 50 1 A15 49 2 101 57 B53 B19 IDI 49 1 A16 A50 2 10156 B52 B18 101 48 N C A17 A51 N C N C B51 B17 IDI 16 A18 A52 IDI 24 COM6 B50 B16 5 DI 17 A19 53 IDI 25 6 B49 15 5 DI 18 A20 A54 IDI 26 6 B48 14 5 DI 19 21 55 101 27 6 B47 13 5 DI 20 22 56 101 28 6 B46 B12 5 DI 21 23 A57 IDI 29 6 B45 11 5 DI 22 24 58 101 30 6 B44 10 5 DI 23 25 59 101 31 6 B43 5 26 A60 COM4 IDI 47 B42 B8 IDI 39 A27 61 4 10146 B41 B7 IDI 38 A28 A62 COM4 IDI 45 B40 B6 IDI 37 A29 A63 COM4 10144 B39 5 IDI 36 A30 64 4 10143 B38 B4 101 35 A31 65 4 10142 B37 B3 IDI 34 A32 66 4 10141 B36 2 IDI 33 A33 67 4 10140 B35 1 IDI 32 A34 A68 N C Hardware Information 19 ADLINIC p Pin Definition Pin Definition IDI n Isolated digital in
28. MSB LSB BASE 0x8Ch R Read Back Start BASE 0x8Eh R IDO 15 0 BASE 0x90h R IDO 31 16 BASE 0x92h R IDO 47 32 BASE 0x94h R IDO 63 48 Bit value 0 Output Power MOSFET is OFF Initial value 1 Output Power MOSFET is ON Register Format ADLINK TECHNOLOGY INC J Watchdog Timer Load Safety DO Setup Read Back Registers The PCI 7442 provides a 32 bit watch dog timer WDT with 10 MHz clock The WDT counter loads the 32 bit value of two 16 bit WDT_LOAD_CONFIG Registers in turn The corresponding hexa decimal value you set determines the overflow time of WDT counter The overflow time is calculated by the value that you set multiplied 100 ns The timer interval is from 0 to 429 496 seconds Address R W Value Mapping MSB LSB BASE 0x94h WDT LOAD CONFIG 15 0 BASE 0x96h WDT LOAD CONFIG 31 16 When the WDT interrupt asserts you can set the system to send out Safety DO value by setting the SafetyOut Enable bit When WDT INT asserts the system process may halt or be offline This function thus prevents untoward damage You can configure the default 64 CH safety DO values which are stored in the flash memory When WDT interrupt asserts and the SafetyOut Enable bit is enabled the PCI 7442 enters the safety DO procedure which sends out the default safety value to 64 CH digital outputs You can program the 64 CH safety default DO values by access ing the last WDTSafety DO Setu
29. R IDI 111 96 BASE 0xC4h R IDI 127 112 Bit value 1 The input is ON 0 The input is OFF Inital value Register Format 47 ADLINIC COS Interrupt Control Registers The interrupt mode in the PCI 7443 is disabled by default You can write the registers listed below to enable the interrupt function In interrupt mode you may enable the COS Change of State inter rupt function to monitor the statuses of enabled input channels whenever the statuses change from 0 to 1 or from 1 to 0 After processing the interrupt request event you must clear the interrupt request in order to handle another interrupt request Take note that it takes time for a system to clear the interrupt Also any uncleared COS interrupt that comes before the previous interrupt is neglected To clear the interrupt request write 1 to the corre sponding bit The COS interrupt is enabled by four registers Because the 128 digital inputs are divided into four 32 bit onboard buses every 32 inputs are connected to a CPLD When users enable COS inter EAO BASE 0x06h the first CPLD CPLDO produces inter rupt signal while the first 32 bit inputs IDI 31 0 have change of state When users enable COS interrupt EA1 BASE 0x46h the second CPLD CPLD1 produces interrupt signal while the second 32 bit inputs IDI 63 32 have change of state When users enable COS interrupt EA2 BASE 0x86h the third CPLD CPLD2 duces interrupt signal w
30. Site Sales amp Service Telephone No Fax No Mailing Address http www adlinktech com service adlinktech com 886 2 8226 5877 886 2 8226 5717 9F No 166 Jian Yi Road Chungho City Taipei Hsien 235 Taiwan ROC ADLINK TECHNOLOGY AMERICA INC Sales amp Service Toll Free Fax No Mailing Address info adlinktech com 1 866 4 ADLINK 235465 1 949 727 2099 8900 Research Drive Irvine CA 92618 USA ADLINK TECHNOLOGY EUROPEAN SALES OFFICE Sales amp Service Toll Free Fax No Mailing Address emea adlinktech com 49 211 4955552 49 211 4955557 Nord Carree 3 40477 D sseldorf Germany ADLINK TECHNOLOGY SINGAPORE PTE LTD Sales amp Service Telephone No Fax No Mailing Address singapore adlinktech com 65 6844 2261 65 6844 2263 84 Genting Lane 07 02A Cityneon Design Center Singapore 349584 ADLINK TECHNOLOGY INDIA LIAISON OFFICE Sales amp Service Telephone No Fax No Mailing Address india adlinktech com 91 80 57605817 91 80 26671806 No 1357 Ground Floor Anupama Aurobindo Marg JP Nagar Ph 1 Bangalore 560 078 E A ADLINK TECHNOLOGY ADLINK TECHNOLOGY BEIJING Sales amp Service Telephone No Fax No Mailing Address market adlinkchina com cn 82 2 20570565 82 2 20570563 4F Kostech Building 262 2 Yangjae Dong Seocho Gu Seoul 137 130 Korea ADLINK TECHNOLOGY BEIJING Sales amp Service Telephone No Fax No Mailing A
31. ach TTL channel any time The voltage level suits with 5 V TTL level and 3 3 V TTL level But the driving strength of each channel is 4 mA Pay particular attention to the current consumption of the TTL channel Operation theory 31 ADLINK BA LOGY INC 32 Operation theory ADLINK BA TECHNOLOGY INC 4 Register Format This chapter provides the detailed descriptions of the register for mats intended for programmers who want to operate the card series through low level programming This chapter is intended for users that have basic understanding of the PCI interface The PCI 7442 7443 7444 card registers are all 16 bit wide and can only be accessed using 16 bit I O instructions The isolated digital input output control is by accessing registers mentioned in this chapter 4 1 7442 1 0 Registers Isolated Digital Input Register There are 64 isolated inputs on a PCI 7442 card The statuses of the 64 lines can be read from the four isolated input registers Each bit corresponds to each channel The bit value 1 means that the input is ON and 0 means that the input is OFF Address R W Value Mapping MSB bit15 LSB bit0 BASE 0x02h R IDI 15 0 BASE 0x04h R IDI 31 16 BASE 0x42h R IDI 47 32 BASE 0x44h R IDI 63 48 Bit value 1 The input is ON 0 The input is OFF Initial value Register Format 33 ADLINIC COS Interrupt Control Registers There
32. acket gt ADLINK All in One CD gt User s manual If any of the items is damaged or missing contact your dealer immediately NOTE The packaging of OEM versions with non standard con figuration functionality or package may vary according to different configuration requests CAUTION The boards must be protected from static discharge and physical shock Never remove any of the socketed parts except at a static free workstation Use the anti static bag shipped with the product to handle the board Wear a grounded wrist strap when servicing Introduction 5 ADLINIC PN 1 5 Software Support ADLINK provides versatile software drivers and packages to address different approaches in building a system Aside from pro gramming libraries such as DLLs for many Windows based sys tems ADLINK also provides drivers for other software packages including LabVIEW All software options may be found in the ADLINK All in One CD Programming library If you are writing you own programs the following function librar ies are available DOS Library For Borland C C and Visual C the functions descriptions are included in this user s guide PCIS DASK Included device drivers and DLL for Windows 98 NT 2000 XP A DLL is a binary compatible across Windows 98 NT 2000 XP That means all applications developed with PCIS DASK are compatible across Windows 98 NT 2000 XP The developing environment can be VB VC Delphi BC
33. ad Back Regis ters You can read back the direction statuses to check if the directions meet your need Address R W Value Mapping MSB LSB BASE 0x3C R TTL_IO_STATUS 15 0 BASE 0x3E R TTL_IO_STATUS 31 16 Bit value 0 I O direction is input Default 1 direction is output When the direction setting is output you can send out data through the TTL I O output channel Address R W Value Mapping MSB LSB BASE 0x40 W TTL_IO_DO 15 0 BASE 0x42 WwW TTL_IO_DO 31 16 Bit value 0 Output in low logic Default 1 Output in high logic Register Format 65 ADLINIC When the direction setting is input you can read data through the TTL I O input channel Address R W Value Mapping MSB LSB 0 40 TTL IO DI 15 0 0 42 TTL IO DI 31 16 Bit value 0 Input in low logic 66 1 Input in high logic Default Register Format ADLINK pw TECHNOLOGY INC 4 4 Handling PCI Controller Registers The 1 7442 7443 7444 card adopts the PLX PCI 9030 PCI bus controller You should notice some registers when you attempt to handle the card via low level programming The interrupt control register INTCSR Ox4Ch of PCI 9030 takes charge of all interrupt information from local bus to PCI bus When you want to develop your own interrupt function driver both interrupt reg
34. are sampled by a 33 MHz clock It means the pulse width of the digital input have to last longer than 31 ns or the COS latch register won t latch the correct input data The COS latch register will be erased after clearing the interrupt request Name Digital Input 8 CH are all enable E COS Latch register Interrupt Request Figure 3 2 COS Timing 28 Operation theory ADLINK COS detection architecture The COS interrupt system is used in PCI 7442 7443 COS inter rupt occurs when the any of enabled DI line sense the status changes either from HIGH to LOW or from LOW to HIGH The COS interrupt system can generate an interrupt request signal and the software can service this request with ISR Note that PCI 7442 has two banks bank 0 from DIO to 0131 and bank 1 from 0132 to 63 while 7443 has four banks bank 0 from DIO to DI31 and bank 1 from DI32 to 63 bank 2 from DI64 to DI95 and bank 3 from DI96 to 127 These banks are cascaded together toward the same IRQ line via CPLD You can use commands to know which bank or which DI line has COS when it happens Also you can use commands to disable or enable the COS function of certain DI lines The COS function for each is disabled by default Refer to Figure 3 3 for the COS detection architecture 010 0151 210 263 gt 3 CNT pis2 pi63 lt PCI Bridge 6164 0195 0164 01127 CN2 6196 0127 BUS Figure 3 3 COS
35. are two different interrupt modes in PCI 7442 Both interrupt modes are disabled by default You can write the registers listed below to enable the interrupt In the first mode users enable the COS Change of State interrupt function to monitor the status of enabled input channels and whenever the status change from 0 to 1 or 1 to 0 In the second mode you can enable the Watchdog Timer WDT Counter The interrupt asserts when the WDT Counter counts to zero After processing the interrupt request event you have to clear the interrupt request in order to handle another interrupt request Take note that it takes time for a system to clear the interrupt That is any COS interrupt or WDT interrupt that came before the previous interrupt and has not cleared will be ignored To clear the interrupt request write 1 to the correspond ing bit CLRn The WDT INT control registers are shown below The COS interrupt is enabled by two registers Because the 64 digital inputs are divided into two 32 bit onboard buses every 32 inputs are connected to a CPLD When you enable COS interrupt BASE 0x06h the first CPLD CPLDO generates an inter rupt signal while the first 32 inputs IDI 31 0 have state change When you enable COS interrupt EA1 BASE 0x46h the second CPLD CPLD1 generates an interrupt signal while the second 32 inputs IDI 63 32 have state change Address BASE 0x06h Reset Value 0x0000h Read Write W
36. atus Register Format 1 Enabled 0 Disabled 51 E A ADLINK TECHNOLOGY INC 52 Address BASE 0x46h Reset Value 0x0000h Read Write R Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 COS1E Bit15 Bit14 Bit13 Bit12 Bit1 1 Bit10 Bit9 14 0 Bit15 Address BASE 0x86h Reset Value 0x0000h Read Write R Not used COS1E COS 1 Interrupt enable status 1 Enabled 0 Disabled Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito 52 Bit15 Bit14 Bit13 Bit12 Bit1 1 Bit10 Bit9 Bit8 14 0 Bit15 Address BASE 0xC6h Reset Value 0x0000h Read Write R Not used COS2E COS 2 Interrupt enable status 1 Enabled 0 Disabled Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 COS3E Bit15 Bit14 Bit13 Bit12 Bit1 1 Bit10 Bit9 Bit14 0 Bit15 Not used COS3E COS 3 Interrupt enable status 1 Enabled 0 Disabled Register Format ADLINK BA TECHNOLOGY INC COS Setup Latch Registers The PCI 7443 provides the Change of State COS interrupt func tion in each digital input channel This function allows you to moni tor the status of input channels by setting these registers By enabling the COS Setup registers the card generates an interrupt when the corresponding channel cha
37. cards layout and pin definitions for internal and external con nectors Chapter 3 Operation Theory This section illustrates the tech nology features and functions of the cards Chapter 4 Register Format This chapter provides detailed descriptions of the register formats that are necessary to oper ate the cards Warranty Policy This presents the ADLINK Warranty Policy terms and coverages ADLINIC PN 1 3 Conventions Take note of the following conventions used throughout the man ual to make sure that you perform certain tasks and instructions properly NOTE Additional information aids and tips that help you per form particular tasks IMPORTANT Critical information and instructions that you MUST perform to complete a task WARNING Information that prevents physical injury data loss mod ule damage program corruption etc when trying to com plete a particular task ADLINK BA TECHNOLOGY INC M iii List of FIQUEFGS iv 1 introduction ici Flo ao nea db ra 1 VA ME 2 1 2 Applications att reine aides 2 1 8 SpecifICations 3 1 4 Unpacking Checklist esses 5 1 5 Software Support esses 6 Programming library 6 DAQ LVIEW PnP LabVIEW Driver 6 DAQBenchTM ActiveX
38. d BitO CLR2 COS 2 interrupt clear 1 Clear 0 No effect Bit8 EA2 COS 2 Interrupt enable disable Register Format 1 Enabled 0 Disabled 49 ADLINIC 50 Address BASE 0xC6h Reset Value 0x0000h Read Write W CLR3 Bit7 Bit Bits Bit2 Bito EA3 Bit15 14 Bit13 Bit12 11 Bit1O Bit9 Bits Bit15 9 Not used Bit7 1 Not used Bito CLR3 COS 3 interrupt clear 1 Clear 0 No effect Bit8 COS 3 interrupt enable disable 1 Enabled 0 Disabled Register Format ADLINK pw TECHNOLOGY INC Interrupt Status COS INT Control Read Back Registers When any COS interrupt occurs these registers provide informa tion to recognize the interrupt status and the interrupt setup condi tion read back Address BASE 0x06h Reset Value 0x0000h Read Write C3IS 215 C1IS COIS Bit7 Bits BitO COSOE Biti5 Bit14 Bit13 Bit12 1 Bits 14 4 Not used Bito CISO COS 0 INT Status 1 COS assert 0 COS not assert CIS1 COS 1 INT Status 1 COS assert 0 COS not assert Bit2 CIS2 COS 2 INT Status 1 COS assert 0 COS not assert Bi3 CIS3 COS 3 INT Status 1 COS assert 0 COS not assert Bit15 COSOE COS 0 Interrupt enable st
39. ddress market adlinkchina com cn 86 10 5885 8666 86 10 5885 8625 Room 801 Building E Yingchuangdongli Plaza No 1 Shangdidonglu Haidian District Beijing China ADLINK TECHNOLOGY SHANGHAI Sales amp Service Telephone No Fax No Mailing Address market adlinkchina com cn 86 21 6495 5210 86 21 5450 0414 Floor 4 Bldg 39 Caoheting Science and Technology Park No 333 Qinjiang Road Shanghai China ADLINK TECHNOLOGY SHENZHEN Sales amp Service Telephone No Fax No Mailing Address market adlinkchina com cn 86 755 2643 4858 86 755 2664 6353 C Block 2nd Floor Building A1 Cyber tech Zone Gaoxin Ave 7 5 High tech Industrial Park S Nanshan District Shenzhen Guangdong Province China ADLINK BA TECHNOLOGY INC Using this manual 1 1 Audience and scope This manual guides you when using ADLINK NuDAQ digital input output PCI cards The card s hardware and register informa tion are provided for faster application building This manual is intended for computer programmers and hardware engineers with advanced knowledge of data acquisition and high level program ming 1 2 How this manual is organized This manual is organized as follows Chapter 1 Introduction This chapter intoduces the NuDAQ digital input output PCI cards including the card features spec ifications software support information and package contents Chapter 2 Hardware Information This chapter presents the
40. down as a mode of intrrupt The interrupt asserts when the watch dog timer counter counts to zero You can control WDT enable and clear WDT INT by setting two bits WDTE and WIC in Bank2 WDT INT Control Hot Reset Hold Control Register The PCI 7442 also provides some special safety functions indus trial applications When the WDT interrupt asserts you can set the system to send out Safety DO value to prevent some untoward damage by setting the SOE bit When the system goes to an unexpected or normal hot system reset without turning off the sys tem power you can choose whether to allow the PCI 7442 board to retain the original DO values before the system hot reset or allow the PCI 7442 board to enter the power up initial procedure to send out the default initial DO values which you configured Refer to Section 3 3 for details By setting the HRHE bit users can enable Hot_Reset_Hold function anytime This function is spe cially useful for unstable environments Address BASE 0x8Ah Reset Value 0x0000h Read Write W WSOE WIC WDTE HRHE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito Bitl5 Biti4 Bit12 Bit10 Bit9 Bit8 Bit15 4 Not used Bito HRHE Hot Reset Hold Enable enables hot system reset DO hold function 1 Enabled 0 Disabled WDTE WDT interrupt enable disable 1 Enabled 0 Disabled Bit2 WIC WDT interrupt clear Register Format 45 E A
41. ear the inter rupt request the COS latch register automatically clears Since you can simply read these registers to know the statuses after interrupts these registers free the CPU from the overwhelming task of constantly polling all inputs enabling it to handle other tasks Address R W Value Mapping MSB LSB BASE 0x08h R IDI COS LATCH DATA 15 0 BASE 0x0Ah R IDI COS LATCH DATA 31 16 BASE 0x48h R IDI COS LATCH DATA 47 32 BASE 0x4Ah R IDI COS LATCH DATA 63 48 Bit value 1 The input is on 0 The input is off initial value Register Format 37 ADLINIC TTL IO Setup Status DO and DI Registers The PCI 7442 provides an extra 32 channel TTL function for optional applications These TTL I O channels are divided among two 16 bits banks and are divided between two connectors JP3 and JP4 You may choose the direction of each TTL channel any time by setting up the two bank TTL IO setup register Address R W Value Mapping MSB LSB BASE 0x0Ch W TTL_IO_SETUP 15 0 BASE 0x4Ch W TTL IO SETUPT 21 16 Bit value 0 direction is input default 1 direction is output When you set up the direction of TTL I O channels the statuses of setting can be read back through TTL IO Status Read Back Regis ter in each back You can read back the I O direction statuses to check if the settings are correct Addres
42. erMOSFET is OFF Initial value 1 Output PowerMOSFET is ON You do not have to set the register value for the Isolated DO Read Back Start All Ch PortO Port1 You only need to send out the address 0x00h BASE 0x02h BASE 0x0Ch in Read mode before reading all 128 bit all channels 64 bit portO port1 channel output data When the DO bank receives the Start command the 64 128 bit DO data readback procedure proceeds You can check if the DO readback procedure is finished by get nNDO_RBReady flag status Register Format ADLINK BA TECHNOLOGY INC Power up DO Setup Read Back Register After the system powers up the PCI 7444 can enter the initial pro cedure which sends out the default initial value to 128 CH digital outputs You can configure the default power up DO values and store them in the flash memory to prevent the DO from entering an unknown status when the system turns on You may set the 128 CH power up default DO values by access ing the Power up DO Setup Registers in turn After accessing the latest Power up DO Setup Register Base 0x24h the card needs at least 500 ms to finish the writing to the flash memory pro cedure You may check if the procedure is finished or not by the nAction_Ready flag Address R W Value Mapping MSB LSB BASE 0x16h W IDO 15 0 BASE 0x18h IDO 31 16 BASE 0x1Ah IDO 47 32 BASE 0x1Ch W IDO 63 48 BASE
43. et the system to send out the Safety DO value to prevent untoward dam age using the WSOE bit In addition when the system performs an unexpected or abnormal hot system reset you can set the PCI 7444 to retain its original DO values before system hot reset Oth erwise the PCI 7444 enters the power up initial procedure to send out the default initial DO values you configured By setting the HRHE bit you can enable the Hot Reset Hold function anytime This function is applicable for unstable operating environments Address BASE 0x3Ah Reset Value 0x0000h Read Write W WSOE WIC WDTE HRHE Bite Bits Biti Bito Biti5 Bit14 Bit13 Bit12 Biti1 Bit10 Bit9 Bit8 Bit15 4 Not used Bit3 WSOE WDT Safety DO send out enable 1 Function is enabled 0 Function is disabled default Bit2 WIC WDT interrupt clear 1 Clear WDT interrupt 0 No effect WDTE WDT interrupt enable control 1 WDT is enabled 0 WDT is disabled default BitO HRHE Enable hot system reset DO hold function Register Format ADLINIC 64 Address 0 Reset Value 0x0000h Read Write 1 Function is enabled 0 Function is disabled ARDYS SRDYS RBRDYS SOES WIS WDTES HRHES Bit4 Bit3 Bit2 Bit Biti5 4 Bit13 Bit12 Biti1
44. etting is input users can read data through the TTL input channel Address R W Value Mapping MSB LSB BASE 0x0Eh R TTL IO DI 15 BASE 0x4Eh R TTL_IO_DI 31 16 Bit value 0 Input in low logic 56 1 Input in high logic Default Register Format ADLINK BA TECHNOLOGY INC 4 3 PCI 7444 1 0 Registers Isolated Digital Output Read Back Registers The PCI 7444 has 128 isolated digital outputs These lines are divided between four output connectors CN1A CN1B CN2A and CN2B They are controlled by eight 16 bit registers Each digital output line is controlled by each bit of the eight control registers You must send out the corresponding DO output data and send out the start command in the end All 128 bit all channels 64 bit Port 0 or Port 1 DO data is then sent out after receiving the com mand BASE 0x08h 0x12h 0x14h The output device is Open Drain Power MOSFET Driver The Isolated DO Send Out At The Same 0 All Ch does not need any register value You only need to send out the address BASE 0x08h BASE 0x12h BASE 0x14h in Write mode after setting up all 128 bit all channel or 64 bit portO port1 channel output data When the DO back receives the Start command the 64 128 bit DO data is sent out at the same time You can check if the DO send procedure is finished by get nDO_SendReady flag status
45. hile the second 32 bit inputs IDI 95 64 have change of state When users enable COS interrupt BASE 0xC6 the fourth CPLD CPLD3 produces interrupt signal while the second 32 bit inputs IDI 127 96 have change of state Address BASE 0x06h Reset Value 0x0000h Read Write W CLRO Bit7 5 Bito Biti5 Bit14 Bit13 Bit12 11 Bit9 Bit15 9 Not used Bit7 1 Not used Bito CLRO COS 0 interrupt clear 1 Clear 0 No effect 48 Register Format Bit8 Address BASE 0x46h Reset Value 0x0000h Read Write W A ADLINK BA TECHNOLOGY INC COS 0 Interrupt enable disable 1 Enabled 0 Disabled CLR1 Bit7 Bit 5 Bits Bit2 Bito EA1 Bit15 14 Bit13 Bit12 Bit11 Bit1O Bit9 Bit15 9 Not used 1 Not used Bito CLR1 COS 1 interrupt clear 1 Clear 0 No effect Bit8 EA1 COS 0 Interrupt enable disable Address BASE 0x86h Reset Value 0x0000h Read Write W 1 Enabled 0 Disabled CLR2 Bit7 Bit 5 Bit3 Bit2 BitO EA2 Bit15 Bit14 Bit13 Bit12 11 Bit9 Bits Bit15 9 Not used Bit7 1 Not use
46. ial value Register Format ADLINK BA TECHNOLOGY INC TTL IO Setup Status DO and DI Register The PCI 7443 provides an extra 32 CH TTL function for optional applications These TTL I O channels are divided into two 16 bits banks These channels are divided between two connec tors JP3 and JP4 You can choose the direction of each TTL channel any time by setting up the two bank TTL IO setup register Address R W Value Mapping MSB LSB BASE 0x0Ch W TTL IO SETUPT 15 0 BASE 0x4Ch W TTL_IO_SETUP 31 16 Bit value 0 I O direction is input Default 1 direction is output When you set up the direction of TTL channels the status of the setting can be read through TTL IO Status Read Back Regis ters You can read back the I O direction statuses to check if the settings are correct Address R W Value Mapping MSB LSB BASE 0x0Ch R TTL_IO_STATUS 15 0 BASE 0x4Ch R TTL_IO_STATUS 31 16 Bit value 0 I O direction is input Initial value 1 direction is output When the direction setting is output you can send out data through the TTL I O output channel Address R W Value Mapping MSB LSB BASE 0x0Eh TTL IO DO 15 0 BASE 0x4Eh W TTL_IO_DO 31 16 Bit value 0 Output in low logic Default 1 Output in high logic Register Format 55 ADLINIC When the I O direction s
47. ined after hot system reset Yes Yes Programmable power up DO status Yes Yes cdam 758 Watchdog timer Yes Yes TTL I O channels 32 32 32 1250 Vrms isolation Yes Yes Yes Board ID feature Yes Yes Yes 1 2 Applications The PCI 7442 7443 7444 is suitable for these applications Machine automation Industrial ON OFF control External relay driving Signal switching Laboratory automation 2 Introduction ADLINK pw TECHNOLOGY INC 1 3 Specifications Optical isolated digital input PCI 7442 PCI 7443 only Input channels 64 PCI 7442 128 PCI 7443 Note Use an efficient cooling system and pay particular attention to the card and chassis temperature when using the digital input channels Input voltage High 5 V 28 V non polarity Low 0 V 1 5 V non polarity Input resistance 4 7 Isolated voltage 1250 Vnus Interrupt source Change of State COS Optical isolated digital output PCI 7442 PCI 7444 only Output channels 64 PCI 7442 128 PCI 7444 Output type Open drain power MOSFET driver Output device TPC8206 Output range 5V 40V Sink current 250 mA for all channel 60 100 duty 300 mA max Isolation voltage 1250 Vnus Data transfer Programmed Isolated 5 power supply PCI 7442 PCI 7444 only Output voltage 5 Output current 100 mA maximum at 40 C Programmable TTL
48. isters in PCI 9030 and in the PCI 7442 7443 7444 card have to work together For detailed information about the interrupt control register in PCI 9030 refer to the PCI 9030 databook The PCI 7442 7443 7444 card s function library provides simple and easy to use functions that handle interrupt procedures These functions eliminate the handling of the interrupt register in the PCI controller It is recommended that you use these functions instead of developing your own interrupt functions Register Format 67 ADLINIC 68 Register Format ADLINK pw TECHNOLOGY INC Warranty Policy Thank you for choosing ADLINK To understand your rights and enjoy all the after sales services we offer please read the follow ing carefully 1 Before using ADLINK s products please read the user man ual and follow the instructions exactly When sending in damaged products for repair please attach an RMA appli cation form which can be downloaded from http rma adlinktech com policy 2 All ADLINK products come with a limited two year war ranty one year for products bought in China gt The warranty period starts on the day the product is shipped from ADLINK s factory gt Peripherals and third party products not manufactured by ADLINK will be covered by the original manufactur ers warranty gt For products containing storage devices hard drives flash cards etc please back up your data before send ing them for repair
49. nal 68 Terminal B34 Terminal 68 Terminal B34 Terminal 1 Terminal A35 Terminal Terminal A35 CN2B CN1B Terminal 68 68 Terminal B35 Terminal B1 i i Terminal A34 Terminal B35 Terminal B1 Terminal A34 Figure 2 5 PCI 7440 Series Connector Pin Reference 12 Hardware Information ADLINK BA TECHNOLOGY INC 2 2 7442 Pin Assignments CN2 Connector CN2B CN2A V5V B68 B34 V5V IDO 0 A1 A35 IDO 8 IGND B67 33 IGND IDO 1 A2 A36 IDO 9 IGND B66 B32 IGND IDO 2 A37 IDO 10 IGND B65 31 IGND IDO 3 A4 A38 IDO 11 IGND B64 B30 IGND IDO 4 A5 A39 IDO 12 IGND B63 B29 IGND IDO 5 A6 A40 IDO 13 IGND B62 B28 IGND IDO 6 A7 A41 DO 14 IGND B61 B27 IGND IDO 7 A42 IDO 15 VDD8 B60 B26 VDD7 VDD1 AQ A43 VDD2 DO 63 B59 B25 1 55 A10 A44 IGND DO 62 B58 B24 1 54 A11 45 IGND DO 61 B57 B23 IDO_53 A12 46 DO 60 B56 B22 1 52 A13 A47 IGND DO 59 B55 B21 1 51 GND A14 A48 IGND DO 58 54 B20 1 50 A15 A49 IGND DO 57 53 B19 IDO 49 GND A16 A50 IGND DO 56 B52 B18 48 N C A1
50. nges its state Address R W Value Mapping MSB LSB BASE 0x08h IDI COS EN 63 0 BASE 0x0Ah IDI COS 16 BASE 0x48h W IDI COS EN 47 32 BASE 0x4Ah IDI COS EN 63 48 BASE 0x88h W IDI COS EN 79 64 BASE 0x8Ah IDI COS EN 95 80 BASE 0xC8h W IDI_COS_EN 111 96 BASE 0xCAh W IDI COS EN 127 112 IDI COS Change of State function enable IDI channel 0 127 0 Disable COS function 1 Enable COS function Register Format 53 E A ADLINK TECHNOLOGY 54 When COS occurs the COS Latch registers also latch the DI 31 0 DI 63 32 DI 95 64 and DI 127 96 data respectively Once you clear the interrupt request the COS Latch register clears automatically Since you can read these registers to know the statuses after interrupts these registers free the CPU from constantly polling all inputs and enable the system to handle more tasks Address R W Value Mapping MSB LSB BASE 0x08h R IDI COS LATCH DATA 15 0 BASE 0x0Ah R IDI_COS_LATCH_DATAJ31 16 BASE 0x48h R IDI COS LATCH DATA 47 32 BASE 0x4Ah R IDI COS LATCH DATA 63 48 BASE 0x88h R IDI COS LATCH DATA 79 64 BASE 0x8Ah R IDI_COS_LATCH_DATA 95 80 BASE 0xC8h R IDI COS LATCH DATA 111 96 BASE 0xCAh R IDI COS LATCH DATA 127 112 Bit value 1 The input is ON 0 The input is OFF Init
51. p register in turn After accessing the last WDTSafety DO Setup register BASE 0x9Eh it takes 500 ms to finish writing the procedure to the flash memory You can check if the procedure is finished or not by nAction Ready flag Address R W Value Mapping MSB LSB BASE 0x98h IDO 15 0 BASE 0x9Ah W 100 31 16 BASE 0x9Ch W IDO 47 32 BASE 0x9Eh W IDO 63 56 Bit value 0 Output Power MOSFET is OFF Initial value 1 Output Power MOSFET is ON Register Format 43 ADLINIC 44 You can read the configured the Safety DO values which are stored in the flash memory by sending out the WDTSafety DO ReadBack command BASE 0x96h The flash memory read pro cedure starts in 50 ms The finished flag can be checked by nAction Ready flag After the Read Back procedure you can read back the 64 bit WDTSafety DO Read Back registers in turn Address R W Value Mapping MSB LSB BASE 0x96h R Read Back Start BASE 0x98h R IDO 15 0 BASE 0x9Ah R IDO 31 16 BASE 0x9Ch R IDO 47 32 BASE 0x9Ch R IDO 63 56 Bit value 0 Output Power MOSFET is OFF Initial value 1 Output Power MOSFET is ON Register Format ADLINK BA TECHNOLOGY INC WDT INT Control Hot Reset and Hold Control Register There are two different interrupt modes in PCI 7442 the COS INT function and the watch dog timer WDT You may enable the WDT counter and let it count
52. put channel n common junction for input channel 0 7 COM2 common junction for input channel 8 15 COM3 common junction for input channel 16 23 COM4 common junction for input channel 24 31 COM5 common junction for input channel 32 39 COM6 common junction for input channel 40 47 COM7 common junction for input channel 48 55 COM8 common junction for input channel 56 63 20 Hardware Information ADLINK BA TECHNOLOGY INC 24 PCI 7444 Pin Assignments CN2 Connector CN2B CN2A V5V B68 B34 V5V IDO 64 1 A35 IDO 72 IGND B67 33 IGND IDO 65 A2 A36 IDO 73 IGND B66 B32 IGND IDO 66 A37 IDO 74 IGND B65 31 IGND IDO 67 A4 A38 IDO 75 IGND B64 B30 IGND IDO 68 5 A39 IDO 76 IGND B63 B29 IGND IDO 69 A40 IDO 77 IGND B62 B28 IGND IDO 70 A41 DO 78 IGND B61 B27 IGND IDO 71 A8 A42 IDO 79 VDD16 B60 26 0015 009 9 A43 VDD10 IDO 127 59 B25 IDO 119 GND A10 A44 IGND IDO 126 B58 24 IDO 118 A11 45 IGND IDO 125 B57 B23 IDO 117 GND A12 A46 IGND IDO 124 B56 B22 IDO 116 A13 47 IGND IDO 123 55 21 IDO 115 GND A14 A48 IGND IDO 122 B54 B20 IDO 114 GND A15 A49 IGND IDO 121 B
53. ranty is not transferable or extendible Other categories not protected under our warranty 4 Customers are responsible for shipping costs to transport damaged products to our company or sales office 5 To ensure the speed and quality of product repair please download an RMA application form from our company web site http rma adlinktech com policy Damaged products with attached RMA forms receive priority If you have any further questions please email our FAE staff service adlinktech com 70 Warranty Policy
54. s OFF Initial value 1 Output PowerMOSFET is ON You do not need to set any register for the WDTSafety DO Read Back Start You only need to send out the address BASE 0x28h in Read mode before reading all 128 channel output safety data When the DO bank receives the Start command the flash memory read procedure starts after 100 ms You can check if the proce dure is finished by get nAction Reagy flag status Address R W Value Mapping MSB LSB 0x28h R Read Back Start BASE 0x2Ah R IDO 15 0 BASE 0x2Ch R IDO 31 16 BASE 0x2Eh R IDO 47 32 BASE 0x30h R IDO 63 48 0x32h IDO 79 64 0x34h IDO 95 80 0x36h IDO 111 96 0x38h IDO 127 112 Bit value 0 Output PowerMOSFET is OFF Initial value 1 Output PowerMOSFET is ON 62 Register Format ADLINK pw TECHNOLOGY INC WDT INT Control Hot Reset Hold Control Register The PCI 7444 has the watchdog timer as interrupt mode The WDT interrupt mode is disabled by default In this mode you can enable the WDT to count down The interrupt asserts when the WDT Counter reaches to zero You can enable the WDT and clear the WDT INT by setting two Bit WDTE and WIC in the WDT INT Control Hot Reset Hold Control Register The PCI 7444 provides some special safety functions for industrial applications When the WDT interrupt asserts you can s
55. s R W Value Mapping MSB LSB BASE 0x0Ch R TTL_IO_STATUS 15 0 BASE 0x4Ch R TTL_IO_STATUS 31 16 Bit value 0 I O direction is input default 1 direction is output When the direction setting is output you can send out data through the TTL output channel Address R W Value Mapping MSB LSB BASE 0x0Eh W TTL IO DO 15 0 BASE 0x4Eh W TTL_IO_DO 31 16 Bit value 0 Output is low default 1 Output is high 38 Register Format ADLINK BA TECHNOLOGY INC When the I O direction setting is input you can read data through the TTL I O input channel Address R W Value Mapping MSB LSB BASE 0x0Eh R TTL_IO_DI 15 0 BASE 0x4Eh R TTL_IO_DI 31 16 Bit value 0 Input is low 1 Input is high Initial value Register Format 39 ADLINIC Isolated Digital Output and Read Back Registers There are 64 isolated digital outputs on each PCI 7442 board These lines are divided between two output connectors CN2A and CN2B These are controlled by four 16 bit registers in bank2 Each digital output line is controlled by each bit of the four control registers You must send out the corresponding DO output data then send out the start command to bank2 to complete the pro cess The 64 bit DO data will then be sent out at the same time The output device type is Open Drain Power MOSFET driver DO Send Out Start does not need an
56. t multiplied 100 ns The timer interval is from 0 to 429 496 seconds Address R W Value Mapping MSB LSB BASE 0x36h W WDT_LOAD_CONFIG 15 0 BASE 0x38h WDT LOAD 16 When the WDT interrupt asserts you can set the system to send out Safety DO value by setting the SafetyOut Enable bit When WDT INT asserts the system process may halt or be offline This function thus prevents untoward damage You can configure the default 128 CH safety DO values which are stored in the flash memory When WDT interrupt asserts and the SafetyOut Enable bit is enabled the PCI 7444 enters the safety DO procedure which sends out the default safety value to 128 CH digital outputs You can program the 128 CH safety default DO values by access ing the last WDTSafety DO Setup register in turn After accessing the last WDTSafety DO Setup register BASE 0x34h it takes 500 ms to finish writing the procedure to the flash memory You can check if the procedure is finished or not by nAction Ready flag Register Format 61 ADLINIC Address R W Value Mapping MSB LSB BASE 0x26h W IDO 15 0 BASE 0x28h IDO 31 16 BASE 0x2Ah W IDO 47 32 0x2Ch IDO 63 48 BASE 0x2Eh IDO 79 64 BASE 0x30h IDO 95 80 BASE 0x32h W IDO 111 96 BASE 0x34h W IDO 127 112 Bit value 0 Output PowerMOSFET i
57. to CISO COS 0 interrupt status 1 COS interrupt assert 0 COS interrupt no assert Bit1 CIS1 COS 1 interrupt status 1 COS interrupt assert 0 COS interrupt no assert Bit15 COSOE COS 0 interrupt enable status 1 COS 0 interrupt enabled 0 COS O interrupt disabled Address BASE 0x46h Reset Value 0x0000h Read Write R Bit 5 Bit2 Bit15 Bit14 Bit13 Bit12 Bit1O Bit9 Bits Bit14 0 Not used Bit15 COS1E COS 1 interrupt enable status 36 1 COS 1 interrupt enabled 0 COS 1 interrupt disabled Register Format ADLINK BA TECHNOLOGY INC COS Setup Latch Registers The PCI 7442 provides a Change of State COS interrupt function on any one of digital input channel This function allows you to monitor the status of digital channels by setting these regis ters By enabling the COS Setup registers it will generate an interrupt when the corresponding channel changes its state Address R W Value Mapping MSB LSB BASE 0x08h IDI COS EN 15 0 BASE 0x0Ah W IDI_COS_EN 31 16 BASE 0x48h IDI COS EN 47 32 BASE 0x4Ah W IDI COS EN 63 48 IDI COS n Change of State function enable of IDI channel n n 0 63 Bit value 0 Disable COS function 1 Enable COS function When COS occurs the COS latch registers also latch the IDI 31 0 IDI 63 32 data respectively Once you cl
58. ut 1 OCN2 64 CH isolated digital output connector 2 64 CH isolated digital input connector 3 51 Board ID DIP switch 4 16 0 15 TTL connector 5 JP4 16 15 31 TTL connector Hardware Information 9 ADLINK p Figure 2 2 shows the location the PCI 7443 connectors DIP Switch LT NH u rt tt tt rt nt att 0 Figure 2 2 7443 Layout CN2 64 CH isolated digital input connector IDI 64 127 CN1 64 CH isolated digital input connector IDI 0 63 1 Board ID DIP switch JP3 16 CH 0 16 TTL connector or BR ow Pp JP4 16 CH TTL16 31 TTL I O connector 10 Hardware Information ADLINK Figure 2 3 shows the location of the PCI 7444 connectors and DIP switch Figure 2 3 PCI 7444 Layout 1 CN2 64 CH isolated digital output connector IDO 64 127 2 64 CH isolated digital output connector IDO 0 63 3 S1 Board ID DIP switch 4 16 0 15 TTL connector 5 16 15 31 TTL connector Hardware Information 11 ADLINIC Pp Bracket Layout Es CN2B CN2A 7 e e Figure 2 4 PCI 7440 Series Card Bracket Connector Pin Reference Termi
59. y register value You only need to send out the address BASE 0x88h in Write mode after setting up all 64 bit channel output data When the back2 receives the Start command the 64 bit DO data is sent out at the same time You can check if the DO send procedure is finished by get nDO_SendReady flag status Address R W Value Mapping MSB LSB BASE 0x80h W IDO 15 0 BASE 0x82h IDO 31 16 BASE 0x84h IDO 47 32 BASE 0x86h W IDO 63 48 BASE 0x88h W Send Out Start Bit value 0 Output Power MOSFET is OFF Initial value 1 Output Power MOSFET is ON 40 Register Format ADLINK pw TECHNOLOGY INC The isolated DO statuses can be read back from the registers When you want to read the 64 bit DO statuses you must first send the Read Back Start command BASE 0x80h You can in turn read the isolated DO when DO read back procedure is ready DO ReadBack Start does not need any register value You only need to send out the address BASE 0x80h in Read mode before reading back all 64 bit channel output data When the back2 receives the Start command the 64 bit DO data readback procedure proceeds You can check if the DO readback procedure is finished by get nDO_RBReady flag status Address R W Value Mapping MSB LSB BASE 0x80h R DO Read Back Start BASE 0x82h R IDO 15 0 BASE 0x84h R IDO 31 16 BASE 0x86h R IDO 47 32 BASE 0x88h R IDO

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