Digital Circuit Design Using Xilinx ISE Tools
Contents
1. amp bitwise nand O fill logical logical case case O fill logical versions are legal for real It lt lt or equal gt gt or equal O fill all arelegal for real lt lt shift left gt shift right zero fill no ve shifts shift by x or z results in unknown addition subtraction if any bit is x or z for then entire result is unknown multiply divide modulus integer divide truncates fraction legal for real Verilog Unary Operators Operator Name Examples logical negation 1123 is bO O 1 or x for ambiguous legal for real bitwise unary negation blOxz is 1 bO1xx unary reduction and amp 4 b1111 is 1 bl amp 2 bxl is 1 bx amp Z bzl is 1 bx unary reduction nand amp 4 bl111 is 1 bO amp 2 bxl1 is 1 bx unary reduction or Note unary reduction nor Reduction is performed left first bit to right unary reduction xor Beware of the non associative reduction operators unary reduction xnor z is treated as x for all unary operators unary plus 2 bxz is 2 bxz m is the same as m legal for real unary minus 2 bxz is x m is unary minus m legal for real Source ASIC Design by Smith http www ee eng hawaii edu msmith ASICSs Files pdf CH1 1 3 pdf Table 1 Verilog Operators 6 Continuous assignments Continuous assignments are sometimes known as data flow statements because they describe how data moves from one place ei2. 4 b0001 S1 4 b0010 S2 4 bp0100 S3 4 b1000 Internal Variables reg SIZE 1 0 state Seq part of the FSM reg SIZE 1 0 next state combo part of FSM Moore State machine Code starts Here Determine the next state for each state in the state machine using the input sequence given to it The output next state is combinatorial in nature always state or in seq begin FSM COMBO next state 4 b0001 case state SO if in seq 1 bl begin next state S1 end else begin next state S0 end S1 if in seq 1 b0 begin next state S2 end else begin next state S1 end S2 if in seq 1 bl begin next state S3 end else begin next state S0 end S3 if in seq 1 bl begin next state S1 end else begin next state S2 ptb dkb 2013 37 EE 3320 end Always include a Default state in your state machine default next state S0 endcase end always posedge clk begin FSM SEQ if reset 1 b0 begin state lt CK2Q SO end else begin state lt CK2Q next state end end always state or reset begin OUTPUT LOGIC if reset 1 b0 begin out seq lt CK2Q 1 b0 end else begin case state SO begin out seq lt 1 b0 end S1 begin out seq 1 b0 end S2 begin out seq 1 b0 en
3. Digital Circuit Design Using Xilinx ISE Tools Table of Contents OO N Un A J O OO 2 Introduction Programmable logic devices FPGA Creating a new project in Xilinx ISE 3 Opening a project 3 2 Creating an Verilog input file for a combinational logic design 3 3 Editing the Verilog source file Compilation and Implementation of the Design Functional Simulation of Combinational Designs 5 Adding the test vectors 5 2 Simulating and viewing the simulation result waveforms 5 3 Saving the simulation results Preparing and downloading bitstream for the Spartan FPGA Testing a Digital logic circuit 7 Observing the outputs using the on board LEDs and Seven Segment Display Design and Simulation of sequential circuits using Verilog 9 Design of Sequential Circuits 9 2 Simulation of Sequential Circuits Design and Simulation of Finite State machines in Verilog 10 Hierarchical circuit design using Modules 11 Post synthesis Timing simulation with Modelsim Appendix A Verilog Hardware Modeling Introduction to the Verilog Language B Digilent BASYS board ptb dkb 2013 1 EE 3320 1 Introduction Xilinx Tools is a suite of software tools used for the design of digital circuits implemented using Xilinx Field Programmable Gate Array FPGA or Complex Programmable Logic Device CPLD The design procedure consists of a design entry b compilation and implementation of the design c f
4. Yellow Data ports Pmod connector signals USB signals HIE a B 2 Testing the Digilent board The Digilent Adept tool can be used to test the functionality of a BASYS board as follows e Connect the board to the USB and set the power switch to ON e Run Digilent Adept e Click on Test gt Start Test ptb dkb 2013 60 EE 3320 iA Digilent Adept BASYS 2 Connect Basse 00 v Product Basys2 250 Test Register I O File I O O Ex Settings Coa Board information loaded Found device ID f5045093 Found device ID 11c1a093 Initialization Complete Device 1 XC3S250E Device 2 XCF02S Figure B 1 The Digilent Adept test function e The tool shows you the current switch configuration and the display counts 0000 1111 FFFF ptb dkb 2013 A Digilent Adept BASYS 2 Connect Besys2 v Product Basys2 250 Test Register I O File I O I O Ex Settings ME m Buttons EOD Start Test Stop Test Device 2 XCF02S Figure B 2 Testing the Digilent board 61 EE 3320
5. 4 HUI Sx Instanc Memory i Source m s Default wcfg B Console This is a Full version of ISim Time resolution is 1 ps Simulator is doing circuit initialization process Finished circuit initialization process ISim gt E Console CompilationLog Breakpoints i Find in Files Results cn Search Results Figure 30 The iSIM window launched from Project Navigator Behavioral simulation using ModelSim You can also use ModelSim to simulate your design To use ModelSim ensure that the Simulator field is set to Modelsim PE Verilog in Project Design Properties you may change it back to iSIM if you so choose as shown in Figure ptb dkb 2013 49 EE 3320 ar Design Properties Name Location Working directory Description Project Settings Property Marne C Wsers ord091020 mux4x1 C Wsers ord091020 mux4tx 1 Top Level Source Type Product Category Farniby Device Package Speed Synthesis Tool Simulator Preferred Language Property Speco in Project File All Spartan3E AC3S250E CP132 4 AST VHDL Veriloq Modelsim PE Verilog Verilog Store all values aa Figure 31 Changing the simulator field in Design Properties a Eie He Ie e 1 Double clicking on the Simulate Behavioral Model will launch the ModelSim simulator interface In the Library window click on Work directory all designs are saved in the Work directory choose the test bench that you
6. bilinxlbinor gate Add to project Xilinx ISE software Select Verilog Module and in the File Name area enter the name of the Verilog source file you are going to create Also make sure that the option Add to project is selected so that the source need not be added to the project again Then click on Next to accept the entries This pops up the following window Figure 7 ptb dkb 2013 9 EE 3320 New Source Wizarc Define Module Specify ports for module Module name Direction In the Port Name column enter the names of all input and output pins and specify the Direction accordingly A Vector Bus can be defined by entering appropriate bit numbers in the MSB LSB columns Then click on Next to get a window showing all the new source information Figure 8 ptb dkb 2013 10 EE 3320 Summary Project Navigator will create a new skeleton source with the following specifications Add to Project Yes Source Directory C ilinx binlor gate Source Type Verilog Module Source Name or gate v Module name or_gate Port Definitions a b Z Figure 8 New Source Wizard window snapshot from Xilinx ISE software Once you click on Finish the source file will be displayed in the sources window in the Project Navigator Figure 1 If a source has to be removed just right click on the source file in the Sources in Project window in the Project Navigator and select Remove in that Then select Project
7. gt Delete Implementation Data from the Project Navigator menu bar to remove any related files 3 3 Editing the Verilog source file The source file will now be displayed in the Project Navigator window Figure 9 The source file window can be used as a text editor to make any necessary changes to the source file All the input output pins will be displayed Save your Verilog program periodically by selecting the File gt Save from the menu You can also edit Verilog programs in any text editor and add them to the project directory using Add Copy Source ptb dkb 2013 11 EE 3320 ISE Project Navigator O 76xd C Users grd091020 or_gate or_gate xise or gate v Bl File Edit View Project Source Process Tools Window Layout Help be Mel X do a AABRFAA SEDAN PT Design O Gx timescale ins 1ps yj View Implementation M Simulation SILLI Company dg Hierarchy Engineer te or gate E3 xc3s50 5pq208 Create Date 14 50 12 07 24 2013 Wee or_gate or_gate v Design Name 4 Module Name or gate Project Name Target Devices Tool versions Description Dependencies Revision Revision 0 01 File Created Additional Comments No Processes Running Processes orate MUI LTTE LALLA A MM A IM module or gate a amp B fim Be B Design Summary Reports Design Utilities User Constraints Synthesize XST Imple
8. reset St top fsmO clk sto Ef top fsm state 0001 0001 X000 yoron ogo jyo100 yooo Jo100 T1000 Foor jo100 jypooi yo010 Yoroo y1o00 y0100 jJDOO GH top fsm next state 0001 0001 Jno10 0001 Too10 o100 1000 Joo yooo JDO01 Atop fsm in seq sto Atop fsm out seq 0 Now 500000 ps Cursor 1 218120 ps 4 ria A i E O ps to 216228 ps LESE ptb dkb 2013 39 EE 3320 9 1 2 Mealy State Machine Example The state machine diagram of the Mealy State machine for sequence detector example is shown below uU 1 1 define CK2Q 5 Defines the Clock to Q Delay of the flip flop module mealy fsm reset clk in seq out seq input reset input clk input in seq output out seq reg out seq reg in seq reg 7 Parameters defining State machine States parameter SIZE 3 parameter SO 3 b001 S1 3 b010 S2 3 b100 Internal Variables reg SIZE 1 0 state Seq part of the FSM reg SIZE 1 0 next state combo part of FSM i ne Register the input always posedge clk begin REG INPUT if reset 1 b0 begin in seq reg lt CK2Q 1 b0 end else begin in seq reg lt CK2Q in seq end end esee Mealy State machine Code starts Here De
9. 1750 100 a lt Tpl Db lt pL 100 end endmodule a ISE Project Navigator O 76xd C Users grd091020 or_gate or_gate xise TB or gate v B File Edit View Project Source Process Tools Window Layout Help D amp Ediz xoBxlec 255 a X m unmc v r f Design en8x a jj View QE Implementatio gt output a l Behavioral eps b cia input z Fey op Module top or Hierarchy Associated Module reg a b declaration that a and b are registers di E or gate Instantiate the Unit Under Test UUT 3 2 3 xc3s100e 4cp132 2 or gate uut 7 or gate v a a i lv or tb v b b Iz Zz z m Js z initial Qo begin test stimuli a lt 1 b0 b lt 1 b0 100 a lt 1 b0 b lt i bi 100 a lt 1 b1 b lt 1 b0 i 100 No Processes Runni Ld a in a lt 1 bi Py No single design module is selected b lt 1 bi ay Design Utilities 100 end ET endmodule m m kg EL namay oL B Figure 16 Simulation window in ISE showing the newly created test bench ptb dkb 2013 19 EE 3320 5 2 Simulating and Viewing the Output Waveforms In the process window right click on Simulate Behavioral Model and click on Run eR RR RR o RR IR IR E E E E E E E E E ER mm File Edit Meu Project Source Process Tools Window Layout Help Deas x E xe e i we s se 2 a 2X c B om a Design Y mif View 7
10. 3320 ETEEN Ha 2 lv S Figure 5 Create New source window snapshot from Xilinx ISE software If you would like to create a new source file from the ISE window right click on the project name and choose New source or click on the New source button on the toolbar as shown in Figure 5 You may also choose Project gt New Source from the menu 3 2 Creating a Verilog HDL input file for a combinational logic design In this lab we will enter a design using a structural or RTL description using the Verilog HDL You can create a Verilog HDL input file v file using the HDL Editor available in the Xilinx ISE Tools or any text editor If adding an already existing source file v file to the project in the project Navigator window select Project gt Add Copy Source and browse through the disk for the source file If creating a new source file in the Project Navigator window select Project gt New Source A window pops up as shown in Figure 6 Note Add to project option is selected by default If you do not select it then you will have to add the new source file to the project manually ptb dkb 2013 8 EE 3320 Select Source Type Select source type file name and its location 4 IP CORE Generator amp Architecture Wizard Schematic System Generator Project User Document Py Verilog Module ti Verilog Test Fixture j VHDL Module VHDL Library P VHDL Package VHDL Test Bench C
11. a b c d sel y input a b c d input 1 0 sel output y reg y always a or b or c or d or sel case sel a b Eu 3 y d default y 1 b0 One bit binary value 0 endcase endmodule In the example shown sel is the 2 bits wide select input to the multiplxer The default case in the case statement is reached when the variable value does not match any of the case options The 4x1 multiplexer can also be implemented using a set of if then else constructs as follows module mux4x1 a b c d sel y input a b c d input 1 0 sel output y reg y always a or b or c or d or sel if sel 2 b00 y a else if sel 2 b01 y b else if sel 2 b10 y c else if sel 2 b11 y d else y 1 b0 endmodule Even though both the code segments shown above realize a 4x1 multiplexer each one of them leads to a different hardware implementation for the given logic Explaining the hardware implementations for specific Verilog construct 1s beyond the scope of this document Interested readers can refer to the links in the Verilog tutorial available in Appendix A ptb dkb 2013 13 EE 3320 4 Compilation and Implementation of the Design The design has to be compiled and implemented before it can be checked for correctness by running functional simulation or downloaded onto the prototyping board With the top level Verilog file opened can be done by double clicking that file in
12. circuit the states can be represented by the following ways e Binary encoding In this each of the state is represented in binary code 1 e 000 001 010 e Gray encoding In this each of the state 1s represented in gray code 1 e 000 001 011 e One Hot In this only one bit is high and rest are low i e 0001 0010 0100 1000 e One Cold In this only one bit is low rest are high 1 e 1110 1101 1011 0111 9 1 State Machine Design in Verilog State machine design in Verilog is illustrated with the following example Example Use Verilog HDL to design a sequence detector with one input X and one output Z The detector should recognize the input sequence 101 The detector should keep checking for the appropriate sequence and should not reset to the initial state after it has recognized the sequence The detector initializes to a reset state when input RESET is activated For example for input X 110110101 FSM output Z 000100101 ptb dkb 2013 36 EE 3320 9 1 1 Moore State Machine Example The state machine diagram of the Moore State machine for sequence detector example is shown below define CK2Q 5 Defines the Clock to Q Delay of the flip flop module moore fsm reset clk in seq out seq input reset input clk input in seq output out seq reg out seq Parameters defining State machine States parameter SIZE 4 parameter SO
13. module in a single hierarchy The module definition by itself does not create a module Modules are created by being instantiated in another module like this module module name 1 lt portlist gt module name 2 instance name gt porLtlist endmodule top type 3 type 3 module top typel child Ipbrts port indicates a port list type childHiports f which will be explained later endmodule module tvpel p module type2 pogytzs types leaf3 portz typel nodel hortz endmodule module tvype3 ports 5 15 odule does not instantiate any other modules endmodule ptb dkb 2013 59 Appendix B This section contains some useful information on the Digilent BASYS board that will be used in this lab For further details please refer to the Digilent user s manual B 1 Spartan 3E pin definitions Basys2 Spartan 3E pin definitions C CC ED NN CA CF ie m al zz no w e b C2 LE e SW7 r4 O C2 AN2 C3 Mi2 CG Li4 CA Li3 MEME L2 F13 F14 D13 13 14 G12 Q o N HI y Go ii Co d o MCLK RCCLK Gi BTN3 r p J3 B13 TCK FPGA Fi2 ANO K3 SW2 A2 TDOUSB Ki2 Bi o A4 TDO S8 M3 TTS viwe e w A12 Bi2 Bit B BS Ba AS ATO Bo AQ P4 FPGA pin definition table color key Gre Not available to user Green User O devices
14. or gate design ptb dkb 2013 21 EE 3320 6 Preparing and downloading bitstream file for the Spartan FPGA A bitstream file needs to be prepared for each design and downloaded onto the Digilent prototyping board 6 1 Generating a User Constraint File In order to test the design in the Digilent board the inputs need to be connected to the switches buttons on the board and the outputs need to be connected to the onboard LED s This is specified by a User Constraint File ucf file To create a UCF for your design do the following ue ISE Project Navigator O 76xd CN g B File Edit View Project Source Process i a i S BA alAli S aAa m a O x C M Simulation E ES xc35250e 4cp132 mI top top or tb tb or gate tb or gate v E a m or gate or gate or gate v or gate uct sl E T FQ No Processes Running Processes or gate or gate x Design Summary Reports Design Utilities Create Schematic Symbol View Command Line Log File View HDL Instantiation Template User Constraints Create Timing Constraints LO Pin Planning PlanAhead Pre Synthesis VO Pin Planning Plan amp head Past Synthesis C Floorplan AreayTO Logic PlanAhead 3 Synthesize XST Implement Design Translate Ed Map E PD Place amp Route pE Generate Programming File iEn LUN Tal re are BI Ice l Libraries Figure 19 Launching XilinxPlanAhead from Xilinx ISE Double click on the Flo
15. ord09 1020 mux4x 1 VHDL Library e VHDL Package VHDL Test Bench File name Location v Add to project Figure 26 Creating a text fixture in Xilinx ISE Associate your design with the test bench that you are about to create by selecting mux4x1 as the source and click on Next and then Finish ptb dkb 2013 46 EE 3320 Figure 27 Associating the testbench with the design The tool generates a test bench with some boilerplate code as shown in Figure B File Edit View Project Source Process Tools Window Layout Help iDn8Hdi ixoBxlee rr eRpr ali zans N rfi Design eDn8x is p 19 Revision 20 Revision 0 01 File Created 21 Additional Comments Hierarchy 22 E E mudd a3 MI M MB B MM M HL Bg M LL P PL P P P Cg M HL PL P P P M LLL M HL P P P P M HL CL C CC Gg M AAT oe Gh gA xc3s250e 4cp132 24 g E v muxbd tb muxbd tb v E 25 module mux4xi tb e V uut mud muxbd 26 A 27 Inputs 28 reg a a 29 reg b 7 30 reg C 26 31 reg d pur 32 reg 1 0 sel Q ss Unit under test UUT Q 34 outputs 35 wire y 36 37 Instantiate the Unit Under Test UUT 38 mux4xi uut 39 a a cae 40 ba Code automatically generated by Xilinx 41 Cc c 2 id ISE You may edit this by adding your 43 sel sel Lb rides scr gt m own test bench or modify it suitably ec Processes muxdxl tb 45 E a ISim Simulator 4
16. project properties Select the device and design flow for the project Property Narne Product Category Family Device Package Speed Top Level Source Type Synthesis Tool XST HDL Vellog vr Simulator Modelsim SE Verilog Preferred Language ri Property Specification in Project File Store all values O v Manual Compile Order VHDL Source Analysis Standard VHDL93 S O ee Enable Message Filtering Figure 3 New Project Wizard Project settings For each of the properties given below click on the value area and select from the list of values that appear o Device Family Family of the FPGA used In this laboratory we will be using the Spartan3E FPGAs ptb dkb 2013 5 EE 3320 o Device The number of the FPGA device Note the device number on the FPGA on the Digilent board If you are unsure ask the TA gt E 733 8 E TCLs Sy Ae pe J ous I3 N T una d AA DIGILENT s005 dc ad THEORY LE NN Check your board for the device number o Package The type of package with the number of pins The Spartan FPGA used in this lab is packaged in C6DGQ which is equivalent to CPG132 package If you are unsure ask the T A o Speed The Speed grade is 4 ptb dkb 2013 6 EE 3320 o Synthesis Tool XST VHDL Verilog o Simulator The tool used to simulate and verify the functionality of the design Choose ISim as the simulator Then click on N
17. the HDL editor window in the right half of the Project Navigator and the view of the project being in the Module view the Implement Design option can be seen in the Process Window Design Entry Utilities and Generate Programming File options can also be seen in the process view The former can be used to include user constraints 1f any and the latter will be discussed later To compile the design expand the Implement Top Module Figure 10 by clicking on Process gt Implement Top Module OR by right clicking on the design and choosing Implement Top Module It will go through steps like Check Syntax Compile Logic Interpret Feedbacks Reformat Logic and Optimize Hierarchy If any of these steps could not be done or done with errors it will place a IQ mark in front of that otherwise a tick mark will be placed after each of them to indicate the successful completion If everything 1s done successfully a mark will be placed before the Synthesize XST option If there are warnings one can see mark in front the Console window present at the bottom of the Navigator window Every time the design file is saved all these marks disappear asking for a fresh compilation K ISE Project Navigator O 6xd CAUsersygrd091020Nor gatexXor gate xise or gate v je g Eile Edit View Project Source Tool
18. time or event controls as well as all of the control constructs in the language As a result an initial block may cause activity to occur throughout the entire simulation of the model When the initial statement finishes execution the initial block terminates If the initial statement is a compound statement then the statement finishes after its last statement finishes Example initial x 0 a simple initialization initial begin x 1 i am initialization y f x Tl x 0 a value change 1 time unit later y E x end ptb dkb 2013 56 EE 3320 b Always Block Always blocks also begin at time 0 The only difference between an always block and an initial block is that when the always statement finishes execution it starts executing again Note that if there is no time or event control in the always block simulation time can never advance beyond time 0 Example always 10 clock clock 8 Behavioral modeling constructs a Conditional if else construct The if else statement controls the execution of other statements 1n a procedural block Syntax if condition statements if condition statements else statements it condition statements else if condition statements statements Example Simple if statement if enable q lt d One else statement if reset 1 bl g a DI else q lt d Nested if else if statements if reset 1 b0O counter l
19. want to simulate mux4x1 tb right click and choose Simulate Wee uoueweenwn o 0 THAT TN 000 CREER NR gt t E oom n ptb dkb 2013 File Edit View Compils Simulate Add Library Tools Layout Bookmarks Window Help ax Bl ge wi 6 X adr i LO AF GENES tt ELEME ColumnLayout 211Columns a ER Be a i Search v fai B5 e FFE I 3 i WI r A Library i aaa xl Sr rocesses es Active sisi d d xd ag Wave Default vine npe Poh jane AR E T A zi d work Lbrary C Users grd09 1020 mux4x t work i gbl Modue C Xiinx 13 3 ISE DS ISEjveriiog src EN mux4x1 Module C fUsers ardo9 t 3090 morti mtcr v Bl moxaxt tb Module C Users grd09 pl HAI foatfxib Lbrary MODEL_TECH Simulate Bi 7 2 ib empty Library MODEL TECH Smulate with Coverage Hef mtAvn Ubrary MODEL_TECH Edit AN miom Library MODEL TECH efr xdi mPa library MODEL_TECH acs di mboUPF Lbrary MODEL TECH Update f mium Library MODEL_TECH D H os Library MODEL_TECH sv_std Library MODEL TECH fil vital 2000 Library MODEL_TECH Delete f ieee Library MODEL TECH Copy if modeism J Lbrar MODEL_TECH A xi std Library MODEL TECH x std developerskit Library SMODEL_TECH Properties Fr ynops y Library MODEL TECH fill verilog Library MODEL_TECH v eio 32 The ModelSim window 50 EE 3320 E L In the Sim window on the left ri
20. 0N FT Cathodes Figure 31 Timing diagram for Multiplexed Seven Segment Displays ptb dkb 2013 33 EE 3320 8 Design and Simulation of Sequential Circuits using Verilog HDL The procedure to create Verilog design files for sequential circuits in Xilinx ISE is the same as that for combinational circuits The main difference between combinational and sequential designs is the presence of flip flops registered outputs or nodes in the Declaration section of a sequential design 8 1 Design of Sequential Circuits For large complex state machines it is easier to specify them as programs A sequential circuit can be described either as a procedural block or a state machine in Verilog 1 A D flip with asynchronous reset can be modeled as a Procedural block as follows data D FF with Asynch reset clock reset module dff async data clock reset q input data clock reset output q reg q logic begins here always posedge clock or reset if reset 1 b0 q lt 1 b0 else q lt data endmodule ptb dkb 2013 34 EE 3320 2 A D flip with synchronous reset can be modeled as a Procedural block as follows D q Flip flop with Synch Reset module dff sync data clock reset q input data clock reset output q reg q logic begins here always 8 posedge clock if reset 1 b0 q lt 1 b0 else q lt data endmodule 8 2 Simulation of sequential designs Exc
21. 1 0 sel output y reg y always a or b or c or d or sel case sel a b e 3 y d default y 1 b0 One bit binary value 0 endcase endmodule A sample test bench for the multiplexer module mux4xl tb output a b c d output 1 0 sel input y reg a b c d reg 1 0 sel initial begin a lt 1 bl b lt 1 b0 c lt 1 bl d lt 1 b0 Wait 100 ns for global reset to finish 100 Add stimulus here sel lt 2 b00 200 a lt 1 bl1 b lt 1 bl1 ptb dkb 2013 45 EE 3320 sel lt 2 b01 400 sel lt 2 b10 600 sel lt 2 b11 800 sel lt 2 b00 end mux4xl mux4x1 inst a b c d sel y endmodule As explained in the previous section create a new project named mux4X1 and add a new verilog source mux4X1 v with the code shown above To add a test bench select the project in the source list and right click to select Add New source When the New source wizard pops up select Verilog Text Fixture and choose an appropriate name for your test bench say mux4XI1 tb and click on Next New Source Wizard Select Source Type Select source type file name and its location BMM File a ChipScope Definition and Connection File Implementation Constraints File 4 IP CORE Generator amp Architecture Wizard MEM File t Schematic amp System Generator Project User Document mux4x1 tb Verilog Module Mh Verilog Test Fixture Hg VHDL Module C Users
22. 2 des Implementation Fae Simulation Behavioral Top Module top or Hierarchy Associated Module j or gate E A xc3sl100e 4cp132 or gate s or tb e B b i f I We FQ No Processes Running re En Processes or tb IL G ISim Simulator Behawioral Check Syntax ria Simulate Behavioral bhiodel r F r Rerun Al TU Stop Run With Current Data EN Process Properties a Start Figure 17 Launching the iSIM simulator from Project Navigator If the code is free of syntax errors this will launch the ISim simulator window as shown in figure Note In case you encounter an error when trying to launch the simulator right click on the design and ensure that manual compile order is not checked Also make sure that the test bench passes the syntax checks You will be able to observe the simulation waveforms as per the test stimulus in this window ptb dkb 2013 20 EE 3320 Ex Sim 0 76xd Default wcfg nnn aa 8H DAXO a d A SAMS Il 9 ReJaunch Instances and Processes 0 amp X Objects ensx je zY T SA Simulation Objects for or_tb 2 E egmI DEIEBm TEEME Instance and Process Name D 13 or tb oi Object Name Value P iJ gib gj Bz 1 Q 1B a 1 lb b 1 o 12 2r 4 I i m 4 m p 4 E E ina E Instanc Memory HE Source iM E m r s Default wcfg amp Console Figure 18 The iSIM simulator window behavorial simulation for
23. 6 i A Behavioral Check Syntax 47 x EA Simulate Behavioral Model 48 Initialize Inputs puse 49 a 0 m 50 b 0 51 c 0 52 d 0 53 sel 0 54 55 Wait 100 ns for global reset to finish 56 100 57 58 Add stimulus here 59 60 end 61 62 endmodule 63 64 ar Start amp Design i Fies Libraries 7 ISE Design Suite InfoCenter OJE Design Summary out of date OB mux4xt_tb v a Figure 28 Adding the verilog testbench to the project ptb dkb 2013 47 EE 3320 Double click on Behavioral Check Syntax in the process window to make sure there are mo syntax errors in your code A KA mark will appear if there are no errors as shown in Figure a ISE Project Navigator O 76xd C Users q 1 xxl 1 3 File Edit View Project Source Process Tools Window Layout Help La t xoa i 2 225 a8 B85T 2 rf 9 Design O xX 26 i View 9 Implementation Efl Simulation 27 Inputs g Behavioral x 28 reg a 29 reg b Ka Hierarchy o 30 reg C zd tj mux xi 31 reg d eet E E xc3s250e 4cp132 32 reg 1 0 sel g V muxbxl tb mux xl tb v E 33 mm uut mux4xl muxdxl v gt 34 Outputs A 35 wire y P 36 i 37 Instantiate the Unit Under Test UUT m 38 mux4xi uut p 39 a a px 40 b b 41 c c 42 d d 43 sel sel 44 y 45 E 46 47 initial begin 48 Initialize Inputs 49 a 0 50 b 0 51 c 0 La N
24. EXT to save the entries The Project Summary window Figure 4 will show you a summary of your project details In this example we have used the project name or gate Pay attention to the highlighted details in particular Mew Project Wizard n Project Summary Project Navigator will create a new project with the following specifications Project Project Name or gate Project Path C Users qrd091020 or gate Working Directory C Users gqrd091020 or gate Description Top Level Source Type HDL Device Device Family Device Package Speed Top Level Source Type HDL Synthesis Tool XST VHDL Verilog Simulator HModelsim 5E Verilog Preferred Language Yerilog Property Specification in Project File Store all values Manual Compile Order false VHDL Source Analysis Standard VHDL 9593 Message Filtering disabled Figure 4 New Project Wizard Project Summary snapshot from Xilinx ISE software Click on Finish All project files such as schematics netlists Verilog files VHDL files etc will be stored in a subdirectory with the project name A project can only have one top level HDL source file or schematic Modules can be added to the project to create a modular hierarchical design see Section 9 In order to open an existing project in Xilinx Tools select File gt Open Project to show the list of projects on the machine Choose the project you want and click OK ptb dkb 2013 7 EE
25. Xx 4 NET a LOC M4 j B top 8 d xc3s250e 4cp132 Sh E v top top v i or_th0 tb or gate tb_or_gate v S v d or_gate or gate or gate L i or gate ucf lj gl Hierarchy g 1 2 NET b LOC L3 SESNET 2 LOC M5 4 You can use this option to manually edit the ucf file Oo s a 15 T No Processes Running Processes or_gate ucf EB User Constraints E Edit Constraints Text ca 39 z9 28 w gt Start 9 Design Fies Libraries E Design Summary 3 or gate ucf a Figure 21 User Constraint File snapshot from Xilinx ISE software You may verify the generated UCF file by clicking on or gate ucf in the Design window in ISE If you would like to modify the UCF file manually to change the switches etc you may do so by clicking on the Edit Constraints Text option in the Process window Figure 15 6 2 Generating a Bit Stream file bit In order to program the FPGA you will need to generate a bit stream file of your design In the Xilinix ISE process window a Right click on Generate Programming File and select Process Properties ptb dkb 2013 24 EE 3320 J No Processes Runni Processes or_gate or gate Create Schematic Symbol View Command Line Log File View HDL Instantiation Template User Constraints Create Timing Constraints I O Pin Planning PlanAhead Pre Synthesis VO Pin Planning Plan4head Post Synthesi
26. d S3 begin out seq lt 1 b1 end default begin out seq 1 b0 end endcase end end End Of Block OUTPUT LOGIC endmodule End of Module Moore state machine Except for the additional clock signal simulation of finite state machines can be done using a test bench in the same way it was done for combinatorial circuits The following is a sample test bench for the Moore state machine The same can be used to test the Mealy state machine as well module sm tb reset clk in seq out seq output reset output clk output in_seq input out_seq reg clk reg reset reg 15 0 data reg in seq integer 1i ptb dkb 2013 38 EE 3320 The input data sequence is defined in the vector data Each clock one bit of data is sent to the state machine which will detect the sequence 101 in this data initial begin data 16 b0010100110101010 i 0 reset 1 b0 1200 reset 1 b1 60000 finish end Clock Generation initial begin clk 0 forever begin 600 clk clk end end Right shifting of data to generate the input sequence always posedge clk begin 50 in seq data gt gt i i itl end endmodule module top wire clk reset wire in_seq out seq moore fsm fsmO reset clk in seq out seq sm tb fsm tb reset clk in seq out seq endmodule wave default File Edit view Insert Format Tools Window d X BA Xe x Bl e A a BE Atop fsm
27. ept for the additional clock signal simulation of sequential designs can be done using test_bench in the same way it was done for combinatorial circuits The clock signal can be generated in the test bench using a simple initial block as follows module test bench clk output clk reg clk initial begin clk 0 forever begin 5 clk clk Time period of the clock is 10 time units end rest of the logic endmodule ptb dkb 2013 35 9 Design and Simulation of Finite State machines in Verilog Basically a Finite State Machine FSM consists of a combinational logic sequential logic and output logic Where combinational logic is used to decide the next state of the FSM sequential logic is used to store the current state of the FSM Types of State Machines There are many ways to code finite state machines but before we get into the coding styles it is important to understand the basics There are two types of state machines Mealy and Moore Sequential Logic Moore Model Sequential Logic Mealy Model in a Moore model outputs of a circuit are function of the amp n a Mealy model outputs of a circuit are a function of the present state only present state and the present inputs of the circuit Inputs Outputs Inputs Source EE3320 Digital Circuits course slides Depending on the need either type of state machine can be used Encoding Style Since the state machine needs to be represented as a digital
28. ght click on the test bench name and choose Add wave RA ModelSim PE Student Edition 10 2c File Edit View Compile Simulate Add Structure Tools Layout Bookmarks Window Help ERA 5 x a1 9 B mux4xi_tb mux4x1 tb Eee E sa uut mux4x1 SINITIALS47 mux4xi tb X vsim_capacity Add Wave To Add Dataflow Ctrl D Add to Copy Ctrl C Find Ctrl F Save Selected Expand Selected Collapse Selected Collapse All Code Coverage Test Analysis XML Import Hint Show Figure 33 Adding test bench signals to the simulator Click on Run or Run All to run the simulation Simulate gt Run gt Run all You may choose to run the simulation for a specified time by typing the run command in the ModelSim prompt ptb dkb 2013 5 EE 3320 o _ ET oe T e t z s t Layout Simulate v Columriayout AllColumns v E a M ModelSim PE Student Edition 102c a tht n C7 ANNE File Edit View Compile Simulate Add Structure Tools Layout Bookmarks Window Help E g id 6 SRO O ME 05 489 we f uw Hl oss5 EM TIS We L j 3e 9 Se Jas RAG 1 0 ENIBMI TIE k i 5 t hb wd gt CS tx d active es Ht gg Wave Dait rire Desunt Desgnunt ye rop Category st we ee ee ee mux4x IL mux4x1 tb Modu XJ Instance ecc amp mx 2 uut T ecc F 7 7 acc dil mx Dh z Ea p Run all Simulation Waveforms for mux4x1_tb Fi
29. gure 34 Running the simulation and observing waveforms in ModelSim ptb dkb 2013 52 EE 3320 Appendix A Verilog Hardware Modeling This is just an introductory level tutorial to the Verilog language The reader is encouraged to go through the following Verilog tutorials to understand the language better e http www asic world com verilog vbehave html e http www vol webnexus com requires free registration 1 Module A module is the basic building block in Verilog It is defined as follows module lt module name gt lt portlist gt module components endmodule The module name gt is the type of this module The lt portlist gt 1s the list of connections or ports which allows data to flow into and out of modules of this type Verilog models are made up of modules Modules in turn are made of different types of components These include e Parameters e Nets e Registers e Primitives and Instances e Continuous Assignments e Procedural Blocks e Task Function definitions 2 Ports Ports are Verilog structures that pass data between two or more modules Thus ports can be thought of as wires connecting modules The connections provided by ports can be either input output or bi directional inout inl in outl out hidi module Todi input ini output outi out NS inout bidi Port List endmodule ptb dkb 2013 53 EE 3320 Module instantiations also contain port lists This i
30. he test bench used to test the Moore State machine can be used to test the Mealy state machine as well ptb dkb 2013 4 EE 3320 The operation of the Mealy state machine is shown in the waveform below wave default File Edit View Insert Format Tools Window S Medal RK ee x mie EF E E E top fsm reset SH dic EE sto Ef top fsmO state on 001 1 oro od joo i00 foro yoo forgo Foor yoi0 rod jyo10 i00 yo0 E top fsmO next_state 001 On foro E e ford j100 foro oo yoi0 ford 100 jo foro yio0 oig 100 J001 foo top fsm in seq sto top fsmO in_seq_reg 0 M top fsm out seq 0 Now 500000 ps 326010 ps TE JN 4 0 ps to 245898 ps Finite State machine design is a very efficient and elegant way of designing logic and is widely used in the industry It is to be noted that the above examples do not enumerate all the possible methods and tricks of finite state machine design Also the implementation details how the Verilog FSM code i1s translated to combinatorial and sequential logic are not discussed here The following factors are taken into account while designing a state machine e Area v s Delay of the state machine encoding logic and the combinatorial logic e Timing of the entire state machine design If the combinatorial logic leading to a particular state change takes lot of delay in the hardware logic circuit it could be split into mult
31. iple states Multiple state additions might lead to excessive latency in the finite state machine ptb dkb 2013 42 EE 3320 10 Hierarchical Circuit Design Using Modules It is always a good practice to keep a design modular and hierarchical This is important for designs of moderate to high complexity Refer to section on hierarchies and Instantiation in the Verilog tutorial in Appendix A Often you will use a circuit module over and over again Instead of creating these modules every time you need them it would be more efficient to make a cell or module out of them You can then use this module every time to need it by instantiating the module in your circuit Verilog supports hierarchical design by creating instances of another modules that can be used in a design In the example depicted in Figure 24 a 4 bit equivalence circuit is designed using 1 bit equivalence circuit modules a3 63 a2 bz ef bl ant bp eq 4 Figure 24 Hierarchical circuit design example 4 bit equivalence circuit e Module Definition A module functional block definition is specified in a file separate from the top level design file using the module module equiv p q r input p input q output r assign r p q equivalence function is xnor function endmodule ptb dkb 2013 43 EE 3320 e Module Usage A design using a module includes a declaration of module interface and instantiation of each module in the Declaration section I
32. ment Design Generate Programming File Configure Target Device Analyze Design Using ChipScope input a input b output z e ST ty ID IOWNM endmodule Start 8 Design l Files tibraries B Console Started Launching ISE Text Editor to edit or gate v Launching Design Summary Report Viewer 4 8 console Errors J Warnings d Find in Files Results Ln29Col1 Verilog Figure 9 Verilog Source code editor window in the Project Navigator from Xilinx ISE software e Adding Logic in the generated Verilog Source code template A brief Verilog Tutorial is available in Appendix A For the language syntax and for construction of logic equations please refer to Appendix A The Verilog source code template generated shows the module name the list of ports and also the declarations input output for each port Combinational logic code can be added to the verilog code after the declarations and before the endmodule line For example an output z in an OR gate with inputs a and b can be described as assign z alb Remember that the variable names are case sensitive e Other constructs for modeling a logic function A given logic function can be modeled in many ways in verilog Verilog offers numerous constructs to efficiently model designs Here is an example in which a 4x1 multiplexer is implemented using a case statement ptb dkb 2013 12 EE 3320 module mux4x1
33. nal Designs 5 1 Creating a Testbench To check the functionality of a design we have to apply test vectors and simulate the circuit In order to apply test vectors a testbench file is written Essentially it will supply all the inputs to the module designed and can check the outputs of the module Example For the 2 input OR Gate the test bench is created as follows 1 Right click on the design or gate and select New Source mmary ES File Edit Wiew Project Source Process Tools Window Layout Help i D3 E ka ERI 36 H3 xw e ji A 25 eer a ZX Sa m c Design rm x i View X J amp 2 Implementation PA Simulation Top Module top_or i Hierarchy Associated Module am or gate ERE DES xc3s100e 4cp132 i all or gate p i d m Pi Mew Source i Add Source 2e REl Add Copy of Source T1 Open dE Remowe w Manual Compile Order Mowe to First Mowe Up Mowe Down Mowe to Last Check All Uncheck All CQ No Processes Running j Implement Top Module Processes o roqate FilePath Dis p lay Design Surmrn E Design Utilitie User Constrair Create Tir IYO Pin Ple LVO Pin Ple assal 1 al H eea E Ea View RTL 4 Figure 13 Adding a test bench to your design stepl Floorplan G9 synthesize X a Source Properties Fe ee TI EL i el Expand All Collapse All dM Find Ctrl F Design Properties ae MIT LH L al aiaa m 2 Fr
34. nitializing Scan Chain Board information loaded Found device ID f5045093 Found device ID 11c1a093 Initialization Complete Device 1 XC35250E Device 2 XCFO2S Set Config file for XC35250E C Wsers grd091020 top or_gate bit Preparing to program XC35250E Programming Verifying programming of device Programming Successful Figure 27 Programming the FPGA using Adept Now you can test the functional behavior of your design on the FPGA using the switches and LEDS on the BASYS board Ensure that the Programming Successful message appears in the message window If you face problems please ensure gt The USB cable is connected to the board The board is powered ON Check the switch settings as shown in Figure 19 The FPGA device on the board matches the one that you specified in your design properties Eg XC3S250E or XC3S100E Note that if there is a mismatch you will usually encounter an error stating Unable to associate file with device due to IDCODE conflict If this occurs re check your design properties ptb dkb 2013 28 EE 3320 7 Testing a Digital Logic Circuit using the Digilent BASYS board Testing a downloaded design requires connecting the inputs of the design to switches or ports and the outputs of the design to LEDs or 7 segment displays In case of sequential circuits the clock input s must also be connected to clock sources These inputs and outputs can be connec
35. nstantiation of module equiv in the 4 bit equivalence circuit shown in Figure 21 can be done as follows module equiv4bit a3 b3 a2 b2 al b1 a0 b0 eq4 input a3 b3 a2 b2 a1 b1 a0 b0 output eq4 equiv equiv equiv equiv eq0 a0 b0 r0 eqi1 al bl r1 eq2 a2 b2 r2 eq3 a3 b3 r3 assign eq4 r0 amp rl amp r2 amp r3 endmodule NOTE For creation of the module we can either use the design wizard provided by the Xilinx Or create our own ptb dkb 2013 AA EE 3320 11 Post Synthesis Timing Simulation The Xilinx ISE contains a simulator called iSIM which can be used to verify the behavior of your designs You may also use the Modelsim simulator which can also be invoked directly from Xilinx in order to perform functional and timing simulations It has an Integrated Development environment that can be used to develop and debug Verilog synthesizable and behavioral logic Section 5 2 explains usage of the Modelsim simulator from Xilinx ISE to verify the functionality of a given digital logic circuit using a test bench This chapter deals with performing post synthesis timing simulations using the Modelsim simulator We will look at simulation and timing synthesis using an example of a 4X1 multiplexer In order to perform the simulation we wil need two files a design file and a test bench as shown below The multiplexer design file mux4x1 v module mux4x1 a b c d sel y input a b c d input
36. o Processes Running i do di P Processes muxbd tb 53 sel 0 x4 2 y ISim Simulator 54 m E Y Behavioral Check Syntax 55 HH Wait 100 ns for global reset to finish 2d bimulate Behavioral Model 100 m 58 Add stimulus here 59 sel lt 2 b00 60 100 61 a lt 1 bi 62 b lt 1 bi E b 63 sel 2504 Test stimuli added here 64 100 Syntax check successful 65 sel lt 2 b10 66 100 67 sel lt 2 b11 68 100 69 70 end ML 72 endmodule 72 4 n Start 8 Design l Fies Libraries Zz ISE Design Suite InfoCenter E Design Summary out of date 2 mux4x1_tb v a Le 5 Figure 29 Checking syntax Now you are ready to simulate your design Behavioral simulation using iSIM In order to run the iSIM simulator double click on the Simulate Behavioral Model in the process window this will launch the iSIM window as shown in Figure 29 The output y has been highlighted in red for clarity ptb dkb 2013 48 EE 3320 Ez ISim O 76xd Default wcfg s File Edit View Simulation Window Layout Help Da Ei a ix Instances and Processes D amp X Objects f E El zn IE Gl Simulation Objects for mux4x1 tb alsa go G Instance and Process Name D J mux4xi tb m Object Name Value ij gibi gl ld y lb d 1 T lb c 0 D 0 Ub sel L 0 1 o Design ports inputs outputs X1 1 000 000 ns m gt 4 gt 4 gt
37. ocess Tools Window Layout Help DIPaeRILEXSExloe i s AaRr a Wi Rams Swlir sc 9 Design 908x 4 module or_gate a b Z jj Vew Implementation M Simulation 5 input a b 3 output z s Hierarchy M as Fel a or gate e xc3s50 5pq208 dd or gate or gate v always a or b begin case a b 2 b00 2 b01 2 b10 2 bils 1 b0 1 bi 1 b1 1 b1 Design Summary Reports endcase E Design Utilities end User Constraints endmodule 8 TO Synthesize XST View RTL Schematic View Technology Schematic C Check Syntax C Generate Post Synthesis Simulation Model E CAA Implement Design e 9 Translate C Generate Post Translate Simulation Model 8 Qu Map Generate Post Map Static Timing Analyze Post Map Static Timing Manually Place amp Route FPGA Editor C Generate Post Map Simulation Model H 4O Place amp Route Generate Programming File Configure Target Device Analyze Design Using ChipScope Generating Report Number of warnings 0 Total time 0 secs Process Generate Post Place amp Route Static Timing completed successfully K m El Errors Warnings i Find in Files Results Figure 12 Implementing the Design snapshot from Xilinx ISE software If there are no errors then the tool shows that the design has been synthesized successfully as in Figure 12 ptb dkb 2013 15 EE 3320 5 Functional Simulation of Combinatio
38. om the new source wizard pop up select Verilog Test Fixture and enter a name for the test bench eg or_tb in the File name field as shown in the Figure and click Next ptb dkb 2013 16 EE 3320 Select Source Type Select source type file name and its location fn BMM File a ChipScope Definition and Connection File Implementation Constraints File 4j IP CORE Generator amp Architecture Wizard amp MEM File Schematic File name C Wsers ord091020 or_gate VHDL Library VHDL Package VHDL Test Bench Figure 14 Adding a test bench to your design step 2 3 The New source wizard will show the design that the test bench is associated with this should be the design that you wish to simulate in this case or gate Click Next and then Finish ptb dkb 2013 17 EE 3320 Associate Source Select a source with which to associate the new source Figure 15 Adding a test bench to your design step 3 4 The ISE project navigator will generate some boilerplate test bench code for you you may either modify this code or replace it with the following code Refer to the Figure module or thbh a b Z OUL PUL a Output D input z reg a b declaration that a and b are registers Instantiate the Unit Under Test UUT Or Gare nut 4 initial begin ptb dkb 2013 18 EE 3320 test stimuli a lt bU p lt 1750 100 a lt 1 pU Db lt 17 pls 100 a lt 1 7 bl Ob lt
39. orplan Area IO Logic Plan Ahead option in the process window This will launch the Xilinx Plan Ahead tool ptb dkb 2013 22 EE 3320 inde ayout View Help File Edit Toots V O Q Kg Eroon JL I X ign target xc3s250ecp132 4 Setting switches SWO SW1 as inputs and LEDO as output Figure 20 Assigning pins to inputs outputs in Xilinx PlanAhead In the PlanAhead window shown in Figure 14 click on the nets that are assigned to the design in this case a b z and in the I O ports window assign the pin number aliases as specified on the Digilent board Refer to I O pin mapping information for the Digilent board o For the OR_GATE example the user constraints may be specified as follows We can use switches SWO and SWI on the Digilent board as inputs a and b and LEDO as the output z Note that Pin P11 and L3 are FPGA pins connected to SWO and SW1 on the Digilent Board Pin M5 of the FPGA is connected to LEDO on the Digilent Board NET a noc Input a connects to SWO pin P11 on FPGA Input b connects to SW1 pin L3 on the FPGA NET b LOC NET z LOC Output z connects to LEDO pin M5 on the FPGA ptb dkb 2013 23 EE 3320 ar SE Project Navigator 0 76 C Users grd091020toptopxise forgatese E O E File Edit View Project Source Process Tools Window Layout Help 18 H3 db 4 x a Design View 9 Implementation M Simulation PF TPA sTSiMiIfj 0s9 Od
40. s Floorplan amp rea IO Logic PlanAhead 4A HIV LLL H 2E Translate a lah Map H Fa Place amp Route Generate Programming File Configure Target Device EM Run ReRun Am Rerun All Stop View Text Report Eorce Process Up to Date No Search Results Implement Top Module Design Goals amp Strategies E Process Properties Figure 22 Setting the Process Properties in Xilinx ISE b In Startup options select JTAG Clock and click Apply and then OK Em Process Properties Startup Options Switch Mame Property Mame eae pues gStartUpClk FPGA Start Up Clock Configuration Options Startup Options Readback Options g DONE cycle Done Output Events Default 4 g GTS cycle Enable Outputs Output Events Default 5 g GWE cycle Release Write Enable Output Events Default 6 gLCK cycle Wart for DLL Lock Output Events Default MoWait g DonePipe Enable Internal Done Pipe g DriveDone Drive Done Pin High E Property display level Standard Display switch names Figure 23 Setting CLK option on Xilinx ISE ptb dkb 2013 25 EE 3320 c Double click on Generate Programming file or right click and choose Run P C No Processes Running Design Summary Reports Design Utilities User Constraints Vet Create Timing Constraints de VO Pin Planning PlanAhead Pre Synthesis 2 VO Pin Planning PlanAhead Post S
41. s Window Layout Help O e E p x E H Implement Top Module e a RA TD Je x zZ PF Design p Run 1 module or gate a b z jf View eal Implementation BA Sir ReRun 2 input a b 3 output z7 d Hierarchy SIME il he c 4 reg z z ve or gate di Stop 5 amp EB xc3s50 5pq208 Run With Current Data 6 always a or b SIT ee or gate or gate v Force Process Up to Date 7 begin B8 case tfa bl 71 Process Properties E 10 2 b00 z 1 bo 11 2 b 01 z 1 bl M 12 2 b10 z l bi RE zZ b11 z 1 bl J No Processes Running 14 Sr oa 15 i Onee or gate 16 endcase 2 Mesign Summary Reports 17 end E Design ti 8 endmodule e Ic User Constraint 1 OD Synthesize XST Ee pa Implement Design uE Translate a Generate Post Translate Simulation head D Qa Map NM Generate Post Map Static Timing Analyze Post Map Static Timing Manually Place amp Route FPGA Editor Generate Post Map Simulation Model no Place amp Route C2 Generate Programming File Ge ae Configure Target Device eu Analyze Design Using ChipScope Clicking this 1s equivalent to selecting the Implement Top Module option Active process list 4 m i IEEE TE 3840 x 1200px Figure 10 Implement Top Module option in Xilinx ISE ptb dkb 2013 14 EE 3320 xd CAL grd091020 or gate or_ File Edit View Project Source Pr
42. s the means of connecting signals in the parent module with signals in the child module module top wire sourcel source Port List wire sinkl sink d wire hus foo fE sourcel zsource2 sinkl sink hus endmodule 3 Nets Nets are the things that connect model components together They are usually thought of as wires in a circuit Nets are declared in statements like this net type range delay3 list of net identifiers Example wire wl w2 tri 31 0 buss2 wire wire number 5 wire number 2 amp wire number 3 4 Registers Registers are storage elements Values are stored in registers in procedural assignment statements Registers can be used as the source for a primitive or module instance 1 e registers can be connected to input ports but they cannot be driven in the same way a net can Registers are declared in statements like this reg l ngel list of register adentariers 7 Example reg l 2 reg 31 0 bus32 ptb dkb 2013 54 EE 3320 5 Operators in Verilog Logical arithmetic and relational operators available in Verilog are described in Table 1 conditional legal for real associates right to left others associate left to right logical or A smaller operand is zero filled from its msb O fill legal for real amp amp logical and O fill legal for real bitwise or bitwise nor O fill bitwise xor bitwise xnor equivalence O fill amp bitwise and
43. t 4 o0000 else 1f enable L Dl amp amp up en 1 bl counter lt counter IL bls else af enable I bl amp 4 down enm I blI counter lt counter 1 b0 else counter lt counter Redundant code b Case statement ptb dkb 2013 57 EE 3320 The case statement compares an expression to a series of cases and executes the statement or statement group associated with the first matching case Case statement supports single or multiple statements Multiple statements can be grouped using begin and end keywords Syntax case expression lt casel gt statement caseZ2 t statement default statement endcase Example module mux a b c d sel y l1nput a Dy dj Input 1 0 sel QULDUL y reg y always a or b or c or d or sel case sel 0 y a 1 y b 2 y Cc 3 y d default Jdisplay Error in SEL endcase endmodule 9 Module instantiations and hierarchies Verilog allows you to represent the hierarchy of a design A more common way of depicting hierarchical relationships 1s We say that a parent instantiates a child module That is it creates an instance of it to be a submodel of the parent In this example system instantiates comp 1 comp 2 ptb dkb 2013 58 EE 3320 comp 2 instantiates sub 3 Modules in a hierarchy have both a type and a name Module types are defined in Verilog There can be many module instances of the same type of
44. te InfoCenter mr Console DINFO MDLCompiler 1835 Analyzing Verilog file Cilxilinx bin or gate or gate v into library work INFO ProjectMgmt Parsing design hierarchy completed successfully Launching Design Summary Report Viewer i Console Q tros Warnings Find in Fies Results Figure 1 Xilinx ISE Project Navigator window snapshot from Xilinx ISE software ptb dkb 2013 3 EE 3320 3 1 Opening a project Select File gt New Project to create a new project This will launch the New Project Wizard Figure 2 on the desktop Fill up the necessary entries as follows Create New Project Specify project location and type Enter a name locations and comment for the project Name Booo f Location Working Directory C Wsers Description Select the type of toptevel source for the project Toptevel source type Name Write the name of your new project E g or_gate Location The directory where you want to store the new project Working Directory The directory where all your project related files will be saved Description Optional A brief description of your project Leave the top level module type as HDL Example If the project name were or gate enter or gate as the project name and then click Next ptb dkb 2013 4 EE 3320 Clicking on NEXT should bring up the Project Settings window Project Settings Ensure that these values are correct Specify device and
45. ted to appropriately on the Digital Lab workbench The Digilent BASYS board used in the Digital Circuits lab has the following features which can be used to test the digital logic in the design 1 8 Switches which can be used to drive up to 8 inputs 2 4 Buttons which can be used as reset signals or input switches 3 8 LEDs Which can be used to display up to 8 design outputs 4 4 Seven segment displays which can be used to display four digits of information on the board 5 Mini USB interface 6 Power on switch XILINX SPAATAN Figure 28 The Digilent BASYS board with Spartan 3 FPGA ptb dkb 2013 29 EE 3320 32 2 o d B a PS 2 VGA Port Pmod Connectors I O Devices Port Figure 29 Digilent BASYS Board Architecture www digilentinc com In order to use the respective input output device on the board the pin number of the device must be connected properly to the design s input output On the Digilent board the pin number of these inputs outputs is as follows ptb dkb 2013 30 EE 3320 Table 1 Pin mapping on the Digilent BASYS board 7 1 Observing outputs using the on board LEDs and Seven Segment Displays The Digilent board has four on board 7 segment displays see Figure 22 that are connected to the corresponding on board Spartan 3E FPGA chip This display can be used to observe the outputs of your design without using any additional wires if the design conforms
46. termine the next state for each state in the state machine using the input sequence given to it next state is combinatorial in nature always state or in seq reg begin FSM COMBO next state 3 b000 case state SO if in seq reg 1 b1 begin next state S1 end else begin next state S0 end ptb dkb 2013 40 EE 3320 S1 if in seq reg 1 b0 begin next state S2 end else begin next state S1 end S2 if in seq reg 1 bl begin next state S1 end else begin next state S0 end default next state S0 endcase end always posedge clk begin FSM SEQ if reset 1 b0 begin state lt CK2Q SO end else begin state lt CK2Q next state end end Based on the combinatorial next state signal and the input sequence determine the output out seq of the finite state machine always 8 state or in seq reg or reset begin OUTPUT LOGIC if reset 1 b0 begin out seq 1 b0 end else begin case state SO begin out seq 1 b0 end S1 begin out seq 1 b0 end S2 begin if in seq reg 1 bl out seq lt 1 b1 else out seq 1 b0 end default begin out seq 1 b0 end endcase end end End Of Block OUTPUT LOGIC endmodule End of Module Mealy state machine Except for the additional clock signal simulation of finite state machines can be done using a test bench in the same way it was done for combinatorial circuits T
47. ther a net or register to another They are usually thought of as representing combinational logic In general any logic functionality which can be implemented by means of a continuous assignment can also be implemented using primitive instances ptb dkb 2013 55 EE 3320 A continuous assignment looks like this assign delay3 list of net assignments Examples assign wl w2 amp w3 assign 1 mynet enable mynet 1s assigned the value after time unit 7 Procedural Blocks Procedural blocks are the part of the language which represents sequential behavior A module can have as many procedural blocks as necessary These blocks are sequences of executable statements The statements in each block are executed sequentially but the blocks themselves are concurrent and asynchronous to other blocks There are two types of procedural blocks initial blocks and always blocks initial lt statement gt always lt statement gt There may be many initial and always blocks in a module Since there may be many modules in a model there may be many initial and always blocks in the entire model All initial and always blocks contain a single statement which may be a compound statement e g initial begin statementl statement2 end a Initial Block All initial blocks begin at time O and execute the initial statement Because the statement may be a compound statement this may entail executing lots of statements There may be
48. to the pin assignments for the on board 7 segment display Figure 22 shows the 7 segment display with the conventional labeling of individual segments ptb dkb 2013 3 EE 3320 Common anode il ff v I l I Z I1 I1 LI dE d Pd CA CB CC CD CE CF CG DP Four digit Seven i DP Segment Display yay Individual cathodes Fieure 30 7 segment display source Basvs user s manual The Digilent board contains a 4 digit common anode seven segment LED display The display is multiplexed so only seven cathode signals CA CB CC CD CE CF CG exist to drive all 28 segments in the display Four digit enable signals ANO ANI AN2 AN3 drive the common anodes as shown in Figure 22 and these signals determine which digit the cathode signals illuminate Table 2 Seven segment display LED mapping on the Digilent board ptb dkb 2013 32 EE 3320 This connection scheme creates a multiplexed display where driving the anode signals and corresponding cathode patterns of each digit in a repeating continuous succession can create the appearance of a 4 digit display Each of the four digits will appear bright and continuously illuminated if the digit enable signals are driven low once every 1 to l6ms for a refresh frequency of 1KHz to 60Hz The Seven segment display timing to drive all the four displays is shown below Refresh period 1ms to 16ms h n Digit period Refresh 4 ANO ANIC SCO A7 N04 1 ANS
49. unctional simulation and d testing and verification Digital designs can be entered in various ways using the above CAD tools using a schematic entry tool using a hardware description language HDL Verilog or VHDL or a combination of both In this lab we will only use the design flow that involves the use of Verilog HDL The CAD tools enable you to design combinational and sequential circuits starting with Verilog HDL design specifications The steps of this design procedure are listed below 1 Create Verilog design input file s using template driven editor Compile and implement the Verilog design file s 3 Create the test vectors and simulate the design functional simulation without using a PLD FPGA or CPLD 4 Assign input output pins to implement the design on a target device 5 Download bitstream to an FPGA or CPLD device 6 Test design on FPGA CPLD device A Verilog input file in the Xilinx software environment consists of the following segments Header module name list of input and output ports Declarations input and output ports registers and wires Logic Descriptions equations state machines and logic functions End endmodule All your designs for this lab must be specified in the above Verilog input format Note that the state diagram segment does not exist for combinational logic designs Software used We will use Xilinix Tools v13 3 and Digilent Adept v2 2 0 in this lab Hardware We
50. will use a BASYS2 kit from Digilent Inc with a Spartan FPGA from Xilinx to implement the designs 2 Programmable Logic Device FPGA In this lab digital designs will be implemented in the Pegasus board which has a Xilinx Spartan 3E FPGA XC3S250E This FPGA part belongs to the Spartan family of FPGAs These devices come in a variety of packages We will be using devices that are packaged in 208 pin package with the following part number XC2S50 PQ208 This FPGA is a device with about 250K gates Detailed information on this device 1s available at the Xilinx website ptb dkb 2013 2 EE 3320 3 Creating a New Project Xilinx Tools can be started by clicking on the Project Navigator Icon on the Windows desktop This should open up the Project Navigator window on your screen This window shows see Figure 1 the last accessed project a ISE Project Navigator O 76xd CAUsersigrd091020 or gatelor gate xise Design Summary E File Edt View Project Source Process Tools Window Layout Help i f DAHA S XOSxloa 222 5a s7 e rf fi Desgn nax Overmew jj Vew S imolenentaton M Smuaton Ui x sa or gate xc3150 5p4208 Vids or gate or_getev i amp i5b5booog Ba gmj t 3 g 8 Last accessed project TC No single design module is selected o YW Design Utilities Date Generated 07 24 2013 1459 30 Process i Summary window window F Sut Deep O Fes rares gt ISE Design Su
51. ynthesis I Floorplan Area TO Logic PlanAhead A Synthesize AST ls U Implement Design J Generate Programming File Configure Target Device Generate Target PROM ACE File Manage Configuration Project IMPACT u Analyze Design Using ChipScope Figure 24 Generating a bistream file for your design This will generate a bitstream file that you can use to program the FPGA 6 2 Programming the Digilent Board using Adept To program the FPGA on the Digilent board do the following e Connect the Digilent board to the USB cable make sure the switch is set to ON position e Launch the Digilent Adept tool Start gt All Programs gt Digilent gt Adept ptb dkb 2013 26 EE 3320 USB Connector Battery Connector Power Switch comes Product Basys2 250 Program PROM wDFED2S Program This shows the FPGA version automatically this should match the version on your board Board information loaded Found device ID f5045093 Found device ID 11c1a093 Initialization Complete Device 1 XC35250E Device 2 XCF025 ptb dkb 2013 Figure 26 The Digilent Adept window 2f EE 3320 e Click on Browse and select the bitfile that you generated in step 6 1 or_gate bit and click on Program iP Digilent Adept i TR BASYS 2 Connect Product Basys2 250 Config Test Register I O File I O O Ex dios 4035 250E co Ma ALFIUZS Loading board information I
Download Pdf Manuals
Related Search