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1. 21 POEZ ERE 22 808 22 I S A ana ee ee er eee 23 hac 24 WO CP TER 26 ics 26 L Sha E E E E unn l a n 29 Pouro IND RII MUSEI SEED I a UMS 30 papua sas naa asa tes Es 37 PP 38 Eroute 20195 5922 2 900 629 0 mipd ao ma eds 39 PICUIC 2 E 40 UM Er PCT 4 SU 2 42 RE 43 Ioue 220 Nie 44 360te 2 2 45 uude ee eee er 46 IOUT MY 46 5 RET EO EP 50 IO EQ EE AD IM ONU 53 E obe 55 CT N 57 s err asi 60 goutte 5 61 ACH et 64 Silo d e
2. 65 S xo 65 ui dou tars uic 66 ie 67 F Pili eee 68 Figures e eee ee cd daa 69 F PSI l Oceanside E do qud aka 70 Sui d 70 76 PO UC S D 83 uuu REED 94 Pu amada 85 UE Siu 86 Pm 87 QUES Wise eo 88 Papure D abes tust ner oe ee 88 S re S O kawsu uhay 89 i C saa 93 Sul 3 IR S E MES SQ 95 runt O uuaasqupasspusanaanupasscasnasqupaasssupsannaunapanarquanasqubasssupanphuupsaquwqoasmuyo 102 104 A 112 FO BHI LO aaa MCI 113
3. 105 0 den Aare 106 TIOR 109 MMS 6 1 115 dr e 116 bh TULIT 130 RCTKE A A VOM 131 132 aha 139 li 140 bl OO LA 142 121 lp uu suu u 157 PADS 167 ETE 170 Tobi kr ia 172 bane 224 Fable PPP ROC TP POPE 231 VII SECTION 1 AIMS AND TOOLS 1 INTRODUCTION j j jd j jl lj ji j iii di 1 1 Objective of the present work In the last few years of this century the technology has spelled the society with miracles The fast growth of electronics has opened a variety of advance topics to be learned by the students The training to the newer topic in the electronics needs a structured easy to understand methodology The in flow of the newer and n
4. OUT 20H IN 21H ANI 08H JNZ RTRAN INX H DCR B JNZ EMPTY RST3 8020 8021 8023 8025 2 802A 802B 902 802 7E D3 20 DB 21 E6 08 CA 20 80 23 05 C2 19 80 DF Here ANI O1H checks TxRDY condition ANI 08H checks parity error JZ RTRAN makes a loop to transmit same byte if parity error has occurred Register B 15 a counter Location 8100H to 8109H store data to be transmitted SLAVE PROGRAM Mnemonics MVI A 00H OUT 21H OUT 21H OUT 21H MVI A 40H OUT 21H MVI A FE OUT 21H A 35H OUT 21H MVI B 09H LXI H 8200H IN 21H ANI 02H JZ EMPTY IN 20H MOV INX H Memory address 77 8000 8002 8004 8006 8008 800A 900 900 9010 9012 8014 8016 8019 801B 801D 8020 8022 8023 Machine codes 3E 00 D3 21 D3 21 D3 21 3E 40 D3 21 3E FE D3 21 3E 35 D3 21 06 09 21 00 82 DB 21 E6 02 CA 19 80 DB 20 77 23 DCR B 8024 05 JNZ EMPTY 9025 2 19 80 RST 3 9028 DF The program is first executed in the slave kit and then in the master kit The data of the slave kit is then checked It is observed that the location 8200H to 8209H of the slave kit contains the same data of master kit stored at 8100H to 8109H This is One Way communication from the master to the slave kit e PROGRAM FOR TWO WAY COMMUNICATION Both the kits are loaded with master and slave program Master kit 1s the
5. MM eo a eee te 114 Ei rm 115 1 99 95 117 Gulio di epe 127 an gt et NET 127 UU o aes 128 39 1 EE ETE 129 5 131 ol ER ERI AMD EAM EIN ELI ELLE 132 P 133 134 141 T 143 L oi S Per rS 144 Piste US osere PCT 156 Sui LOZ ae sss tah ae 162 Sir 163 Faeute 160 l sur J A osa 181 Powe PN REDE 189 un RT EIE 190 EQ EE ADMIN ON S aS 192 Figure suaiun Aero 193 SP iugi EORR TENES 194 199 agro PLAT RC TC TEE 201 Pie We 0 E S ACH 206 suro l 208 Peur T 209 Pear T
6. 80H EN Set cursor to 80h 148 NOP NOP CLR LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL NOP NOP NOP NOP NOP NOP NOP CLR MOV SETB NOP NOP NOP NOP EN WAIT LCD A V WRITE TEXT A T WRITE TEXT A C WRITE TEXT A WRITE TEXT A WRITE TEXT A C WRITE TEXT A TH WRITE TEXT A WRITE TEXT RS 0COH EN 149 Display data Set cursor to INIT LCD NOP NOP NOP CLR LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL LCALL LCALL CLR MOV SETB NOP NOP NOP NOP NOP NOP NOP EN WAIT LCD A N WRITE TEXT A C WRITE TEXT A WRITE_TEXT A WRITE TEXT A WRITE TEXT A O WRITE TEXT A TR WRITE TEXT A WRITE TEXT DELI DELI RS 38H EN 150 Display DATA LCD ready subroutine RS 0 Function set for lline 5 8 HI to LO pulse CLEAR LCD CLR LCALL CLR MOV SETB NOP NOP NOP NOP NOP NOP NOP CLR LCALL CLR MOV SETB NOP NOP NOP NOP NOP NOP NOP CLR LCALL RET CLR MOV SETB NOP NOP NOP EN WAIT LCD RS EN EN WAIT LCD RS 06H EN EN WAIT LCD RS 01H EN 151 Check for data fetch RS 0 Display on cursor on cmd HI to LO pulse Check for data fetch
7. eeecococe eoooeoo OOOO0 eoooooe 0000000 0000000 FIGURE 8 7 STEP BY STEP DISPLAY PATTERN THE MODULE After the completion of last step data 7fh 15 given to the port twelve more times selecting each time the corresponding column so that the display will be cleared and again loop back to step In this way moving message 5x7 HNP 1s displayed 133 o SOFTWARE FLOWCHART Figure 8 8 shows the flowchart of the software used for moving message display INITIALZE THE DPTR TO 700H amp CLEAR DISPLAY LOAD COUNTS IN R6 R7 INITIALIZE R3 FOR AND FOR PORT2 amp 3 LOAD THE DATA FROM RAM amp RI INTO P2 ROTATE RI FOR NXT COLUMN SELECTION AND INC R3 FOR NXT DATA PROVIDE DELAY FOR PROPER SWITCHING BETWEEN EACH COLUMN YES INCR DPTR FROM 701H DO IT AGAIN TO 72BH amp P2 00H IN LOOP FIGURE 8 SOFTWARE FLOW CHART 134 MOVING MESSAGE DISPLAY SOFTWARE The software 1s responsible to maintain t
8. 209 Figure 2 RN 210 Exeutre d2 210 Figures Feur 2 492259225534 22992080044 E daa 216 sui ke oe rr ee eres ween tre asap 217 ILLNM 218 Lora Turo DS Er RSS 220 Foure PAN PETER 22 Four AN Lo MEE 221 ii Ada dai 222 F u nao a 223 prune 224 i 2 ET 225 230 S re 231 E1986 12 20A quA 232 2608 utet dies 232 VI Tables L J oaa TT 16 Ju JL 20 Tabe MTTRRUTER 27 L E Lc E 47 LEM d ML 52 Dl 3 RERUM IEEE 54 BU RUN 73 21 o OS EP 100 100 bL uyu at feta ihn yet tente d 103 TEO I I M 104 Table ADM E EID 105 4121
9. Equate to DATAI AJMP MAIN ORG 130H Start program from 130h MAIN MOV SP 50H Move stack pointer to 50h LCALL INIT LCD Call initialization codes LCALL CLEAR LCD Call clear LCD codes CLR RS Set cursor to 00h of LCD MOV 80H Means 80h 00h 80h SETB EN HI to LO pulse NOP NOP NOP NOP NOP 146 NOP NOP CLR LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL NOP NOP NOP NOP NOP NOP NOP CLR MOV SETB NOP NOP NOP NOP EN WAIT LCD A D WRITE_TEXT A r WRITE_TEXT A WRITE_TEXT A WRITE TEXT A WRITE TEXT A WRITE TEXT A WRITE TEXT A 7 WRITE TEXT RS 0COH EN 147 Give time to LCD for data start giving data to LCD to be displayed from 80h Writes data to LCD Cursor position at 87h move cursor to i e 80h 40h 0COh NOP NOP NOP CLR LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL LCALL LCALL LCALL LCALL LCALL CLR MOV SETB NOP NOP NOP NOP NOP EN WAIT LCD start giving data to Display WRITE TEXT A 5 WRITE TEXT A H WRITE_TEXT A T WRITE_TEXT A P WRITE_TEXT A U WRITE_TEXT A R WRITE_TEXT A WRITE_TEXT DELI Stay here for a while DELI DELI RET_HOME Again back to 80h CLEAR LCD Clear LCD cursor on Right RS
10. LL LLLI KEBBE gt Vcc Supply Voltage V Figure 8 SN75189A NOISE REJECTION 5 TA 259 See Note A 10 40 100 400 1000 ty Pulse Duration ns 4000 10000 NOTE A Maximum amplitude of a positive going pulse that starting from O V will not cause a change in the output level Figure 10 T Data for free air temperatures below 0 C and above 70 C are applicable to SN55189 and SN55189A circuits only 4 TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 Ij Input Current mA MC1489 MC1489A SN55189 SN55189A SN75189 SN75189A QUADRUPLE LINE RECEIVERS SLLS095D SEPTEMBER 1973 REVISED OCTOBER 1998 TYPICAL CHARACTERISTICS INPUT CURRENT vs INPUT VOLTAGE Vcc 5V 8 Control Open 25 20 15 10 5 0 5 10 15 20 25 Vi Input Voltage V Figure 11 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and lim
11. Operational description Operating 8251A Universal Synchronous Asynchronous Receiver and Transmitter Functional description Operational description Programming the 8251 Memory organization of 8085 Basics of microcontroller 89 51 DOE 20 as der Pin descripuoles ss a AURA Major blocks of microcontroller 89 51 Special Function regtster Input Output devices of microcontroller 89C51 P1 structure and operation Reading the Writing 0 to Avoid damaging the port Instructions reading the status of input port Reading tel y vagari TE IS TEES Read modify write Instructions OUP PO Memory organization of 89 51 Programi MECMO oue 3 6 Contents IDala THeDIOLV ood aree ed EA ce oan Direct and Indirect address area Section 2 EXPERIMENTS ON MICROPROCESSOR Chapter 4 Advance experiments 8251 Roll of 8251 with microprocessor 8085 Continuous transmission of data over TxD pin
12. RS 232 pin details are noted from the user s manual of the ESA 85 microprocessor kit and TxD pin is connected to RxD and RTS with CTS Command Status Port address 20H Data Port address 21H Mode word CDH Command word 35H The program is loaded from 8000H memory location and the data to be transmitted 1s stored at 8100H Mnemonics MVI A 00H OUT 21H OUT 21H OUT 21H MVI A 40H OUT 21H MVI A CD OUT 21H MVI A 35H OUT 21H LXI H 8100H LXI D 8200H IN 21H ANI 01H JZ EMPTY MOV A M INX H OUT 20H IN 21H ANI 02H JZ WAIT IN 20H XCHG MOV INX H MVI A 09H EMPTY WAIT Memory address 74 8000 8002 8004 8006 8008 800A 800C 900 9010 8012 8014 8017 801A 801C 8021 8022 8023 8025 2 9029 902 802E 802 8030 8031 Machine codes 3E 00 D3 21 D3 21 D3 21 3E 40 D3 21 3E CD D3 21 3E 35 D3 21 21 00 81 11 00 82 DB 21 E6 01 CA 1A 80 7E 25 D3 20 DB 21 E6 02 CA 25 80 DB 20 EB 77 23 09 CMPL 9033 BD XCHG 8034 EB JNZ EMPTY 8035 C2 1A 80 RST 3 8038 DF The program is executed and the first 10 data stored at 8100H to 8109H are checked The data gets transmitted to 8200H to 8209H location This is a block moving using serial communication technique for the given kit RST 3 instruction brings the control back to monitor program 4 3 SERIAL COMMUNICATION BETWEEN TWO KITS In this experiment co
13. jo 0 0 0 jo fji Cos 8000 1 O jo jo o 0 jo 0 jo jo 0 9 4000 O 1 0 o jo jo 0 0 jo 0 0 jo jo 2000 0 0 j1 jo 0 o 0 0 0 jo 0 C11 10009 o 0 0 0 jo 0 0 0 0 o 0 C12 0800H 0 0 jo 1110 0 0 0 jo 0 jo 0 13 0400H O 0 jo j jo 0 0 0 0 jo jo 4 02004 0 jo jo O jo 1 0 JO 0 0 0 jo 0 C15 0100 0 0 jo 0 0 jo jo I 0 jo 0 o o jo 0 TABLE 8 2 COLUMN SELECTION CODES FOR 15X7 MATRIX MOVING MESSAGE DISPLAYS Note that P2 7 15 not connected so treated as 0 code generation When single column is selected one has to provide the corresponding row selection codes also to lit the LED s of selected column The row selection code differs as per the user requirement for the 131 message to display To display 5 7 on the module one has to select the column first and provide row the data codes Each row column selection pattern is separated by less than Is delay This switching delay between the row column selection pattern 1s such that human eye can not detect the single row column selection pattern and form a continuous character pattern of 5 7 this case Table 8 3 shows the row selection codes to be provided when particular column is selected to display message 5 7 COLUMN ROW ROWS R7 TO PORTI SELECTEI CODE P1 4 P1 3 P1 2 P1 1 P1 0 R5 R4 R3
14. 15 interpreted during T4 8085 understands that 15 a code of two bytes instruction and second byte 15 stored in consecutive location So it makes PC 4002H and fetches the data from this 162 location Like this fetching the codes and data continues which in turn makes the signals on the pins of microprocessor to change with time as shown in figure 10 2 From Figure 10 2 one can understand that first Instruction NOP is made of one machine cycle M OF second instruction MVI A FFH is made of two machine cycles M OF and MR while third instruction JMP START is made of three machine cycles Mi OF M2 MR and M3 MR Op code fetch is made of four T states and memory read MR is made of three T states The timing waveforms show CLK address lines ALE RD and status line IO SO Sl which confirm the type of cycle o APPARATUS USED The ESA 85 microprocessor kit manufactured by Electro Systems Associates Bangalore and the PC based 24 channel logic state Analyzer LA 2124 manufactured by Electro Systems Associates Bangalore is used for this experiment The photograph of experimental setup 15 shown in Figure 10 3 In Figure 10 3 the various components of the set up are shown with their names on it e g a cable connecting the capture unit with parallel port of PC 15 given the name Computer interface cable capture un computer LA 2124 interface cable e v lw microprocessor
15. RS 0 Entry mode set for LCD HI to LO pulse Check for data fetch Return to main program RS 0 Clear LCD HI to LO pulse NOP NOP NOP NOP CLR EN LCALL WAIT LCD Check for data fetch RET Return to main program WRITE TEXT Write DATA to LCD SETB RS RS 1 MOV DATAI Move desired char to P1 SETB EN HI to LO pulse NOP NOP NOP NOP NOP NOP NOP CLR EN LCALL WAIT LCD Check for data fetch RET Return to main program WAIT LCD Check for data fetch MOV R2 03H Count in R2 MOV R3 0FFH Count In R3 CLR EN EN 0 RS 0 RW 1 CLR RS SETB RW MOV DATAI OFFH as input port SETB EN 1 MOV A DATAI Get data from LOOP JB ACC 7 HERE2 Check for DB7 Bit HERE2 NOP High check more NOP DJNZ R3 HERE2 152 RET HOME DELAY AGAIN HERE1 DELI AGAINI PON DJNZ CLR CLR LCALL RET CLR MOV SETB NOP NOP NOP NOP NOP NOP NOP CLR LCALL RET MOV MOV NOP NOP DJNZ DJNZ RET MOV MOV MOV MOV MOV JNB MOV DJNZ RET END e FINAL OUTPUT R2 LOOP EN RW DELAY RS DATA 20H EN EN WAIT LCD R2 03 R3 250 R3 HEREI R2 AGAIN 89H 10H R5 25 00H 8DH 00H 88H 60H PON 88H 00H R5 AGAINI Otherwise EN 0 RW 0 Provide delay Return to main program gt RS 0 Return home cmd HI to LO pulse Check for data fetch Return to main
16. 1 100 0E 06 FIGURE 12 26 A 0 AND 5 0 OUTPUT OF A LINES CONDITION 0 AND 5 1 four B inputs have a path to the outputs B Fie Edit View Simulation Trace Plot Tools jy seus meg SCHEMATIC1 QUAD2TO1MUX P f 8 x Analysis Watch Devices Time 100 0E 06 FIGURE 12 26 B 0 AND 5 1 OUTPUT OF B LINES 232 CIRCUIT FILE Libraries Local Libraries STMLIB quad2tolmux stl From PSPICE NETLIST section of pspice91 ini file lib nom lib Analysis directives TRAN 0 100us 0 PROBE INC quad2tolmux SCHEMATICI net INCLUDING quad2tol mux SCHEMATICI net source QUAD2TOIMUX X U5A N00342 N00357 Y1 G_DPWR G DGND 741 532 PARAMS IO LEVEL Z0 MNTYMXDLY 0 X USB N00348 N00367 Y2 G_DPWR G DGND 741 532 PARAMS IO LEVEL Z0 MNTYMXDLY 0 X 05 N00351 N00377 G_DPWR G DGND 741 532 PARAMS IO LEVEL Z0 MNTYMXDLY 0 X USD N00354 N00387 Y4 5 DPWR G DGND 741 532 PARAMS IO LEVEL Z0 MNTYMXDLY 0 X U4A N00065 N00068 G DPWR G DGND 741 504 PARAMS IO LEVEL 0 MNTYMXDLY 0 X 04 N00068 N00118 G DPWR G DGND 741 504 PARAMS IO LEVEL 0 MNTYMXDLY 0 X U4C N00071 N00203 G DPWR G DGND 741 504 PARAMS IO LEVEL 0 MNTYMXDLY 0 X N00318 N00068 00203 N00342 5 DPWR 6 DGND 74LS11 PARAMS IO LEVEL 0 MNTYMXDLY 0 X UIB N00321 N00068 00203 N00348 5 DPWR G DGND 74LS11 PARAMS O LEVEL 0 MNTYMXDLY 0
17. E Memory This option sets up the buffer memory length used for acquisition Choose the proper memory size from option available in this mode F Threshold Voltage This allows the voltage threshold to be set This 1s the point at which the high low 1 0 logic break occurs in the digital logic being tested For TTL this is 1 4 Volts for CMOS this is half of volts usually 2 5 Volts Apart from above setting the logic analyzer can be set for different colors printing varieties board address etc Various file management like saving certain analysis and later loading it renaming directory changing may be available as per logic analyzer models 3 RUN THE CAPTURE CYCLE In this phase actual data collection 15 done Normally after proper setup command may be used to start sampling Acquire command also can be used Acquire once or repeat randomly option may be available 4 ANALYZE THE RESULTS This 1s the very important part of the data collection interpretation To help the analysis better various facilities like cursor movement in display relative 159 measurement of position of states changing channels are provided One should refer to operation manual of concerned logic analyzer for better usage It also needs better understanding of what should be going on in the target digital system while capturing the data Try to fit this understanding with the logic state display of waveform and decide the proper work
18. GROUP A GROUP B FIGURE 5 4 Mode 2 status word format E MODE 1 EXPERIMENT In this experiment the basic concept of parallel communication through handshaking signal is studied Port A and Port B are taken as two I O devices The interfacing of their data bus and handshaking signals are achieved from a single 8255 chip EXPERIMENT I STUDY OF MODE I PORT A OUTPUT AND PORT B INPUT Figure 5 5 A shows the circuit diagram to use 8255 Mode 1 Here Port is configured as output Port while Port B is configured as input Port Data communication in Mode 1 can be done by two ways STATUS CHECK and INTERRUPT driven We will discuss about interrupt driven communication From Figure 5 5 A we know that to generate interrupt for Port A and Port B the interrupt enable flip flops INTE and are to be set through Port C pins PCs and respectively The control word to configure 8255 in Mode 1 with Port A O P amp Port B I P 1s as follows 87 OUTPUT X FIGURE 5 5 B Handshaking signals indicating timing to output data from Port A 88 FROM E PERIPHERAL FIGURE 5 5 C Handshaking signals indicating timing to receive data by Port B X Port B I O Port B in mode 1 PCy PC Port A O P Port A in mode 1 gt O mode To set and the required BSR control words are as follows X X X B S R 0 0 0 0 0 OD
19. PARAMETER MEASUREMENT INFORMATIONT Vcc ViT V IT V1 lon V Response 1 Control loL J Rc Rc Unless Otherwise Cc Specified Ve Figure 1 Vir Vir_ VoL Vcc x see Note VI O Open ly Response Control Open NOTE A is tested for all four receivers simultaneously Figure 2 liL lec Vcc J los Response Control Open Figure 3 los T Arrows indicate actual direction of current flow Current into a terminal is a positive value 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 MC1489 MC1489A SN55189 SN55189A SN75189 SN75189A QUADRUPLE LINE RECEIVERS SLLS095D SEPTEMBER 1973 REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION Vcc Pulse Generator see Note A See Note C Response CL 15 pF Control see Note B Open TEST CIRCUIT lt 10 ns lt 10 ns 4 V inn 90 90 ps 50 50 10926 X 1096 0 V lt PHL M tPLH 3 VOH 90 em Output ine 5096 o JEMEN ie OL trLH VOLTAGE WAVEFORMS NOTES A The pulse generator has the following characteristics Zo 50 tw 500 ns B CI includes probe and jig capacitances C All diodes are 1N3064 or equivalent Figure 4 Test Circuit and Voltage Wavef
20. 2 and 3 respectively e SERIAL DATA BUFFER The Serial Data Buffer 1s actually two separate registers a transmit buffer and a receive buffer register When data is moved to SBUF it goes to the transmit buffer where it 1s held for serial transmission Moving a byte to SBUF 15 what initiates the transmission when data is moved from SBUF it comes from the receive buffer TIMER REGISTER Register pairs THO TLO and TL1 are the 16 bit counting registers for Timer Counters 0 and 1 respectively e CONTROL REGISTER Special Function Registers IP IE TMOD TCON T2CON SCON and PCON contain control and status bits for the interrupt system the Timer Counters and the serial port 3 3 Input Output Devices of Microcontroller 89C51 Four ports PO P2 and P3 of 89 51 microcontroller are the main Input Output devices The four ports of the 89C51 PO P2 P3 each use eight pins making them 8 bit ports Port and Port 2 can be used for either address or data Port 3 can be used to provide interrupt and serial communication signals Port 15 used for data only no dual function For this reason 24 of the pins may each be used for one of two entirely different functions Address corresponding to each port 15 as follow Port O 80h Port 1 90h Port 2 AOh Port 3 BOh All ports are bit addressable The port pins are also TTL as well as CMOS compatible 56 e PI P3 STRUCTURE AND OPERATION A
21. 40 Synchronous Mode Receive In this mode character synchronization can be internally or externally achieved If the SYNC mode has been programmed ENTER HUNT command should be included in the first command instruction word written Data on the RxD pin is then sampled on the rising edge of RxC The content of the Rx buffer is compared at every bit boundary with the first SYNC character until a match occurs If the 8251A has been programmed for two SYNC characters the subsequent received character is also compared when both SYNC characters have been detected the USART ends the HUNT mode and 1s In character synchronization SYNDET is then set high and 15 reset automatically by the STATUS READ If parity is programmed SYNDET will not be set until the middle of the parity bit instead of the middle of the last data bit In the external SYNC mode synchronization is achieved by applying a high level on the SYNDET pin thus forcing the 8251 out of the HUNT mode The high level can be removed after one RxC cycle An ENTER HUNT command has no effect in the Asynchronous mode of operation Parity error and overrun error are both checked in the same way as in the Asynchronous Rx mode Parity 15 checked when not in HUNT regardless of whether the receiver is enabled or not CPU BYTE 5 2 BIT CHAR DATA CHARACTER ASSEMBLED SERIAL DATA OUTPUT TxD SYNC SYNC CHARZ DATA CHARACTER RECEIVE FORMAT SERI
22. ALOA E 7 77 GROUP A po GROUP B DEFINED BY MODE O OR MODE 1 SELECTION FIGURE 2 11 MODE 2 STATUS WORD FORMAT 2 3 2 8251A Universal Synchronous Asynchronous Receiver and Transmitter USART Figure 2 12 shows Pin diagram and block diagram of 8251A PPI chip e FUNCTIONAL DESCRIPTION e General The 8251A is Universal Synchronous Asynchronous Receiver Transmitter designed for a wide range of Intel Microprocessor such like 8048 8080 8085 8086 and 8088 Like other I O devices in a microcomputer system its functional configuration is programmed by the system s software for maximum flexibility The 8251A can support most serial data techniques in use including IBM Bi sync In a communication environment an interface device must convert parallel format system data into serial format for transmission and convert incoming serial format data into parallel system data for reception The interface device must also delete or insert bits or characters that are functionally unique to the communication technique In essence the 8251A Universal Synchronous Asynchronous Receiver and Trasmitter USART INTEL DATASHEET 20 interface should appear transparent to the CPU a simple input or output of byte oriented system data D D Dc RXp gt Voc GND RxC D lt DTR D lt RTS De DSR D lt RESET Txc c CLK wR cc TxD cs TxEMPTY cD oe CTS RD SYNDET B
23. An Introduction to Microcomputers Volume 0 to 3 Adam Osborne and Associates Inc 1977 P K Ghosh and P R Sridhar 0000 to 8085 Introduction to Microprocessor for Engineers and scientists 25 edition Prentice hall of India edition New Delhi Padmanbhan K Learn to use Microprocessor 4 edition EFY Enterprises P Itd New Delhi 1999 R S Gaonkar Microprocessor architecture programming and application with the 8085 21 edition Penram International Mumbai Rashid Mohammad Spice for circuits and electronics using PSPICE 2 and 3 edition Prentice hall of India Eastern Economy Edition New Delhi 210 edition New Singh Renu Microprocessor Interfacing and Application Age Publication P Itd 2006 Stan Gibilisco and Neil Sclater Encyclopedia Of Electronics 1 2 edition McGraw hill publishing inc N Y Taub Herbert Digital circuits and microprocessor Tata McGraw hill Publishing company Limited England 1982 Theagarajan R and Dhanasekaran S Microprocessor and its Applications New Age international P Itd New Delhi 1997 Titus Christopher A Larsen David G Titus Jonathan A 8085A Cookbook Howard W Sams amp Co Inc 1980 Walter Bosshart Printed Circuit Board Design and Technology Tata McGraw hill Publishing company Limited New Delhi 1993 Furht Himansu Parikh Microprocessor and Borivaje interfacing communication using the Intel SDK 85 Pren
24. To check the proper working of RAM chip perform following commands gt D 8000 L 10 If there 15 any problem with the EPROM of the target the ICE would respond with following massage similarly ICE would respond to RAM Thus one can test the proper working of the target system If one knows the exact contents of EPROM of target one can compare it with ICE memory checking 2 Testing I O One can check desired I O chip of target by obtaining their proper port address From Table 2 we learn that in present target we have 8255 8259 8279 8253 and 8251 as I O interfacing chips We will understand I O testing by considering 8255 at U35 in target system For this chip the port address are as following Port A 40H Port B 41H Port C 42H Control register 43H 181 We will develop a small assembly language program and run it through ICE to test the proper working of 8255 at U35 position in the target In the said program we configure all ports of 8255 as output ports and output on all port pins 05 or 15 alternately to produce a square wave at each pin After executing the program through ICE one can check using oscilloscope the square wave on each port pin To develop the program follow the following steps l 2 START Open the Ms Dos editor Type the following program MVI A 80H OUT 43H MVI A 00H OUT 40H OUT 41H OUT 42H MVI A FFH OUT 40H OUT 41H OUT 42H JMP START Save this program with
25. WR Write A LOW on this input pin enables the CPU to write data or control words into the 82 55 Ag and A port select O and port select 1 These input signals in conjunction with the RD and WR inputs control the selection of one of the three ports or the control word register They are normally connected to the least significant bits of the address bus Ao and Aj RESET Reset A HIGH on this input initializes the control register to OBH and all ports A B C are set to the input mode Bus hold devices internal to the 82C55A will hold the port inputs to a logic 1 state with a maximum hold current of 400uA Group and Group B controls The functional configuration of each port is programmed by the systems software In essence the CPU outputs a control word to the 82C55A The control word contains information such as mode set bit reset etc that initializes the functional configuration of a 82 55 Each of the control blocks Group A and Group B accepts commands from the Read Write Control logic receives control words from the internal data bus and issues the proper commands to its associated ports Control Group Port and Port C upper C7 Control Group B Port and Port C lower C5 Co The control word register can be both written and read as shown in the Basic Operation table Figure 2 3 shows the control word format for both read and write operations When
26. http www old computer com museum computer asp st amp c 805 http www orcad com http www rdos net sim http www thefreecountry com http www tomshardware com http www x86 org http www x86 64 org The detailed literature survey suggested that we need to develop the study material on the concentrated topic like microprocessor microcontroller circuit simulation and development tools CHAPTER 2 BASICS OF MICROPROCESSOR 085 2 1 INTRODUCTION 9085 Is one of the topics of present work Some experiments which can enlighten the basic concepts of 8085 was planned To understand 8085 properly the concept like timing diagram interrupts and interfacing are necessary For this the basic block diagram instruction set and programming aspects are to be thoroughly understood Following are necessary to study 8085 e Address data and control bus e Detailed knowledge of instruction sets e Timing process 8085 e Basic programming technique 2 2 MAJOR BLOCKS OF MICROPROCESSOR 8085 The block diagram of 8085 is shown in Figure 2 1 e GENERAL FEATURES O O O It is a 40 pin DIP device It is 8 bit parallel central processor Needs 5 V supply Basic speed is 3 MHz and above Has four vectored interrupts Facility of serial Input Output Can handle decimal binary and double precision arithmetic Can access directly 64KB memory On chip system controller and
27. 3 ov O jm 15 27PF WR XTAL 126 22 222 226 0 ON RARARAR 0 010 2222520 0 01UF FIGURE 8 3 CIRCUIT DIAGRAM OF MOVING MESSAGE DISPLAY 128 The corresponding rows of all the three displays are connected in series Hence there are seven rows and fifteen columns in the display This can be visualized from Figure 8 4 R2 R3 R4 R5 R6 R7 C15 C14 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 2 FIGURE 8 4 INTERNAL DIAGRAM OF 15X7 DISPLAY MODULE the seven rows of the display are connected to inputs of 7415245 that is IC U2 The output of the same is connected to port of microcontroller Out of total fifteen columns 1 from to C15 columns to C7 are connected to port2 of microcontroller through 74L S245 U4 Similarly the remaining eight columns C8 to C15 are connected to port3 of microcontroller through 7415245 U3 The microcontroller is provided with power on reset and a working frequency of 11 0592 MHz The connection details of modules with the microcontroller ports are shown in detail in Table 8 1 129 Signal from display A T 9c51 Port Pins DP1 DP2 DP3 R1 U2 A0 R2 U2 AI R3 U2 A2 R4 U2 A3 R5 U2 A4 R6 U2 A5 R7 U2 A6 C1 U3
28. D2 Do FUNCTION CLEAR DISPLAY RESET DISPLAY CLEAR DISPLAY FROM SHIFT SET DDRAM 0 SHIFT 0 I D 1 ENTRY MODE 0 CURSOR OR DISPLAY SHIFT AFTER DATA TRANSFER 1 DISPLAY ON OFF O 0 S C SHIFT DISPLAY CURSOR SHIFT CURSOR 0 R L SHIFT INTERFACE SINGLE 0 LINE DISPLAY LOAD ADDRS COUNTER WITH CGO ADDRS CG5 CG4 CG3 CG2 cai cao cas SUBSEQUENT DATA GOES TO CGRAM LOAD ADDRS COUNTER WITH DD0 TO ADDRS pps DD4 DD3 DD6 SUBSEQUENT DATA GOES TO DDRAM 141 READ BUSY BUSY FLAG BF FLAG ADDRS BF AC6 AC5 4 AC3 AC2 AC1 ACO AND 0 ADDRS COUNTER READ COUNTER 0 6 WRITE DATA CG DD RAM DATA 00 07 TO WRITE CGRAM OR DDRAM PLACE DATA CG DD RAM DATA FROM READ CGRAM OR DDRAM ON 00 07 TABLE 9 2 INSTRUCTION TABLE Here 16x1 CFAHI601 A YYB JB LCD module is used One can use any 16x1 module Figure 9 1 shows the block diagram of an LCD module eme geren Inzinicti n re m a CORTE Emin TECHN ED RAPA srt E bits re driver FIGURE 9 1 BLOCK DIAGRAM LCD MODULE The modules on chip memory include a CG character generator ROM CGRAM DD display data RAM an instruction register and a data register The CGROM stores patterns
29. Digital Gate MODEL PARAMETERS sss sk sk sk sj ok ok o ok okk D SII D 504 TPLHMN 1 800000 09 1 200000E 09 TPLHTY 4 500000E 09 3 000000 09 7 000000 09 4 500000 09 2 000000 09 1 200000 09 TPHLTY 5 000000E 09 3 000000 09 17 500000 09 5 000000 09 Digital IO MODEL PARAMETERS gt F gt gt k gt 2k gt k gt F 2k K R R OKE 2 IO STM IO 5 DRVL 0 60 6 DRVH 0 AtoD1 AtoD_S AtoD2 AtoD_S_NX AtoD3 AtoD_S AtoD4 AtoD_S_NX DtoAl DtoA_STM DtoA_S DtoA2 DtoA_STM DtoA_S DtoA3 DtoA_STM DtoA_S DtoA4 DtoA_STM DtoA_S TSWHLI 788 000000 12 TSWHL2 795 000000E 12 TSWHL3 788 000000 12 TSWHLA 795 000000E 12 TSWLHI 889 000000E 12 TSWLH2 88 7 000000E 12 TSWLH3 889 000000E 12 TSWLHA 88 7 000000E 12 TPWRT 100 000000 03 100 000000 03 JOB CONCLUDED TOTAL JOB TIME 39 229 2 A Quadruple 2 to 1 line multiplexer circuit is shown in Figure 12 24 It consists of AND and OR gate The digital input is shown in Figure 12 26 Use function table and simulate circuit using OrCad Capture CIS Plot output for one any condition using function table U1A 1 12 2 1 3 741511 741532 U1B 3 741511 741532 U4A U 741804 741504 04 5 gt 6 74LS04 FIGURE 12 24 QUADRUPLE 2 TO 1 LINE MULTIPLEXER CIRCUIT Quadruple 2 to 1 line multiplexer is a 74157 digital IC It has four multiplexers each capable of selec
30. END C project stim230ac stl written on Wed Feb 23 17 07 01 2005 by Stimulus Editor Serial Number 0 Version 9 1 IStimulus Get V Analog Plot Axis Settings Xrange 05 60ms Yrange 300 300 AutoUniverse IXminRes Ins IYminRes In STIMULUS SIN 0 230V 50000 circuit file for profile Full wave phase controller Diode MODEL PARAMETERS k sk sk sk sk sk sj ok ok ok ok ok o k k D1N4007 D1N4739 DIN4001 X X2 Xl Dgk IS 14 110000E 09 2 110000 15 14 110000E 09 100 000000 18 212 N 1 984 1 984 ISR 2 012000E 09 IKF 94 81 94 81 BV 1 500000 03 9 1 75 IBV 10 000000 06 1 2 10 000000 06 72056 IBVL 01 NBVL 21148 RS 03389 2 512 03389 5 TT 5 700000 06 5 700000E 06 25 890000E 12 89 000000 12 25 890000 12 50 000000 12 VJ 2 3245 75 3245 M 44 384 44 TBVI 604 396000 06 X X2 Xl Dsernes X X2 Xl Delay X X2 Xl Dkarev X_X2 X1 Dakfwd IS 10 000000E 15 1 000000E 12 100 000000E 12 40 000000E 12 RS 01 01 CJO 5 000000E 12 5 000000 12 5 000000 12 X X2 Xl Dbreak X_X1 x1 x1 x1 x1 dio IS 10 000000E 15 128 100000E 12 BV 220 100 000000 09 RS 5 I CJO 5 000000E 12 circuit file for profile Fullwave phase controller kee 3 Voltage Controlled Switch MODEL PARAMETERS SS ok ok sk sk sk sk sk sk sk sk obe obe ok k o ok ok ok ok oe ok ok ak ak ak X X2 Xl Vswitch RON 016 ROFF 1 818182 06 VON 5 VOF
31. MOV MOV MOVC MOV MOV MOV MOV RL MOV INC LCALL CJNE DJNZ DJNZ RET MOV MOV MOV RET MOV MOV DJNZ DJNZ RET ORG DB DB DB DB DB A R3 point next data on memory DELAYI provide switching delay R3 08 NXTDATA R3 lt 8 get the next data RI 01H Column 1 selection of P2 A R3 Get the data from memory A A DPTR sent data to for row codes 00H Off port3 connected display P2 RI select column of display A RI Get the selection code of A column in again R3 point next data on memory DELAYI provide switching delay R3 15 NXTDATAT R3 lt 15 get the next data R7 ABI If R7 00h jump to ABI R6 AB2 If R6 00h jump to AB2 OFFH Clear the display P2 00H 00H R5 01 Switching delay between columns R4 230 R4 HEREI R5 HERE2 700H Codes for 30H 36H 36H 36H OEH 3BH 57H 6FH 57H 3BH 3EH 5EH 6EH 76H 78H 7FH 7FH 7FH 77H 77H 77H 00H 00H 7BH 77H 6FH 00H 00H 76H 76H 76H 79H 7FH 7FH 7FH 7FH 7FH 136 DB 7FH 7FH 7FH 7FH 7FH 7FH 7FH DB 7FH END Software Explanation Software provides initialization and data write function for the display module Row selection codes are controlled by Port 1 of microcontroller and are stored in memory location at address 700h These row selection codes can be fetched by means of data pointer
32. P32 P3 3 P3 4 P1 2 P1 3 P1 4 1 5 TABLE 7 CONNECTION DETAILS OF LCD AND AT89C51 MICROCONTROLLER 115 un gt x un Z Q TABLE 7 1 B CONNECTION DETAILS OF KEYBOARD AND 9 51 MICROCONTROLLER e CIRCUIT FUNCTION The 10 4 matrix keyboard shown in Figure 7 2 provides 40 keys The keyboard has actually 8 rows and 5 columns The first ten keys will represent numbers 0 9 next twenty six keys represent the alphabets A to Z and remaining four keys represent the symbols The circuit shows that rows are connected with PO P0 0 to PO 7 and columns are connected with P2 P2 0 to P2 4 As high potential 15 applied to rows and columns of the keyboard initially they remain high 45v The columns and rows make contact only when a key Is pressed When a key 15 pressed the key must be identified by its column and the row and the intersection of the column and row must change from high to low To detect a pressed key the microcontroller grounds all rows by providing 0 to the Port then it read the columns If the data read from the columns P2 4 to P2 0 11111 no key has been pressed and the process continues until a key press is detected However if one of the column bits has zero this means that a key press has occurred For example if P2 4 to P2 0 11110 shows a key in column 1 has been pressed After a 116 key press 15 detected the microcontroller will go through the process o
33. TABLE 9 3 ADDRESSES FOR DISPLAY POSITION On power on the LCD DDRAM is set to 00h so we can directly write data to first 8 bits from left side as shown in Table 3 However the 9 character as shown in memory map is at address 40h This means that if we write a character after 8 character directly it will not appear on 9 character position That 15 because the 9 character will effectively be written to address 09h but the 9 character position 15 at address 40h Thus we need to send command to the LCD that tells it to position the cursor on the 9 character position The set cursor position instruction is 80h To this we must add the address of the location where we wish to position the cursor So to display character at 9 position we must add 80h 09h 0C0h Thus sending to the LCD will position the cursor on 9 character position of the LCD and write the user defined character 143 93 INTERFACING LCD MODULE WITH MICROCONTROLLER 89C51 Figure 9 2 shows the schematic diagram of the interface module LCD MODULE AT89C51 SS ZZZ22822 CON2 11 0592MHz FIGURE 9 2 SCHEMATIC DIAGRAM OF INTERFACE MODULE All required signals are taken out to connector J1 Pin configuration of J1 Is as follows PIN NUMBER SIGNAL PIN NUMBER SIGNAL I GND 9 D2 2 VCC 9 D3 3 RS 10 D4 4 R W 11 D5 5 E 12 D6 6 DO 13 D7 7 D1 14 VCC Note that BL1 anode co
34. and work out to perform my research work easily am thankful to him for use his scientific and innovative idea for my research work In deep sense of gratitude for my parent Dr Basanti Chandrakant Nanavati and Dr Chandrakant J Nanavati without there blessing and moral support could not perform this task easily am especially thankful to my parents for there help in all regards and give me opportunity to gain a higher level education Also 1 am thankful to Miss Priti J Joshi Mr J B Joshi Mrs 5 J Joshi Mr P J Joshi and Miss B J Joshi for their moral support during my completion period of my Ph D work thankful to my colleagues Mr Anand Bhaskar for plan out research problem and discuss on research problems am thankful to him for his helping hand on my research work 1 am thankful to Dr Kapil K Bhatt lecturer Department of Physics Wilson College Mumbai Dr Urmiben M Joshi and Dr K P Thummer for their useful tips in research problems am thankful to my sister Mrs Kruti Buch my brother in law Mr Harshal Buch for their love and help me in moral boost my research work 1 am thankful to my little nephew Mr N H Buch whose smiling face makes my work easy and boost me for to cheer up me in my hard work am thankful to Mr Udaybhai J Khachar for his kind help during discussing on various problems am thankful to Mr Jatin Kamdar Dr Bimal H Vyas Dr Chetan M Thakar Mr Jatin Joshi Mr Rajendra
35. port C 24 Both input and output are latched The 5 bit control port port C 15 used for control and status for the 8 bit Bi Directional bus port port Bi Directional Bus I O Control Signal Definition CONTROL WORD D7 De Ds D4 D3 D2 D1 Dc 2 0 1 INPUT 0 OUTPUT PORT 1 INPUT 0 OUTPUT GROUP MODE 1 INPUT 0 OUTPUT DATA FROM CPU TO 8255 IBF PERIPHERAL BUS DATA FROM DATA FROM PERIPHERAL 8255 TO TO 8255 PERIPHERAL DATA FROM 8255 TO 8085 Mode 2 Bi Directional timing diagram 25 CONTROL WORD CONTROL WORD D7 De Ds D3 02 D1 Do D7 De Ds D3 02 D1 Do ER ER 2 2 2 1 INPUT 1 INPUT 0 OUTPUT 0 OUTPUT FIGURE 2 10 A Mode 2 And Mode 0 Input Output Configuration INTR Interrupt Request A high on this output can be used to interrupt the CPU for both input or output operations CONTROL WORD CONTROL WORD D7 De Ds D4 D3 D2 D1 Do D7 De 05 D4 D3 D2 D1 Do EE 1 lt FIGURE 2 10 B Mode 2 And Mode 1 Input Output Configuration FIGURE 2 10 MODE 2 COMBINATIONS 26 Output operations OBF Output Buffer Full The OBF output will go LOW to indicate that the CPU has written data out to port A ACK Acknowledge A LOW on this input enables the three state output buffer of port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE flip flop associated with
36. 0 0 0 161 NOP instruction A FF instruction JMP instruction Milopcode Fetch cycle Fetch cycle 2 Reod Cycle Mi opcode Fetch cycle M2 BOLA eb e dO OM Pp UIN OECD T T CLK 15 H Higher order N Higher order Higher order 60 Memor y address Memory address 40H Memory address address t I l i i i i i dod 10 M 0 S1 1 0 1 OF XI10 M 0 51 1 So O MR gt FIGURE 10 2 TIMING WAVEFORM OF THREE INSTRUCTION PROGRAM During this time higher byte of address AD remains same RD remains low during T and clock pulses Approximately after middle of T4 RD becomes high again At this stage code for first instruction NOP 15 taken 8085 and interpreted T4 state 1s needed for interpretation 8085 now knows that 1s only one byte instruction So in next location of RAM memory another code for next instruction is stored Hence it advances PC by one and makes it to contain 4001H to fetch the code of next instruction 1 e MVI A FFH Now address pins contain logic state as follows Pin Logic states Pin Logic states Ais 0 0 A14 1 0 0 0 0 AD 0 0 AD 0 A10 0 AD 0 Ao 0 0 Ag 0 ADo Program Address 4001H A new OF starts with ALE Again during RD goes low The opcode byte 3E 15 available on data lines
37. 0 DC 12V In first statement PSPICE automatically consider 12V DC voltage source between node 1 and 0 In second we have define DC voltage of 12V between node 2 and O Independent DC current source In general I is symbolic identification for current source In general it can be written as 199 I lt NAME gt N N DC value Here lt gt 15 current source stimuli name N and N are as described independent DC voltage source EXAMPLE H I 0 3 5mA D 2 0 DC 3 5mA Statements are similar to DC voltage source For current we have given values in Ampere Dependent Sources These types of sources are again divided in four types of sources e Voltage Controlled Voltage sources e Voltage Controlled Current sources e Current Controlled Voltage sources e Current Controlled Current sources They could have either fixed value or a polynomial value Polynomial Sources The symbolic representation of this source is POLY n where 1 15 default And it 15 number of dimensions of polynomial which depend on the number of controlling sources Poly n controlling nodes coefficients values Here the output source or the controlling sources can be voltages or currents For voltage controlled sources the number of controlling nodes must be twice the number of dimensions but for current controlled sources it 15 equal to controlling nodes These are arbitrary values Example Let us consider three co
38. 102 done with interrupt pins which would ultimately connect each interrupting switch SW to SW5 with the interrupt pin of 8085A refer to Table 6 3 NAND eate Interrupt SW 7400 TRAP SW UIB 7400 RST 7 5 s U1D 7400 RST 5 5 SW U2A 7400 INTR Table 6 3 Connections of interrupt generating switches with interrupt pins of 8085A SWI SW2 SWA SW5 To generate individual independent interrupt on any of the 8085A interrupt pin press any switch from swl to sw5 Switch sw6 generates simultaneous interrupts on all pins of 8085A 2 Code providing circuit for INTR This 15 specially designed for INTR Eight SPDT switches are used to set Os and or 15 on the data lines through a buffer IC 741 5245 The fixed terminals of all switches 1 terminal 2 of switches sw7 to sw14 are connected to individual data lines through 74LS245 The floating terminals of switches are connected with ground or VCC i e terminal 3 of switches are connected with ground and terminals 1 are connected with VCC The outputs of 74LS245 are terminated on another connecter J3 From connecter J3 wires are stretched to data pins of 8085A kit The pins G and DIR of 74LS245 are connected to INTA and 5V respectively When INTA from 8085A becomes low it enables 74LS245 to pass the status of switches sw7 to sw14 to the data lines 103 c CD DATA 1 2 3 gt 4 5 lt 6 a 7 8 FIGURE 6 2 CODE PROVIDING
39. 2 Since Q 0 and is connected to the transistor gate the transistor is off 3 When the MI transistor is off 1 blocks any path to the ground for any signal connected to the input pin and the input signal is directed to the tri state BUF2 4 When reading the input port in instructions such as MOV we really reading the data present at the pin In other words it 15 bringing into the CPU the status of the external pin This instruction activates the read pin of BUF2 TRI STATE buffer2 and lets data at the pins flow into the CPU s internal bus WRITING 0 TO THE PORT Now what happens if we write a 0 to a port that was configured as an input port If we write a 0 low to port bits then Q 0 and Q 1 As a result of Q 1 As a result of Q 1 the transistor is on If is on it provides the path to ground for both R1 and input pin Therefore any attempt to read the input pin will always get the low ground signal regardless of the status of the Input pin This can also lead to damage the port as explained next AVOID DAMAGING THE PORT When connecting a switch to an input port of the 89C51 we must be very careful This is due to the fact that the wrong kind of connection can damage the port Never connect direct to the 89C51 port pin If a switch with Vcc and ground 15 connected directly to the pin and the transistor is on it will sink current from both internal loa
40. 211 1 Moore K E Fronheisher Vinay Khanna John Dylaune G G Sawyer M E Edison T C Daly J F Vittera Motorola semiconductor product Inc Microprocessor applications manual McGraw hill publishing inc N Y Motorola microprocessor 68C00 applications 2 3 4 5 6 T 5 9 10 11 12 13 14 15 16 17 Ahson S L Microprocessor with application in process control Tata McGraw hill Publishing Company Limited New Delhi 1992 Baker R Jecob Li Harry W Boyce David E CMOS Circuit design layout and simulation Prentice hall of India Bose Sanjay Digital System From Gates to Microprocessor 286 edition New Age International Itd 1992 Dr H N Pandya Printed Circuit Board Gujarat Granth Nirman Board Ahmedabad India Dr H N Pandya Understanding P C B Designing software 1 edition Saurashtra University Rajkot 2006 Electronics concepts handbook vol 1 to 3 McGraw hill publishing inc N Y Giacoletto Electronics Designers handbook one edition McGraw hill publishing inc 9nd edition Tata Hall Dougles Microprocessor and Digital system McGraw hill Publishing Company Limited J C Whitaker Electronics Handbook IEEE Press John Markus Guidebook of Electronics Circuit McGraw hill publishing inc Kenneth J Ayala The 8051 microcontroller Architecture Programming D edition Penram Intern
41. 2E 5 RO5 775 216 ENDS OPAMP DEC 10 10HZ 100K HZ AC VM 7 VP 7 PROBE END OUTPUT WAVEFORM FILTER PSpice A D Lite FILTER active Fie Edit View Simulation Trace Plot Tools Window Help 9 Jesus FILTER Ure 49 c dal Analysis watch Devices 1 FIGURE 12 15 FREQUENCY RESPONSE FOR ACTIVE BAND PASS FILTER 12 3 1 2 DC CIRCUITS Following the nomenclature discussed in the introduction part of this chapter we have tested following DC circuits EXAMPLE 1 Bipolar transistor circuit is shown in Figure 12 16 where the output is taken from node 4 Calculate and print the sensitivity of the collector current with respect to all parameter Print the details of bias point 217 OrCad Spice A D package to write Pspice simulation text file BIASING SENSITIVITY OF BIPOLAR TRANSISTOR AMPLIFIER FIGURE 12 16 BIASING SENSITIVITY OF BIPOLAR TRASISTOR AMPLIFIER Here we will simulate above circuit using text file For this we will use VCC70 DC I5V VRC 6 4 DC OV END the output The output for sensitivity analysis and the bias point follow R17347K R2302K RC 76 10K RE502K XQ1 43 5 SUBCKT 6 7 5 RB 12 100 RE351 RC4610 RBE 23 1K RO 43 100K VI 7 1 DC 0V F1 43 VI20 ENDS QMOD SENS I VRC The SENS command does not required PRINT command for printing 218 SMALL SIGNAL BIAS SOLUTION TEMPERATURE
42. 8150 JMP 8100 RST 6 5 RST 5 5 96 Now enter following program at 8150 and 8100 for RST 6 5 and RST 5 5 service routines For RST 5 5 AT 8150 8150 7E MOV DATA TO A FROM 8400 8151 D3 41 OUT 41H OUTPUT THROUGH PORT B 8153 23 INX H 8154 05 DCR B 8155 C2 59 81 JNZOUT ALL BYTES TRANSFERRED 8158 76 HLT YES HALT 8159 OUT C9 RET OTHERWISE RETURN TO MAIN PROGRAM For RST 6 5 AT 8100 8100 DB 40 IN 40H READ FROM PORT A 8102 12 STAX D AND STORE AT DE 8500 8103 13 INX D ONWARD 8104 C9 RET AND RETURN TO MAIN PROGRAM Note that in this case you may have to interface Port A and Port B through buffer chip e g 7407 This logic of programs for mode 2 15 almost equivalent as mode 1 977 6 ADVANCE EXPERIMENTS ON INTERRUPTS Pad d d d d 4 d d In this experiment the basic concepts of interrupt of 8085A are studied Interrupt checking interrupt reorganition their vector addresses priority masking etc are understood through the specially designed interfacing circuit These circuits are to be connected to the microprocessor kit ESA 85 61 ROLL OF HARDWARE AND SOFTWARE INTERRUPTS WITH MICROPROCESSOR 80852 o BASICS THEORY An interrupt In 8085A is a facility to suspend execution of any current program of 8085A temporarily and switch to the program execution of interrupting device The microprocessor based system 15 alway
43. 8251A D6 D2 SYNDET BRKDET TxEMPTY PARITY ERROR The PE flag is set when a parity error is detected It is reset by the ER bil of the Command Instruction PE does not inhibit operation of 8251 OVERRUN ERROR The OE flag is set when the CPU does not read a character before the next one become available It is reset by the ER bit of the Command Instruction OE does not inhibit operation of the 8251 However previously overrun character is lost FRAMING ERROR Async only The EE flag is set when a valid stop is not detected at the end of every character It is reset by the ER bit of the Command Instruction eE does not inhibit operation of the 8251 DATA SET READY Indicate that the DSR is at a zero level FIGURE 2 19 STATUS READ FORMAT Some of the bits in the Status Read format have identical meaning to external output pins so that the 8251A can be used in a completely polled or interrupt driven environment TxRDY 15 an exception 43 2 4 MEMORY ORGANIZATION OF 8085 8085A is mostly interfaced with RAM and EPROM memory chips We know that 8085A has 16 address lines This enables it to address 64 Kilobytes KB of memory locations To make a useful system 8085 generally EPROM and RAM chips together comprise this address space 6264 is a commonly used RAM chip with 2764A and 27128 EPROM chips widely used chip with 8085A Figure 2 20 and 2 21 shows pin d
44. CIRCUIT DESCRIPTION SS ok ok ok sk sk sk sk 8k jesse ok ok ok ok dede he obe obe obe k ok ok ok ok ok ok ok ak ak ak k Libraries Local Libraries STMLIB stim230ac stl From PSPICE NETLIST section of pspice91 ini file nom lib Analysis directives TRAN 0 50ms 0 PROBE full wave phase controller 5CHEMATIC net INCLUDING full wave phase controller SCHEMATIC1 net source FULLWAVE PHASE CONTROLLER D DI N00011 DIN4007 D D2 00011 N00027 D1N4007 D D3 0 00014 DIN4007 D D4 N00014 N00027 D1N4007 V N00011 NOOO14 STIMULUS V1 D D5 00273 DIN4739 R_R4 N00352 N00273 1 11MEG X X2 N00027 00368 0 2N3669 C CI N00352 0 0 01u X Xl N00273 N00352 N00368 232646 R RI N00273 N00027 10k R3 N00368 100 RESUMING full wave phase controller schematicl fullwave phase controller sim cir full wave phase controller 5CHEMATIC I als INCLUDING full wave phase controller SCHEMATIC1 als ALIASES 211 D DI D1 1 0 2 N00011 D D2 D2 1 N00011 22N00027 D D3 D3 1 0 2 N00014 D D4 D4 1 N00014 22N00027 V VI V1 N00011 N00014 D 5 D5 1 0 2 N00273 R R4 R4 1 N00352 2 N00273 X X2 X2 A N00027 G N00368 K 0 C CI C1 N00352 0 X X1 B2 N00273 E N00352 1 00368 R RI R1 12N00273 2 N00027 R R3 R3 1 0 22N00368 ENDALIASES RESUMING full wave phase controller schematicl fullwave phase controller sim cir
45. CIRCUIT FOR INTR o EXPERIMENTAL o HARDWARE CONNECTION Inspect the hardware details of your microprocessor kit Find out the correct pins of the connector which lead to the connection to interrupt pins of 8085A processor chip For example the kit we have used ESA 85 2 ELECTRO SYSTEMS ASSOCIATES BANGALORE is having following details for interrupt pins of 8085A which is shown in Table 6 4 Connector P1 Not available Not available Table 6 4 Details of interrupt pins of 8085A Using the information such as presented in Table 6 4 one should connect the wires from connector on interfacing module refer to Figure 6 1 to the connector on microprocessor kit In our case this is shown in Table 6 5 We have bypassed the circuit of the kit 104 Connector J1 Connector Kit 8085 processor of interfacing module P 1 7 PIN A RST 5 5 Direct on chip 8085A INTR Table 6 5 Connection over connector J1 of interfacing module For understanding the interrupt INTR one should connect the data lines ADO to AD7 of 8085A with the connector J3 of interfacing module Also the INTA pin of 8085A is to be connected with pin 2 of connector J4 of interfacing module Connect 5 V supply with pin 1 of J4 In our case the connection of data lines with interfacing module is as shown in Table 6 6 interfacing module 2 5 w 18 9 Connector J4 Connector kit interfacing module Table 6 6 Connection over connect
46. Mode Stimulus file Editor local Model libraries Stimulatior primitive Custom OrCad Pspice include file FIGURE 12 5 CONFIGURATION PSPICE Here in model editor we created model or used in built model and configured as a global or local model which are used in our circuit Every stimuli we have used as an input we need to give input waveforms which are generated at stimulus editor and this generated stimulus are stored in stimulus file with STL extension Also user defined or standard included file which are stored as INC should be added to this configuration Stimulation output file until now we had discussed about circuit design part model simulation configuration and some associated files which we need for simulation After simulation Pspice generates output file They are either in the form of waveform or text file These file are known as waveform data file and output file Waveform data file Waveform data file displays graphically output of simulation Pspice reads circuits file netlist file model library and inputs of the circuit automatically and displays circuit analysis waveform at different net pins of components and parts which are cross probed This can be set simulation progresses or as simulation computes In output waveform data file you can add more waveform by add trace or by add cross probes in circuit file Output file The output file is ASCII text file Output file contains netlist of prepar
47. On all other products production testing of all parameters processing does not necessarily include testing of all parameters INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 MC1489 MC1489A SN55189 SN55189A SN75189 SN75189A QUADRUPLE LINE RECEIVERS SLLS095D SEPTEMBER 1973 REVISED OCTOBER 1998 gt 1A OK 1 CONT 2 THRS ADJ 2 2 5 3A 19 3 CONT 9 13 logic symbolt 4 CONT 125 T This symbol is in accordance with ANSI IEEE Std 91 1984 and IEC Publication 617 12 Pin numbers shown are for the D J N NS and W packages logic diagram positive logic A Y Response Control schematic each receiver Vcc 1 66 ko Output Y Response Control Input A GND MC1489 MC1489A SN55189 5 55189 5 75189 5 75189 Resistor values shown nominal 35 TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MC1489 MC1489A SN55189 SN55189A SN75189 SN75189A QUADRUPLE LINE RECEIVERS SLLS095D SEPTEMBER 1973 REVISED OCTOBER 1998 absolute maximum ratings over operating free air temperature unless otherwise noted t Supply voltage Vcc see Note 1 2 10 V PP 30 V uy TT E 20 mA Continuous total power dissipation See Dissipati
48. PSW register contains program status information as detailed in figure 3 3 54 MSB LSB CY AC 50 OV P SYMBOL POSITION NAME AND SIGNIFICANCE CY PSW 7 Carry flag AC PSW 6 Auxiliary carry flag for BCD operation FO PSW 5 Flag O available to the user for general purposes PSW 4 Register bank select control bits 1 amp PSW 3 0 Set Cleared by software to determine working register bank PSW 2 Overflow flag PSW User defined flag PSW 0 Parity flag Set Cleared by hardware each instruction cycle to indicate an odd even number of one bits in the accumulator i e even parity NOTE THE CONTENTS OF RS1 RS0 ENABLE THE WORKING REGISTER BANKS AS FOLLOWS 000 BANK 0 00H 07H O 1 BANK 1 08H OFH 1 0 BANK 2 10H 17H 1 1 BANK 3 18H FIGURE 3 3 PROGRAM STATUS WORD REGISTER STACK POINTER The Stack Pointer Register is 8 bits wide It is incremented before data 1s stored during PUSH and CALL executions While the stack may reside anywhere in on chip RAM the Stack Pointer is initialized to 07H after a reset This causes the stack to begin at location 08H DATA POINTER The Data Pointer DPTR consists of a high byte DPH and a low byte DPL Its intended function 15 to hold a 16 bit address It may be manipulated as 16 bit register or as two independent 8 bit registers 55 PORTS 0 TO 3 P2 and P3 are the SFR latches of Ports 0
49. Probe Probe Output WIDTH Width PRINT Print statement The results from AC DC analysis can be obtained in the form of table The print statement for DC AC output takes the form PRINT AC DC output variables The maximum number of output variable is eight in any print statement But more then one print command can be used to get more output Variables are printed as a table with each column corresponding to one output variable The result of this statement are stored 1n output file Example PRINT DC V 2 V 3 6 V R5 VCE QO I VIN 6 The number of output variable can be changed by the NUMDGT option on the OPTIONS statement here we will not discuss this statement PLOT STATEMENT The results from dc analysis can also be obtained in the form of line printer plots The plots are drawn by using characters and the results can be obtained from any kind of printer The plot statement for dc outputs takes the following form PLOT DC output variables lower limit value upper limit This statement also having same constrains for output as print statement It also permit 8 output variable for any plot statement But it also allow more then one PLOT statement Example PLOT DC V 2 V 3 5 VCE Q2 IC Q2 DC V 5 V 4 7 0 10V IB Q1 0 50MA 1 50MA SOMA 204 12 3 Here few things to be noted for Ist statement the y axis 1s by d
50. R2 R1 C15 39H O 04 CM 0 04 C13 0 04 2 C12 O 0 CH 0 O C10 0 co 0 Cos 0 co7 SH 0 1 6 0 CO 0 C04 5EH 0 I O 0 1 04 2 c2 0 1 od coi 78H 101 4 TABLE 8 3 ROW COLUMNS SELECTION CODE TO GENERATE CHARACTER PATTERN OF 5 7 By means of software burnt in microcontroller these codes are output to three ports and corresponding pattern is created on display module This can be visualized in Figure 7 6 FIGURE 8 6 5 7 MESSAGE PATTERN ON DISPLAY MODULE By means of software appropriate column 15 selected and row codes for each digit 1 e 5 width 7 hieght are fetched from the ROM Row codes are saved on memory location 700h onwards For moving the message 5x7 shift the row data 132 selection right side once as the data on ROM are 700h onwards So for first shift DPTR data pointer must be set to 701h and for continuous shifting increment the DPTR till the last data saved For better understanding Figure 8 7 shows the step by step display pattern of the module o o o e e e e e e o e e o e e o o e e O e O e OOOOO
51. X UIC N00324 N00068 00203 00351 5 DPWR G DGND 74LS11 PARAMS 233 IO LEVEL 0 MNTYMXDLY 0 X U2A N00327 N00068 N00203 N00354 5 DPWR G DGND 741 511 PARAMS 1 LEVEL 0 MNTYMXDLY 0 X U2B N00330 N00118 00203 00357 5 DPWR G DGND 74LS11 PARAMS IO LEVEL 0 MNTYMXDLY 0 X U2C N00333 N00118 00203 00367 5 DPWR G DGND 74LS11 PARAMS IO LEVEL 0 MNTYMXDLY 0 X U3A N00336 N00118 300203 00377 5 DPWR G DGND 74LS11 PARAMS 1 MNTYMXDLY 0 X U3B N00339 N00118 00203 N00387 5 DPWR G DGND 74LS11 PARAMS IO LEVEL 0 MNTYMXDLY 0 UAI STIM 1 0 G_DPWR G DGND N00318 IO STM STIMULUS AI A2 STIM 1 0 G DPWR G DGND N00321 IO STM STIMULUS A2 A3 STIM 1 0 G DPWR G DGND N00324 IO STM STIMULUS A3 A4 STIM 1 0 G DPWR G DGND N00327 IO STM STIMULUS A4 U BI STIM 1 0 G_DPWR G DGND N00330 IO STM STIMULUS BI U B2 STIM 1 0 G DPWR G DGND N00333 IO STM STIMULUS B2 U B3 STIM 1 0 G DPWR G DGND N00336 IO STM STIMULUS B3 BA STIM 1 0 G DPWR G DGND N00339 IO STM STIMULUS B4 5 STIM 1 0 86 DPWR 5 DGND N00065 IO STM STIMULUS S STIM 1 0 G DPWR 5 DGND 300071 IO STM STIMULUS E RESUMING quad2tolmux schematicl quad2tol mux sim cir quad2tolmux SCHEMATICI als INCLUDING quad2tol mux SCHEMATICI als ALIASES X U5A USA A N00342 BzN00357 Y Y1 VCC G DPWR GND G_DGND 234 X USB GND G_ X_U5C GND G_ X USD GND G_ X
52. _ Y2 Y2 _ Y3 Y3 _ Y4 Y4 _ GND GND _ _ VCC VCC ENDALIASES RESUMING quad2tol mux schematicl quad2to mux sim cir END 05 1 5us 0 Repeat Forever 505 505 0 EndRepeat STIMULUS STIM 1 1 CLOCKP 1005 50500 05 0 505 1 Repeat Forever Sus 0 505 1 EndRepeat STIMULUS B2 STIM 1 1 CLOCKP 1005 505 1 0 05 1 50 0 Repeat Forever 505 505 0 EndRepeat STIMULUS STIM 1 1 CLOCKP 1005 50500 0s 0 5us 1 Repeat Forever 236 Sus 0 505 EndRepeat STIMULUS 4 STIM 1 1 CLOCKP 1005 50500 050 5us 1 Repeat Forever 505 0 505 EndRepeat STIMULUS STIM 1 1 CLOCKP 1005 505 10 05 1 505 0 Repeat Forever 505 1 505 0 EndRepeat STIMULUS 2 STIM 1 1 CLOCKP 1005 50500 050 5us 1 Repeat Forever 505 0 505 EndRepeat STIMULUS AI STIM 1 1 CLOCKP 1005 5us 1 0 05 1 50 0 Repeat Forever 505 505 0 EndRepeat STIMULUS AI STIM 1 1 CLOCKP 1005 Sus 1 0 05 1 505 0 257 Repeat Forever 505 1 505 0 EndRepeat STIMULUS 2 STIM 1 1 CLOCKP 1005 50500 050 505 Repeat Forever 505 0 505 EndRepeat STIMULUS STIM 1 1 CLOCKP 1005 505 10 05 1 505 0 Repeat Forever 505 505 0 EndRepeat STIMULUS 4 STI
53. add to simulation profile 192 OrCAD Capture SCHEMATIC1 PAGE1 E ale s gt e e ej 9l lol y 65 elal V ElI Simulation Settings paper spice General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Add as Global Filename Include Files Include files are loaded before the circuit They can include most valid PSpice commands such as PARAM and FUNC definitions OK Cancel Help Windows Media Player Ul PSpice Microsoft Word amp X OrCAD Capture StmEd example sti Simulation Settings FIGURE 12 4 IMPLEMENTATION OF INC FILE Configuring model library stimulus and include files Pspice normally needs model library stimulus and include files to complete the definition of a part and run simulation These files depend on configuration of your model libraries and other associated files Most of these are automatically configuration setup but you can change as per your design You can configure by adding or deleting files from this automatically generated configuration Also you can apply these file as a local means for your circuit or as global means for any circuit which are to be simulated The whole configuration we had discussed could be figured as following figure 12 5 193 OrCad Stimulus editor Globa Mode Libraries Mode Input OrCad Definitions waveform
54. are listed below gt For all key has been released Os are output to all rows PO at once and the columns P2 are read and checked repeatedly until all the columns are high When all columns are found to be high the program waits for a short amount of time before it goes to the next stage of waiting for a key to be pressed For any key closure the columns are scanned over and over in an infinite loop until one of them has a 0 on it After the key press detection it scans the columns P2 again It ensures that the first key press detection was not an erroneous one It goes to the next stage to detect which row it belongs to otherwise it goes back into the loop to detect a real key press 124 gt For which row the key belongs to it grounds one row at a time by sending appropriate code to Port 0 and reading the columns each time If it finds that all columns are high this means that the key press cannot belong to that row therefore it grounds the next row and continues until it finds the row the key press belongs to After finding the row it sets up the starting address for the look up table holding the key codes for that row and goes to the next stage to identify the key Forany key press it rotates the columns bits right one bit at a time in the carry and checks to see if it is low 0 If the carry flag is set DPTR in incremented once Upon finding the zero it pulls out the ASCII code for that k
55. as discussed in introduction of this chapter We have configured input waveform as shown in below Figure 12 12 SIN Attributes Mame WT Offset value E Amplitude 12304 Frequency Hz 50 Time delay sec 0 Damping factor 0 Phase angle degrees 0 Cancel Apply FIGURE 12 12 INPUT WAVEFORM ATTRIBUTES The frequency response analysis is invoked by TRAN command The output as shown in Figure 12 13 15 invoked by using PROBE command For NP 10 FSTART Os FSTOP 50ms the statement is TRAN 0 50ms 0 SCHEMA TIC1 Fullwave phase controller OrCAD PSpice A D fullwave phase controller SCHEMATIC1 Fullwave phase controller active File Edit View Simulation Trace Plot Tools Window Help 37 amp SCHEMATIC1 Fullwave phase P amp amp amp Miry E P575 s Sms Bs 81 2 U R1 1 E fullwave pha eircuit file for profile Fullwave phase controller Reading and checking circuit Circuit read in and checked no errors Calculating bias point for Transient Analysis Bias point calculated Transient Analysis Transient Analysis finished Simulation complete xj 4 Time step 2 043 0 Time 05 Analysis A Watch A Devices For Help press Fi FIGURE 12 13 OUTPUT WAVEFORM OF FULL PHASE CONTROLLER CIRCUIT 210 The output circuit file will be generated as below Output circuit File circuit file for profile Full wave phase controller
56. bits e Synchronization can be achieved internally or externally e Sync character can be automatically inserted e Synchronous baud rate can be DC to 265K baud o For Asynchronous operation e The character length can be 5 6 7 or 8 bits e Clock rate be 1 16 or 64 times baud rate e Break character generation facility is available e Stop bits can be programmed to be 1 or 2 e n built false start bit detection facility e Automatic break detect and handling facility e Asynchronous baud rate from DC to 19 2K baud o be operated full duplex and double buffered mode o Parity over run and frame error be detected Direct interface ability of 8251A with 8085A microprocessor has given good applied gadgets like l Interfacing with CRT terminal 2 Interfacing with telephone lines In the present work it is aimed to present the important characteristics of 8251A In such a way that student can verify the same experimentally without using extensive hardware The examples shown above need good amount of hardware to use 8251A For more details refer to section 1 chapter 2 We concentrate on the asynchronous mode of 82514A 4 2 CONTINUOUS TRANSMISSION OF DATA ON TxD PIN In this experiment the basic understanding of transmission section 8251A is considered The data stored into the register of 8085A is transmitted over TxD pin continuously The faithful transmission of the data 15 verified by the waveform displayed
57. disables interrupts and provides INTA signal The device should sense this signal Generally the device sends the code of RSTn instruction or the code of CALL instruction which provides a chance to user to have his own address e g CALL user address in response to INTA The RSTn code would provide vector address where as CALL code needs user s supplied address When the device generates code for CALL instruction the 8085A provides two more INTA pulses cycles In response to these two cycles the device has to provide 2 byte address of the service routine In this paper through a given circuit simple way is provided to generate address of service routine o PRIORITY AND MASKING In 8085 the default priority of interrupts are as follows TRAP RST 7 5 RST 6 5 RST 5 5 INTR This means TRAP assumes highest priority and INTR assumes lowest priority Masking is a facility by which one can avoid the interrupts i e even if interrupts take place they are not recognized if they are masked In 8085A masking be performed on RST 7 5 RST 6 5 and RST 5 5 only TRAP 15 non maskable For masking a special instruction SIM 15 to be executed o ENABLING AND DISABLING INTERRUPTS In order to get the interrupts serviced i e to make pc to point to vector addresses for valid interrupts they are to be enabled This condition of enabling 1s applicable to RST 7 5 RST 6 5 RST 5 5 and INTR The TRAP is not conditioned to ena
58. error detection sets the corresponding status bit The framing Error status bit 1s set 1f the Stop bit 15 absent at the end of the data byte asynchronous mode RxRDY Receiver Ready This output indicates that the 8251A contains a character that is ready to be input to the CPU RxRDY be connected to the interrupt structure of the CPU or for polled operation the CPU can check the condition of RxRDY using a Status Read operation RxEnable when off holds RxRDY in the Reset Condition For Asynchronous mode to set RxRDY the Receiver must be enabled to sense a Start bit and a complete charater must be assembled and transferred to the Data Output Register For Synchronous mode to set RxRDY the Receiver must be enabled and a character must finish assembly and be transferred to the Data Output Register Failure to read the receiver character from the Rx Data Output Register prior to the assembly of the next Rx Data character will set overrun condition error and the previous character will be written over and lost If the Rx Data 16 being read by the CPU when the internal transfer 15 occurring overrun error will be set and the old character will be lost 34 RxC Receiver Clock The receiver Clock controls the rate at which the character 15 to be received In the Synchronous mode the Baud Rate 1x is equal to the actual frequency of the RxC In Asynchronous mode the Baud Rate is a fraction of the actual RxC frequency A portion o
59. experiment Set these switches in the interface module for following states We have done this because we want to use CALL instruction in response to INTR SW14 SWI3 SWI2 SWII SWIO SW9 SWS SW 1 1 0 0 1 1 0 1 These settings of switches will input data to 741 5245 On occurring of INTR the first INTA low pulse will occur We connected this INTA with G Pin 19 of 7ALS245 Hence INTA will enable 74LS245 to put data CD on data lines of microprocessor kit This data is code of CALL instruction On interpretation the microprocessor will generate two more INTA pulses This will enable 7415245 two more times to output data CD and CD This will in effect becomes equivalent to provide instruction 108 CALL CDCD At address CDCD store the codes of instruction JMP 8800 and store the codes of following program at 8800 onward MVIA 30H 8800 3E 30 MVI B 30H 9802 06 30 ADD B 9804 90 STA 8400H 9805 32 00 84 RST 3 9808 DF Thus when INTR occurs the service routine at 8800H will be executed giving result at 3400 o PROCEDURE First connect interfacing module with kit using information supplied in Tables Now execute program from location 8000 to enable all interrupts Now to generate any interrupt press any key from SW1 to SW5 The service routine of the respective interrupt will get executed and result will be available at respective memory location Following Table 6 8 guides for the same SWITCH I
60. for generating 192 different characters These are fixed in ROM and can not be altered The CGRAM stores segment patterns for up to 16 user 142 designed characters such as logos special symbols or other simple graphics characters that we design on the 5x8 matrix To create a custom character we write a series of 5 bit words to the CGRAM Each word represents the segment pattern for one row in the desired character The patterns stored in CGRAM disappear on powering down so we must reload them on each time we power up Each character in the CGROM and has an 8 bit address or character code Conveniently the codes for the upper and lower case Roman alphabet and common punctuation are same as the ASCII codes for those characters 21h through 7dh For example the pattern for A 1s stored at address 41h B is stored at 42h and so on An 8 bit instruction register IR stores instruction code and addresses and an 8 bit data register DR stores character codes When we read or write to the chip we must select the appropriate register The DDRAM stores up to eighty 8 bit character codes each character position on the display corresponds to an address in the DDRAM and the character codes stored in the DDRAM determine what 1s displayed at each position Display position DDRAM address is shown below in Table 9 3 for the LCD module 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OOh Oth 02h 03h 04h 05h 06h 07h 40h 41h 42h 43h 44h 45h 46h 47h
61. in microprocessor kit communication through 8251A can be done with the help of TxD RxD and modem control signals For serial communication a well known standard RS 232 is used Figure 4 7 shows how one can interface 8251A with outside world following RS 232 standard From 8253 To RS 232 connector To RS 232 connector microprocessor RESET RxRDY CLK WR CS To RS 232 connector To RS 232 connector To RS 232 connector To RS 232 connector FIGURE 4 7 HARDWARE DETAILS OF MICROPROCESSOR KIT SHOWING 8251A AND RS 232 INTERFACING At this stage it is necessary to know what are the specifications of RS 232 standards One should note that RS 232 was developed particularly for the communication between terminal and modem It is also interesting to note that RS 232 standard was developed before the existence of TTL logic Hence to establish serial communication among two devices which use ICs following TTL logic require translator levels which takes care of the differences of RS 232 voltage level and TTL voltage level 5 232 Figure 4 8 shows 5 232 25 connector and its signals The signals divided into four groups data signals control signals timing signals and grounds For data lines the voltage level from 3 V to 15 V 15 defined as logic 0 and from 3 V to 15 Vas logic 1 normally voltage levels are 12
62. in order to use with the target We have considered ESA 85 microprocessor kit as a target here We use ICE to test the memory and I O section of the given kit o Experimental o Hardware installation of ICE PC based ICEs are supplied with one PC adapter card main control unit and target adapter The PC adapter card fits Into the free slot of motherboard of a PC Then main unit is connected with this adapter card through 1 to 1 cable The adapter has some DIP switches By setting them on or off one can select desired I O address for ICE 169 The target adapter fits Into the target The target can be a system being developed or a microprocessor kit Remove the 8085 of the target and insert this adapter o Software installation of ICE PCICE 15 equipped with its own software Load the software properly in your PC For Electro System Associates made PCICE this file is PCICE EXE Now switch on the power supply of ICE and turn on computer Run PCICE EXE If installation Is proper a prompt with gt sign will appear in ESA PCICE Now we want to know how to use PCICE For this we will consider a working microprocessor kit We have used ESAS5 2 kit of Electro System Associates Bangalore Remove the 8085A Processor from the Kit and fix the target adapter in its place The other end of target adapter fits into the main unit of PCICE Testing a microprocessor Kit We have considered the microprocessor kit as o
63. is continuously high until the CPU sends its first character to the 8251A which usually is a SYNC character When the CTS line goes low the first character is serially transmitted out All characters are shifted out on the falling edge of TxC Data is shifted out at the same rate as the TxC Once transmission has started the data stream at the TxD output must continue at the TxC rate If the CPU does not provide the 8251A with a data character before the 8251A Transmitter Buffers become empty The SYNC characters or character if in single SYNC character mode will be automatically inserted the TxD data stream In this case the TxEMPTY pin is raised high to signal that the 8251A is empty and SYNC characters are bing sent out does not go low when SYNC is being shifted out The TxEMPTY pin is internally reset by a data character being written into the 8251A Below Figure 2 16 shows Mode instruction format for Synchronous Mode De Ds D4 D2 D4 Do EP L2 CHARACTER LENGTH 1 o o 1 5 BITS 6 BITS PARITY ENABLE 1 ENABLE 0 DISABLE gt EVEN PARITY GENERATION CHECK 1 ENABLE O DISABLE EXTERNAL SYNC DETECT 1 SYNDET IS AN INPUT O SYNDET IS AN OUTPUT SINGLE CHARACTER SYNC 1 SINGLE SYNC CHARACTER O DOUBLE SYNC CHARACTER FIGURE 2 16 SYNCHRONOUS MODE INSTRUCTION FORMAT
64. kit As i FIGURE 10 3 PHOTOGRAPH OF THE EXPERIMENATAL SETUP o EXPERIMENTAL The experimental setup for using logic analyzer includes a PC data capture unit of logic analyzer pods parallel port cable and a target unit 1 e hardware device under test We will take microprocessor trainer kit as target system It is assumed that you have loaded proper software of logic analyzer in the computer 163 For hardware connections we will connect pods with microprocessor kit and pod connector of data capture unit Each pin of this connector 15 called channel Each pin will be given number from 1 onwards on data capture unit Now one has to decide which signal of kit 1s to be connected with particular channel of the connector of capture unit Let us take the case of program that we have discussed Figure 10 2 which shows timing waveforms of these program instructions contains 22 signals of 8085 CLK 1 address lines 16 ALE 1 RD 1 status lines 3 To understand the timing waveforms of present program we may have to connect those 22 signals with channels The logic analyzer under consideration has total 24 channels You can connect two more signals of 8085 of your choice e g WR and READY they are optional Table 10 1 guides you how to connect pods After connecting pods turn on the PC and run the software of logic analyzer The starting screen will be different depending on the type of logic analyzer You may have
65. memory This pin is also the program pulse input PROG during flash programming PSEN Pin no 29 Program store enable is read strobe to external program memory When the 89C51 is executing code from external program memory PSEN activations are skipped during each access to external data memory 50 Pin 31 External Access Enable EA must strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH EA should be connected to Vcc for internal program execution This pin also receives the 12v programming enable voltage Vpp during programming for parts that require 12 volt Vpp Port 0 Pin no 39 to 32 Port 0 is 8 bit open drain Bi Directional I O port As an output port each pin sink eight TTL inputs When 175 are written to port 0 pins the pins can be used as high impedance inputs It can also be configured to be the multiplexed low order address data bus during accesses to external program and data memory In this mode PO has internal pull ups It also receives the code bytes during flash programming and outputs the code bytes during program verification External pull ups are required during program verification Port 1 Pin no 01 to 08 Port 1 is an 8 bit bi directional I O port with internal pull ups The port 1 output buffers can sink source four TTL inputs When 1 s are written to port 1 pin they are pulled high by the intern
66. one that transmits the data The program remains the same 78 MASTER PROGRAM Mnemonics Memory address Machine codes MVI A 00H 8000 3E 00 OUT 21H 8002 D3 21 OUT 21H 8004 D3 21 OUT 21H 8006 D3 21 MVIA 40H 8008 3E 40 OUT 21H 800A D3 21 MVI A FE 800C 3E FE OUT 21H 800E D3 21 MVI A 25H 8010 3E 25 OUT 21H 8012 D3 21 MVI B 09H 8014 06 09 LXI H 8100H 8016 21 00 81 EMPTY IN 21H 8019 DB 21 ANI OIH 801B E6 01 JZ EMPTY 801D CA 1A 80 MOV A M 8020 7E OUT 20H 8021 D3 20 INX H 8023 23 DCR B 8024 05 JNZ EMPTY 8025 C2 19 80 MVI A 35H OUT 21H MVI B 09H LXI H 8200H IN 21H ANI 02H JZ WAIT IN 20H MOV M A INX H DCR B JNZ WAIT RST 3 WAIT 8028 802A 802C 802E 8031 8033 8035 8038 803A 803B 803C 803D 8040 3E 35 D3 21 06 09 21 00 82 DB 21 E6 02 CA 31 80 DB 20 T4 25 05 C2 31 80 DF Data to be transmitted are stored at 8100H and received data are stored at 8200H SLAVE PROGRAM Mnemonics MVI A 00H OUT 21H OUT 21H OUT 21H MVI A 40H OUT 21H MVI A FE OUT 21H MVI A 35H OUT 21H MVI B 09H LXI H 8200H IN 21H ANI 02H JZ W AIT IN 20H WAIT Memory address 79 8000 8002 8004 8006 8008 800A 800C 800E 8010 8012 8014 8016 8019 90 901 8020 Machine codes 3E 00 D3 21 D3 21 D3 21 3E 40 D3 21 3E FE D3 21 3E 35 D3 21 06 09 21 00 82 DB 21 E6 02 CA 19 80 DB 20 9022 77 INX
67. or reset using a single Output instruction This feature reduce software requirement in control based application When Port 15 being used as status control for Port A or B these bits can be set or reset by using the Bit Set Reset operation just as if they were output ports Figure 2 5 shows Bit Set Reset format for port C CONTROL WORD BIT SET RESET L d 1 SET 0 RESET Don t Care BIT SET RESET FLAG 0 ACTIVE FIGURE 2 6 Bit Set Rest Format e Interrupt Control Functions When 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset of port C This function allows the programmer to enable or disable a CPU interrupt by a specific I O device without affecting any other device in the interrupt structure 19 INTE Flip Flop Definition BIT SET INTE 15 Set Interrupt Enable BIT RESET INTE Is Reset Interrupt Disable Operating Modes e Mode 0 basic Input Output This functional configuration provides simple input and output operations for each of the three ports No handshaking is required data 15 simply written to or read from specific port Mode 0 Basic Functional Definitions Two 8 bit ports and two 4 bit ports Any port can be input or ou
68. program More than 2ms delay Return to main program More than 2s delay Return to main program End of Program Program given here will Display Dr K P JOSHIPURA first and then it is cleared to display VICE CHANCELLOR and keeps on displaying these two words one by one continuously 153 SECTION 4 DEVELOPMENT TOOLS 10 ADVANCE EXPERIMENTS ON LOGIC ANALYZER I j 1 jf l Pf l Pp dd 44 154 10 1 INTRODUCTION The logic analyzer 15 an instrument which provides the analysis of the logical states of digital signals with respect to time Here a logical state means the HIGH or LOW conditions of the digital signals with respect to time In digital circuits particularly microprocessor based circuits it Is very important to know the timing relation of various signals Such information of timing relation provides the ways to determines whether the system under test Is working properly or not Conventional tools like oscilloscope is not useful to correlate the timings of digital signals because it has limited capacity to catch the number of signals and low operating frequency Generally in complex digital circuit e g microprocessor system there is usually eight or more number of signals to be analyzed So for such systems logic analyzer 15 the proper tool It 15 also known as Hardware debugging tool PRINCIPLE OF WORKING Basically lo
69. qe m spes m eem m emm eT PT PPP PTT PT Pp pT PT p h fo pe x xxx III TABLE 10 2 COMPARISON OF PREDICTED SIGNAL WAVEFORM WITH SIGNALS WAVEFORMS CAPTURED BY LOGIC ANALYZER 167 11 ADVANCE EXPERIMENTS ON PCICE d d d d 4 d d 4d d d 4 i 168 11 1 INTRODUCTION Emulation means attempting to be equal In our context the emulation is aimed at making a target microprocessor system equal in performance to a developed and working system Here In circuit means within the target system circuit and Emulator means a tool or device which helps to develop a target into working microprocessor system Basically ICE can do the following 1 Read or write memory locations or Input Output I O ports of target 2 Display CPU registers 3 Change CPU status 4 Map selectively memory or I O ports of the target system into resources of the development system 5 Execute software on the target with single step or trace facility Now a days PC based ICEs are very popular Hence we will consider one such ICE made by Electro System Associate Bangalore 112 USING ICE IN THE LABORATORY In Circuit Emulator provides the probing without affecting the circuit function so it becomes very useful experiment in the laboratory The installation of ICE is necessary to understand
70. regardless of the number of stop bit programmed This character is then loaded into the parallel I O buffer of the 8251A The RxRDY pin 15 raised to signal the CPU that a character 15 ready to be fetched If a previous character has not been fetched by the CPU the present character replaces it in the I O buffer and the OVERRUN Error flag 15 raised thus the previous character 15 lost of the error flags can be reset by an Error Reset instruction The occurrence of any of these errors will not affect the operation of the 8251A Below figure 2 15 shows Asynchronous Mode transmission and receiver format TRANSMITTER OUTPUT TRANSMISSION FORMAT Generatec by 8251 CPU BYTE 2 8 BIT CHAR Dc D1 Dx DATA CHARACTER ASSEMBLED SERIAL DATA OUTPUT TxE STOP BITS START DATACHARACTER STOP BITS RECEIVE FORMAT SERIAL DATA INPUT RxD RECEIVER INPUT Does Not Appear Dc Dx onthe Data Bus CPU BYTE 5 8 CHAR START RxD BIT DATA BITS PARITY BIT MARKING STOP If Character Length Pu is Defined as 5 6 or 7 Programmed bits the unused bits Character Length are set to 0 FIRGURE 2 15 ASYNCHRONOUS MODE TRANSMITER AND RECEIVER FORMAT 39 AUTOMATICALLY INSERTED BY USART Falls upon CPU writing a character to the USART TxEMPTY y D7 Synchronous Mode Transmission The TxD output
71. routine RS 38H EN DELAY EN WAIT LCD RS DATAI 0EH EN DELAY EN WAIT_LCD RS 06H EN DELAY EN WAIT LCD Clear LCD sub routine RS 122 MOV SETB LCALL CLR LCALL RET WRITE TEXT WAIT LCD LOOP HERE2 DELAY SETB MOV SETB LCALL CLR LCALL RET MOV MOV CLR CLR SETB MOV SETB MOV JB NOP NOP DJNZ DJNZ CLR CLR LCALL RET MOV DATAI 01H EN DELAY EN WAIT LCD Data write LCD sub routine RS DATAI A EN DELAY EN WAIT LCD LCD delay sub routine R2 03H amp 0FFH EN RS RW OFFH EN A DATAI ACC 7 HERE2 R3 HERE2 R2 LOOP EN RW DELAY Delay sub routine for keyboard R2 37 123 AGAIN MOV R3 255 HERE1 NOP NOP DJNZ R3 1 DJNZ R2 AGAIN RET ORG 900H Look up table for key code CODE1 DB 4 3955 759 CODE2 DB 254 6 8 0 CODE3 DB CODE4 DB B D F H J CODES DB K Q S CODES DB L N P R T CODE7 DB 0 amp CODES DB IONS END e SOFTWARE EXPLANATION Software provides LCD initialization and data write function for the LCD module LCD is cleared and message PRESS ANY KEY is displayed on the LCD module After that the program for detection and identification of key activation 1s started PO and P2 are initialized as output and input respectively The major stages of the program
72. test for proper functioning is called TARGET First of all decide which are the signals which you want to study for proper functioning of the circuit The circuit may be microprocessor based system Now associate these signals with the numbers of the channels of logic analyzer by noting the names of the signals with number of the channel pins of capture unit Consider the following case where some address lines data lines and control signals of microprocessor circuit are shown associated with pins channels of the capture unit capture unit capture unit ADDR2 3 DATA6 ww DATA3 12 X TABLE 10 1 ASSOCIATED WITH PINS CHANNELS OF THE CAPTURE UNIT In above Table 10 1 24 channel logic analyzer 1s considered 22 channels are used one can associate any signal with any pin of the capture unit Now with such note physically connect the signals using pods with the pins of capture unit one by one After this connect the other connector with the parallel 157 port of pc through a cable e g LPTI At this stage we would assume that we want to test the proper working of a microprocessor training kit So now turn on the power of the kit Load a small program Note that you must have thorough idea of how each instruction of this program 15 being executed through the hardware of microprocessor kit This will help to analyze the signals captured by logic analyzer 2 CONFIGURING THE ANALYZER Configuring the analyzer
73. the control word is read bit D7 will always be a logic 1 as this implies control word mode information 15 CONTROL WORD Group B PORT C LOWER 1 INPUT 0 OUTPUT PORT B 1 INPUT 0 OUTPUT MODE SELECTION 1 0 0 MODE 1 PORT C UPPER 1 INPUT 0 OUTPUT PORT A 1 INPUT 0 OUTP MODE Le STON 00 MODE 0 01 MODE 1 1X MODE 2 MODE SET FLAG 1 ACTIVE FIGURE 2 3 Mode definition format for 82C55A INPUT OPERATION READ PORT gt Data bus PORT B gt Data bus PORT C gt Data bus Control word gt Data bus OUTPUT OPERATION WRITE Data bus Port A Data bus port B Data bus port C Data bus Z Control word DISABLE FUNCTION Data bus gt Three state NE EDEA Data bus gt Three state Table 2 1 82C55A BASIC OPERATION EE 16 MASTER RESET OR MODE CHANGE INTERNAL DATA INTERNAL DATA OUT LATCHED Ports A and C The 82C55A contains three 8 bit ports A B and C All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A INPUT MODE RESET OR MODE CHANGE EXTERNAL EXTERNAL PORT A PIN INTERNAL DATA IN PORTB C PIN INTERNAL DATA OUT LATCHED OUTPUT MODE OUTPUT MODE FIGURE 2 4 A PORT A BUS HOLD CONFIGURATION FIGURE 2 4 B PO
74. the file name 8255 SW ASM Now to assemble the machine codes of this program use 8085 assembler For this you must have stored 8085 Micro Assembler in your computer For this assembler type the following command CAPCICENX8085VX8085 EXE Note that we have stored X8085 EXE in the directory named X8085 as per above path This will present following display 8085 Macro Assembler Version 4 01A copyright C 1985 by 2500 A D Software Inc Listing Destination N T D E L P CR N The Listing Destination asks to indicate the choice where the assembled codes can be listed Here N No Output 182 T Terminal Output D Disk Output E Error only Output List on off listing P Printer Output If one selects N the assembler will assemble the codes but it will not show listing anywhere The selection of T would display assembled codes and program instruction on the monitor screen The D will ask for need to generate cross references It will not show listing on the screen but OBJ file will be created The selection of E will indicate the errors which may take place during assembly L will provide options like T D and P where user wants to listing P will print the codes We select D On hitting enter key the following line 1s displayed Generate cross reference Y N cr N We go for Y On selecting Y the following line is displayed Input Filename Provide proper pathname f
75. through control word register The selection of the Ports and control word registers is done by pins Ao and 8255 can be used in three different modes mode 0 mode 1 amp mode 2 Since mode 0 is very simple we will not consider in present paper e MODE 1 This mode is known as STROBED I O MODE The data transfer takes place under the control of HANDSHAKING signals Port amp B works as I O Ports amp Port C provides handshaking signals Mode 1 can be divided into I P amp O P modes Figure 5 1 illustrates both of these modes 92 MODE 1 PORT AJ CONTROL WORD 07 De 05 D4 03 02 D D7 De 05 D4 D3 D2 Di Do DD FIGURE 5 1 A Mode 1 Strobed Input definitions 93 MODE PORTA CONTROL WORD D7 D D5 D4 D3 D2 Di Do 45 1 INPUT 0 OUTPUT CONTROL WORD D7 D 05 D4 D3 D2 D1 Do KX FIGURE 5 1 B Mode 1 Strobed Output definitions The handshaking signals are as follows 1 STB STROBE INPUT A low on this Input loads data into the input latch 2 IBF Input Buffer Full Flip Flop A high on the Output indicates that data has been loaded into the latch 1 e an acknowledgement IFB is set by STB input being low and is reset by the rising edge of the RD input 3 OBF Output Buffer Full Flip Flop The OBF output will go low to indicate that the CPU has written data out to the specified Port The OBF flip flop will be set by the rising edge of the
76. to set the following CLOCK Select the clock source i e internal from logic analyzer or external from target system We select external clock If you select internal clock then you may have to specify clock speed DISPLAY You have to specify one of the following 1 Timing waveform 2 State list 3 Mixed mode For present case choose Timing waveform TRIGGER The technique of starting the analyzer to collect or acquire data at a specific point 1s called trigger Word recognition 15 one of the ways for triggering logic analyzer One can select the specific condition of signals to take place and at that point trigger the logic analyzer For example in our program the first instruction is NOP stored at 4000h location If you want to start the logic analyzer at the beginning of execution of this instruction the logic states of the signals are as follows CHANNEL SIGNALS STATUS CHANNEL SIGNALS STATUS CHo CLK LOW CH AD LOW CH A15 LOW LOW A14 HIGH AD LOW 164 A13 LOW CHis AD LOW CH LOW ADo LOW CH Au LOW ALE HIGH A10 LOW CHis RD HIGH CH Ao LOW WR HIGH Ag LOW IO sr LOW AD LOW S HIGH CHio LOW ADs LOW CH READY HIGH CH is considered LSB and CH is considered MSB of the 24 bit trigger Word So our trigger word becomes CH CH CH
77. verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent Tl deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is gran
78. 0 4 These positions are the various location number of 2K buffer memory Also note that B T 000018000ns is also displayed at top right corner This is the 165 difference of positions of cursor B and T in memory location i e B T 900 000 900 converted into time scale of nanoseconds Each clock pulse is of 20ns The data of 900 pulses are stored in 900 location rate 50 MHz So B T 900 X 20ns 18000ns With arrow keys of ASCII keyboard you can move cursor left or right Utility Exit Help INTERNAL Bi Trigger x1101110 OO0000100 Z 28 Bi Search XXXXXxXxXX 1 Tri Logic TRUE n uodoOgGg69uUn B 000004200n s Uolti 01 500U 9 138 M1 2 lt M1 gt 2 18 amp Move TRIGGER M3 d o i FIGURE 10 4 THE DISPLAY OF LOGIC STATE OF THREE INSTRUCTION PROGRAM OBTAINED LOGIC STATE ANALYZER LA2124 From above discussion the important information for us 1s that from location zero whatever signals we wanted to capture are displayed at the time of triggering event taking place So all waveforms from extreme left of them start showing logic states starting at location zero You can easily match the data of logic analyzer with our theoretical prediction of waveforms At extreme top right number X1101110 00000000 000000100 15 the trigger word that we have framed In this number X 15 there b
79. 22 2E5 ENONLIN 25 40 POLY 2 305 00 0 1 0 1 5 1 2 1 7 E2 10 12 POLY 500 0 1 0 1 5 1 2 1 7 Voltage Controlled current source The symbolic representation of this source is shown in Figure 12 7 b The linear form 15 G G name N N NC NC lt transconductance value Where N N NC and NC are positive and negative nodes of the respective controlling voltage G name N N POLY value lt lt controlling node controlling node gt gt pairs 4 polynomial coefficients values Some typical statement for Voltage Controlled Voltage sources GAB 124610 GVOLT 4 7 20 22 2E5 GNONLIN 25 40 POLY 2 30500 0 1 0 1 5 1 2 1 7 G2 10 12 POLY 500 0 1 0 1 5 1 2 1 7 Current Controlled current source The symbolic representation of this source is shown in Figure 12 7 C Its linear form 15 F General statement for this is F name N N VN current gain value Where N N are positive and negative nodes of the respective current sources VN is voltage source through which controlling current flows The controlling current is assumed that it flows from positive node to negative node Voltage source VN monitors the controlling current must be an independent voltage source which value could be zero or infinite The nonlinear statement is shown below F name N N POLY value VNI VN2 VN3 polynomial coefficients values gt Current Controlled voltage source The symbolic rep
80. 27 000 DEG C Sk sk sk se ok ok ok ok ok ok ok ok ok k k k k k k k k k k ole k k k k k k Node Voltage Node Voltage Node Voltage Node Voltage 3 2960 4 12 1520 5 5864 6 12 1520 7 15 0000 XQI 1 5960 XQI1 2 5952 XQI 3 5867 1 4 12 1500 VOLTAGE SOURCE CURRENTS NAME CURRENT VCC 5 912 04 2 848 04 XQI VI 8 456 06 TOTAL POWER DISSIPATION 8 87 03 WATTS DC SENSITIVITY ANALYSIS TEMPERATURE 27 000 DEG C DC SENSITIVITIES OF OUTPUT I VRC ELEMENT ELEMENT ELEMENT NORMALIZED NAME VALUE SENSITIVITY SENSITIVITY AMPS UNIT AMPS PERCENT RI 4 700E 04 5 48 09 2 576 06 R2 2 000 E403 1 252E 07 2 505E 06 RC 1 000 04 3 134 10 3 134 08 2 000 03 1 288 07 2 576 06 XQI RB 1 000 02 3 705 09 3 705 09 XQI RE 1 000 00 1 288 07 1 288 09 XQI RC 1 000 01 3 134 10 3 134 11 XQI RBE 1 000 03 3 705 09 3 705 08 XQI RO 1 000 05 1 273 10 1 273 07 1 500 01 1 898 05 2 848 06 0 000 00 1 101 06 0 000 00 XQI VI 0 000 00 4 38 04 0 000 00 JOB CONCLUDED TOTAL JOB TIME 2 A Zener voltage regulator is shown in figure 12 17 Plot the dc transfer characteristic if the input voltage is varied from 15V to 15V with an increment 0 5V The Zener voltage of the diodes are the same and V 5 2 V the current at the Zener breakdown is L 0 5 uA The model parameter are IS 0 5UA RS 1 BV 5 20 and IBV 0 5UA
81. 50 RC 10 TF 0 12NS TR 5NS CJE 0 4PF PE 0 8 ME 0 4 CJC 0 5PF PC 0 8 MC 0 333 CCS 1PF VA 50 TRAN 0 01 4 PROBE END El e Edit View Simulation Trace Plot Tools Window lp co p kd amp amp EX1241 amp Q iiia P525 RP 5 of Fil Q 44 dsl i Example 12 1 Emitter Coupled Trigger Circuit xi K Analysis Watch Devices 1 1 FIGURE 12 20 OUTPUT WAVEFORM FOR EMITTER COUPLED SCHMITT TRIGGER CIRCUIT 242 12 3 2 DIGITAL EXPERIMENTS For digital devices certain models are created in Pspice They are nothing but the software representation of basic building blocks of digital primitives Using such models from the Pspice library we have tested following digital circuit EXAMPLE 1 A 3 to 8 line decoder circuit is shown in Figure 12 21 It consists of AND and OR gate The digital input is shown in Figure 12 22 Simulate circuit using OrCad Capture CIS Plot output for one any condition of truth table FIGURE 12 21 A 3 TO 8 LINE DECODER CIRCUIT Decoder is a combinational circuit that converts binary information from n input lines to maximum 2 unique output lines Here we have considered the 3 to 8 line decoder circuit of Figure 12 21 The three inputs are decoded into eight outputs each output representing one of the minterms of the 3 input variables The three inverters provide the complement of the inputs and each one of the eight AND gates generate one of the minterms The
82. 69 8E 18 VOLTAGE SOURCE CURRENTS NAME CURRENT 3 155 30 X X2 X1 Vlak 2 663E 24 X X2 Xl VdVdt 0 000E 00 X_X2 X1 VIgf 4 431 20 X_X1 x1 x1 x1 xl vmon 1 280 22 X_X1 x1 x1 x1 x1 v0c 9 249 29 X_X1 x1 x1 x1 x1 xcl vsense 0 000E4 00 X Xl xl xl xl xl xrbl vsense 1 076 19 X Xl xl xl xl xl xrb2 vsense 1 075 19 TOTAL POWER DISSIPATION 0 00 00 WATTS JOB CONCLUDED TOTAL JOB TIME 1 36 On reading circuit file you can find few things It 15 showing local global libraries as we have used STMLIB stim230ac stl as local library for stimulus and lib nom lib as a global library Then you can see Analysis directives for analysis type and output probing In simulation circuit file you can see INCLUDE file Diode Voltage Controlled Switch MODEL PARAMETERS NODE VOLTAGES and VOLTAGE SOURCE CURRENTS At the end of simulation you can find total power dissipation and total job time taken by simulator and output waveform as shown in Figure 12 12 215 3 A filter circuit is shown in Figure 12 14 Plot the frequency response of the output voltage The frequency is varied from 10Hz to 100M Hz with an increment of 1 decade and 10 point per decade FIGURE 12 14 A FILTER CIRCUIT TEXT FILE VINIOACI RI 1220K R2 2 4 20K R3 3 0 10K R415 10K R545 10K R667 100K RL 7 0 100K C1 24 0 01UF XAI 2340 OPAMP XA2 567 0 OPAMP SUBCKT OPAMP 1274 RI 1 2 2 0E6 GB43120 1M R234 10K C234 15619UF EA 453 4
83. 8004 C3 00 80 The data OF in A before the execution of SIM instruction masks interrupts RST 7 5 RST 6 5 and RST 5 5 Now execute main program stored at 8000H Press SW6 to generate all interrupts simultaneously This would allow RST 7 5 to be serviced first as it is having highest priority since TRAP is not connected But instead INTR will be serviced because RST 7 5 RST 6 5 and RST 5 5 are masked in main program Verify by examining location 8400 One can set proper masking in SIM and verify the masking for further combinations of interrupts RST 7 5 RST 6 5 and RST 5 5 110 SECTION 3 EXPERIMENTS ON MICROCONTROLLER 99 51 CHAPTER 7 ADVANCE EXPERIMENTS ON KEYBOARD INTERFACE 4 d d d d d d 4d 4d 4 4 i4 4 i Myriad of microcontroller projects include switches and a combination of switches that we call keypad or keyboard which allows user to control the circuits inside The control might be of any kind It might involve changing of switch position to begin an operation to press a key of option selection or for any assigned operation to be performed related to that key press For small tasks one can use pushbutton toggle or slide switches Many of the large projects might call for a keyboard with an array of switches Keyboards offer more options than individual switches or pushbuttons at lower cost and compact size It 1s the basic input device for any system by which human can easi
84. 8023 23 DCR B 8024 05 JNZ WAIT 9025 2 19 80 MVI 25H 9028 25 OUT 21H 802A D3 21 MVIB 09H 902 06 09 IN 21H 8031 DB 21 ANI 01H 9033 E6 01 JZ EMPTY 8035 CA 31 80 MOV A M 8038 7E OUT 20H 8039 D3 20 INX H 803B 23 DCR B 803C 05 JNZ EMPTY 803D C2 19 80 RST 3 8040 DF Data to be transmitted are stored at 8100H and received data are stored at 8200H The slave program is executed first The data transfer on both kits is verified Data from the location 8100H to 8109H of the master kit is now at 8200H to 8209H on the slave kit Similarly the data at 8100 to 8109H of the slave kit 1s stored in the master kit at memory location 8200H to 8209H 90 5 ADVANCE EXPERIMENTS 8255 did PT di PT P PT PT T T T T 51 ROLL OF 8255 WITH MICROPROCESSOR 8085 The 8255 chip is very widely used chip with the 8085A processor The basic description of 825 is done in earlier chapter 2 Our basic aim is to understand the mode I and II operations of 8255 without involving the extra hardware that is this experiment can be performed within a given microprocessor kit The basics of mode I and mode II are explained in the following topic e BASICS OF 8255 Generally 8255 1s understood by its block diagram which contains A DATA BUS BUFFER R W CONTROL LOGIC THREE PORTS A B amp C AND THEIR CONTROL BLOCKS Each Port consists of 8 bit Each Port can be configured
85. 825 as receiver and transmitter in the same kit Serial communication between two kits Chapter 5 Advance experiments 8255 Roll of 8255 with microprocessor 8085 Mode 1 4 2 5 2 5 5 26 5 5 Port as output port and port B as input Port 1i mod L y 99230 Ee r bx Mode 2 expem nh aur Port as output port and port B as input Chapter 6 Advance experiments on interrupt Roll of hardware and software interrupts with Microprocessor 8089 4 E ESSET To generate the interrupts as per user s choice and execute IIS SEFVICO TOUN wiv scan vox rr To verify the priorities of Interrupts To understand the masking of interrupts Section 3 EXPERIMENTS ON MICROCONTROLLER 99 51 Chapter 7 Advance experiments on Keyboard interface Basics of keyboard used Interfacing of keyboard with 89 51 Microcontroller Chapter 3 Advance experiments on matrix display Basics display USE scs mo darme sanaw Basic knowledge of 5X7 matrix LED display Running character display interface using 89C51 Chapter 9 Advance experiments on LCD display pasu sss Basics Interfacing of LCD module with micr
86. 88 5 75188 QUADRUPLE LINE DRIVERS SLLS094B SEPTEMBER 1983 REVISED MAY 1995 THERMAL INFORMATIONT MAXIMUM SUPPLY VOLTAGE vs FREE AIR TEMPERATURE RL 2 3 from each output to GND Vcc Maximum Supply Voltage V 0 75 50 25 0 25 50 75 100 125 TA Free Air Temperature Figure 6 T Data for temperatures below 0 C and above 70 are applicable to SN55188 circuit only APPLICATION INFORMATION VCC 12V Vcc 2 12 V Output to RTL 0 7 V to 3 7 V 1 4 SN55188 or SN75188 3V Output to DTL 0 7 V to 5 7 V cu 1 4 SN55188 E a or SN75188 3 Output to HNIL Vcc 0 7 V to 10 V 1 4 SN55188 1 5 75188 E u Diodes placed in series with the Vcc and Vcc leads will Output to MOS protect the SN55188 SN75188 in the fault condition in which 10 Vto 0 V the device outputs are shorted to 15 V and the power supplies 1 4 SN55188 10 ko are at low voltage and provide low impedance paths to ground or SN75188 12 Figure 8 Power Supply Protection to Meet Power Off Fault Conditions of Figure 7 Logic Translator Applications ANSI EIA TIA 232 E 4 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to
87. 89 YzD5 VCC G_DPWR GND G_DGND X U3A 00048 00115 00189 Y D6 VCC G_DPWR GND G_DGND X U3B 00078 00115 00189 Y D7 VCC G_DPWR GND G_DGND X 4 U4A A N00078 00048 VCC G_DPWR GND G_DGND X UAB U4B A N00115 00058 VCC G_DPWR GND G_DGND X_U4C U4C A N00189 00068 VCC G_DPWR GND G_DGND U_Z Z VCC G_DPWR GND G_DGND OUT N00078 U_Y Y VCC G_DPWR GND G_DGND OUT NO00115 UX X VCC G_DPWR GND G_DGND OUTZNO00189 _ D0 D0 _ _ D1 D1 _ _ D2 D2 _ _ D3 D3 _ _ D4 D4 _ _ D5 D5 _ _ D6 D6 _ _ D7 D7 _ _ GNDZGND ENDALIASES RESUMING 3to8line schematic1 3to8line sim cir END IStimulus Get X Digital Y Digital Z Digital Plot Axis Settings Xrange Os 40us AutoUniverse IXminRes Ins YminRes In 227 STIMULUS Z STM 1 1 CLOCKP 1005 505 1 0 08 1 50 0 Repeat Forever 505 505 0 EndRepeat STIMULUS Y STIM 1 1 CLOCKP 10US 5US 00 05 0 5us Repeat Forever 505 0 5us 1 EndRepeat STIMULUS X STIM 1 1 CLOCKP 10US 5US 0 0 0s 0 5us 1 Repeat Forever 505 0 505 1 EndRepeat STIMULUS Z STIM 1 1 CLOCKP 1005 505 10 05 1 505 0 Repeat Forever 505 1 505 0 EndRepeat STIMULUS Y STIM 1 1 CLOCKP 1005 505 00 050 5us 1 Repeat Forever 505 0 505 228 EndRepeat
88. 9 INTERRUPTS SIGNAL CONDITION COMMENTS RST 75 Low to High transitions AL Sensitive RST 6 5 _ o High level sensitive RST 5 5 o High level sensitive ow to high leve TRAP transition and High level TABLE 6 1 SIGNAL CONDITIONS FOR RECOGNITION ON DIFFERENT INTERRUPT PINS OF 8085A o VECTOR ADDRESSES The devices generate Interrupts to have execution of their programs I E execution of their service routines For this the processor should know about the address of the service routine To reduce the hardware for this matter 8085A has ready made addresses for interrupt pins RST 7 5 RST 6 5 RST 5 5 and TRAP This means whichever device generates interrupt on any of these pins the address of the service routine for that device is given by the 8085A In other words the addresses of service routine for respective interrupting pins are pre defined Hence these addresses are called vector addresses Table 6 2 Provides vector addresses of interrupts pins of 8085A Vector address RST 7 5 003C RST 6 5 0034 RST 5 5 002C TRAP 0024 TABLE 6 2 VECTOR ADDRESSES OF INTERRUPTS OF 8085A o SPECIAL CHARACTERISTIC OF INTR The INTR pin 8085A has a special characteristic in terms of providing the address of the service routine of the device connected with it The interrupting device which generates interrupt on pin INTR has to provide the address of its subroutine 100 Whenever interrupt occurs on INTR the 8085A
89. A0 C2 U3 Al C3 U3 A2 C4 U3 A3 C5 U3 A4 DP2 C1 U3 A5 C2 U3 A6 C3 U3 A7 C4 U4 A0 5 04 DP3 C1 U4 A2 C2 U4 A3 C3 U4 A4 C4 U4 A5 C5 U4 A6 TABLE 8 1 CONNECTION DETAILS OF DISPLAY MODULE CONNECTED TO 89 51 MICROCONTROLLER PORTS e CIRCUIT FUNCTION To display character pattern certain data codes must be applied to the buffer IC 74LS245 inputs AO to A7 whose output BO to B7 is connected to 15x7 matrix displays by means of microcontroller port output is used to control the seven rows Port3 and Port4 are used to control the fifteen columns of 15x7 matrix display Figure 5 shows the block diagram of the moving message display 130 P1 0 P1 1 P1 2 Pio P1 4 PRS P1 6 st CO CO CO CO CO n n PALAA FIGURE 8 5 CORRESPONDENCE OF PORTS WITH ROW COLUMN OF 15X7 DISPLAYS Each column can be selected by sending corresponding data to Port3 and Port2 For example to select the first column C01 one has to send 00h to Port3 and 40h to Port2 Table 8 2 shows the column selection code from to C15 COLUMN 0040 O 0 jo 0 0 0 1 0 jo jo fo 0 10 19 19 E 1 o fo 0 jo jo JO 0 0 1 0 0 jo 0 C04 0008H 0 0 jo jo o 0 jo 1 0 jo fo 5 0004 o o 0 0 0 0 jo 0 jo fo 0 1 0 0 C06 0002H 0 jo jo JO 0 jo jo 1 0 7 0001 O jo jo o jo
90. AL DATA INPUT RxE SYNC SYNC CHARZ DATA CHARACTER CPU BYTE 2 2 BIT CHAR DATA CHARACTER FIGURE 2 17 SYNCHRONOUS MODE DATA FORMAT The CPU can command the receiver to enter the HUNT mode if synchronization is lost This will also set all the used character bits in the buffer to a one thus preventing possible false SYNDET caused by data 41 that happens to be in Rx Buffer at ENTER HUNT time Note that the SYNDET FLIP FLOP 15 reset at each Status Read regardless of whether internal or external SYNC has been programmed This does not cause the 9251 to return to the HUNT mode When in SYNC mode but not in HUNT Sync detection 15 still functional but only occurs at the known word boundaries Thus if one Status Read indicates SYNDET and a second Status Read also indicates SYNDET then the programmed SYNDET characters have been received since the previous Status Read When external SYNDET mode is selected internal Sync detect 16 disabled and the SYNDET FLIP FLOP may be set at any bit boundary COMMAND INSTRUCTION DEFINITION Once the function definition of the 8251A has been programmed by the Mode instruction and the Sync characters are loaded 1f 1n Sync mode then the device is ready to be used for data communication The Command instruction controls the actual operation of the selected format Functions such as Enable Transmit Receive Error Reset and Modem Controls are provided by the Command instr
91. CHis CH I I I 0 I I I 0 0 0 0 0 CH CH CH CH CH 0 0 0 0 0 0 0 0 0 I 0 0 Enter this binary data to frame trigger word in logic analyzer Put the trigger cursor at zero buffer location So display will show captured data from very first buffer location when trigger word matches MEMORY This option sets up the buffer memory length used for acquisition Choose proper size There may be few trivial settings We at present don t consider them For better understanding one must refer to manual of one s logic analyzer Now turn on the power of kit Enter the codes from 4000H location onward and run the program Power on the data capture unit Now give command to capture data Within no time captured data will be displayed on monitor screen Fig 10 4 shows the timing waveform for our program o RESULT AND DISCUSSION From Figure 10 4 you will realize that we have named all 24 channels having correspondence with 8085A signals viz CLK Ajs READY Note that READY 158 actually not connected with logic analyzer These channel names are at the extreme left side of the display i e column 1 of display Column number three displays the binary values 1 High or Low of the all signals at the position where cursor is lying At the top right corner you will find three cursors named A B and T A 1s positioned at location 000690 B 1s positioned at 000900 and T 16 at 000000 See Figure 1
92. D RxRDY TxRDY CH 0 9 TxD RESET CLK READ TxRDY WRITE TRANSMIT CONTROL CONTROL TxE TxC RL LOGIC MODEM CONTROL RECEIVE p BUFFER RxD S F RxRDY RxR d RxC SYNDET FIGURE 2 12 PIN DISCRIPTION AND BLOCK DIAGRAM OF 8251 44 dd 30 e Data Bus Buffer This 3 state Bi Directional 8 bit buffer is use to interface the 8251A to the system Data Bus Data is transmitted or received by the buffer upon execution of INput or OUTput instruction of the CPU Control words Command words and Status information are also transmitted through the Data Bus Buffer The Command Status 8 bit registers communicate with the system bus through the Data Bus Buffer This functional block accepts inputs from the system Control bus and generates control signals for overall device operation It contains the Control Word Register and Command Word Register that store the various control formats for the device functional definition e RESET Reset A HIGH on this input forces the 8251A into an Idle mode The device will remain at Idle until a new set of control words 15 written into the 8251A to program its functional definition Minimum RESET pulse width 15 6 tcy clock must be running A command reset operation also puts the device into the Idle state e CLK Clock CLK input is used to generate internal device timing and is normally connected to the Phase 2 TTL output of the Cl
93. DPTR Initially data pointer 15 set to 700h memory location which points to the first row selection data code The display is cleared by providing the opposite logic to Port 1 Port 2 and Port 3 by means of the sub routine CLRDISP For the data write on display module DATANXT sub routine is executed in the program In DATANXT sub routine is used for column selection R3 set to 00h to get 1 code from data pointer address 700h R6 and R7 provides the continuous display for one whole fifteen data write function for certain period of time approx 1 sec Initially the value of R3 00h so when first time the Instruction MOVC A a DPTR is executed the data present at memory location 700h is stored A That is the data for row selection and 15 sent to Port 1 Now the column 15 selected to display the row data So the register R1 1s used to provide the P3 the column selection codes After that rotating the data of by means of accumulator using RL instruction to get the next column selection code Incrementing DPTR provides next row selection codes As the Port 3 eight bits are controlling the eight column selection codes we are comparing the R3 with 08h by means of CJNE R3 08 NXTDATA If is less than 08 the program jump to NXTDATA otherwise step down and execute the next instruction After eight data write column selection Port 2 1s activated to control the next seven column selection codes NXTDATAI is same as NXTDATA the only di
94. E address Last List specifies the data user wants to enter into successive bytes of memory One can do following with this command A Replace the byte Type new value at the current value B Advance to the next byte Press SPACE BAR C Return to the preceding byte Press the HYPHEN Key D Stop E command Press ENTER key Example E 100 This will display like 100 173 One can type new value at or to next location by pressing SPACE BAR or END the EDIT command by pressing ENTER KEY if he is satisfied with the content of location 100 7 Fill F command This command fills specified memory area with specified values DATA Syntax F range list List specifies the data user wants to enter Example F 100 L 100 42 45 52 54 41 Here ICE fills memory location 100 through with value specified ICE repeats the five values until all the 100H bytes are filled 8 Move command Copies the contents of a block of memory to another block of memory Syntax M range address Here address 1s starting address of the destination Example M 100 110 500 9 Memory Map MM command Maps the 8085 processor s memory to onboard RAM i e Emulator s memory or target memory Syntax MM range E W T Here E Map to Emulator memory i e onboard W write protect the emulation memory T Map to target memory Example MM 0 FFF E W In this command ICE will map to locations 0 to FFF in e
95. ECTION NAME STARTING ADDRESS ENDING ADDRESS SIZE 5 8255 SW OBJ x Code 8000 9019 001A OK K K OK K K K K K K K Link Error 0 Output Format Intel Hex Thus linker convert 8255 SW OBJ file into 8255 SW HEX file Now run PCICE Go for the following dialog MM 0000 FFFF T gt EX cr gt ctrl D This will open a check box as follows Interact with 1t as shown below 184 DOWNLOAD DOWNLOAD FILE HEX STARTING ADDRESS END ADDRESS LOAD OFFSET ADDRESS C PCICE 8255_sw HEX lt cr gt this will take address itself 0000 cr This will run the program on target Now one can check waveform on oscilloscope on every pin of 8255 ports 185 J I o4 d od d Y d d d v d v 3 CHAPTER 12 ADVANCE EXPERIMENTS ON PSPICE T PT Pj PT PT T T T 186 12 1 INTRODUCTION The designing of the circuit and its implementation to check whether the designed circuit works properly or not can have two approaches first built the design circuitry on the PCB and test it by giving proper inputs and observing proper output This is a conventional approach where the satisfactory working of the design demands for extreme care The hardware created once needs to be made again if something goes wrong It 15 a general observation in the field that no hardware designed first time would work with a first attempt Hence this first approach takes enough time an
96. F 1 5 213 circuit file for profile Full wave phase controller INITIAL TRANSIENT SOLUTION TEMPERATURE 27 000 DEG C k oko ok ok sk sk sk sk sk sk kso ok ok ok ehe sk sk obe obe obe ok ok ok ok ok ook ak ak ak NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE N00011 865 5E 18 N00014 865 5E 18 N00027 1 738E 15 N00273 704 5E 18 N00352 562 3E 18 N00368 6 330E 18 X X2 X1 Itot 0 0000 X X2 Xl prod 0 0000 X X2 Xl dlayl 4 841E 24 X2 X1 dlay2 68 45E 24 X 2 1 0 0 0000 X X2 Xl dvdtl 0 0000 X X2 Xl dvdt2 0 0000 X 2 1 1 4 115 18 X X2 Xl gate2 0 0000 X X2 Xl gate4 0 0000 X X2 X l anode0 1 721E 15 X X2 Xl anode2 0 0000 X_X2 X1 break1 1 585E 12 X X2 Xl contot 0 0000 X X2 Xl condvdt 0 0000 X X2 Xl congate 0 0000 X X2 Xl conmain 0 0000 X X2 X l control 33 5 1E 18 X_X1 x1 x1 x1 x1 x 469 8E 18 X_X1 x1 x1 x1 x1l ca 1 000E 09 X XI xl xl xl1 x1 cc 92 49E 27 X XI xl xl xl x1 e1 562 3E 18 X_X1 x1 x1 x1 x1 x1 469 8E 18 X XIl xl xl xl x1 mon 0 0000 X_X1 x1 x1 x1 x1 rla 4307 2000 X 107 6 21 X XI xl xl xl1 x1 r2a 2182 8000 214 X XI xl xl xl1l x1 r2c 107 5E 21 X 0 0000 X XI xl xl xl x1 mona 128 0E 24 X XI xlI xl xl xl1 rlaa 4307 2000 X 0 0000 X XI xl xl xl xl xcl 6 0 0000 X XI xl xl xl x1 xrb1 6 6 330E 18 X_X1 x1 x1 x1 x1 xrb2 6 4
97. GND 74511 PARAMS 2275 IO LEVEL 0 MNTYMXDLY 0 X U2A N00078 N00115 NO0068 D3 5 DPWR G DGND 74511 PARAMS IO LEVEL 0 MNTYMXDLY 0 X U2B N00048 N00058 N00189 D4 5 DPWR G DGND 74511 PARAMS IO LEVEL 0 MNTYMXDLY 0 X U2C N00078 00058 N00189 D5 5 DPWR G DGND 74511 PARAMS IO LEVEL 0 MNTYMXDLY 0 X U3A N00048 N00115 N00189 5 DPWR G DGND 74511 PARAMS IO LEVEL 0 MNTYMXDLY 0 X U3B N00078 00115 00189 D7 5 DPWR G DGND 74511 PARAMS IO LEVEL 0 MNTYMXDLY 0 X 4 N00078 00048 G DPWR G DGND 74504 PARAMS IO LEVEL 0 MNTYMXDLY 0 X UAB N00115 N00058 G DPWR G DGND 74504 PARAMS IO LEVEL 0 MNTYMXDLY 0 X N00189 00068 G DPWR G DGND 74504 PARAMS IO LEVEL 0 MNTYMXDLY 0 U_Z STIM 1 0 G DPWR G_DGND N00078 IO STM STIMULUS Z U Y STIM 1 0 G DPWR G DGND N00115 IO STM STIMULUS Y UX STIM 1 0 G DPWR G DGND N00189 IO STM STIMULUS X RESUMING 3to8line schematic1 3to8line sim cir ANC 3to8line SCHEMATIC1 als INCLUDING 3to8line SCHEMATIC1 als ALIASES X UIA U1A A N00048 00058 300068 Y DO VCC G_DPWR GND G_DGND X UIB UIB AzN00078 00058 00068 Y D1 VCC G_DPWR GND G_DGND X UIC 00048 300115 00068 Y D2 VCC G_DPWR GND G_DGND X U2A U2A A N00078 00115 00068 Y D3 VCC G_DPWR GND G_DGND X U2B U2B A N00048 300058 00189 YzD4 VCC G_DPWR GND G_DGND 226 X U2C U2C AzN00078 300058 001
98. L2 2 724000E 09 TSWHL3 2 724000E 09 TSWHL4 2 724000E 09 TSWLHI 2 104000E 09 TSWLH2 2 104000E 09 TSWLH3 2 104000E 09 TSWLH4 2 104000E 09 TPWRT 100 000000E 03 100 000000 03 JOB CONCLUDED TOTAL JOB TIME 05 240 CHAPTER 13 CONCLUSION d d d d d d d 4 4d d 4d 4 In present work the development of experiments based 8085 microprocessor 89 51 microcontroller their interfacing debugging and simulation are concentrated The experiments are framed with necessary theoretical background and study material In Section 1 basics of microprocessor and microcontroller are discussed section 2 contains the experiments on 8085 and interfacing with its peripherals devices Section 3 is completely devoted to experiments on 89C5 Section 4 discusses the Logic analyzer In Circuit Emulator and Pspice All the experiments are well tested and represented with study material These experiments will be help to the students who are desirous to learn themselves In some experiments PCB designing 15 also given It 15 hoped that this work would benefit to the learners 242 Appendix B References BOOKS B 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 B 11 B 12 B 13 A W Moore K E Fronheisher Vinay Khanna John D laune G Sawyer M E Edison T C Daly J F Vittera Motorola semiconductor product Inc Microprocessor applications manual McGraw hill publishing inc N Y A
99. LUTION TEMPERATURE 27 000 DEG C Node Voltage Node Voltage Node Voltage Node Voltage 1 0 0000 2 0 0000 3 27779 4 8 3369 5 2 0189 6 360 0E 09 7 15 0000 8 54 00 09 9 0 0000 10 15 0000 12 0 0000 VOLTAGE SOURCE CURRENTS NAME CURRENT VCC 6 164E 04 VIN 0 000E 00 VX 0 000E 00 TOTAL POWER DISSIPATION 9 25E 03 WATTS 208 2 Design and simulate a Full wave phase controller circuit using OrCad Capture CIS Plot output for 230V amplitude 50Hz frequency input signal For above circuit we have used OrCad Capture CIS to simulate Full wave Phase controller circuit Below Figure 12 10 shows circuit diagram of full wave phase controller V1 D1N4007 D1N4007 D3 04 2N2646 gt gt 2N3669 D1N4007 D1N4007 lt c E 3 100 FIGURE 12 10 FULL WAVE PHASE CONTROLLER CIRCUIT Solution In above circuit we have used THYRISTOR 2N2646 2N3669 and Zener diode 1N4739 and input voltage 1s ac type and fixed frequency We have considered a voltage source with a peak magnitude of 230V 50Hz frequency The input voltage is generated using Pspice Stimulus Editor Figure 12 11 shows input voltage waveform File Edit Stimulus Plot View Tools Window Help i Les p a S E S S q ET AG BG Ja F ah on FIGURE 12 11 INPUT WAVEFORM FOR FULL WAVE PHASE CONTROLLER 209 Now configure OrCad Capture CIS simulation
100. Low Power idle and Power Down Modes It 15 also a low power high performance CMOS 8 bit microcontroller with 4K bytes of flash Programmable and Erasable Read Only Memory PEROM The on chip flash memory allows the program memory to be reprogrammed in system or by a conventional non volatile memory programmer By combining a versatile 8 bit CPU with flash on a monolithic chip the 89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications Figure 3 1 shows the pin configurations of 89C51 microcontroller 49 VCC PO 0 ADO PO AD PO 2 AD2 P0 3 AD3 PO 4 5 ADS PO 6 AD6 PO 7 AD7 RXD P3 0 EA VPP 89 51 ALE PROG P32 PSEN P2 7 A15 P2 6 A14 P2 5 A13 P2 4 A12 P2 3 A11 P2 2 A10 P2 9 P2 0 A8 FIGURE 3 1 PIN CONFIGURATION OF 89C51 MICROCONTROLLER Pin Description VCC Pin no 40 Supply voltage 5V GND Pin no 20 Ground XTALI Pin no 19 Input to the inverting oscillator amplifier and input to the internal clock operating circuit XTAL2 Pin no 18 An output from the inverting oscillator amplifier clock RST Pin no 09 Reset input A high on this pin for two machine cycles while the oscillator is running resets the device ALE PROG Pin no 30 Address Latch Enable output pulse for latching the low byte of the address during accesses to external
101. M 1 1 CLOCKP 1005 5US 0 0 0s 0 5us Repeat Forever 505 0 505 EndRepeat STIMULUS STIM 1 1 CLOCKP 1005 50500 0s 0 5us Repeat Forever 505 0 5us 1 EndRepeat STIMULUS B2 STIM 1 1 CLOCKP 1005 5US 1 0 0s 1 238 5us 0 Repeat Forever 505 Sus 0 EndRepeat STIMULUS STIM 1 1 CLOCKP 1005 5US 00 050 505 Repeat Forever 505 0 505 EndRepeat STIMULUS STIM 1 1 CLOCKP 1005 505 1 0 05 1 505 0 Repeat Forever 505 505 0 EndRepeat STIMULUS S STIM 1 1 CLOCKP 1505 5US 0 0 05 0 1005 1 Repeat Forever 5us 0 1005 EndRepeat circuit file for profile QUAD2TOIMUX Digital Gate MODEL PARAMETERS D_LS32 D LS04 D LSII TPLHMN 5 600000 09 3 600000 09 3 200000 09 TPLHTY 14 000000E 09 9 000000 09 8 000000 09 22 000000 09 15 000000 09 15 000000 09 TPHLMN 5 600000 09 4 000000E 09 4 000000 09 239 TPHLTY 14 000000E 09 10 000000E 09 10 000000E 09 TPHLMX 22 000000 09 15 000000E 09 20 000000E 09 circuit file for profile QUAD2TOIMUX Digital IO MODEL PARAMETERS IO STM IO LS DRVL 0 157 DRVH 0 108 AtoD1 AtoD_LS AtoD2 AtoD LS NX AtoD3 AtoD_LS AtoD4 AtoD LS NX DtoAl STM DtoA LS DtoA2 DtoA_STM DtoA LS DtoA3 DtoA_STM DtoA LS DtoA4 STM DtoA LS TSWHLI 2 724000E 09 TSWH
102. OBF Controlled by bit set reset of PC4 Input Operations STB Strobe input A LOW on this loads data into the input latch IBF Input Buffer Full Flip Flop A HIGH on this output indicates that data has been loaded into the input latch INTE 2 The INTE associated with IBF Controlled by bit set reset of e Special mode combination considerations There several combinations of modes possible For any combination some or all of port C lines are used for control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of port C the state of all the port C lines except the ACK and STB lines will be placed on the data bus In place of the ACK and STB line states flag status will appear on the data bus in the PC2 PC4 and PC6 bit positions as illustrated by Table 2 3 INTERRUPT ALTERNATE PORT C ENABLE FLAG POSITION PIN SIGNAL MODE ACKg Output Mode 1 INTE B PC2 EE or STBg Input Mode 1 INTE A2 STB Input Mode 1 Or Mode 2 Output Mode 1 Or Mode INTE AI PC6 2 TABLE 2 3 INTERRUPT ENABLE FLAGS IN MODE 1 AND MODE 2 Though a Write port C command only the port c pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write port C command nor can the interrupt enable flags be accessed 27 To write to any port C output programmed as an output in Mode 1 group or to
103. READ DATA AT PORT B 8102 12 STAX D STORE TO DESTINATION 8103 13 INX D POINTED TO BY DE 8104 C9 RET AND RETURN TO MAIN PROGRAM In this experiment the hardware detail is shown in Figure 5 7 7 When port A as input port in mode 2 part 2 Connect RST 5 5 to INTRA and connect RST 6 5 with INTRB dotted line connection configuration PB PBO PORT B IN MODE 1 FIGURE 5 7 Port A as Input Port and Port B as Output Port 95 Now to make Port A input in mode 2 and Port B output in mode 1 connect the pins of 8255 as follows PA 9000 8002 8004 8006 8008 800A 800C 900 9010 9011 8014 8017 8018 p PBo PB PB Now enter the following program LOOP PAs PB 5 PA PB PC OBFg 8 ACKg 199 PC IBFA Through Inverter COUNTER CONTROL WORD TO CONFIGURE PORT A IN MODE 2 AND PORT B AS O P IN MODE 1 BSR MODE WORD TO SET INTE BSR MODE WORD TO SET DATA TO ENABLE ALL INTERRUPTS SOURCE POINTER DESTINATION POINTER Enter JMP instruction at addresses FEOC and FE06 as follow 06 11 MVI B 11H 3E D4 MVIA D4H D3 43 OUT 43H 3E 09 MVIA 09H D3 43 OUT 43H 3E 05 MVI A 05H D3 43 OUT 43H 3E 0C MVI A 08H 30 SIM 210084 8400H 110085 LXID 8500H C3 1780 JMP LOOP FEOC JMP
104. RT B AND C BUS HOLD CONFIGURATION FIGURE 2 4 BUS HOLD CONFIGURATION Port A One 8 bit data output latch buffer and one 8 bit data input latch Both pull up and pull down bus hold devices are present on port A Bus hold configuration for port 1s shown in figure 2 4 A Port B One 8 bit data input output latch buffer and one 8 bit data Input buffer Bus hold configuration for port B 1s shown in figure 2 4 B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B Bus hold configuration for port C 1s shown in figure 2 4 B Operational description Mode selection There are three basic modes of operation that can be selected by the system software Mode 0 Basic Input Output Mode 1 Strobed Input Output Mode 2 Bi directional Bus 17 ADDRESS BUS CONTROL BUS DATA BUS AEN 0 21 RE WR 9 PC4 PC7 11 CONTROL OR CONTROL OR O C L I U PB7 PB0 CONTROL PA7 PA0 FIGURE 2 5 BASIC MODE DEFINITIONS AND BUS INTERFACE When the reset Input goes high all ports will be set to the Input mode with all 24 port lines held at a logic one level by Internal bus hold devices After the reset is removed the 82C55A c
105. ST CIRCUIT VOLTAGE WAVEFORMS NOTES A The pulse generator has the following characteristics ty 0 5 us PRR x 1 MHz Zo 50 0 B CI includes probe and jig capacitance Figure 1 Test Circuit and Voltage Waveforms 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 1488 5 55188 5 75188 QUADRUPLE LINE DRIVERS SLLS094B SEPTEMBER 1983 REVISED MAY 1995 TYPICAL CHARACTERISTICST VOLTAGE TRANSFER CHARACTERISTICS Vo Output Voltage V 2 0 02 04 06 08 1 Input Voltage V Figure 2 SHORT CIRCUT OUTPUT CURRENT vs FREE AIR TEMPERATURE los Short Circuit Output Current mA 12 100 75 50 25 0 25 50 75 100 125 150 TA Free Air Temperature C Figure 4 1 2 1 4 1 6 1 8 2 IC lo Output Current mA SR Slew Rate V us OUPUT CURRENT vs OUTPUT VOLTAGE 0 16 12 8 4 0 4 8 12 16 Vo Output Voltage V Figure 3 SLEW RATE vs LOAD CAPACITANCE 1000 oe L l C NJIJ HARRIN 1 00 L I 1 P II I IA 01 1 1 111 a ail H Ej RENS a L ERE 100 1000 10000 CL Load Capacitance pF Figure 5 T Data for temperatures below 0 C and above 70 C are applicable to SN55188 circuit only 4 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1488 5 551
106. TE TEXT A f T WRITE TEXT P2 PO 00H A P2 A 1FH A 1FH AAB1 DELAY A P2 A 1FH A t FH OVER AAB2 A P2 A 1FH A 40FDH A P2 A 1FH A 1FH ROW2 A P2 A 1FH A 1FH 0 7 120 Make P2 input port Ground all rows Read all columns Mask unused bits Check till all keys released Call 20ms delay see if any key 1s pressed Mask unused bits Check for key press Jump to check again Ground row 1 Read all columns Mask unused bits Key in row 1 find column Ground row 2 Read all columns Mask unused bits Key in row 2 find column Ground row 3 Read all columns Mask unused bits Key in row 3 find column Ground row 4 ROWI 2 ROW3 ROW4 ROWS ROW O ROWT MOV ANL CJNE MOV MOV ANL CJNE MOV MOV ANL CJNE MOV MOV ANL CJNE MOV MOV ANL CJNE LJMP MOV LJMP MOV LJMP MOV LJMP MOV LJMP MOV LJMP MOV LJMP MOV LJMP A P2 A A ROWA 40EFH A P2 A A 1FH ROWS 40DFH A P2 A A 1FH ROW6 2 A 1FH A 1FH ROW7 PO 07FH A P2 A 1FH A 1 ROWS AAB2 DPTR CODE1 GET DPTR CODE2 GET DPTR CODE3 GET DPTR CODE4 GET DPTR CODES GET DPTR CODE6 GET DPTR CODE7 GET 121 R
107. TRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 MC1489 MC1489A SN55189 SN55189A SN75189 SN75189A QUADRUPLE LINE RECEIVERS SLLS095D SEPTEMBER 1973 REVISED OCTOBER 1998 electrical characteristics over operating free air temperature range Vcc 5 V 1 unless otherwise noted SNSB MC1489 MC1489A TEST t SN55189A diis PARAMETER FIGURE TEST CONDITIONS SN75189A MIN MAX MIN MAX fee Vim Positive going input Ta 55 C to 125 C 06 19 GR Ta 55 C to 125 C Negative going input threshold voltage Low level Vi 3V lop 10 mA 0 2 0 45 02 045 V output voltage 8 3 High level V 25 3 6 83 36 83 mA Low level Vj 25V 3 6 8 3 3 6 8 3 Short circuit output current Supply current Vi 5V Outputs open 0 m characteristics are measured with the response control terminal open t All typical values are at Vcc 5 V TA 25 VIT switching characteristics Vcc 5 V 15 pF TA 25 TEST Propagation delay time low to high level output Propagation delay time high to low level output Emm s tTLH Transition time low to high level output tTHL Transition time high to low level output 4 TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MC1489 MC1489A SN55189 SN55189A SN75189 SN75189A QUADRUPLE LINE RECEIVERS SLLS095D SEPTEMBER 1973 REVISED OCTOBER 1998
108. TS PIN NO 37 Clock output for use as a system clock when a crystal or R C network is used as an input to the CPU The period of CLK is twice the X input period IO M OUTPUTS PIN NO 34 IO M indicates whether the read write is to memory or I O device 3 stated during HOLD and HALT mode SID INPUTS PIN NO 5 Serial data input line The data on this line 15 loaded into accumulator bit 7 whenever a instruction 15 executed SOD OUTPUTS PIN NO 4 Serial data output line The output SOD 15 set or reset as specified by the SIM Instruction VCC 5 V supply PIN NO 40 VSS Ground reference PIN NO 20 2 5 INPUT OUTPUT DEVICES OF MICROPROCESSOR 8085 8085A processor can be interfaced with various I O devices through their controller peripheral chips We have considered in present work following peripheral chips 1 82C55A PPI Programmable Peripheral Interface 2 8251A USART Universal Synchronous Asynchronous Receiver and Transmitter 2 3 1 82C 55A Programmable Peripheral Interface Figure 2 2 shows Pin diagram and block diagram of 82C55A PPI chip e FUNCTIONAL DESCRIPTION e Data Bus buffer This 3 state bi directional 8 bit buffer is used to interface the 82C55A to the system data bus Data is transmitted or received by the 82C55A Programmable Peripheral Interface PPD INTEL Datasheet 13 buffer upon execution of input or output instructions by the CPU Control words and st
109. The operating temperature is 50 Vin has a normal voltage of 10V dc The details of the operating point are to be printed FIGURE 12 17 ZENER VOLTAGE REGULATOR ZENER DIODE CHARACTERISTICS VIN 1 0 DC 10V RI 1 2 500 D1 23 DNAME D2 0 3 DNAME RL201K model DNAME D IS 0 5UA RS 1 BV 5 IBV 0 5UA TEMP 50 DC VIN 15 15V 0 5V PRINT DC V 2 PROBE END The information about the operating point which is obtained from the output file is as follows OPERATING POINT INFORMATION TEMPERATURE 50 000 DEG C NAME DI D2 MODEL DNAME DNAME Ip ID 3 19 03 3 19 03 220 Vp VD 1 56E 01 5 45 00 Rp REQ 8 69E 00 8 76E 00 Cp CAP 0 00 00 0 00E 00 Simulation Trace Plot Tools Window Help ZENER 49 dal E ZENER act ZENER ZENER DIODE CHARACTER 1 Analysis Watch Devices 1 For Help press Fi FIGURE 12 18 OUTPUT WAVEFORM OF ZENER DIODE CHARACTRISTICS 3 An emitter coupled Schmitt trigger circuit is shown in Figure 12 19 Plot the hysteresis characteristics of the circuit from the results of the transient analysis The input voltage is varied from 1V to 3V and 3V to IV QbreakN7 QbreakN7 FIGURE 12 19 EMITTER COUPLED SCHMITT TRIGGER CIRCUIT 221 EMITTER COUPLED TRIGGER CIRCUIT OPTIONS ACCT VDD 5 0 DC 5 VIN 10 PWL 0 IV 23V 4 1V R1524 9K R2 5 3 3 6K RE401K Q1 214 QM Q2324 QM MODEL QM NPN IS 1E 16 50 BR 0 1 RB
110. UAA X UAB X X UIA USB AzN00348 B N00367 2 VCC G_DPWR DGND U5C A N00351 B N00377 Y Y3 VCC G DPWR DGND USD A N00354 00387 4 VCC G DPWR DGND U4A A N00065 00068 VCC G_DPWR GND G_DGND U4B A N00068 YzN00118 VCC G_DPWR GND G_DGND U4C A N00071 YzN00203 VCC G_DPWR GND G_DGND U1A A N00318 B N00068 C N00203 YzN00342 VCC G_DPWR GND G_DGND X UIB 00321 00068 C N00203 YzN00348 VCC G_DPWR GND G_DGND X U1C A N00324 00068 C N00203 YzN00351 VCC G_DPWR GND G_DGND X U2A U2A A N00327 B N00068 C N00203 YzN00354 VCC G_DPWR GND G_DGND X U2B U2B AzN00330 BzN00118 00203 00357 VCC G_DPWR GND G_DGND X U2C U2C A N00333 BzN00118 00203 YzN00367 VCC G_DPWR GND G_DGND X U3A U3A A N00336 B N00118 00203 00377 VCC G_DPWR GND G_DGND X U3B 00339 BzN00118 00203 YzN00387 VCC G_DPWR GND G_DGND UAI U A2 A3 U 4 U BI U B2 U B3 U B4 5 Al VCC G_DPWR GND G_DGND OUT N00318 A2 VCC G_DPWR GND G_DGND OUT N00321 A3 VCC G_DPWR GND G_DGND OUT N003724 A4 VCC G_DPWR GND G_DGND OUT N00327 B1 VCC G_DPWR GND G_DGND OUTZNO00330 B2 VCC G_DPWR GND G_DGND OUT N00333 B3 VCC G_DPWR GND G_DGND OUT N00336 B4 VCC G_DPWR GND G_DGND OUT N00339 S VCC G_DPWR GND G_DGND OUT N00065 235 ULE E VCC G_DPWR GND G_DGND OUT N00071 _ Y1 Y1
111. URE 1 PIN CONFIGURATION OF 5X7 DISPLAY MODULE RI R2 repeat 22 ZN ZN ZN R3 w Z ZN ZN ZN ZX _ BS R4 mu Z ZN ZX ris R5 m ZN ZN ZN ZX ms 81 R6 EE SE ZN YN ZN ZN ZN R7 Z N ZN ZN Hd Gp C4 C3 C2 Cl FIGURE 8 2 INTERNAL DIAGRAM OF 5X7 DISPLAY MODULE Figure 8 1 describes the pin arrangement of seven rows and five columns Figure 8 2 shows the internal arrangement of LED s in 5x7 matrix One can note that in order to lit any particular LED one has to connect the positive voltage to the corresponding column and ground the corresponding row 82 BASIC KNOWLEDGE OF 5X7 MATRIX LED DISPLAY In this experiment three 5x7 modules are combined resulting in a 15x7 matrix display Thus 89 51 microcontroller controls the seven rows and fifteen columns of the display The corresponding rows and columns of the display are activated under the control of software written for microcontroller to create the effect of moving characters 93 RUNNING CHARACTER DISPLAY INTERFACE USING 89 51 To interface the 89 51 with three 5x7 display modules the IC 741 5245 as buffer drivers 15 used The details of the circuit diagram are shown in Figure 8 3 g rg rg rg rg g g g tO 189 51 dd 55 o2 zl 21 oo
112. UT 21H 8004 D3 21 OUT 21H 8006 D3 21 MVIA 40H 8008 3E 40 OUT 21H 800A D3 21 MVI A CD 800C 3E CD OUT 21H 800E D3 21 MVI A 11H 8010 11 OUT 21H 9012 D3 21 EMPTY IN 21H 8014 DB 21 ANI 01 8016 E6 01 JZ EMPTY 8018 CA 14 80 MVIA AA 801B 3E AA 12 OUT 20H 801D D3 20 JMP EMPTY 801F C3 14 80 In the above program machine codes and memory location where program 15 stored 1s also given by entering program through the keyboard of the microprocessor kit The program 16 executed for data DATA 55H and Pin 19 TxD of 8251A is connected to CRO and the data transmission 15 observed as following Table 4 1 Expected waveform SB Start bit Start bit S1 S2 Two stop bit SB Start bit 51 S2 Two stop bit TABLE 4 1 OBSERVED AND THEORITICAL OUTPUT OF TxD PIN OF 8251A 4 3 8251 AS A RECEIVER AND TRANSMITTER ON THE SAME KIT In this experiment the receiver and transmitter part of 8251A are studied To interface transmitter circuitry and receiver circuitry the kit ESA 85 1s used The basics of receiver transmitter and interfacing circuits are discussed earlier EXPERIMENT II 8251 5 A RECEIVER AND TRANSMITTER ON THE SAME Apparatus 8085A based microprocessor kits a single power supply 5V 12V and CRO Procedure In this experiment data are stored at 8100 to 8109 and transmitted through TxD pin The same data is received through RxD and stored at 8200 to 8209 73
113. V This is negative true logic 69 Because of incompatibility with TTL logic voltage translator called line drivers and line receiver are required for TTL logic with the RS 232 signals The minimum interface required three lines pins 2 3 and 7 as shown in Figure 4 9 These lines are defined in relation to the DTE the terminal transmits at pin 2 and receives on pin 3 On the other hand the DCE transmits on pin 3 and receivers on pin 2 Typically data transmission with a handshake requires eight lines Transmitter Receiver Data Data Terminal Communication Equipment Bodl ss Transmitter Equipment DTE DCE Signal Ground FIGURE 4 8 MINIMUM CONFIGURATION OF CONTROL SIGNAL BETWEEN DTE AND DCE Protective Ground Transmitted data TxD DCE Received data RxD gt DTE Request To Send RTS DCE m Clear To Send CTS gt DTE Data Set Ready DSR DTE m Signal Ground Received Line Signal Detector Reserved for Data Set Testing Reserved for Data Set Testing m Unassigned m Sec Rec d Line Sig Detector Sec Clear To Send Secondary Transmitted Data Transmission Signal Element Timing DCE Source Secondary Received Data 46 2 Received Signal Element Timing DCE Source 4 j Unassigned 4 Secondary Request To Send lt DCE lt Data Terminal Ready Signal Q
114. Vcc 12 V 5 6 576 No load T All typical values are at TA 25 C t The algebraic convention in which the less positive more negative limit is designated as minimum is used in this data sheet for logic voltage levels only e g if 6 V is a maximum the typical value is a more negative voltage Not more than one output should be shorted at a time 4 TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1488 5 55188 5 75188 QUADRUPLE LINE DRIVERS SLLS094B SEPTEMBER 1983 REVISED MAY 1995 switching characteristics Vc c 9 V TA 25 PARAMETER TEST CONDITIONS TYP MAX UNIT tPLH Propagation delay time low to high level output 220 350 Propagation delay time high to low level output RI 3 100 175 tTHL Transition time high to low level outputt tTLH Transition time low to high level outputt 3 kO to 7 kO CL 2500 pF tTHL Transition time high to low level output See Figure 1 T Measured between 10 and 90 points of output waveform t Measured between 3 V and 3 V points on the output waveform EIA TIA 232 E conditions tTLH Transition time low to high level outputt See Figure 1 PARAMETER MEASUREMENT INFORMATION Input EM 3V Input 1 5 V 1 5 V OV Pulse tPHL gt tPLH Generator 90 see Note Output 90 N 50 50 10 _10 M tTLH TE
115. WHY To understand this consider Figure 5 B Here before microprocessor writes data to Port signal INTRA that is pin PC3 15 already high which we have connected with RST 6 5 So execution of EI will generate an interrupt on RST 6 5 JMP FEOC at its vector address 0034H will take control at FEOCH Then service routine which starts with instruction MOV A M will output a byte to the Port A After that JNZ will transfer control to main processor instruction JMP LOOP if all bytes from source are not transmitted Now let us understand how the Port B will generate INTRg When the service routine for RST 6 5 writes data for Port A through instruction MOV A M and OUT 00H OBF A Will go low for some time This OBF A we have connected with 91 5 Hence Port B receives strobe pulse and data from Port A STBg will make high Now to let the CPU know to read the data RD 1 IBF 1 and 5 1 will make INTRg high See Figure 5 5 C This high INTRg which we have connected with RST 5 5 will cause program control to jump to location 002CH which is a vector location of RST 5 5 At this address the instruction JMP FEO6H will transfer control to location 8100H At this location the service routine for RST 5 5 is written the instruction IN will make the RD low to read the data from Port B amp store it from 8300H onward The low RD will make the INTRg low After sometime the RD will go high causing to be low w
116. WR input and reset by ACK input being low 94 4 ACK Acknowledge Input A low on this input informs the 8255 that the data from Port or Port has been accepted 1 a response from the peripheral device indicating that it has received the data output by the CPU 5 INTR Interrupt Request A high on this output can be used to interrupt the CPU when the input device 15 requesting service or an output device has accepted data transmitted by the CPU The status word for Mode 1 15 illustrated 1n Figure 5 2 For INPUT gt GROUP A GROUP B For OUTPUT gt gt e LL GROUP A GROUP B FIGURE 5 2 Mode 1 status word format MODE 2 STROBED BI DIRECTIONAL BUS I O Bi directionality 1s available with Port A only Port B can be used in Mode 0 or Mode 1 as input or output The five bits of Port C are used to generate handshaking signals Figure 5 3 illustrate the details of Mode 2 85 OBFA ACKA STBA IBFA 3 DATA FROM n CPU TO 8255 WR gt 7 c INTR gt 1 N ACK EN STB DATA FROM PERIPHERAL TO 8522 DATA FROM 8255 IO PERIPHERAL DATA FROM 8255 TO 8085 FIGURE 5 3 details of mode 2 including hardware and signal timings The control signals have the same meaning as in Mode 1 Figure 5 4 shows the status word definition for the Mode 2 96 2 gt gt m gt gt li ka B
117. al pull ups and can be used as inputs As inputs port 1 pins that are externally being pulled low will source current because of the internal pull ups Port also receives the low order address bytes during flash programming and verification Port 2 Pin no 21 to 28 Port 2 is 8 bit bi directional I O port with internal pull ups The port 2 output buffers can sink source four TTL inputs When 176 are written to port 2 pins they are pulled high by the internal pull ups and can be used as inputs As inputs port 2 pins that are externally being pulled low will source current because of the internal pull ups It emits the high order address byte during fetches from external program memory and during accesses to external data memory the use 16 bit addresses During the accesses to external data memory that use 8 bit addresses port 2 emits the contents of the P2 special function register It also receives the high order address bits and some control signals during flash programming and verification 51 Port 3 Pin no 10 to 17 Port 3 15 an 8 bit Bi Directional I O port with internal pull ups The port 3 output buffers can sink source four TTL inputs When 175 are written to port 3 pins they are pulled high by the internal pull ups and can be used as inputs As inputs port 3 pins that are externally being pulled low will source current Ir because of the pull ups It also serves the function of various special features of the 89C51 a
118. an only Ce got in one way the way of exper ence there 9 no other way SAri Swami vivakand Affectionately fanatical To My Adored Grandparents Mr J N Nanavati and Mrs H J Nanavati And My Parents Dr C J Nanavati and Dr B C Nanavati Statement under O Ph D of Saurashtra University The content of this thesis is my own work carried out under the supervision of Dr H N Pandya and leads to some contribution In Electronics supported by necessary references Mr M C Nanavati Department Of Electronics saurashtra University Rajkot 360 005 Gujarat India This 1s to certify that the present work submitted by Mr M C Nanavati for the Ph D degree of Saurashtra University Rajkot has been the result of about 5 years of work under my supervision and 15 a valuable contribution the field of electronics Dr H N Pandya Head Department Of Electronics saurashtra University Rajkot 360 005 Gujarat India Acknowledgement am thankful to my GOD LORD SHIVA for give me opportunity to gain a higher level education am thankful to Saurashtra University for register me as a research student and permit me to use laboratory and other available resources of Department and University am thankful to my GURU Research advisor Dr H N Pandya Head Department Of Electronics Saurashtra University Rajkot Gujarat India for his keen interest in my research work and keep me morally boost in my difficulties
119. an remain in the input mode with no additional initialization required This eliminates the need to pull up or pull down resistors in all CMOS designs The control word register will contain 9BH During the execution of the system program any of the other modes may be selected using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine Any port programmed as an output port is initialized to all zeros when the control word 1s written The modes for port A and port B can be separately defined while port C 1s divided into two portions as required by the Port A and Port B definitions AII of the output registers including the status flip flops will be reset whenever the mode 15 changed Modes may be combined so that their functional definition can be tailored to almost any I O structure The mode definitions and possible mode combination mode combinations may seem confusing at first but after a cursory review of the complete device 18 operation a simple logical I O approach will surface The design of the 82C55A has taken into account things such as efficient PC board layout control signal definitions Vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins e Single Bit Set Reset feature Any of the eight bits of port C can be set
120. at they also have enough locations to accommodate the service routine as they are also very close This means one cannot write service routine at these locations also For this reason before servicing the interrupt user has to store codes of desired JMP instruction at FE12 FE02 and FEO6 Table 6 7 also contains these secondary addresses From Table 6 7 we learn that the service routine for RST 7 5 RST 6 5 and RST 5 5 should be written from 8700 8600 and 8500 addresses onward Note that TRAP 15 not free our kit Hence we have not written any service routine For each interrupt following service routine are written For RST 7 5 MVI A 30H 8700 3E 30 MVI B 30H 9702 06 30 ADD B 8704 90 5 8200 8705 32 00 82 RST 3 8708 DF This service routine will add 30H with 30H and stores the answer at 8200H when RST 7 5 interrupt take place For RST 6 5 MVI A 30H 8600 3E 30 MVI B 30H 5602 06 30 ADD B 8604 90 STA 8100H 9605 32 00 81 RST 3 8608 DF This is same as RST 7 5 service routine except that this routine will store the result at 8100 107 For RST 5 5 MVI A 30H 8500 3E 30 MVI B 30H 9502 06 30 ADD B 8504 90 STA 8000H 8505 32 00 80 RST 3 8508 DF This is same as RST 7 5 s service routine Except that 1t store the result at 8000 For INTR On occurring INTR user has to supply code on receiving INTAs In present experiment we have to use switches SW7 to SWIA to generate such code to perform
121. ational Mumbai and Applications Microprocessor Data handbook Revised Edition BPB Publication New Delhi Osborne Adam An Introduction to Microcomputers Volume 0 to 3 Adam Osborne and Associates Inc 1977 P K Ghosh and P R Sridhar 0000 to 8085 Introduction to 214 edition Prentice hall of Microprocessor for Engineers and scientists India EEE edition New Delhi Padmanbhan K Learn to use Microprocessor 4 edition EFY Enterprises New Delhi 1999 R S Gaonkar Microprocessor architecture programming application with the 8085 3 edition Penram International Mumbai gt Head Department Of Electronics Saurashtra University Rajkot Gujarat India 18 19 20 21 22 23 24 Rashid Mohammad Spice for circuits and electronics using PSPICE 254 and 3 edition Prentice hall of India Eastern Economy Edition New Delhi d NT 2 edition Singh Renu Microprocessor Interfacing and Application New Age Publication P Itd 2006 Stan Gibilisco and Neil Sclater Encyclopedia Of Electronics 1 and 20d edition McGraw hill publishing inc N Y Taub Herbert Digital circuits and microprocessor Tata McGraw hill Publishing company Limited England 1982 Theagarajan Dhanasekaran S Microprocessor and its Applications New Age international P ltd New Delhi 1997 Titus Christopher A Larsen David G Titus Jonathan A 8085 Cookboo
122. atus information are also transferred through the data bus buffer lt gt PA PA lt PA lt Ar P PA lt PA RE 3 WR cs cS eX RESET GND gt D oc K D lt gt D PCs lt D PCs lt D PC lt D lt D lt V lt lt sK gt lt PBe lt 7K PBs PB lt z Ky PB PB lt gt PBs GROUF A REDE IO GROUP A A PA PAo GROUP IO UPPER PC7 PC4 4 Bi Directional Data Bus DATA p p C es J BUFFER GROUP B PORT C a LOWER N PCa IER RD WR A1 Ao RESET READ GROUP B WRITE CONTROL CONTROL GROUP B IC LOGIC GEN PORT B BE BUR 8 CS FIGURE 2 2 Pin description and Functional block diagram of 82C55A 14 Read write and control logic The function of this 15 to manage all of the internal and external transfers of both Data and Control or status words It accepts inputs from the CPU Address and Control buses and in turn commands to both of the Control Groups CS Chip Select A LOW on this input pin enables the communication between the 82C55A and the CPU RD Read A LOW on this input pin enables the 82C55A to send the data or status information to the CPU on the data bus In essence it allows the CPU to read from the 82C55A
123. ble Disable target signals commands Using this command target control signals can be enabled or disabled individually or as a whole Interrupts Reset Hold Clock and Ready signals can be controlled For individual control following are the commands Enable Disable Target Reset ER DR Enable Disable Target TRAP ET DT Enable Disable Target RST 7 5 ER7 DR7 Enable Disable Target RST 6 5 ER6 DR6 Enable Disable Target RST 5 5 ER5 DR5 Enable Disable Target INTR EUDI Enable Disable Target HOLD EH DH Enable Disable Target CLOCK ETC DTC Enable Disable Target ICE CLOCK EIC DIC To control all signal using one command EX and DX are used for enabling and disabling respectively 2 Display Enable Disable target signals A EL Lists the enabled target signals B DL Lists the disabled target signals COMMAND TO CONFIGURE CE IN PC BASE ADDRSS BA command This specifies the base address for the ICE at which the user wants to configure the ICE Syntax BA address ASSEMBLER RELATED COMMANDS 1 Assemble A command This command creates executable machine code from assembly language statements All numeric values are in hexadecimal format Syntax a address 176 Here address specifies the location where user will type assembly language mnemonics Don t put H after hexadecimal values DB DW and ORG pseudo instructions are supported 2 Unassembled U command Disassembles bytes and displays their cor
124. bling In 8085A this enabling is done by executing an instruction called EI This means prior to any interrupt request user should include EI instruction in his main program Disabling of interrupt is valid for RST 7 5 RST 6 5 RST 5 5 and INTR One has to use DI instruction for this purpose A reset also will disable interrupts When any interrupt is recognized the processor disables the other interrupts except TRAP 101 o COMMON HARDWARE FOR THE EXPERIMENT To study the various concepts of the 8085A interrupts we have designed and tested a circuit which is shown in Fig 6 1 J2 POWER SUPPLY 74LS00 PIN 1 TRAP PIN 2 RST 7 5 PIN 3 RST 6 5 PIN 4 RST 5 5 PIN 5 INTR Figure 6 1 Interrupt generation circuit This circuit 15 divided into two parts 1 Interrupt generation circuit 2 Code providing circuit for INTR 1 Interrupt generation circuit In this circuit to generate interrupts for five different interrupt pins 1 e TRAP RST 7 5 RST 6 5 RST 5 5 and INTR of 8085A five pushbutton types of switches are used one terminal of all these switches swl sw2 sw3 sw4 and sw5 are connected with ground The other terminal of these switches becomes single inputs to individual NAND gates Refer to Fig 6 1 The second input of all NAND gates are connected to ground through the switch sw6 The outputs of these NAND gates are terminated on a strip connecter J1 Then individual wire connection from 11 is to be
125. bus connector e g system expansion connector The other connector of capture unit contains pins to be interfaced with the parallel port of computer 50 a centronics cable will be enough to connect the Parallel port connector data capture unit with the computer parallel port Pins to be connected with target through pods FIGURE 10 1 TYPICAL DATA CAPTURE UNIT 2 DATA STORAGE This is made of a bank of memory chips The collected information of all channels is stored in these chips for further processing Information is collected every clock time of analyzer Generally logic analyzer has limited capacity of storage 3 DATA PROCESSING AND RELATED ELECTRONICS This is associated with the interfacing card plugged into free slot of the motherboard of the computer 4 DATA DISPLAY UNIT The monitor of the PC 15 used as display unit The software supplied with PC based analyzer controls the means and types of displays on screen in user friendly ways 156 5 KEYBOARD CONTROL PANEL In PC based logic analyzer the PC ASCII keyboard is just sufficient for all control and parameter settings Even mouse also can be used DETAILED WORKING OF A LOGIC ANALYZER We will divide this topic into various sections to discuss systematically how one can use the logic analyzer We will mostly consider PC based logic analyzer Following section will help to understand 1 HARDWARE PREPARATION The digital circuit which we want to
126. c Monte Carlo and sensitivity or worst case analyses which describes the circuit behavior for various changes in components 187 values Here AC DC and transient analysis are basic analysis of a circuit while parametric Monte Carlo and sensitivity or worst case analyses are advance analysis of the circuit With limitation to our discussion we will discuss only AC DC and transient analysis e DC Analysis DC analysis of the circuit performs in response to a direct current source DC analysis calculates DC sweep Bias point DC sensitivity and small signal DC transfer While using DC analysis PSpice computes steady state voltage and current sweeping a sources model parameter and temperature effects on different values of DC sweep Other three points of analysis depend on automatically generated bias point data in which DC sensitivity and small signal DC transfer small signals DC gain Input Output resistances are function of bias points e AC Analysis AC analysis of the circuit performs in response to a small signal alternative current source AC analysis can be divided into two parts First is AC sweep and second is NOISE You can say AC analysis analyses AC sweep with output noise Here AC sweep computes small signal response of the circuit sweeping to one or more source over a range of frequencies It also includes voltage and current with their magnitude and phase To get a noise analysis we must run AC sweep analysis of a circui
127. change an interrupt enable flag the Set Reset port C Bit command must be used With a Set Reset port C Bit command any port C line programmed as an output including IBF and OBF can be written or an interrupt enable flag can be either set or reset Port C lines programmed as inputs including ACK and STB lines associated with Port C are not affected by a Set Reset port C Bit command Writing to the corresponding port C bit positions of the ACK and STB lines with the Set Reset port C Bit command will affect the Group A and Group B interrupt enable flags as shown in Table 2 3 Current drive capability Any output on port A B and C can sink or source 2 5mA This feature allows the 82C55A to directly drive Darlington type drivers and high voltage displays that require such sink or source current Reading Port C Status In Mode 0 Port C transfers data to or from the peripheral device When the 82C55A is programmed to function in Modes and 2 port C generates or accepts handshaking signals with the peripheral device Reading the contents of signals of port C allows the programmer to test or verify the status of each peripheral device and change the program flow accordingly There 15 not special instruction to read the status Information form port C A normal read operation of port C Is executed to perform the function 28 INPUT CONFIGURATION D7 D D5 D4 D3 D2 D1 Do OUTPUT CONFIGURATION D7 D6 25 D4 D3 D2 D1 Do
128. clock generator 1 3 us instruction cycle INTA nerer TRAF SD sor INTR RST INTERRUPT CONTROL SERIAL O CONTROL I 8 BIT INTERNAL DATA BUS f ACCUM LATOR FLAG FUP FLOPS i REGB REGD INSTRUCTION REGH REG L L DECODER ARITHMATIC AND STACK POINTER LOGIC MACHINE CYCLE PROGAM COUNTER UNIT ENCODING INCREMENTER DECREMENTEF ADDRESS LATCH POWER 5V SUPPLY GND ADDRESS DATA ADDRESS BUFFER BUFFER CONTROL STATUS DMA RESET AD ADc Ai5 ADDRESS DATA ADDRESS CLKOUT RE WRALE S HLDA BUS BUS HOLE RESET RESETOL Vcc HLDA CLKOUT RESETIN READY RD WR ALE 80 A15 A14 A13 A12 A11 A10 A9 A8 FIGURE 2 1 Block diagram and Pin configuration of 8085A DESCRIPTION 8085 contains following blocks 1 Registers special purpose and general purpose 2 Interrupt control 3 Serial I O control 4 Address data buffers 5 Timing and control unit 6 IR and decoder 7 Arithmetic logic unit ALU General purpose registers are B C D E H and L each of 8 bits They can be used as independent 8 bit registers or paired 16 bits registers Following pairs are possible BC DE and HL Pairs are used for 16 bit arithmetic and to address the data in memory HL 15 as special type of pair which always stores the address of memory location for accessing Special purpose registers are A FLAGS PC SP and IR The accumulator 15 one default operand storag
129. country com W 26 http www tomshardware com W 27 http www x86 org W 28 http www x86 64 org 247 1488 5 55188 5 75188 QUADRUPLE LINE DRIVERS SLLS094B SEPTEMBER 1983 REVISED MAY 1995 Meet or Exceed the Requirements of ANSI 5 55188 4 OR W PACKAGE EIA TIA 232 E and ITU Recommendation 1488 5 75188 D OR N PACKAGE V 28 TOP VIEW Designed to Be Interchangeable With Motorola MC1488 Current Limited Output 10 mA Typical Power Off Output Impedance 300 Minimum e Slew Rate Control by Load Capacitor Flexible Supply Voltage Range Input Compatible With Most TTL Circuits description SN55188 FK PACKAGE TOP VIEW The MC1488 SN55188 and SN75188 are monolithic quadruple line drivers designed to interface data terminal equipment with data communications equipment in conformance with ANSI EIA TIA 232 E using a diode in series with each supply voltage terminal as shown under typical applications The SN55188 is characterized for operation over the full military temperature range of 55 C to 125 C The MC1488 and 5 75188 characterized for operation from 0 C to 70 C FUNCTION TABLE drivers 2 4 A B Y _ NC No internal connection H H L L X H X L H H high level L low level X irrelevant Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments
130. crocontroller In this case the software 15 written such that the key press 1s displayed on the LCD module Software for keyboard interface and display initialization Is self explanatory and is given as below LCD amp Keyboard Interface with Microcontroller Main program MOD51 DBO EQU P1 0 EQU P1 1 DB2 EQU PI DB3 EQU P1 3 DB4 EQU P1 4 DB5 EQU P1 DB6 EQU 1 6 DB7 EQU P1 7 EN EQU P3 4 RW EQU P3 3 RS EQU DATAI EQU LJMP MAIN ORG 150H MAIN LCALL INIT LCD LCD initialization LCALL CLEAR LCD Clear LCD CLR RS MOV 80H Set cursor at 80h SETB EN LCALL DELAY CLR EN LCALL WAIT LCD 118 MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL NOP NOP NOP NOP NOP NOP NOP CLR MOV SETB LCALL CLR LCALL MOV LCALL MOV LCALL MOV A WRITE TEXT A TR WRITE TEXT A WRITE_TEXT A WRITE TEXT A 5 WRITE TEXT A lt WRITE TEXT A WRITE TEXT A N WRITE TEXT RS DATAI 0COH EN DELAY EN WAIT LCD A WRITE TEXT WRITE A 119 Write the message to LCD AABI AAB2 OVER LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV LCALL MOV MOV MOV ANL CJNE LCALL MOV ANL CJNE SJMP MOV MOV ANL CJNE MOV MOV ANL CJNE MOV MOV ANL CJNE MOV WRITE TEXT WRITE TEXT A WRITE TEXT A WRITE TEXT A WRI
131. cuit using text file For this we will use OrCad Spice A D package to write Pspice simulation text file Two stage Bipolar transistor amplifier VCC 10 0 DC 15V DC 15 common collector voltage VIN 1 0 AC IMV input AC ImV peak for frequency response VX 1 12 DC OV RS 12 2 150 206 C1 23 IOUF 10 3 200K R23 0 50K Q1 435 0 Q2N2222 transistor Q1 and Q2 have model name Q2N2222 Q2 7 6 8 0 Q2N2222 104 12K REI 5 03 6K CEI 5 0 150 C2 4 6 IOUF R3 60 120K R4 6 0 30K RC2 10 7 6 8K RE2 8 0 3 6K CE2 8 0 25UF C3 7 9 JOUF 9 0 10K model Q2N2222 NPN transistor model DEC 10 1OHZ IOMEGHZ AC analysis PLOT AC 9 9 AC plot PROBE END 207 OUTPUT WAVEFORMS TWOSTAGEBI OrCAD PSpice A D TWOSTAGEBI active File Edit View Simulation Trace Plot Tools Window Sy GR ld TWOSTAGEBI amp amp amp Q mnr kj Z RB of IIb 84 T 18Hz 188Hz 4 x wo stage Bipolar transistor amplifier x A eading and checking circuit ircuit read in and checked no errors alculating bias poin paint calculated Start 10 Freq 10 00 06 End 10 00 and Noise Analysis nalysis finishe Simulation complete P Analysis A Watch A Devices D practical examYTWOSTAGEBI dat active Freg 10 00 06 FIGURE 10 9 OUTPUT WAVEFORM OF TWO STAGE BIPOLAR TRANSISTOR AMPLIFIER SIMULATION OUTPUT FILE SMALL SIGNAL BIAS SO
132. d R1 and external Vcc This can be too much current for and will blow the transistor and as a result damage the port bit We are using buffer driver IC to convert any input switch to a buffer driver IC before it is fed to the 89 51 pin e INSTRUCTIONS READING THE STATUS OF INPUT PORT Mnemonics Examples MOV A Px MOV A PI JNB JNB P1 2 TARGET JB PX sss JB P1 3 TARGET MOV C Px y MOV C PI 4 CJNE A CJNE A TARGET 58 READINGLATCH Since in reading the port some instructions read the port and some others read the latch we next consider the case of reading the port where it reads the internal port latch ANL A is an instruction that reads the latch instead of the input pin when this instruction is executed l The read latch activates the tri state buffer of BUFI and brings the data from the Q latch into CPU 2 This data is ANDed with the contents of register A 3 The result is written to the latch After writing the result to the latch there are two possibilities 1 If Q O0 then Q 1 and MI is and the output pin has 0 the same as the status of the output pin has 1 the same as the status of the Q latch 2 If Q 1 then Q 0 and the is off and the output pin has 1 the same as the status of the Q latch So the instruction that reads a value performs an operation and rewrites it to the latch This is often called read modify write These t
133. d becomes costly In the second approach circuit performance is not checked by physically building the circuit Instead the performance is checked through software called simulation The advantages of simulating a circuit design are those which permit Evolution of the effects of variations 1n elements such as resistors transistors transformers and so on 2 The assessment of performance improvements or degradations 3 Evolution of the effects of noise and signal distortion without the need of expensive measuring instruments 4 Sensitivity analysis to determine the permissible bounds due to tolerances on each and every value or parameter of active elements 5 Fourier analysis without expensive wave analyzers 6 Evaluation of the effects of nonlinear elements on the circuit performance 7 Optimization of the design of electronic circuits In terms of circuit parameters One of the widely used simulation software Is PSPICE Let us discuss about PSPICE brietly o Whatis Pspice Spice means Simulation Program with Integrated Circuit Emphasis It is a simulation program that models the behavior of circuit By using OrCAD capture you can think as software based breadboard of our circuit that you can use to test and refine your design before putting all the components on your breadboard general purpose PCB or prototypes PCBs Pspice can perform DC AC and transient analysis that can be tested for different inputs It also analyses parametri
134. de of collector voltage of terminal Q4 with respect to ground Phase of drain source voltage of MOSFET M6 Phase of voltage at port B of transmission line Real part of voltage at node 2 with respect to node 3 Imaginary part of voltage at node 2 with respect to node 3 196 Current output In AC current output can be analyzed by following The common statements for that are as follow I lt NAME Current through NAME IX lt NAME gt current into terminal X of lt NAME gt IZ lt NAME gt Current at port Z of transmission line lt NAME gt Example IM RX Magnitude of current through resistor RX IR RX Magnitude of current through real part resistor RX II RX Imaginary part of current through resistor RX IM VIN magnitude of current through source VIN IR VIN II VIN real or imaginary part of current IAG TI Group delay of current at port of transmission line Here few things should be noted that current through listed elements could be analyzed without changing in circuit for other element We should put zero valued voltage source in series with the device Element Letter Capacitor C Independent current source Inductor Resistor Transmission line lt D Independent voltage source Here we should not forget that while doing AC analysis sometimes we need to perform frequency response That can be obtained by three different sweeps They are Linear sweep LIN Octave sweep OCT and
135. decade sweep DEC The common statements for all above sweep are AC LIN NP Fstart Fstop AC NP Fstart Fstop AC DEC NP Fstart Fstop Here AC is a type of ac analysis command LIN OCT DEC are type of sweeps NP is number of points in a frequency sweep Fstart is start frequency and 197 Fstop is a stop frequency While using LIN OCT DEC only one sweep can be possible in a statement The uses of this sweep are as follows LINEAR SWEEP LIN In linear sweep sweep increases linearly from starting to ending frequency NP becomes the total no of points in the sweep This type of analysis is used in narrow range of frequency OCTAVE SWEEP In octave sweep the analysis of the frequency 15 swept logarithmically by octave and NP ts number of points per octave The sweep 15 used is wide range of frequency DECADE SWEEP DEC It is same as octave but swept In decade NP 15 number of points per decade This sweep is used in widest range of frequency EXAMPLE AC LIN 300 100 Hz 300Hz AC LIN 1 60Hz 120Hz AC 10 100Hz 100KHz AC DEC NP KHz Il0MEGHZ After going through these statements we should note few things 1 Fstart should be smaller then Fstop 2 NP 1 could be possible but it calculate the frequency at Fstart 3 Pspice automatically calculates bias points for linearized circuit parameter around bias point for frequency response analysis 4 In an AC circuit at least one source should have AC val
136. duction in order to provide a fast and cost effective device For this it is very essential that all the learners should have at least basic knowledge of using simulation software Considering this we have designed and performed some experiments which give the idea about the environment of Pspice 205 The experiment developed consists of AC circuit DC circuit and digital circuits The same are discussed as follows 12 3 1 ANALOG EXPERIMENTS In these experiments the analog components are considered i e resistors diodes capacitors BJT FET MOSFET Op Amp etc The circuits incorporating such component may be AC type or DC type to have the experience in the both the cases we have designed AC circuit and DC circuit both 12 3 1 1 AC CIRCUITS In AC circuits the representation of circuit parameters are slightly different 1 e voltage and current representation are different from DC This is discussed in the introduction of this chapter To understand better the AC circuits analysis we have considered the following circuits EXAMPLE 1 A Two stage bipolar transistor amplifier is shown in Figure 12 8 The output is taken at node 9 Plot the magnitude and phase angle of the voltage gain and the magnitude of input impedance for frequencies from 10Hz to 1OMHz with a decade increment and 10 points per decade The peak input voltage is 1 mV FIGURE 12 8 TWO STAGE BIPOLAR TRANSISTOR AMPLIFIER Here we will simulate above cir
137. e maximum supply voltage curve Figure 6 In the FK and J packages 5 55188 chips are alloy mounted DISSIPATION RATING TABLE TA lt 25 DERATING FACTOR TA 70 C TA 125 C POWER RATING ABOVE Ta 25 C POWER RATING POWER RATING 950 mW 7 6 mW C 1375 mW 11 0 mW C 1375 mW 11 0 mW C 1150 mW 9 2 mW C 1000 mW 8 0 mW C PACKAGE SN55188 MC1488 SN75188 UNIT MIN NOM MAX MIN NOM MAX 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 1488 5 55188 5 75188 QUADRUPLE LINE DRIVERS SLLS094B SEPTEMBER 1983 REVISED MAY 1995 electrical characteristics over operating free air temperature range 9 V unless otherwise noted SN55188 MC1488 SN75188 PARAMETER TEST CONDITIONS UNIT MIN MAX Voce 9 V V VoH High level output voltage VCC 13 2 V Vcc 13 2 V VCC 9 V 1 9 V VoG 9 V VoL Low level output voltage I 10 5t 10 5 13 2 B i Short circuit output OS H current at high level s HO B cS E SH Ne Short circuit output Output resistance VOCs 20 Vooos power off Vo 2Vto2V Vcc 9 V All inputs at 1 9 V pigs All inputs at 0 8 V VoC 15 V 1 9 No load TA 25 9 Icc Supply current from Ic c 15 ope VOC 4 9 V 9 V n m No load PD Total power dissipation T 12 V
138. e register for some arithmetic and logical instruction second operand can be register or memory Flags register stores the result of arithmetic or logical instruction by setting or resetting the individual flip flops Following is the structure D7 De Ds Da Dz D1 Do S Z x ac x P x CY Carry flag set when carry or borrow occurs P Parity flag set for even parity AC Auxiliary flag set when carry occur due to operation of Ds digit Used for BCD arithmetic Z Zero flag set 1f the result 1s zero 5 Sign flag set if the result is negative number Stack pointer register always points to the last byte of the stack at TOS Filling up of stack decrements SP while retrieving of stack increments SP Used by PUSH and POP instruction Instruction register is not user accessible It stores the op code byte of any instruction and gives this information to decoder instruction decoder Interrupt control unit takes care of following interrupts INTR RST 7 5 RST 6 5 RST 5 5 and TRAP They are written above in their increasing priority TRAP is non maskable Except TRAP other interrupts can be enabled or disabled by interrupt enable EI or DI instructions RST means restart execution from predefined location They have vectored addresses RST 6 5 RST 5 5 and INTR are level sensitive while RST 7 5 is edge sensitive TRAP is edge and level sensitive Sampling of interrupts takes place one cycle before the last cycle of
139. ead all columns Mask unused bits Key in row 4 find column Ground row 5 Read all columns Mask unused bits Key in row 5 find column Ground row 6 Read all columns Mask unused bits Key in row 6 find column Ground row 7 Read all columns Mask unused bits Key in row 7 find column Ground row 8 Read all columns Mask unused bits Key in row 8 find column Keep doing the same task set Data pointer to codel Get the column and key code set Data pointer to code2 Get the column and key code set Data pointer to code3 Get the column and key code set Data pointer to code4 Get the column and key code set Data pointer to code5 Get the column and key code set Data pointer to code6 Get the column and key code set Data pointer to code7 Get the column and key code ROWS GET GETDATA INIT LCD MOV RRC JNC INC LJMP CLR MOVC MOV LCALL MOV LCALL LJMP CLR MOV SETB LCALL CLR LCALL CLR MOV SETB LCALL CLR LCALL CLR MOV SETB LCALL CLR LCALL RET CLEAR LCD CLR DPTR CODE8 Set Data pointer to codes A Rotate Acc right once with carry GETDATA DPTR GET A A A DPTR R7 A CLEAR LCD A R7 WRITE TEXT AABI Check for no carry Increment DPTR by one Back in loop Get the key code from look up table Clear LCD Write the key code on LCD scan for the next key pressed LCD initialization sub
140. ecause we have not connected READY signal 23 channel with logic analyzer From analysis purpose we have marked some cursor positions on Figure 10 4 to compare it with marked position of Figure 10 2 These marks are referred to as ti to ts t4 ts te 15 tg Since machine cycles are not mentioned in standard display of logic analyzer we have manually indicated them as in Figure 10 4 Comparing the logical states at marked position to t3 ty ts te t7 tg to of Figure 10 2 and Figure 10 4 we can construct a table as shown in Table 10 2 Here predicted signal waveforms and captured signal waveforms can be compared for proper working of the program under consideration The comparison reveals that the microprocessor kit works properly because expected timing waveforms are exactly reproduced on the logic analyzer display Note that ti t2 to of logic state analyzer 166 are shown in binary high or low and 1 t2 to of predicted waveforms are shown in hexadecimal as well as in binary high or low states For example for predicted signal waveform Figure 10 2 entry 40H against marking t represents logical states of address pin 5 to Ag while 00 for the same t represents address data AD to ADo ex fo mess m ms A12 40 40 40 40 40 40 40 40 40 eee m mes m ms A mss A mss m epp wem eps AD I I 00 00 01 02 FF 03 C3 04 LLL LL pem won n
141. ed circuit commands simulation results massages for warning and error in prepared in OrCad capture or in text file 194 Until now we had discussed files inputs and outputs and other configuration which are associated with circuit which we had prepared in OrCad capture Now we will discuss about text simulation In this we need to understand some command for input and output We also need to understand how we can configure AC DC and transient analysis in text file e Simulation through Text file Doing simulation from text file we have to make part for AC DC and transient analysis command Here we discuss AC analysis DC analysis and transient analysis one by one After understanding of these commands we will discuss one example for each o commands sources In a AC circuit analysis we have two different statements for current and voltage The statements for there sources in general form are as follow V NAME N N lt magnitude value phase value IcNAME gt N N AC magnitude value lt phase value Here NAME means voltage or current source stimuli name N and N is node where source connected The magnitude value Is the peak value of sinusoidal voltage and phase value 15 In degree Example VOLTAGE STATEMENT VACI2ACO2V 2 volt AC input between node 1 and 2 without phase change VACP 2 AC 2V 90DEG 2 V AC input between node and 2 with 90 phase ang
142. efault In the second the range for voltage V 5 and V 4 7 is OV to 10 that for current IBQ Q1 is MA to 50 and that for the current IC Q1 is 50 MA to 50 MA PROBE STATEMENT Probe is a graphics post processor or wave form analyzer for Pspice The simulation result cannot be used directly by Probe First the results have to be processed by the PROBE command which writes the processed data on a file PROBE DAT for use by Probe The command takes one of these forms PROBE PROBE one or more output variables In the 1 statement where no output variable is specified the PROBE command writes all the node voltage and all the element currents into PROBE DAT file The element currents are written 1n the forms that are permitted as output variables In the 2 statement where the output variable 16 specified Pspice writes only the specified output variable to the PROBE DAT file This form 15 suitable for users without a fixed disk to limit size of the PROBE DAT file Example PROBE PROBE V 5 V 4 3 V C1 V C2 2 1 VBE QI WIDTH WIDTH STATEMENT The width of the output in columns can be set by the width statement which has the general form of width out lt value gt The lt value gt is in columns and must be either 80 or 132 The default value is 80 EXPERIMENTS It is the demand of today s technology that one must be able to simulate the circuit design before actual commercial pro
143. er an interrupt is accepted INTA OUTPUT PIN NO 11 INTERRUPT ACKNOWLEDGE is used instead of and has the same timing as RD during the instruction cycle after an INTR is accepted It can be used to activate the 8259 INTERRUPT CHIP or some other INTERRUPT PORT RST 5 5 RST 6 5 AND RST 7 5 INPUTS PIN NO 9 8 AND 7 RESTART INTERRUPTS These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted Priority is highest for RST 7 5 then RST 6 5 lastly RST 5 5 these have higher priority then INTR TRAP INPUT PIN NO 6 TRAP INTERRUPT is a non maskable restart interrupt It is recognized at the same time as INTR It is unaffected by any mask or INTERRUPT enable It has the highest priority of any interrupt RESETIN INPUTS PIN NO 36 RESET sets the program counter to zero and resets the INTERRUPT Enable and HLDA flip flop None of the other flags or registers except the Instruction Register are affected The CPU 16 held in the reset condition as long as reset 1s applied RESETOUT OUTPUTS PIN NO 3 Indicates CPU 15 being reset It can be used as a system RESET The signal 15 synchronized to the processor clock 12 Xj X2 INPUTS PIN NO 1 AND2 Crystal or R C network connections to set the internal clock generator X can also be an external clock input instead of crystal The input frequency 1s divided by 2 to give the internal operating frequency CLKOUT OUTPU
144. es one instruction of a progarm at a time and displays the contents of all registers the status of all flags and the decoded form of the instruction to be executed Syntax T address numbers Here address specifies the address at which ICE is to start executing instructions number specifies the number of instructions to be executed This must be hexadecimal number The default value is 1 Example T 100 10 3 Proceed P command It executes one instruction at a time and steps over a subroutine Syntax P address address specifies the address from where the execution has to begin Example P 100 4 Go G command Runs the program currently in memory Syntax G address Breakpointl Breakpoint10 Address specifies the address in the program currently in memory at which user wants execution to begin TRACE COMMAND 1 Forward Trace FT command Starts tracing the processor s status from the specified trigger address It traces up to 2K machine cycle along with the external trace bits Syntax FT lt address gt Address specifies the trigger address of the processor s memory from which the ICE begins recording instruction Example FT 100 178 2 Backward Trace BT command Stops recording the processor s status at the specified trigger address It traces upto 2k machine cycles along with the external trace bits Syntax BT address address specifies the
145. ess the key numbered 1 13 for example the control lines 1 amp 13 are shorted and show continuity One can check the working of keyboard by pressing each key and measuring the continuity between numbered control lines 7 2 Interfacing of Keyboard with 89 51 Microcontroller To see the key press of the keyboard LCD Liquid Crystal Display 15 one of the better alternatives today So to see the result of key pressed we have used the 1 line 16 character LCD module The details of the circuit diagram are shown in Figure 7 3 113 LCD amp Keyboard Interface With Microcontroller FIGURE 7 3 CIRCUIT DIAGRAM OF KEYBOARD INTERFACE WITH 89 51 MICROCONTROLLER We have connected each control line of the keyboard to Vcc via 10K resistor Figure 7 4 shows the logic for single key of the keyboard Initially the rows and columns are getting 5v The columns control lines 1 5 are connected to Port 2 P2 0 P2 4 and the row control lines 6 13 are connected to Port P0 0 to P0 7 On the other side of ATS89C5 microcontroller LCD module 15 interfaced with Port 1 P1 0 P1 7 and Port P3 2 P3 3 amp P3 4 The connection details of the Keyboard amp LCD module are listed in Table 7 1 a and Table7 1 b 114 ROW Control Line E g 13 COLUMN Control Line E g 1 FIGURE 7 4 THE LOGIC FOR SINGLE KEY OF THE KEYBOARD Signal from LCD module A T 9c51 Port Pins
146. ewer topics has surmounted the slow pace of learning Students are desirous of learning many new things in electronics but the latest electronics topics have not been chewed by the faculties to feed the young ones that 1s students It is our basic objective In the present work to convert such complex conceptual aspects to a level that can be easily understood by the student We have developed the experiments which can train students to easily understand and verify the concepts themselves by performing experiment on there own We also planed to prepare material regarding experiments which is included in the concerned experiments Thus the objectives of the present work 15 to design and develop experiments on advance topics like microprocessor microcontroller circuit simulation and on the development tool to help the students learn this topic with ease along with the study material 1 2 Literature Survey In the first attempt to gather information about the experiments in the field of electronics the books on such topic were searched The well known books written by ZBAR PAUL B Basic Electronics Text Lab Manual 4 and 7 edition Tata hill Publishing company Limited and listed below were studied But the content of the books were of basic electronics type We tried to refer the various books 8085 which may give some idea on the interfacing experiments on 8085 Some of the books we found useful are listed below 198
147. ey from the look up table When the key code identified and transferred to accumulator from look up table the display 1s cleared and key code is written on the LCD module The program is looped back for the other key press detection Final Output When the system is started initial message on LCD PRESS ANY KEY will be displayed As soon as the key 15 pressed on the keyboard the display is cleared and key assigned code will be displayed on the LCD module 125 8 ADVANCE EXPERIMENTS ON DISPLAY INTERFACE 4 d d d d d d 4d 4 4 i4 4 i 126 Moving message displays are now days getting more importance for better advertisement Due to different varieties and versatility such displays are useful at various places for example to show the information for the trains 1n railway stations or in hotel lounges to assist the hosts These displays are available starting from simple LED s to LCD modules In this chapter a simple way to design and construct a moving message display system using AT89C51 microcontroller is emphasized 81 BASICS OF DISPLAY USED 29 The 5x7 matrix modules made of Kwality Photonics Private Limited 1s used for this experiment the module number 15 KLP1057I It is common anode type of module The details of this module are shown in Figure 8 1 and Figure 8 2 R2 CI RA C3 C4 RI R3 14 13 1211 10 9 8 12 3 45 6 7 R5 R7 C2 C3 R4 C5 R6 FIG
148. f identifying the key Starting from the top row the microcontroller grounds it by providing a low to row connected to control line 13 P0 0 only then it reads the columns If the data read is all 175 no key in that row is activated and the process is moved to the next row It grounds the next row reads the columns and checks for any zero This process continues until the row 15 identified After identification of the row in which the key has been pressed the next task 1s to find out which column the pressed key belongs to Finally microcontroller gets the key pressed by matching the logic combination of row and column Then the pressed key assigned code 15 displayed on the LCD module e SOFTWARE FLOWCHART Start LCD Initialization Set LCD Cursor to Ground Next Row and Display Start Up Message Ground All Rows ey Press in this Row Get the Key Pressed All Keys Open Get the Key Code for the Look Up Table yes Display Key Code on LCD Read All Columns Return Any Key Down Read All Columns for Debouce Check yes FIGURE7 5 SOFTWARE FLOWCHART FOR KEYBOARD INTERFACE WITH 89 51 MICROCONTROLLER 117 KEYBOARD INTERFACE WITH ATS9C51 SOFTWARE software is responsible for identifying the key pressed and displaying the key code on the LCD module For this reading the codes and outputting the same to the proper Port at proper time 1s done through proper instructions of the mi
149. f the mode instruction selects this factor 1 1 16 or 1 64 the Data is sampled into the 8251A on the rising edge of SYNDET BRKDET SYNC Detect Break Detect This pin is used in Synchronous mode for SYNDET and may be used as either input or output programmable through the Control Word It 15 reset to output mode low upon RESET When used as an output internal Sync mode the SYNDET pin will go HIGH to indicate that the 8251A has located the SYNC character in the Receive mode If the 8251A is programmed to use double Sync characters bi sync then SYNDET will go HIGH In the middle of the last bit of the second Sync character SYNDET is automatically reset upon a Status Read operation When used as an input external SYNC detect mode a positive going signal will cause the 8251A to start assembling data characters on the rising edge of the next RxC Once in SYNC the HIGH input signal can be removed When External SYNC Detect 16 programmed internal SYNC Detect 1s disabled BREAK Async Mode Only This output will go high whenever the receiver remains low through two consecutive stop bit sequences including the start bits data bits and parity bits Break Detect may also be read as Status bit 15 reset only upon master chip Reset or Rx Data returning to a one state Operational description General The complete functional definition of the 8251A is programmed by the system s software A set of co
150. fference 1s in column selection which is now controlled by Port 2 After the completion of DATANXT routine DPTR Is incremented once and column selection codes are left as 1t 1s so that the display moved the one column left And fetch the new column selection C01 on very right side of the display module Again the DATANXT is called to provide the data write function to the microcontroller ports This increment in DPTR causes the program to start fetching row codes from next memory address 700h onwards which results visualizes the moving message on the display 137 In this program appropriate delay is provided by means of DELAY sub routine so that change in each row column selection code is not visualized by human eye and constant moving message is displayed on the 15x7 display module e FINAL OUTPUT Program given here will display moving message of 5x7 HNP continuously 138 Piola j j i11 1111111 CHAPTER 9 ADVANCE EXPERIMENTS ON LCD INTERFACE lli i l jl l bit 139 91 INTRODUCTION Sometimes it becomes necessary to display complex message which can not be tackled by simple LED s or 7 segment displays Such display messages could be made up of numbers characters of the alphabet and other symbols This type of display messages can be handled by different types of LCD modules A module contains one or more rows of character positions Each character position consists of a matrix that 16 typically five seg
151. for 0 0 0 0 0 I 0 I 05 for 99 HARDWARE CONNECTION Take available 8085 microprocessor based kit from the user s manual find out the connector for 8255 Determine the correlation of connector pins with the 8255 pins and connect them as follows PA PB PAs gt PA PB PA3 PB PA PBo PC gt PC PC PC Through Inverter PC INTRA gt RST 6 5 FEOC H PCy INTRB gt RST 5 5 FE06 H Also find out the control word Port address and address for Port A Port B and Port C of 8255 in your kit In our case we have control word register address 03H and Port A B and C as 00H 01H and 02H respectively The following program 15 entered in the kit 9000 8002 8004 8006 8008 800A 800C 900 9010 9011 8014 8017 8018 LOOP 06 11 3E A6 D3 43 03 3E 0D D3 43 03 3E 05 D3 43 03 3E 08 30 21 00 82 11 00 83 FB C3 17 80 MVI B 11H MVI A A6H OUT 03H MVI A OUT 03H MVI A 05H OUT 03H MVI A 08H SIM LXI H 8200H LXI D 8300H EI JMP LOOP COUNTER CONTROL WORD FOR 8255 IO CONTROL WORD REGISTER BSR WORD TO SET INTE TO CONTRL WORD REGISTER BSR WORD TO SET INTEs PCO TO CONTRL WORD REGISTER DATA TO ENABLE ALL INTERRRUPTS THROUGH SIM POINTER TO DATA SOURCE POINTER TO DATA DESTINATION ENABLE INTERRUPTS REPEAT Generall
152. gic analyzer works on the principle of sampling the information of signal states at very fast rate compared to repetitive rate of signals then storing this information into proper sized memory and later display it on the screen for user s analysis For such sampling work the logic analyzer has a data capture unit which collects the data logical state conditions at various points of time of signals under consideration CONSTRUCTION OF LOGIC ANALYZER The logic analyzer can be divided into following simple parts in first attempt of understanding 1 DATA CAPTURE UNIT 2 DATA STORAGE 3 DATA PROCESSING AND RELATED ELECTRONICS 4 DATA DISPLAY UNIT 5 KEY BOARD CONTROL PANEL 1 DATA CAPTURE UNIT A typical data capture unit 15 shown in figure 10 1 It has small PCB fixed into a small metal case with connector at two ends The PCB contains proper electronics component to collect the information of the logic states of all parallel inputs channels 155 One connector is having pins which are to be connected with signals under consideration through the test probes called For each pin of connector a separate pod 15 provided One end of pod is connected with the pin of the connector and other end of pod 1s connected with signal The connecting point for a signal can be a separate wire a pin or directly the pin of some IC of interest Usually signals of a typical microprocessor based system are the pins of output
153. gram FIGURE 2 9 Output Control Signal definition OBF Output Buffer Full Flip flop The OBF output will go LOW to indicate that the CPU has written data out to be specified port This does not mean valid data is sent out of the port at this time since OBF can go true before data 1s available Data 1s guaranteed valid at the rising edge of OBF The OBF flip flop will be set by the rising edge of the WR input and reset by ACK input being low ACK Acknowledge Input A LOW on this input informs the 82C55A that the data from port A or port 15 ready to be accepted In essence a response from the peripheral device indicating that it is ready to accept data INTR Interrupt Request A HIGH on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR is set when is a ONE OBF is a ONE and INTE is a ONE It is reset by the falling edge of WR e Mode 2 Strobed Bi Directional Bus I O The functional configuration provides a means for communicating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data Bi Directional bus I O HANDSHAKING signals are provided to maintain proper bus flow discipline similar to mode 1 Interrupt generation and enable disable function are also available Mode 2 Basic functional definitions Used in Group A only One 8 bit Bi Directional bus port port A and 5 Bit control port
154. he movement of the characters on the display For this reading the codes and outputting the same to the proper port at proper time 1s done through proper instructions of the microcontroller In the present case the software is written such that the message 5x7 HNP is displayed sequentially Software for display initialization and data write 15 self explanatory and is given as below Moving message display using 15x7 matrix Main program MOD51 LJMP MAIN ORG 150H MAIN MOV SP 40H Move stack pointer to 40H NEXT MOV DPTR 700H Load Data pointer 700H LCALL CLRDISP Clear display LCALL DATANXT Call data and display to module MOV RO 24H Store no of data in RO NEXTI INC DPTR Increment DPTR to point next data MOV P2 00 Clear port2 LCALL DATANXT Call data and display to module DJNZ RO NEXTI If RO is not zero jump to next LJMP NEXT Run program in continuous loop DATANXT MOV R6 01 Initialize count in AB2 MOV R7 100 Initialize count in R7 ABI MOV R3 400H R3 00h for 1 code from memory MOV RI 01H Column 1 selection of P3 NXTDATA MOV A R3 Get the data from memory MOVC A A DPTR MOV sent data to for row codes MOV P2 Off port2 connected display MOV P3 RI select column of display MOV A Get the selection code of RL A column in again 135 CLRDISP DELAYI1 HERE2 VALUE MOV INC LCALL CJNE
155. hich is inverted and applied as 1 to Port A This high state of ACKA will make INTRA high to fetch another byte from memory thus executing the service routine for RST 5 5 In this way alternate generation of RST 6 5 and 5 5 will execute service routine to transmit bytes from the source and receive at destination E MODE 2 EXPERIMENT In this experiment the concept of Bi directional communication is studied In a 8255 Port A can be configured in Bi directional mode In this mode the control signals are generated by Port C pins The Bi directionality of the communication is studied by two different experiments In first experiment Port A is configured as O P Port and Port B 1s configured as I P Port In second experiment Port A is configured as I P Port and Port B is configured as O P Port In this experiment the hardware details 1s shown in Figure 5 6 The pin connections are also shown as below e HARDWARE CONNECTION For case one i e to make Port A Output and Port B Input connect the pins on the 8255 connector as per your kit connection as follows PBo PA PB PBe PA gt PB PA PB PA gt PB PC OBF 8 PA PC IBFg Through Inverter 02 PA7 PAC When port A as input port in mode 2 part 2 Connect RST 5 5 to INTRA and connect RST 6 5 with INTRB dotted line connection configurat
156. hson S L Microprocessor with application in process control Tata MCGraw hill Publishing Company Limited New Delhi 1992 Baker R Jecob Li Harry W Boyce David E CMOS Circuit design layout and simulation Prentice hall of India d x 2 edition Bose Sanjay Digital System From Gates to Microprocessor New Age International P Itd 1992 Dr H N Pandya Printed Circuit Board Gujarat Granth Nirman Board Ahmedabad India 1 edition Dr H N Pandya Understanding P C B Designing software saurashtra University Rajkot 2006 Electronics concepts handbook vol 1 to 3 McGraw hill publishing inc N Giacoletto Electronics Designers handbook gad edition McGraw hill publishing inc Hall Dougles Microprocessor and Digital system 2 edition Tata McGraw hill Publishing Company Limited J C Whitaker The Electronics Handbook IEEE Press John Markus Guidebook of Electronics Circuit McGraw hill publishing inc Kenneth J Ayala The 8051 microcontroller Architecture Programming and nnd Applications edition Penram International Mumbai Microprocessor Data handbook Revised Edition BPB Publication New Delhi Motorola microprocessor 68C00 applications Head Department Of Electronics Saurashtra University Rajkot Gujarat India 244 B 14 B 15 B 16 B 17 B 18 B 19 B 20 B 21 B 22 B 23 B 24 B 25 Appendix B Osborne Adam
157. iagram of EPROM 2764A and RAM 6264 respectively The address space of 8085A in Hexadecimal HEX location induces from 0000H to FFFFH Normally in memory organization of 8085A first few Kilobytes of memory locations are used for EPROM area and rest are used for RAM area A typical memory organization of 8085A 15 shown in Figure 2 22 and 2 23 For interfacing 2764A with 8085A a decoder 7415155 and latching 7415373 are used The interfacing circuit for the same 1s shown in Figure 2 23 Note that this circuit 15 a part of the detailed circuitry of microprocessor trainer kit 1 2 3 4 5 6 7 8 9 FIGURE 2 20 PIN DIAGRAM OF 27644 EPROM 0000 to 8085 Introduction to Microprocessor for Engineers and scientists 2 edition P K Ghosh and P R Sridhar 7 Microprocessor Architecture Programming and Application with the 8085 3 Ed R S Gaonkar Intel Datasheet 44 1 2 3 4 5 6 7 8 FIGURE 2 21 PIN DIAGRAM OF 6264 RAM 741 5373 de multiplexes to AD lines of 8085A when ALE becomes high and it enables IC 741 5373 trough its pin no 11 G to latch the address Ao to A Active low enable pin no 1 that is OC of IC 74LS373 15 permanently erounded The output of Qo to Q7 of 74LS373 i e Ag to A address lines are connected with the address lines Ao to of EPROM 270644 The rest of the address lines of 2764A 1 e A8 to A12 address lines are connected with corresponding address line
158. ile generation during capture simulation When simulation starts capture generates netlist and circuit file These files are most important in simulation process before analysis or anything else it do 1 Netlist This file contains device name device values and connection between two devices Capture generates NET file name 2 Circuit file This file contains commands and describes what type of simulation should run It 15 also refers to other files which contains netlist model stimulus and user defined information which apply to simulation Capture generates CIR file name for this file Simulation profile configuration To configure simulation profile we need model files stimulus files and include files before starting simulation Model files and stimulus files can be edited 1n model editor and stimulus editor User can enter data for user defined model in NOTEPAD or such like text editor can be used v Model files Model files are nothing but a model library These files contain electrical definitions of a part provided by part manufacturer or datasheet of the part In simulation this file 15 used as an information of a part which will respond to different input These definitions are containing model parameter and sub circuit netlist Model parameter and sub circuit netlist are generally available in datasheet PSPICE have many in built parts model Model parameter defines the behavior of a part 191 and subcircuit netl
159. ine receivers designed to satisfy the requirements of the standard interface between TE RIA a data terminal equipment and data communica gt tion equipment as defined by TIA EIA 232 F A tS separate response control CONT terminal is 1Y 18 4CONT provided for each receiver A resistor or a resistor NC 17 NC and bias voltage source can be connected 2A 16 4Y between this terminal and ground to shift the input NC is NC threshold levels An external capacitor can be 2CONT T connected between this terminal and ground to provide input noise filtering The SN55189 and SN55189A are characterized for operation over the full military temperature range of 55 C to 125 C 1489 MC1489A SN75189 and 5 75189 characterized for operation from 0 C to 70 C NC No internal connection Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet Motorola is a trademark of Motorola Incorporated PRODUCTION DATA information is current as of publication date Copyright O 1998 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL PRF 38535 all parameters are tested standard warranty Production processing does not necessarily include TEXAS unless otherwise noted
160. ines of 741 5 155 selects 6264 through output pin 2Y be accepting A15 20 4 1 As shown in above table The detailed circuit diagram is shown in figure 2 23 Note that since this is Read Write memory one should connect RD and WR pins with 6264 In 8085A system WR is connected with WR and RD is connected with OE of 6264 6264 has two chip select lines 1 CS and CS2 CS is driven by 74LS155 while CS is connected with Vcc From Figure 2 23 we learn that the EPROM memory area ranges from 0000H to IFFFH Similarly from Figure 2 24 the RAM area extends from 4000H to 5FFFH Such type of memory maps help to understand the memory management aspect of the system 47 CHAPTER 3 BASICS OF MICROCONTROLLER 69C51 31 INTRODUCTION The 89C51 is an embedded microcontroller chip which has a computer processor with all its support functions memory and I O built into the device These built in functions minimize the need for external circuits and devices to be designed in the final application The 89C51 15 a member of the Microcontroller 51 family The features of the 89 51 e Compatible with MCS 51 products e 4K bytes of In System reprogrammable flash memory Endurance 1 000 write erase cycles e Fully static operation 0 Hz to 24 MHz e Three level program memory lock e 128 x 8 bit internal RAM e 32 programmable I O lines Two 16 bit Timer Counter e Six interrupt sources e Programmable Serial channel e
161. ing any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1998 Texas Instruments Incorporated This datasheet has been download from www datasheetcatalog com Datasheets for electronics components
162. ing of target system 10 DEBUGGING OF MICROPROCESSOR KIT USING LOGIC STATE ANALYZER To understand the working of a microprocessor we have to understand the timing waveforms of that microprocessor For this logic state analyzer 1s one of the best available tools For present experiment 8085 based kit is used BASICS OF TIMING WAVEFORMS Normally 8085 based trainer kits include 8085 processor latches logic ICs memory chips peripheral chips keyboard 7 segments displays etc To test whether the hardware of the kit works properly or not we can run a known program on the kit and check the expected timing waveforms on various pins of concerned ICs or across connectors whatever the case may be using logic analyzer For this one must have thorough knowledge of what should be going inside the kit and the microprocessor while program 15 being executed Let us discuss this with real example Take any microprocessor trainer kit You must have its user s manual with circuit layout Load into its memory usually RAM the following program by entering its instruction codes START NOP MVI A FFH JMP START We have deliberately chosen such a small program because our aim is to understand the timing waveforms of instructions The program includes one byte two byte and three bytes instructions We assemble and store this program from location 4000H onward 4000H 1s our choice you can have your own The codes on locations 4000H t
163. ion RST 5 5 PB7 PBC PORT B IN MODE I FIGURE 5 6 Port A as Output Port and Port B as Input Port Now enter the following program after modifying branch location as per your kit s requirement 93 9000 0611 MVI B 11H COUNTER 8002 3E C6 MVI A C6H CONTROL WORD TO 8004 D3 03 OUT 03H CONFIGURE PORT A IN MODE 2 AND PORT B AS I P PORT IN MODE 1 8006 3E OD MVI A 0DH BSR MODE WORD TO 8008 D3 03 OUT 03H SET PCs 800A 3E 05 MVI A 05H BSR MODE WORD TO 900 D3 03 OUT 03H SET 900 08 MVI A 08H DATA TO ENABLE ALL INTERRUPTS 9010 30 SIM 8011 21 00 82 LXI H 8200H SOURCE POINTER 8014 11 00 83 LXI D 8300H DESTINATION POINTER 9017 LOOP FB El 9018 C3 17 80 JMP LOOP The vector addresses in our system are as follows INTRA RST 6 5 FEOC JMP 8150 INTRg RST 5 5 8100 This means enter the codes of instruction JMP 8150 at address FEOC the codes of JMP 8150 at address This is only true for our kit Modify as per your kit Now enter at 8150 and 8100 locations following program which are service routine for RST 6 5 and RST 5 5 respectively For RST 6 5 AT 8150 8150 TE MOV TAKE DATA FROM 8200 TO 8151 D3 00 OUT OOH OUTPUT TO PORT A 8153 23 INX H 8154 05 DCR B 8155 C2 59 81 JNZOUT ALL BYTES TAKEN 8158 76 HLT YES HALT 8159 OUT C9 RET OTHERWISE GO TO MAIN PROGRAM 94 For RST 5 5 AT 8100 8100 DB O1 IN 01H
164. is a process of letting the analyzer know how it has to work It 15 also called setup procedure Typically following things are to be set A Clock Specify whether you want internal or external clock Here internal clock means the clock of logic analyzer while external clock means the clock of the target or any other external reference clock For every clock pulse the parallel inputs are sampled and the logic levels 0 or 1 stored in the analyzer memory B Rate If you have selected internal clock then you may have to specify the clock speed or sampling rate of logic analyzer There may be few options Select the befitting C Display Here you have to choose setup the type of display information Generally there are three options Timing waveforms state list or mixed a Timing waveform In this display mode the screen shows the captured data graphically as a series of waveforms one for each channel The channels are listed along the Y axis The X axis represents the position in the data buffer in order of increasing time Here you can compare the logical states of signals with respect to time cursor may help for this b State list In this display mode data for each position is shown grouped and can be loaded into ASCII Hexadecimal Binary and Decimal format Each data point position in the state display 15 numbered The display can be scrolled up or down c Mixed Mode In this mode the screen 15 divided into tw
165. ist defines the structure and function of a part during use in circuit This model library are stored in LIBRARY directory by OrCAD with LIB extensions User can enter his own part as described above v Stimulus files A stimulus file contains time based definitions for analog input stimuli This file can be created manually using model text view of the model editor which are normally saved as STM or it may be generated using stimulus editor with STL file name Figure 12 3 shows implementation of STL in simulation profile 8777 D Capture pti 2 SCHEMA HE TIC1 PAGE1 by e e AIGA vv Tels ee V e Simulation Settings paper spice paper publication 51 Browse Stimulus files X 21 example stl Add as Global Add to Design 4 start Windows Media Player PSpice Microsoft Word amp X OrCAD Capture Stimulus Editor exa Simulation Settings FIGURE 12 3 IMPLEMENTATION OF STIMULUS FILE v Include files It is user defined file which contains PSPICE commands and text comment which appear in the PSPICE output file OrCad supply include file for standard simulation Figure 12 4 shows where to implement this simulation profile This include file you can modify using windows standard text editor such like NOTEPAD or you can generate your own include file by saving INC and
166. itation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent Tl deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regard
167. ition such as Data Set Ready DTR Data Terminal Ready The DTR output signal is a general purpose 1 bit inverting output port It can be set LOW by programming the appropriate bit in the Command instruction word The DTR output signal 15 normally used for modem control such Data Terminal Ready RTS Request to Send The RTS output is signal is a general purpose I bit inverting output port It can be set LOW by programming the appropriate bit in the Command instruction word The RTS output signal is normally used for modem control such as Request to Send e CTS Clear to Send A LOW on this input enables the 8251A to transmit serial data if the Tx Enable bit in the Command byte 15 set to a ONE If either a Enable off or CTS off condition occures while the Tx will transmit all the data in the USART written prior to Tx Disable Command before shutting down e Transmitter Buffer The transmitter Buffer accepts parallel data from the Data Bus Buffer converts it to a serial bit stream inserts the appropriate characters or bits based on the communication technique and output a composite serial stream of data on the TxD output pin on the falling edge The transmitter will begin transmission upon being enabled if CTS 0 The TxD line will be held in the marking state 32 immediately upon a master Reset or when Tx enable or CTS is off or the transmitter 1s empty Transmitter Control The transmitter Con
168. itor It is a graphical input waveform editor that lets you define the shape of time based signals which are used during circuit simulation By using stimulus editor you can generate different types of waves such like sine wave pulses piecewise linear exponential pulses single frequency FM shapes Figure 12 1 shows sine wave of 1 KHz frequency with 10V amplitude File Edit Stmulus Plot View Tools Help example NUM LOCK OFF 1 29ms 1 925675676 Wstat 19 Stimulus Editor g FIGURE 12 1 STIMULUS EDITOR e Model editor As we know it is model definition generator for PSpice to use during simulation This can be generated by standard data sheet of a particular device This will display device characteristic curves so you can verify the 189 behavior of the device As you finish editing of you part it will automatically create part which can be directly used as a part in design Figure 12 2 shows how to create model in model editor 5 7415 OrCAD Model Editor 741500 File Edit View Model Plot Tools Window Help Models List Model Name Type Creation Date Time interface and model names optional DPWR SG DPWR DGND S G DGND params MNTYMXDLY 0 IO LEVEL 0 Q Windows Media Player Eh PSpice Microsoft Word 28 74s OrCAD Model E 2 2 12 52 PM FIGURE 12 2 MODEL EDITOR o Simulation profile configuration To configure simulation profile
169. its are desired they are added by 8251A and removed at receiver Number of data bits parity bits and number of stop bits are programmable Each data byte 1s headed by a start pulse and ended by stop bits 65 o Programming of 82514A To achieve proper data communication with microprocessor and peripheral devices 8251A has to be programmed correctly Figure 4 4 explains logic sequence for proper programming of 8251A MASTER RESET OR SOFTWARE RESET LOAD MODE INSTRUCTION ASYNCHRONOUS MODE YES LOAD FRIST SYNC CHARACTER SINGLE SYNC CHARACTER YES LOAD SECOND SYNC CHARACTER LOAD COMMAND INSTRUCTION lt 5 TRANSMIT DATA SINGLE SYNC CHARACTER FIGURE 4 4 FLOWCHART SHOWING LOGICAL SEQUENCE OF PROGRAMMING 8251 66 Mode instruction format for synchronous and asynchronous and command word format are described in Figure 4 5 and Figure 4 6 respectively These Figures are self explanatory Baud rate Sync mode Async mode x1 Async mode x16 Async mode x64 Character length 5 bits 6 bits 7 bits 8 bits parity control 0 No parity 0 Odd parity 111 Even parity framing contor FIGURE 4 5 MODE WORD FORMAT Status word 15 of 8 bits Each bit provides status of signal Following explai
170. k Howard W Sams amp Co Inc 1980 Walter Bosshart Printed Circuit Board Design and Technology Tata McGraw hill Publishing company Limited New Delhi 1993 Apart from the above books book on SDK 85 microprocessor trainer kit was found useful The details of the book are as follow suggested us to following useful web site 25 Borivaje Furht Himansu Parikh Microprocessor interfacing communication using the Intel SDK 85 Prentice Hall January 1986 We also used the internet facility to find out best useful this work This W 1 TO W 28 http docs hp com en B6057 96002 ch04 html http groups google co in groups dir hl en amp sel 0 16823622 16823610 http groups google co in sci electronics design Ink hppg amp hl en http linuxassembly org http tech groups yahoo com group emu8086 http tech groups yahoo com group win32 nasm users http www 2cpu com http www 8052 com http www brothersoft com Home Education Science 8085 Simulatot _19818 html http www chip architect com Editor In Chief McGraw hill publishing inc N Y http www clickon cpu com http www cpu museum com http www cpu museum net http www datasheetcatalog com http www emu8086 com http www emulation com http www emulators com pentium4 htm http www freemware org http www ieee org http www intel com http www microprocessor sscc ru
171. kumar Khar Mr Jaipalsinh Zala and Mr Hemanshu Vachhani for there moral support during my breakdowns and discussion on different topics am thankful to Mr Manishbhai R Pandya Mr Taresh P Bhatt for their help to cheer up me in my tense and problematic days am thankful to Mr Manishbhai for help me at Department of Electronics for providing me help at laboratory work Last but not list am thankful to Mrs Kirenben H Pandya madam and Miss S H Pandya for their help and moral boosting in tense matter At the last am again thankful to my GOD LORD SHIVA who gives me Power and strength to gain this higher degree of education and to fight against those problems to come over 1 am thankful to Lord Shiva for his blessings Thank you all of you who help me during this period of education Maulin Chandrakant Nanavati Contents Section 1 AIMS AND TOOLS Title Quote Dedicated to Certificate Acknowledgement luglio i D M Objective of the present work asa EET RRRTERCREUREREEET PARES Basics of microprocessor 8085 INMMOUUCHON Major blocks of microprocessor 8085 General ICAU CS ees sae DEScripllOlisoses es s SES SRCUESEVERPRES E Pin descripto g s mu 9 358 309 3 9 356 939 2928 Input Output devices of microprocessor 8085 82C55A Programmable Peripheral Interface Functional description
172. le CURRENT STATEMENT IAC34AC5A 5 AMP IAC 34 AC9 A 60 DEG AC out put variable AC analysis output variable are sinusoidal quantities and can be represented as complex numbers An output variable can have magnitude 195 phase group delay real and imaginary part The common suffix parts of output variable are listed below Suffix Meaning none Peak magnitude M Peak magnitude DB Peak magnitude in decibels P Phase in radiance G Group delay R Real part I Imaginary part Voltage output Below listed common statements are useful in voltage output V lt NODE gt V Nx Ny V lt gt Vx NAME Vxy NAME name Vz NAME Using above particular statements VM 6 VM 8 12 VDB R1 VP D1 VCM Q4 VDSP M6 VBP T1 VR 2 3 VIQ 3 Voltage at node with respect to ground Voltage at node X with respect to node Y Voltage across two terminal devices name Voltage at terminal X of three terminal device name Voltage across terminal X and Y of three terminal device Voltage at part Z of transmission line lt name gt common statements and suffix we can understand some Magnitude at voltage at node 6 with respect to ground Magnitude at voltage at node with respect to node 12 Db magnitude of voltage across resistor where terminal X 15 assumed more positive then Y as shown in below figure Phase of anode voltage of diode D1 with respect to cathode Magnitu
173. ll four ports in the 89C51 are Bi Directional Each consists of a latch Special Function Register PO through P3 an output driver and an input buffer The output drivers of Ports 0 and 2 and input buffers of Port 0 are used in accesses to external memory All the Port 3 pins are multifunctional They are not only port pins but also serve the functions of various special features Figure 3 4 shows the structure of and its components INTERNAL CPU BUS WRITE TO LATCH FIGURE 3 4 89 51 STRUCTURE The other ports P2 and P3 are basically the same except with extra circuitry to allow their dual functions PO 1s also having the same structure but without load as shown in figure 3 4 The 89C51 ports have both the latch and buffer Now the question 15 In reading the port are we reading the status of the latch It totally depends on which instruction we are using Therefore when reading the ports there are two possibilities 1 Reading the input pin or 2 Reading the latch To make any bits of 89C51 an input port we first must write a 1 logic high to that bit Look at the following sequences of events to see why e READING THE INPUT PIN To make any bits of 89C51 an input port we first must write a 1 logic high to that bit Look at the following sequences of events to see why 1 By writing 1 to the port bit it is written to the latch and the D latch has high on its Q Therefore Q 1 and Q 0 57
174. ly communicate with machine There are many applications in which keyboards are used like Electronic Locks EPROM Programmers and many Test Instruments This chapter provides the one of the perspective to add keyboard to the microcontroller based system 71 Basics of Keyboard Keyboard used in this experiment 15 4x10 matrix keyboard An 8x5 matrix keyboard is arranged into 4x10 matrixes This arrangement will provide a compact 40 key 4x10 matrix keyboard which can be easily implemented to any application Figure 7 1 shows the 8x5 matrix arrangement Figure 7 2 shows the 4x10 matrix arrangement for the 40 keyboard This will provide the internal as well as the final pictorial representation of the keyboard P0 0 c Ci lt cr lt lt vi lt lt c Figure 7 1 8X5 matrix arrangement of Keyboard 112 reps pepe Te pep po El FIGURE 7 2 4x10 MATRIX FOR 40 KEY KEYBOARD Thirteen control lines are shown in Figure 7 2 which are interfaced with the microcontroller Each key 1s connected to its corresponding two control lines one row side and one column side These thirteen control lines are divided into row and column signals One to Five control lines are controlling the columns and Six to Thirteen are for the rows compare this with Figure 7 1 See the numbers like 1 13 1 12 2 13 5 8 shown in Figure 7 2 These numbers show that when the user pr
175. ments or dots wide and eight segments tall The module forms characters by turning on the appropriate segments in a character position LCD s are available In several sizes 1x16 1 line of 16 characters 2x16 and 2x20 are some popular sizes used in products In this chapter emphasis on LCD interface with microcontroller based system 15 done 92 BASICS OF LCD MODULE USED In this experiment 1x16 LCD module is used Table 9 1 summarizes the signals in the 1x16 LCD modules SYMBOL INPUT OUTPUT FUNCTION INPUT SIGNAL GROUND INPUT SUPPLY VOLTAGE 45V INPUT CONTRAST ADJUST REGISTER SELECT 1 DATA 0 INSTRUCTION INPUT REGISTER BUSY FLAG ADDRS COUNTER INPUT READ 1 WRITE 0 SELECT INPUT ENABLE INPUT OUTPUT 0 INPUT OUTPUT DATA BIT 1 INPUT OUTPUT DATA BIT 2 INPUT OUTPUT INPUT OUTPUT 4 INPUT OUTPUT 5 INPUT OUTPUT 6 INPUT OUTPUT 7 INPUT BACKLIGHT ANODE INPUT BACKLIGHT CATHODE TABLE 9 1 SIGNALS OF 1X16 LCD MODULE LCD modules use backlighting to allow viewing in dim light A module may be reflective which does not use backlight Transmissive which must use backlight or transflective which may use backlight or not LCD module is a specialized microcontroller in it self It contains its own RAM and ROM and executes the instructions shown below 1n Table 9 2 140 INSTRUCTION 07 Ds Da
176. mmunication between two identical but independent kits are studied The experiment 15 divided into two parts 1 One kit working as a transmitter while another kit working as a receiver i e One way communication 2 Both the kit are working as a receiver and transmitter 1 Two way communication The circuit details and interfacing remains same as discussed in previous two experiments EXPERIMENT SERIAL COMMUNICATION BETWEEN TWO KITSE Apparatus 8085A based microprocessor kits a single power supply 5V 12V and CRO Procedure For data transfer between two 8085A based microprocessor kits using RS 232 interface the two kits are connected using RS 232 connectors as shown in Figure 4 10 75 MASTER KIT SLAVE KIT FIGURE 4 10 CONNECTION OF THE RS 232 SIGNALS BETWEEN TWO e PROGRAM FOR ONE WAY COMMUNICATION KITS In this case two separate programs are written for both kits The two programs are identified as master and slave program MASTER PROGRAM Mnemonics MVI A 00H OUT 21H OUT 21H OUT 21H MVI A 40H OUT 21H MVI A FE OUT 21H MVI A 25H OUT 21H MVI B 09H LXI H 8100H IN 21H ANI 01H JZ EMPTY EMPTY Memory address 76 8000 8002 8004 8006 8008 800A 800C 900 9010 8012 8014 8016 8019 801 801D Machine codes 3E 00 D3 21 D3 21 D3 21 3E 40 D3 21 3E FE D3 21 25 D3 21 06 09 21 00 81 DB 21 E6 01 CA 1A 80 RTRAN
177. mulator s memory in write protected mode 10 Memory Test MT command This commands tests a block of memory Syntax MT range If any of the memory location in range 15 bad or does not exist ICE displays an error request Memory verification failure 9 XX XX and stops memory testing Example MT 0 174 INPUT OUTPUT COMMNADS 1 Input port 1 command This command 15 useful to read the contents of specified port Syntax I port count Here port means port address Count specifies the numbers of times the port is to be read Example I F8 In the example count is not specified 2 Output port O command This command sends a value of a byte to an output port Syntax port byte value Here port specifies the output port address bytevalue is data byte to be directed to the port Example O 2F 4F REGISTER RELATED COMMANDS 1 Register R command Displays or alters the contents of one or more CPU registers Syntax Register name value Value specifies the register value to store valid register names A B C D E H L SP PC and F Example R B 40 F Flag register will display flig bit status as follows Flag name set Clear Sign NG Negative positive Zero ZR NZ Auxiliary AC NA Parity PE Even PO Odd Carry CY NC R command without any parameter will display contents of all registers and flags 175 TARGET CONTORL COMMANDS 1 Ena
178. nged by manipulating the values of the 89 5175 Special Function Registers SFRs SFRs are accessed as if they were normal Internal RAM The only difference is that Internal RAM 15 from address 00h through 7Fh whereas SFR register exist in the address range of 80h through FFh Each SFR has an address 80h through FFh and a name Table 3 2 contains a list of all the SFRs and their addresses 53 Accumulator B Register Program Status Word Stack Pointer Data Pointer 2 Bytes Interrupt Priority control Interrupt Enable control Timer Counter Mode Control Timer Counter Control Timer Counter 0 High Byte Timer Counter 0 Low Byte Timer Counter 1 High Byte Timer Counter 1 Low Byte Serial Control Serial Data Buffer Power Control Bit Addressable TABLE 3 2 LIST OF SFRS AND THEIR ADDRESSES e ACCUMULATOR ACC 15 the Accumulator register The mnemonics for Accumulator Specific instructions however refer to the Accumulator simply as A e REGISTER The B register is used during multiply and divide operations For other instructions it can be treated as another scratch pad register e RREGISTER The registers are a set of eight registers that are named R2 R3 R4 R5 R6 and R7 Along with accumulator R registers are very important helper registers Accumulator alone would not be very useful if 1t were not for these R registers They are used to temporarily store values e PROGRAM STATUS WORD The
179. nnected to VCC and BL2 cathode connected to GND and 10k pot is connected to set the contrast of the LCD e Connection Details of LCD Module with AT89C51 Microcontroller Ports Signal from J1 89 51 Signal from J1 ATS89C51 GND GND D2 PI2 Vcc Vcc D3 P1 3 RS 3 2 D4 P1 4 R W p3 3 D5 P1 5 E 3 4 D6 P1 6 DO P1 0 D7 P1 7 DI P1 1 144 SOFTWARE FLOWCHART Start gt PROVIDE DELAY BETWEEN WORDS CALL INIT_LCD CALL RET_HOME CALL CLEAR_LCD CALL CLEAR LCD 80H AND REPEAT THE PROCEDURE SAME FROM SECOND BLOCK SET CURSOR TO 80H LCD ENABLE HI TO LOW PULSE SECOND WORD FETCHED AND DISPLAYED GIVE TIME TO LCD FOR DATA CALL WAIT LCD START GIVING DATA JUMP START TO LCD CALL WRITE TEXT FROM 80 TO 87H GIVE SOME TIME TO DATA TO BE FETCHED SET CURSOR TO 0 LCD ENABLE HI TO LOW PULSE GIVE TIME TO LCD FOR DATA CALL WAIT LCD START GIVING DATA TO LCD CALL WRITE TEXT FROM 0C0H TO 0C7H FIGURE 9 3 SOFTWARE FLOW CHART 145 LCDMODULE SOFTWARE Software for LCD initialization and data write is self explanatory and is given as below Name plate using LCD LCD initialization and DATATI write program Main program MOD51 DBO EQU P1 0 Equate P1 P1 0 to P1 7 EQU P1 1 to DB0 DB7 DB2 EQU P1 2 DB3 EQU 1 3 DB4 EQU 1 4 DB5 EQU 1 5 DB6 EQU 6 DB7 EQU P1 7 EN EQU P3 4 Equate P3 P3 2 to P3 4 RW EQU P33 to EN RW RS respectively RS EQU P3 2 DATAI EQU
180. ns each bit of status word Status word 1s shown in figure 4 6 DO TxRDY TxRDY status bit is not conditioned by CTS or TxEN DI RxRDY Receiver Ready D2 TxEMPTY Transmitter Empty Means output register of transmitter 1s empty no data is being sent if TxEN 1 D3 PE Parity Error PE flag is set whenever parity error 15 detected 67 D4 OE Overrun Error The OE flag is set when the microprocessor does not read a character before the next one becomes available 1n the receiver s buffer D5 FE Framing Error Asynchronous mode only The FE flag 15 set when a valid stop bit 1s not detected at the end of every character Note that PE OE and FE errors can be reset by ER bit of command instruction and they do not inhibit operation of the 8251A D6 Syndet Brkdet Same as I O pin D7 DSR Data Set Ready This status bit indicates that DSR is at a zero level TRANSMITTER ENABLE 1 ENABLE DISABLE wt DATA TERMINAL READY 1 WILL FORCE DTR OUT PUT TO BE ZERO b RECEIVER ENABLE 1 ENABLE SEND BREAK CHARACTER 1 TxD LOW O NORMAL ERROR RESET 1 RESET ERROR FLAGES PE OE AND FE REQUEST TO SEND 1 WILL FORCE RTC TO LOW we INTERNAL RESET 1 RETURNS 8251 MODE INSTRUCTION STATUS WORD FORMAT EXTERNAL HUNT MODE 1 ENABLES SEARCH FOR SYNC CHARACTER FIGURE 4 6 COMMAND WORD FORMAT AND STATUS WORD 68 o Interfacing of 8251
181. nstruction Definition The 8251A can be used for either Asynchronous or Synchronous data communication To understand how the Mode instruction defines the functional operation of the 8251A the designer can best view the device as two separate components one Asynchronous and other Synchronous sharing the same package The format definition can be changed only after a Master Chip Reset For explanation purposes the two formats will be isolated When parity 15 enabled it is not considered as one of the data bits for the purpose of programming word length The actual parity bit received on the Rx Data line cannot be read on the Data Bus In the case of programmed character length of less then 8 bits the least significant Data Bus bits will hold the data unused bits are don t care when writing data to the 8251 and will be zeros when reading the data from the 8251A Below Figure 2 14 shows Mode instruction format for Asynchronous Mode 37 D7 De D5 D4 D3 D2 Di Do E EE Lad BAUD RATE FACTOR CHARACTER LENGTH 5 BITS 6BITS 7BITS 8BITS PARITY ENABLE 1 ENABLE 0 DISABLE EVEN PARITY GENERATION CHECK 1 ENABLE 0 DISABLE NUMBER OF STOP BITS O ERE _ O 1 1 ONLY AFFECTS Tx Rx NEVER REQUIRES MORE THAN ONE BIT FIGURE 2 14 ASYNCHRONOUS MODE INSTRUCTION FORMAT e Asynchronous Mode Transmission Whenever a data character is sent by the CPU the 8251A automa
182. nterrupt Final service result location routine address TRAP RST 7 5 8200 RST 5 5 8500 8090 INTA 8800 8400 TABLE 6 8 FOR INSPECTING MEMORY LOCATIONS mw EM ee WW In this experiment at the result location one must find 60H data for successful execution of service routines 63 TO VERIFY THE PRIORITIES OF INTERRUPT The hardware and other details remains as discussed 6 2 Other details are as follows 109 o PROCEDURE Connect all connections of interfacing module with microprocessor kit Now press switch SW6 reset key This will generate all interrupt simultaneously But as per hardware priority TRAP assumes highest priority So its service routine will be executed Note that in our case TRAP 15 not available To check priority of RST 7 5 disconnect TRAP Now press SW6 only the service routine of RST 7 5 will be executed since RST 7 5 assumes highest priority You can verify this by examining location 8200 Similarly one can check priority of any interrupts 64 TOUNDERSTAND THE MASKING OF INTERRUPTS The hardware and other details for this experiment do not change much more Other details are as follows o PROCEDURE Use instruction SIM to mask the RST 7 5 RST 6 5 and RST 5 5 Disconnect TRAP Let all other interrupts be connected Now enter following program from 8000 to onward as main program START MVI A OFH 9000 SIM 8002 30 El 9003 JMP START
183. ntrol words must be sent out by the CPU to initialize the 8251A to support the desired communications format These control words will program the BAUD RATE CHARACTER LENGTH NUMBER OF STOP BITS SYNCHRONOUS or a SYNCHRONOUS OPERATION EVEN ODD OFF PARTY etc in the 35 synchronous mode operations are also provided to select either internal or external synchronization Once programmed the 8251A is ready to perform its communication functions The TxRDY output 15 raised HIGH to signal the CPU that the 8251A is ready to receive a data character from the CPU This output TxRDY 15 reset automatically when the CPU writes a character into the S251A On the other hand the 8251A receives serial data from the MODEM or I O device Upon receiving an entire character the Rx RDY is raised HIGH to signal the CPU that the 8251A has a complete character ready for the CPU to fetch RxRDY is reset automatically upon the CPU data read operation The 8251A cannot begin transmission until the TxENABLE Transmitter Enable bit 15 set in the Command instruction and it has received a Clear To Send CTS input The TXD output will be held in the marking state upon Reset Programming the 251A Prior to starting data transmission or reception the 8251 must be loaded with a set of control words generated by the CPU These control signals define the complete functional definition of the 8251A and must immediately follow a Reset operation internal or exte
184. ntrolling variables A B and C with output Y source Below Figure 12 7 shows a source that 1s controlled by A B and C the output source takes the form of Y f A B C Where Y can be voltage or current and A B amp C can be voltage or current or any combination 200 Here Figure 12 7 NC NC N and N are positive and negative nodes with respective controlling sources and output source Voltage Controlled Voltage sources The symbolic representation of Voltage controlled voltages source is shown in figure 12 7 a Where E 15 taken as a linear form Vout HI c Current controlled Voltage source d Current controlled voltage source FIGURE 12 7 DC DEPENDENT SOURCES common statement for linear form of voltage controlled voltage source 15 as follow E name N N NC NC voltage gain value Where N N NC and NC are positive and negative nodes of the respective controlling voltage similarly for nonlinear form the common statement can be as follow E name N N POL Y value lt lt controlling node controlling node gt gt pairs polynomial coefficients values gt The POLY source was described as above The number of controlled node 15 twice the number of dimensions Output and controlling nodes could be the same for particular node which could be more then one Some typical statement for Voltage Controlled Voltage sources EAB 124610 201 EVOLT 4 7 20
185. o 4005H will be as follows 4000 00 START NOP 4001 3E FF MVI A FFH 4003 C3 00 40 JMP START Usually all kits a key in keyboard to run the program Such keys are Go or Run Press Go key The routine for will ask for program address 160 Enter the address 4000H This will make PC to contain 4000h Hence address pins will have logic states as shown below during the first T state Pin Logic states Pin Logic states Ais 0 AD 0 A14 1 0 A13 0 ADs 0 A12 0 AD 0 A 0 0 A10 0 AD 0 Ao 0 0 Ag 0 ADo 0 Program Address 4000H In order to execute whole program 8085 will have to fetch code of first instruction 1 NOP for this 8085 will generate an OF Opcode Fetch cycle Since AD ADopins are multiplexed address on these pins 15 to be stored latched in other external latch IC For this 8085 generates ALE signal which generally enables latch IC Hence when stable address 4000H 15 on address pins ALE 15 generated It lasts almost half the time of clock pulse This clock pulse we call T Now to understand following write up consider Figure 10 2 To fetch code 00 for NOP 8085 will generate RD control signal in T gt clock cycle This will enable memory chip to give out code 00 from location 4000H on data bus Do D So after some time when RD becomes low AD7 ADp pins will receive following logic states AD ADs AD AD AD 0 0 0 0 0
186. o parts one area for a state list display and another for timing display The topmost line of the state list always 15 the leftmost point display in the timing waveform but selections scroll together when moving through the data Cursors appear at the same data positions in the state list and timing sections 158 All above three options can have more setup parameters e g timing mode may offer the name to be associated with channels D Trigger The technique of starting the analyzer at a specific point 15 called triggering There are two triggering methods a Edge triggering Here one of the parallel inputs is selected as the trigger signals and the logic level desired 15 selected The hardware 15 started and when desired trigger occurs a transition from low to high for example the logic analyzer starts recording the data This method 15 convenient in simple situation and 15 easy but 15 not sufficient the case of complex problems where the trigger input may have transition several times in the program b Word recognition Here the user selects which logic level each input must be in to trigger the logic analyzer Unused or don t care inputs may be designated so that either logic level of the input will trigger the analyzer One has to maintain the correspondence of input channel and the trigger word bits In other words one should find out the MSB of trigger word represents the channel 0 or highest available channel
187. o power supply The RS 232 connector details are noted and CTS pin is identified and connected to 5V to make CTS 0 This enables 8251A transmissions A small program is run to reset 8251A MVIA OOH OUT 21H OUT 21H OUT 21H MVIA 40H OUT 21H In the above program first two instructions select synchronous mode Next two instructions select two sync bytes as zeros Last two instructions are used to perform software reset by making IR bit 1 in command word To configure 8251A as per above specifications mode control word would be 52 51 2 Li B I I 0 0 I I 0 I CDH Command word enables transmitter for data transmission Generally Error Reset 15 also made high So command word becomes 71 EH IR RTS ER SBRK RxE DTR 0 0 0 I 0 0 0 I To start data transmission the CPU fills the buffer register of transmitter with data For this microprocessor checks the status of 8251A by reading its status word to confirm that buffer is empty This can be done by IN PORT instruction i e IN 21H and the remaining program for data transmission is as follows MVIA CDH OUT 21H MVIA OUT 21H IN 21H READ STATUS WORD ANI AND CHECK RXRDY 1 JZ EMPTY IFRXRDY 0 WAIT MVIA AA MOVE DATA TO A OUT 20H OUTPUT FOR TRANSMISSION JMP EMPTY TRANSMIT CONTINUOUSLY The complete program looks like this Mnemonics Memory address Machine codes MVIA 00H 8000 3E 00 OUT 21H 8002 D3 21 O
188. oaurashtra University Re Accredited Grade by NAAC CGPA 2 93 Nanavati Maulin C 2007 The development of Advance Experiments useful to the students of Electronics field thesis PhD Saurashtra University http etheses saurashtrauniversity edu 1d 912 Copyright and moral rights for this thesis are retained by the author A copy can be downloaded for personal non commercial research or study without prior permission or charge This thesis cannot be reproduced or quoted extensively from without first obtaining permission in writing from the Author The content must not be changed in any way or sold commercially any format or medium without the formal permission of the Author When referring to this work full bibliographic details including the author title awarding institution and date of the thesis must be given Saurashtra University Theses Service http etheses saurashtrauniversity edu repository sauuni ernet in The Author THE DEVELOPMENT OF ADVANCE EXPERIMENTS USEFUL TO THE STUDENTS OF ELECTRONICS FIELD Thesis Submitted to the Saurashtra University Rajkot For The Degree of Doctor of Philosophy Science Electronics By Maulin Chandrakant Nanavati Department Of Electronics Saurashtra University Rajkot 360 005 Gujarat India Research Supervisor Dr H N Pandya Head Department Of Electronics Saurashtra University Rajkot 360 005 Gujarat India MAY 2007 CErudition c
189. ock Generator No external inputs or outputs are reference to CLK but the frequency of CLK must be greater then 30 times the Receiver or Transmitter data bit rate WR Write A LOW on this input informs the 8251A that the CPU is writing data or control words to the 8251A RD Read A LOW on this input informs the 8251A that the CPU 15 reading data or status information from the 82514A control Data This input in conjunction with the WR and RD inputs informs the 8251A that the word on the Data Bus is either a data character control word or status information control status 0 data 09 8251A DATA gt DATA BUS 0 DATA BUS gt 8251A DATA STATUS DATA BUS STWSODARES m CI p WARS SONO 31 CS Chip Select A LOW on this input selects the 8251A No reading or writing will occur unless the device is selected When CS is high the Data Bus is in the float state and RD and WR have no effect on the chip e Modem Control The 8251A has a set of control inputs and outputs that can be used to simplify the interface to almost any modem The modem control signals are general purpose in nature and can be used for functions other then modem control if necessary DSR Data Set Ready The DSR output signal is a general purpose 1 bit inverting output port Its condition can be tested by the CPU using Status Read operation The DSR input is normally used to test modem cond
190. ocontroller Contents Section 4 DEVELOPMENT TOOLS Chapter 10 Advance experiments on logic state analyzer 154 lilloi HOS 155 Debugging of microprocessor kit using logic state analyzer a simple laboratory experiment 160 Chapter 11 Advance experiments on 168 erngereu rentem 169 Using In circuit emulator in the laboratory 169 Chapter 12 Advance experiments Pspice 186 io if 9 187 Commands of Pspce 204 ane cove aka ua 205 toes ccd teow sews 206 PO ERES ERES 206 DC gt Clu e E eds erai ine ES PETS 217 Digital eara d 223 ici rrP mm 241 Appendix Datasheet a a 243 MC1488 Quadruple line drivers MC1489 Quadruple line recelvers Appendix B 040004045 RCNH 244 III Figures Renee ee nee eee 8 Silo uama 14 PUHU 16 EEUU 17 luli PP TR 18 PIQUED ee 19 Sur
191. oltage Vcc at or below 25 C free air temperature see Notes 1 and 2 15 V mPULVOHaJE Vj riina NEE R AAA 15Vto7 V VO TUN RENE ng 15 V to 15 V Continuous total power dissipation see Note 2 See Dissipation Rating Table Operating free air temperature range Ta SN55188 55 C to 125 C MC1488 SN75188 0 C to 70 C Storage temperature Tango Teig etur bx ie duh ica pupa quq aa 65 C to 150 C Case temperature for 60 seconds FK package 260 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds Dor N package 260 C Lead temperature 1 6 mm 1 16 inch from case for 60 seconds J or W package 300 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 Allvoltage values are with respect to the network ground terminal 2 Foroperation above 25 C free air temperature refer to th
192. on Rating Table Operating free air temperature range Ta SN55189 SN55189A 55 C to 125 C MC1489 MC1489A SN75189 SN75189A 0 C to 70 C Storage temperature range 4 65 C to 150 C Case temperature for 60 seconds FK package 260 C Lead temperature 1 6 mm 1 16 inch from case for 60 seconds J or W package 300 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds D or NS package 260 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 All voltage values are with respect to the network ground terminal DISSIPATION RATING TABLE TA lt 25 C DERATING FACTOR TA 70 C TA 125 C POWER RATING ABOVE TA 25 C POWER RATING POWER RATING 950 mW 7 6 mW C PACKAGE 1375 mW 11 0 mW C 1375 mW 11 0 mW C 1150 mW 9 2 mW C 625 mW 4 0 mW C 1000 mW 8 0 mW C t In the J package SN55189 and SN55189A chips are either silver glass or alloy mounted recommended operating conditions 35 TEXAS INS
193. on the oscilloscope For this experiment we have used 8251A chip embedded in the microprocessor kit ESA 85 Hence it is necessary to understand the basics of 8251A and its interfacing with the microprocessor kit o Basics of 8251A 8251A is made of following units 1 Data bus buffer 2 Read write control 3 Modem control 4 Transmitter section 5 Receiver section Data bus buffer accepts data and commands from microprocessor and passes them to 8251A Similarly the status word data bytes assembled by 8251A are passed to microprocessor through this unit Read write unit is driven by microprocessor control signals It has RD WR RESET CS and C D pins Out of these RD WR RESET and CS have conventional meaning C D pin when HIGH declares that the byte on data bus buffer 1s a command or status word and 1f LOW the conformation of data on data bus Modem control unit has few control signals DSR Data Set Ready DTR Data Terminal Ready RTS Request To Send and CTS Clear To Send RTS is command controlled while DSR can be status checked The transmitter section works as shown in Figure 4 1 Transmit data OUTPUT SHIFT REGISTEF TRANSMITTER BUFFEF TxC Transmitter clock REGISTEF Parallel data TRANSMITTER CONTROL LOGIC TxRDY Transmitter Ready TxE Transmitter empty FIGURE 4 1 TRANSMITTER SECTION OF 8251A Transmitter accepts parallel bytes from microprocessor via internal bus of 8251A These b
194. operation of the decoder may be further clarified from its input output relationships listed in below Figure 12 22 Observe that the output variables are mutually exclusive because one output can be equal to 1 at any 223 one time Input and Output signals are shown in Figure 12 23 and 12 24 simultaneously Inputs Outputs ESRSESLAILSALALILALIESLS TABLE 12 1 INPUT OUTPUT RELATIONSHIPS FOR 3 TO 8 LINE DECODER CIRCUIT INPUT WAVEFORM FOR X Y AND Z uS Stimulus Editor 4bitmagcomp stl FIGURE 12 22 INPUT WAVEFORM FOR X Y AND Z 224 OUTPUT WAVEFORMS OF 3 TO 8 LINE DECODER SCHEMATIC1 4BITMAGCOMP OrCAD PSpice A D 4bitmagcomp SCHEMATIC1 4BITMAGCOMP active File Edit View Simulation Trace Plot Tools Window Help ay E i i pu Analysis Watch Devices 1 FIGURE 12 23 OUTPUT WAVEFORMS OF 3 TO 8 LINE DECODER CIRCUIT FILE Libraries Local Libraries STMLIB 3to8line stl From PSPICE NETLIST section of pspice91 file nom lib Analysis directives TRAN 0 10005 0 OPTIONS DIGINITSTATE 0 PROBE ANC 3to8line SCHEMATIC1 net INCLUDING 3to8line SCHEMATIC1 net source 3to8line X UIA N00048 N00058 NO0068 DO G DPWR G DGND 74511 PARAMS IO LEVEL 0 MNTYMXDLY 0 X UIB N00078 00058 NO0068 D1 G_DPWR G DGND 74511 PARAMS IO LEVEL 0 MNTYMXDLY 0 X UIC N00048 N00115 NO0068 D2 6 DPWR G D
195. or J3 and J4 of interfacing module After proper hardware connection one can perform various experiments on interrupts 105 62 GENERATE THE INTERRUPT OF CHOICE AND EXECUTE ITS SERVICE ROUTINE o APPERATUS USED Microprocessor kit Interfacing module Power supply o PREPARATION First of all we should develop service routines for different interrupts to understand the aim of this experiment The vectored addresses of all interrupts of 8085A are not having enough space to accommodate any service routine Hence it is a common practice to write JMP instructions at the vectored addresses For present experiment the JMP instruction for the interrupts are as presented in Table 6 7 _ Ll RST 5 5 002C JMP JMP 8500 INTR Vector address of CALL CDCD any RSTn inst Or address indicated In CALL address instruction TABLE 6 7 JUMP INSTRUCTIONS OF VECTORED ADDRESSES Enter the following program at location 8000H onward to enable all interrupts START MVI A OFH 8000 3E OF SIM 8002 30 El 8003 FB JMP 8004 C3 00 80 START From table 6 7 one can learn that if interrupt RST 7 5 takes place the instruction JMP FEI2 written at 003C in the EPROM area will take control at RAM 106 location FEI2 The codes of these JUMP instructions are permanently stored in EPROM Hence one cannot change these instructions But looking at these new locations 1 FEI2 and FE06 in table 6 7 we find th
196. or the file 8255 SW ASM and press enter This will ask following Output Filename We simply press enter This will display following Active commands Ctr S Stop Output Ctrl Q Start Output Esc C Stop Assembly Esc T Terminal Output Esc P Printer Output Esc D Disk Output Esc M multiple Output Esc N No Output 72500 A D 8085 Macro Assembler Version 4 Input filename CAPCICEAS255 SW ASM Output filename 8255 SW OBJ 183 Lines assembled 12 Assembly Error 0 C PCICE X8085 gt One can check the listing of the assembled code by typing EDIT 8255_SW LST At this stage we have assembled the codes of testing program in the filename 8255 SW OBJ After assembling code we have to use linker to link the file For that type following command C PCICE x8085 link cr Following is the dialog for the linker 2500 A D Linker copyright C 1985 version 4 01A Input Filename Enter here proper filename e g C PCICE 8255_sw OBJ lt cr gt Enter offset for code Enter address 8000 here lt cr gt Input Filename This asks another filename to be linked if so In our case only one file is required so press enter lt cr gt Output Filename lt cr gt Library Filename lt cr gt Options D S A M X H E T 1 2 3 lt cr gt default lt cr gt Following 15 the display LOAD 2 gt k gt KE F S
197. orms 35 TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MC1489 MC1489A SN55189 SN55189A SN75189 SN75189A QUADRUPLE LINE RECEIVERS SLLS095D SEPTEMBER 1973 REVISED OCTOBER 1998 TYPICAL CHARACTERISTICS SN65189 SN75189 OUTPUT VOLTAGE vs INPUT VOLTAGE Rc 5 kQ Rc 13 kO VC 25V VC 25V V Vcc 5V TA 25 See Figure 1 2 1 0 Input TRA V Vo Output Voltage V Figure 5 5 65189 SN75189A OUTPUT VOLTAGE vs INPUT VOLTAGE 5 TA 2 259 See Figure 1 Vo Output Voltage V Input Voltage V Figure 6 4 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 MC1489 MC1489A SN55189 SN55189A SN75189 SN75189A QUADRUPLE LINE RECEIVERS SLLS095D SEPTEMBER 1973 REVISED OCTOBER 1998 TYPICAL CHARACTERISTICST Input Threshold Voltage V Amplitude V 4 100 75 50 25 0 INPUT THRESHOLD VOLTAGE INPUT THRESHOLD VOLTAGE VS VS FREE AIR TEMPERATURE SUPPLY VOLTAGE 25 50 75 100 125 150 TA Free Air Temperature Figure 7 SN75189 NOISE REJECTION Vcc 25V TA 25 See Note A 10 40 100 400 1000 400 ty Pulse Duration ns e 0000 NOTE A Maximum amplitude of a positive going pulse that starting from 0 V will not cause a change in the output level Figure 9 Input Threshold Voltage V Amplitude V co
198. r H N Pandya Debugging microprocessor kit using logic state analyzer a simple laboratory experiment Lab Experiment LE Bangalore India December 2003 Vol 3 No 4 Pg 312 R P 9 Mr M C Nanavati Dr H N Pandya Using In circuit Emulator in the laboratory Lab experiment LE Bangalore India March 2006 Vol 6 No Pg 39 e WEBSITES 1 http docs hp com en B6057 96002 ch04 html W 2 http groups google co in groups dir hl 2en amp sel 0 16823622 16823610 W 3 http groups google co in sci electronics design Ink hppg amp hl en W 4 http linuxassembly org W 5 http tech groups yahoo com group emu 8086 W 6 http tech groups yahoo com group win32 nasm users W 7 http www 2cpu com W 8 http www 8052 com 246 Appendix B W 9 http www brothersoft com Home Education Science 8085 Simulatot 1981 8 html W 10 http www chip architect com W 11 http www clickon cpu com W 12 http www cpu museum com W 13 http www cpu museum net W 14 http www datasheetcatalog com W 15 http www emu8 amp 086 com W 16 http www emulation com W 17 http www emulators com pentium4 htm W 18 http www freemware org W 19 http www 1eee org W 20 http www intel com W 21 http www microprocessor sscc ru W 22 http www old computer com museum computer asp st 1 amp c 805 W 23 http www orcad com W 24 http www rdos net sim W 25 http www thefree
199. rate at which the character 15 to be transmitted In the Synchronous transmission mode the Baud Rate 1x is equal to the TxC frequency In Asynchronous transmission mode the baud rate 1s a fraction of the actual TxC frequency A portion of the mode instruction selects the factor it can be 1 1 16 or 1 64 the TxC The falling edge of TxC shifts the serial data out of the 9251 Receiver Buffer receiver accepts serial data converts this serial input to parallel format checks for bits or characters that are unique to the 33 communication technique and sends an assembled character to the CPU serial data 15 input to RxD pin and 15 clocked in on the rising edge of RxC Receiver control This function block manage all receiver related activity which consists of the following features The RxD initialization circuit prevents the 8251A from mistaking unused input line for an active low data line in the break condition Before starting to receive serial characters on the RxD line a valid 1 must first be detected after chip master Reset Once this has been determined a search for a valid low Start bit 1s enabled This feature 15 only active the asynchronous mode and is only done once for each master Reset The Flase Start bit detection circuit prevents false starts due to a transient noise spike by first detecting the falling edge and then strobing the normal center of the Start bit RxD low Parity
200. resentation of this source is shown in figure 9 D Its linear form 15 H General statement for this 1s H name N N VN lt transresistance value Where N N are positive and negative nodes of the respective voltage sources VN is voltage source through which controlling current flows The nonlinear statement 15 202 H name N N POLY value VN2 polynomial coefficients values gt Dc output Variables Pspice has some unique features for printing or plotting output voltage or current The voltage output and current output 15 two divisions of the output variables The variable can be assigned the symbol of a device to identify whether the output voltage or current 15 across the device or through the device Few two and three terminal device with their symbols are listed below Device symbol Element Number of terminals C Capacitor Two D Diode Two L Inductor Two R Resistor Two Independent voltage V Two source Three D Drain B MESFET S Source G Gate Three D Drain J JFET G Gate S Source Three C Collector Q BJT B Base E Emitter Voltage output The common statement is as same as discussed in AC command voltage output Current output The common statement is as same as discussed in AC command current output 203 122 COMMANDS FOR PSPICE The common commands for AC and DC analysis are as shown below COMMAND OUTPUT PRINT Print Plot PROBE
201. responding source statements including addresses and byte values The disassembled code looks like a listing for an assembled file Syntax U range Example U 100 10 COMMANDS TO MANAGE BREAK POINTS By setting breakpoints the ICE 15 controlled in execution of programs breakpoint is an address that stops program execution each time the address 1s encountered By setting breakpoints at key addresses in the program one can examine the status of memory or bus at that point The commands listed below control the break points Commands Action Breakpoint set BS Sets one or more breakpoint s Breakpoint clear BC Clears one or more breakpoint s Breakpoint disable BD Disables breakpoints Breakpoint enable BE Enables breakpoints Breakpoint List BL Lists all breakpoints PROGRAM EXECUTION CONTROL COMMANDS In this category cycle step CS go G Single step T proceed P command are included 1 Cycle step CS command This command executes a program in steps of execution cycle It stops processor while executing each machine cycle Syntax CS lt address gt Here address specifies the address of the memory area from where the execution has to begin Example CS 100 It exhibits the status of the processor in terms of execution cycle for each byte of program as follows 177 Address Data Status Ext trace bits 100 3E OF 1111 101 90 MR 1111 102 32 OF 1111 2 Single step T command This command execut
202. results of instruction execution are provided in flag register by ALU PIN DISCRIPTION A15 OUTPUT 3 5 PIN NO 21 TO 28 Address bus the most significant 8 bits of the memory address or the 8 bits of the I O address 3 state during Hold and Halt modes AD AD INPUT OUTPUT 3 STATE PIN NO 12 TO 19 Multiplexed address data bus Lower 8 bits of the memory address or I O address appear on the bus during the first clock cycle of the machine state It then becomes the data bus during the second and third clock cycles 3 state during HOLD and HALT modes ALE OUTPUT PIN NO 30 Address latch enable It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals 10 The falling edge of ALE is set to guarantee setup and hold times for the address information ALE can also be used to strobe the status information ALE 15 never 3 stated So S OUTPUT PIN NO 29 amp 33 Data bus status encoded status of the bus cycle So S Cycle 0 HALT 1 WRITE 0 READ 1 FETCH O CO S1 can be used on an advanced R W status RD OUTPUT 3 STATED PIN NO 32 READ indicates the selected memory or I O device 15 to be read and that the data bus 1s available for the data transfer 3 stated during HOLD and HALT WR OUTPUT 3 STATED PIN NO 31 WRITE indicates the data on the data bus 15 to be written into the selected memory or I O device Data i
203. rnal The control words are split into two formats 1 Mode instruction 2 Command instruction Mode instruction This instruction defines the general operational characteristics of the 8251A It must follow a Reset operation internal or external Once the Mode instruction has been written into the 8251A by the CPU SYNC characters or Command instructions may be written Command instruction This instruction defines a word is used to control the actual operation of the 8251A Both the Mode and Command instructions must conform to a specified sequence for proper device operation The Mode instruction must be written immediately following a Reset operation prior to using the 8251A for data communication 36 MODE INSTRUCTION SYNC CHARACTER 1 SYNC MODE SYNC CHARACTER 2 ONLY COMMAND INSTRUCTION DATA COMMAND INSTRUCTION DATA COMMAND INSTRUCTION FIGURE 2 13 TYPICAL DATA BLOCK All control words written into the 8251A after the Mode instruction will load the Command instruction Command instructions can be written into 8251A at any time in the data block during the operation of the 8251A To return to the Mode instruction format the master Reset bit In the Command instruction word can be set to initiate an internal Reset operation which automatically places the 8251A back into the Mode instruction format Command instructions must follow the Mode instruction or Sync characters Mode I
204. rt 63H 8253 U8 Port A Timer 0 15 used in single stepping Timer 1 1s used for baud clock generation Timer 2 1s available to user Signals are available on connector P2 Port B Port C Control Port 8251A at U2 Data port Used for serial communication Command port 10H 11H 12H 13H 20H 21H 8279 at U22 Data port 30H Used for implementing keyboard display Command port 31H interface 8259 at U4 Data port 51H Available to user provides 52H 70H 71H 72H support up to 8 interrupts Command port 8255 4 at U12 Port A Used for reading the DIP switch and for implementing parallel printer interface and audio tape interface Port B Port C 171 TABLE 11 2 ADDRESSING OF ESA85 2 KIT We are now ready to test proper working of kit using PCICE But for that one must know basic commands of PCICE Following is a brief list of all these commands for PCICE made by Electro System Associates Bangalore Command summary All PCICE commands accept parameters except Q command Parameters are separated by commas or spaces MEMORY RELATED COMMANDS 1 Specifying valid address Allocation in memory can be specified by this command A hexadecimal number or a symbol can be used for specifying address If symbol 15 used it should be enclosed by two signs Example Hexadecimal 100 Symbol ToS TL ART 96 Here is a symbol it is CASE SENSITIVE 2 Specifying valid address range There are
205. s busy executing certain program During such times if external devices want the service from 8085A for execution of its dedicated program they inform the processor by the use of interrupts For this the device has to have a connection over any of the interrupt pins There can be more then one devices which be connected with interrupt pins of 8085A o INTERRUPT CHECKING BY 8085 The 8085A does not know at what time which device may put interrupt request This means the device can put interrupt request at any time This 15 why interrupt process is called asynchronous events To take care of such at any time Occurring processes interrupts the 8085A checks during the penultimate clock of every instruction whether any interrupt request has occurred on any interrupt pins or not o RECOGNITION There is a definite way for the interrupt recognition This is different for different hardware pins of 8085A Table 6 1 describes the conditions that have to meet in order for the interrupt requests to be recognized by the 80985 As shown in Table 6 1 a device connected with RST 7 5 pin needs to perform a low to high transition in order to get its interrupt recognized by 8085A While device connected with RST 6 5 RST 5 5 and INTR pins have to maintain a HIGH level on the corresponding interrupt pin till 8085 completes the execution of current instruction The heavy lines in the signal drawings in Table 6 1 explain this situation 9
206. s of 8085A The EPROM 2764A has a pin named OE which helps to read data out This OE pin directly connected with the RD of 8085A Also pin PGM and Vpp are connected with Vcc 45 Figure 2 23 RAM 6264 INTERFACING CIRCUIT FOR 8085A The chip selection is controlled by the decoder 741 5 155 74L S155 is used to select the memory chips 2764 EPROM 6264 RAM and I O chips 8279 and 8255 46 To separate the memory and I O device the output pins of 74LS155 are divided into two groups that is 1YO 1Y2 and are for I O device selection and 2YO 2Y 1 2Y2 and 2Y3 are for memory chip selection 7ALS155 has four enable pins out of which three are active low and one remaining two where one 15 active low and another 15 active high are connected with IO M of 8085A Here active high is connected with enabling of outputs of internal decoder of 74LS155 While active low is connected with the internal decoder 2 of 74LS155 Hence whenever IO M pin of 8085A is high I O devices are selected and when IO M is low memory chips are selected This we can explain as below table 2 4 IO M B A15 SELECTION 1 RAM 6264 2Y1 TABLE 2 4 SELECTION USING ADDRESS LINES The interfacing circuit of RAM 6264 involves 74LS373 and 741 5155 and 8085 IC 74LS373 74LS155 are having the same connection details with the 9085 as discussed above The only difference in this one is that the and B input l
207. s set up at the trailing edge of WR 3 state during HOLD and HALT modes READY INPUT PIN NO 35 If READY 158 high during a read or writes cycle it indicates that the memory or peripheral 15 ready to send or receive data If READY 15 low the CPU will wait for READY to go high before completing the read or write cycle HOLD INPUT PIN NO 39 HOLD indicates that another master 16 requesting the use of the address and data buses The CPU upon receiving the hold request will relinquish the use of buses soon after the completion of the current machine cycle Internal processing can regain the buses only after the HOLD Is removed When the HOLD is acknowledged the Address Data RD WR and IO M lines are 3 stated HLDA OUTPUT PIN NO 38 HOLD ACKNOWLEDGE indicates that the CPU has received the HOLD request and that it will relinquish the buses in the next clock cycle HLDA 11 goes low after the HOLD request is removed The CPU takes the buses one half clock cycles after HLDA goes low INTR INPUT PIN NO 10 INTERRUPT REQUEST is used as a general purpose interrupt It is sampled only during the next to the last clock cycle of the instruction If it 1s active the program counter PC will be inhibited from incrementing and an INTA will be issued During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine The INTR is enabled and disable by software It 15 disabled by RESET and immediately aft
208. s shown below in table 3 1 Alternate Function RXD serial input port TXD serial output port INTO external interrupt 0 INTI external interrupt 1 TO timer 0 external input T1 timer 1 external input WR external data memory write strobe RD external data memory read strobe TABLE 3 1 PORT 3 DUAL FEATURES It also receives some control signals for Flash programming and verification 3 2 Major Blocks of Microcontroller 89C51 The major blocks of microcontroller 89C51 are Special Function Register SFR Accumulator B Register R Register Program Status Word PSW Stack Pointer SP Data Pointer DPTR Ports 0 to 3 Serial Data Buffer po sor EM der 10 Timer Register 11 Control Register Figure 3 2 shows a function block diagram of the 89 51 microcontroller 52 F0O0 F07 F20 F27 PORT 0 DRIVERS PORT 2 DRIVERS PORT 0 RAM AND REGISTER LATCH FLASH PROGRAM ADDRESS REGISTER E STACK REGISTER POINTER BUFFER TMFZ TMF 1 PC INCREMENTER PROGRAM COUNTER INTERRUPT SERIAL PS PORT AND TIMEF BLOCKS PSEN TIMING INSTRUCTI EA Vpp BET CONTROL REGISTER PORT 1 PORT 3 LATCH LATCH PORT 1 DRIVERS PORT 3 DRIVERS F10 F17 F30 F37 FIGURE 3 2 BLOCK DIAGRAM OF 89C51 e SPECIAL FUNCTION REGISTER SFR The 89C51 15 a flexible microcontroller with a relatively large number of modes of operations This operating mode of 89 51 be inspected as well as cha
209. semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright 1995 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments j standard warranty Production processing does not necessarily include testing of all parameters EXAS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 1488 5 55188 5 75188 QUADRUPLE LINE DRIVERS SLLS094B SEPTEMBER 1983 REVISED MAY 1995 logic symbolt 1A 3 4y 2A 1 6 2B 5 2Y 3A 2 8 SB 10 3Y 4A 12 11 a 13 4Y T This symbol is in accordance with ANSI IEEE Std 91 1984 and IEC Publication 617 12 Pin numbers shown are for the D and N packages schematic each driver To Other Drivers VCC A Input s B GND Other Drivers Vcc To Other Drivers Resistor values shown are nominal 35 TEXAS INSTRUMENTS logic diagram positive logic idi 3Y 3B 10 u 4Y 13 Positive logic A driver 1 Y or B drivers 2 thru 4 Output 2 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1488 5 55188 5 75188 QUADRUPLE LINE DRIVERS SLLS094B SEPTEMBER 1983 REVISED MAY 1995 absolute maximum ratings over operating free air temperature unless otherwise noted t Supply voltage Vcc at or below 25 C free air temperature see Notes 1 and 2 15 V Supply v
210. ssed by both direct and indirect addressing can be divided into 3 segments 1 Register Banks 0 3 Locations through 1FH 32 bytes ASMSI and the device after reset default to register bank 0 To use the other register banks the user must select them in the software Reset initializes the Stack Pointer to location 07H and it is incremented once to start from location 08H which is the first register RO of the second register bank Thus in order to use more than one register bank the SP should be initialized to a different location of the RAM where it 1s not used for data storage 2 Bit Addressable Area 16 bytes have been assigned for this segment 20H 2FH Each one of the 128 bits of this segment can be directly addressed 0 7FH Each of the 16 bytes of the segment can also be addressed as a byte 3 Scratch Pad Area Bytes 30H to 7FH are available to the user as data RAM However if the stack pointer has been initialized to this area enough number of bytes should be left aside to prevent SP data destruction 61 SECTION 2 EXPERIMENTS ON MICROPROCESSOR 4 ADVANCE EXPERIMENTS 8251 111111 PT T T ids The LC 8251A is useful for synchronous or asynchronous serial communication One can directly interface 8251A with 8085A microprocessor The basic futures of this interface chip are as follows o ForSynchronous operation e Character length can be 5 6 7 or 8
211. t It computes propagated noise contribution at output net from every noise generated circuits RMS sum of those contributors and equivalent input noise e Transient Analysis These analysis are time based which are performed in response to time varying sources It calculates all node voltages and branch currents over a time interval and their instantaneous values are the output of such analysis o How to use Pspice program In Pspice we have two methods to simulate our circuit First method 15 to draw circuit in OrCad capture and second method to write text file in Pspice software We will discuss both by means of drawing the circuit and by writing text file for our circuit in different examples In first method we need more understanding and associate other program and files which are generated during simulation While in second method we have to just write the text for our circuit and set profile to get simulated output This file 1s stored 188 as a CIR which will be discussed later In this section we will discuss about OrCad capture OrCad capture 15 a design entry program In this you have to prepare your circuit for simulation which means placeing and connecting part symbols input waveforms enabling analyses points in circuit where result should be obtained In capture we need stimulus waveform and model definitions for Pspice for use during simulation These files are generated at stimulus editor and model editor e Stimulus ed
212. ted under any patent right copyright mask work right or other intellectual property right of covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1998 Texas Instruments Incorporated This datasheet has been download from www datasheetcatalog com Datasheets for electronics components MC1489 MC1489A SN55189 SN55189A SN75189 SN75189A QUADRUPLE LINE RECEIVERS SLLS095D SEPTEMBER 1973 REVISED OCTOBER 1998 Input Resistance 3 KQ to 7 SN55189 SN55189A JOR W PACKAGE MC1489 MC1489A SN75189 SN75189A Input Signal Range 30 V D OR NSt PACKAGE Operate From Single 5 V Supply TOP VIEW e Built In Input Hysteresis Double Thresholds 1A 14 Voc Response Control that Provides 1CONT 4A 121 2A 4 111 4Y 2CONT 5 10 Input Threshold Shifting Input Noise Filtering Meet or Exceed the Requirements of I 6 9 TIA EIA 232 F and ITU Recommendation 8 V 28 Fully Interchangeable With Motorola T The NS package is only available left end taped and reeled MC1489 and MC1489A For SN75189 order SN75189NSR description SN55189 SN55189A FK PACKAGE These devices are monolithic low power Schottky quadruple l
213. the instruction being executed on the descending edge of the clock pulse A valid interrupt must occur at least 160 5 before sampling time RSTs interrupts are masked by SIM instruction and can be read off by RIM instruction serial input output is possible through SID and SOD pins of 8085 For each bit transaction SIM or RIM instruction is to be executed RIM inputs bits while SIM outputs the bits 8085 has multiplexed address and data lines AD LOW ADDRESS LINES During T clock cycle high ALE latches address present on ADo AD pins into external latch During other clock cycles To same pins 1 ADo AD work as data lines D7 Do Timing and control unit includes pins for clock control signal RD WR READY and ALB status lines So 5 and IO M DMA HOLD and reset RESETIN RESETOUT Clock is provided by crystal 26 MHz frequency Crystal frequency is internally divided by 2 READY is for synchronization of external slow memory or device So S and IO M are for hardware debugging and represent machine status HOLD and HLDA are used for DMA application RESETIN is for 3055 initialization and RESETOUT for peripheral initialization IR and decoder are for instruction code byte storage and identification of the type of instruction ALU can perform arithmetic and logical operation on operands of 8 bit length These two operands are stored in A and one temporary register before ALU operation Some
214. tically adds a Start bit low level followed by the data bits least significant bit first and the programmed number of Stop bits to each character Also an even or odd Parity bits 15 inserted prior to the Stop bit s as defined by the Mode instruction The character is then transmitted as a serial data stream on the TxD output The serial data is shifted out on the falling edge of the TxC at a rate equal to 1 1 16 or 1 64 that of the as defined by the Mode instruction BREAK characters can be continuously sent to the TxD if commanded to do so When no data characters have been loaded into the 8251A the TxD output remains HIGH marking unless a BREAK continuously low has been programmed e Asynchronous Mode Receiver The RxD line is normally high A falling edge on this line triggers the beginning of a START bit The validity of this START bit is checked by again strobing this bit at its nominal center 16 or 64X mode only If a low 15 detected again it 15 38 valid STRAT bit and the bit counter will start counting The bit counter thus locates the center of the data bits the parity bit 1f 1t exists and the stop bit 1f parity error occurs the parity error flag 1s set Data and parity bits are sampled on the RxD pin with the rising edge of the RxC If a low level is detect as the STOP bit the Framing Error flag will be set The STOP bit signals the end of a character Note that the receiver requires only one stop bit
215. tice Hall January 1986 e RESEARCH PAPERS R P 1 Mr M C Nanavati Dr H N Pandya Experimenting with 8251 a USART chip Lab experiments LE Bangalore India APRIL 2004 Vol 4 No 1 Pg 52 R P 2 Mr M C Nanavati Dr H N Pandya Dr D G Vyas Study of 8255 through experiments using microprocessor kit Lab experiment LE Bangalore India April 2004 Vol 4 No 2 Pg 89 Editor In Chief McGraw hill publishing inc N Y 245 Appendix B R P 3 Mr M C Nanavati Dr H N Pandya Study of interrupts of 8085 Lab experiment LE Bangalore India June 2005 Vol 5 No 2 Pg 119 R P 4 Mr M C Nanavati Dr H N Pandya Mr A B Bhaskar Keyboard interface with 89 51 Microcontroller Electronics maker Delhi India January 2007 Issue 128 No 12 Pg 52 56 R P 5 Mr M C Nanavati Dr H N Pandya Mr A A Bhaskar Running character display using AT89C51 Microcontroller part I Electronics maker Delhi India November 2006 Issue 126 No 11 Pg 39 41 R P 6 Mr M C Nanavati Dr H N Pandya Mr A A Bhaskar Running character display using 89 51 Microcontroller part II Electronics maker Delhi India December 2006 Issue 127 No 11 Pg 38 41 R P 7 Mr M C Nanavati Dr H N Pandya Mr A A Bhaskar Electronic Name plate Using AT89C51 Microcontroller Electronics maker Delhi India June 2006 Issue 121 No 11 Pg 51 56 R P 8 Mr M C Nanavati D
216. ting one of two input lines Output Y1 can be selected to be equal to either Al or B1 Similarly output Y2 may have the values of A2 or B2 and so on One input selection line S suffices to select one of two lines in all four multiplexers The control input E enables the multiplexers in the O state and disables them in the state Although the circuit contains four multiplexers we may think of it as a circuit that selects one in a pair of 4 input lines As shown in Table 12 2 the unit is selects when E 0 Then if 5 0 the four A inputs have a path to the outputs On the other hand if S 1 the four B inputs are selected The outputs have all 075 when E 1 regardless of the value of S 230 OUTPUT Y SELECT A SELECT B TABLE 12 2 FUNCTIONAL TABLE OF IC 74157 INPUT WAVEFORM FOR A B S and E KM Stimulus Editor QUAD2TO1MUX stI FIGURE 12 25 INPUT WAVEFORM FOR A B LINES AND S E CONTROL LINES OUTPUT WAVEFORMS FOR TWO DIFFERENT CONDITIONS Figure 12 26 a and b shows two different output conditions of IC 74157 Condition 1 is 0 AND 5 0 In this condition output Y will be the input of signal A and Condition 2 is E20 AND 5 In this condition output Y will be the input of signal B CONDITION E 0 AND 5 0 four inputs have a path to the outputs 231 File Edit View Simulation Trace Plot Tools Window Help jy seus amp Q hw e EA 48 E quad2to 1mu Analysis watch Devices
217. to be mapped Range can also be declared by indicating starting address and length of memory E Map to emulation memory i e On board W Write protect the emulation memory 1 e memory of ICE tool Map to Target memory In the format WIT indicate either W or T Assume that we want to test whole address space of target system 1 e 0000H to FFFFH then command will be MM 0000 FFFF T We have dropped E and W because we do not want emulation memory We will also use all resources of target Hence we should also enable all control signals and clock of target For this EX command is 1s available EX enables following control signals of the target RESET TRAP RST 7 5 RST 6 5 RST 5 5 INTR HOLD READY CLOCK Note that individual control signal from the above list can also be enabled with different commands Also commands make target system to work on its own no help from emulation system EPROM TESTING Suppose now we want to check the contents of first 10 memory location of EPROM of target Then perform following command D range This becomes D 0000 L 10 or D 0000 000A You can see the commands on the screen Figure 11 1 shows this interaction 180 0080 FFFF gt D 0000 8895 0000 40 30 OF 39 gt 8000 8005 8000 11 00 FF 00 FF 99 gt 4000 4005 4999 06 01 02 03 04 05 gt 7000 7885 7000 00 01 02 04 95 FIGURE 11 1 EPROM LOCATION TESTING ON TARGET RAM CHECKING
218. tput Outputs are latched Input are not latched 16 different Input Output configurations possible mnm armies Group B Permit D3 D1 PORT A UPPER PORT B LOWER p p pr pee n Oe 91116 T oer 3 ma mw V T 9 Ow mmu Oupa _ op o T 9m ma 5 Ow Ww v T T p wm ma mu Lom Y o ma 1 O T 9 me Om mp LES T T Uma 1 1 9 9 me ma Ot Oupa _ ET T me ma 8 Ow Ww T 1 T O me ma H pa LET T T Table 2 2 Mode 0 port definition 16 combination for input out configuration 20 D7 Do CS Ao OUTPUT Mode 0 Basic Output FIGURE 2 7 Mode 0 Basic Input Output timing diagram Mode 1 Strobed Input Output This functional configuration provides a means for transferring I O data to or from a specified port in conjunction with strobes or handshaking signals In mode 1 port A and port B use the lines on port C to generate or accept these handshaking signals Mode 1 Basic function Definitions Two Groups Group A and Group B Each group contains one 8 bit port and one 4 bit control data port The 8 bit data port can be either input or output Both inputs and outputs are latched The 4 bit 1s used for control and status of the 8 bit port Input control Signal Definition STB Strobe Inp
219. trigger address of the processor s memory at which the ICE has to stop recording the information Example BT 100 LIST COMMAND 1 List L command Lists the contents of the trace buffer Syntax L address 1 address 2 gt Address 1 specifies the starting address from where the listing of the trace buffer contents here to start Address 2 specifies the ending address of the list L command is used along with BT or FT commands 2 LZ command This command lists the content of the buffer along with the disassembled program instruction RESET COMMAND Resets the emulation processor Syntax X address Address specifies the address to which the processor s PC has to be changed If address is not specified PC will be set to OOOO PCICE SYSTEM CONTROL COMMAND This includes Help Quit Shell escape and redirection comment do etc commands In addition to this upload and download commands are available Generally in testing a target its memory and I O sections are considered Let us consider both for the target kit 1 Testing memory We learn from the memory map of target that locations 0000H to 3FFFH and 8000H to FFFFH are available as EPROM and RAM location respectively To test target memory we have to MAP its memory For this MM command of ICE 1s to be used The format of MM Memory map command is 179 MM range E W T Here range indicates starting address and ending address of memory
220. trol manages all activities associated with the transmission of serial data It accepts and issues signals both externally and internally to accomplish this function TxRDY Transmitter Ready This output signals the CPU that the transmitter is ready to accept a data character The TxRDY output pin can be used as an interrupt to the system since it is masked by TxEnable or for polled operatin the CPU can check TxRDY using Status Read operation TxRDY 15 automatically reset by the leading edge of WR when a data character 1s loaded from the CPU Note that when using the polled operation the TxRDY status bit 1s not masked by TxEnable but will only indicate the Empty Full Status of the Tx Data Input Register TxE Transmitter Empty When the 8251A has no characters to send the TxEMPTY output will go HIGH It resets upon receiving a character from CPU if the transmitter is enable TxEMPTY remains high when the transmitter is disable can be used to indicate the end of a transmission mode so that the CPU knows when to turn the line around in the half duplex operational mode In the Synchronous mode a HIGH on this output indicates that a character has not been loaded and the SYNC character or characters are about to be or are being transmitted automatically as fillers does not go low when the SYNC characters are being shifted out TxC Transmitter The transmitter Clock controls the
221. two formats for this A Range 15 declared by starting address and ending address Example 100 10f B Range is declared by starting address and the length denoted L of the range Example 100 L 10 Note that 100 1s in Hexadecimal and 1015 also in Hexadecimal 3 DUMP command D This command displays the contents of a range of memory addresses Syntax D range Example d 100 10f d 100 L 20 172 4 Compare command This command compares two portions of memory Syntax C range address If the range and address memory areas are identical ICE displays nothing If there are difference ICE displays them in the following format Syntax address bytel byte2 address2 Example 100 10f 300 Here 300 15 a starting address of range of some area in memory 5 Search S command This command searches a range of address for a pattern of one or more byte values Syntax S range list Here List specifies the pattern of one or more byte values or a string one wants to search for Enclose string values in quotation marks If the list parameters contains more then one byte value ICE displays only the first address where the value occurs If list contains only one byte value ICE displays all address where the value occurs in the specified range Example S 100 110 41 S 100 1AO ph 6 Edit E command This command helps to edit data into memory at the address specified by the user Syntax
222. uality Detector 4 Ring Indicator 4 Data Signal Rate Selector DTE DCE Source 4 2 Transmit Signal Element Timing DTE Source Unassigned 4 ND 1 ON gt Q LD FIGURE 4 9 RS 232 SIGNAL DEFINITIONS AND PIN ASSIGNMENTS Let s come back to Figure 4 7 In this figure we have used two level translators ICs MC1488 and MC1489 From this two ICs MC1488 converts the TTL voltage level of 8251A to a negative logic and RS 232 voltage level The MC1489 converts the RS 232 signals to a positive TTL voltage level In Figure 4 7 three parts Appendix Appendix A 70 of MC1488 translates TxD DTR and RTS signals of 8251A to RS 232 level while three parts of IC MC1489 are used to convert RS 232 levels to the TTL level which are connected with RxD DSR and CTS The details of IC MC 1488 and MC1489 are given in appendix I EXPERIMENT I CONTINUOUS TRANSMISSION DATA ON TxD PIN PU AIM To transmit given data continuously in asynchronous mode over TxD pin of 9251 with following specifications o Baud rate same as clock o Character length 8 bit o Parity not required o Stop bits two Software reset is to be performed and then proceed Command status Port 21H Data Port address 20H Apparatus 8085A based microprocessor kits a single power supply 5V 12V and CRO Procedure The 8085A microprocessor kit with 8251A and level translator ICs MC1488 and MC1489 is connected t
223. uction Below Figure 2 18 shows command instruction format D7 De 05 D4 D3 D2 D1 Do IR RTS ER SBRKRxE TRANSMIT ENABLE 1 ENABLE 0 DISABLE DATA TERMINAL READY High will force DTR output to zero RECEIVE ENABLE 1 ENABLE 0 DISABLE SEND BREAK CHARACTER 1 forces TxD low 0 Normal operation ERROR RESET 1 resets error flags 0 Normal operation REQUEST TO SEND High will force RST output to zero INTERNAL RESET High returns 8251 to Mode Instruction Format ENTER HUNT MODE 1 enables search for Sync characters FIGURE 2 18 COMMAND INSTRUCTION FORMAT Once the mode instruction has been written into the 8251A and Sync character inserted of necessary then all further control writes C D 1 42 will load a command instruction A Reset Operation internal or external will return the 8251A to the Mode Instruction format STATUS READ DEFINITION In data communication systems it is often necessary to examine the status of the active device to ascertain of errors have occurred or other conditions that require the processor s attention The 8251A has facilities that allow the programmer to read the status of the device at any time during the functional operation A normal read command is issued by the CPU with C D 1 to accomplish this function Below Figure 2 19 shows Status read format for
224. ues otherwise Pspice analysis is not meaningful For independent voltage and current source which have AC values are input in AC Pspice analysis 5 Gas a suffix is required for group delay output In this for output change to be smooth we should have small steps of frequency DC commands DC source Dc source can be divided into two parts They are independent DC sources and dependent DC sources Independent DC sources As we discussed in AC sources we have two sources voltage source and current source Similarly in DC we have two types of sources in 198 DC source i e independent DC voltage and dependent DC current sources Figure 12 6 shows independent DC voltage and current source They could be time variant or time 1n variant V lt NAME gt lt gt FIGURE 12 6 INDEPENDENT DC VOLTAGES AND CURRENT SOURCE Independent DC voltage source In general V is symbolic identification for independent voltage source In general it can be written as V lt NAME gt N N DC lt NAME gt Here V lt NAME gt means DC voltage stimuli name N and N are positive and negative node The flow of current 15 from N to N The source need to be grounded In DC analysis DC source 15 set of DC voltage values We can use as a AMMETER by zero value voltage source into circuit for current measurement These sources behave like a short circuit It will not effect on circuit operations EXAMPLE VI 1 0 12V VI 2
225. ur target system To check its proper working we should have the details of its memory and I O hardware For ESA85 2 kit following are the details 1 Memory Memory capacity Address range 27128 EPROM at U5 16K X 8 0000 to 3FFF 62256 RAM at U7 32K X 8 9000 to FFFF 2764 EPROM at 06 4000 to 5FFF 6000 to 7FFF 27128 EPROM at U6 4000 to 7FFF 62256 RAM at U6 4000 to 7FFF TABLE 11 1 MEMORY MAP OF 5 85 2 KIT From table 11 1 we learn that in ESA85 2 kit whole 64K bytes of address space 15 divided such that 0000 to 3FFF 1 16K bytes are occupied by EPROM and 8000 to FFFF 1 e 32K bytes are occupied by RAM From 4000 to 7FFF i e 16K space is free for user expansions User can fix 2764 27128 EPROM or 6264 62256 6264 RAM at U6 4000 to 5 6000 to f C RAM at this locations We assume that user has not used this space So from 0000 to and 8000 to FFFF location are available 170 2 I O addressing DEVICE ADDRESS USAGE 8255A 1 at 040 Port A 00H This chip 15 available to user and signals Port B 01H are available at J1 connector Port C 02H Control Port 03H 8255A 2 at U35 Port A 40H This 8255 chip 15 also available to user and Port B 41H signals are available at J2 connector Port C 42H Control Port 43H 8255A 3 at U36 Port A 60H This chip is not available to user It is used Port B 61H used for implementing PROM processing Port C 62H system Control Po
226. ut A LOW on this input loads data into the input latch 21 MODE 1 PORT CONTROL WORD 07 De 05 04 03 D2 D 07 De 05 D4 D3 02 Di Do LX FIGURE 2 8 A Mode 1 Strobed Input definitions OTO tsi tSIB A E u Gs IBF AAA k INTR m EE INPUT FROM PERIPHERAL FIGURE 2 8 B Mode 1 Strobed Input definitions timing diagram FIGURE 2 8 Input Control Signal definition IBF Input Buffer Full flip flop A HIGH on this output indicates that the data has been loaded into the input latch in essence and 22 acknowledgment IBF is set by STB input being low and reset by the rising edge of the RD input INTR Interrupt Request A HIGH on this output can be used to interrupt the CPU when and input device 1s requesting service INTR is set by the condition STB is a ONE IBF is a ONE and INTE is a ONE It 15 reset by the falling edge of RD This procedure allows input device to request service from the CPU by simply strobing its data into the port INTE Controlled by bit set reset of PCa INTE B Controlled by bit set reset of PC Output control Signal Definition MODE PORTA CONTROL WORD D7 D 05 D4 03 D2 01 Do CONTROL WORD D7 D 05 D4 D3 D2 D1 Do 1 FIGURE 2 9 A Mode 1 Strobed Output definitions 23 WR OBF INTR ACK OUTPUT FIGURE 2 9 B Mode 1 Strobed Output definitions timing dia
227. we need model files stimulus files and include files before starting simulation Model file and stimulus file can be edited in model editor and stimulus editor User can enter data for user defined model in notepad or such like text editor and can be used e Model file Model file are nothing but a model library This file contains electrical definitions of a part provided by part manufacturer or datasheet of the part In simulation this file used as an information of a part to determine how a part will respond to different inputs at different time These definitions contain model parameters and sub circuit netlist Model parameter and sub circuit netlist are generally available in part datasheet Pspice has many in built parts models Model parameter defines the behavior of a part and sub circuit netlist defines the structure and function 190 of a part during use in circuit These model libraries are stored in library directory of OrCad with LIB extension User can enter own part as described above Important files for simulation To simulate the circuit Pspice should know which parts are used and how they are connected in your circuit What type of analysis to be used which part model and which type stimulus definitions are to be used in circuit This can be obtained by various data files datasheets Few are generated by capture while other can be obtained by in built library and some which are not available can be created by user F
228. y at the vector addresses of RSTs jump instructions are stored Find out from the manual of your kit these jump locations for RST6 5 and RST5 5 In our case they FEOCH and FEO6H for RST6 5 and RST5 5 respectively Note that such RSTs hardware interrupts should be free to use in the kit 90 In our case the locations where RST6 5 and RST 5 5 jumps were not sufficient to provide enough memory locations so we again used two more jump instructions as follows At FEOCH JMP 810C for RST 6 5 At FE06H 8100 for RST 5 5 You can check your kit for such situation Now store following service routines for RST6 5 and RST5 5 at the final jump address For RST 6 5 enter following program starting at 8 MOVA M TAKE DATA FROM 8200H TO A 810D D3 40 00 OUT 00H OUTPUT TO PORT A 810F 23 INX H 8110 05 DCR B 8111 C2 15 81 JNZ OUTI ALL BYTES TAKEN 8114 76 HLT YES HAULT 9115 C9 RET OTHERWISE GOTO MAIN PROGRAM For RST 5 5 enter following program starting at 8100H 8100 DB 01 41 INOIH READ DATA FROM PORT B 8102 12 STAX D STROE TO DESTINATION 8103 13 INX D POINTED TO BY DE 8104 C9 RET AND RETURN TO MAIN PROGRAM Now enter source data at 8200 When you run the above program the source data at 8200 will be copied at destination addresses 8300 onward UNDERSTANDING PROGRAM In the main program when instruction EI will be executed it will generate interrupt on RST 6 5
229. ypes of instructions use the port as the destination operand READ MODIFY WRITE INSTRUCTIONS Mnemonics Example ANL ANL PLA ORL ORL PILA XRL XRL PILA JBC JBC P1 1 TARGET CPL CPL 2 INC INC PI DEC DEC DJNZ DJNZ P1 TARGET MOV MOV 2 Px y CLR P1 3 SETB SETB 4 59 e OUTPUT PORTS ports are configured as output port as power is applied to 89 51 microcontroller and also by providing proper reset pulse 34 Memory Organization of 89 51 The 89 51 has separate address spaces for Program Memory and Data Memory e PROGRAM MEMORY The Program Memory can be up to 64K bytes long the 4K byte internal and 60K byte external Figure 3 5 shows a map of the 89C51 Program memory 60K BYTES EXTERNAL 4 K BYTES INTERNAL FIGURE 3 5 THE 89 51 PROGRAM MEMORY e DATA MEMORY The 89C51 can address up to 64K bytes of Data Memory external to the chip The MOV X instruction is used to access the external data memory The 89C51 has 128 bytes of on chip RAM plus a number of Special Function Registers SFRs The lower 128 bytes RAM can be accessed either by direct addressing MOV data addr or 60 by indirect addressing MOV Figure 3 6 shows 89C51 Data Memory organization SFR DIRECT ADDRESSING ONLY DIRECT amp INDIRECT ADDRESSING FIGURE 3 6 THE 89 51 PROGRAM MEMORY DIRECT AND INDIRECT ADDRESS AREA The 128 bytes of RAM which can be acce
230. ytes are transferred to output shift register which shift them bit by bit on TxD pin This activity 16 done under the control of control logic When buffer register becomes empty it makes TxRDY pin high to signal microprocessor to send data When output register is empty it makes TxE pin high indicate that it has nothing to transmit The receiver works as shown in Figure 4 2 64 RxD Receiver data REGISTER RxC Receiver clock RECEIVER BUFFER Parallel data dons LU RxRDY Receiver Ready 6 Syndet Brkdet Transmitter empty FIGURE 4 2 RECEIVER SECTION OF 8251A Receiver section accepts data bits at RxD on every RxC pulse The logic circuit of receiver separates framing information start bit stop bit or sync bytes and assembles data byte and passes this assembled byte to receiver buffer register At this time it informs microprocessor to collect assembled bytes from buffer by making RxRDY high 8251A offers two ways of data transmission and or reception Synchronous and Asynchronous Asynchronous mode format is shown in Figure 4 3 Provided For Transmitter by 8251 MARKING DATA BITS PARITY STOP BIT BIT Typ PIN Does not For Receiver appear on data bus PARITY STOP MARKING DATA BITS ELS FIGURE 4 3 ASYNCHRONOUS MODE FORMAT OF 8251A In Asynchronous mode data bytes are accompanied by framing bits 1 e start bit and stop bits to distinguish each data byte from other If parity b

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