DE2 Development and Education Board User Manual
Contents
1. amp a B u cx HERE DH Paty E L5 hs 5 RNI E Hexe p l Eb 2 peg A 4 rh ERA p Segment Display Espera Display HEX5 sa HEXA RNI2 RANIA ExS D a E aT HEYA DO 2 M 8 Sell Ad J 3 4 E won Hed D 5l la cd sii EC u P Anis PH Je HEXA Du a 2 Pg HEXZ E VEGAS ibl aegmant Display Evgenera Display n HEX HEX vitx HEX2 Dd HEX D Fecgment Display HE xIT B P HEX 00 3 E PM hat HEXT Of E HExD D gt AD D 1 4 ZW E a HEW IS 21 Dg CU veecs3 XH Li 7 n ME ue DE Hg HEXO_ gt ED 2 HEM te ltda TU 0 Le E k Tr segmant Diepla l Peg iptay Segment Display Figure 4 6 Schematic diagram of the 7 segment displays Figure 4 7 Position and index of each segment in a 7 segment display 30 DE2 User Manual 31 NOTE D Va DE2 User Manual HEX5 0 PIN_T2 Seven Segment Digit 5 0 Table 4 4 Pin assignments for the 7 segment displays 4 4 Clock Inputs The DE2 board includes two oscillators that produce 27 MHz and 50 MHz clock signals The board also includes an SMA connector which can be used to connect an external clock source to the board The schematic of the clock circuitry is shown in Figure 4 8 and the associated pin assignments appear in Table 4 5 Important To use the 27 MHz clock the TD RESET pin PIN c4 must be asserted to a high logic level 32 DE2 User Manual MR2. BBS forum http www terasic com english discuss htm INDIE SYAN DE2 User Manual Chapter 2 Altera DE2 Board This chapter presents the features and design characteristics of the DE2 board 2 1 Layout and Components A photograph of the DE2 board is shown in Figure 2 1 It depicts the layout of the board and indicates the location of the connectors and key components USB USB USB Ethernet Blaster Device Host Mic Line Line Video VGAVideo 10 100M Port Port Port in in Out In Pot RS 232 Port FE T tot DC Power Supply Connector 1 27 MHz Oscillator 24 bit Audio Codec l r A Bm tE PS 2 Keyboard Mouse Port Power ON OFF Switch ma NAM UE sud m BUSES PE VGA 10 bit DAC USB Host Slave Controller TV Decoder NTSCIPAL FO eral Aa U Ethernet 10 100M Controller sS EM im 3 Expansion Header 2 JP2 15 TR m WEM die Altera USB Blaster Controller Chipset E pag rt Expansion Header 1 JP4 Altera EPCS16 Configuration Device a Altera Cyclone Il FPGA RUN PROG Switch for JTAG AS Modes NU r m 16x2 LCD Module p omm NE SD Card Slot 7 Segment Displays 8 Green LEDs 18 Red LEDs ESE IrDA Transceiver 18 Toaale Switch mimiuininimimininiuiuiu lui 1 1 SMA External Clock oggle Switches LU LU ye ye ye 15 pA 1 d i I 4 Debounced Pushbutton Switches 50 MHz Oscillator 8
3. Write sequential Write Address 0 Length 0 File Length Write a File to SDRAM sequential Read Address 0 Length 0 Entire Sdram Load SDRAM Contentto a File Figure 3 5 Accessing the SDRAM 14 NOTE 5 DE2 User Manual A 16 bit word can be written into the SDRAM by entering the address of the desired location specifying the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 5 depicts the result of writing the hexadecimal value 6CA into location 200 followed by reading the same location The Sequential Write function of the Control Panel 15 used to write the contents of a file into the SDRAM as follows l 2 Specify the starting address in the Address box Specify the number of bytes to be written in the Length box If the entire file 15 to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 initiate the writing of data click on the Write a File to SDRAM button 4 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Sequential Read function is used to read the contents of the SDRAM and place them into a file as follows l 2 Specify the starting address in the Address box Specify the number of bytes to be copied into the file in the Length box If the
4. and SECAM into 4 2 2 component video data compatible with 16 bit 8 bit CCIR601 CCIR656 The ADV7181 is compatible with a broad range of video devices including DVD players tape based sources broadcast sources and security surveillance cameras The registers in the TV decoder can be programmed by a serial I2C bus which is connected to the Cyclone II FPGA as indicated in Figure 4 19 The pin assignments are listed in Table 4 13 Detailed information on the ADV7181 is available on the manufacturer s web site and from the Datasheet folder on the DE2 System CD ROM 44 DE2 User Manual Tl ai MHZ AM WoCa3 lt r TD RESET RT D e TD H5 V VCC18 V VCC33 AV VCC33 PV VOC18 TC28 V5 _ o 100U 8 BC114 C 1210 GNO 3 C20 C30 V VCCIB PV VCCIB 0 014 0 18 CVBS IN RI 35 RT 1 7K ou A BC115 CH Od C32 1DU C33 10U CH C35 f 1 11 i GNO sO AM VCC33 VGND 27M 34 C38 37 10U 10U GND GNO TD RESET nRESET V VCC33 0 1 nPWRDWN GND 22 ALSE 2C SCLK d EX pc SDAT E E 7 SCLK SDATA I2C ADDRESS READ IS 0x40 I2C ADDRESS WRITE If 0x41 Table 4 13 TV Decoder pin assignments 45 oN OT A DE2 User Manual 4 13 Implementing a TV Encoder Although the DE2 board does not include a TV encoder chip the ADV7123 10 bit high speed triple ADCs can be used to implement a professional quality TV encoder with the digital
5. embedded processor Bag of six rubber silicon covers for the DE2 board stands The bag also contains some extender pins which can be used to facilitate easier probing with testing equipment of the board s I O expansion headers Clear plastic cover for the board 9V DC wall mount power supply The DE2 Board Assembly To assemble the included stands for the DE2 board Assemble a rubber silicon cover as shown in Figure 1 2 for each of the six copper stands on the DE2 board The clear plastic cover provides extra protection and 1s mounted over the top of the board by using additional stands and screws 4 Figure 1 2 The feet for the DE2 board 1 3 Here are the addresses where you can get help if you encounter problems Getting Help Altera Corporation 101 Innovation Drive san Jose California 95134 USA Email university Oaltera com Terasic Technologies No 356 Sec 1 Fusing E Rd Jhubei City HsinChu County Taiwan 302 Email support terasic com Web DE2 terasic com Arches Computing Unit 708 222 Spadina Ave Toronto Ontario Canada M5T3A2 Email DE2supportO archescomputing com Web DE2 archescomputing com DE2 User Manual A BBS Bulletin Board System Forum for the DE2 board has been created at the address shown below This Forum is meant to serve as a repository for information about the DE2 board and to provide a resource through which users can ask questions and share design examples
6. processing part implemented in the Cyclone II FPGA Figure 4 20 shows a block diagram of a TV encoder implemented in this manner TV Encoder Block Cyclone 235 0 Composite tel sie z Y U cos V sin Clock BESTE Calculate or Y S Video Timing MAS EUM lor RCA Y C U cos V sin S Video SIN or RCA Pb g 05 Y U V Tables RCA_Pr Figure 4 20 A TV Encoder that uses the Cyclone II FPGA and the ADV7123 4 14 Using USB Host and Device The DE2 board provides both USB host and device interfaces using the Philips ISP1362 single chip USB controller The host and device controllers are compliant with the Universal Serial Bus Specification Rev 2 0 supporting data transfer at full speed 12 Mbit s and low speed 1 5 Mbit s Figure 4 21 shows the schematic diagram of the USB circuitry the pin assignments for the associated interface are listed in Table 4 14 Detailed information for using the ISP1362 device is available in its datasheet and programming guide both documents can be found on the manufacturer s web site and from the Datasheet folder on the DE2 System CD ROM The most challenging part of a USB application is in the design of the software driver needed Two complete examples of USB drivers for both host and device applications can be found in Sections 5 3 and 5 4 These demonstrations provide examples of software drivers for the Nios II processor 46 DE2 User Manual Figure 4 21 USB I
7. which are named HEX7 0 can be entered into the corresponding boxes and displayed by pressing the Set button A keyboard connected to the PS 2 port can be used to type text that will be displayed on the LCD display Choosing the LED amp LCD tab leads to the window in Figure 3 4 Here you can turn the individual LEDs on by selecting them and pressing the Set button Text can be written to the LCD display by typing it in the LCD box and pressing the corresponding Set button The ability to set arbitrary values into simple display devices is not needed in typical design activities However it gives the user a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is suspected Thus it can be used for troubleshooting purposes 13 DE2 User Manual IE DE2 Control Panel Open Help About FLASH SDRAM SRAM PS amp 7 SEG LED amp LCD LED LCD Text for display Clear ow Figure 3 4 Controlling LEDs and the LCD display 3 3 SDRAM SRAM Controller and Programmer The Control Panel can be used to write read data to from the SDRAM and SRAM chips on the DE2 board We will describe how the SDRAM may be accessed the same approach 15 used to access the SRAM Click on the SDRAM tab to reach the window in Figure 3 5 IE DE2 Control Panel Open Help About P52 amp 7 SEG LED amp LCD TOOLS FLASH SDRAM sRAM SORAM Random Access Address 200 wDATA ECA DATA
8. 2 MHZ Y VCC33 NOTE The 27M signal is an input to the TV decoder chip and the 2 MMHZ signal is an output of the same chip and is fed to the FPGA GND OUT P see figure 4 19 PIN D13 27 MHz clock input PIN N2 50 MHz clock input PIN P26 External SMA clock input Table 4 5 Pin assignments for the clock inputs 4 5 Using the LCD Module The LCD module has built in fonts and can be used to display text by sending appropriate commands to the display controller which 15 called HD44780 Detailed information for using the display 15 available in its datasheet which can be found on the manufacturer s web site and from the Datasheet folder on the DEZ System CD ROM A schematic diagram of the LCD module showing connections to the Cyclone II FPGA is given in Figure 4 9 The associated pin assignments appear in Table 4 6 33 G1 8050 CO B VC C5 O VCC43 CD_ON Le LCD BLON LCD EN LCD WR R15 680 DE2 User Manual G2 8550 VCC43 Q4 8550 O R16 VCC43 680 Z Q5 2 8050 n 2 X 16 DIGITAL U2 LCD16 Figure 4 9 Schematic diagram of the LCD module LCD LCD DATA 1 LCD 2 LCD DATA 3 LCD DATA 4 LCD DATA 5 LCD DATA 6 LCD DATA 7 LCD RW LCD EN LCD RS LCD ON LCD BLON PIN J1 PIN J2 PIN H1 PIN H2 PIN J4 PIN J3 PIN H4 PIN H3 PIN K4 PIN K3 PIN K1 PIN L4 PIN 2 LCD Command Data Select 0 Command 1 Data Table 4 6 Pin ass
9. Cursor Enable are checked e Connect a VGA monitor to the DE2 board and you should see on the screen the default image shown in Figure 3 9 The image includes a cursor which can be controlled by means of the X Y axes scroll bars on the DE2 Control Panel The image in Figure 3 9 is stored in an M4K memory block in the Cyclone II FPGA It is loaded into the M4K block in the MIF Hex Intel format during the default bit stream configuration stage We will next describe how you can display other images and use your own images to generate the binary data patterns that can be displayed on the VGA monitor Another image is provided in the file picture dat in the folder DE2_demonstrations pictures on the DE2 System CD ROM You can display this image as follows e Select the SRAM page of the Control Panel and load the file picture dat into the SRAM e Select the TOOLS page and choose Asynchronous 1 for the SRAM multiplexer port as shown in Figure 3 10 Click on the Configure button to activate the multi port setup 20 DE2 User Manual IE DE2 Control Panel Open Help About FLASH SDRAM SRAM PS2 amp 7 SEG LED amp LCD SDRAM Multiplexer Host USB Port FLASH Multiplexer Host USB Port SRAM Multiplexer Asynchronous 1 Board Test Figure 3 10 Use the Asynchronous Port 1 to access the image data in the SRAM The FPGA 15 now configured as indicated in Figure 3 11 Select the VGA page and deselect the ch
10. Finally there 15 a time period called the front porch d where the RGB signals must again be off before the next hsync pulse can occur The timing of the vertical synchronization vsync is the same as shown in Figure 4 12 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Figures 4 13 and 4 14 show for different resolutions the durations of time periods a b c and d for both horizontal and vertical timing Detailed information for using the ADV7123 video DAC is available in its datasheet which can be found on the manufacturer s web site and from the Datasheet folder on the DE2 System CD ROM The pin assignments between the Cyclone II FPGA and the ADV7123 are listed in Table 4 8 An example of code that drives a VGA display 15 described in Sections 5 2 and 5 3 38 DE2 User Manual Back porch b Front porch d Display interval HSYNC Sync a Figure 4 12 WGA horizontal timing specification DATA Lese mem wr pee owe wem 21 es 100 oa e ooo Dooa rera a fa far os e aa ewe veros va 2 108 05 09 coo sm i zi 00 vr ono Figure 4 13 WGA horizontal timing specification www mem s m om www wem s 7 ow 1 xw me 3 Figure 4 14 VGA vertical timing specification 39 DE2 User Manua
11. QE 4 4 9 SS SCAN ORE E II den E cout 42 ALO ES 2 SEAL PO mE 42 4 11 Fast Ethernet Network Controller vin cncscueusticvecactussonensnarecadonswaneustenesacbusvovendnateenlensvaseuctenesacees 43 LI MEM AA e 44 AAS implementa a TV Encode araceli eii 46 Ald Usne USB UR UT Tm 46 LESSER Ip 48 AIO Usus SDRAM SRM EPIS piden tetur po tios once 49 Chapter 5 Examples of Advanced Demonstrations 22 9 2 eee eee 2222000 54 5 1 DEXEGCIOD atra sia 54 Altera DE2 Board 5 2 BOX HUND 55 5 3 US BP US ds 57 5 4 A AA a 59 359 A o A A 61 5 6 Ethernet Packet Sending 62 5 7 DC MEP NTC E A 64 INDE oA DE2 User Manual Chapter 1 DE2 Package The DE2 package contains all components needed to use the DE2 board in conjunction with a computer that runs the Microsoft Windows software 1 1 Package Contents Figure 1 1 shows a photograph of the DE2 package Figure 1 1 The DE2 package contents DE2 User Manual The DE2 package includes 1 2 DE2 board USB Cable for FPGA programming and control CD ROM containing the DE2 documentation and supporting materials including the User Manual the Control Panel utility reference designs and demonstrations device datasheets tutorials and a set of laboratory exercises CD ROMs containing Altera s Quartus II 5 0 Web Edition software and the Nios II 5 0
12. entire contents of the SDRAM are to be copied which involves all 8 Mbytes then place a checkmark in the Entire SDRAM box 3 Press Load SDRAM Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner 3 4 Flash Memory Programmer The Control Panel can be used to write read data to from the Flash memory chip on the DE2 board It can be used to Erase the entire Flash memory Write one byte to the memory Read one byte from the memory Write a binary file to the memory Load the contents of the Flash memory into a file 15 INDE YA DE2 User Manual Note the following characteristics of the Flash memory e The Flash memory chip is organized as 4 M or 1 M on some boards x 8 bits e You must erase the entire Flash memory before you can write into it Be aware that the number of times a Flash memory can be erased 1s limited e The time required to erase the entire Flash memory is about 20 seconds Do not close the DE2 Control Panel in the middle of the operation To open the Flash memory control window shown in Figure 3 6 select the FLASH tab in the Control Panel IE DE2 Control Panel Open Help About LED amp LCD SDRAM SRAM Random Access Address 0 wDATA 00 DATA 00 Chip Erase 24 Sec Write Read sequential Write Address 0 Length 0 File Length Write a File to FLASH se
13. listed in Table 4 12 For detailed information on how to use the DM9000A refer to its datasheet and application note which are available on the manufacturer s web site and from the Datasheet folder on the DE2 System CD ROM ENET DO ENET D15 y 514 N VCC33 D NGND 0 0 1U CHSGND ENET D13 ENET D12 ENET D11 ENET 010 ENET_D9 R19 R20 49R9 49R9 N_VOC33 O ENET D8 7 M VCC33 for eeprom GND ENET INT ENET IOR 5 ENET IOW L1 BEAD IS S E A A St RD a CA E ARA T lg a YAMAHA N_V0c25 2 RD N e 9 3 5 ON VCC33 2U OWAIT WAKE UP worm ca CHSGND CHSGND BC57 BC58 TC30 0 1U 0 1U 1090 85 3 C 1210 ENET RESET Y N VCC33 Oy BE CT SPEED ACT A SPEED NGND GND oh Figure 4 18 Fast Ethernet schematic DATA 0 PIN D17 DM9000A DATA O ENET DATA 1 PIN C17 DM9000A DATA ENET DATA 2 PIN B18 DM9000A DATA 2 43 INDE 5 A DE2 User Manual 7 PIN B15 DM9000A DATA 7 ENET CMD DM9000A Command Data Select 0 Command 1 Data ENET CS N DM9000A Chip Select ENET INT DM90004 Interrupt ENET RD N DM9000A Read ENET_WR_N DM9000A Write ENET_RST_N DM9000A Reset Table 4 12 Fast Ethernet pin assignments 4 12 TV Decoder The DE2 board is equipped with an Analog Devices ADV7181 TV decoder chip The ADV7181 is an integrated video decoder that automatically detects and converts a standard analog baseband television signal NTSC PAL
14. of monitors should work 56 DE2 User Manual e Connect the audio output of the DVD player to the line in port of the DE2 board and connect a speaker to the line out port If the audio output jacks from the DVD player are of RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the DE2 board this 1s the same type of plug supported on most computers e Load the bit stream into FPGA Press KEYO on the DE2 board to reset the circuit Figure 5 2 illustrates the setup for this demonstration Video In Line Out VGA LCD CRT Monitor Figure 5 2 The setup for the TV box demonstration 5 3 USB Paintbrush USB 15 a popular communication method used in many multimedia products The DE2 board provides a complete USB solution for both host and device applications In this demonstration we implement a Paintbrush application by using a USB mouse as the input device This demonstration uses the device port of the Philips ISP1362 chip and the Nios II processor to implement a USB mouse movement detector We also implemented a video frame buffer with a VGA controller to perform the real time image storage and display Figure 5 3 shows the block diagram of the circuit which allows the user to draw lines on the VGA display screen using the USB mouse The VGA Controller block 15 integrated into the Altera Avalon bus so that it can be controlled by the Nios II processor Once the program running o
15. the line in port blue color on the DE2 board e Connect a headset speaker to the line out port green color on the DE2 board e Load the bit stream into the FPGA e You should be able to hear a mixture of the microphone sound and the sound from the music player e Press KEYO to adjust the volume it cycles between volume levels 0 to 9 Figure 5 8 illustrates the setup for this demonstration MP3 Any Audio Output Microphone 3 i mu Eh i ITTTETTETTERTETTTETTTETTTIY TT TT PELIS Figure 5 8 The setup for the Karaoke Machine 5 6 Ethernet Packet Sending Receiving In this demonstration we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 board As illustrated in Figure 5 9 we use the Nios II processor to send and receive Ethernet packets using the DM9000A Ethernet PHY MAC Controller The demonstration can be set up to use either a loop back connection from one board to itself or two DE2 boards connected together 62 INDE oA DE2 User Manual On the transmitting side the Nios II processor sends 64 byte packets every 0 5 seconds to the After receiving the packet the DM9000A appends a four byte checksum to the packet and sends it to the Ethernet port On the receiving side the DM9000A checks every packet received to see if the destination MAC address in the packet 1s identical to the MAC address of the DE2 board If the packet received does have the
16. 05 M4K RAM blocks e 483 840 total RAM bits e 35embedded multipliers e 4PLLs e 475 user I O pins e FineLine BGA 672 pin package Serial Configuration device and USB Blaster circuit Altera s EPCS16 Serial Configuration device On board USB Blaster for programming and user API control JTAG and AS programming modes are supported NOTE DVA DE2 User Manual SRAM 512 Kbyte Static RAM memory chip e Organized as 256K x 16 bits e Accessible as memory for the Nios II processor and by the DE2 Control Panel SDRAM 8 Mbyte Single Data Rate Synchronous Dynamic RAM memory chip e Organized as 1M x 16 bits x 4 banks e Accessible as memory for the Nios II processor and by the DE2 Control Panel Flash memory 4 Mbyte NAND Flash memory 1 Mbyte on some boards e 8 bit data bus e Accessible as memory for the Nios II processor and by the DE2 Control Panel SD card socket e Provides SPI mode for SD Card access e Accessible as memory for the Nios II processor with the DE2 SD Card Driver Pushbutton switches e 4 pushbutton switches Debounced by a Schmitt trigger circuit e Normally high generates one active low pulse when the switch is pressed Toggle switches e 18 toggle switches for user inputs e A switch causes logic O when in the DOWN closest to the edge of the DE2 board position and logic when in the UP position Clock inputs 50 MHz oscillator 27 MHz oscillator e SMA external clock input NOTE 5 DE2 User M
17. 2 Using the LEDs and Switches The DE2 board provides four pushbutton switches Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 4 3 The four outputs called KEYO KEY3 of the Schmitt Trigger device are connected directly to the Cyclone II FPGA Each switch provides a high logic level 3 3 volts when it is not pressed and provides a low logic level O volts when depressed Since the pushbutton switches are debounced they are appropriate for use as clock or reset inputs in a circuit Pushbutton depressed Pushbutton released Before Debouncing Schmitt Trigger Debounced Figure 4 3 Switch debouncing There are also 18 toggle switches sliders on the DE2 board These switches are not debounced and are intended for use as level sensitive data inputs to a circuit Each switch is connected directly to a pin on the Cyclone II FPGA When a switch 15 in the DOWN position closest to the edge of the board it provides a low logic level 0 volts to the FPGA and when the switch 15 in the UP position it provides a high logic level 3 3 volts 26 DE2 User Manual There are 27 user controllable LEDs on the DE2 board Eighteen red LEDs are situated above the 18 toggle switches and eight green LEDs are found above the pushbutton switches the gu green LED is in the middle of the 7 segment displays Each LED is driven directly by a pin on the Cyclone II F
18. A The procedure for downloading a circuit from a host computer to the DE2 board 15 described in the tutorial Quartus II Introduction This tutorial is found in the DE2 tutorials folder on the DE2 System CD ROM and it is also available on the Altera DE2 web pages The user is encouraged to read the tutorial first and to treat the information below as a short reference The DE2 board contains a serial EEPROM chip that stores configuration data for the Cyclone II FPGA This configuration data 1s automatically loaded from the EEPROM chip into the FPGA each time power is applied to the board Using the Quartus II software it 15 possible to reprogram the FPGA at any time and it is also possible to change the non volatile data that is stored in the serial EEPROM chip Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream 15 downloaded directly into the Cyclone II FPGA The FPGA will retain this configuration as long as power 15 applied to the board the configuration 15 lost when the power 15 turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCSIO serial EEPROM chip It provides non volatile storage of the bit stream so that the information 15 retained even when the power supply to the DE2 board 15 turned off When the board s p
19. Altera DE2 Board JAN DTE RA DE2 Development and Education Board User Manual Version 1 2 Copyright 2005 Altera Corporation Altera DE2 Board Chapter FDEZ PA A 1 1 1 PAC ARI A o A l 1 2 e DE nn E E S 2 1 3 ruis A E E R 3 Chapter ZA Mera DB2 Doar hoen anon 4 24 Lavourtaud ie osea 4 22 the DE 5 2 9 Power up The IE Read exe DI deere aldea 9 Chapter 3 DE2 Control Panel siii 1 SN Control 0 11 2 2 Controlling the LEDs 7 Segment Displays and LCD 13 3 3 SDRAM SRAM Controller and Programmer eese nennen 14 AS Memory trotamundos 15 3 5 Overall Structure of the DE2 Control Panel cccccncnoonnnnnnnnnnnnnnnnnnonnnnnnnnnnnononannnnnnnnnos 17 3 6 TOOLS Multi Port SRAM SDRAM Flash 15 3 7 CONTO e E E E 20 Chapter 4 Usine the DEZ Board m ndame 24 4 Constan the Cyclone due T T 24 SB IDS AG VC E TE 26 4 3 Using the 7 segment 30 4 4 rore TIDI RE Tm 22 4 5 Usme me BB DI COT ERUNT 33 ZO Usi te Expansion uentus pipi leal 35 4 7 IA PP e En A 37 4S Using Te Fit GIO CODE
20. FLASH D5 FLASH A21 1 Q FLASH WE FLASH D4 W C FLASH RESET 4 F VCC33 LE FLASH D3 FLASH A19 FLASH D2 FLASH A18 FLASH A8 FLASH D1 FLASH A7 Q FLASH A6 o FLASH DO FLASH A5 FLASH OE FLASH A4 FLASH A3 FLASH CE TONO SE orem FLASH A2 FLASH A1 R43 4 7K S29AL032DTFN TSOP 48 FLASH OE Figure 4 25 Flash schematic 50 DRAM DOQJ9 DRAM DQ 10 DRAM DQ 11 DRAM DQ 12 DRAM DQ 13 DRAM DQ 14 DRAM DQ 15 DRAM BA 0 DRAM BA 1 DRAM LDOM DRAM_UDQM DRAM_RAS_N DRAM_CAS_N DRAM_CKE DRAM_CLK DRAM_WE_N DRAM_CS_N SRAM SRAM ADDR I SRAM ADDR 2 SRAM ADDR 3 SRAM ADDRIA4 SRAM ADDRI 5 SRAM SRAM_ADDRI7 SRAM ADDRI8 SRAM_ADDRI9 SRAM ADDR 10 SRAM_ADDR 11 SRAM ADDR 12 SRAM ADDR 13 SRAM ADDR 14 SRAM ADDR 15 DE2 User Manual PIN AB2 SDRAM Data 9 Table 4 16 SDRAM pin assignments 51 DE2 User Manual SRAM ADDR 16 PIN AB8 SRAM Address 16 Table 4 17 SRAM pin assignments 52 FL ADDR 10 FL ADDR 11 FL ADDR 12 FL ADDR 13 FL ADDR 14 FL ADDR 15 FL ADDR 16 FL ADDR 17 FL ADDR 18 FL ADDR 19 FL ADDR 20 FL ADDR 21 FL DQ O FL DQ 1 FL 2 FL 3 FL DQ 4 FL DQ 5 FL DQ 6 FL DQ 7 FL CEN FL OE N FL RST N FL WE N DE2 User Manual PIN AE17 FLASH Address 10 Table 4 18 Flash pin assignments 53 NOTE D Va DE2 User Manual Chapter 5 Examples of Advanced Demonstrations This chapter provi
21. MB SDRAM 512 KB SRAM 4 MB Flash Memory Figure 2 1 The DE2 board The DE2 board has many features that allow the user to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware 15 provided on the DE2 board e Altera Cyclone II 2C35 FPGA device e Altera Serial Configuration device EPCS16 e USB Blaster on board for programming and user API control both JTAG and Active Serial AS programming modes are supported e 512 Kbyte SRAM e 8 Mbyte SDRAM INDE 5 A DE2 User Manual 4 Mbyte Flash memory 1 Mbyte on some boards e SD Card socket e 4 pushbutton switches e 18 toggle switches e 18 red user LEDs e Ogreen user LEDs 50 MHBZz oscillator and 27 MHz oscillator for clock sources e 24 bit CD quality audio CODEC with line in line out and microphone in jacks e VGA DAC 10 bit high speed triple DACs with VGA out connector e TV Decoder NTSC PAL and TV in connector e 10 100 Ethernet Controller with a connector e USB Host Slave Controller with USB type A and type B connectors e RS 232 transceiver and 9 pin connector e PS 2 mouse keyboard connector IrDA transceiver e Two 40 pin Expansion Headers with diode protection In addition to these hardware features the DE2 board has software support for standard I O interfaces and a control panel facility for accessing various components Also software is provided for a number of demonstrations that illustrate
22. PGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off A schematic diagram that shows the pushbutton and toggle switches 15 given in Figure 4 4 A schematic diagram that shows the LED circuitry appears in Figure 4 5 A list of the pin names on the Cyclone II FPGA that are connected to the toggle switches 15 given in Table 4 1 Similarly the pins used to connect to the pushbutton switches and LEDs are displayed in Tables 4 2 and 4 3 respectively GND vi OVCC33 Aros ORAL 4 MEN RINT AA KEY I Ha VA KEYS 4 120 C17 C18 C18 0 10 0 10 l CND GND SWO SA SW SW3 SW SANT END GH D GHD GND VECI WECI WECIA WECIA WECIA 33 WECIA SWO SW 3 amp Ni GND GND GND GND GND GND GND GND GND GND GND GND GND GND DPDT SW DPDT SW DPDT Sw DPDT Sw DPDT Sw DPDT Sw cB cB c 10 ow GND GND GND GND GND MOD 33 MOD 3 WOG33 VIGO VIGO VICO SW10 SW11 SW12 SW13 GND GND GND GND GND GND GN GND GND GND GN GND R40 120 DPDT SW DPDT SW DPDT SW DPDT SW DPDT SW SW14 SW15 SW16 SW17 RN27 GND GND D GND nes SW17 VCC33 VCC33 VCC33 VCC33 Pee ii SAL GND GND GND GND gt SW14 GND GND 4 GND 4 GNO DPDT SW DPDT SW DPDT SW DPDT SW 120 Figure 4 4 Schematic diagram of the pushbutton and toggle switches Ar LEDRILEDR LEDR2LEDR A LEDRSLEDR GAO Fill Ar LEDRALEDR
23. SP1362 host and device schematic OTG ADDR 0 OTG ADDR 1 OTG DATA 0 OTG DATA 1 OTG_DATA 2 OTG DATA 3 OTG DATA 4 OTG_DATA 5 OTG_DATA 6 OTG DATA 7 OTG_DATA 8 OTG_DATA 9 OTG_DATA 10 OTG_DATA 11 OTG_DATA 12 OTG_DATA 13 OTG_DATA 14 OTG_DATA 15 INDE oA DE2 User Manual OTG CS N PIN F1 ISP1362 Chip Select Table 4 14 USB 15P1362 pin assignments 4 15 Using IrDA The DE2 board provides a simple wireless communication media using the Agilent HSDL 3201 low power infrared transceiver The datasheet for this device is provided in the DatasheetNrDA folder on the DE2 System CD ROM Note that the highest transmission rate supported is 115 2 Kbit s and both the TX and RX sides have to use the same transmission rate Figure 4 22 shows the schematic of the IrDA communication link Please refer to the following website for detailed information on how to send and receive data using the IrDA link http techtrain microchip com webseminars documents IrDA_BW pdf The pin assignment of the associated interface are listed in Table 4 15 IRDA R amp D IRDA TXD Figure 4 22 IrDA schematic 48 DE2 User Manual IRDA TXD PIN AE24 IRDA Transmitter IRDA RXD PIN AE25 IRDA Receiver Table 4 15 IrDA pin assignments 4 16 Using SDRAM SRAM Flash The DE2 board provides an 8 Mbyte SDRAM 512 Kbyte SRAM and 4 Mbyte 1 Mbyte on some boards Flash memory Figures 4 23 4 24 and 4 25 show the schematics of the mem
24. a template for other projects because it defines ports that correspond to all of the user accessible pins on the Cyclone II FPGA 5 2 TV Box Demonstration This demonstration plays video and audio input from a DVD player using the VGA output and audio CODEC on the DE2 board Figure 5 1 shows the block diagram of the design There are two major blocks in the circuit called 2C Config and TV_TO_VGA The TV_TO_VGA block consists of the itu r656 decoder Dual Port Line Buffer HsyncX2 YCrCb2RGB and VGA_Timing_Generator The figure also shows the TV Decoder ADV7181 and the VGA DAC ADV7123 chips used As soon as the bit stream is downloaded into the FPGA the register values of the TV Decoder chip are used to configure the TV decoder via the 126 AV Config block which uses the I2C protocol to communicate with the TV Decoder chip Following the power on sequence the TV Decoder chip will be unstable for a time period the Lock Detector 1s responsible for detecting this instability The itu 656 decoder block extracts YCrCb 4 4 4 video signals from the 4 2 2 data source sent from the TV Decoder It also generates a 13 5 MHz pixel clock YPixel Clock with blanking signals indicating the valid period of data output Because the video signal from the TV Decoder 1s interlaced we need to perform de interlacing on the data source We used the Dual Port Line Buffer block and Hsyncx2 block to perform the de interlacing operation where the pixel
25. anual Audio CODEC Wolfson WM8731 24 bit sigma delta audio CODEC Line level input line level output and microphone input jacks e Sampling frequency 8 to 96 KHz e Applications for MP3 players and recorders PDAs smart phones voice recorders etc VGA output e Uses the ADV7123 240 MHz triple 10 bit high speed video DAC e With 15 pin high density D sub connector e Supports up to 1600 x 1200 at 100 Hz refresh rate e Can be used with the Cyclone II FPGA to implement a high performance TV Encoder NTSC PAL TV decoder circuit e Uses ADV7181B Multi format SDTV Video Decoder Supports NTSC M J 4 43 PAL B D G H I M N SECAM e Integrates three 54 MHz 9 bit ADCs e Clocked from a single 27 MHz oscillator input e Multiple programmable analog input formats Composite video CVBS S Video Y C and YPrPb components Supports digital output formats 8 bit 16 bit ITU R BT 656 YCrCb 4 2 2 output HS VS and FIELD e Applications DVD recorders LCD TV Set top boxes Digital TV Portable video devices 10 100 Ethernet controller e Integrated MAC and PHY with a general processor interface e Supports 100Base T and IOBase T applications e Supports full duplex operation at 10 Mb s and 100 Mb s with auto MDIX e Fully compliant with the IEEE 802 3u Specification e Supports IP TCP UDP checksum generation and checking e Supports back pressure mode for half duplex mode flow control USB Host Slave controller Complies fully with U
26. aw Data button and a file named Raw Data Gray dat will be generated and stored in the same directory as the original image file You can change the file name prefix from Raw Data to another name by changing the File Name field in the displayed window Raw Data Gray dat 15 the raw data that can be downloaded directly into the SRAM on the DE2 board and displayed on the VGA monitor using the VGA controller IP described in the DE2 USB API project The mgConv tool will also generate Raw Data BW dat and its corresponding TXT format for the black and white version of the 1mage the threshold for judging black or white level 1s defined 1n the BW Threshold 22 DE2 User Manual 53 Terasic Image Converter Bw Threshold 128 Band of RGB Red Processed Line o File Name Raw D ata Figure 3 13 The image converter window Image Source R G B Band B amp W Output Result Filter Threshold 640x480 Filter Color Picture N A Raw Data Gray Color Picture R G B BW Threshold Raw Data BW optional Raw Data BW txt Grayscale N A N A Data Gray Picture Grayscale N A BW Threshold Raw Data BW Picture Raw Data BW txt Note Raw Data BW txt is used to fill in the MIF Intel Hex format for M4K SRAM 23 NOTE 5 Va DE2 User Manual Chapter 4 Using the DE2 Board This chapter gives instructions for using the DE2 board and describes each of its I O devices 4 1 Configuring the Cyclone II FPG
27. click on the Program Configure box which results in the image displayed in the figure Now click Start to download the configuration file into the FPGA 5 Start the executable DE2 control panel exe on the host computer The Control Panel user interface shown in Figure 3 2 will appear 6 Open the USB port by clicking Open Open USB Port 0 The DE2 Control Panel application will list all the USB ports that connect to DE2 boards The DE2 Control Panel can control up to 4 DE2 boards using the USB links The Control Panel will occupy the USB port until you close that port you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port 11 DE2 User Manual 7 The Control Panel 15 now ready for use experiment by setting the value of some 7 segment display and observing the result on the DE2 board Chain1 cdf ul E E Hardware Setup USB Blaster USB 0 Mode JTAG Progress 3 El DR DEZ sustem DE2 control panel DEZ USB_SPLsof EP2CSSFB 2 E C FREPERERE 0 mm Auto Detect Delete Ga Add File EE Change File Add Device Figure 3 1 Quartus II Programmer window IE DE2 Control Panel Open Help About FLASH SDRAM sSRAM PS2 7 SEG LED amp LCD aa HE 6 HEX 5 HEx 4 HEX 3 HEA 2 HEN HE 0 FS2 Keyboard Figure 3 2 The DE2 Control Panel The concept of the DE2 Control Panel 1s illustrated 1n F
28. clock 1s changed 55 DE2 User Manual to 27 MHz from 13 5 MHz and the Hsync is changed to 31 4 kHz from 15 7 kHz Internally the Dual Port Line Buffer uses a 1 Kbyte long dual port SRAM to double the YCrCb data amount Y x 2 Cr x 2 Cb x 2 signals in the block diagram Finally the YCrCb2RGB block converts the YCrCbx2 data into RGB output The VGA Timing Generator block generates standard VGA sync signals HS and VS to enable the display on a VGA monitor TD DATA 7 0 Cr 7 0 VGA R 9 0 VGA R TD HS Cb 7 0 Dual Port L_Ct17 0 2 yeber pr VGA_G Blank e Blank er To ROB VGA B TD VS i cock Cb 7 0 x2 VGA B 9 0 VGA B IV NT TS K mTD HSx2 Video DAC OSC 27 7123 120 SCLK VGA BLANK Decoder TD HS Tp ns mTD_HSx2 mai osc 27 x2 VGA SYNC I2C SDAT 7181 osc 27 VGA CLK I2C AV Config RESET DASA Lock Sync en TD HS Detector OSC_50 _ Cyclone Il 2C35 VGA D SUB Figure 5 1 Block diagram of the TV box demonstration Demonstration Setup File Locations and Instructions e Project directory DE2 TV e Bit stream used DE2 TV sof or DE2_TV pof e Connect a DVD player s composite video output yellow plug to the Video in RCA jack of the DE2 board The DVD player has to be configured to provide NTSC output o 60 Hz refresh rate o 4 3 aspect ratio Non progressive video e Connect the VGA output of the DE2 board to a VGA monitor both LCD and CRT type
29. des a number of examples of advanced circuits implemented on the DE2 board These circuits provide demonstrations of the major features on the board such as its audio and video capabilities and USB and Ethernet connectivity For each demonstration the Cyclone II FPGA or EPCS16 serial EEPROM configuration file 15 provided as well as the full source code in Verilog HDL code All of the associated files can be found in the DE2_demonstrations folder from the DE2 System CD ROM For each of demonstrations described in the following sections we give the name of the project directory for its files which are subdirectories of the DE2 demonstrations folder Installing the Demonstrations To install the demonstrations on your computer perform the following l Copy the directory DE2 demonstrations into a local directory of your choice It is important to ensure that the path to your local directory contains no spaces otherwise the Nios II software will not work 2 Inthe directory DE2 demonstrations go to the subdirectory fixpaths 3 Run the DE2 fixpaths bat batch file In the dialog box that pops up select the directory DE2 demonstrations in your local directory where you copied the files to Click OK 4 When fixpaths 1s finished press any key to complete the process 5 1 DE2 Factory Configuration The DE2 board 15 shipped from the factory with a default configuration that demonstrates some of the basic features of the board The setup requ
30. e Configure button to enable the connection from the Flash Memory to the Asynchronous Port 1 of the Flash Controller indicated in Figure 3 7 4 Set toggle switches SWI and SWO to OFF DOWN position and ON UP position respectively 5 Plug your headset or a speaker into the audio output jack and you should hear the music played from the Audio DAC circuit 6 Note that the Asynchronous Port 1 is connected to the Audio DAC part as shown in Figure 3 7 Once you selected Asynchronous Port 1 and clicked the Configure button the Audio DAC Controller will communicate with the Flash memory directly In our example the AUDIO DAC Verilog module defines a circuit that reads the contents of the Flash memory and sends it to the external audio chip 19 NOTE DVA DE2 User Manual 3 7 VGA Display Control The Control Panel provides a tool with the associated IP that allows the user to display an image via the VGA output port To illustrate this feature we will show how an image can be displayed on a VGA monitor Perform the following steps to display a default image Select the VGA tab in the Control Panel to reach the window in Figure 3 9 IE DE2 Control Panel Open Help About P52 amp 7 SEG LED amp LCD TOOLS FLASH SDRAM SRAM VGA ABIERA DE2 Board Cursor 180 Cursor 60 M Detault image Figure 3 9 Displayed image and the cursor controlled by the scroll bars e Make sure that the checkboxes Default Image and
31. e of the board s 7 segment displays and also on the green LEDs If the user clicks on the Clear button in the window panel of the software driver the host computer sends a different USB packet to the board which causes the Nios II processor to clear the hardware counter to zero 59 NBrs DE2 User Manual Link to Host PC Setup Package p u Philips Enumeration Information Device Port Communication Figure 5 5 Block diagram of the USB device demonstration Demonstration Setup File Locations and Instructions e Project directory DE2_NIOS_DEVICE_LED HW e Bit stream used DE2_NIOS_DEVICE_LED sof or pof e Nios II Workspace DE2_NIOS_DEVICE_LEDIHW e Borland BC Software Driver DE2_NIOS_DEVICE_LED SW e Load the bit stream into FPGA e Run Nios IL IDE with HW as the workspace Click on Compile and Run e Connect the USB Device connector of the DE2 board to the host computer using a USB cable type A gt B A new USB hardware device will be detected e Specify the location of the driver as DE2 NIOS DEVICE LED D12test inf Philips PDIUSBDI2 SMART Evaluation Board Ignore any warning messages produced during installation e The host computer should report that a Philips PDIUSBDI2 SMART Evaluation Board is now installed e Execute the software DE2 NIOS DEVICE LED SW ISP1362DcUsb exe on the host computer Then experiment with the software by clicking on the ADD and Clear buttons Figure 5 6 illustrates t
32. eckbox Default Image The VGA monitor should display the picture dat image from the SRAM as depicted in Figure 3 12 You can turn off the cursor by deselecting the Cursor Enable checkbox Host Port Usar Port 1 Asyne 1 SDRAM User Port 2 Async 2 Controller User Port 3 Async 3 SDRAM Host Port USB User Port 1 Async 1 Flash Blaster User Port 2 Async 2 Controller User Port 3 Async 3 Host Port DE2 Control Panel SRAM Usar Port 3 Asyine 3 Controller User Port 2 Asynie 2 User Port 1 Async 1 USB Command Controller VGA DAC ILCD CR Monitor Controller Figure 3 11 Multi Port Controller configured to display an image from the SRAM 21 DE2 User Manual Figure 3 12 A displayed image You can display any image file by loading 1t into the SRAM chip or into an M4K memory block in the Cyclone II chip This requires generating a bitmap file which may be done as follows 1 Ze Load the desired image into an image processing tool such as Corel PhotoPaint Resample the original image to have a 640 x 480 resolution Save the modified image in the Windows Bitmap format Execute DE2 control paneNmgConv exe an image conversion tool developed for the DE2 board to reach the window in Figure 3 13 Click on the Open Bitmap button and select the 640 x 480 Grayscale photo for conversion When the processing of the file is completed click on the Save R
33. er on the DE2 System CD ROM Figure 4 16 shows the related schematics and Table 4 10 lists the Cyclone II FPGA pin assignments UART RXD A RXD LEDR Ayo RN24 330 VCC330 TXD LEDG Ss UART_TXD pas 1U C14 1U C15 C16 1U 1U GND GND Figure 4 16 MAX232 RS 232 chip schematic UART RXD PIN C25 UART Receiver UART TXD PIN B25 UART Transmitter Table 4 10 RS 232 pin assignments 4 10 PS 2 Serial Port The DE2 board includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 4 17 shows the schematic of the PS 2 circuit Instructions for using a PS 2 mouse or keyboard can be found by performing an appropriate search on various educational web sites The pin assignments for the associated interface are shown in Table 4 11 VCC5 VCC5 O O R36 R37 2K 2K PS2 DAT R38 120 lt lt PS2 CIK E A gt vCC5 D1 D2 O BAT54S BAT54S T t w GND VCC33GND Figure 4 17 PS 2 schematic NBrs DA DE2 User Manual PS2 CLK PIN D26 PS 2 Clock PS2 DAT PIN C24 PS 2 Data Table 4 11 PS 2 pin assignments 4 11 Fast Ethernet Network Controller The DE2 board provides Ethernet support via the Davicom DM9000A Fast Ethernet controller chip The DM9000A includes a general processor interface 16 Kbytes SRAM a media access control MAC unit and a 10 100M PHY transceiver Figure 4 18 shows the schematic for the Fast Ethernet interface and the associated pin assignments are
34. guration Device Figure 4 1 The JTAG configuration scheme Configuring the EPCS16 in AS Mode Figure 4 2 illustrates the AS configuration set up To download a configuration bit stream into the EPCS16 serial EEPROM device perform the following steps Ensure that power 15 applied to the DE2 board Connect the supplied USB cable to the USB Blaster port on the DE2 board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the PROG position The EPCS16 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the pof filename extension Once the programming operation 15 finished set the RUN PROG switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS16 device to be loaded into the FPGA chip 25 JA OF m AN DE2 User Manual USB Blaster Circuit RUN PROG Quartus II AS Mode Programmer Config AS Mode Kd JTAG Config Port Power on Config EPCS16 Serial Configuration Device Figure 4 2 The AS configuration scheme In addition to its use for JTAG and AS programming the USB Blaster port on the DE2 board can also be used to control some of the board s features remotely from a host computer Details that describe this method of using the USB Blaster port are given in Chapter 3 4
35. he setup for this demonstration 60 DE2 User Manual Figure 5 6 The setup for the USB paintbrush demonstration 5 5 A Karaoke Machine This demonstration uses the microphone in line in and line out ports on the DE2 board to create a Karaoke Machine application The Wolfson WM8731 audio CODEC is configured in the master mode where the audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically As indicated in Figure 5 7 the I2C interface is used to configure the Audio CODEC The sample rate and gain of the CODEC are set in this manner and the data input from the line in port 15 then mixed with the microphone in port and the result is sent to the line out port For this demonstration the sample rate 15 set to 48 kHz Pressing the pushbutton KEYO reconfigures the gain of the audio CODEC via the I2C bus cycling through one of the ten predefined gains volume levels provided by the device I2C Audio j Line out Configuration Audio ines Push Button CODEC ne Piper Mic in ADC to DAC 61 DE2 User Manual Figure 5 7 Block diagram of the Karaoke Machine demonstration Demonstration Setup File Locations and Instructions e Project directory DE2_i2sound e Bit stream used i2sound sof or i2sound pof e Connect a microphone to the microphone in port pink color on the DE2 board e Connect the audio output of a music player such as an MP3 player or computer to
36. ignments for the LCD module 34 INDE D n DE2 User Manual e n A 4 6 Using the Expansion Header The DE2 Board provides two 40 pin expansion headers Each header connects directly to 36 pins on the Cyclone II FPGA and also provides DC 45V VCC5 DC 3 3V VCC33 and two GND pins Figure 4 10 shows the related schematics Each pin on the expansion headers 15 connected to two diodes and a resistor that provide protection from high and low voltages The figure shows the protection circuitry for only four of the pins on each header but this circuitry 15 included for all 72 data pins Table 4 7 gives the pin assignments I AO I AT lc AS px 5 VECI 0 C 5 al 2 GND EL E f Al d DA GNb ves f protection resistors and diodes i Dim not shown for other ports gs q Dm lo Bo Bi Ia Be y ER VECS GND protection resistors and diodes s E xs not shown for other ports DE s DE2 User Manual GPIO 10 PIN N18 GPIO Connection O 10 36 NOTE D Va DE2 User Manual GPIO 1 11 PIN_P24 GPIO Connection 1 11 Table 4 7 Pin assignments for the expansion headers 4 7 Using VGA The DE2 board includes a 16 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone II FPGA and the Analog Devices ADV7123 triple 10 bit high speed video DAC is used to produce the analog data signals red green and blue The associated schematic 15 given
37. igure 3 3 The IP that performs the control functions is implemented in the FPGA device It communicates with the Control Panel window which 15 active on the host computer via the USB Blaster link The graphical interface 15 used to issue commands to the control circuitry The provided IP handles all requests and performs data transfers between the computer and the DE2 board 12 DE2 User Manual 7 SEG Display Gp Bep Abe PS amp 7 5EG LED E LCD TOOLS FLASH SORAM SRAM TGA SDRAM Fandom cca ss Address 7 DATA Inn DATA omn USB SDRAM i Blaster Flash SRAM Figure 3 3 The DE2 Control Panel concept The DE2 Control Panel can be used to change the values displayed on 7 segment displays light up LEDs talk to the PS 2 keyboard read write the SRAM Flash Memory and SDRAM load an image pattern to display as VGA output load music to the memory and play music via the audio DAC The feature of reading writing a byte or an entire file from to the Flash Memory allows the user to develop multimedia applications Flash Audio Player Flash Picture Viewer without worrying about how to build a Flash Memory Programmer 3 2 Controlling the LEDs 7 Segment Displays and LCD Display A simple function of the Control Panel is to allow setting the values displayed on LEDs 7 segment displays and the LCD character display In the window shown in Figure 3 2 the values to be displayed by the 7 segment displays
38. in Figure 4 11 and can support resolutions of up to 1600 x 1200 pixels at 100 MHz 37 DE2 User Manual VGA VCC5 R A TK RSET R 560 BC117 BC118 GHD 0 1 dd oun VGA GO VGA Gl VGA Ge OR VGA R VGA G3 ar Hi C VGA G VGA G4 3 n GA B R97 VGA 5 E VGA G6 VGA G7 WGA Gg REG Roy gt ROS VGA G8 i 7S 7S fo VGA BLANK END GND GND VGA HS VGA Vs 23 LOFP48 0 5 4 VGA VECS OVGA VECS GND DBIS RA F2 BC 120 BC121 01u 0711 GND GND GND e m ea ea ab 28 en ea en Biia sess ss dalla C O E c c cC Coco SSIS SHS Figure 4 11 VGA circuit schematic The timing specification for VGA synchronization and RGB red green blue data can be found on various educational web sites for example search for VGA signal timing Figure 4 12 illustrates the basic timing requirements for each row horizontal that is displayed on a VGA monitor An active low pulse of specific duration time a in the figure is applied to the horizontal synchronization Async input of the monitor which signifies the end of one row of data and the start of the next The data RGB inputs on the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed
39. ired for this demonstration and the locations of its files are shown below Demonstration Setup File Locations and Instructions e Project directory DE2 Default e Bit stream used DE2 Default sof or DE2 Default pof 54 INDE 5 A DE2 User Manual e Power on the DE2 board with the USB cable connected to the USB Blaster port If necessary that is if the default factory configuration of the DE2 board is not currently stored in EPCS16 device download the bit stream to the board by using either JTAG or AS programming e You should now be able to observe that the 7 segment displays are displaying a sequence of characters and the red and green LEDs are flashing Also Welcome to the Altera DE2 Board is shown on the LCD display Optionally connect a VGA display to the VGA D SUB connector When connected the VGA display should show a pattern of colors e Optionally connect a powered speaker to the stereo audio out jack e Place toggle switch SW17 in the UP position to hear a 1 kHz humming sound from the audio out port Alternatively if switch SW17 1s DOWN the microphone in port can be connected to a microphone to hear voice sounds or the line in port can be used to play audio from an appropriate sound source The Verilog source code for this demonstration 15 provided in the DE2 Default folder which also includes the necessary files for the corresponding Quartus II project The top level Verilog file called DE2 Default v can be used as
40. k signals to the audio CODEC The design also mixes the data from microphone in with line in for the Karaoke style effects I2C Audio recut Configuration Nios Audio DAC Audio CPU Controller CODEC i dig Mic in ADC to DAC Figure 5 11 Block diagram of the SD music player demonstration Demonstration Setup File Locations and Instructions e Project directory DE2 SD Audio e Bit stream used DE2 SD Card Audio sof or pof e Nios Il Workspace DE2 SD Card Audio e Format your SD card into FAT 6 format e To play a music file with this demonstration the file must use the WAV format Copy one or more such WAV files onto the FAT16 formatted SD Card Due to a limitation in the software used for this demonstration it is necessary to reformat the whole SD Card if any WAV file that has been copied onto the card needs to be later removed from the SD Card e Load the bit stream into the FPGA e Run the Nios II IDE under the workspace DE2 SD Card Audio e Connect a headset or speaker to the DE2 board and you should be able to hear the music played from the SD Card Figure 5 12 illustrates the setup for this demonstration 65 DE2 User Manual alo NECI with music files WAV Figure 5 12 The setup for the SD music player demonstration Copyright O 2005 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other
41. l Table 4 8 ADV7123 pin assignments 40 INDE 5 A DE2 User Manual 4 8 Using the 24 bit Audio CODEC The DE2 board provides high quality 24 bit audio via the Wolfson WMS 8731 audio CODEC enCOder DECoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The WMS8731 is controlled by a serial I2C bus interface which is connected to pins on the Cyclone II FPGA A schematic diagram of the audio circuitry 15 shown in Figure 4 15 and the FPGA pin assignments are listed in Table 4 9 Detailed information for using the WM8731 codec is available in its datasheet which can be found on the manufacturer s web site and from the Datasheet folder on the DE2 System CD ROM I2C ADDRESS READ IS 0x34 I2C AD x3 i C DRESS WRITE IS 0x35 AGND AGND C5 47K 1000P AGND AGND AGND gt AUD DACDAT UD DACLRCK C 1210 BC1 BC2 BC3 BC4 0 1U 0 1U 0 1U 0 1U R12 0 SND AGND Figure 4 15 Audio CODEC schematic PIN_C5 Audio CODEC ADC LR Clock PIN_B5 Audio CODEC ADC Data PIN C6 Audio CODEC DAC LR Clock Table 4 9 Audio CODEC pin assignments 41 INDE Ya DE2 User Manual 4 9 RS 232 Serial Port The DE2 board uses the MAX232 transceiver chip and a 9 pin D SUB connector for RS 232 communications For detailed information on how to use the transceiver refer to the datasheet which is available on the manufacturer s web site and from the Datasheet fold
42. lock in the Cyclone II chip The connection between the Audio DAC Controller and a lookup table in the FPGA is used to produce a test audio signal of 1 kHz To let users implement and test their IP cores written in Verilog without requiring them to implement complex API Host control software and memory SRAM SDRAM Flash controllers we provide an integrated control environment consisting of a software controller in C a USB command controller and a multi port SRAM SDRAM Flash controller 1 DE2 User Manual 7 SEG LUT JTAG T SEG USB Blaster O Link Serial to Parallel Hardware Conversion i LED A PS 2 Controller Keyboard USB Link ATERN DE Board PC Side DE2 Control Panel Y LCD Controller Host Port User Port 3 Async 3 4 SDRAM User Port 2 Async 2 4 Controller User Port 1 Async 1 4 Host Port User Port 3 Async 3 4 SRAM User Port 2 Async 2 4 Controller User Port 1 Async 1 FPGA VGA DAC Memory Controller Host Port User Port 3 Async 3 Flash UserPort2 Async 2 Controller User Port1 Async 1 1 kHz Sine Wave Audio DAC Look up Table Controller 16x2 LCD Module SDRAM Memory SRAM Memory BR VGA LCD CRT DAC Monitor Flash Memory Audio 1 DAC Figure 3 7 The DE2 Control Panel block diagram Users can connect circuits of their own design to one of the User P
43. lt VGA output pattern 10 NOTE 5 DE2 User Manual Chapter 3 DE2 Control Panel The DE2 board comes with a Control Panel facility that allows a user to access various components on the board through a USB connection from a host computer This chapter first presents some basic functions of the Control Panel then describes its structure in block diagram form and finally describes its capabilities 3 1 Control Panel Setup To run the Control Panel application it 15 first necessary to configure a corresponding circuit in the Cyclone II FPGA This is done by downloading the configuration file DE2_USB_API sof into the FPGA The downloading procedure is described in Section 4 1 In addition to the DE2 USB APL sof file it is necessary to execute on the host computer the program DE2 control panel exe Both of these files are available on the DE2 System CD ROM that accompanies the DE2 board in the directory DE2 control panel Of course these files may already have been installed to some other location on your computer system To activate the Control Panel perform the following steps 1 Connect the supplied USB cable to the USB Blaster port connect the 9V power supply and turn the power switch ON 2 Set the RUN PROG switch to the RUN position start the Quartus II software Select Tools gt Programmer to reach the window in Figure 3 1 Click on Add File and in the pop up window that appears select the DE2 USB 5 file Next
44. n the Nios II processor 15 started it will detect the existence of the USB mouse connected to DE2 board Once the mouse 15 moved the Nios II processor 15 able to keep track of the movement and record it in a frame buffer memory The VGA Controller will overlap the 57 DE2 User Manual data stored in the frame buffer with a default image pattern and display the overlapped image on the VGA display Philips ISP1362 Host Altera Avalon Figure 5 3 Block diagram of the USB paintbrush demonstration Demonstration Setup File Locations and Instructions Project directory DE2 NIOS HOST MOUSE VGA Bit stream used DE2 _ NIOS HOST MOUSE VGA sof Nios II Workspace DE2 NIOS HOST MOUSE VGA e Connect a USB Mouse to the USB Host Connector type A of the DE2 board e Connect the VGA output of the DE2 board to a VGA monitor both LCD and CRT type of monitors should work Load the bit stream into FPGA e Run the Nios II and choose DE2_NIOS_HOST_MOUSE_VGA as the workspace Click on the Compile and Run button e You should now be able to observe a blue background with an Altera logo on the VGA display e Move the USB mouse and observe the corresponding movements of the cursor on the screen Left click mouse to draw white dots lines and right click the mouse to draw blue dots lines on the screen 58 DE2 User Manual Figure 5 4 illustrates the setup for this demonstration VGA Out USB Device TE VGA Driver Controlle
45. niversal Serial Bus Specification Rev 2 0 e Supports data transfer at full speed and low speed e Supports both USB host and device e Two USB ports one type A for a host and one type B for a device NOTE 5 DE2 User Manual e Provides a high speed parallel interface to most available processors supports Nios II with a Terasic driver e Supports Programmed I O PIO and Direct Memory Access DMA Serial ports e One RS 232 port e One PS 2 port DB 9 serial connector for the RS 232 port e PS 2 connector for connecting a PS2 mouse or keyboard to the DE2 board IrDA transceiver e Contains a 115 2 kb s infrared transceiver e 32mALED drive current e Integrated EMI shield e EC825 1 Class 1 eye safe e Edge detection input Two 40 pin expansion headers e 72 Cyclone II I O pins as well as 8 power and ground lines are brought out to two 40 pin expansion connectors e 40 pin header is designed to accept a standard 40 pin ribbon cable used for IDE hard drives e Diode and resistor protection is provided 2 3 Power up the DE2 Board The DE2 board comes with a preloaded configuration bit stream to demonstrate some features of the board This bit stream also allows users to see quickly if the board 15 working properly To power up the board perform the following steps 1 Connect the provided USB cable from the host computer to the USB Blaster connector on the DE2 board For communication between the host and the DE2 board it 1s necessary
46. ntire Flash checkbox to indicate that you want to copy the entire contents of the Flash memory into a specified file Click on the Load Flash Content to a File button to activate the reading process 3 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner 3 5 Overall Structure of the DE2 Control Panel The DE2 Control Panel facility communicates with a circuit that 1s instantiated 1n the Cyclone II FPGA This circuit 15 specified in Verilog code which makes it possible for a knowledgeable user to change the functionality of the Control Panel The code is located inside the DE2 demonstrations directory on the DE2 System CD ROM To run the Control Panel the user must first set it up as explained in Section 3 1 Figure 3 7 depicts the structure of the Control Panel Each input output device 1s controlled by a controller instantiated in the FPGA chip The communication with the PC 1s done via the USB Blaster link A Command Controller circuit interprets the commands received from the PC and performs the appropriate actions The SDRAM SRAM and Flash Memory controllers have three user selectable asynchronous ports in addition to the Host port that provides a link with the Command Controller The connection between the VGA DAC Controller and the FPGA memory allows displaying of the default image shown on the left side of the figure which 1s stored in an M4K b
47. orts of the SRAM SDRAM Flash controller Then they can download binary data into the SRAM SDRAM Flash Once the data 15 downloaded to the SDRAM Flash users can configure the memory controllers so that their circuits can read write the SDRAM Flash via the User Ports connected 3 6 TOOLS Multi Port SRAM SDRAM Flash Controller The TOOLS page of the Control Panel GUI allows selection of the User Ports We will illustrate a typical process by implementing a Flash Music Player The music data is loaded into the Flash memory User Port 1 1n the Flash Controller is used to send the music data to the Audio DAC Controller and hence to the audio output jack 18 NOTE DVA DE2 User Manual You can implement this application as follows 1 Erase the Flash memory as explained in Section 3 4 Then write a music file into the Flash memory You can use the file music wav in the directory DE2_demonstrations nusic on the DE2 System CD ROM 2 In the DE2 Control Panel select the TOOLS tab to reach the window in Figure 3 8 IE DE2 Control Panel Open Help About FLASH SDRAM SRAM VvGA PS2 amp 7 SEG LED amp LCD TOOLS SDRAM Multiplexer Host USB Port FLASH Multiplexer Asynchronous 1 SRAM Multiplexer Host USB Port Board Test Figure 3 8 TOOLS window of the DE2 Control Panel 3 Select the Asynchronous 1 port for the Flash Multiplexer and then click on the Configure button to activate the port You need to click th
48. ory chips The pin assignments for each device are listed in Tables 4 16 4 17 and 4 18 The datasheets for the memory chips are provided in the Datasheet folder on the DE2 System CD ROM U17 R_VCC33 4 GND DRAM_DO 5 DRAM D15 R VCC33 5 GND DRAM D1 5 DRAM D14 DRAM D2 50 DRAM D13 GND 6 40 R_VCC33 DRAM D3 AR DRAM D12 DRAM D4 a DRAM D11 R_VCC33 E GND DRAM D5 D DRAM D410 DRAM DG La DRAM_D9 GND R_VCC33 DRAM Dr E DRAM R_VCC33 A GND DRAM LDGOM AQ DRAM WE 6 9 DRAM UDQM DRAM_CAS 3 DRAM CLK DRAM RAS DRAM_CKE DRAM CS 19 E DRAM_BAD i DRAM A11 DRAM BA1 DRAM A39 DRAM A10 DRAM A8 DRAM AO DRAM A7 DRAM A1 DRAM A6 DRAM 10 DRAM A5 DRAM A3 DRAM A4 R_VCC33 GND SDRAM 1Mx16x4 DIP54 TSOP Figure 4 23 SDRAM schematic SRAM_A0 SRAM A17 SRAM_A1 4 SRAM A16 SRAM AZ 42 SRAM_A15 SRAM A3 41 SRAM OE SRAM A4 4 SRAM UB SRAM CE 2 gj SRAM_LB SRAM DO n SRAM SRAM D1 E 7 SRAM D14 SRAM_D2 5 SRAM D13 SRAM D3 i SRAM D12 R VCC33 4 GND GND OR VCC33 SRAM D4 SRAM D11 SRAM D5 F SRAM D10 SRAM D6 SRAM D8 SRAM D7 9g SRAM DS SRAM WE E SRAM_A5 8 7 SRAM A14 SRAM A SRAM A13 SRAM_A7 SRAM A12 SRAM 4 SRAM ATi SRAM AS 3 SRAM A10 IS61LV25616 DIP44 TSOP Figure 4 24 SRAM schematic 49 N DTE SYN DE2 User Manual u20 FLASH A16 FLASH A17 FLASH A15 FLASH A14 GND FLASH A13 FLASH AO GND FLASH A12 FLASH D7 FLASH A11 FLASH A10 FLASH D6 FLASH A9 FLASH A20 Q 4n
49. ower 15 turned on the configuration data in the EPCS16 device 15 automatically loaded into the Cyclone II FPGA The sections below describe the steps used to perform both JTAG and AS programming For both methods the DE2 board 15 connected to a host computer via a USB cable Using this connection the board will be identified by the host computer as an Altera USB Blaster device The process for installing on the host computer the necessary software device driver that communicates with the USB Blaster 15 described in the tutorial Getting Started with Altera s DE2 Board This tutorial 1s available on the DE2 System CD ROM and from the Altera DE2 web pages 24 DE2 User Manual Configuring the FPGA in JTAG Mode Figure 4 1 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone II FPGA perform the following steps Ensure that power 15 applied to the DE2 board Connect the supplied USB cable to the USB Blaster port on the DE2 board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the RUN position The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension USB Blaster Circuit cr PROG RUN l Quartus Il USD JTAG Config Sian HTML RUN denim JTAG Config Port Auto Power on Config EPCS16 Serial Confi
50. p LEDRSLEOR B LEA LEDRGLEDR af LEDR7LEDR e RNA af LEDRBLEDR Po d LEDRSLEUR A LEDGSLEDG LEDRTPREDR LEDRTREOR HA LEDRTAREDR AF LELDRISEUH ae LEDRTBEUR A LEDRILEDR GHU AF HN3 LET Na Dis 1 M 1 LES LED FF LEs LED AF LEDG3LEDG GAD le AF LED LE Dr AF B LEDGSLEDG l AM LEDESLEDE ae LECMSTLEDG GHD Figure 4 5 Schematic diagram of the LEDs DE2 User Manual Table 4 1 Pin assignments for the toggle switches 28 DE2 User Manual Table 4 2 Pin assignments for the pushbutton switches Table 4 3 Pin assignments for the LEDs 29 DE2 User Manual 4 3 Using the 7 segment Displays The DE2 Board has eight 7 segment displays These displays are arranged into two pairs and a group of four with the intent of displaying numbers of various sizes As indicated in the schematic in Figure 4 6 the seven segments are connected to pins on the Cyclone II FPGA Applying a low logic level to a segment causes it to light up and applying a high logic level turns it off Each segment in a display is identified by an index from 0 to 6 with the positions given in Figure 4 7 Note that the dot in each display is unconnected and cannot be used Table 4 4 shows the assignments of FPGA pins to the 7 segment displays I eg ANS REC HEXE DO n YT TT WwOC33 LLL rj
51. quential Read Address 0 Length 0 Entire Flash Load FLASH Contentto a File Figure 3 6 Flash memory control window A byte of data can be written into a random location on the Flash chip as follows 1 Click on the Chip Erase button The button and the window frame title will prompt you to wait until the operation 1s finished which takes about 20 seconds 2 Enter the desired address into the Address box and the data byte into the wDATA box Then click on the Write button To read a byte of data from a random location enter the address of the location and click on the Read button The rDATA box will display the data read back from the address specified The Sequential Write function 1s used to load a file into the Flash chip as follows l Specify the starting address and the length of data in bytes to be written into the Flash memory You can click on the File Length checkbox to indicate that you want to load the entire file 16 NOTE 5 DE2 User Manual 2 Click on the Write a File to Flash button to activate the writing process 3 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Sequential Read function 15 used to read the data stored in the Flash memory and write this data into a file as follows 1 Specify the starting address and the length of data in bytes to be read from the Flash memory You can click on the E
52. r IP SRAM Video FrameBuffer DE2 Board Www terasic com VGA Monitor Figure 5 4 The setup for the USB paintbrush demonstration 5 4 USB Device Most USB applications and products operate as USB devices rather than USB hosts In this demonstration we show how the DE2 board can operate as a USB device that can be connected to a host computer As indicated in the block diagram in Figure 5 5 the Nios II processor is used to communicate with the host computer via the host port on the DE2 board s Philips ISP1362 device After connecting the DE2 board to a USB port on the host computer a software program has to be executed on the Nios II processor to initialize the Philips ISP1362 chip Once the software program is successfully executed the host computer will identify the new device in its USB device list and ask for the associated driver the device will be identified as a Philips PDIUSBDI2 SMART Evaluation Board After completion of the driver installation on the host computer the next step is to run a software program on the host computer called SPI1362DcUsb exe this program communicates with the DE2 board In the JSP1362DcUsb program clicking on the Add button in the window panel of the software causes the host computer to send a particular USB packet to the DE2 board the packet will be received by the Nios II processor and will increment the value of a hardware counter The value of the counter is displayed on on
53. rd to store music or video files Such players may also include high quality DAC devices so that good audio quality is produced The DE2 board provides the hardware and software needed for SD card access and professional audio performance so that it is possible to design advanced multimedia products using the DE2 board In this demonstration we show how to implement an SD Card Music Player on the DE2 board in which the music files are stored in an SD card and the board can play the music files via its CD quality audio DAC circuits We use the Nios II processor to read the music data stored in the SD Card and use the Wolfson WM 8731 audio CODEC to play the music The audio CODEC is configured in the slave mode where external circuitry must provide the ADC DAC serial bit clock BCK and left right channel clock LRCK to the audio CODEC As shown in Figure 5 11 we provide an Audio DAC Controller to achieve the clock generation and the data flow control The Audio DAC Controller is integrated into the Avalon bus architecture so that the Nios II processor can control the application 64 YA DE2 User Manual During operation the Nios II processor will check if the FIFO memory of the Audio DAC Controller becomes full If the FIFO is not full the processor will read a 512 byte sector and send the data to the FIFO of the Audio DAC Controller via the Avalon bus The Audio DAC Controller uses a 48 kHz sample rate to send the data and cloc
54. same MAC address or 1s a broadcast packet the DM9000A will accept the packet and send an interrupt to the Nios II processor The processor will then display the packet contents 1n the Nios II IDE console window 64 Bytes Data mm 64 Bytes Data 4 Bytes Checksum 64 Bytes Data 4 Bytes Checksum Nios Il Interrupt Davicom 4 CPU 4 DM9000A Read Data Ethernet 64 Bytes Data 4 Bytes Checksum A Figure 5 9 Packet sending and receiving using the Nios II processor Demonstration Setup File Locations and Instructions e Project directory DE2 NET e Bit stream used DE2_NET sof or DE2_NET pof e Nios II Workspace DE2 NET e Plug a CATS5 loop back cable into the Ethernet connector of DE2 e Load the bit stream into the FPGA e Run the Nios IL IDE under the workspace DE2 NET e Click on the Compile and Run button e You should now be able to observe the contents of the packets received 64 byte packets sent 68 byte packets received because of the extra checksum bytes 63 DE2 User Manual Figure 5 10 illustrates the setup for this demonstration 10 100Mbps CAT 5 Cable DEUM Loopback LLL le j Device a A L TUTTE TTT ATT TTT eT ea i i EL T a H Ethernet Driver Figure 5 10 The setup for the Ethernet demonstration 5 7 SD Card Music Player Many commercial media audio players use a large external storage device such as an SD card or CF ca
55. the advanced capabilities of the DE2 board In order to use the DE2 board the user has to be familiar with the Quartus II software The necessary knowledge can be acquired by reading the tutorials Getting Started with Altera s DE2 Board and Quartus II Introduction which exists in three versions based on the design entry method used namely Verilog VHDL or schematic entry These tutorials are provided in the directory DE2_tutorials on the DE2 System CD ROM that accompanies the DE2 board and can also be found on Altera s DE2 web pages 2 2 Block Diagram of the DE2 Board Figure 2 2 gives the block diagram of the DE2 board To provide maximum flexibility for the user all connections are made through the Cyclone II FPGA device Thus the user can configure the FPGA to implement any system design DE2 User Manual 50 Mhz 27 Mhz Extin USB 2 0 Host Device 10 100 Ethernet P hy MAC SD Card Cyclone FPGA 2035 IrDA Transceiver Flash 1 Mbyte User Green LEDs 8 SDRAM 8 Mbytes 16 bit Audio CODEC VGA 10 bit Video DAC PS2 amp RS 232 Ports Toggle Switches 18 User Red LEDs 18 16x 2 LCD Module SRAM 512 Kbytes 7T SegmentDisplay 8 f Expansion Headers 2 Pushbutton Switches 4 EPCS16 Config Device USB Blaster Figure 2 2 Block diagram of the DE2 board Following is more detailed information about the blocks in Figure 2 2 Cyclone II 2C35 FPGA e 33 216 LEs e 1
56. to install the Altera USB Blaster driver software If this driver 15 not already installed on the host computer it can be installed as explained in the tutorial Getting Started with Altera s DE2 Board This tutorial is available on the DE2 System CD ROM and from the Altera DE2 web pages 2 Connect the 9V adapter to the DE2 board 3 Connect a VGA monitor to the VGA port on the DE2 board 4 Connect your headset to the Line out audio port on the DE2 board 9 NOTE DVA DE2 User Manual 5 Turn the RUN PROG switch on the left edge of the DE2 board to RUN position the PROG position is used only for the AS Mode programming 6 Turn the power on by pressing the ON OFF switch on the DE2 board At this point you should observe the following e All user LEDs are flashing e All 7 segment displays are cycling through the numbers 0 to F e The LCD display shows Welcome to the Altera DE2 Board e The VGA monitor displays the image shown in Figure 2 3 e Set the toggle switch SW17 to the DOWN position you should hear a 1 kHz sound e Set the toggle switch SW17 to the UP position and connect the output of an audio player to the Line in connector on the DE2 board on your headset you should hear the music played from the audio player MP3 PC iPod or the like e You can also connect a microphone to the Microphone in connector on the DE2 board your voice will be mixed with the music played from the audio player DE2 Board Figure 2 3 The defau
57. words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties representations or guarantees of any kind whether express implied or statutory including without limitation warranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 66
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