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J-Link / J-Trace User Guide (UM08001)

1. Selects whether an ETM is present on the target or not Setting this variable in another function EMU ETM IsPresent as InitEmu does not have any effect R W Example EMU ETM IsPresent 0 Use ETM as trace source Setting this variable in another function as InitEmu does not have any effect W Example EMU ETM USeETM 1 EMU ETM Usel a m Disable use of hardware units for JTAG transmis sions since this can cause problems on some hardware designs W Example EMU JTAG DisableHWTransmissions 1 JTAG _ DisableHWTransmissions Set base address of core debug component for CoreSight compliant devices Setting this vari able disables the J Link auto detection of the core debug component base address Used on CORESIGHT CoreBaseAddr devices where auto detection of the core debug component base address is not possible due to incorrect CoreSight information Example CORESIGHT CoreBaseAddr 0x80030000 Pre select an AP as an AHB AP that J Link uses for debug communication Cortex M Setting this variable is necessary for example when debugging multi core devices where multiple AHB APs are present one for each device This function can only be used if a AP layout has been configured via CORESIGHT AddAP Example W CORESIGHT AddAP 0 CORESIGHT_AHB_AP CORESIGHT AddAP 1 CORESIGHT AHB AP CORESIG
2. Trace signal ETMv1 ETMv2 ETMv3 Trace signal 1 PIPESTAT 0 PIPESTAT 0 TRACEDATA O Trace signal 2 PIPESTAT 1 PIPESTAT 1 TRACECTL Trace signal 3 PIPESTAT 2 PIPESTAT 2 Logic 1 Trace signal 4 TRACESYNC PIPESTAT 3 Logic O Trace signal 5 TRACEPKT 0 TRACEPKT 0 Logic 0 Trace signal 6 TRACEPKT 1 TRACEPKT 1 TRACEDATA 1 Trace signal 7 TRACEPKT 2 TRACEPKT 2 TRACEDATA 2 Trace signal 8 TRACEPKT 3 TRACEPKT 3 TRACEDATA 3 Trace signal 9 TRACEPKT 4 TRACEPKT 4 TRACEDATA 4 Trace signal 10 TRACEPKT 5 TRACEPKT 5 TRACEDATA 5 Trace signal 11 TRACEPKT 6 TRACEPKT 6 TRACEDATA 6 Trace signal 12 TRACEPKT 7 TRACEPKT 7 TRACEDATA 7 Trace signal 13 TRACEPKT 8 TRACEPKT 8 TRACEDATA 8 Trace signal 14 TRACEPKT 9 TRACEPKT 9 TRACEDATA 9 Trace signal 15 TRACEPKT 10 TRACEPKT 10 TRACEDATA 10 Trace signal 16 TRACEPKT 11 TRACEPKT 11 TRACEDATA 11 Trace signal 17 TRACEPKT 12 TRACEPKT 12 TRACEDATA 12 Trace signal 18 TRACEPKT 13 TRACEPKT 13 TRACEDATA 13 Trace signal 19 TRACEPKT 14 TRACEPKT 14 TRACEDATA 14 Trace signal 20 TRACEPKT 15 TRACEPKT 15 TRACEDATA 15 Table 10 7 Assignment of trace information pins between ETM architecture versions 10 2 4 Trace signals Data transfer is synchronized by TRACECLK 10 2 4 1 Signal levels The maximum capacitance presented by J Trace at the trace port connector including the connector and interfacing logic is less than 6pF The trace port lines have a matched imp
3. CHAPTER 5 Working with J Link and J Trace Device 0 Device 1 Device 2 ane Chip IR len Chip IR len Chip IR len Position 18180 ARM 4 Xilinx 8 ARM 4 0 0 ARM 4 Xilinx 8 ARM 4 2 12 Xilinx 8 ARM 4 Xilinx 8 1 8 Table 5 5 Example scan chain configurations The target device is marked in blue 5 3 4 JTAG Speed There are basically three types of speed settings e Fixed JTAG speed e Automatic JTAG speed e Adaptive clocking These are explained below Fixed JTAG speed The target is clocked at a fixed clock speed The maximum JTAG speed the target can handle depends on the target itself In general CPU cores without JTAG synchroniza tion logic such as ARM7 TDMI can handle JTAG speeds up to the CPU speed ARM cores with JTAG synchronization logic such as ARM7 TDMI S ARM946E S ARM966EJ S can handle JTAG speeds up to 1 6 of the CPU speed JTAG speeds of more than 10 MHz are not recommended 5 3 4 2 Automatic JTAG speed Selects the maximum JTAG speed handled by the TAP controller Note On ARM cores without synchronization logic this may not work reliably because the CPU core may be clocked slower than the maximum JTAG speed 5 3 4 3 Adaptive clocking J Link J Trace 0 08001 If the target provides the RTCK signal select the adaptive clocking function to syn chronize the clock to the processor clock outside the core This ensures there are no synchronization problems over the JT
4. 5 14 1 2 Via J Link Commander Simply start J Link Commander which is part of the J Link software and documenta tion package and enter the vcom enable disable command as in the screenshot below After changing the configuration a power on cycle of the debug probe is nec essary in order to use the new configuration For feature information about how to use the J Link Commander please refer to J Link Commander Command line tool on page 63 3 CAWorkULinkARM Output ReleaseULink exe SEGGER J Link Commander U4 81f for help Compiled Mar 6 2614 11 02 49 version U4 81f compiled Mar 6 2014 11 02 41 J Link 09 compiled Feb 12 2014 21 47 56 9 00 FlashBP FlashDL JFlash J e The new configuration applies after power cycling the debug probe J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 186 CHAPTER 5 Working with J Link and J Trace J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 187 Chapter 6 Flash download This chapter describes how the flash download feature of the DLL can be used in dif ferent debugger environments J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 188 6 Flash download 6 1 Introduction The J Link DLL comes with a lot of flash loaders that allow direct programming of internal flash memory for popular microcontrollers Moreover the J
5. 2 for 1 e 6 x Table 1 11 Built in intelligence of older J Link models J Link J Trace UM08001 45 2004 2014 SEGGER Microcontroller GmbH amp Co KG 46 CHAPTER 1 Introduction 1 7 Supported IDEs J Link J Trace can be used with different IDEs Some IDEs support J Link directly for other ones additional software such as J Link RDI is necessary in order to use J Link The following tables list which features of J Link J Trace can be used with the different IDEs ARM7 9 Debug Flash Flash Trace IDE 4 3 support download breakpoints support IAR EWARM yes yes yes yes Keil MDK yes yes yes no Rowley yes yes no no CodeSourcery yes no no no Yargato GDB yes yes yes no RDI compliant toolchains such as yes yes yes no RVDS ADS ARM Cortex M3 Debug Flash Flash Trace SWO IDE 4 support download breakpoints support support IAR EWARM yes yes yes yes yes Keil MDK yes yes yes yes yes Rowley yes yes no no no CodeSourcery yes no no no no Yargato GDB yes yes yes no no ARM11 ARM11 has currently been tested with IAR EWARM only Debug Flash Flash Trace IDE 4 3 support download breakpoints support IAR EWARM yes 2 2 no Rowley yes 2 lt 2 2 1 Requires J Link RDI license for download of
6. 315 N eels 274 315 Open collector 2 2 315 P Processor Core 316 Program Status Register PSR 316 R RDI Support pev tetuer 112 REMAPPING iier ex eee ts 316 Remote Debug Interface RDI 316 RESET sse rre Ee vera el cael es 315 RICK ecu eo ie re aieo RE EET v EE RENE EE 316 RTOS steer UNDO Ltd ian 316 2004 2014 SEGGER Microcontroller GmbH amp Co KG 322 5 Scan Chain x neam nns 316 Semihosting 316 Server command 74 vuv 74 DisableChecks 74 EnableChecks 2 2 4 75 flash breakpoints 75 QO re ties LE 75 url v eri cree esa 76 jtagconf ttc divin xr Renee t en xa 76 memU6 77 MEMU E 76 RHOD 77 E 78 SETBP io co aries ee ees 78 80 Sleep zer Vr xe 81 SDGed 81 21512 PEE 81 scere er 83 Aves unde 83 SetDbgPowerDownOncClose 180 SetSysPowerDownOnldle 180 85
7. The following 3rd party applications using JLink amp RM dll have been found CIAR Embedded Workbench for ARM 6 40 DLL 4 68 in NTooNCMARNARM VB40BSARM bin C IAR Embedded Workbench for ARM DLL V4 72 in C Tool CMAR ARM_V6505 4RM bin Embedded Workbench for ARM 6 40 DLL V4 63a in C Tool C IAR ARM_V6405 4RM bin CIAR Embedded Workbench for ARM DLL V4 72a in CNTooNCVARNARM V6BDTNARMNbin Embedded Workbench for ARM 5 50 DLL v4 68 in CATooNCXARNARM V5S0GNARMNbin CIAR Embedded Workbench for ARM 6 10 DLL V4 68 in C Tool C ARARM_V6104 4RM bin CIAR Embedded Workbench for ARM 6 21 DLL V4 68 in VB21CXARMbin Embedded Workbench for ARM 6 30 DLL V4 68 in CATooNCNARNARM VB30 amp ARMbin Keil MDK V4 72a DLL V4 68a in C KeilV472a 4RM Segger Select All SelectNone Select the ones you would like to replace by this version The previous version will be renamed and kept in the same folder allowing manual undo In case of doubt do not replace existing DLL s You can always perform this operation at a later time via start menu 7 The Installation Complete dialog box appears after the copy process Close the installation wizard with the Finish gt button i Installation Complete The J Link software and documentation pack is successfully installed on your PC 8 Connect your J Link via USB with your PC The J Link will be identifie
8. 0xD3 Supervisor mode ARM IRQ FIQ disabled All SPSR registers 0x10 All other registers which are unpredictable after reset are set to 0 The hardware RESET pin is not affected 5 8 1 8 7 Reserved Reserved reset type 5 8 1 9 Type 8 Software for ATMEL AT91SAM7 MCUs The reset pin of the device is disabled by default This means that the reset strate gies which rely on the reset pin low pulse on reset do not work by default For this reason a special reset strategy has been made available It is recommended to use this reset strategy This special reset strategy resets the peripherals by writing to the RSTC_CR register Resetting the peripherals puts all peripherals in the defined reset state This includes memory mapping register which means that after reset flash is mapped to address 0 It is also possible to achieve the same effect by writing 0x4 to the RSTC CR register located at address OxfffffdOO 5 8 1 10 Type 9 Hardware for NXP LPC MCUs After reset a bootloader is mapped at address 0 on ARM 7 LPC devices This reset strategy performs a reset via reset strategy Type 1 in order to reset the CPU It also ensures that flash is mapped to address 0 by writing the MEMMAP register of the LPC This reset strategy is the recommended one for all ARM 7 LPC devices J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 161 5 8 2 Strategies for Cortex M devices J Link sup
9. 1 oorr eis 307 313 Supported flash devices 190 191 197 204 316 T Nbre 153 Controller 2 20 316 Target 316 ua qu cR 274 316 TDI iesus A er dues nak ein ERR hice 274 316 TDQu 274 317 Test Access Port 317 Transistor transistor logic TTL 317 Watchpoint 2 4 317 WONGS TE 317 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG
10. 7 4 2 Compatibility with various debuggers Flash breakpoints can be used in all debugger which use the proper J Link API to set breakpoints Compatible debuggers debug interfaces are IAR Embedded Workbench Keil MDK GDB based debuggers Freescale Codewarrior Mentor Graphics Sourcery CodeBench RDI compliant debuggers Incompatible debuggers debug interfaces e Rowley Crossworks J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 206 CHAPTER 7 Flash breakpoints 7 5 FAQ Q Why can flash breakpoints not be used with Rowley Crossworks A Because Rowley Crossworks does not use the proper J Link API to set breakpoints Instead of using the breakpoint API Crossworks programs the debug hardware directly leaving J Link no choice to use its flash breakpoints J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 207 Chapter 8 RDI RDI Remote Debug Interface is a standard defined by ARM trying to standardize a debugger debug probe interface It is defined for cores only that have the same CPU register set as ARM7 CPUs This chapter describes how to use the RDI DLL which comes with the J Link software and documentation package The J Link RDI DLL allows the user to use J Link with any RDI compliant debugger and IDE J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 208 8 RDI 8 1 Introduction Remote Debu
11. Rit timer interrupt Once a Shot on each led i 0 i lt NB LEB i 91F Clear utput AT91C BASE PIOA led nask i Stop Bond ti 91F_PI0_Set0utput 91 led_mask i tlhe Once Shot on each led for i NBLEB 1 i 0 i AT91F_PIO ClearOutput AT91C BASE PIOA led mask i wait AT91F_PIO_SetOutput AT91C_BASE_PIOA led 1 wait 2 Choose Project Options and select the Debugger category Change the J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 211 Driver option to RDI Options for node Basic Custom Build Build Actions Third Party Driver 3 Go to the RDI page of the Debugger options select the manufacturer driver JLinkRDI d11 and click OK Options for node Basic LI Third Party Driver 4 Now an extra menu RDI has been added to the menu bar Choose RDI Configure to configure the J Link For more information about the generic setup of J Link RDI please refer to Configuration on page 226 2 Embedded Workbench IDE Iul J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 212 8 RDI 8 3 1 3 Debugging on Cortex M3 devices The RDI protocol has only been specified by ARM for ARM 7 9 cores For Cortex M there is no official extension of the RDI
12. than 32KBytes 2 Coming soon 3 Requires emulator with trace support 4 Debug support includes the following Download to RAM memory read write CPU register read write Run control go step halt software breakpoints in RAM and hardware breakpoints in flash memory J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 47 Chapter 2 Licensing This chapter describes the different license types of J Link related software and the legal use of the J Link software with original SEGGER and OEM products J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 48 CHAPTER 2 Licensing 2 1 Components requiring a license The following programs features require a full featured J Link PLUS ULTRA PRO 1 or an additional license for the J Link base model e J Flash e J Link RDI e Flash breakpoints FlashBP J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 49 2 2 License types For each of the software components which require an additional license there are different types of licenses which are explained in the following Built in License This type of license is easiest to use The customer does not need to deal with a license key The software automatically finds out that the connected J Link contains the built in license s The license is burned into the J Link debug probe and can be used on any computer
13. lt 0 Error Note ReturnValue is hex encoded Return value 0 is 00000000 return value 1 is FFFFFFFF 3 3 4 4 qSeggerSTRACE read Syntax qSeggerSTRACE read lt NumItems gt Parameter NumItems Maximum number of trace data addresses to be read Hexadecimal Description Read the last recently called instruction addresses The addresses are returned LIFO meaning the last recent address is returned first Note For more information please refer to 08002 J Link SDK user guide chapter STRACE Response lt ReturnValue gt lt Item0 gt lt Iteml gt ReturnValue is a 4 Byte signed integer gt 0 Number of items read lt 0 Error ItemN is a 4 Byte unsigned integer 0x00000000 OxFFFFFFFF Address of the executed instruction Note ReturnValue and ItemN are hex encoded e g 3 Items read 0x08000010 0x08000014 0x08000018 Response will be 00000003080000100800001408000018 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 87 3 3 5 Command line options There are several command line options available for the GDB Server which allow configuration of the GDB Server before any connection to a J Link is attempted or any connection from a GDB client is accepted Note Using GDB Server CL device interface endian and speed are mandatory options to correctly connect to the target and should be given before connection via GDB Using GDB Server GUI the manda
14. 15 060914 OO Subchapter 1 5 1 Added target supply voltage and target supply current to specifications Subchapter 5 2 1 Pictures of ways to connect J Trace 14 060818 TQ Subchapter 4 7 Using DCC for memory reads added 13 060711 OO Subchapter 5 2 2 Corrected JTAG Trace connec tor pinout table 12 060628 OO Subchapter 4 1 Added ARM966E S to List of sup ported ARM cores J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG Revision Date By Explanation Subchapter 5 5 2 2 changed i 08050752 5 5 2 3 Sdded ARM9 download speed updated Subchapter 8 2 1 Screenshot Start sequence updated 980528 Sk 8 2 2 ID sequence removed Chapter Support and FAQ merged Various improvements Chapter Literature and references added Chapter Hardware Added common information trace signals 4 Ob 02a 199 Added timing diagram for trace i Chapter Designing the target board for trace added 8 060117 00 Chapter Related Software Added JLinkARM dll Screenshots updated 7 051208 OO Chapter Working with J Link Sketch added Chapter Working with J Link Connecting multiple J Links to your PC added 6 051118 Chapter Working with J Link Multi core debug ging added Chapter Background information J Link firm ware added 5 051103 TQ Chapter
15. the debugger can be started Debug Start Stop debug session Blinky nVision3 Disassembly R10 BH R12 7 13 5 R14 LR R15 PC J Link J Trace 0 08001 358 341 342 353 355 355 356 347 348 E59FF 818 E59FF 818 E59FF 818 ESOFF 818 E59FF 818 B9286E58 0x00000018 E51FF128 Reset fiddr Undef fddr SWI_Addr Pabt Rddr DAbt_Addr IRQ_Addr FIQ_Addr Reset fiddr PC PC 10x8018 PC Undef PC PC 110x0018 PC SWI fddr PC PC 0 0618 PC PAbt_Addr 0 0018 DAbt_Addr PC PC 0 0618 Reserved Vector IRQ_Addr RO R4 R6 R9 R11 R13 R14 PC PC 6x6126 Vector from VicUectAddr PC PC 6x0126 FIQ Addr Reset_Handler Undef_Handler SWI_Handler PAbt_Handler DAbt_Handler 6 Reserved Address IRQ_Handler FIQ Handler 00000000 00000000 00000000 00000000 600000DF 00000000 00000000 00000000 600000DF 00000000 00000000 00000000 00000000 00000000 600000DF 00000000 2004 2014 SEGGER Microcontroller GmbH amp Co KG 226 CHAPTER 8 RDI 8 4 Configuration This section describes the generic setup of J Link RDI same for all debuggers using the J Link RDI configuration dialog 8 4 1 Configuration file JLinkRDl ini settings are stored in the file JLinkRDI ini This file is located in the same direc tory as JLinkRDI dll 8 4 2 Using different configurations It can be
16. For these J Links we recommend to re configure them to use the new enumeration method report real serial number Re configuration can be done by using the J Link Configurator which is part of the J Link software and documentation package Re configuring J Link to use the new method does not have any bad side effects on the current debug environment Usually the user does not see any difference as long as only one emulator is connected J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 152 CHAPTER 5 Working with J Link and J Trace In order to re configure a J Link to use the new USB identification method use the J Link Configurator which comes with the J Link software and documentation package For more information about the J Link Configurator and how to use it please refer to J Link Configurator on page 127 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 153 5 7 J Link control panel Since software version V3 86 J Link the J Link control panel window allows the user to monitor the J Link status and the target status information in real time It also allows the user to configure the use of some J Link features such as flash download flash breakpoints and instruction set simulation The J Link control panel window can be accessed via the J Link tray icon in the tray icon list This icon is available when the debug session is started SRA 13 35 To open
17. HIGH level output voltage Voy with a load of 10 Vou gt 80 of Vig JTAG SWD Interface Timing SWO sampling frequency Max 7 5 MHz Data input rise time Trai lt 20ns Data input fall time Trai lt 20ns Data output rise time Trdo Trdo lt 10ns Data output fall time lt 10ns Clock rise time Tre lt 3ns Clock fall time Tg lt 3ns Table 1 1 J Link specifications 1 3 2 3 Hardware versions Versions 1 4 Obsolete Obsolete Version 5 0 Obsolete Identical to version 4 0 with the following exception e Uses a 32 bit RISC CPU e Maximum download speed using DCC is over 700 Kbytes second e JTAG speed Maximum JTAG frequency is 12 MHz possible JTAG speeds are 48 MHz n where n is 4 5 resulting in speeds of 12 000 MHz n 4 9 600 MHz n 5 8 000 MHz n 6 6 857 MHz n 7 6 000 MHz n 8 5 333 MHz n 9 4 800 MHz n 10 e Supports adaptive clocking Version 5 2 Obsolete Identical to version 5 0 with the following exception e Target interface RESET is open drain Version 5 3 Obsolete Identical to version 5 2 with the following exception e target supply current limited 5V target supply pin 19 of Kick Start versions of J Link is current monitored and limited J Link automatically switches off 5V supply in case of over current to protect both J Lin
18. 124 4 3 2 Configuring J Link using the mme 124 4 4 ori M U 126 4 5 J Link Configu katoE ie oett eer tee tere du cua OR ERE ETE IP Ru Y Ud 127 4 5 1 Configure J Links using the J Link 11 127 4 6 J Link USB nenne nnn nnn 129 4 6 1 Connecting to different J Links connected to the same host PC via USB 129 4 7 Using the J Einlke DEE 131 4 7 1 What is the JLink DLE uiii rea 131 4 7 2 Updating the DLL in third party 1 6 3 131 4 7 3 Determining the version of JLink DLL cece cece cece e eee 132 4 7 4 Determining which DLL is used by 132 4 8 Getting started with J Link and ARM DS 5 0 133 4 8 1 Replacing the RDDI DLL 4 1 1 133 4 8 2 Using J Link 05 5 Development 5 50 eats 133 5 Working with J Link and J TT866 si roo o P OO net t ts E 135 5 1 Connecting the target system nee 136 5 1 1 Power on SEQ
19. 2 01 44 nen 258 9 11 2 Reset Cortex M3 based devices 66 259 9 11 3 LPC288x flash programming memes 259 9 11 4 259 9 12 eld cT 260 9 13 hinter 261 9 14 mM 262 9 14 1 ro Re E c eg a a dane C oe o ol E c RC A 262 9 15 Silicon ba oce 263 9 15 1 EFM32 series devices lies n e m O E V ea Dada 263 9 16 ST MicroelectrOhlics idee sa eee Ouest eu ha ge ode MARE EE e KR UR Da ERO 264 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 9 16 1 STRO IX ees 265 9 16 2 STM32FIOXXX qe EE 265 9 16 3 STM32F2900CTasvet sis eek ees ava due re Oud Too ra int id eee Eat eleva iu is vau ads 267 9 16 4 STM32F4XxX ecc aen Ra Rer E E ie a EDO ac GR ER S E RA S 268 9 17 Texas Instruments iere RA FER pete Red 269 9 17 1 AM33 5 Xiru 269 9 17 2 AM35XX Ree IR ETE CEN iaa e 270 9 17 3 44 ey 270 9 17 4 EE 270 9 17 5 pni EE 270 9 17 6 m 271 9 17 7 OMAP3550 ose eem Rx xe ches ee d
20. 8 RDI 5 Confirm the choices by clicking the Apply button afterwards the Connect button Connection E ditor config dll C Program Files SEGGER JLinkARM_V350g JLinkRDI dil modeedosrioad reer config dl C Program Fies GEGGERIILRRARM VaSOgLInkRDI dl OK cancel 6 The J Link RDI Configuration dialog will be opened For more information about the generic setup of J Link RDI please refer to Configuration on page 226 7 Click the OK button to connect to the target Build the project and start the debugger Note that at least one action for example step or run has to be per formed in order to initiate the download of the application E C Work Basic ghs MULTI Debugger void wait void Begin unsigned int waiting time 0 20027 wait b500 PUSH LR 0x20027e wait 0x2 b084 SUB SP SP 16 change speed 0 200280 wait 0x4 fT7f fffd4 BL O xffffffaBG change speed 0x20022c for waiting time 0 waiting time lt LedSpeed waiting timect 0 200284 wvait 0x8 2000 Nov RO waiting time 0 0 200286 wait Oxa e000 OxO wait Oxe 0 20028 Eum 0x200288 wait Oxe 3001 ADD RO waiting time 1 e 0 20028 wait Oxe 4922 R1 PC 136 sLedSpeed 0 200314 0 20028 wait 0x10 680b R3 R1 0 e 0 20028 wait Ox12 4298 RO waiting time R3 e 0 200290 wait 0x14 d3fa xfffffff4 waitcOxc 0 200288 End 0 200292 wait Ox16 b004 SP 16 0 200294
21. ARM_0 ARM A RR while 1 LED_ToggleLED1 0000C580 0000 588 05 Delay 200 00000150 00001F60 0000B63C 00001 50 00000000 00000000 00000000 00000000 00002890 00000000 00000515 0000 5 0 00001 85 00000514 CPSR 000000 3 05_ Initially disable interrupts 05 InitKern initialize 08 08 InitHW initialize Hardware for 0 LED Init initialize LED ports You need to create at least one task here 05 CREATETASK amp TCBO HP Task Task0 100 Stack0 05 CREATETASK amp TCBl LP Task Taskl 50 Stackl z ace eet ee main_led c 00000000 0xESSFF018 0 59 018 0 59 018 0 59 018 Instr MAIN LED 35 0 00000010 0 59 018 OxE1A00000 0 59 014 0 59 014 00000020 0 00002584 0 0000003 0 00000040 0 00000044 00000030 0 00000048 0 00002300 0 0000004 OXEAFFFFFE 00000040 OxEAFFFFFE OxEAFFFFFE OxEAFFFFFE 00000050 0 000000 0 0007 0 28 028 0 89 0 00 gt bi MAIN_LED 35 0 gt go Stopped at 0 00000514 due to SW Instruction Breakpoint Stopped at 0 00000514 MAIN _LED main Line 35 8 3 4 GHS MULTI 8 3 4 4 Software version J Link RDI has been tested with GHS MULTI version 4 07 There should be no prob lems with other versions of GHS MULTI All screenshots are taken from GHS MULTI version 4 07 8 3 4 2 C
22. RDI Testing speed 3FOFOFOF 3FOFOFOF 3FOFOFOF 3FOFOFOF 3FOFOFOFAuto JTAG gt 2EF gt oc 00 OkHz gt 48 gt 00 Writing 0x4 00 Writing 0x4 00 Writing 0x4 Data EA Writing 0x4 EA 00 Writing 0x4 27 00 00 FF Writing 0x4 00 00 00 00 00 00 00 00 00 EA FE FF FF EA 01 00 00 00 02 00 00 00 30 B5 15 48 01 68 82 68 00 FO 00 30 00 14 12 47 B5 47 B5 00 00 4 00 00 00 00 13 27 24 00 00 48 24 Writing 0x54 bytes 8 0 00000178 gt 3E68 gt 4c 00 00 03 B4 Warning Chip has already been halted 34 08 00 00 81 4D 49 00 00 BO bytes bytes bytes 00 by EA Ces bytes bytes Writing 0 4 bytes 2004 2014 SEGGER Microcontroller GmbH amp Co KG 235 85 Semihosting Semihosting is a mechanism for ARM targets to communicate input output requests from application code to a host computer running a debugger It effectively allows the target to do disk operations and console I O and is used pri marily for flash loaders with ARM debuggers such as AXD 8 5 1 Overview Semihosting Semihosting is a mechanism for ARM targets to communicate input output requests from application code to a host computer running a debugger This mechanism is used to allow functions in the C library such as printf scanf to use the screen and key
23. ST LINK Third Party Driver XDS100 Setup For debuggers software which does not provide such a functionality the J Link DLL automatically detects that mutliple J Links are connected to the PC and shows a selection dialog which allows the user to select the appropriate J Link he wants to connect to SEGGER J Link V4 15y beta Emulator selection So even in IDEs which do not have an selection option for the J Link it is possible to connect to different J Links J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 131 4 7 Using the J Link DLL 4 7 1 What is the JLink DLL J LinkARM d1l is a standard Windows DLL typically used from C C but also Visual Basic or Delphi projects It makes the entire functionality of the J Link J Trace available through the exported functions The functionality includes things such as halting stepping the ARM core reading writing CPU and ICE registers and reading writing memory Therefore it can be used in any kind of application accessing a CPU core 4 7 2 Updating the DLL in third party programs The JLink DLL can be used by any debugger that is designed to work with it Some debuggers are usually shipped with the J Link DLL already installed Anyhow it may make sense to replace the included DLL with the latest one available to take advan tage of improvements in the newer version 4 7 2 1 Upd
24. cess and the target and allows some in progress configurations SEGGER J Link GDB Server V4 74 File Localhost only GDB waiting for connection Initial SWD speed 4000 kHz Stay on top Show log window J Link Connected Current SWD speed 4000 kHz Generate logfile z Cache reads CPU STM32F41 3 30 a Little endian Verify download Init regs on start 0 Bytes downloaded 1 JTAG device It shows following information IP address of host running debugger Connection status of J Link Information about the target core Measured target voltage Bytes that have been downloaded Status of target Log output of the GDB Server optional if Show log window is checked Initial and current target interface speed Target endianess These configurations can be made from inside GDB Server Localhost only If checked only connections from 127 0 0 1 are accepted Stay on top Show log window Generate logfile If checked a log file with the GDB lt gt GDB Server lt gt J Link communication will be created e Verify download If checked the memory on the target will be verified after download e Init regs on start If checked the register values of the target will be set to a reasonable value before on start of GDB Server 3 3 2 4 Running GDB from different programs We assume that you already have a solid knowledge of the software
25. ware leads to improved stability and higher performance 1 6 2 Intelligence on the PC side DLL This is the basic implementation level for support of a CPU core This implementation is not J Link model dependend since no intelligence for the CPU core is necessary in the J Link firmware This means all target sequences JTAG SWD are generated on the PC side and the J Link simply sends out these sequences and sends the result back to the DLL Using this way of implementation also allows old J Links to be used with new CPU cores as long as a DLL Version is used which has intelligence for the CPU But there is one big disadvantage of implementing the CPU core support on the DLL side For every sequence which shall be send to the target a USB or Ethernet trans action is triggered The long latency especially on a USB connection significantly affects the performance of J Link This is true especially when performing actions where J Link has to wait for the CPU frequently An example is a memory read write operation which needs to be followed by status read operations or repeated until the memory operation is completed Performing this kind of task with only PC side intel ligence will have to either make some assumption like Operation is completed after a given number of cycles or will have to make a lot of USB Ethernet transactions The first option fast mode will not work under some circumstances such as low CPU speeds the second slow m
26. 002838 002842 002877 002881 002916 002920 002955 002959 002994 002998 903033 003037 003072 003076 003111 003115 003150 003154 003189 003193 003201 003203 003224 003226 003241 003243 003260 003262 003277 003279 003303 003305 003327 003329 003349 003351 003371 003372 003375 003393 Clk Init 116 Clk_Init 122 RCC SYscLKconfi g u32 Ck Init 128 main 16 main 26 003096 003414 08008 4876 main 34 J Link J Trace 0 08001 FLASH Ha fcycleaccesscmd u32 FLASH PrefetchBufferCmd u32 NVIC setVectorTable u32 u32 2004 2014 SEGGER Microcontroller GmbH amp Co KG 297 11 3 Embedded Trace Buffer ETB The ETB is a small circular on chip memory area where trace information is stored during capture It contains the data which is normally exported immediately after it has been captured from the ETM The buffer can be read out through the JTAG port of the device once capture has been completed No additional special trace port is required so that the ETB can be read via J Link The trace functionality via J Link is limited by the size of the ETB While capturing runs the trace information in the buffer will be overwritten every time the buffer size has been reached 2 J Link ARM SEGGER J Link Commander VU3 72c for help Compiled Jul 4 2007 26 17 14 DLL rsi 72c compiled Jul 4 2007 20 17 09 Firmware J Link compiled Jun 14 2007 14 36 33
27. 12 MHz 288 MHz 57 6 MHz 48 MHz 14 4 MHz The Blinky program is available in different targets Simulator configured for software Simulator MCB2300 Flash runs from Internal Flash located on chip used for production or target debugging El E 1 2 E Bic E Lco 4c B B Load C Keil3030 ARM RV30 Boards Keil MCB2300 Blinky Flash Blinky AXF J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 224 8 RDI Select Project Options for Target lt NameOfTarget gt to open the project options dialog and select the Debug tab Options for Target LPC2378 Flash RDI Interface Driver ULINK ARM D ULINK Cortes EIL Loeb Choose RDI Interface Driver from the list as shown above click the Settings button Select the location of JLinkRDI d11 in Browse for RDI Driver DLL field and click the Configure RDI Driver button RDI Interface Driver Setup x C Program Files SEGGER LinkARM_V359a JLinkRDI_dll FERE lemos The J Link RDI Configuration dialog will be opened For more information about the generic setup of J Link RDI please refer to Configuration on page 226 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 225 After finishing configuration the project be build Project Build Target
28. 2 4 7 Flasher ARM Flasher ARM is a programming tool for microcontrollers with on chip or external Flash memory and ARM core Flasher ARM is designed for programming flash targets with the J Flash soft ware or stand alone In addition to that Flasher ARM has all of the J Link functionality Flasher ARM connects via USB or via RS232 interface to a PC running Microsoft Windows 2000 Win dows XP Windows 2003 or Windows Vista Flasher ARM has a built in 20 pin JTAG connector which is compatible with the Licensing standard 20 pin connector defined by ARM Flasher Licenses Comes with built in licenses for flash download and J Flash 2 4 8 Flasher RX J Link J Trace 0 08001 Flasher RX is a programming tool for Renesas RX600 series microcontrollers with on chip or external flash memory and Renesas RX core Flasher RX is designed for programming flash targets with the J Flash software or stand alone In addition to that Flasher RX has all of the J Link RX functionality Flasher RX connects via Ethernet USB or via RS232 interface to a PC run ning Microsoft Windows 2000 Windows XP Windows 2003 Windows Vista or Windows 7 Flasher RX itself has a built in 20 pin JTAG connector but is shipped with an 14 pin adapter for Renesas RX devices Licenses Comes with built in licenses for flash download and J Flash 2004 2014 SEGGER Microcontroller GmbH amp Co KG 55 2 4 9 Flasher Flasher ARM is a programmi
29. 2 54mm male that mates with IDC sockets mounted on a ribbon cable later J Link products like the J link ULTRA these pins are reserved for firmware extension pur poses They can be left open or connected to GND in normal debug environment They are not essential On VTref 1 2 NC nTRST 3 GND TDI 5 e 6 GND TMS 7 es GND TCK 9 10 GND RTCK 11 e 12 GND TDO 13 14 GND RESET 15 16 GND DBGRQ 17 e 18 GND 5V Supply 19 e e 20 GND for JTAG SWD in general The following table lists the J Link J Trace JTAG pinout PIN SIGNAL TYPE Description VTref Input This is the target reference voltage It is used to check if the target has power to create the logic level reference for the input comparators and to control the output logic levels to the target It is normally fed from Vdd of the target board and must not have a series resistor Not con nected NC This pin is not connected in J Link nTRST Output JTAG Reset Output from J Link to the Reset signal of the target JTAG port Typically connected to nTRST of the target CPU This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection TDI Output JTAG data input of target CPU It is recommended that this pin is pulled to a defined state on the target board Typically connected to TDI of the target CPU TMS
30. Cache Memory IV Download to Flash m Interface TCP IP Misc USB C TCP P IP Address Port Auto 0 Autodetect JLink Info Scan 27 1 0 1 EIE 9 Ping State ready J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 194 6 4 3 6 Flash download Mentor Sourcery CodeBench To use the J Link flash download feature in Mentor Sourcery CodeBench the follow ing steps need to be performed Current versions of Sourcery CodeBench do not pass the device name selected in CodeBench to the J Link DLL Therefore a device override via J Link settings file is needed Copy the J Link settings file template from SJLINK_INST_DIRS Samples JLink SettingsFiles Sample jlinksettings to the directory where the CodeBench project is located Open the Sample jlinksettings in a text editor and scroll to the FLASH sec tion Change the line Device UNSPECIFIED to the device name that shall be selected keep the quotation marks A list of valid device names found here http www segger com jlink supported devices html List of known devices Change the line Override 0 to Override 1 Select the settings file to be used in Sourcery CodeBench Name 5 32 4071 Test Debug E Main 09 Arguments PG Environment ES Debugger E Source Common Debug interface nk x WP Board stmazr4dis
31. Description Writes JTAG data Before calling this function please make sure that the JTAG chain has been config ured correctly by setting the appropriate global DLL variables For more information about the known global DLL variables please refer to Global DLL variables on page 169 api int JTAG StoreIR unsigned int Cmd Prototype api int JTAG WriteDR unsigned __int64 tdi int NumBits 5 10 2 10JTAG StoreDR Description Stores JTAG data in the DLL JTAG buffer Before calling this function please make sure that the JTAG chain has been config ured correctly by setting the appropriate global DLL variables For more information about the known global DLL variables please refer to Global DLL variables on page 169 Prototype api int JTAG StoreDR unsigned __int64 tdi int NumBits 5 10 2 11 Write Description Writes a JTAG sequence max 64 bits per pin Prototype api int JTAG Write unsigned _ int64 tms unsigned _ int64 tdi int NumBits J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 168 CHAPTER 5 Working with J Link and J Trace 5 10 2 12JTAG Store Description Stores a JTAG seuqnece max 64 bits per pin in the DLL JTAG buffer Prototype api int JTAG Store unsigned _ int64 tms unsigned 1664 tdi int NumBits 5 10 2 13JTAG GetU32 Description Gets 32 bits JTAG data starting at given bit position Prototype api int JT
32. ETB ETB is a small circular on chip memory area where trace information is stored during capture EmbeddedICE The additional hardware provided by debuggable ARM processors to aid debugging Halfword A 16 bit unit of information Contents are taken as being an unsigned integer unless otherwise stated Host A computer which provides data and other services to another computer Especially a computer providing debugging services to a target being debugged ICache Instruction cache ICE Extension Unit A hardware extension to the EmbeddedICE logic that provides more breakpoint units J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 315 ID Identifier IEEE 1149 1 The IEEE Standard which defines TAP Commonly but incorrectly referred to as JTAG Image An executable file that has been loaded onto a processor for execution In Circuit Emulator ICE A device enabling access to and modification of the signals of a circuit while that cir cuit is operating Instruction Register When referring to a TAP controller a register that controls the operation of the TAP IR See Instruction Register Joint Test Action Group JTAG The name of the standards group which created the IEEE 1149 1 specification Little endian Memory organization where the least significant byte of a word is at a lower address than the most significant byte See also Big endian Memory coherency A memory is
33. If you experience problems with a particular core do not hesitate to contact Segger ARM7TDMI Rev 1 ARM7TDMI Rev 3 ARM7TDMI S Rev 4 ARM720T ARM920T ARM922T ARM926EJ S ARM946E S ARM966E S ARM1136JF S ARM1136J S ARM1156T2 S ARM1156T2F S ARM1176JZ S ARM1176JZF ARM1176JZF S Cortex A5 Cortex A8 Cortex A9 Cortex MO Cortex M1 Cortex M3 Cortex M4 Cortex R4 Renesas RX J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 42 CHAPTER 1 Introduction 1 6 Built in intelligence for supported CPU cores In general there are two ways to support a CPU core in the J Link software 1 Intelligence in the J Link firmware 2 Intelligence on the PC side DLL Having the intelligence in the firmware is ideal since it is much more powerful and robust The J Link PC software automatically detects which implementation level is supported for the connected CPU core If Intelligence in the firmware is available it is used If you are using a J Link that does not have intelligence in the firmware and only PC side intelligence is available for the connected CPU a warning message is shown J Link x x Warning 1 6 1 Intelligence in the J Link firmware On newer J Links the intelligence for a new CPU core is also available in the J Link firmware which means for these J Links the target sequences are no longer gener ated on the PC side but directly inside the J Link Having the intelligence in the firm
34. Initializes the CPU register with default values on startup Note For the GUI version this setting is persistent for following uses of GDB Server until changed via noir or the GUI Example jlinkgdbserver ir 3 3 5 6 jtagconf Syntax jtagconf lt IRPre gt lt DRPre gt Description Configures a JTAG scan chain with multiple devices on it lt IRPre gt is the sum of IRLens of all devices closer to TDI where IRLen is the number of bits in the IR Instruction Register of one device lt DRPre gt is the number of devices closer to TDI For more detailed information of how to configure a scan chain with multiple devices please refer to See Determining values for scan chain configuration on page 143 Example Select the second device where there is 1 device in front with IRLen 4 jlinkgdbserver jtagconf 4 1 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 91 3 3 5 7 localhostonly Description Starts the GDB Server with the option to listen on localhost only This means that only TCP IP connections from localhost are accepted or on any IP address To allow remote debugging connecting to GDBServer from another PC deactivate this option If no parameter is given it will be set to 1 active Note For the GUI version this setting is persistent for following uses of GDB Server until changed via command line option or the GUI Syntax LocalhostOnly lt State gt Exam
35. J Trace Rev 1 All tests have been performed in the testing environment which is described on Mea suring download speed on page 308 The actual speed depends on various factors such as JTAG clock speed host CPU core etc 1 3 7 4 Hardware versions Version 1 This J Trace uses a 32 bit RISC CPU Maximum download speed is approximately 420 KBytes second 600 KBytes second using DCC J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 36 CHAPTER 1 Introduction 1 3 8 J Trace for Cortex M 1 for Cortex M is a JTAG SWD emulator designed for Cor tex M cores which includes trace ETM support J Trace for Cortex M can also be used as a J Link and it also supports 7 9 cores Tracing ARM7 9 targets is not supported 1 3 8 1 Additional features e Has all the J Link functionality e Supports tracing on Cortex M targets 1 3 8 2 Specifications The following table gives an overview about the specifications general mechanical electrical for J Trace for Cortex M All values are valid for the latest hardware ver sion of J Trace for Cortex M General For a complete list of all operating sys Supported OS tems which are supported please refer to Supported OS on page 19 Electromagnetic compatibility EMC EN 55022 EN 55024 Operating temperature T59C 60 C Storage temperature 20 C 65 C Relative humidity non conde
36. Section Command strings updated 53 081216 Chapter Working with J Link Pro updated Chapter Working with J Link Pro added 52 081212 AG Chapter Licensing Section Original SEGGER products updated 51 081202 Several corrections Chapter Flash download and flash breakpoints 90 Section Supported devices 49 081029 Several corrections Chapter Working with J Link and J Trace 48 080916 AG Section Connecting multiple J Links 1 to your PC updated 47 080910 Chapter Licensing updated Chapter Licensing added Chapter Hardware J Link OEM versions moved to chapter Licensing Chapter Hardware 45 080902 Section JTAG Trace connector JTAG Trace connector pinout corrected Section J Link OEM versions updated Chapter J Link control panel moved to chapter 44 080827 AG Working with J Link Several corrections Chapter Flash download and flash breakpoints is 0809826 Section Supported devices updated Chapter Flash download and flash breakpoints 12 980820 Section Supported devices updated i Chapter Flash download and flash breakpoints updated 1 080811 Chapter Flash download and flash breakpoints section Supported devices updated Chapter Flash download and flash breakpoints updated 40 080630 Chapter J Link status window renamed to J Link control panel Various
37. SetRestartOnClose Specifies restart behavior on close SetDbgPowerDownOnClose Used to power down the debug unit of the target CPU when the debug session is closed SetSysPowerDownOnIl dle Used to power down the target CPU when there are no transmissions between J Link and target CPU for a specified timeframe SupplyPower Activates Deactivates power supply over pin 19 of the JTAG connector SupplyPowerDefault Activates Deactivates power supply over pin 19 of the JTAG connector permanently Table 5 11 Available command line options J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 177 5 11 1 1 device This command selects the target device Syntax device DeviceID DeviceID has to be a valid device identifier For a list of all available device identifi ers please refer to chapter Supported devices on page 190 Example device AT91SAM7S256 5 11 1 2 DisableFlashBPs This command disables the FlashBP feature Syntax DisableFlashBPs 5 11 1 3 EnableFlashBPs This command enables the FlashBP feature Syntax EnableFlashBPs 5 11 1 4 map exclude This command excludes a specified memory region from all memory accesses All subsequent memory accesses to this memory region are ignored Memory mapping Some devices do not allow access of the entire 4GB memory area Ideally the ent
38. Unlocking 249 If your device has been locked by setting the MCU security status to secure and mass erase via debug interface is not disabled J Link is able to unlock your Kinetis K40 K60 device The device can be unlocked by using the unlock command in J Link Commander For more information regarding the MCU security status of the Kinetis devices please refer to the user manual of your device 9 6 1 2 Tracing The first silicon of the Kinetis devices did not match the data setup and hold times which are necessary for ETM Trace On these devices a low drive strength should be configured for the trace clock pin in order to match the timing requirements J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 250 CHAPTER 9 Device specifics On later silicons this has been corrected This bug applies to all devices with mask 0M33Z from the 100MHz series The J Link software and documentation package comes with a sample project for the Kinetis 40 and K60 devices which is pre configured for the TWR 40 and TWR 60 eval boards and ETM ETB Trace This sample project can be found at Sam ples JLink Projects 9 6 1 3 Data flash support Some devices of the Kinetis family have an additional area called FlexNVM which can be configured as data flash The size of the FlexNVM to be used as data flash is con figurable and needs to be configured first before this area can be used as data flash
39. and subpriority PriorityGroup specifies the length This parameter can be one of the 4 bits for subpriority XXX Xx x Xxx 3 bits for subpriority NUIC PriorityGroup_2 2 bits for pre emption priority 2 bits for subpriority NUIC PriorituGroup 3 3 bits for pre emption priority 1 bits for subpriority NUIC PriorituGroup 4 4 bits for pre emption priority bits for subpriority Check the parameters assert NUIG PRIORITY GROUPCNUIC PriorityGroup priorit e priority grouping pre emption priority rouping bits Following values NUIC PriorityGroup 0 bits for pre emption priority NUIC PriorityGroup 1 1 bits for pre emption priority Set the PRIGROUPI18 81 bits FIER d to NUIC PriorityGroup value SCB gt AIRCR RIRCR UECTKEY MASK NUIC PriorityGroup Function Name 108 Description Input NUIC_Init Initializes the NUIC parameters in the NUIC InitStruct NUIC InitStruct pointer to a NUIC InitT that contains the configuration informat specified NUIC peripheral None None amp Output Return He NUIC_Init lt NUIC_InitTypeDef NUIC_InitStruct gt 318 u32 tmppriority 0 00 tmpreg 0x00 tmpmask 0 005 B 9 u32 tmppre tmpsub eripheral according to the specified Def structure n for the 08000842 4770 Dma2_Channe 1_IRQHand er A2_Channel1_IRQHandler ext 67 08000844 4770 Bx DMA2 Channe12 IRQHandler DM
40. and the color indica tor is red Target interface Shows the selected target interface JTAG SWD and the cur rent JTAG speed The target current is also shown Only visible if J Link is con nected Endian Shows the target endianess Only visible if J Link is connected Device Shows the selected device for the current debug session License Opens the J Link license manager About Opens the about dialog J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG CHAPTER 5 Working with J Link and J Trace 5 7 1 2 Settings In the Settings section project and debug specific settings can be set It allows the configuration of the use of flash download and flash breakpoints and some other tar get specific settings which will be explained in this topic Settings are saved in the configuration file This configuration file needs to be set by the debugger If the debugger does not set it settings can not be saved All settings can only the changed by the user himself All settings which are modified during the debug session have to be saved by pressing Save settings otherwise they are lost when the debug session is closed Section Flash download In this section settings for the use of the J Link FlashDL feature and related set tings be configured When a license for J Link FlashDL is found the color indi cator is green and License found appears right to the J Link FlashDL usage settings
41. e change all the code in your system including library code to use the new SWI number e reconfigure your debugger to use the new SWI number 8 5 3 Implementation of semihosting in J Link RDI When using J Link RDI in default configuration semihosting is implemented as fol lows e A breakpoint vector catch is set on the SWI vector e When this breakpoint is hit J Link RDI examines the SWI number e If the SWI is recognized as a semihosting SWI J Link RDI emulates it and trans parently restarts execution of the application e If the SWI is not recognized as a semihosting SWI J Link RDI halts the processor and reports an error See Unexpected unhandled SWIs on page 237 8 5 3 1 DCC semihosting J Link RDI does not support using the debug communications channel for semihost ing 8 5 4 Semihosting with AXD This semihosting mechanism can be disabled or changed by the following debugger internal variables semihosting_enabled Set this variable to 0 to disable semihosting If you are debugging an application run ning from ROM this allows you to use an additional watchpoint unit Set this variable to 1 to enable semihosting This is the default Set this variable to 2 to enable Debug Communications Channel DCC semihosting The S bit in vector_catch has no effect unless semihosting is disabled semihosting_vector This variable controls the location of the breakpoint set by J Link RDI to detect a semihosted SWI I
42. is the maximum time period in milliseconds to wait Example Wait for halt with a timeout of 2 seconds monitor waithalt 2000 3 3 3 33 wice Syntax wice RegIndex value or RegIndex value Description Writes to given IceBreaker register where value is the data to write Example gt monitor 0 0 0x100 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 84 J Link software and documentation package 3 3 4 SEGGER specific GDB protocol extensions J Link GDB Server implements some functionality which not part of the standard GDB remote protocol in general query packets These SEGGER specific general query packets can be sent to GDB Server on the low level of GDB via maintanace com mands or with a custom client connected to GDB Server General query packets start with a 4 SEGGER specific general queries are followed by the identifier Segger plus the command group the actual command and its parameters Following SEGGER specific general query packets are available Query Packet Explanation qSeggerSTRACE config Configure STRACE for usage qSeggerSTRACE start Start STRACE qSeggerSTRACE stop Stop STRACE qSeggerSTRACE read Read STRACE data Table 3 4 General Queries J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 85 3 3 4 1 qSeggerSTRACE config
43. monitor memU8 0x50000000 OxFF lt Writing OxFF address 0x50000000 3 3 3 13 memU16 Syntax memU16 lt address gt lt value gt Description Reads or writes a halfword from to a given address If lt value gt is specified this com mand writes the value to the given address Otherwise this command reads from the given address Example Read gt monitor memU16 0x50000000 lt Reading from address 0x50000000 Data 0x3004 Write gt monitor memU16 0x50000000 0 00 lt Writing OxFF00 8 address 0x50000000 3 3 3 14 memU32 Syntax MemU32 address value Description Reads or writes a word from to a given address If value is specified this com mand writes the value to the given address Otherwise this command reads from the given address This command is similar to the long command Example Read gt monitor memU32 0x50000000 lt Reading from address 0x50000000 Data 0x10023004 Write gt monitor memU32 0x50000000 0x10023004 lt Writing 0x10023004 address 0x50000000 3 3 3 15 reg Syntax reg lt RegName gt lt value gt reg lt RegName gt lt address gt Description Reads or writes from to given register If lt value gt is specified this command writes the value into the given register If lt address gt is specified this command writes the memory content at address lt address gt to register lt RegName gt Otherwise this com mand reads
44. 0x123456 3 3 3 22 semihosting ThumbSWI Syntax semihosting ThumbSWI Value Description Sets the SWI number used for semihosting in thumb mode The default value for the ThumbSWI is OxAB Example gt monitor semihosting ThumbSWI lt Semihosting Thumb SWI number set to 3 3 3 23 setargs Syntax setargs lt ArgumentString gt Description Set arguments for the application where all arguments are in one lt Argument String gt separated by whitespaces The argument string can be gotten by the application via semihosting command SYS GET CMDLINE 0x15 Semihosting has to be enabled for getting the argumentstring semihosting enable monitor setargs can be used before enabeling semihosting The maximum length for lt ArgumentString gt is 512 characters Example gt monitor setargs test 0 1 2 arg0 4 lt Arguments test 0 1 2 arg0 4 3 3 3 24 setbp Syntax setbp Addr lt Mask gt Description Sets an instruction breakpoint at the given address where Mask can be 0x03 for ARM instruction breakpoints Instruction width 4 Byte mask out lower 2 bits or 0 01 for THUMB instruction breakpoints Instruction width 2 Byte mask out lower bit If no mask is given an ARM instruction breakpoint will be set Example Set a breakpoint implicit for ARM instructions gt monitor setbp 0x00000000 Set a breakpoint on a THUMB instruction gt monitor setbp 0x00000100 0x01 J Link
45. 1 Intelligence in the J Link firmware sess men 42 1 6 2 Intelligence the PC side 1 6 nnn 42 1 6 3 Firmware intelligence per 0 44 1 7 S pported IDES story erri E Dr Ree Ra x E EE Pd rera TE 46 2 Reo ERI 47 Zid a e OA RUE E RR P CAR UR e e RR Components requiring a license48 2 2 License tyPES SEPATU 49 2 2 1 Built in CEN E naii ana p a E EAE E EA 49 2 2 2 Key based 1 6 O sea se a sua sena sea nnn 49 2 3 Legal use of SEGGER J Link 50 2 3 1 Use of the software with 3rd party 16 44 12 50 2 4 Original SEGGER prod cts 5 enero ten eoo a Pe cu erp e pda 51 2 4 1 Je LIN 51 2 4 2 J LinK PLUS icone cx vaca xo e v Ner ert i e X e e e ER o veer 51 2 4 3 Jslinlc ULTRA es exerce EY Sade e e pa neue PETI ARR EY CREE 52 2 4 4 SEL 52 2 4 5 J lra CE RE devs ARRA RA ERR ese TR ERE 53 2 4 6 J Trace for Cortex M icacu ect ax ke Fo RR Yu e X TR Fe EEE EY ROTE T x 53 2 4 7 ai riarlgil idem 54 2 4 8 aire
46. 37 2011 6 16 37 1 2011 Sep 6 16 37 2011 Sep 6 16 37 2011 Sep 6 16 37 2011 Sep 6 16 37 2011 Sep 6 16 37 2011 Sep 6 16 37 2011 Sep 16 37 2011 Sep 16 37 2011 Aug 18 19 57 Old 2011 Aug 18 19 57 Old 2011 Jul 26 17 24 Old 2011 Jul 26 17 24 Old 2011 Sep 6 16 37 2011 Aug 11 17 30 Old 2011 Jul 26 17 24 Old 2011 Sep 6 16 37 2011 Sep 16 37 2011 Sep 6 16 37 2011 Jul 26 17 24 Old 2004 2014 SEGGER Microcontroller GmbH amp Co KG 128 CHAPTER 4 Setup In order to configure a J Link to use the new USB identification method reporting the real serial number simply select Real SN as USB identification method and click the OK button The same dialog also allows configuration of the IP settings of the connected J Link if it supports the Ethernet interface Configure J Link Note When re configuring older J Links which use the old enumeration method USB identification USB 0 USB 3 you can only have 1 J Link connected which uses the old method at the same time So re configuration has to be done one at a time J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 129 4 6 J Link USB identification In general when using USB there are two ways in which a J Link can be identified e serial number e By USB address Default configuration of J Link is Identification by serial number Identification via USB address is used for compatibility and
47. 6 nennen 174 5 10 7 Executing J Link script files dx coe rex IR pear E ERE CARI ei 174 5 11 Command strings eene bias E taa Ee lee 176 5 11 1 List of available 11111 176 5 11 2 Using command strings missiera n err nen c en ed RA E 181 5 12 Switching off CPU clock during 183 5 13 Cache handlliig e preter e dut y ead Ede excu ra i va pei 184 5 13 1 Cache COHERENCY c cC 184 5 13 2 Cache clean area ced cd xe e xr praia e V CE RR ER RR C EY RUE V i de 184 5 13 3 Cache handling of ARM7 0 184 5 13 4 Cache handling of ARMO 184 5 14 Virtual COM Port VCOM dj entere tory ances Suae Ex d enc EE CO naa Iv ER dee Fa dE au RE es 185 5 14 1 Configuring Virtual COM emen 185 Flash downlodtd Eve olet TR COS Co 187 6 1 11314 aer 188 6 2 LICENSING 189 6 3 SUPPOFtEd devices ER 190 6 4 Setup for various debuggers internal 191 6 4 1 TAR Embedded nnn menm nnne nennen nnn 191 6 4 2 Keil MD Konic sce pde ete ee RE Va dE ev Ev
48. ARM 0 Processor Close the Connection Control Window fg ARM A RR ARM Ltd RDI targets Separator ARM instruction set simulator JLinkRDI dll J Link ARM RDI Interface Connection Broker Simulator Broker al Motorola Macraigor Wiggler emulator 82 MOT_WIGGLER Macraigor Wiggler pple ree ARM Ltd Direct Connection HS 26 5 U Versatile Platform for 926 0 5 USB port J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 219 9 Now the RealView Debugger is connected to J Link 2 RVDEBUG Start STR71x 0 ARM A RR Mo source for context _ENTRY_ lt entry point Click to Load C temp emb0S Start STR71x RAM Start STR7lx axf 00000000 SS DESDE 00000000 00000000 00000000 00000000 00000000 00000000 00000000 CPSR 00000003 0 0000000 Unknown Location gt connect route 2 gt connect 10 Advanced_info searched in Local Advanced_info Using Advanced info based on Default or All Warning Vector catching specification is not supported by target Warning No stack heap or top of memory defined using defaults Connected Target is ARM Vehicle ARM MultiP RDI 91 51 via DLL Mode Little Endian J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 220 8 RDI 10 A project or an image is needed for debugging After downloading J Link is used to debug the target 2 RYDEBUG Start_STR71x
49. ARM Rev 5 Hardware U5 38 S N 1 Features gt RDI FlashBP FlashDL JFlash GDB kHz 0 0 41069264 ARM J x1D192192 C L 32 gt DCache 32kB 4 256 32 gt 3 A 1 lt ARM gt 8 data comp decs 4 counters sequencer CETBL x 61 gt 1 9 01 1 88888800 42 x82 1 gt agp 211512121215 66800680 668006080 The result of the limited buffer size is that not more data can be traced than the buffer can hold Through this limitation is an ETB not in every case an fully fledged alternative to the direct access to an ETM via J Trace J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 298 CHAPTER 11 Background information 11 4 Flash programming J Link J Trace comes with a DLL which allows amongst other functionalities reading and writing RAM CPU registers starting and stopping the CPU and setting breakpoints The standard DLL does not have API functions for flash programming However the functionality offered can be used to program the flash In that case a flashloader is required 11 4 1 How does flash programming via J Link J Trace work This requires extra code This extra code typically downloads a program into the RAM of the target system which is able to erase and program the flash This program is called RAM code and knows how to program the flash it contains an implementa tion of the flas
50. Chapter Working with J Link Section Virtual COM Port VCOM added Chapter Setup Section Getting started with J Link and DS 5 V4 82 Rev 0 140218 JL Chapter Related Software Section GDB Server Command line option notimout added V4 80f Rev 0 140204 JL Chapter Related Software Section GDB Server Command line options and remote commands added V4 80 Rev 1 131219 JL NG Chapter Related Software Section GDB Server Remote commands and command line options description improved Several corrections V4 80 Rev 0 131105 JL Chapter Related Software Section GDB Server SEGGER specific GDB protocol extensions added V4 76 Rev 3 130823 JL Chapter Flash Download Replaced references to GDB Server manual Chapter Working withc J Link Replaced references to GDB Server manual V4 76 Rev 2 130821 JL Chapter Related Software Section GDB Server Remote commands added V4 76 Rev 1 130819 JL Chapter Related Software Section SWO Viewer Sample code updated V4 76 Rev 0 130809 JL Chapter Related Software Sections reordered and updated Chapter Setup Section Using JLinkARM dll moved here V4 71b Rev 0 130507 JL Chapter Related Software Section SWO Viewer Added new command line options V4 66 Rev 0 130221 JL Chapter Introduction Section S
51. Configure SWO for stimulus port 0 measure CPU frequency and calculate SWO frequency gt monitor SWO EnableTarget 0 01 0 SWO enabled succesfully Configure SWO for stimulus ports 0 2 fixed SWO frequency and measure CPU frequency gt monitor SWO EnableTarget 0 1200000 5 0 SWO enabled succesfully Configure SWO for stimulus ports 0 255 fixed CPU and SWO frequency gt monitor SWO EnableTarget 72000000 6000000 OxFF 0 SWO enabled succesfully 3 3 3 30 SWO GetMaxSpeed Syntax SWO GetMaxSpeed CPUFrequency Hz Description Prints the maximum SWO speed supported by and matching both J Link and the target CPU frequency Example Get SWO speed for 72MHz CPU speed gt monitor SWO GetMaxSpeed 72000000 Maximum supported SWO speed is 6000000 Hz J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 83 3 3 3 31 SWO GetSpeedinfo Syntax SWO GetSpeedInfo Description Prints the base frequency and the minimum divider of the connected J Link With this the available SWO speeds for J Link can be calculated and the matching one for the target CPU frequency can be selected Example monitor SWO GetSpeedInfo Base frequency 60000000Hz MinDiv 8 Available SWO speeds for J Link are 7 5MHz 6 66MHz 6MHz 3 3 3 32 waithalt Syntax waithalt lt Timeout gt or wh lt Timeout gt Description Waits for target to halt code execution where Timeout
52. Device specifics Section Freescale subsection Data flash support added Chapter Licensing Veen eG Bove OF Section Device based license updated Chapter Flash download Section J Link commander updated Chapter Support and FAQs Section Frequently asked questions updated Chapter J Link and J Trace related software Section J Link Commander updated V4 51h Rev 0 120717 Chapter Working with J Link V4 51e Rev 1 120704 EL Section Reset strategies updated and corrected Added reset type 8 Chapter Device specifics Section ST updated and corrected Chapter J Link and J Trace related software V4 51b Rev 0 120611 EL Section SWO Viewer added Chapter Device specifics Section ST subsection ETM init for some STM32 devices added Section Texas Instruments updated Chapter Target interfaces and adapters Section Pinout for SWD updated V4 51a Rev 0 120606 EL Chapter Device specifics VE Aa Reve 429412 Section Texas Instruments updated V4 46 Rev O 120416 Chapter Support updated Chapter Working with J Link Me REN a EE Section J Link script files updated J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG Revision Date By Explana
53. For more information about how to use J Link script files please refer to Executing J Link script files on page 174 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 272 9 18 Toshiba J Link has been tested with the following Toshiba devices TMPM321F10FG TMPM322F10FG TMPM323F10FG TMPM324F10FG TMPM330FDFG TMPM330FWFG TMPM330FYFG TMPM332FWUG TMPM333FDFG TMPM333FWFG TMPM333FYFG TMPM341FDXBG TMPM341FYXBG TMPM360F20FG TMPM361F10FG TMPM362F10FG TMPM363F10FG TMPM364F10FG TMPM366FDFG TMPM366FWFG TMPM366FYFG TMPM370FYDFG TMPM370FYFG TMPM372FWUG TMPM373FWDUG TMPM374FWUG TMPM380FWDFG TMPM380FWFG TMPM380FYDFG TMPM380FYFG TMPM382FSFG TMPM382FWFG TMPM395FWXBG CHAPTER 9 Device specifics Currently there are no specifics for these devices J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 273 Chapter 10 Target interfaces and adapters This chapter gives an overview about J Link J Trace specific hardware details such as the pinouts and available adapters J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 274 10 Target interfaces and adapters 10 1 20 JTAG SWD connector 10 1 1 Pinout for JTAG J Link and J Trace have a JTAG connector compati ble to ARM s Multi ICE The JTAG connector is a 20 way Insulation Displacement Connector IDC keyed box header
54. J Trace Permitted combinations are SWO output SWO input Deviation percent 6MHz n 12 6MHz n 10 0 4MHz n 18 4MHz n 15 0 lt 3 2MHz n 36 2MHz n 30 0 Table 5 7 Permitted SWO speed combinations Example 2 Target CPU running at 10 MHz Possible SWO output speeds are 10MHz 5MHz 3 33MHz J Link V7 Supported SWO input speeds are 6MHz n n gt 1 6MHz 3MHz 2MHz 1 5MHz Permitted combinations are SWO output SWO input Deviation percent 2 2 5 2 2 n 3 0 1MHz n 10 1MHz 6 0 769kHz n 13 750kHz n 8 2 53 Table 5 8 Permitted SWO speed combinations J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 147 5 5 Multi core debugging J Link J Trace is able to debug multiple cores on one target system connected to the same scan chain Configuring and using this feature is described in this section 5 5 1 How multi core debugging works Multi core debugging requires multiple debuggers or multiple instances of the same debugger Two or more debuggers can use the same J Link J Trace simultaneously Configuring a debugger to work with a core in a multi core environment does not require special settings All that is required is proper setup of the scan chain for each debugger This enables J Link J Trace to debug more than one core on a target at the same time The follow
55. JTAG emulator supporting a large number of CPU cores Based on a 32 bit RISC CPU it can communicate at high speed with the supported target CPUs J Link is used around the world in tens of thousand places for development and production flash programming purposes J Link is supported by all major IDEs such as IAR EWARM Keil MDK Rowley CrossWorks Atollic TrueSTUDIO IAR EWRX Renesas HEW Renesas e2studio and many others Licenses Comes with liicenses for Unlimited breakpoints in flash mem ory Unlimited Flash Breakpoints RDI and J Flash J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 52 CHAPTER 2 Licensing 2 4 3 J link ULTRA J link ULTRA is a JTAG SWD emulator designed for ARM Cor tex and other supported CPUs It is fully compatible to the stan dard J Link and works with the same PC software Based on the highly optimized and proven J Link it offers even higher speed as well as target power measurement capabilities due to the faster CPU built in FPGA and High speed USB interface It connects via USB to a PC running Microsoft Windows 2000 Windows XP Windows 2003 Windows Vista or Windows 7 an J link ULTRA has a built in 20 pin JTAG SWD connector f Licenses um Unlimited breakpoints in flash memory Unlimited Flash Break points RDI and J Flash 2 4 4 J Link PRO J Link PRO is a JTAG emulator designed for ARM cores It con nects via USB or Ethernet to a PC runni
56. Output JTAG mode set input of target CPU This pin should be pulled up on the target Typically connected to TMS of the target CPU TCK Output JTAG clock signal to target CPU It is recommended that this pin is pulled to a defined state of the target board Typically connected to TCK of the target CPU 11 RTCK Input Return test clock signal from the target Some targets must synchronize the JTAG inputs to internal clocks To assist in meeting this requirement you can use a returned and retimed TCK to dynamically control the TCK rate J Link supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes Con nect to RTCK if available otherwise to GND 13 TDO Input JTAG data output from target CPU Typically connected to TDO of the target CPU Table 10 1 J Link J Trace pinout J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 275 PIN SIGNAL TYPE Description Target CPU reset signal Typically connected to the RESET 15 RESET I O pin of the target CPU which is typically called nRST nRESET or RESET This pin is not connected in J Link It is reserved for com patibility with other equipment to be used as a debug IBBORO NG request signal to the target system Typically connected to DBGRQ if available otherwise left open This pin can be used to supply power to the tar
57. Ox7FD00000 0x7FDO1FFF On chip USB DMA RAM Ox7FD02000 0x7FD02000 Reserved Ox7FFFDO0OO0 0x7FFFFFFF Boot block remapped from on chip flash memory 0x80000000 0xDFFFFFFF Reserved OxE0000000 OxEFFFFFFF VPB peripherals OxF0000000 0xFFFFFFFF AHB peripherals The problematic memory areas are 0x00080000 0x3FFFFFFF Reserved 0x40008000 0x7FCFFFFF Reserved Ox7FD02000 0x7FD02000 Reserved 0x80000000 0xDFFFFFFF Reserved To exclude these areas from being accessed through J Link the map exclude com mand should be used as follows map exclude 0x00080000 0x3FFFFFFF map exclude 0x40008000 0x7FCFFFFF map exclude 0x7FD02000 0x7FD02000 map exclude 0x80000000 0xDFFFFFFF 5 11 1 5 map indirectread This command can be used to read a memory area indirectly Indirectly reading means that a small code snippet is downloaded into RAM of the target device which reads and transfers the data of the specified memory area to the host Before map indirectread can be called a RAM area for the indirectly read code snippet has to be defined Use therefor the map ram command and define RAM area with a size of gt 256 byte Typical applications Refer to chapter Fast GPIO bug on page 258 for an example Syntax map indirectread lt StartAddressOfArea gt lt EndAddress gt Example map indirectread Ox3fffc000 Ox3fffcfff 5 11 1 6 map ram This command should be used to define an area in RAM of the target device The area must be 256 byte aligned The
58. PC with 2 6 GHz Pentium 4 running Win2K USB 2 0 port USB 2 0 hub J Link Target with ARM7 running at 50MHz Below is a screenshot of JLink exe after the measurement has been performed EGGER J Link Commander 03 86 Compiled Jun 27 2008 19 42 43 asion U3 86 compiled Jun 27 2008 19 42 28 J Link ARM U6 compiled Jun 27 2008 18 35 51 JTAG speed Info TotalIRLen 4 IRPrint x 1 Found JTAG device Total IRLen 4 Id of device H8 x3JF F F F Found ARM with core Id 8x3FB8FBFBF J Link gt speed 12000 JTAG speed 126606 kHz J Link gt testwspeed Speed test Writing 8 128kb into memory address 6x66666000 128 kByte written 185ms 706 6 kb sec J Link gt J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 309 13 2 Troubleshooting 13 2 1 General procedure If you experience problems with J Link J Trace you should follow the steps below to solve these problems Close all running applications on your host system Disconnect the J Link J Trace device from USB Disable power supply on the target Re connect J Link J Trace with the host system attach USB cable Enable power supply on the target Try your target application again If the problem remains continue the following procedure 7 Close all running applications on your host system again 8 Disconnect the J Link J Trace device from USB 9 Disable power supply on the target 10 Re
59. Pinout The following table lists the JTAG Trace connector pinout It is compatible to the Trace Port Physical Interface described in ETM 8 2 2 Single target connector 281 pinout PIN SIGNAL Description 1 NC No connected 2 NC No connected 3 NC No connected 4 No connected 5 GND Signal ground 6 TRACECLK Clocks trace data on rising edge or both edges 7 DBGRQ Debug request Debug acknowledge from the test chip high when in 8 RPG PER state iim 9 RESET Open collector output from the run control to the target system reset 10 EXTTRIG Optional external trigger signal to the Embedded trace Macrocell ETM Not used Leave open on target system 11 TDO Test data output from target JTAG port Signal level reference It is normally fed from Vdd of the 12 VTRef target board and must not have a series resistor 13 RTCK Return test clock from the target JTAG port 14 VSupply Supply voltage It is normally fed from Vdd of the target board and must not have a series resistor 15 Test clock to the run control unit from the JTAG port Trace signal For more information please refer to 16 Trace signal 12 Assignment of trace information pins between ETM archi tecture versions on page 283 17 TMS Test mode select from run control to the JTAG port Trace signal For more information please refer to 18 Trace signal 11 Assignment of trace i
60. Questions Q A Supported CPUs Which CPUs are supported J Link J Trace should work with any ARM7 9 and Cortex M3 core For a list of supported cores see section Supported CPU cores on page 41 Converting data files I want to download my application into flash memory using J Link Commander but my application is a hex data file and J Link Commander supports bin files only How do I download it Please use the J Flash which is part of the J Link software and documentation package software to convert your hex mot file to a bin file For data file conversion no J Flash license is necessary Using J Link in my application I want to write my own application and use J Link J Trace Is this possible Yes We offer a dedicated Software Developer Kit SDK See section J Link Soft ware Developer Kit SDK on page 116 for further information Using DCC with J Link Can I use J Link J Trace to communicate with a running target via DCC Yes The DLL includes functions to communicate via DCC on cores which support DCC such as ARM7 9 11 Cortex A R series Read status of JTAG pins Can J Link J Trace read back the status of the JTAG pins Yes the status of all pins can be read This includes the outputs of J Link J Trace as well as the supply voltage which can be useful to detect hardware problems on the target system J Link support of ETM Does J Link support the Em
61. SEGGER Microcontroller GmbH amp Co KG 268 CHAPTER 9 Device specifics 9 16 4 STM32F4xxx These device are Cortex M4 based All devices of this family are supported by J Link 9 16 4 1 ETM init The following sequence can be used to prepare STM32F4xxx devices for 4 bit ETM tracing int v Enable GPIOE clock volatile int 0x40023830 0x00000010 Assign trace pins to alternate function in order to make them usable as trace pins PE2 Trace clock PE3 TRACE_DO TRACE D1 TRACE D2 PE6 TRACE D3 volatile int 0x40021000 0 00002 0 DBGMCU_CR enable trace I O and configure pins for 4 bit trace volatile int 0 0042004 amp 7 lt lt 5 Preserve all bits except the trace pin configuration v 7 lt lt 5 Enable trace I O and configure pins for 4 bit trace volatile int 0 0042004 v 9 16 4 2 Debugging with software watchdog enabled If the device shall be debugged with one of the software watchdogs independed watchdog window watchdog enabled there is an additional init step necessary to make the watchdog counter stop when the CPU is halted by the debugger This is configured in the DBGMCU_APB1_FZ register The following sequence can be used to enable debugging with software watchdogs enabled Configure both watchdog timers to be halted if the CPU is hal
62. STM32 Unlock JLinkSTM32 exe is a free command line tool which be used to disable the hardware watchdog of STM32 devices which can be activated by programming the option bytes Moreover the J Link STM32 Commander unsecures a read protected STM32 device by re programming the option bytes J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 115 Note Unprotecting a secured device or will cause a mass erase of the flash memory SEGGER J Link Unlock tool f TM32F1 x devices Compiled Apr 16 200 9 59 58 roller GmbH amp Co KG www segger com Solutions for real time microcontroller applications Connecting O K Performing init sequence 0 K SWD speed 8000 k Unlocking flash 0 K Pr any key to exit J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 116 CHAPTER 3 J Link software and documentation package 3 12 J Link Software Developer Kit SDK The J Link Software Developer Kit is needed if you want to write your own program with J Link J Trace The J Link DLL is a standard Windows DLL typically used from C programs Visual Basic or Delphi projects are also possible It makes the entire functionality of J Link J Trace available through its exported functions such as halt ing stepping the CPU core reading writing CPU and ICE registers and reading writing memory Therefore it can be used in any kind of application accessing an CPU core The standard D
63. Save data file as 4 Select Binary file bin as file type so J Flash knows that the file shall be saved as binary bin file 5 Click Save J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 196 CHAPTER 6 Flash download 6 4 6 J Link RDI The configuration for J Link RDI is done via the J Link RDI configuration dialog 5 SEGGER J Link R ta Configuration For more information about the J Link RDI configuration dialog please refer to 0 08004 J Link RDI User Guide chapter Configuration dialog J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 197 6 5 Setup for various debuggers CFI flash The setup for download into CFI compliant memory is different from the one for internal flash In this section the setup for different debuggers is explained 6 5 1 Embedded Workbench Keil Using the J Link flash download feature with IAR Embedded Workbench Keil MDK is quite simple First start the debug session and open the J Link Control Panel In the tab Settings you will find the location of the settings file SEGGER J Link 4 15r beta Control panel Close the debug session and open the settings file with a text editor Add the follow ing lines to the file CFI CFISize lt FlashSize gt CFIAddr lt FlashAddr gt GENERAL WorkRAMSize lt RAMSize gt WorkRAMAddr lt RAMAddr gt Afte
64. Setup JTAG Speed added Chapter Background information Flash program ming added 4 9519285 Setup Scan chain configuration added Some smaller changes 3 051021 Performance values updated 2 051011 Chapter Working with J Link added 1 050818 TW Initial version J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 13 About this document This document describes J Link and J Trace It provides an overview over the major features of J Link and J Trace gives you some background information about JTAG ARM and Tracing in general and describes J Link and J Trace related software pack ages available from Segger Finally the chapter Support and FAQs on page 307 helps to troubleshoot common problems For simplicity we will refer to J Link ARM as J Link in this manual For simplicity we will refer to J link Pro as J Link Pro in this manual Typographic conventions This manual uses the following typographic conventions Style Used for Body Body text Text that you enter at the command prompt or that appears on the Keywora display that is system functions file or pathnames Reference Reference to chapters tables and figures or other documents GUIElement Buttons dialog boxes menu names menu commands Table 1 1 Typographic conventions
65. Target power supply via Pin 19 is active Target power supply via Pin 19 is active Emulator pulls ORANGE RESET low active RED Emulator pulls RESET low active Table 5 4 J Link bi color output indicator J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 140 CHAPTER 5 Working with J Link and J Trace 5 3 JTAG interface By default only one device is assumed to be in the JTAG scan chain If you have mul tiple devices in the scan chain you must properly configure it To do so you have to specify the exact position of the CPU that should be addressed Configuration of the scan is done by the target application A target application can be a debugger such as the IAR C SPY debugger ARM s AXD using RDI a flash programming application such as SEGGER s J Flash or any other application using J Link J Trace It is the applica tion s responsibility to supply a way to configure the scan chain Most applications offer a dialog box for this purpose 5 3 1 Multiple devices in the scan chain J Link J Trace can handle multiple devices in the scan chain This applies to hard ware where multiple chips are connected to the same JTAG connector As can be seen in the following figure the and TMS lines of all JTAG device are connected while the TDI and TDO lines form a bus to Device1 to Device Currently up to 8 devices in the scan chain are supp
66. W JTAG ResetPin 0 SYS Sleep 5 Give pin some time to get low JTAG ResetPin 1 Pulls reset pin low Releases nTRST pin Used to issue a reset of the debug logic of the CPU Value assigned to reset pin reflects the state 0 Low 1 high W Example JTAG TRSTPin 0 SYS Sleep 5 Give pin some time to get low JTAG TRSTPin 1 Pulls TCK pin LOW HIGH Value assigned to reset pin reflects the state 0 LOW 1 HIGH JTAG TRSTPin JTAG TCKPin R W Example JTAG TCKPin 0 Pulls TDI pin LOW HIGH Value assigned to JTAG TDIPin reset pin reflects the state 0 LOW 1 HIGH R W Example JTAG TDIPin 0 Pulls TMS pin LOW HIGH Value assigned to JTAG TMSPin reset pin reflects the state 0 LOW 1 HIGH R W Example JTAG TMSPin 0 If the connected device has an ETB and you want to use it with J link this variable should be set to 1 Setting this variable in another function as EMU ETB IsPresent InitEmu does not have any effect W Example void InitEmu void EMU ETB IsPresent 1 Table 5 10 Global DLL variables J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 171 Variable Description R W Use ETB instead of RAWTRACE capability of the emulator Setting this variable in another func EMU ETB UseETB tion as InitEmu does not have any effect R Example EMU ETB UseETB 0
67. a complete list of all operating sys Supported OS tems which are supported please refer to Supported OS on page 23 Electromagnetic compatibility EMC EN 55022 EN 55024 Operating temperature 5 C 60 Storage temperature 209C 65 C Relative humidity non condensing Max 90 rH Mechanical Size without cables 100mm x 53mm x 27mm Weight without cables 73g Available interfaces USB interface USB 2 0 Hi Speed Target interface 20 pin J Link debug interface connector JTAG SWD Interface Electrical Target interface voltage Vir 1 8V 5V Target supply voltage 4 5V 5V Target supply current Max 300 Table 1 2 J link ULTRA specifications J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 30 CHAPTER 1 Introduction Reset Type Open drain Can be pulled low or tristated Reset low level output voltage VoL VoL lt 10 of VIF For the whole target voltage range 1 8V lt Vip lt 5V LOW level input voltage ViL lt 40 of Vig HIGH level input voltage Vy Vion gt 60 of Vig For 1 8V lt Vir lt 3 6V LOW level output voltage with a load of 10 VoL lt 10 of VIF HIGH level output voltage with a load of 10 kOhm VoH gt 90 of VIF For 3 6 lt Vir lt 5V LOW level output voltage with a load of 10 VoL lt 20 of HIGH level outp
68. abort ARM7 9 devices only On some CPUs during the init sequence for enabling access to the internal memory for exam ple on the TMS470 some dummy reads of memory are required which will cause an abort as long as the access init is not completed The default state is Checks enabled 3 3 3 6 flash breakpoints Syntax monitor flash breakpoints lt Value gt Description This command enables disables the Flash Breakpoints feature By default Flash Breapkoints are enabled and can be used for evaluation Example Disable Flash Breakpoints gt monitor flash breakpoints 0 lt Flash breakpoints disabled Enable Flash Breakpoins gt monitor flash breakpoints 1 lt Flash breakpoints enabled 3 3 3 7 getargs Syntax getargs Description Get the currently set argument list which will be given to the application when calling semihosting command SYS_GET_CMDLINE 0x15 The argument list is given as one string Example No arguments set via setargs gt monitor getargs lt No arguments Arguments set via setargs gt monitor getargs lt Arguments test 0 1 2 arg0 4 3 3 3 8 go Syntax go J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 76 J Link software documentation package Description Starts the target CPU Example gt monitor go 3 3 3 9 halt Syntax halt Description Halts the target CPU Example gt monitor halt 3 3 3 10 inter
69. been tested with the following NXP devices LPC1111 LPC1113 LPC1311 LPC1313 LPC1342 LPC1343 LPC1751 LPC1751 LPC1752 LPC1754 LPC1756 LPC1758 LPC1764 LPC1765 LPC1766 LPC1768 LPC2101 LPC2102 LPC2103 LPC2104 LPC2105 LPC2106 LPC2109 LPC2114 LPC2119 LPC2124 LPC2129 LPC2131 LPC2132 LPC2134 LPC2136 LPC2138 LPC2141 LPC2142 LPC2144 LPC2146 LPC2148 LPC2194 LPC2212 LPC2214 LPC2292 LPC2294 LPC2364 LPC2366 LPC2368 LPC2378 LPC2468 LPC2478 LPC2880 LPC2888 LPC2917 LPC2919 LPC2927 LPC2929 PCF87750 SJA2010 SJA2510 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 258 CHAPTER 9 Device specifics 9 11 1 LPC ARM 7 based devices 9 11 1 1 Fast GPIO bug The values of the fast GPIO registers can not be read direct via JTAG from a debug ger The direct access to the registers corrupts the returned values This means that the values in the fast GPIO registers normally can not be checked or changed from a debugger Solution Workaround J Link supports command strings which can be used to read a memory area indirect Indirectly reading means that a small code snippet will be written into RAM of the target device which reads and transfers the data of the specified memory area to the debugger Indirectly reading solves the fast GPIO problem because only direct regis ter access corrupts the register contents Define a 256 byte aligned area in RAM of the LPC target device with the J Link
70. checkbox If the Over ride checkbox is enabled a button appears which let the user choose the new location of the log file e Settings file Shows the path where the configuration file is placed This config uration file contains all the settings which can be configured in the Settings tab e Override device selection If this checkbox is enabled a dropdown list appears which allows the user to set a device manually This especially makes sense when J Link can not identify the device name given by the debugger or if a particular device is not yet known to the debugger but to the J Link software e Allow caching of flash contents If this checkbox is enabled the flash con tents are cached by J Link to avoid reading data twice This speeds up the trans fer between debugger and target Allow instruction set simulation If this checkbox is enabled instructions will be simulated as far as possible This speeds up single stepping especially when FlashBPs are used Save settings When this button is pushed the current settings in the Settings tab will be saved in a configuration file This file is created by J Link and will be created for each project and each project configuration e g Debug RAM Debug Flash If no settings file is given this button is not visible Modify breakpoints during execution This dropdown box allows the user to change the behavior of the DLL when setting breakpoints if the CPU is running The following o
71. com mand map ram define afterwards the memory area which should be read indirect with the command map indirectread to use the indirectly reading feature of J Link Note that the data in the defined RAM area is saved and will be restored after using the RAM area This information is applicable to the following devices LPC2101 LPC2102 LPC2103 LPC213x 01 LPC214x all devices LPC23xx all devices LPC24xx all devices Example J Link commands line options can be used for example with the C SPY debugger of the IAR Embedded Workbench Open the Project options dialog and select Debug ger Select Use command line options in the Extra Options tap and enter in the textfield jlink_exec_command map ram 0 40000000 0 40003 map indirec tread Ox3fffc000 Ox3fffcfff map exclude Ox3fffd000 Ox3fffffff as shown in the screenshot below ptions for node Project General ptions Compiler Assembler Custom Build Build Actions Linker link exec command map ram 0 40000000 040003fff map indire gt Simulator Angel IAR ROM monitor J LinkAJ Trace LMI FTDI Macraigor RDI Third Party Driver With these additional commands are the values of the fast GPIO registers in the C SPY debugger correct and can be used for debugging For more information about J Link command line options refer to subchapter Command strings on page 176 J Link J Trace UM08001 2004 2014 SEGGER Microcontr
72. corrections Chapter Flash download and flash breakpoints Section Licensing updated 39 080627 AG Section Using flash download and flash breakpoints with different debuggers updated Chapter J Link status window added J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG Revision Date By Explanation Chapter Support and FAQs Section Frequently Asked Questions updated 38 080618 Chapter Reset strategies Section Cortex M3 specific reset strategies updated Chapter Reset strategies 37 080617 Section Cortex M3 specific reset strategies updated Chapter Hardware Section Differences between different versions updated 938 2RUSSOL Chapter Working with J Link and J Trace Section Cortex M3 specific reset strategies added Chapter J Link and J Trace related software 35 080215 Section J Link software and documentation package in detail updated Chapter J Link and J Trace related software Section J Link TCP IP Server Remote J Link J Trace use updated Chapter Working with J Link and J Trace Section Command strings updated 94 Chapter Flash download and flash breakpoints Section Introduction updated Section Licensing updated Section Using flash download and flash breakpoints with different debuggers updated Chapter Flash download and flash breakpoints added 33 080
73. d e va res C Re E OO E o E 271 9 18 Ioh 272 10 Target interfaces and adapters Den ta 273 10 1 20 pin JTAG SWD connector 1 1 1 2 snas ana na nn n 274 10 1 1 Pinout for JTAG ecc a Eae ORE Era RR EE EX Fev uta cata 274 10 1 2 Pino t for SWD 277 10 1 3 Pinout for SWD Virtual COM Port 279 10 2 38 pin Mictor JTAG and Trace connector 0 4 0 000000 0 0 280 10 2 1 Connecting the target 280 10 2 2 PINOUT DE 281 10 2 3 Assignment of trace information pins between ETM architecture versions 283 10 2 4 5 9 eve deel nels 283 10 3 19 JTAG SWD Trace 2 285 10 3 1 Target power supply Rex rn er RR CO VC ROG E CELER 286 10 4 9 JTAG SWD 41 1 nnn nnn nnn 287 10 5 ERR 288 11 Background antoriallobi actua ves ES ac rado eoo Naas ore catal are Memes 289 11 1 290 11 1 1 Test access Port TAP uen dde axe eae ds ke er 290 11 1 2 Da
74. data which was located in the defined area will not be corrupted Data which resides in the defined RAM area is saved and will be restored if necessary This command has to be executed before map indirectread will be called Typical applications Refer to chapter Fast GPIO bug on page 258 for an example Syntax map ram lt StartAddressOfArea gt lt EndAddressOfArea gt Example map ram 0x40000000 0x40003fff J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 179 5 11 1 7 map reset This command restores the default memory mapping which means all memory accesses are permitted Typical applications Used with other map commands to return to the default values The map reset command should be called before any other map command is called Syntax map reset Example map reset 5 11 1 8 SetAllowSimulation This command can be used to enable or disable the instruction set simulation By default the instruction set simulation is enabled Syntax SetAllowSimulation 0 1 Example SetAllowSimulation 1 Enables instruction set simulation 5 11 1 9 SetCheckModeAfterRead This command is used to enable or disable the verification of the CPSR current pro cessor status register after each read operation By default this check is enabled However this can cause problems with some CPUs e g if invalid CPSR values are returned Please note that if this check is turned off SetChe
75. debuggers do not even allow memory access if the CPU is running Fortunately there is one other option DCC Direct communication channel can be used to communicate with the CPU while it is executing the application program All that is required is that the application program calls a DCC handler from time to time This DCC handler typically requires less than 1 us per call The DCC handler as well as the optional DCC abort handler is part of the J Link soft ware package can be found in the Samples DCC IAR directory of the package 5 9 1 What is required e An application program on the host typically a debugger that uses DCC e A target application program that regularly calls the DCC handler e The supplied abort handler should be installed optional An application program that uses DCC is JLink exe 5 9 2 Target DCC handler The target DCC handler is a simple C file taking care of the communication The func tion DcC_Process needs to be called regularly from the application program or from an interrupt handler If a RTOS is used a good place to call the DCC handler is from the timer tick interrupt In general the more often the DCC handler is called the faster memory can be accessed On most devices it is also possible to let the DCC generate an interrupt which can be used to call the DCC handler 5 9 3 Target DCC abort handler An optional DCC abort handler a simple assembly file can be included in the ap
76. desirable to use different configurations for different targets If this is the case a new folder needs to be created and the JLinkARM d1l as well as the JLinkRDI d11 needs to be copied into it Project A needs to be configured to use JLinkRDI d11 A in the first folder project B needs to be configured to use the DLL in the second folder Both projects will use separate configuration files stored in the same directory as the DLLs they are using If the debugger allows using a project relative path such as IAR EWARM Use for example PROJ_DIR RDI it can make sense to create the directory for the DLLs and configuration file in a subdirectory of the project 8 4 3 Using mutliple J Links simulatenously Same procedure as using different configurations Each debugger session will use their own instance of the JLinkRDI dll 8 4 4 Configuration dialog The configuration dialog consists of several tabs making the configuration of J Link RDI very easy J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 227 8 4 4 4 General tab J Link RDI Configuration 24 x General init JTAG Flash Breakpoints CPU Loa J Link RDI an ADI compliant software for J Link ARM It requires a license RDI which can be obtained from SEGGER www segger com This software is also capable of programming the flash memory of several micros which can be used to download your progr
77. download and flash breakpoints Section Supported devices updated Chapter Flash download and flash breakpoints TOOTO EN Section Supported devices updated Chapter Working with J Link and J Trace 79 091201 Section Reset strategies updated Chapter Licensing Section J Link OEM versions updated Chapter Licensing 19 Section J Link OEM versions updated Chapter Introduction 2 Section J Link J Trace models updated Chapter Introduction Section Specifications updated Section Hardware versions updated 76 090828 Section Common features of the J Link product family updated Chapter Target interfaces and adapters Section 5 Volt adapter updated Chapter Introduction Section J Link J Trace models updated i URIZAR AG Chapter Working with J Link and J Trace Section SWD interface updated Chapter Introduction Section Supported IDEs added Section Supported CPU cores updated 74 090722 Section Model comparison chart renamed to Model comparison Section J Link bundle comparison chart removed Chapter Introduction Section J Link and J Trace models added Sections Model comparison chart amp J Link bundle comparison chart added Chapter J Link and J Trace models removed 73 090701 IKN Hardware renamed to Target interfaces amp adapters Section JTAG Isolator added Chapter Target interf
78. due to the hardware archi tecture 5 13 1 Cache coherency When debugging or otherwise working with a system with processor with cache it is important to maintain the cache s and main memory coherent This is easy in sys tems with a unified cache and becomes increasingly difficult in systems with hard ware architecture A write buffer and a D Cache configured in write back mode can further complicate the problem ARM9 chips have no hardware to keep the caches coherent so that this is the responsibility of the software 5 13 2 Cache clean area J Link J Trace handles cache cleaning directly through JTAG commands Unlike other emulators it does not have to download code to the target system This makes setting up J Link J Trace easier Therefore a cache clean area is not required 5 13 3 Cache handling of ARM7 cores Because ARM7 cores have a unified cache there is no need to handle the caches dur ing debug 5 13 4 Cache handling of ARM9 cores ARM cores with cache require J Link J Trace to handle the caches during debug If the processor enters debug state with caches enabled J Link J Trace does the fol lowing When entering debug state J Link J Trace performs the following e it stores the current write behavior for the D Cache e it selects write through behavior for the D Cache When leaving debug state J Link J Trace performs the following e it restores the stored write behavior for the D Cache
79. e jit invalidates the D Cache Note The implementation of the cache handling is different for different cores However the cache is handled correctly for all supported cores J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 185 5 14 Virtual Port 5 14 1 Configuring Virtual COM Port In general the VCOM feature can be disabled and enabled for debug probes which comes with support for it via J Link Commander and J Link Configurator Below a small description howto use them to configure the feature is given Note VCOM can only be used when debugging via SWD target interface Pin 5 J Link Tx out Pin 17 J Link Rx in Note Currently only J Link models with hardware version 9 or newer comes with VCOM capabilites 5 14 1 1 Via J Link Configurator The J Link software and documentation package comes with a free GUI based utility called J Link Configurator which auto detects all J Links that are connected to the host PC via USB amp Ethernet The J Link Configurator allows the user to enable and disable the VCOM For more information about the J Link Configurator please refer to J Link Configurator on page 127 Configure J Link General Product SEGGER J Link ARM 9 00 SN 59200005 Nickname r USB Identification Real SN v Real SN 59200006 Virtual COM Port T Note The new configuration Disable applies after power cycling the debug probe
80. execution on close The default is to restart target execution This can be disabled by using this command Syntax SetRestartOnClose 0 1 Example SetRestartOnClose 1 5 11 1 13 SetDbgPowerDownOnClose When using this command the debug unit of the target CPU is powered down when the debug session is closed Note This command works only for Cortex M3 devices Typical applications This feature is useful to reduce the power consumption of the CPU when no debug session is active Syntax SetDbgPowerDownOnClose value Example SetDbgPowerDownOnClose SetDbgPowerDownOnClose 1 Enables debug power down on close 0 Disables debug power down on close 5 11 1 14 SetSysPowerDownOnldle When using this command the target CPU is powered down when no transmission between J Link and the target CPU was performed for a specific time When the next command is given the CPU is powered up Note This command works only for Cortex M3 devices Typical applications This feature is useful to reduce the power consumption of the CPU Syntax SetSysPowerDownOnIdle value Note A for lt value gt disables the power down on idle functionality J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 181 SetSysPowerDownOnIdle 10 The target CPU is powered down when there is transmission between J Link and target CPU for at least 10ms 5 11 1 1
81. for J Links with hardware version 6 but it can not be guaranteed that these J Links are always fast enough in disabling the watchdog 5 8 2 11 Type 10 Reset for Samsung S3FN60D devices On the Samsung S3FN60D devices the watchdog may be running after reset if the watchdog is active after reset or not depends on content of the smart option bytes at addr OxCO The watchdog keeps counting even if the CPU is in debug mode e g halted by a halt request or halted by vector catch When using this reset strategy J Link performs a reset of the CPU and peripherals using the SYSRESETREQ bit and sets VC CORERESET in order to halt the CPU after reset before it executes a single instruc tion Then the watchdog of the S3FN60D device is disabled J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 164 CHAPTER 5 Working with J Link and J Trace 5 9 Using DCC for memory access The ARM7 9 architecture requires cooperation of the CPU to access memory when the CPU is running not in debug mode This means that memory can not normally be accessed while the CPU is executing the application program The normal way to read or write memory is to halt the CPU put it into debug mode before accessing mem ory Even if the CPU is restarted after the memory access the real time behavior is significantly affected halting and restarting the CPU costs typically multiple millisec onds For this reason most
82. if the Cortex M4 or the Cortex MO shall be debugged in order to guarantee proper functionality Script file can be found at JLINK_INST_DIR Samples JLink Scripts For more information about how to use J Link script files please refer to Executing J Link script files on page 174 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 260 CHAPTER 9 Device specifics 9 12 J Link has been tested with the following OKI devices ML67Q4002 ML67Q4003 ML67Q4050 ML67Q4051 ML67Q4060 ML67Q4061 Currently there are no specifics for these devices J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 261 9 13 Renesas J Link has been tested with the following Renesas devices R5F56104 R5F56106 R5F56107 R5F56108 R5F56216 R5F56217 R5F56218 R5F562N7 R5F562N8 R5F562T6 R5F562T7 R5F562TA Currently there are no specifics for these devices J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 262 CHAPTER 9 Device specifics 9 14 Samsung J Link has been tested with the following Samsung devices S3FN60D 9 14 1 S3FN60D On the S3FN60D the watchdog may be running after reset depends on the content of the smart option bytes at addr OxCO The watchdog keeps counting even if the CPU is in debug mode e g halted So please do not use the watchdog when debug ging to avoid unexpected behavior of the target application A special
83. is a tool that analyzes SWO output Status summary of the analysis are output to standard out the details of the analysis are stored in a file Usage SWOAnalyzer exe lt SwWOfile gt This can be achieved by simply dragging the SWO output file created by the J Link DLL onto the executable Creating an SWO output file In order to create the SWO output file which is th input file for the SWO Analyzer the J Link config file needs to be modified It should contain the following lines SWO SWOLogFile C TestSwo dat J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 111 3 0 JTAGLoad Command line tool JTAGLoad is a tool that can be used to open an svf Serial vector format file The data in the file will be sent to the target via J Link J Trace SEGGER JTAG Load Compiled 13 33 56 on Dec 2 2005 Executing file C J_Trace svf J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 112 CHAPTER 3 J Link software and documentation package 3 10 J Link RDI Remote Debug Interface The J Link RDI software is an remote debug interface for J Link It makes it possible to use J Link with any RDI compliant debugger The main part of the software is an RDI compliant DLL which needs to be selected in the debugger There are two addi tional features available which build on the RDI software foundation Each additional feature
84. ok ok ok ck ok ok ok ok ok ck ck ck ck ck ck ck ck ck ok ck ck ck ok ck ck ck ck k ck kk kk kk 2012 2013 SEGGER Microcontroller GmbH amp Co KG www segger com Support support segger com J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 108 CHAPTER 3 J Link software and documentation package ck ckck ck ckck ck ck ck ck ck ck ck ck ck k ck k kk File SWO c Purpose Simple implementation for output via SWO for Cortex M processors It can be used with any IDE This sample implementation ensures that output via SWO is enabled in order to gurantee that the application does not hang END OF HEADER ERE KERR REE kkk e ke ke kkhk kkk kk kk kkk kkk kkk kkk kkk k kkk kk k kk k k Prototypes to be placed a header file such as SWO h E void SWO_PrintChar char c void SWO_PrintString const char s I kkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkk kkk kkhk kkk kkk kkk k Defines for Cortex M debug unit define ITM 5 032 volatile unsigned int 0xE0000000 STIM word access define ITM STIM 08 volatile char 0xE0000000 STIM Byte access define ITM ENA volatile unsigned 0 0000 00 ITM Enable Reg define ITM TCR volatile unsigned i
85. parsed line by line and one command is executed at a time J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 114 CHAPTER 3 J Link software and documentation package Syntax CommanderScript lt CommandFilePath gt Example See Using command files on page 64 DRPre DRPost IRPre and IRPost Scan Chain Configuration STR91x allows to configure a specific scan chain via command line To use this fea ture four command line options has to be specified in order to allow a proper connec tion to the proper device In case of passing an incomplete configuration the utility tries to auto detect Syntax DRPre DRPre DRPost lt DRPost gt IRPre IRPre IRPost lt IRPost gt Example JLink exe DRPre 1 DRPost 4 IRPre 16 IRPost 20 IP Selects IP as host interface to connect to J Link Default host interface is USB Syntax lt IPAddr gt Example JLinkSTR91x exe IP 192 168 1 17 Additional information To select from a list of all available emulators on Ethernet please use as lt IPAddr gt SelectEmuBySN Connect to a J Link with a specific serial number via USB Useful if multiple J Links are connected to the same PC and multiple instances of J Link STR91x Commander shall run and each connects to another J Link Syntax SelectEmuBySN lt SerialNo gt Example JLinkSTR91x exe SelectEmuBySN 580011111 3 11 2 J Link STM32 Unlock Command line tool J Link
86. period This feature allows set ting an unlimited number of breakpoints even if the application program is located in flash memory thereby utilizing the debugging environment to its fullest The debugger is trying to set a breakpoint in flash memory at address 008000200 The target CPU has run out of hardware breakpoints In order to set the requested breakpoint a software breakpoint in flash memory can be set Unlimited breakpoints in flash memory Flash Breakpoints is an enhanced feature of J Link which requires an additional license Some members of the J Link family such as the J Link Pro and J Link EDU already come with built in license for unlimited breakpoints in flash memory In order to buy a license for unlimited breakpoints in flash memory for the connected emulator please get in touch with sales segger com For more information regarding this feature please refer to http www segger com jlink_buy_flashbps html However using this feature without the additional license is possible and permitted if used for evaluation only Evaluate unlimited breakpoints in flash memory now J Link S N 58004070 B breakpoints are currently set 1 Addr 0508000200 Type Implementation Hard 2 Addr 0 0800020 Type Any Implementation Hard 3 Addr 0208000220 Type Implementation Hard 4 Addr 0 0800023 Any Implementation Hard 5 Addr 008000286 Implementation H
87. port 2333 The connection on this port can be opened all the time as soon as GDBServer is started even before this remote command is executed Example monitor semihosting enable Semihosting enabled VectorAddr 0x08 3 3 3 20 semihosting lOClient Syntax semihosting IOClient lt ClientMask gt Description GDB itself can handle file I O operations too With this command it is selected wheter to print output via TELNET port 2333 GDB or both lt ClientMask gt is e 1for TELNET Client Standard port 2333 Default e 2 for GDB Client e or 3 for both Input via GDB Client Example Select TELNET port as output source gt monitor semihosting ioclient 1 lt Semihosting I O set to TELNET Client Select GDB as output source gt monitor semihosting ioclient 2 lt Semihosting I O set to GDB Client Select TELNET port and GDB as output source gt monitor semihosting ioclient 3 lt Semihosting I O set to TELNET and GDB Client 3 3 3 21 semihosting ARMSWI Syntax semihosting ARMSWI lt Value gt J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 80 J Link software and documentation package Description Sets the SWI number used for semihosting in ARM mode The default value for the ARMSWI is 0x123456 Example gt monitor semihosting ARMSWI 0x123456 Semihosting ARM SWI number set to
88. second Unlimited number of breakpoints in flash FlashBP J Link GDBServer J Link RDI and J Flash production programming software e Embedded Trace Buffer ETB support J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 31 e Galvanic isolation from host via Ethernet 1 3 4 2 Hardware versions Version 1 1 Compatible to J Link e Provides an additional Ethernet interface which allows to communicate with J Link via TCP IP Version 4 e New design based on STM32F407 FPGA Cyclone IV Version 4 3 Identical to version 4 with the following exception e Pin 1 VTref is used for measuring target reference voltage only Buffers on J Link side are no longer powered through this pin but via the J Link internal volt age supplied via USB 1 3 5 J Link Lite ARM J Link Lite ARM is a fully functional OEM version of J Link If you are selling evaluation boards J Link Lite ARM is an inex pensive emulator solution for you Your customer receives a widely acknowledged JTAG emulator which allows him to start right away with his development 1 3 5 1 Additional features e Very small form factor e Fully software compatible to J Link e Supports any ARM7 9 11 Cortex A5 A8 A9 Cortex M0 M0 M1 M3 M4 Cortex R4 R5 core JTAG clock up to 4 MHz SWD SWO supported for Cortex M devices Flash download into supported MCUs Standard 20 pin 0 1 inch JTAG connector compatible to J Link 1 3 5 2
89. second scan chain following dialog box shows the configuration for the second ARM core on your target Options for node BTL_AT91_ 430 Category General Options C C Compiler Assembler Custom Build Build Actions Linker Debugger Simulator Angel IAR ROM monitor Macraigor RDI Third Party Driver Setup Connection Factory Settings Communication USB Meee aaa bbb cec ddd JTAG scan chain number fi JTAG scan chain with multiple targets Scan chain contains non amp RM devices Preceeding bits fo Log communication TOOLKIT DIR cspycomm log 7 Start debugging your second core Example number number 1 2 3 debugger 1 debugger 2 ARM7TDMI ARM7TDMI S ARM7TDMI 0 1 ARM7TDMI ARM7TDMI ARM7TDMI 0 2 ARM7TDM 1 ARM7TDMI S ARM7TDMI S 1 2 Table 5 9 Multicore debugging Cores to debug are marked in blue 5 5 3 Things you should be aware of Multi core debugging is more difficult than single core debugging You should be aware of the pitfalls related to JTAG speed and resetting the target JTAG speed 5 5 3 1 Each core has its own maximum JTAG speed The maximum JTAG speed of all cores in the same chain is the minimum of the maximum JTAG speeds For example e Core 1 e Core 2 2MHz maximum JT
90. strings The behavior of the J Link can be customized via command strings passed to the JLinkARM d11 which controls J Link Applications such as the J Link Commander but also the C SPY debugger which is part of the IAR Embedded Workbench allow pass ing one or more command strings Command line strings can be used for passing commands to J Link such as switching on target power supply as well as customize the behavior by defining memory regions and other things of J Link The use of command strings enables options which can not be set with the configuration dialog box provided by C SPY 5 11 1 List of available commands The table below lists and describes the available command strings Command Description device Selects the target device DisableFlashBPs Disables the FlashPB feature EnableFlashBPs Enables the Flashps feature map exclude Ignore all memory accesses to specified area map indirectread Specifies an area which should be read indirect map ram Specifies location of target RAM Map reset Restores the default mapping which means all mem ory accesses are permitted SetAllowSimulation Enable Disable instruction set simulation SetCheckModeAfterR ead Enable Disable CPSR check after read operations SetResetPulseLen Defines the length of the RESET pulse in milliseconds SetResetType Selects the reset strategy
91. targets Build scripts Notes parser options Debugger JLink GDBServer Select target i Target Device 3359 Little Endian Device list Target Connection SWD 7 4000 7 kHz IP Address localhost 2331 Override register definition file E J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 270 CHAPTER 9 Device specifics 9 17 1 2 Selecting the device when using GDBServer When using the J Link GDBServer the device needs to be known before GDB con nects to the GDBServer since GDBServer connects to the device as soon as it is started So selecting the device via monitor command is too late In order to select the device before GDBServer connects to it simply start it with the following com mand line device lt DeviceName gt Example JLinkGDBServer device AM3359 9 17 1 3 Selecting the device when using J Link Commander For J Link Commander type device lt DeviceName gt Then J Link Commander will perform a reconnect with the device name selected before 9 17 1 4 Known values for lt DeviceName gt For a list of all supported devices please refer to http www segger com jlink supported devices html 9 17 1 5 Required J Link hardware version The special handling for the AM335x cannot be supported by some older hardware versions of J Link so the device cannot be used with these versions The following hardware versions come with AM335x suppor
92. the J Link is connected to This type of license applies to the J Link PLUS J Link ULTRA and J Link Pro Key based license This type of license is used if you already have a J Link but order a license for a J Link software component at a later time In addition to that the key based license is used for trial licenses To enable this type of license you need to obtain a license key from SEGGER Free trial licenses are available upon request from www segger com This license key has to be added to the J Link license management How to enter a license key is described in detail in Licensing on page 203 Every license can be used on different PCs but only with the J Link the license is for This means that if you want to use flash breakpoints with other J Links every J Link needs a license This means that for example if you want to use the unlimited breakpoints in flash memory feature with different J Links which do not come with a built in license a license is needed for each of these J Links 2 2 1 Built in license This type of license is easiest to use The customer does not need to deal with a license key The software automatically finds out that the connected J Link contains the built in license s To check what licenses the used J Link have simply open the J Link commander JLink exe The J Link commander finds and lists all of the J Link s licenses automatically as can be seen in the screenshot below E C Windows syste
93. the steps of an init sequence An example for different soft ware tools such as J Link GDB Server IAR Workbench and RDI is given Set JTAG speed to 30kHz Reset target Perform peripheral reset Disable watchdog Initialize PLL Use full JTAG speed J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 244 9 Device specifics Samples GDB Sample connect to the J Link gdb server target remote localhost 2331 monitor flash device AT91SAM7S256 monitor flash download 1 monitor flash breakpoints 1 Set JTAG speed to 30 kHz monitor endian little monitor speed 30 Reset the target monitor reset 8 monitor sleep 10 Perform peripheral reset monitor long OxFFFFFDOO 0xA5000004 monitor sleep 10 Disable watchdog monitor long OxFFFFFD44 0x00008000 monitor sleep 10 Initialize PLL monitor long OxFFFFFC20 0 00000601 monitor sleep 10 monitor long OxFFFFFC2C 0x00480a0e monitor sleep 10 monitor long OxFFFFFC30 0 00000007 monitor sleep 10 monitor long OxFFFFFF60 0x00480100 monitor sleep 100 monitor speed 12000 break main load continue IAR Sample kkk kkk kkk kkk EERE EKER ERE k kkk kk kkk k k k kkk kkk kkk k kk kkk _Init __emulatorSpeed 30000 Set JTAG speed to 30 kHz __writeMemory32 0xA5000004 00 Memory Perform peripheral reset leep 20000 H ite
94. to communicate with R Example JTAG DRPre 2 Used for JTAG chain configuration Sets the num ber of IR bits of all devices which are closer to JTAG IRPost TDI than the one we want to communicate with Example JTAG IRPost 6 Used for JTAG chain configuration Sets the num ber of devices which are closer to TDI than the JTAG DRPost one we want to communicate with R Example JTAG DRPost 0 Table 5 10 Global DLL variables J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 170 5 Working with J Link and J Trace Variable Description R W IR Len in bits of the device we want to commu JTAG_TRLen nicate with R Example JTAG IRLen 4 Computed automatically based on the values of JTAG_IRPre JTAG_DRPre JTAG_IRPost and JTAG_TotalIRLen JTAG DRPost R Example v JTAG TotalIRLen En Disables auto JTAG detection of J Link Has to be disabled for devices which need some spe cial init for example to add the core to the JTAG JTAG AllowTAPReset chain which is lost at a TAP reset W Allowed values 0 Auto detection is enabled 1 Auto detection is disabled Sets the JTAG interface speed Speed is given in kHz JTAG_Speed Example W JTAG_Speed 2000 2MHz JTAG speed Pulls reset pin low Releases nRST pin Used to issue a reset of the CPU Value assigned to reset pin reflects the state 0 Low 1 high JTAG ResetPin Example
95. version of the JLinkARM dll you are facing the DLL version can be viewed by right clicking the DLL in explorer and choosing Properties from the context menu Click the Version tab to display information about the product ver sion jlinkarm dll Properties Company Name Internal Name Language Original Filename Product Name 4 7 44 Determining which DLL is used by a program To verify that the program you are working with is using the DLL you expect it to use you can investigate which DLLs are loaded by your program with tools like Sysinter nals Process Explorer It shows you details about the DLLs used by your program such as manufacturer and version y Process Explorer Sysinternals www sysinternals com E E System Idle Process Interrupts W DPC E E System E Bg explorer exe procexp exe Keyboard Language Indicator Shell SEGGER J Link ARM interface D Windows NT BASE API Client Microsoft Corporation 5 00 2195 6688 IAR Log Window IAR Systems 4 06 0000 0000 LZ Expand Compress API DLL Microsoft Corporation 5 00 2185 6611 MFCDLL Shared Library Retail Ve Microsoft Corporation 7 10 3077 0000 Multiple Provider Router DLL Microsoft Corporation 5 00 2185 6611 Process Explorer is at the time of writing a free utility which can be downloaded from www sysinternals com J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 133 4 8 Getting started with J Link and AR
96. which allow data file conversion Another possibility is to use J Flash which is part of the J Link software and documentation package For convert ing data files no J Flash license is needed In order to convert a hex mot file into a bin file using J Flash the following needs to be done 1 Start J Flash 2 Click File Open data file to open the data file to be converted in J Flash 3 Click File Save data file as 4 Select Binary file bin as file type so J Flash knows that the file shall be saved as binary bin file 5 Click Save J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 200 6 Flash download 6 6 Using the DLL flash loaders in custom applica tions The J Link DLL flash loaders make flash behave as RAM from a user perspective since flash programming is triggered by simply calling the J Link API functions for memory reading writing For more information about how to setup the J Link API for flash programming please refer to UM08002 J Link SDK documentation available for SDK customers only J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 201 Chapter 7 Flash breakpoints This chapter describes how the flash breakpoints feature of the DLL can be used in different debugger environments J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 202 CHAPTER 7 Flash breakpoints 7 1
97. with sample script files for different devices The sample script files can be found at JLINK_INST_DIR Sam ples JLink Scripts 5 10 6 Script file writing example In the following a short example how a J Link script file could look like In this example we assume a JTAG chain with two devices on it Cortex A8 4 bits IRLen cus tom device 5 bits IRLen void InitTarget void Report J Link script example JTAG Reset Perform TAP reset and J Link JTAG auto detection if JTAG TotalIRLen 9 Basic check if JTAG chain information matches MessageBox Can not find xxx device return 1 JTAG DRPre 0 Cortex A8 is closest to no no pre devices JTAG DRPost 1 1 device custom device comes after the Cortex A8 JTAG IRPre 0 Cortex A8 is closest to TDO no no pre IR bits JTAG IRPost custom device after Cortex A8 has 5 bits IR len JTAG IRLen 4 We selected the Cortex A8 it has 4 bits IRLen CPU CORTEX A8 We are connected to a Cortex A8 JTAG AllowTAPReset 1 We are allowed to enter JTAG reset We have a non CoreSight compliant Cortex A8 here which does not allow auto detection of the Core debug components base address so set it manually to overwrite the DLL auto detection CORESIGHT_CoreBaseAddr 0x80030000 5 10 7 Executing J Link script files 5 10 7 1 In J Link commander When J Link commander is started it searches fo
98. 00 003329 0 0800077 003349 0 0800 003351 Ox080082AC 003371 003372 8 003375 0 0800088 RCC GetFlagstatus _ 66 RCC GetFlagstatus Clk_Init 66 RCC_GetFlagstatus CIkK_Init 66 RCC GetFlagstatus clk_iInit 66 RCC GetFlagstatus Clk_Init 66 RCC_GetFlagstatus u8 Clk_Init 66 RCC GetFlagstatus u8 Clk_Init 66 RCC_GetFlagstatus u8 Clk_Init 66 RCC_GetFlagstatus Clk_Init 66 RCC GetFagstatus u8 _ 66 RCC_GetFlagstatus u8 ClkInit 66 RCC_GetFlagstatus Clk_Init 66 RCC_GetFlagstatus u8 CIkK_Init 66 RCC_USBCLKConfi g u32 clk_Init 76 RCC_ADCCLKConTig u32 _ 84 RCC_PCLK2Config u32 Clk_Init 90 RCC PCLK1Config u32 Clkrnit 98 RCC_HCLKContig u32 104 FLASH_SetLatency u32 clk_Init 110 FLASH HalfCycleAccesscmd u32 Clkrnit 116 FLASH PrefetchBuffercmd u32 Clk Init 122 RCC sYSCLKConfi g u32 _ 128 main 16 NVIC_setVectorTable u32 u32 J Link J Trace UM08001 003393 OxOS00BFCZ 003395 0x0800084C maint 26 NVIC_PriorityGroupconfig u32 1 _0 0800 4 Ox800BF28 08008 6 9800 RO RO 0 0 0800 8 PUSH R4 LR 0800 88 50 SP SP 0 20 debugt 0800 FO
99. 00 Logging started 2005 10 28 07 36 060 028 0000 DLL Compiled Oct 4 2005 09 14 54 060 031 0026 ARM SetMaxSpeed 3FOFOFOF 3FOFOFOF 3FOFOFOF 3FOFOFOF 3FOFOFOF Speed 4000 kHz 060 059 0000 ARM SetEndian ARM ENDIAN LITTLE 060 060 0000 ARM SetEndian ARM ENDIAN LITTLE 060 060 0000 ARM ResetPullsRESET ON 060 060 0116 ARM Reset SpeedIsFixed 0 060 176 0000 ARM WriteIceReg 0x02 00000000 060 177 0016 ARM WriteMem FFFFFC20 0004 Data 8 OxFFFFFC20 gt 1D7 gt 060 194 0014 ARM WriteMem FFFFFC2C 0004 Data OxFFFFFC2C gt 195 gt 060 208 0015 ARM WriteMem FFFFFC30 0004 Data 8 OxFFFFFC30 gt 195 gt 060 223 0002 ARM ReadMem 00000000 0004 speed 060 225 0001 ARM WriteMem 00000000 0004 Data 8 0x00000000 gt 195 gt 060 226 0001 ARM_ReadMem 00000000 0004 Data 060 227 0001 ARM WriteMem FFFFFF00 0004 Data 8 OxFFFFFFOO gt 195 gt 060 228 0001 ARM ReadMem FFFFF240 0004 Data 060 229 0001 ARM ReadMem FFFFF244 0004 Data 060 230 0001 ARM ReadMem FFFFFF6C 0004 Data 060 232 0000 ARM WriteMem FFFFF124 0004 Data OxFFFFF124 gt 195 gt 060 232 0001 ARM_ReadMem FFFFF130 0004 Data 060 233 0001 ARM ReadMem FFFFF130 0004 Data 060 234 0001 ARM ReadMem FFFFF130 0004 Data 060 236 0000 ARM ReadMem FFFFF130 0004 Data 060 237 0000 ARM ReadMem FFFFF130 0004 Data 060 238 0001 ARM ReadMem FFFFF130 0004 Data 060 239
100. 000 R6 hy 6616198F 2 2 0 2 2 aat R 8880888088 R10 i AOA Rii R12 B8BBBBB5F 3 662G1FD8 R14 080102495 AAAAOHAA R9 Ri6 66666606 Rii R12 0020208080 R14 88080808888 10000036 66000600 R14 800188708 2000007 66600806 Ri4 80080080 gt R FQGGGGF9 00202840 Ri4 gt R 888080887F A 4 m 256 KB flash 64 KB RAM Loading binary tile pin I Writing bin data into target mem Info J Link Flash download F1 programming performed for 1 range 16384 byt AM Info J Link Flash download 1 time needed 0 8445 Prepare 0 1165 Compar e 8 0205 Program 654s Verify 8 815s Restore 8 837s5 J Link 6 4 5 2 Converting non bin files As previously mentioned J Link Commander supports programming of bin files into flash memory If the data file to be programmed is in non bin format hex mot srec the file needs to be converted into binary first There are various free soft ware utilities available which allow data file conversion Another possibility is to use J Flash which is part of the J Link software and documentation package For convert ing data files no J Flash license is needed In order to convert a hex mot file into a bin file using J Flash the following needs to be done 1 Start J Flash 2 Click File Open data file to open the data file to be converted in J Flash 3 Click File
101. 00002780 RRRARAARARARARERE EEE REAARAREREREREREER ERA RARERERERERERE ERS 35 int main void 36 05 IncDI Initially disable interrupts 37 08 InitKern initialize 08 Led 0 00000000 38 05 InitHV initialize Hardware for 05 0x00000451 39 LED Init initialize LED ports 0 200015 0 40 You need to create at least one task here 0 00001 5 41 O5_CREATETASK sTCBO HP Task Task0 100 Stack0 iene 0 00000450 42 05 CREATETASK amp TCBl LP Task Taskl 50 Stackl i cpsr nzcvqIFT SVC 43 05 Start Start multitasking ay i AERE 44 return 0 25 nzcvqift_User 45 5 46 EFI ese zi ARM 1 Memory Start address 0x0 Tabl Hex No prefix Tab2 Hex No prefix Tab3 No prefix Tab4 10 wei C temp embOS_StarSTR71x4RC ARM 1 ES9FF018 59 018 59 018 0 00000010 59 018 1400000 59 014 59 014 0 00000020 00002444 00000030 00000040 00000044 0 00000030 00000048 000022 0 0000004 EAFFFFFE 0 00000040 EAFFFFFE EAFFFFFE EAFFFFFE iIennnnnnsn wannnnnn weaornenn No Pos J Link _1 Stat STR ZIxaxf 7 For Help press F1 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 215 8 3 3 RVDS RealView developer suite 8 3 3 1 Software version J Link RDI has been tes
102. 0001 ARM ReadMem FFFFF130 0004 Data 060 240 0001 ARM ReadMem FFFFF130 0004 Data 060 241 0001 ARM WriteMem FFFFFD44 0004 Data OxFFFFFD44 gt 195 gt 060 277 0000 ARM WriteMem 00000000 0178 Data 060 277 0000 ARM WriteMem 000003C4 0020 Data Writing 0x178 bytes 0x00000000 060 277 0000 ARM _WriteMem 000001CC 00F4 Data Writing 0x20 bytes 8 0 000003 4 060 277 0000 ARM WriteMem 000002C0 0002 Data 060 278 0000 ARM WriteMem 000002C4 0068 Data Writing OxF6 bytes 0x000001CC 060 278 0000 ARM WriteMem 0000032C 0002 Data 060 278 0000 ARM WriteMem 00000330 0074 Data Writing 0x6A bytes 0 000002 4 060 278 0000 ARM WriteMem 000003B0 0014 Data Writing 0x74 bytes 0x00000330 060 278 0000 ARM WriteMem 000003A4 000C Data Writing 0x14 bytes 8 0 000003 0 060 278 0000 ARM WriteMem 00000178 0054 Data Writing OxC bytes 0x000003A4 060 278 0000 ARM SetEndian ARM ENDIAN LITTLE 060 278 0000 ARM SetEndian ARM ENDIAN LITTLE 060 278 0000 ARM ResetPullsRESET OFF 060 278 0009 ARM Reset 060 287 0001 ARM Halt J Link J Trace UM08001 3FOFOFOF 01 05 07 gt JTAGSpeed 06 1 00 4000 OD 0c 01 40 00 10 ES OF 00 00 00 05 00 01 FF 00 00
103. 04 128 XMC4104 64 XMC4200 256 XMC4400 256 XMC4400 512 XMC4402 256 XMC4500 1024 XMC4500 768 XMC4502 XMC4504 Currently there are no specifics for these devices J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 9 10 Luminary Micro 255 J Link has been tested with the following Luminary Micro devices LM3S101 LM3S102 LM3S301 LM3S310 LM3S315 LM3S316 LM3S317 LM3S328 LM3S601 LM3S610 LM3S611 LM3S612 LM3S613 LM3S615 LM3S617 LM3S618 LM3S628 LM3S801 LM3S811 LM3S812 LM3S815 LM3S817 LM3S818 LM3S828 LM3S2110 LM3S2139 LM3S2410 LM3S2412 LM3S2432 LM3S2533 LM3S2620 LM3S2637 LM3S2651 LM3S2730 LM3S2739 LM3S2939 LM3S2948 LM3S2950 LM3S2965 LM3S6100 LM3S6110 LM3S6420 LM3S6422 LM3S6432 LM3S6610 LM3S6633 LM3S6637 LM3S6730 LM3S6938 LM3S6952 LM3S6965 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 256 CHAPTER 9 Device specifics 9 10 1 Unlocking LM3Sxxx devices If your device has been locked accidentially e g by bad application code in flash which mis configures the PLL and J Link can not identify it anymore there is a spe cial unlock sequence which erases the flash memory of the device even if it can not be identified This unlock sequence can be send to the target by using the unlock comnmand in J Link Commander J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 257 9 11 NXP J Link has
104. 207 Chapter Device specifics Section ATMEL AT91SAM7 Recommended init sequence added Chapter Device specifics 32 0080129 SK Section NXP LPC Fast GPIO bug list of device enhanced Chapter Device specifics PE SS Section NXP LPC Fast GPIO bug updated Chapter Device specifics Section Analog Devices updated Section ATMEL updated Section Freescale added Section Luminary Micro added 30 071211 Section NXP updated Section OKI added Section ST Microelectronics updated Section Texas Instruments updated Chapter Related software Section J Link STR91x Commander updated 29 070912 lt Chapter Hardware section Target board design updated Chapter Related software Section J LinkSTR91x Commander added Chapter Device specifics a 070242 Section ST Microelectronics added Section Texas Instruments added Subsection AT91SAM9 added J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG Revision Date By Explanation 28 070912 AG Chapter Working with J Link J Trace Section Command strings updated 27 070827 TQ Chapter Working with J Link J Trace Section Command strings updated 26 070710 SK Chapter Introduction Section Features of J Link updated Chapter Background Information Section Embedded Trace Macrocell added Section E
105. 4 Linux Mac OSX 10 5 and higher 23 2004 2014 SEGGER Microcontroller GmbH amp Co KG 24 CHAPTER 1 Introduction 1 3 J Link J Trace models J Link J Trace is available in different variations each designed for different pur poses target devices Currently the following models of J Link J Trace are avail able J Link J Link PLUS J Link PRO J Link ULTRA J Link ULTRA J Trace ARM J Trace for Cortex M In the following the different J Link J Trace models are described and the changes between the different hardware versions of each model are listed To determine the hardware version of your J Link J Trace the first step should be to look at the label at the bottom side of the unit J Links J Traces have the hardware version printed on the back label If this is not the case with your J Link J Trace start JLink exe As part of the initial message the hardware version is displayed Link J C Program Files SEGGER JLinkARM_ 402d JLink exe arget 0 0000 JTAG speed 5 kHz J Link J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 25 1 3 1 Model comparison The following tables show the features which are included in each J Link J Trace model Hardware features J Link J Link J Link J Link J Trace Plus ULTRA Pro for Cortex M USB yes yes yes yes yes yes Ethernet no no no yes no no Tracin
106. 5 Enable trace I O and configure pins for 4 bit trace volatile int 0xE0042004 9 16 2 2 Option byte programming J Flash supports programming of the option bytes for STM32 devices In order to program the option bytes simply choose the appropriate Device which allows option byte programming in the CPU settings tab e g STM32F103ZE allow bytes J Flash will allow programming a virtual 16 byte sector at address J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 266 CHAPTER 9 Device specifics 0x06000000 which represents the 8 option bytes and their complements You do not have to care about the option bytes complements since they are computated auto matically The following table describes the structure of the option bytes sector Address 31 24 23 16 15 8 7 0 0x06000000 complement Option byte 1 complement Option byte 0 0x06000004 complement Option byte 3 complement Option byte 2 0x06000008 complement Option byte 5 complement Option byte 4 0x0600000C complement Option byte 7 complement Option byte 6 Table 9 1 Option bytes sector description Note Writing a value of OxFF inside option byte will read protect the STM32 In order to keep the device unprotected you have to write the key value into option byte 0 Note originally located at address OxiFFFF800 Ox1FFFF800 is done automatically by J
107. 5 SupplyPower This command activates power supply over pin 19 of the JTAG connector The KS Kickstart versions of J Link have the V5 supply over pin 19 activated by default Typical applications This feature is useful for some eval boards that can be powered over the JTAG con nector Syntax SupplyPower 0 1 Example SupplyPower 1 5 11 1 16 SupplyPowerDefault This command activates power supply over pin 19 of the JTAG connector perma nently The KS Kickstart versions of J Link have the V5 supply over pin 19 activated by default Typical applications This feature is useful for some eval boards that can be powered over the JTAG con nector Syntax SupplyPowerDefault 0 1 Example SupplyPowerDefault 1 5 11 2 Using command strings 5 11 2 1 J Link Commander The J Link command strings can be tested with the J Link Commander Use the com mand exec supplemented by one of the command strings 2 J Link ARM 3 58c oy x SEGGER J Link Commander U AE edr Compiled Jan 12 2007 12 version U3 58c compiled Jan 12 2007 12 54 35 J Link compiled Feb 89 28087 19 59 46 ARM Rev 5 05 30 UTarget 3 313U JTAG speed 3 kHz 1 JTAG devic AFGF x4F1F F F lt ARM gt may t J Link gt exec map exclude 0x10800808 0x3FFFFFFF J Link J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 182 5 Working with J Link and J Trace Example exec SupplyPowe
108. 8001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 285 10 3 19 JTAG SWD and Trace connector J Trace provides a JTAG SWD Trace connector This connector is a 19 pin connector It connects to the target via an 1 1 cable VTref 1 2 SWDIO TMS GND 3 4 SWCLK TCK GND 5 ee 6 SWO TDO ewe 7 e8 TDI NC 9 10 nRESET 5V Supply 11 12 TRACECLK 5V Supply 13 14 TRACEDATA O0 GND 15 16 TRACEDATA 1 GND 17 18 TRACEDATA 2 GND 19 e 20 TRACEDATA 3 The following table lists the J Link J Trace SWD pinout PIN SIGNAL TYPE Description VTref Input This is the target reference voltage It is used to check if the target has power to create the logic level reference for the input comparators and to control the output logic levels to the target It is normally fed from Vdd of the target board and must not have a series resistor SWDIO TMS I O output SWDIO Single bi directional data pin JTAG mode set input of target CPU This pin should be pulled up on the target Typically connected to TMS of the target CPU SWCLK TCK Output SWCLK Clock signal to target CPU It is recommended that this pin is pulled to a defined state of the target board Typically connected to TCK of target CPU JTAG clock signal to target CPU SWO TDO Input JTAG data output from target CPU Typically connected to TDO of the target
109. A2 Channe12 IRQHander text 68 08000846 4770 2_ 1 _ 1 I2 Channel3 IRQHandler text 69 08000848 4770 MA2 Channel4 5 IRQHandler DMA2 Channel 4 s IRQHandler text 70 0800084 4770 LR oid NVIC priori tvsroupconfiofu32 NVIC Prioritysroup R4 RO P R4 0 700 NVIC PriorityGroupconfig o R4 0 600 NVIC PriorityGroupconfig 0 R4 0x500 08000860 EQ 2 NVIC PriorityGroupconfig o 08000862 5 46 80 R4 0 400 08000866 0002 NVIC PriorityGroupconfig o 08000868 R4 0 300 vIC PriorityGroupconfig 1 NVIC PriorityGroupconfig 2 N 5 46 boos F5B46FC0 0008 08000850 08000854 08000856 0800085 0800085 FSB46FAO 0005 5 1 08000876 F7FEFCAB BL assert failed SCB gt AIRCR VECTKEY MASK NVIC Priori tyGroup NVIC Prierityaroupconfig 2 0800087 F8DF0058 LDR W 0800087 6800 LOR RO Ro RO PC 0 58 9 of 002368 002403 002407 002442 002446 002481 002485 002520 002524 002559 002563 002598 002602 002637 002641 002676 002680 002715 002719 002754 002758 002793 002797 002832 002836 002871 002875 002883 002885 002906 002908 002923 002925 002942 002944 002959 002961 002985 002987 002009 003011 003031 003033 003053 003054 003057 003075 0 0800 5 4 0 0800 080085 4 0 0800 0x0800B5A4 0x0800
110. AG this pin may be connected to nTRST otherwise leave open This pin is used as VCOM Tx out on J Link side in case 5 J Link Tx Output VCOM functionality of J Link is enabled For further informa tion about VCOM please refer to Virtual COM Port VCOM on page 185 Single bi directional data pin A pull up resistor is required 1 0 ARM recommends 100 kOhms Clock signal to target CPU It is recommended that this pin is pulled to a defined state 3 SWGEK the target board Typically connected to of target CPU This pin is not used by J Link when operating in SWD mode 11 Not used NC If the device may also be accessed via JTAG this pin may be connected to RTCK otherwise leave open Serial Wire Output trace port Optional not required for SWD communication Target CPU reset signal Typically connected to the RESET 15 RESET I O pin of the target CPU which is typically called nRST nRESET or RESET This pin is used as VCOM Rx in on J Link side in case 17 J Link Rx VCOM functionality of J Link is enabled For further informa tion please refer to Virtual COM Port VCOM on page 185 This pin can be used to supply power to the target hard 5V Sup ware Older J Links may not be able to supply power on this 19 Output pin For more information about how to enable disable the ply power supply please refer to Target power supply on page 278 Table 10 5 J Link J T
111. AG GetU32 int BitPos 5 10 2 14JTAG WriteClocks Description Writes a given number of clocks Prototype api int JTAG WriteClocks int NumClocks 5 10 2 15JTAG StoreClocks Description Stores a given number of clocks in the DLL JTAG buffer Prototype api int JTAG StoreClocks int NumClocks 5 10 2 16JTAG Reset Description Performs a TAP reset and tries to auto detect the JTAG chain Total IRLen Number of devices If auto detection was successful the global DLL variables which determine the JTAG chain configuration are set to the correct values For more information about the known global DLL variables please refer to Global DLL variables on page 169 Note This will not work for devices which need some special init for example to add the core to the JTAG chain which is lost at a TAP reset Prototype api int JTAG Reset void 5 10 2 17SYS Sleep Description Waits for a given number of miliseconds During this time J Link does not communi cate with the target Prototype api int SYS Sleep int Delayms J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 169 5 10 2 18CORESIGHT_AddAP Description Allows the user to manually configure the AP layout of the device J Link is connected to This makes sense on targets where J Link can not perform a auto detection of the APs which are present of the target system Type can only be a known global J Link DLL AP c
112. AG interface If you use the adaptive clocking feature transmission delays gate delays and syn chronization requirements result in a lower maximum clock frequency than with non adaptive clocking 2004 2014 SEGGER Microcontroller GmbH amp Co KG 145 5 4 SWD interface The J Link support ARMs Serial Wire Debug SWD SWD replaces the 5 pin JTAG port with a clock SWDCLK a single bi directional data SWDIO providing all the normal JTAG debug and test functionality SWDIO and SWCLK are overlaid on the TMS and TCK pins In order to communicate with a SWD device J Link sends out data on SWDIO synchronous to the SWCLK With every rising edge of SWCLK one bit of data is transmitted or received on the SWDIO 5 4 1 SWD speed Currently only fixed SWD speed is supported by J Link The target is clocked at a fixed clock speed The SWD speed which is used for target communication should not exceed target CPU speed 10 The maximum SWD speed which is supported by J Link depends on the hardware version and model of J Link For more information about the maximum SWD speed for each J Link J Trace model please refer to J Link J Trace models on page 24 5 4 2 SWO Serial Wire Output SWO support means support for a single pin output signal from the core The Instrumentation Trace Macrocell ITM and Serial Wire Output SWO can be used to form a Serial Wire Viewer SWV The Serial Wire Viewer provides a low cost met
113. AG speed 4MHz maximum JTAG speed e Scan chain 2MHz maximum JTAG speed J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 150 CHAPTER 5 Working with J Link and J Trace 5 5 3 2 Resetting the target All cores share the same RESET line You should be aware that resetting one core through the RESET line means resetting all cores which have their RESET pins con nected to the RESET line on the target J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 151 5 6 Connecting multiple J Links J Traces to your In general it is possible to have an unlimited number of J Links J Traces connected to the same PC Current J Link models are already factory configured to be used ina multi J Link environment older J Links can be re configured to use them in a multi J link environment 5 6 1 How does it work USB devices are identified by the OS by their product id vendor id and serial number The serial number reported by current J Links is a unique number which allows to have an almost unlimited number of J Links connected to the same host at the same time The sketch below shows a host running two application programs Each application communicates with one CPU core via a separate J Link Older J Links J Traces all reported the same serial number which made it necessary to configure them for USBO 3 if multiple J Link should be connected to the same PC in parallel
114. Allow connections from outside localhost Linux default logtofile Generate a GDB Server log file nologtofile Do not generate a GDB Server log file Default halt Halt the target on start of GDB Server nohalt Do not halt the target on start of GDB Server Default silent Do not show log output nosilent Show log output Default stayontop Set the GDB Server GUI to be the topmost window nostayontop Do not be the topmost window Default vd Verify after downloading novd Do not verify after downloading Default Table 3 7 Persistent command line options J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 88 CHAPTER 3 J Link software and documentation package Following additional command line options are available These options are tempo rary for each start of GDB Server Command line option Explanation jtagconf Configures a JTAG scan chain with multiple devices on it log Log the GDB Server communication to a specific file notimeout Do not close GDB Server when target connection fails singlerun Start GDB Server in single run mode scriptfile Use a J Link scriptfile select Select the interface to connect to J Link USB IP settingsfile Select the J Link Settings File Execute gdb file on first connection Execute gdb file on every connection cpu Select the CPU core Deprecated use devic
115. B SP SP 0x20 debug 0800 001 8 8 BL debug ENTR SECTION S itl 0800 4 F7FFFFG2 BL Clk Init NVIC setvectorTable NVIC VectTab FLASH 0x0 OSOOBFBS 2100 MOVS R1 0x0 OS00BFBA 05 6000 MOVS RD 0 8000000 0800 rODirCes 8L nvic_setvectorrable riori OSOGBFCI F4AF7040 MOV RO 0 300 0800 6_ FOD1FC4l PriorityGroupconfig Ti Tick ITCont NAI i 0800BFD0 2001 IOVS RO 0 1 CED BL 5 Eres 1 2001 MOVS RO xi 08008 08 1 BL SysTick c oun TE PB2PeriphRese h A I Rew ETE 5108 DISABLE O800BFDC 2100 Movs R1 0 0 OSODBFDE F44F7082 MOV 0 104 0800 2 F7FFFASO BL RCC_APB2PeriphRes etcmd RCC APB2Periphclockcmd RCC APB2Periph GPIOA RCC APB2Periph GPIOG ENABLE NVIC SetVectorTable 2 assert param IS NVIC OFFSET Offset NVIC setvectorTable 2 003065 003383 0 080008 LOR PC 0x1C 003066 003384 8000 CMP R5 RO 003067 003385 0X0800D8AE Bcc NVIC_SetvectorTable_4 08008 6 2101 Movs R1 0 1 08008 8 F44F7082 MOV RO 0x104 0800 F7FFFA20 BL APB2Periphclockcmd GPIO Initstructure GPIO Pin MASK DSODBFFO F44F7080 MOV RO 0 100 0800 4 F8AD0000 STRH RO SP GPIO_Initstructure PIO Mode cero mode IN FLOATING P SCB gt VTOR NVIC VectTab Offset amp u32 0x1FFFFF80 SetVectorTable 4 003068 003386 OXD
116. BEBE 0x0800B5A4 0x0800BEBE 080085 4 0 0800 0 080085 4 00800854 008008544 0 0800 0 080085 4 008008544 0 0800 0 080085 4 0 0800 0x080085A4 0x0800BEBE 0x0800B5A4 0 0800 0 0800 8 OxOB00B3EC 0x0800BED0 0x0800837C 0 0800 06 0 08008334 Ox0800BEDE 0 080082 4 0x0800BEE4 0 0800070 0 0800 0 08000746 0 0800 0 0 0800077 0x0800BEFE 0x0800B2AC 0XxX0800BEFC 0x0800BFB8 0x0800088C 0 0800 2 RCC GetFlagstatus _ 66 RCC_GetFlagStatus us Clk_Init 66 RCC_GetFlagStatus us Clk_Init 66 RCC GetFlagstatus clk_init 66 RCC_GetFlagstatus Clk_Init 66 RCC_GetFlagStatus Clk_Init 66 RCC GetFlagstatus _ 66 RCC_GetFlagstatus us Clk_iInit 66 RCC_GetFlagStatus us _ 66 RCC GetFlagstatus Clk Init 66 RCC GetFlagstatus us Clknit 66 RCC_GetFlagStatus us Clk_Init 66 RCC GetFlagstatus Clk Init 66 RCC_USBCLKConfi g u32 76 RCC_ADCCLKConFi g u32 1 _ 84 RCC_PCLK2Confi g u32 _ 90 RCC PCLK1Config u32 98 RCC HCLKConfi g u32 ClkoInit 104 FLASH SetLatency u32 Clkanit 110 002725 002760 002764 002799 002803
117. Basically J Link RDI con sists of a additional DLL JLinkRDI d11 which builds the interface between the RDI API and the normal J Link DLL The JLinkRDI d11 itself is part of the J Link software and documentation package 8 3 1 IAR Embedded Workbench IDE J Link RDI can be used with Embedded Workbench for ARM 8 3 1 1 Supported software versions J Link RDI has been tested with Embedded Workbench IDE version 4 40 There should be no problems with other versions of IAR Embedded Workbench IDE All screenshots are taken from IAR Embedded Workbench version 4 40 Note Since IAR EWARM V5 30 J Link is fully and natively supported by EWARM so RDI is no longer needed 8 3 1 2 Configuring to use J Link RDI 1 Start the IAR Embedded Workbench and open the tutor example project or the desired project This tutor project has been preconfigured to use the simulator driver In order to run the J Link RDI you the driver needs to be changed IAR Embedded Workbench IDE EN nj sd st enable the clock of the PIO PMC EnablePeriphClock 91 BASE PMC 1 lt lt AT91C ID PIOA configure the PIO Lines corresponding to LEDI to LED4 be outputs No need to set these pins to be driven by the PIO because it i Options CfgOutput 91 BASE PIOA LED MASK X J LED s the EB55 we must apply a i to turn off LEDs SetOutput 91 BASE LED
118. C 9 e e 10 nRESET The following table lists the output of the 9 pin Cortex M connector PIN SIGNAL TYPE Description 1 VTref Input This is the target reference voltage It is used to check if the target has power to create the logic level reference for the input comparators and to control the output logic levels to the target It is normally fed from Vdd of the target board and must not have a series resistor SWDIO TMS I O output SWDIO Single bi directional data pin JTAG mode set input of target CPU This pin should be pulled up on the target Typically connected to TMS of the target CPU 4 SWCLK TCK Output SWCLK Clock signal to target CPU It is recommended that this pin is pulled to a defined state of the target board Typically connected to TCK of target CPU JTAG clock signal to target CPU 6 SWO TDO Input When using SWD this pin is used as Serial Wire Output trace port optional not required for SWD communica tion JTAG data output from target CPU Typically connected to TDO of the target CPU This pin normally pin 7 is not existent on the 19 pin JTAG SWD and Trace connector 8 TDI Output JTAG data input of target CPU It is recommended that this pin is pulled to a defined state on the target board Typically connected to TDI of the target CPU For CPUs which do not provide TDI SWD only devices this pin is not used J Link will ignore the s
119. C7060 ADuC7061 ADuC7062 ADuC7128 ADuC7129 ADuC7229x126 ADuCRFO2 ADuCRF101 9 1 1 ADuC7xxx 9 1 1 1 Software reset CHAPTER 9 Device specifics A special reset strategy has been implemented for Analog Devices ADUC7xxx MCUs This special reset strategy is a software reset Software reset means basically RESET pin is used to perform the reset the reset is initiated by writing special func tion registers via software The software reset for Analog Devices ADUC7xxxx executes the following sequence The CPU is halted A software reset sequence is downloaded to RAM A breakpoint at address 0 is set The software reset sequence is executed It is recommended to use this reset strategy This sequence performs a reset of CPU and peripherals and halts the CPU before executing instructions of the user program It is the recommended reset sequence for Analog Devices ADUC7xxx MCUs and works with these devices only This information is applicable to the following devices Analog ADuC7020x62 Analog ADuC7021x32 Analog ADuC7021x62 Analog ADuC7022x32 Analog ADuC7022x62 Analog ADuC7024x62 Analog ADuC7025x32 Analog ADuC7025x62 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 241 Analog ADuC7026x62 Analog ADuC7027x62 Analog ADuC7030 Analog ADuC7031 Analog ADuC7032 Analog ADuC7033 Analog ADuC7128 Analog ADuC7129 Analog ADuC7229x126 J Link J Trace UM08001 2004 2014 SEGGER Microcontr
120. CHA 8x85 205 telse TAB FLASH 206 Set the Uector Table Bae location at 0 08000000 207 NUIC SetUectorTable NUIC UectTab FLASH 8x05 NUIC PriorityGroupConfig NUIC PriorityGroup 45 7 SysTick end of count event each 1s with input clock equal to 9MHz CHCLK 8 defaul Seis En Si y interrupt SusTick ITConf ig ENABLE 5 SysTick CounterCnd SysTick Counter Enable 4 Buttons port init 4 GPIO enable clock and release Reset RCC_APB2PeriphResetCmd 2 GPIOR 1 RCC_APB2Periph_GPIOG DISABLE RCC_APB2PeriphClockCmd RCC_APB2Periph_GPIOA RCC_APB2Periph_GPIOG ENABLE GPIO InitStructure GPIO Pin GPIO InitStructure GPIO Mode GPIO Mode IN FLORTING GPIO InitStructure GPIO Speed GPIO Rene _S MHz GPIO_Init B1_PORT amp GPIO InitStructure GPIO InitStructure GPIO Pin B2 GPIO InitStructure GPIO Mode GPIO Mode IN FLORTING GPIO InitStructure GPIO Speed GPIO InitCB2 PORT amp GPIO InitStructure EXT CRT SECTIONO 7 port and ADC init 7 Enable ADC1 and GPIOC clock RCC_APB2PeriphResetCmd RCC_APB2Periph_ADC1 RCC_APB2Periph_GPIOC DISABLE RCC_APB2PeriphClockCmd lt RCC_APB2Periph_ADCi RCC_APB2Periph_GPIOC ENABLE 0800 BOLA SP SP 0x68 O800BFA2 B070 R4 R5 R6 PC DrawTable 0 08008 4 0x800BF28 98008 6 0800 RO RO 0x0 os BFAS PUSH R4 LR OSO0BFAA Boss SU
121. CPU When using SWD this pin is used as Serial Wire Output trace port Optional not required for SWD communica tion This pin normally pin 7 is not existent on the 19 pin JTAG SWD and Trace connector TDI Output JTAG data input of target CPU It is recommended that this pin is pulled to a defined state on the target board Typically connected to TDI of the target CPU For CPUs which do not provide TDI SWD only devices this pin is not used J Link will ignore the signal on this pin when using SWD NC NC Not connected inside J Link Leave open on target hard ware 10 nRESET I O Target CPU reset signal Typically connected to the RESET pin of the target CPU which is typically called nRST nRESET or RESET 11 5V Supply Output This pin can be used to supply power to the target hard ware For more information about how to enable disable the power supply please refer to Target power supply on page 286 12 TRACECLK Input Input trace clock Trace clock 1 2 CPU clock 13 5V Supply Output This pin can be used to supply power to the target hard ware For more information about how to enable disable the power supply please refer to Target power supply on page 286 14 TRACE DATA 0 Input Input Trace data pin O Table 10 9 19 pin JTAG SWD and Trace pinout J Link J Trace UM08001 2004 2014 SEGGER Microcontroll
122. DIFSAS BL debug ENTR CRT SECTION IK Init i OSODBFB4 F7FFFF 2 BL Clk Init NVIC SetvectorTable NVIC VectTab FLASH 0x0 08006 2100 R1 OSODBFBA 05 6000 MOVS RO 0 8000000 DSODBFBE 001 65 BL nvic_setvectortable Pi ir riori 0800 2 44 7040 MOV RO 0x300 0800 6_ FOOIFC41 BL Prioritysroupconfig Tick ITConf O800BFDO 2001 IMS O800BFD2 FOO1FB1A BL T sysTick_rrconti g 0800 06 2001 MOVS RO 0800 8 FOOIFAEB BL SytT ick countercmd APB2Peri PIOA RCCCAPB2Periph GPIOG DISABLE 0800 0 2100 wovs R1 0x0 OSODBFDE F44F7082 MOV RO 0 104 0800 2 F7FFFASO BL RCC_APB2PeriphResetcmd RCC APB2Periphclockcmd RCC_APB2Periph GPIOA RCC APB2Periph GPIOG ENABLE 0800 6 2101 wovs R1 0xl OSDDBFES F44F7082 MOV RO 0 104 0800 F7FFFA20 BL APB2PeriphClockcmd GPIO Initstructure GPIO Pin B1 MASK DSODBFFO F44F7080 MOV RO 0 100 OSDOBFF4 8 00000 STRH RO SP GPIO Initstructure s GPIO Mode IN FLOATING OSDOBFFS 2004 RO 0x4 08008 22200003 STRE RO SP 0x3 GPIO Initstructure GPIO speed GPIO Speed 50MHz 295 2004 2014 SEGGER Microcontroller GmbH amp Co KG 296 CHAPTER 11 Background information Embedded Workbench IDE SCB gt HFSR xFFFFFFFF3 SCB gt DFSR xFFFFFFFF Function Name Description Input NIC PriorityGroupConfig Configures t
123. Dynamic Linked Library DLL 314 E Embedded Trace Buffer ETB 297 314 Embedded Trace Macrocell ETM 293 314 EmbeddedICE 314 General Query Packets 84 H gt vache 314 pre 314 314 ICE Extension Unit 314 315 IEEE 11491 315 Image 315 In Circuit Emulator 315 Instruction Register 315 IR ore m RE ree EE EE 315 J JeFlash ARM ur e iE x Snes es 103 J Link J Trace UM08001 J Link Adapters x s RR ERA erue 288 Developer Pack DLL 116 Supported chips 188 189 202 203 J Link Commander 63 J Link GDB Server 66 BEBE 112 J Link STR9 Commander 113 J Link TCP IP Server 98 J Mem Memory Viewer 102 Joint Test Action Group JTAG 315 HN PL 290 TAP controler nee 291 JTAGLOad 111 L Little endian 315 Memory coherency 315 Memory management unit MMU 315 Memory Protection Unit MPU 315
124. E Flash download License found On Skip download on CRC match C Off Verify download Enabled 10272 bytes downloaded e Auto This is the default setting of J Link FlashDL usage If a license is found J Link FlashDL is enabled Otherwise J Link FlashDL will be disabled inter nally e On Enables the J Link FlashDL feature If no license has been found an error message appears e Off Disables the J Link FlashDL feature e Skip download on CRC match J Link checks the CRC of the flash content to determine if the current application has already been downloaded to the flash If a CRC match occurs the flash download is not necessary and skipped Only available if J Link FlashDL usage is configured as Auto or On e Verify download If this checkbox is enabled J Link verifies the flash content after the download Only available if J Link FlashDL usage is configured as Auto or On Section Flash breakpoints In this section settings for the use of the FlashBP feature and related settings can be configured When a license for FlashBP is found the color indicator is green and License found appears right to the FlashBP usage settings E Flash breakpoints Auto License found C n 7 Show info window during C Off program E nabled e Auto This is the default setting of FlashBP usage If a license has been found the FlashBP feature will be enabled Otherwi
125. ER Microcontroller GmbH amp Co KG 70 CHAPTER 3 J Link software and documentation package The screenshot below shows an debug session in IDE For download and more infor mation about emIDE please refer to http emide org File Edit View Search Project Build Debug Jlink Plugins Settings Help PRS OB XAA A 0 Bud targetes ip wow VP 5 Dl 10 include BSP h 11 0 00100228 ir 12 FSIS III III III IIR IIIS OE 0x0010022C sp sp 12 23 0500100230 0 0x00100234 r3 sp 4 14 ER 0x00100238 0x1000f8 BSP Init 15 static void Delay void 16 volatile int i 0x00100240 0 10014 lt BSP_SetLED gt 17 0x00100244 ro 1 0 00100248 0 10019 lt BSP_ToggleLED 1 i 1000 0x0010024C r3 2 4 19 while i 0x00100250 r3 r3 1 20 0x00100254 r3 sp 4 0x00100258 0 1001 lt 1 gt 050010025 05100244 lt 28 gt OI III III III III III ttt main ES Clint main void 4 volatile int cnt cnt 0 BSP_Init Initiali BSP SetLED 0 while 1 BSP ToggleLED cente _Delay 0 0 0x0 Filename Address Unitsize 8bit Goto Address 0 000000 5 aa 000000000 04 0 1f eS Bc 00 10 00 60 00 9f e5 OF 0 a0 ei xi 8c e0 ae Code C Tool C emiIDE V21VermVExempleWend oxoooo0010 10 f 26 ei 58 10 Sf es 58 20 9f
126. F105R8 3 STM32F105RB STM32F105RC 3 STM32F105V8 STM32F105VB STM32F105VC 3 STM32F107RB STM32F1N7RC To enable the J Link flash loader J Link J Trace at Project gt Options for Tar get gt Utilities has to be selected It is important that Update Target before Debug ging is unchecked since otherwise uVision tries to use its own flashloader Device Target Output Listing User C C Asm Linker Debug r Configure Flash Menu Command Use Target Driver for Flash Programming Cortex M R J LINK J Trace Settings Update Target before Debugging RET C Use Extemal Tool for Flash Programming Omed Mamets _ Run Independent Lose J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 193 Then J Link has to be selected as debugger To select J Link as debugger simply choose J Link J Trace from the list box which can be found at Project gt Options for Target gt Debug V Options for Target MCBSTM32E Flash Device Target Output Listing User Linker Debug Utiities Use Simulator Settings Use Cortex M R J LINK J Trace Settings Limit Speed to Real Time Load Application at Startup Run to main Load Application at Startup Runto main lnitialization File lnit
127. Flash Example The address 0x06000000 is a virtual address only The option bytes are remap from 0 06000000 to To program the option bytes 2 and 3 with the values and OxBB but leave the device unprotected your option byte sector at addr 0x06000000 should look like as follows Address 31 24 23 16 15 8 7 0 0x06000000 0x00 OxFF 5 5 0 06000004 0 44 OxBB 0x55 OxAA 0x06000008 0x00 OxFF 0x00 OxFF 0x0600000C 0x00 OxFF 0x00 OxFF Table 9 2 Option bytes programming example For a detailed description of each option byte please refer to 57 programming man ual PM0042 section Option byte description 9 16 2 3 Securing unsecuring the device The user area internal flash of the STM32 devices can be protected secured against read by untrusted code The J Flash software allows securing a STM32F10x device For more information about J Flash please refer to UM08003 J Flash User Guide In order to unsecure a read protected STM32F10x device SEGGER offers two software components J Flash J Link STM32 Commander command line utility For more information about J Flash please refer to UM08003 J Flash User Guide For more information about the J Link STM32 Commander please refer to J Link STM32 Unlock Command line tool on page 114 Note memory Unsecuring a secured device will cause a mass erase of the internal flash 9 16 2 4 Hardware watchdog The hardw
128. Flash TBC 4 0 080001 34 Unknown Any Flash TBC 5 0 08000150 Unknown Flash TBC 6 0080001 64 Unknown Flash TBC Watchpoints Handie Address Access 1 _0 8000000 0x08000120 0x00001000 Write 16 bit Vector catch EP Ready JLINKARM ReadMem Done 1 494 sec in 219 calls 2 Section Code Lists all breakpoints which are in the DLL internal breakpoint list are shown Handle Shows the handle of the breakpoint Address Shows the address where the breakpoint is set Mode Describes the breakpoint type ARM THUMB Permission Describes the breakpoint implementation flags Implementation Describes the breakpoint implementation type The break point types are RAM Flash Hard An additional TBC to be cleared or TBS to be set gives information about if the breakpoint is still written to the target or if it s just in the breakpoint list to be written cleared Note It is possible for the debugger to bypass the breakpoint functionality of the J Link software by writing to the debug registers directly This means for ARM7 ARM9 cores write accesses to the ICE registers for Cortex M3 devices write accesses to the memory mapped flash breakpoint registers and in general simple write accesses for software breakpoints if the program is located in RAM In these cases the J Link software can not determine the breakpoints set and the list is empty Section Data In this section all d
129. Flash of the target device is possible and the Unlimited Flash Breakpoints can be used It also comes with some functionality not directly implemented in the GDB These can be accessed via monitor commands sent directly via GDB too SEGGER J Link GDB Server V4 74 eJ File Help Localhost only GDB Connected to 127 0 0 1 initial SWD speed 4000kHz 7 Stay ontop Show log window J Link Connected i Current SWD speed 4000 kHz Generate logfile 3 Cache reads CPU STM32F41 715 Executing 1 330v B Little endian mo Init regs on start Log output Clear loa J Link connected Firmware J Link Pro V4 compiled Jul 16 2013 21 45 59 Feature s RDI FlashBP FlashDL JFlash GDB a Checking target voltage Listening on TCP IP port 2331 Connecting to target Connected to target Waiting for GDB connection Connected to 127 0 0 1 n Read 4 bytes address 0 00000000 Data 0x20001850 Starting target CPU 4 4 0 Bytes downloaded 1 JTAG device 2 GNU Project Debugger GDB is freely available debugger distributed under the terms of the GPL The latest Unix version of the GDB is freely available from the GNU committee under http www gnu org software gdb download J Link GDB Server is distributed free of charge 3 3 4 J Link GDB Server CL Windows Lunux J Link GDB Server CL is commandline only version of the GDB Server T
130. For simplicity the setup process of J Link Pro referred to as J Link is described in this section 4 3 1 Configuring J Link using J Link Configurator The J Link software and documentation package comes with a free GUI based utility called J Link Configurator which auto detects all J Links that are connected to the host PC via USB amp Ethernet The J Link Configurator allows the user to setup the IP interface of J Link For more information about how to use the J Link Configurator please refer to J Link Configurator on page 127 4 3 2 Configuring J Link using the webinterface All emulators of the J Link family which come with an Ethernet interface also come with a built in web server which provides a web interface for configuration This enables the user to configure J Link without additional tools just with a simple web browser The Home page of the web interface shows the serial number the current IP address and the MAC address of the J Link LJ i D J Link Pro Webserver SEGGER Microcontroller Home Home Network information Network configuration Emulator information System information Firmware build Dec 22 2008 09 24 26 Serial Number Emulator status About Network information Configuration type User assigned IP Address 192 168 90 11 16 Gateway 192 168 1 1 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 125 Network configuration page allows configuration o
131. G defines a TAP Test access port The TAP is a general purpose port that can provide access to many test support functions built into a component It is composed as a minimum of the three input connections TDI TCK TMS and one output con nection TDO An optional fourth input connection nTRST provides for asynchro nous initialization of the test logic PIN Type Explanation TCK Input uu test clock input TCK provides the clock for the test ogic TDI Input Serial test instructions and data are received by the test logic at test data input TDI TMS signal received at test mode select TMS is decoded by the TAP controller to control test operations Test data output TDO is the serial output for test TOS instructions and data from the test logic nTRST Input The optional test reset NTRST input provides for asyn optional chronous initialization of the TAP controller Table 11 1 Test access port 11 1 2 Data registers JTAG requires at least two data registers to be present the bypass and the bound ary scan register Other registers are allowed but are not obligatory Bypass data register A single bit register that passes information from TDI to TDO Boundary scan data register A test data register which allows the testing of board interconnections access to input and output of components when testing their system logic and so on 11 1 3 Instruction registe
132. HT AddAP 2 CORESIGHT APB AP Use second AP as AHB AP for target communication CORESIGHT IndexAHBAPTOUse 1 CORESIGHT IndexAHBAPToUse Table 5 10 Global DLL variables J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 172 5 Working with J Link and J Trace Variable Description R W Pre select an AP as an APB AP that J Link uses for debug communication Cortex A R Setting this variable is necessary for example when debugging multi core devices where multiple APB APs are present one for each device This function can only be used if a AP layout has been configured via CORESIGHT AddAP CORESIGHT_ Example W IndexAPBAPToUse CORESIGHT AddAP 0 CORESIGHT AHB AP CORESIGHT AddAP 1 CORESIGHT APB AD CORESIGHT AddAP 2 CORESIGHT APB AD Use third AP as APB AP for target communication CORESIGHT IndexAPBAPTOUse 2 Used to determine what reset type is currently selected by the debugger This is useful if the script has to behave differently if a specific reset type is selected by the debugger and the script file has a ResetTarget function which over MAIN ResetType rides the J Link reset strategies R Example if MAIN ResetType 2 22 41 else seed Used to check if this is the first time we run ning into InitTarget Useful if some init steps
133. IC to the mictor connector to within approximately 0 5 inches 12 5mm of each other Any greater differences directly impact the setup and hold time requirements 12 1 3 Minimizing Crosstalk Normal high speed design rules must be observed For example do not run dynamic signals parallel to each other for any significant distance keep them spaced well apart and use a ground plane and so forth Particular attention must be paid to the TRACECLK signal If in any doubt place grounds or static signals between the TRACECLK and any other dynamic signals 12 1 4 Using impedance matching and termination Termination is almost certainly necessary but there are some circumstances where it is not required The decision is related to track length between the ASIC and the JTAG Trace connector see Terminating the trace signal on page 305 for further ref erence J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 305 12 2 Terminating the trace signal To terminate the trace signal you can choose between three termination options e Matched impedance e Series source termination e DC parallel termination Matched impedance Where available the best termination scheme is to have the ASIC manufacturer match the output impedance of the driver to the impedance of the PCB track on your board This produces the best possible signal Series source termination This method requires a resistor fitted in series wi
134. Introduction The J Link DLL supports a feature called flash breakpoints which allows the user to set an unlimited number of breakpoints in flash memory rather than only being able to use the hardware breakpoints of the device Usually when using hardware break points only a maximum of 2 ARM 7 9 11 to 8 Cortex A R breakpoints can be set The flash memory can be the internal flash memory of a supported microcontroller or external CFI compliant flash memory In the following sections the setup for different debuggers to use the flash breakpoints feature is explained How do breakpoints work There are basically 2 types of breakpoints in a computer system hardware break points and software breakpoints Hardware breakpoints require a dedicate hardware unit for every breakpoint In other words the hardware dictates how many hardware breakpoints can be set simultaneously ARM 7 9 cores have 2 breakpoint units called watchpoint units in ARM s documentation allowing 2 hardware breakpoints to be set Hardware breakpoints do not require modification of the program code Software breakpoints are different The debugger modifies the program and replaces the breakpointed instruction with a special value Additional software breakpoints do not require additional hardware units in the processor since simply more instructions are replaced This is a standard procedure that most debuggers are capable of however this usually requires the program to be l
135. J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 14 SEGGER Microcontroller GmbH amp KG develops and distributes software development tools and ANSI C software components middleware for embedded sys tems in several industries such as telecom medical technology consumer electronics automotive industry 7 SEGG ER and industrial automation SEGGER s intention is to cut software development time for embedded applications by offering compact flexible and easy to use middleware allowing developers to concentrate on their application Our most popular products are emWin a universal graphic software package for embed ded applications and embOS a small yet efficient real time kernel emWin written entirely in ANSI C can easily be used on any CPU and most any display It is comple mented by the available PC tools Bitmap Converter Font Converter Simulator and Viewer embOS supports most 8 16 32 bit CPUs Its small memory footprint makes it suitable for single chip applications Apart from its main focus on software tools SEGGER develops and produces programming tools for flash microcontrollers as well as J Link a JTAG emulator to assist in develop ment debugging and production which has rapidly become the industry standard debug probe for microcontrollers microprocessors Corporate Office http www segger com United States Office http www segger us com EMBEDDED SOFT
136. J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 94 CHAPTER 3 J Link software and documentation package 3 3 5 18 novd Description Do not explicitly verify downloaded data Note For the GUI version this setting is persistent for following uses of GDB Server until changed via command line option or the GUI Syntax vd 3 3 5 19 port Description Starts GDB Server listening on a specified port This option overrides the default lis tening port of the GDB Server The default port is 2331 Note Using multiple instances of GDB Server setting custom values for this option is necessary Syntax port Port Example jlinkgdbserver port 2345 3 3 5 20 scriptfile Description Passes the path of a J Link script file to the GDB Server This scriptfile is executed before the GDB Server starts the debugging identifying communication with the tar get J Link scriptfiles are mainly used to connect to targets which need a special con nection sequence before communication with the core is possible For more information about J Link script files please refer to J Link script files on page 165 Syntax scriptfile lt ScriptFilePath gt Example scriptfile C My Projects Default JLinkScript 3 3 5 21 select Description Specifies the host interface to be used to connect to J Link Currently USB and TCP IP are available Syntax select lt Interface gt lt SerialNo gt lt IPA
137. J Link J Trace User Guide Software Version V4 86 Manual Rev 2 Date June 6 2014 Document UM08001 SEGGER A product of SEGGER Microcontroller GmbH amp Co KG www segger com Disclaimer Specifications written in this document are believed to be accurate but are not guar anteed to be entirely free of error The information in this manual is subject to change for functional or performance improvements without notice Please make sure your manual is the latest edition While the information herein is assumed to be accurate SEGGER Microcontroller GmbH amp Co KG the manufacturer assumes no responsibility for any errors or omissions The manufacturer makes and you receive no warranties or conditions express implied statutory or in any communication with you The manufacturer specifically disclaims any implied warranty of merchantability or fitness for a particular purpose Copyright notice You may not extract portions of this manual or modify the PDF file in any way without the prior written permission of the manufacturer The software described in this doc ument is furnished under a license and may only be used or copied in accordance with the terms of such a license 2014 SEGGER Microcontroller GmbH amp Co KG Hilden Germany Trademarks Names mentioned in this manual may be trademarks of their respective companies Brand and product names are trademarks or registered tr
138. J Trace 5 8 1 4 Type 3 No reset No reset is performed Nothing happens 5 8 1 5 Type 4 Hardware halt with WP The hardware RESET pin is used to reset the CPU After reset release J Link continu ously tries to halt the CPU using a watchpoint This typically halts the CPU shortly after reset release the CPU can in most systems execute some instructions before it is halted The number of instructions executed depends primarily on the JTAG speed the higher the JTAG speed the faster the CPU can be halted Some CPUs can actually be halted before executing any instruction because the start of the CPU is delayed after reset release 5 8 1 6 Type 5 Hardware halt with DBGRQ The hardware RESET pin is used to reset the CPU After reset release J Link continu ously tries to halt the CPU using the DBGRQ This typically halts the CPU shortly after reset release the CPU can in most systems execute some instructions before it is halted The number of instructions executed depends primarily on the JTAG speed the higher the JTAG speed the faster the CPU can be halted Some CPUs can actually be halted before executing any instruction because the start of the CPU is delayed after reset release 5 8 1 7 Type 6 Software This reset strategy is only a software reset Software reset means basically no reset just changing the CPU registers such as PC and CPSR This reset strategy sets the CPU registers to their after Reset values 0
139. J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 81 3 3 3 25 sleep Syntax sleep lt Delay gt Description Sleeps for a given time where lt Delay gt is the time period in milliseconds to delay While sleeping any communication is blocked until the command returns after the given period Example gt monitor sleep 1000 lt Sleep 1000ms 3 3 3 26 speed Note Deprecated For setting the initial connection speed use command line option speed instead Syntax speed lt kHz gt auto adaptive Description Sets the JTAG speed of J Link J Trace Speed can be either fixed in kHz automatic recognition or adaptive In general Adaptive is recommended if the target has an RTCK signal which is connected to the corresponding RTCK pin of the device S cores only For detailed information about the different modes refer to JTAG Speed on page 144 The speed has to be set after selecting the interface to change it from its default value Example monitor speed auto Select auto target interface speed 8000 kHz monitor speed 4000 Target interface speed set to 4000 kHz monitor speed adaptive Select adaptive clocking instead of fixed JTAG speed 3 3 3 27 step Syntax step lt NumSteps gt or si NumSteps Description Performs one or more single instruction steps where lt NumSteps gt is the number of instruction steps to perform If NumSteps is not specified only
140. LL does not have API functions for flash programming However the functionality offered can be used to program flash In this case a flash loader is required The table below lists some of the included files and their respective pur pose The J Link SDK requires an additional license and is available upon request from www segger com J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 117 Chapter 4 Setup This chapter describes the setup procedure required in order to work with J Link J Trace Primarily this includes the installation of the J Link software and documenta tion package which also includes a kernel mode J Link USB driver in your host sys tem J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 118 CHAPTER 4 41 Installing the J Link software and documentation pack J Link is shipped with a bundle of applications corresponding manuals and some example projects and the kernel mode J Link USB driver Some of the applications require an additional license free trial licenses are available upon request from www segger com Refer to chapter J Link software and documentation package on page 61 for an over view about the J Link software and documentation pack 4 1 1 Setup procedure To install the J Link software and documentation pack follow this procedure Note We recommend to check if a newer version of the J Link software and doc umen
141. Link If you are selling evaluation boards J Link Lite ARM is an inexpensive emulator solution for you Your customer receives a widely acknowledged JTAG emulator which allows him to start right away with his development Limitations JTAG speed is limited to 4 MHz Licenses No licenses are included All licenses can be added Note J Link Lite ARM is only delivered and supported as part of Starter Kits It is not sold to end customer and not guaranteed to work with custom hardware J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 59 2 6 OBs J Link OBs J Link On Board are single chip versions of J Link which are used on var ious evalboards It is legal to use J Link software with these boards J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 60 CHAPTER 2 Licensing 2 7 Clones Clones are copies of SEGGER products which use the copyrighted SEGGER Firmware without a license It is strictly prohibited to use SEGGER J Link software with illegal clones of SEGGER products Manufacturing and selling these clones is an illegal act for various reasons amongst them trademark copyright and unfair business practise issues The use of illegal J Link clones with this software is a violation of US European and other international laws and is prohibited If you are in doubt if your unit may be legally used with SEGGER J Link software please get i
142. Link DLL also allows programming of CFI compliant external NOR flash memory The flash down load feature of the J Link DLL does not require an extra license and can be used free of charge Why should I use the J Link flash download feature Being able to download code directly into flash from the debugger or integrated IDE significantly shortens the turn around times when testing software The flash down load feature of J Link is very efficient and allows fast flash programming For exam ple if a debugger splits the download image into several pieces the flash download software will collect the individual parts and perform the actual flash programming right before program execution This avoids repeated flash programming Once the setup of flash download is completed Moreover the J Link flash loaders make flash behave as RAM This means that the debugger only needs to select the correct device which enables the J Link DLL to automatically activate the correct flash loader if the debugger writes to a specific memory address This also makes it very easy for debugger vendors to make use of the flash download feature because almost no extra work is necessary on the debugger side since the debugger has not to differ between memory writes to RAM and memory writes to flash J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 189 6 2 Licensing No extra license required The flash download feature can be used fre
143. M DS 5 J Link supports ARM DS 5 Development via the RDDI protocol For commerically using J Link via RDDI in ARM DS 5 an RDI RDDI license is required J Link models which come with an RDI license can also be used via RDDI RDDI can be evaluated free of charge In order to use J Link in ARM DS 5 Development Studio the RDDI DLL in DS 5 needs to be replaced by the SEGGER version of this DLL The SEGGER version of the RDDI still allows using ARM s DSTREAM in DS 5 After installing the J Link software and documentation package the J Link DLL Updater is started which allows easily updat ing the RDDI DLL in DS 5 An backup of the original DLL is made automatically 4 8 1 Replacing the RDDI DLL manually If J Link DLL Updater is unable to find a DS 5 installation and does not list it for updating the RDDI DLL can always be replaced manually For more information about how to manually update the RDDI DLL please refer to SJLINK INST DIRS NMRDDIMManuallInstallation txt 4 8 2 Using J Link in DS 5 Development Studio Please follow the following steps in order to use J Link in DS 5 after replacing the RDDI DLL accordingly Connect J Link and target Open ARM DS 5 Open DS 5 Project for target Open Debug Configurations Select DS 5 Debugger on the left side Press New button In the Connection tab select The target from the device database Bare Metal Debug Debug via DSTREAM RVI Click on the Browse button right to the Text b
144. M32F103ZE device speed 1000 exec setcfiflash 0x64000000 Ox64FFFFFF exec setworkram 0x20000000 0x2000FFFF w4 0x40021014 0x00000114 RCC AHBENR FSMC clock enable w4 0x40021018 0x000001FD GPIOD G clock enable w4 0x40011400 OxB4BB44BB GPIOD low config NOE NWE gt Output NWAIT gt Input w4 0x40011404 OxBBBBBBBB GPIOD high config A16 A18 w4 0x40011800 OxBBBBBBBB GPIOE low config A19 A23 w4 0x40011804 OxBBBBBBBB GPIOE high config D5 D12 w4 0x40011C00 0 44 GPIOF low config 0 5 w4 0x40011C04 OxBBBB4444 GPIOF high config A6 A9 w4 0x40012000 0 44 GPIOG low config A10 A15 w4 0x40012004 0x444B4BB4 GPIOG high config NE2 gt output w4 0 0000008 0x00001059 CS control reg 2 16 bit write enable Type NOR flash w4 0 000000 0x10000505 CS2 timing reg read access w4 0 000010 0x10000505 CS2 timing reg write access speed 4000 mem 0x64000000 100 loadbin C STMB672_STM32F103ZE_TestBlinky bin 0x64000000 mem 0x64000000 100 6 5 3 1 Converting non bin files As previously mentioned J Link Commander supports programming of bin files into flash memory If the data file to be programmed is in non bin format hex mot srec the file needs to be converted into binary first There are various free soft J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 199 ware utilities available
145. Memory32 0x00008000 OxFFFFFD44 Memory Disable Watchdog 20000 iteMemory32 0x00000601 0xFFFFFC20 Memory PLL leep 20000 iteMemory32 0x10191c05 0xFFFFFC2C Memory PLL 20000 iteMemory32 0x00000007 0xFFFFFC30 Memory PLL 20000 iteMemory32 0x002 0100 0xFFFFFF60 Memory Set 1 wait state for Sleep 20000 flash 2 cycles emulatorSpeed 12000000 Use full JTAG speed Kt K H EAER N H M HO OHO RRR RRR RK RR KKK Sk RK KR KKK RR KR KK KKK ck ckckckckckckckckchckckckc k kckchckckckckckck kk kkk kkk kck ck kk execUserReset execUserReset message execUserReset _Init RK kk k KK RK RE KK KERR ck ckckckckckckckckckckckckckckckckckckchckckckckckckckckckckckckck kk kkk kkk kkk k k execUserPreload execUserPreload message execUserPreload _Init J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 245 RDI Sample SetJUTAGSpeed 30 Set JTAG speed to 30 kHz Reset 0 0 Write32 0xFFFFFD00 0xA5000004 Perform peripheral reset Write32 0xFFFFFDA44 0x00008000 Disable watchdog Write32 0xFFFFFC20 0x00000601 Set PLL Delay 200 Write32 0xFFFFFC2C 0x00191C05 Set PLL and divider Delay 200 Write32 0xFFFFFC30 0x00000007 Select master clock and processor clock Write32 0xFFFFFF60 0x00320300 Set flash wait st
146. Microcontroller GmbH amp Co KG 158 5 Working with J Link and J Trace 5 7 1 7 SWV In this section SWV information are shown 15 J Link ARM e Status Shows the encoding and the baudrate of the SWV data received by the target Manchester UART currently J Link only supports UART encoding e Bytes in buffer Shows how many bytes are in the DLL SWV data buffer e Bytes transferred Shows how many bytes have been transferred via SWV since the debug session has been started e Refresh counter Shows how often the SWV information in this section has been updated since the debug session has been started e Host buffer Shows the reserved buffer size for SWV data on the host side e Emulator buffer Shows the reserved buffer size for SWV data on the emulator side J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 159 5 8 Reset strategies J Link J Trace supports different reset strategies This is necessary because there is no single way of resetting and halting an CPU core before it starts to execute instruc tions For example reset strategies which use the reset pin can not succeed on tar gets where the reset pin of the CPU is not connected to the reset pin of the JTAG connector Reset strategy O is always the recommended one because it has been adapted to work on every target even if the reset pin Pin 15 is not connected What is the problem if the core executes some instru
147. NSEGGERNJLinkARM V350gNJLinkRDI dll RDI Target List Name Version Description _ Remote A v1 2 Angel debug protocol serial port Ex Multi ICE v2 2 5 ARM JTAG debug interface parallel port 4RMulator v1 4 ARM instruction set simulator Bonnae Duplicate M 5 After adding the DLL an additional Dialog opens and asks for description These values are voluntary if you do not want change them just click OK Use the fol lowing values and click OK Short Name JLinkRDI Description J Link RDI Interface Create New RDI Target JLinkRDI J Link ARM ADI Interface __ cancel 6 Back the RDI Target List Dialog select JLink RDI and click Configure For more information about the generic setup of J Link RDI please refer to Configu J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 218 8 RDI ration on page 226 RDI Target List Name Version Description JLinkADI J Link ARM RDI Interface Remote A v1 2 Angel debug protocol serial port Ex Multi ICE v2 25 ARM JTAG debug interface parallel port ARMulator 1 4 ARM instruction set simulator 7 Click the OK button in the configuration dialog Now close the RDI Target List dialog Make sure your target hardware is already connected to J Link 8 In the Connection control dialog expand the JLink ARM RDI Interface and select the
148. OM FCCOB5 0x00 FlexNVM partition code 256 KB data flash FSTAT 0x80 Start command execution while FSTAT amp 0x80 0 Wait until flash controller has finished J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 252 9 7 J Link has been tested with the following Fujitsu devices Currently there are no specifics for these devices Fujitsu MB9AF102N MB9AF102R MB9AF104N MB9AF104R MB9BF104N MB9BF104R MB9BF105N MB9BF105R MB9BF106N MB9BF106R MB9BF304N MB9BF304R MB9BF305N MB9BF305R MB9BF306N MB9BF306R MB9BF404N MB9BF404R MB9BF405N MB9BF405R MB9BF406N MB9BF406R MB9BF504N MB9BF504R MB9BF505N MB9BF505R MB9BF506N MB9BF506R J Link J Trace UM08001 CHAPTER 9 Device specifics 2004 2014 SEGGER Microcontroller GmbH amp Co KG 253 9 8 Itron J Link has been tested with the following Itron devices e TRIFECTA Currently there are no specifics for these devices J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 254 9 9 Infineon CHAPTER 9 Device specifics J Link has been tested with the following Infineon devices UMF1110 UMF1120 UMF5110 UMF5120 XMC1100 TO16F00xx XMC1100 TO38F00xx XMC1100 TO38FOxxx 1201 028 XMC1201 TO38FOxxx 1202 016 00 1202 028 00 1202 038 00 1203 016 0 XMC1301 TO16F00xx XMC1302 T038X0xxx XMC4100 128 XMC41
149. R J Link Commander 03 86 for help Compiled Jun 27 2008 19 42 43 ersion 03 86 compiled Jun 27 2008 19 42 28 J Link ARM 06 compiled Jun 27 2008 18 35 51 00 IRPrint x 1 Total IRLen 4 ce 0 Found ARM with core Id x3F F F F lt ARM gt J Link 5 1 3 Problems If you experience problems with any of the steps described above read the chapter Support and FAQs on page 307 for troubleshooting tips If you still do not find appro priate help there and your J Link J Trace is an original SEGGER product you can contact SEGGER support via e mail Provide the necessary information about your target processor board etc and we will try to solve your problem A checklist of the required information together with the contact information can be found in chapter Support and FAQs on page 307 as well J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 137 5 2 Indicators J Link uses indicators LEDs to give the user some information about the current status of the connected J Link All J Links feature the main indicator Some newer J Links such as the J Link Pro Ultra come with additional input output Indicators In the following the meaning of these indicators will be explained 5 2 4 Main indicator For J Links up to V7 the main indicator is single color Green J Link V8 comes with a bi color indicator Green amp Red LED which can show multiple col
150. RM Rev 5 Updating firmware Replacing firmware Firmware update successful 5 Waiting for new firmware to boot DLL version U2 70a Firmuare 05 00 Speed set to 30 kHz J Link In the screenshot for help compiled Oct 25 2005 14 02 40 J Link compiled Oct 26 2005 14 41 31 ARM Rev 5 e The red box identifies the new firmware e The green box identifies the old firmware which has been replaced 11 5 2 Invalidating the firmware Downdating J Link J Trace JLinkARM dll using older versions of the JLinkARM dll Note risk Note is not performed automatically through an old J Link J Trace will continue using its current newer firmware when Downdating J Link J Trace is not recommended you do it at your own Note also the firmware embedded in older versions of JLinkARM dll might not execute properly with newer hardware versions To downdate J Link J Trace you need to invalidate the current J Link J Trace firm ware using the command exec InvalidateFW 5 JLink exe ic xi SEGGER J Link Commander U2 74 61 Compiled 16 17 23 on Nov 25 2005 DLL version U2 74b Firmware Hardware S N UTarget 0 0000 Speed set to 30 kHz J Link gt exec invalidatefw Info Updating firmware US 66 Info Replacing firmware Info Firmware update successful Info Waiting for new firmware to boot J Link for help compiled Nov 25 2005 16 17 13 J Lin
151. Ri RO 0xC 1 003095 003413 0x08000886 POP R4 PC SysTick setReload 900000 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 11 2 3 2 Code coverage Source code tracing 2 IAR Embedded Workbench IDE 200 system Clk_InitO 47 NUIC init zu ifndef FLASH Set the Vector Table base location 0 20000000 NUIC SetUectorTable NUIC UectTab RAM 8x85 205 else UECT TRB FLASH 2806 2807 Set the Vector Table base location at 0 08000000 x mS SetUectorTable NUIC UectTab FLASH 8x85 tend NUIC PrioricyGroupConFig NUIC Priority roup 7 Z4 SysTick end of count event each 1s with input clock equal to 9MHz HCLK 8 defaul T ITConf ig ENABLED SysTick_CounterCmd SysTick_Counter_Enable gt 7 Buttons rt init 44 GPIO enable clock and release Reset RCC_APB2PeriphResetCmd RCC_APB2Periph_GPIOA i RCC_APB2Periph_GPIOG DISABLE RCC_APB2PeriphClockCmd RCC_APB2Periph_GPIOA i RCC_APB2Periph_GPIOG ENABLE GPIO InitStructure GPIO Pin MASK GPIO InitStructure GPIO Mode GPIO_Mode_IN_FLOATING GPIO InitStructure GPIO Speed GPIO Speed 5UMHz GPIO Init Bi PORT amp GPIO_InitStructure gt GPIO InitStructure GPIO Pin B2 MASK GPIO InitStructure GPIO Mode GPIO Mode IN FLORTING GPIO InitStructure GPIO Speed GPIO Speed 5UMHz GPIO Init B2 PORT amp GPIO_InitStructure gt EX
152. SDDDSBA LOR RO PC 0x10 003069 003387 oxosoonsec ANDS RO RO RS 003070 003388 0 080008 ORRS RO RO R4 003071 003389 0x080008C0 LOR R1 0 10 003072 003390 oxosoopscz LOR R1 R1 003073 003391 0x0800D8C4 STR RO R1 0x8 003074 003392 oxosoonsce RO R4 R5 PC NVIC PriorityGroupconfig NVIC PriorityGroup 4 003075 003393 DX0S0DBFC2 RO 0 300 003076 003394 0x0800BFC6 BL NVIC PriorityGroupconfig void NVIC PriorityGroupconfig us2 NVIC_PriorityGroup t NVIC_PriorityGroupcontig 003077 003078 003395 003396 0 0800084 0 0800084 PUSH wovs R4 R4 LR RO assert param IS NVIC PRIORITY GROUP NVIC PriorityGroup 003079 003397 0 08000850 R4 0x700 003080 003398 008000854 003081 003399 008000856 R4 0 600 003082 003400 0x0800D85A 003083 003401 Ox0800D85C R4 0 500 003084 003402 008000860 003085 003403 008000862 0 400 003086 003404 0 08000866 003087 003405 0 08000868 R4 0x300 003088 003406 0x0800D86C EN OU On Di 003089 003407 0 0800086 NVIC PriorityGroupconfig 2 executed executed executed executed executed SCB AIRCR AIRCR VECTKEY MASK NVIC_PriorityGroup NVIC PriorityGroupconfig 2 003090 003408 0x0800D87A LDR W RO PC 58 003091 003409 0x0800087E LOR 003092 003410 0x08000880 LOR R1 PC 0x4 003093 003411 0 08000882 R1 R1 R4 003094 003412 0 08000884 SR
153. SEGGER Microcontroller GmbH amp Co KG www segger com Solutions for real time microcontroller applications Please enter the target CPU frequency or press lt enter gt to select device for automatic CPU frequency detection gt 72000000 ng debug initializ sfully Target CPU is running 72000 kHz Receiving SVO 6000 kHz imulus 3 8 Using the syntax given below List of available command line options you can directly start J Link SWO Viewer CI with parameters E Command Prompt C Program Files 86 SEGGERULInkARM V478jULinkSWOViewerCL exe device stm32f103zg C gt C Program Files x86 gt SEGGER JLinkARM_U478 j JLinkSWOUiewerCL exe device stm32f183zg SEGGER J Link SWO Viewer i Nov 22 2013 20 09 16 SEGGER Microcontroller GmbH amp Co KG www segger com Solutions for real time microcontroller applications Fully CPU is running 72615 kHz SWO data 6000 kHz stimulus port s gt J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 105 3 7 1 Usage J Link SWO Viewer is available via the start menu It asks for a device name or CPU clock speed at startup to be able to calculate the correct SWO speed or to connect to a running J Link GDB Server SEGGER J Link SWO Viewer V4 78j Config Please enter the target CPU frequency or select a device for automatic CPU frequency detection Device STM32F1032G Select CPU frequenc
154. Server Refer to http www eclipse org for detailed information about Eclipse Note We only support problems directly related to the GDB Server Problems and questions related to your remaining toolchain have to be solved on your own J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 72 CHAPTER 3 J Link software and documentation package 3 3 3 Supported remote monitor commands J Link GDB Server comes with some functionality which are not part of the standard GDB These functions can be called either via a gdbinit file passed to GDB Server or via monitor commands passed directly to GDB forwarding them to GDB Server To indicate to GDB to forward the command to GDB Server monitor has to be prepended to the call For example a reset can be triggered in the gdbinit file with reset or via GDB with monitor reset Following remote commands are available Remote command Explanation clrbp Removes an instruction breakpoint epis Reads or writes from to cp15 register device Select the specified target device ETN Do not check if an abort occurred after memory read ARM7 9 only oe Check if an abort occurred after memory read ARM7 9 only flash breakpoints Enables Disables flash breakpoints getargs Get the arguments for the application go Starts the target CPU halt Halts the target CPU jtagconf Confi
155. Specifications The following table gives an overview about the specifications general mechanical electrical for J Link Lite ARM All values are valid for J Link hardware version 8 General For a complete list of all operating sys Supported OS tems which are supported please refer to Supported OS on page 23 Electromagnetic compatibility EMC EN 55022 EN 55024 Operating temperature 5 C 60 Storage temperature 209C 65 C Relative humidity non condensing Max 90 rH Size without cables 28mm x 26mm x 7mm Weight without cables 6g Mechanical USB interface USB 2 0 full speed JTAG 20 pin Target interface 14 pin available JTAG SWD Interface Electrical Table 1 3 J Link Lite specifications J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 32 CHAPTER 1 Introduction Power supply USB powered Max 50mA Target Supply current Target interface voltage Vir 3 3V Target supply voltage 4 5V if powered with 5V on USB Target supply current Max 300 LOW level input voltage Max 40 of Vir HIGH level input voltage Min 60 of JTAG SWD Interface Timing Data input rise time T qi Max 20ns Data input fall time T qj Max 20ns Data output rise time Trao Max 10ns Data output fall time Max 10ns Clock rise t
156. Syntax qSeggerSTRACE config ConfigString Parameter ConfigString String containing the configuration data separating settings by Description Configures STRACE for usage Configuration for example includes specification of the trace port width to be used for tracing 1 bit 2 bit 4 bit default Port Width Var Note For more information please refer to UM08002 J Link SDK user guide chapter STRACE Response lt ReturnValue gt ReturnValue is a 4 Byte signed integer gt 0 lt 0 Error Note ReturnValue is hex encoded Return value 0 is 00000000 return value 1 is FFFFFFFF 3 3 4 2 qSeggerSTRACE start Syntax qSeggerSTRACE start Description Starts capturing of STRACE data Note For more information please refer to 08002 J Link SDK user guide chapter STRACE Response lt ReturnValue gt ReturnValue is 4 Byte signed integer gt 0 lt 0 Error Note ReturnValue is hex encoded Return value 0 is 00000000 return value 1 is FFFFFFFF 3 3 4 3 qSeggerSTRACE stop Syntax qSeggerSTRACE stop Description Stops capturing of STRACE data Note For more information please refer to 08002 J Link SDK user guide chapter STRACE J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 86 CHAPTER 3 J Link software and documentation package Response lt ReturnValue gt ReturnValue is a 4 Byte signed integer gt 0
157. T CRT SECTIONCO 4 4 port and ADC init 44 Enable ADC1 and GPIOC clock M ccc fPB2Periph GPIOC DISABLE RCC_APB2PeriphClockCmd lt RCC_APB2Periph_ADC1 i RCC 2 GPIOC ENABLE 002403 002407 002442 002446 002481 002485 002520 002524 002559 002563 002598 002602 002637 002641 002676 002680 002715 002719 002754 002758 002793 002797 002832 002836 002871 002875 002883 002885 002906 002908 002923 002925 002942 002944 002959 002961 002985 002987 003009 003011 003031 003033 003053 003054 003057 OX0800B5A4 0x0800BEBE 002725 Ox0800BSA4 002760 002764 0x0800B5A4 002799 002803 Ox0800B5A4 002838 002842 Ox0800BSA4 002877 002881 Ox0800BSA4 002916 002920 Ox0800B5A4 002955 OxO800BEBE 002959 Ox0800BSA4 002994 002998 Ox0800BSA4 003033 0 0800 003037 0 0800 5 4 003072 003076 008008544 003111 0 0800 003115 Ox0800B5A4 003150 003154 0 0800 5 4 003189 003193 0 080083 8 003201 0 0800 amp 003203 O0x0800B3EC 003224 0 0800 00 003226 0x0800B37C 003241 0 0800 06 003243 0 08008334 003260 0 0800 003262 0x080082E4 003277 0 0800 4 003279 0 0800070 003303 0 0800 003305 0 08000746 003327 0 08
158. The sample below shows how to configure the FlexNVM area to be used as data flash out of the target application For J Flash there are also projects that are already preconfigured to configure the data flash size of Kinetis device The projects can be found at SJLINK_INST_DIR Samples JFlash ProjectFiles One of these sample projects is the MK40DX256xxx10 ConfigureDataFlash jflash For more information about how configuration of the data flash works please refer to the appropriate user manual of the device Configure FlexNVM area as data flash The follwing sample configures the data flash size of Kinetis device It is created for a MK40DX256xxx10 device The sequence is almost the same for all Kinetis devices only the lines which configure size of the data flash may be modified In this sample the data flash is set to max size EEPROM size is set to 0 bytes define FSTAT volatile unsigned char 0x40020000 0x00 define FCCOBO volatile unsigned char 0 40020000 0x07 define FCCOB1 volatile unsigned char 0x40020000 0x06 define FCCOB2 volatile unsigned char 0x40020000 0x05 define FCCOB3 volatile unsigned char 0x40020000 0x04 define FCCOB4 volatile unsigned char 0x40020000 Ox0B define FCCOB5 volatile unsigned char 0x40020000 0x0A define FCCOB6 volatile unsigned char 0x40020000 0x09 define 7 volatile u
159. The script file allows maxi mum flexibility so almost any target initialization which is necessary can be sup ported 5 10 1 Actions that be customized The script file support allows customizing of different actions performed by J Link If an generic implemented action is replaced by an action defined in a script file depends on if the corresponding function is present in the script file In the following all J Link actions which can be customized using a script file are listed and explained 5 10 1 1 ResetTarget Decsription If present it replaces the reset strategy performed by the DLL when issuing a reset Prototype void ResetTarget void 5 10 1 2 InitEMU Decsription If present it allows configuration of the emulator prior to starting target communica tion Currently this function is only used to configure if the target which is connected to J Link has an ETB or not For more information how to configure the existence of an ETB please refer to Global DLL variables on page 169 Prototype void InitEMU void 5 10 1 3 InitTarget Decsription If present it can replace the auto detection capability of J Link Some targets can not be auto detected by J Link since some special target initialization is necessary before communication with the core is possible Moreover J Link uses a TAP reset to get the JTAG IDs of the devices in the JTAG chain On some targets this disables access to the core Prototy
160. Trigger condition The ETM can be configured in software to store trace information only after a specific sequence of conditions When the trigger condition occurs the trace capture stops after a programmable period 11 2 2 Code tracing and data tracing Code trace Code tracing means that the processor outputs trace data which contain information about the instructions that have been executed at last Data trace Data tracing means that the processor outputs trace data about memory accesses read write access to which address and which data has been read stored In general J Trace supports data tracing but it depends on the debugger if this option is available or not Note that when using data trace the amount of trace data to be captured rises enormously 11 2 3 J Trace integration example IAR Embedded Work bench for ARM In the following a sample integration of J Trace and the trace functionality on the debugger side is shown The sample is based on IAR s Embedded Workbench for ARM integration of J Trace J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 294 CHAPTER 11 Background information 11 2 3 1 Code coverage Disassembly tracing IAR Embedded Workbench IDE 195 ttendif 196 19 ENTREGRTZBECTEONG 198 Init c system 199 1 InitO 27 NUIC init 203 wifaact FLASH Set the Vector Table base location at 0 20000000 204 NUIC SetUectorTable NUIC FE
161. UENCE EDU Ex EIE 136 5 1 2 Verifying target device connection 50 136 5 1 3 PFODIEM eie oe Re gis 136 5 2 519 eed 137 5 2 1 Main 137 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 5 2 2 InputindiCatOr ode re 139 5 2 3 Qutput indicator ev eraty wer ea paa e a e C E ied 139 5 3 Bapteshiua ie t t ww m 140 5 3 1 Multiple devices in the scan chain 66 nnns 140 5 3 2 Sample configuration dialog boxes sss meme 140 5 3 3 Determining values for scan chain 143 5 3 4 JTAG SPEEA EP 144 5 4 SWDiniterface oett eve ava On vi ae Rer e n 145 5 4 1 SWD Speedio TEE 145 5 4 2 on E 145 5 5 Multi core debugging reote eti erant eee cine e exe wea c DRE Ra 147 5 5 1 How multi core debugging 1 147 5 5 2 Using multi core debugging in detail 148 5 5 3 Things you should be aware nemen 149 5 6 Con
162. WARE Middleware emWin Graphics software and GUI emWin is designed to provide an effi cient processor and display control ler independent graphical user interface GUI for any application that operates with a graphical display Starterkits eval and trial versions are available embOS Real Time Operating System embOS is an RTOS designed to offer the benefits of a complete multitasking system for hard real time applications with minimal resources The profiling PC tool embOSView is included emFile File system emFile is an embedded file system with FAT12 FAT16 and FAT32 support emFile has been optimized for mini mum memory consumption in RAM and ROM while maintaining high speed Various Device drivers e g for NAND and NOR flashes SD MMC and Com pactFlash cards are available emUSB USB device stack A USB stack designed to work on any embedded system with a USB client controller Bulk communication and most standard device classes are sup ported ec J Link J Trace UM08001 SEGGER TOOLS Flasher Flash programmer Flash Programming tool primarily for microcon trollers J Link The de facto standard debug probe supporting multiple architectures and debug interfaces J Trace Debug probe with trace capabilities J Link with Trace memory supporting the ARM ETM Embedded Trace Macrocell J Link J Trace Related Software Add on software to be used with SEGGER s indus try st
163. aces and adapters Section Target board design updated Several corrections J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG Revision Date By Explanation Chapter Working with J Link Section J Link control panel updated Chapter Flash download and flash breakpoints 72 Section Supported devices updated Chapter Device specifics Section NXP updated Chapter Device specifics 5 030815 AG US Section NXP updated Chapter Introduction 70 090605 AG Section Common features of the J Link product family updated Chapter Working with J Link Section Reset strategies updated 69 090515 Section Indicators updated Chapter Flash download and flash breakpoints Section Supported devices updated Chapter J Link and J Trace related software Section J Link STM32 Commander added 98 939925 Ae Chapter Working with J Link Section Reset strategies updated Chapter Working with J Link n 929402 AG Section Reset strategies updated Chapter Background information Section Embedded Trace Macrocell ETM updated xi Ogee AS Chapter J Link and J Trace related software Section Dedicated flash programming utilities for J Link updated 65 090320 Several changes the manual structure Chapter Working with J Link 94 goodies AS Section Indicators added Chapte
164. act network admin tunnel server J Link Commander cannot connect to 1 Make sure Remote server is started correctly 2 Make sure the entered serial number is correct 3 Make sure port 19020 is not blocked by any firewall Contact network admin Table 3 11 To test whether a connection to the tunnel server can be established or not a network protocol analyzer like Wireshark can help The network transfer of a successful connection should look like 192 168 11 31 88 84 155 118 TCP 51439 gt j link Seq 1 1 192 168 11 31 88 84 155 118 TCP 51439 gt j link PSH ACK Seq 1 192 168 11 31 88 84 155 118 TCP 51439 gt j link PSH ACK Seq 5 88 84 155 118 192 168 11 31 TCP j link gt 51439 Seq 1 Ack 5 88 84 155 118 192 168 11 31 TCP j link gt 51439 ACK Seq 1 Ack 9 1 88 84 155 118 192 168 11 31 TCP j link gt 51439 PSH ACK Seq 1 A 192 168 11 31 88 84 155 118 TCP 51439 gt j link PSH ACK Seq 9 192 168 11 31 88 84 155 118 TCP 51439 gt j link PSH ACK Seq 13 88 84 155 118 192 168 11 31 j link gt 51439 ACK Seq 5 80 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 102 CHAPTER 3 J Link software and documentation package 3 5 Memory Viewer 1 displays memory contents of target systems and allows modifications of RAM and SFRs Special Function Registers while the target is running Thi
165. ademarks of their respec tive holders Contact address SEGGER Microcontroller GmbH amp Co KG In den Weiden 11 D 40721 Hilden Germany Tel 49 2103 2878 0 49 2103 2878 28 Email support segger com Internet http www segger com Revisions This manual describes the J Link and J Trace device For further information on topics or routines not yet specified please contact us Revision Date By Explanation Chapter Device specifics V4 86 Rev 2 140606 AG Section Silicon Labs EFM32 series devices added Chapter Related Software Section GDB Server Command line options halt nohalt added Description for GDB Server CL version added Chapter Flash download Section Mentor Sourcery CodeBench added Chapter Working with J Link Section Virtual COM Port VCOM improved V4 84 Rev 0 140321 EL Chapter Target interfaces and adapters Section Pinout for SWD Virtual COM Port VCOM added V4 86 Rev 1 140527 JL V4 86 Rev 0 140519 AG J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG Revision Date By Explanation V4 82 Rev 1 140228 EL Chapter Related Software Section Command line options Extended command line option speed Chapter J Link software and documentation package Section J Link STR91x Commander Added command line option parameter to specify a customized scan chain
166. ake sure that the JTAG chain has been config ured correctly by setting the appropriate global DLL variables For more information about the known global DLL variables please refer to Global DLL variables on page 169 Prototype api int JTAG SetDeviceId int DeviceIndex unsigned int Id 5 10 2 6 JTAG GetDeviceld Description Retrieves the JTAG Id of a specified device in the JTAG chain The index of the device depends on its position in the JTAG chain The device closest to TDO has index O Prototype api int JTAG GetDeviceId int DeviceIndex J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 167 5 10 2 7 JTAG_WritelR Description Writes a JTAG instruction Before calling this function please make sure that the JTAG chain has been config ured correctly by setting the appropriate global DLL variables For more information about the known global DLL variables please refer to Global DLL variables on page 169 Prototype 5 10 2 8 JTAG_StorelR Description Stores a JTAG instruction in the DLL JTAG buffer Before calling this function please make sure that the JTAG chain has been config ured correctly by setting the appropriate global DLL variables For more information about the known global DLL variables please refer to Global DLL variables on page 169 api int JTAG WriteIR unsigned int Cmd Prototype 5 10 2 9 WriteDR
167. aken as being an unsigned integer unless otherwise stated J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 318 14 Glossary J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 319 Chapter 15 Literature and references This chapter lists documents which we think may be useful to gain deeper under standing of technical details J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 320 15 Literature and references Reference Title Comments Embedded Trace Macrocell ETM Architecture Specification ARM 00143 This document defines the ETM standard including signal protocol and physical interface It is publicly available from ARM www arm com RealView ICE and RealView RVI Trace User Guide ARM DUI 0155C This document describes ARM s realview ice emulator and require ments on the target side It is publicly available from ARM www arm com Table 15 1 Literature and References J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 321 Index A Adaptive clocking 314 Application Program Interface 314 B Blg endiam oc eet ertet Re 314 Cache cleaning 314 CODFOCGOSSOFE aeter 314 D Dirty data 2c eret 314
168. alted before executing any instruction because the start of the CPLI is delayed after reset release If a pause has been specified J Link waits for the specified time before trying to halt the CPU This can be useful if a bootloader which resides in flash or ROM needs to be started after reset Cancel Apply Instruction set simulation This enables instruction set simulation which speeds up single stepping instructions especially when using flash breakpoints Reset strategy This defines the behavior how J Link RDI should handle resets called by software J Link supports different reset strategies This is necessary because there is no single way of resetting and halting an ARM core before it starts to execute instructions For more information about the different reset strategies which are supported by J Link and why different reset strategies are necessary please refer to Reset strategies on page 159 8 4 4 7 Log tab A log file can be generated for the J Link DLL and for the J Link RDI DLL This log files may be useful for debugging and evaluating They may help you to solve a prob lem yourself but is also needed by the support to help you with it Default path of the J Link log file c NJLinkARM log Default path of the J Link RDI log file c NJLinkRDI log J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 234 CHAPTER 8 Example of logfile content 060 028 00
169. am to flash Requires the add license FlashDL and to set an unlimited number of software breakpoints in flash Requires the add license FlashBP Connection to J Link USB Device 0 About of contig ma e E License Reset Config Cancel Apply Connection to J Link This setting allows the user to configure how the DLL should connect to the J Link Some J Link models also come with an Ethernet interface which allows to use an emulator remotely via TCP IP connection License J Link RDI License managment 1 The License button opens the J Link RDI License management dialog J Link RDI requires a valid license J Link RDI License management X Feature Serial number Expiration Add license Display serial number 2 Click the Add license button and enter your license Confirm your input by click J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 228 8 ing the OK button Add license 3 The J Link RDI license is now added J Link RDI License management LAO 8 4 4 2 Init tab Macro file RDI A macro file can be specified to load custom settings to configure J Link RDI with advanced commands for special chips or operations For example a macro file can be used to initialize a target to use the PLL before the target application is downloaded in o
170. ample code for terminal 2 4 107 3 8 SWO AtialyZei eee edt s tute ux edes Aces Uv cad ia xU NS 110 3 9 JTAGLoad Command line tool 1 nnn 111 3 10 J Link RDI Remote Debug 0 1 6 112 3 10 1 Flash download and flash breakpoints 6 112 3 11 Processor specific tools aa Ea E a 113 3 11 1 J Link STR91x Commander Command line tool 113 3 11 2 J Link STM32 Unlock Command line tool cem 114 3 12 J Link Software Developer Kit 5 4 6 6 nnns 116 c RM E LC 117 4 1 Installing the J Link software and documentation 118 4 1 1 Setup procedure eism cetero wes vao guy ve E DIA eX RR UR 118 4 2 Setting up the USB 1 121 4 2 1 Verifying correct driver installation 0 mene 121 4 2 2 Uninstalling the J Link USB 122 4 3 Setting up the IP interface cte eror pe D Ee XR Y ea ae tee 124 4 3 1 Configuring J Link using J Link
171. andard JTAG emulator this includes flash programming software and flash breakpoints 2004 2014 SEGGER Microcontroller GmbH amp Co KG Table of Contents bon Ato oe 21 1 1 Requiretments o eese esercita lem PD La 22 1 2 Supported OS s oes ved xu exer evertere ix 23 1 3 J Link 7 J2Trace models rene tee ve o C E E PU le C D e va e ED o 24 1 3 1 Model cormparisQn sies ester erre e v ERR E REN A EAA AUAA ARE 25 1 3 2 J LMK E M E 26 1 3 3 eve doa te A 29 1 3 4 30 1 3 5 Jsbink Bite Loses eo dere enters RR er EXER MEDNREERUK 31 1 3 6 JaLink Lite Cortex ARN IIR M E 32 1 3 7 RAGE ARM cos etse tte ob Ese eie o eden aedes end RUE E dt a 33 1 3 8 J Trace for Cortex Mi rirorio verte cates re Deed mee va e mee e bs o e c 36 1 3 9 Flasher ARMs E RUE A 38 1 3 10 J LINK I Mu E 39 1 4 Common features of the J Link product 4 6 40 1 5 Supported CPU Coresa oo ee oe We ea xx dn n ra ee o Pe e E 41 1 6 Built in intelligence for supported CPU cores 10 6 42 1 6
172. arators and to control the output logic levels to the target It is normally fed from Vdd of the target board and must not have a series resistor 2 Morgon NC This pin is not connected in J Link nected This pin is not used by J Link If the device may also be 3 Not Used NC accessed via JTAG this pin may be connected to nTRST otherwise leave open This pin is not used by J Link If the device may also be 5 Not used NC accessed via JTAG this pin may be connected to TDI other wise leave open Single bi directional data pin A pull up resistor is required SNBO Do ARM recommends 100 kOhms Clock signal to target CPU It is recommended that this pin is pulled to a defined state eu on the target board Typically connected to TCK of target CPU This pin is not used by J Link when operating in SWD mode 11 Not used NC If the device may also be accessed via JTAG this pin may be connected to RTCK otherwise leave open Serial Wire Output trace port Optional not required for Pre Input SWD communication Target CPU reset signal Typically connected to the RESET 15 RESET I O pin of the target CPU which is typically called nRST nRESET or RESET 17 Not used NC This pin is not connected in J Link This pin can be used to supply power to the target hard 5V Sup ware Older J Links may not be able to supply power on this 19 Output pin For more information about how to enable disable the ply power supply please ref
173. ard 6 Addr 008000266 Implementation Hard J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 204 CHAPTER 7 Flash breakpoints 7 3 Supported devices J Link supports flash breakpoints for a large number of microcontrollers You can always find the latest list of supported devices on our website http www segger com jlink supported devices html In general J Link be used with any ARM7 9 11 Cortex MO M1 M3 M4 and Cor tex A5 A8 R4 core even if it does not provide internal flash Furthermore flash breakpoints are also available for all CFI compliant external NOR flash devices J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 205 7 4 Setup amp compatibility with various debuggers 7 4 1 Setup In compatible debuggers flash breakpoints work if the J Link flash loader works and a license for flash breakpoints is present No additional setup is required The flash breakpoint feature is available for internal flashes and for external CFI flash For more information about how to setup various debuggers for flash download please refer to Setup for various debuggers internal flash on page 191 If flash break points are available can be verified using the J Link control panel x SEGGER J Link 4 35g beta Control panel Using fastest method E Programmed sectors fastest methoc far J verride memory map
174. are watchdog of a STM32F10x device can be enabled by programming the option bytes If the hardware watchdog is enabled the device is reset periodically if the watchdog timer is not refreshed and reaches If the hardware watchdog is enabled by an application which is located in flash and which does not refresh the watchdog timer the device can not be debugged anymore J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 267 Disabling the hardware watchdog In order to disable the hardware watchdog the option bytes have to be re pro grammed SEGGER offers a free command line tool which reprograms the option bytes in order to disable the hardware watchdog For more information about the STM32 commander please refer to J Link STM32 Unlock Command line tool on page 114 9 16 2 5 Debugging with software watchdog enabled If the device shall be debugged with one of the software watchdogs independed watchdog window watchdog enabled there is an additional init step necessary to make the watchdog counter stop when the CPU is halted by the debugger This is configured in the DBGMCU CR register The following sequence be used to enable debugging with software watchdogs enabled Configure both watchdog timers to be halted if the CPU is halted by the debugger volatile int 0 0042004 1 lt lt 8 1 lt lt 9 9 16 3 STM32F2xxx These device are Cortex M3 based All devi
175. arting GDB Server Syntax s singlerun 3 3 5 25 speed Description Starts GDB Server with a given initial speed Available parameters are adaptive auto or a freely selectable integer value in kHz It is recommended to use either a fixed speed or if it is available on the target adaptive speeds Note Using GDB Server CL this option is mandatory to correctly connect to the target and should be given before connection via GDB Syntax speed lt Speed_kHz gt J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 96 CHAPTER 3 J Link software and documentation package Example jlinkgdbserver speed 2000 3 3 5 26 stayontop Description Starts the GDB Server in topmost mode It will be placed above all non topmost win dows and maintains it position even when it is deactivated Note For the CL version this setting has no effect Note For the GUI version this setting is persistent for following uses of GDB Server until changed via command line option or the GUI Syntax stayontop 3 3 5 27 swoport Description Set up port on which GDB Server should listen for an incomming connection that reads the SWO data from GDB Server Default port is 2332 Note Using multiple instances of GDB Server setting custom values for this option is necessary Syntax SWOPort Port Example jlinkgdbserver SWOPort 2553 3 3 5 28 telnetport Description Set up port on wh
176. ata breakpoints which are listed in the DLL internal breakpoint list are shown Handle Shows the handle of the data breakpoint Address Shows the address where the data breakpoint is set AddrMask Specifies which bits of Address are disregarded during the compari son for a data breakpoint match A 1 in the mask means disregard this bit Data Shows on which data to be monitored at the address where the data breakpoint is set Data Mask Specifies which bits of Data are disregarded during the comparison for a data breakpoint match A 1 in the mask means disregard this bit Ctrl Specifies the access type of the data breakpoint read write CtriMask Specifies which bits of Ctrl are disregarded during the comparison for a data breakpoint match 5 7 1 4 Log In this section the log output of the DLL is shown The user can determine which function calls should be shown in the log window J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 157 Available function calls to log Register read write Memory read write set clear breakpoint step go halt is halted m 5 7 1 5 CPU Regs In this section the name and the value of the CPU registers are shown 13 J Link ARM 0 00100 8 0 00000000 5 7 1 6 Target Power In this section currently just the power consumption of the target hardware is shown 13 J Link ARM J Link J Trace 0 08001 2004 2014 SEGGER
177. ates SetJTAGSpeed 12000 9 2 2 AT91SAM9 9 2 2 1 JTAG settings We recommend using adaptive clocking This information is applicable to the following devices AT91RM9200 AT91SAM9260 AT91SAM9261 AT91SAM9262 AT91SAM9263 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 246 CHAPTER 9 Device specifics 9 3 DSPGroup J Link has been tested with the following DSPGroup devices e DA56KLF Currently there are no specifics for these devices J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 247 9 4 Ember For more information please refer to Silicon Labs on page 263 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 248 CHAPTER 9 Device specifics 9 5 Energy Micro For more information please refer to Silicon Labs on page 263 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 9 6 Freescale J Link has been tested with the following Freescale devices 9 6 1 9 6 1 1 MAC7101 MAC7106 MAC7111 MAC7112 MAC7116 MAC7121 MAC7122 MAC7126 MAC7131 MAC7136 MAC7141 MAC7142 MK10DN512 MK10DX128 MK10DX256 MK20DN512 MK20DX128 MK20DX256 MK30DN512 MK30DX128 MK30DX256 MK40N512 MK40X128 MK40X256 MK50DN512 MK50DX256 MK50DN512 MK50DX256 MK51DX256 MK51DN512 MK51DX256 MK51DN512 MK51DN256 MK51DN512 MK52DN512 MK53DN512 MK53DX256 MK60N256 MK60N512 MK60X256 Kinetis family
178. ating the J Link DLL in the IAR Embedded Workbench for ARM EWARM It s recommended to use the J Link DLL updater to update the J Link DLL in the IAR Embedded Workbench The IAR Embedded Workbench IDE is a high performance integrated development environment with an editor compiler linker debugger The compiler generates very efficient code and is widely used It comes with the J LinkARM d11 in the arm bin subdirectory of the installation directory To update this DLL you should backup your original DLL and then replace it with the new one Typically the DLL is located in c Program Files IAR Systems V Embedded Work bench 6 n arm bin After updating the DLL it is recommended to verify that the new DLL is loaded as described in Determining which DLL is used by a program on page 132 J Link DLL updater The J Link DLL updater is a tool which comes with the J Link software and allows the user to update the JLinkARM d11 in all installations of the IAR Embedded Work bench in a simple way The updater is automatically started after the installation of a J Link software version and asks for updating old DLLs used by IAR The J Link DLL updater can also be started manually Simply enable the checkbox left to the IAR installation which has been found Click Ok in order to update the JrinkARM dll used by the IAR installation 13 SEGGER J Link DLL Updater 3 86 x The following 3rd party applications using JLink amp RM dll have been fou
179. ax 3ns Clock rise time Max 3ns Clock fall time Max 3ns Data setup time Min 3ns Data hold time Ty Min 2ns Table 1 7 J Trace for Cortex M3 specifications 1 3 8 3 Download speed The following table lists performance values Kbytes s for writing to memory RAM Hardware Cortex M3 190 Kbytes s 12MHz SWD 760 KB s 12 MHz JTAG 190 Kbytes s 12MHz SWD 1440 KB s 25 MHz JTAG Table 1 8 Download speed differences between hardware revisions J Trace for Cortex M3 V2 J Trace for Cortex M V3 1 The actual speed depends on various factors such as JTAG clock speed host CPU core etc 1 3 8 4 Hardware versions Version 2 Obsolete Version 3 1 Identical to version 2 0 with the following exceptions e Hi Speed USB e Voltage range for trace signals extended to 1 2 3 3 V e Higher download speed J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 38 CHAPTER 1 1 39 Flasher ARM Flasher ARM is a programming tool for microcontrollers with on chip or external Flash memory and ARM designed for programming flash targets with the J Flash soft ware or stand alone In addition to that Flasher ARM has all of the J Link functionality For more information about Flasher ARM please refer to UM08007 Flasher ARM User s Guide 1 3 9 1 The following table gives an overview about the specifications general mechanical electrical for Flashe
180. bedded Trace Macrocell ETM No ETM requires another connection to the ARM chip and a CPU with built in ETM Most current ARM7 ARM9 chips do not have ETM built in J Link support of ETB Does J Link support the Embedded Trace Buffer ETB Yes J Link supports ETB Most current ARM7 ARM9 chips do not have ETB built in Hegisters on ARM 7 ARM 9 targets I m running J Link exe in parallel to my debugger on an ARM 7 target I can read memory okay but the processor registers are different Is this normal If memory on an ARM 7 9 target is read or written the processor registers are modified When memory read or write operations are performed J Link preserves the register values before they are modified The register values shown in the debugger s register window are the preserved ones If now a second instance in this case J Link exe reads the processor registers it reads the values from the hardware which are the modified ones This is why it shows different register val ues J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 313 Chapter 14 Glossary This chapter describes important terms used throughout this manual J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 314 CHAPTER 14 Glossary Adaptive clocking A technique in which a clock signal is sent out by J Link J Trace J Link J Trace waits for the returned clock before generating the nex
181. board of the host rather than having a screen and keyboard on the target system This is useful because development hardware often does not have all the input and output facilities of the final system Semihosting allows the host computer to provide these facilities Semihosting is also used for Disk I O and flash programming a flash loader uses semihosting to load the target program from disk Semihosting is implemented by a set of defined software interrupt SWI operations The application invokes the appropriate SWI and the debug agent then handles the SWI exception The debug agent provides the required communication with the host In many cases the semihosting SWI will be invoked by code within library functions Usage of semihosting The application can also invoke the semihosting SWI directly Refer to the C library descriptions in the ADS Compilers and Libraries Guide for more information on sup port for semihosting in the ARM C library Semihosting is not used by all tool chains most modern tool chains such as IAR use different mechanisms to achive the same goal Semihosting is used primarily by ARM s tool chain and debuggers such as AXD Since semihosting has been used primarily by ARM documents published by ARM are the best source of add information For further information on semihosting and the C libraries see the C and Libraries chapter in ADS Compilers and Libraries Guide Please see also the Writing Cod
182. breakpoint which means that the CPU can not be stopped after reset with the BP O reset strat egy 5 8 1 2 Type 1 Hardware halt with 0 The hardware reset pin is used to reset the CPU Before doing so the ICE breaker is programmed to halt program execution at address 0 effectively a breakpoint is set at address O If this strategy works the CPU is actually halted before executing a sin gle instruction This reset strategy does not work on all systems for two reasons e If nRESET and nTRST are coupled either on the board or the CPU itself reset clears the breakpoint which means the CPU is not stopped after reset e Some MCUs contain a bootloader program sometimes called kernel which needs to be executed to enable JTAG access 5 8 1 3 Type 2 Software for Analog Devices ADuC7xxx MCUs This reset strategy is a software strategy The CPU is halted and performs a sequence which causes a peripheral reset The following sequence is executed The CPU is halted A software reset sequence is downloaded to RAM A breakpoint at address 0 is set The software reset sequence is executed This sequence performs a reset of CPU and peripherals and halts the CPU before exe cuting instructions of the user program It is the recommended reset sequence for Analog Devices ADuC7xxx MCUs and works with these chips only J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 160 CHAPTER 5 Working with J Link and
183. cation installation path C Program Files SEG or choose an alternative location Confirm Setup will install J Link ARM V3 58c in the following folder To install into a different folder click Browse and select another folder You can choose not to install J Link ARM V3 58c by clicking Cancel to exit Setup Destination Folder CX SSEGGERWJLinkARM_V358e 4 The Choose options dialog is opened The Install J Link Serial Port Driver installs the driver for J Links with CDC functionality It is not preselected since J Links without CDC functionality do not need this driver The Create entry in start menu creates a entry in start menu It is preselected The Add shortcuts to desktop option can be selected in order to create a shortcut on the desktop Accept or deselect the options and confirm the selection with the Next gt button a Choose options Choose options for creating shortcuts Create entry in start menu IV Add shortcuts to desktop Cancel J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 120 4 Setup 5 The installation process will be started Installing 6 The J Link DLL Updater pops up which allows you to update the DLL of an installed IDE to the DLL verion which is included in the installer For furhter infor mation about the J Link DLL updater please refer to J Link DLL updater on page 131
184. ce 235 8 5 3 Implementation of semihosting in J Link 236 8 5 4 Semihosting with 236 8 5 5 Unexpected Unhandled 5 15 2 4 0 0 0 6 6 nnn n 237 9 Device Specifies seti ato ote Ie nicus Scc Lect 239 9 1 Analog DeviCes sk eee itt da an en ELE A 240 9 1 1 PD UG PK qe Er 240 9 2 ugue PEE 242 9 2 1 DUERRS AC 243 9 2 2 245 9 3 6 eles 246 9 4 EMDBDe r Rm 247 9 5 Energy MICI ciet erie ed e Y 248 9 6 I II 249 9 6 1 Kinetis Y eem wey vei exta cha eva tees 249 9 7 auci e 252 9 8 EE 253 9 9 iioi eee iret o pev terc f epe TRIER 254 9 10 Eurminaty MICEQuF ore terr ex e FX DIE pea ER er FEE KE E FR 255 9 10 1 Unlocking EM3SXxx devices essei rd ex ale de E RR AX E PR RYE YR RU ees 256 9 11 257 9 11 1 LPC ARMZ based
185. ces of this family are supported by J Link 9 16 3 1 ETM init The following sequence can be used to prepare STM32F2xxx devices for 4 bit ETM tracing int v Enable GPIOE clock volatile int 0x40023830 0x00000010 Assign trace pins to alternate function in order to make them usable as trace pins PE2 Trace clock TRACE_DO TRACE D1 PES TRACE D2 PE6 TRACE D3 volatile int 0x40021000 0 00002 0 DBGMCU_CR enable trace I O and configure pins for 4 bit trace volatile int 0 0042004 amp 7 lt lt 5 Preserve all bits except the trace pin configuration v 7 lt lt 5 Enable trace I O and configure pins for 4 bit trace volatile int 0xE0042004 9 16 3 2 Debugging with software watchdog enabled If the device shall be debugged with one of the software watchdogs independed watchdog window watchdog enabled there is an additional init step necessary to make the watchdog counter stop when the CPU is halted by the debugger This is configured in the DBGMCU_APB1_FZ register The following sequence can be used to enable debugging with software watchdogs enabled Configure both watchdog timers to be halted if the CPU is halted by the debugger volatile int 0xE0042008 1 lt lt 11 1 lt lt 12 J Link J Trace 0 08001 2004 2014
186. ch are supported please refer to Supported OS on page 23 Electromagnetic compatibility EMC EN 55022 EN 55024 Operating temperature 5 C 60 C Storage temperature 209 65 C Relative humidity non condensing Max 90 rH Mechanical Size without cables 100mm x 53mm x 27mm Weight without cables 70g Available interfaces USB interface USB 2 0 full speed JTAG 20 pin Target interface 14 pin adapter available JTAG SWD Interface Electrical USB powered Max 50mA Target Supply current Power supply Target interface voltage Vir 1 2V 5V Target supply voltage 4 5V if powered with 5V on USB Target supply current Max 300 Open drain Can be pulled low or Reset type deu j Reset low level output voltage VoL VoL lt 10 of Vir For the whole target voltage range 1 2V lt Vip lt 5V LOW level input voltage Vip lt 40 of Table 1 1 J Link specifications J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 27 HIGH level input voltage gt 60 of VIF For 1 8V lt Vir lt 3 6V LOW level output voltage VoL with a load of 10 kOhm VoL lt 10 of HIGH level output voltage Voy with load of 10 gt 90 of VIF For 3 6 lt Vir lt 5V LOW level output voltage with a load of 10 kOhm VoL lt 20 of Vig
187. ckModeAfterRead 0 the success of read operations cannot be verified anymore and possible data aborts are not recognized Typical applications This verification of the CPSR can cause problems with some CPUs e g if invalid CPSR values are returned Note that if this check is turned off SetCheckModeAfterRead 0 the success of read operations cannot be verified anymore and possible data aborts are not recognized Syntax SetCheckModeAfterRead 0 1 Example SetCheckModeAfterRead 0 5 11 1 10 SetResetPulseLen This command defines the length of the RESET pulse in milliseconds The default for the RESET pulse length is 20 milliseconds Syntax SetResetPulseLen value Example SetResetPulseLen 50 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 180 CHAPTER 5 Working with J Link and J Trace 5 11 1 11 SetResetType This command selects the reset startegy which shall be used by J Link to reset the device The value which is used for this command is analog to the reset type which shall be selected For a list of all reset types which are available please refer to Reset strategies on page 159 Please note that there different reset strategies for ARM 7 9 and Cortex M devices Syntax SetResetType lt value gt Example SetResetType 0 Selects reset strategy type 0 normal 5 11 1 12 SetRestartOnClose This command specifies whether the J Link restarts target
188. coherent if the value read by a data read or instruction fetch is the value that was most recently written to that location Obtaining memory coherency is difficult when there are multiple possible physical locations that are involved such as a system that has main memory a write buffer and a cache Memory management unit MMU Hardware that controls caches and access permissions to blocks of memory and translates virtual to physical addresses Memory Protection Unit MPU Hardware that controls access permissions to blocks of memory Unlike an MMU an MPU does not translate virtual addresses to physical addresses Multi ICE Multi processor EmbeddedICE interface ARM registered trademark RESET Abbreviation of System Reset The electronic signal which causes the target system other than the TAP controller to be reset This signal is also known as nSRST nSYSRST nRST or NRESET in some other manuals See also nTRST nTRST Abbreviation of TAP Reset The electronic signal that causes the target system TAP controller to be reset This signal is known as nICERST in some other manuals See also nSRST Open collector A signal that may be actively driven LOW by one or more drivers and is otherwise passively pulled HIGH Also known as a wired AND signal J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 316 CHAPTER 14 Glossary Processor Core The part of a microprocessor that reads in
189. connect J Link J Trace with the host system attach the USB cable 11 Enable power supply on the target 12 Start JLink exe 13 If JLink exe displays the J Link J Trace serial number and the target proces sor s core ID the J Link J Trace is working properly and cannot be the cause of your problem 14 If the problem persists and you own an original product not an OEM version see section Contacting support on page 311 13 2 2 Typical problem scenarios J Link J Trace LED is off Meaning The USB connection does not work Remedy Check the USB connection Try to re initialize J Link J Trace by disconnecting and reconnecting it Make sure that the connectors are firmly attached Check the cable connections on your J Link J Trace and the host computer If this does not solve the problem check if your cable is defect If the USB cable is ok try a different host computer J Link J Trace LED is flashing at a high frequency Meaning J Link J Trace could not be enumerated by the USB controller Most likely reasons a Another program is already using J Link J Trace b The J Link USB driver does not work correctly Remedy a Close all running applications and try to reinitialize J Link J Trace by disconnect ing and reconnecting it b If the LED blinks permanently check the correct installation of the J Link USB driver Deinstall and reinstall the driver as shown in chapter Setup on pag
190. covery Change Matches project settings Debugger Options J Link Startup 1 Memory Map Advanced Settings File workspace_loc STM32F4071E_Test Sample jinksettings x Browse Semihosting ot z Additional steps for enabling Flash Breakpoints feature By default Mentor Sourcery CodeBench does not allow the user to use the J Link unlimited number of breakpoints in flash feature since it only allows hardware breakpoints being set by default Enabling this feature requires an additional tweak in the J Link settings file 6 4 4 Make sure that all steps from Mentor Sourcery CodeBench on page 194 to enable flash download have been performed Make sure that Sourcery CodeBench uses a J Link DLL with version V4 85d or later If an earlier version is used this tweak does not work To update the DLL used by CodeBench copy the J Link DLL from the J Link installation directory to C Tool C Mentor CodeBench bin arm none eabi jlinkarm dll Open the settings file in a text editor and scroll to the BREAKPOINTS section Add the line ForcelmpTypeAny 1 Make sure that CodeBench uses the settings file J Link GDB Server The configuration for the J Link GDB Server is done by the gdbinit file The follow ing command has to be added to the gdbinit file to enable the J Link flash down load feature monitor flash device DeviceName J Link J Trace UM08001 2004 2014 SEGGER Microcontroller G
191. ctions after RESET The instructions which are executed can cause various problems Some cores can be completely confused which means they can not be switched into debug mode CPU can not be halted In other cases the CPU may already have initialized some hard ware components causing unexpected interrupts or worse the hardware may have been initialized with illegal values In some of these cases such as illegal PLL set tings the CPU may be operated beyond specification possibly locking the CPU 5 8 1 Strategies for ARM 7 9 devices 5 8 1 1 Type 0 Hardware halt after reset normal The hardware reset pin is used to reset the CPU After reset release J Link continu ously tries to halt the CPU This typically halts the CPU shortly after reset release the CPU can in most systems execute some instructions before it is halted The num ber of instructions executed depends primarily on the JTAG speed the higher the JTAG speed the faster the CPU can be halted Some CPUS can actually be halted before executing any instruction because the start of the CPU is delayed after reset release If a pause has been specified J Link waits for the specified time before trying to halt the CPU This can be useful if a bootloader which resides in flash or ROM needs to be started after reset This reset strategy is typically used if nRESET and nTRST are coupled If nRESET and nTRST are coupled either on the board or the CPU itself reset clears the
192. d and after a short period the J Link LED stops rapidly flashing and stays on permanently J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 121 4 22 Setting up the USB interface After installing the J Link software and documentation package it should not be nec essary to perform any additional setup sequences in order to configure the USB inter face of J Link 4 2 1 Verifying correct driver installation To verify the correct installation of the driver disconnect and reconnect J Link J Trace to the USB port During the enumeration process which takes about 2 seconds the LED on J Link J Trace is flashing After successful enumeration the LED stays on permanently Start the provided sample application JLink exe which should display the compila tion time of the J Link firmware the serial number a target voltage of 0 000V a complementary error message which says that the supply voltage is too low if no target is connected to J Link J Trace and the speed selection The screenshot below shows an example a C Program FilessSEGGER JLinkARM_ 386 JLink exe SEGGER J Link Commander 1 C for help gt Compiled Jun 27 2608 19 DLL version 03 86 compiled Jun 27 2008 19 42 28 i are J Link ARM U6 compiled Jun 27 2008 18 35 51 06 00 t 0 0000 JTAG speed 5 kHz J Link gt In addition you can verify the driver installation by consulting the Windows device manager If the driver is i
193. ddr gt Example jlinkgdbserver select usb 580011111 jlinkgdbserver select ip 192 168 1 10 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 95 Additional information For backward compatibility when USB is used as interface serial numbers from 0 3 are accepted as USB 0 3 to support the old method of connecting multiple J Links to a PC This method is no longer recommended to be used Please use the connect via emulator serial number method instead 3 3 5 22 settingsfile Description Select a J Link settings file to be used for the target device The settings fail can con tain all configurable options of the Settings tab in J Link Control panel Syntax SettingsFile lt PathToFile gt Example jlinkgdbserver SettingsFile C Temp GDB Server jlink 3 3 5 23 silent Description Starts the GDB Server in silent mode No log window messages will be shown Note For the GUI version this setting is persistent for following uses of GDB Server until changed via command line option or the GUI Syntax silent 3 3 5 24 singlerun Description Starts GDB Server in single run mode When active GDB Server will close when all client connections are closed In normal run mode GDB Server will stay open and wait for new connections When started in single run mode GDB Server will close immediately when connecting to the target fails Make sure it is powered and connected to J Link before st
194. e 117 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 310 13 J Link J Trace does not get any connection to the target Most likely reasons a The JTAG cable is defective b The target hardware is defective Remedy Follow the steps described in General procedure on page 309 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 311 13 3 Contacting support Before contacting support make sure you tried to solve your problem by following the steps outlined in section General procedure on page 309 You may also try your J Link J Trace with another PC and if possible with another target system to see if it works there If the device functions correctly the USB setup on the original machine or your target hardware is the source of the problem not J Link J Trace If you need to contact support send the following information to support segger com A detailed description of the problem J Link J Trace serial number Output of JLink exe if available Your findings of the signal analysis Information about your target hardware processor board etc J Link J Trace is sold directly by SEGGER or as OEM product by other vendors We can support only official SEGGER products J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 312 CHAPTER 13 Support and FAQs 13 4 Frequently Asked
195. e can be established cor retly the device as well as the interface and interface speed have to be given on start of GDB Server either via command line options or the configuration dialog If the target device option device is given the configuration dialog will not pop up 3 3 2 2 Setting up GDB Server CL version The command line version of GDB Server is part of the J Link Software Package for all supported platforms On Windows its name is JLinkGDBServerCL exe on Linux and Mac it is JLinkGDB Server J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 68 J Link software documentation package Starting GDB Server on Windows To start GDB Server CL on Windows open the Run prompt Windows R or a com mand terminal cmd and enter lt PathToJLinkSoftware gt JLinkGDBServerCL exe lt CommandLineOptions gt Starting GDB Server on Linux Mac To start GDB Server CL on Linux Mac open a terminal and call JLinkGDBServer lt CommandLineOptions gt Command Line Options When using GDB Server CL at least the mandatory command line options have to be given Additional command line options can be given to change the default behavior of GDB Server For more information about the available command line options please refer to Com mand line options on page 87 3 3 2 3 GDB Server user interface The J Link GDB Server s user interface shows information about the debugging pro
196. e for ROM chapter in ADS Developer Guide 8 5 2 SWI interface The ARM and Thumb SWI instructions contain a field that encodes the SWI number used by the application code This number can be decoded by the SWI handler in the system See the chapter on exception handling in ADS Developer Guide for more information on SWI handlers Semihosting operations are requested using a single SWI number This leaves the other SWI numbers available for use by the application or operating system The SWI used for semihosting is 0x123456 in ARM state OxAB in Thumb state The SWI number indicates to the debug agent that the SWI is a semihosting request In order to distinguish between operations the operation type is passed in rO All other parameters are passed in a block that is pointed to by r1 The result is returned in rO either as an explicit return value or as a pointer to a data block Even if no result is returned assume that rO is corrupted J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 236 CHAPTER 8 RDI The available semihosting operation numbers passed in rO are allocated as follows 0x00 to 0x31 These are used by ARM 0x32 to OxFF These are reserved for future use by ARM 0x100 to Ox1FF Reserved for applications 8 5 2 1 Changing the semihosting SWI numbers It is strongly recommended that you do not change the semihosting SWI numbers 0x123456 ARM or OxAB Thumb If you do so you must
197. e instead Table 3 8 General command line options J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 89 3 3 5 1 Description Pre select the CPU core of the connected device so the GDB Server already knows the register set even before having established a connection to the CPU Note Deprecated please use device instead Anyhow does not hurt if this option is set too Syntax CPU lt CPUCore gt Example jlinkgdbserver CPU ARM7_9 Add information The following table lists all valid values for cPUCore lt CPUCore gt Supported CPU cores CPU_FAMILY_ARM7_9 Pre select ARM7 and ARMO as CPU cores CPU FAMILY CORTEX A Pre select Cortex A and Cortex R as CPU cores CPU FAMILY CORTEX M Pre select Cortex M as CPU core CPU FAMILY RX600 Pre select Renesas RX600 as CPU core Table 3 9 GDB allowed values for CPUCore 3 3 5 2 device Description Tells GDBServer to which device J Link is connected before the connect sequence is actually performed It is recommended to use the command line option to select the device instead of using the remote command since for some devices J Link already needs to know the device at the time of connecting to it since some devices need special connect sequences e g devices with TI ICEPick modules In such cases it is not possible to select the device via remote commands since they are configured afte
198. e of charge J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 190 6 Flash download 6 3 Supported devices J Link supports download into the internal flash of a large number of microcontrol lers You can always find the latest list of supported devices on our website http www segger com jlink supported devices html In general J Link be used with any ARM7 9 11 Cortex MO M1 M3 M4 and Cor tex A5 A8 R4 core even if it does not provide internal flash Furthermore flash download is also available for all CFI compliant external NOR flash devices J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 191 6 4 Setup for various debuggers internal flash The J Link flash download feature can be used by different debuggers such as IAR Embedded Workbench Keil MDK GDB based IDEs For different debuggers there are different steps required to enable J Link flash download In this section the setup for different debuggers is explained 6 4 4 IAR Embedded Workbench Using the J Link flash download feature in IAR EWARM is quite simple First choose the right device in the project settings if not already done The device settings can be found at Project gt Options gt General Options gt Target Options for node at91sam7s ek Compiler Assembler Output Converter Custom Build Build Actions Linker Debugger Simulator Angel GDB S
199. e of software SEGGER J Link software may only be used with original SEGGER products and autho rized OEM products The use of the licensed software to operate SEGGER product clones is prohibited and illegal 2 3 1 Use of the software with 3rd party tools For simplicity some components of the J Link software are also distributed from partners with software tools designed to use J Link These tools are primarily debug ging tools but also memory viewers flash programming utilities but also software for other purposes Distribution of the software components is legal for our partners but the same rules as described above apply for their usage They may only be used with original SEGGER products and authorized OEM products The use of the licensed software to operate SEGGER product clones is prohibited and illegal J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 51 2 44 Original SEGGER products The following products are original SEGGER products for which the use of the J Link software is allowed 2 4 1 J Link J Link is a JTAG emulator designed for ARM cores It connects via USB to a PC running Microsoft Windows 2000 Windows XP Windows 2003 Windows Vista or Windows 7 J Link has a built in 20 pin JTAG connector which is compatible with the standard 20 pin connector defined by ARM Licenses Comes with built in licenses for flash download 2 4 2 J Link PLUS J Link PLUS is a USB powered
200. e the J Link SWOViewer need to be told that the CPU is run ning at 14 MHz to make SWO speed auto detection to work no matter what speed the CPU is really running at J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 264 CHAPTER 9 Device specifics 9 16 ST Microelectronics J Link has been tested with the following ST Microelectronics devices STR710FZ1 STR710FZ2 STR711FRO STR711FR1 STR711FR2 STR712FRO STR712FR1 STR712FR2 STR715FRO STR730FZ1 STR730FZ2 STR731FVO STR731FV1 STR731FV2 STR735FZ1 STR735FZ2 STR736FVO STR736FV1 STR736FV2 STR750FVO STR750FV1 STR750FV2 STR751FRO STR751FR1 STR751FR2 STR752FRO STR752FR1 STR752FR2 STR755FRO STR755FR1 STR755FR2 STR755FVO STR755FV1 STR755FV2 STR911FM32 STR911FM44 STR911FW32 STR911FW44 STR912FM32 STR912FM44 STR912FW32 STR912FW44 STM32F101C6 STM32F101C8 STM32F101R6 STM32F101R8 STM32F101RB STM32F101V8 STM32F101VB STM32F103C6 STM32F103C8 STM32F103R6 STM32F103R8 STM32F103RB STM32F103V8 STM32F103VB J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 265 9 16 1 5 91 9 16 1 1 JTAG settings These device are ARM966E S based We recommend to use adaptive clocking for these devices 9 16 1 2 Unlocking The devices have 3 TAP controllers built in When starting J Link exe it reports 3 JTAG devices A special tool J Link STR9 Commander JLinkSTR91x exe is available to directly access the
201. e used in batch mode which allows the user to use J Link commander for batch processing and without user interaction Please do not confuse command file with J Link script files please refer to J Link script files on page 165 for more information about J Link script files When using J Link com mander in batch mode the path to a command file is passed to it The syntax in the command file is the same as when using regular commands in J Link commander one line per command J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 65 Example JLink exe CommanderScript C CommandFile jlink Contents of CommandFile jlink e h exec device STM32F103ZE loadbin C firmware bin 0x08000000 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 66 J Link software documentation package 3 3 J Link GDB Server The GNU Project Debugger GDB is a freely available and open source debugger It can be used in command line mode but is also integrated in many IDEs like emIDE or Eclipse J Link GDB Server is a remote server for GDB making it possible for GDB to connect to and communicate with the target device via J Link GDB Server and GDB commu nicate via a TCP IP connection using the standard GDB remote protocol GDB Server receives the GDB commands does the J Link communication and replies with the answer to GDB With J Link GDB Server debugging in ROM and
202. ecome high reset active and then low reset no longer active afterwards 4 Clear vC CORERESET 5 8 2 2 Type 1 Core Only the core is reset via the vECTRESET bit The peripherals are not affected After setting the vECTRESET bit J Link waits for the s RESET ST bit in the Debug Halting Control and Status Register DHCSR to first become high and then low afterwards The CPU does not start execution of the program because J Link sets the VC CORERESET bit before reset which causes the CPU to halt before execution of the first instruction Note In most cases it is not recommended to reset the core only since most tar get applications rely of the reset state of some peripherals PLL External memory interface etc and may be confused if they boot up but the peripherals are already configured 5 8 2 3 Type 2 ResetPin J Link pulls its RESET pin low to reset the core and the peripherals This normally causes the CPU RESET pin of the target device to go low as well resulting in a reset of both CPU and peripherals This reset strategy will fail if the RESET pin of the target device is not pulled low The CPU does not start execution of the program because J Link sets the vc CORERESET bit before reset which causes the CPU to halt before execution of the first instruction 5 8 2 4 Type 3 Connect under Reset J Link connects to the target while keeping Reset acti
203. ed All licenses can be added 2 5 5 IAR J Link Lite IAR J Link Lite is an OEM version of J Link sold by IAR Limitations IAR J Link Lite can not be used with Keil MDK This limitation can NOT be lifted if you would like to use J Link with Keil MDK you need to buy a separate J Link JTAG speed is limited to 4 MHz Licenses No licenses are included All licenses can be added Note IAR J Link is only delivered and supported as part of Starter Kits It is not sold to end customer directly and not guaranteed to work with custom hardware J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 58 CHAPTER 2 Licensing 2 5 6 J Trace 1 is an OEM version of J Trace sold by Limitations IAR J Trace can not be used with Keil MDK This limitation can NOT be lifted if you would like to use J Trace with Keil MDK you need to buy a separate J Trace Licenses No licenses are included All licenses can be added 2 5 7 J Link Lite LPC Edition J Link Lite LPC Edition is an OEM version of J Link sold by NXP Limitations J Link Lite LPC Edition only works with NXP devices This limita tion can NOT be lifted if you would like to use J Link with a device from an other manufacturer you need to buy a separate J Link Licenses No licenses are included 2 5 8 SEGGER J Link Lite ARM J Link Lite ARM is a fully functional OEM version of SEGGER J
204. edance of 50 The J Trace unit will operate with a target board that has a supply voltage range of 3 0V 3 6V 10 2 4 2 Clock frequency For capturing trace port signals synchronous to TRACECLK J Trace supports a TRACECLK frequency of up to 200MHz The following table shows the TRACECLK frequencies and the setup and hold timing of the trace signals with respect to TRACE CLK Parameter Min Max Explanation Tperiod 5ns 1000ns Clock period Fmax 1MHz 200MHz Maximum trace frequency Tch 2 5ns 2 High pulse width Tcl 2 5ns Low pulse width Table 10 8 Clock frequency J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 284 10 Target interfaces and adapters Parameter Min Max Explanation Tsh 2 5ns Data setup high Thh 1 5ns P Data hold high 5 2 5ns Data setup low Thl 1 5ns Data hold low Table 10 8 Clock frequency The diagram below shows the TRACECLK frequencies and the setup and hold timing of the trace signals with respect to TRACECLK Tperiod Full TRACECLK Tch Tel DATA X Tsh Thh 5 Thl Half rate TRACECLK Note 1 supports half rate clocking mode Data is output on each edge of the TRACECLK signal and TRACECLK max lt 100MHz For half rate clocking the setup and hold times at the JTAG Trace connector must be observed J Link J Trace UM0
205. er GmbH amp Co KG 286 10 Target interfaces and adapters PIN SIGNAL TYPE Description TRACE 16 DATA 1 Input Input Trace data pin 0 TRACE 18 DATA 2 Input Input Trace data 0 TRACE 20 DATA 3 Input Input Trace data 0 Table 10 9 19 pin JTAG SWD and Trace pinout Pins 3 5 15 17 19 are GND pins connected to GND in J Trace CM3 They should also be connected to GND in the target system 10 3 1 Target power supply Pins 11 and 13 of the connector can be used to supply power to the target hardware Supply voltage is 5V max current is 300mA The output current is monitored and protected against overload and short circuit Power can be controlled via the J Link commander The following commands are available to control power Command Explanation power on Switch target power on power off Switch target power off power on perm Set target power supply default to on power off perm Set target power supply default to off Table 10 10 Command List J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 287 10 4 9 JTAG SWD connector Some target boards only provide 9 pin JTAG SWD connector for Cortex M For these devices SEGGER provides a 20 pin gt 9 pin Cortex M adapter VTref 1 2 SWDIO TMS GND 3 4 SWCLK GND 5 ee 6 SWO 7 8 TDI N
206. er to Target power supply on page 278 Table 10 3 J Link J Trace SWD pinout Pins 4 6 8 10 12 14 16 18 20 are GND pins connected to GND in J Link They should also be connected to GND in the target system J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 278 CHAPTER 10 Target interfaces and adapters 10 1 2 1 Target board design We strongly advise following the recommendations given by the chip manufacturer These recommendations are normally in line with the recommendations given in the table Pinout for SWD on page 277 In case of doubt you should follow the recommen dations given by the semiconductor manufacturer Typical target connection for SWD JTAG connector Target board 5V supply Voltage Optional to supply the target board from J Link 10 1 2 2 Pull up pull down resistors A pull up resistor is required on SWDIO on the target board ARM recommends 100 kOhms In case of doubt you should follow the recommendations given by the semiconductor manufacturer 10 1 2 3 Target power supply Pin 19 of the connector can be used to supply power to the target hardware Supply voltage is 5V max current is 300mA The output current is monitored and protected against overload and short circuit Power can be controlled via the J Link commander The following commands are available to control power Command Explanation power on Switch
207. erent reset strategies for different CPUs Moreover the reset strategies which are available differ from CPU core to CPU core J Link can perform various reset strategies and always selects the best fitting strategy for the selected device Example gt monitor reset lt Resetting target 3 3 3 18 semihosting breakOnError Syntax semihosting breakOnerror lt Value gt J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 79 Description Enables or disables halting the target at the semihosting breakpoint in SVC handler if an error occurred during a semihosting command for example a bad file handle for SYS_WRITE The GDB Server log window always shows a warning in these cases breakOnError is disabled by default Example Enable breakOnError gt monitor semihosting breakOnError 1 3 3 3 19 semihosting enable Syntax semihosting enable lt VectorAddr gt Description Enables semihosting with the specified vector address If no vector address is speci fied the SWI vector at address 0x8 will be used GDBServer will output semihost ing terminal data from the target via a separate connection on port 2333 Some IDEs already establish a connection automatically on this port and show terminal data in a specific window in the IDE For IDEs which do not support semihosting terminal output directly the easiest way to view semihosting output is to open a telnet connection to the GDBServer on
208. erver J Link Remote Server allows using J Link J Trace remotely via TCP IP This enables you to connect to and fully use a J Link J Trace from another computer Perfor mance is just slightly about 10 lower than with direct USB connection ui q IPStat Connected to 127 0 0 1 wW WR NES of USBStat About waiting for client on port 19020 The J Link Remote Server also accepts commands which are passed to the J Link Remote Server via the command line 3 4 14 List of available commands The table below lists the commands accepted by the J Link Remote Server Command Description Selects the port which the J Link Remote Server is pum listening usb Selects a usb port for communication with J Link Table 3 10 Available commands 3 4 1 1 port Syntax port lt Portno gt Example To start the J Link Remote Server listening on port 19021 the command should look as follows port 19021 3 4 1 2 usb Syntax usb lt USBIndex gt Example Currently usb 0 3 are supported so if the J Link Remote Server should connect to the J Link on usb port 2 the command should look as follows usb 2 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 99 3 4 2 Tunneling mode The Remote server provides a tunneling mode which allows remote connection to a J Link J Trace from any computer even from outside
209. erver IAR ROM monitor J Link J Trace LMI FTDI Macraigor RDI Third Party Driver To use the J Link flash loaders the IAR flash loader has to be disabled To disable the IAR flash loader the checkbox Use flash loader s at Project gt Options gt Debug ger gt Download has to be disabled as shown below Options for node at91sam7s ek General Options C C Compiler Assembler Output Converter Custom Build Build Actions Linker Angel GDB Server IAR ROM monitor J Link J Trace LMI FTDI Third Party Driver 6 4 2 Keil MDK To use the J Link flash download feature in Keil MDK the following steps need to be performed J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 192 CHAPTER 6 Flash download First choose the device in the project settings if not already done The device set tings can be found at Project gt Options for Target gt Device X Options for Target MCBSTM32E Flash Device Target Output Listing User Linker Debug Utiities Database Generic CPU Data Base 71 Vendor STMicroelectronics Device STM32F103ZE Toolset ARM 3 STM32F103VF 3 STM32F103VG 3 STM32F103ZC 3 STM32F1037D ARM 32bit Cortex M3 Microcontroller 72MHz 512kB Flash 64 SRAM 2 0B Active 3 12 bit 16 ch A D Converter 2 12 bit D A Converter d 034 3 sTM32F1032G SDIO Fast 0 Pots 3 STM32
210. es 58 30 9f es Code C TooNC emIDE V2 1 arm Example Vend 0x00000020 03 00 52 ei 04 00 91 34 04 00 82 34 fb ff ff 0500000030 48 10 9f eS 48 20 9f eS 00 30 a0 02 00 51 1 0x0 Oxo 0 2004 0 209841 0 0 0 0x0 0 0 0 0 6 0x00000040 04 30 81 14 fc ff ff 1a 00 00 Of el cO 00 cO 0500000050 00 0 29 1 00 00 a0 00 10 a0 24 20 9f e5 0x00000060 Of e0 a0 el 12 ff 2f el fe ff ff ea le ff 2f el 0x00000070 00 10 00 60 02 10 00 00 00 20 00 00 00 20 00 0 00000080 00 00 20 00 00 00 20 00 28 02 10 00 db 0 21 Variable Value 0 00000090 2 40 eS 47 0 21 e3 28 40 9f e5 d1 0 21 cut 0 00000000 0 000000 0 24 dO 9f eS d2 0 21 20 40 9f 5 d3 0 21 0x000000b0 1 dO 9f eS 1 00 9f eS 0f a0 el 10 ff 2f el 05000000 0 fe ff ea 00 01 20 00 00 01 20 00 00 00 20 00 0 00000080 00 01 20 00 00 OS 20 00 00 10 00 10 30 9f e5 0x000000e0 02 29 a0 00 20 83 eS 01 30 a0 03 00 a0 1 0x000000f0 1e ff 2f el 44 ff ff 3c 30 9f eS 38 20 5 At C Tool C EMIDEV 1 1 arm Example Vendor ATMEL_ 1 Src Main c 28 At C Tool C EMIDEV 1 1 arm Example Vendor ATMEL_ 1 Src Main c 29 Command Console GDB can be used stand alone as a console application To connect GDB to GDB Server enter target remote localhost 2331 into the run ning GDB Within GDB all GDB commands and the remote monit
211. et REN 54 2 4 9 Ethic 55 2 5 J Link OEM versions a X DAA 56 2 5 1 Analog Devices MIDASLINK 56 2 5 2 Atmel SAMCE E Fe Tag dw Sw var a dio DN YE Cei 56 2 5 3 Dig JTAG EINK TEE 57 2 5 4 J Link J LINK KS nece yx x vez e xen Ce E EE RE E 57 2 5 5 J GNK EI ET 57 2 5 6 TAR 2 58 2 5 7 NXP J Eink Lite EPC gt rere rt terrain eene yr e sivas 58 2 5 8 SEGGER J Link Lite 2 1 666 nni sia sna nnne nn 58 2 6 J GNK OBS 59 2 7 rie pellet an pee iin Bons Ay 60 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 16 J Link software and documentation 61 3 1 Software nna sena sea a rea rea area EEE ESSE SESE EERE EES 62 3 2 J Link Commander Command line 63 3 2 1 Command line options een ee
212. et an unlimited number of breakpoints if the program is located either in RAM or in flash by setting and resetting breakpoints according to program code An info window can be displayed while flash breakpoints are used showing the cur rent operation Depending on your JTAG speed the info window may only hardly to be seen Programming sector 0 128 Bytes addr 0x00000000 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 233 8 4 4 6 CPU tab J Link RDI Configuration 24 x General Init JTAG Flash Breakpoints CPU Log Allows the emulator to simulate individual instructions when single stepping instructions This does not normally have any disadvantages and makes debugging much faster especially when using flash breakpoints Reset strategy J Link supports different reset strategies This is necessary because there is no single way of resetting and halting an core before it starts to execute instructions Hardware halt after reset normal Delay after reset 0 ms The hardware RESET pin is used to reset the CPU After reset release J Link continuously tries to halt the CPU This typically halts the CPU shortly after reset release the CPU can in most systems execute some instructions before it is halted The number of instructions executed depends primarily on the JTAG speed the higher the JTAG speed the faster the CPU can be halted Some CPUs can actually be h
213. et device to enable the CPU frequency auto detection of the J Link DLL To select a ST STM32F207IG as target device the command line should look as below J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 106 CHAPTER 3 J Link software and documentation package For a list of all supported device names please refer to lt Ref gt Syntax device DeviceID Example deivce STM32F207IG 3 7 2 3 itmmask Defines a set of stimulusports from which SWO data is received and displayed by SWO Viewer If itmmask is given itmport will be ignored Syntax itmmask Mask Example Listen on ports 0 and 2 itmmask 0x5 3 7 2 4 itmport Defines the stimulus port from which SWO data is received and displayed by the SWO Viewer Default is stimulus port 0 The command line should look as below Syntax itmport lt ITMPortIndex gt Example itmport 0 3 7 2 5 outputfile Define a file to which the output of SWO Viewer is printed Syntax outputfile lt PathToFile gt Example outputfile C Temp Output log 3 7 2 6 settingsfile Select a J Link settings file to use for the target device Syntax settingsfile lt PathToFile gt Example settingsfile C Temp Settings jlink 3 7 2 7 swofreq Define the SWO frequency that shall be used by J Link SWO Viewer for sampling SWO data Usually not necessary to define since optimal SWO speed is calculated automa
214. ew TE YT Y WIR PAR QR FEE agus 191 6 4 3 Mentor Sourcery CodeBench 411 1 16 194 6 4 4 J Link GDB Server oriori irea er tr ee xix Haa We REX Ya RR V Fea any i 194 6 4 5 JzLink Gommafidet eiee EA trou eg RT FOR RERO TS 195 6 4 6 EDEN mm 196 6 5 Setup for various debuggers CFI 0 0 0 197 6 5 1 IAR Embedded Workbench MDK emen 197 6 5 2 2 RIPE PEL 198 6 5 3 J Link comitnander o mtv Dre aea exc c vs XY eee dx 198 6 6 Using the DLL flash loaders in custom applications 200 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 18 DIGARDOUMS i icio ctm ti eo Rr 201 7 1 IMEFOGUGHON 202 7 2 Brei Ee 203 7 2 1 Free for evaluation and non commercial 4 203 7 3 S pported devices dco et eret ER EE ERE SA 204 7 4 Setup amp compatibility with various debuggers 0 1 nnn 205 7 4 1 SeLbup ive eve ete cete boule cdi eo a 205 7 4 2 Compatibili
215. f the signal path therefore sees the distorted signal and might not operate cor rectly Care must be taken not to connect devices in this way unless the distor tion does not affect device operation J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 306 12 Designing the target board for trace 12 3 Signal requirements The table below lists the specifications that apply to the signals as seen at the JTAG Trace connector Signal Value Fmax 200MHz Ts setup time min 2 0ns Th hold time min 1 0ns TRACECLK high pulse width min 1 5ns TRACECLK high pulse width min 1 5ns Table 12 1 Signal requirements J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 307 Chapter 13 Support and FAQs This chapter contains troubleshooting tips together with solutions for common prob lems which might occur when using J Link J Trace There are several steps you can take before contacting support Performing these steps can solve many problems and often eliminates the need for assistance This chapter also contains a collection of frequently asked questions FAQs with answers J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 308 CHAPTER 13 Support and FAQs 13 1 Measuring download speed 13 1 1 Test environment JLink exe has been used for measurement performance The hardware consisted of
216. f network related settings IP address subnet mask default gateway of J Link The user can choose between automatic IP assignment settings are provided by a DHCP server in the network and manual IP assignment by selecting the appropriate radio button umm e J Link Pro Webserver SEGGER Microcontroller Home Network configuration Network information Network configuration C Automatic Manual System information M DHCP IP address rez 168 n Subnet mask 255 255 1 About Gateway 168 Emulator status J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 126 4 Setup 4 4 FAQs Q How can I use J Link with GDB and Ethernet A You have to use the J Link GDB Server in order to connect to J Link via GDB and Ethernet J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 4 5 J Link Configurator Normally no configuration is required especially when using J Link via USB For spe cial cases like having multiple older J Links connected to the same host PC in paral lel they need to be re configured to be identified by their real serial number when enumerating on the host PC This is the default identification method for current J Links J Link with hardware version 8 or later For re configuration of old J Links or for configuration of the IP settings use DHCP IP address subnet mask of a J Lin
217. face Note Deprecated Use command line option i instead Syntax interface lt InterfaceIdentifier gt Description Selects the target interface used by J Link J Trace 3 3 3 11 jtagconf Syntax jtagconf lt IRPre gt lt DRPre gt Description Configures a JTAG scan chain with multiple devices on it lt IRPre gt is the sum of IRLens of all devices closer to TDI where IRLen is the number of bits in the IR Instruction Register of one device lt DRPre gt is the number of devices closer to TDI For more detailed information of how to configure a scan chain with multiple devices please refer to See Determining values for scan chain configuration on page 143 Note To make sure the connection to the device can be established correctly it is recommended to configure the JTAG scan chain via command line options at start of GDB Server Example Select the second device where there is 1 device in front with IRLen 4 gt monitor jtagconf 4 1 3 3 3 12 memU8 Syntax MemU8 lt address gt lt value gt Description Reads or writes a byte from to a given address If lt value gt is specified this com mand writes the value to the given address Otherwise this command reads from the given address J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 77 Example Read gt monitor memU8 0x50000000 lt Reading from address 0x50000000 Data 0x04 Write gt
218. firmware If connecting fails J Link Commander goes through all target interfaces supported by the connected J Link and tries to connect to the device J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 64 CHAPTER 3 J Link software and documentation package Syntax If lt TargetInterface gt Example JLink exe If SWD Additional information Currently the following target interfaces are supported JTAG e SWD IP Selects IP as host interface to connect to J Link Default host interface is USB Syntax IP lt IPAddr gt Example JLink exe IP 192 168 1 17 Additional information To select from a list of all available emulators on Ethernet please use as lt IPAddr gt SelectEmuBySN Connect to a J Link with a specific serial number via USB Useful if multiple J Links are connected to the same PC and multiple instances of J Link Commander shall run and each connects to another J Link Syntax SelectEmuBySN lt SerialNo gt Example JLink exe SelectEmuBySN 580011111 Speed Starts J Link Commander with a given initial speed Available parameters are adap tive auto or a freely selectable integer value in kHz It is recommended to use either a fixed speed or if it is available on the target adaptive speeds Default inter face speed is 100kHz Syntax Speed Speed kHz Example JLink exe Speed 4000 3 2 2 Using command files J Link commander can also b
219. flash controller of the device This tool can be used to erase the flash of the controller even if a program is in flash which causes the ARM core to stall For more information about the J Link STR9 Commander please refer to J Link STR91x Commander Command line tool on page 113 When starting the STR91x commander a command sequence will be performed which brings MCU into Turbo Mode While enabling the Turbo Mode a dedicated test mode signal is set and controls the GPIOs in output The IOs are maintained in this state until a next JTAG instruction is send ST Microelectronics Enabling Turbo Mode is necessary to guarantee proper function of all commands in the STR91x Commander 9 16 1 3 Switching the boot bank The bootbank of the STR91x devices can be switched by using the J Link STR9 Com mander which is part of the J Link software and documentation package For more information about the J Link STR9 Commander please refer to J Link STR91x Com mander Command line tool on page 113 9 16 2 STM32F10xxx These device are Cortex M3 based devices of this family are supported by J Link 9 16 2 1 ETM init The following sequence can be used to prepare STM32F10xxx devices for 4 bit ETM tracing int v DBGMCU_CR enable trace I O and configure pins for 4 bit trace volatile int 0 0042004 amp 7 lt lt 5 Preserve all bits except the trace pin configuration v 7 lt lt
220. formed by the commands excluding writing the OTP sector and erasing the flash can be undone This tool can be used to erase the flash of the con troller even if a program is in flash which causes the CPU core to stall ork JLinkARM Dutput Debug JLinkSTR91x exe primary flash manually where selects 256 Kbytes device a 1624 KBytes device and 3 a 2048 Show configuration r content and security status Read memory Syntax lt NumBytes gt Erase f gt OTP not be erased gt gt 5 and 1 are available sk gt of bank 4 of bank to the OTP sectors 2 writeotp lt Wordi gt lt Word2 gt lt Word8 gt When starting the STR91x commander a command sequence will be performed which brings MCU into Turbo Mode While enabling the Turbo Mode a dedicated test mode signal is set and controls the GPIOs in output The IOs are maintained in this state until a next JTAG instruction is send ST Microelectronics Enabling Turbo Mode is necessary to guarantee proper function of all commands in the STR91x Commander 3 11 1 1 Command line options J Link STR91x Commander can be started with different command line options In the following the command line options which are available for J Link STR91x Com mander are explained CommandFile Selects a command file and starts J Link STR91x Commander in batch mode The batch mode of J Link Commander is similar to the execution of a batch file The com mand file is
221. g Cortex M3 M4 ARM7 9 11 No tracing Cortex A5 A8 A9 R4 ARM7 9 11 SUPPRUSE cores COR OMe MOS MSIE Sce Renesas RX M1 Cortex A5 A8 A9 R4 JTAG yes yes yes yes yes yes SWD yes yes yes yes yes no SWO yes yes yes yes yes no ETM Trace no no no no yes yes Software features Software features are features implemented in the software primarily on the host Software features can either come with the J Link or be added later using a license string from Segger J Link Stink Link J Trace J Flash yes opt yes yes yes yes yes Flash breakpoints yes opt yes yes yes yes yes Flash download yes yes yes yes yes yes GDB Server yes yes yes yes yes yes RDI yes opt yes yes yes yes yes 1 Most IDEs come with its own flashloaders so in most cases this feature is not essential for debugging your applications in flash The J Link flash download FlashDL feature is mainly used in debug environments where the debugger does not come with an own flashloader for example the GNU Debugger For more infor mation about how flash download via FlashDL works please refer to Flash download on page 187 2 In order to use the flash breakpoints with J Link no additional license for flash download is required The flash breakpoint feature allows setting an unlimited num ber of breakpoints even if the application program is not located in RAM but in f
222. g Interface RDI is an Application Programming Interface API that defines a standard set of data structures and functions that abstract hardware for debugging purposes J Link RDI mainly consists of a DLL designed for ARM cores to be used with any RDI compliant debugger The J Link DLL feature flash download and flash breakpoints can also be used with J Link RDI RDI compliant ad Debugger J Link RDI DLL 8 1 1 Features Can be used with every RDI compliant debugger Easy to use Flash download feature of J Link DLL can be used Flash breakpoints feature of J Link DLL can be used Instruction set simulation improves debugging performance J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 209 8 2 Licensing In order to use the J Link RDI software a separate license is necessary for each J Link For some devices J Link comes with a device based license and some J Link models also come with a full license for J Link RDI but the normal J Link comes with out any licenses For more information about licensing itself and which devices have a device based license please refer to Licensing on page 47 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 210 8 RDI 8 3 Setup for various debuggers The J Link RDI software is an ARM Remote Debug Interface RDI for J Link It makes it possible to use J Link with any RDI compliant debugger
223. get hard 5V Sup ware Older J Links may not be able to supply power on this 19 Output pin For more information about how to enable disable the ply power supply please refer to Target power supply on page 276 Table 10 1 J Link J Trace pinout Pins 4 6 8 10 12 14 16 18 20 are GND pins connected to GND in J Link They should also be connected to GND in the target system 10 1 1 1 Target board design We strongly advise following the recommendations given by the chip manufacturer These recommendations are normally in line with the recommendations given in the table Pinout for JTAG on page 274 In case of doubt you should follow the recommen dations given by the semiconductor manufacturer You may take any female header following the specifications of DIN 41651 For example Harting Molex Tyco Electronics J Link J Trace UM08001 part no 09185206803 part no 90635 1202 part no 2 215882 0 2004 2014 SEGGER Microcontroller GmbH amp Co KG 276 CHAPTER 10 Target interfaces and adapters Typical target connection for JTAG JTAG connector Target board supply Voltage NTRST and RTCK may not be available on some CPUs Optional to supply the target board from J Link 10 1 1 2 Pull up pull down resistors Unless otherwise specified by developer s manual pull ups pull downs are recom mended to 100 kOhms 10 1 1 3 Target power supply Pin 19 of the connector can be u
224. gures a JTAG scan chain with multiple devices on it memu8 Reads or writes a byte from to given address memU16 Reads or writes a halfword from to given address memU32 Reads or writes a word from to given address reg Reads or writes from to given register regs Reads and displays all CPU registers reset Resets and halts the target CPU semihosting breakOn Error Enable or disable halting the target on semihosting error semihosting enable Enables semihosting semihosting IOClient Set semihosting I O to be handled via Telnet port or GDB semihosting ARMSWI Sets the SWI number used for semihosting in ARM mode semihosting ThumbSWI Sets the SWI number used for semihosting in thumb mode setargs Set the arguments for the application setbp Sets an instruction breakpoint at a given address sleep Sleeps for a given time period speed Sets the JTAG speed of J Link J Trace step Performs one or more single instruction steps SWO DisableTarget Undo target configuration for SWO and disable it in J Link SWO EnableTarget Configure target for SWO and enable it in J Link SWO GetMaxSpeed Prints the maximum supported SWO speed for J Link and Target CPU SWO GetSpeedInfo Prints the available SWO speed and its minimum divider waithalt Waits for target to halt code execution wice Writes to given IceBreaker register Table 3 2 GDB remo
225. h programming algorithm for the particular flash Different flash chips have different programming algorithms the programming algorithm also depends on other things such as endianess of the target system and organization of the flash memory for example 1 8 bits 1 16 bits 2 16 bits or 32 bits The RAM code requires data to be programmed into the flash memory There are 2 ways of supply ing this data Data download to RAM or data download via DCC 11 4 2 Data download to RAM The data or part of it is downloaded to an other part of the RAM of the target sys tem The Instruction pointer R15 of the CPU is then set to the start address of the Ram code the CPU is started executing the RAM code The RAM code which con tains the programming algorithm for the flash chip copies the data into the flash chip The CPU is stopped after this This process may have to be repeated until the entire data is programmed into the flash 11 4 3 Data download via DCC In this case the RAM code is started as described above before downloading any data The RAM code then communicates with the host computer via DCC JTAG and J Link J Trace transferring data to the target The RAM code then programs the data into flash and waits for new data from the host The WriteMemory functions of J Link J Trace are used to transfer the RAM code only but not to transfer the data The CPU is started and stopped only once Using DCC for communication is typicall
226. he command line version is part of the Software and Documentation Package and also included in the Linux and MAC versions Except for the missing GUI J Link GDB Server CL is identical to the normal version All sub chapters apply to the command line version too J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 67 3 3 2 Debugging with J Link GDB Server With J Link GDB Server programs can be debugged via GDB directly on the target device like a normal application The application can be loaded into RAM or flash of the device Before starting GDB Server make sure a J Link and the target device are connected 3 3 2 1 Setting up GDB Server GUI version The GUI version of GDB Server is part of the Windows J Link Software Package JLinkGDBServer exe When starting GDB Server a configuration dialog pops up letting you select the needed configurations to connect to J Link and the target SEGGER J Link GDB Server V4 74 Config m Connection to J Link Serial No m Target device STM32F4171G E Little endian m Target interface Speed Auto selection Adaptive clocking e 4000 kHz Command line option select USB device STM32F417lG if SWD speed 4000 All configurations can optionally be given in the command line options Note To make sure the connection to the target devic
227. he he ke EERE ERE Macro file for J LINK RDI KKK KKK KKK KK ck ck ck KKK KKK ckck ck ck ck ck kc ck ckck kk kk File Purpose LPC2294 setup Setup for Philips LPC2294 chip ck Cckckckckckck ck ck ckck kckckckck ck KK KKK KKK KKK KEK ckck ckckck ckckck kck ck ck ck ck ck ck ck ck kk kk SetJTAGSpeed 1000 Reset 0 Write32 0xEO1FCO40 0x00000001 Write32 0xFFE00000 0x20003CE3 Write32 0xE002C014 0 0 6001 4 SetJTAGSpeed 2000 J Link J Trace 0 08001 Map User Flash into Vector area at 0 3f Setup CSO Setup PINSEL2 Register 2004 2014 SEGGER Microcontroller GmbH amp Co KG 230 8 RDI 8 4 4 3 JTAG tab mium RDI Configuration METTI contig JTAG speed This allows the selection of the JTAG speed There are basically three types of speed settings which are explained below e Fixed JTAG speed e Automatic JTAG speed e Adaptive clocking For more information about the different speed settings supported by J Link please refer to JTAG Speed on page 144 JTAG scan chain with multiple devices The JTAG scan chain allows to specify the instruction register organization of the tar get system This may be needed if there are more devices located on the target sys tem than the ARM chip you want to access or if more than one target sys
228. herals by setting the SYSRESETREQ bit in the AIRCR 3 Wait for the s RESET ST bit in the pHCSR to first become high reset active and then low reset no longer active afterwards 4 Clear vC CORERESET This type of reset may fail if e J Link has no connection to the debug interface of the CPU because it is in a low power mode e The debug interface is disabled after reset and needs to be enabled by a device internal bootloader This would cause J Link to lose communication after reset since the CPU is halted before it can execute the internal bootlader 5 8 2 10 Type 9 Reset for LPC1200 devices On the NXP LPC1200 devices the watchdog is enabled after reset and not disabled by the bootloader if a valid application is in the flash memory Moreover the watchdog keeps counting if the CPU is in debug mode When using this reset strategy J Link J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 163 performs a reset of the CPU and peripherals using the SYSRESETREQ bit in the ATRCR and halts the CPU after the bootloader has been performed and before the first instruction of the user code is executed Then the watchdog of the LPC1200 device is disabled This reset strategy is only guaranteed to work on modern J Links J Link V8 J Link Pro J link ULTRA J Trace for Cortex M J Link Lite and if a SWD speed of min 1 MHz is used This reset strategy should also work
229. hod of obtaining information from inside the MCU Usually it should not be necessary to configure the SWO speed because this is usually done by the debugger 5 4 2 1 Max SWO speeds The supported SWO speeds depend on the connected emulator They can be retrieved from the emulator To get the supported SWO speeds for your emulator use J Link Commander J Link si 1 Select target interface SWD J Link SWOSpeed Currently following speeds are supported Emulator Speed formula Resulting max speed J Link V9 60MHz n n gt 8 7 5 MHz J Link Pro ULTRA V4 3 2GHz n n gt 64 50 MHz Table 5 6 J Link supported SWO input speeds 5 4 2 2 Configuring SWO speeds The max SWO speed in practice is the max speed which both target and J Link can handle J Link can handle the frequencies described in SWO on page 145 whereas the max deviation between the target and the J Link speed is about 3 The computation of possible SWO speeds is typically done in the debugger The SWO output speed of the CPU is determined by TRACECLKIN which is normally the same as the CPU clock Example Target CPU running at 72 MHz n is be between 1 and 8192 Possible SWO output speeds are 72MHz 36MHz 24MHz J Link V9 Supported SWO input speeds are 60MHz gt 8 7 5MHz 6 66MHz 6MHz J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 146 CHAPTER 5 Working with J Link and
230. ialization File BI Edit Bj Edit Restore Debug Session Settings Restore Debug Session Settings 3 Breakpoints Toolbox IV Breakpoints Toolbox Watch Windows amp Performance Analyzer Watch Windows Memory Display IV Memory Display CPU DLL Paramet Driver DLL Paramet SARMCM3 DLL DLL Dialog DLL Paramet Dialog DLL Parameter 5 DLL 032 5 DLL estma2Fi 03ZE Now setup the Download Options at Project gt Options for Target gt Debug gt Settings Check Verify Code Download and Download to Flash as shown in the screenshot below Cortex JLink JTrace Target Driver Setup Debug Trace Flash Download r J Link J Trace Adapter JTAG Device Chain SN 173000305 gt usB amp o v IDCODE Device Name IRlen Move Device Junk ARM Pro TDO 0x3BA00477 CoreSight JTAG DP x06414041 Unknown JTAG device HW V300 V4 35c TDI gt Down FW J Link ARM Pro V3x compilec Port Max Clock 6 Automatic Detection ID CODE x Manual Configuration Device Name Delete Update IR len Si Debug Connect amp Reset Options Cache Options Download Options Reset Normal Cache Code Verify Code Download v eset iter Connect
231. ich GDB Server should listen for an incoming connection that gets target s printf data Semihosting and anylized SWO data Default port is 2333 Note Using multiple instances of GDB Server setting custom values for this option is necessary Syntax TelnetPort Port Example jlinkgdbserver TelnetPort 2554 3 3 5 29 vd Description Verifys the data after downloading it Note For the GUI version this setting is persistent for following uses of GDB Server until changed via command line option or the GUI Syntax vd J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 97 3 3 5 30 x Description Starts the GDB Server with gdbinit configuration file In contrast to the com mand line option the GDB Server runs the commands in the gdbinit file once only direct after the first connection of a client Syntax x lt ConfigurationFilePath gt Example jlinkgdbserver x C MyProject Sample gdb 3 3 5 31 Description Starts the GDB Server with a gdbinit configuration file GDB Server executes the commands specified in the gdbinit file with every connection of a client start of a debugging session Syntax lt ConfigurationFilePath gt Example jlinkgdbserver xc C MyProject Sample gdb J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 98 J Link software and documentation package 3 4 J Link Remote S
232. ignal on this pin when using SWD 9 NC NC Not connected inside J Link Leave open on target hard ware Table 10 11 9 pin JTAG SWD pinout Pins 3 and 5 are GND pins connected to GND on the Cortex M adapter They should also be connected to GND in the target system J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 288 10 Target interfaces and adapters 10 5 Adapters There are various adapters available for J Link as for example the JTAG isolator the J Link RX adapter or the J Link Cortex M adapter For more information about the different adapters please refer to http www segger com jlink adapters html J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 289 Chapter 11 Background information This chapter provides background information about JTAG and ARM The ARM7 and ARM9 architecture is based on Reduced Instruction Set Computer RISC principles The instruction set and the related decode mechanism are greatly simplified com pared with microprogrammed Complex Instruction Set Computer CISC J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 290 CHAPTER 11 Background information 11 1 JTAG JTAG is the acronym for Joint Test Action Group In the scope of this document the JTAG standard means compliance with IEEE Standard 1149 1 2001 11 1 1 Test access port TAP JTA
233. ime Max 10ns Clock fall time Max 10ns Table 1 3 J Link Lite specifications 1 36 J Link Lite Cortex M J Link Lite Cortex M is a specific OEM version of SEGGER J Link Lite which is designed to be used with Cortex M devices If you are selling evaluation boards J Link Lite CortexM is an inex pensive emulator solution for you Your customer receives a widely acknowledged JTAG SWD emulator which allows him to start right away with his development Very small form factor JTAG clock up to 4 MHz SWD SWO supported 3 3V target interface voltage 1 3 6 1 Specifications Fully software compatible to J Link Any 0 0 1 3 4 core supported Flash download into supported MCUs Standard 9 or 19 0 05 Samtec FTSH connector The following table gives an overview about the specifications general mechanical electrical for J Link Lite Cortex M General Supported OS For a complete list of all operating sys tems which are supported please refer to Supported OS on page 23 Electromagnetic compatibility EMC EN 55022 EN 55024 Operating temperature 5 C 60 Storage temperature 20 C 65 C Relative humidity non condensing Max 90 rH Size without cables 41mm x 34mm x 8mm Weight without cables 6g USB interface Mechanical USB 2 0 full speed Target interface 19 0 05 Samtec FTSH co
234. ing figure shows a host debugging two CPU cores with two instances of the same debugger Both debuggers share the same physical connection The core to debug is selected through the JTAG settings as described below J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 148 CHAPTER 5 Working with J Link and J Trace 5 5 2 Using multi core debugging in detail 4 5 Connect your target to J Link J Trace Start your debugger for example IAR Embedded Workbench for ARM Choose Project Options and configure your scan chain The picture below shows the configuration for the first CPU core on your target Options for node BTL_AT91_ 430 Category Factory Settings General Options C C Compiler Setup Connection Assembler m Communication Custom Build Build Actions USB Linker bbb cec ddd Debugger Simulator JTAG scan chain Angel JTAG scan chain with multiple targets number o Scan chain contains non amp RM devices IAR ROM monitor Macraigor RDI T Third Party Driver Freceeding bits 7 Log communication TOOLKIT DIR cspycomm log Start debugging the first core Start another debugger for example another instance of IAR Embedded Work bench for ARM J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 149 6 Choose Project Options and configure your
235. intelligence per model There are different models of J Link J Trace which have built in intelligence for dif ferent CPU cores In the following we will give you an overview about which model of J Link J Trace has intelligence for which CPU core 1 6 3 1 Current models The table below lists the firmware CPU support for J Link amp J Trace models currently available ARM ARM Cortex Cortex M Renesas J Link J Trace 7 9 11 RX600 model UOISJ9A JTAG JTAG JTAG JTAG J Link s o o z JTAG J Link Pro 3 J link ULTRA 1 J Link Lite ARM 8 J Link Lite Cortex M 8 99 9 O OOOO o000 0900 Q 00000 Oo 000 9 9 000 9 J Link Lite RX 8 J Trace ARM 1 J Trace for Cortex M 3 e e Table 1 10 Built in intelligence of current J Links J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 1 6 3 2 Older models The table below lists the firmware CPU support for older J Link amp J Trace models which are not sold anymore 2 Cortex Renesas J Link J Trace 1 9 11 AIR Cortex M RX600 model S JTAG JTAG JTAG JTAG SWD JTAG not sup J Link Q o e ported not sup J Link 4 o eo ported t 2 J Link 5 e J Link 6 e o e J Link 7 3 eo J Link Pro 11
236. ire memory can be accessed if a memory access fails the CPU reports this by switching to abort mode The CPU memory interface allows halting the CPU via a WAIT signal On some devices the WAIT signal stays active when accessing certain unused mem ory areas This halts the CPU indefinitely until RESET and will therefore end the debug session This is exactly what happens when accessing critical memory areas Critical memory areas should not be present in a device they are typically a hard ware design problem Nevertheless critical memory areas exist on some devices To avoid stalling the debug session a critical memory area can be excluded from access J Link will not try to read or write to critical memory areas and instead ignore the access silently Some debuggers such as IAR C SPY can try to access memory in such areas by dereferencing non initialized pointers even if the debugged program the debuggee is working perfectly In situations like this defining critical memory areas is a good solution Syntax map exclude lt SAddr gt lt EAddr gt Example This is an example for the map exclude command in combination with an NXP LPC2148 MCU Memory map 0x00000000 0x0007FFFF On chip flash memory 0x00080000 0x3FFFFFFF Reserved 0x40000000 0x40007FFF On chip SRAM J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 178 CHAPTER 5 Working with J Link and J Trace 0x40008000 0x7FCFFFFF Reserved
237. is allows the J Link RDI software to download program into flash A small piece of code will be downloaded and executed in the target RAM which then programs the flash memory This provides flash loading abilities even for debuggers without a build in flash loader An info window can be shown during download displaying the current operation Depending on your JTAG speed you may see the info window only very short J Link flash programming Finished flash programming J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 232 8 RDI 8 4 4 5 Breakpoints tab J Link RDI Configuration 21 General Init JTAG Flash Breakpoints CPU Log Software breakpoints as opposed to hardware breakpoints are breakpoints which modify program memory This allows setting an unlimited number of breakpoints if the program is located in RAM r w Use flash breakpoints Allows setting an unlimited number of breakpoints if the program is located in RAM or flash which is extremely valuable when debugging a program located in flash This feature is available only if flash programming is enabled Show info window during program Cancel Apply Use software breakpoints This allows to set an unlimited number of breakpoints if the program is located in RAM by setting and resetting breakpoints according to program code Use flash breakpoints This allows to s
238. k and host computer Peak current lt 10 ms limit is 1A operating current limit is 300mA J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 28 CHAPTER 1 Introduction Version 5 4 Obsolete Identical to version 5 3 with the following exception e Supports 5V target interfaces Version 6 0 Obsolete Identical to version 5 4 with the following exception Outputs be tristated Effectively disabling the JTAG interface Supports SWD interface SWD speed Software implementation 4 MHz maximum SWD speed J Link supports SWV Speed limited to 500 kHz Version 7 0 Obsolete Identical to version 6 0 with the following exception e Uses an additional pin to the UART unit of the target hardware for SWV support Speed limited to 6 MHz Version 8 0 Identical to version 7 0 with the following exception e SWD support for non 3 3V targets Version 9 1 e New design based on STM32F205 Version 9 2 Identical to version 9 1 with the following exception e Pin 1 VTref is used for measuring target reference voltage only Buffers on J Link side are no longer powered through this pin but via the J Link internal volt age supplied via USB J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 29 1 3 3 J Link ULTRA J Link ULTRA is a JTAG SWD emulator designed for ARM Cor tex and other supported CPUs It is fully compatible to the standard J Link and w
239. k compiled Nov 17 2005 16 12 19 ARM Rev 5 J Link compiled NOU 17 2005 16 12 19 ARM Rev 5 J Link compiled Nov 17 2005 16 12 19 ARM Rev 5 CRC CD83 In the screenshot the red box contains information about the formerly used J Link 1 firmware version J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 301 Use an application for example JLink exe which uses the desired version of JLinkARM dll This automatically replaces the invalidated firmware with its embedded firmware JLink exe SEGGER J Link Commander 02 68 01 for help Compiled 14 02 49 on Oct 25 2005 Updating firmware J Link compiled Oct 26 2665 14 41 31 ARM Rev 5 Replacing firmware J Link compiled NOU 17 2665 16 12 19 ARM Rev 5 Firmware update successful 5 Waiting for new firmware to boot DLL version U2 70a compiled Oct 25 2005 14 02 40 Firmware J Link compiled Oct 26 2005 14 41 31 ARM Rev 5 Hardware U5 6 S N UTarget 0 0000 Speed set to 30 kHz J Link gt In the screenshot e The red box identifies the new firmware e The green box identifies the old firmware which has been replaced J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 302 CHAPTER 11 Background information J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 303 Chapter 12 Designing the target board for trace This chapte
240. k supporting the Ethernet interface SEGGER provides a GUI based tool called J Link Configurator The J Link Configurator is part of the J Link software and docu mentation package and can be used free of charge DLL J Link Server via Server via SWD 34ink RDI Config J dink TCP IP Server uh J Mem License Agreement 93 Remove J Link ARM V4 35e 4 5 1 127 Configure J Links using the J Link Configurator A J Link can be easily configured by selecting the appropriate J Link from the emula tor list and using right click Configure 13 SEGGER J Link Configuration V4 35e beta 0 1 2 4 S 6 8 8 1 0 J Link J Trace UM08001 J Link ARM Pro V3 00 Link ARM Pro V3 00 J Link ARM Pro V3 00 J Link ARM Pro V3 00 J Link ARM Pro V3 00 J Link ARM Pro V3 00 J Link ARM Pro V3 00 J Link ARM Pro V3 00 J Link ARM Pro V3 00 J Link ARM Pro V3 00 J Link ARM Pro V3 00 173001007 173001008 173001040 173001041 173001042 173001043 173001044 173001045 173001046 173001048 173001049 192 168 6 6 192 168 6 5 192 168 8 4 192 168 8 7 192 168 8 6 192 168 8 2 192 168 8 3 192 168 8 5 192 168 4 253 192 168 6 2 192 168 6 4 00 22 C7 E 00 22 C7 02 04 12 00 22 7 02 04 13 00 22 7 02 04 14 00 22 7 02 04 15 00 22 7 02 04 16 00 22 C7 02 04 18 00 22 7 02 04 19 2011 16 37 2011 Sep 6 16
241. l J Flash Stand alone flash programming application For more informa tion about J Flash please refer to J Flash ARM User s Guide 0 08003 J Link SWO Viewer Free of charge utility for J Link Displays the terminal output of the target using the SWO pin Can be used in parallel with a debugger or stand alone J Link SWO Ana lyzer Command line tool that analyzes SWO RAW output and stores it into a file JTAGLoad Command line tool that opens an file and sends the data it via J Link J Trace to the target J Link Configurator GUI based configuration tool for J Link Allows configuration of USB identification as well as TCP IP identification of J Link For more information about the J Link Configurator please refer to J Link Configurator on page 127 RDI support Provides Remote Debug Interface RDI support This allows the user to use J Link with any RDI compliant debugger Processor specific tools Free command line tools for handling specific processors Included are STR9 Commander and STM32 Unlock Table 3 1 J Link J Trace related software a Full featured J Link PLUS PRO ULTRA or an additional license for J Link base model required J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 63 3 2 J Link Commander Command line tool J Link Commander JLink exe is tool that be used for verifying proper insta
242. l Open Sy JLinkRDI JLinkArm dll J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 214 8 RDI 3 Now J Link RDI is available in the Target Environments list Choose Target Target Environments Target ARM TP 1 551 CMTooNCA SRVT DLL 1 0 0 19 ARMUL 151 C ToolKC armulate dll 1 4 0 89 Flemave J Link 1 51 C AJLinkRDIMJLinkADI dll Rename Save Configure AAA Segger JLink ARM JTAG Cancel Help 4 Select J Link and press OK to connect to the target via J Link For more informa tion about the generic setup of J Link RDI please refer to Configuration on page 226 After downloading an image to the target board the debugger window looks as follows AXD ARM 1 C work emb0S emb0S_ARM_RYDS21 start CPU_STR71X SAMPLE Main_LED c Eile Search Processor Views SystemViews Execute Options Window Help 5 ra HIDE alee magaalaga al E ARM 1 Registers p 22 void Taskl void 4 Register Value 23 while 1 current 45 4 24 LED_ToggleLED1 ro 0x20001580 25 05 Delay 200 irl 0x20001588 26 i 27 2 0 00000150 P3 0 00001 80 0 2000063 prs 0 00001 70 29 31 6 0 00000000 000000000 000000000 000000000 0
243. l lation of the USB driver and to verify the connection to the target CPU as well as for simple analysis of the target system It permits some simple commands such as memory dump halt step go etc to verify the target connection Program Enid Lue JLink exe lt 3 2 1 Command line options J Link Commander can be started with different command line options for test and automation purposes In the following the command line options which are available for J Link Commander are explained CommandFile Selects a command file and starts J Link Commander in batch mode The batch mode of J Link Commander is similar to the execution of a batch file The command file is parsed line by line and one command is executed at a time Syntax CommanderScript lt CommandFilePath gt Example See Using command files on page 64 Device Pre selects the device J Link Commander shall connect to For some devices J Link already needs to know the device at the time of connecting since special handling is required for some of them For a list of all supported device names please refer to http www segger com jlink_supported_devices html Syntax Device lt DeviceName gt Example JLink exe Device STM32F103ZE If Selects the target interface J Link shall use to connect to the target By default J Link Commander first tries to connect to the target using the target interface which is currently selected in the J Link
244. lash memory Without this feature the number of breakpoints which can be set in flash is limited to the number of hardware breakpoints typically two for ARM 7 9 up to six for Cortex M For more information about flash breakpoints please refer to Flash breakpoints on page 201 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 26 CHAPTER 1 Introduction 1 3 2 J Link J Link is a JTAG emulator designed for ARM cores It connects via USB to a PC running Microsoft Windows 2000 or later For a complete list of all operating systems which are supported please refer to Supported OS on page 23 J Link has a built in 20 pin JTAG connector which is compatible with the standard 20 pin connector defined by ARM 1 3 2 1 Additional features e Direct download into flash memory of most popular micro controllers supported Full speed USB 2 0 interface Serial Wire Debug supported Serial Wire Viewer supported Download speed up to 1 MBytes second Debug interface JTAG SWD speed up to 15 MHz RDI interface available which allows using J Link with RDI compliant software The actual speed depends on various factors such as JTAG SWD clock speed host CPU core etc 1 3 2 2 Specifications The following table gives an overview about the specifications general mechanical electrical for J Link General For a complete list of all operating sys Supported OS tems whi
245. m32 cmd exe elem eem S EGGER J Link Commander 04 80 for help E 20 2013 19 38 62 4 80 compiled Dec 20 2013 19 3 3 E J Link 09 compiled Dec 11 2013 19 z v9 00 aac s GDB RDI FlashBP FlashDL JFlash with ID x2BAG1477 M4 gt tt endian lt BP gt slots and 2 literal slots Total IRLen 4 d Target interface J Link The J Link PLUS in the example above contains licenses for all features Note that GDB and FlashDL feature are no longer required 2 2 2 Key based license When using a key based license a license key is required in order to enable the fea ture License keys can be added via the J Link License Manager How to enter a license via the license manager is described in Licensing on page 203 Like the built in license the key based license is only valid for one J Link so if another J Link is used it needs a separate license J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 50 CHAPTER 2 Licensing 2 3 Legal use of SEGGER J Link software The software consists of proprietary programs of SEGGER protected under copyright and trade secret laws All rights title and interest the software are and shall remain with SEGGER For details please refer to the license agreement which needs to be accepted when installing the software The text of the license agreement is also available as entry in the start menu after installing the software Us
246. mbH amp Co KG 195 lt DeviceName gt is the name of the device for which download into internal flash mem ory shall be enabled For a list of supported devices please refer to Supported devices on page 190 For more information about the GDB monitor commands please refer to J Link GDB Server on page 66 6 4 5 J Link Commander J Link Commander supports downloading bin files into internal flash memory of ular microcontrollers In the following it is explained which steps are necessary to prepare J Link Commander for download into internal flash memory 6 4 5 1 Preparing J Link Commander for flash download To configure J Link Commander for flash download simply select the connected device by typing in the following command exec device lt DeviceName gt lt DeviceName gt is the name of the device for which download into internal flash mem ory shall be enabled For a list of supported devices please refer to Supported devices on page 190 In order to start downloading the binary data file into flash please type in the following command loadbin lt filename gt lt addr gt lt Filename gt is the path of the binary data file which should be downloaded into the flash lt Addr gt is the start address the data file should be written to 15 J Link Commander JTAG speed gt J Lin eed 40 4000 kHz 5 1 79 CPSR 20000007F lt S mode THUMB FIQ dis gt 66262D66 aug R3 66600
247. mbedded Trace Buffer added 25 070516 SK Chapter Working with J Link J Trace Section Reset strategies in detail Software for Analog Devices ADuC7xxx MCUs updated Software for ATMEL AT91SAM7 MCUs added Chapter Device specifics Section Analog Devices added Section ATMEL added 24 070323 SK Chapter Setup Uninstalling the J Link driver updated Supported ARM cores updated 23 070320 SK Chapter Hardware Using the JTAG connector with SWD updated 22 070316 SK Chapter Hardware Using the JTAG connector with SWD added 21 070312 SK Chapter Hardware Differences between different versions supplemented 20 070307 SK Chapter J Link J Trace related software J Link GDB Server licensing updated 19 070226 SK Chapter J Link J Trace related software updated and reorganized Chapter Hardware List of OEM products updated 18 070221 SK Chapter Device specifics added Subchapter Command strings added 17 070131 SK Chapter Hardware Version 5 3 Current limits added Version 5 4 added Chapter Setup Installating the J Link USB driver removed Installing the J Link software and documentation pack added Subchapter List of OEM products updated OS support updated 16 061222 SK Chapter Preface Company description added J Link picture changed
248. merated and is in Idle mode GREEN switched off for 10ms once per second J Link heart beat Will be activated after the emulator has been in idle mode for at least 7 seconds ORANGE Reset is active on target RED flashing at 1 Hz Emulator has a fatal error This should not normally hap pen Table 5 2 J Link single color LED main color indicator J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 139 5 2 2 Input indicator Some newer J Links such as the J Link Pro Ultra come with additional input output Indicators The input indicator is used to give the user some information about the status of the target hardware 5 2 2 1 Bi color input indicator Indicator status Meaning GREEN Target voltage could be measured Target is connected ORANGE Target voltage could be measured RESET is pulled low active on target side RESET is pulled low active on target side If no target is RED connected reset will be also active on target side Table 5 3 J Link bi color input indicator 5 2 3 Output indicator Some newer J Links such as the J Link Pro Ultra come with additional input output Indicators The output indicator is used to give the user some information about the emulator to target connection 5 2 3 1 Bi color output indicator Indicator status Meaning OFF Target power supply via Pin 19 is not active GREEN
249. mitation can NOT be lifted if you would like to use J Link with a device from an other manufacturer you need to buy a separate J Link Licenses Licenses for RDI J Link FlashDL and FlashBP are included Other licenses can be added per 2 5 2 Atmel SAM ICE SAM ICE is an OEM version of J Link sold by Atmel Limitations SAM ICE works with Atmel devices only This limitation can NOT be lifted if you would like to use J Link with a device from an other manufacturer you need to buy a separate J Link Licenses Licenses for RDI and GDB Server are included Other licenses can be added J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 57 2 5 5 Digi Link Digi JTAG Link is OEM version of J Link sold by Digi Interna tional Limitations Digi JTAG Link works with Digi devices only This limitation can NOT be lifted if you would like to use J Link with a device from an other manufacturer you need to buy a separate J Link Licenses License for GDB Server is included Other licenses can be added 2 5 4 IAR J Link J Link KS IAR J Link IAR J Link KS are OEM versions of J Link sold by IAR Limitations IAR J Link IAR J Link KS can not be used with Keil MDK This lim itation can NOT be lifted if you would like to use J Link with Keil MDK you need to buy a separate J Link IAR J Link does not sup port kickstart power Licenses No licenses are includ
250. n flash loaders The flash loaders can of course be used if they match your flash configura tion which is something that needs to be checked with the vendor of the debugger 11 4 4 4 Write your own flash loader Implement your own flash loader using the functionality of the JLinkARM dll as described above This can be a time consuming process and requires in depth knowl edge of the flash programming algorithm used as well as of the target system J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 300 11 Background information 11 5 J Link J Trace firmware The heart of J Link J Trace is a microcontroller The firmware is the software exe cuted by the microcontroller inside of the J Link J Trace The J Link J Trace firm ware sometimes needs to be updated This firmware update is performed automatically as necessary by the JLinkARM dll 11 5 1 Firmware update Every time you connect to J Link J Trace JLinkARM dll checks if its embedded firm ware is newer than the one used the J Link J Trace The DLL will then update the firmware automatically This process takes less than 3 seconds and does not require a reboot It is recommended that you always use the latest version of JLinkARM dll c JLink exe eiat SEGGER J Link Commander 02 68 01 Compiled 14 62 49 Oct 25 2005 J Link compiled Oct 26 2005 14 41 31 ARM Rev 5 J Link compiled NOU 17 2005 16 12 19 A
251. n touch with us End users may be liable for illegal use of J Link software with clones J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 61 Chapter 3 J Link software and documenta tion package This chapter describes the contents of the J Link software and documentation pack age which can be downloaded from www segger com J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG J Link software and documentation package Software overview The J Link software and documentation package which is available for download from http www segger com jlink software html includes some applications to be used with J Link It also comes with USB drivers for J Link and documentations in pdf format Software Description JLink Commander Command line tool with basic functionality for target analysis J Link GDB Server The J Link GDB Server is a server connecting to the GNU Debugger GDB via TCP IP It is required for toolchains using the GDB protocol to connect to J Link J Link GDB Server command line ver sion Command line version of the J Link GDB Server Same func tionality as the GUI version J Link Remote Server Utility which provides the possibility to use J Link J Trace remotely via TCP IP J Mem Memory Viewer Target memory viewer Shows the memory content of a run ning target and allows editing as wel
252. nd IAR Embedded Workbench for ARM 4 404 DLL V3 20h in VA40ANARMbin IAR Embedded Workbench for ARM 4 414 DLL V3 80c in C ToolKCMARARM_V4414 4RM bin IAR Embedded Workbench for ARM 4 424 DLL V3 84 in V442ANARMbin vi IAR Embedded Workbench for ARM 4 314 DLL V3 82 in V431ANARMbin IAR Embedded Workbench for ARM 4 304 DLL V3 80c in C Tool CMARARM_V4304 4RM bin IAR Embedded Workbench for ARM 5 10 DLL V3 78d in ENTooNCMARNARM V5TONARMbin IAR Embedded Workbench for ARM 5 20 DLL V3 85f in C NTooNCMARNSARM 520 betaB85ARMbin IAR Embedded Workbench for ARM 5 20 DLL V3 85j in C NTooNCXARNARM V520 beta302NARMbin IAR Embedded Workbench for ARM 5 11 DLL V3 78 in NTooNCMARNSARM V511 BETA B 7XARMbin IAR Embedded Workbench for ARM 5 11 DLL V3 85h in C T ooh CMAR SARM V511 3799V4RMbin Select All Select None Select the ones you would like to replace by this version The previous version will be renamed and kept in the same folder allowing manual undo In case of doubt do not replace existing DLL s fou can always perform this operation at a later time via start menu taa J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 132 CHAPTER 4 Setup 4 7 3 Determining the version of JLink DLL To determine which
253. necting multiple J Links J Traces to your PC 151 5 6 1 How does it work Deere aea ae uox Re X MER e X a Ys 151 5 7 J Link control panels aeree oo prier or E HARE Er Ex 153 5 7 1 pb a 153 5 8 Reset strategies eese n cr da 159 5 8 1 Strategies for ARM 7 9 4 666 nnn 159 5 8 2 Strategies for Cortex M 0 eene 161 5 9 Using DCC for memory amp eee n 164 5 9 1 What is required seni take eve Rouge RETO data eda AERE C dA a 164 5 9 2 Target DCC handler eere eret ert e net OR needs Le Pee ER Rana 164 5 9 3 Target DCC abort handl r iiri eet ir EE IR EX ELI ala E EP IR ERR REC ina 164 5 10 SEE 66 EE 165 5 10 1 Actions that be customized 1 2 6 165 5 10 2 Script file API functions ene renes e ERE RA n 165 5 10 3 Global DLE variables iseni ia ian Tima a ERATE PR Er 169 5 10 4 Global DLE constants encre ee nec Aa 172 5 10 5 Script file languag6e niri enen aaa Er ak et aie ir Fa dee Uh REX VERE A UR Me Ru ca 173 5 10 6 Script file writing example 1 1 66
254. ner mem driver Properties 4 2 2 Uninstalling the J Link USB driver If J Link J Trace is not properly recognized by Windows and therefore does not enu merate it makes sense to uninstall the J Link USB driver This might be the case when e The LED on the J Link J Trace is rapidly flashing e The J Link J Trace is recognized as Unknown Device by Windows To have a clean system and help Windows to reinstall the J Link driver follow this procedure 1 Disconnect J Link J Trace from your PC 2 Open the Add Remove Programs dialog Start Settings Control Panel gt Add Remove Programs and select Windows Driver Package Segger J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 123 jlink USB click the Change Remove button Ea Add Remove Programs 3 Confirm the uninstallation process Uninstall Driver Package Q J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 124 4 Setup 4 3 Setting up the IP interface Some emulators of the J Link family have or future members will have an additional Ethernet interface to communicate with the host system These emulators will also come with a built in web server which allows configuration of the emulator via web interface In addition to that you can set a default gateway for the emulator which allows using it even in large intranets
255. nformation pins between ETM archi tecture versions on page 283 19 TDI Test data input from run control to the JTAG port Trace signal For more information please refer to 20 Trace signal 10 Assignment of trace information pins between ETM archi tecture versions on page 283 21 nTRST Active low JTAG reset Table 10 6 JTAG Trace connector pinout J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 282 10 Target interfaces and adapters PIN SIGNAL Description 22 Trace signal 9 23 Trace signal 20 24 Trace signal 8 25 Trace signal 19 26 Trace signal 7 27 Trace signal 18 28 Trace signal 6 29 Trace signal 17 Trace signals For more information please refer to 30 Trace signal 5 Assignment of trace information pins between ETM archi 31 Trace signal 16 tecture versions on page 283 32 signal 4 33 Trace signal 15 34 Trace signal 3 35 Trace signal 14 36 Trace signal 2 37 signal 13 38 signal 1 Table 10 6 JTAG Trace connector pinout J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 283 10 2 3 Assignment of trace information pins between ETM architecture versions The following table show different names for the trace signals depending on the ETM architecture version
256. ng Microsoft Windows 2000 Windows XP Windows 2003 Windows Vista or Windows 7 J Link has a built in 20 pin JTAG connector which is compat ible with the standard 20 pin connector defined by ARM Licenses Comes with built in licenses for all J Link related software prod ucts J Link FlashDL FlashBP RDI J Link GDB Server and J Flash J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 245 J Trace J Trace is a JTAG emulator designed for ARM cores which includes trace ETM support It connects via USB to a PC run ning Microsoft Windows 2000 Windows XP Windows 2003 Windows Vista or Windows 7 J Trace has a built in 20 pin JTAG connector and a built in 38 pin JTAG Trace connector which is compatible with the standard 20 pin connector and 38 pin con 53 nector defined by ARM Licenses Comes with built in licenses for flash download 2 4 6 J Trace for Cortex M J Link J Trace UM08001 J Trace for Cortex M is JTAG SWD emulator designed for Cor tex M cores which include trace ETM support J Trace for Cor tex M can also be used as a regular J Link and it also supports ARM7 9 cores Please note that tracing on ARM7 9 targets is not supported by J Trace for Cortex M In order to use ETM trace on ARM7 9 targets a J Trace is needed Licenses Comes with built in licenses for flash download 2004 2014 SEGGER Microcontroller GmbH amp Co KG 54 2
257. ng tool for microcontrollers with on chip or external Flash memory and ARM core Flasher ARM is designed for programming flash targets with the J Flash soft ware or stand alone In addition to that Flasher ARM has all of the J Link functionality Flasher ARM connects via USB or via RS232 interface to a PC running Microsoft Windows 2000 Win dows XP Windows 2003 or Windows Vista Flasher ARM has a built in 20 pin JTAG connector which is compatible with the standard 20 pin connector defined by ARM Licenses Comes with built in licenses for flash download and J Flash 3 mi J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 56 CHAPTER 2 Licensing 25 J Link OEM versions There are several different OEM versions of J Link on the market The OEM versions look different but use basically identical hardware Some of these OEM versions are limited in speed some of these can only be used with certain chips and some of these have certain add on features enabled which normally requires license In any case it should be possible to use the J Link software with these OEM versions How ever proper function cannot be guaranteed for OEM versions SEGGER Microcontrol ler does not support OEM versions support is provided by the respective OEM 2 5 1 Analog Devices mIDASLink mIDASLink is an OEM version of J Link sold by Analog Devices Limitations mIDASLink works with Analog Devices chips only This li
258. ning values for scan chain configuration When do I need to configure the scan chain If only one device is connected to the scan chain the default configuration can be used In other cases J Link J Trace may succeed in automatically recognizing the devices on the scan chain but whether this is possible depends on the devices present on the scan chain How do I configure the scan chain 2 values need to be known e position of the target device in the scan chain total number of bits in the instruction registers of the devices before the tar get device IR len The position can usually be seen in the schematic the IR len can be found in the manual supplied by the manufacturers of the others devices ARM7 ARM9 have an IR len of four Sample configurations The diagram below shows a scan chain configuration sample with 2 devices con nected to the JTAG port Device 0 Device 1 TDO TDI TDO Examples The following table shows a few sample configurations with 1 2 and 3 devices in dif ferent configurations Device 0 Device 1 Device 2 Chip IR len Chip IR Chip IR len Position IRon ARM 4 s 0 0 ARM 4 Xilinx 8 0 0 Xilinx 8 ARM 4 1 8 Xilinx 8 Xilinx 8 ARM 4 2 16 Table 5 5 Example scan chain configurations J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 144 5 3 4 1
259. nnector 9 pin 0 05 Samtec FTSH connector JTAG SWD Interface Electrical Table 1 4 J Link Lite Cortex M specifications J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 33 Power supply USB powered Max 50mA Target Supply current Target interface voltage Vir 3 3V Target supply voltage 4 5V 5V Target supply current Max 300 LOW level input voltage Vr Max 40 of Vir HIGH level input voltage Min 60 of Vig JTAG SWD Interface Timing Data input rise time T qj Max 20ns Data input fall time Trai Max 20ns Data output rise time Trao Max 10ns Data output fall time Max 10ns Clock rise time Max 10ns Clock fall time Tg Max 10 5 Table 1 4 J Link Lite Cortex M specifications 1 3 7 J Trace ARM J Trace is a JTAG emulator designed for ARM cores which includes trace ETM support It connects via USB to a PC run ning Microsoft Windows 2000 or later For a complete list of all operating systems which are supported please refer to Sup ported OS on page 19 J Trace has a built in 20 pin JTAG con nector and a built in 38 pin JTAG Trace connector which are compatible to the standard 20 pin connector and 38 pin con nector defined by ARM 1 3 7 1 Additional features e Supports tracing on ARM7 9 targets e JTAG speed up to 12 MHz e Download speed up to 420 Kby
260. not recommended Background information USB address really means changing the USB Product Id PID The following table shows how J Links enumerate in the different identification modes Identification PID Serial number Serial number is real serial number of the J Link or user assigned USB address 0 Deprecated 0 0101 123456 USB address 1 Deprecated 0x0102 123456 USB address 2 Deprecated 0x0103 123456 USB address 3 Deprecated 0x0104 123456 Table 4 1 J Link enumeration in different identification modes Serial number default 0x0101 4 6 1 Connecting to different J Links connected to the same host PC via USB In general when having multiple J Links connected to the same PC the J Link to connect to is explicitly selected by its serial number Most software debuggers pro vide an extra field to type in the serial number of the J Link to connect to The following screenshot shows the connection dialog of the J Flash software Project settings J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 130 4 following screenshot shows the connection dialog of EWARM Options for node Generic Cortex M General Options C C Compiler Assembler Output Converter Custom Build Build Actions Linker Debugger Simulator Angel GDB Server IAR ROM monitor J Link J Trace TI Stellaris Macraigor PE micro RDI
261. nsigned char 0x40020000 0x08 define FCCOB8 volatile unsigned char 0x40020000 0 0 void ConfigureDataFlash void KR KKK KKK KKK KKK KEK KEK KKK KKK KEK KKK KEK KEK KE KKK KKK KKK KKK KEK KEK KEKE KK KEKE KK KEKE ko ko ko ko ko ko ConfigureDataFlash Notes Needs to be located in RAM since it performs flash operations which make instruction fetching from flash temporarily not possible void ConfigureDataFlash void 1 unsigned char v Read out current configuration first FSTAT 0x70 Clear error flags in status register FCCOBO 0x03 Read resource FCCOB1 0x80 Read from data flash IFR area with offset OxFC 0x8000FC FCCOB2 0x00 FCCOB3 OxFC FCCOB8 0x00 Select IFR area to be read FSTAT 0x80 Start command execution while FSTAT amp 0x80 0 Wait until flash controller has finished 7 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 251 Check current data flash amp EEPROM config Kd v FCCOB6 IFR offset OxFD if v OxFF EEPROM data set size already configured return v FCCOB7 IFR offset OxFC if v OxFF FlexNVM partition code already configured return eh Configure EEPROM size and data flash size via the program partition command FCCOBO 0x80 Program partition FCCOB4 Ox3F EEPROM data size code 0 KB EEPR
262. nsing Max 90 rH Size without cables 123mm x 68mm x 30mm Weight without cables 120g Mechanical USB interface USB 2 0 Hi Speed JTAG SWD 20 pin Target interface 14 pin adapter available JTAG SWD Trace 19 pin JTAG SWD Interface Electrical USB powered Max 50mA Target Supply current Power supply Target interface voltage Vir 1 2V 5V Target supply voltage 4 5V if powered with 5V on USB Target supply current Max 300mA LOW level input voltage Max 40 of Vir HIGH level input voltage Min 60 of Vir JTAG SWD Interface Timing Data input rise time Max 20ns Data input fall time Trai Max 20ns Data output rise time Trao Max 10ns Data output fall time Max 10ns Clock rise time Max 3ns Table 1 7 J Trace for Cortex M3 specifications J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 37 Clock fall time Max 3ns Trace Interface Electrical USB powered Power supply Max 50mA Target Supply current Target interface voltage Vip 1 2V 5V Voltage interface low pulse Viri Max 40 of Vir Voltage interface high pulse Vy Min 60 of Vir Trace Interface Timing TRACECLK low pulse width Ty Min 2ns TRACECLK high pulse width Twp Min 2ns Data rise time 4 Max 3ns Data fall time M
263. nstalled and your J Link J Trace is connected to your com puter the device manager should list the J Link USB driver as a node below Univer sal Serial Bus controllers as shown in the following screenshot De e Manage JOf x ain Yew e Sm 9 9 ER VMBASIC Batteries Computer Disk drives Display adapters 23 DVD CD ROM drives 52 Floppy disk controllers amp 9 Floppy disk drives amp IDE ATA ATAPI controllers E Keyboards A Mice and other pointing devices EF Network adapters 7 Ports COM amp LPT qr Sound video and game controllers System devices Universal Serial Bus controllers Intel 823714B EB PCI to USB Universal Host Controller J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 122 CHAPTER 4 Setup Right click on the driver to open a context menu which contains the command Prop erties If you select this command a J Link driver Properties dialog box is opened and should report This device is working properly J Link driver Properties Use tis device enable If you experience problems refer to the chapter Support and FAQs on page 307 for help You can select the Driver tab for detailed information about driver provider version date and digital sig
264. nt 0O0xEOO000E80 ITM Trace Control Reg f 5k kk kk sk kc tec ke he ke e ek ke ck kk EERE hee ke e kkk kkk kkk RE RRR EKER EER KR k kk kkk k k kk k k k k k KK SWO PrintChar Function description Checks if SWO is set up If it is not return to avoid program hangs if no debugger is connected If it is set up print a character to the ITM_STIM register in order to provide data for SWO Parameters Chacracter to printed Notes Additional checks for device specific registers can be added Af void SWO_PrintChar char c Check if ITM_TCR ITMENA is set if amp 1 0 return Check if stimulus port is enabled if ITM_ENA amp 1 0 return Wait until STIMx is ready then send data 7 while ITM 5 U8 amp 1 0 ITM 5 U8 c J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 109 E kkkkkkk kc e ke e ke e ek ke EEK EER kk kkk kkk kkk kk SWO PrintString Function description Print a string via SWO void SWO_PrintString const char s Print out character per character while s SWO_PrintChar 5 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 110 CHAPTER 3 J Link software and documentation package 3 8 SWO Analyzer SWO Analyzer SwoAnalyzer exe
265. nuals n Processor Specific Utilities J Release Notes 4 Back Connect to the J Link J Trace via J Link commander J Link Commander can be used to verify a connection to the J Link can be estab lished as follows Start J Link Commander From within J Link Commander enter ip tunnel lt SerialNo gt If the connection was successful it should look like in this screenshot 2 J Link ARM V4 54 4 SEGGER J Link Commander U4 54 for help Compiled Sep 11 2012 18 33 18 Can not connect to J Link via USB J Link gt ip tunnel 59888808 Connecting to tunnel 5900000A DLL version 04 54 compiled Sep 11 2012 18 32 59 Firmware J Link 09 compiled Oct 2 2012 09 11 43 Hardware 9 0 S N 59000000 UTarget 3 3120 Info 11 9 IRPrint 0 0011 Info Found Cortex M4 Little endian Info TPIU fitted Info EIM fitted Info FPUnit 6 code BP slots and 2 literal slots Found 2 JTAG devices Total IRLen 9 Id x4BA80477 IRLen 04 IRPrint Axi CoreSight JTAG DP CARM 1 Id 6x66413641 IRLen 05 IRPrint xi STM32 Boundary Scan Cortex M4 identified JTAG speed 100 kHz J Link J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 101 Troubleshooting Solution 1 Make sure the Remote server is not blocked by any firewall Problem Remote server cannot connect to tunnel server 2 Make sure port 19020 is not blocked by any firewall 3 Cont
266. oard 304 12 1 1 AVOIGINGStUDS 304 12 1 2 Minimizing Signal Skew Balancing PCB Track 304 12 1 3 Minimizing Crosstalk en Ferte a 304 12 1 4 Using impedance matching and termination 0 4 4 304 12 2 Terminating the trace 0 666 nnn 305 12 2 1 Rules for series terminators 22 2 4 mener 305 12 3 Signal requirerments d per rea E aaa HD vi IEEE TUR See 306 S ppot and PAGS ou SUP ra o Ct e cpu C MR p Ep RM I Idem BUT 307 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 20 13 1 5 308 13 1 1 Test environment ooi ep PN YR eN 308 13 2 TOUDIESHOOUING RE RE yea RUE oe 309 13 2 1 General seen nn nnn 309 13 2 2 Typical problem scenarios 1 4 6 6 nemen mense nnn nnn 309 13 3 Contacting SuppOTt ii rear pre yir pris e ptu purae gr au
267. ocated in RAM What is special about software breakpoints in flash Flash breakpoints allows setting of an unlimited number of breakpoints even if the user application is not located in RAM On modern microcontrollers this is the stan dard scenario because on most microcontrollers the internal RAM is not big enough to hold the complete application When replacing instructions in flash memory this requires re programming of the flash which takes much more time than simply replacing a instruction when debugging in RAM The J Link flash breakpoints feature is highly optimized for fast flash programming speed and in combination with the instruction set simulation only re programs flash is absolutely necessary which makes debugging in flash using flash breakpoints almost as flawless as debugging in RAM What performance can expect Flash algorithm specially designed for this purpose sets and clears flash breakpoints extremely fast on microcontrollers with fast flash the difference between software breakpoints in RAM and flash is hardly noticeable How is this performance achieved We have put a lot of effort in making flash breakpoints really usable and convenient Flash sectors are programmed only when necessary this is usually the moment exe cution of the target program is started A lot of times more then one breakpoint is located in the same flash sector which allows programming multiple breakpoints by programming just a single secto
268. ode will be more reliable but very slow due to the high number of USB Ethernet transactions It simply boils down to The best solution is having intelligence in the emulator itself J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 43 1 6 2 1 Limitations of PC side implementations e Instability especially on slow targets Due to the fact that a lot of USB transactions would cause a very bad perfor mance of J Link on PC side implementations the assumption is made that the CPU Debug interface is fast enough to handle the commands requests without the need of waiting So when using the PC side intelligence stability can not be guaranteed in all cases especially if the target interface speed JTAG SWD is significantly higher than the CPU speed e Poor performance Since a lot more data has to be transferred over the host interface typ USB the resulting download speed is typically much lower than for implementations with intelligence in the firmware even if the number of transactions over the host interface is limited to a minimum fast mode e No support Please understand that we can not give any support if you are running into prob lems when using a PC side implementation Note Due to these limitations we recommend to use PC side implementations for evaluation only J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 44 CHAPTER 1 Introduction 1 6 3 Firmware
269. olatile unsigned int 0xE0040304 Formatter and flush N Control Register U32 ITMPort 0 The stimulus port from which SWO data is received and displayed U32 TargetDiv 1 Has to be calculated according to N the CPU speed and the output baud rate static void EnableSWO U32 StimulusRegs Enable access to SWO registers DEMCR 1 lt lt 24 ITM LSR OxC5ACCE55 Initially disable ITM and stimulus port To make sure that nothing is transferred via SWO when changing the SWO prescaler etc Stimulusregs ITM_ENA StimulusRegs amp 1 lt lt ITMPort ITM_ENABLE StimulusRegs Disable ITM stimulus port ITM_TCR 0 Disable ITM Initialize SWO prescaler etc TPIU_SPPR 0x00000002 Select NRZ mode TPIU_ACPR TargetDiv 1 Example 72 48 1 5 MHz ITM_TPR 0x00000000 DWT_CTRL 0x400003FE FFCR 0x00000100 Enable ITM and stimulus port ITM_TCR 0x1000D Enable ITM StimulusRegs 1 lt lt _ITMPort Enable ITM stimulus port 3 7 4 Target example code for terminal output BRR KERR ERE RRR kc kc k EEE ERR EKER kkk kkk kk kk kkk kk kk kk kkk SEGGER MICROCONTROLLER GmbH amp Co KG Solutions for real time microcontroller applications i ACKCKCkCk ck ck ck kck KkCk ckCk KKK KKK ck ck ck ck ck ck ck ok ok ok ok okok ok ck
270. oller GmbH amp Co KG 242 92 ATMEL CHAPTER 9 Device specifics J Link has been tested with the following ATMEL devices 915 2 915 4 AT91SAM3A8C AT91SAM3N1A AT91SAM3N1B AT91SAM3N1C AT91SAM3N2A AT91SAM3N2B AT91SAM3N2C AT91SAM3N4A AT91SAM3N4B AT91SAM3N4C AT91SAM3S1A AT91SAM3S1B AT91SAM3S1C AT91SAM3S2A AT91SAM3S2B AT91SAM3S2C AT91SAM3S4A AT91SAM3S4B AT91SAM3S4C AT91SAM3U1C AT91SAM3U2C AT91SAM3U4C 915 1 AT91SAM3U2E AT91SAM3UAE AT91SAM3X2C 915 2 AT91SAM3X2G AT91SAM3X2H AT91SAM3X4C AT91SAM3X4E AT91SAM3X4G AT91SAM3X4H AT91SAM3X8C AT91SAM3X8E AT91SAM3X8G AT91SAM3X8H AT91SAM7A3 AT91SAM7L64 AT91SAM7L128 AT91SAM7S16 AT91SAM7S161 915 7532 915 75321 915 7564 915 75128 915 75256 915 75512 915 75 2 915 75 256 AT91SAM7SE512 AT91SAM7X128 AT91SAM7X256 AT91SAM7X512 AT91SAM7XC128 AT91SAM7XC256 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 243 e 915 7 512 e 915 9 128 e AT91SAMOXE256 9 2 1 915 7 9 2 1 1 Reset strategy The reset pin of the device is per default disabled This means that the reset strate gies which rely on the reset pin low pulse on reset do not work per default For this reason a special reset strategy has been made available It is recommended to use this reset strategy This special reset strategy resets
271. oller GmbH amp Co KG 259 9 11 1 2 RDI J Link comes with a device based RDI license for NXP LPC21xx LPC24xx devices This means the J Link RDI software can be used with LPC21xx LPC24xx devices free of charge For more information about device based licenses please refer to License types on page 49 9 11 2 Reset Cortex M3 based devices For Cortex M3 based NXP LPC devices the reset itself does not differ from the one for other Cortex M3 based devices After the device has been reset the core is halted before any instruction is performed For the Cortex M3 based LPC devices this means the CPU is halted before the bootloader which is mapped at address 0 after reset The user should write the memmap register after reset to ensure that user flash is mapped at address 0 Moreover the user have to correct the Stack pointer R13 and the PC R15 manually after reset in order to debug the application 9 11 3 LPC288x flash programming In order to use the LPC288x devices in combination with the J Link flash download feature the application you are trying to debug should be linked to the original flash addr 0x10400000 Otherwise it is user s responsibility to ensure that flash is re mapped to 0x0 in order to debug the application from addr 0x0 9 11 4 LPC43xx devices of the LPC43xx dual core devices One Cortex M4 core and Cor tex MO core For these devices a J Link script file is needed exact file depends on
272. one instruction step will be performed Example gt monitor step 3 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 82 CHAPTER 3 J Link software and documentation package 3 3 3 28 SWO DisableTarget Syntax SWO DisableTarget PortMask 0x01 OxFFFFFFFF Description Disables the output of SWO data on the target Undoes changes from SWO Enable Target and stops J Link to capture it Example Disable captureing SWO from stimulus ports 0 and 1 monitor SWO DisableTarget 3 SWO disabled succesfully 3 3 3 29 SWO EnableTarget Syntax SWO EnableTarget CPUFreq Hz SWOFreq Hz PortMask 0x01 0xFFFFFFFF Mode 0 Description Configures the target to be able to output SWO data and starts J Link to capture it CPU and SWO frequency can be for auto detection If CPUFreq is 0 J Link will measure the current CPU speed If SWOFreq is 0 J Link will use the highest available SWO speed for the selected measured CPU speed Note CPUFreq has to be the speed at which the target will be running when doing SWO If the speed is different from the current speed when issuing CPU speed auto detec tion getting SWO data might fail SWOFreq has to be a quotient of the CPU and SWO speeds and their prescalers To get available speed use SWO GetSpeediInfo PortMask can be a decimal or hexadecimal Value Values starting with the Prefix Ox are handled hexadecimal Example
273. onfiguring to use J Link RDI 1 Start Green Hills Software MULTI integrated development environment Click Con nect Connection Organizer to open the Connection Organizer d Connection rganizer J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 221 2 Click Method New the Connection Organizer dialog Ez Connection Organizer 3 The Create a new Connection Method will be opened Enter a name for your configuration in the Name field and select Custom in the Type list Confirm your choice with the Create button Create New Connection Method 4 The Connection Editor dialog will be opened Enter rdiserv in the Server field and enter the following values in the Arguments field config dll lt FullPathToJLinkDLLs gt Note that JLinkRDI d11 and JLinkARM d11 must be stored the same directory If the standard J Link installation path or another path that includes spaces has been used enclose the path in quotation marks Example config dll C Program Files NSEGGERNJLinkARM V350gNJLinkRDI dll Refer to GHS manual MULTI Configuring Connections for ARM Targets chapter ARM Remote Debug Interface rdiserv Connections for a complete list of pos sible arguments Connection Editor 9 Comet Gees nen J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 222
274. only need to be executed once per debug ses sion Example MAIN_IsFirstIdentify if MAIN IsFirstIdentify 1 R else Eses Table 5 10 Global DLL variables 5 10 4 Global DLL constants Currently there are only global DLL constants to set the global DLL variable cpu If necessary more constants will be implemented in the future 5 10 4 1 Constants for global variable CPU The following constants can be used to set the global DLL variable cpu ARM7TDMI ARM7TDMIR3 ARM7TDMIR4 ARM7TDMIS ARM7TDMISR3 ARM7TDMISR4 ARM9 ARM9TDMIS 920 922 ARM926EJS ARM946EJS J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 966 5 968 5 ARM11 ARM1136 ARM1136J ARM1136JS ARM1136JF ARM1136JFS ARM1156 ARM1176 ARM1176J ARM1176JS ARM1176IF ARM1176JFS CORTEX MO CORTEX M1 CORTEX M3 CORTEX M3R1PO CORTEX_M3R1P1 CORTEX_M3R2P0 CORTEX_M4 CORTEX_A5 8 9 CORTEX_R4 CORESIGHT_AHB_AP CORESIGHT_APB_AP CORESIGHT_JTAG_AP CORESIGHT_CUSTOM_AP 5 10 5 Script file language 173 The syntax of the J Link script file language follows the conventions of the C lan guage but it does not support all expresisons and operators which are supported by the C language In the following the supported operators and expressions are listed 5 10 5 1 Supported Operators The following operators are suppor
275. onstant For a list of all available constants please refer to Global DLL con stants on page 172 Prototype api int CORESIGHT AddAP int Index unsigned int Type Example CORESIGHT AddAP 0 CORESIGHT AHB AP First AP is a AHB AP CORESIGHT AddAP 1 CORESIGHT APB AP Second AP is a APB AP CORESIGHT AddAP 2 CORESIGHT JTAG AP Third AP is a JTAG AP 5 10 3 Global DLL variables The script file feature also provides some global variables which are used for DLL configuration Some of these variables can only be set to some specifc values other ones can be set to the whole datatype with In the following all global variables and their value ranges are listed and described Note All global variables are treated as unsigned 32 bit values and are zero ini tialized Variable Description R W Pre selct target CPU J Link is communicating with Used in InitTarget to skip the core auto detection of J Link This variable can only be set to a known global J Link DLL constant For a list W of all valid values please refer to Global DLL con stants on page 172 Example CPU ARM926EJS Used for JTAG chain configuration Sets the num ber of IR bits of all devices which are closer to JTAG IRPre TDO than the one we want to communicate with R W Example JTAG IRPre 6 Used for JTAG chain configuration Sets the num ber of devices which are closer to TDO than the JTAG DRPre one we want
276. or commands are available For more information about debugging with GDB refer to its online manual available at http sourceware org gdb current onlinedocs gdb A typical startup of a debugging session can be like J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 71 gdb file C temp Blinky elf Reading symbols from C temp Blinky elf done gdb target remote localhost 2331 Remote debugging using localhost 2331 0x00000000 in gdb monitor reset Resetting target gdb load Loading section isr vector size 0x188 lma 0x8000000 Loading section text size 0x568 1 0x8000188 Loading section init array size 0x8 lma 0x80006f0 Loading section fini array size 0x4 lma 0x80006f8 Loading section data size 0x428 lma 0x80006fc Start address 0x8000485 load size 2852 Transfer rate 146 KB sec 570 bytes write gdb break main Breakpoint 1 at 0x800037a file Src main c line 38 gdb continue Continuing Breakpoint 1 main at Src main c 38 38 Cnt 0 gdb Eclipse CDT Eclipse is an open source platform independent software framework which has typi cally been used to develop integrated development environment IDE Therefore Eclipse can be used as C C IDE if you extend it with the CDT plug in http www eclipse org cdt CDT means C C Development Tooling project and is designed to use the GDB as default debugger and works without any problems with the GDB
277. orks with the same PC software Based on the highly optimized and proven J Link it offers even higher speed as well as target power measurement capabilities due to the faster CPU built in FPGA and High speed USB interface It connects via USB to a PC running Microsoft Windows 2000 or later For a complete list of all operating systems which are sup ported please refer to Supported OS on page 19 J link ULTRA fe has a built in 20 pin JTAG SWD connector 7 1 3 31 Additional features Fully compatible to the standard J Link Very high performance for all supported CPU cores Hi Speed USB 2 0 interface Download speed up to 3 MByte second Debug interface JTAG SWD speed up to 15 MHz Serial Wire Debug SWD supported Serial Wire Viewer SWV supported SWO sampling frequencies up to 100 MHz Serial Wire Output SWO supported Target power can be supplied Target power consumption can be measured with high accuracy The actual speed depends on various factors such as JTAG SWD clock speed host CPU core etc 1 3 3 2 Specifications The following table gives an overview about the specifications general mechanical electrical for J link ULTRA All values are valid for J link ULTRA hardware version 1 Note Some specifications especially speed are likely to be improved in the future with newer versions of the J Link software freely available General For
278. ors green red and orange J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 5 2 1 1 CHAPTER 5 Working with J Link and J Trace Single color indicator J Link V7 and earlier Indicator status Meaning GREEN flashing at 10 Hz Emulator enumerates GREEN flickering Emulator is in operation Whenever the emulator is exe cuting a command the LED is switched off temporarily Flickering speed depends on target interface speed At low interface speeds operations typically take longer and the OFF periods are typically longer than at fast speeds GREEN constant Emulator has enumerated and is in Idle mode GREEN switched off for 10ms once per second J Link heart beat Will be activated after the emulator has been in idle mode for at least 7 seconds GREEN flashing at 1 Hz Emulator has a fatal error This should not normally hap pen Table 5 1 J Link single color main indicator 5 2 1 2 Bi color indicator J Link V8 Indicator status Meaning GREEN flashing at 10 Hz Emulator enumerates GREEN flickering Emulator is in operation Whenever the emulator is exe cuting a command the LED is switched off temporarily Flickering speed depends on target interface speed At low interface speeds operations typically take longer and the OFF periods are typically longer than at fast speeds GREEN constant Emulator has enu
279. orted One or more of these devices can be CPU cores the other devices can be of any other type but need to comply with the JTAG standard 5 3 1 1 Configuration The configuration of the scan chain depends on the application used Read JTAG interface on page 140 for further instructions and configuration examples 5 3 2 Sample configuration dialog boxes As explained before it is responsibility of the application to allow the user to config ure the scan chain This is typically done in a dialog box some sample dialog boxes are shown below J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 141 SEGGER J Flash configuration dialog This dialog box can be found at Options Project settings J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 142 CHAPTER 5 Working with J Link and J Trace SEGGER J Link RDI configuration dialog box This dialog can be found under RDI Configure for example in IAR Embedded Work bench For detailed information check the IAR Embedded Workbench user guide J Link RDI Configuration IAR J Link configuration dialog box This dialog box can be found under Project Options f Options for node at91sam7s ek General Options C C Compiler Assembler Output Converter Custom Build Build Actions Linker Debugger Simulator J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 143 5 3 3 Determi
280. ox at the bottom connection e In the Dialog select the J Link which is connected to the target e g JLinkUSB 174200001 Select Debug Hardware x Unknown J LinkUSB 59200005 J Link J LinkLISB 174200001 Unknown JLinkIP 192 168 11 122 J Link Pro Unknown J LinkIP 192 168 6 4 J Link Unknown J LinkIP 192 168 6 1 J Link Unknown J LinkIP 192 168 6 2 J Link ARM e Click e Add the device name to the connection string e g JLinkUSB 174200001 Device J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 134 STM32F103ZG Debug Configurations Create manage and run configurations C C Application C C Attach to Application E C C Postmortem Debugger E C C Remote Application 4 05 5 Debugger Filter platforms TAR 4 DSTRAM_Atmel ATS15AM Jh DStream A DSTREAM flash blinky Mc 96 96 Atmel AT915AM9G2 Iron Python Run eV Tron Python unittest Java Applet 3 Java Application CHAPTER 4 Setup MCBSTRS Evaluation Board E d Jython unittest B Launch Group 0 PyDev Django 43 PyDev Google App Run Python Run Python unittest Remote Java Application Filter matched 32 of 32 items e Click Apply e Inthe Files tab select the application to download e In the Debugger tab select Debug from symbol and enter main or select Debug from entry
281. pe void InitTarget void 5 10 2 Script file API functions In the following the API functions which can be used in a script file to communicate with the DLL are explained J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 166 CHAPTER 5 Working with J Link and J Trace 5 10 2 1 MessageBox Description Outputs a string in a message box Prototype 1___ int MessageBox const char sMsg 5 10 2 2 MessageBox1 Description Outputs a constant character string in a message box In addition to that a given value can be a constant value the return value of a function or a variable is added right behind the string Prototype api int MessageBoxl const char sMsg int v 5 10 2 3 Report Description Outputs a constant character string on stdio Prototype 1___ int Report const char sMsg 5 10 2 4 Report1 Description Outputs a constant character string on stdio In addition to that a given value can be a constant value the return value of a function or a variable is added right behind the string Prototype api int Reporti const char sMsg int v 5 10 2 5 JTAG SetDeviceld Description Sets the JTAG Id of a specified device in the JTAG chain The index of the device depends on its position in the JTAG chain The device closest to has index 0 The Id is used by the DLL to recognize the device Before calling this function please m
282. ple jlinkgdbserver LocalhostOnly 0 Listen on any IP address Linux MAC default jlinkgdbserver LocalhostOnly 1 Listen on localhost only Windows default 3 3 5 8 log Description Starts the GDB Server with the option to write the output into a given log file The file will be created if it does not exist If it exists the previous content will be removed Paths including spaces need to be set between quotes Syntax log LogFilePath Example jlinkgdbserver log C my path to file log 3 3 5 9 logtofile Description Starts the GDB Server with the option to write the output into a log file If no file is given via 1og the log file will be created in the GDB Server application directory Note For the GUI version this setting is persistent for following uses of GDB Server until changed via nologtofile or the GUI Syntax logtofile Example jlinkgdbserver logtofile jlinkgdbserver logtofile log C my path to file log 3 3 5 10 halt Description Halts the target after connecting to it on start og GDB Server For most IDEs this option is mandatory since they rely on the target to be halted after connecting to GDB Server J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 92 CHAPTER 3 J Link software and documentation package Note For the GUI version this setting is persistent for following uses of GDB Server until changed via nohalt or the GUI S
283. pli cation The DCC abort handler allows data aborts caused by memory reads writes via DCC to be handled gracefully If the data abort has been caused by the DCC commu nication it returns to the instruction right after the one causing the abort allowing the application program to continue to run In addition to that it allows the host to detect if a data abort occurred In order to use the DCC abort handler 3 things need to be done Place a branch to DCC Abort at address 0x10 vector used for data aborts e Initialize the Abort mode stack pointer to an area of at least 8 bytes of stack memory required by the handler e Add the DCC abort handler assembly file to the application J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 165 5 10 J Link script files In some situations it it necessary to customize some actions performed by J Link In most cases it is the connection sequence and or the way in which a reset is per formed by J Link since some custom hardware needs some special handling which can not be integrated into the generic part of the J Link software J Link script files are written in C like syntax in order to have an easy start to learning how to write J Link script files The script file syntax does support most statements if else while declaration of variables which are allowed in C but not all of them Moreover there are some statements that are script file specific
284. point Click Apply Start a new debug session with the newly created debug configuration Now the debug session should start and downloaded the application to the tar get J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 135 Chapter 5 Working with J Link and J Trace This chapter describes functionality and how to use J Link and J Trace J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 136 CHAPTER 5 Working with J Link and J Trace 5 11 Connecting the target system 5 1 1 Power on sequence In general J Link J Trace should be powered on before connecting it with the target device That means you should first connect J Link J Trace with the host system via USB and then connect J Link J Trace with the target device via JTAG Power on the device after you connected J Link J Trace to it 5 1 2 Verifying target device connection If the USB driver is working properly and your J Link J Trace is connected with the host system you may connect J Link J Trace to your target hardware Then start JLink exe which should now display the normal J Link J Trace related information and in addition to that it should report that it found JTAG target and the target s core ID The screenshot below shows the output of JLink exe As can be seen it reports a J Link with one JTAG device connected C Program Files SEGGER JLinkARM_ 386 JLink exe SEGGE
285. ports different specific reset strategies for the Cortex M cores All of the following reset strategies are available in JTAG and SWD mode All of them halt the CPU after the reset Note It is recommended that the correct device is selected in the debugger so the debugger can pass the device name to the J Link DLL which makes it possible for J Link to detect what is the best reset strategy for the device Moreover we recom mend that the debugger uses reset type 0 to allow J Link to dynamically select what reset is the best for the connected device 5 8 2 1 Type 0 Normal This is the default strategy It does whatever is the best way to reset the target device If the correct device is selected in the debugger this reset strategy may also perform some special handling which might be necessary for the connected device This for example is the case for devices which have a ROM bootloader that needs to run after reset and before the user application is started especially if the debug interface is disabled after reset and needs to be enabled by the ROM bootloader For most devices this reset strategy does the same as reset strategy 8 does 1 Make sure that the device halts immediately after reset before it can execute any instruction of the user application by setting the vc CORERESET the DEMCR 2 Reset the core and peripherals by setting the SYSRESETREQ bit in the AIRCR 3 Wait for the s RESET ST bit in the pHCSR to first b
286. pra ETC Euren ut 311 13 Frequently Asked Questions sss nennen hee nne nnn nnn 312 14 Glossa y apii Lo peti dad olt id tto dd aod Iu e teh MOI 313 18 Literature and 319 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 21 1 Introduction This chapter gives a short overview about J Link and J Trace J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 22 CHAPTER 1 Introduction 11 Requirements Host System To use J Link or J Trace you need a host system running Windows 2000 or later For a list of all operating systems which are supported by J Link please refer to Supported OS on page 23 Target System A target system with a supported CPU is required You should make sure that the emulator you are looking at supports your target CPU For more information about which J Link features are supported by each emulator please refer to Model comparison on page 25 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 1 2 J Link J Trace be used on the following operating systems J Link J Trace 0 08001 Supported OS Microsoft Windows 2000 Microsoft Windows XP Microsoft Windows XP x64 Microsoft Windows Vista Microsoft Windows Vista x64 Windows 7 Windows 7 x64 Windows 8 Windows 8 x6
287. protocol regarding the register assignement that has been approved by ARM Since IAR EWARM version 5 11 it is possible to use J Link RDI for Cortex M devices because SEGGER and IAR have been come to an agreement regarding the RDI register assignment for Cortex M The following table lists the register assignment for RDI and Cortex M read Assigned register 0 RO 1 R1 2 R2 3 R3 4 RA 5 R5 6 R6 7 R7 8 R8 9 R9 10 R10 11 R11 12 R12 13 MSP PSP depending on mode 14 R14 LR 16 R15 PC 17 XPSR 18 APSR 19 IPSR 20 EPSR 21 IAPSR 22 EAPSR 23 IEPSR 24 PRIMASK 25 FAULTMASK 26 BASEPRI 27 BASEPRI MAX 28 CFBP CONTROL FAULT BASEPRI PRIMASK Table 8 1 Cortex M register mapping for IAR J Link RDI J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 213 8 3 2 ARM AXD ARM Developer Suite ADS 8 3 2 1 Software version JLinkRDI d11 has been tested with ARM s AXD version 1 2 0 and 1 2 1 There should be no problems with other versions of ARM s AXD All screenshots are taken from ARM s AXD version 1 2 0 8 3 2 2 Configuring to use J Link RDI 1 Start the ARM debugger and select Options Configure Target This opens the Choose Target dialog box Choose Target ARM TPA 1 51 CXToohC SRVT DLL ARMUL 1 5 1 C ToolSC armulate dll 2 Press the Add Button to add the JLinkRDI dl
288. ptions are available Allow Allows settings breakpoints while the CPU is running If the CPU needs to be halted in order to set the breakpoint the DLL halts the CPU sets the break points and restarts the CPU Allow if CPU does not need to be halted Allows setting breakpoints while the CPU is running if it does not need to be halted in order to set the breakpoint If the CPU has to be halted the breakpoint is not set Ask user if CPU needs to be halted If the user tries to set a breakpoint while the CPU is running and the CPU needs to be halted in order to set the breakpoint the user is asked if the breakpoint should be set If the breakpoint can be set without halting the CPU the breakpoint is set without explicitly confirmation by the user Do not allow It is not allowed to set breakpoints while the CPU is running J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 156 CHAPTER 5 Working with J Link and J Trace 5 7 1 3 Break Watch In the Break Watch section all breakpoints and watchpoints which are in the DLL internal breakpoint and watchpoint list are shown 13 SEGGER J Link ARM Control panel Ot x General Settings Break watch Log CPU Reas Target Power Sw Device Emulator alej Breakpoints Handie Address Mode Permission Implementation 1 0 0800011 Unknown Flash TBC 2 008000128 Unknown Flash 3 0 08000124 Unknown
289. r The instruction register holds the current instruction and its content is used by the TAP controller to decide which test to perform or which data register to access It consist of at least two shift register cells J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 291 11 1 4 TAP controller The TAP controller is a synchronous finite state machine that responds to changes at the TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry TAP controller state diagram Reset gt tms 1 tms 0 IR Scan DR Scan tms 0 tms 0 Capture DR Capture IR tms 1 tms 0 tms 0 tms 0 Pause DR Pause IR tms 1 tms 0 tmsz1 tms 0 ime Exit2 DR 4 Exit2 IR tms 1 tms 1 Update IR tms 1 tms 0 Update DR M 11 1 4 1 State descriptions Reset The test logic is disabled so that normal operation of the chip logic can continue unhindered No matter in which state the TAP controller currently is it can change into Reset state if TMS is high for at least 5 clock cycles As long as TMS is high the TAP controller remains in Reset state Idle Idle is a TAP controller state between scan DR or IR operations Once entered this state remains active as long as TMS is low DR Scan Temporary controller state If TMS remains low a scan sequence for the selected da
290. r 1 exec map reset exec map exclude 0x10000000 0x3FFFFFFF 5 11 2 2 IAR Embedded Workbench The J Link command strings can be supplied using the C SPY debugger of the IAR Embedded Workbench Open the Project options dialog box and select Debugger Options for node Project General Options C C Compiler Assembler Custom Build alge J Link J Trace J LinkAJ Trace LMI FTDI Macraigor RDI Third Party Driver On the Extra Options page select Use command line options Enter jlink exec command CommandLineOption in the textfield as shown in the screenshot below If more than one command should be used separate the com mands with semicolon ptions for node Project General Options C C Compiler Assembler Custom Build Build Actions J Link J Trace LMI FTDI Macraigor RDI Third Party Driver J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 183 5 12 Switching off CPU clock during debug We recommend not to switch off CPU clock during debug However if you do you should consider the following Non synthesizable cores ARM7TDMI ARM9TDMI ARM920 etc With these cores the TAP controller uses the clock signal provided by the emulator which means the TAP controller and ICE Breaker continue to be accessible even if the CPU has no clock Therefore switching off CPU clock during debug is normally possible if the CPU clock is periodically typically using a reg
291. r Hardware 63 090212 Several corrections Section Hardware Versions Version 8 0 added Chapter Working with J Link and J Trace Section Reset strategies updated Chapter J Link and J Trace related software Section J Link STR91x Commander og Command line tool updated Chapter Device specifics Section ST Microelectronics updated Chapter Hardware updated Chapter Working with J Link 93 920129 19 Section Cortex M3 specific reset strategies Chapter Working with J Link 60 IUTE Me Section Cortex M3 specific reset strategies Chapter Hardware 59 090108 KN Section Target board design for JTAG updated Section Target board design for SWD added Chapter Working with J Link Pro 58 090105 AG Section Connecting J Link Pro the first time updated J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG Revision Date By Explanation Chapter Working with J Link Pro Section Introduction updated 57 081222 Section Configuring J Link Pro via web interface updated Chapter Introduction Section J Link Pro overview updated Chapter Working with J Link Pro Section FAQs added 29 s Chapter Support and FAQs Section Frequently Asked Questions updated 55 081218 Chapter Hardware updated Chapter Working with J Link and J Trace 2 827 AG
292. r The contents of program memory are cached avoiding time consuming reading of the flash sectors A smart combination of soft ware and hardware breakpoints allows us to use hardware breakpoints a lot of times especially when the debugger is source level stepping avoiding re programming the flash in these situations A built in instruction set simulator further reduces the num ber of flash operations which need to be performed This minimizes delays for the user while maximizing the life time of the flash All resources of the ARM microcon troller are available to the application program no memory is lost for debugging J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 203 7 2 Licensing In order to use the flash breakpoints feature separate license is necessary for each J Link For some devices J Link comes with device based license and some J Link models also come with a full license for flash breakpoints but the normal J Link comes without any licenses For more information about licensing itself and which devices have a device based license please refer to Licensing on page 47 7 2 1 Free for evaluation and non commercial use In general the unlimited flash breakpoints feature of the J Link DLL can be used free of charge for evaluation and non commercial use If used in a commercial project a license needs to be purchased when the evaluation is complete There is no time limit on the evaluation
293. r ARM Specifications Introduction core Flasher ARM is Flasher SEGGER www segger com General Supported OS For a complete list of all operating sys tems which are supported please refer to Supported OS on page 19 Mechanical USB interface USB 2 0 full speed Target interface JTAG SWD 20 pin JTAG Interface Electrical Power supply USB powered Max 50mA Target Supply current Target interface voltage Vir 1 2V Target supply voltage 4 5V if powered with 5V on USB Target supply current Max 300 For the whole target voltage range 1 8V lt Vip lt 5V LOW level input voltage Max 40 of Vir HIGH level input voltage Vy Min 60 of Vir For 1 8V lt Vir lt 3 6V LOW level output voltage with a load of 10 kOhm Max 10 of HIGH level output voltage with a load of 10 kOhm Min 90 of VIF For 3 6 lt Vir lt 5V LOW level output voltage VoL with a load of 10 kOhm Max 20 of Vir HIGH level output voltage Voy with a load of 10 kOhm Power supply Min 80 of Vir SWD Interface Electrical USB powered Max 50mA Target Supply current Target interface voltage Vir 1 2V 5V SWD interface is 5V tolerant but can output a maximum of 3 3V SWD signals Target supply voltage 4 5V if powe
294. r a script file called Default JLinkScript in the folder wich contains the JLink exe and the J Link DLL by default the installation folder e g C Program Files GEGGER JLinkKARM_V456 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 175 If this file is found it is executed instead of the standard auto detection of J Link If this file is not present J Link commander behaves as before and the normal auto detection is performed 5 10 7 2 In debugger IDE environment To execute a script file out of your debugger IDE simply select the script file to exe cute in the Settings tab of the J Link control panel and click the save button after the debug session has been started Usually a project file for J Link is set by the debugger which allows the J Link DLL to save the settings of the control panel in this project file After selecting the script file restart your debug session From now on the script file will be executed when starting the debug session 5 10 7 3 In GDB Server In order to execute a script file when using J Link GDB Server simply start the GDB Server using the following command line paramter scriptfile lt file gt For more information about the scriptfile command line parameter please refer to J Link GDB Server on page 66 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 176 CHAPTER 5 Working with J Link and J Trace 5 11 Command
295. r describes the hardware requirements which have to be met by the tar get board J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 304 CHAPTER 12 Designing the target board for trace 12 1 Overview of high speed board design Failure to observe high speed design rules when designing a target system contain ing an ARM Embedded Trace Macrocell ETM trace port can result in incorrect data being captured by J Trace You must give serious consideration to high speed signals when designing the target system The signals coming from an ARM ETM trace port can have very fast rise and fall times even at relatively low frequencies Note These principles apply to all of the trace port signals TRACEPKT 0 15 PIPESTAT 0 2 TRACESYNC but special care must be taken with TRACECLK 12 1 1 Avoiding stubs Stubs are short pieces of track that tee off from the main track carrying the signal to for example a test point or a connection to an intermediate device Stubs cause impedance discontinuities that affect signal quality and must be avoided Special care must therefore be taken when ETM signals are multiplexed with other pin functions and where the PCB is designed to support both functions with differing tracking requirements 12 1 2 Minimizing Signal Skew Balancing PCB Track Lengths You must attempt to match the lengths of the PCB tracks carrying all of TRACECLK PIPESTAT TRACESYNC and TRACEPKT from the AS
296. r the GDB client already connected to GDBServer and requested the target regis ters which already requires a connection to the target Note Using GDB Server CL this option is mandatory to correctly connect to the target and should be given before connection via GDB Syntax device lt DeviceName gt Example jlinkgdbserver device AT91SAM7SE256 Add information For a list of all valid values for lt DeviceName gt please refer to http www seg ger com jlink supported devices html 3 3 5 3 endian Description Sets the endianess of the target where endianess can either be little or big Note Using GDB Server CL this option is mandatory to correctly connect to the target and should be given before connection via GDB J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 90 CHAPTER 3 J Link software and documentation package Syntax endian lt endianess gt Example jlinkgdbserver endian little 3 3 5 4 if Description Selects the target interface which is used by J Link to connect to the device The default value is JTAG Note Using GDB Server CL this option is mandatory to correctly connect to the target and should be given before connection via GDB Syntax if lt Interface gt Example jlinkgdbserver if SWD Add information Currently the following values are accepted for lt Interface gt JTAG SWD FINE 2 wire JTAG PIC32 3 3 5 5 ir Description
297. r this the file should look similar to the sample in the following screenshot Default ini Notepad BREAKPOINTS showInfowin 1 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 198 6 Flash download Save the settings file and restart the debug session Open the J Link Control Panel and verify that the MemMap tab shows the new settings for CFI flash and work RAM area Log NET CPU Ress Target 59 Device Emulator MemMap Perfomance gt CFI Flash Work Contig 0 10000000 0 103 Config 0 00200000 0 00203 Info Memory 0 00000000 OxFFFFFFFF 4GB Normal Ready JLINK_ETM_IsPresent Done 0 603 37 calls 4 6 5 2 J Link GDB Server The configuration for the J Link GDB Server is done by the gdbinit file The follow ing commands have to be added to the gdbinit file to enable the flash download feature monitor WorkRAM lt SAddr gt lt EAddr gt monitor flash CFI lt SAddr gt lt EAddr gt For more information about the GDB monitor commands please refer to J Link GDB Server on page 66 6 5 3 J Link commander J Link Commander supports downloading bin files into external CFI flash memory In the following it is explained which steps are necessary to prepare J Link Commander for download into external CFI flash memory based on a sample sequence for a ST ST
298. race SWD pinout Pins 4 6 8 10 12 14 16 18 20 are GND pins connected to GND in J Link They should also be connected to GND in the target system J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 280 10 Target interfaces and adapters 10 2 38 pin Mictor JTAG and Trace connector 1 provides a JTAG Trace connector This connector is a 38 mictor plug It connects to the target via a 1 1 cable The connector on the target board should be TYCO type 5767054 1 or a compatible receptacle J Trace supports 4 8 and 16 bit data port widths with the high density target connector described below Target board trace connector Pin 1 chamfer J Trace can capture the state of signals PIPESTAT 2 0 TRACESYNC TRACEPKT n 0 at each rising edge of each TRACECLK or on each alternate rising or falling edge 10 2 1 Connecting the target board 1 connects to the target board via 38 pin trace cable This cable has a recep tacle on the one side and a plug on the other side Alternatively J Trace can be con nected with a 20 pin JTAG cable Warning Never connect trace cable and JTAG cable at the same time because this may harm your J Trace and or your target eiqe E to o o 9 eiqe E t 1 E 2 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 10 2 2
299. rder to speed up the download J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG Comands the macro file 229 Command Description SetJTAGSpeed x Sets the JTAG speed x speed in kHz O Auto Waits a given time Perey x delay in milliseconds Resets the target x delay in milliseconds Go Starts the ARM core Halt Halts the ARM core Read8 Addr Read16 Addr Read32 Addr Reads a 8 16 32 bit value Addr address to read as hex value Verify8 Addr Data Verifies a 8 16 32 bit value Verifyl16 Addr Data Addr address to verify as hex value Verify32 Addr Data Data data to verify as hex value Write8 Addr Data Writes a 8 16 32 bit value Writel6 Addr Data Addr address to write as hex value Write32 Addr Data Data data to write as hex value WriteVerify8 Addr Data Writes and verifies a 8 16 32 bit value WriteVerifyl16 Addr Data Addr address to write as hex value WriteVerify32 Addr Data Data data to write as hex value WriteRegister Reg Data a register WriteJTAG IR Cmd Writes the JTAG instruction register WriteJTAG DR nBits Data Writes the JTAG data register Table 8 2 Macro file commands Example of macro file f kk e ck ke ke ke cec se e she ke he e he e e ke ke ke ck
300. red with 5V on USB Table 1 9 Flasher ARM specifications J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 39 Target supply current 300 LOW level input voltage Max 0 8V HIGH level input voltage Min 2 0V LOW level output voltage with a load of 10 kOhm Meise HIGH level output voltage with a load of 10 kOhm xd Table 1 9 Flasher ARM specifications 1 3 10 J Link ColdFire J Link ColdFire is a BDM emulator designed for ColdFire cores It connects via USB to a PC running Microsoft Windows 2000 Windows XP Windows 2003 or Windows Vista J Link ColdFire has a built in 26 pin BDM connector which is compatible to the standard 26 pin connector defined by Freescale For more infor mation about J Link ColdFire BDM 26 please refer to UM08009 J Link ColdFire BDM26 User s Guide J Link J Trace UM08001 3 ColdFire 26 2004 2014 SEGGER Microcontroller GmbH amp Co KG 40 1 4 CHAPTER 1 Introduction Common features of the J Link product family USB 2 0 interface Full Speed Hi Speed depends on J Link model Any ARM7 9 11 including thumb mode Cortex A5 A8 Cortex M0 M1 M3 M4 Cortex R4 core supported Automatic core recognition Maximum JTAG speed 12 25 MHz depends on J Link model Seamless integration into the IAR Embedded Workbench IDE No power supply required powered th
301. rena nnn 63 3 2 2 USING COMMANA TIES sutaria extre trei 64 3 3 J LINK GDB SCRVEF 66 3 3 1 J Link GDB Server CL Windows Lunux 4 1 1 6 66 3 3 2 Debugging with J Link GDB Server emen 67 3 3 3 Supported remote monitor 1 6 72 3 3 4 SEGGER specific GDB protocol extensions nmm 84 3 3 5 Command lirie options Du na e ex n e 87 3 4 J Link Remote Server asa sena sea a rea sea ana nnn nnn 98 3 4 1 List of available nnns 98 3 4 2 TUNMELING MOUS ee eer ee vex xx etia 99 3 5 3 oa tain eere ke 102 3 6 PME ER 103 3 7 J Onk SWO VIEWER siesta ie toad suspe utu rU Te E wies 104 3 7 1 Usage ER Ec d EA EL dud 105 3 7 2 List of available command line options 105 3 7 3 Configure SWO output after device 107 3 7 4 Target ex
302. reset strategy has been implemented for this device which disables the watchdog right after a reset has been performed We recommend to use this reset strategy when debugging a Samsung S3FN60D device J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 9 15 Silicon Labs 263 J Link has been tested with the following Silicon Labs devices 9 15 1 EFM3 2 series devices EFM32G200F16 EFM32G200F32 EFM32G200F64 EFM32G210F128 EFM32G230F32 EFM32G230F64 EFM32G230F128 EFM32G280F32 EFM32G280F64 EFM32G280F128 EFM32G290F32 EFM32G290F64 EFM32G290F128 EFM32G840F32 EFM32G840F64 EFM32G840F128 EFM32G880F32 EFM32G880F64 EFM32G880F128 EFM32G890F32 EFM32G890F64 EFM32G890F128 EFM32TG108F4 EFM32TG108F8 EFM32TG108F16 EFM32TG108F32 EFM32TG110F4 EFM32TG110F8 EFM32TG110F16 EFM32TG110F32 EFM32TG210F8 EFM32TG210F16 EFM32TG210F32 EFM32TG230F8 EFM32TG230F16 EFM32TG230F32 EFM32TG840F8 EFM32TG840F16 EFM32TG840F32 EM351 EM357 9 15 1 1 SWO Usually the SWO output frequency of a device is directly dependent on the CPU speed The SWO speed is calculated as lt CPUFreq gt n On the EFM32 series this is not the case The SWO related units ITM TPIU are chip internally wired to a fixed 14 MHz clock AUXHFRCO This will cause the auto detection of J Link to not work by default for these devices if the CPU is running at a different speed than AUXHFRCO All utilities that use SWO speed auto detection lik
303. rough USB Support for adaptive clocking All JTAG signals can be monitored target voltage can be measured Support for multiple devices Fully plug and play compatible Standard 20 pin JTAG SWD connector 19 pin JTAG SWD and Trace connector standard 38 pin JTAG Trace connector USB and 20 pin ribbon cable included Memory viewer J Mem included Remote server included which allows using J Trace via TCP IP networks RDI interface available which allows using J Link with RDI compliant software Flash programming software J Flash available Flash DLL available which allows using flash functionality in custom applications Software Developer Kit SDK available Full integration with the IAR C SPY debugger advanced debugging features available from IAR C SPY debugger 14 pin JTAG adapter available J Link 19 pin Cortex M Adapter available J Link 9 pin Cortex M Adapter available Adapter for 5V JTAG targets available for hardware revisions up to 5 3 Optical isolation adapter for JTAG SWD interface available Target power supply via pin 19 of the JTAG SWD interface to 300 mA to tar get with overload protection alternatively on pins 11 and 13 of the Cortex M 19 pin trace connector J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 41 1 5 Supported CPU cores J Link J Trace has been tested with the following cores but should work with any ARM7 9 11 Cortex M0 M1 M3 M4 and Cortex A5 A8 A9 R4 core
304. rver the target is not explicitly halted and the CPU registers will not be inited After closing all GDB connections the target is started again and continues running Some IDEs rely on the target to be halted after connect In this case do not use nohalt but halt Note For the GUI version this setting is persistent for following uses of GDB Server until changed via halt or the GUI Syntax nohalt Example jlinkgdbserver nohalt 3 3 5 15 nosilent Description Starts the GDB Server in non silent mode All log window messages will be shown Note For the GUI version this setting is persistent for following uses of GDB Server until changed via command line option or the GUI Syntax nosilent 3 3 5 16 nostayontop Description Starts the GDB Server in non topmost mode All windows can be placed above it Note For the CL version this setting has no effect Note For the GUI version this setting is persistent for following uses of GDB Server until changed via command line option or the GUI Syntax nostayontop 3 3 5 17 notimeout Description GDB Server automatically closes after a timout of 5 seconds when no target voltage can be measured or connection to target fails This command line option prevents GDB Server from closing to allow connecting a target after starting GDB Server Note The recommended order is to power the target connect it to J Link and then start GDB Server Syntax notimeout
305. s makes it pos sible to look into the memory of a target system at run time RAM can be modified and SFRs can be written You can choose between 8 16 32 bit size for read and write accesses J Mem works nicely when modifying SFRs especially because it writes the SFR only after the complete value has been entered J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 103 3 6 J Flash J Flash is an application to program data images to the flash of a target device With J Flash the internal flash of all J Link supported devices can be programmed as well as common external flashes connected to the device Beside flash programming all other flash operations like erase blank check and flash content verification can be done J Flash requires an additional license from SEGGER to enable programming For license keys as well as evaluation licenses got to http www segger com or contact us directly Connection USB Init JTAG speed 30 JTAG speed Auto TAP number not used IR len not used Chip Generic ARM7 ARMS Clock speed lt don t care gt Endian Little Device no device selected no device selected Flash Id device selected J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 104 J Link software and documentation package 3 7 J Link SWO Vie
306. s requires an RDI license in addition to its own license Evaluation licenses are available free of charge For further information go to our website or contact us directly Note The RDI software as well as flash breakpoints and flash downloads do not require a license if the target device is an LPC2xxx In this case the software ver ifies that the target device is actually an LPC 2xxx and have a device based license 3 10 1 Flash download and flash breakpoints Flash download and flash breakpoints are supported by J Link RDI For more infor mation about flash download and flash breakpoints please refer to J Link RDI User s Guide UM08004 chapter Flash download and chapter Breakpoints in flash memory J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 113 3 11 Processor specific tools The J Link software and documentation package includes some tools which support processor specific functionalities like unlocking a device 3 11 1 J Link STR91x Commander Command line tool J Link STR91x Commander JLinkSTR91x exe is tool that can be used to configure STR91x cores It permits some STRO9 specific commands like Set the configuration register to boot from bank O or 1 Erase flash sectors Read and write the OTP sector of the flash Write protect single flash sectors by setting the sector protection bits Prevent flash from communicate via JTAG by setting the security bit All of the actions per
307. scale updated Chapter Working with J Link Ven os Section Reset strategies updated Chapter Working with J Link Mee TOURA ae Section Reset strategies updated Chapter Working with J Link Section J Link script files updated Section Command strings upadted Chapter Target interfaces and adapters 20 TODAS PAR Section 19 pin JTAG SWD and Trace connector corrected Chapter Setup Section J Link configurator added 89 100630 AG Several corrections Chapter J Link and J Trace related software 98 00529 AG Section SWO Analyzer added 87 100617 Several corrections J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG Revision Date By Explanation Chapter Introduction Section J Link J Trace models updated 59 e Chapter Target interfaces adapters Section Adapters updated Chapter Introduction 85 100440 Section J Link J Trace models updated Chapter Working with J Link and J Trace Several corrections 88 SIN Chapter Flash download amp flash breakpoints Section Supported devices updated Chapter Introduction 83 00524 MEN Section J Link J Trace models updated Chapter Working with J Link pe sp Oe bes 26 Section J Link script files added Chapter Device Specifics Section Luminary Micro updated 92 SUBE Chapter Flash
308. se rFlashBP will be disabled inter nally e Enables the FlashBP feature If no license has been found an error message appears e Off Disables the FlashBP feature e Show window during program When this checkbox is enabled the Program ming flash window is shown when flash is re programmed in order to set clear flash breakpoints J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 155 Flash download and flash breakpoints independent settings These settings do not belong to the J Link flash download and flash breakpoints set tings section They can be configured without any license needed General Settings Breakpoints Log CPU Reas Target Power SWV Device Emulator male r Log file T Override JEMLink log Clear r Settings file T Gyeride Not specified E Flash download B Flash breakpoints Auto License found Auto License found On Skip download on CRC match On IV Show info window during C Iv Verify download C Off program Disabled Disabled Override device selection Allow caching of flash contents On Allow instruction set simulation Gyeride memory map Modify breakpoints during execution allow x Ready JLINKARM GetSpeed Done 1 208 sec in 32 calls 2 e Log file Shows the path where the J Link log file is placed It is possible to override the selection manually by enabling the Override
309. sed to supply power to the target hardware Supply voltage is 5V max current is 300mA The output current is monitored and protected against overload and short circuit Power can be controlled via the J Link com mander The following commands are available to control power Command Explanation power on Switch target power on power off Switch target power off power on perm Set target power supply default to on power off perm Set target power supply default to off Table 10 2 Command List J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 277 10 1 2 Pinout for SWD The J Link and J Trace JTAG connector is also PE mde patible to ARM s Serial Wire Debug SWD Notused 3 GND On later J Link products like the J link ULTRA i x ME these pins reserved for firmware extension pur 9e 1 poses They can be left open or connected to GND Notused 11 12 normal debug environment They are not essential swo 13 14 GND for JTAG SWD in general RESET 15 916 GND Not used 17 18 GND The following table lists the J Link J Trace SWD 5v supply 19 20 GND pinout PIN SIGNAL TYPE Description This is the target reference voltage It is used to check if the target has power to create the logic level reference for 1 VTref Input the input comp
310. structions from memory and executes them including the instruction fetch unit arithmetic and logic unit and the register bank It excludes optional coprocessors caches and the memory management unit Program Status Register PSR Contains some information about the current program and some information about the current processor state Often therefore also referred to as Processor Status Register Also referred to as Current PSR CPSR to emphasize the distinction to the Saved PSR SPSR The SPSR holds the value the PSR had when the current function was called and which will be restored when control is returned Remapping Changing the address of physical memory or devices after the application has started executing This is typically done to make RAM replace ROM once the initialization has been done Remote Debug Interface RDI RDI is an open ARM standard procedural interface between a debugger and the debug agent The widest possible adoption of this standard is encouraged RTCK Returned TCK The signal which enables Adaptive Clocking RTOS Real Time Operating System Scan Chain A group of one or more registers from one or more TAP controllers connected between TDI and TDO through which test data is shifted Semihosting A mechanism whereby the target communicates I O requests made in the application code to the host system rather than attempting to support the I O itself SWI Software Interrupt An instruc
311. t J Link V8 or later J Link PRO V3 or later J Link ULTRA V4 or later Flasher ARM V4 or later 9 17 2 AM35xx AM37xx Script is not needed Refer to AM335x special handling Same needs to be done for AM35xx AM37xx 9 17 3 4430 Script is not needed Refer to AM335x special handling Same needs to be done for AM35xx AM37xx 9 17 4 OMAP L138 Needs a J Link script file to guarantee proper functionality J Link script file can be found at JLINK_INST_DIR Samples JLink Scripts For more information about how to use J Link script files please refer to Executing J Link script files on page 174 9 17 5 TMS470M Needs a J Link script file to guarantee proper functionality J Link script file can be found at JLINK_INST_DIR Samples JLink Scripts For more information about how to use J Link script files please refer to Executing J Link script files on page 174 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 271 9 17 6 530 Needs J Link script file to guarantee proper functionality J Link script file can be found at JLINK_INST_DIR Samples JLink Scripts For more information about how to use J Link script files please refer to Executing J Link script files on page 174 9 17 7 OMAP3550 Needs a J Link script file to guarantee proper functionality J Link script file can be found at JLINK_INST_DIR Samples JLink Scripts
312. t clock pulse The technique allows the J Link J Trace interface unit to adapt to differing signal drive capabilities and differing cable lengths Application Program Interface A specification of a set of procedures functions data structures and constants that are used to interface two or more software components together Big endian Memory organization where the least significant byte of a word is at a higher address than the most significant byte See Little endian Cache cleaning The process of writing dirty data in a cache to main memory Coprocessor An additional processor that is used for certain operations for example for floating point math calculations signal processing or memory management Dirty data When referring to a processor data cache data that has been written to the cache but has not been written to main memory is referred to as dirty data Only write back caches can have dirty data because a write through cache writes data to the cache and to main memory simultaneously See also cache cleaning Dynamic Linked Library DLL A collection of programs any of which can be called when needed by an executing program A small program that helps a larger program communicate with a device such as a printer or keyboard is often packaged as a DLL Embedded Trace Macrocell ETM ETM is additional hardware provided by debuggable ARM processors to aid debugging with trace functionality Embedded Trace Buffer
313. t is set to the SWI entry in the exception vector table by default 8 5 4 1 Using SWls in your application If your application requires semihosting as well as having its own SWI handler set semihosting vector to an address in your SWI handler This address must point to an instruction that is only executed if your SWI handler has identified a call to a semihosting SWI All registers must already have been restored to whatever values they had on entry to your SWI handler J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 237 8 5 5 Unexpected unhandled SWIs When an unhandled SWI is detected by J Link RDI the message box below is shown J Link RDI Warning J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 238 8 RDI J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 239 Chapter 9 Device specifics This chapter describes for which devices some special handling is necessary to use them with J Link J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 240 9 1 Analog Devices J Link has been tested with the following MCUs from Analog Devices AD7160 ADuC7020x62 ADuC7021x32 ADuC7021x62 ADuC7022x32 ADuC7022x62 ADuC7024x62 ADuC7025x32 ADuC7025x62 ADuC7026x62 ADuC7027x62 ADuC7028x62 ADuC7030 ADuC7031 ADuC7032 ADuC7033 ADuC7034 ADuC7036 ADuC7038 ADuC7039 ADu
314. ta registers i oc re her exe e Mie ea d bee Ti re we Va date dde Mie eta tele 290 11 1 3 Iristr ctioniregIstel cso 04 doe ort eor I ERA II NEUEN E RE ERE RI i PR AR 290 11 1 4 Thes rAP sconttroller 2 ED Mc ee ah 291 11 2 Embedded Trace Macrocell 2 nnns 293 11 2 1 Trigger conditionis 293 11 2 2 Code tracing and data 10 293 11 2 3 1 integration example IAR Embedded Workbench for ARM 293 11 3 Embedded Trace Buffer ETB 2 1141 4 4 lt 297 11 4 Flash programming tad tee o Y abu 298 11 4 1 How does flash programming via J Link J Trace 298 11 4 2 Data download to RAM 5 esse keen 298 11 4 3 Data download via DCC 1 1 47 2 0 4 4 4 4 4 6 66 enn nnns 298 11 4 4 Available options for flash programming 1 1 298 11 5 J Link J Trace ena n a n 300 11 5 1 Firmware update eei e Rem e ED EE 300 11 5 2 Invalidating the 11 nene 300 12 Designing the target board 2 303 12 1 Overview of high speed b
315. ta registers is initiated IR Scan Temporary controller state If TMS remains low a scan sequence for the instruction register is initiated Capture DR Data may be loaded in parallel to the selected test data registers Shift DR The test data register connected between TDI and TDO shifts data one stage towards the serial output with each clock J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 292 CHAPTER 11 Background information Exit1 DR Temporary controller state Pause DR The shifting of the test data register between TDI and TDO is temporarily halted Exit2 DR Temporary controller state Allows to either go back into Shift DR state or go on to Update DR Update DR Data contained in the currently selected data register is loaded into a latched parallel output for registers that have such a latch The parallel latch prevents changes at the parallel output of these registers from occurring during the shifting process Capture IR Instructions may be loaded in parallel into the instruction register Shift IR The instruction register shifts the values in the instruction register towards TDO with each clock Exit1 IR Temporary controller state Pause IR Wait state that temporarily halts the instruction shifting Exit2 IR Temporary controller state Allows to either go back into Shift IR state or go on to Update IR Update IR The values contained in the instruction regis
316. target power on power off Switch target power off power on perm Set target power supply default to on power off perm Set target power supply default to off Table 10 4 Command List J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 279 10 1 3 Pinout for SWD Virtual COM Port VCOM J Link and J Trace JTAG connector is also compatible to ARM s Serial Wire Debug SWD Vater bd INE Not used 3e 4 GND On later J Link products like the J link ULTRA Jj LinkTx 5e GND these pins are reserved for firmware extension swbpio 79 e8 GND purposes They can be left open or connected to SWCLK 9e 10 GND in normal debug environment They not Notused 11 e 12 GND essential for JTAG SWD in general swo 13 14 GND RESET 159 16 GND The following table lists the J Link J Trace SWD j LinkRx 179 18 GND pinout 5V Supply 99 20 GND PIN SIGNAL TYPE Description This is the target reference voltage It is used to check if the target has power to create the logic level reference for 1 VTref Input the input comparators and to control the output logic levels to the target It is normally fed from Vdd of the target board and must not have a series resistor 2 This pin is not connected in J Link nected This pin is not used by J Link If the device may also be 3 Not Used NC accessed via JT
317. tation pack is available for download before starting the installation Check therefore the J Link related download section of our website http www segger com download_jlink html 1 Before you plug your J Link J Trace into your computer s USB port extract the setup tool Setup JLinkARM V VersionNumber zip The setup wizard will install the software and documentation pack that also includes the certified J Link USB driver Start the setup by double clicking Setup JLinkARM V Version Number gt exe The license Agreement dialog box will be opened Accept the terms with the Yes button S3 License Agreement J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 119 2 Welcome dialog box is opened Click Next gt to open the Choose Destina tion Location dialog box a Welcome Welcome to J Link ARM V 3 58c Setup program This program will install J Link ARM V3 58c on your 22 computer Click Cancel to quit Setup click Next to continue with the Setup program WARNING This program is protected by copyright law and international treaties Unauthorized reproduction or distribution of this program or any portion of it may result in severe civil and criminal penalties and will be prosecuted to the maximum extent possible under law 3 Accept the GERNJLinkARM V VersionNumber your choice with the Next button default A Choose Destination Lo
318. te commands J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 73 Following remote commands deprecated and only available for backward compa bility Remote command Explanation Select the specified target device device Note Use command line option device instead Select the target interface interface Note Use command line option i instead Sets the JTAG speed of J Link J Trace speed Note For the initial connection speed use com mand line option speed instead Table 3 3 GDB remote commands Note The remote commands are case insensitive Note Optional parameters are set into square brackets Note The examples are described as follows Lines starting with 4 are comments and not used GDB GDB Server Lines starting with gt gt are input commands from the GDB Lines starting with is the output from GDB Server as printed in GDB J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 74 J Link software and documentation package 3 3 3 1 clrbp Syntax CIrBP lt BPHandle gt or ci BPHandle Description Removes an instruction breakpoint where lt BPHandle gt is the handle of breakpoint to be removed If no handle is specified this command removes all pending breakpoints Example gt monitor clrbp 1 or monitor ci 1 3 3 3 2 cp15 Synta
319. ted by the J Link script file language Additive operators Equality operators Bitwise operators amp Logical operators amp amp 5 10 5 2 Supported type specifiers Multiplicative operators Bitwise shift operators lt lt gt gt Relational operators lt gt lt gt Assignment operators lt lt gt gt amp A The following type specifiers are supported by the J Link script file language void char int 32 bit int64 5 10 5 3 Supported type qualifiers The following type qualifiers are supported by the J Link script file language e const e Signed J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 174 CHAPTER 5 Working with J Link and J Trace e unsigned 5 10 5 4 Supported declarators The following type qualifiers are supported by the J Link script file language e Array declarators 5 10 5 5 Supported selection statements The following selection statements are supported by the J Link script file language if statements e if else statements 5 10 5 6 Supported iteration statements The following iteration statements are supported by the J Link script file language e while e do while 5 10 5 7 Jump statements The following jump statements are supported by the J Link script file language return 5 10 5 8 Sample script files The J Link software and documentation package comes
320. ted by the debugger volatile int 0xE0042008 1 lt lt 11 1 lt lt 12 J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 9 17 Texas Instruments 269 J Link has been tested with the following Texas Instruments devices AM3352 AM3354 AM3356 AM3357 AM3358 AM3359 OMAP3530 OMAP3550 OMAP4430 OMAP L138 TMS470M TMS470R1A64 TMS470R1A128 TMS470R1A256 TMS470R1A288 TMS470R1A384 TMS470R1B512 TMS470R1B768 TMS470R1B1M TMS470R1VF288 TMS470R1VF688 TMS470R1VF689 9 17 1 AM335x The AM335x series devices need some special handling which requires that correct device is selected in the J Link DLL When used out of a debugger this is usually done automatically see Software reset on page 240 For J Link Commander amp J Link GDBServer this needs to be done automatically 9 17 1 1 Selecting the device in the IDE When using J Link in an IDE there is usually a way to directly select the device in the IDE since it usually also needs this information for peripheral register view etc The selected device is then usually automatically passed to the J Link DLL The screenshot below is an example for a device selection inside emIDE http www emide org Debugger Start the application v Run to main GDB commands after connection monitor reset load Project targets options mmm Project settings Build
321. ted with ARM RVDS version 2 1 and 3 0 There should be no problems with earlier versions of RVDS up to version v3 0 1 All screenshots are taken from ARM s RVDS version 2 1 Note RVDS version 3 1 does not longer support RDI protocol to communicate with the debugger 8 3 3 2 Configuring to use J Link RDI 1 Start the Real View debugger Z RYDEBUG lt Start_STR71x gt Not connected no PC or scope Click to Connect to a Target No Register Context J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 216 8 RDI 2 Select File Connection Connect to Target 2 RVDEBUG Start STR71x _ lt No Register Context 3 Inthe Connection Control dialog use the right mouse click on the first item and select Add Remove Edit Devices Connection Control SouhailXredebug brd erface parallel port Remote nn serial port Server localhos E epit nect 41 ARMOAK Ma Jonnect ARM 0ak ARM Vehicle SRMOT WIGGLER Macraigor Wiggler EAS IRE DIR RM Ltd Direct Connection 3 S VPB926EJ S U Versatile Platform for ARMS26EJ S USB port RealViewICE fRealView ICE ARM JT G debug interface TCP IP J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 217 4 Now select Add DLL to add the JLinkRDI d11 Select the installation path of the software for example C Program Files
322. tegy 0 normal first in order to reset the core amp peripherals and halt the CPU immediately after reset After the CPU is halted the watchdog is disabled since the watchdog is running after reset by default and if the target appli cation does not feed the watchdog J Link loses connection to the device since it is reset permanently 5 8 2 8 Type 7 Reset for Analog Devices CPUs ADI Halt after kernel Performs a reset of the core and peripherals by setting the SYSRESETREQ bit in the AIRCR The core is allowed to perform the ADI kernel which enables the debug inter face but the core is halted before the first instruction after the kernel is executed in order to guarantee that no user application code is performed after reset Type 8 Reset core and peripherals J Link tries to reset both core and peripherals by setting the SYSRESETREQ bit in the AIRCR The vc CORERESET bit is used to halt the CPU before it executes a single instruction 5 8 2 9 Type 8 Reset core and peripherals Performs a reset by setting the SYSRESETREQ bit in the AIRCR VC CORERESET in the DEMCR is also set to make sure that the CPU is halted immediately after reset and before executing any instruction Reset procedure 1 Make sure that the device halts immediately after reset before it can execute any instruction of the user application by setting the vc CORERESET in the DEMCR 2 Reset the core and perip
323. tem is connected to one J Link at once J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 231 8 4 4 4 Flash tab J Link RDI Configuration 24 x General Int JTAG Flash Breakpoints CPU Log w Enable flash programming Allows programming the flash This is required to download a program into flash memory or to set software breakpoints in flash flash breakpoints Device Atmel ATS1SAM7S64 Clock speed 48000000 Hz RAM 16 KB address 0 200000 rw Cache flash contents Allows caching of flash contents This avoids reading data twice and speeds up the transfer between debugger and target Allow flash download Allows program download to flash Y our debugger does not need to have a flash loader This feature requires an additional license FlashDL Show info window during download Cancel Apply Enable flash programming This checkbox enables flash programming Flash programming is needed to use either flash download or to use flash breakpoints If flash programming is enabled you must select the correct flash memory and flash base address Furthermore it is necessary for some chips to enter the correct CPU clock frequence Cache flash contents If enabled the flash contents is cached by the J Link RDI software to avoid reading data twice and to speed up the transfer between debugger and target Allow flash download Th
324. ter are loaded into a latched parallel out put from the shift register path Once latched this new instruction becomes the cur rent one The parallel latch prevents changes at the parallel output of the instruction register from occurring during the shifting process J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 293 11 2 Embedded Trace Macrocell ETM Embedded Trace Macrocell ETM provides comprehensive debug and trace facilities for ARM processors ETM allows to capture information on the processor s state with out affecting the processor s performance The trace information is exported immedi ately after it has been captured through a special trace port Microcontrollers that include an ETM allow detailed program execution to be recorded and saved in real time This information can be used to analyze program flow and execution time perform profiling and locate software bugs that are otherwise very hard to locate A typical situation in which code trace is extremely valuable is to find out how and why a program crash occurred in case of a runaway program count A debugger provides the user interface to J Trace and the stored trace data The debugger enables all the ETM facilities and displays the trace information that has been captured J Trace is seamlessly integrated into the IAR Embedded Workbench IDE The advanced trace debugging features can be used with the IAR C SPY debug ger 11 2 1
325. tes second e DCC speed up to 600 Kbytes second Measured with J Trace 7 50 MHz 12MHz JTAG speed 1 3 7 2 Specifications for J Trace General Supported OS For a complete list of all operating sys tems which are supported please refer to Supported OS on page 23 Electromagnetic Compatibility EMC EN 55022 EN 55024 Operating Temperature 5 C 40 C Storage Temperature 20 C 65 C Relative Humidity non condensing lt 90 rH Size without cables 123mm x 68mm x 30mm Weight without cables 120g Mechanical USB Interface USB 2 0 full speed Target Interface JTAG 20 pin 14 pin adapter available JTAG Trace Mictor 38 pin Table 1 5 J Trace specifications J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 34 CHAPTER 1 Introduction JTAG SWD Interface Electrical Power Supply USB powered lt 300mA Supported Target interface voltage 3 0 3 6 V 5V adapter available Table 1 5 J Trace specifications J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 35 1 3 7 3 Download speed The following table lists performance values Kbytes s for writing to memory RAM Hardware ARM7 via JTAG ARM9 via JTAG 420 0 Kbytes s 280 0 Kbytes s 12MHz JTAG 12MHz JTAG Table 1 6 Download speed differences between hardware revisions
326. th signal The resistor value plus the output impedance of the driver must be equal to the PCB track impedance DC parallel termination This requires either a single resistor to ground or a pull up pull down combination of resistors Thevenin termination fitted at the end of each signal and as close as pos sible to the JTAG Trace connector If a single resistor is used its value must be set equal to the PCB track impedance If the pull up pull down combination is used their resistance values must be selected so that their parallel combination equals the PCB track impedance Caution At lower frequencies parallel termination requires considerably more drive capability from the ASIC than series termination and so in practice DC parallel termination is rarely used 12 2 1 Rules for series terminators Series source termination is the most commonly used method The basic rules are 1 The series resistor must be placed as close as possible to the ASIC pin less than 0 5 inches 2 The value of the resistor must equal the impedance of the track minus the output impedance of the output driver So for example a 50 PCB track driven by an out put with a 17 impedance requires a resistor value of 33 3 A source terminated signal is only valid at the end of the signal path At any point between the source and the end of the track the signal appears distorted because of reflections Any device connected between the source and the end o
327. the peripherals by writing to the RSTC_CR register Resetting the peripherals puts all peripherals in the defined reset state This includes memory mapping register which means that after reset flash is mapped to address 0 It is also possible to achieve the same effect by writing 0x4 to the RSTC CR register located at address OxfffffdOO This information is applicable to the following devices AT91SAM7S all devices AT91SAM7SE all devices AT91SAM7X all devices AT91SAM7XC all devices AT91SAM7A all devices 9 2 1 2 Memory mapping Either flash or RAM can be mapped to address O After reset flash is mapped to address 0 In order to majlink supported devices html RAM to address 0 a 1 can be written to the RSTC CR register Unfortunately this remap register is a toggle regis ter which switches between RAM and flash with every time bit zero is written In order to achieve a defined mapping there are two options 1 Use the software reset described above 2 Test if RAM is located at using multiple read write operations and testing the results Clearly 1 is the easiest solution and is recommended This information is applicable to the following devices AT91SAM7S all devices AT91SAM7SE all devices AT91SAM7X all devices AT91SAM7XC all devices AT91SAM7A all devices 9 2 1 3 Recommended init sequence In order to work with an ATMEL AT91SAM7 device it has to be initialized The follow ing paragraph describes
328. the given register J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 78 gt monitor reg pc lt Writing register gt monitor reg 0 lt Writing register gt monitor reg PC lt Reading register 3 3 3 16 regs Syntax regs Description Read register value P R P CHAPTER 3 J Link software and documentation package Write value to register 0x00100230 C 0x00100230 0x00000040 0 0x14813004 0 00100230 Reads all CPU registers Example gt monitor regs lt PC 00100230 CPSR RO 14813004 R1 R4 00000000 R5 USR 8 00000000 R13 00000000 8 00000000 R13 00200000 SVC R13 002004E8 ABT R13 00200100 IRQ 13 00200100 UND R13 00200100 3 3 3 17 reset Syntax reset Description 20000013 S 00000001 R2 00000000 R6 9 00000000 R14 00000000 9 00000000 R14 00000000 R14 0010025C R14 00000000 R14 00000000 R14 00000000 Write value from address to register VC mode ARM 00000001 R3 000003B5 00000000 R7 00000000 10 00000000 R11 00000000 R12 00000000 R10 00000000 R11 00000000 R12 00000000 SPSR 00000010 SPSR 00000010 SPSR 00000010 SPSR 00000010 SPSR 00000010 Resets and halts the target CPU Make sure the device is selected prior to using this command to make use of the correct reset strategy Add information There are diff
329. the local network To give access to a J Link neither a remote desktop or vpn connection nor changing some difficult firewall settings are necessary When started in tunneling mode the Remote server connects to the SEGGER tunnel server via port 19020 and registers with its serial number To connect to the J Link from the remote computer an also simple connection to tunnel SerialNo can be established and the debugger is connected to the J Link TCP IP Server USBStat ide Connected to tunnel server Status Example scenario A device vendor is developing a new device which shall be supported by J Link Because there is only one prototype a shipment to SEGGER is not possible Instead the vendor can connect the device via J Link to a local computer and start the Remote server in tunneling mode He then gives the serial number of the J Link to an engineer at SEGGER The engineer at SEGGER can use J Link Commander or a debugger to test and debug the new device without the need to have the device on his desk J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 100 J Link software and documentation package Start J Link Remote Server in tunneling mode J J Link ARM V4 80 EJ J Flash E J Link Commander E J Link Configurator EJ Link DLL Updater Link GDB Server Link SWO Viewer E J Mem License Agreement 8 Remove J Link ARM V4 80 d Ma
330. the status window simply click on the tray icon 12 J Link ARM of x Settings Break watch Log CPU Regs Target Power swv Show tray icon Iv Start minimized Always on top Process JESTooNCMARVARM_V520_beta902 common bin larld J Link J Link ARM 0 5 00 7 Target interface Adaptive Endian 327 I Device Jatstsam7s256 License About 5 7 1 Tabs J Link status window supports different features which grouped tabs organization of each tab and the functionality which is behind these groups will be explained in this section 5 7 1 1 General In the General section general information about J Link and the target hardware are shown Moreover the following general settings can be configured e Show tray icon If this checkbox is disabled the tray icon will not show from the next time the DLL is loaded e Start minimized If this checkbox is disabled the J Link status window will show up automatically each time the DLL is loaded e Always on top if this checkbox is enabled the J Link status window is always visible even if other windows will be opened The general information about target hardware and J Link which are shown in this section are e Process Shows the path of the file which loaded the DLL e J Link Shows OEM of the connected J Link the hardware version and the Serial number If no J Link is connected it shows not connected
331. tically based on the CPU frequency and the capabilities of the connected J Link J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 107 Syntax swofreq lt SWOFreq gt Example swofreq 6000 3 7 3 Configure SWO output after device reset In some situations it might happen that the target application is reset and it is desired to log the SWO output of the target after reset during the booting process For such situations the target application itself needs to initialize the CPU for SWO output since the SWO Viewer is not restarted but continuously running Example code for enabling SWO out of the target application define ITM_ENA volatile unsigned 0 0000 00 ITM Enable define ITM_TPR volatile unsigned 0 0000 40 Trace Privilege Register define ITM TCR volatile unsigned int OxEO000E80 ITM Trace Control Reg define ITM LSR volatile unsigned int OxEOO000FBO ITM Lock Status Register define DHCSR volatile unsigned 0 000 0 Debug register define DEMCR volatile unsigned int O0xEOO00EDFC Debug register define TPIU ACPR volatile unsigned int 0xE0040010 Async Clock N presacler register define SPPR volatile unsigned int 0xE00400F0 Selected Pin Protocol Register define DWT CTRL volatile unsigned int 0xE0001000 DWT Control Register define FFCR v
332. tion Chapter Flash download added Chapter Flash breakpoints added Chapter Target interfaces and adapters V4 36 Rev 1 110927 Section 20 pin JTAG SWD connector updated Chapter RDI added Chapter Setup updated Chapter Device specifics updated Chapter Working with J Link Section J Link script files updated Chapter Introduction TUTO Section J Link J Trace models corrected V4 26 Rev 0 110427 Several corrections Chapter Introduction V4 24 Rev 1 110228 Section J Link J Trace models corrected Chapter Device specifics Section ST Microelectronics updated Chapter Device specifics Section Samsung added Chapter Working with J Link ME PENT O AC Section Reset strategies updated Chapter Target interfaces and adapters Section 9 pin JTAG SWD connector added Chapter J Link and J Trace related software Section J Link software and documentation package in detail updated 110202 AG Chapter Introduction Section Built in intelligence for supported CPU cores added Chapter Working with J Link Section Reset strategies updated Chapter Device specifics Section Freescale updated Ved OLS Chapter Flash download and flash breakpoints Section Supported devices updated Section Setup for different debuggers CFI flash updated Chapter Device specifics we 1010286 AG Section Free
333. tion that causes the processor to call a programer specified subroutine Used by ARM to handle semihosting TAP Controller Logic on a device which allows access to some or all of that device for test purposes The circuit functionality is defined in IEEE1149 1 Target The actual processor real silicon or simulated on which the application program is running TCK The electronic clock signal which times data on the TAP data lines TMS TDI and TDO TDI The electronic signal input to a TAP controller from the data source upstream Usu ally this is seen connecting the J Link J Trace Interface Unit to the first TAP control ler J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 317 TDO The electronic signal output from a TAP controller to the data sink downstream Usually this is seen connecting the last TAP controller to the J Link J Trace Inter face Unit Test Access Port TAP The port used to access a device s TAP Controller Comprises TCK TMS TDI TDO and nTRST optional Transistor transistor logic TTL A type of logic design in which two bipolar transistors drive the logic output to one or zero LSI and VLSI logic often used TTL with HIGH logic level approaching 5V and LOW approaching OV Watchpoint A location within the image that will be monitored and that will cause execution to stop when it changes Word A 32 bit unit of information Contents are t
334. tools used for building your application assembler linker C compiler and especially the debugger and the debugger frontend of your choice We do not answer questions about how to install and use the chosen toolchain J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 69 GDB is included in many IDEs and most commonly used in connection with the GCC compiler toolchain This chapter shows how to configure some programs to use GDB and connect to GDB Server For more information about any program using GDB please refer to its user manual emIDE is full featured free and open source IDE for embedded development including support for debugging with J Link To connect to GDB Server with emIDE the GDB Server configurations need to be set in the project options at Project gt Properties gt Debugger Select the target device you are using the target connection endianess and speed and enter the additional GDB start commands The typically required GDB commands are Initially reset the target monitor reset Load the application load Other commands to set up the target e g Set PC to RAM initialize external flashes can be entered here too emIDE will automatically start GDB Server on start of the debug session If it does not or an older version of GDB Server start in emIDE click on JLink gt Run the JLink plugin configuration J Link J Trace 0 08001 2004 2014 SEGG
335. tory options can also be sleceted in the con figuration dialog Command line option Explanation device Select the connected target device endian Select the device endianness if Select the interface to connect to the target speed Select the target communication speed Table 3 5 Mandatory command line options Note Using multiple instances of GDB Server setting custom values for port SWOPort TelnetPort is necessary Command line option Explanation port Select the port to listen for GDB clients swoport Select the port to listen for clients for SWO RAW output telnetport Select the port to listen for clients for printf output Table 3 6 Port selection command line options The GDB Server GUI version uses persistent settings which are saved across different instances and sessions of GDB Server These settings can be toggled via the check boxes in the GUI Note GDB Server CL always starts with the settings marked as default For GUI and CL the settings can be changed with following command line options For all persistent settings there is a pair of options to enable or disable the feature Command line option Explanation ir Initialize the CPU registers on start of GDB Server Default noir Do not initialize CPU registers on start of GDB Server localhostonly Allow only localhost connections Windows default nolocalhostonly
336. ty with various n 205 7 5 FAQ S CRI A E 206 220 0 tun nus E craton mura cece hie Ahead ols Stee i 207 8 1 i 208 8 1 1 208 8 2 LICENSING 209 8 3 Setup for various 210 8 3 1 Embedded Workbench IDE mnm 210 8 3 2 AXD ARM Developer Suite 5 2 4 3 4 3 4 213 8 3 3 ARM RVDS RealView developer suite 4 215 8 3 4 GHS MULTI x rene errem ener eed om eri XR er kane REO area 220 8 3 5 KEIL MDK piVision IDE i ra eck s 223 8 4 Config rationz ico eie eee cip to sigo pia eed gutter intu vr Tigra 226 8 4 1 Configuration file 226 8 4 2 Using different configurations 1 nnne 226 8 4 3 Using mutliple J Links simulatenously 1 226 8 4 4 Configuration dialog AE Ern Pat Y ple 226 8 5 SEMINOSUIA EMT 235 8 5 1 OVERVIEW 235 8 5 2 The SWI interfa
337. ular timer interrupt switched on every few ms for at least a few us In this case the CPU will stop at the first instruction in the ISR typically at address 0x18 Synthesizable cores ARM7TDMI S 5 etc With these cores the clock input of the TAP controller is connected to the output of a three stage synchronizer which is fed by clock signal provided by the emulator which means that the TAP controller and ICE Breaker are not accessible if the CPU has no clock If the RTCK signal is provided adaptive clocking function can be used to synchronize the JTAG clock provided by the emulator to the processor clock This way the JTAG clock is stopped if the CPU clock is switched off If adaptive clocking is used switching off CPU clock during debug is normally possi ble if the CPU clock is periodically typically using a regular timer interrupt switched on every few ms for at least a few us In this case the CPU will stop at the first instruction in the ISR typically at address 0x18 J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 184 CHAPTER 5 Working with J Link and J Trace 5 13 Cache handling Most target systems with external memory have at least one cache Typically ARM7 systems with external memory come with a unified cache which is used for both code and data Most ARM9 systems with external memory come with separate caches for the instruction bus I Cache and data bus D Cache
338. upported OS Added Linux and Mac OSX V4 62b Rev 0 130219 EL Chapter Introduction Section J Link J Trace models Clock rise and fall times updated V4 62 Rev 0 130129 JL Chapter Introduction Section J Link J Trace models Sub section J link ULTRA updated V4 62 Rev 0 130124 EL Chapter Target interfaces and adapters Section 9 pin JTAG SWD connector Pinout description corrected J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG Revision Date By Explanation Chapter Intoduction Mae Reve Section J Link J Trace models updated Chapter Working with J Link Section J Link script files Sub section Executing J Link script files updated V4 58 Rev 0 121126 Chapter Related Software Section J Link SWO Viewer Added sub section Configure SWO output after device reset V4 56b Rev 0 121112 JL Chapter Related Software Section J Link Commander V4 56a Rev 0 121106 JL Renamed Commander script files to Commander files and script mode to batch mode Renamed J Link TCP IP Server to J Link Remote V4 56 Rev 0 121022 Server Chapter Related Software V4 54 Rev 1 121009 JL Section TCP IP Server subsection Tunneling Mode added Chapter Flash Breakpoints Section Licensing updated V4 54 Rev 0 120913 EL Chapter
339. ut voltage Voy with a load of 10 kOhm VoH gt 80 of Vig JTAG SWD Interface Timing SWO sampling frequency Max 100 MHz Data input rise time Tri Trai lt 20ns Data input fall time lt 20ns Data output rise time Trao Trdo lt 10ns Data output fall time lt 10ns Clock rise time Tre lt 3ns Clock fall time lt 3ns Analog power mea surement interface Sampling frequency 50 kHz Resolution 1 mA Table 1 2 J link ULTRA specifications 1 3 4 J Link PRO J Link PRO is a JTAG emulator designed fully compatible to J Link and connects via Ethernet USB to a PC running Microsoft Windows 2000 or later Linux or Mac OS X For a complete list of all operating syst ported please refer to Supported OS on comes with licenses for all J Link related SEGGER software products which allows using J Link PRO out of the box 1 3 4 1 Additional features e Fully compatible to J Link e More memory for future firmware extensions ARM11 X Scale Cortex R4 and Cortex A8 e Additional LEDs for power and RESET i Comes with web interface for easy built in web server Serial Wire Debug supported Serial Wire Viewer supported Comes with built in licenses for for ARM cores It is ems which are sup page 19 J Link Pro ndication TCP IP configuration Download speed up to 3 MByte
340. ve reset is pulled low and remains low while connecting to the target This is the recommended reset strategy for STM32 devices This reset strategy has been designed for the case that communi cation with the core is not possible in normal mode so the vc CORERESET bit can not be set in order to guarantee that the core is halted immediately after reset J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 162 CHAPTER 5 Working with J Link and J Trace 5 8 2 5 Type 4 Reset core amp peripherals halt after bootloader Same as type 0 but bootloader is always executed This reset strategy has been designed for MCUs CPUs which have a bootloader located in ROM which needs to run at first after reset since it might initialize some target settings to their reset state When using this reset strategy J Link will let the bootloader run after reset and halts the target immediately after the bootloader and before the target application is started This is the recommended reset strategy for LPC11xx and LPC13xx devices where a bootloader should execute after reset to put the chip into the real reset state 5 8 2 6 5 Reset core amp peripherals halt before bootloader Basically the same as reset type 8 Performs a reset of core amp peripherals and halts the CPU immediately after reset The ROM bootloader is NOT executed 5 8 2 7 6 Reset for Freescale Kinetis devices Performs a via reset stra
341. wait 0x18 beos 0 200296 wait Oxla 4718 Finished executing setup script Downloading program text and data Please Wait Download complete running C Work Basic ghs J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 223 8 3 5 KEIL pVision IDE 8 3 5 1 Software version J Link has been tested with KEIL MDK 3 34 There should be no problems with other versions of KEIL uVision All screenshots are taken from MDK 3 34 8 3 5 2 Configuring to use J Link RDI Start KEIL uVision and open the project W Blinky p ision3 C Keil3030 ARMARY30 B oards Keil MCB 2300 Blinky Abstract txt es LPC2378 Flash A Blinky project a simple program for the LPC2378 using Keil MCB2300 Evaluation Board and demonstrating interrupt functionality Example functionality 9 Documentation Clock Settings XTAL PLL processor clock USB clock peripheral clock UART1 settings baudrate 9600 8 data bits 1 stop bits no parity TimerO timer is activating clock is every 1 second Starting conversion every 1 and displaying bargraph on 8 LEDs it works in interrupt mode D conversion is done in interrupt mode D value is sent every 1 second on UART1 text is displayed to textual LCD bargraph is displayed to textual LCD according to potentiometer position 8 LEDs state represent the potentiometer position
342. wer Free of charge utility for J Link Displays the terminal output of the target using the SWO pin The stimulus port s from which SWO data is received can be chosen by using the port checkboxes 0 to 31 Can be used in parallel with a debugger or stand alone This is especially useful when using debuggers which do not come with built in support for SWO such as most GDB GDB Eclipse based debug environments SEGGER J Link SWO Viewer V4 78j File Edit Help 0 e m x 16 15 if guy 0 Stop Clear 31 24 23 Data from stimulus HEREEERBR 4485 Loops sec 4485 Loops sec 4485 Loops sec 4485 Loops sec 4485 Loops sec 4485 Loops sec 4485 Loops sec 4485 Loops sec 4485 Loops sec 4485 E Loops sec 4485 IE 4 r Device STM32F103ZG CPUFreq 72016 kHz SWOFreq 6000 kHz 2984 bytes 3 7 0 4 J Link SWO Viewer CL Commandline only version of SWO Viewer commands avaible for J Link SWO Viewer be used with J Link SWO Viewer Similar to the GUI Version J Link SWO Viewer asks for a device name or CPU clock speed at startup to be able to calculate the correct SWO speed or to connect to a running J Link GDB Server CAProgram Files 686 SEGGERULinkARM V478jULinkSWOViewerCL exe o a SEGGER J Link SWO Viewer Compiled Nov 22 2613 20 09 16 lt c 2012
343. x 15 CRn CRm lt 1 gt lt op2 gt lt data gt Description Reads or writes from to cp15 register If data is specified this command writes the data to the cp15 register Otherwise this command reads from the cp15 register For further information please refer to the ARM reference manual Example Read gt monitor 15 1 2 6 7 lt Reading CP15 register 1 2 6 7 0x0460B77D Write gt monitor 15 1 2 6 7 OXFFFFFFFF 3 3 3 3 device Note Deprecated Use command line option device instead Syntax device lt DeviceName gt Description Selects the specified target device This is necessary for the connection and some special handling of the device Note The device should be selected via commandline option device when starting GDB Server Example gt monitor device 5 32 417 lt Selecting device STM32F417IG 3 3 3 4 DisableChecks Syntax DisableChecks J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 75 Description Disables checking if a memory read caused an abort ARM7 9 devices only On some CPUs during the init sequence for enabling access to the internal memory for exam ple on the TMS470 some dummy reads of memory are required which will cause an abort as long as the access init is not completed 3 3 3 5 EnableChecks Syntax EnableChecks Description Enables checking if a memory read caused an
344. y faster than using WriteMemory for RAM download because the overhead is lower 11 4 4 Available options for flash programming There are different solutions available to program internal or external flashes con nected to ARM cores using J Link J Trace The different solutions have different fields of application but of course also some overlap 11 4 4 1 J Flash Complete flash programming solution J Flash is a stand alone Windows application which can read write data files and program the flash in almost any ARM system J Flash requires an extra license from SEGGER 11 4 4 2 RDI flash loader Allows flash download from any RDI compliant tool chain RDI Remote debug interface is a standard for debug transfer agents such as J Link It allows using J Link from any RDI compliant debugger RDI by itself does not include download to flash To debug in flash you need to somehow program your application program debuggee into the flash You can use J Flash for this purpose use the flash loader supplied by the debugger company if they supply a matching flash loader or use the flash loader integrated in the J Link RDI software The RDI software as well as the RDI flash loader require licenses from SEGGER J Link J Trace 0 08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 299 11 4 4 3 Flash loader of compiler debugger vendor such as IAR A lot of debuggers some of them integrated into an IDE come with their ow
345. y kHz 72016 Measure f Cancel When running in normal mode J Link SWO Viewer automatically performs the neces sary initialization to enable SWO output on the target in GDB Server mode the ini tialization has to be done by the debugger 3 7 2 List of available command line options J Link SWO Viewer can also be controlled from the command line if used in a auto mated test environment etc When passing all necessary information to the utility via command line the configu ration dialog at startup is suppressed Minimum information needed by J Link SWO Viewer is the device name to enable CPU frequency auto detection or the CPU clock speed The table below lists the commands accepted by the J Link SWO Viewer Command Description cpufreq Select the CPU frequency device Select the target device Selects a set of itm stimulus ports which should be used itmmask to listen to 1 Selects a itm stimulus port which should be used to listen itmport to outputfile Print the output of SWO Viewer to the selected file settingsfile Specify a J Link settings file swofreq Select the CPU frequency Table 3 12 Available command line options 3 7 2 4 cpufreq Defines the speed in Hz the CPU is running at If the CPU is for example running at 96 MHz the command line should look as below Syntax cpufreq lt gt Example cpufreq 96000000 3 7 2 2 device Select the targ
346. yntax halt Example jlinkgdbserver halt 3 3 5 11 noir Description Do not initialize the CPU registers on startup Note For the GUI version this setting is persistent for following uses of GDB Server until changed via ir or the GUI Syntax noir 3 3 5 12 nolocalhostonly Description Starts GDB Server with the option to allow remote connections from outside local host Same as localhostonly 0 Note For the GUI version this setting is persistent for following uses of GDB Server until changed via command line option or the GUI Syntax nolocalhostonly 3 3 5 13 nologtofile Description Starts the GDB Server with the option to not write the output into a log file Note For the GUI version this setting is persistent for following uses of GDB Server until changed via nologtofile or the GUI Note When this option is used after log no log file will be generated when log is used after this option a log file will be generated and this setting will be overrid den Syntax nologtofile Example jlinkgdbserver nologtofile Will not generate a log file jlinkgdbserver nologtofile log C pathto file log Will generate log file jlinkgdbserver log C pathto file log nologtofile Will not generate a log file J Link J Trace UM08001 2004 2014 SEGGER Microcontroller GmbH amp Co KG 93 3 3 5 14 nohalt Description When connecting to the target after starting GDB Se

J-Link / J-Trace User Guide (UM08001)

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