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1. 12 1 Function Description eire tte eur terere eie b debeam im 12 1 Timer 0 Control Register T0CONJ 12 2 Block Diagram LEE 12 3 eere eti eo dus e debe ca tee 12 4 IATER 12 4 Timer 1 Control Register T1CON a n r 12 5 Timer 1 Functior Description ite eoe perte er ie e eO d etes tee Red 12 6 Block Diagram ete delete tope diesen up ie ee otii 12 9 Chapter 13 Watch Timer OVOIVIOW AE estate d E e o sia 13 1 Watch Timer Control Register 8 13 2 Watch Timer Circuit Diagram t eu Rete epe M qe e etui esed be ERR ete 13 3 Chapter 14 LCD Controller Driver OVGIVIOW u eee M 14 1 ECD Circ it eed vn elie e m eoe date e Ber 14 2 LGD RAM Address Area citerior ee ic Rue rs e ie o Rok eae a e eat e ed niece 14 3 LCD Gontrol Register EGON 2 1 eee oi evn atte GL re re ecc ree rte etie 14 4 LCD Voltage Dividing RESI Stor nisasie de S Oe SU ey ee 14 5 Common COM Signals creto eee ee eoe eoe a po Ere ua 14 6 Segment SE Sign ls tnde perdidit vem dee 14 6 viii S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER Table of Contents conti
2. 18 3 19 1 Flash Memory Control Register 19 3 19 2 Flash Memory User Programming Enable Register FMUSR 19 4 19 3 Flash Memory Sector Address Register High Byte FMSECH 19 5 19 4 Flash Memory Sector Address Register Low Byte FMSECL 19 5 19 5 Program Memory Address 19 6 19 6 Sector Configurations in User Program 19 8 20 1 Input Timing for External Interrupts seen nm 20 5 20 2 Input Timing for nRESET u u S uu eire eei i err cox d Rl uc 20 5 20 3 Stop Mode Release Timing Initiated by 20 6 20 4 Stop Mode Release Timing Initiated by 20 7 20 5 LVR Low Voltage Reset Timing eene 20 9 20 6 Serial Data Transfer 2 20 10 20 7 Waveform for UART Timing Characteristics 20 11 20 8 Timing Waveform for the UART 20 12 20 9 Clock Timing Measurement at 20 14 20 10 Clock Timing Measurement at 20 14 20 11 Operating Voltage harige i veas Eee tenia 20 15 21 1 Package Dimensions 80 1420
3. Shift RIP Figure 17 9 Timing Diagram for Serial Port Mode 3 Operation 17 10 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 UART SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS S3C8 series multiprocessor communication features lets a master S3C828B F828B C8289 F8289 C8285 F8285 send a multiple frame serial message to a slave device in a multi S3C828B F828B C8289 F8289 C8285 F8285 configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART modes 2 or 3 In these modes 2 and 3 9 data bits are received The 9th bit value is written to RB8 UARTCON 2 The data receive operation is concluded with a stop bit You can program this function so that when the stop bit is received the serial interrupt will be generated only if RB8 1 To enable this feature you set the MCE bit in the UARTCON register When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identity the
4. shiu uA d eai node a dee atu eei iere 10 1 Basic Timer BT 15 A quer iiv ae eni 10 1 Basic Timer Control Register 22 4 044 2 2 0 1110 00000006 00 0 800 0 nennen ennt 10 1 Basic Timer Function Description cess u aite ioco eie dh te tid e De de 10 3 S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER vii Table of Contents continued Chapter 11 8 bit Timer A B 8 Bit Timer Aceite imul eie tu d eese duele HO nut Ire dO 11 1 11 1 Timer A Control Register 11 2 Timer A Function Description sissie tti e cce Dite tem Biya Db Lae egal suas 11 3 Block Diagram E Rite demde pie entend eoe degit in eerie iudi Du Haee uae ios 11 6 8 Bit Timer teed ee 11 7 OV EIMIOW EROR cea been geen ce bak anes acd EE oe 11 7 sees tte a un 11 8 Timer B Pulse Width Calculations 11 9 12 16 bit Timer 0 1 uii oa erc IR EL e ddl 12 1 iu
5. 4 12 IMR Interrupt Mask nenne nnne 4 13 INTPND Interrupt Pending Register 5 2 en cd or deer Poe 4 14 IPH Instruction Pointer High Byte emen 4 15 IPL Instruction Pointer Low Byte 4 15 IPR Interrupt Priority Register pirining aa a usasapa 4 16 IRQ Interrupt Request 4 17 LCON LGD Gontrol Register nente eet aks aca 4 18 OSCCON Oscillator Control sak u ake uushami a ua 4 19 Port 0 Control Register High 4 20 POCONL Port 0 Control Register Low Byte 2 4 21 POINTH Port 0 Interrupt Control Register High Byte 4 22 POINTL Port 0 Interrupt Control Register Low 4 23 POPND Port 0 Interrupt Pending Register essere 4 24 P1CONH Port 1 Control Register High 4 25 P1CONL Port 1 Control Register Low ene 4 26 P1PUR Port 1 Pull up Resistor Enable Register 4 27 P2CONH Port 2 Control Register High Byte enn 4 28 P2CONL Port 2 Control Register Low Byte 2 4 29 Port Control Register High 4 30 P3CONL Port Control Register Low Byte
6. aii eee ge ee ea 0 Figure 14 10 LCD Signal Waveforms 1 8 Duty 1 4 Bias Continued ELECTRONICS 14 11 LCD CONTROLLER DRIVER S3C828B F828B C8289 F8289 C8285 F8285 NOTES 14 12 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 A D CONVERTER 10 BIT ANALOG TO DIGITAL CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 bit digital values The analog input level must lie between the AV pep AVgg values The A D converter has the following components Analog comparator with successive approximation logic D A converter logic resistor string type control register ADCON Eight multiplexed analog data input pins ADO AD7 10 bit A D conversion data output register ADDATAH L 8 bit digital input port Alternately I O port AVpe_r pins AV gg is internally connected to Vas FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at the first you must set ADCEN signal for ADC input enable at port 2 the pin set with 1 can be used for ADC analog input And you write the channel selection data in the A D converter control register ADCON 4 7 to select one of the eight analog input pins ADCO 7 and set the conversion start or enable bit ADCON O The read write ADCON register is located in se
7. 16 3 16 4 Serial I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 16 4 16 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 16 4 3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER xiii List of Figures Concluded Page Title Page Number Number 17 1 UART Control Register 17 2 17 2 UART Interrupt Pending Bits 5 4 17 3 17 3 UART Data Register 17 4 17 4 UART Baud Rate Data Register 17 4 17 5 UART Functional Block 17 6 17 6 Timing Diagram for Serial Port Mode 0 Operation 17 7 17 7 Timing Diagram for Serial Port Mode 1 Operation 17 8 17 8 Timing Diagram for Serial Port Mode 2 Operation 17 9 17 9 Timing Diagram for Serial Port Mode Operation 17 10 17 10 Connection Example for Multiprocessor Serial Data Communications 17 12 18 1 Block Diagram for Battery Level 18 1 18 2 Battery Level Detector Control Register 18 2 18 3 Battery Level Detector Circuit and Block Diagram
8. 19 2 19 2 ISP sector size edt d n ee ie te SO eda Dh ete exes 19 7 19 3 iue teet ie edge e n Retired 19 7 20 1 Absolute Maximum 20 2 20 2 D C Electrical 20 2 20 3 A C Electrical Characteristics 20 5 20 4 Input Output Gapacitance l u 2 one tono oe ete t Pe m e cmn 20 6 20 5 Data Retention Supply Voltage in Stop Mode 20 6 20 6 A D Converter Electrical Characteristics 20 8 20 7 Low Voltage Reset Electrical Characteristics a a 20 9 20 8 Battery Level Detector Electrical 20 9 20 9 Synchronous SIO Electrical Characteristics esse 20 10 20 10 UART TIMING characteristics IN MODE 0 11 1MH2 20 11 20 11 Main Oscillator Characteristics 40040 20 13 20 12 Sub Oscillation Characteristics 20 13 20 13 Main Oscillation Stabilization Time 20 14 20 14 Sub Oscillation Stabilization Time ccecccceeccccecceececeeeeseeceeeeeceeeeeenseeseeeeessneeeeenees 20 14 20 15 Internal Flash ROM Electrical Characteri
9. 00040000 000 21 1 21 2 Package Dimensions 80 1212 00 4400 21 2 22 1 S3F828B F8289 F8285 Pin Assignments 80 1420 22 2 22 2 S3F828B F8289 F8285 Pin Assignments 80 1212 22 3 22 3 Operating Voltage Range ooo ee rite be dei teret 22 6 23 1 SMDS Product Configuration 5 52 23 2 23 2 TB828B 9 5 Target Board Configuration eee 23 3 23 3 40 Pin Connectors J101 J102 for 828 9 5 23 7 23 4 S3E8280 Cables for 80 QFP 23 7 xiv S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER List of Tables Table Title Page Number Number 1 1 S3C828B F828B C8289 F8289 C8285 F8285 Pin Descriptions 1 7 2 1 S3C828B F828B Register Type 2 4 2 2 S3C8289 F8289 Register Type 2 5 2 3 S3C8285 F8285 Register Type 2 5 4 1 Set TREGISISS a aie e ee 4 1 4 2 Set 1 Bank 0 Registers uu u sua au ates 4 2 4 3 Set Bank 1 Regislets ia u ona rii hana eia us 4 3 5 1 Interr pt Vectors u neri 5 6 5 2 Interrupt Contr
10. 4 31 P4CONH Port 4 Control Register High Byte 4 32 P4CONL Port 4 Control Register Low 4 33 P4PUR Port 4 Pull up Resistor Enable Register 4 34 S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER xix List of Register Descriptions Continued Register Full Register Name Page Identifier Number P5CONH Port 5 Control Register High 4 35 P5CONL Port 5 Control Register LOW 4 36 P5PUR Port 5 Pull up Resistor Enable 4 37 P6CONH Port 6 Control Register High 4 38 P6CONL Port 6 Control Register Low 4 39 P7CON Port 7 2 2 e iee i 4 40 P8CON Port 8 Control Register u l n cel ce ee eee riim ds 4 41 PP Register Page Pointer csc dec eddie di eed iode kena 4 42 RPO Register Pointer ee ee DD pet e ba D pex bte iod 4 43 RP1 Register Pointer u ERR n 4 43 SIOCON SIG Gontrol Ftegislter ss L h ead 4 44 SPH Stack Pointer High 4 45 SPL Stack Pointer Low Byte Ae deed 4 45 STPCON Stop Control Register u teet deed edere edet usa al 4 46 SYM System Mode Register si rem edt ibn
11. 4 32 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER P4CONL Port 4 Control Register Low Byte EDH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 3 SEG21 0 Input mode 1 Output mode N channel open drain 1110 Output mode push pull Alternative function SEG21 5 4 P4 2 SEG20 Input mode Output mode N channel open drain Output mode push pull 1 Alternative function SEG20 3 2 4 1 5 19 0 0 Input mode 1 Output mode N channel open drain 0 1 0 Output mode push pull 1 Alternative function SEG19 0 0 Input mode 0 Output mode N channel open drain Output mode push pull Alternative function SEG18 ELECTRONICS 4 33 CONTROL REGISTERS S3C828B F828B C8289 F8289 C8285 F8285 P4PUR Port 4 Pull up Resistor Enable Register EEH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P4 7 Pull up Resistor Enable Bit 0 Pull up disable Pull up enable 6 P4 6 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 5 P4 5 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 4 P4 4 Pull up Resistor Enable Bit EN Pull up disable Pull up enable 3 P4 3 Pull up Resistor Enable Bit 0 Pull up disable
12. aee dm EHE ones tele aa ua teenie 1 1 Features i ei gei uU RU qub etui E 1 2 Block Biagram E 1 4 Pin ASsigrimebt AE eee 1 5 ua Sasu nasa aa 1 7 SS u u Re ie uqaqa V Rr ne 1 9 Chapter 2 Address Spaces OVV OW nahen derer dansq tienen adu Eee 2 1 Program Memory FIO M sce ccs accorde Su ehem te te ege s on ae u s ku 2 2 SMart Options oin edet tta EQ aae ee d ese x ede dead ohn i 2 3 Register Architecture oon erede t eds eer Podere uve sabe aude Ue e e doe du Ro uve eee tva dace 2 4 ect ventes edet edid anna aed 2 9 Register Set 1 td PE PERCHE n ie E een Be 2 11 Register pM un a ii e i E E 2 11 Prime Register Space di a Na u 2 12 Working Registers sic ia sleet usus a uu eee 2 13 Using The Register Poi its iie Ee ee RO eod lee kei ce Erg 2 14 Register Addressing u eodem rv et do Rr E d 2 16 Common Working Register A
13. input INTPNDS Capture INT Match Signal Pending T1CON 4 3 T1CON 4 3 Timer 1 Data Register Figure 12 6 Simplified Timer 1 Function Diagram Capture Mode 12 8 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 16 BIT TIMER 0 1 BLOCK DIAGRAM T1CON O 1 7 5 OVF H INTPND 2 IRQ3 Data Bus 104 gt T1CON 2 256 _ fxx64 I Clear 8 16 bit Up Counter R fxx 1 U Read Only x T1CON 1 0 4 TAINT INTPND 3 IRQ3 T1OUT 0 1 X T1CON 4 3 T1CON 4 3 Match Signal T1CON T1OVF Timer 1 Data Register Data Bus Figure 12 7 Timer 1 Functional Block Diagram ELECTRONICS 12 9 16 BIT 0 1 53 828 828 8289 8289 8285 8285 NOTES 12 10 ELECTRONICS 3C822B F822B C8289 F8289 C8285 F8285 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set bit 1 of the watch timer control register WTCON 1 to 1 And if you want to service watch timer overflow interrupt IRQ5 vector EEH then set the WTCON 6 to 1 The watch timer overflow interrupt pending condition WTCON 0 must be cleared by software the application s interrupt service routine by means of writing a 0 to the WTCON O interrupt pending
14. seen 6 6 7 1 Crystal Ceramic Oscillator fX u u su s U a uuu umu a usss 7 2 7 2 External Oscillator fX science u idees nce eevee 7 2 7 3 RG Oscillator o 7 2 7 4 Crystal Ceramic Oscillator fxr 7 2 7 5 Crystal Ceramic Oscillator fxT for low 7 2 7 6 External Oscillator DL ertet ete ied diet dl vest dens 7 2 7 7 System Clock Circuit 7 3 7 8 System Clock Control Register 2 7 4 7 9 Oscillator Control Register 05 7 5 7 10 STOP Control Register 5 7 5 9 1 Port 0 High Byte Control Register 9 4 9 2 Port 0 Low Byte Control Register 9 4 9 3 Port 0 High Byte Interrupt Control Register 9 5 9 4 Port 0 Low Byte Interrupt Control 9 5 9 5 Port 0 Interrupt Pending Register 9 6 9 6 Port 1 High Byte Control Register 9 7 9 7 Port 1 Low Byte Control Register 9 8 9 8 Port 1 Pull up Resistor Enable Register 1
15. 0 Set watch timer interrupt to 0 25s 1 Set watch timer interrupt to 3 91ms al Watch Timer Enable Bit EN Disable watch timer Clear frequency dividing circuits Enable watch timer 0 Watch Timer Interrupt Pending Bit EN No interrupt pending when read clear pending bit when write Interrupt is pending when read NOTE Watch timer clock frequency fw is assumed to be 32 768 kHz ELECTRONICS 4 5 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 5 4 54 ELECTRONICS 53 828 828 8289 8289 8285 8285 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and I O blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels 0 also called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from dev
16. 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 AO RR 8 Al IR Given RO 1AH R1 O2H registerO2H OFH and register 03H OFFH INCW RRO gt RO 1AH R1 03H INCW R1 gt Register 02H 10H register 03H OOH In the first example the working register pair RRO contains the value 1AH in register RO and 02H in register R1 The statement NCW RRO increments the 16 bit destination by one leaving the value 03H in register R1 In the second example the statement NCW R1 uses Indirect Register IR addressing mode to increment the contents of general register 03H from OFFH to 00H and register 02H from OFH to 10H A system malfunction may occur if you use a Zero 2 flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP INOCW RRO LD R2 R1 OR R2 RO JR NZLOOP ELECTRONICS 6 45 INSTRUCT
17. 4FFH 1024 Bytes 100H 8FFH 2048 Bytes NOTE The selection of the ISP reset vector address by Smart Option 003CH 7 003CH 5 is not dependent of the selection of ISP sector size by Smart Option 003CH 2 003CH 0 ELECTRONICS 19 7 EMBEDDED FLASH MEMORY INTERFACE S3C828B F828B C8289 F8289 C8285 F8285 SECTOR ERASE User can erase a flash memory partially by using sector erase function only in User Program Mode The only unit of flash memory to be erased and programmed in User Program Mode is called sector The program memory of S3F828B is divided into 512 sectors for unit of erase and programming respectively Every sector has all 128 byte sizes of program memory areas So each sector should be erased first to program a new data byte into a sector Minimum 10ms delay time for erase is required after setting sector address and triggering erase start bit 0 Sector Erase is not supported in Tool Program Modes MDS mode tool or Programming tool Sector 511 128 byte Sector 510 128 byte Sector 127 128 byte Sector 11 128 byte Sector 10 128 byte Sector 0 9 128 byte x 10 S3F828B Figure 19 6 Sector Configurations in User Program Mode 19 8 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 EMBEDDED FLASH MEMORY INTERFACE THE SECTOR ERASE PROGRAM PROCEDURE IN USER PROGRAM MODE Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memor
18. 8data bits LSB first Stop bit 1 When receiving the stop bit is written to the RB8 bit in the UARTCON register The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the baud rate generated by BRDATA 2 Select mode 1 8 bit UART by setting UARTCON bits 7 and 6 to 01B 3 Write transmission data to the shift register UDATA F7H set 1 bank 0 The start and stop bits are generated automatically by hardware Mode 1 Receive Procedure 1 Select the baud rate to be generated by BRDATA 2 Select mode 1 and set the RE Receive Enable bit in the UARTCON register to 1 3 The start bit low 0 condition at the RxD P3 5 pin will cause the UART module to start the serial data receive operation lee fL gm dL Write to Shift Register UDATA Start Bit DO Stop Bit Transmit Mee TL JL Rn JL mL Om gu giam RxD Start Bit DO D1 D2 D3 D4 D5 D6 D7 Stop Bit Bit Detect Sample Time I ng RIP Figure 17 7 Timing Diagram for Serial Port Mode 1 Operation 17 8 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 UART SERIAL PORT MODE 2 FUNCTION DESCRIPTION In mode 2 11 bits are transmitted through the TxD P3 4 pin or received through the RxD P3 5 pin Each data frame has four components
19. Figure 14 1 LCD Function Diagram ELECTRONICS 14 1 LCD CONTROLLER DRIVER 53 828 828 8289 8289 8285 8285 LCD CIRCUIT DIAGRAM SEG37 P3 3 SEG Port SEG18 P4 0 Driver SEG10 P6 0 SEG6 P7 0 LCD Displa RAM COM7 SEG5 P8 7 FOOH F25H i COM Port COM3 SEG1 P8 3 Driver COM2 SEGO P8 2 COM 1 P8 1 COMO P8 0 Data Bus Timing Controller LCD Voltage Control Figure 14 2 LCD Circuit Diagram 14 2 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA RAM addresses of page 15 are used as LCD data memory These locations can be addressed by 1 bit or 8 bit instructions If the bit value of a display segment is 1 the LCD display is turned on If the bit value is 0 the display is turned off Display RAM data are sent out through the segment pins SEGO SEG37 using the direct memory access DMA method that is synchronized with the f signal RAM addresses in this location that are not used for LCD display can be allocated to general purpose use SEG36 SEG37 00 COMO 1 2 COMS 4 5 COM6 COM7 Som Oj o Figure 14 3 LCD Display Data RAM Organization ELECTRONICS 14 3 LCD CONTROLLER DRIVER 53 828 828 8289 8289 8285 8285 LCD CONTROL REGISTER LCON ALCON is located in page 15 of set1 bankO at address DOH and is read write addressable using
20. Timer B Clock TBOF 1 TBDATAL DEH TBDATAH 1EH TBOF 0 TBDATAL DEH TBDATAH 1EH TBOF 1 TBDATAL 7EH TBDATAH 7EH TBOF 0 TBDATAL 7EH TBDATAH 7EH Figure 11 8 Timer B Output Flip Flop Waveforms in Repeat Mode 11 10 ELECTRONICS 53 828 828 8289 8289 8285 8285 8 BIT PROGRAMMING TIP To generate 38 kHz 1 3duty signal through P3 0 This example sets Timer B to the repeat mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are 8 795 us 17 59 us 37 9 kHz 1 3 Duty Timer B is used in repeat mode Oscillation frequency is 4 MHz 0 25 us TBDATAH 8 795 us 0 25 us 35 18 TBDATAL 17 59 us 0 25 us 70 36 Set P3 0 to TBPWM mode ORG 0100H Reset address START DI LD TBDATAL 70 2 Set17 5 us LD TBDATAH 35 2 Set 8 75 us LD TBCON 00000110B Clock Source fxx Disable Timer B interrupt Select repeat mode for Timer B Start Timer B operation Set Timer B Output flip flop TBOF high LD P3CONL 02H Set P3 0 to TBPWM mode This command generates 38 kHz 1 3 duty pulse signal through P3 0 ELECTRONICS 11 11 8 BIT A B S3C828B F828B C8289 F8289 C8285 F8285 PROGRAMMING TIP To generate a one pulse signal through P3 0 This example sets Timer B to the one shot mode
21. dst 2 4 EO R 1 IR Given RegisterOOH register 01H 02H and register 02H 17H RR 00H gt RegisterOOH 98H C 1 RR 01H gt Register 01H 02H register 02H 8BH C 1 In the first example if general register OOH contains the value 31H 00110001B the statement RR 00H rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 RRC Rotate Right Through Carry RRC Operation dst dst 7 lt C lt dst 0 dst lt dst n 1 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB Flags Format Examples 6 74 C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set ifthe result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 CO R C1 IR
22. tSCK tHIGH lt gt 1 0 7VDD 0 3VDD Figure 20 7 Waveform for UART Timing Characteristics ELECTRONICS 20 11 ELECTRICAL DATA S3C828B F828B C8289 F8289 C8285 F8285 20 12 Shift 4 lt gt Data 14 151 0 D1 Out D MEN Data In Vai Kaio Vaid Valio NOTE symbols shown in this diagram are defined as follows fsck Serial port clock cycle time ts1 Output data setup to clock rising edge ts2 Clock rising edge to input data valid Output data hold after clock rising edge tH2 Input data hold after clock rising edge Figure 20 8 Timing Waveform for the UART Module ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 ELECTRICAL DATA Table 20 11 Main Oscillator Characteristics TA 25 C to 85 C Oscillator Clock Configuration Parameter Test Condition kas Typ Units Main oscillation 3 0V 3 6V 0 4 MHz frequency 20 3 6 0 4 Main oscillation 3 0 V 3 6 V 0 4 Oscillator frequency wn External Xin input frequency 3 0V 3 6V 0 4 Clock MN 2 0 V 3 6 V 0 4 RC Frequency 3 3 V 0 4 MHz Oscillator Table 20 12 Sub Oscillation Characteristics TA 25 C to 85 C Oscillator Clock Configuration Parameter Test Condition Max Units Crystal Sub oscillation 2 0 V 3 6 V 35 kHz XTn requency OSCCON
23. IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 CLR XOR XOR XOR IR1 r1 r2 r1 lr2 R2 R1 RRC CPIJE LDC LDW IR1 Ir r2 RA ri lrr2 RR2 RR1 SRA CPIJNE LDC CALL IR1 Irr r2 RA r2 Irr1 IA1 RR LDCD LDCI LD IR1 r1 Irr2 r1 lrr2 R2 R1 LDCPD ra Irr1 LDCPI ra lrr1 SWAP CALL IR1 IRR1 XOR IR2 R1 LDW IR2 RR1 LD R2 IR1 LD IR2 R1 6 ADD R1 IM ADC R1 IM SUB R1 IM SBC R1 IM OR R1 IM AND R1 IM TCM R1 IM TM R1 IM MULT IM RR1 DIV IM RR1 CP R1 IM XOR R1 IM LDW RR1 IML LD IR1 IM LD R1 IM CALL DA1 7 BOR ro Rb BCP r1 b R2 BXOR ro Rb BTJR r2 b RA LDB ro Rb BITC r1 b BAND ro Rb BIT r1 b LD r1 x r2 LD r2 x r1 LDC r1 Irr2 xL LDC r2 Irr2 xL LD r1 Ir2 LD Ir r2 LDC r1 Irr2 xs LDC r2 xs ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX D E JP INC cc DA WFI SBO SB1 IDLE STOP DI El RET IRET RCF SCF CCF JP ING cc DA ELECTRONICS INSTRUCTION SET 53 828 828 8289 8289 8285 8285 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump
24. In the second example OOH is the destination register The statement LD 00H 0 RO loads bit zero of register RO to the specified bit bit zero of the destination register leaving 04H in general register 00H ELECTRONICS 6 51 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 LDC LDE Load Memory LDC LDE dst src Operation dst lt src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes or rr values an even number for program memory and odd odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 opc dst src 2 10 C3 r Irr 2 opc src dst 2 10 D3 Irr r 3 opc dst src XS 3 12 E7 r XS rr 4 opc src dst XS 3 12 F7 XS rr r 5 opc dst src XL XLy 4 14 r XL rr 6 opc src dst XL XLy 4 14 B7 XL rr r 7 dst 0000 DA DA 4 14 A7 r DA 8 opc src 0000 DA DA 4 14 B7 DA r 9 dst 0001 DA DA 4 14 A7 r DA 10 src 0001 DA DA 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats and 4 the destination address XS rr and the source address XS rr are each one byte 3 For formats 5 6 the destination address rr and
25. PORTS PORT 5 Port 5 is an 8 bit I O port with individually configurable pins Port 5 pins are accessed directly by writing or reading the port 5 data register P5 at location in set 1 bank 1 P5 0 P5 7 can serve as inputs with without pull ups as output open drain or push pull And they can serve as segment pins for LCD also Port 5 Control Registers P5CONL Port 5 has two 8 bit control registers for P5 4 P5 7 and PSCONL for P5 0 P5 3 A reset clears the P5CONH and P5CONL registers to configuring all pins to input mode Port 5 Pull up Resistor Enable Register P5PUR Using the port 5 pull up resistor enable register set1 bank1 you can configure pull up resistors to individual port 5 pins Port 5 Control Register High Byte 5 F9H Set 1 Bank 1 R W mw 4 SEG30 EN 5 SEG31 P5 6 SEG32 P5 7 SEG33 P5CONH bit pair pin configuration settings 00 Input mode Output mode N channel open drain Output mode push pull Alternative function SEG33 SEG30 Figure 9 16 Port 5 High Byte Control Register PSCONH ELECTRONICS 9 15 PORTS S3C828B F828B C8289 F8289 C8285 F8285 Port 5 Control Register Low Byte PSCONL Set 1 Bank 1 R W P5 0 SEG26 us 1 SEG27 P5 2 SEG28 P5 3 SEG29 P5CONL bit pair pin configuration settings Input mode Output mode N channel open drain Output mode push pull Alternative function
26. dst src dst dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Set if a borrow occurred cleared otherwise Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise Always set to 1 Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src dst 2 4 22 r r src 6 23 r Ir src dst 3 6 24 R R 25 R IR dst src 3 6 26 R IM Given R1 12H R2 registerO1H 21H register 02H register OAH SUB R1 R2 gt R1 OFH R2 03H SUB R1 R2 gt R1 08H R2 03H SUB 01H 02H gt Register 01H register 02H gt E SUB 01H 02H Register 01H 17H register 02H SUB 01H 90H RegisterO1H 91H C S andV 1 SUB 01H 265H gt Register 01H OBCH CandS 1 V o In the first example if working register R1 contains the value 12H and if register R2 contains the value the statement SUB
27. 9 8 9 9 Port 2 High Byte Control Register 2 9 9 9 10 Port 2 Low Byte Control Register 2 9 10 9 11 Port High Byte Control Register 9 11 9 12 Port Low Byte Control Register 9 12 9 13 Port 4 High Byte Control Register PACONH seen 9 13 9 14 Port 4 Low Byte Control Register PACONL eee 9 14 9 15 Port 4 Pull up Resistor Enable Register P4PUR 9 14 9 16 Port 5 High Byte Control Register PBCONH seen 9 15 9 17 Port 5 Low Byte Control Register 9 16 9 18 Port 5 Pull up Resistor Enable Register 5 9 16 9 19 Port 6 High byte Control Register PeCONH 9 17 9 20 Port 6 Low byte Control Register PO amp CONL seen 9 18 9 21 Port 7 Control Register 2 9 19 9 22 Port 8 Control Register 1 9 20 xii S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER List of Figures Continued Page Title Page Number Number 10 1 Basic Ti
28. In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value 00001110B ELECTRONICS 6 29 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 dst src Operation dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison Flags Set if a borrow occurred src gt dst cleared otherwise Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc dst 2 4 A2 r r src 6 A3 r Ir src dst 3 6 A4 R R A5 R IR dst src 3 6 A6 R IM Examples 1 Given R1 O2Hand R2 03H CP R1 R2 gt Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 B 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which
29. Source page 9 not used for the S3C8289 5 1111 Destination Page 15 0001 Source page 15 Others Not used for the S3C828B 9 5 Others Not used for the S3C828B 9 5 NOTES 1 In the 53 828 microcontroller the internal register file is configured as eleven pages Pages 0 9 15 The pages 0 9 are used for general purpose register file 2 In the S3C8289 microcontroller the internal register file is configured as five pages Pages 0 3 15 3 In the S3C8285 microcontroller the internal register file is configured as three pages Pages 0 1 15 The page 0 1 is used for general purpose register file 4 The page 15 of S3C828B 9 5 is used for LCD data register or general purpose regiser Figure 2 6 Register Page Pointer PP ELECTRONICS 2 9 ADDRESS SPACES 53 828 828 8289 8289 8285 8285 PROGRAMMING TIP Using the Page Pointer for RAM clear Page 0 Page 1 LD SRP LD RAMCLO CLR DJNZ CLR LD LD RAMCL1 CLR DJNZ CLR PP 00H 0COH R0 0FFH GRO RO RAMCLO GRO PP 10H RO 0FFH RO RO RAMCL1 GRO Destination 0 0 Page 0 RAM clear starts RO 00H Destination lt 1 Source 0 Page 1 RAM clear starts RO 00H NOTE You should refer to page 6 39 and use DJNZ instruction properly when DJNZ instruction is used in your program 2 10 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 ADDRESS SPACES REGISTER SET 1 The term set 1 refers to the upper 64 byt
30. Vpp 2 0 V to 3 6 V Symbol Conditions Max Unit Voltage of BLD BLDCON 2 0 000b 2 4 V BLDCON 2 0 101b 2 65 AV BLDCON 2 0 000 101 100 mv 0110 Current Consumption lBLD Vpp 3 3 V 120 uA BLD Circuit Response Time Tg fw 32 768 kHz 1 ms 209 ELECTRONICS 20 9 ELECTRICAL DATA S3C828B F828B C8289 F8289 C8285 F8285 Table 20 9 Synchronous SIO Electrical Characteristics Ta 25 C to 85 C Vpp 2 0 V to 3 6 V SCK Cycle time ines ns SCK high low width fae tig 500 S eee SI setup time to SCK high ii 250 peeves a SI hold time to SCK high um 400 BRENNEN S Output delay for SCK to SO tkso External SCK source 300 pee e NNNM SCK SI SO Output Data Figure 20 6 Serial Data Transfer Timing 20 10 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 ELECTRICAL DATA Table 20 10 UART Timing Characteristics in Mode 0 11 1MHz TA 25 C to 85 C Vpp 2 0 V to 3 6 V Load Capacitance 80pF Parameter Symbol Serial port clock cycle time Output data setup to clock rising edge 151 Clock rising edge to input data valid loo t Output data hold after clock rising edge Input data hold after clock rising edge Serial port clock High Low level width NOTES 1 Alltimings are in nanoseconds ns and assume a 11 1 MHz CPU clock frequency 2 The unit topy means one CPU clock period
31. fxx 4 100 AD4 1 1 fxx 1 101 AD5 110 AD6 End of conversion bit 111 AD7 0 Conversion not complete 1 Conversion complete Figure 15 1 A D Converter Control Register ADCON 15 2 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 A D CONVERTER A D Converter Data Register High Byte ADDATAH Set 1 Bank 0 Read Only A D Converter Data Register Low Byte ADDATAL F5H Set 1 Bank 0 Read Only wi J ns Figure 15 2 A D Converter Data Register ADDATAH L INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range AVss to AVper usually lt Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first conversion bit is always 1 2 AVper ELECTRONICS 15 3 A D CONVERTER 53 828 828 8289 8289 8285 8285 BLOCK DIAGRAM ADCON 2 1 ADCON 6 4 1 Select one input pin of the assigned pins Clock To ADCON 3 Selector EOC Flag AAA E ADCON O a AD C Enable Analog Input Pins Comparator ADC0 ADC7 U pproximation 2 0 2 7 Logic amp Register L1 X a ADCON 0 AD C Enable Upper 8 bit is loaded to E A D Conversion D
32. 2 0 V to 3 6 V Min Typ Max Uni Middle output Vpp 2 7V to 3 6V 1 4 bias 0 75Vpp 0 2 0 75Vpp 0 75Vpgp40 2 V Itage 1 LCD clock 0Hz Vi co V voltage LO DD 0 5Vpp 0 2 0 5Vpp 0 5Vpp 0 2 0 25Vpg 0 2 0 25 0 25Vpp 0 2 IV cp 15 pA per common pin mV Voltage drop i 0 7 IV SEGx 15 uA per common pin Voltage drop x 0 34 Supply current 2 Run mode Vpp 3 3V 0 3V Crystal oscillator C1 C2 22pF Idle mode Vpp 3 3V 0 3V Crystal oscillator C1 C2 22pF Run mode Vpp 3 3V 0 3V 25 C OSCON 7 1 32kHz crystal oscillator Idle mode Vpp 3 3V 0 3V 25 C OSCON 7 1 32kHz crystal oscillator Stop mode Vpp 3 3V 0 3V NOTES 1 It is middle output voltage when the Vpp and VI co pin are connected 2 Supply current does not include current drawn through internal pull up resistors LCD voltage dividing resistors the LVR block and external output current loads 3 l pp4 and include a power consumption of subsystem oscillator 4 and are the current when the main system clock oscillation stop and the subsystem clock is used OSCCON 7 1 Ipps is the current when the main and subsystem clock oscillation stops Every values in this table is measured when bits 4 3 of the system clock control register CLKCON 4 3 is set to 11B 20 4 ELECTRONICS 3C828B F828B C8289 F8289 C
33. Enable counting operation Timer 0 counter clear bit 0 No affect 1 Clear the timer 0 counter when write Figure 12 1 Timer 0 Control Register TOCON 12 2 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 16 BIT TIMER 0 1 BLOCK DIAGRAM Data Bus 16 bit up Counter H L Read Only fxx 256 M fxx 64 U fxx 8 fxx 1 X R Pending TOINT 16 bit Comparator IRQ2 Counter clear signal TOCON 3 or Match signal Timer 0 Data H L Reg Read Write Figure 12 2 Timer 0 Functional Block Diagram ELECTRONICS 12 3 16 BIT 0 1 53 828 828 8289 8289 8285 8285 16 BIT 1 OVERVIEW The 16 bit timer 1 is an 16 bit general purpose timer counter Timer 1 has three operating modes one of which you select using the appropriate T1CON setting Interval timer mode Toggle output at T1OUT pin Capture input mode with a rising or falling edge trigger at the T1CAP pin PWM mode T1PWM Timer 1 has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 or 1 with multiplexer External clock input 16 bit counter T1CNTH L 16 bit comparator and 16 bit reference data register T1 DATAH L O pins for capture input or PWM or match output T1 PWM T1OUT Timer 1 overflow interrupt IRQ3 vector
34. Hex 7 6 5 4 3 2 LOD Control Register 208 Watch Timer Control Register WTCON 209 DH 0 0 0 0 0 20 DH 0 SIO Control Register SIOCON 224 EOH 0 0 0 0 0 0 SlODataRegister SIODATA 225 EH 0 0 0 0 0 0 SIO Pre scaler Register Timer 0 Control Register SIOPS 226 EH 0 0 TOCON 227 E3H 0 0 Timer 0 Counter Register High Byte TOCNTH 228 0 0 0 0 Timer 0 Counter Register Low Byte Timer 0 Data Register High Byte row 29 es TODATAH Timer Control Register TACON 232 0 0 0 0 0 0 Timer A Counter Register 233 E9H 0 0 0 0 0 0 Timer 1 Control Register TICON 235 EBH 0 0 0 0 0 0 Timer 1 Counter Register High Byte Timer 1 Counter Register Low Byte Timer 1 Data Register High Byte T1CNTH 236 ECH 0 0 TICNTL 237 EDH 0 0 TIDATAH Timer B Data Register High Byte TBDATAH Timer B Control Register A D Converter Control Register TBCON 242 F2H ADCON 243 A D Converter Data Register Low Byte ADDATAL 245 FH UART Control Register UARTCON 246 FH 0 0 0 0 0 0 248 Interrupt Pending Register O x oj xi x ojo j2 2 ojojoj 2 jojoj ojojo OSO lol oO
35. IRQ2 gt IRQ3 IRQ4 0 1 0 gt gt 1 IRQ3 IRQ4 gt IRQ2 01 1 gt gt Subgroup 1 0 0 gt gt 0 IRQ3 gt IRQ4 1 0 1 gt gt 1 IRQ4 gt IRQ3 1 1 0 gt gt Group C 1 1 1 Undefined 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 Figure 5 8 Interrupt Priority Register IPR ELECTRONICS 5 13 INTERRUPT STRUCTURE 53 828 828 8289 8289 8285 8285 INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit O to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not
36. Set 1 Bank 1 R W 5 4 4 0 6 0 5 10 P6 1 SEG11 P6 2 SEG12 P6 3 SEG13 P6CONL bit pair pin configuration settings Input mode Input mode pull up Output mode push pull Alternative function SEG13 SEG10 Figure 9 20 Port 6 Low byte Control Register PECONL 9 18 ELECTRONICS 53 828 828 8289 8289 8285 8285 PORTS PORT 7 Port 7 is an 4 bit I O port with individually configurable pins Port 7 pins are accessed directly by writing or reading the port 7 data register P7 at location F7H in set 1 bank 1 P7 0 P7 3 can serve as inputs with without pull ups as push pull outputs And they can serve as segment pins for LCD also Port 7 Control Registers P7CON Port 7 has a 8 bit control registers P7CON for P7 0 P7 3 A reset clears the P7CON register to OOH configuring all pins to input mode Port 7 Control Register P7CON FDH Set 1 Bank 1 R W 5 4 j 0 P7 0 SEG6 P7 1 SEG7 P7 2 SEG8 P7 3 SEG9 P7CONH bit pair pin configuration settings Input mode Input mode pull up Output mode push pull Alternative function SEG9 SEG6 Figure 9 21 Port 7 Control Register P7CON ELECTRONICS 9 19 VO PORTS S3C828B F828B C8289 F8289 C8285 F8285 PORT8 Port 8 is an 8 bit I O port with individually configurable pins Port 8 pins are accessed directly by writing or reading the port 8 data register P8 at location F8H in set 1 bank 1 P8 0 P8 7 can se
37. The other slaves continue operating normally Full Duplex Multi S3C828B F828B C8289 F8289 C8285 F8285 Interconnect TxD RxD TxD Master Slave 1 RxD TxD RxD Slave 2 TxD RxD Slave n S3C828B 9 5 S3C828B 9 5 S3C828B 9 5 53 828 9 5 Figure 17 10 Connection Example for Multiprocessor Serial Data Communications 17 12 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 BATTERY LEVEL DETECTOR BATTERY LEVEL DETECTOR OVERVIEW The S3C828B F828B C8289 F8289 C8285 F8285 micro controller has a built in BLD Battery Level Detector circuit which allows detection of power voltage drop or external input level through software Turning the BLD operation on and off can be controlled by software Because the IC consumes a large amount of current during BLD operation It is recommended that the BLD operation should be kept OFF unless it is necessary Also the BLD criteria voltage can be set by the software The criteria voltage can be set by matching to one of the 3 kinds of voltage below that can be used 2 2 V 2 4 V or 2 8 V Vpp reference voltage or external input level External reference voltage The B p block works only when BLDCON 3 is set If Vpp level is lower than the reference voltage selected with BLDCON 2 0 BLDCON 4 will be set If Vpp level is higher BLDCON 4 will be cleared When users need to minimize current consumption do not operate the BLD block Vpp Pin H Battery
38. oio Oscillator control register INTPND 249 F9H OSCCON 250 FAH STOP control register STPCON 251 FBH o 0 0 0 0 Location FCH is not mapped Basic Timer Counter BTCNT 253 FOH o 0 0 O 0 Location FEH is not mapped ELECTRONICS gt x O gt x x O RESET and POWER DOWN S3C828B F828B C8289 F8289 C8285 F8285 Table 8 3 S3C828B F828B C8289 F8289 C8285 F8285 Set 1 Bank 1 Register and Values after RESET Register Name Flash Memory Sector Address Register FMSEC High Byte Flash Memory Sector Address Register FMSEC Low Byte Flash Memory Control Register FMCO Port 0 Control Register High Byte POCON Port 0 Control Register Low Byte POCON P Port 0 Interrupt Control Register POINT High Byte Port 0 Interrupt Control Register Low Byte OINT Port 0 Interrupt Pending Register POPND Bit Values after RESET Port 1 Pull up Resistor Enable Register P1PU Port 2 Control Register High Byte P2CON H L N H L H L Port 1 Control Register High Byte P1CONH Port 1 Control Register Low Byte P1CONL R H Port 2 Control Register Low Byte P2CONL Port 3 Control Register High Byte P3CONH L H Port 4 Control Register High Byte P4CON Port 1 Data Register Port 2 Data Register Port 8DataRe
39. was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 91 IR Given Register OAAH register 01H 02H and register 02H 17H RL 00H gt Register 00H 55H C 1 RL 01H gt Register 01H 02H register 02H 2EH C 0 In the first example if general register OOH contains the value OAAH 10101010B the statement RL 00H rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 71 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 RLC Rotate Left Through Carry RLC Operation dst dst 0 lt dst 7 dst n 1 lt n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Flags Format Examples 6 72 C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set ifthe result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D U
40. 1 BT clock Figure 20 4 Stop Mode Release Timing Initiated by Interrupts ELECTRONICS 20 7 ELECTRICAL DATA S3C828B F828B C8289 F8289 C8285 F8285 Table 20 6 A D Converter Electrical Characteristics TA 25 C to 85 C 2 7 V to 3 6 V Vss 0 V Resolution bit Vgg 3 072V 2 Differential linearity DLE Vss 0V i error CPU clock 10 MHz Offset error of top EOT 3 Offset error of bottom EOB 3 Conversion time 1 Tcow 10 bit resolution uS 50 x fxx 4 8 MHz Analog input voltage VIAN Vpp V Analog input impedance Analog reference AVREF Vpp V voltage Analog input current Vpp 3 3 V 5 uA Analog block current 2 lape Vpp 3 3 V 1 5 When power down mode NOTES 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 IADC is an operating current during A D converter 20 8 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 ELECTRICAL DATA Table 20 7 Low Voltage Reset Electrical Characteristics TA 25 C Parameter Symbol Test Condition Min Typ Max Unit Voltage of LVR Viva TA 25 C 2 0 EUM Vpp Voltage rising time NOTE current of LVR circuit is consumed when LVR is enabled by Smart Option Figure 20 5 LVR Low Voltage Reset Timing Table 20 8 Battery Level Detector Electrical Characteristics 25
41. 2 2 S3C8289 F8289 Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte 1 040 common working register area four 192 byte prime register area and four 64 byte set 2 area LCD data registers CPU and system control registers Mapped clock peripheral I O control and data registers Total Addressable Bytes General purpose registers including the 16 byte common working register area two 192 byte prime register area and two 64 byte set 2 area LCD data registers CPU and system control registers Mapped clock peripheral I O control and data registers Total Addressable Bytes ELECTRONICS 2 5 ADDRESS SPACES 53 828 828 8289 8289 8285 8285 1 Bank 0 System and Peripheral Control Registers Register Addressing Mode General Purpose Data Registers Indirect Register System Registers Indexed Mode and Register Addressing Mode Stack Operations General Purpose Register Register Addressing Mode Page 0 Prime 15 Data Registers 7 Prime All Addressing 7 Data Registers All addressing modes Los LCD Display Reigster Figure 2 3 Internal Register File Organization 53 828 828 Modes 2 6 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 Seti Bank 0 System and Peripheral Control Registers Register Addressing Mode System Registers Re
42. 3 3V during programming NOTES 1 Parentheses indicate pin number for 80 TQFP 1212 package 2 Vpp Test had batter connect to Vpp S3F828B only Table 22 2 Comparison of S3F828B F8289 F8285 and S3C828B C8289 C8285 Features S3F828B 9 5 S3C828B 9 5 64K 32K 16K byte Flash ROM 64K 32K 16K byte mask ROM Operating voltage 2 0 V to 3 6 V 2 0 V to 3 6 V Flash MCU programming mode Vpp 3 3 V TEST 12 5 V Programmability User program multi time Programmed at the factory 22 4 ELECTRONICS 53 828 828 8289 8289 8285 8285 S3F828B F8289 F8285 FLASH MCU OPERATING MODE CHARACTERISTICS When 12 5 V is supplied to the TEST pin of the 530828B C8289 C8285 the Flash ROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 22 3 below Table 22 3 Operating Mode Selection Criteria 15 0 3 3 V 0 Flash ROM read 12 5V 0 0000 Flash ROM program 12 5V 0 0000H Flash ROM verify 12 5V 1 Flash ROM read protection NOTES 1 The Vpp Test pin had batter connect to Vpp S3F828B only 2 0 means Low level 1 means High level Table 22 4 D C Electrical Characteristics TA 25 C to 85 C Vpp 2 0 V to 3 6 V Max Unit Supply current Run mode i 8 0 mA Vpp 3 3V 0 3V 36 Crystal oscillator C1 C2 22pF Idle mode 2 0 Vpp 3 3
43. 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example lt NOT The carry flag is complemented IfC 1 the value of the carry flag is changed to logic zero 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex ope 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 CLR clear CLR dst Operation dst lt 0 Flags
44. 67 SEG17 P6 7 66 SEG16 P6 6 65 Fo SEG15 P6 5 64 3 SEG14 P6 4 63 SEG13 P6 3 62 SEG12 P6 2 61 E3 SEG11 P6 1 NT4 23 NT5 24 4 P0 5 S3F828B F8289 F8285 80 TQFP 1212 NT6 C4 25 NT7 Cj 26 P1 0 TTCAP 4 27 P1 3 BUZ Cj 30 P1 4 SO 4 31 1 5 5 32 1 6 51 4 33 P2 0 ADO C 34 P24 AD1 35 P2 2 AD2 C3 36 7 6 28 P1 2 T1OUT T1PWM C4 29 P2 3 AD3 37 P2 4 AD4 C 38 P2 5 AD5 39 P2 6 AD6 J 40 S3F828B F8289 F8285 FLASH MCU SEG10 P6 0 SEG9 P7 3 SEG8 P7 2 SEG7 P7 1 SEG6 P7 0 COM7 SEG5 P8 7 COM6 SEG4 P8 6 COMBS SEG3 P8 5 COM4 SEG2 P8 4 COM3 SEG1 P8 3 COM2 SEGO P8 2 COM 1 P8 1 COMO P8 0 VLC3 VLC2 VLC1 VLCO AVss AVREF P2 7 AD7 VBLDREF 22 3 S3F828B F8289 F8285 FLASH MCU S3C828B F828B C8289 F8289 C8285 F8285 Table 22 1 Descriptions of Pins Used to Read Write the EPROM Main Chip During Programming Pin Name P3 4 Serial data pin Output port when reading and input port when writing Can be assigned as a Input push pull output port Serial clock pin Input only pin Power supply pin for Flash ROM cell writing indicates that FLASH MCU enters into the writing mode When 12 5 V is applied FLASH MCU is in writing mode and when 3 3 V is applied FLASH MCU is in reading mode Option nRESET nRESET Chip Initialization Vpn Vss Vpp Vss Power supply pin for logic circuit VDD should be tied to
45. 7 0b 2 2 V 3 6 V 35 L OSCCON 7 1b External XT y input 2 0 V 9 6 V 100 clock frequency ELECTRONICS 20 13 ELECTRICAL DATA S3C828B F828B C8289 F8289 C8285 F8285 Table 20 13 Main Oscillation Stabilization Time Ta 25 C to 85 C Vpp 2 0 V to 3 6 V Oscillator Test Condition Min Typ Crystal fx 1 MHz Oscillation stabilization occurs when Vpp is Ceramic uh equal to the minimum oscillator voltage range External clock Xin input high and low width ty 62 5 1 fx XIN Vpp 0 1V 0 1V 0 1V Figure 20 9 Clock Timing Measurement at Table 20 14 Sub Oscillation Stabilization Time TA 25 C to 85 C Vpp 2 0 V to 3 6 V Oscillator Test Condition Unit Eu pcm cue m External clock XT N input high and low width ty ty 5 15 ns Figure 20 10 Clock Timing Measurement at XT 20 14 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 ELECTRICAL DATA Instruction Clock fx Main Sub oscillation frequency 28MHz LL dh hume 2 5 MHz 10 MHz 1 05 MHz 4 2 MHz 6 25 kHz main 8 2kHz sub 400 kHz main 32 8 kHz sub Supply Voltage V Minimum instruction clock 1 4 x oscillator frequency n 1 2 8 16 Figure 20 11 Operating Voltage Range Table 20 15 Internal Flash ROM Electrical Characteristics TA 25 C to 85 C Vpp 2 0 V to 3 6 V Paramet
46. 8285 8285 PORTS 2 Port 2 is an 8 bit I O port that can be used for general purpose I O as A D converter inputs ADCO ADC7 The pins are accessed directly by writing or reading the port 2 data register P2 at location F2H in set 1 bank 1 2 0 2 7 can serve as inputs as outputs push pull or you can configure the following alternative functions In input mode ADC or external reference voltage input are also available Low byte pins 2 0 2 3 ADO AD3 High byte pins 2 4 2 7 AD4 AD7 pREF Port 2 Control Registers P2CONH P2CONL Port 2 has two 8 bit control registers 2 for 2 4 2 7 and P2CONL for P2 0 P2 3 A reset clears the P2CONH and P2CONL registers also control the alternative functions Port 2 Control Register High Byte 2 E8H Set 1 Bank 1 R W mm 4 AD4 P2 5 AD5 P2 6 AD6 P2 7 AD7 NBLDREF P2CONH bit pair pin configuration settings Input mode Input mode pull up Output mode push pull Alternative function AD4 AD7 BLD external input enable Figure 9 9 Port 2 High Byte Control Register 2 ELECTRONICS 9 9 5 S3C828B F828B C8289 F8289 C8285 F8285 Port 2 Control Register Low Byte P2CONL E9H Set 1 Bank 1 R W P2 3 AD3 P2CONL bit pair pin configuration settings Input mode Output mode pull up Output mode push pull Alternative function ADO AD3 Figure 9 10 Port 2 Low Byte Control
47. AER ERO 6 26 CCF Complement Garry Flag u 5 enum ie tede 6 27 CLR Clear it aee E ende 6 28 COM 59 7 9 hers deo ile ei ass 6 29 CP COmpare ted redeo erepto id de dd eic etd eed 6 30 CPIJE Compare Increment and Jump on Equal seen 6 31 CPIJNE Compare Increment and Jump on Non Equal eee 6 32 DA Decimal Adjust 3 ih dae S etre ctas diego ite 6 33 DEC oi idee nt Batis debe gei irs nte eS EE ete su tes 6 35 DECW Decrement Word d o Re er Rd ete ey Pe ae tup 6 36 DI Disable Interr pts ssi req ecd ege 6 37 DIV Divide Unsignedg nete Avene ates 6 38 DJNZ Decrement and Jump if Non Zero eese 6 39 EI Enable Interrupts cs 5 tn tt De DD Fea d c d nde 6 40 ENTER Enter rinn 6 41 EXIT E E E E E hne patate ib nme 6 42 IDLE ldle COperatior 2 x coit citet di vis Be dp 6 43 INC Increment 6 44 INCW IncrementWOFd o uu eee eee ote e epe eyes 6 45 Interr pt iRefUrfi a ete eee ei oad tee deer etate 6 46 JP Jumps i oid Rad d 6 47 JR Jump HhelatiVe tanti etd citt i mda 6 48 LD 6 49 LDB Load
48. Address Data Address Data 0043 IP Address Data Address Data 43 Address 44 Address L 45 Address H Address H 01 PC 0120 43 44 Address L 10 45 Address PC 0130 120 130 Routine Memory Memory 6 60 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET NOP Operation NOP Operation Flags Format Example No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex ope 1 4 FF When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 61 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 OR Logical OR OR Operation Flags Format Examples 6 62 dst src dst lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Setif the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected B
49. Bank 1 R W 7 6 5 4 3 2 0 198 PND7 PND6 PND5 PND4 PND3 PND2 PND1 PNDO POPND bit configuration settings Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending Figure 9 5 Port 0 Interrupt Pending Register POPND 9 6 ELECTRONICS 53 828 828 8289 8289 8285 8285 PORTS 1 Port 1 is an 7 bit I O port with individually configurable pins Port 1 pins are accessed directly by writing or reading the port 1 data register P1 at location F1H in set 1 bank 1 1 0 1 6 can serve inputs as outputs push pull or open drain or you can configure the following alternative functions Low byte pins P1 0 P1 3 TTOUT T1PWM BUZ High byte pins P1 4 P1 6 SO SCK SI Port 1 Control Register P1CONH P1CONL Port 1 has two 8 bit control registers P1CONH for 1 4 1 6 and P1CONL for 1 0 1 3 A reset clears the P1CONH and P1CONL registers to OOH configuring all pins to input mode You use control registers settings to select input or output mode push pull or open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module Port 1 Pull up Resistor Enable Register P1PUR Using the port 1 pull up resistor enable
50. Bit 6 51 S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER xxi List of Instruction Descriptions Continued Instruction Full Register Name Page Mnemonic Number LDC LDE Load d Memory D eg eee eee vache reece ete 6 52 LDCD LDED Load Memory 8 0 6 54 LDCI LDEI Load Memory and Incremernt u eene nne 6 55 LDCPD LDEPD Load Memory with 6 56 LDCPI LDEPI Load Memory with 6 57 LDW Noc Roo tae eed stalin tia a al one 6 58 MULT Multiply nsigried u rh S ai ale onde 6 59 Next TEE 6 60 u n l e ect eie ds Ug Cte D 6 61 OR Logical OR DR 6 62 POP Pop irom Stack ine ao etate cain iden e 6 63 POPUD Pop User Stack 6 64 POPUI Pop User Stack Incrementing essen 6 65 PUSH Push to Stack tae ded RR eee der ient rede dicet ter sienten 6 66 PUSHUD Push User Stack 6 67 PUSHUI Push User Stack Incrementing 6 68 RCF Reset Garry Flag ette eeu d eoe en ees 6 69 RET s 6 70 RL Rotate Left Eee d dI THEE DE
51. Comparator BLDour VBAT VBLDREF BANDGAP BLD Enable Disable SS P2CONH 7 6 NOTES 1 The reset value of BLDCON is 2 VREF is about 1V Figure 18 3 Battery Level Detector Circuit and Block Diagram Table 18 1 BLDCON Value and Detection Level BLDCON 2 0 0 0 0 2 2V 1 O 1 24V 0 1 1 2 8V Other values Not available ELECTRONICS 18 3 BATTERY LEVEL DETECTOR S3C828B F828B C8289 F8289 C8285 F8285 NOTES 18 4 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMEORY INTERFACE OVERVIEW The S3F828B F8289 F8285 has an on chip flash memory internally instead of masked ROM The flash memory is accessed by LDC instruction and the type of sector erase and a byte programmable flash a user can program the data in a flash memory area any time you want The S3F828B s embedded 64K byte memory has two operating features and The S3F8289 F8285 s embedded 32 16K byte memory respectively has one operating feature as below Tool Program Mode S3F828B F8289 F8285 User Program Mode S3F828B Only ELECTRONICS 19 1 EMBEDDED FLASH MEMORY INTERFACE S3C828B F828B C8289 F8289 C8285 F8285 TOOL PROGRAM MODE This mode is for the erase and programming full area of flash memory by external programming tools The 6 pins of S3F828B F8289 F8285 are connected to a programming tool and programmed by Serial OTP MTP Tools SPW2 plus s
52. EN Bank 0 is selected Bank 1 is selected ELECTRONICS 4 CONTROL REGISTERS S3C828B F828B C8289 F8289 C8285 F8285 FMCON Flash Memory Control Register D2H Set 1 Bank1 RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R R W Addressing Mode Register addressing mode only 7 4 Flash Memory Mode Selection Bits 0 1 0 1 Programming mode 1 0 1 0 Sector erase mode ro fs oumae 3 Sector Erase Status Bit Read only 0 Success sector erase 1 Fail sector erase 2 41 Not used for the S3C828B C8289 C8285 0 Flash Operation Start Bit EN Operation stop bit Operation start bit NOTE The FMCON 0 will be cleared automatically just after the corresponding operation completed 4 10 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER FMSECH Flash Memory Sector Address Register High Byte DOH Set 1 Bank1 Bit Identifier 6 s 4 3 2 1 9 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address Bits High Byte The 15th gth to select a sector of Flash ROM NOTE The high byte flash memory sector address pointer value is higher eight bits of the 16 bit pointer address FMSECL Flash Memory Sector Address Register Low Byte D1H Set 1 Bank1 Bit Identifier 7 6 5 4 3 2 A 9 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W
53. Figure 1 2 S3C828B F828B C8289 F8289 C8285 F8285 Pin Assignments 80 QFP 1420C ELECTRONICS 1 5 PRODUCT OVERVIEW SEG31 P5 5 SEG32 P5 6 SEG33 P5 7 SEG34 P3 0 TBPWM SEG35 P3 1 TAOUT TAPWM SEG36 P3 2 TACLK SEG37 P3 3 TACAP P3 4 TxD P3 5 RxD VDD Vss XOUT XIN TEST XTIN XTOUT nRESET VREG 0 P0 1 INT1 S3C828B F828B C8289 F8289 C8285 F8285 ELELTLELTLTLTI TT TL DL EL T 80 SEG30 P5 4 79 SEG29 P5 3 78 1 SEG28 P5 2 SEG27 P5 1 76 SEG26 P5 0 75 SEG25 P4 7 74 1 SEG24 P4 6 73 SEG23 P4 5 72 SEG22 P4 4 71 1 SEG21 P4 3 70 1 SEG20 P4 2 69 1 SEG19 P4 1 68 SEG18 P4 0 67 SEG17 P6 7 66 3 SEG16 P6 6 65 3 SEG15 P6 5 64 SEG14 P6 4 63 3 SEG13 P6 3 62 SEG12 P6 2 61 3 SEG11 P6 1 53 828 828 53 8289 8289 S3C8285 F8285 Q Q N 80 1212 NT2 NT3 NT4 NT5 NT6 NT7 P1 3 BUZ P1 4 SO P1 5 SCK P2 0 ADO P2 1 AD1 P2 2 AD2 P2 3 AD3 P2 4 ADA P2 5 AD5 P2 6 AD6 P0 2 P0 3 P0 4 P0 5 P0 6 P0 7 P1 0 T1CAP P1 1 T1CLK P1 2 T10UT TTPWM SEG10 P6 0 SEG9 P7 3 SEG8 P7 2 SEG7 P7 1 SEG6 P7 0 COM7 SEG5 P8 7 COMG SEGA P8 6 COM5 SEG3 P8 5 COM4 SEG2 P8 4 COM3 SEG1 P8 3 COM2 SEGO P8 2 COM1 P8 1 COMO P8 0 VLC3 VLC2 VLC1 VLCO AVsS AVREF P2 7 AD7 VBLDREF NOTE The sequence of pins in TQFP package is disagreement with that in QFP package Fig
54. Format Examples 6 28 The destination location is cleared to 0 No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 BO R B1 IR Given Register 4FH register 01H 02H and register 02H OOH gt Register 00H 00H CLR 01H gt Register 01H 02H register 02H OOH In Register R addressing mode the statement CLR clears the destination register OOH value to OOH In the second example the statement CLR 01H uses Indirect Register addressing mode to clear the 02H register value to 00H ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET COM Complement COM dst Operation dst lt NOT dst The contents of the destination location are complemented one s complement all 1s are changed to Os and vice versa Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 60 R 61 IR Examples Given R1 07H and register 07H COM RI gt R1 OF8H QR gt R1 0O07H register 27H OEH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B
55. Level Detector fBLD BLDCON 4 BLD Out BLDCON 5 E BLDCON 3 VBLDREF BLD Run Battery Level Setting 2 7 6 ExtRef Input Enable BLDCON 2 0 Set the Level Figure 18 1 Block Diagram for Battery Level Detect ELECTRONICS 18 1 BATTERY LEVEL DETECTOR S3C828B F828B C8289 F8289 C8285 F8285 BATTERY LEVEL DETECTOR CONTROL REGISTER BLDCON The bit of BLDCON controls to run or disable the operation of Battery level detect Basically this Vp p is set as 2 2 V by system reset and it can be changed in 3 kinds voltages by selecting Battery Level Detect Control register BLDCON When you write bit data value to BLDCON an established resistor string is selected and the Vg is fixed in accordance with this resistor Figure 18 2 shows specific Vg p of 3 levels Battery Level Detector Control Register BLDCON D2H Set 1 Bank 0 R W Detection voltage selection bits 000 VBLD 2 2V 101 VBLD 2 4V 011 VBLD 2 8V VIN source bit 0 Internal source 1 External source BLD Enable Disable bit 0 Disable BLD BLD Output bit T Enable BLD 0 VIN gt VREF When BLD is enable 1 VIN lt VREF When BLD is enable Figure 18 2 Battery Level Detector Control Register BLDCON 18 2 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 BATTERY LEVEL DETECTOR Resistor String Battery Level Detect Control D2H Set 1 Bank 0 R W
56. O ADCEN Data ADCEN ADC Select To ADC BLDEN BLD Select To BLD Figure 1 10 Pin Circuit Type F 2 P2 7 VLCO 4E VLC1 2 T COM SEG Output Disable L VLC2 3 Out Figure 1 11 Pin Circuit Type H 4 ELECTRONICS 1 11 PRODUCT OVERVIEW 53 828 828 8289 8289 8285 8285 Pull up Resistor 4 Resistor Open Drain Enable Data Output Disable1 SEG Circuit Output Type H 4 Disable2 Figure 1 12 Pin Circuit Type H 8 P4 P5 Pull up Resistor lt Resistor Enable Data Output Disable1 Circuit Output Type H 4 Disable2 Figure 1 13 Pin Circuit Type H 9 P3 0 P3 3 P6 P7 P8 1 12 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C828B C8289 C8285 microcontroller has two types of address space Internal program memory ROM Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3C828B has an internal 64 Kbyte mask programmable ROM S3C8289 has an internal 32 Kbyte mask programmable ROM The S3C8285 has an internal 16 Kbyte mask programmable ROM The 256 byte physical register space is expanded into an addressable area of 320 bytes using addressing modes A 38 byte LCD display register file is implemented ELECTRONICS 2 1 ADDR
57. P3 1 nable SEG35 output at P3 Output mode push pull Alternative function RxD TxD 1 P3 0 TBPWM SEG control bit 0 Enable TBPWM output at P3 0 1 Enable SEG34 output at P3 0 NOTE TAOUT TAPWM SEG35 outputs depend on P3CONL 3 P3CONL 2 The TBPWM or SEG34 outputs depend on P3CONL 1 P3CONL 0 Figure 9 11 Port High Byte Control Register P3CONH ELECTRONICS 9 11 PORTS S3C828B F828B C8289 F8289 C8285 F8285 Port Control Register Low Byte P3CONL EBH Set 1 Bank 1 R W FT P3 0 TBPWM NN 1 TAOUT SEG34 P3 2 TACLK P3 3 TACAP SEG36 SEG35 SEG37 P3CONL bit pair pin configuration settings 00 Input mode TACAP 01 Input mode pull up 10 Output mode push pull 11 Alternative function TAOUT TAPWM TBPWM SEG37 SEG34 Figure 9 12 Port 3 Low Byte Control Register PSCONL 9 12 ELECTRONICS 53 828 828 8289 8289 8285 8285 PORTS PORT 4 Port 4 is an 8 bit I O port with individually configurable pins Port 4 pins are accessed directly by writing or reading the port 4 data register P4 at location in set 1 bank 1 P4 0 P4 7 can serve as inputs with or without pull ups as output open drain or push pull And they can serve as segment pins for LCD also Port 4 Control Registers PACONL Port 4 has two 8 bit control registers PACONH for P4 4 P4 7 PACONL for
58. Programming Enable Register FMUSR FFH Set 1 Bank 1 R W Flash memory user programming enable bits 10100101 Enable user programming mode Other values Disable user programming mode Figure 19 2 Flash Memory User Programming Enable Register FMUSR 19 4 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 EMBEDDED FLASH MEMORY INTERFACE FLASH MEMORY SECTOR ADDRESS REGISTERS There are two sector address registers for addressing a sector to be erased The FMSECL Flash Memory Sector Address Register Low Byte indicates the low byte of sector address and FMSECH Flash Memory Sector Address Register High Byte indicates the high byte of sector address The FMSECH is needed for S3F828B because it has 512 sectors respectively One sector consist of 128 bytes Each sector s address starts XXOOH or XX80H that is a base address of sector is XXOOH or XX80H So FMSECL register 6 0 don t mean whether the value is 1 or 0 We recommend that the simplest way is to load sector base address into FMSECH and FMSECL register When programming the flash memory you should write data after loading sector base address located in the target address to write data into FMSECH and FMSECL register If the next operation is also to write data you should check whether next address is located in the same sector or not In case of other sectors you must load sector address to and FMSECL register according to the sector Flash Memory Sector Add
59. Pull up enable 2 P4 2 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 1 P4 1 Pull up Resistor Enable Bit o Pull up disable Pull up enable 0 P4 0 Pull up Resistor Enable Bit EN Pull up disable Pull up enable NOTE A pull up resistor of port 4 is automatically disabled only when the corresponding pin is selected as push pull output or alternative function 4 34 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER P5CONH Port 5 Control Register High Byte F9H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P5 7 SEG33 0 Input mode 1 Output mode N channel open drain 1110 Output mode push pull Alternative function SEG33 5 4 P5 6 SEG32 Input mode Output mode N channel open drain Output mode push pull 1 Alternative function SEG32 3 2 P5 5 SEG31 0 0 Input mode 1 Output mode N channel open drain 0 1 0 Output mode push pull 1 Alternative function SEG31 0 0 Input mode 0 Output mode N channel open drain Output mode push pull Alternative function SEG30 ELECTRONICS 4 35 CONTROL REGISTERS S3C828B F828B C8289 F8289 C8285 F8285 P5CONL Port 5 Control Register Low Byte FAH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register address
60. R R W Addressing Mode Register addressing mode only 7 Flash Memory Sector Address Bit Low Byte The 7th bit to select a sector of Flash ROM 6 0 Not used for the S3C828B C8289 C8285 NOTE The low byte flash memory sector address pointer value is lower eight bits of the 16 bit pointer address ELECTRONICS 4 11 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 FMUSR Flash Memory User Programming Enable Register FFH Set 1 Bank1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory User Programming Enable Bits 1 0 1 0 0 1 0 1 Enable user programming mode Others Disable user programming mode 4 12 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER IMR Interrupt Mask Register DDH Set 1 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit External Interrupts 0 4 0 7 0 Disable mask 1 Enable unmask 6 Interrupt Level 6 IRQ6 Enable Bit External Interrupts 0 0 0 3 0 Disable mask 1 Enable unmask 5 Interrupt Level 5 IRQ5 Enable Bit UART Transmit UART Receive Watch Timer 0 Disable mask 1 Enable unmask 4 Interrupt Level 4 IRQ4 Enable Bit SIO 0 Disable mask 1 Enable unmask 3 Interrupt Level 3 IRQ3 Enable Bit Timer 1 Match Capture or Ove
61. R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET SWAP swap Nibbles SWAP Operation Flags Format Examples dst dst 0 3 dst 4 7 The contents of the lower four bits and upper four bits of the destination operand are swapped C Undefined Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R F1 IR Given Register register 02H and register 03H OA4H SWAP 00H gt Register 00H SWAP 02H gt Register 02H register 03H 4AH In the first example if general register contains the value 00111110B the statement SWAP swaps the lower and upper four bits nibbles in the OOH register leaving the value 11100011 ELECTRONICS 6 83 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 TCM Test Complement Under Mask TCM Operation Flags Format Examples 6 84 dst src dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The
62. Register P2CONL 9 10 ELECTRONICS 53 828 828 8289 8289 8285 8285 PORTS PORT 3 Port 3 is an 6 bit I O port with individually configurable pins Port 3 pins are accessed directly by writing or reading the port 3 data register P3 at location F3H in set 1 bank 1 P3 0 P3 5 can serve as inputs with or without pull ups as push pull outputs And the P3 0 P3 3 can serve as segment pins for LCD or you can configure the following alternative functions Low byte pins P3 0 P3 3 TBPWM TAPWM TACLK High byte pins P3 4 P3 6 TxD RxD Port 3 Control Registers PSCONH P3CONL Port 3 has two 8 bit control registers for P3 4 P3 5 and PSCONL for P3 0 P3 3 A reset clears the P3CONH and P3CONL registers to configuring all pins to input mode You use control registers settings to select input or output mode enable pull up resistors and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabled in the associated peripheral module Port Control high Register High Byte EAH Set 1 Bank 1 R W Not used P3 5 RxD P3 4 TxD P3 1 TAOUT TAWM SEG35 control bit P3CONH bit pair pin configuration settings 0 Enable TAOUT TAPWM output at P3 1 00 Input mode RxD Input mode pull up RxD Enable SE
63. S W IRQ4 810 interrupt S W EAH n UART data transmit S W IRQ5 UART data receive S W EEH Watch timer overflow S W m P0 0 External interrupt S W m V External interrupt S W IRQ6 F P0 2 External interrupt S W F6H P0 3 External interrupt S W m F8H P0 4 External interrupt S W F P0 5 External interrupt S W IRQ7 m FCH 0 6 External interrupt S W FEH P07 External interrupt S W NOTES 1 Within a given interrupt level the low vector address has high priority For example has higher priority than E2H within the level IRQ 0 the priorities within each level are set at the factory 2 External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting Figure 5 2 S3C828B C8289 C8285 Interrupt Structure 5 4 ELECTRONICS 53 828 828 8289 8289 8285 8285 INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S8C828B F828B C8289 F8289 C8285 F8285 interrupt structure are stored in the vector address area of the internal 64 Kbyte ROM OH FFFFH or 16 32 Kbyte see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not
64. SEG29 SEG26 Figure 9 17 Port 5 Low Byte Control Register PSCONL Port 5 Pull up Resistor Enable Register PSPUR Set 1 Bank 1 R W P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 P5PUR bit configuration settings 0 1 Pull up Disable Pull up Enable Figure 9 18 Port 5 Pull up Resistor Enable Register 5 9 16 ELECTRONICS 53 828 828 8289 8289 8285 8285 PORTS PORT 6 Port 6 is an 8 bit I O port with individually configurable pins Port 6 pins are accessed directly by writing or reading the port 5 data register P6 at location F6H set 1 bank 1 6 0 6 7 can serve as inputs with without pull ups as push pull outputs And they can serve as segment pins for LCD also Port 6 Control Registers P6CONL Port 6 has two 8 bit control registers PeCONH for P6 4 P6 7 and PeCONL for 6 0 6 3 A reset clears the P6CONH P6CONL registers to configuring all pins to input mode Port 6 Control Register High Byte PECONH FBH Set 1 Bank 1 R W P6 4 SEG14 P6 5 SEG15 P6 6 SEG16 P6 7 SEG17 P6CONH bit pair pin configuration settings 00 Input mode 01 Input mode pull up 10 Output mode push pull 11 Alternative function SEG17 SEG14 Figure 9 19 Port 6 High byte Control Register ELECTRONICS 9 17 PORTS S3C828B F828B C8289 F8289 C8285 F8285 Port 6 Control Register Low Byte PECONL FCH
65. SP OOFCH In the first example general register contains the value 01H The statement POP loads the contents of location OOFBH 55H into destination register OOH and then increments the stack pointer by one Register then contains the value 55H and the SP points to location OOFCH ELECTRONICS 6 63 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example 6 64 dst src dst lt src lt IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 92 R IR Given RegisterOOH 42H user stack pointer register register42H and register 02H 70H POPUD 02H 00H gt Register 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement POPUD 02H 00H loads the contents of register 42H into the destination register 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Exa
66. Sree tea 7 6 Chapter 8 RESET and Power Down System RESET ibm ahua chia aati ete 8 1 OVOtVIQW icu E nuts hae ie Sed ant anak a aa h uu s Rede iue oo De eed RE qp 8 1 Normal Mode RESET 8 1 Hardware RESET Values iet e Pel ee pene Fun e SER e eee va PC 8 2 Power Down MOod6 s 1 iiie tutte eei pite E 8 5 St p M d M 8 5 Ce Rr 8 6 Chapter 9 Ports OVEIVIQW m 9 1 Port Data Registers dm tetris eoe cie a coe ERU dee eet eee vec pee p ct Rue 9 2 OZ mte eee eee 9 3 TP PX Sees tele 9 7 Por C I 9 9 scs aaepe 9 11 POIL z a un s Sila ne S e ede C EIE Sasa en ee Ga des 9 13 iat gode ep ee diede Hee DRE A Iob eT foe 9 15 Pon c 9 17 IP age ena ad amsa er reece anite 9 19 POR e acetic dad dodi E d od eed Sham Gera Annee re end d eh edet 9 20 Chapter 10 Basic Timer
67. Start bit 0 8 data bits LSB first Programmable 9th data bit Stop bit 1 The 9th data bit to be transmitted can be assigned a value of 0 or 1 by writing the TB8 bit UARTCON 3 When receiving the 9th data bit that is received is written to the RB8 bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 clock frequency Mode 2 Transmit Procedure 1 Select mode 2 9 bit UART by setting UARTCON bits 6 and 7 to 10B Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 2 Write transmission data to the shift register UDATA F7H set 1 bank 0 to start the transmit operation Mode 2 Receive Procedure 1 Select mode 2 and set the receive enable bit RE the UARTCON register to 1 2 The receive operation starts when the signal at the RxD P3 5 pin goes to low level Jr i Jo AL Write to Shift Register UARTDATA Shift 1 TxD start Bit Do X D1 X D2 X D3 X D4 X D5 X D6 X D7 X TB8 Stop Bit TIP Transmit es N A H f H l H f H RxD Start Bit DO D1 2 D3 D4 D5 D6 D7 RB8 Sup I Bit Detect Sample Time 1 1 gt Shift 5 E RIP Figure 17 8 Timing Diagram for Serial Port Mode 2 Operation ELECTRONI
68. The contents of the source are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 C4 RR RR C5 RR IR dst src 4 8 C6 RR IML Examples Given R4 06H R5 1CH R6 O5H R7 0O02H register register 01H 02H register 02H and register 03H OFH LDW RR6 RR4 gt R6 O6H R7 1CH R4 06H R5 1CH LDW 00H 02H gt RegisterOOH register 01H OFH register 02H register 03H LDW RR2 R7 gt R2 OFH LDW 04H 01H gt Register register OFH LDW RR6 1234H gt R6 12H R7 34H LDW 02H 0FEDH gt Register 02H OFH register 03H OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H into the destination word OOH 01H This leaves the value 03H in general register 00H and the value OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats 6 58 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET MULT multiply Unsigned MULT Operation Flags Format Examples O6H dst src dst lt dst src The 8 bit destination operand even register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both o
69. Timer 0 interrupt IRQ2 vector E2H generation Timer 0 control register TOCON set 1 Bank 0 E3H read write FUNCTION DESCRIPTION Interval Timer Function The timer 0 module can generate an interrupt the timer 0 match interrupt TOINT TOINT belongs to interrupt level IRQ2 and is assigned the separate vector address E2H The TOINT pending condition is automatically cleared by hardware when it has been serviced Even though TOINT is disabled the application s service routine can detect a pending condition of TOINT by the software and execute it s sub routine When this case is used the TOINT pending bit must be cleared by the application subroutine by writing a 0 to the pending bit In interval timer mode a match signal is generated when the counter value is identical to the values written to the TO reference data registers TODATAH L The match signal generates a timer 0 match interrupt TOINT vector E2H and clears the counter If for example you write the value 0010H to TODATAH L and OFH to TOCON the counter will increment until it reaches 10H At this point the TO interrupt request is generated the counter value is reset and counting resumes ELECTRONICS 12 1 16 BIT 0 1 53 828 828 8289 8289 8285 8285 TIMER 0 CONTROL REGISTER You use the timer 0 control register TOCON to Enable the timer 0 operating interval timer Select the timer 0 inp
70. Watch Timer Control Register 13 2 13 2 Watch Timer Circuit 13 3 14 1 EGD F nctlon Diagram s s cett ete ed DR erbe bo a dol 14 1 14 2 LCD Circuit Diagram ooo edet ce detener detinet esee i e dete net 14 2 14 3 LCD Display Data RAM Organization 14 3 14 4 LCD Control Register LCON a a 14 4 14 5 LCD Voltage Dividing Resistor 14 5 14 6 Select No Select Signal in 1 2 Duty 1 2 Bias Display Mode 14 7 14 7 Select No Select Signal in 1 3 Duty 1 3 Bias Display Mode 14 7 14 8 LCD Signal Waveforms 1 3 Duty 1 3 000 1 14 8 14 9 LCD Signal Waveforms 1 4 Duty 1 3 14 9 14 10 LCD Signal Waveforms 1 8 Duty 1 4 14 10 15 1 A D Converter Control Register 15 2 15 2 A D Converter Data Register 15 3 15 3 A D Converter Functional Block 15 4 15 4 Recommended A D Converter Circuit for Highest Absolute Accuracy 15 5 16 1 Serial I O Module Control Registers 16 2 16 2 SIO Pre scaler Register 16 3 16 3 SIO Functional Block
71. bit After the watch timer starts and elapses a time the watch timer interrupt pending bit WTCON 0 is automatically set to 1 and interrupt requests commence in 3 91 ms 0 25 0 5 and 1 second intervals by setting Watch timer speed selection bits WTCON 3 2 The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to BUZ output pin for Buzzer By setting WTCON 3 and WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 3 91 ms High speed mode is useful for timing events for program debugging sequences The watch timer supplies the clock frequency for the LCD controller f Therefore if the watch timer is disabled the LCD controller does not operate Watch timer has the following functional components Real Time and Watch Time Measurement Using a Main Clock Source or Sub clock Clock Source Generation for LCD Controller I O pin for Buzzer Output Frequency Generator BUZ Timing Tests in High Speed Mode Watch timer overflow interrupt IRQ5 vector EEH generation Watch timer control register WTCON set 1 bank 0 read write ELECTRONICS 13 1 WATCH 3C822B F822B C8289 F8289 C8285 F8285 WATCH TIMER CONTROL REGISTER WTCON The watch timer control register WTCON is used to select the watch timer interrupt time and Buzzer signal to enable or disable the watch timer function It is located in set 1 b
72. example destination working register R1 contains the value 07H 00000111B and source register 01H the value 00000011B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the second example destination register 01H contains the value 03H 0000001 1B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H in register 01H ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET BTJ RF Bit Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b isa 0 then PC PC dst The specified bit within the source operand is tested If it is a 0 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst sre opc dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains the v
73. instructions are used to control system stack operations The 53 828 8289 8285 architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 18 High Address PCL PCH Flags Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 18 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SPO is stored in the SPL register After a reset t
74. is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 6 30 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET Compare Increment Jump Equal CPIJE Operation Flags Format Example dst src RA Ifdst src 0 lt PC RA Ir lt e Ir 1 The source operand is compared to subtracted from the destination operand If the result is the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src T 3 d Cc r NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 register 03H 02H R1 R2 SKIP R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comp
75. loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples dst src mr rm 1 dst src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F3 Ir r Given RO 7FH R6 21H andR7 LDCPI RR6 RO RR6 lt RR6 1 7FH contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH LDEPI RR6 RO RR6 lt RR6 1 contents of RO is loaded into external data memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH ELECTRONICS 6 57 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 LDW Load Word LDW dst src Operation dst lt src The contents of the source a word are loaded into the destination
76. maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is commonly used for stack operations ELECTRONICS 2 11 ADDRESS SPACES 53 828 828 8289 8289 8285 8285 PRIME REGISTER SPACE The lower 192 bytes OOH BFH of the S8C828B C8289 C 8285 s ten or four or two 256 byte register pages is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 1 2 3 4 5 6 7 8 9 or 15 you must set the register page pointer PP to the appropriate source and destination values sg s T Ru p V aa o KX SS CPU and system control SS 5 General purpose Page 15 LCD Data Peripheral and I O Register Area LCD data register Figure 2 7 Set 1 Set 2 Prime Area Register and LCD Data Register Map 2 12 ELECTRONICS 53 828 828 8289 8289 8285 8285 ADDRESS SPACES WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can b
77. mode 1 if UARTCON 5 1 then the receive interrut will not be activated if a valid stop bit was not received In mode 0 the UARTCON 5 bit should be 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit 3 Theinterrupt pending bits of Rx and Tx are in the INTPND register Figure 17 1 UART Control Register UARTCON 17 2 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 UART UART INTERRUPT PENDING BITS The UART interrupt pending bits INTPND 5 4 are located in set 1 bank 0 at address F9H it contains the UART data transmit interrupt pending bit INTPND 4 and the receive interrupt pending bit INTPND 5 In mode 0 the receive interrupt pending bit INTPND 5 is set to 1 when the 8th receive data bit has been shifted In mode 1 2 and 3 the INTPND 5 bit is set to 1 at the halfway point of the stop bit s shift time When the CPU has acknowledged the receive interrupt pending condition the INTPND 5 bit must then be cleared by software in the interrupt service routine In mode 0 the transmit interrupt pending bit INTPND 4 is set to 1 when the 8th transmit data bit has been shifted In mode 1 2 or 3 the INTPND 4 bit is set at the start of the stop bit When the CPU has acknowledged the transmit interrupt pending condition the INTPND 4 bit must then be cleared by software in the interrupt service routine Interrupt Pending Register INTPND F
78. of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space n Even address Figure 2 11 16 Bit Register Pair 2 16 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 FFH EOH DOH COH BFH Special Purpose Registers e H Bank 1 Bank 0 Control Registers System Registers CFH Register Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and RP1 to locations C8H CFH that is to the common working register area NOTE In the S3C828B C8289 C8285 microcontroller pages 0 9 15 are implemented Pages 0 9 15 contain all of the addressable registers in the internal register file Register Addressing Only Can be Pointed by Register Pointer ADDRESS SPACES General Purpose Register Page 0 Page 0 4 4 All Indirect Register All Addressing Indexed Addressing Modes Addressing Modes Modes Can be Pointed to By register Pointer Figure 2 12 Register File Add
79. one or both of the register pointers RPO and Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src src 2 4 31 IM The statement SRP 40H sets register pointer 0 RPO at location OD6H to 40H and register pointer 1 RP1 at location OD7H to 48H The statement SRPO 50H sets RPO to 50H and the statement SRP1 68H sets RP1 to 68H ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 4 7 statement STOP halts all microcontroller operations ELECTRONICS 6 81 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 SUB subtract SUB Operation Flags Format Examples 6 82
80. register addressing mode It has the following control functions LCD duty and bias selection LCD clock selection LCD display control Internal External LCD dividing resistors selection The LCON register is used to turn the LCD display on off to select duty and bias to select LCD clock and control the flow of the current to the dividing in the LCD circuit A reset clears the LCON registers to OOH configuring turns off the LCD display select 1 8 duty and 1 4 bias select 128Hz for LCD clock and Enable internal LCD dividing resistors The LCD clock signal determines the frequency of COM signal scanning of each segment output This is also referred as the LCD frame frequency Since the LCD clock is generated by watch timer clock fw The watch timer should be enabled when the LCD display is turned on LCD Control Register LCON DOH Set 1 Bank 0 R W Internal LCD dividing register enable bit LCD display control bit 0 Enable internal LCD dividing resistors 0 All LCD signals are low 1 Disable internal LCD dividing resistors Turn off the P Tr 1 Turn display on Turn on the P Tr LCD clock selection bits Not used 00 fw 2 128 Hz 01 fw 27 256 Hz LCD duty and bias selection bits 10 fw 2 512 Hz 000 1 8 duty 1 4 bias 11 fw 25 1024 Hz 001 1 4 duty 1 3 bias 010 1 3 duty 1 3 bias 011 1 3 duty 1 2 bias 1xx 1 2 duty 1 2 bias NOTES 1 x means don t ca
81. selected by software software assignable pull ups P8 0 P8 7 can alternately be used as outputs for LCD COM SEG ELECTRONICS 9 1 5 S3C828B F828B C8289 F8289 C8285 F8285 PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all four S3C828B F828B C8289 F8289 C8285 F8285 port data registers Data registers for ports 0 1 2 3 4 5 6 7 and 8 have the general format shown in Figure 9 1 Table 9 2 Port Data Register Summary Register Name mnemonic Decimal Hex Location Rw Set 1 Bank 1 R W x F6H R W Port 5 data register Port 6 data register Set 1 Bank 1 Set 1 Bank 1 FeH Set 1 Banki Port 7 data register Port 8 data register Port 3 data register P3 243 P6 246 9 2 ELECTRONICS 53 828 828 8289 8289 8285 8285 PORTS PORT 0 Port 0 is an 8 bit I O Port that you can use two ways General purpose I O External interrupt inputs for INTO INT7 Port 0 is accessed directly by writing or reading the port 0 data register PO at location FOH in set 1 bank 1 Port 0 Control Register POCONH POCONL Port 0 has two 8 bit control registers POCONH for 0 4 0 7 andPOCONL for P0 0 P0 3 A reset clears the POCONH and POCONL registers to 00H configuring all pins to input mode In input mode three different selections are available Schmitt trigger input with interrupt generation on falling signal
82. service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 Read only Interrupt level request pending bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ 5 14 ELECTRONICS 53 828 828 8289 8289 8285 8285 INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S8C828B C8289 C8285 interrupt structure the timer A overflow interrupt IRQO belongs to this category of interrupts in which pending condition is cleared au
83. single 32 byte common area In case of S3C828B F828B the total number of addressable 8 bit registers is 2 695 Of these 2 695 registers 13 bytes are for CPU and system control registers 38 bytes are for LCD data registers 68 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 2 560 registers are for general purpose use page 0 page 9 in case of S3C8289 F82889 page 0 page and S3C8285 F8285 page0 paget1 You can always address set 1 register locations regardless of which of the ten register pages is currently selected Set 1 locations however can only be addressed using register addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C828B F828B Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte 2 576 common working register area ten 192 byte prime register area and ten 64 byte set 2 area LCD data registers CPU and system control registers Mapped clock peripheral control and data registers Total Addressable Bytes 2 4 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 ADDRESS SPACES Table
84. target slave Note that in this case an address byte differs from a data byte In an address byte the 9th bit is 1 and in a data byte it is O The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes The MCE bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless a valid stop bit is received ELECTRONICS 17 11 UART 53 828 828 8289 8289 8285 8285 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications Set all S8C828B F828B C8289 F8289 C8285 F8285 devices masters and slaves to UART mode 2 or Write the MCE bit of all the slave devices to 1 The master device s transmission protocol is First byte the address identifying the target slave device 9th bit 1 Next bytes data 9th bit 4 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data
85. undefined Table 6 3 Instruction Set Symbols Description Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Description Condition code Working register only Bit b of working register Bit 0 LSB of working register Working register pair Register or working register Bit b of register or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed short offset addressing mode Indexed long offset addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Immediate long addressing mode ELECTRONICS Actual Operand Range See list of condition codes in Table 6 6 Rn 0 15 Rn b n 0 15 b 0 7 Rn 0 15 RRp p 0 2 4 14 reg or Rn reg 0 255 n 0 15 reg b reg 0 255 b 0 7 reg or RRp reg 0 254 even number only where 0 2 14 addr addr 0 254 even num
86. zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir src dst 3 6 74 R R 75 R IR dst src 3 6 76 R IM Examples Given RO OC7H R1 02H R2 18H register OOH 2BH register 1H 02H and registerO2H 23H TM RO R1 gt RO OC7H R1 02H Z 0 TM RO R1 gt RO OC7H R1 0O2H register02H 23H Z 0 TM 00H01H gt Register OOH 2 register 01H 02H Z 0 00H 01H gt Register OOH 2BH registerO1H 02H register 02H 23H Z 00H 54H gt Register 00H 2BH Z 1 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TM RO R1 tests bit one in the destination register for 0 value Because the mask value does not match the test bit the 27 flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 WFI tor Int
87. 0 3V T Crystal oscillator C1 C2 22pF Ippa 9 Run mode 3 3V 0 3V 28 0 uA 25 C OSCCON 7 1 32kHz crystal oscillator lpp4 9 mode Vpp 3 3V 0 3V j 4 0 25 C OSCCON 7 1 32kHz crystal oscillator Stop mode 2 0 25 C to 10 85 C 1 Supply current does not include current drawn through internal pull up resistors LCD voltage dividing resistors the LVR block and external output current loads 2 lpp and include a power consumption of subsystem oscillator 3 lpps and are the current when the main system clock oscillation stops and the subsystem clock is used OSCCON 7 1 4 pps is the current when the main and subsystem clock oscillation stops 5 Every values in this table is measured when bits 4 3 of the system clock control register CLKCON 4 3 is set to 11B NOTES ELECTRONICS 22 5 53 828 8289 8285 FLASH MCU S3C828B F828B C8289 F8289 C8285 F8285 Instruction Clock fx Main Sub oscillation frequency 2 8 MHz 2 5 MHz 1 05 MHz 6 25 kHz main 8 2kHz sub 400 kHz main 32 8 kHz sub 27 Supply Voltage V Minimum instruction clock 1 4 1 oscillator frequency n 1 2 8 16 Figure 22 3 Operating Voltage Range 22 6 ELECTRONICS 53 828 828 8289 8289 8285 8285 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development sup
88. 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 CALL Procedure CALL Operation Flags Format Examples 6 26 dst SP lt SP 1 SP lt PCL SP lt SP 1 SP lt PCH PC lt dst The current contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 3 14 F6 DA dst 2 12 F4 IRR dst 2 14 D4 IA Given RO 35H R1 21H PC 1A47H andSP 0002H CALL 3521H gt SP 0000 Memory locations 0000H 0001H where 4AH is the address that follows the instruction CALL RRO gt SP 0000H 0000H 1AH 0001H 49H CALL 40H gt SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location 0000H The PC is then loaded with the value
89. 1 MHz 3 0 Input high voltage All input pins except Viyo Ving 0 7Vpp Ports0 1 nRESET 0 8Vpp Xin and XT XT out Vpp 0 1 Input low voltage All input pins except Vi Vir Ports0 1 nRESET Xin and XTi XTour 20 2 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 ELECTRICAL DATA Table 20 2 D C Electrical Characteristics Continued 25 C to 85 C Vpp 2 0 V to 3 6 V Symbol Conditions i Unit Output high voltage Voy Vpp 27V to 3 6V V lon 1 mA All output pins Output low voltage Vor Vpp 2 7V to 3 6V lg 15 mA 1 2 All output ports except Vo 1 Input high leakage Vin Vpp uA current All input pins except Vin Vpp Xout gt XTn XTour Input low leakage litt Vin OV current All input pins except for nRESET iz l2 0 Xin XTn XTour leakage current All output pins Output low leakage lot Vour 0V 3 current All output pins LCD voltage Rico 25 25 50 80 kQ dividing resistor Oscillator feed Rosci 3 V Ta 25 600 1600 3000 back resistors Xin Von Xour OV Rosc2 Vpp 3 V 25 Ports 0 8 T4 25 C 25 nRESET Pull up resistor 0 3 L2 ELECTRONICS 20 3 ELECTRICAL DATA S3C828B F828B C8289 F8289 C8285 F8285 Table 20 2 D C Electrical Characteristics Continued TA 25 to 85 C Vpp
90. 10 ELECTRONICS 4 39 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 P7CON Port 7 Control Register FDH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P7 3 SEG9 Input mode Input mode pull up Output mode push pull Alternative function SEG9 5 4 3 2 P7 1 SEG7 0 0 Input mode Input mode pull up 0 Output mode push pull EN Alternative function SEG7 1 0 P7 0 SEG6 O 0 Input mode 1 Input mode pull up Output mode push pull EHEN Alternative function SEG6 4 40 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER P8CON Port 8 Control Register FEH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P8 7 P8 4 COM7 COM4 SEG5 SEG2 0 Input mode 1 Input mode pull up KEE Output mode push pull Alternative function COM7 COM4 SEG5 SEG2 5 4 P8 3 COM3 SEG1 Input mode Input mode pull up Output mode push pull 1 Alternative function COM3 SEG1 3 2 P8 2 COM2 SEGO 0 0 Input mode 1 Input mode pull up 0 1 0 Output mode push pull 1 Alternative function COM2 SEGO 0 0 Input mode 0 Input mode pull up Output mode push pull Alternative functi
91. 2 S3C828B C8289 C8285 Interrupt Structure seen 5 3 Interrupt Vector Addresses uie tenir te ete ee Pe PERI ER ODIT 5 5 Enable Disable Interrupt Instructions El DI 5 7 System Level Interrupt Control 5 7 Interrupt Processing Control 5 8 Peripheral Interrupt Control 2 5 9 2 ie pta Ree eg 5 10 Interrupt Mask Register IMR 5 11 Interrupt PriorityRegister IPIR 5 12 Interrupt Request Register IRQ us n S aaa 5 14 Interrupt Pending Function 5 15 Interrupt Source Polling 5 16 Interrupt Service Routinas o rcgem certe e aeaa 5 16 Generating Interrupt Vector 0 nennen uuu 5 17 Nesting Of Vectored 5 17 e e ER ee eae REP eta 5 17 Fast Int rrupt PrOGessilig iet ic teneri o Re E er da E Lc Pet e po quo se 5 17 Ch
92. 24 bytes 1 Normal vector address 0100H 11 2048 bytes ISP reset vector address selection bits ISP protection enable disable bit 00 200H ISP area size 256 byte 0 Enable not erasable by LDC 01 A area size 512 byte 1 Disable Erasable by LDC 10 500H ISP area size 1024 byte 11 900H ISP area size 2048 byte ROM Address 003FH These bits should be LVR enable disable bit always logic 110b Criteria Voltage 2 2V 0 Disable LVR 1 Enable LVR ROM Address 003CH ROM Address 003DH 7 6 5 4 2 4 0 Not used NOTE 1 After selecting ISP reset vector address in selecting ISP protection size don t select upper than ISP area size 2 When any values are written in the Smart Option area 003CH 003FH by LDC instruction the data of the area may be changed but the Smart Option is not affected The data for Smart Option should be written in the Smart Option area 003CH 003FH by OTP MTP tools SPW2 plus single programmer or GW PRO2 gang programmer Figure 2 2 Smart Option ELECTRONICS 2 3 ADDRESS SPACES 53 828 828 8289 8289 8285 8285 REGISTER ARCHITECTURE In the S3C828B F828B C8289 F8289 C8285 F8285 implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a
93. 285 80 QFP 1420C 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 L3 SEG12 P6 2 L3 SEG11 P6 1 L3 SEG10 P6 0 L3 SEG9 P7 3 L3 SEG8 P7 2 L3 SEG7 P7 1 L3 SEG6 P7 0 L3 COM7 SEG5 P8 7 L3 COM6 SEG4 P8 6 L3 COM5 SEG3 P8 5 L3 COM4 SEG2 P8 4 COM3 SEG1 P8 3 L3 2 5 8 2 1 COM1 P8 1 LI COMO P8 0 3 VLC3 L3 Vic2 L3 L3 Vico L3 AVss 1 AVREF 1 P2 7 AD7 NBLDREF L3 P2 6 AD6 m P2 5 AD5 PO 4 INT4 PO 5 INT5 PO 6 INT6 PO 7 INT7 P1 0 T1CAP P1 1 T1CLK P1 3 BUZ P1 4 SO P1 5 SCK 1 6 5 P2 0 ADO P2 1 AD1 P2 2 AD2 P2 3 AD3 P2 4 AD4 P1 2 T1OUT T1PWM Figure 22 1 S3F828B F8289 F8285 Pin Assignments 80 QFP 1420C 22 2 ELECTRONICS 53 828 828 8289 8289 8285 8285 SEG31 P5 5 SEG32 P5 6 SEG33 P5 7 SEG34 P3 0 TBPWM SEG35 P3 1 TAOUT TAPWM SEG36 P3 2 TACLK SEG37 P3 3 TACAP C SDAT P3 4 TxD SCLK P3 5 RxD Vpp Vpp Vss Vss Xour XIN VPP TEST XTour nRESET nRESET VREG PO O INTO PO 1 INT1 Figure 22 2 S3F828B F8289 F8285 Pin Assignments 80 1212 ELECTRONICS GQ N NT2 21 22 2 3 80 3 SEG30 P5 4 79 E3 SEG29 P5 3 78 SEG28 P5 2 77 E3 SEG27 P5 1 76 SEG26 P5 0 75 1 5 25 4 7 74 3 5 24 4 6 73 SEG23 P4 5 72 3 5 22 4 4 71 SEG21 P4 3 70 5 20 4 2 69 3 SEG19 P4 1 68 SEG18 P4 0
94. 289 C8285 F8285 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter S3C828B F828B C8289 F8289 C8285 F8285 electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute maximum ratings Input output capacitance D C electrical characteristics electrical characteristics Oscillation characteristics Oscillation stabilization time Data retention supply voltage in stop mode LVR timing characteristics BLD electrical characteristics Serial I O timing characteristics A D converter electrical characteristics UART timing characteristics Internal Flash ROM electrical characteristics Operating voltage range ELECTRONICS 20 1 ELECTRICAL DATA S3C828B F828B C8289 F8289 C8285 F8285 Table 20 1 Absolute Maximum Ratings 25 C Parameter Symbol Rating Unit Supply voltage Vpp 0 3 to 4 6 V Input voltage Vi 0 3 to Vpp 0 3 Output voltage Vo lt 0 3 to Vpp 0 3 Output current high 15 mA Output current low 30 Operating temperature TA 25 to 85 C Storage temperature 65 to 150 Table 20 2 D C Electrical Characteristics T4 25 C to 85 C Vpp 2 0 V to 3 6 V Parameter Symbol Conditions Min Typ Max Unit Operating voltage fx 0 4 4 2 MHz 32 8kHz 2 0 fx 0 4 10MHz 2 7 fx 0 4 11
95. 3 CPU Clock System Clock Selection Bits note fxx 16 2 0 Not used for the S3C828B C8289 C8285 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 4 8 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER FLAGS System Flags Register D5H Set 1 RESET Value x x x x x x 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag C 0 Operation does not generate a carry or borrow condition 1 Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Z EN Operation result is a non zero value Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 Operation generates a negative number MSB 1 4 Overflow Flag V 0 Operation result is lt 127 gt 128 Operation result is gt 127 or lt 128 3 Decimal Adjust Flag D EN Add operation completed Subtraction operation completed 2 Half Carry Flag H 0 No carry out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carry out of bit or subtraction generated borrow into bit 1 Fast Interrupt Status Flag FIS EN Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag
96. 4 0 4 3 A reset clears the P4CONH and P4CONL registers to OOH configuring all pins to input mode Port 4 Pull up Resistor Enable Register P4PUR Using the Port 4 pull up resistor enable register PAPUR set 1 bank 1 you can configure pull up resistors to individual port 4 pins Port 4 Control Register High Byte P4CONH ECH Set 1 Bank 1 R W 17 6 5 4 3 2 4 0 16 P4 4 SEG22 P4 5 SEG23 P4 6 SEG24 P4 7 SEG25 P4CONH bit pair pin configuration settings 00 Input mode 01 Output mode N channel open drain 10 Output mode push pull 11 Alternative function SEG25 SEG22 Figure 9 13 Port 4 High Byte Control Register ELECTRONICS 9 13 PORTS S3C828B F828B C8289 F8289 C8285 F8285 Port 4 Control Register Low Byte PACONL EDH Set 1 Bank 1 R W P4 0 SEG18 1 SEG19 P4 2 SEG20 P4 3 SEG21 P4CONL bit pair pin configuration settings Input mode Output mode N channel open drain Output mode push pull Alternative function SEG21 SEG18 Figure 9 14 Port 4 Low Byte Control Register PACONL Port 4 Pull up Resistor Enable Register PAPUR EEH Set 1 Bank 1 R W Tg P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 P4PUR bit configuration settings 0 Pull up Disable Pull up Enable Figure 9 15 Port 4 Pull up Resistor Enable Register P4PUR 9 14 ELECTRONICS 53 828 828 8289 8289 8285 8285
97. 4 47 TOCON Timer 0 Gontrol Fegister c ote itte ee 4 48 T1CON Timer t Gontro Register nep eei teure dienes 4 49 TACON Timer A Control R gist r uns ibs erre e I IER ed ene Pope i ee 4 50 Timer B Control Register 4 51 UARTCON UART Control ROegiS 8er iced 1 nacti ale eo mete tee dio edes 4 52 WTCON Watch Timer Control Register 4 53 Xx S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add Will erret i eo vend ss as rere cs 6 14 ADD ay cathode i deis 6 15 AND AND sy una a tee e ER suq u p dd 6 16 BAND BIEAND uu pu o p ER e RO a dt bs pei Pee ee ded eee 6 17 BCP BikKCompares 2 RU eer ERES stri etd ie e e e pre ead 6 18 BITC Bit Complement us u rre tte e cere ted etse topi eee oed eos 6 19 BITR Bit Iesot x iut dabei deed eda 6 20 BITS 6 21 BOR BEOR goal D inue bo iat ce eek im dei eR 6 22 BTJRF Bit Test Jump Relative on 6 23 BTJRT Bit Test Jump Relative on Tre a al ul HS nennen 6 24 BXOR BIEXOR aha sits ee on be o ete P PL nde ado doter 6 25 CALL Call Procedure iie n RP p i
98. 53 828 828 8289 8289 8285 8285 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems i
99. 8 fxx 4 Not used for the 53 828 8289 8285 3 Timer 0 Counter Clear Bit 0 No effect Clear the timer 0 counter when write 2 Timer 0 Counter Enable Bit EN Disable counting operation Enable counting operation 1 Timer 0 Match Interrupt Enable Bit EN Disable interrupt Enable interrupt 0 Timer 0 Interrupt Pending Bit No timer 0 interrupt pending when read Clear timer 0 interrupt pending bit when write TO interrupt is pending NOTE The TOCON 3 value is automatically cleared to 0 after being cleared counter 4 48 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER T1CON Timer 1 Control Register FBH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 1 Input Clock Selection Bits 0 0 fxx 1024 0 1 fxx 256 EN fxx 64 0 fxx 1 1 External clock T1CLK falling edge External clock T1CLK rising edge 1 Counter stop Interval mode T1OUT Capture mode Capture on rising edge counter running OVF can occur Capture mode Capture on falling edge counter running OVF can occur PWM mode OVF and match interrupt can occur 2 Timer 1 Counter Enable Bit EN No effect Clear the timer 1 counter when write 1 Timer 1 Match Capture Interrupt Enable Bit EN Disable interrupt Enable interrupt 0 Timer 1 Overflow Interrupt Enable Bit 0 D
100. 82 P8 7 COM2 COM7 SEG0 SEG5 lt P7 0 P7 3 SEG8 SEG9 PortG 4 P6 0 P6 7 SEG10 SEG17 1 4 7 ELECTRONICS 53 828 828 8289 8289 8285 8285 PRODUCT OVERVIEW PIN ASSIGNMENT 80 1 SEG28 P5 2 79 SEG27 P5 1 78 SEG26 P5 0 25 4 7 76 SEG24 P4 6 75 SEG23 P4 5 74 3 5 22 4 4 73 SEG21 P4 3 72 F3 SEG20 P4 2 71 SEG19 P4 1 70 SEG18 P4 0 69 1 SEG17 P6 7 68 SEG16 P6 6 67 SEG15 P6 5 66 SEG14 P6 4 65 SEG13 P6 3 SEG29 P5 3 SEG30 P5 4 SEG31 P5 5 SEG32 P5 6 SEG33 P5 7 SEG34 P3 0 TBPWM SEG35 P3 1 TAOUT TAPWM SEG36 P3 2 TACLK COM7 SEG5 P8 7 SEG37 P3 3 TACAP 5 COM6 SEG4 P8 6 P3 4 TxD S3C828B F828B COMBS SEG3 P8 5 P3 5 RxD S3C8289 F8289 I COM4 SEG2 P8 4 VDD COM3 SEG1 P8 3 SEG12 P6 2 SEG11 P6 1 SEG10 P6 0 SEG9 P7 3 SEG8 P7 2 SEG7 P7 1 SEG6 P7 0 e Vss S3C8285 F8285 COM2 SEGO P8 2 XOUT COM1 P8 1 XIN COMO P8 0 ME 80 QFP 1420C VLC2 XTOUT VLC1 nRESET VLC0 VREG AVss P0 0 INT0 AVREF P0 1 INT1 P2 7 AD7 VBLDREF P0 2 INT2 P2 6 AD6 P0 3 INT3 P2 5 AD5 PO 4 INT4 25 PO 5 INT5 C 26 PO 6 INT6 C 27 PO 7 INT7 C 28 P1 0 T1CAP C4 29 1 1 1 30 P1 3 BUZ 32 P1 4 SO 33 P1 5 SCK 34 1 6 51 35 P2 0 ADO 36 P2 1 AD1 C 37 P2 2 AD2 C 38 P2 3 AD3 C 39 P2 4 AD4 C 40 P1 2 T1OUT T1PWM 31
101. 8285 F8285 ELECTRICAL DATA Table 20 3 A C Electrical Characteristics 25 C to 85 C Vpp 2 0 V to 3 6 V Interrupt input high low tintH tint All interrupt Vpp V width 0 0 0 7 External Interrupt Figure 20 1 Input Timing for External Interrupts tRSL nRESET 0 2 VDD Figure 20 2 Input Timing for nRESET ELECTRONICS 20 5 ELECTRICAL DATA S3C828B F828B C8289 F8289 C8285 F8285 Table 20 4 Input Output Capacitance TA 25 C to 85 C Vpp 0 V Input f 1 MHz unmeasured pins 10 pF capacitance are returned to Vss Output Cour capacitance capacitance Table 20 5 Data Retention Supply Voltage in Stop Mode 25 C to 85 C Data retention supply voltage Data retention Vpppn 2V supply current Stop mode T4 25 C Disable LVR block Occurs Oscillation Stabilization r Stop Mode 4 gt Time Y Normal 4 Data Retention Mode gt 4 9 4 operating Mode Execution of STOP Instrction nRESET twAIT is the same as 16 x 1 BT clock Figure 20 3 Stop Mode Release Timing Initiated by RESET 20 6 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 ELECTRICAL DATA Idle Mode x Basic Timer Active 1 Stop Mode lt Normal lt Data Retention Mode gt Operating Mode Execution of STOP Instruction NOTE twarr is the same as 16 x
102. 8289 C8285 RP1 Register Pointer 1 D7H Set 1 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset points to address in register set 1 selecting the 8 byte working register slice CSH CFH 2 0 Not used for the S3C828B C8289 C8285 ELECTRONICS CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 SIOCON sio contro Register EOH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 SIO Shift Clock Selection Bit EN Internal clock P S clock External clock SCK 6 Data Direction Control Bit MSB first mode 1 LSB first mode 5 SIO Mode Selection Bit EN Receive only mode Transmit Receive mode 4 Shift Clock Edge Selection Bit EN Tx at falling edges Rx at rising edges Tx at rising edges Rx at falling edges 3 SIO Counter Clear and Shift Start Bit 0 No action 1 Clear 3 bit counter and start shifting 2 SIO Shift Operation Enable Bit EN Disable shifter and clock counter Enable shifter and clock counter 1 SIO Interrupt Enable Bit 0 Disable SIO Interrupt Enable SI
103. 85 F8285 CONTROL REGISTER P2CONL Port 2 Control Register Low Byte E9H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 AD3 0 Input mode 1 Input mode pull up KEE Output mode push pull Alternative function AD3 5 4 P2 2 AD2 Input mode Input mode pull up Output mode push pull 1 Alternative function AD2 3 2 P2 1 AD1 Input mode 0 0 1 Input mode pull up 1 0 Output mode push pull 0 0 Input mode 0 Input mode pull up Output mode push pull Alternative function ADO ELECTRONICS 4 29 CONTROL REGISTERS S3C828B F828B C8289 F8289 C8285 F8285 P3CONH Port 3 Control Register High Byte EAH Set 1 Bank 1 RESET Value 0 0 0 0 Read Write E _ _ R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the 53 828 8289 8285 5 P3 1 TAOUT TAPWM SEG35 P3CONL 3 2 11 only 0 TAOUT TAPWM out SEG35 out 4 P3 0 TBPWM SEG34 P3CONL 3 2 11 only 0 TBPWM out 1 SEG34 out 3 2 P3 5 RxD o 0 Input mode RxD ENEN Input mode pull up RxD Output mode push pull Alternative function RxD out 1 0 P3 4 TxD ENEN Input mode pull up ifo Output mode push pull Alternative function TxD 4 30 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTR
104. 9 C8285 F8285 INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ r dst Operation r 1 lf r 0 PC lt PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE Incase of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or SRP1 instruction Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken rA RA 8 no jump r OtoF Example Given R1 02H and LOOP is the label of a relative address SRP 0COH DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION
105. 9H Set 1 Bank 0 R W Not used Timer A overflow interrupt pending bit Timer A match capture interrupt pending bit Timer 1 overflow interrupt pending bit Timer 1 match capture interrupt pending bit Tx interrupt pending bit for UART Rx interrupt pending bit for UART 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending Figure 17 2 UART Interrupt Pending Bits INTPND 5 4 ELECTRONICS 17 3 UART 53 828 828 8289 8289 8285 8285 UART DATA REGISTER UDATA UART Data Register UDATA F7H Set 1 Bank 0 R W Transmit or receive data Figure 17 3 UART Data Register UDATA UART BAUD RATE DATA REGISTER BRDATA The value stored in the UART baud rate register BRDATA lets you determine the UART clock rate baud rate UART Baud Rate Data Register BRDATA F8H Set 1 Bank 0 R W Baud rate data Figure 17 4 UART Baud Rate Data Register BRDATA BAUD RATE CALCULATIONS Mode 0 Baud Rate Calculation In mode 0 the baud rate is determined by the UART baud rate data register BRDATA in set 1 bank 0 at address F8H Mode 0 baud rate fxx 16 x BRDATA 1 Mode 2 Baud Rate Calculation The baud rate in mode 2 is fixed at the fosc clock frequency divided by 16 Mode 2 baud rate fxx 16 Modes 1 and 3 Baud Rate Calculation In modes 1 and 3 the baud rate is determined by the UART baud rate data register BRDATA in set 1 bank 0 at a
106. B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET BXOR Bit XOR BXOR BXOR Operation Flags Format Examples dst src b dst b src dst O lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst b 0 src 3 6 27 ro Rb opc dst 3 6 27 Rb NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 00000011B BXOR H1 01H 1 gt R1 O6H registerO1H BXOR 01H 2 R1 gt Register 01H O7H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to O6H The value of source register
107. C2 VLC3 Vss COMO VLCO VLC1 VLC2 VLC3 Vss COM1 VLCO VLC1 VLC2 VLC3 Vss 2 VLCO VLC1 VLC2 VLC3 Vss VLCO VLC1 VLC2 VLC3 Vss SEGO VLCO VLC1 VLC2 VLC3 Vss SEG1 VLCO 1 3 VLCO OV 1 3 VLCO COMO SEGO VLCO NOTE VLC2 VLC3 Figure 14 9 LCD Signal Waveforms 1 4 Duty 1 3 Bias ELECTRONICS 14 9 LCD CONTROLLER DRIVER S3C828B F828B C8289 F8289 C8285 F8285 m W OOM Td 7 2 W OOE FR 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Vss 6 gt 1 coms com4 L COM7 VLCO VLC1 VLC2 VLC3 Vss L a a 5 G 8 camo HOOLI ome VLCo VLC2 VLC3 Vss 1 VLCo se 2 Vss 2 VLCO VLC1 VLC2 VLC3 Vss SEGO SEG5 COMO 14 10 Figure 14 10 LCD Signal Waveforms 1 8 Duty 1 4 Bias ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 LCD CONTROLLER DRIVER 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 VLC1 FR Vss tc 1 Frame VLCI VLc2 VLC3 Vss SEG6 BESSA cue Se ae Sa as ae VECO cuve mas E A sm Ee gt 2 ce MBOS SEG6 COMO p5999 9 8 9 55 9 056s69 OV VLC3 Feeney IUE Vice2 SSS
108. C8285 F8285 microcontroller supports nineteen interrupt sources All nineteen of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE 53 828 828 8289 8289 8285 8285 Levels Vectors Sources Reset Clear RESET 100H Basic Timer Overflow H W DCH ms Timer A match capture S W DEH U Timer A overflow H W S W IRQI nn Timer B match H W IRQ2 2 xz V n RO Timer 0 match S W E4H T L Timer 1 match capture S W E6H nT Timer 1 overflow H W
109. CH FMSECL to sector value of write address Load a transmission data into a working register Load a flash memory upper address into upper register of pair working register Load a flash memory lower address into lower register of pair working register Load transmission data to flash memory location area on LDC instruction by indirectly addressing mode Set Flash Memory User Programming Enable Register FMUSR to 00000000B O09 c qo os PROGRAMMING TIP Program SB1 LD FMSECH 17H LD FMSECL 80H Set sector address 1780H 17FFH LD R2 17H Set ROM address in the same sector 1780H 17FFH LD R3 84H LD R4 78H Temporary data LD FMUSR 0A5H User Program mode enable LD FMCON 01010000B Start program LDC RR2 R4 Write the data to a address of same sector 1784H NOP Dummy Instruction This instruction must be needed LD FMUSR 0 User Program mode disable 19 10 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 EMBEDDED FLASH MEMORY INTERFACE READING The read operation of programming starts by LDC instruction THE PROGRAM PROCEDURE IN USER PROGRAM MODE 1 Load a flash memory upper address into upper register of pair working register 2 Load a flash memory lower address into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode PROGRAMMING TIP Reading LD R2 3H
110. CNTL EDH bank 0 T1DATAH T1DATAL EEH EFH bank 0 SIO interrupt IRQ4 SIOCON EOH bank 0 SIODATA E1H bank 0 SIOPS E2H bank 0 UART data transmit IRQ5 UARTCON F6H bank 0 UART data receive UDATA F7H bank 0 BRDATA F8H bank 0 Watch timer overflow WTCON D1H bank 0 PO 0 external interrupt IRQ6 POCONL E1H bank 1 P0 1 external interrupt POINTL bank 1 P0 2 external interrupt POPND bank 1 P0 3 external interrupt P0 4 external interrupt IRQ7 POCONH EOH bank 1 PO 5 external interrupt POINTH E2H bank 1 P0 6 external interrupt POPND E4H bank 1 P0 7 external interrupt ELECTRONICS 5 9 INTERRUPT STRUCTURE S3C828B F828B C8289 F8289 C8285 F8285 SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing and to control fast interrupt processing see Figure 5 5 A reset clears SYM 1 and SYM 0 to 0 The 3 bit value for fast interrupt level selection SYM 4 SYM 2 is undetermined The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate 5 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this pu
111. CON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using Register addressing mode A reset clears BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of 5 4096 To disable the watchdog function you must write the signature code 1010B to the basic timer register control bits 7 4 The 8 bit basic timer counter set 1 bank 0 FDH can be cleared at any time during the normal operation by writing a 1 to BTCON 1 To clear the frequency dividers write a 1 to 0 ELECTRONICS 10 1 BASIC 53 828 828 8289 8289 8285 8285 Basic Control Register BTCON D3H Set 1 R W Watchdog timer enable bits Divider clear bit 1010B Disable watchdog function 0 effect Other value Enable watchdog function 1 Clear dvider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bits 00 fxx 4096 01 fxx 1024 10 fxx 128 11 fxx 16 Figure 10 1 Basic Timer Control Register 10 2 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by set
112. CS 17 9 UART 53 828 828 8289 8289 8285 8285 SERIAL PORT MODE 3 FUNCTION DESCRIPTION In mode 3 11 bits are transmitted through the TxD P3 4 pin or received through the RxD P3 5 pin Mode 3 is identical to mode 2 except for baud rate which is variable Each data frame has four components Start bit 0 8data bits LSB first Programmable 9th data bit Stop bit 1 Mode 3 Transmit Procedure 1 Select the baud rate generated by BRDATA 2 Select mode 3 operation 9 bit UART by setting UARTCON bits 6 and 7 to 11B Also select the 9th data bit to be transmitted by writing UARTCON 3 TB8 to 0 or 1 3 Write transmission data to the shift register UDATA F7H set 1 bank 0 to start the transmit operation Mode 3 Receive Procedure 1 Select the baud rate to be generated by BRDATA 2 Select mode 3 and set the RE Receive Enable bit in the UARTCON register to 1 3 The receive operation will be started when the signal at the RxD P3 5 pin goes to low level Tx JL Write to Shift Register UARTDATA TxD start Bit X X ps X Y ps X pe X vv X ree Stop Bit TIP Transmit RxD start Bi DO x D1 D2 X D3 X D4 D5 X D6 X D7 RBS Bit Detect Sample Time
113. CTION SET 53 828 828 8289 8289 8285 8285 RET Return RET Operation lt SP Flags Format Example 6 70 SP SP 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Given SP OOFCH SP 101AH andPC 1234 RET gt PC 101AH SP 00 The statement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET RL Rotate Left RL Operation dst C lt dst 7 dst 0 dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags Format Examples C Set if the bit rotated from the most significant bit position bit 7
114. E6H and match capture interrupt IRQ3 vector E4H generation Timer 1 control register T1CON set 1 Bank 0 EBH read write 12 4 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 16 BIT TIMER 0 1 TIMER 1 CONTROL REGISTER T1CON You use the timer 1 control register T1CON to Select the timer 1 operating mode interval timer capture mode or PWM mode Select the timer 1 input clock frequency Clear the timer 1 counter T1CNTH T1CNTL Enable the timer 1 overflow interrupt or timer 1 match capture interrupt Clear timer 1 match capture interrupt pending conditions T1CON is located in set 1 and Bank 0 at address EBH and is read write addressable using Register addressing mode A reset clears T1CON to OOH This sets timer 1 to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer 1 interrupts To disable the counter operation please set T1CON 7 5 to 111B You can clear the timer 1 counter at any time during normal operation by writing a 1 to T1CON 3 The timer 1 overflow interrupt T1OVF is interrupt level IRQ3 and has the vector address E6H When timer 1 overflow interrupt occurs and is serviced interrupt IRQ3 vector E4H you must write T1 CON 1 to 1 To generate the exact time interval you should write T1 CON by the CPU the pending condition is cleared automatically by hardware To enable the timer 1 match capture which clear counter and inter
115. ESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset 1 0 1 0 Disable watchdog timer function Others Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits 9 EX 1 fxx 128 1 1 fxx 16 4 Basic Timer Counter Clear Bit 1 EN No effect Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer Timer Counters 2 No effect 1 Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to Immediately following the write operation the 0 value is automatically cleared to O 3 The fxx is selected clock for system main OSC or sub OSC ELECTRONICS 4 7 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 System Clock Control Register D4H Set 1 RESET Value 0 0 0 Read Write R W R W R W Addressing Mode Register addressing mode only 7 Oscillator IRQ Wake up Function Bit EN Enable IRQ for main wake up in power down mode Disable IRQ for main wake up in power down mode 6 5 Not used for the S3C828B C8289 C8285 4
116. ESS SPACES 53 828 828 8289 8289 8285 8285 PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S3C828B F828B has 64K bytes internal mask programmable program memory the S3C8289 F8289 has 32K bytes and the S3C8285 F8285 has 16K bytes The first 256 bytes of the ROM are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H in the S8C828B C8289 C8285 The reset address of ROM can be changed by a smart option only in the S3F828B Full Flash Device Refer to the chapter 19 Embedded Flash Memory Interface for more detail contents Decimal 65 535 Decimal 32 767 64K bytes Internal Program Memory Area 32K bytes 16 383 Internal Program Memory Area 16K bytes Internal Program Memory Area Decimal Interrupt Vector Area Interrupt Vector Area S3C828B F828B S3C8289 F8289 S3C8285 F8285 Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 ADDRESS SPACES SMART OPTION ROM Address 003EH ISP lecti its ISP reset vector ses enable in des disable bit 01 512 bytes used 0 OBP reset vector address 10 10
117. F8289 C8285 F8285 HARDWARE RESET VALUES Table 8 1 8 2 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values 1 0 shows the reset bit value as logic one or logic zero respectively means that the bit value is undefined after a reset dash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 S3C828B F828B C8289 F8289 C8285 F8285 Set 1 Register and Values after RESET Register Name Mnemonic Address _ Bit Values after RESET Dec Hex 7 6 Locations DOH D2H are not mapped Basictimercontrolregistr BTCON 211 DH 0 0 O O O System clock contiolregister__ CLKCON 212 peo System flags register 213 D5H Register pointer 0 Register pointer 1 Stack pointer high byte Stack pointer low byte Instruction pointer high byte Instruction pointer ow byte NOTES 1 means that the bit value is undefined following reset 2 Adash means that the bit is neither used nor mapped but the bit is read as 0 8 2 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 RESET and POWER DOWN Table 8 2 S3C828B F828B C8289 F8289 C8285 F8285 Set 1 Bank 0 Register and Values after RESET Register Name Mnemonic Bit Values after RESET Dec
118. Given Register 55H register 01H 02H register 02H 17H andC 0 RRC 00H gt Register 2AH C 1 RRC 01H gt Register 01H 02H register 02H OBH C 1 In the first example if general register OOH contains the value 55H 01010101B the statement RRC rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010 in destination register OOH The sign flag and overflow flag are both cleared to 0 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 SB1 Select Bank 1 SB1 Operation Flags Format Example 6 76 BANK lt 1 SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3C8 series microcontr
119. H PUSH 40H gt Register 40H 4FH stack register 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value OOOOH and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example dst src IR IR 1 dst lt src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 82 IR R Given RegisterOOH register 01H 05H and register 02H PUSHUD 00H 01H gt RegisterOOH 2 register 01H 05H register 02H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack point
120. H R W R W R W Port 2 Data Register P2 242 F2H Port 3 Data Register P3 243 F3H Ponts Data Reger Pm Pons baa Regier Flash Memory User Programming Enable Register FMUSR ELECTRONICS 246 247 248 F6H F7H R W R W R W R W R W R W R W R W R W R W R W R W R W 4 3 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 Name of individual bit or related bits Bit number s that is are appended to the register name for bit addressing Register location in the internal Register address Register ID Full Register name hexadecimal register file FLAGS System Flags Register Bit Identifier RESET Value Read Write Bit Addressing Register addressing modelonly Mode p 7 Carry Flag C 0 Operation does not generate a carry or borrow condition Operation generates carry out or borrow into high order bit 7 gt 6 Zero Flag Z Operation result is a non zero value 0 Operation result is zero 5 Sign Flag S Y Operation generates positive number MSB 0 Operation generates negative number MSB 1 R Read only Description of the Bit number W Write only effect of specific MSB Bit 7 R W Read write bit settings LSB Bit 0 Not used Type of addressing that must be used to address the bit 1 bit 4 bit or 8 bit RESET value notation Not used x Undetermined value 0 Logic zero 1 Logi
121. H Invalid addressing mode Use working register addressing instead SRP 0COH ADD R3 45H gt 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 14 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 15 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five
122. H MCU OVERVIEW The S3F828B F8289 F8285 single chip CMOS microcontroller is the Flash MCU version of the S3C828B C8289 C8285 microcontroller It has an on chip Flash MCU ROM instead of a masked ROM The Flash ROM is accessed by serial data format The S3F828B F8289 F8285 is fully compatible with the 53 828 8289 8285 both in function and in pin configuration Because of its simple programming requirements the S3F828B F8289 F8285 is ideal as an evaluation chip for the S3C828B C8289 C8285 NOTE This chapter is about the Tool Program Mode of Flash MCU If you want to know the User Program Mode refer to the chapter 19 Embedded Flash Memory Interface ELECTRONICS 22 1 53 828 8289 8285 FLASH MCU SEG29 P5 3 SEG30 P5 4 SEG31 P5 5 SEG32 P5 6 SEG33 P5 7 SEG34 P3 0 TBPWM SEG35 P3 1 TAOUT TAPWM SEG36 P3 2 TACLK SEG37 P3 3 TACAP SDAT P3 4 TxD SCLK P3 5 RxD VDD VDD Vss Vss Xour XIN VPP TEST XTour nRESET nRESET VREG PO O INTO PO 1 INT1 PO 2 INT2 PO 3 INT3 ELELELEL D DLELDLTLTLTLTLTLTI TL TIL TI TT C1 ET LI E O O1 G SEG28 P5 2 80 SEG27 P5 1 79 78 77 76 75 74 SEG26 P5 0 SEG25 P4 7 SEG24 P4 6 SEG23 P4 5 SEG22 P4 4 SEG21 P4 3 73 72 71 SEG20 P4 2 SEG19 P4 1 SEG18 P4 0 SEG17 P6 7 SEG16 P6 6 SEG15 P6 5 SEG14 P6 4 SEG13 P6 3 70 69 68 67 S3C828B F828B C8289 F8289 C8285 F8285 66 65 53 828 8289 8
123. IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory lt Next Instruction LSB Must be Zero Current Instruction OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS 53 828 828 8289 8289 8285 8285 ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that suppo
124. IGNALS The 38 LCD segment signal pins are connected to corresponding display RAM locations at page 15 Bits of the display RAM are synchronized with the common signal output pins When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal to the corresponding segment pin 14 6 ELECTRONICS 53 828 828 8289 8289 8285 8285 LCD CONTROLLER DRIVER Select lt H Non Select 1 i 1 Frame VLC1 2 3 VLC 0 VLC1 2 3 Vss VLC1 2 3 VLC 0 COM SEG Figure 14 6 Select No Select Signal in 1 2 Duty 1 2 Bias Display Mode gt gt Select lt Non Select 1 F 1 lt 1 Frame gt Figure 14 7 Select No Select Signal in 1 3 Duty 1 3 Bias Display Mode ELECTRONICS 14 7 LCD CONTROLLER DRIVER S3C828B F828B C8289 F8289 C8285 F8285 SEG2 SEG1 VLCO VLC1 VLC2 VLC3 Vss VLCO VLC1 VLC2 VLC3 Vss VLCO VLC1 VLC2 VLC3 Vss VLCO VLC1 VLC2 VLC3 Vss VLCO VLC1 VLC2 VLC3 Vss VLCO 1 3 VLCO SEG0 COMO OV 1 3 VLCo VLCO NOTE VLCO2 VLC3 Figure 14 8 LCD Signal Waveforms 1 3 Duty 1 3 Bias 14 8 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 LCD CONTROLLER DRIVER p Vss VLCO VLC1 VL
125. ION SET 53 828 828 8289 8289 8285 8285 Interrupt Return IRET Operation Flags Format Example NOTE 6 46 IRET Normal IRET Fast FLAGS lt SP PC IP SP lt SP 1 FLAGS lt FLAGS lt SP FIS 0 SP SP 2 SYM 0 lt 1 This instruction is used at the end of an interrupt service routine lt restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Hex Normal 1 10 internal stack BF 12 internal stack IRET Bytes Cycles Opcode Hex Fast opc 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next
126. IOPS BLOCK DIAGRAM m SIO INT SIOCON 0 IRQ4 CLK ear Pending SIOCON 1 SIOCON 3 Interrupt Enable SIOCON 7 l SIOCON 4 SIOCON 2 Edge Select Shift Enable SIOCON 5 SCK Mode Select CLK g Bit SIO Shift Buffer MS so fxx 2 gt SIODATA E1H bank 0 A SIOCON 6 LSB MSB First Mode Select SI l Data Bus Figure 16 3 SIO Functional Block Diagram ELECTRONICS 16 3 SERIAL I O INTERFACE S3C828B F828B C8289 F8289 C8285 F8285 SERIAL I O TIMING DIAGRAM Transmit Complete SCK SI SO Transmit IRQS Complete _ Set SIOCON 3 Figure 16 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 16 4 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 UART UART OVERVIEW The UART block has a full duplex serial port with programmable operating modes There is one synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes Serial I O with baud rate of fxx 16 x BRDATA 1 8 bit UART mode variable baud rate 9 UART mode fxx 16 9 UART mode variable baud rate UART receive and transmit buffers are both accessed via the data register UDATA is set 1 bank 0 at address F7H Writing to the UART data register loads the transmit buffer reading the UART data register accesses a physically separate receive buffer When accessing a receive data buffer shift
127. M Examples Given R1 10H R2 1 registerO1H 20H registerO2H and register 03H OAH SBC R1 R2 gt R1 OCH R2 03H SBC R1 R2 gt R1 05H R2 registerO3H OAH SBC 01H 02H gt Register 01H 1CH register 02H SBC 01H 02H Register 01H 15H registerO2H 03H register 03H OAH SBC O1H 8AH gt Register 01H 95H C S andV 1 In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 77 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 SCF set Carry Flag SCF Operation Flags Format Example 6 78 Ce 1 The carry flag C is set to logic one regardless of its previous value Setto 1 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 DF The statement SCF sets the carry flag to logic one ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET SRA Shift Right Arithmetic SRA Operation Flags Format Examples dst dst 7 lt dst 7 C lt dst 0 dst lt dst n 1 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is
128. O Interrupt 0 SIO Interrupt Pending Bit EN No interrupt pending when read Clear pending condition when write Interrupt is pending 4 44 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER SPH stack Pointer High Byte Set 1 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL stack Pointer Low Byte D9H Set 1 RESET Value X x x x x x X x Read Write R W R W R W RW R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SP0 The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset ELECTRONICS 4 45 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 STPCON Stop Control Register FBH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE Before ex
129. OL REGISTER P3CONL Port 3 Control Register Low Byte EBH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 TACAP SEG37 0 Input mode TACAP 1 Input mode pull up TACAP KEE Output mode push pull Alternative function SEG37 5 4 P3 2 TACLK SEG36 Input mode TACLK Input mode pull up TACLK Output mode push pull 1 Alternative function SEG36 3 2 P3 1 TAOUT TAPWM SEG35 0 0 Input mode Input mode pull up Output mode push pull Alternative function TAOUT TAPWM SEG35 0 0 Input mode 0 Input mode pull up Output mode push pull Alternative function TBPWM SEG34 ELECTRONICS 4 31 CONTROL REGISTERS S3C828B F828B C8289 F8289 C8285 F8285 P4CONH Port 4 Control Register High Byte ECH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 7 SEG25 Input mode Output mode N channel open drain KEREN Output mode push pull Alternative function SEG25 5 4 3 2 0 0 Input mode Output mode N channel open drain 0 Output mode push pull EN Alternative function SEG23 1 0 P4 4 SEG22 0 0 Input mode 1 Output mode N channel open drain ESEN Output mode push pull EHEN Alternative function SEG22
130. ON The control register for the UART is called UARTCON in set 1 bank 0 at address It has the following control functions Operating mode and baud rate selection Multiprocessor communication and interrupt control Serial receive enable disable control 9th data bit location for transmit and receive operations modes 2 and only UART transmit and receive interrupt control A reset clears the UARTCON value to 00H So if you want to use UART module you must write appropriate value to UARTCON UART Control Register UARTCON F6H Set 1 Bank 0 R W vso vs uen woe ne seo se re 76 Jus Operating mode and Transmit interrupt enable bit baud rate selection bits 0 Disable see table below 1 Enable Multiprocessor communication Received interrupt enable bit enable bit for modes 2 and 3 only 0 Disable 0 Disable 1 Enable 1 Enable Serial data receive enable bit Location of the 9th data bit that was 0 Disable received UART mode 2 or 3 0 or 1 1 Enable Location of the 9th data bit to be transmitted in UART mode 2 or 3 0 or 1 MS1 MSO Mode Description Baud Rate Shift register fxx 16 x BRDATA 1 8 bit UART fxx 16 x BRDATA 1 9 bit UART fxx 16 9 bit UART fxx 16 x BRDATA 1 NOTES 1 In mode 2 or 3 if the UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In
131. P P3 3 gt 8 Bit Timer 16 Bit Counter 0 T1CAP P1 0 gt 16 Bit Timer 1 1 1 gt Counter 1 T1OUT T1PWM P1 2 4 P0 0 P0 7 INTO INT7 0 1 0 1 Port 0 P1 1 T1CLK P1 2 T10UT T1PWM P1 3 BUZ4 IO Port 1 1 4 50 1 5 5 P1 6 SI P2 0 P2 6 ADO AD6 P2 7 AD7 VBLDREF Port2 XIN XOUT y nRESET XTi XTour REG t t 1 d Watchdog Port I O and Interrupt Control SAM88RC CPU Timer Basic Timer Battery Level Detector VBLDREF P2 7 AD7 Watch Timer BUZ P1 3 LCD Driver Controller COM0 COM1 P8 0 P8 1 2 7 5 0 5 5 8 2 8 7 SEG6 SEG9 P7 0 P7 3 gt SEG10 SEG17 P6 0 P6 7 gt SEG18 SEG25 P4 0 P4 7 gt SEG26 SEG33 P5 0 P5 7 SEG34 SEG37 P3 0 P3 3 VLCO VLC3 SO P1 4 lt gt SCK P1 5 SI P1 6 P3 0 TBPWM SEG34 P3 1 TAOUT TAPWM SEG35 P3 2 TACLK SEG36 lt gt P3 3 TACAP SEG37 P3 4 TxD P3 5 RxD P4 0 P4 7 SEG18 SEG25 Port 3 4 P5 0 P5 7 64 32 16 2 5K 1K 512 Kbyte byte ROM Register File TxD P3 4 RxD P3 5 10 bit ADC 4 ADO0 AD6 P2 0 P2 6 lt ADTIP2 7 VBLDREF SEG26 SEG33 4 VO Port 5 Figure 1 1 Block Diagram 4 gt P8 0 P8 1 COMO COM1 Port8 P
132. R RE ete euet 6 71 RLC Rotate Left through Carry ente ded podre er dr e Re o 6 72 RR Rotate Rig hits i iue e e deed artis os im indio Date ee ee ieee 6 73 RRC Rotate Right through 6 74 SBO Select Bark e Re RR ede E Renfe ide ei dle 6 75 SB1 Select Bank etate tieu 6 76 SBC Subtract with u e Atto e estes 6 77 SCF Set Carry iot i ee e spatula a 6 78 SRA Shift Right Arithirietic iccirco iecit inei de ne ieri ed 6 79 SRP SRPO SRP 1 E nt 6 80 STOP Stop Operation St su teet i e eR este at a u asa sad 6 81 SUB S blract 5 tide be a etus 6 82 SWAP SWap NIDDI6S u seed iride ttt lr ri RU GP yir e eee 6 83 TCM Test Complement under nemen 6 84 TM Testunder Mask nde d dus eve ies 6 85 WFI Wait for Interrupts Za pu ete nt tu use oe 6 86 XOR Logical Exclusive ORs iiu Ft ed tg te i im e ge ROO e o ia 6 87 xxii S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER 53 828 828 8289 8289 8285 8285 PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS PRODUCT OVERVIEW Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes Among the major CPU features are Efficient register orient
133. REG SEG7 P7 1 59 60 1 SEG8 P7 2 PO O INTO 9 F3 1 SEG9 P7 3 61 62 SEG10 P6 0 PO 2 INT2 C3 5 F3 P0 3 INT3 SEG11 P6 1 63 3 64 SEG12 P6 2 P0 4 INT4 F3 P0 5 INT5 SEG13 P6 3 J 65 66 SEG14 P6 4 PO 6 INT6 C3 E3 P0 7 INT7 SEG15 P6 5 C3 67 68 SEG16 P6 6 P1 0 T1CAP Cj 3 E3 P1 1 T1CLK SEG17 P6 7 69 70 SEG18 P4 0 P1 2 T1OUT T1PWM L3 P1 3 BUZ SEG19 P4 1 71 72 SEG20 P4 2 1 4 50 L3 P1 5 SCK SEG21 P4 3 C3 73 74 SEG22 P4 4 1 6 5 L3 P2 0 ADO SEG23 P4 5 75 76 SEG24 P4 6 P2 1 AD1 Cj L3 P2 2 AD2 SEG25 P4 7 77 78 SEG26 P5 0 P2 3 AD3 L L3 P2 4 AD4 SEG27 P5 1 79 80 SEG28 P5 2 Figure 23 3 40 Connectors J101 J102 for TB828B 9 5 Target System J102 J101 Target Board J101 J102 41 42 1 2 Target Cable for 40 Pin Connector Part Name AS40D A Order Code SM6306 79 80 39 40 40 DIP Connectors 10j2euuo 39 40 79 80 Figure 23 4 S3E8280 Cables for 80 QFP Package ELECTRONICS 23 7 DEVELOPMENT TOOLS 53 828 828 8289 8289 8285 8285 NOTES 23 8 ELECTRONICS
134. RUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 ADC Add with carry ADC dst src Operation dst lt dst src c The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands Flags C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set ifthe result is negative cleared otherwise V Set i
135. S 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER POCONL Port 0 Control Register Low Byte E1H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 PO 3 INT3 0 Schmitt trigger input mode 1 Schmitt trigger input mode with pull up resistor KEE Output mode open drain Output mode push pull 5 4 PO 2 INT2 Schmitt trigger input mode Schmitt trigger input mode with pull up resistor Output mode open drain 1 Output mode push pull 3 2 PO 1 INT1 0 0 Schmitt trigger input mode 1 Schmitt trigger input mode with pull up resistor 0 1 0 Output mode open drain 1 0 0 Schmitt trigger input mode 0 Schmitt trigger input mode with pull up resistor Output mode open drain Output mode push pull ELECTRONICS 4 21 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 POINTH Port o Interrupt Control Register High Byte E2H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 PO 7 External interrupt INT7 Enable Bits fo Disable interrupt ofa Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge 5 4 PO 6 External interrupt INT6 Enable Bits fo fo Disable interrupt ofa Enable interrupt
136. S 15 1 A D CONVERTER 53 828 828 8289 8289 8285 8285 CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to set up A D conversion Therefore total of 50 clocks are required to complete an 10 bit conversion When fxx 8 is selected for conversion clock with an 8 MHz fxx clock frequency one clock cycle is 1 us Each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits set up time 50 clocks 50 clock 1us 50 us at 1 MHz A D CONVERTER CONTROL REGISTER ADCON The A D converter control register ADCON is located at address F3H set 1 bank 0 It has three functions Analog input pin selection ADCON 6 4 End of conversion status detection ADCON 3 ADC clock selection ADCON 2 1 A D operation start or enable ADCCON 0 After a reset the start bit is turned off You can select only one analog input channel at a time Other analog input pins ADO AD7 can be selected dynamically by manipulating the 4 6 bits And the pins not used for analog input can be used for normal I O function A D Converter Control Register ADCON F3H Set 1 Bank 0 R W EOC bit is read only Always logic 0 Start or enable bit 0 Disable operation 1 Start operation A D input pin selection bits 0 0 0 ADO Clock Selection bit 001 AD1 0 0 fxx 16 010 AD2 0 1 fxx 8 011 AD3 1 0
137. SET 53 828 828 8289 8289 8285 8285 El Enable Interrupts El Operation Flags Format Example 6 40 SYM 0 lt 1 An El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the El instruction No flags are affected Bytes Cycles Opcode Hex opc 1 4 9F Given SYM OOH El If the SYM register contains the value OOH that is if interrupts are currently disabled the statement El sets the SYM register to 01H enabling all interrupts SYM 0 is the enable bit for global interrupt processing ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 ENTER Enter ENTER Operation SP lt SP 2 SP lt IP IP PC PC IP IP lt IP 2 INSTRUCTION SET This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Example Bytes Cycles Opcode Hex 14 1F The diagram below shows one example o
138. SSING MODES 3C828B F828B C8289 F8289 C8285 F8285 INDIRECT REGISTER ADDRESSING MODE Concluded Register File MSB Points to RPO or RPO or RP1 Selected RP points to start of working register 4 bit Working Block Register Address src Register OPCODE Next 2 bit Point Pair Example Instruction to Working References either Register Pair Program Memory or 1 of 4 Data Memory Program Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory p CEERAND Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS 53 828 828 8289 8289 8285 8285 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations in set 1 using Indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesse
139. T Pending OUT Timer 1 Buffer Register Match Signal lt T1CON 2 Timer 1 Data Register Figure 12 4 Simplified Timer 1 Function Diagram Interval Timer Mode 12 6 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 16 BIT TIMER 0 1 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the T1PWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 1 data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFFFH and then continues incrementing from 0000H Although you can use the match signal to generate a timer 1 overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the T1PWM pin is held to Low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to x 65536 see Figure 12 5 0 Capture Signal Interrupt Enable Disable s T1OVF IRQ3 T1CON 1 16 Bit Up Counter lt INTPND 2 Overflow INT TIINT Match INT Match 16 Bit Comparator Timer 1 Buffer Register High level wh
140. TBDATAL register is loaded into the 8 bit counter Figure 11 7 Timer B Functional Block Diagram 11 8 ELECTRONICS 53 828 828 8289 8289 8285 8285 8 BIT PULSE WIDTH CALCULATIONS tHIGH 4 gt tLOW To generate the above repeated waveform consisted of low period time t ow and high period time tyi When TBOF 0 ti ow TBDATAL 2 x 1 fx OH lt TBDATAL lt 100H where fx The selected clock TBDATAH 2 x 1 fx TBDATAH lt 100H where fx The selected clock When TBOF 1 ti ow TBDATAH 2 x 1 lt TBDATAH lt 100H where fx The selected clock tuigH TBDATAL 2 x 1 fx lt TBDATAL lt 100H where fx The selected clock make tow 24 15 4 MHz fx 4 MHz 4 1 MHz When TBOF 0 24 us TBDATAL 2 fx TBDATAL 2 x tus TBDATAL 22 15 us TBDATAH 2 fx TBDATAH 2 x 1us TBDATAH 13 When TBOF 1 15 us TBDATAL 2 TBDATAL 2 x 1us TBDATAL 13 tLow 24 us TBDATAH 2 fx TBDATAH 2 x 1us TBDATAH 22 ELECTRONICS 11 9 8 BIT A B S3C828B F828B C8289 F8289 C8285 F8285 Timer B Clock 0 TBDATAL 01 FFH TBDATAH 00H 0 TBDATAL 00H TBDATAH 01 FFH 0 TBDATAL 00H TBDATAH 00H 1 TBDATAL 00H TBDATAH 00H
141. TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir src dst 3 6 64 R R 65 R IR dst src 3 6 66 R IM Given RO OC7H R1 02H R2 12H register OOH 2BH register 1H 02H and registerO2H 23H TCM RO R1 gt RO OC7H R1 02H Z 1 TCM RO R1 gt RO OC7H R1 02H registerO2H 23H Z 0 TCM 00H 01H gt RegisterOOH 2BH registerO1H 02H Z l TCM 00H 01H gt Register OOH 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt RegisterOOH 2BH Z 0 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement RO R1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET TM Test Under Mask dst src Operation dst AND src This instruction tests selected bits in the destination operand for a logic
142. TION In mode 0 UART is input and output through the RxD P3 5 pin and TxD P3 4 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 Select mode 0 by setting UARTCON 6 and 7 to 00B 2 Write transmission data to the shift register UDATA F7H set 1 bank 0 to start the transmission operation Mode 0 Receive Procedure Select mode 0 by setting UARTCON 6 and 7 to 00B 2 Clear the receive interrupt pending bit INTPND 5 by writing 0 to INTPND 5 3 Set the UART receive enable bit UARTCON 4 to 1 4 shift clock will now be output to the TxD P3 4 pin and will read the data at the RxD P3 5 pin receive interrupt IRQ5 vector ECH occurs when UARTCON 1 is set to 1 Write to Shift Register UDATA Pn TxD Shift Clock EN EN m EN 4 Transmit Write to UARTPND Clear RIP and set RE RE e Shift 8 RxD Data In DO D1 D2 D3 D4 D5 D6 D7 TxD Shift Clock 1 2 3 4 5 6 7 8 Figure 17 6 Timing Diagram for Serial Port Mode 0 Operation ELECTRONICS 17 7 UART 53 828 828 8289 8289 8285 8285 SERIAL PORT MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted through the TxD P3 4 pin or received through the RxD P3 5 pin Each data frame has three components Start bit 0
143. TO interrupt request is pending when read 4 24 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER P1CONH Port 1 Control Register High Byte 5 Set 1 Bank 1 RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode 7 6 5 4 ELECTRONICS Register addressing mode only Not used for the S3C828B C8289 C8285 P1 6 S o o 1 ouput moge P1 5 SCK o o Schmit wager input mode SCR pu Fo 1 output mode P1 4 SO EN 0 Schmitt trigger input mode EN 1 Output mode N channel open drain 0 Output mode push pull 1 Alternative function SO CONTROL REGISTERS S3C828B F828B C8289 F8289 C8285 F8285 P1CONL Por 1 Control Register Low Byte E6H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 BUZ Schmitt trigger input mode Output mode N channel open drain Output mode push pull Alternative function BUZ Output mode N channel open drain Output mode push pull 1 1 Not used for the S3C828B C8289 C8285 4 26 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER P1 PUR Port 1 Pull up Resistor Enable Register E7H Set 1 Bank 1 Bit Identifier os owe Los e
144. ach four bits Given The carry flag 1 and LABEL X 1FF7H JR CLABELX PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET LD Load LD dst src Operation dst lt src Flags Format The contents of the source are loaded into the destination The source s contents are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst opc src 2 4 r IM r8 r R src opc dst 2 4 r9 R r r OtoF dst src 2 4 C7 r Ir D7 Ir r E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM src dst 3 6 F5 IR R opc dst src 3 6 87 r x r opc src dst x 3 6 97 x r r ELECTRONICS 6 49 INSTRUCTION SET S3C828B F828B C8289 F8289 C8285 F8285 LD Load LD Continued Examples Given RO O1H R1 OAH register OOH 01H registerO1H 20H register 02H 02H LOOP and register LD RO 10H gt RO 10H LD R0 01H gt RO 20H registerO1H 20H LD 01H RO gt Register 01H 01H RO 01H LD R1 RO gt R1 20 0 01H LD RO R1 gt RO O1H R1 OAH registerO1H OAH LD 00H 01H gt RegisterOOH 20H register 01H 20H LD 02H 00H gt Register 02H 20H registerOOH 01H LD 00H 0AH
145. ack address OFBH lt Stack address OFCH RPO lt Stack address OFDH PP lt Stack address OFEH ELECTRONICS 53 828 828 8289 8289 8285 8285 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indirect Register IR Indexed X Direct Address DA Indirect Address 1 Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES 3C828B F828B C8289 F8289 C8285 F8285 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Registe
146. alue 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101 in register R1 Because the result of the complement is not 0 the zero flag 2 in the FLAGS register OD5H is cleared ELECTRONICS 6 19 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 BITR Bit Reset BITR Operation Flags Format Example 6 20 dst b dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst b 0 2 4 77 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITR 11 gt R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET BITS set BITS Operation Flags Format Example dst b dst b lt 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst b 1 2 4 77 rb NOTE In the second byte of
147. alue 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is O the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 BTJ RT Bit Test Jump Relative on True BTJRT Operation Flags Format Example 6 24 dst src b If src b isa 1 thenPC PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 000001 11B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range 127 to 128 ELECTRONICS 3C828
148. ance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Ri Giheung Eup Yongin City Gyeonggi Do Korea C P O Box 37 Suwon 449 900 TEL 82 031 209 1934 FAX 82 031 209 1889 Home Page URL Http www samsungsemi com Printed in the Republic of Korea Preface The S3C828B F828B C8289 F8289 C8285 F8285 Microcontroller User s Manual is designed for application designers and programmers who are using the S3C828B F828B C8289 F8289 C8285 F8285 microcontroller for application development It is organized in two main parts Part Programming Model Part II Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3C828B F828B C8289 F8289 C8285 F8285 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Cha
149. and POP a 2 24 Chapter 7 Clock Circuit switching the GPIU GIOCK 2 iei tdt a lavas de sae ies o eddie es 7 6 Chapter 11 8 bit Timer A B To Generate 38 kHz 1 3 duty signal through 0 11 11 To Generate a one pulse signal through 3 0 nennen 11 12 Chapter 19 Embedded Flash Memory Interface Sector Erase SG 19 9 seins iei eae adiu eidem ib h u ua 19 10 PROACIN Gs 2 0 EET 19 11 Hard Lock Protection fos Bere e e OP UD a e B 19 12 3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER xvii List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A D Converter Control 4 5 BLDCON Battery Level Detector Control Register 4 6 BTCON Basic Timer Control 4 7 CLKCON System Clock Control 4 8 FLAGS System Flags Reglister uui eee er deri rb r es dee een 4 9 FMCON Flash Memory Control 4 10 FMSECH Flash Memory Sector Address Register High 4 11 FMSECL Flash Memory Sector Address Register Low Byte 4 11 FMUSR Flash Memory User Programming Enable Register
150. and pending control 1 bit programmable port Schmitt trigger input or push pull open drain output mode selected by software software assignable pull ups Alternately P1 0 P1 6 be used as TTOUT T1PWM BUZ SO SCK SI 1 bit programmable port Input or push pull output mode selected by software software assignable pull ups Alternatively P2 0 P2 7 can be used ADO AD7 Vg 1 bit programmable port Input or push pull output mode selected by software software assignable pull ups Alternately P3 0 P3 5 can be used as TBPWM TAOUT TAPWM TACLK TACAP TxD RxD or LCD SEG 1 bit programmable port Input or push pull open drain output mode selected by software software assignable pull ups 4 0 4 7 can alternately be used as outputs for LCD SEG 1 bit programmable port Input or push pull open drain output mode selected by software software assignable pull ups 5 0 5 7 can alternately be used as outputs for LCD SEG 1 bit programmable port Input or push pull output mode selected by software software assignable pull ups 6 0 6 7 can alternately be used as outputs for LCD SEG 1 bit programmable port Input or push pull output mode selected by software software assignable pull ups P7 0 P7 3 can alternately be used as outputs for LCD SEG 1 bit or 2 bit or 4 bit programmable port Input or push pull open drain output mode
151. ank 0 at address D1H and is read write addressable using register addressing mode A reset clears WTCON to 00H This disable the watch timer So if you want to use the watch timer you must write appropriate value to WTCON Watch Timer Control Register WTCON D1H Set 1 Bank 0 R W Watch timer clock selection bit timer interrupt pending bit 0 Select main clock divided by 2 fx 128 0 Interrupt request is not pending 1 Select sub clock fxt Clear pending bit when write O 1 Interrupt request is pending Watch timer INT Enable Disable bit Watch timer Enable Disable bit 0 Disable watch timer INT 0 Disable watch timer 1 Enable watch timer INT Enable watch timer Buzzer signal selection bits 00 0 5 kHz Watch timer speed selection bits 01 1 kHz 00 Set watch timer interrupt to 1 s 10 2 kHz 01 Set watch timer interrupt to 0 5 s 11 4 kHz 10 Set watch timer interrupt to 0 25 s 11 Set watch timer interrupt to 3 91 ms Figure 13 1 Watch Timer Control Register WTCON 13 2 ELECTRONICS 3C822B F822B C8289 F8289 C8285 F8285 WATCH TIMER CIRCUIT DIAGRAM WTCON 7 WTCON 6 WT INT Enable WTCON 5 WTCON 4 WTCON 3 WTCON 2 WTCON 1 WTCON 0 Pending Bit Enable Disable Frequency Dividing Circuit Clock Selector 32 768 kHz WTCON 6 WTINT fw 64 0 5 gt ed IRQ5 fw 32 1 kHz fw 16 2 kHz fw 8 4 kHz S
152. apter 6 Instruction Set tci in e eua tas kutmu eoe ede ede 6 1 Data CEPR 6 1 Fiegister AGGne Sin iss scence cats nr n stan cee cas dds 6 1 Addressing MOdes eae aed de alate 6 1 Flags Register FLAGS uu tee a et Pl ed he Ero lo ny ee Ae 6 6 Flag Descriptloris eed eae rece eue 6 7 Instruction Set Notations 6 8 Condition Codes Aol peer d exuti ded he p 6 12 Instruction Descriptions dee 6 13 vi S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER Table of Contents continued Part Il Hardware Descriptions Chapter 7 Clock Circuit OVGIVIQW iei 7 1 System Clock 2 a uA 7 1 Main Oscillator CCU S u 62 1 e ener eere Re Ge eerte rettet 7 2 Sub Oscillator GIICUlIs 3 5 it nii Eae nd icm ED tl dee etaed ree Sie dece 7 2 Clock Status During Power Down 7 3 System Clock Control Register 7 4 Oscillator Control Register OSCCON cccecccceseeeeeeeeeeeeeeeeeeeeeceeeeeeeeeeeaeeeeaeceeeeeeeeeeeeeeeeeeeeeeneeess 7 5 Switching the GRU CIoGK i das ee OR Eee trei herede Be tee
153. are affected Format Bytes Cycles Opcode Addr Mode Hex dst src Examples Given R6 10H R7 33H R8 12H program memory location 1033H OCDH and external data memory location 1033H ODDH LDCD R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is decremented by R8 OCDH R6 10H R7 32H RR6 lt RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt 6 1 R8 ODDH R6 10H R7 32H 6 54 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples and dst src dst src m rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src TL Irr Given R6 10H R7 33H R8 12H program memory locations 1033H 1034H external data memor
154. arison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET 3C828B F828B C8289 F8289 C8285 F8285 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example 6 32 dst src RA Ifdst src 0 PC RA Ir lt Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src ope 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 and register 03H 04H CPIJNER1 R2 SKIP gt R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because th
155. ata Register P2CONH L Assign Pins to ADC Input O AVREF Conversion Result ADDATAH L 10 bit D A Converter AVss F4H F5H Set 1 Bank 0 Figure 15 3 A D Converter Functional Block Diagram 15 4 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 A D CONVERTER VDD Reference Voltage Input AVREF lt VDD AVREF Analog Input Pin ADORADI S3C828B 9 5 AVss Figure 15 4 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS 15 5 A D CONVERTER 53 828 828 8289 8289 8285 8285 5 15 6 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 SERIAL I O INTERFACE SERIAL I O INTERFACE OVERVIEW Serial I O module SIO can interface with various types of external device that require serial data transfer The components of each SIO function block are 8 bit control register SIOCON Clock selector logic 8 bit data buffer SIODATA 8 bit pre scaler SIOPS 3 bit serial clock counter Serial data I O pins SI SO External clock input output pins SCK The SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO modules follow these basic steps 1 Configure the I O pins at port SO SCK SI by loading the appropriate value t
156. atchdog functions system reset Two 8 bit timer counter and two 16 bit timer counter with selectable operating modes Watch timer for real time LCD Controller driver converter with 8 selectable input pins Synchronous SIO modules The 53 828 828 8289 8289 8285 8285 is versatile microcontroller for camera LCD and ADC application etc They are currently available in 80 pin TQFP and 80 pin QFP package The S3F828B F8289 F8285 are FLASH version of the S3C828B C8289 C8285 microcontroller The S3F828B microcontroller has an on chip FLASH ROM instead of a masked ROM The S3F828B F8289 F 8285 is comparable to the S3C828B C8289 C8285 both in function and in pin configuration The S3F828B only is a full flash The full flash means that data can be written into the program ROM by an instruction ELECTRONICS PRODUCT OVERVIEW FEATURES CPU e SAM88 RC CPU core Memory Program Memory ROM 64K x 8 bits program memory S3C828B F828B 32K x 8 bits program memory 53 8289 8289 16K x 8 bits program memory S3C8285 F 8285 Internal flash memory program memory N Sector size 128 bytes V 10 years data retention V Fast programming time chip erase 50ms sector erase 10ms byte program 30us User programmable by LDC instruction Y Endurance 10 000 erase program cycles Y Sector 128 bytes erase available Y Byte programmable Y External serial programming support Y E
157. ber only 0 15 Rn or reg reg 0 255 n 0 15 RRp p 0 2 14 RRp or reg reg 0 254 even only where p 0 2 14 reg Rn reg 0 255 n 0 15 addr RRp addr range 128 to 127 where p 0 2 14 addr RRp addr range 0 65535 where p 0 2 14 addr addr range 0 65535 addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction data data 0 255 data data range 0 65535 6 9 INSTRUCTION SET DEC R1 RLC R1 INC R1 JP IRR1 DA R POP R1 COM R PUSH R2 DECW RR1 R1 INCW RR1 CLR R1 RRC R1 SRA R1 RR R1 SWAP R1 gt m 53 828 828 8289 8289 8285 8285 Table 6 5 Opcode Quick Reference OPCODE MAP LOWER NIBBLE HEX DEC ADD ADD ADD ADD 1 r1 r2 r1 lr2 R2 R1 IR2 R1 RLC ADC ADC ADC ADC 1 r1 r2 r1 lr2 R2 R1 IR2 R1 INC SUB SUB SUB SUB 1 r1 r2 r1 lr2 R2 R1 IR2 R1 SRP 0 1 SBC SBC SBC SBC IM r1 r2 r1 lr2 R2 R1 IR2 R1 DA OR OR OR OR 1 r1 r2 r1 lr2 R2 R1 IR2 R1 POP AND AND AND AND IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 COM TCM TCM TCM TCM 1 r1 r2 r1 lr2 R2 R1 IR2 R1 PUSH IR2 r1 r2 r1 lr2 R2 R1 IR2 R1 DECW PUSHUD PUSHUI MULT MULT 1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 RL POPUD POPUI DIV DIV 1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 INCW
158. bles CPU Control Instructions CCF Complement carry flag Disable interrupts El Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SBO Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRP0 SIC Set register pointer 0 SRP1 SIC Set register pointer 1 STOP Enter Stop mode ELECTRONICS 6 5 INSTRUCTION SET 3C828B F828B C8289 F8289 C8285 F8285 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions two others FLAGS 3 FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 R W
159. both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set ifthe result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 52 r r 53 r Ir src dst 3 6 54 R R 55 R IR dst src 3 6 56 R IM Given R1 12H R2 registerO1H 21H register 02H register AND R1 R2 E R1 02H R2 03H AND R1 R2 gt R1 02H R2 03H AND 01H 02H gt Register 01H 01H register 02H 03H AND 01H 02H gt Register 01H register 02H 03H gt AND 01H 25H Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst O lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the des
160. by falling edge KEE Enable interrupt by rising edge Enable interrupt by both falling and rising edge 3 2 P0 5 External interrupt INT5 Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge 1 0 0 4 interrupt INT4 Enable Bits fo fo Disable interrupt 0 1 Enable interrupt by falling edge 0 1 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge 4 22 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER POINTL Port o Interrupt Control Register Low Byte ESH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 PO 3 External interrupt INT3 Enable Bits lolo Disable interrupt 1011 Enable interrupt by falling edge 1110 Enable interrupt by rising edge Enable interrupt by both falling and rising edge 5 4 PO 2 External interrupt INT2 Enable Bits o o 1 enabeinterupt byfaling edge U y 0 Enabeinterupr by sing edge 3 2 P0 1 External interrupt INT1 Enable Bits 0 0 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge 1 0 PO 0 External interrupt INTO Enable Bits 0 Disable inte
161. c one Figure 4 1 4 4 Register Description Format ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER ADCON A D Converter Control Register F3H Set 1 Bank 0 Bit Identifier p xe a a 2 j ac j el RESET Value _ 0 0 0 0 0 0 0 Read Write R W R W R W R R W R W R W Addressing Mode ELECTRONICS Register addressing mode only Not used for the S8C828B C8289 C8285 A D Input Pin Selection Bits End of Conversion Bit Read only EN Conversion not complete Conversion complete Clock Source Selection Bits o Start or Enable EN Disable operation Start operation 4 5 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 BLDCON Battery Level Detector Control Register D2H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 Read Write R W R R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3C828B C8289 C8285 5 Vin Source Bit Internal source 0 External source 4 BLD Output Bit Read only 0 Vin gt Vggr when BLD is enabled Vin lt Ver when BLD is enabled 3 BLD Enable Disable Bit 0 Disable BLD Enable BLD 2 0 Detection Voltage Selection Bits 0 0 Vgp 22V 4 6 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER BTCON Basic Timer Control Register D3H Set 1 Bit Identifier gt 5 4 3 2 a o R
162. cantas Zoro Tag Z status flag FIS Sign flag S Half carry flag H Overflow V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET FLAG DESCRIPTIONS FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute co
163. cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 02 r r 03 r Ir SIC dst 3 6 04 R R 05 R IR opc dst src 3 6 06 R IM Given R1 12H R2 register 01H 21H register 02H register OAH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 03H ADD 01H 02H gt Register 01H 24H register 02H gt gt ADD 01H 02H Register 01H 2BH register 02H ADD 01H 25H Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains The statement ADD R1 R2 adds to 12H leaving the value 15H in register R1 ELECTRONICS 6 15 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 AND Logical AND AND Operation Flags Format Examples OAH 6 16 dst src dst lt dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are
164. cted Bytes Cycles dst 2 Given R1 and register 03H DEC R1 gt R1 02H DEC R gt Register 03H OFH INSTRUCTION SET Opcode Addr Mode Hex dst 00 R 01 IR In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register by one leaving the value OFH ELECTRONICS INSTRUCTION SET 53 828 828 8289 8289 8285 8285 D ECW Decrement Word DECW Operation Flags Format Examples 21H NOTE 6 36 dst dst lt 051 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 80 RR 8 81 IR Given RO 12H R1 34H R2 register 30H OFH and register 31H DECW RRO gt RO 12H R1 33H DECW R2 Register 30H OFH register31H 20H In the first example destination register RO contains the value 12H and register R1 the value 34H The statement DECW RRO a
165. d Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 40 R 41 IR ELECTRONICS 6 33 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 DA Decimal Adjust DA Example 6 34 Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD RIRO I C lt 0 H 0 Bits 4 7 3 bits 0 3 C R1 lt DA R1 I R1 lt 3CH 06 If addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H R0 C lt 0 H lt 0 Bits 4 7 3 bits 0 3 1 DA QR QR1 lt 31 0 leave the value 31 BCD in address 27H R1 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 DEC Decrement DEC Operation Flags Format Examples dst dst lt 051 1 The contents of the destination operand are decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffe
166. ddress F8H Mode 1 and 3 baud rate fxx 16 x BRDATA 1 17 4 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 UART Table 17 1 Commonly Used Baud Rates Generated by BRDATA Mode Baud Rate Oscillation Clock BRDATA Decimal Hexdecimal Mode 2 0 5 MHz 8 MHz 230 400 Hz 115 200 Hz 57 600 Hz 38 400 Hz 19 200 Hz 3 23H 9 600 Hz 47H 02 0 7 4 800 Hz 11 0592 MHz 143 8FH 62 500 Hz 10 MHz 09 09H 64 9 x 02H 05H 0BH 11H k 5 5 1 9 615 Hz 10 MHz 40H 38 461 Hz 8 MHz 0CH ELECTRONICS 17 5 UART 53 828 828 8289 8289 8285 8285 BLOCK DIAGRAM SAM8 Internal Data Bus zz UARTDATA viii u Baud Rate Be Generator Zero Detector Write to Shift UDATA Start Tx Control EN Pod Tx Clock TIP Send 7 TxD P3 4 lt E Shift _ L uc RxD P3 5 Interrupt RIE gt Rx Clock RIP Receive E i Rx Control Start Shift 1 to 0 y Transition D gt Detector Bit Detector Value L MS1 Shift Register UARTDATA RxD P3 5 SAM8 Internal Data Bus Figure 17 5 UART Functional Block Diagram ELECTRONICS 17 6 3C828B F828B C8289 F8289 C8285 F8285 UART UART MODE 0 FUNCTION DESCRIP
167. ddresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example DI state SYM 0 lt 0 Bit zero of the system mode control register SYM 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex opc 1 4 8F Given SYM 01H DI Ifthe value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure ELECTRONICS 6 37 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 DIV Divide Unsigned DIV dst src Operation dst src dst UPPER REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored
168. e TB828B 9 5 target board is used for the S3C828B F828B C8289 F8289 C8285 F8285 microcontroller It is supported with the SMDS2 TB828B 9 5 To User_Vcc on RESET Idle Stop ORO 208 QFP S3E8280 EVA Chip 100 Pin Connector 50 Pin Connector 50 Pin Connector Smart Option Source Device Solution External S3F8285 S3F8285 Internal S3F828B S3F8289 JP8 JP6 JP7 smps2 O o o us Smart Option Selection Figure 23 2 TB828B 9 5 Target Board Configuration ELECTRONICS 23 3 DEVELOPMENT TOOLS 53 828 828 8289 8289 8285 8285 Table 23 1 Power Selection Settings for TB828B 9 5 User Vcc Operating Mode Comments Settings The SMDS2 SMDS2 To User Vcc Mera supplies Voc to the target Off fee On TB8285 Vcc Bn board evaluation chip and I Vss the target system bra SMDS2 SMDS2 The SMDS2 SMDS2 To User Vcc He External T supplies Vcc only to the target Off ES On TB8285 Vcc 1 board evaluation chip lt Vss gt The target system must have its own power supply SMDS2 SMDS2 NOTE The following symbol in the To User_Vcc Setting column indicates the electrical short off configuration Table 23 2 Main clock Selection Settings for TB828B 9 5 Main Clock Settings Operating Mode Comments Set the XI switch to MDS piste when the target board is connected to the SMDS2 SMDS2 XOUT XIN L N
169. e o RESET Value _ 0 0 0 0 0 0 0 Read Write _ R W R W R W R W R W R W R W Addressing Mode Register addressing mode only Not used for the S3C828B C8289 C8285 P1 6 Pull up Resistor Enable Bit Pull up disable B Pull up enable P1 5 Pull up Resistor Enable Bit Pull up disable Pull up enable P1 4 Pull up Resistor Enable Bit Pull up disable Pull up enable P1 3 Pull up Resistor Enable Bit Pull up disable lel Pull up enable P1 2 Pull up Resistor Enable Bit 0 1 Pull up disable Pull up enable P1 1 Pull up Resistor Enable Bit Pull up disable Pull up enable P1 0 Pull up Resistor Enable Bit Pull up disable lel Pull up enable NOTE A pull up resistor of port 1 is automatically disabled only when the corresponding pin is selected as push pull output or alternative function ELECTRONICS N NI CONTROL REGISTERS S3C828B F828B C8289 F8289 C8285 F8285 P2CONH Port 2 Control Register High Byte E8H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7 AD7 V 5 DREF 5 4 P2 6 AD6 0 0 Input mode 0 1 Input mode pull up 0 0 Input mode Input mode pull up 0 O Input mode 0 1 Input mode pull up KEE Output mode push pull Alternative function AD4 4 28 ELECTRONICS 3C828B F828B C8289 F8289 C82
170. e original instruction Figure 2 17 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address 10101011 Selects RPO or RP1 Address EEEO address These address bits indicate 8 bit working register addressing Register pointer Three low order bits provides five high order bits 8 bit physical address Figure 2 16 8 Bit Working Register Addressing ELECTRONICS 2 21 ADDRESS SPACES 53 828 828 8289 8289 8285 8285 Selects RP1 R11 8 bit address Register 110011 011 form instruction 10101 011 address LD R11 R2 OABH Specifies working register addressing Figure 2 17 8 Bit Working Register Addressing Example 2 22 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 ADDRESS SPACES SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP
171. e result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET DA Decimal Adjust DA Operation Instruction ADD ADC SUB SBC Flags Format dst dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 06 0 0 0 9 1 0 3 06 0 0 0 0 9 60 1 0 9 0 A F 66 1 0 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 0 0 8 1 6 06 0 1 7 F 0 0 9 A0 60 1 1 6 1 6 9A 66 1 Set if there was a carry from the most significant bit cleared otherwise see table Z Set if result is 0 cleared otherwise S Set if result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffecte
172. e seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces working register slice is 8 bytes eight 8 bit working registers R0 R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers RO R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area in set 1 COH CFH Slice 32 Slice 31 11111XXX RP1 Registers R8 R15 Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Slice 2 Slice 1 Figure 2 8 8 Byte Working Register Ar
173. e timer 1 can generate two interrupts the timer 1 overflow interrupt T1OVF and the timer 1 match capture interrupt T3OVF is belongs to interrupt level IRQ3 vector E6H T1INT also belongs to interrupt level IRQ3 but is assigned the separate vector address E4H A timer 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a 0 to the INTPND 2 interrupt pending bit However the timer 1 match capture interrupt pending condition must be cleared by the application s interrupt service routine by writing a 0 to the INTPND 3 interrupt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 1 reference data register TIDATAH T1DATAL The match signal generates a timer 1 match interrupt vector E4H and clears the counter If for example you write the value 1087H to TTIDATAH T1DATAL the counter will increment until it reaches 1087 At this point the timer 1 interrupt request is generated the counter value is reset and counting resumes With each match the level of the signal at the timer 1 output pin is inverted see Figure 12 4 Capture Signal Interrupt Enable Disable CI T1CON 1 ear 16 Bit Up Counter lt T1INT INTPND 3 16 Bit Comparator INTPND3 Match IN
174. eading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin see Figure 11 4 Interrupt Enable Disable TAOVF IRQO Overflow INT CLK 8 Bit Up Counter TAINT IRQO TACAP input INTPND 1 Capture INT P3 3 Match Signal Pending TACON 4 3 TACON 4 3 Timer A Data Register Figure 11 4 Simplified Timer A Function Diagram Capture Mode ELECTRONICS 11 5 8 S3C828B F828B C8289 F8289 C8285 F8285 BLOCK DIAGRAM 0 TACON 7 5 INTPND O fxx 256 _ 64 Clear 8 8 bit Up Counter bx U Read Only P 8 bit Comparator Timer A Buffer Register Match Signal TACON Data Bus Figure 11 5 Timer A Functional Block Diagram 11 6 ELECTRONICS 53 828 828 8289 8289 8285 8285 8 BIT 8 BIT OVERVIEW The S3C828B F828B C8289 F8289 C8285 F8285 micro controller has an 8 bit counter called timer B Timer B which can be used to generate the carrier frequency of a remote controller signal Pending condition of timer B is cleared automatically by hardware Timer B has two functions As anormal interval timer generating a timer B interrupt at programmed time intervals To supply a clock sou
175. eas Slices ELECTRONICS 2 13 ADDRESS SPACES 53 828 828 8289 8289 8285 8285 USING THE REGISTER POINTS Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset they point to the working register common area RPO points to addresses COH C7H and points to addresses C8H CFH To change register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 9 and 2 10 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 9 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 10 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the
176. ected RP points to start of working register block Register Pair 16 Bit address added to offset p Program Memory Data Memory lt 16 Bits Value used in Instruction OPERAND 16 Bits The values in the program address RR2 04H are loaded into register R4 Identical operation to LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 ELECTRONICS 53 828 828 8289 8289 8285 8285 ADDRESSING MODES INDEXED ADDRESSING MODE Concluded Register File MSB Points to RPO or RPO or RP1 Selected RP points Program Memory to start of working OFFSET register block OFFSET NEXT 2 Bits Register Register Address OPCODE Point to Working Pair fo 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits 16 Bits Instruction OPERAND Value used in Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES 3C828B F828B C8289 F8289 C8285 F8285 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the ope
177. ection 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET Mnemonic Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI Operands dst dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst dst src dst src src dst src dst src S3C828B F828B C8289 F8289 C8285 F8285 Table 6 1 Instruction Group Summary Instruction Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre decrement Load program memory with pre decrement Load external data memory with pre increment Load program memory with pre increment Load word Pop from stack Pop user stack decrementing Pop user stack incrementing Push to stack Push user stack decrementing Push user stack incrementing ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC ds
178. ecute the STOP instruction You must set this STPCON register as 10100101b Otherwise the STOP instruction will not execute as well as reset will be generated 4 46 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER SYM System Mode Register DEH Set 1 Bit Identifier 7 5 4 3 2 a o RESET Value 0 x x x 0 0 Read Write R W R W R W R W R W R W Addressing Mode 4 2 NOTES 1 2 3 Register addressing mode only Not used But you must keep 0 Not used for the S3C828B C8289 C8285 Fast Interrupt Level Selection Bits 1 Fast Interrupt Enable Bit 2 0 Disable fast interrupt processing Global Interrupt Enable Bit 9 EN Disable all interrupt processing all interrupt processing Enable You can select only one interrupt level at a time for fast interrupt processing Setting SYM 1 to 1 enables fast interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 Following a reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to 5 0 ELECTRONICS CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 Timer 0 Control Register E3H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 0 Input Clock Selection Bits TBOF fxx 256 fxx 64 fxx
179. ed TOSONO Bytes Cycles Opcode Addr Mode Hex dst src ope esibio src 3 6 17 rO Rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H R1 01H 1 gt R1 O7H registerO1H 01H If destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET BITC Bit Complement BITC Operation Flags Format Example dst b dst b lt NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected IOZONO Bytes Cycles Opcode Addr Mode Hex dst NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC gt RI OSH If working register R1 contains the v
180. ed architecture Selectable CPU clock sources Idle and Stop power down mode release by interrupt Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER The S3C828B F828B C8289 F 8289 C8285 F8285 single chip CMOS microcontroller are fabricated using the highly advanced CMOS process based on Samsung s newest CPU architecture The S3C828B 53 8289 53 8285 are microcontroller with a 64K byte 32K byte 16K byte mask programmable ROM embedded respectively The S3F828B is a microcontroller with a 64K byte Flash ROM embedded The S3F8289 is a microcontroller with a 32K byte Flash ROM embedded The S3F8285 is a microcontroller with a 16K byte Flash ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the S3C828B F828B C8289 F8289 C8285 F8285 by integrating the following peripheral modules with the powerful SAMB core FLASH Nine programmable I O ports including six 8 bit ports and one 7 bit port one 6 bit port one 4 bit port for a total of 65 pins Eight bit programmable pins for external interrupts One 8 bit basic timer for oscillation stabilization and w
181. edges Schmitt trigger input with interrupt generation on rising signal edges Schmitt trigger input with interrupt generation on falling rising signal edges Port 0 Interrupt Enable and Pending Registers POINTH POINTL To process external interrupts at the port 0 pins the additional control registers are provided the port 0 interrupt enable register POINTH high byte E2H set 1 bank 1 POINTL Low byte set1 bank1 and the port 0 interrupt pending register POPND E4H set 1 bank 1 The port 0 interrupt pending register POPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the POPND register at regular intervals When the interrupt enable bit of any port 0 pin is 1 a rising or falling signal edge at that pin will generate interrupt request The corresponding POPND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application Software must the clear the pending condition by writing a 0 to the corresponding POPND bit ELECTRONICS 9 3 5 S3C828B F828B C8289 F8289 C8285 F8285 Port 0 Control Register High Byte POCONH EOH Set 1 Bank 1 R W INT7 INT6 INT5 POCONH bit pair pin configuration settings 00 Schmitt tri
182. efined 0 0 11 gt gt 0 gt gt ENEN 1 gt gt o cC gt gt B 1 0 1 gt gt 1 1 0 IA gt gt B 1 Group priority undefined Interrupt Subgroup C Priority Control Bit o 6 gt IRQ7 1 7 gt IRQ6 Interrupt Group C Priority Control Bit 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Interrupt Subgroup B Priority Control Bit 0 IRQ3 gt IRQ4 IRQ4 gt RQ3 Interrupt Group B Priority Control Bit 0 IRQ2 gt IRQ4 IRQ4 gt IRQ2 Interrupt Group A Priority Control Bit o gt IRQ1 1 IRQ gt IRQO NOTE Interrupt group A IRQO IRQ1 Interrupt group B IRQ2 IRQ3 IRQ4 Interrupt group C IRQ5 IRQ6 IRQ7 4 16 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER IRQ Interrupt Request Register DCH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R Addressing Mode Register addressing mode only 7 Level 7 IRQ7 Request Pending Bit External Interrupts 0 4 0 7 Not pending Pending 6 Level 6 IRQ6 Request Pending Bit External Interrupts 0 0 0 3 Not pending Pending 5 Lev 15 IRQ5 Request Pending Bit UART Transmit UART Receive Watch Timer Not pending 1 Pending 4 Level 4 IRQ4 Request Pending Bit SIO Not pending 1 Pending 3 Level 3 IRQ3 Request Pending Bit Timer 1 Match Capture or Overflow 0 Not pendi
183. elector fx Main clock where fx 4 19 MHz Sub clock 32 768 kHz fxr fx 128 fw Watch timer frequency WATCH TIMER BUZ 1 Hz fLCD 1024 Hz fBLD 4096 Hz Figure 13 2 Watch Timer Circuit Diagram ELECTRONICS 13 3 WATCH S3C822B F822B C8289 F8289 C8285 F8285 NOTES 13 4 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The S3C828B F828B C8289 F8289 C8285 F8285 microcontroller can directly drive an up to 256 dot 32 segments x 8 commons LCD panel Its LCD block has the following components LCD controller driver Display RAM for storing display data 6 common segment output pins 2 5 0 7 5 5 32 segment output pins SEG6 SEG37 2 common output pins COMO COM 1 Four LCD operating power supply pins Vi LCD bias by internal external register The LCD control register LCON is used to turn the LCD display on and off switch the current to the dividing resistors for the LCD display and frame frequency Data written to the LCD display RAM can be automatically transferred to the segment signal pins without any program control When a subsystem clock is selected as the LCD clock source the LCD display is enabled even in the main clock stop or idle mode VLCO VLC3 R 5 LCD COM0 COM1 Controller Driver 2 COM2 COM7 d SEGO SEG5 SEG6 SEG37
184. en Match Signal data gt counter E T1CON 2 Lower level when T1OVF data counter INTPND 3 Pending Timer 1 Data Register Figure 12 5 Simplified Timer 1 Function Diagram PWM Mode ELECTRONICS 12 7 16 BIT 0 1 53 828 828 8289 8289 8285 8285 Capture Mode In capture mode a signal edge that is detected at the T1CAP pin opens a gate and loads the current counter value into the timer 1 data register You can select rising or falling edges to trigger this operation Timer 1 also gives you capture input source the signal edge at the T1CAP pin You select the capture input by setting the values of the timer 1 capture input selection bits in the port 1 control register PI CONH 1 0 set 1 bank 1 E6H When P1CONH 1 0 is 00 the T1CAP input is selected Both kinds of timer 1 interrupts can be used in capture mode the timer 1 overflow interrupt is generated whenever a counter overflow occurs the timer 1 match capture interrupt is generated whenever the counter value is loaded into the timer 1 data register By reading the captured data value in TIDATAH T1DATAL and assuming a specific value for the timer 1 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAP pin see Figure 12 6 T1CON 0 T1OVF IRQ3 16 Bit Up Counter INTPND 2 Overflow INT Interrupt Enable Disable T1CON 1 T1INT IRQ3
185. er ELECTRONICS 6 67 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 PUSHUI Push User Stack Incrementing PUSHUI Operation Flags Format Example 6 68 dst src lt IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst sre opc dst src 3 8 83 IR R Given Register OOH register 01H 05H register 04H 2AH PUSHUI 00H 01H gt RegisterOOH register 01H O5H register 04H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET RCF Reset Carry Flag RCF Operation Flags Format Example RCF 0 The carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 CF Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 69 INSTRU
186. er Symbol Conditions Min Typ Max Unit Programming Time 1 Chip Erasing Time 2 Sector Erasing Time 3 NOTES 1 Programming time is the time during which one byte 8 bit is programmed 2 The Chip Erasing time is the time during which all 64K byte block is erased 3 Sector Erasing time is the time during which all 128 byte block is erased 4 Chip Erasing is available in Tool Program Mode only ELECTRONICS 20 15 ELECTRICAL DATA S3C828B F828B C8289 F8289 C8285 F8285 NOTES 20 16 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 2 1 MECHANICAL DATA MECHANICAL DATA 5 030 OVERVIEW The S3C828B F828B C8289 F8289 C8285 F8285 microcontroller is currently available in 80 pin QFP TQFP package 23 90 0 30 80 QFP 1420C 80 Y 0 80 0 20 NOTE Dimensions are in millimeters Figure 21 1 Package Dimensions 80 QFP 1420C ELECTRONICS 0 80 0 20 0 05 2 65 0 10 3 00 MAX MECHANICAL DATA 53 828 828 8289 8289 8285 8285 14 00 BSC EI 0 09 0 20 80 1212 O O N m e e S N 0 60 70 15 1 20 MAX NOTE Dimensions are in millimeters Figure 21 2 Package Dimensions 80 TQFP 1212 21 2 ELECTRONICS 53 828 828 8289 8289 8285 8285 S3F828B F8289 F8285 FLASH MCU S3F828B F8289 F8285 FLAS
187. erface Four programmable operating modes 8 bit Serial Interface 8 bit transmit receive mode 8 bit receive mode LSB first or MSB first transmission selectable Internal or External clock source ELECTRONICS 53 828 828 8289 8289 8285 8285 FEATURES Continued Battery Level Detector 3 creteria voltage selectable 2 2V 2 4V 2 8V En Disable by software for current consumption Low Voltage Reset LVR Criteria voltage 2 2V En Disable by smart option ROM address Two Power Down Modes only CPU clock stops Stop selected system clock and CPU clock stop Oscillation Sources Crystal ceramic or RC for main clock Main clock frequency 0 4 MHz 11 1MHz 32 768 kHz crystal oscillation circuit for sub clock Instruction Execution Times 360 5 at 11 1 MHz fx minimum Operating Voltage Range 20V to 3 6 V at 0 4 4 2MHz e 2 7 V to 3 6 V at 0 4 10 0MHz 3 0 Vto 3 6 V at 0 4 11 1MHz Operating Temperature Range e 25 C to 85 C Package Type e 80 0 1420 80 TQFP 1212 Smart Option Low Voltage Reset LVR level and enable disable are at your hardwired option ROM address 3FH ISP related option selectable ROM address 3EH ELECTRONICS PRODUCT OVERVIEW PRODUCT OVERVIEW S3C828B F828B C8289 F8289 C8285 F8285 BLOCK DIAGRAM TAOUT TAPWM P3 1 lt a pit Timer TACLK P3 2 Counter A TACA
188. eries microcontrollers The SASM88 takes a source file containing assembly language statements and translates into a corresponding source code object code and comments The SASM88 supports macros and conditional assembly It runs on the MS DOS operating system It produces the relocatable object code only so the user should link object file Object files can be linked with other object files and loaded into memory HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler ROM code must be needed to fabricate a microcontroller which has a mask ROM When generating the ROM code file by HEX2ROM the value FF is filled into the unused ROM area up to the maximum ROM size of the target device automatically TARGET BOARDS Target boards are available for all S3C8 series microcontrollers All required target system cables and adapters are included with the device specific target board ELECTRONICS 23 1 DEVELOPMENT TOOLS 53 828 828 8289 8289 8285 8285 IBM PC or Compatible RS 232C SMDS2 Target lt gt PROM OTP Writer Unit Application System A lt gt RAM Break Display Unit lt gt Trace Timer Unit TB828B 9 5 SAM8 Base Unit Target Board EVA gt Power Supply Unit Chip Figure 23 1 SMDS Product Configuration SMDS2 23 2 ELECTRONICS 53 828 828 8289 8289 8285 8285 DEVELOPMENT TOOLS TB828B 9 5 TARGET BOARD Th
189. ernally to Vas to reduce current leakage Using nRESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock fxx 16 because CLKCON 3 and CLKCON 4 are cleared to 00B After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3C828B F828B C8289 F8289 C8285 F8285 interrupt structure that can be used to release Stop mode are External interrupts PO 0 PO0 7 INTO INT7 Please note the following conditions for Stop mode release If you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged except STPCON register Ifyou use an internal or external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the ap
190. errupt WFI Operation Flags Format Example 6 86 The CPU is effectively halted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex opc 1 4n 3F n 1 2 3 The following sample program structure shows the sequence of operations that follow a WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 XOR Logical Exclusive OR XOR Operation Flags Format Examples dst src dst lt dst src INSTRUCTION SET The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a O bit is stored Unaffected Always reset to 0 Unaffected Unaffected IO ONO Given RO 0C7H R1 02H and register 02H XOR RO R1 gt XOR RO R1 gt XOR 00H 01H gt XOR 00H 01H gt XOR OOH 54H gt src dst dst src 23H Set if the result is 0 cleared otherwise Set i
191. es of the register file locations COH FFH The upper 32 byte area of this 64 byte space EOH FFH is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 contains 68 mapped system and peripheral control registers The lower 32 byte area contains 16 system registers DOH DFH and a 16 byte common working register area COH CFH You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For the S3C828B the set 2 address range COH FFH is accessible on pages 0 9 3C8289 the set 2 address range COH FFH is accessible on pages 0 3 S3C8285 the set 2 address range COH FFH is accessible on pages 0 1 The logical division of set 1 and set 2 is
192. example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H 80H 81H ADC 80H 82H 80H lt 80H 82H C ADC 80H 83H 80H lt 80H 83H C ADC 80H 84H 80H lt 80H 84H C ADC 80H 85H 80H lt 80H 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles ELECTRONICS 2 15 ADDRESS SPACES 53 828 828 8289 8289 8285 8285 REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address
193. f arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 6 13 r Ir src dst 3 6 14 R R 6 15 R IR dst src 3 6 16 R IM Examples Given R1 10H R2 1 registerO1H 20H registerO2H and register 03H OAH ADC R1 R2 E Ri 14H R2 ADC R1 R2 gt Ri 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H ADC 01H 02H gt Register 01H 2BH register 02H ADC 01H 11H gt Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value The statement R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 6 14 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET ADD aaa ADD dst src Operation dst lt dst src Flags Format Examples The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed C Set if there is a carry from the most significant bit of the result
194. f how to use an ENTER statement Before Address IP 0050 Address Data 40 Enter PC 0040 43 SP 0022 22 Data Stack ELECTRONICS 41 Address H 42 Address L Address H 01 10 After Data Address Data 40 Enter 41 Address H 42 Address L 43 Address H 110 Routine IPL 50 Data Memory Stack 6 41 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 exit Operation IP lt SP SP lt SP 2 PC 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack Example The diagram below shows one example of how to use an EXIT statement Before After Address Data Address Data IP 0050 0052 Address Data Address Data 50 PCL old 60 Main 51 PCH SP 0022 SP 0022 140 Exit 20 IPH 1 00 21 IPL 50 22 Data 22 Data Memory Stack Stack 6 42 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET IDLE Operation IDLE Operation The IDLE instruction stops the CPU clock w
195. f the result bit 7 is set cleared otherwise 02H R2 RO OC5H RO OE4H Register 0 Register 00H Register 00H Bytes 2 29H 08H 7FH Cycles Opcode Hex B2 B3 B4 B5 6 B6 02H 02H register 02H register 01H 02H register 01H 02H register 02H Addr Mode dst src r r r Ir R R R IR R IM 23H 18H registerOOH 2BH register 01H In the first example if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result 0C5H in the destination register RO ELECTRONICS INSTRUCTION SET 53 828 828 8289 8289 8285 8285 5 6 88 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generated for the S3C828B F828B C8289 F8289 C8285 F8285 by an external crystal can range from 0 4 MHz to 11 1 MHz The maximum CPU clock frequency is 11 1 MHz The Xj and pins connect the external oscioollator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control regi
196. g as the data value is greater than gt the counter value One pulse width is equal to x 256 see Figure 11 3 0 Capture Signal Interrupt Enable Disable TAOVF IRQO TACON 1 8 Bit Up Counter lt lt INTPND O Overflow INT TAINT IRQO Match INTPND 1 8 Bit Comparator Pending TAPWM Output Timer A Buffer Register High level when Match Signal data gt counter A TACON 2 Lower level when TAOVF data lt counter Timer A Data Register Figure 11 3 Simplified Timer A Function Diagram PWM Mode 11 4 ELECTRONICS 53 828 828 8289 8289 8285 8285 8 BIT Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the timer A data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the values of the timer A capture input selection bits in the port control register PSCONL 7 6 set 1 bank 1 EBH When P3CONL 7 6 is 00 the TACAP input is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the timer A data register By r
197. gger input mode 01 Schmitt trigger input mode pull up 10 Output mode open drain 11 Output mode push pull Figure 9 1 Port 0 High Byte Control Register POCONH Port 0 Control Register Low Byte POCONL E1H Set 1 Bank 1 R W P0 3 P0 2 P0 0 INT3 INT2 INT1 INTO POCONL bit pair pin configuration settings 00 Schmitt trigger input mode 01 Schmitt trigger input mode pull up 10 Output mode open drain 11 Output mode push pull Figure 9 2 Port 0 Low Byte Control Register POCONL 9 4 ELECTRONICS 53 828 828 8289 8289 8285 8285 Port 0 Interrupt Control Register High Byte POINTH E2H Set 1 Bank 1 R W INT6 5 POINTH bit configuration settings Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge Figure 9 3 Port 0 High Byte Interrupt Control Register POINTH PORTS Port 0 Interrupt Control Register Low Byte POINTL E3H Set 1 Bank 1 R W To INT3 INT2 INT1 INTO POINTL bit configuration settings 00 Disable interrupt 01 Enable interrupt by falling edge 10 Enable interrupt by rising edge 11 Enable interrupt by both falling and rising edge Figure 9 4 Port 0 Low Byte Interrupt Control Register POINTL ELECTRONICS 9 5 5 S3C828B F828B C8289 F8289 C8285 F8285 Port 0 Interrupt Pending Register POPND Set 1
198. gister PB Port 5 Control Register High Byte P5CONH Po Port 4 Data Register P4 7 Port 5 Control Register Low Byte P5CONL Port 6 Control Register High Byte P6CONH Port 6 Control Register Low Byte P6CON 5 Dec D 230 E E 236 E E 243 249 250 F 251 F 252 F 253 254 Port 7 Control Register P7CON Port 8 Control Register P8CON 0H 1H 2H EOH E1H E2H E3H E4H E7H E8H E9H AH BH EH FH FOH F2H F5H F6H F7H F8H F9H AH BH CH H H FH L Flash Memory User Programming Enable FMUSR 255 F Register 8 4 S3C828B F828B C8289 F8289 C8285 F8285 RESET and POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts for more details see Figure 7 3 NOTE Do not use stop mode if you are using an external clock source because input must be restricted int
199. gister Addressing Mode General Purpose Register Register Addressing Mode 25H Page 15 Prime 38 Data Registers All addressing modes LCD Display Reigster ADDRESS SPACES FFH Page 3 Page 2 Page 1 FFH Page 0 Set 2 General Purpose EOH Data Registers Indirect Register Indexed Mode and Stack Operations 256 Bytes COH BFH Prime wp 192 Bytes Data Registers All Addressing Modes 00H Figure 2 4 Internal Register File Organization S3C8289 F8289 ELECTRONICS 2 7 ADDRESS SPACES 53 828 828 8289 8289 8285 8285 0 0 System and Set 2 Peripheral Control Registers General Purpose Register Addressing Mode Data Registers Indirect Register System Registers Indexed Mode and Register Addressing Mode Stack Operations General Purpose Register Register Addressing Mode Page 0 Prime Page 15 Data Registers 7 Data Registers All Addressing T All addressing modes M LCD Display Reigster Figure 2 5 Internal Register File Organization 53 8285 8285 Modes 2 8 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 ADDRESS SPACES REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 256 byte internal register file using an 8 bit data bus into as many as 16 separately addressable register pages Page addressing is con
200. gt LABEL W 1000H PC 1000H JP 00H gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement C LABEL replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 JR Jump Relative JR Operation Flags Format Example 6 48 cc dst If cc istrue PC lt PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst cc opc dst 2 6 ccB RA cc Oto F NOTE In the first byte of the two byte instruction format the condition code and the opcode are e
201. gt RegisterOOH OAH LD O0H 10H gt RegisterOOH 01H register 01H 10H LD 00H 02H gt RegisterOOH O1H registerO1H 02 register 02H 02H LD RO LOOP R1 gt RO OFFH R1 OAH LD LOOP RO R1 gt Register31H OAH RO O1H R1 OAH 6 50 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst bjo src 3 6 47 rO Rb opc dst 3 6 47 Rb rO NOTE In the second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and general register LDB R0 00H2 gt RO 07H register 05H LDB 00H 0 RO gt RO 06H register 04H In the first example destination working register RO contains the value 06H and the source general register the value 05H The statement LD 0 00 2 loads the bit two value of the register into bit zero of the RO register leaving the value 07H in register RO
202. he FLAGS FLAGS prime register The fast interrupt status bit in the FLAGS register is set The interrupt is serviced Qr mco Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register The fast interrupt status bit in FLAGS is cleared automatically Relationship to Interrupt Pending Bit Types As described previously there are two types of interrupt pending bits One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared by the application program s interrupt service routine You can select fast interrupt processing for interrupts with either type of pending condition clear function by hardware or by software Programming Guidelines Remember that the only way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing an El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends 5 18 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically des
203. he SP value is undetermined Because only internal memory space is implemented in the S8C828B C8289 C8285 the SPL must be initialized to an 8 bit value in the range 00H FFH The SPH register is not needed and can be used as general purpose register if necessary When the SPL register contains the only stack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose data register However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of OOH ELECTRONICS 2 23 ADDRESS SPACES PROGRAMMING TIP Standard Stack Operations Using PUSH and POP 53 828 828 8289 8289 8285 8285 The following example shows you how to perform stack operations in the internal register using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP 2 24 SPL ZOFFH PP RPO RP1 R3 R3 RP1 RPO PP SPL lt FFH Normally the SPL is set to OFFH by the initialization routine Stack address OFEH Stack address OFDH Stack address OFCH Stack address OFBH Tq pu PP RPO RP1 R3 R3 St
204. high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B ELECTRONICS 2 19 ADDRESS SPACES 53 828 828 8289 8289 8285 8285 Selects RPO or RP1 Address OPCODE 4 bit address Register pointer provides three provides five low order bits high order bits Together they create an 8 bit register address Figure 2 14 4 Bit Working Register Addressing Selects RPO R6 OPCODE Register Instructi 01110 110 address 6740 47 70 N HO 76H Figure 2 15 4 Bit Working Register Addressing Example 2 20 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 ADDRESS SPACES 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100 This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 16 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address the three low order bits of the complete address are provided by th
205. hile allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F ES Example The instruction IDLE stops the CPU clock but not the system clock ELECTRONICS 6 43 INSTRUCTION SET INC Increment INC Operation Flags Format Examples 6 44 dst dst lt dst 1 The contents of the destination operand are incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Hex dst opc 1 4 rE r OtoF dst 2 4 20 21 Given RO 1BH registerOOH OCH and register 1BH OFH INC RO gt RO 1CH INC OH gt RegisterOOH INC RO gt RO registerO1H 10H 53 828 828 8289 8289 8285 8285 Addr Mode dst r In the first example if destination working register R0 contains the value 1BH the statement ING RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register 00H assuming that it contains the value 0CH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from 0FH to 10H ELECTRONICS
206. iagram ee 1 4 1 2 3C828B F828B C8289 F8289 C8285 F8285 Pin Assignments 80 QFP 1420C 1 5 1 3 3C828B F828B C8289 F8289 C8285 F8285 Pin Assignments 80 TQFP 1212 1 6 1 4 Pin Gircuit Type Aiacis a a sie sven ee edv ete re Oe eV E eode 1 9 1 5 B ain oe pO IUE UR o eir 1 9 1 6 Piri Gircult Type Gv acess iode pe ER ere e e UP ER Ero e deep end 1 9 1 7 Pin Circuit Type D 1 P3 4 P3 5 etd tr erre erede 1 9 1 8 Pin Gircuit Type PO coat ete tte eee ee aa 1 10 1 9 Pin Circuit Type F 1 P2 0 P2 6 nnne 1 10 1 10 Pin Circuit Type F 2 P2 7 ero e eI tet ee DR RE E 2 1 11 1 11 Pin Gircuit Type Hed acted dette ee itn 1 11 1 12 Pini Circuit Type H 8 P4 aiu m rete edo dette ee 1 12 1 13 Pin Circuit Type H 9 P3 0 P3 3 P6 P7 P8 1 12 2 1 Program Memory Address 2 2 2 2 SMart ES 2 3 2 3 Internal Register File Organization S3C828B F828B 2 6 2 4 Internal Register File Organization 53 8289 8289 2 7 2 5 Internal Register File Organization S3C8285 F8285 2 8 2 6 Register Page Pointer BP ieu eren e pU qe el P petere 2 9 2 7 Set 1 Set 2 P
207. ic interrupt level for fast interrupt processing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 ELECTRONICS 5 17 INTERRUPT STRUCTURE 53 828 828 8289 8289 8285 8285 FAST INTERRUPT PROCESSING Continued Two other system registers support fast interrupt processing The instruction pointer IP contains the starting address of the service routine and is later used to swap the program counter values and When a fast interrupt occurs the contents of the FLAGS register is stored in an unmapped dedicated register called FLAGS FLAGS prime NOTE For the S3C828B F828B C8289 F8289 C8285 F8285 microcontroller the service routine for any one of the eight interrupt levels IRQ0 IRQ7 can be selected for fast interrupt processing Procedure for Initiating Fast Interrupts To initiate fast interrupt processing follow these steps 1 Load the start address of the service routine into the instruction pointer IP 2 Loadthe interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing the following events occur The contents of the instruction pointer and the PC are swapped The FLAG register values are written to t
208. ice to device The S3C828B C8289 C8285 interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3C828B C8289 C8285 uses eighteen vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the S3C828B C8289 C8285 interrupt structure there eighteen possible interrupt sources When service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used
209. igned to support the large register files that are typical of most SAM8 microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide No special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Section 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to S
210. imer A is an 8 bit general purpose timer counter Timer A has three operating modes one of which you select using the appropriate TACON setting Interval timer mode Toggle output at TAOUT pin Capture input mode with a rising or falling edge trigger at the TACAP pin PWM mode TAPWM Timer A has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 or 1 with multiplexer External clock input pin TACLK 8 bit counter TACNT 8 bit comparator and 8 bit reference data register TADATA I O pins for capture input or PWM or match output TAPWM TAOUT Timer A overflow interrupt IRQ0 vector DEH and match capture interrupt IRQ0 vector DCH generation Timer A control register TACON set 1 Bank 0 E8H read write ELECTRONICS 11 1 8 S3C828B F828B C8289 F8289 C8285 F8285 TIMER A CONTROL REGISTER TACON You use the timer A control register TACON to Select the timer A operating mode interval timer capture mode PWM mode Select the timer A input clock frequency Clear the timer A counter TACNT Enable the timer A overflow interrupt or timer A match capture interrupt Clear timer A match capture interrupt pending condition TACON is located in set 1 Bank 0 at address E8H and is read write addressable using Register addressing mode A reset clears TACON to 00H This sets timer A to normal interval timer mode selects an inp
211. in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers Flags Set ifthe V flag is set and quotient is between 28 and 29 41 cleared otherwise Z Set if divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Setifquotientis gt 28orifdivisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst sre opc src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 O3H R2 register40H 80H DV RRO R2 RO 03H R1 40H DV RRO R2 RO 03H R1 20H DV RRO 20H gt RO O3H R1 80H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 6 38 ELECTRONICS 3C828B F828B C8289 F828
212. ing mode only 7 6 P5 3 SEG29 Input mode Output mode N channel open drain Output mode push pull Alternative function SEG29 5 4 3 2 O 0 Input mode Output mode N channel open drain 0 Output mode push pull EN Alternative function SEG27 1 0 P5 0 SEG26 0 0 Input mode 1 Output mode N channel open drain Output mode push pull EREN Alternative function SEG26 4 36 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER P5PUR Port 5 Pull up Resistor Enable Register EFH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P5 7 Resistor Enable Bit 0 Pull up disable 1 Pull up enable 6 P5 6 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 5 P5 5 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 4 P5 4 Resistor Enable Bit Pull up disable Pull up enable 1 3 P5 3 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 2 P5 2 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 1 P5 1 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 0 P5 0 Pull up Resistor Enable Bit Pull up disable Pull up enable NOTE A pull up resistor of port 5 is automatically disabled only when the corresponding pin is selected as push pull ou
213. ingle programmer or GW PRO2 gang programmer The other modules except flash memory module are at a reset state This mode doesn t support the sector erase but chip erase all flash memory erased at a time and two protection modes Hard lock protection Read protection Table 19 1 Descriptions of Pins Used to Read Write the Flash in Tool Program mode Normal Chip During Programming Pin No lo Function O Serial data pin Output port when reading and input port when writing Can be assigned as an input or push pull output port 10 11 Serial clock pin Input only pin 16 8 9 14 Power supply pin for Flash ROM cell writing indicates that FLASH MCU enters into the writing mode When 12 5V is applied FLASH MCU is in writing mode and when 3 3V is applied FLASH MCU is in reading mode Option 17 nRESET nRESET Chip Initialization Power supply pin for logic circuit Vpp Should be tied to 3 3 V during programming NOTES 1 Parentheses indicate pin number for 80 TQFP 1212 package 2 Vpp Test pin had batter connect to Vpp S3F828B only USER PROGRAM MODE This mode supports sector erase byte programming byte read and one protection mode Hard lock protection The read protection mode is available only in Tool Program mode So in order to make a chip into read protection you need to select a read protection option when you program a initia
214. instruction will not be executed and reset will be generated Figure 7 10 STOP Control Register STPCON ELECTRONICS 7 5 CLOCK CIRCUIT 53 828 828 8289 8289 8285 8285 SWITCHING THE CPU CLOCK Data loading in the oscillator control register OSCCON determine whether a main or a sub clock is selected as the CPU clock and also how this frequency is to be divided by setting CLKCON This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies 5 0 select the main clock fx or the sub clock fxT for the CPU clock OSCCON 3 start or stop main clock oscillation and OSCCON 2 start or stop sub clock oscillation CLKCON 4 3 control the frequency divider circuit and divide the selected fxx clock by 1 2 8 16 For example you are using the default CPU clock normal operating mode and a main clock of fx 16 and you want to switch from the fx clock to a sub clock and to stop the main clock To do this you need to set CLKCON 4 8 to 11 OSCCON 0 to 1 and OSCCON 3 to 1 simultaneously This switches the clock from fx to fxr and stops main clock oscillation The following steps must be taken to switch from a sub clock to the main clock first set OSCCON 3 to 0 to enable main clock oscillation Then after a certain number of machine cycles has elapsed select the main clock by setting OSCCON O to 0 8 PROGRAMMING Switching the CPU c
215. interrupt can occur and the IP is still correct at 100H 0H FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET JP Jump JP JP Operation Flags Format 1 Examples cc dst Conditional dst Unconditional If cc istrue PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the No flags are affected Bytes Cycles Opcode Addr Mode 2 dst cc dst 3 8 ccD DA cc 0to F dst 2 8 30 IRR NOTES 1 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Given The carry flag 1 register 00 01H andregister 01 20H JP C LABEL W
216. interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W IR IRQ1 IRQ2 RQ3 IRQ5 IRQ6 IRQ7 Interrupt level enable 0 Disable mask interrupt level 1 Enable un mask interrupt level NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 11 INTERRUPT STRUCTURE 53 828 828 8289 8289 8285 8285 INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized i
217. isable overflow interrupt 1 Enable overflow interrupt NOTE The T1CON 2 value is automatically cleared to 0 after being cleared counter ELECTRONICS 4 4 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 Timer Control Register E8H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer A Input Clock Selection Bits 0 fxx 1024 RH fxx 256 fo 1 o ofai fxx 8 fxx system clock External clock TACLK falling edge External clock TACLK rising edge Counter stop O Oo J J of ofa Capture mode capture on rising edge counter running OVF can occur Capture mode capture on falling edge counter running OVF can occur PWM mode OVF interrupt can occur 2 Timer Overflow Interrupt Enable Bit 0 No effect 1 Clear the timer A counter when write 1 Timer A Match Capture Interrupt Enable Bit EN Disable interrupt Enable interrupt 0 Timer A Overflow Interrupt Enable Bit EN Disable overflow interrupt Enable overflow interrupt NOTE The TACON 2 value is automatically cleared to 0 after being cleared the counter 4 50 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER TBCON Timer B Control Register F2H Set 1 Bit Identifier 2 a 1 e Ja RESET Value 0 0 0 0 0 0 0 0 Read W
218. ister 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing to Program or Data 3 9 3 10 Direct Addressing for Load Instructions 3 10 3 11 Direct Addressing for Call and Jump Instructions 2 3 11 3 12 Indirect Addressing det enter eoe deest dun 3 12 3 13 Relative Addressing om actor noce een 3 13 3 14 Immediate Addressing 1 edel inihi e aed 3 14 S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER xi List of Figures Continued Figure Title Page Number Number 4 1 Register Description Format 5 eres 4 4 5 1 S3C8 Series Interrupt Types uuu 5 2 5 2 S3C828B C8289 C8285 Interrupt Structure eene 5 4 5 3 ROM Vector Address 4 5 5 5 4 Interrupt Function 5 8 5 5 System Mode Register SYM nennen nennen enne 5 10 5 6 Interrupt Mask Register IMR essen nemen rene 5 11 5 7 Interrupt Request Priority 5 12 5 8 Interrupt Priority Register IPR sese 5 13 5 9 Interrupt Request Register 5 14 6 1 System Flags Register FLAGS
219. l your code to a chip by using Tool Program mode by using a programming tool The S3F828B has the pumping circuit internally therefore 12 5V into Vpp Test pin is not needed To program flash memory in this mode several control registers will be used There are four kind functions programming reading sector erase hard lock protection 19 2 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 EMBEDDED FLASH MEMORY INTERFACE FLASH MEMORY CONTROL REGISTERS USER PROGRAM MODE FLASH MEMORY CONTROL REGISTER FMCON register is available only in user program mode to select the Flash Memory operation mode sector erase byte programming and to make the flash memory into a hard lock protection Flash Memory Control Register FMCON D2H Set 1 Bank 1 R W Flash memory mode selection bits Not used 0101 Programming mode 1010 Sector erase mode Flash operation start bit 0110 Hard lock mode 0 Operation stop bit Others Not available 1 Operation start bit This bit will be cleared automatically just after the corresponding Sector erase status bit operation completed 0 Success sector erase 1 Fail sector erase Figure 19 1 Flash Memory Control Register FMCON The bitO of FMCON register 0 is a start bit for Erase and Hard Lock operation mode Therefore operation of Erase and Hard Lock mode is activated when you set FMCON O to 1 Also you should wait a time of Erase Sector erase o
220. le fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register Function Description Interrupt mask register Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQO IRQ7 Interrupt priority register Controls the relative processing priorities of the interrupt levels The seven levels of S3C828B F828B C8289 F8289 C8285 F8285 are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode register This register enables disables fast interrupt processing dynamic global interrupt processing and external interface control An external memory interface is implemented in the S3C828B F828B C8289 F8289 C8285 F8285 microcontroller NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended ELECTRONICS 5 7 INTERRUPT STRUCTURE S3C828B F828B C8289 F8289 C8285 F8285 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or b
221. load flash memory upper address to upper of pair working register LD R3 0 load flash memory lower address to lower pair working register LOOP LDC RO RR2 read data from flash memory location Between 300H and 3FFH INC R3 CP R3 0H JP NZ LOOP ELECTRONICS 19 11 EMBEDDED FLASH MEMORY INTERFACE S3C828B F828B C8289 F8289 C8285 F8285 HARD LOCK PROTECTION User can set Hard Lock Protection by write 0110 in FMCON7 4 If this function is enabled the user cannot write or erase the data in a flash memory area This protection can be released by the chip erase execution in the tool program mode In terms of user program mode the procedure of setting Hard Lock Protection is following that Whereas in tool mode the manufacturer of serial tool writer could support Hardware Protection Please refer to the manual of serial program writer tool provided by the manufacturer THE PROGRAM PROCEDURE IN USER PROGRAM MODE 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Control Register FMCON to 01100001B 3 Set Flash Memory User Programming Enable Register FMUSR to 00000000B 8 PROGRAMMING Hard Lock Protection SB1 LD FMUSR 0A5H User Program mode enable LD FMCON 01100001B Hard Lock mode set amp start NOP Dummy Instruction This instruction must be needed LD FMUSR 0 User Program mode disable 19 12 ELECTRONICS 3C828B F828B C8289 F8
222. lock 1 This example shows how to change from the main clock to the sub clock MA2SUB LD OSCCON 01H Switches to the sub clock Stop the main clock oscillation RET 2 This example shows how to change from sub clock to main clock SUB2MA AND OSCCON 07H Start the main clock oscillation CALL DLY16 Delay 16 ms AND OSCCON 06H Switch to the main clock RET DLY16 SRP 0COH LD R0 4 20H DEL NOP DJNZ RO DEL RET 7 6 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW During a power on reset the voltage at Vpp goes to High level and the RESET pin is forced to Low level The RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings the S3C828B F828B C8289 F8289 C8285 F8285 into a known operating status To allow time for internal CPU clock oscillation to stabilize the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required time of a reset operation for oscillation stabilization is 1 millisecond Whenever a reset occurs during normal operation that is when both and RESET are High level the nRESET pin is forced Low level and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a
223. mer Control Register 200240 40 0 000000000 00000 10 2 10 2 Basic TimeriBlock Diagrarm etm 10 4 11 1 Timer A Control Register 11 2 11 2 Simplified Timer A Function Diagram Interval Timer 11 3 11 3 Simplified Timer A Function Diagram PWM 11 4 11 4 Simplified Timer A Function Diagram Capture 11 5 11 5 Timer A Functional Block 11 6 11 6 Timer B Conttol FIegister 2 2 1 0 m irte Pe ede dacs 11 7 11 7 Timer B Functional Block Diagram seen 11 8 11 8 Timer B Output Flip Flop Waveforms in Repeat Mode 11 10 12 1 Timer 0 Control Register 3 12 2 12 2 Timer 0 Functional Block enn 12 3 12 3 Timer 1 Control Register 12 5 12 4 Simplified Timer 1 Function Diagram Interval Timer Mode 12 6 12 5 Simplified Timer 1 Function Diagram PWM Mode 12 7 12 6 Simplified Timer 1 Function Diagram Capture Mode 12 8 12 7 Timer 1 Functional Block Diagram eene enne 12 9 13 1
224. mmunication For Multiprocessor Configurations Chapter 18 Battery Level Detector OVOIVIGWss nsi ted M oce E Re each ie a Ad E aya ua Battery Level Detector Control Register BLDCON S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER Table of Contents Concluded Chapter 19 Embedded Flash Memory Interface OCIA EN s Sum ieee ere ie betel eens ee amam Ss 19 1 Tool Program Mode 1 eode deeded 19 2 User Program M dE 22 tne p me e PH 19 2 Flash Memory Control Registers User Program Mode eene 19 3 Flash Memory Control Register uuu u i len ORE cgo Eoi Sede gite Rede 19 3 Flash Memory User Programming Enable 19 4 Flash Memory Sector Address 19 5 ISP TM On Board Programming Sector 19 6 ISP Reset Vector And ISP Sector Size 1 19 7 ette DE ctun uade ttr i utei dre ie ie 19 8 The Sector Program Procedure in User Program 19 9 Programming P 19 10 The Program Procedure In User Program Mode seen eene 19 10 Heading edad tai dap dme ab p IUD 19 11 The Program Procedure In User Program Mode sese enm enne 19 11 Hard Lock Protection oet c
225. mode TAOUT 01 Capture mode capture on rising edge Counter running OVF can occur 10 Capture mode Capture on falling edge Counter running OVF can occur 11 PWM mode OVF interrupt can occur Figure 11 1 Timer A Control Register TACON 11 2 ELECTRONICS 53 828 828 8289 8289 8285 8285 8 BIT A FUNCTION DESCRIPTION Timer A Interrupts IRQ0 Vectors DCH and DEH The timer A can generate two interrupts the timer A overflow interrupt TAOVF and the timer A match capture interrupt TAINT TAOVF is interrupt level IRQO vector DEH TAINT also belongs to interrupt level IRQO but is assigned the separate vector address DCH A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a 0 to the INTPND O interrupt pending bit However the timer A match capture interrupt pending condition must be cleared by the application s interrupt service routine by writing a 0 to the INTPND 1 interrupt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the timer A reference data register TADATA The match signal generates a timer A match interrupt TAINT vector DCH and clears the counter If for example you write the value 10H to TADATA the counter will incremen
226. mple dst src dst lt src IR IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src SIC dst 3 8 93 R IR Given Register 01H register 01H 70H POPUI 02H 900H gt Register 2 register 01H 70H register 02H 70H If general register OOH contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination general register 02H The user stack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 PUSH Push To Stack PUSH Operation Flags Format Examples 6 66 src SP lt SP 1 SP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH OAAH SPH OOH andSPL OO
227. n write 1 Interrupt is pending when read 0 Timer A Overflow Interrupt Pending Bit 0 No interrupt pending when read clear pending bit when write Interrupt is pending when read 4 14 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER IPH instruction Pointer High Byte DAH Set 1 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 RESET Value X X X X X X X x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH ELECTRONICS 4 15 CONTROL REGISTERS S3C828B F828B C8289 F8289 C8285 F8285 IPR Interrupt Priority Register FFH Set 1 Bank 0 RESET Value X x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 4 and 1 Register addressing mode only Priority Control Bits for Interrupt Groups A B and C 0 Group priority und
228. naffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 10 R 4 11 IR Given Register OOH register 01H 2 and register 02H 17H C 0 RLC 00H gt RegisterOOH 54H C 1 RLC 01H gt Register 01H 02H register 02H 2EH C 0 In the first example if general register 00H has the value 10101010B the statement RLC OOH rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the flag replaces bit zero of register leaving the value 55H 01010101B The MSB of register resets the carry flag to 1 and sets the overflow flag ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET RR Rotate Right RR Operation Flags Format Examples dst lt st 0 dst 7 lt dst 0 dst dst n 1 0 6 The contents of the destination operand are rotated right bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set ifthe result is 0 cleared otherwise S Set ifthe result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst
229. ne specified by the concatenated 16 bit vector address NOTE A 16 bit vector address always begins at an even numbered ROM address within the range of OOH FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent INSTRUCTION POINTER IP The instruction pointer IP is adopted by all the S3C8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair DAH and DBH The names of IP registers are IPH high byte IP15 IP8 and IPL low byte IP7 IPO FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles To select a specif
230. ng 1 Pending 2 Level 2 IRQ2 Request Pending Bit Timer 0 Match Not pending 1 Pending 1 Level 1 IRQ1 Request Pending Bit Timer B Match Not pending 1 Pending 0 Level 0 IRQ0 Request Pending Bit Timer Match Capture or Overflow Not pending 1 Pending ELECTRONICS 4 1 N CONTROL REGISTERS S3C828B F828B C8289 F8289 C8285 F8285 LCON LCD Control Register DOH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Internal LCD Dividing Resistors Enable Bit 0 Enable internal LCD dividing resistors 1 Disable internal LCD dividing resistors 6 5 LCD Clock Selection Bits fw 25 1024 Hz 4 2 LCD Duty and Bias Selection Bits note 1 8duty 1 4 bias 1 4duty 1 3 bias 1 3duty 1 3 bias 1 3duty 1 2 bias 1 2duty 1 2 bias Not used for the S3C828B C8289 C8285 0 LCD Display Control Bits 0 All LCD signals are low Turn off the P Tr 1 Turn display on Turn on the P Tr NOTES 1 x means don t care 2 When 1 3 bias is selected the bias levels are set as Vi Vici Vice VI c3 and Vas 3 When 1 2bias is selected the bias levels are set as Vi Vi c4 Vi co Vi c3 and Vas 4 18 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER OSCCON oscillator Control Register FAH Set 1 Bank 0 RESET Value 0 0 0 0 Read Wri
231. ns SEG6 SEG9 Input or push pull output and software assignable pull ups I O port with bit programmable pins 50 51 48 49 COMO COM1 Input or push pull output and software assignable pull ups LCD power supply pins 52 57 50 55 2 7 SEGO SEG5 PRODUCT OVERVIEW S3C828B F828B C8289 F8289 C8285 F8285 Table 1 1 S3C828B F828B C8289 F8289 C8285 F8285 Pin Descriptions Continued P Pin Circuit Pin Type Description Numbers in lt External interrupts input pins Timer 1 capture input T1CLK Timer 1 external clock input BUZ Output pin for buzzer signal P1 3 SO SCK SI Serial clock serial data output and serial data input ADO AD6 lO converter analog input channels F 1 2 0 2 6 07 P2 7Ng DREF A D converter reference voltage AVSS A D converter ground VBLDREF Battery level detector reference voltage INTO INT7 4 21 28 19 26 P0 0 P0 7 E4 29027 O gt U m 4 4 N TAOUT TAPWM TxD RxD Uart data output input P8 2 P8 7 1 LCD common signal outputs COM2 COM7 SEGO SEG5 5 0 5 5 LCD segment signal outputs COM2 COM7 P8 2 P8 7 SEG6 SEG9 P7 0 P7 3 SEG10 SEG17 P6 0 P6 7 SEG18 SEG25 4 0 4 7 SEG26 SEG33 P5 0 P5 7 SEG34 P3 0 TBPWM SEG35 P3 1 TAOUT TAPWM SEG36 P3 2 TACLK SEG37 P3 3 TACAP needed 0 1 RESET 1 S
232. ntended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product S3C828B F828B C8289 F8289 C8285 F8285 8 Bit CMOS Microcontrollers User s Manual Revision 1 Publication Number 21 S3 C828B F828B C8289 F8289 C8285 F8285 042005 2005 Samsung Electronics rights reserved part of this publication may be reproduced stored in a retrieval system or transmitted any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are designed and manufactured in accord
233. nto groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA IRQO IRQ1 GroupB 2 IRQ4 Group C IRQ5 IRQ6 IRQ7 IPR IPR IPR Group A Group B Group Al A2 1 2 C1 2 21 22 C21 C22 IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship gt C gt A The setting 101B would select the relationship C B A The functions of the other IPR bit settings are as follows 5 controls the relative priorities of group C interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C 0 controls the relative priority setting of IRQO and IRQ1 interrupts 5 12 ELECTRONICS 53 828 828 8289 8289 8285 8285 INTERRUPT STRUCTURE Interrupt Priority Register IPR Set 1 Bank 0 R W 1 Group priority 4 4 a L Group A D7 D4 D1 0 IRQ0 gt IRQ1 ITT 1 IRQ1 gt IRQ0 0 0 0 Undefined Group B 0 0 1 gt gt 0
234. nued Chapter 15 10 bit Analog to Digital Converter OVerVIeW ix Petr ed cg acon el e He o Ete at ed iced Function Description Conversion Timing A D Converter Control Register ADCON Internal Reference Voltage Levels Block Diagram Chapter 16 Serial I O Interface VET VIO PM edendi e ee ei SIO Control Register SIOCON ccccecceeeeceeeeeeeeeeeeeeeeeeeceaeeseeaeesaaeeecaeeeeaeeeceaeeseaeeeeeaeeseeaeeneneeeesaeees SIO PRe Scaler Register SIOPS E Serial I O Timing Diagram Chapter 17 UART eM PC Programming Procedure ide npe d RR tr UART Control Register UARTCON UART Interrupt Pending Bits ses citare cet tete teet cer cci dece aen UART DatasJRegisten UDATA 5 5 bat Rm band eren d ull PER UART Baud Rate Data Register BRDATA BAUD Rate Calculations Block Diagram rima red itetum eate ahh usa sq kia g ai UART Mode 0 Function Serial Port Mode 1 Function Description Serial Port Mode 2 Function Description Serial Port Mode Function Serial Co
235. o Connection 100 Pin Connector SMDS2 SMDS2 Set the XI switch to XTAL EVA Chip when ae 2 S3E8280 as a standalone unit and is not connected to the A SMDS2 SMDS2 XIN XOUT XIN XTAL Target Board 23 4 ELECTRONICS 53 828 828 8289 8289 8285 8285 DEVELOPMENT TOOLS Table 23 3 Device Selection Settings for TB828B 9 5 Device Selection Operating Mode Comments Settings Device Selection 8249 5 fee 828B TB828B Device Selection 8289 5 TB8289 Operate with TB828B Target System Operate with TB8289 Device Selection 8289 5 828B TB8285 8285 8289 SMDS2 SELECTION 5 8 Operate with TB8285 In order to write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a switch as follows Otherwise the program memory writing function is not available Table 23 4 The SMDS2 Tool Selection Setting SMDS2 Setting SMDS2 o SMDS2 IDLE LED Operating Mode R W RW gt Target SMDS2 System The Yellow LED is ON when the evaluation chip S3E8280 is in idle mode STOP LED The Red LED is ON when the evaluation chip S3E8280 is in stop mode ELECTRONICS 23 5 DEVELOPMENT TOOLS 53 828 828 8289 8289 8285 8285 Table 23 5 Smart Option Source Settings for TB828B 9 5 Select Smart Option Source Select Smart Option Source Smart Opti
236. o the P1CONH register if necessary Load an 8 bit value to the SIOCON control register to properly configure the serial I O module In this operation SIOCON 2 must be set to 1 to enable the data shifter For interrupt generation set the serial I O interrupt enable bit SIOCON 1 to 1 When you transmit data to the serial buffer write data to SIODATA and set SIOCON 3 to 1 the shift operation starts When the shift operation transmit receive is completed the SIO pending bit SIOCON 0 is set to 1 and an SIO interrupt request is generated ELECTRONICS 16 1 SERIAL I O INTERFACE S3C828B F828B C8289 F8289 C8285 F8285 SIO CONTROL REGISTER SIOCON The control register for serial interface module SIOCON is located at EOH in set 1 bank 0 It has the control settings for SIO module Clock source selection internal or external for shift clock Interrupt enable Edge selection for shift operation Clear 3 bit counter and start shift operation Shift operation transmit enable Mode selection transmit receive or receive only Data direction selection MSB first or LSB first A reset clears the SIOCON value to 00H This configures the corresponding module with an internal clock Source at the SCK selects receive only operating mode and clears the 3 bit counter The data shift operation and the interrupt are disabled The selected data direction is MSB first Serial I O Module Control Regi
237. ock source for an external interrupt When BTCNT 4 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume the normal operation In summary the following events occur when stop mode is released 1 During the stop mode a power on reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts 2 If a power on reset occurred the basic timer counter will increase at the rate of fxx 4096 If an interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows When a BTCNT 4 overflow occurs the normal CPU operation resumes ELECTRONICS 10 3 BASIC 53 828 828 8289 8289 8285 8285 RESET STOP Bits 3 2 Basic Timer Control Register y Write 1010xxxxB to Disable fxx 4096 fxx 1024 8 Bit Up Counter fxx 128 BTCNT Read Only Start the CPU NOTE NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Figure 10 2 Basic Timer Block Diagram 10 4 ELECTRONICS 53 828 828 8289 8289 8285 8285 8 BIT 8 8 BIT OVERVIEW The 8 bit t
238. of ISP sector can be varied by settings of Smart Option You can choose appropriate ISP sector size according to the size of On Board Program software Decimal 65 535 Decimal 32 767 64K bytes Internal Program Memory Area 32K bytes 16 383 Internal Program Memory Area 16K bytes Internal Program Memory Area Decimal Interrupt Vector Area S3F828B S3F8289 S3F8285 Figure 19 5 Program Memory Address Space 19 6 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 EMBEDDED FLASH MEMORY INTERFACE Table 19 2 ISP sector size Smart Option 003CH ISP Size Selection Bit Area of ISP Sector ISP Sector Size Bit 2 Bit Bito 100H 2FFH 512 Byte 512 Bytes NOTE The area of the ISP sector selected by Smart Option bit 003CH 2 003CH 0 can not be erased and programmed by LDC instruction in User Program mode we 0 0 0 0 IO ISP RESET VECTOR AND ISP SECTOR SIZE If you use ISP sectors by setting the ISP Enable Disable bit to 0 and the Reset Vector Selection bit to 0 at the Smart Option you can choose the reset vector address of CPU as shown in Table 19 3 by setting the ISP Reset Vector Address Selection bits Table 19 3 Reset Vector Address Smart Option 003CH Reset Vector Usable Area for ISP Sector Size ISP Reset Vector Address Selection Bit Address After POR ISP Sector 0100H _ _ 0200H 100H 1FFH 256 Bytes 100H 2FFH 512 Bytes 100H
239. oge det depo Roe even ede det eee sca due dee Rede deo 19 12 The Program Procedure In User Program Mode seen enne 19 12 Chapter 20 Electrical Data ee Liv ee A NR um n M 20 1 Chapter 21 Mechanical Data SI WS 21 1 Chapter 22 S3F828B F8289 F8285 Flash MCU OVGIVIOW Lane rn HUI E B a De SE EH OS DDR se ee ee 22 1 Operating Mode Characteristics uuu Do n etate eR Rega exa een ade gone bns 22 5 Chapter 23 Development Tools ihi EB EIER UL VD RP ODE a SHEER HOC HEAR ER 23 1 lale 23 1 SAMA Assemblet z ere it eli e e eletti ieget mk uqu 23 1 SASMBOS ires bI eis eo Ya ohhh eh Netegrity sees 23 1 FIEXQROM E 23 1 TargetiBOatdsz eio e etie ei ente de 23 1 TB828B 9 5 Target Board ite peti iere SiN eh eti m de mis eae 23 3 SMDS2 Selection SAMDB ne u REEL e da eked del esa e e ED eal Fak 23 5 Idle LED u e tinte RR gi decedente er iit e EET EPA 23 5 Stop E ED ii secs gap oti ede near te e or ep ea D eo de n do rem derer Ee e eR REN 23 5 S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 Block D
240. ol Register 5 7 5 3 Interrupt Source Control and Data Registers 5 9 6 1 Instruction Group 6 2 6 2 Flag Notation Conventions 6 8 6 3 Instruction Set SyMbols i viedo aes eerste 6 8 6 4 Instruction Notation Conventions 6 9 6 5 Opcode Quick Reference nr 6 10 6 6 Condition codos hissini nutu ER der iet o pe Pete SD e RSS ca eat 6 12 8 1 S3C828B F828B C8289 F8289 C8285 F8285 Set 1 Register and Values after RESET ineunte erp rep Recte iceberg gd 8 2 8 2 S3C828B F828B C8289 F8289 C8285 F8285 Set 1 BankO Register and Values after RESET iecit ic Lee de eterne aasan 8 3 8 3 S3C828B F828B C8289 F8289 C8285 F8285 Set 1 Bank1 Register and Values after RESET iter aided ioc hs tated tian ha ak 8 4 9 1 S3C828B F828B C8289 F8289 C8285 F8285 Port Configuration Overview 9 1 9 2 Port Data Register 9 2 S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER xv List of Tables continued Table Title Page Number Number 17 1 Commonly Used Baud Rates Generated by 17 5 18 1 BLDCON Value and Detection 18 3 19 1 Descriptions of Pins Used to Read Write the Flash in Tool Program mode
241. ollers No flags are affected Bytes Cycles Opcode Hex opc 1 4 5F The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET SBC subtract with Carry SBC dst src Operation dst lt dst src The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Flags Set if a borrow occurred src gt dst cleared otherwise Z Set ifthe result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src ope 2 4 32 r r 6 33 r Ir src dst 3 6 34 R R 35 R IR dst src 3 6 36 R I
242. on COM1 COMO ELECTRONICS 4 41 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 Register Page Pointer DFH RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits 0 0 Destination page 0 0 1 Destination page 1 Lo 0 1 0 Destination page 2 not used for the 5368285 0 1 1 Destination page not used for the S3C8285 oe Destination page 4 not used for the S3C8289 C8285 1011 0 1 Destination page 5 not used for the S3C8289 C8285 fo 1 0 Destination page 6 not used for the S3C8289 C 8285 o i 1 1 Destination page 7 not used for the S3C8289 C8285 1 0 0 Destination page 8 not used for the S3C8289 C8285 Destination 9 not used for the S3C8289 C8285 1 1 1 Destination page 15 Others Not used for the S3C828B C8289 C8285 3 0 Source Register Page Selection Bits 0 Source 0 Source 1 10 1 0 Source page 2 not used for the 5308285 01 0 1 1 Source page not used for the 53 8285 Source 4 not used for the 53 8289 8285 fo 1 0 1 Source page 5 not used for the S3C8289 C8285 1 1 0 Source page 6 not used for the S3C8289 C8285 HH Source 7 not used for the 53 8289 8285 Source page 8 not
243. on Source Operating Mode Comments Settings The Smart Option is selected by external smart option Target internal externa 828 9 5 bae switch SW1 The Smart Option is selected by internal smart option area Internal Do External TB828B 9 5 003EH 0003FH of ROM But this selection is not available Table 23 6 Smart Option Switch Setting for TB828B 9 5 Smart Option Setting Comments ON Smart Option be selected this switch when the Smart N N N N N one Option source is selected by external The SW1 3 SW1 1 22452759 T High 1 comparable to the 00 2 0 The SW1 8 SW1 6 are comparable to Smart Option the 003EH 7 5 The SW1 9 is comparable to the 003FH 0 SW1 5 1 4 is not connected SW1 10 is not used 23 6 ELECTRONICS 53 828 828 8289 8289 8285 8285 DEVELOPMENT TOOLS J101 J102 SEG29 P5 3 C L3 SEG30 P5 4 P2 5 AD5 C3 41 42 P2 6 AD6 SEG31 P5 5 L3 SEG32 P5 6 P2 7 AD7 VBLDREF 43 44 F3 AVREF SEG33 P5 7 C L3 SEG34 P3 0 TBPWM AVss 45 46 5 Vico SEG35 P3 1 TAOUT TAPWM C3 4 SEG36 P3 2 TACLK Vici 9 47 48 F3 Vice SEG37 P3 3 TACAP P3 4 TxD VLC3 49 50 COMO P8 0 P3 5 RxD VDD COM1 P8 1 51 52 COM SEGO P8 2 Vss 5 XouT COM3 SEG1 P8 3 53 5 54 COM4 SEG2 P8 4 XIN TEST COM5 SEG3 P8 5 55 5 56 COM6 SEG4 P8 6 XTIN C3 E3 XTour COM7 SEG5 P8 7 57 58 L3 SEG6 P7 0 nRESET Cj r3 V
244. ormation about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual Data and counter registers are not described in detail in this reference chapter More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual The locations and read write characteristics of all mapped registers in the 530828B C8289 C8285 register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers RegsterMame Mnemonic Decimal Hex RW Basic Timer Control Register BTCON 211 D3H R W RW m o w RW RW RW RW RW interrupt Request Register m o n RW RW Register Page Pointer PP 23 DH R W ELECTRONICS 4 1 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 Table 4 2 Set 1 Bank 0 Registers x RegisterName Mnemonic Decimal He rw Waren Timer convo nease woon aw Battery Level Detector Control Register _ BLocon RW SIO Control pee SIOCON 12 1 4 S10 Pre soaler Register 26 _ D NR RC Timer 0 Counter RegisteHigh Bye TOONTH R Timer 0 Counter RegisterLow Byte 229 R Timer A Counter Regis
245. ory Register File 8 bit Register File Address dst ADDRESS OPCODE Point to One Register in Register One Operand File Instruction Example Address of Operand used by Instruction Instruction Execution Value used in Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3C828B F828B C8289 F8289 C8285 F8285 INDIRECT REGISTER ADDRESSING MODE Continued Register File NN Example REGISTER Instruction dst PAIR References OPCODE Points to Program Register Pair Jebi Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND lt CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS 53 828 828 8289 8289 8285 8285 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO RPO Selected RP points Program Memory to start fo 4 bit working register Worki block orking gt Register Point to the Address Working Register ADDRESS 1 of 8 Sample Instruction Value used in OPERAND OR R3 R6 Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRE
246. ource peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence Reset clear 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine gt oN Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM 0 to 1 It allows the CPU to process the next interrupt request 5 16 ELECTRONICS 53 828 828 8289 8289 8285 8285 INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location oa fF Branch to the service routi
247. perands are treated as unsigned integers C Setifresultis gt 255 cleared otherwise Z Set if the result is 0 cleared otherwise S Set if MSB of the result is 1 cleared otherwise V Cleared D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Given RegisterOOH 20H register 01H register 02H 09H register 03H MULT 00H 02H gt Register 01H register 01H 20H register 02H 09H MULT 00H 01 gt Register register 01H MULT 00H 30H gt Register 06H register 01H OOH In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair OOH 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H ELECTRONICS 6 59 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 next Operation PC lt IP IP IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 10 OF Example The following diagram shows one example of how to use the NEXT instruction Before After
248. port system in turnkey form The development support system is configured with a host system debugging tools and support software For the host system any standard computer that operates with MS DOS Windows 95 and 98 as its operating system can be used One type of debugging tool including hardware and software is provided the sophisticated and powerful in circuit emulator SMDS2 and OPENice for S3C7 S3C9 S3C8 families of microcontrollers The SMDS2 is a new and improved version of SMDS2 Samsung also offers support software that includes debugger assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be sized moved scrolled highlighted added or removed completely SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM88 The 5 5 88 is a relocatable assembler for Samsung s S3C8 s
249. propriate control and clock settings before entering Stop mode When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed Using an Internal Interrupt to Release Stop Mode Activate any enabled interrupt causing Stop mode to be released Other things are same as using external interrupt How to Enter into Stop Mode Handling STPCON register then writing STOP instruction keep the order LD STPCON 10100101B STOP NOP NOP NOP ELECTRONICS 8 5 RESET and POWER DOWN S3C828B F828B C8289 F8289 C8285 F8285 IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals timers remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared
250. pter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the S3C8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3C828B F828B C8289 F8289 C8285 F8285 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part 11 If you are not yet familiar with the S3C8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Late
251. r you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3C828B F828B C8289 F8289 C8285 F8285 microcontroller Also included in Part II are electrical mechanical Flash and development tools data It has 17 chapters Chapter 7 Clock Circuit Chapter 16 Serial I O Interface Chapter 8 RESET and Power Down Chapter 17 UART Chapter 9 I O Ports Chapter 18 Battery Level Detector Chapter 10 Basic Timer Chapter 19 Embedded Flash Memory Chapter 11 8 bit Timer A B Chapter 20 Electrical Data Chapter 12 16 bit Timer 0 1 Chapter 21 Mechanical Data Chapter 13 Watch Timer Chapter 22 S3F828B F8289 F8285 Flash MCU Chapter 14 LCD Controller Driver Chapter 23 Development Tools Chapter 15 10 bit to Digital Converter Two order forms are included at the back of this manual to facilitate customer order for S C828B F828B C8289 F8289 C8285 F8285 microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview S368 Series Microcontrollers adieu aa edis statua P inire ge 1 1 S3C828B F828B C8289 F8289 C8285 F8285 1 1
252. r File 8 bit Register OPERAND NN gt Register in Register LE One Operand File Instruction Value used Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File o cM RPO ot RP1 RPO or RP1 Selected RP points to start 4 bit of working register Program Memory Working Register block OPCODE Point to the OPERAND gt Working Register Two Operand 1 of 8 Instruction Example lt Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS 53 828 828 8289 8289 8285 8285 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations COH FFH in set 1 using the Indirect Register addressing mode Program Mem
253. r Hard lock to complete it s operation before a byte programming or a byte read of same sector area by using LDC instruction When you read or program byte data from or into flash memory this bit is not needed to manipulate The sector erase status bit is read only If an interrupt is requested during the operation of Sector erase the operation of Sector erase is discontinued and the interrupt is served by CPU Therefore the sector erase status bit should be checked after executing Sector erase The sector erase operation is success if the bit is logic 0 and is failure if the bit is logic 1 NOTE When the ID code A5H is written to the FMUSR register a mode of sector erase user program and hard lock may be executed unfortunately So it should be careful of the above situation ELECTRONICS 19 3 EMBEDDED FLASH MEMORY INTERFACE S3C828B F828B C8289 F8289 C8285 F8285 FLASH MEMORY USER PROGRAMMING ENABLE REGISTER The FMUSR register is used for a safety operation of the flash memory This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise After reset the user programming mode is disabled because the value of FMUSR is 00000000 by reset operation If necessary to operate the flash memory you can use the user programming mode by setting the value of FMUSR to 10100101B The other value of 10100101b User Program mode is disabled Flash Memory User
254. rand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte _ LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDG R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS 53 828 828 8289 8289 8285 8285 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE A Memory Address Upper Address Byte Lower Address Byte Used OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3C828B F828B C8289 F8289 C8285 F8285 INDIRECT ADDRESS MODE IA In Indirect Address
255. rce to the 8 bit timer counter module timer B for generating the timer B overflow interrupt Timer B Control Register TBCON F2H Set 1 Bank 0 R W Timer B input clock selection bits Timer B output flip flop control bit 00 fxx 0 TBOF is low 01 fxx 2 1 is high 10 fxx 4 11 fxx 8 Timer mode selection bit 0 One shot mode 1 Repeating mode Timer B interrupt time selection bits 00 Elapsed time for low data value 01 Elapsed time for high data value 10 Elapsed time for low and high data values 11 Not available Timer B start stop bit 0 Stop timer B 1 Start timer B Timer B interrupt enable bit 0 Disable interrupt 1 Enable interrupt Figure 11 6 Timer B Control Register ELECTRONICS 11 7 8 S3C828B F828B C8289 F8289 C8285 F8285 BLOCK DIAGRAM 6 7 2 a bod1 fxx 2 Pl D 1 Other Block own Counter TBOF 8 Repeat Control TBCON 3 IRQ1 Interrupt Control INT GEN TBINT Timer B Data Low Byte Register Timer B Data High Byte Register Data Bus TBCON 4 5 NOTE The value of the TBDATAL register is loaded into the 8 bit counter when the operation of the timer B starts If a borrow occurs in the counter the value of the TBDATAH register is loaded into the 8 bit counter However if the next borrow occurs the value of the
256. re 2 When 1 3 bias is selected the bias levels are set as VLCO VLC1 VLC2 VLC3 and VSS 3 When 1 2 bias is selected the bias levels are set as VLCO VLC1 VLC2 VLC3 and VSS Figure 14 4 LCD Control Register LCON 14 4 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 LCD VOLTAGE DIVIDING RESISTOR 1 4 Bias S3C828B C8289 C8285 VDD 1 2 Bias S3C828B C8289 C8285 LCON 7 0 Enable internal resistors NOTES 1 Internal LCD dividing resistors The resistors can be disconnected by LCON 7 2 R External LCD dividing resistors 3 When 1 3 bias is selected the bias levels are set as VLCO VLC1 VLC2 VLC3 and Vss LCD CONTROLLER DRIVER 1 3 Bias 53 828 8289 8285 VDD LCON 7 0 Enable internal resistors o VLCD Voltage Dividing Resistor Adjustment S3C828B C8289 C8285 Figure 14 5 LCD Voltage Dividing Resistor Connection ELECTRONICS 14 5 LCD CONTROLLER DRIVER S3C828B F828B C8289 F8289 C8285 F8285 COMMON COM SIGNALS The common signal output pin selection COM pin selection varies according to the selected duty cycle In 1 8 duty mode COMO COM7 SEG6 SEG37 pins are selected In 1 4 duty mode SEG2 SEG37 In 1 3 duty mode 0 2 SEG1 SEG37 pins are selected In 1 2 duty mode COMO COM 1 SEGO SEG37 pins are selected pins are selected SEGMENT SEG S
257. rea 2 18 4 Bit Working Register Addressing 2 19 8 Bit Working Register nennen enne enne 2 21 System And User Stack itr oui rer p Pe teer prie diri pete dir qe 2 23 S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER Table of Contents continued Chapter 3 Addressing Modes 3 1 Register Addressing Mode R cies ice e ete ce debi rige retine sies 3 2 Indirect Register Addressing Mode IR eee nnne 3 3 uu ceperit deed ie eee dete iad 3 7 Dir ct Address Mode DA 3 rer eee e d een ode terere en ete eei pe dos 3 10 Indirect Address Mode 1A n erret ern asap Tee nee cra dee 3 12 Relative Address Mode R cci nietos deo ded e 3 13 Irimediate RE am el e Ne d eei epe eid eet Pe ege Bald pepe et eue re 3 14 Chapter 4 Control Registers COVOrVIOW 5 i ms HEUS Note D DA ELI ELE t 4 1 Chapter 5 Interrupt Structure 2 di eem OE See S aa 5 1 InterruptUTypeSu 5
258. register reception of the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the next byte has been completely received one of the bytes will be lost In all operating modes transmission is started when any instruction usually a write operation uses the UDATA register as its destination address In mode 0 serial data reception starts when the receive interrupt pending bit INTPND 5 is 0 and the receive enable bit UARTCON 4 is 1 In mode 1 2 and 3 reception starts whenever an incoming start bit 0 is received and the receive enable bit UARTCON 4 is set to 1 PROGRAMMING PROCEDURE To program the UART modules follow these basic steps 1 Configure P3 5 and P3 4 to alternative function RxD P3 5 TxD P3 4 for UART module by setting the P5CONH register to appropriately value Load an 8 bit value to the UARTCON control register to properly configure the UART I O module For interrupt generation set the UART I O interrupt enable bit UARTCON 1 or UARTCON O to 1 When you transmit data to the UART buffer write data to UDATA the shift operation starts When the shift operation transmit receive is completed UART pending bit INTPND 4 or INTPND 5 is set to 1 and an UART interrupt request is generated ELECTRONICS 17 1 UART 53 828 828 8289 8289 8285 8285 UART CONTROL REGISTER UARTC
259. register P1PUR E7H set 1 bank 1 you can configure pull up resistors to individual port 1 pins Port 1 Control Register High Byte P1CONH E5H Set 1 Bank 1 R W P1 5 SCK P1 6 SI Not used for S3C828B C8289 C8285 P1CONH bit pair pin configuration settings 00 Input mode SI SCK in 01 Output mode N channel open drain 10 Output mode push pull 11 Alternative function SCK out SO not used for P1 6 Figure 9 6 Port 1 High Byte Control Register PI CONH ELECTRONICS 9 7 5 S3C828B F828B C8289 F8289 C8285 F8285 Port 1 Control Register Low Byte P1CONL E6H Set 1 Bank 1 R W P1 0 T1CAP 1 T1CLK P1 2 T1OUT P1 3 T1PWM BUZ P1CONL bit pair pin configuration settings 00 Input mode T1CAP 01 Output mode N channel open drain 10 Output mode push pull 11 Alternative function BUZ T1OUT T1PWM not used for P1 0 P1 1 When use this port 1 user must be care of the pull up resistance status Figure 9 7 Port 1 Low Byte Control Register P1CONL Port 1 Pull up Resistor Enable Register P1PUR E7H Set 1 Bank 1 R W MSB 17 6 5 4 3 2 4 0 19 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 Not used for the S3C828B C8289 C8285 P1PUR bit configuration settings 0 1 Pull up Disable Pull up Enable Figure 9 8 Port 1 Pull up Resistor Enable Register P1PUR 9 8 ELECTRONICS 53 828 828 8289 8289
260. reset operation All interrupt is disabled watchdog function basic timer is enabled Ports 0 8 and set to input mode and all pull up resistors are disabled for the I O port Peripheral control and data register settings are disabled and reset to their default hardware values The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed at normal mode by smart option reset address at ROM can be changed by Smart Option in the 53 828 full flash device Refer to The Chapter 19 Embedded Flash Memory Interface for more detailed contents NORMAL MODE RESET OPERATION In normal masked ROM mode the Test pin is tied to Vas A reset enables access to the S3C828B 64Kbyte S3C8289 32 Kbyte and S3C8285 16 Kbyte on chip ROM The external interface is not automatically configured NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 RESET and POWER DOWN S3C828B F828B C8289
261. ress Register FMSECH DOH Set 1 Bank 1 R W Flash Memory Setor Address High Byte NOTE The high byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address Figure 19 3 Flash Memory Sector Address Register High Byte FMSECH Flash Memory Sector Address Register FMSECL D1H Set 1 Bank 1 R W Don t care Flash Memory Sector Address Low Byte NOTE Thelow byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address Figure 19 4 Flash Memory Sector Address Register Low Byte FMSECL ELECTRONICS 19 5 EMBEDDED FLASH MEMORY INTERFACE S3C828B F828B C8289 F8289 C8285 F8285 ISP ON BOARD PROGRAMMING SECTOR ISP sectors located in program memory area can store On Board Program software Boot program code for upgrading application code by interfacing with I O port pin The ISP sectors can be erased or programmed by LDC instruction for the safety of On Board Program software The ISP sectors are available only when the ISP enable disable bit is set 0 that is enable ISP at the Smart Option If you don t like to use ISP sector this area can be used as a normal program memory can be erased or programmed by LDC instruction by setting ISP disable bit 1 at the Smart Option Even if ISP sector is selected ISP sector can be erased or programmed in the Tool Program mode by Serial programming tools The size
262. ressing ELECTRONICS 2 17 ADDRESS SPACES 53 828 828 8289 8289 8285 8285 COMMON WORKING REGISTER AREA After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block RPO COH C7H C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH Page 15 LCD Data 1100 0000 Register Area 1 1100 1000 1100 1000 NOTE In case of S3C8289 F8289 page0 page3 and S3C8285 F8285 page0 page1 Figure 2 13 Common Working Register Area 2 18 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 ADDRESS SPACES PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Examples 1 10 0C2H 40H Invalid addressing mode Use working register addressing instead SRP 0COH LD R2 40H R2 C2H the value in location 40H 2 ADD 0C3H 45
263. rflow 0 Disable mask 1 Enable unmask 2 Interrupt Level 2 IRQ2 Enable Bit Timer 0 Match 0 Disable mask 1 Enable unmask 4 Interrupt Level 1 IRQ1 Enable Bit Timer Match 0 Disable mask 1 Enable unmask 0 Interrupt Level 0 IRQO Enable Bit Timer A Match Capture or Overflow 0 Disable mask 1 Enable unmask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU ELECTRONICS 4 1 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 INTPND Interrupt Pending Register F9H Set 1 Bank0 RESET Value _ _ 0 0 0 0 0 0 Read Write _ _ R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3C828B C8289 C8285 5 Rx Interrupt Pending Bit for UART EN No interrupt pending when read clear pending bit when write Interrupt is pending when read 4 Tx Interrupt Pending Bit for UART EN No interrupt pending when read clear pending bit when write Interrupt is pending when read E Timer 1 Match Capture Interrupt Pending Bit EN No interrupt pending when read clear pending bit when write Interrupt is pending when read 2 Timer 1 Overflow Interrupt Pending Bit EN No interrupt pending when read clear pending bit when write Interrupt is pending when read 1 Timer A Match Capture Interrupt Pending Bit No interrupt pending when read clear pending bit whe
264. rime Area Register and LCD Data Register 2 12 2 8 8 Byte Working Register Areas 2 13 2 9 Contiguous 16 Byte Working Register 2 14 2 10 Non Contiguous 16 Byte Working Register Block 2 15 2 11 16 Bit Register ue odii ee dee nete dee 2 16 2 12 Register File Addressing 1 ciet Ie creto ie 2 17 2 13 Common Working Register 2 18 2 14 4 Bit Working Register Addressing eene 2 20 2 15 4 Bit Working Register Addressing Example eee 2 20 2 16 8 Bit Working Register 2 21 2 17 8 Bit Working Register Addressing Example eene 2 22 2 18 Stack Operations aai ete ei oeil a Un Le Sede ERRORIS 2 23 3 1 Register Addressing ii o pie ee epe e rU e ee 3 2 3 2 Working Register Addressing sese 3 2 3 3 Indirect Register Addressing to Register 2 22 11 3 3 3 4 Indirect Register Addressing to Program 3 4 3 5 Indirect Working Register Addressing to Register File 3 5 3 6 Indirect Working Register Addressing to Program or Data 3 6 3 7 Indexed Addressing to Reg
265. rite R W R W R W R W R W R W R W R W Addressing Mode 7 6 ELECTRONICS Register addressing mode only Timer B Input Clock Selection Bits 0 fxx 1 1 fxx 2 Timer Interrupt Time Selection Bits Generating after low data is borrowed fo Generating after high data is borrowed 1 0 Generating after low and high data are borrowed 1 1 Not available Timer B Interrupt Enable Bit Disable Interrupt Enable Interrupt Timer B Start Stop Bit K Stop timer B Start timer B Timer B Mode Selection Bit 0 One shot mode 1 Repeating mode Timer B Output flip flop Control Bit 0 is low TBPWM low level for low data high level for high data is high TBPWM high level for low data low level for high data CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 UARTCON UART Control Register F6H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 UART Mode Selection Bits 0 0 Mode 0 shift register fxx 16 x BRDATA 1 0 1 Mode t 8 bit UART fxx 16 x BRDATA 1 1 0 Mode 2 9 bit UART fxx 16 Mode 3 9 bit UART fxx 16 x BRDATA 1 5 Multiprocesssor Communication Enable Bit for modes 2 and 3 only 0 Disable 1 Enable 4 Serial Data Receive Enable Bit Disable Enable 1 3 TB8 Location of the 9
266. rpose System Mode Register SYM DEH Set 1 R W uss 0 Always logic 0 Global interrupt enable bit 3 0 Disable all interrupts processing Not used for the S3C828B C8249 C8245 1 Enable all interrupts processing Fast interrupt level selection bits 1 Fast interrupt enable bit 2 0 IRQ0 0 Disable fast interrupts processing 1 IRQ1 1 Enable fast interrupts processing 0 IRQ2 1 IRQ3 0 IRQ4 1 IRQ5 0 IRQ6 1 IRQ7 0 0 0 0 1 1 1 1 NOTES 1 You can select only one interrupt level at a time for fast interrupt processing 2 Setting SYM 1 to 1 enables fast interrupt processing for the interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 3 Following a reset you must enable global interrupt processing by executing El instruction not by writing a 1 to SYM O Figure 5 5 System Mode Register SYM 5 10 ELECTRONICS 53 828 828 8289 8289 8285 8285 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0
267. rrectly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when you execute the SB1 instruction ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION 6 8 Flag 2 5 D H 0 1 x 53 828 828 8289 8289 8285 8285 Table 6 2 Flag Notation Conventions Description Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is
268. rrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge ELECTRONICS 4 23 CONTROL REGISTERS 53 828 828 8289 8289 8285 8285 POPND Port o Interrupt Pending Register E4H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 PO 7 External Interrupt INT7 Pending Bit EN Clear pending bit when write PO 7 INT7 interrupt request is pending when read 6 PO 6 External Interrupt INT6 Pending Bit Clear pending bit when write 1 PO 6 INT6 interrupt request is pending when read 5 P0 5 External Interrupt INT5 Pending Bit EN Clear pending bit when write PO 5 INT5 interrupt request is pending when read 4 PO 4 External Interrupt INT4 Pending Bit EN Clear pending bit when write P0 4 INT4 interrupt request is pending when read 3 PO 3 External Interrupt INT3 Pending Bit 0 Clear pending bit when write 1 interrupt request is pending when read 2 PO 2 External Interrupt INT2 Pending Bit EN Clear pending bit when write PO 2 INT2 interrupt request is pending when read 1 PO 1 External Interrupt INT1 Pending Bit Clear pending bit when write 1 PO 1 INT1 interrupt request is pending when read 0 PO0 0 External Interrupt INTO Pending Bit EN Clear pending bit when write PO 0 IN
269. rt RA addressing BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE Program Memory Address Used Current Value Displacement Current Instruction OPCODE Signed Displacement Value Sample Instructions JR ULT 4 OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES S3C828B F828B C8289 F8289 C8285 F8285 IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD Figure 3 14 Immediate Addressing 3 14 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER CONTROL REGISTERS OVERVIEW In this chapter detailed descriptions of the S3C828B C8289 C8285 control registers are presented in an easy to read format You can use this chapter as a quick reference source when writing application programs Figure 4 1 illustrates the important features of the standard register description format Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed inf
270. rupt pending bit To detect a match capture or overflow interrupt pending condition when or T1OVF is disabled the application program should poll the pending bit When a 1 is detected a timer 1 match capture or overflow interrupt is pending When her sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the interrupt pending bit Timer 1 Control Register T1 CON EBH Set 1 Bank 0 R W 2 Timer 1 overflow interrupt enable Timer 1 input clock selection bits 0 Disable overflow interrupt 000 fxx 1024 1 Enable overflow interrupt 001 fxx 256 010 fxx 64 011 fxx 8 Timer 1 match capture interrupt enable bit 100 fxx 1 0 Disable interrupt 101 External clock T1CLK falling edge 1 Enable interrupt 110 External clock T1CLK rising edge 111 Counter stop Timer 1 counter clear bit 0 No effect 1 Clear the timer 1 counter when write Timer 1 operating mode selection bits 00 Interval mode T1OUT 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF and match interrupt can occur Figure 12 3 Timer 1 Control Register T1CON ELECTRONICS 12 5 16 BIT 0 1 53 828 828 8289 8289 8285 8285 1 FUNCTION DESCRIPTION Timer 1 Interrupts IRQ2 Vectors E4H and E6H Th
271. rve as inputs with without pull ups as push pull outputs And they can serve as segment pins for LCD also Port 8 Control Registers P8CON Port 8 has a 8 bit control registers for 8 0 8 7 A reset clears the P8CON register to configuring all pins to input mode Port 8 Control Register P8CON FEH Set 1 Bank 1 R W P8 1 P8 0 aus 2 COM2 COM1 COMO P8 3 COM3 SEGO P8 7 P8 4 SEG1 COM7 COM4 SEG5 SEG2 P8CON bit pair pin configuration settings Input mode Input mode pull up Output mode push pull Alternative function COM7 COMO SEG5 SEGO Figure 9 22 Port 8 Control Register 9 20 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 BASIC TIMER BASIC TIMER OVERVIEW S3C828B F828B C8289 F8289 C8285 F8285 has an 8 bit basic timer BASIC TIMER BT You can use the basic timer BT in two different ways As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction or signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider fxx divided by 4096 1024 128 or 16 with multiplexer 8 bit basic timer counter set 1 Bank 0 FDH read only Basic timer control register BTCON set 1 D3H read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BT
272. ry location 0105H 01H 0104H LDC RO 1000H RR2 RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H 04H LDE RO 1000H RR2 RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H 04H LDC 0 1104 RO lt contents of program memory location 1104H RO 88H LDE 0 1104 RO contents of external data memory location 1104H RO 98H LDC note 1105H RO 11H contents of RO is loaded into program memory location 1105H 1105H lt LDE 1105H RO 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE These instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 LDCD LDED Load Memory and Decrement LDCD LDED dst src Operation dst lt src rr lt mt These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes lrr an even number for program memory and an odd number for data memory Flags No flags
273. s only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or RP1 Selected RP Value used in points to Instruction Ng OPERAND start of working register block Program Memory Base Address E Two Operand Instruction Point to One of the Example Woking Register 1 of 8 Sample Instruction LD 4BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES INDEXED ADDRESSING MODE Continued MSB Points to RPO or RP1 Program Memory OFFSET OPCODE 4 bit Working Register Address LSB Selects or 8 Bits Sample Instructions LDC R4 04H RR2 LDE R4 04H RR2 NEXT 2 Bits gt Point to Working Register Pair 3C828B F828B C8289 F8289 C8285 F8285 Register File RPO or Sel
274. sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 40us width pulse The program parameters are Timer B is used in one shot mode Oscillation frequency is 4 MHz 1 clock 0 25 us TBDATAH 40 us 0 25 us 160 TBDATAL 1 Set P3 0 to TBPWM mode ORG START DI LD LD LD Pulse out LD 11 12 0100H TBDATAH 160 2 TBDATAL 1 TBCON 00000001B P3CONL 02H TBCON 00000101B 40 us 4 Reset address Set 40 us Set any value except OOH Clock Source fosc Disable Timer B interrupt Select one shot mode for Timer B Stop Timer B operation Set Timer B output flip flop TBOF high Set P3 0 to TBPWM mode Start Timer B operation to make the pulse at this point After the instruction is executed 0 75 us is required before the falling edge of the pulse starts ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 16 BIT TIMER 0 1 16 BIT TIMER 0 1 16 BIT TIMER 0 OVERVIEW The 16 bit timer 0 is an 16 bit general purpose timer Timer 0 has the interval timer mode by using the appropriate TOCON setting Timer 0 has the following functional components Clock frequency divider fxx divided by 256 64 8 or 1 with multiplexer from timer is one of the clock frequencies 16 bit counter TOCNTH L 16 bit comparator and 16 bit reference data register TODATAH L
275. ster CLKCON Oscillator control register OSCCON and STOP control register STPCON CPU CLOCK NOTATION In this document the following notation is used for descriptions of the CPU clock fx main clock fxT sub clock fxx selected system clock ELECTRONICS 7 1 CLOCK CIRCUIT MAIN OSCILLATOR CIRCUITS XIN XOUT Figure 7 1 Crystal Ceramic Oscillator fx XIN XOUT Figure 7 2 External Oscillator fx XIN XOUT Figure 7 3 RC Oscillator fx 53 828 828 8289 8289 8285 8285 SUB OSCILLATOR CIRCUITS 32 768 kHz c Figure 7 4 Crystal Ceramic Oscillator fxr Normal 32 768 kHz Figure 7 5 Crystal Ceramic Oscillator fxT for Low Current gt XTIN XTOUT Figure 7 6 External Oscillator fxT ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CLOCK CIRCUIT CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows In Stop mode the main oscillator is halted Stop mode is released and the oscillator is started by a reset operation or an external interrupt with RC delay noise filter and can be released by internal interrupt too when the sub system oscillator is running and watch timer is operating with sub system clock In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or b
276. ster SIOCON EOH Set 1 Bank 0 R W SIO shift clock selection bit SIO interrupt pending bit 0 Internal clock P S Clock 0 No interrupt pending 1 External clock SCK 0 Clear pending condition when write 1 Interrupt is pending Data direction control bit uu 0 MSB first mode SIO interrupt enable bit 0 Disable SIO interrupt 1 LSB first mode 1 Enable SIO interrupt SIO mode selection bit 0 Receive only mode 1 Transmit receive mode SIO shift operation enable bit 0 Disable shifter and clock counter 1 Enable shifter and clock counter Shift clock edge selection bit 0 Tx at falling edges Rx at rising edges 1 Tx at rising edges Rx at falling edges SIO counter clear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting Figure 16 1 Serial Module Control Registers SIOCON 16 2 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 SERIAL I O INTERFACE SIO PRE SCALER REGISTER SIOPS The control register for serial I O interface module SIOPS is located at E2H in set 1 bank 0 The value stored in the SIO pre scaler register SIOPS lets you determine the SIO clock rate baud rate as follows Baud rate Input clock fxx 4 Pre scaler value 1 or SCK input clock where the input clock is fxx 4 SIO Pre scaler Register SIOPS E2H Set 1 Bank 0 R W Baud rate fxx 4 SIOPS 1 Figure 16 2 SIO Pre scaler Register S
277. stics 20 15 22 1 Descriptions of Pins Used to Read Write the 22 4 22 2 Comparison of 53 828 8289 8285 and S3C828B C8289 C8285 Features 22 4 22 3 Operating Mode Selection 2 22 5 22 4 D C Electrical 22 5 23 1 Power Selection Settings for 828 9 5 23 4 23 2 Main clock Selection Settings for 828 9 5 23 4 23 3 Device Selection Settings for 828 9 5 23 5 23 4 The SMDS2 Tool Selection Setting eene 23 5 23 5 Smart Option Source Selection Settings for 828 9 5 23 6 23 6 Smart Option Switch Setting for TB828B 9 5 l a 23 6 xvi S3C828B F828B C8289 F8289 C8285 F8285 MICROCONTROLLER List of Programming Tips Description Page Number Chapter 2 Address Spaces Using the Page Pointer for RAM clear Page 0 1 2 10 Setting the Register Pointers eie obe i REED ERI 2 14 Using the RPs to Calculate the Sum of a Series 1 2 15 Addressing the Common Working Register 2 19 Standard Stack Operations Using PUSH
278. t 246 external interrupt 248 P0 4 external interrupt 250 P0 5 external interrupt 252 P0 6 external interrupt N O GO N OJN o 254 P0 7 external interrupt 5 6 ELECTRONICS 53 828 828 8289 8289 8285 8285 INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register IMR enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enab
279. t 1 bank 0 at address F3H The pins witch are not used for ADC can be used for normal I O During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 6 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON 0 When a conversion is completed ADCON 3 the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATAH L register where it can be read The A D converter then enters an idle state Remember to read the contents of ADDATAH L before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the A D converter has no sample and hold circuitry it is very important that fluctuation in the analog level at the ADO AD7 input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to noise will invalidate the result If the chip enters to STOP or IDLE mode in conversion process there will be a leakage current path in A D block You must use STOP or IDLE mode after ADC operation is finished ELECTRONIC
280. t src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask dst src Test under mask 6 4 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nib
281. t until it reaches At this point the timer A interrupt request is generated the counter value is reset and counting resumes With each match the level of the signal at the timer A output pin is inverted see Figure 11 2 Interrupt Enable Disable TACON 1 TAINT IRQO INTPND 1 8 Bit Comparator INTPND 1 Match INT Pending Capture Signal 8 Bit Up Counter lt TAOUT Timer A Buffer Register TACON 4 3 Match IX TACON TAOVF Timer A Data Register Figure 11 2 Simplified Timer A Function Diagram Interval Timer Mode ELECTRONICS 11 3 8 S3C828B F828B C8289 F8289 C8285 F8285 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAPWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer A data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H Although you can use the match signal to generate a timer A overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TAPWM pin is held to Low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to High level for as lon
282. te R W R W R W R W Addressing Mode Register addressing mode only 7 Sub Oscillator Circuit Selection Bit EW Select normal circuit for sub oscillator Select power saving circuit for sub oscillator note Automatically cleared to 0 when the sub oscillator is stopped by OSCCON 2 or the CPU is entered into stop mode in sub operating mode Not used for the 53 828 8289 8285 3 Main Oscillator Control Bit Main oscillator RUN 1 Main oscillator STOP 2 Sub Oscillator Control Bit Sub oscillator RUN Sub oscillator STOP e Not used for the S3C828B C8289 C8285 0 System Clock Selection Bit 0 Select main oscillator for system clock 1 Select sub oscillator for system clock NOTE A capacitor 0 1uF should be connected between VREG GND when the sub oscillator is used to power saving mode OSCCON 7 1 ELECTRONICS 4 1 CONTROL REGISTERS S3C828B F828B C8289 F8289 C8285 F8285 POCONH Port 0 Control Register High Byte EOH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 7 INT7 Schmitt trigger input mode Schmitt trigger input mode with pull up resistor KEE Output mode open drain Output mode push pull 1 Schmitt trigger input mode with pull up resistor Output mode open drain ERES Output mode push pull 4 20 ELECTRONIC
283. ter R Timer 1 Counter Registerigh Byte mont 236 nR Timer Counter Registerow Byte Eb R 5 M RR Timer 1 Data RegisterLow Byte TIDATAL em Timer B Data TBDATAH Timer B Data Register Low Byte E te Timer B Convoi Register moon 22 EM A D Converter Control Register ADCON A D Converter Data acto z nie AID Converter Data RegisterLow Byte ADDATAL 245 Fem UART Control eee UARTCON er e e UART Baud Rate Data Register BRDATA 24 Pending INTPND eee ee STOP STPCON FB Location FCH is not mapped ascTmerome n Location FEH is not mapped Interrupt Priority Register IPR 255 FFH R W 4 2 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 Table 4 3 Set 1 Bank 1 Registers Mnemonic Decimal Hex CONTROL REGISTER R W R W R W R W R W R W R W R W R W R W R W R W R W Port 2 Control Register Low Byte P2CONL 233 9 Port 3 Control Register High Byte P3CONH 234 EAH Port 3 Control Register Low Byte P3CONL R W R W R W Port 4 Control Register High Byte P4CONH 236 ECH Port 4 Control Register Low Byte P4CONL 237 EDH Port 4 Pull up Resistor Enable Register P4PUR R W R W R W Port 5 Pull up Resistor Enable Register P5PUR 239 EFH Port 0 Data Register PO 240 FO
284. th data bit to be transmitted in UART mode 2 or 3 0 or 1 2 RB8 Location of the 9th data bit to be transmitted in UART mode 2 or 3 0 or 1 1 Receive Interrupt Enable Bit 0 Disable Rx interrupt Enable Rx interrupt 0 Transmit Interrupt Enable Bit 0 Disable Tx interrupt 1 Enable Tx interrupt NOTES 1 In mode 2 and 3 if the MCE bit is set to 1 then the receive interrupt will not be activated if the received 9 data bit In mode 1 if MCE 1 the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE bit should be 0 2 descriptions for 8 bit 9 bit UART mode do not include start and stop bits fr serial data receive and transmit 3 Rx Tx interrupt pending bits in INTPND register 4 52 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER WTCON Watch Timer Control Register D1H Set 1 Bit Identifier 7 6 5 4 3 2 4 o RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W RW R W R W R W R W Addressing Mode Register addressing mode only 7 Watch Timer Clock Selection Bit EJ Main system clock divided by 27 fxx 128 Sub system clock fxt 6 Watch Timer Interrupt Enable Bit 0 Disable watch timer interrupt Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits 3 2 Watch Timer Speed Selection Bits 0 0 Set watch timer interrupt to 1 05 1 EN Set watch timer interrupt to 0 5s
285. the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITS R13 o R1 OFH If working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001 111B ELECTRONICS 6 21 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 BOR sit or BOR dst src b BOR dst b src Operation dst 0 lt dst 0 src b Flags Format Examples 6 22 or dst b lt dst b src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 src 3 6 07 ro Rb dst 3 6 07 Rb ro NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H BOR 1 01H 1 E R1 07H register 01H 03H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the first
286. the source address XL rr are each two bytes 4 DA andr source values for formats 7 and 8 used to address program memory the second set of values used in formats 9 and 10 are used to address data memory 6 52 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET LDC LDE Load Memory LDC LDE Examples Continued Given RO 11H R1 34H R2 O1H R3 04H Program memory locations 0103H 4FH 0104H 1A 0105H 6DH and1104H 88H External data memory locations 0103H 5FH 0104H 2AH 0105H 7DH and1104H 98H LDC RO RR2 RO lt contents of program memory location 0104H RO 1AH R2 O1H R3 04H LDE RO RR2 RO contents of external data memory location 0104H RO 2AH R2 01H R3 04H LDC nete RR2 RO 11H contents of RO is loaded into program memory location 0104H RR2 working registers R2 nochange LDE RR2 RO 11H contents of RO is loaded into external data memory location 0104H RR2 working registers RO R2 R3 nochange LDC RO 01H RR2 RO lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H LDE RO 01H RR2 RO lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H 04H LDC note 01 H RR2 RO 11H contents of RO is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 RO 11H contents of RO is loaded into external data memo
287. tination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected IOZONO Bytes Cycles Opcode Addr Mode Hex dst src 3 6 67 Pp dst 3 6 67 Rb ro NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H registerO1H 05H BAND 01H 1 R1 gt Register 01H O5H R1 07H In the first example source register 01H contains the value 05H 00000101 and destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit 0 value of register R1 destination leaving the value 06H 000001 10B in register R1 ELECTRONICS 6 17 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 BCP sit Compare BCP Operation Flags Format Example 6 18 dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to 0 Undefined Unaffected Unaffect
288. ting 7 4 to any value other than 1010B The 1010B value disables the watchdog function A reset clears BTCON to automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock The MCU is reseted whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occuring To do this the value must be cleared by writing a 1 to BTCON 1 at regular intervals If asystem malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during the normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop mode has been released by an external interrupt In stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset cl
289. to OOB If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed 8 6 ELECTRONICS 53 828 828 8289 8289 8285 8285 PORTS l O PORTS OVERVIEW The S3C828B F828B C8289 F8289 C8285 F8285 microcontroller has nine bit programmable I O ports 8 The port 1 is a 7 bit port the port 3 is a 6 bit port the port 7 is a 4 bit port and the others are 8 bit ports This gives a total of 65 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required Table 9 1 gives you a general overview of the 53C828B F828B C8289 F8289 C8285 F8285 I O port functions Table 9 1 S3C828B F828B C8289 F8289 C8285 F8285 Port Configuration Overview Configuration Options 1 bit programmable port Schmitt trigger input or push pull open drain output mode selected by software software assignable pull ups P0 0 P0 7 can be used as inputs for external interrupts INTO INT7 with noise filter interrupt enable
290. to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE 53 828 828 8289 8289 8285 8285 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source S4 Type 2 One level IRQn one vector V4 multiple sources S Sj Type 3 One level IRQn multiple vectors V V multiple sources S4 S 5 1 Sham In the S3C828B C8289 C8285 microcontroller two interrupt types are implemented Levels Vectors Sources Type 1 V1 V S81 51 2 M 52 5 Sn V1 51 3 IRQn V2 S2 V3 5 Vi mais Sn r Sn 1 NOTES Sn 2 1 number of Sn and Vn value is expandable 2 In the S3C828B C8289 C8285 implementation tme E Sn m interrupt types 1 and 3 are used Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS 53 828 828 8289 8289 8285 8285 INTERRUPT STRUCTURE 3C828B C8289 C8285 INTERRUPT STRUCTURE The S3C828B F828B C8289 F8289
291. to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Decimal 65 535 Decimal 32 767 64K bytes Internal Program Memory Area 32K bytes 16 383 Internal Program Decimal Memory Area 16K bytes Internal Program Memory Area Interrupt Vector Area Interrupt Vector Area S3C828B F828B S3C8289 F8289 3C8285 F8285 Figure 5 3 ROM Vector Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE S3C828B F828B C8289 F8289 C8285 F8285 Table 5 1 Interrupt Vectors Vector Address Interrupt Source Request Reset Clear Decimal Interrupt Priority in H W S W Value Level 220 Timer A match capture P 224 Timer B match 228 Timer 1 match capture 230 Timer 1 overflow 232 SIO interrupt NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 If two or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware 3 Timer or Timer 1 can not service two interrupt sources simultaneously then only one interrupt source have to be used 25 234 UART data transmit 236 UART data receive 238 Watch timer overflow 240 P0 0 external interrupt 242 P0 1 external interrupt 244 0 2 external interrup
292. tomatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register ELECTRONICS 5 15 INTERRUPT STRUCTURE 53 828 828 8289 8289 8285 8285 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software Ur m NS The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one levels are currently requesting service The interrupt must be enabled at the interrupt s s
293. tput or alternative function ELECTRONICS 4 3 N CONTROL REGISTERS S3C828B F828B C8289 F8289 C8285 F8285 P6CONH Port 6 Control Register High Byte FBH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P6 7 SEG17 Input mode Input mode pull up Output mode push pull Alternative function SEG17 5 4 3 2 0 0 Input mode Input mode pull up 0 Output mode push pull EN Alternative function SEG15 1 0 P6 4 SEG14 0 0 Input mode 1 Input mode pull up Output mode push pull EREN Alternative function SEG14 4 38 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER P6CONL Port 6 Control Register Low Byte FCH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P6 3 SEG13 0 Input mode 1 Input mode pull up KEE Output mode push pull Alternative function SEG13 5 4 P6 2 SEG12 Input mode Input mode pull up Output mode push pull 1 Alternative function SEG12 3 2 P6 1 SEG11 0 0 Input mode 1 Input mode pull up 0 1 0 Output mode push pull 1 Alternative function SEG11 0 0 Input mode 0 Input mode pull up Output mode push pull Alternative function SEG
294. trolled by the register page pointer PP DFH In the S83C828B C8289 C8285 microcontroller a paged register file expansion is implemented for LCD data registers and the register page pointer must be changed to address other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W Destination register page selection bits Source register page selection bits 0000 Destination Page 0 0000 Source page 0 0001 Destination Page 1 0001 Source page 1 0010 Destination Page 2 Not used for the S3C8285 0001 Source page 2 not used for the S3C8285 0011 Destination Page 3 Not used for the S3C8285 0001 Source page 3 not used for the S3C8285 0100 Destination Page 4 Not used for the S3C8289 5 0001 Source page 4 not used for the S3C8289 5 0101 Destination Page 5 Not used for the S3C8289 5 0001 Source page 5 not used for the S3C8289 5 0110 Destination Page 6 Not used for the S3C8289 5 0001 Source page 6 not used for the S3C8289 5 0111 Destination Page 7 Not used for the S3C8289 5 0001 Source page 7 not used for the S3C8289 5 1000 Destination Page 8 Not used for the S3C8289 5 0001 Source page 8 not used for the S3C8289 5 1001 Destination Page 9 Not used for the S3C8289 5 0001
295. unchanged and is shifted into bit position 6 7 6 0 5 7 Set if the bit shifted from the LSB position bit zero was 1 Z Set ifthe result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 DO R D1 IR Given Register 00 register 02H register 03H 1 SRA 00H gt RegisterOOH OCD C 0 SRA 02H gt Register 02H register 03H 0 In the first example if general register OOH contains the value 9AH 10011010B the statement SRA shifts the bit values in register right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value 11001101B in destination register ELECTRONICS 6 79 INSTRUCTION SET 53 828 828 8289 8289 8285 8285 SRP SRPO SRP1 set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples 6 80 src src src Ifsrc 1 1andsrc 0 Othen RPO 8 7 lt src 3 7 Ifsrc 1 Oandsrc 0 1 then 8 7 lt src 3 7 If src 1 Oandsrc 0 Othen RPO 4 7 lt src 4 7 RPO 3 lt 0 4 7 lt src 4 7 RP1 3 e 1 The source data bits one and zero LSB determine whether to write
296. ure 1 3 S3C828B F828B C8289 F8289 C8285 F8285 Pin Assignments 80 TQFP 121 2 ELECTRONICS 53 828 828 8289 8289 8285 8285 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1 1 S3C828B F828B C8289 F8289 C8285 F8285 Pin Descriptions Pin Description I O port with bit programmable pins Schmitt trigger input or push pull open drain output and software assignable pull ups P0 0 P0 7 are alternately used for external interrupt input noise filters interrupt enable and pending control Share note Pins INTO INT7 I O port with bit programmable pins T1CAP Schmitt trigger input or push pull open drain output and software assignable pull T1OUT T1PWM ups BUZ SO SCK Sl I O port with bit programmable pins ADO AD6 Input or push pull output and software assignable pull ups AD7 VBLDREF I O port with bit programmable pins TBPWM SEG34 Input or push pull output and software TAOUT TAPWM assignable pull ups SEG35 TACLK SEG36 TACAP SEG37 TxD RxD ean ELECTRONICS I O port with bit programmable pins Input or push pull open drain output and software assignable pull ups I O port with bit programmable pins Input or push pull open drain output and software assignable pull ups I O port with bit programmable pins Input or push pull output and software assignable pull ups SEG18 SEG25 78 80 1 5 SEG26 SEG33 76 80 1 3 SEG10 SEG17 I O port with bit programmable pi
297. used for the 53 8289 8285 0 1 Source page 9 not used for the 53 8289 8285 1 1 Source page 15 Others Not used for the S3C828B C8289 C8285 NOTES 1 Inthe S3C828B microcontroller the internal register file is configured as eleven pages pages 0 9 15 The pages 0 9 are used for general purpose register file 2 In the S3C8289 microcontroller the internal register file is configured as eleven pages pages 0 3 15 The pages 0 3 are used for general purpose register file 3 In the S3C8285 microcontroller the internal register file is configured as eleven pages pages 0 1 15 The pages 0 1 are used for general purpose register file 4 The page 15 of S3C828B C8289 C8285 is used for LCD data register or general purpose register 4 42 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CONTROL REGISTER RPO Register Pointer 0 D6H Set 1 Bit Identifier 7 e s 4 3 2 a a o RESET Value 1 1 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the S3C828B C
298. ut clock frequency Clear the timer 0 counter TOCNT Enable the timer 0 interrupt and clear timer 0 interrupt pending condition TOCON is located in set 1 bank 0 at address E3H and is read write addressable using register addressing mode A reset clears TOCON to OOH This sets timer 0 to disable interval timer mode selects the TBOF and disables timer 0 interrupt You can clear the timer 0 counter at any time during normal operation by writing a 1 to TOCON 3 To enable the timer 0 interrupt IRQ2 vector E2H you must write TOCON 2 and TOCON 1 to 1 To generate the exact time interval you should write TOCON 3 and 0 which cleared counter and interrupt pending bit To detect an interrupt pending condition when TOINT is disabled the application program polls pending bit 0 When 1 is detected a timer 0 interrupt is pending When the TOINT sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the timer 0 interrupt pending bit 0 Timer 0 Control Registers TOCON E3H Set 1 Bank 0 R W Timer 0 input clock selection bits Timer 0 interrupt pending bit 000 TBOF 0 No interrupt pending 001 fxx 256 0 Clear pending bit when write 010 fxx 64 1 Interrupt is pending 011 fxx 8 1 fxx Timer 0 interrupt enable bit 0 Disable interrupt 1 Enable interrupt Not used Timer 0 count enable bit 0 Disable counting operation 1
299. ut clock frequency of fxx 1024 and disables all timer A interrupts You can clear the timer A counter at any time during normal operation by writing a 1 to TACON 2 The timer A overflow interrupt TAOVF is interrupt level IRQO and has the vector address DEH When a timer A overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware or must be cleared by software To enable the timer A match capture interrupt IRQO vector DCH you must write TACON 1 to 1 To detect a match capture interrupt pending condition the application program polls INTPND 1 When a 1 is detected a timer A match or capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a to the timer A match capture interrupt pending bit INTPND 1 Timer A Control Register E8H Set 1 Bank 0 R W Timer A input clock selection bits Timer A overflow interrupt enable bit 000 fxx 1024 0 Disable oveflow interrupt 001 fxx 256 1 Enable overflow interrupt 010 fxx 64 011 fxx 8 Timer A match capture interrupt enable bit 100 fxx 0 Disable interrupt 101 External clock TACLK falling edge 1 Enable interrupt 110 External clock TACLK rising edge Counter stop Timer A counter clear bit 0 No effect Timer A operating mode selection bits T Clear Mie timer counter when write 00 Interval
300. west clock divided by 16 is selected as the system clock To select faster speeds load the appropriate values to CLKCON 3 and CLKCON 4 Figure 7 8 System Clock Control Register CLKCON 7 4 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 CLOCK CIRCUIT Oscillator Control Register OSCCON FAH Set 1 bank 0 R W giri S Not used for S3C828B C8289 C8285 mn clock selection bit 0 Main oscillator select Subsystem oscillator select Not used for S8C828B C8289 C8285 Subsystem oscillator circuit selection bit 1 0 Normal circuit for sub oscillator 1 Power saving circuit for sub oscillator Subsystem oscillator control bit 0 Subsystem oscillator RUN 1 Subsystem oscillator STOP Mainsystem oscillator control bit 0 Mainsystem oscillator RUN 1 Mainsystem oscillator STOP NOTES 1 A capacitor 0 1mF should be connected between VREG and GND when the sub oscillator is used to power saving mode OSCCON 7 1 2 OSCCON 7 automatically cleared to 0 when the suboscillator is stopped by OSCCON 2 or the CPU is entered into stop mode in sub operating mode Figure 7 9 Oscillator Control Register OSCCON STOP Control Register STPCON FBH Set 1 bank 0 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction NOTE Before executing the STOP instruction set the STPCON register as 10100101b Otherwise the STOP
301. with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes Description Flags Set 0000 F Always false 1000 Always true 0111 note 1 1111 note NC No carry 0 0110 note 7 Zero 2 1 1110 note NZ Not zero Z 0 1101 PL Plus 6 0 0101 Minus S 1 0100 OV Overflow V 1 1100 NOV No overflow V 0 0110 note EQ Equal Z 1 1110 note NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S V 0 0010 LE Less than or equal Z OR S V 1 1111 note UGE Unsigned greater than or equal 0 0111 note ULT Unsigned less than 1 1011 UGT Unsigned greater than 0 AND Z 0 1 0011 ULE Unsigned less than or equal C OR 2 1 NOTES 1 It indicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 For operations involving unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET INST
302. working register area to support program requirements PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO lt 70H RP1 lt 78H SRP1 48H RPO lt nochange lt 48H SRPO 0A0H RPO lt AOH RP1 lt nochange CLR RPO RPO lt 00H RP1 lt nochange LD RP1 0F8H RPO lt nochange lt OF8H Register File Contains 32 8 Byte Slices 00001 X XX 8 Byte Slice 16 Byte RP1 Contiguous Working 00000XXX 8 Byte Slice Register block RPO Figure 2 9 Contiguous 16 Byte Working Register Block 2 14 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 ADDRESS SPACES F7H R7 8 Byte Slice FOH RO Register File 16 Byte Contains 32 Contiguous 11110 XXX 8 Byte Slices working Register block RPO 7H R15 00000 XXX 8 Byte Slice RO RP1 Figure 2 10 Non Contiguous 16 Byte Working Register Block PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15H respectively SRPO 80H RPO lt 80H ADD RO R1 RO lt RO Ri ADC RO R2 RO RO R2 C ADC RO R3 RO RO R3 C ADC RO R4 RO lt RO R4 C ADC RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this
303. xpandable OBPTM on board program sector Data Memory RAM Excluding LCD display data memory 2560 x 8 bits data memory S3C828B F828B 1024 x 8 bits data memory S3C8289 F8289 512 x 8 bits data memory 53 8285 8285 Instruction Set T8instructions Idle and stop instructions added for power down modes 65 I O Pins e 25 pins 40 pins Sharing with LCD signal outputs Interrupts 8interrupt levels 18 interrupt sources Fast interrupt processing feature 8 Bit Basic Timer Watchdog timer function 4Fkinds of clock source S3C828B F828B C8289 F8289 C8285 F8285 8 Bit Timer Counter A Programmable 8 bit internal timer External event counter function PWM and capture function 8 Bit Timer Counter B Programmable 8 bit internal timer Carrier frequency generator 16 Bit Timer Counter 0 Programmable 16 bit internal timer 16 Bit Timer Counter 1 Programmable 16 bit internal timer External event counter function PWM and capture function Watch Timer Interval time 3 91mS 0 25S 0 55 and 15 at 32 768kHz 0 5 1 2 4 kHz Selectable buzzer output LCD Controller Driver 32 segments and 8 common terminals 1 2 1 3 1 4 and 1 8 duty selectable e Internal resistor circuit for LCD bias Analog to Digital Converter 8 channel analog input 10 bit conversion resolution e 25uS conversion time UART Full duplex serial I O int
304. y Sector Address Register FMSECH FMSECL Set Flash Memory Control Register FMCON to 10100001B Set Flash Memory User Programming Enable Register FMUSR to 00000000 Check the Sector erase status bit whether Sector erase is success or not amp PROGRAMMING Sector Erase SB1 reErase LD FMUSR 0A5H User Program mode enable LD FMSECH 10H LD FMSECL 00H Set sector address 1000H 107FH LD FMCON 10100001B Start sector erase NOP Dummy Instruction This instruction must be needed NOP Dummy Instruction This instruction must be needed LD FMUSR 0 User Program mode disable TM FMCON 00001000B Check Sector erase status bit JR NZ reErase Jump to reErase if fail ELECTRONICS 19 9 EMBEDDED FLASH MEMORY INTERFACE S3C828B F828B C8289 F8289 C8285 F8285 PROGRAMMING A flash memory is programmed in one byte unit after sector erase And for programming safety s sake must set FMSECH and FMSECL to flash memory sector value The write operation of programming starts by LDC instruction You can write until 128byte because this flash sector s limits is 128byte So if you written 128byte must reset FMSECH and FMSECL THE PROGRAM PROCEDURE IN USER PROGRAM MODE Must erase sector before programming Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Control Register FMCON to 01010000B Set Flash Memory Sector Register FMSE
305. y an external or internal interrupt Stop Release Main System Sub system Watch Timer BLD Oscillator Oscillator Circuit Circuit LCD Controller Selector 1 OSCCON 3 Stop OSCCON 0 OSCCON 2 Basic Timer 0 i STOP OSC 1 1 1 4096 Timer Counter i inst gt Watch Timer Frequency BLD STPCON Dividing Circuit t LCD Controller gt SIO UART 1 1 1 11 1 2 1 8 1 16 A D Converter CPU Clock gt IDLE Instruction Figure 7 7 System Clock Circuit Diagram ELECTRONICS 7 3 CLOCK CIRCUIT 53 828 828 8289 8289 8285 8285 SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in the set 1 address D4H It is read write addressable and has the following functions Oscillator frequency divide by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON D4H Set 1 R W og EAEREAEAEVEVENEN shes used Not used must keep always 0 must keep always 0 Oscillator IRQ wake up function bit Divide by selection bits for 0 Enable IRQ for main wake up in CPU clock frequency power down mode 00 16 1 Diable IRQ for main wake up 01 fxx 8 in power down mode 10 fxx 2 11 fxx 1 non divided After a reset the slo
306. y direct manipulation of SYM O nterrupt level enable disable settings IMR register nterrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information EI Interrupt Request Register Polling Read only Cycle RESET Y y IRQO IRQ7 Interrupts Interrupt Priority Register Interrupt Interrupt Mask Register Global Interrupt Control El DI or SYM 0 manipulation Figure 5 4 Interrupt Function Diagram 5 8 ELECTRONICS 53 828 828 8289 8289 8285 8285 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Timer A match capture E8H bank 0 Timer A overflow bank 0 EAH bank 0 Timer B match IRQ1 TBCON F2H bank 0 TBDATAH TBDATAL FOH F1H bank 0 Timer 0 match IRQ2 TOCON bank 0 E4H E5H bank 0 TODATAH TODATAL E6H E7H bank 0 Timer 1 match capture IRQ3 T1CON EBH bank 0 Timer 1 overflow T1
307. y locations 1033H ODDHand1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and is incremented by one 6 lt RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and is incremented by one lt RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 6 55 INSTRUCTION SET 3C828B F828B C8289 F8289 C8285 F8285 LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples 6 56 dst src mr m 1 dst src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src ope 2 14 F2 r r Given RO 77H R6 7 OOH LDCPD RR6 RO RR6 lt RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH LDEPD RR6 RO RR6 lt RR6 1 77H contents of RO is
308. ystemresetpin Tw cstat oscilator prs for sub ok Main oscillator pins P8 0 P8 1 T L O O O c l gt T 17 18 15 16 15 14 13 12 5 Test input it must be connected to Vas Vss Power input pins A capacitor must be connected between Vpp and Vss NOTE Parentheses indicate pin number for 80 TQFP 1212 package 1 8 ELECTRONICS S3C828B F828B C8289 F8289 C8285 F8285 PIN CIRCUITS VDD P Channel N Channel Figure 1 4 Pin Circuit Type A VDD P Channel Data Out Output 4 N Channel Disable Figure 1 6 Pin Circuit Type C ELECTRONICS PRODUCT OVERVIEW VDD Pull up Resistor Schmitt Trigger Figure 1 5 Pin Circuit Type B VDD Pull up Resistor VDD Fe Pull up Enable O I O Data HEN Pin Circuit Output Type C Disable Figure 1 7 Pin Circuit Type D 1 P3 4 P3 5 1 9 PRODUCT OVERVIEW 53 828 828 8289 8289 8285 8285 Pull up Resistor Open drain H lt Resistor Enable Enable Disable Schmitt Trigger Figure 1 8 Pin Circuit Type E 4 PO P1 Pull up Enable Data Circuit Output Disable ADCEN Data ADCEN ADC Select To ADC Figure 1 9 Pin Circuit Type F 1 2 0 2 6 ELECTRONICS 53 828 828 8289 8289 8285 8285 PRODUCT OVERVIEW VDD Pull up Enable Data Output Disable Circuit ol
309. ytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 42 r r 43 r Ir src dst 3 6 44 R R 45 R IR dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register OOH 08H registerO1H 37H and register 08H OR RO R1 gt RO 3FH R1 2 OR RO R2 gt RO 37H R2 O1H registerO1H 37H OR 00H 01H gt RegisterOOH 3FH register 01H 37H OR 01H 00H gt RegisterOOH 08H register 01H OR 00H 02H gt RegisterOOH OAH In the first example if working register RO contains the value 15H and register R1 the value 2AH the statement RO R1 logical ORs the RO and R1 register contents and stores the result in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS 3C828B F828B C8289 F8289 C8285 F8285 INSTRUCTION SET POP Pop From Stack POP Operation Flags Format Examples dst dst lt SP SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 50 R 8 51 IR Given Register OOH 01H register 01H 1BH SPH 0D8H SPL 0D9H OFBH and stack register 55H POP 00H gt Register 55H SP OOFCH POP 00H gt RegisterOOH 01H register 01H 55H

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