56F807 - Freescale Semiconductor
Contents
1. Oty Description Ref Designators Vendor Part s Resistors Continued 3 47K Q R74 R76 R77 SMEC RC73L2A47KOHMJT 1 4700 R78 SMEC RC73L2A4700HMJT 1 10M R1 SMEC RC73L2A10MOHMJT 20 1K O R38 R41 R44 R47 R50 R53 R56 SMEC RC73L2A1KOHMJT R59 R62 R86 R95 R124 14 270 Q R64 R68 R98 R106 SMEC RC73L2A2700HMJT 16 240 R39 R40 R42 R43 R45 R46 R48 SMEC RC73L2A240HMJT R49 R51 R52 R54 R55 R57 R58 R60 R61 1 120 O 1 4W R63 YAGEO CFR 120QBK Potentioneters 7 10K R2 R3 R36 R37 R97 R111 R116 BC MEPCOPAL ST4B103CT Inductors 4 1 0mH L1 L2 L3 L4 Panasonic EXC ELSA35V LEDs 1 Red LED LED1 Hewlett Packard HSMS C650 4 Yellow LED LED2 LED4 LED6 LED8 Hewlett Packard HSMY C650 5 Green LED LED3 LED5 LED7 LED9 LED10 Hewlett Packard HSMG C650 Diodes 3 S2B FM401 D1 D2 D3 Vishay DL4001DICT Capacitors 5 2 2uF 50V DC C1 C3 C18 C24 NICHICON UWX1H2R2MCR2GB 31 0 1uF C7 C17 C23 C29 C31 C33 SMEC MCCE104K2NR T1 C35 C37 C38 C40 C41 C43 C45 C48 C50 C52 C54 C65 C66 1 470uF 16V DC C4 ELMA RV 16V471MH10R 2 47uF 16V DC C5 C6 ELMA RV2 16V470M R 8 470pF C19 C22 C25 C28 SMEC MCCE471J2NO T1 56F807EVM User Manual Rev 3 Freescale Semiconductor Oty Description Ref Designators Vendor Part s Capacitors Continued2. INDEX1 5 0V FILTER HOME 1 GROUND PHASE A PHASE B INDEX HOME Figure 2 16 Zero Crossing Encoder Interface 2 20 CAN Interface The 56F807EVM board contains a CAN physical layer interface chip that is attached to the MSCAN RX and MSCAN TX pins on the 56F807 The EVM board uses a Philips PCA82C250 high speed 1Mbps physical layer interface chip Due to the 5 0V operating voltage of the CAN chip a pull up to 5 0V is required to level shift the Transmit Data output line from the 56F807 A primary J24 and daisy chain J25 CAN connector are provided to allow easy daisy chaining of CAN devices CAN bus termination of 120 ohms can be provided by adding a jumper to JG3 Refer to Table 2 11 for the CAN connector signals and to Figure 2 17 for a connection diagram 56F807EVM User Manual Rev 3 2 24 Freescale Semiconductor 56F807 MSCAN_TX MSCAN_RX CAN Transceiver TXD RXD VCC VREF SLOPE CANH CAN Connector CAN Interface Daisy Chain CAN Connector CANL 5 GND 1 PCA82C250T JG3 CAN Bus Terminator Figure 2 17 CAN Interface Table 2 11 CAN Header Description J24 and J25 Pin Signal Pin Signal 1 NC 2 NC 3 CANL 4 CANH 5 GND 6 NC 7 NC 8 NC 9 N
3. 56F807EVM User Manual Rev 3 Freescale Semiconductor Symbols 12V DC power supply 1 4 Numerics 16 bit 3 3V Hybrid Controller 2 1 4 0Amp power supply 2 13 4 Channel 10 bit Serial D A 2 1 56F807 Technical Data Preface x 64Kx16 bits of Data memory 2 1 64Kx16 bits of Program memory 2 1 8 00MHZ crystal oscillator 2 1 A A D Preface 1x A D Port A compatible peripheral 2 2 Analog to Digital A D Preface ix B Back EMF 2 23 signals 2 15 C CAN Preface ix interface 2 1 CAN bus termination 2 1 CAN bypass 2 1 CAN in Automation CiA Preface ix CAN interface 2 1 CAN physical layer peripheral 2 2 CAN Specification 2 0B Preface x CiA Preface ix CiA Draft Recommendation DR 303 1 Preface x Connector A D 2 33 2 34 Address bus 2 32 CAN 2 36 Data bus 2 33 External Memory Control 2 29 PWM 2 36 SCI 2 34 2 35 SPI 2 35 INDEX Connectors Peripheral Expansion 2 27 Controller Area Network CAN Preface ix D D A Preface ix D A converter 2 17 Data memory 2 5 Debugging 2 8 Development Card 2 1 Digital to Analog D A Preface ix DSP56800 Family Manual Preface x DSP56F801 803 805 807 User s Manual Preface x E Encoder Hall Effect circuits 2 24 Encoder Timer 2 30 Evalation Module EVM Preface ix EVM Preface ix External Memory Control Signal 2 29 external memory expansion connectors 2 2 external oscillator frequency input 2 1 F FSRAM 2 1 2 5 G General Purpose Input and Outpus GPIO Pr
4. 180 960 560 960 80 260 180 i VAS et AS APER YA 1 HOLOHNNOO G SZZEXVN emm l s NE HIA asa 1084954504 5 T 5 a Y Appendix A Rev 3 Freescale Semiconductor A 19 56F807EVM User Manual Rev 3 A 20 Freescale Semiconductor Appendix B 56F807EVM Bill of Material Oty Description Ref Designators Vendor Part s Integrated Circuits 1 DSP56F807FV80 U1 Freescale DSP56F807FV80 5 LM393 U3 U6 U16 National LM393M 1 741 244 9 ON Semiconductor MC74LCX244DW 2 74AC04 U12 U15 Fairchild 74AC04SC 1 MC33269DT 5 0 U10 ON Semiconductor MC33269DT 5 0 1 MC33269DT 3 3 U11 ON Semiconductor MC33269DT 3 3 1 GS72116 U2 GSI GS72116TP 12 1 MAX3245 U13 Maxim MAX3245EEAI 1 MAX5251 U14 Maxim MAX5251BEAP 1 PCA82C250T U8 Philips Semiconductor PCA82C250T 1 74AC00 U18 Fairchild 74ACOOSC Resistors 20 16K Q R8 R11 R16 R19 R24 R29 SMEC RC73L2A16KOHMJT R31 R32 R107 R108 R112 R113 10 1MQ R4 R5 R12 R13 R20 R21 R30 SMEC RC73L2A1MOHMJT R33 R109 R114 18 5 1KQ R6 R7 R14 R15 R22 R23 R34 SMEC RC73L2A5 1KOHMJT R35 R69 R72 R73 R75 R79 R81 R96 R110 R115 12 10K R82 R85 R117 R123 R125 SMEC RC73L2A10KOHMJT 2 510 R70 R71 SMEC RC73L2A510HMJT Appendix B Rev 3 Freescale Semiconductor
5. dNG 8181590 IVNOLLdO NOLLOQGHS d LASHA uod lt lt o O IS 01 9214 Ag e g r LH ZHINO0 8 Nol 1 VA 557424 OSO Appendix A Rev 3 A 3 Freescale Semiconductor A4oul N Wie 2120 9 weibolg V 91n614 3 I q I 5 7 ifi 81 JO 19949 ubiseq qasq euDiseqg 0002 91 1840190 Aepuow ejeq y S9IS01V 9 JequinN ezis A H lu u nooq AYOWAW AVES VIVO 8 NvdOOHud ol 0192 217 087 XV4 0609 Ly 087 8298 euozuy d l l peou 101113 1983 0012 UOISIAIG SI2NPOid pJepuels 450 ct di9tt Je ola gt Azou n 2320 3T9 9TXMVO yu yl 188 984 an 39 H 39 L YM 2189 m W lt lt lt O z ELY AE ET BS lt lsi 0lv en Sd pue 314 91XMT9 ON H IHVSIG NVAS A Ida YNa WWAS NOT LO uadNfnfr 418YN4 vus 56F807EVM User Manual Rev 3 Freescale Semiconductor A 4 S10 98UU09 9S pue ZEZ SY r V eJnDi4 81 jo 1eeug ubiseg 4450 eubisag 0002 ZZ 18qW8A0N Aepuow 91eq V JequinN S91901Y 9 iu unood zIS SHOLO3NNOO 19S ONV cEc SH l 8298 euozuy odwa peoH 101113 1583 0012 012 617 087 XY4 0609 Lp 087 UOISIAIG SIIMPOIH pJepuels 450 z E MNUHVSIQ cec sa L
6. g v 21n614 3 q ei gl jo 8 19949 ubisag 0490 eubisag 0002 pz 1990120 Aepsan ejeq a JequnwN azi od S91901Y69 wesch IS NOI19313Q LINVA 39V11OA H3AO QNV E INN AYVANOOIS PHIL 0192 6 ip 087 XV4 8298 euozuy adway peog 1011131583 0012 UOISIAIG SIONPOIH piepuels dsa 0609 6 Lv 087 0H ASNAS LINYA T WMd 454 A et NOlLOdLud LINYA HOVLOA dG4AO INN qad n DNISSOJO OUAZ Odd 601 qadan WMd Odd 001 awa YOVE O HSVHd A0 S anio T 91 999 aa S A ens HSNHS INN AMVGNOOHS 9L ella AISIHNI 244 ENS NV eu ASVGONOO HS 101 HHdNNC Tawa dad i84 gaan NOD Tetris Arepuoo s ast TVINSS ENS WMd oda ENS AOLOANNOD INN AYWINODAS SSOND ONSZ Dad ENS AWA HOVE v HSVHd 03 V 3W A SNISSOND OYAZ g ESVH X 2 ENS yx ONISSON ONHZ V HSVH4 SSNS SN IVNSdWSI SAING HOLON HSNES INFIANO E HSVHd YOLOW aam 508 20 INA AAVONODES na x8 ens r 262 258 3W3 HE ENS awa yows g msvud wa ys ens 8816 0 n 96 SE Da X 0932 ENS ANISSONO ONSZ D goung 0437 ENS ve _ ze e S5049 0432 24d ENS LIHIHNI Dad Ens ad ENS NEE o s lt 98d TOULNOD Sg HATIA YOLOW ENV 9 92 SI OHd ENS HSNHS 14444 0 D SSVHd NOLONW S 8Hd EnS
7. 155 0 32 AYVONODIS L OLSZ Elp 087 vi 0609 Lp 087 v8298 euozuy d l r peoy 101113 1583 0017 UOISIAIG SIonpo4d pJepuels 450 ONISSOHO OHHZ 6 INn AHVOIONOOHS 390 20 uuo vc uuo vc Z I3WOH lt lt E 198 098 300 L T Le uuo yz uuo bz 654 898 SH 9 x ouaz ens ECH ER 300 y 929 8 X ouaz ens D v x ouaz ens A0 8 LOHZJAJH IIVH WHSGOONH Z OHHZ 2 LOHNNOO A0 S HNOH 9 XHUdNI S HSVHd E NId NX HSVHa GNDONO 2 A0 S T aOLOANNOD 4u4dOONH AYAVUINODHS 56F807EVM User Manual Rev 3 Freescale Semiconductor A 14 510100 2 uoisuedX3 3404 pL y 91n614 3 q T 91 jo pl 1eeug ubisag 1490 euDiseq 0002 91 4840190 Aepuow ejeq 8 S91901Y69 vw 229 T Ag o 8 4 a sad 9 s vad SHOLOANNOO NOISNVdX3 LHOd 490 Bn 1 n tad z 004 012 617 087 vi 0609 Lp 087 ET 18299 euozuy duel peoy 101113 1583 0016 UOISIAIG PIEPUEIS 45
8. 10 0 01uF C32 C34 C36 C39 C44 C46 C49 SMEC MCCE103K2NR T1 C53 C55 C57 4 1 0uF 50V DC C60 C63 NICHICON UWX1H010MCR1GB Jumpers 8 3 x 1 Bergstick JG1 JG2 JG5 J14 J15 JG16 J16 SAMTEC TSW 103 07 S S JG17 4 4 x 2 Bergstick JG11 JG15 J23 J26 SAMTEC TSW 104 07 S D 6 1 x 2 Bergstick JG3 JG4 JG6 JG7 JG8 JG9 SAMTEC TSW 102 07 S S 4 3 x 3 Bergstick JG10 JG12 JG13 JG14 SAMTEC TSW 103 07 S T 2 9 x 2 Bergstick J6 J7 SAMTEC TSW 109 07 S D 3 6 x 1 Bergstick J18 J21 J22 SAMTEC TSW 106 07 S S 6 5 x 2 Bergstick J9 J12 J17 J20 J24 J25 SAMTEC TSW 105 07 S D 2 4 x 1 Bergstick J13 J19 SAMTEC TSW 104 07 S S 3 7 x 2 Bergstick J3 J10 J11 SAMTEC TSW 107 07 S D 2 6 x 1 MTA J4 J5 AMP MTA 640456 6 1 6 x 2 Bergstick J8 SAMTEC TSW 106 07 S D 2 20 x 2 Shrouded J1 J2 3M 2540 6002UB Test Points 8 1 x 1 Bergstick TP1 TP8 Samtec TSW 101 07 S S Crystals 1 8 00MHz Crystal Y1 CTS ATS08ASM T Connectors 1 DB25M Connector P1 AMPHENOL 617 C025P AJ121 1 2 1mm coax P2 Switch Craft RAPC 722 Power Connector 1 DE9F Connector P3 AMPHENOL 617 C009S AJ120 Switches 5 SPST Pushbutton S1 S5 Panasonic EVQ PADO5R 1 SPDT Toggle S6 C amp K GT11MSCKE Appendix A Rev 3 Freescale Semiconductor Qty Description Ref Designators Vendor Part s Transistors 1 2N2222A Q1 ZETEX FMMT2222ACT Miscellaneous 28 Shunt SH1 SH28 Samtec SNT 100 BL T 6 Rubber Feet RF1 RF6 3M SJ5018BLKC
9. 147 CEC SH IV33SvzEXVIN 34039404 H3dWNr NMOGLNHS cEc SH HOLDENNOD 1 T p anv NI ZEZ SU lla H z 0158 x neg 499 1nOSH rr LIL mom 1noru 911 NISH 21 EN NGU nisy Lungen LT SIL mum Neu MEN 1nozu tr vil vs 7 Nil 1004 ter gt gt SIA alnoz8 LL 121 axa eu CA 10061 NIEL Loe sio nozi Her E s ENOL MILL rer lt oaxi usa 420 Ed ano 29 LK ano A gt a 692 4 25 199 P 19 z n 299 t ML anti 09 10 g 1099 EN AEE 3 a 9 8 v Appendix A Rev 3 A 5 Freescale Semiconductor 2 y q 9uueyo y jenas Bngag s V inBij 3 I q I 5 8 ii gl Jo sS 1999 ubisag qasq s ubis q 0002 91 1990120 AEpUON ejeq y JequinN azi A H SOLSOLVES juauinooq IS V G TANNVHO 11435 ONEGAG ail 0192 217 087 XV4 0606 61 087 v8298 euozuy d l r peoy 101113 1584 0017 UOISIAIG SIINPOIH pJepuels 450 01 168 YA VAG E ger YOLOANNOO 0 1VIH3S A 4 81929 INDV an9a Lo su 0 gr 040 m 083 ALS 204 gr Jino 964 o1no yI 19 o1s4 yr 283 59 yK rad sq 09438 JBIAtO av134 p 9893 3198 pr 1108 L YT gino 1100 gt gt osin e gj VINO NIQ 1900 zi vai GGA z A y n Ag e 56F807EVM User Manual Rev 3 Freescale Sem
10. 56F807 Evaluation Module User Manual 56F800 16 bit Digital Signal Controllers DSP56F807EVMUM Rev 3 07 2005 freescale com Ya Ya freescale semiconductor TABLE OF CONTENTS Preface vii TE EE vii UN AI ds vil QUEEN ROSE ais daa doch qb AR booa Fede geg vii Notation Conventions vil Definitions Acronyms and Abbreviations ix 12770 abad HH x Chapter 1 Introduction LI JOF8SUTEVYM ERHALE 1 1 1 2 56F807EVM ConfigurationJumpers 1 2 1 AA OD AMAS 1 4 Chapter 2 Technical Summary 2 AR 2 3 22 E 2 5 23 RS 232 Serial Communications 2 6 Ld o KIA parda Aaa 2 7 2 ULU aya ya So lit WA AWA ULI Citons 2 7 27 Deme LEDS dad A AAA E 2 8 27 Deme ono o mr rrr 2 8 ITA o 2 9 2 7 Parallel JTAG Interface Connector 2 10 25 IIIA 2 11 PS AA B r sa ER 2 12 10 7 o EE 2 13 213 Primary UNI INIRE sada dd bad EM EE RS be d dA bada ba ad 2 14 2 12 Secondary UNI 3 nterface Los carreta AO HER EROR AERE br ER DG anaes 2 15 2 13 General Purpose Switches and Run Stop Switch 2 16 2 14 Serial 10 bit 4 channel D A Converter 2 17 2 15 Motor Control PWM Signals and LEDs 2 18 2 16 Mo
11. 01V3 lt srov V3NOH IX3QNI 183SVHd DEED 03WOH 0X30N1 083SVHd 0v3svHd aL zar TEL 081 ew 241 K oi Appendix A Rev 3 A 15 Freescale Semiconductor 99811934 NVI peeds uBiH sSL V inBij3 3 I q I o 8 V ja 81 JO CL l uS uBiseq qdSq s ubis q 0002 91 1840190 Aepuow ejeq y JequnnN azi A H S9LSOLVES juauinooq IS 4ov4u41NI NYO d44458 H H L 0192 217 087 XV4 0609 Ly 087 v8298 euozuy d l r peoy 101113 1584 0017 UOISIAIG SI2NPOid pJepuels 450 TNVO 021 698 8 sna NYD HNVO cor 1052928V9d GND 34018 Le TNVO At HNVO ei 1 43uA gt gt XH NVOSN DOA axl lt XI NVOSW YJOLOHNNOO Sna NWO NIVHO ASIVG HOLOHNNOO SA NWO A s a 9 8 v Freescale Semiconductor 56F807EVM User Manual Rev 3 A 16 10 98UU09 9Y LI pue 396181 JSOH elt I lieied 9L v 9INBI4 El q fi 81 JO 9 jeeus ubiseg 0490 Jeubiseq 0002 go s qul s q eps ni ejeg 8 _ J9qUuInN azi as rer S9190 Y69 well IS 22 HOLO3NNOO DVLP ANY 39VAH3INI 135uV1 ISOH OVIT 1311 4 SNL 0152 217
12. 56F807EVM board contains a Primary and Secondary Quadrature Encoder Hall Effect interface connected to the hybrid controller s first and second Quad Encoder input ports The circuit is designed to accept 3 0V to 5 0V encoder or Hall Effect sensor inputs Input noise filtering is supplied on the input path for the Quadrature Encoder Hall Effect interface along with additional noise rejection circuitry inside the device Figure 2 16 contains the primary encoder interface The secondary encoder interface is a duplicate of the primary encoder interface Technical Summary Rev 3 Freescale Semiconductor 2 23 2 19 Zero Crossing Detection An attached UNI 3 motor drive board contains logic that can send out pulses when the phase voltage of an attached 3 phase motor drops to zero The motor drive board circuits generate a 0 to 5 0V DC pulse via voltage comparators The resulting pulse signals are sent to a set of jumper blocks shared with the Encoder Hall Effect interface The jumper blocks allow the selection of Zero Crossing signals or Quadrature Encoder Hall Effect signals When in operation the controller will only monitor one set of signals Encoder Hall Effect or Zero Crossing Figure 2 16 contains the Zero Crossing and Encoder Hall circuits ZERO_X_A gt gt ZERO X B5 ZERO X C5 56F807 PHASEA1 FILTER PHASEB FILTER FILTER
13. 8 Schematic Diagram of the Power Supply Technical Summary Rev 3 Freescale Semiconductor 2 13 2 11 Primary UNI 3 Interface Motor control signals from a family of motor driver boards can be connected to the EVM board via the Primary UNI 3 connector interface The Primary UNI 3 connector interface contains all of the signals needed to drive and control the motor drive boards These signals are connected to various groups of the hybrid controller s input and output ports A D TIMER and PWM Port A The header JG14 is used to select between the Back EMF and Motor Phase Current signals Refer to Table 2 6 for the pin out of the Primary UNI 3 connector J1 Table 2 6 Primary UNI 3 Connector Description Ji Pin Signal Pin Signal 1 PWM_AT 2 Shield 3 PVVM AB 4 Shield 5 PVVM BT 6 Shield 7 PVVM BB 8 Shield 9 PWM CT 10 Shield 11 PWM_CB 12 GND 13 GND 14 5 0V DC 15 5 0V DC 16 Analog 3 3V DC 17 Analog GND 18 Analog GND 19 Analog 15V DC 20 Analog 15V DC 21 Motor DC Bus Voltage Sense 22 Motor DC Bus Current Sense 23 Motor Phase A Current Sense 24 Motor Phase B Current Sense 25 Motor Phase C Current Sense 26 Motor Drive Temperature Sense 27 NC 28 Shield 29 Motor Drive Brake Control 30 Serial COM 31 PFC PWM 32 PFC Inhibit 33 PFC Zero Cross 34 Zero Cross A 35 Zero Cross B 36 Zero Cross C 37 Shield 38 Back EMF Phase A Sense 39 Back EMF Phase B Sense 40 Back EMF Ph
14. 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the su
15. SENSE PHA IS 205 AAA Figure 2 12 FAULTA1 Selection Circuit Table 2 9 FAULTA1 Source Selection Jumper JG1 Comment 1 2 Phase A Over Current Sense input 2 3 DC Bus Over Current Sense input 56F807EVM User Manual Rev 3 2 20 Freescale Semiconductor Motor Protection Logic 2 16 2 Secondary UNI 3 Motor Protection Logic The Secondary UNI 3 interface is similar to the Primary UNI 3 interface The Secondary UNI 3 Over Voltage signal is connected to the hybrid controller s PWM group B s fault input FAULTBI The three Secondary UNI 3 Phase Over Current signals are connected to the device s PWM group B fault inputs i e FAULTB1 FAULTB2 and FAULTB3 The Secondary UNI 3 interface is similar to the circuits contained in Figure 2 13 The FAULTBI input can be sourced from the Phase A Over Current circuit or the DC Bus Over Current circuit Jumper JG16 provides the selection reference Figure 2 14 and Table 2 10 DC BUS VOLTAGE SENSE V_sense_DCB gt EXAMPLE DC PHASE CURRENT SENSE 5 0V Figure 2 13 DC Bus Over Voltage and Phase Over Current Detection Circuits Technical Summary Rev 3 Freescale Semiconductor 2 21 DC BUS CURRENT SENSE sense DCB gt gt N7 lt l LM393 PHASE A CURRENT SENSE PHA IS gt AAA e TS Figure 2 14 FAULTB1 Selection Circuit Table 2 10 FAULTB1 Source Selecti
16. Table 2 5 shows the pin out for this connector When using the parallel JTAG interface the jumper at JG4 should be removed as shown in Table 2 4 DB 25 Connector Parallel JTAG Interface 56F807 TDI IN OUT TDI TDO OUT IN TDO P TRST OUT TRST TMS OUT TMS TCK OUT TCK P RESET OUT RESET Jumper Removed Enable JTAG I F Jumper Pin 1 2 Disable JTAG I F Figure 2 5 Block Diagram of the Parallel JTAG Interface Table 2 5 Parallel JTAG Interface Connector Description P1 Pin Signal Pin Signal 1 NC 14 NC 2 PORT_RESET 15 PORT_IDENT 3 PORT_TMS 16 NC 4 PORT_TCK 17 NC 5 PORT_TDI 18 GND 6 PORT_TRST 19 GND 56F807EVM User Manual Rev 3 2 10 Freescale Semiconductor External Interrupts Table 2 5 Parallel JTAG Interface Connector Description Continued P1 Pin Signal Pin Signal 7 NC 20 GND 8 PORT IDENT 21 GND 9 PORT VCC 22 GND 10 NC 23 GND 11 PORT TDO 24 GND 12 NC 25 GND 13 PORT CONNECT 2 8 External Interrupts Two on board push button switches are provided for external interrupt generation as shown in Figure 2 6 S2 allows the user to generate a hardware interrupt for signal line IRQA S3 allows the user to generate a hardware interrupt for signal line IRQB These two switches allow the user to generate interrupts fo
17. Yo 62 S VHd ENS SNES 14444 0 V ESVHd HOLON A BNN SOT S I ms a Hi SOT S A ens d 8 Ll Ka a si ND y eb o on Sanmad sj WMa xl 6 YERMd 12 Md 8 EgNMd wma 9 s 46 28 4 zana y VENA sv xd e L OgWMd W Appendix A Rev 3 A 9 Freescale Semiconductor sJeduinf pue souaimMs asodng 219U99 Jaen 6 v 91n614 3 a I 9 8 v l 81 JO 6 1999 ubisag 4490 s ubis q 0002 91 1990190 Aepuow ejeq y Aen S91901V 9 M naco 9ZIS 401 suadWnfr ANY S3HOLIMS 3804 4 1YH3N35 Y3SN lll 019 6 ip 08h KVA 0609 1 087 iiis v8298 euozuy d l r EI peoy 101113 1583 0012 rad UOISIAIG SI2NPOid pJepuels 450 01 208 AE CT suzan SHVMLIOS T 904 lt lt uem JOLS NNY Or cel 0d SHHOLIMS HSOdund VMANMH x dunnr z r aaa d TT aa rad 0218 99 Z MS lt lt O vs t MS d 3 q 9 8 v 56F807EVM User Manual Rev 3 Freescale Semiconductor A 10 10399198 mduj Bojeuy aBe3J0A JIN3 1989 343 In 9SByg JOJOW 0L V 9INBIY 81 jo OL Jeeus ubiseg 4450 eubisag 0002 91 1840190 Aepuow ejeq y J qunN azi S91901V 9 jueumood IS HOLO43 13S LNdNI DOIVNY ADVLIOA AWSA MOVE LNAYYND ASVHd HOLOW oul 0192 6 7 087 XV4 0609 17 087 8298 euozuy odwa peoy 101113 1583 0012 UOI
18. attach his own Port D GPIO compatible peripheral J23 Connector to allow the user to attach his own Port E GPIO compatible peripheral J17 Connector to allow the user to attach their own A D Port A compatible peripheral J9 Connector to allow the user to attach his own A D Port B compatible peripheral J12 56F807 s external memory expansion connectors J6 J7 and J8 On board power regulation from an external 12V DC supplied power input P2 Light Emitting Diode LED power indicator LED10 Three on board real time user debugging LEDs LED1 3 Six on board Primary PWM monitoring LEDs LED4 9 Primary UNI 3 Motor interface J1 Encoder Hall Effect interface and selector JG12 Over Voltage sensing U16 Over Current sensing U3 Phase Current sensing U3 and U4 Back EMF sensing and selector JG14 56F807EVM User Manual Rev 3 2 2 Freescale Semiconductor 2 1 56F807 Temperature sensing Zero Crossing detection and selector JG14 Pulse Width Modulation Secondary UNI 3 Motor interface J2 Encoder Hall Effect interface and selector JG13 Over Voltage sensing U16 Over Current sensing U6 Phase Current sensing US and U6 Back EMF sensing and selector JG10 Temperature sensing Zero Crossing detection and selector JG10 Pulse Width Modulation Manual RESET push button S1 Manual interrupt push button for IRQA S2 Manual interrupt pus
19. oxu woo terres Azeutid aman n AAO V ESWHA INN xepuooes 811nV4i LaLinyi XL RR lax SEMITOA gaan INN Azepuos s 0811 0g11nv4 2851 2851 00 lt 00X8 Las 1881 00 1 5 00x 0891 0851 S WMd IND xepuooss SSNMd C 98 1 1 14 OLSH H OLSH b WMd INn Azepuos s v8 Md amp C PWM 13534 lt 13838 Wa INn xepuooes 8INMd amp Fr t SAMd Z WMd IND Axepuooes CRW MA amp 2814 0319 ma 0315 T Wd E INQ repuooes I8WWd 814 WLX3 GE 0 WMd IND Azepuos s 09WMd 0814 WX RH TAX VAE E 0 1008X s 10081X3 NV VNV 9NV 9VNV goul HSNHS anal tn 9 SVNV vou D HSNSS ANN A8 1 cn YNY PNY H HSNHS awa X I en Axeurid ENV EVNY V ASNAS awa air En Axeuriq 2 eVNV god asnas I en NV IVNV SOd ena A tn xewpxg NV NISSONO ONEZ 03WOH 03WoH 0X30NI OX30NI 108333 TWH Og3SYHd 08Hd NIGOONZ ANVHINd Oy3SVHd OVHd Lem gau O ASWHd t IND EVLINVA EVIINVA Am XSAO 8 geng t IND 2711 2411 3 ININIM XSAO V SSVHd t IND Azewtza 11 WE AITOA HHAO t IND xeurza ovianvd 2451 2451 ISI 1781 0951 0951 S WMd IND Azeurza SVINMd C q SWIM Y WMd t IND pYINMd s VV VNM d E wa INn amp EWM zwa E INQ Axeura 2VIAMd r CY Md Tuma E INQ reurza IV Md 6 T
20. profile Quad Flat Pack MPIO Multi Purpose Input and Output Port shares package pins with other peripherals on the chip and can function as a GPIO OnCE On Chip Emulation a debug bus and port created by Freescale to enable designers to create a low cost hardware interface for a professional quality debug environment PCB Printed Circuit Board PLL Phase Locked Loop PWM Pulse Width Modulation RAM Random Access Memory ROM Read Only Memory SCI Serial Communications Interface SPI Serial Peripheral Interface Port SRAM Static Random Access Memory UART Universal Asynchronous Receiver Transmitter Preface Rev 3 Freescale Semiconductor ix References The following sources were referenced to produce this manual 1 DSP56800 Family Manual DSP56800FM Freescale Semiconductor 2 DSP56F801 803 805 807 User s Manual DSP56F801 7UM Freescale Semicon ductor 3 56F807 Technical Data DSP56F807 Freescale Semiconductor 4 CiA Draft Recommendation DR 303 1 Cabling and Connector Pin Assignment Version 1 0 CAN in Automation 5 CAN Specification 2 0B BOSCH or CAN in Automation 56F807EVM User Manual Rev 3 x Freescale Semiconductor Chapter 1 Introduction The 56F807EVM is used to demonstrate the abilities of the 56F807 and to provide a hardware tool allowing the development of applications that use the 56F807 The 56F807EVM is an evaluation module board that includes a 56F807 part peripheral expansion con
21. the operating mode of the hybrid controller as it exits RESET Refer to the DSP56F801 803 805 807 User s Manual for a complete description of the chip s operating modes Table 2 2 shows the two operation modes available on the 56F807 Table 2 2 Operating Mode Selection Operating Mode JG7 Comment 0 1 2 Bootstrap from internal memory GND 3 No Jumper Bootstrap from external memory 3 3V Technical Summary Rev 3 Freescale Semiconductor 2 7 2 6 Debug LEDS Three on board Light Emitting Diodes LEDs are provided to allow real time debugging for user programs These LEDs will allow the programmer to monitor program execution without having to stop the program during debugging refer to Figure 2 4 User LEDI is controlled by Port B s PBO signal User LED2 is controlled by PB1 User LED3 is controlled by PB2 Setting PBO PBI or PB2 to a Logic One value will turn on the associated LED 56F807 INVERTING BUFFER RED LED PBO SK YELLOW LED RA GREEN LED AN Figure 2 4 Schematic Diagram of the Debug LED Interface 2 7 Debug Support The 56F807EVM provides an on board Parallel JT AG Host Target Interface and a JTAG interface connector for external Target Interface support Two interface connectors are provided to support each of these debugging approaches These two connectors are designated the JTAG connector and the Host Parallel Interface Conn
22. vio k 24 x lt sI oHa Ens 6811 128 928 y 68 HSNHS 170 4 vg JLNHdHH OO O HSVHda ECH INN AYVANODHS ARE NL eu 338 LINI ENS m 91 210 y r 1661 E lt SI Dud ens zg11nv4 lt lt l ely Li 24 HSNHS LINYA s 4 HSVHd siu t INQ AHVGINOOUS 33H IWITT ENS m W Cu T ED y 010 y r reeu 7 T lt SI vHd ens SI VHd S y 4 l v n y TH ASNES LINYA avs P LNHHHOO V HSVHA 18 INN AYVUNODAS EM 01 WL Su 338 LIWN ENS H TV ASNS LINYA LNSNWN 0O 808 Ja LNAHUND V HSVHd INN 4 iyimnva K bor TV ASNAS LINWA LNSHH O HHAO S08 2G t INQ 4 tV HSNHS LINWA ILNSHH O O ASWHd INn 4 CV HSNHS LINWA 4 ASWHd t INQ 4 IV SNAS LINWA LNAJAND V HSVHd INn 4 Ce 01 y TWiT 4320 184 984 z mO a 4 gen S VHd d ars A0 Sr veu AE an anyo Net y r 99 91 CINY NI ocd 62H m an i ji EI BEI gL 2 45 siToHa en gvi1nv3 you un ys 224 AES Ki og 438 LIMIT T EN s 2 l y r 24 s eua en evi1nv3 218 gu Li ys FLH EI z 338 LIN TEN nus I EL ED EDD een amp si vHd en T su ST VHd d ven T ys 98 A0 Sr AEE RI vu q AOL 334 LIWA En eu NUS v 56F807EVM User Manual Rev 3 Frees
23. 0 Pin Signal Pin Signal 1 PWMAO 2 PVVMA1 3 PWMA2 4 PVVMA3 5 PVVMA4 6 PVVMA5 7 FAULTAO 8 FAULTA1 9 FAULTA2 10 FAULTA3 11 ISAO 12 ISA1 13 ISA2 14 GND 56F807EVM User Manual Rev 3 2 36 Freescale Semiconductor Test Points 2 22 18 PWM Port B Expansion Connector The PWM Port B is attached to this connector Refer to Table 2 29 for the connection information Table 2 29 PWM Port B Connector Description 411 Pin Signal Pin Signal 1 PWMBO 2 PWMB1 3 PWMB2 4 PWMB3 5 PWMB4 6 PWMB5 7 FAULTBO 8 FAULTB1 9 FAULTB2 10 FAULTB3 11 ISBO 12 ISB1 13 ISB2 14 GND 2 23 Test Points The 56F807EVM board has a total of eight test points Four test points are located near the breadboard area 3 3VA AGND 3 3V and GND Three test points are located near the Primary UNI 3 connector J1 15VA GND and 15VA The final test point GND is located in the upper left corner of the board Technical Summary Rev 3 Freescale Semiconductor 2 37 56F807EVM User Manual Rev 3 2 38 Freescale Semiconductor Appendix A 56F807EVM Schematics Appendix A Rev 3 Freescale Semiconductor A 1 10SS9901d 208499 L V nBid 3 q 01 muy 8l jo L 19949 ubisag 0480 ueufiseq 0002 91 1900190 Aepuoy ejeq S91901V 9 Joqunn jueunooq azis 105589014 2084934584 enu 0192 617 087 XV4 18299
24. 04 8 1404 T A E O 01 6 18d 8 1 98d 3 1404 S d 9 E vad NEO 0 6 ead y zgd Laa 8 H OSIN 98a bad e sad 9 8 M10S vua y 20 101 zaa nee Tad e L 00 1 osa 21 NV T 0105 T z Mee z oxu 8 1104 2 E 2 a v asa T K XL NVOSW oaxi istic i 8 SINV 24 8 H LENY NV 9 S Hun Bd Y 6NY Dn z 1 NY Nu A z ofa asa 6811 3 2811 VAS E O 0 5 LeLinyi 0g11nv3 NV 8 1 Env S8WMd rad 9 s NV B i INY Lou 08WMd NY z ONY 7 SP sna viva UE TONINOO ssssadv T A s q Tig AE 0 H El 1N3A3 01830 0 6 m 55 Gia 015 8 0 6 13938 9 s a 8 L SI td H g 20 9r iq 0d ZP 1170143 lt Ist ola T G ANNVH YAWIL 8 THNNVHO HHWIL T 9 9 S o ee S contet 601 t e 201 z LOL 7 L 001 t F _ V HENNVHO MSHWIL Sp 5 D TANNVHO AWIL hores v v 8 ee e 91 e 001 L s r W las T TIOS HE b lt os z oxu z osn L amp ax L K ISO vit TAMA t 2451 Ls H 0751 0 6 2V110V3 inva 8 L WM SYNMd 9 9 EYNMd 2YNAd IYNMd z L OYNMd 508 ssasqav T AO 8 11 m 3 hw EI an HY LIN 0L 6 DIN 8 1 EN nj 9 S v Sv vV tv z 1 zV IN Ov EIE 91
25. 087 0609 6 17 087 t 13299 euozuy adwa 918 gul peog 1011131583 0012 Agee UOISIAIG s onpold PIEPUES 480 002YP2 002YP2 xojoeuuo SVLD YES 1981 fM l E 2 iss 10 1383H d 9 S yok szy amio 8 1 S r 135307 EDD 002YP2 13834 r lt mul SK yes or 6 8 Net AS Et 5 atqesta 395101 3S0H paeog uo uis T wszaa E 2 por z 57 103NNO0 1804 11H ops or an9 92 jo uno 19 o o amp oM 00 1409 FT al a ys Recht 2 4 m vz PAZ by r 99 LHOd 69H 4 Acet Or EVE eaz y ozz r oF val ee en 894 30 1804 zr 1SEL T7 Se We r DT ISHI 1HOd y Tres n m m PAL yi Ey Er TL 1804 i s l EAL evi o WoL TT y WoL 180d Y ol gr 241 rei Le 02 RE SWI 1804 Jee ar tA iyi 998 Lo 13534 d m 13534 1804 NS e 042 sou IN30T 1804 ozz rou 20eJ18quI VIC TelTezed Appendix A Rev 3 A 17 Freescale Semiconductor a Y UP Sdl tdl edi LNIOd 1541 LNIOd 1541 LNIOd 1531 GNnod DO TVNY VA 20401 ani LO692660W ae av38 3114434 A minoa ano Ly Lil 1002 NIA E 95 vn L
26. 13 A12 14 A13 15 A14 16 A15 17 GND 18 3 3V 56F807EVM User Manual Rev 3 2 32 Freescale Semiconductor Peripheral Connectors 2 22 10 Data Bus Expansion Connector The 16 bit Data bus connector contains the device s external memory data signal lines Refer to Table 2 21 for the Data bus connector information Table 2 21 External Memory Address Bus Connector Description J7 Pin Signal Pin Signal 1 DO 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 D9 11 D10 12 D11 13 D12 14 D13 15 D14 16 D15 17 GND 18 3 3V 2 22 11 A D Port A Expansion Connector The 8 channel Analog to Digital conversion Port A is attached to this connector See Table 2 22 for the connection information Table 2 22 A D Port A Connector Description J9 Pin Signal Pin Signal 1 ANO 2 AN4 3 AN1 4 AN5 5 AN2 6 ANG 7 AN3 8 AN7 9 GNDA 10 3 3VA Technical Summary Rev 3 Freescale Semiconductor 2 33 2 22 12 A D Port B Expansion Connector The 8 channel Analog to Digital conversion Port B is attached to this connector Refer to Table 2 23 for the connection information Table 2 23 A D Port B Connector Description 412 Pin Signal Pin Signal 1 AN8 2 AN12 3 AN9 4 AN13 5 AN10 6 AN14 7 AN11 8 AN15 9 GNDA 10 3 3VA 2 22 13 Serial Communications Port 0 Expansion Connector The Serial Com
27. 3 8 AGND Technical Summary Rev 3 Freescale Semiconductor 2 17 2 15 Motor Control PWM Signals and LEDS The 56F807 has two independent groups of dedicated PWM units Each unit contains six PWM three Phase Current sense and four Fault input lines PWM group A s PWM lines are connected to the UNI 3 interface connector and to a set of six PWM LEDs via inverting buffers The inverting buffers are used to isolate and drive the controller s PWM group A s outputs to the PWM LEDs The secondary PWM signals are routed to the Secondary UNI 3 connector The PWM LEDs indicate the status of PWM group A signals as shown in Figure 2 11 PWM Group A and B signals are routed out to headers J10 and J11 respectively and are available for use by the end user 56F807 UNI 3 PWMAO gt gt PWMAO PWMA1 gt gt PVVMA1 PWMA2 gt gt PWMA2 PWMA3 gt gt PWMA3 PWMA4 gt gt PWMA4 PVVMA5 22 PVVMA5 3 3V LED4 YELLOW LED e PHASE A TOP LED5 GREEN LED lt 4 PHASE A BOTTOM LED LED6 BUFFER YELLOVV LED 4 PHASE B TOP LED7 GREEN LED 74 4 PHASE B BOTTOM LED8 YELLOW LED 4 PHASE c TOP LED9 GREEN LED 4 PHASE C BOTTOM Figure 2 11 PVVM Group A nterface and LEDs 56F807EVM User Manual Rev 3 2 18 Freescale Semiconductor Motor Protection Logic 2 16 M
28. 3 RXD1 5 PE4 SCLK 6 PE5 MOSI 7 PE6 MISO 8 PE7 ss 9 GND GND 10 3 3V 3 3V 2 22 4 External Memory Control Signal Expansion Connector The External Memory Control Signal connector contains the device s external memory control signal lines Refer to Table 2 15 for the names of these signals Table 2 15 External Memory Control Signal Connector Description J8 Pin Signal Pin Signal 1 RD 2 IRQA 3 WR 4 RQB 5 PS 6 RESET 7 DS 8 RSTO 9 CLKO 10 DE 11 GND 12 3 3V Technical Summary Rev 3 Freescale Semiconductor 2 29 2 22 5 Primary Encoder Timer Channel A Expansion Connector The Primary Encoder Timer Channel A port is an MPIO port attached to the Timer A expansion connector The port can act as a Quadrature Decoder interface port or as a general purpose Timer port See Table 2 16 for the signals attached to the connector Table 2 16 Timer A Connector Description J18 Pin Signal Alternate 1 TAO PhaseA0 2 TA1 PhaseB0 3 TA2 INDEXO 4 TA3 HOMEO 5 3 3V 3 3V 6 GND GND 2 22 6 Secondary Encoder Timer Channel B Expansion Connector The Secondary Encoder Timer Channel B port is an MPIO port attached to the Timer B expansion connector The port can act as a Quadrature Decoder interface port or as a general purpose Timer port Refer to Table 2 17 for the signals attached to the connector Table 2 17 Timer B Connect
29. C 10 NC Technical Summary Rev 3 Freescale Semiconductor 2 25 2 21 Software Feature Jumpers The 56F807EVM board contains two software feature jumpers that allow the user to select User Defined software features Two GPIO port pins PDO and PD1 are pulled high with 10K ohm resistors on JG16 and JG17 Attaching a jumper will ground the respective Port D signal line see Figure 2 18 56F807 User Jumper 0 JG16 1 2 3 User Jumper 1 JG17 Figure 2 18 Software Feature Jumpers 56F807EVM User Manual Rev 3 2 26 Freescale Semiconductor 2 22 Peripheral Connectors The EVM board contains a group of Peripheral Expansion Connectors used to gain access to the resources of the 56F807 These signal groups have Expansion Connectors Port B Port D Port E External Memory Control Encoder A Timer Channel A Encoder B Timer Channel B Timer Channel C Timer Channel D Port A Address Bus Data Bus A D Input Port A A D Input Port B Serial Communications Port 0 Serial Communications Port 1 Serial Peripheral Port PWM Port A PWM Port B Technical Summary Rev 3 Peripheral Connectors Freescale Semiconductor 2 27 2 22 1 Port B Expansion Connector Port B is a GPIO port which is connected to the Port B header The pins of the port PBO PB7 are dedicated to general purpose I O and Interrupt operations The GPIO port pin
30. CI UART s 3 3V signal levels to RS 232 compatible signal levels and connects to the host s serial port via connector P3 Flow control is not provided but could be implemented using uncommitted GPIO signals The pin out of connector P3 is listed in Table 2 1 The RS 232 level converter transceiver can be disabled by placing a jumper at JG9 56F807 RS 232 Level Converter Interface FORCEOFF Jumper Removed Enable RS 232 Jumper Pin 1 2 Disable RS 232 Figure 2 2 Schematic Diagram of the RS 232 Interface Table 2 1 RS 232 Serial Connector Description P3 Pin Signal Pin Signal 1 Jumper to 6 amp 4 6 Jumper to 1 amp 4 2 TXD 7 Jumper to 8 3 RXD 8 Jumper to 7 4 Jumper to 1 amp 6 9 N C 5 GND 56F807EVM User Manual Rev 3 2 6 Freescale Semiconductor Operating Mode 2 4 Clock Source The 56F807EVM uses an 8 00MHz crystal Y 1 connected to its External Crystal Inputs EXTAL and XTAL The 56F807 uses its internal PLL to multiply the input frequency by 10 to achieve its 80MHZ maximum operating frequency An external oscillator source can be connected to the controller by using the oscillator bypass connector JG6 and JG18 see Figure 2 3 EXTERNAL OSCILLATOR HEADERS 56F807 Figure 2 3 Schematic Diagram of the Clock Interface 2 5 Operating Mode The 56F807EVM provides a boot up MODE selection jumper JG7 This jumper is used to select
31. DOTVNV LIOA SI E INN Sit En tdl Vi A0 Ei anyo T 990 k 1 yk goa S A en ESNS HOWITOA 4HAO INN wi 6044 8019 Old ONY NOLL LINYA HOWL IOA 4HAO INN AYVNIYd HHdW D SNISSONO ONHZ Odd AWA ADVE O SSVHd WIER awa XoVH V ESVHd V 403 8 ONISSOJD ONSZ HSVHd X OH3Z ONISSOND ONSZ V 45 V X 5 5 INMRINO E HSSVHd S gHd EN ESNAS SNDIVHHdWEI SAING YOLOM SNV HSNES INHNNDO SNE NOION T Ton lt 091 WSdWnD HISUNE Dad XISIHNI g g E on WINES gt HORE uadunr WOD Ierzes SSO 0437 Dad WMd 244 d H Tia Daa stor AOLOANNOD INN 4 or gt gt 8 AN3 NE awa xovg g aswHa 8 9 3 8 X OH3Z 5NISSOND ouaz E SSVHd 0437 ve ze SSOND OxuZ Dad SIN DAS 0 Hud baq sad CIONLNOO Sieg HAING NOLOH RO eme ge 92 SI OHd EN s sNHS INERAINO ASVHA OLOW ye SI VHd 6 SNES LNAYANO V 45 NOLOW LNY Tam Ha mS ONY HSNES HDVLTOA 808 NOLOW SL En el Str tn vasero Bs O SIND A0 6 EINN A0 8 O y iE at ee SVWMd so aa or IO WMa 8 SS EYNMd ag a 9 ZVWMd za Wa LA SS rd av ua z OVWMd Ae uma 56F807EVM User Manual Rev 3 Freescale Semiconductor A 8 uonoojeg eBejoA 19AQ pue INN
32. EMF Phase B Sense 40 Back EMF Phase C Sense Technical Summary Rev 3 Freescale Semiconductor 2 15 2 13 General Purpose Switches and Run Stop Switch Two general purpose user pushbutton switches are connected to Port D GPIO signals PD3 and PD4 A Run Stop toggle switch is connected to GPIO signal PDS Refer to Figure 2 9 56F807 GP 1 SWITCH o GP 2 SVVITCH o Figure 2 9 Run Stop and General Purpose Svvitches 56F807EVM User Manual Rev 3 2 16 Freescale Semiconductor Serial 10 bit 4 channel D A Converter 2 14 Serial 10 bit 4 channel D A Converter The 56F807EVM board contains a serial 10 bit 4 channel D A converter connected to the 56F807 s SPI port The output pins are uncommitted and are connected to a 4X2 header J26 to allow easy user connections Refer to Figure 2 10 for the D A connections and Table 2 8 for the header s pin out The D A s output full scale range value can be set to a value from 0 0V to 2 4V by a trimpot R97 This trimpot is preset to 2 05V which provides approximately 2mV per step 56F807 MAX5251 DIN D A CONNECTOR J26 Figure 2 10 Serial 10 bit 4 Channel D A Converter Table 2 8 D A Header Description J20 Pin Signal Pin Signal 1 D A Channel 0 2 AGND 3 D A Channel 1 4 AGND 5 D A Channel 2 6 AGND 7 D A Channel
33. MAA A 18 Bypass Capacitors and Spare Gates A 19 56F807EVM User Manual Rev 3 Freescale Semiconductor Preliminary 1 1 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 LIST OF TABLES 56F807EVM Default Jumper Options 1 3 RS 232 Serial Connector Description la aa abd aaa abd ERE RERO 2 6 C peratine 100 EE 2 7 JTAG Oh DE xag AH EE Oe RR 2 9 Parallel JTAG Interface Disable Jumper Selection 2 9 Parallel JTAG Interface Connector Description 2 10 Primary UNI 3 Connector Description 35 bus dyes ete ie ae A Nie 2 14 secondary UNI 3 Connector Description 2 15 WA ener Lari MAA 2 17 FAULTAI source Selection Iutnpet uu saa daaa aaa MR daa sa da aa 2 20 FAULIBISouce Selection HIPS aaa yaaa 2 22 CAN Header Dementi indidem br POPE ER ERR UR A or Re 2 25 Pon Connector ET P R RI ERA 2 28 Porn D Connector DOSGRINIONL a a aaa ac ed oe oe 2 28 Port E Connector Description aded dC CR ed Ene oed deed ROCA 2 29 External Memory Control Signal Connector Description 2 29 Timer A Connector Description 2 30 Timer B Eege E 2 30 Timer Connector et ETH 2 31 Timer D Connector Le
34. SIAIG si npold pJepuels 450 6 8 L 6 8 L sr oua ens O O dana xg ens sr ona en O O O ana xg en s aua ens O O ga awa xg ens sr ana en O a awa Ma EN sr vua ens O Ol vanas xg ens si wa en O vana xg en lt SI oHd ENS lt sr oHd EN 2INY X 8 200 YNV y c z lt 9 4W3 vg ens lt 9 3w3 ya 9 lt SI ad ens lt SI gHd en LNY 9 S ENV NER y lt a JW3 M8 ens lt 8 dW3 vg SI vHd ENS lt SI vHd En 0 NV4 E RANA ENV Eve lt V 3N3 ya ENS lt V anq ya orar a a 9 8 v Appendix A Rev 3 A 11 Freescale Semiconductor SU S 1 2 eseud c pue Lb W 911614 3 q E m 81 JO IL 1eeus ubiseg qdsq ueufiseq 0002 91 1940120 Aepuow ejeq 8 q quln S9190 Y69 amoo 229 3SN3S 1 H3AO ASWHd AYVANOOIS ANY AYWWIYd SL 0192 217 087 XY4 0609 217 087 8298 euozuy adway peoy 101113 1583 0017 UOISIAIG SI9NpOid PIEPUEIS 4504 IH ASNES LINYA INAYANO 508 OG ILNSNWNH O V HSVHd F INN AYWVUANODHS EGENT 01 y AINIT 1 H3AO 238 184 ME z 21093108 am SI YHd S zor ys A0 S seu NUS T anyo TE genge LINYA CP y D ow 6NV LINSWNDO HHAO SNA DA RS INN AYVUNODHAS a P up
35. Test Action Group JTAG port interface connector for an external debug Host Target Interface J3 On board Parallel JTAG Host Target Interface with a connector for a PC printer port cable P1 RS 232 interface for easy connection to a host processor U13 and P3 CAN interface for high speed 1 0Mbps communications US and J24 CAN bypass and bus termination J25 and JG3 Connector to allow the user to connect his own SCIO MPIO compatible peripheral J15 Technical Summary Rev 3 Freescale Semiconductor 2 1 Connector to allow the user to connect his own SCI1 MPIO compatible peripheral J14 Connector to allow the user to connect his own SPI MPIO compatible peripheral J13 Connector to allow the user to connect his own PWMA or MPIO compatible peripheral J10 Connector to allow the user to connect his own PWMB MPIO compatible peripheral J11 Connector to allow the user to connect his own CAN physical layer peripheral J16 Connector to allow the user to connect his own Timer A MPIO compatible peripheral J18 Connector to allow the user to connect his own Timer B MPIO compatible peripheral J21 Connector to allow the user to connect his own Timer C MPIO compatible peripheral J19 Connector to allow the user to connect his own Timer D MPIO compatible peripheral J22 Connector to allow the user to attach his own Port B GPIO compatible peripheral J20 Connector to allow the user to
36. ale Semiconductor Program and Data Memory 2 2 Program and Data Memory The 56F807EVM uses one bank of 128Kx16 bit Fast Static RAM GSI GS72116 labeled U2 for external memory expansion see the FSRAM schematic diagram in Figure 2 1 This physical memory bank is split into two logical memory banks of 64Kx16 bits one for Program memory and the other for Data memory By using the controller s program strobe PS signal line along with the memory chip s AO signal line half of the memory chip is selected when Program memory accesses are requested and the other half of the memory chip is selected when Data memory accesses are requested This memory bank will operate with zero wait state accesses while the 56F807 is running at 70MHz However when running at 80MHz the memory bank operates with four wait state accesses This memory bank can be disabled by removing the jumper at JG8 56F807 GS72116 A0 A15 T A1 A16 A0 DQ0 DQ15 OE WE Jumper Pin 1 2 Enable SRAM Jumper Removed Disable SRAM Figure 2 1 Schematic Diagram of the External Memory Interface Technical Summary Rev 3 Freescale Semiconductor 2 5 2 3 RS 232 Serial Communications The 56F807EVM provides an RS 232 interface by the use of an RS 232 level converter Maxim MAX3245EEAI designated as U13 Refer to the RS 232 schematic diagram in Figure 2 2 The RS 232 level converter transitions the S
37. ase C Sense 56F807EVM User Manual Rev 3 Freescale Semiconductor Secondary UNI 3 Interface 2 12 Secondary UNI 3 Interface A Secondary UNI 3 Motor Drive interface is available on the EVM board Motor control signals from a family of motor driver boards can be connected to the EVM board via the Secondary UNI connector interface The Secondary UNI 3 connector interface contains all of the signals needed to drive and control the motor drive boards These signals are connected to various groups of the controller s input and output ports A D TIMER and PWM Port B The header JG10 is used to select between the Back EMF and Motor Phase Current signals Refer to Table 2 7 for the pin out of the Secondary UNI 3 connector J2 Table 2 7 Secondary UNI 3 Connector Description J2 Pin A Signal Pin Signal 1 PWM AT 2 Shield 3 PVVM AB 4 Shield 5 PVVM BT 6 Shield 7 PVVM BB 8 Shield 9 PWM CT 10 Shield 11 PWM CB 12 GND 13 GND 14 NC 15 NC 16 NC 17 Analog GND 18 Analog GND 19 NC 20 NC 21 Motor DC Bus Voltage Sense 22 Motor DC Bus Current Sense 23 Motor Phase A Current Sense 24 Motor Phase B Current Sense 25 Motor Phase C Current Sense 26 Motor Drive Temperature Sense 27 NC 28 Shield 29 Motor Drive Brake Control 30 Serial COM 31 PFC PWM 32 PFC Inhibit 33 PFC Zero Cross 34 Zero Cross A 35 Zero Cross B 36 Zero Cross C 37 Shield 38 Back EMF Phase A Sense 39 Back
38. cale Semiconductor A 12 10399 98 32 H4 IIEH 10 49p09U3 3 n3e1penp BuIsso19 0 197 ZL V 91n614 a v m i Jo 21 seng usaq 0450 19ubisag 0002 91 1840199 Kepuow areq y JequinwN ASH 591901769 juauinsoq all 139 103443 11 HO H4400N4 4Hn1YHdYnO NISSOHO OH32Z AHVWIHd L 0192 617 087 0605 8147 087 82598 euozuy odwa peoy 101113 1583 0012 UOISIAIG SIINPOIA PIEPUEIS 458 ANOH 9 NId ONISSOHO Oduz 2 adozy L XHGNI S NId 1 T 24 geng sy NId 03WOH N HSVHd Nid mi 7 7 wyo yz iyu A wyo bz ua 53 xn 18 0X30NI lt A lt OX onaz ory Spy AA IN Pru COILOHNNOO 4d02 L mun 029 2 uuo pz wyo pz L AHIODNH 9 ogasvHd amp aos 7 ery ru WE K 8 x ouaz z JT anzz 4d027 ech 819 10 uuo pa uuo pz JE anyo 0v3svHd lt lt 2 yu 6 u LK v x ouaz Lor EI SEH A0 1904448 IIVH NHGIOOONH E Z ONISSOMO OHHZ Z L Ann LOANNOD a q 9 8 v Appendix A Rev 3 A 13 Freescale Semiconductor 10399 98 32 H4 IIEH 40 19p09U3 91n 21penD BuISsS019 0197 Alepuo99S V nBij 3 I q I 5 8 I 7 ii 81 jo L 1eeus ubisag qasq 1euBiseg 0002 91 4940120 AepuoW ajeg y Jequin NOY S91901V 9 Miner ezIS 40193138 124444 T VH HO 4 3000 3 1 0
39. econdary Encoder Input Selected 2 3 5 6 amp 8 9 JG14 Primary UNI 3 3 Phase Current Sense Selected as inputs to A D 2 3 5 6 amp 8 9 JG15 Primary UNI 3 serial selected 1 2 34 5 6 7 8 JG16 PDO input selected as a high input 1 2 JG17 PD1 input selected as a high input 1 2 Introduction Rev 3 Freescale Semiconductor 1 3 56F807EVM Connections An interconnection diagram is shown in Figure 1 3 for connecting the PC and the external 12V DC power supply to the 56F807EVM board Parallel Extension Cable 56F807EVM comme Computer dili P1 Connect cable Hn P2 to Parallel Printer port External with 2 1mm 12V receptacle Power connector Figure 1 3 Connecting the 56F807EVM Cables Perform the following steps to connect the 56F807EVM cables 1 Connect the parallel extension cable to the Parallel port of the host computer 2 Connect the other end of the parallel extension cable to P1 shown in Figure 1 3 on the 56F807EVM board This provides the connection which allows the host computer to control the board 3 Make sure that the external 12V DC 4 0A power supply is not plugged into a 120V AC power source 4 Connect the 2 1mm output power plug from the external power supply into P2 shown in Figure 1 3 on the 56F807EVM board 5 Apply power to the external power supply The green Power On LED LED 10 will illuminate when power is correctly a
40. ector 56F807EVM User Manual Rev 3 2 8 Freescale Semiconductor Debug Support 2 7 1 JTAG Connector The JTAG connector on the 56F807EVM allows the connection of an external Host Target Interface for downloading programs and working with the 56F807 s registers This connector is used to communicate with an external Host Target Interface which passes information and data back and forth with a host processor running a debugger program Table 2 3 shows the pin out for this connector Table 2 3 JTAG Connector Description J3 Pin Signal Pin Signal 1 TDI 2 GND 3 TDO 4 GND 5 TCK 6 GND 7 NC 8 KEY 9 RESET 10 TMS 11 3 3V 12 NC 13 NC 14 TRST When this connector is used with an external Host Target Interface the parallel JTAG interface should be disabled by placing a jumper in jumper block JG4 Reference Table 2 4 for this yumper s selection options Table 2 4 Parallel JTAG Interface Disable Jumper Selection JG4 Comment No jumpers On board Parallel JTAG Interface Enabled 1 2 Disable on board Parallel JTAG Interface Technical Summary Rev 3 Freescale Semiconductor 2 9 2 7 2 Parallel JTAG Interface Connector The Parallel JTAG Interface Connector P1 allows the 56F807 to communicate with a Parallel Printer Port on a Windows PC reference Figure 2 5 By using this connector the user can download programs and work with the 56F807 s registers
41. eface 1x GPIO Preface ix 2 28 2 32 signals 2 16 H Hall Effect Quadrature Encoder interface 2 1 Host Parallel Interface Connector 2 8 Host Target Interface 2 8 Index Rev 3 Freescale Semiconductor Index 1 IC Preface ix Integrated Circuit IC Preface ix J Joint Test Action Group JTAG Preface 1x JTAG Preface ix 1 1 2 1 connector 2 9 JTAG port interface 2 1 Jumper Group 1 3 1 1 3 JG10 1 3 JG11 1 3 JG12 1 3 JG13 1 3 JG14 1 3 15 1 3 16 1 3 JG17 1 3 JG2 1 3 JG3 1 3 JG4 1 3 5 1 3 JG6 1 3 JG7 1 3 JG8 1 3 JG9 1 3 L Logic motor bus over current 2 1 motor bus over voltage 2 1 motor zero crossing 2 1 Low Profile Quad Flat Pack LQFP Preface ix LQFP Preface ix motor bus over current 2 1 over voltage 2 1 Motor Phase signals 2 15 Motor Phase Current 2 23 MPIO Preface ix 2 28 2 29 2 30 port 2 31 MPIO compatible peripheral 2 1 Multi Purpose Input and Output MPIO Preface ix O On board power regulation 2 2 OnCE Preface ix 1 1 On Chip Emulation OnCE Preface ix P Parallel JTAG Host Target Interface 2 1 PCB Preface ix Phase Locked Loop PLL Preface ix PLL Preface ix Port B GPIO compatible peripheral 2 2 Port D GPIO compatible peripheral 2 2 Port E GPIO compatible peripheral 2 2 Printed Circuit Board PCB Preface ix Program memory 2 5 Pulse VVidth Modulation PVVM Preface ix PVVM Preface ix PVVMA compatible peripheral 2 2 PVVMB compatible perip
42. er rr A 2 31 External Memory Address Bus Connector Description 2 32 External Memory Address Bus Connector Description 2 33 A D Port A Connector Dieter ag AEN 2 33 A D Port B Connector Description aaa 2 34 ADA E MMS 2 34 SCH Comedor MIO aaa ad aaa ada EE d 2 35 di MAA 2 35 CAN Connector Descriptio IIIA 2 36 List of Tables Rev 3 Freescale Semiconductor V 2 28 PWM Port Connector Description 2 36 2 29 PWM Port B Connector Description 2 37 56F807EVM User Manual Rev 3 vi Freescale Semiconductor Preface This reference manual describes in detail the hardware on the 56F807 Evaluation Module Audience This document is intended for application developers who are creating software for devices using the Freescale 56F807 part Organization This manual is organized into two chapters and two appendixes Chapter 1 Introduction provides an overview of the EVM and its features Chapter 2 Technical Summary describes in detail the S6F807EVM hardware Appendix A 56F807EVM Schematics contains the schematics of the 56F807EVM Appendix B 56F807EVM Bill of Material provides a list of the materials used on the 56F807EVM board Suggested Reading More documentation on the 56F807 and the 56F807EVM kit may be found at URL http vvvvvv freescale com Preface Rev 3 Freescale Semiconducto
43. erter 2 17 PWM Group A Interface and LEDS circa 2 18 PAULA ein rd dar dd e 2 20 DC Bus Over Voltage and Phase Over Current Detection Circuits 2 21 FAULTBI Selection Circuit so oe AAA 2 22 Primary Back EMF or Motor Phase Current Sense Signals 2 23 Zer Crossing Encoder Ob i224 VERE EE AA 2 24 ERC Pa 2 25 Feature IO uu ss SHEEN ba OC AAA AAA 2 26 vole Me A 2 25 00 AMA A 3 Program amp Data SRAM Memory A 4 300 Di a ARAS A 5 Debug Serial Chanel D A CO exu ERR es A 6 3 Usar LEDS IIIA A 7 List of Figures Rev 3 Freescale Semiconductor iii A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 Primary UNI 3 Interface and Over Voltage Fault Detection A 8 Secondary UNI 3 and Over Voltage Detection A 9 User General Purpose Switches and Jumpers A 10 Motor Phase Current Back EMF Voltage Analog Input Selector A 11 Primary and Secondary 3 Phase Over Current Sense A 12 Primary Zero Crossing Quadrature Encoder or Hall Effect Selector A 13 Secondary Zero Crossing Quadrature Encoder or Hall Effect Selector A 14 Por Expansion Connector ua qa sd we ERA A 15 High Speed CAN Mi IIIA A 16 Parallel JTAG Host Target Interface and JTAG Connector A 17 Foner
44. euozuy edue peoy 101113 1583 0012 UOISIAIG Sjonpo4g PIEPUEIS 450 0609 617 087 Tos 89 VAG E yatu oot ange we LA ane 20 19 O8A4L0849SdS0 get 224Y0A 200V YSSA yy 19dV9A 1207 VSSA 193HV VSSA du 2007 00 mL ano sde 100V VAA 19 ddA hay yy 1938 Yaon ddA gp VAE E o 3402 VAGA 6017SSA 80178SA 4017904 10178SA 90100 SO een SOU 004 SOI_SSA FOI O0A YOL SSA 601 00 OI Sen SO OGA SO SSA AE e LO GGA VOL SSA ain 08AIL0849SdS0 88 Hr ss m 9098 5198 NWO X _NVOSN gt XH NVOSIN ISON HSH son XENYOSAA4c er XL NVOSM OSIN amp OSIN YAP E o0 vrr CHE 30 5 Lia nia SINN SIVNV sol mr NY PLYNY SWL m HSNHS ANAL en Axepuooes LNY LVNV 1881 O HSNAS Awa ya I tn Azepuos s Z NY HAM XIL DWLL 8 HSNHS ana ya I tn Azepuos s LENY LLVNV V asnas ama x8 I en Axepuooes OLNV OLVNV 101 ad asnas 1 cn Azepuos s NY VNV epa asnas A en Azepuos s 8VNV 191 5H 104 EN Dad Azepuos s 001 oer 091 Song Oda NISSOMO ONRZ V3NOH HINOH E bara LX30NI LX30NI 01 Ey TL sxrssowp ousz wcdooNz xuwanooas tad zal o DNISSOHD ONUZ Dad WEE EVHd tal rer 01 Wa daa reuria 001 HS 001 WMa Azepuos s INTWUND WHAO O ESVHA IND Arepuos s EAL INVA 6811 INMNINO WAZAO g SSVHd INN xepuodas 2811 calva boxe
45. h button for IRQB S3 General purpose push button on GPIO PD3 S4 General purpose push button on GPIO PD4 S5 General purpose toggle switch for RUN STOP control PDS S6 General purpose jumper on GPIO PDO JG16 General purpose jumper on GPIO PD1 JG17 56F807 The 56F807EVM uses a Freescale DSP56F807FV80 part designated as U1 on the board and in the schematics This part will operate at a maximum speed of 80MHz A full description of the 56F807 including functionality and user information is provided in these documents DSP56800 Family Manual DSP56800FM Provides a detailed description of the core processor including internal status and control registers and a detailed description of the family instruction set DSP56F801 803 805 807 User s Manual DSP56F801 7UM Provides an overview description of the hybrid controller and detailed information about the on chip Technical Summary Rev 3 Freescale Semiconductor 2 3 components including the memory and I O maps peripheral functionality and control status register descriptions for each subsystem 56F807 Technical Data DSP56F807 Provides features list and specifications including signal descriptions DC power requirements AC timing requirements and available packaging Refer to these documents for detailed information about chip functionality and operation They can be found on this URL http www freescale com 56F807EVM User Manual Rev 3 2 4 Freesc
46. heral 2 2 Q Quad Encoder 2 23 Quadrature Decoder interface port 2 30 Quadrature Encoder Hall Effect interface 2 23 R RAM Preface ix Random Access Memory RAM Preface ix Read Only Memory ROM Preface ix real time debugging 2 8 ROM Preface ix RS 232 interface 2 6 level converter 2 6 schematic diagram 2 6 RS 232 interface 2 1 56F807EVM User Manual Rev 3 ndex 2 Freescale Semiconductor S SCI Preface ix Serial Communications Port 2 34 2 35 SCIO compatible peripheral 2 1 SCI1 compatible peripheral 2 2 Serial Communications Interface SCI Preface ix Serial Peripheral Interface SPI Preface ix SPI Preface ix Serial Peripheral Interface 2 35 SPI compatible peripheral 2 2 SRAM Preface ix external data 2 1 external program 2 1 Static Random Access Memory SRAM Preface ix T Timer compatible peripheral 2 2 U UART Preface ix UNI 3 Back EMF 2 23 connector interface 2 14 DC Bus Over Voltage signal 2 19 Motor Drive interface 2 15 Motor interface Primary 2 2 Secondary 2 3 Over Voltage signal 2 21 UNI 3 connector interface 2 14 Universal Asynchronous Receiver Transmitter UART Preface ix Z Zero Crossing circuits 2 24 Index Rev 3 Freescale Semiconductor Index 3 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona
47. iconductor A 6 sq41 Joen pue YA Md 9 V 1 81 jo 9 Jesus u ls q qdsq i ubis q X Jequnn az S91901VY 9 juauwno90q E 9031 43SN QNV V LYOd NMd oul 0LSZ Lp 087 0609 617 087 y9239 euozuy du r peoy 101113 1584 0017 UOISIAIG SIIMPOIH pJepuels 450 ozz E Ma 9014 SC 031 N3389 an ozin DKCH 504 m az n dsfn ue ozz gt lt 08d aai agy Pw voly 1031 vain DECH ozz Mu 8018 ji ROS Q31N33H9 5257 DESCH as n ozz p 2018 Q31MOTI3A as n T02V72 042 lt eynmd NN SCH I WEN N3389 2031 Y OVTZ asin 012 ALWLS WMd Tasmoms P lt p SH osin ozz lt iynmd 664 d41N44H9 DER asin ozz t Ma 864 iid Q31MOTI3A son vsin Nana 3 a A 7 Appendix A Rev 3 Freescale Semiconductor uon q ine i 96e JOA 19AO pue 39831934 INN 2 1 91nb14 3 a 5 m 81 jo 1eeug ubisag qasq ueufiseq 0002 pz 1890190 epsen ejeq 8 JequnwN azi H S91S01VE9 wueunooq IS NOI193130 LINVA 49V110A 43A0 ANY 39V3H31NI E INN AHVINIHd 0192 617 087 vi 0609 61 087 Y3299 euozuy du l peog 101113 1523 0012 uols Alq S ONPOld PIEPUEIS 450 OV ASNAS LINWA D WMd 454 yauv duvod Ov3u8 3HL1V
48. itability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal inju
49. munications Port 0 SCIO is attached to this connector See Table 2 24 for the connection information Table 2 24 SCIO Connector Description 415 Pin Signal 1 TXDO 2 RXDO 3 GND 56F807EVM User Manual Rev 3 2 34 Freescale Semiconductor Peripheral Connectors 2 22 14 Serial Communications Port 1 Expansion Connector The Serial Communications Port 1 SCI is attached to this connector Refer to Table 2 25 for the connection information Table 2 25 SCI1 Connector Description J14 Pin Signal 1 TXD1 2 RXD1 3 GND 2 22 15 Serial Peripheral Interface Expansion Connector The Serial Peripheral Interface SPI is attached to this connector Refer to Table 2 26 for the connection information Table 2 26 SPI Connector Description J13 Pin Signal 1 MOSI 2 MISO 3 SCLK 4 GND Technical Summary Rev 3 Freescale Semiconductor 2 35 2 22 16 CAN Expansion Connector The CAN port is attached to this connector See Table 2 27 for the connection information Table 2 27 CAN Connector Description J16 Pin Signal 1 MSCAN_TX 2 MSCAN_RX GND 2 22 17 PWM Port A Expansion Connector The PWM Port A is attached to this connector Refer to Table 2 28 for the connection information Table 2 28 PWM Port A Connector Description J1
50. nectors external memory and a CAN interface The expansion connectors are for signal monitoring and user feature expandability The 56F807EVM is designed for the following purposes Allowing new users to become familiar with the features of the 56800 architecture The tools and examples provided with the 56FSOTEVM facilitate evaluation of the feature set and the benefits of the family Serving as a platform for real time software development The tool suite enables the user to develop and simulate routines download the software to on chip or on board RAM run it and debug it using a debugger via the VTAG OnCE port The breakpoint features of the OnCE port enable the user to easily specify complex break conditions and to execute user developed software at full speed until the break conditions are satisfied The ability to examine and modify all user accessible registers memory and peripherals through the OnCE port greatly facilitates the task of the developer Serving as a platform for hardware development The hardware platform enables the user to connect external hardware peripherals The on board peripherals can be disabled providing the user with the ability to reassign any and all of the hybrid controller s peripherals The OnCE port s unobtrusive design means that all of the memory on the board and on the chip are available to the user 1 1 56F807EVM Architecture The 56F807EVM facilitates the evaluation of various feat
51. ommunications Port 1 Expansion Connector 2 35 2 22 15 Serial Peripheral Interface Expansion Connector 2 35 22210 CAN Expansion EECHER 2 36 2 22 17 PWM Port A Expansion Connector 2 36 2 22 18 PWM Port B Expansion Conaorlor EEN A EAR Ee 2 37 Au A A 2 37 Appendix A 56F807EVM Schematics Appendix B 56F807EVM Bill of Material 56F807EVM User Manual Rev 3 ii Freescale Semiconductor 1 1 1 2 1 3 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 A 1 A 2 A 3 A 4 A 5 A 6 LIST OF FIGURES Block Diagram ofthe 56F807EVM 1 2 SOFS07EVM Mo PP AKE 1 3 Connecting the S5OFBOTEVM Cables IIIA AAA 1 4 Schematic Diagram of the External Memory Interface 2 5 Schematic Diagram of the RS 232 Interface 2 6 Schematic Diagram of the Clock Interface Lieu ies ac oed RARA 2 7 Schematic Diagram of the Debug LED Interface 2 8 Block Diagram of the Parallel JTAG Interface 2 10 Schematic Diagram of the User Interrupt Interface 2 11 Schematic Diagram of the RESET Interface A Sit AE ENEE de AS 2 12 Schematic Diagram of the Power Supply Wawa 2 13 Run Stop and General Purpose Switches 2 16 Serial 10 bit 4 Channel D A Conv
52. on Jumper gt FAULTB1 JG2 Comment 1 2 Phase A Over Current Sense input 2 3 DC Bus Over Current Sense input 56F807EVM User Manual Rev 3 2 22 Freescale Semiconductor Quadrature Encoder Hall Effect Interface 2 17 Back EMF and Motor Phase Current Sensing The primary and secondary UNI 3 connectors supply Back EMF and Motor Phase Current signals from the three phases of a motor attached to a motor drive unit The Back EMF signals on the UNI 3 connectors are derived from a resistor divider network contained in the motor drive unit These resistors divide down the attached motor s Back EMF voltages to a 0 to 3 3V level The Motor Phase Current signals are derived from current sense resistors Both of these signal groups are then routed to a group of header pins JG14 that allow the end user to select which signal group the device s A D will monitor Refer to Figure 2 15 for the design of a single channel The Secondary UNI 3 s Back EMF signals are simularly derived and routed to a group of header pins JG10 that allow the end user to select which signal group the controller s A D will monitor reference Table 2 8 Typical Motor Phase Current Back EMF Analog Input Selector JG14 2 AN2 BACK EMF A55 1 PHASE A SENSE 5 3 Figure 2 15 Primary Back EMF or Motor Phase Current Sense Signals 2 18 Quadrature Encoder Hall Effect Interface The
53. oon ea ADS r 2 S T z T SE DEE 0091 ava 31iuu34 anro de vs Le ewe linon ano by ur x Loo n ZE Be 1 OG ACT LNaNI BINT Age om NI WHMOd VNduqXu Loon y iq 56F807EVM User Manual Rev 3 Freescale Semiconductor A 18 L dun s eo oJedg pue sioysede ssed g gL y 2 1614 El a 9 8 v T 91 jo gl Jesys ubiseg 0490 ueufiseq 0002 91 4840190 Aepuow ejeq g eu S91901Y69 vw 229 S31V9 3uVd38 ANY SHOLI9VdVO SSVAAB lli zr T 012 617 087 vi 0609 617 087 419 EN ALS 48268 euozuy due HDH 188 084 629 peoy 101113 1583 0012 s T ET BS UOISIAIG S ONPOJd PIEPUEIS 450 UT TT 3211 HI y y az in ar 1 Me At AES POOHPL POOHPL SOIOSNNOO SOIOSNNOO PPZXOTPL sna VLVG snd ssadaav T 1 il I ii I il I ano ML ano e ian il anoo anro amoo EEN anyo EIN anyo 2 280 150 080 600 870 662 950 S59 bro evo 2 1 il D il D mus Ave ris n ATS w AS AS ATS rer rer E6ENT rem E6ENT vin WIIS HOVIN Was o oo NVO T i 1 i 00408 i T 7 anyo anyo 3022 anyo 09 il o il y 80 il 860 il i anro Mee anoo cke anro le Aug gt ano xl anl le ano le
54. or Description J21 Pin Signal Alternate 1 TBO PhaseA1 2 TB1 PhaseB1 3 TB2 INDEX1 4 TB3 HOME1 5 3 3V 3 3V 6 GND GND 56F807EVM User Manual Rev 3 2 30 Freescale Semiconductor Peripheral Connectors 2 22 7 Timer Channel C Expansion Connector The Timer Channel C port is an MPIO port attached to the Timer C expansion connector Refer to Table 2 18 for the signals attached to the connector Table 2 18 Timer C Connector Description J19 Pin A Signal 1 TCO 2 TC1 3 3 3V 4 GND 2 22 8 Timer Channel D Expansion Connector The Timer Channel D port is an MPIO port attached to the Timer D expansion connector Refer to Table 2 19 for the signals attached to the connector Table 2 19 Timer D Connector Description J22 Pin Signal 1 TDO 2 TD1 3 TD2 4 TD3 5 3 3V 6 GND Technical Summary Rev 3 Freescale Semiconductor 2 31 2 22 9 Address Bus Expansion Connector The 16 bit Address bus connector contains the hybrid controller s external memory address signal lines The upper 8 bits A8 A15 can also be used as Port A GPIO lines See Table 2 20 for the Address bus connector information Table 2 20 External Memory Address Bus Connector Description J6 Pin Signal Pin Signal 1 AO 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 AT 9 A8 10 A9 11 A10 12 A11
55. otor Protection Logic The 56F807EVM contains two UNI 3 connectors that interface with various motor drive boards Primary UNI 3 and Secondary UNI 3 The device can sense error conditions generated by the motor power stage boards via signals on the UNI 3 connector The motor driver board s Motor Supply DC Bus Voltage Current and Motor Phase Currents are sensed on the power stage board The conditioned signals are transferred to the board via the UNI 3 connector These analog input signals are compared to a limit set by trimpots If the input analog signals are greater than the limit set by the trimpot a controller digital voltage compatible 3 3V DC fault signal is generated 2 16 1 Primary UNI 3 Motor Protection Logic The Primary UNI 3 DC Bus Over Voltage signal is connected to the hybrid controller s PWM group A fault inputs The three Primary UNI 3 Phase Over Current signals are connected to the device s PWM group A s fault inputs i e FAULTA1 FAULTA2 and FAULTA3 Figure 2 13 contains the diagram of the Over Voltage and one phase of the Phase Over Current circuit for the UNI 3 interface The FAULTAI input can be sourced from the Phase A Over Current circuit or the DC Bus Over Current circuit Jumper JG1 provides the selection reference Figure 2 12 and Table 2 9 Technical Summary Rev 3 Freescale Semiconductor 2 19 DC BUS CURRENT SENSE sense DCB gt gt e FAULTA1 PHASE A CURRENT
56. pplied 56F807EVM User Manual Rev 3 Freescale Semiconductor Chapter 2 Technical Summary The 56F807EVM is designed as a versatile hybrid controller development card for developing real time software and hardware products to support a new generation of applications in digital and wireless messaging servo and motor control digital answering machines feature phones modems and digital cameras The power of the 16 bit 56F807 controller combined with the on board 64K x 16 bit external program static RAM SRAM 64K x 16 bit external data SRAM CAN interface Hall Effect Quadrature Encoder interface motor zero crossing logic motor bus over current logic motor bus over voltage logic and parallel JTAG interface makes the 56F807EVM ideal for developing and implementing many motor controlling algorithms as well as for learning the architecture and instruction set of the 56F807 processor The main features of the S6F807EVM with board and schematic reference designators include 56F807 16 bit 3 3V hybrid controller operating at SOMHz U1 External fast static RAM FSRAM memory U2 configured as 64Kx16 bits of Program memory with wait states at 70MHz 64Kx16 bits of Data memory with 0 wait states at 70MHz 4 Channel 10 bit Serial D A SPI for real time user data display U14 8 00MHz crystal oscillator for frequency generation Y1 Optional external oscillator frequency input connector JGS and JG6 Joint
57. r VIM 0 MM INn Azeurza OVNMd r 0v Md gt gt si ola ED MS dOLS LUVLS Sad 9 80014 FIN Z NOLLOH HSNd 40 rad a Y P 00 1d Elv T NOLINE HSna 40 0 d 9 20014 ev 4442 7r 20014 Hv 28 AHdNNC YESO 144 7r 01d WW oiv TK wsdW n sasn 00d lt 000 d 6v 8v woo peres 84 J 80140 LY CONINOO VUE t IND kuwanoa 9gq 80 W v OSINOO HIYA IND AUWWIYd 988 46 y SOI WN sv SU d WINES vad 4 n r 8014 PN BEE ev NEED OUT HHSD Zad 64C D I ev MOTISA 087 WHSD bad 4 8014 iw 084 A 08 01M ov gt gt 1s1701v vin 56F807EVM User Manual Rev 3 Freescale Semiconductor A 2 SONI 420190po0W s Z Y 3 1 q I o WA 81 jo 2 19949 ubisag qasq ueuBiseq 0002 91 1990190 epuoW ejeq V Jequinw azi A H 991901769 juauinooq IS SOU 8 49019 300N 13838 enu 0192 6 17 087 XvV4 0609 6 17 087 Y8238 euozuy d l r peoy 101113 1583 0012 UOISIAIG S1l9npoid pJepuels ASA 818150 10081X3 lt lt 5 LOOH LNI Zor ON LOOd LXH 301 YadWwnr ION 1004 veu Ag et anyo 899 gt 0 lt lt P es 01 NOLLDEHHSna dour 8u anyo o A et 299 7 lt U 49 01 NOLLQHHS ud VOUI cet Vix S Tv x
58. r his user specific programs Figure 2 6 Schematic Diagram of the User Interrupt Interface 56F807 IRQA Technical Summary Rev 3 Freescale Semiconductor 2 11 2 9 Reset Logic is provided on the 56F807 to generate a clean Power On RESET signal Additional reset logic is provided to support the RESET signals from the JTAG connector the Parallel JTAG Interface and the user RESET push button refer to Figure 2 7 RESET PUSHBUTTON us MANUAL RESET d P RESET Figure 2 7 Schematic Diagram of the RESET Interface 56F807EVM User Manual Rev 3 2 12 Freescale Semiconductor Power Supply 2 10 Power Supply The main power input 12V DC at 4 0A to the 56FSOTEVM is through a 2 1mm coax power jack A 4 0A power supply is provided with the 56F807EVM however less than 500mA is required by the EVM The remaining current is available for user motor control applications when connected to an optional motor power stage board The S6F807EVM provides 3 3V DC voltage regulation for the hybrid controller memory D A CAN parallel JTAG interface and supporting logic refer to Figure 2 8 Power applied to the 56FSOTEVM is indicated with a Power On LED referenced as LED10 12V DC 5 0V 3 3V 3 3V Digital Regulator Regulator 3 3V Analog lid POWER ON 56F807EVM AA PARTS GREEN LED LED10 Figure 2
59. r vil Notation Conventions This manual uses the following notational conventions Term or Value Symbol Examples Exceptions Active High Signals No special AO Logic One symbol attached CLKO to the signal name Active Low Signals Noted with an WE In schematic Logic Zero overbar in text OE drawings Active and in most Low Signals may be figures noted by a backslash WE Hexadecimal Values Begin with a 0FFO symbol 80 Decimal Values No special 10 symbol attached 34 to the number Binary Values Begin with the b1010 letter b attached b0011 to the number Numbers Considered 5 Voltage is often positive unless 10 shown as positive specifically noted 3 3V as a negative value Bold Reference See http www freescale com sources paths emphasis 56F807EVM User Manual Rev 3 viii Freescale Semiconductor Definitions Acronyms and Abbreviations Definitions acronyms and abbreviations for terms used in this document are defined below for reference A D Analog to Digital CAN Controller Area Network serial communications peripheral and method CiA CAN in Automation an international CAN user s group that coordinates standards for CAN communications protocols D A Digital to Analog EVM Evaluation Module GPIO General Purpose Input and Output Port IC Integrated Circuit JTAG Joint Test Action Group a bus protocol interface used for test and debug LQFP Low
60. ry or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part La Z freescale semiconductor Freescale M and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST O Freescale Semiconductor Inc 2005 All rights reserved DSP56F807EVMUM Rev 3 07 2005
61. s may be programmed as inputs outputs or level sensitive interrupt inputs Table 2 12 shows the port pin to headed connections Table 2 12 Port B Connector Description J20 Pin Signal Pin Signal 1 PBO 2 PB1 3 PB2 4 PB3 5 PB4 6 PB5 7 PB6 8 PB7 9 GND 10 3 3V 2 22 2 Port D Expansion Connector Port D is an MPIO port with signal lines attached to various headers The six pins of the port PDO PD5 are dedicated to general purpose operation The remaining two pins PD6 and PD7 are shared with the TXD1 and RXDI signal lines The GPIO port pins may be programmed as inputs outputs or level sensitive interrupt inputs Table 2 13 shows the exclusive Port D signals The shared Port D signals are contained in Table 2 20 Table 2 13 Port D Connector Description J23 Pin Signal Pin Signal 1 PDO 2 PD1 3 PD2 4 PD3 5 PD4 6 PD5 7 GND 8 3 3V 56F807EVM User Manual Rev 3 2 28 Freescale Semiconductor Peripheral Connectors 2 22 3 Port E Expansion Connector Port E is an MPIO port with signal lines attached to various headers The pins of the port are shared with one SCI port SCIO two Address bus lines A6 and A7 and the SPI port Table 2 14 shows the shared pins and functions Table 2 14 Port E Connector Description 417 Pin Signal Alternate Funct Pin Signal Alternate Funct 1 PEO TKDO 2 PE1 RXDO 3 PE2 TXD1 4 PE
62. tor Protection aeo dino oy Sh ho E Y CERES UE RU ERR 2 19 Table of Contents Rev 3 Freescale Semiconductor i 2 16 1 Primary UNI 3 Motor Protection Logic 2 19 2 16 2 Secondary UNI 3 Motor Protection Logic 2 21 2 17 Back EMF and Motor Phase Current Sensing 2 23 2 18 Quadrature Encoder Hall Eftect Interface 2 23 ES E A 2 24 220 LAN IAS rara AAA bd li k 2 24 221 Blue Feature PUES i dea A A A d ede da 2 26 PensheulL Um IIIA AAA 2 27 2221 Fort Expanaton COnnector adria A 2 28 222 2 Port D Expansion COMME IIIA 2 28 2223 For E Expansion e EE 2 29 2 22 4 External Memory Control Signal Expansion Connector 2 29 2 22 5 Primary Encoder Timer Channel A Expansion Connector 2 30 2 22 6 Secondary Encoder Timer Channel B Expansion Connector 2 30 2 22 7 Timer Channel C Expansion Connector 2 31 2225 Timer Channel D Expansion Connector 2 31 2 22 9 Address Bus Expansion Connector 2 32 2 22 10 Data Bus Expansion Connector 2 33 2 22 11 A D Port A Expansion Connector 2 33 2 22 12 A D Port B Expansion Lmmueebeg ad SEENEN RR 2 34 2 22 13 Serial Communications Port 0 Expansion Connector 2 34 2 22 14 Serial C
63. upply 3 3V 5 0V 8 3 3VA Figure 1 1 Block Diagram of the 56F807EVM Seventeen jumper groups JG1 JG17 shown in Figure 1 2 are used to configure various features on the 56F807EVM board Table 1 1 describes the default jumper group settings 56F807EVM User Manual Rev 3 Freescale Semiconductor Figure 1 2 56F807EVM Jumper Reference 56F807EVM Configuration Jumpers Table 1 1 56F807EVM Default Jumper Options Jumper Group Comment Jumper Connections JG1 Primary UNI 3 Phase A Over Current Selected for FAULTA1 1 2 JG2 Secondary UNI 3 Phase A Over Current Selected for FAULTB1 1 2 JG3 CAN termination unselected NC JG4 Enable on board Parallel JTAG Host Target Interface NC JG5 Use on board EXTAL crystal input for oscillator 2 3 JG6 Use on board XTAL crystal input for oscillator 1 2 JG7 Selects device s Mode 0 operation upon exit from reset 1 2 JG8 Enable on board SRAM 1 2 JG9 Disable RS 232 output NC JG10 Secondary UNI 3 3 Phase Current Sense Selected as inputs to A D 2 3 5 6 8 9 JG11 Secondary UNI 3 serial selected 1 2 34 5 6 7 8 JG12 Primary Encoder Input Selected 2 3 5 6 8 9 JG13 S
64. ures present in the 56F807 part and can be used to develop real time software and hardware products based on the Introduction Rev 3 Freescale Semiconductor 1 1 56F807 The 56F807EVM provides the features necessary for a user to write and debug software demonstrate the functionality of that software and interface with the customer s application specific device s The 56F807EVM is flezible enough to allow a user to fully exploit the 56F807 s features to optimize the performance of their product as shown in Figure 1 1 RESET LOGIC MODE IRQ LOGIC Program Memory 64Kx16 bit SRAM Data Memory 64Kx16 bit SRAM Memory Expansion Connector s JTAG Connector DSub Parallel JTAG 25 Pin Interface Low Freq Crystal 1 2 56F807EVM Configuration Jumpers 56F807 RESET SPI MODE IRQ SCI 0 Address Data amp Control SCI 1 CAN TIMER GPIO JTAG OnCE PM SEI AID 0 A D 1 PWM 2 XTAL EXTAL 3 3 V amp GND 4 Channel 10 bit D A RS 232 Interface DSub 9 Pin Peripheral Expansion Connector s CAN Interface Debug LEDs PWM LEDs Over V Sense Over Sense Zero Crossing Detect Pri UNI 3 Sec UNI 3 Power S
Download Pdf Manuals
Related Search