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TQMP2020 User`s Manual - TQ

1. cfg_srds_refclk TSEC_1588_ALARM_OUT1 PORDEVSR2 18 0 SerDes Ref Clock 125 MHz SerDes Ref Clock 125 MHz SerDes Ref Clock 100 MHz SerDes Ref Clock 100 MHz cfg_tsec_reduce EC_MDC PORDEVSRI O eTSEC1 amp eTSEC2 in reduced pin eTSEC1 in reduced mode RGMII mode RTBI RGMII RMII 1 eTSEC1 amp eTSEC2 in std width Reserved TBI GMII MII cfg_tsec1_prtcl 0 1 TSEC1_TXDO PORDEVSRI6 7 00 Reserved Reserved eTSEC1 SGMIl TSEC1_TXD7 01 ETSEC1 gt MIl RMIl Reserved eTSEC1 SGMII ETSEC1 GMII RGMII eTSEC1 RGMII 11 ETSEC1 TBI RTBI Reserved eTSEC1 SGMII cfg_tsec2_prtcl 0 1 TSEC2_TXDO PORDEVSR 18 19 00 Reserved Not used TSEC2_TXD7 01 ETSEC2 gt MII RMII Not used if not configured to SGMII ETSEC2 GMII RGMII Not used if not configured to SGMII 11 eTSEC2 TBI RTBI Not used if not configured to SGMII cfg_tsec3_prtcl 0 1 UART_RTS 0 1 PORDEVSR 20 21 00 Reserved Reserved eTSEC3 SGMII 01 eTSEC3 gt RMII Reserved eTSEC3 SGMII if not configured to SGMII eTSEC3 RGMII eTSEC3 RGMII if not configured to SGMII 11 eTSEC3 RTBI Reserved eTSEC3 gt SGMII if not configured to SGMII cfg_sdhc_cd_pol_sel TSEC2_TXD5 TSEC3_TX_EN PORDEVSRI23 0 eSDHC Card detect polarity is not Not used inverted eSDHC Card detect polarity is not Not used inverted Page 26 User s Ma
2. Local Bus Signal CPU Pin Type Description Module Pin LADO B18 VO Local Bus address data 0 X2 60 LAD1 E20 VO Local Bus address data 1 X2 62 LAD2 A19 VO Local Bus address data 2 X2 64 LAD3 B20 VO Local Bus address data 3 X2 66 LAD4 D19 VO Local Bus address data 4 X2 68 LAD5 A18 VO Local Bus address data 5 X2 70 LAD6 B17 VO Local Bus address data 6 X2 69 LAD7 C20 VO Local Bus address data 7 X2 71 LAD8 F19 VO Local Bus address data 8 X3 14 LAD9 E10 VO Local Bus address data 9 X3 16 LAD10 B16 VO Local Bus address data 10 X3 18 LAD11 D14 VO Local Bus address data 11 X3 20 LAD12 D17 VO Local Bus address data 12 X3 22 LAD13 E11 VO Local Bus address data 13 X3 24 LAD14 A16 VO Local Bus address data 14 X3 26 LAD15 C15 VO Local Bus address data 15 X3 30 LDPO E18 VO Local Bus data parity 0 T 4k7 to VCC3V3 on module X3 8 LDP1 B19 VO Local Bus data parity 1 T 4k7 to VCC3V3 on module X3 10 LA16 B21 0 Local Bus burst address 16 X3 32 LA17 A22 O Local Bus burst address 17 X3 34 LA18 C21 0 Local Bus burst address 18 X3 36 LA19 F21 0 Local Bus burst address 19 X3 38 LA20 E12 0 Local Bus burst address 20 X3 40 LA21 A21 O Local Bus burst address 21 X3 31 LA22 D11 O Local Bus burst address 22 X3 29 LA23 E22 0 Local Bus burst address 23 X3 27 LA24 F20 O Local Bus burst address 24 X2 73 LA25 E21 O Local Bus burst address 25 X2 74 LA26 B22 0 Local Bus burst address 26 X2 76 LA27 F18 0 Local Bus burst address
3. 60 Further applicable document sesse seek ene ee ER ee ek OER ee ER ee ee ek ee ek ee ek ER ee 64 User s Manual TQMP2020 UM 102 2012 by TQ Group Page v Illustration directory Illustration 1 Illustration 2 Illustration 3 Illustration 4 Illustration 5 Illustration 6 Illustration 7 Illustration 8 Illustration 9 TOMP2020 blockdiagramsamseseenemmmm mm mm es 8 Feedback ARESE T REO meer ken ee 15 TT ASE 16 P2020 2010 clock subsystem block diagram sesse seek see eek gee eek eke ee 30 P1020 1011 and P1021 1012 clock subsystem block diagram sss 31 Length alignment Local BUS sesse seek eek seek eek GR ee eek ee ee Rek ee ee ee eek eke 33 Supply structure simplified 40 Stack heights not to scale 59 Overall dimensions top view through board enenesennenseenssensennsennneen 60 Page vi User s Manual TQMP2020 UM 102 2012 by TQ Group Revision history Rev Date Name Pos Modification 100 07 07 2011 Petz Document created 3 2 3 CPU configuration legend updated Table 7 Meaning P2020 for values 10 and 11 of signals PORDEVSRI20 21 corrected 3 2 3 6 Warning added BOM 03 012012 PSHE 3346 100 MHz for TOMP1xxx removed Illustration 6 Added 3 2 4 6 Explanation for Illustration 6 added Table 17 Type of signal HRESET specified more precisely 3 2 3 2 Typo 102 2403 2012 Petz 3 7 Link to Wiki added User s Manual TQMP202
4. the field cfg_device_ID can be configured with different Device IDs depending on the baseboard Pull ups pull downs or active drivers driver conflicts possible must be provided for this on the baseboard During the reset phase respective power up the corresponding signals are driven by the CPLD As these signals are outputs of the CPU or the module a possible driver s conflict must be taken into account in the design of the baseboard The signals UART_SOUTO cfg_eng_use3 VART SOUT1 cfg core1 pll1 and TSEC2_TXD5 TSEC3_TX_EN cfg sdhc cd pol sel are an exception These signals are separated from the plug connector during the reset phase of the module to improve the system integrity User s Manual TQMP2020 UM 102 2012 by TQ Group Page 29 3 2 3 6 Settings via the boot sequencer The CPU configuration with CPU specific boot sequencer cannot replace the configuration via the CPU pins but only complement Because it runs before the software starts it can carry out additional settings which cannot or should not be set by software The standard software delivered with the module U Boot does not depend on the boot sequencer The standard software U Boot delivered with the module does not rely on the boot sequencer The configuration with the boot sequencer starts after the end of the reset In certain cases the configuration via the boot sequencer is indispensable e Multiprocessor environments
5. RESOUT from EI DGND 22K 2K2 Supervisor DGND Illustration 3 Wiring of TRST 3 2 3 CPU configuration User s Manual TQMP2020 UM 102 2012 by TQ Group Page 17 Table6 Legend for Table 7 Table 8 and Table 9 Binary value in bold Default Freescale gt internal value if nothing is connected internal pull up Binary value greyed out Reserved gt do not use Value is fixed in the design not alterable Value is set in the design by comparators not by CPLD EEPROM Default values of CPLD 3 2 3 1 Reset configuration of the hardware The signals listed in Table 7 column 2 are used to define the reset configuration ofthe CPU on the module co m User s Manual TQMP2020 UM 102 2012 by TQ Group Table 7 Reset configuration Config signal 10 signal at the P2020 Register Value Meaning P2020 Meaning P1020 P1021 cfg boot segl0 1 LGPL3 LFWP PORBMSR 10 11 00 Reserved Reserved LapLS 01 Boot sequencer is enabled on I C1 Boot sequencer is enabled on I C1 with normal C addressing mode with normal PC addressing mode 10 Boot sequencer is enabled on 1 C1 Boot sequencer is enabled on C1 with extended I C addressing mode with extended I C addressing mode Boot sequencer is disabled Boot sequencer is disabled No PC ROM is accessed No PC ROM is accessed cfg_sys_pll 0 2 LA 29 31 PORPLLSRI26
6. T 4K7 to VCC3V3 on module Al Machine check processor 0 MERDE Ana T 4K7 to VCC3V3 on module 4105 Machine check processor 1 Merl M23 T 4K7 to VCC3V3 on module X27107 IRQO L24 l External interrupt 0 T 4k7 to VCC3V3 on module X2 115 IRQ1 K26 l External interrupt 1 T 4k7 to VCC3V3 on module X2 117 IRQ2 K29 l External interrupt 2 T 4k7 to VCC3V3 on module X2 119 IRQ3 N25 l External interrupt 3 T 4k7 to VCC3V3 on module X2 121 IRQ4 L26 External interrupt 4 T 4k7 to VCC3V3 on module X2 123 IRQ5 L29 External interrupt 5 T 4k7 to VCC3V3 on module X2 125 IRQ6 K27 l External interrupt 6 T 4k7 to VCC3V3 on module X2 127 IRQ_OUT N29 O Interrupt output T 4k7 to VCC3V3 on module X2 120 low active signal T pull up 4 pull down gt element in series Description Module Pin CLK_OUT T24 O Clock Out gt 22 Q on module X2 81 RTC K24 l Real time clock X2 85 DDR clock driven on module Do not connect for test use only System clock driven on module Do not connect for test use only pull up pull down element in series DDRCLK AC9 O X2 75 SYSCLK W29 O X2 79 oN low active signal Page 48 Table 17 User s Manual TQMP2020 UM 102 2012 by TQ Group Pinout according to functional groups continued CPU Pin Type Description Module Pin IIC1 SDA H28 VO C1 Serial data T 2k4 to VCC3V3 on module X2 133 IICI_S
7. The status signal RY BY of the flash is not used by the CPU The event of write and erasure cycles must be monitored by polling 3 2 7 DDR3 SDRAM e DDR3 SDRAMs 64 bit wide alternatively with without ECC P10xx 32 bit wide with without ECC e 512 Mibyte to 1 Gibyte 2 Gibyte announced P10xx 256 to 512 Mibyte 1 Gibyte announced e DDR3 800 400 MHz clock P10xx DDR3 667 333 MHz clock e Chip select MCSO with stacked DDR also MCS1 e BGA package 96 balls User s Manual TQMP2020 UM 102 2012 by TQ Group Page 37 3 2 8 PC bus All C bus devices on the module are connected to the IC controller IIC1 of the CPU Table 13 shows the used addresses All devices are designed for a maximum I C clock frequency of 400 kHz The pull ups available on the module are sufficient for the bus loads on the module If required that more devices are connected to the bus additional pull ups must be connected in parallel on the baseboard to achieve sufficient low high edges Table 13 IIC1 device addresses Device MSB LSB Data EEPROM 1 0 1 0 0 A2 O A1 O AO R W Configuration 1 0 1 0 1 A2 1 A1 1 AO R W EEPROM SE97B Configuration 0 1 1 0 1 A2 1 A1 1 AO R W EEPROM SE97B Write Protect 9 Temperature Sensor 0 0 1 1 1 A2 1 A1 1 AO R W SE97B Temperature Sensor 1 0 0 1 1 0 0 R W SA560004EDP Real Time Clock 1 1 0 1 0 0 0 R W DS1337 Power Manager 1 0 0 0 1 0 A1 0 A
8. do not connect X1 129 RSVD1022 SD2_TX1 R o Reserved SERDES2 transmit data 1 complement X1 131 do not connect RSVD1022 SD2_TXO O Reserved SERDES2 transmit data 0 do not connect X1 137 RSVD1022 SD2_ TXO _ o Reserved SERDES2 transmit data 0 complement X1 139 do not connect RSVD1022 SD2_RX1 Reserved SERDES2 receive data 1 connect to ground X1 126 RSVD1022 SD2_ RE _ Reserved SERDES2 receive data 1 complement X1 128 connect to ground RSVD1022 SD2_RXO Reserved SERDES2 receive data 0 connect to ground X1 134 RSVD1022 SD2_RXO _ Reserved SERDES2 receive data 0 complement X1 136 connect to ground RSVD1022 SD2_REF_CLK l Reserved SERDES PLL reference clock connect to ground X1 121 RSVD1022 SD2_REF_CLK _ i Reserved SERDES PLL reference clock complement X1 123 connect to ground RSVD4080 EMI2_MDC oO Reserved Ethernet management clock 2 do not connect X1 81 RSVD4080 EMI2_MDIO 7 vo Reserved Ethernet management data in out 2 X1 83 do not connect RSVD1022 POWER_OK GPIO3 19 VO Reserved power ok do not connect X1 159 RSVD1022 POWER EN o Reserved power enable do not connect X1 160 RSVD1022 SDHC_CD VO Reserved eSDHC card detection do not connect X2 34 GPIO1_28 RSVD1022 SDHC_WP VO Reserved eSDHC card write protect do not connect X2 42 GPIO1_29 RSVD1022 IRQ7 l Reserved external interrupt 7 do not connect X2 124 RSVD1022 IRQ8 Reserved external interrupt 8 do not connect X2 126 RSV
9. 1 5 V core voltage VDD VTT VREF e Switch for 3 3 V e DDR3 SDRAM e NOR Flash e Serial EEPROM data configuration e RTC e Temperature sensors e RS232 driver for two serial interfaces e Board to board plug connector system Page 10 User s Manual TQMP2020 UM 102 2012 by TQ Group 3 2 Electronics 3 2 1 CPU As an alternative to the P2020 dual core a P2010 single core can be assembled on the same module Unless otherwise noted the name P2020 also stands for the P2010 in the following and equally for derivatives with and without encryption The P2020 offers a large number of interfaces On account of the high data rates special attention is to be paid to the interfaces mentioned in the following 3 2 1 1 Parallel Modes of the Enhanced Three Speed Ethernet Controller eTSEC The three gigabit Ethernet interfaces TQMP2020 are implemented via eTSECs All relevant pins are routed to the module plug connectors to enable the user to use all possible interface modes supported by the CPU PHY and transformer have to be integrated on the baseboard for RF technical reasons e MIlmode Highest frequency to be transmitted 25 MHz Tx and Rx clock 100 Mbit s e RMIlmode Highest frequency to be transmitted 50 MHz Tx and Rx clock 100 Mbit s Lower number of signals than with MII Timing is tighter than with MII because both clock edges are used e GMl and TBI mode Highest frequency to be trans
10. T 10k to LVDD on module X1 14 TSEC2_RXDO AF28 I eTSEC2 receive data 0 T 10k to LVDD on module X1 12 eTSEC2 receive data valid TREER DM AD2 T 10k to LVDD on module A130 TSEC2_RX_ER AE28 l eTSEC2 receive error T 10k to LVDD on module X1 32 TSEC2_RX_CLK AC29 l eTSEC2 receive clock T 10k to LVDD on module X1 34 low active signal pull up 4 pull down element in series User s Manual TQMP2020 UM 102 2012 by TQ Group Page 55 Table 17 Pinout according to functional groups continued SERDES Signal CPU Pin Type Description Module Pin SD TX3 AD18 O SERDES transmit data 3 X1 89 SD_TX3 AE18 O SERDES transmit data 3 complement X1 91 SD_TX2 AE17 O SERDES transmit data 2 X1 97 SD_TX2 AF17 O SERDES transmit data 2 complement X1 99 SD_TX1 AE13 O SERDES transmit data 1 X1 105 SD_TX1 AF13 O SERDES transmit data 1 complement X1 107 SD_TXO AD12 O SERDES transmit data 0 X1 113 SD_TXO AE12 O SERDES transmit data 0 complement X1 115 SD_RX3 AH18 SERDES receive data 3 X1 94 SD_RX3 AJ18 SERDES receive data 3 complement X1 96 SD_RX2 AH16 SERDES receive data 2 X1 102 SD_RX2 AJ16 SERDES receive data 2 complement X1 104 SD_RX1 AH14 SERDES receive data 1 X1 110 SD_RX1 AJ14 SERDES receive data 1 complement X1 112 SD_RXO AH12 SERDES receive data 0 X1 118 SD_RXO AJ12 SERDES receive data 0 complement X1 120 SD_REF_CLK AG15 SERDES PLL referenc
11. User s Manual TQMP2020 UM 102 2012 by TQ Group Page 35 3 2 4 11 Standard clock frequencies Table 11 Standard clock frequencies with P2020 Clock Frequency MHz Remark SYSCLK 66 666 Input clock system PLL CCB_CLK 400 Platform clock CORE_CLK 1 200 Core clock LCLK 25 50 100 Standard frequency underlined DDRCLK 66 666 Input clock DDR PLL frequency identical with SYSCLK DDR_CLK 800 Data rate MCKx MCKx 400 half data rate physical clock RTC Freely selectable Not connected on module USB_CLK 60 When required externally SD_REF_CLK SD 100 125 When required externally _REF_CLK frequency depending on protocol and data rate 3 2 5 Local Bus The available chip selects are assigned as follows Table 12 Assignment chip selects at the Local Bus Chip select Usage on TQMP2020 LCSO CS_NOR NOR flash boot LCS1 Free LCS2 Free LCS3 Free LCS4 Free LCS5 DMA2_DREQ1 Free if not used for DMA LCS6 DMA2_DACK1 Free if not used for DMA LCS7 DMA2_DDONE1 Free if not used for DMA Page 36 User s Manual TQMP2020 UM 102 2012 by TQ Group 3 2 6 NOR flash e 3 3 V flashes Micron PC28FxxxM29EW alternatively EON EN29GL 16 bit wide e Connected at the Local Bus because of multiplexed addresses and data gt addresses via a latch e One bank with 16 bit bus width e 16 to 256 Mibyte e Access time 100 ns e Chip select LCSO
12. and monitored internally 3 2 2 5 Supervision VDD The required core voltage depends on the CPU P2 or P1 It is set at the voltage regulator by component placement and in the supervisor by the configuration The user cannot change this setting 3 2 2 6 Supervision VREF The DDR3 reference voltage VREF is monitored internally 3 2 2 7 Supervision VTT The DDR3 termination voltage VTT is generated and monitored internally 3 2 2 8 Reset LED e LED is controlled via the HRESET Signal HRESET low gt LED lights up e The supervisor provides duration for at least 200 ms of the HRESET pulse The reset is thereby visible even if the reset pulse at RESIN is very short User s Manual TQMP2020 UM 102 2012 by TQ Group Page 15 3 2 2 9 Self reset The P2020 can request a hardware reset by software The signal HRESET_REQ signals the reset requirement It can be triggered by software by writing to register bit RSTCRIHRESET REOI The following participants can also trigger HRESET_REQ e Boot sequencer error Preamble CRC e eSDHC boot loader error e g boot signature e eSPI boot loader error e g boot signature e Not correctable eLBC ECC Error during boot phase of NAND flash e Rapid IO e e500 watchdog RESIN is connected to HRESET_REQ with a resistor on the module Illustration 2 VCC3V3 R146 FR D31 HRESET_REQ Es 2 TOR il aes TALVG RESIN 2 C5 12 C3 2 03 Hier ggf exteme Be
13. checking enabled eLBC ECC checking enabled cfg_eng_use 0 7 LA 20 22 PORDEVSR2 000x0000 Reserved for engineering use Not used UART_SOUTO Reserved for engineering use Not used ed READY_PO 111x1110 Reserved for engineering use Not used rn i Default Not used SRCID4 see cfg srds pll toe DMA1_DDONE Page 22 User s Manual TQMP2020 UM 102 2012 by TQ Group Table 7 Reset configuration continued Config signal 10 signal at the P2020 Register Value Meaning P2020 cfg_host_agt 0 2 LWE1 LBS1 PORBMSR 13 15 000 Agent onall PCle and SRIO Meaning P1020 P1021 Agent on all PCle LA 18 19 001 Agent on PCle 1 or host SRIO 2 Host on PCle 2 SRIO 1 Host on PCle 3 Agent on PCle 1 Host on PCle2 010 Host on PCle 1 or agent SRIO 2 Agent on PCle 2 SRIO 1 Host on PCle 3 Host on PCle 1 Agent on PCle 2 011 Host on PCle 1 SRIO 2 Host on PCle 2 SRIO 1 Agent on PCle 3 Reserved 100 Agent on PCle 1 SRIO 2 Agent on PCle 2 SRIO 1 Host on PCle 3 Reserved 101 Agent on PCle 1 or host SRIO 2 Host on PCle 2 SRIO 1 Agent on PCle 3 Reserved 110 Host on PCle 1 or agent SRIO 2 Agent on PCle 2 SRIO 1 Agent on PCle 3 Reserved Host processor root complex for all PCle SRIO Host processor root complex for all PCle Table 7 Config signal Reset configuration continued 10 signal at the P2020 Regis
14. e Preconfiguration to boot via other systems or interfaces e g PCle Rapid IO SDRAM e Fixing of incompatibilities with reset values e g preset functionality of the bus driver control LBCTL Wrong data can lead to an unbootable system This condition can be fixed by temporary activation of the default configuration because the boot sequencer is deactivated then See also tip 2 under 3 2 3 5 The CPU operates the I C bus at about 160 kHz when the boot sequencer is used Devices which can only work at a maximum of 100 kHz may not be connected to IIC1 when the boot sequencer is enabled This only affects the baseboard as all FC bus devices on the TQMP2020 can operate at 400 kHz Page 30 A User s Manual TQMP2020 UM 102 2012 by TQ Group 3 2 4 Clock 3 2 4 1 Internal clock structure of the P2020 2010 SYSCLK 66 7 MHz 100 MHz e500 Core Complex 2 e500 Core Complex 1 TCK TSTCLK Dx ci Dd RTC CORE BYPASS CLK LEKI12 17 MHz 150 MHz LSYNC_OUT LSYNC_IN DoE MCK 0 5 66 7 MHz 100 MHz MCKI0 5 SD_REF_CLK ys 100 MHZ or 125 MHz gt lt SD_REF_CLK 100 MHZ or 125 MHz TSEC 1 3 _TX_CLK TSEC 1 3 _RX_CLK TSEC 1 3 _GTX_CLK USB_CLK USBDR lt SDHC_CLK eSDHC SRIO SPI_CLK SPI EC_MDC EC_GTX_CLK125 TSEC_1588_CLK ner sed Pc ee TSEC_1588_CLK_OUT gt O
15. highest stack height bottom side f 2 46 0 0 46 CPU top side not drawn a 5 040 2 X1 l EO EE 1 PM 160 Dig X3 jan TIK ET i u m ja TT DD UDDODUNONDDN00N0000000000000000000000000000000000000F Ti 1 wt ATT Mn 160 2 9 Xx 23 1 71 1 74 Illustration 9 Overall dimensions top view through board 3 7 Bootloader The boot loader U Boot is the basic software delivered with the TQMP2020 More information can be found in the Support Wiki for the TOMP2020 User s Manual TQMP2020 UM 102 2012 by TQ Group Page 61 4 SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS 4 1 EMC The module was developed according to the requirements of electromagnetic compatibility EMC Depending on the target system anti interference measures may still be necessary to guarantee the adherence to the limits for the overall system Following measures are recommended e Robust ground planes adequate ground planes on the printed circuit board Contacting of all DGND pins of the module e With metal casings a good at least according to RF connection of the PCB ground to the housing e A sufficient number of blocking capacitors in all supply voltages e Fast or permanent clocked lines e g clock should be kept short avoid interference of other signals by distance and or shielding do not route tracks via separating trenches e Filtering of all signals which can be con
16. is used the IO voltages at the CPU LVDD and at the PHYs must be the same See also 3 3 2 3 Page 12 User s Manual TQMP2020 UM 102 2012 by TQ Group 3 2 1 2 Serializer Deserializer SerDes The SerDes controller can be operated as a SGMII PCI Express or Serial Rapid IO e SGMII Highest frequency to be transmitted 625 MHz 1 25 Gbit s e PCI Express e Serial Rapid IO Highest frequency to be transmitted 1 25 GHz 2 5 Gbit s Highest frequency to be transmitted 1 563 GHz 3 125 Gbit s Serial Rapid IO SRIO is only supported by the P2020 and the P2010 The following table shows the possible configurations of the SerDes controllers Table 4 SerDes configuration possibilities P2020 10 P1020 11 P1021 12 SerDes lanes Gbaud 3 0 1 2 0 amp 1 2 amp 3 PEX1 x 1 Off Off off 2 5 PEX1 x 1 PEX2 x 1 PEX3 x 2 25 2 5 PEX1 x 2 PEX3 x 2 2 5 2 5 PEX1 x 4 2 5 SRIO2 x 1 SRIO1 x 1 off off 3 125 SRIO2 x 4 1 25 2 5 3 125 SRIO2 x 1 SRIO1 x 1 SGMII2 SGMII3 125 25 1 25 PEX1 x 1 SRIOT x 1 SGMII2 SGMII3 2 5 1 25 PEX1 x1 PEX2 x 1 SGMII2 SGMII3 2 5 1 25 PEX1 x 2 SGMII2 SGMII3 2 5 1 25 Off Off Off Off 2 Underlined also P1020 11 and P1021 12 The configuration of the SerDes controller is carried out via the CPLD which reads the configuration from the configuration EEPROM See also 3 2 3 considering Table 3 User s Manual TQMP2020
17. module X1 69 TSEC_1588_TRIG_IN1 AH20 l IEEE1588 trigger in 1 T 10k to LVDD on module X1 71 TSEC_1588_TRIG_IN2 AG20 IEEE1588 trigger in 2 T 10k to LVDD on module X1 73 TSEC_1588_ALARM_OUT1 AE20 O IEEE1588 alarm out 1 X1 77 TSEC_1588_ALARM_OUT2 AJ20 O IEEE1588 alarm out 2 X1 79 TSEC_1588_CLK_OUT AG22 O IEEE1588 clock out X1 70 TSEC_1588_PULSE_OUT1 AH21 O IEEE1588 pulse out 1 X1 72 TSEC_1588_PULSE_OUT2 AJ22 O IEEE1588 pulse out 2 X1 74 EC_MDC AD20 O Ethernet management data clock X1 76 Ethernet management data in out MDR Az ue T 10k to LVDD on module ne eTSEC Gigabit reference clock EC_GTX_CLK125 AF24 l 10k to DGND on module X1 80 TSEC1 TXDZ TSEC3 TXD3 AF22 O eTSEC1 transmit data 7 eTSEC3 transmit data 3 X1 53 TSEC1 TXD6 TSEC3 TXD2 AD22 O eTSEC1 transmit data 6 eTSEC3 transmit data 2 X1 51 TSEC1_TXD5 TSEC3_TXD1 AD23 O eTSEC1 transmit data 5 eTSEC3 transmit data 1 X1 49 TSEC1_TXD4 TSEC3_TXDO AE21 O eTSEC1 transmit data 4 eTSEC3 transmit data 0 X1 47 TSEC1_TXD3 AJ25 O eTSEC1 transmit data 3 X1 45 TSEC1_TXD2 AH28 O eTSEC1 transmit data 2 X1 41 TSEC1_TXD1 AE25 O eTSEC1 transmit data 1 X1 39 TSEC1_TXDO AD24 O eTSEC1 transmit data 0 X1 37 eTSEC1 transmit enable TSEC1_TX_EN AH24 O 10kto DGND on module X1 55 TSEC1_TX_ER AF23 O eTSEC1 transmit error X1 57 eTSEC1 transmit clock in TSEC1_TX_CLK AJ24 l T 10k to LVDD on module X1 61 TSEC1_GTX_CLK AG25 O eTSEC1 transmit clock out X1 63 TSEC1_CRS TSEC3_RX_DV AJ27 vo eTSEC carrier se
18. to boot e500 core 0 is allowed to boot without without waiting for configuration by an external master while e500 core 1 is prevented from booting until configured by an external master or the other core waiting for configuration by an external master while e500 core 1 is prevented from booting until configured by an external master or the other core Both e500 cores are allowed to boot without waiting for configuration by an external master Both e500 cores are allowed to boot without waiting for configuration by an external master User s Manual TQMP2020 UM 102 2012 by TQ Group Page 21 Table 7 Reset configuration continued Config signal 10 signal at the P2020 Register Meaning P2020 Meaning P1020 P1021 Value cfg_ddr_debug DMA2_DDONEO PORDBGMSRIZ 0 ECC pins driven Debug info ECC pins driven Debug info instead of instead of normal ECC I O normal ECC VO disconnect memory devices disconnect memory devices ECC pins in normal mode ECC pins in normal mode cfg_device_ID 7 5 TSEC2_TXD 4 2 PORDEVSR 29 31 XXX Device ID LSBs for Rapid IO Not used hosts cfg_dram_type TSEC2_TXD1 PORDEVSR 25 0 DDR2 1 8 V CKE low reset DDR2 1 8 V CKE low reset DDR3 1 5 V CKE low reset DDR3 1 5 V CKE low reset cfg_elbc_ecc MSRCIDO PORDEVSR 15 0 eLBC ECC checking disabled eLBC ECC checking disabled eLBC ECC
19. 0 UM 102 2012 by TQ Group Page 1 1 ABOUT THIS MANUAL 1 1 Copyright Copyright protected 2012 by TQ Components GmbH This User s Manual may not be copied reproduced translated changed or distributed completely or partially in electronic machine readable or in any other form without the written consent of TQ Components GmbH 1 2 Tips on safety Improper or incorrect handling of the product can substantially reduce its life span 1 3 Symbols and typographic conventions Table 1 Terms and conventions Symbol Visual Cue Meaning This symbol represents the handling of electrostatic sensitive modules and or components These components are often damaged destroyed by the transmission of a voltage higher than about 50 V A human body usually only experiences electrostatic discharges above approximately 3 000 V This symbol indicates the possible use of voltages higher than 24 V Please note the relevant statutory regulations in this regard Non compliance with these regulations can lead to serious damage to your health and cause damage destruction of the component This symbol indicates a possible source of danger Acting against the procedure described can lead to possible damage to your health and or cause damage destruction of the material used This symbol represents important details or aspects for working with TQ products gt gt gt This specification is used to state the comp
20. 20 10 ee ee ee ee en en en ee ee ee ee ee ee ee ek ek ek eg eg eg egg 30 Internal clock structure of the P1020 1011 and P1021 1012 31 System clock SYSCLK cccsseesseeeeees 32 Core Complex Bus clock CCB_CLK 32 Processor Core clock CORE CLK esse ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 32 Local IE ale d died EA AE EE N 32 Memory bus clocks DDRCLK DDR CLK MCKx MCK ees seen seek ese eek eek ee ee eek ee 34 Real time clock RTC USB clock USB_CLK SERDES clock SD_REF_CLK SD_REF_CLK ccssssssssssesssssscsssssscsssssscsssssscsscssscsscssscencesscencesses 34 Standard clock freQuenci s c cssssssssssssessscsscsssssscsssssscsssssscsssssscsssssucssscsscessssscsusssscsucssscesessseeseeses 35 Hele AR AE A 35 Neil AR 36 DDR3 SDRAM 36 PC bus 37 Data EEPROM 38 Configuration EEPROM cssssssssscssecssecssscssecssecssessusecssecsuessucesssesssecsuceeatecsuessucesasecsersueesneessseess 38 RTC real time clock sees ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 39 Temperature supervision 39 General Purpose I O 39 Tee 40 Power sequeneing sroin nS SSNS UNSS NNNSN 40 SS Ufo a VAL el EER E EEEE A ET 41 VCC3V3IN main supply Al VBAT RTC supply Al LVDD Ethernet I O supply Al BVDD Local Bus SUPPLY sscsssdscsescssssscasssesassceassscsasateavasecasssvasasecasaseavastcasstcasastcasatcasastcasateasaesauaseend 41 CVDD supply USB SDHC a
21. 27 X2 78 LA28 A23 O Local Bus burst address 28 X2 80 LA29 B23 0 Local Bus burst address 29 X2 82 LA30 C23 0 Local Bus burst address 30 X2 84 LA31 D23 0 Local Bus burst address 31 X2 86 low active signal pull up 4 pull down element in series Page 52 m User s Manual TQMP2020 UM 102 2012 by TQ Group Table 17 Local Bus continued Signal CPU Pin Type Pinout according to functional groups continued Description Module Pin Local Bus chip select 0 LCSO CS_NOR D20 O Used internally for NOR flash X3 15 T 4k7 to VCC3V3 on module Local Bus chip select 1 ged mle 7 T 4k7 to VCC3V3 on module EM Local Bus chip select 2 LC524 Ele 2 T 4k7 to VCC3V3 on module ie Local Bus chip select 3 Ber BA e T 4k7 to VCC3V3 on module x323 Local Bus chip select 4 ice eu Q T 4k7 to VCC3V3 on module en Local Bus chip select 5 DMA2 request 1 LCS5 DMA2_DREQ1 D15 VO x AKT to VCC3V3 on module X3 4 Local Bus chip select 6 DMA2 acknowledge 1 LCS6 DMA2_DACK1 D13 O T AKT to VCC3V3 on module X3 6 Local Bus chip select 7 DMA2 done 1 LCS7 DMA2_DDONE1 A17 O T 4k7 to VCC3V3 on module X2 59 LWEO LFWE LBSO F12 Local Bus write enable 0 NAND flash write enable X2 57 byte lane select 0 LWE1 LBS1 D12 O Local Bus write enable 1 byte lane select 1 X3 2 LBCTL E17 0 Local Bus data buffer contro
22. 3 Vee see see se ee Gee ee ee ee ek Ge ek Ge Ge Ge Ge Roe Roe ee ee ee ee ee ee ee ee ek GER Gegee Reg 13 SUPETVISION 2S ER EE 14 Supervision 1 8 V Supervision 1 5 V Supervision VDD 14 SUPETVISION N dd EE SES EENES SENON PEEEESSSS EEEE rEEECARRERE ESEESE ESEESE EEREREA ESSERE EEES EEEE aaS 14 SUPETYISION AAR ERG N 14 RESCUE LED N N HET 14 SARA nme Rre III III III 15 JTAG reset TRST 16 GIP WOM TIGA LIO EE 17 Reset configuration of the hardware ccsssssssecssesssecseccssecseecseeesseeesecesesencecseesseceenceeseesseeesees 17 Freely available reset configuration c ssescssesssecseecsssecseccseecsseccsecesscesscesusecseccsseesucessecsseeesees 26 Other configuration signals eesesesseesseecsssecseessessssecseecseecsscccscesseecsccsucecseesseeesucecseesseesseeeeseetse 26 Configuration data in the EEPROM 27 Error handling and default configuration Settings via the boot sequencer unensessesssenssenssenssenssennssunssenssenssnnssenssenssnnnssenssennsnunssnnnsennnnn 29 Page ii User s Manual TQMP2020 UM 102 2012 by TQ Group Table of contents continued 3 2 4 3 2 4 1 3 2 4 2 3 2 4 3 3 2 4 4 3 2 4 5 3 2 4 6 3 2 4 7 3 2 4 8 3 2 4 9 3 2 4 10 3 2 4 11 3 2 5 3 2 6 3 2 7 3 2 8 3 2 8 1 3 2 8 2 3 2 8 3 3 2 8 4 3 2 9 3 3 3 3 1 3 3 2 3 3 2 1 3 3 2 2 3 3 2 3 3 3 2 4 3 3 2 5 3 3 3 3 3 3 1 3 3 3 2 3 3 3 3 EIKE EE EE EE EE AE 30 Internal clock structure of the P2020
23. 30 000 4 1 4 1 001 5 1 5 1 6 1 6 1 011 8 1 Reserved others Reserved Reserved cfg_core0_pll 0 2 LBCTL PORPLLSR 10 15 000 4 1 Reserved en 001 92 4 5 1 Reserved 010 1 1 1 1 011 3 2 1 5 1 3 2 1 5 1 2 1 2 1 101 5 2 2 5 1 5 2 2 5 1 110 3 1 3 1 111 7 2 3 5 1 Reserved User s Manual TQMP2020 UM 102 2012 by TQ Group A Page 19 Table 7 Reset configuration continued Config signal 10 signal at the P2020 Register Value Meaning P2020 Meaning P1020 P1021 cfg_core1_pll 0 2 LWEO PORPLLSR 2 7 000 4 1 Reserved UART_SOUTI 001 92 4 5 1 Reserved READ FA 010 1 1 1 1 011 3 2 1 5 1 3 2 1 5 1 2 1 2 1 101 5 2 2 5 1 5 2 2 5 1 110 3 1 3 1 111 72837 Reserved cfg_ddr_pll 0 2 TSEC_1588_CLK_OUT PORPLLSR 18 22 000 Reserved 3 1 TSEC_1588_PULSE_OUT 1 2 001 4 1 4 1 010 6 1 6 1 011 8 1 8 1 10 1 10 1 101 12 1 Reserved 110 Reserved Reserved 111 Synchronous mode Synchronous mode cfg_srds_pll_toe TRIG_OUT READY_PO PORDEVSR2 10 Enable PLL lock time out counter Not used POR sequence waits for SerDes PLL to lock while time out counter has not expired 1 Disable PLL lock time out counter Not used POR sequence waits for SerDes PLL to lock cfg_plat_speed LA23 PORDEVSR2 14 0 Platform clock lt 333 MHz Platform clock lt 300 MHz and gt 267 MHz Platform clock 2333 MH
24. 32 via transceiver Signal CPU Pin Type Description Module Pin RS232_SINO UARTO serial in data RS232 level X2 147 RS232_SOUTO 0 UARTO serial out data RS232 level X2 149 RS232_SIN1 l UART1 serial in data RS232 level X2 150 RS232_SOUT1 0 UART1 serial out data RS232 level X2 152 CPUPin Type Description Module Pin UARTO serial in data LVTTL level UART_SINO H29 T 10k to VCC3V3 on module if RS232 transceiver is not X2 151 assembled Do not connect if RS232 transceiver on module is used UART_SOUTO J26 0 UARTO serial out data LVTTL level X2 153 UARTO clear to send LVTTL level ES J28 T 10k to VCC3V3 on module er UART_RTSO J29 O UARTO request to send LVTTL level X2 155 UART1 serial in data LVTTL level UART SINT G24 7 10k to VCC3V3 on module if RS232 transceiver is not X2 159 assembled Do not connect if RS232 transceiver on module is used UART_SOUT1 J25 O UARTI serial out data LVTTL level X2 160 UART1 clear to send LVTTL level VAR GIS nes 10k to VCC3V3 on module X2 156 UART_RTS1 J24 0 UART1 request to send LVTTL level X2 158 low active signal pull up 4 pull down element in series User s Manual TQMP2020 UM 102 2012 by TQ Group Page 51 Table 17 Pinout according to functional groups continued
25. AG26 l eTSEC1 receive clock T 10k to LVDD on module X1 35 TSEC2_TXD7 AE26 O eTSEC2 transmit data 7 X1 54 TSEC2_TXD6 AF26 O eTSEC2 transmit data 6 X1 50 TSEC2_TXD5 TSEC3_TX_EN AB24 o eTSEC2 transmit data 5 eTSEC3 transmit enable J 10k to X1 48 DGND on module TSEC2_TXD4 eTSEC2 transmit data 4 TSEC3_GTX_CLK AB25 eTsEC3 transmit clock out Me TSEC2_TXD3 AG29 O eTSEC2 transmit data 3 X1 44 TSEC2_TXD2 AA25 O eTSEC2 transmit data 2 X1 42 TSEC2_TXD1 AF27 g eTSEC2 transmit data 1 X1 40 TSEC2_TXDO Y24 O eTSEC2 transmit data 0 X1 38 eTSEC2 transmit enable TSEC2_TX_EN AA26 O 10kto DGND on module X1 56 TSEC2_TX_ER AE29 g eTSEC2 transmit error X1 58 eTSEC2 transmit clock in TSEC2_TX_CLK AA24 l T 10k to LVDD on module X1 60 TSEC2_GTX_CLK AG28 O eTSEC2 transmit clock out X1 62 eTSEC2 carrier sense eTSEC3 receive error TSEC2_CRS TSEC3_RX_ER AD25 VO T 10k to LVDD on module X1 64 TSEC2_COL TSEC3_TX_CLK AE27 eTSEC2 collision detect eTSEC3 transmit clock in T 10k X1 66 to LVDD on module TSEC2_RXD7 AD27 l eTSEC2 receive data 7 T 10k to LVDD on module X1 28 TSEC2_RXD6 AB26 l eTSEC2 receive data 6 T 10k to LVDD on module X1 26 TSEC2_RXD5 AC26 l eTSEC2 receive data 5 T 10k to LVDD on module X1 24 TSEC2_RXD4 AD26 l eTSEC2 receive data 4 T 10k to LVDD on module X1 22 TSEC2_RXD3 AB27 I eTSEC2 receive data 3 T 10k to LVDD on module X1 18 TSEC2_RXD2 AD28 l eTSEC2 receive data 2 T 10k to LVDD on module X1 16 TSEC2_RXD1 AF29 l eTSEC2 receive data 1
26. CL G27 VO C1 Serial clock T 2k4 to VCC3V3 on module X2 131 IIC2_SDA H26 VO 1C2 Serial data T 4k7 to VCC3V3 on module X2 134 IIC2_SCL H25 VO P C2 Serial clock T 4k7 to VCC3V3 on module X2 132 low active signal pull up 4 pull down element in series CPUPin Type Description Module Pin HRESET W25 Hard reset driven on module X2 137 P2020 input TQMP2020 output see Illustration 7 HRESET_REQ U24 O Hard reset request T 2k2 to VCC3V3 on module X2 139 connected to RESIN via 10k on module SRESET W24 l Soft reset T 4k7 to VCC3V3 on module X2 141 CKSTP_INO AA29 Checkstop in 0 T 4k7 to VCC3V3 on module X2 135 CKSTP_IN1 AB29 Checkstop in 1 T 4k7 to VCC3V3 on module X2 136 CKSTP_OUTO V25 O Checkstop Out 0 T 4k7 to VCC3V3 on module X2 142 CKSTP_OUT1 Y27 O Checkstop Out 1 T 4k7 to VCC3V3 on module X2 140 low active signal Non CPU Signals Signal T pull up J pull down gt element in series CPU Pin Type Description Real time clock interrupt outputs INTA and Module Pin use for baseboard power sequencing RTC_INT O SQW INTB DS1337 connected together X2 148 T 10k via Schottky diode to VCC3V3 on module Temperature sensor alarm outputs EVENT SE97B TEMP_OS O ALERT and T_CRIT SA56004E connected together X2 146 T 10k to VCC3V3 Reset Input Reset input of voltage superv
27. CPLD transmits a reset sequence on the I C bus IIC1 before the real access This ensures that accesses still running at the time of the reset are completed and the EEPROM is ready to be read To ensure the system integrity the configuration mechanism handles the following errors e C protocol error e Configuration ID missing e CRC incorrect In these cases the CPLD starts another attempt If this also fails the default configuration will be passed to the CPU highlighted in blue in Table 7 This guarantees that the system boots but with certain functional limitations lower clock interfaces partly not available The CRC used the polynomial x x x 1 and the start value OxFF A tool which calculates the CRC can be made available if required Damaged or deleted configuration data generates a CRC error and causes the use of the default configuration With the again bootable system the EEPROM can be rewritten Another possibility is to pull IIC1_SDA low This leads to a protocol error NACK and therefore the default configuration to be used In this manner a system with two different boot configurations can be operated e g a normal operation config EEPROM with boot process via PCle or eSDHC and a service or emergency operation default config with boot loader in the NOR flash The enable bits enable the configuration of single fields not via the module but via the baseboard without reprogramming the EEPROM Thus e g
28. D1022 IRQ9 I Reserved external interrupt 9 do not connect X2 128 RSVD1022 IRQ10 Reserved external interrupt 10 do not connect X2 130 RSVD1022 IRQ11 Reserved external interrupt 11 do not connect X3 1 low active signal pull up 4 pull down element in series Page 58 User s Manual TQMP2020 UM 102 2012 by TQ Group 3 5 Cooling 3 5 1 Power dissipation The maximum power dissipation at 400 1200 800 MHz CCB Core DDR is 16 W cf 3 3 2 1 This value applies to the design of the supply and includes short term peak loads The thermal design power at 400 1200 800 MHz CCB Core DDR is 12 W This value applies to the design of the cooling Because of the thermal inertia of the system a lower power loss is valued in average 3 5 2 Heat sink The Starterkit STKP2020 shows a cooling solution with active cooling fan which is sufficient for many applications Regardless of the shown solution the cooling solution has to be adapted to each specific case Clock frequency stack height available airflow etc The operation without heat sink is also temporarily prohibited This also applies to laboratory use and operation at room temperature 3 6 Mechanics 3 6 1 General information e Double sided SMD component placement e High pin count SMD plug connectors with 0 8 mm pitch e Mating plugs with different heights enable customisation of the stacks heigh
29. DDRCLK SYSCLK The frequency of the Memory Bus clock DDR_CLK corresponds to the DDR data rate It is twice as high as the frequency of the signals MCKx and MCK Favourite frequency DDR_CLK 800 MHz multiplied from DDRCLK 66 666 MHz x 12 TQMP 1 xxx 666 MHz from DDRCLK 66 666 MHz x 10 3 2 4 8 Real time clock RTC The signal RTC is a clock input through which a time base can be created which is independent of the system clock The signal RTC is available at the connector but not connected on the module More detailed information can be found in the hardware specification of the CPU 1 3 2 4 9 USB clock USB_CLK The signal USB_CLK is required for the interface to the external USB PHY The USB controller runs synchronically to CCB_CLK If USB is used a 60 MHz clock must be fed at this signal More detailed information can be found in the hardware specification of the CPU 1 3 2 4 10 SERDES clock SD_REF_CLK SD_REF_CLK The signal pair SD_REF_CLK SD_REF_CLK is required for the SERDES interface The system side runs synchronically to CCB_CLK If the SERDES interface is used depending on protocol and data rate a clock of 100 or 125 MHz must be supplied here If no SERDES clock is supplied the reset configuration has to prevent that the CPU waits for the SERDES PLL to lock after a reset See also cfg_srds_pll_toe under 3 2 3 1 More detailed information can be found in the hardware specification of the CPU 1
30. Manual TQMP2020 UM 102 2012 by TQ Group 3 3 Supply 3 3 1 Power sequencing The module is supplied with 3 3 V only All other voltages are generated on the module The integrated power manager ensures valid power sequencing For that reason the external supplied 3 3 V are routed via a switch To guarantee the correct power sequencing for the variable I O voltages LVDD and CVDD as well LVDD and CVDD may not be supplied by an external supply voltage LVDD and CVDD must be fed via the provided pins VCC3V30UT VCC2V5OUT or VCC1V8OUT see Illustration 7 TQMP2020 VCC3V3IN i Power Manager ie a State Machine VCC3V3 gt VCC3V30UT 1 en EN l LVDD 1 7 a g VOoc2Vv5 gt VCC2V50UT gt 7 1 q Zu J cvpp L J AE i Mes oJ VCC1V8 VCC1V8OUT gt 4 1 l VCC1V5 gt gt VCC1V5 4 y 1 gt i VREF Range gt VREF opt oor Z 1 q gt ft Zn VTT e Range VIT t BE R 1 L VDD gt VDD 4 gt l Timer i p RESIN gt HRESET gt Illustration 7 Supply structure simplified User s Manual TQMP2020 UM 102 2012 by TQ Group Page 41 3 3 2 Supply inputs For the supply voltages to be fed the following limits apply 3 3 2 1 VCC3V3IN main supply Table 14 Requirements for 3 3 V ext
31. O R W ADM1068 Combined in one device Page 38 User s Manual TQMP2020 UM 102 2012 by TQ Group 3 2 8 1 Data EEPROM The serial EEPROM can store e g characteristics of the module and customer specific parameter data In the EEPROM single memory cells can be deleted and be overwritten in contrast to flash At delivery the EEPROM is erased It can e g save application parameters permanently e 32 Kibyte 256 Kibit or not assembled e Is freely available for user s data e Can be used for boot sequencer when required e Controlled via IC controller IIC1 device address see Table 13 3 2 8 2 Configuration EEPROM At delivery the configuration EEPROM contains a standard reset configuration see 3 2 3 5 e Combined device SE97B e 256 bytes 2 Kibit e Used for reset configuration e Update by the CPU is possible e Temporary or permanent write protection possible e Controlled via I C controller IIC1 device address see Table 13 An altered reset configuration can lead under certain circumstances to an unbootable system In this case there are several possibilities to get back to a functioning reset configuration e It is possible to connect an external master programming unit at the IC bus The support of TQ Components can recommend a suitable tool e _ Recovery by module software It is a prerequisite that the software in the NOR flash on the module runs with th
32. TQMP2020 UM 102 24 05 2012 User s Manual TQMP2020 UM 102 2012 by TQ Group 10 Pagei Table of contents 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 3 1 3 1 1 3 1 2 3 2 3 2 1 3 2 1 1 3 2 1 2 3 2 1 3 3 2 2 3 2 2 1 3 2 2 2 3 2 2 3 3 2 2 4 3 2 2 5 3 2 2 6 3 2 2 7 3 2 2 8 3 2 2 9 3 2 2 10 3 2 3 3 2 3 1 3 2 3 2 3 2 3 3 3 2 3 4 3 2 3 5 3 2 3 6 ABOUT THIS MANUAL siscssssssssssssssssssssvsassasvsessanvssanaavassnanvacsnsnvssananvasapaavasananvasssansasasanissssansaasnaavaansaobes 1 COPYHONE EE EE aie eite 1 Tips on safety ed Symbols and typographic conventions id Handling and ESD tips a2 Registered trademarkS c sssssssssssssscssecssecssssssecssecsscssscesaseessessscssseeessecsucesseecaeessecssessaceeseesseeesseesaes 2 ga ele OE EE OE OO 3 Dis laimet ie EE EE seeserekenee Copyright and licence expenses esse seek eek GR ae eek GR Gee eek ee eek eek AAR eek ee Further applicable documents presumed knowledge Acronyms and definition ese eek GR ee Raak ee ee Rek ee ee ee eek GR ee eek GR ee eek ee BRIEF DESCRIPTION 4 0 tse ie BP AE EEEIEE E BR A E SSA E TQMP2020 block diagram System components Electronics Ad OE EE N EE Parallel Modes of the Enhanced Three Speed Ethernet Controller eTSEC 10 Serializer Deserializer SerDes uses se see ee ee RR ek ek eke eg eg eg eke ee 12 VR RE 13 Reset logic and supervisor 13 Supervision 3
33. UM 102 2012 by TQ Group Page 13 3 2 1 3 USB In contrast to P2020 10 and the P1021 12 the P1020 11 possesses two USB controllers Because Local Bus and USB2 are multiplexed with the P1020 11 the second USB PHY ULPI must be connected at the Local Bus This means that the second USB PHY is almost completely limited in its function or the NOR flash can only be partly used 3 2 2 Reset logic and supervisor The reset logic contains the following functions e Supervision of the following voltages used on module 3 3V 2 5V 1 8V 1 5V VDD core voltage VREF reference voltage for DDR3 SDRAM VTT termination voltage for DDR3 SDRAM e _ External reset input debounced with 200 ms delay e PGOOD output e g for power sequencing of an external PHY e Indication of the reset state by a LED HRESET low gt LED lights up 3 2 2 1 Supervision 3 3 V Tolerance range of the fed supply voltage VCC3V3ID 3 201 V to 3 465 V 3 3 V 3 5 Permitted voltage range for CPU and 3 3 V logic VCC3V3 3 135 V to 3 465 V Tolerance of the voltage supervision voltage drop in VCC3V3 taken into account Vreset 3 135 V to 3 201 V Page 14 User s Manual TQMP2020 UM 102 2012 by TQ Group 3 2 2 2 Supervision 2 5 V This supply voltage is generated and monitored internally 3 2 2 3 Supervision 1 8 V This supply voltage is generated and monitored internally 3 2 2 4 Supervision 1 5 V This supply voltage is generated
34. UM 102 2012 by TQ Group Page 33 4 CPU Module Mainboard CPU lh Dee ei l LBus PLL L J LCLKO gt A i i Local Bus Devices LCLKn EET gt I N Zero Delay eae Es additional clocks if necessary LSYNC_OUT i L LSYNC_IN dl i l eh Routing Length on module is matched L LCKLO L LCKLn L LSYNC_OUT L LSYNC_IN EE a EE EE EE el Illustration 6 Length alignment Local Bus Two clock outputs LCKL 0 1 are provided externally A zero delay buffer has to be provided on the baseboard if more participants have to be supplied as clock outputs are available The following applies for the feedback e A feedback is only required if the Local Bus is used in PLL Enable mode e No feedback is required however if the PLL Bypass mode is used it may be present e The adjustment of the cable length is only required if participants which use the clock are connected to the Local Bus on the baseboard If this is not the case the length of the feedback is unimportant On the module are no bus participants which require the clock Page 34 User s Manual TQMP2020 UM 102 2012 by TQ Group 3 2 4 7 Memory bus clocks DDRCLK DDR_CLK MCKx MCK The Platform clock CCB_CLK can be used as an alternative to the Memory Bus clock DDR_CLK or be generated by an own PLL from
35. anual TQMP2020 UM 102 2012 by TQ Group 3 TECHNICAL DATA 3 1 Overview 3 1 1 TQMP2020 block diagram VO Supply Power Management NOR Flash DDR3 SDRAM EEPROM Supervisor Reset 16Bit Are Serial 12C 331 25V Power Sequencing 16 256 MB 256 MB 1 GB 0 32 KB Memory 12C Bus T en pas EE EE EE ES Ee pall As i RTC Freescale QorlQ CPU 1 5V 0 75 V P2020 P1020 1021 12C USB eTSEC WB TePBGA 689 1 i Ee 32 Bit 1200 800 MHz 4 2 USB 2 0 3 2 max Core Supply ULPI R GMII R TBI SGMII MMU FPU VD Cache CPLD 1 i Reset Configuration 1 05 1 00 V from 12C EEPROM l internal E A Interfaces 1 N 1 I 1 I i i Input Clock COP JTAG Local Bus SERDES i RS232 G 1 I 16 Bit Enhanced PCle v1 0a SGMII SRIO Drivers for 66 67 MHz CPU Test amp Debugging Local Bus 4 Lanes i 2 RS232 66 67 MHz DDR Meme A EE II 4 I l T T 40Pins Board to Board Connectors 2 160 1 40 Pins 0 8 mm Pitch optional ee Illustration 1 TQMP2020 block diagram User s Manual TQMP2020 UM 102 2012 by TQ Group Page 9 3 1 2 System components e OorlO processor P2020 or P2010 optional P1020 11 and P1021 12 e Oscillator for CPU clocks e Reset generator and power fail logic e CPLD for reset configuration e Voltage regulator for 2 5 V 1 8 V
36. d MDVAL cfg_rio_sys_size LGPLO LFCLE PORDEVSRI28 0 Large system size Not used up to 65536 devices Small system size Not used up to 256 devices cfg_rom_loc 0 3 TSEC1_TXD 6 4 PORBMSR 4 7 0000 PCle 1 PCle 1 TSEC1_TX_ER 0001 PCle2 PCle 2 0010 SRIO1 Reserved 0011 SRIO2 Reserved 0100 DDR DDR 0101 PCle3 Reserved 0110 On Chip boot ROM SPI config On Chip boot ROM SPI config 0111 On Chip boot ROM eSDHC config On Chip boot ROM eSDHC config 1000 eLBC FCM 8 bit NAND small page eLBC FCM 8 bit NAND small page 1001 Reserved Reserved 1010 eLBC FCM 8 bit NAND large page eLBC FCM 8 bit NAND large page 1011 Reserved Reserved 1100 Reserved Reserved 1101 eLBC GPCM 8 bit ROM eLBC GPCM 8 bit ROM 1110 eLBC GPCM 16 bit ROM eLBC GPCM 16 bit ROM eLBC GPCM 16 bit ROM eLBC GPCM 16 bit ROM formerly probably GPCM 32 bit formerly probably GPCM 32 bit cfg_sgmii2 LGPL1 LFALE PORDEVSRI3 0 eTSEC2 SGMII gt SGMII SerDes lane Not used 2 pins eTSEC2 Std gt TSEC2_ pins Not used cfg_sgmii3 TSEC_1588_ALARM_OUT2 PORDEVSRIA4 0 eTSEC3 SGMII SGMII SerDes lane eTSEC3 gt SGMII 3 pins eTSEC3 Std gt TSEC3_ pins eTSEC3 RGMII Table 7 Config signal 10 signal at the P2020 Reset configuration continued Register Value User s Manual TQMP2020 UM 102 2012 by TQ Group Ta Page 25 Meaning P2020 Meaning P1020 P1021
37. d in the EEPROM The single fields with configuration data consist of an Enable bit and the actual data field in each case Enable 0 Tri State Configuration data see Table 7 1 Actively driven during Reset Table 10 Configuration data in EEPROM Content Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Fixed Configuration ID 0 0 1 0 1 0 1 0 1 Enable cfg_boot_seq 0 1 Enable cfg_sys_pll 0 2 Enable 2 cfg_core0_pll 0 2 Enable cfg_core1_pll 0 2 Enable 3 cfg_ddr_pll 0 2 Enable cfg_srds_pll_toe Enable cfg_plat_speed Enable 4 cfg_core0_speed Enable cfg core1 speed Enable cfg_ddr_speed Enable cfg sys speed Enable 5 cfg cpul0 1 boot Enable cfg ddr debug Enable cfg device IDI7 5 6 Enable cfg dram typelEnable cfg elbc ecc Enable cfg eng usel0 2 7 cfg eng usel3 7 Enable cfg_host_agt 0 1 8 cfg_host_agt 2 Enable cfg_io_ports 0 3 Enable cfg_mem_debug 9 Enable cfg_rio_sys_size Enable cfg_rom_loc 0 3 Enable 10 cfg_sgmii2 Enable cfg sgmii3 Enable cfg_srds_refclk Enable cfg_tsec_reduce Enable 11 cfg_tsec1_prtcl 0 1 Enable cfg_tsec2_prtcl 0 1 Enable cfg_tsec3_prtcl 0 1 12 Enable cfg sdhc cd pol sel unused unused unused unused unused unused 13 CRC checksum Page 28 User s Manual TQMP2020 UM 102 2012 by TQ Group 3 2 3 5 Error handling and default configuration The
38. e clock X1 86 SD_REF_CLK AF15 SERDES PLL reference clock complement X1 88 low active signal Te pull up L pull down element in series Page 56 User s Manual TQMP2020 UM 102 2012 by TQ Group Table 17 Pinouta Module supply Signal PinCount Type ccording to functional groups continued Description Module Pin 2 Supply 3 3 V supply input See below VCC3V3IN X16 X1 8 8 Supply 3 3 V supply input See below n X1 1 X1 2 X1 3 X1 4 X1 5 X1 7 X1 9 X1 11 Battery Voltage connected directly to RTC supply pin and or ed _ ver 1 Supply Win VCC3V3 via Schottky diode A eTSEC IEEE1588 and Ethernet Management I O supply voltage Connect to either VCC3V30UT or VCC2V5OUT depending on x EDD 1 Supply Physical Interface Mode LVDD_VSEL will be set automatically nee depending on LVDD voltage USB eSDHC and eSPI VO supply voltage CVDD 1 Suppl Connect to VCC3V30UT VCC2V5OUT or VCC1V8OUT X2 3 PPY depending on desired I O voltage CVDD_VSEL 0 1 will be set automatically depending on CVDD voltage 3 3 V supply output after power sequencing switch t MEE PUT Supply Use for LVDD and or CVDD supply only sa 2 5 V supply output p Ween Supply Use for LVDD and or CVDD supply only et 1 8 V supply output z NEBR Supply Use for CVDD supply only EE Digital Ground 71 Supply For best signal integrity of high speed lanes connect all of see below the
39. e default reset configuration and that the I C bus can be accessed For a how to see 3 2 3 5 tip 1 3283 User s Manual TOMP2020 UM 102 2012 by TO Group Page 39 RTC real time clock As the CPU does not contain an internal bufferable RTC it was connected externally RTC DS1337U controlled via IC bus of the CPU Battery buffering possible battery on baseboard at VBAT Alarm outputs INTA and SQW INTB Open Drain are routed to a common pin Controlled via IC controller IIC1 device address see Table 13 30 ppm oscillator tolerance over the whole temperature range Temperature supervision Control of all sensors via I C controller IIC1 device addresses see Table 13 Measuring point 1 chip temperature of the CPU by internal measuring diode P10xx availability of the internal diode unclear Implemented by remote channel SA560004EDP Measuring point 1a assembly option External sensor alternatively to CPU internal measuring diode implemented by remote channel SA560004EDP on top side between CPU and switching regulator Measuring point 2 PCB bottom side close to DDR3 Implemented by local channel SA560004EDP Measuring point 3 PCB top side between DDR3 devices Implemented by combined device SE97B 3 2 9 General Purpose l O 16 GPIOs 9 of it multiplexed with other interface signals P1020 16 GPIOs P1021 no GPIOs Configured as input after power on reset Open drain capable Interrupt capable Page 40 User s
40. e on request but not standard 3 2 4 4 Core Complex Bus clock CCB_CLK The Platform or Core Complex Bus clock CCB_CLK is generated from the system clock signal SYSCLK by multiplication The multiplication factor is fixed by the reset configuration The signal merely exists CPU internally It is used for the L2 cache internal as well as for the Local Bus and other interfaces The frequency is set to 400 MHz by default Core frequencies of 600 800 1000 and 1200 MHz are possible with it see 3 2 4 5 TQMP 1 xxx 266 333 400 533 MHz 0 5 x frequency CORE_CLK or constant 266 MHz 3 2 4 5 Processor Core clock CORE_CLK The core clock CORE_CLK is generated by multiplication from CCB_CLK The multiplication factor is fixed by the reset configuration The signal merely exists CPU internally and is used for the e500v2 core s Possible frequencies are 600 800 1000 or 1200 MHz TQMP1020 TQMP1021 333 to 800 MHz gradation depending on CCB_CLK and multiplication factors 3 2 4 6 Local Bus clock LCLK The Local Bus clock LCLK is generated from CCB_CLK divided by LCRR CLKDIV values 4 8 or 16 The division factor LCRR CLKDIV is configurable at run time The signal is used for the Local Bus Possible frequencies with CCB_CLK 400 MHz are 25 50 100 MHz The maximum possible frequency LCLK for the P2020 is 150 MHz TQMP 1 xxx e withCCB_CLK 400MHz 25 50 MHz e withCCB_CLK 267MHz 17 33 66 MHz User s Manual TQMP2020
41. ence conditions of the respective manufacturer are to be adhered to Boot loader licence expenses are paid by TQ Components GmbH and are included in the price Licence expenses for the operating system and applications are not taken into consideration and must be separately calculated declared Page 4 User s Manual TQMP2020 UM 102 2012 by TQ Group 1 9 Further applicable documents presumed knowledge Specifications and manual of the used modules These documents describe the service functionality and special characteristics of the used module incl BIOS Specifications of the used components The manufacturer s specifications of the used components for example CompactFlash cards are to be taken note of They contain if applicable additional information that must be taken note of for safe and reliable operation These documents are stored at TQ Components GmbH Chip errata It is the user s responsibility to make sure all errata published by the manufacturer of each component are taken note of The manufacturer s advice should be followed Software behaviour No warranty can be given nor responsibility taken for any unexpected software behaviour due to deficient components General expertise Expertise in electrical engineering computer engineering is required for the installation and the use of the device User s Manual TQMP2020 UM 102 2012 by TQ Group Page5 1 10 Acronyms and definitions Table 2 Acro
42. erDes lane 1 SGMII 2 x1 1 25 Gbps SerDes lane 2 SGMII 3 x1 1 25 Gbps SerDes lane 3 1101 PCle 1 x1 2 5 Gbps SerDes lane 0 Reserved SRIO 1 1x 2 5 Gbps SerDes lane 1 SGMII 2 x1 1 25 Gbps SerDes lane 2 SGMII 3 x1 1 25 Gbps SerDes lane 3 1110 PCle 1 x1 2 5 Gbps SerDes lane 0 PCle 1 x1 2 5 Gbps SerDes lane 0 PCle 2 x1 2 5 Gbps SerDes lane 1 PCle 2 x1 2 5 Gbps SerDes lane 1 SGMII 2 x1 1 25 Gbps SerDes lane 2 SGMII 2 x1 1 25 Gbps SerDes lane 2 SGMII 3 x1 1 25 Gbps SerDes lane 3 SGMII 3 x1 1 25 Gbps SerDes lane 3 1111 PCle 1 x2 2 5 Gbps SerDes lane 0 1 PCle 1 x2 2 5 Gbps SerDes lane 0 1 SGMII 2 x1 1 25 Gbps SerDes lane 2 SGMII 3 x1 1 25 Gbps SerDes lane 3 SGMII 2 x1 1 25 Gbps SerDes lane 2 SGMII 3 x1 1 25 Gbps SerDes lane 3 en m Table 7 Config signal User s Manual TQMP2020 UM 102 2012 by TQ Group Reset configuration continued 10 signal at the P2020 Register Meaning P2020 Meaning P1020 P1021 cfg_mem_debug DMA2_DACKO PORDBGMSRI5 0 Debug info from eLBC is driven on Debug info from eLBC is driven on MSRCID and MDVAL MSRCID and MDVAL Debug info from DDR is driven on Debug info from DDR is driven on MSRCID and MDVAL MSRCID an
43. ernal VCC3V3IN 3 201 V to 3 465 V Determined by voltage range of components and 3 3 V 3 5 supervisor threshold see 3 2 2 1 Ripple max 30 mV Peak to peak Current 5A TQMP2020 400 1200 800 MHz CCB Core DDR3 consumption 3 3 2 2 VBAT RTC supply e Supply of the RTC e Current consumption only if VBAT gt VCC3V3 Connection via Schottky diode to VCC3V3 is present on module Table 15 Requirements for VBAT Voltage VBAT 1 8 V to 5 5 V Determined by voltage range of RTC see 3 2 8 3 Ripple max 1 Peak to peak Timekeeping 2 uA VCC3V3 IN OV Oscillator running current 3 3 2 3 LVDD Ethernet I O supply LVDD is generated by feedback of the voltages VCC3V30UT or VCC2V5OUT which are monitored and generated on the module In this way the necessary specifications are observed automatically The driver s configuration LVDD_VSEL is done on the module automatically based on the supplied voltage see 3 2 3 3 3 3 2 4 BVDD Local Bus supply BVDD always operates at 3 3 V BVDD cannot be changed and is not accessible externally The driver s configuration BVDD_VSEL 0 1 is done on the module see 3 2 3 3 Page 42 User s Manual TQMP2020 UM 102 2012 by TQ Group 3 3 2 5 CVDD supply USB SDHC and SPI CVDD is generated by feedback of the voltages VCC3V30UT VCC2V5OUT or VCC1V8OUT which are monitored and generated on the module In this way the necessa
44. esent there is still no technical equivalent alternative for printed circuit boards with bromine containing flame protection FR 4 material such printed circuit boards are still used No use of PCB containing capacitors and transformers polychlorinated biphenyls These points are an essential part of the following laws e The law to encourage the circular flow economy and assurance of the environmentally acceptable removal of waste as at 27 9 94 source of information BGBI 1994 2705 e Regulation with respect to the utilization and proof of removal as at 1 9 96 source of information BGBI 1996 1382 1997 2860 e Regulation with respect to the avoidance and utilization of packaging waste as at 21 8 98 source of information BGBI 1998 2379 e Regulation with respect to the European Waste Directory as at 1 12 01 source of information BGBI 2001 3379 This information is to be seen as notes Tests or certifications regarding this were not carried out 5 3 RoHS compliance The TQMP2020 is manufactured RoHS compliant TQ Components GmbH issues the RoHS conformity declaration Page 64 User s Manual TQMP2020 UM 102 2012 by TQ Group 6 APPENDIX 6 1 References Table 20 Further applicable documents No Name Date Company Er 04 2011 1 P2020 QorlQ Integrated Processor Hardware Specifications Rev O Freescale 2 P1020 QorlQ Integrated Processor Hardware Specifications 05 2010 Ened Product Previ
45. ew Preliminary Freescale Confidential Proprietary P1020EC_ Rev H Draft 3 P1021 QorlQ Integrated Processor Hardware Specifications 05 2010 oe Product Preview Preliminary Freescale Confidential Proprietary P1021EC Rev H Draft 4 P1022 13 QorlQ Integrated Processor Hardware Specifications 12 2009 Presale Preliminary Freescale Confidential Proprietary Rev D Zn 5 P2020 QorlQ Integrated Processor Reference Manual P2020RM 03 2011 Freescale Rev 1 TQ Systems GmbH MuhlstraBe 2 Gut Delling 82229 Seefeld info ta group com www tq group com Technology in Quality
46. ion including those protected by a third party unless specified otherwise in writing are subjected to the specifications of the current copyright laws and the proprietary laws of the present registered proprietor without any limitation One should conclude that brands and trademarks are protected through the rights of a third party User s Manual TQMP2020 UM 102 2012 by TQ Group Page 3 1 6 Imprint TQ Components GmbH Gut Delling M hlstra e 2 82229 Seefeld Tel 49 0 8153 9308 0 Fax 49 0 8153 9308 134 Email info tqs de Web http www tg group com 1 7 Disclaimer TQ Components GmbH does not guarantee that the information in this manual is up to date correct complete or of good quality Nor does TO Components GmbH assume guarantee for further usage of the information Liability claims against TQ Components GmbH referring to material or non material related damages caused due to usage or non usage of the information given in the manual or caused due to usage of erroneous or incomplete information are exempted as long as there is no proven intentional or negligent fault of TQ Components GmbH TQ Components GmbH explicitly reserves the rights to change or add to the contents of this manual or parts of it without special notification 1 8 Copyright and licence expenses The drivers and utilities for the used components as well as the BIOS are subject to the copyrights of the respective manufacturers The lic
47. irectory Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Terms and CONVENTIONS serena aera tata 1 AGONY EE RR 5 eTSEC configuration possibilities P2020 10 P1020 11 P1021 12 esse sesse 11 SerDes configuration possibilities P2020 10 P1020 11 P1021 12 nenn 12 Reset OPTIONS AE EE EE saasaa ASES aats RARAS AKASA Ha en sEa Hansen En SAKASAKA 16 Legend for Table 7 Table 8 and Table 9 sesse ese eek eek ee eek eek ee ee Rek GR eek Ag 17 Reset configuration ues sesse seek eek seek es 18 Free reset configuration general purpose 26 Static configuration Signals 26 Configuration data in EEPROM 27 Standard clock frequencies with P2020 35 Assignment chip selects at the Local BUS esse seek eek se eek eek eek eek ee ee eek ee 35 Te device addresses EE 37 Requirements for 3 3 V external sesse ese eek eek ese GER eek GR ee eek ee ee eek ee eek es 41 Requirements for VBAT ssecssssssecssessssssssscssecssessnsecssecsscssuseesecssecsuceeaceesessueesasecaeesseeesaeenssense 41 Signals COP JTAG interface essssscsssessssescssteesssescsssecssseecssecssseeessecssseeesseessseeenseessaneeeneeees 43 Pinout according to functional groups unesesssenssenssenssennssunssenssennsnunssenssennsnnnnsennsennsnnn 45 Stack heights overview 59 Stack heights detailed
48. isor EK T and connection to HRESET REO on module HER Internal 66 666 MHz driver enable CLKOE 2 l T 4k7 to VCC3V3 on module rn PGOOD u o Power good output J 22k to DGND on module X1 158 low active signal T pull up 4 pull down gt element in series User s Manual TQMP2020 UM 102 2012 by TQ Group Page 49 Table 17 Pinout according to functional groups continued CPU Pin Type Description Module Pin SPI_MISO rae ee ae ee if not used En SPI_MOSI z Vo gt re if not used id spre paTas 22 VO E ze Moet CVOD on baseboerdifnotused 1220 EE E26 VO SPI slave select 1 SDHC data line 5 X2 28 a ng F29 VO SPI slave select 2 SDHC data line 6 X2 30 ae E29 VO SPI slave select 3 SDHC data line 7 X2 32 SPI_CLK D23 9 A on baseboard if not used u low active signal pull up 4 pull down gt element in series CPU Pin Type Description Module Pin SDHC_DATAO G28 VO SDHC data line 0 X2 33 SDHC_DATA1 F27 VO SDHC data line 1 X2 35 SDHC_DATA2 G25 VO SDHC data line 2 X2 37 SDHC_DATA3 G26 VO SDHC data line 3 X2 39 SDHC_CMD F26 VO SDHC CMD line X2 36 SDHC_CLK G29 O SDHC clock X2 38 low active signal T pull up pull down element in series Page 50 User s Manual TQMP2020 UM 102 2012 by TQ Group Table 17 Pinout according to functional groups continued RS2
49. l Test Reset X2 104 TRIG_IN AB28 l Watchpoint Trigger in 4k7 to DGND on module X2 99 TRIG_OUT READY U28 o Watchpoint Trigger Out Processor 0 ready X2 101 _PO QUIESCE quiescent state READY_P1 W26 O Processor 1 ready X2 103 MSRCIDO P28 O Memory Debug Source ID 0 X2 87 MSRCID1 R27 O Memory Debug Source ID 1 X2 89 MSRCID2 P27 O Memory Debug Source ID 2 X2 91 MSRCID3 P26 O Memory Debug Source ID 3 X2 93 MSRCID4 N26 O Memory Debug Source ID 4 X2 95 MDVAL M24 O Memory Debug data valid X2 88 SCAN MODE w27 Scan Mode T 1k to VCC3V3 on module X2 92 Test Select TEST_SEL AA28 P2020 P1020 P1021 T 4k7 to VCC3V3 on module X2 94 P2010 P1011 P1012 1 1k to DGND on module low active signal pull up 4 pull down element in series User s Manual TQMP2020 UM 102 2012 by TQ Group Page 47 Table 17 Pinout according to functional groups continued Interrupt Controller DMA Signal CPU Pin Type Description Module Pin DMA1_DREQ Y28 DMA1 request T 4k7 to VCC3V3 on module X2 108 DMA2_DREQO W28 DMA2 request 0 T4k7 to VCC3V3 on module X2 114 DMA1_DACK T28 O DMA1 acknowledge X2 110 DMA2_DACKO T29 O DMA2 acknowledge 0 X2 116 DMA1_DDONE T26 O DMA1 done X2 112 DMA2_DDONEO Y29 O DMA2 done 0 X2 118 Unconditional debug event 0 UES ve T 4K7 to VCC3V3 on module X2 103 Unconditional debug event 1 EET Kae
50. l X2 67 Local Bus address latch enable Signal integrity and timing is critical do not connect if not LALE ig 9 used on baseboard If used keep as short as possible and ad observe length constraints with respect to LAD 0 15 Local Bus UPM general purpose line 0 z LGPLO LFCLE Ble 9 NAND flash command latch enable Xa LGPL1 LFALE C13 O Local Bus GP line 1 NAND flash address latch enable X3 7 LGPL2 LERE LOE A20 o Local Bus GP line 2 NAND flash read enable X3 9 output enable LGPL3 LFWP D10 O Local Bus GP line 3 NAND flash write protect X3 11 Local Bus GP line 4 transaction termination EE gaa B13 VO NAND flash ready busy wait parity byte select X2 61 T 4k7 to VCC3V3 on module LGPL5 C19 0 Local Bus GP line 5 X3 13 LCLKO B15 O Local Bus clock 0 gt 22 Q on module X2 58 LCLK1 A15 Q Local Bus clock 1 22 Q on module X3 33 Local Bus PLL synchronization in LSYNC_IN Al 22 Q on module T 4k7 to VCC3V3 on module X33 LSYNC_OUT AIA o Local Bus PLL synchronization out X3 39 22 Q on module low active signal pull up 4 pull down gt element in series User s Manual TQMP2020 UM 102 2012 by TQ Group Page 53 Table 17 Pinout according to functional groups continued e TSECs IEEE1588 Signal CPU Pin Type Description Module Pin TSEC 1588 CLK IN AG21 l IEEE1588 clock in T 10k to LVDD on
51. lete file name with its Command corresponding extension Page 2 User s Manual TQMP2020 UM 102 2012 by TQ Group 1 4 Handling and ESD tips General handling of your TQ products The TQ product may only be used and serviced by certified personnel who have taken note of the information the safety regulations in this document and all related rules and regulations A general rule is do not touch the TQ product during operation This is especially important when switching on changing jumper settings or connecting other devices without ensuring beforehand that the power supply of the system has been switched off Violation of this guideline may result in damage destruction of the module and be dangerous to your health Improper handling of your TQ product would render the guarantee invalid Proper ESD handling The electronic components of your TQ product are sensitive to electrostatic discharge ESD Always wear antistatic clothing use ESD safe tools packing materials etc and operate your TQ product in an ESD safe environment Especially when you switch modules on change jumper settings or connect other devices 1 5 Registered trademarks TQ Components GmbH aims to adhere to the copyrights of all the used graphics and texts in all publications and strives to use original or licence free graphics and texts All the brand names and trademarks mentioned in the publicat
52. m to baseboard ground plane X1 20 X1 27 X1 36 X1 43 X1 52 X1 59 X1 68 X1 75 X1 84 X1 85 X1 87 X1 90 X1 92 X1 DGND 93 X1 95 X1 98 X1 100 X1 101 X1 103 X1 106 X1 108 X1 109 X1 111 X1 114 X1 116 X1 117 X1 119 X1 122 X1 124 X1 125 X1 127 X1 130 X1 132 X1 133 X1 135 X1 138 X1 140 X1 141 X1 143 X1 146 X1 148 X1 149 X1 151 X1 154 X1 156 X1 157 X2 8 X2 15 X2 24 X2 31 X2 40 X2 47 X2 56 X2 63 X2 72 X2 77 X2 83 X2 90 X2 97 X2 106 X2 113 X2 122 X2 129 X2 138 X2 145 X2 154 X3 3 X3 12 X3 19 X3 28 X3 35 Table 17 Reserved Signal User s Manual TOMP2020 UM 102 2012 by TO Group Page 57 Pinout according to functional groups continued CPU Pin Type Description Module Pin RSVD4080 SD_3 Reserved input 3 connect to ground X1 150 RSVD4080 SD_3 Reserved input 3 complement connect to ground X1 152 RSVD4080 SD_2 Reserved input 2 connect to ground X1 142 RSVD4080 SD_2 Reserved input 2 complement connect to ground X1 144 RSVD4080 SD_1 O Reserved output 1 do not connect X1 153 RSVD4080 SD_1 O Reserved output 1 complement do not connect X1 155 RSVD4080 SD_O O Reserved output 0 do not connect X1 145 RSVD4080 SD O O Reserved output 0 complement do not connect X1 147 RSVD1022 SD2_TX1 o Reserved SERDES2 transmit data 1
53. mitted 125 MHz Tx and Rx clock 1 Gbit s Transmit clock changes signal of GTX_CLK to TX_CLK as well as direction with fallback to 10 100 Mbit s MII e RGMI and RTBI mode Highest frequency to be transmitted 125 MHz Tx and Rx clock 1 Gbit s Lower number of signals than with G MIl or TBI Timing tighter than with G MIl and TBI because both clock edges are used Source clocking User s Manual TQMP2020 UM 102 2012 by TQ Group Page 11 The configuration of the interface modes is carried out via the CPLD which reads the configuration from the configuration EEPROM See also 3 2 3 The above described interfaces except RGMII are supported by the P2020 as well as P2010 With all other CPUs P1020 11 as well as P1021 12 only two eTSECs eTSEC1 3 can be operated in the parallel mode with RGMII The following table shows the possible eTSEC configurations Table 3 eTSEC configuration possibilities P2020 10 P1020 11 P1021 12 eTSEC1 eTSEC2 eTSEC3 Standard interface Standard interface SGMII SGMII Inactive Inactive Inactive Reduced interface Reduced interface SGMII SGMII Inactive Inactive Inactive SGMII SGMII Inactive Inactive Inactive Reduced interface Reduced interface Reduced interface SGMII SGMII Inactive Inactive Inactive Underlined also P1020 11 and P1021 12 Standard interfaces GMII TBI MII Reduced interfaces RGMII RTBI RMII If the parallel mode
54. nction is not required e Pure outputs type O no wiring necessary e Inputs and I Os with pull up pull down type O I O with pull ups or pull downs no wiring necessary e Os which can be configured as an output e g GPIO_5 it is generally sufficient to configure unused pins as an output during initialisation e Continuing notes are found in 1 3 4 3 2 Pinout according to functional groups The wiring on the module is referred to under Description If necessary notes for the handling on the baseboard are supplied User s Manual TQMP2020 UM 102 2012 by TQ Group Page 45 Table 17 Pinout according to functional groups GPIO DMA Timer Signal CPU Pin Type Description Module Pin GPIO_0 IRQ7 R28 VO General Purpose I O 0 External Interrupt 7 X2 2 GPIO_1 IRQ8 R26 VO General Purpose I O 1 External Interrupt 8 X2 4 GPIO_2 IRQ9 P29 VO General Purpose I O 2 External Interrupt 9 X2 6 GPIO 3 IRO10 N24 VO General Purpose I O 3 External Interrupt 10 X2 10 GPIO_4 IRQ11 U29 VO General Purpose I O 4 External Interrupt 11 X2 12 GPIO 5 R24 VO General Purpose I O 5 X2 11 GPIO 6 R29 VO General Purpose I O 6 X2 14 GPIO 7 R25 VO General Purpose I O 7 X2 13 GPIO 8 SDHC CD F22 VO General Purpose I O 8 eSDHC card detection X2 16 GPIO_9 SDHC_WP A24 VO General Purpose I O 9 eSDHC card write protect X2 17 GPIO_10 USB_PCTLO A25 VO General Purpose I O 10 USB Port con
55. nd SPI ese sesse eek ese sek eek sek eek eek gee eek ee eek Rees 42 eo Tes OE ii a 42 MG CSV SOU Te ed VCC2V5OUT i VCCTVBOUT rnr ERREUR NNENRR UNNER NREN RRN User s Manual TQMP2020 UM 102 2012 by TQ Group Page iii Table of contents continued 3 4 3 4 1 3 4 2 3 4 3 3 4 3 1 3 4 3 2 3 5 3 5 1 3 5 2 3 6 3 6 1 3 6 2 3 6 3 3 7 4 1 4 2 5 1 5 2 5 3 6 1 Interfaces to other systems and device sees sesse eek eek ese eek eek Gee eek ee ee eek ee 42 Serlaliterlaes EE ie 42 EOPATAG interfae os ER N ee ese 43 External bus other interfaces use sesse ee ee ek ek ek ek ek eg ek oe Roe ee ee ee ee ee ee ek ek ek ek eg eg eg eg egg 44 Treatment of unused PINS nassi 44 Pinout according to functional group seeks ese eek eek ee Rek eek Geek ee ee Roe eek Geek 44 GOON Te N 158 Power dissipation 58 Heat sink 58 Mechanics 58 General information 58 Notes oftieatien ES EE 59 DiritensiOns E EE EEE EEE TTT TTT 59 Bootloadel A EEA E AAAA AA 60 SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS ccsessessssessssessssessssesseseeseses 61 EME ES 61 ESD EE 61 CLIMATIC AND OPERATIONAL CONDITIONS Reliability and service life Environment protection 63 ROHS stofie le RE 2s Eene Eneee eree csccesscasacessscasccasctassscasscasctassseasseusstasizeanneassttaes 63 APPENDIX EE EE 64 Refstences ss NNN 64 Page iv User s Manual TQMP2020 UM 102 2012 by TQ Group Table d
56. nected externally also slow and DC can radiate RF indirectly this also applies for the power supply 4 2 ESD In order to avoid interspersion on the signal path from the input to the protection circuit in the system the protection against electrostatic discharge should be arranged directly at the inputs of a system As these measures always have to be implemented on the baseboard no special preventive measures were planned on the TQMP2020 According to the data sheets the used devices already have some protection however this is generally not sufficient to meet the legal requirements without any further measures Following measures are recommended for a baseboard e Generally applicable Shielding of the inputs shielding connected well to ground housing on both ends e Supply voltages Protection by suppressor diode s e Slow signal lines RC filtering in certain circumstances Zener diode e Fast signal lines Integrated protective devices suppressor diode arrays with the smallest possible capacity Page 62 User s Manual TQMP2020 UM 102 2012 by TQ Group 5 CLIMATIC AND OPERATIONAL CONDITIONS The possible temperature range strongly depends on the installation situation heat dissipation by heat conduction and convection hence no fixed value can be given for the whole assembly In general a reliable operation is given when following conditions are met e Standard temperature range Chip temperature of CPU 0 C
57. nse eTSEC3 receive data valid X1 65 10k to LVDD on module eTSEC1 collision detect eTSEC3 receive clock TSEC1_COL TSEC3_RX_CLK AH26 l T 10kto LVDD on module X1 67 eTSEC1 receive data 7 eTSEC3 receive data 3 TSEC1_RXD7 TSEC3_RXD3 AG23 l 1 10kto LVDD on module X1 29 eTSEC1 receive data 6 eTSEC3 receive data 2 TSEC1_RXD6 TSEC3_RXD2 AH22 T 10k to LVDD on module X1 25 eTSEC1 receive data 5 eTSEC3 receive data 1 TSEC1_RXD5 TSEC3_RXD1 AJ23 l T 10kto LVDD on module X1 23 eTSEC1 receive data 4 eTSEC3 receive data 0 TSEC1_RXD4 TSEC3_RXDO AE24 l T 10kto LYDD on module X1 21 low active signal pull up 4 pull down gt element in series Page 54 m User s Manual TQMP2020 UM 102 2012 by TQ Group Table 17 e TSECs IEEE1588 continued Signal CPU Pin Type Pinout according to functional groups continued Description Module Pin TSEC1 RXD3 AJ28 l eTSEC1 receive data 3 T 10k to LVDD on module X1 19 TSEC1_RXD2 AE22 l eTSEC1 receive data 2 T 10k to LVDD on module X1 17 TSEC1_RXD1 AD21 l eTSEC1 receive data 1 T 10k to LVDD on module X1 15 TSEC1_RXDO AH25 l eTSEC1 receive data 0 T 10k to LVDD on module X1 13 eTSEC1 receive data valid TSEC1_RX_DV AJ26 l T 10k to LVDD on module X1 31 TSEC1_RX_ER AH23 l eTSEC1 receive error T 10k to LVDD on module X1 33 TSEC1_RX_CLK
58. nted Device SPI Serial Peripheral Interface SerDes Serializer Deserializer TBI Ten Bit Interface TSEC Three Speed Ethernet Controller UART Universal Asynchronous Receiver Transmitter ULPI UTMI Low Pin count Interface UPM User Programmable Machine USB Universal Serial Bus User s Manual TQMP2020 UM 102 2012 by TQ Group Page 7 2 BRIEF DESCRIPTION The TOMP2020 is a universal Minimodule based on the Freescale OorlO processor P2020 It extends the range of Power Architecture based modules towards High End with reduced size The computing performance of the P2020 dual core CPU is approximately double of the MPC8548 at significantly lower power dissipation Alternatively a P2010 single core can be assembled on the module In this case the computing performance corresponds to the MPC8548 The power dissipation is reduced further A P1020 or P1021 dual core or a P1011 or P1012 single core can be assembled on the same printed circuit board as an alternative The characteristic features of the module are e Dual or Single Core max 1 2 GHz e DDR3 32 or 64 bit with ECC e 4x SERDES configurable as PCI Express SGMII or Serial Rapid lO e 3x Gbit Ethernet The Starterkit STKP2020 is used as an Eval Board for the TQMP2020 All function relevant pins of the CPU are routed to the module plug connectors Even when using the module the user has complete freedom as in a design in solution Page 8 User s M
59. nual TQMP2020 UM 102 2012 by TQ Group 3 2 3 2 Freely available reset configuration The signals listed in the following table are not used on the module The baseboard can pass additional configuration data to the CPU on these signals if desired These do not influence the configuration ofthe CPU by hardware after a reset but can merely be utilised by software Table 8 Free reset configuration general purpose Config signal IO Signal at the P2020 Register Value Meaning P2020 Meaning P1020 P1021 cfg_gpinput 0 15 LAD 0 15 GPPORCRIO 15 Oxnnnn_0000 General purpose POR config not used General purpose POR config not used 3 2 3 3 Other configuration signals The module generates the signals listed in the following table They are not read during reset but must be applied permanently Table 9 Static configuration signals Config signal lO Signal at the P2020 Register Value Meaning P2020 Meaning P1020 P1021 IOVSELSR 30 31 IOVSELSR 26 27 01 10 11 2 5 V Local Bus GPIO 8 15 2 5 V Local Bus GPIO 8 15 CE_PB CE_PCO 1 8 V Local Bus GPIO 8 15 1 8 V Local Bus GPIO 8 15 CE_PB CE_PCO 3 3 V Local Bus GPIO 8 15 3 3 V Local Bus GPIO 8 15 CE_PB CE_PCO IOVSELSR 22 23 User s Manual TQMP2020 UM 102 2012 by TQ Group Page 27 3 2 3 4 Configuration data in the EEPROM Table 10 shows how the configuration data is store
60. nyms Acronym Description BGA Ball Grid Array COP Common On chip Processor CPLD Complex Programmable Logic Device CPU Central Processing Unit CRC Cyclic Redundancy Check DDR Double Data Rate DMA Direct Memory Access ECC Error Checking and Correction EEPROM Electrically Erasable Programmable Read only Memory EMC Electromagnetic Compatibility ESD Electrostatic Discharge FR 4 Flame Retardant 4 GMII Gigabit Media Independent Interface GP General Purpose IP Ingress Protection PC Inter Integrated Circuit JTAG Joint Test Action Group LED Light Emitting Diode LSB Least Significant Bit LVTTL Low Voltage Transistor Transistor Logic MII Media Independent Interface MSB Most Significant Bit NAND Not and NC Not Connected NOR Not or PHY Physical Interface Page 6 User s Manual TQMP2020 UM 102 2012 by TQ Group Table 2 Acronyms continued Acronym Description PLL Phase Locked Loop POR Power On Reset RGMII Reduced Gigabit Media Independent Interface RMII Reduced Media Independent Interface ROM Read Only Memory RTBI Reduced Ten Bit Interface RTC Real Time Clock RoHS Restriction of the use of certain Hazardous Substances SDHC Secure Digital High Capacity SDRAM Synchronous Dynamic Random Access Memory SGMII Serial Gigabit Media Independent Interface SMD Surface Mou
61. ry specifications are observed automatically The driver s configuration CVDD_VSEL 0 1 is done on the module automatically based on the supplied voltage see 3 2 3 3 3 3 3 Supply outputs 3 3 3 1 VCC3V30UT VCC3V30UT exclusively supplies the variable I O voltages LVDD or CVDD An additional load is not permitted Voltage 3 3 V 3 3 3 2 VCC2V50UT VCC2V5OUT exclusively supplies the variable I O voltages LVDD or CVDD An additional load is not permitted Voltage 2 5 V 3 3 3 3 VCC1V8OUT VCC1V80UT exclusively supplies the variable I O voltage CVDD An additional load is not permitted Voltage 1 8 V 3 4 Interfaces to other systems and devices 3 4 1 Serial interfaces e Two internal UARTs UART1 and UART2 e Max 115 200 baud limited by driver level shifter e Transceiver for TxD and RxD with RS232compatible levels e Additionally all signals are also available unbuffered at the module plug connectors e Default assembly driver for 2 x RxD and 2 x TxD the control signals RTS and CTS are only available unbuffered User s Manual TQMP2020 UM 102 2012 by TQ Group Page 43 3 4 2 COP JTAG interface All signals of the Freescale COP JTAG interfaces debugging interface are made available externally The COP JTAG interface encloses the following signals Signal direction seen from the module or Starterkit Table 16 Signals COP JTAG interface Pin Signal name Type F
62. schaltung f r HRESET_REQ R ckf hrung auf Basisboard Illustration 2 Feedback HRESET_REQ This enables a self reset trigger The self reset can be prevented or be linked to other conditions depending on the external wiring on the baseboard see Table 5 Page 16 User s Manual TQMP2020 UM 102 2012 by TQ Group The following table shows the reset options depending on the wiring of the RESIN Signals Table5 Reset options External wiring at RESIN input Reset function Self reset is possible None HRESET_REQ is switched through to RESIN on the module No self reset possible Pull up lt 2k2 to VCC3V3 HRESET_REQ cannot trigger a reset on the module Self reset is possible In addition an external reset can be triggered by applying alow level at RESIN Open Drain Open Collector output or push button to DGND Push Pull output or Open Drain Open Collector output with pull up lt 2k2 to VCC3V3 No self reset but only external reset possible HRESET_REQ cannot trigger a reset on the module 3 2 2 10 JTAG reset TRST TRST will be pulled low by HRESET it can still however be triggered separately COP JTAG Debugging This is achieved with the following circuit on the module VCC3V3 Y v18 x LYR971 R95 VCC3V3 yar VCC3V3 OR A Vice voels 2 py m Bl or HRESET m GND 3 n R62 TRST
63. ter Value User s Manual TQMP2020 UM 102 2012 by TQ Group Meaning P2020 Page 23 TQ Meaning P1020 P1021 cfg_io_ports 0 3 TSEC1_TXD 3 1 TSEC2_TX_ER PORDEVSRI9 12 0000 PCle 1 x1 2 5 Gbps SerDes lane 0 SerDes lanes 1 3 powered down PCle 1 x1 2 5 Gbps SerDes lane 0 SerDes lanes 1 3 powered down SerDes lanes 0 3 powered down SerDes lanes 0 3 powered down 0010 PCle 1 x1 2 5 Gbps SerDes lane 0 Reserved PCle 2 x1 2 5 Gbps SerDes lane 1 PCle 3 x2 2 5 Gbps SerDes lane 2 3 0011 Reserved Reserved 0100 PCle 1 x2 2 5 Gbps SerDes lane 0 1 Reserved PCle 3 x2 2 5 Gbps SerDes lane 2 3 0101 Reserved Reserved 0110 PCle 1 x4 2 5 Gbps SerDes lane 0 3 PCle 1 x4 2 5 Gbps SerDes lane 0 3 0111 SRIO 2 1x 3 125 Gbps SerDes lane 0 Reserved SRIO 1 1x 3 125 Gbps SerDes lane 1 SerDes lanes 2 3 powered down 1000 SRIO 2 4x 1 25 Gbps SerDes lane 0 3 Reserved 1001 SRIO 2 4x 2 5 Gbps SerDes lane 0 3 Reserved 1010 SRIO 2 4x 3 125 Gbps SerDes lane 0 3 Reserved 1011 SRIO 2 1x 1 25 Gbps SerDes lane 0 Reserved SRIO 1 1x 1 25 Gbps SerDes lane 1 SGMII 2 x1 1 25 Gbps SerDes lane 2 SGMII 3 x1 1 25 Gbps SerDes lane 3 1100 SRIO 2 1x 2 5 Gbps SerDes lane 0 Reserved SRIO 1 1x 2 5 Gbps S
64. ther IPs Illustration 4 P2020 2010 clock subsystem block diagram Source Freescale 3 2 4 2 Internal clock structure of the P1020 1011 and P1021 1012 SYSCLK 33 MHz 100 MHz TCK TSTCLK RTC CORE_BYPASS_CLK LCK 0 1 lug 167 MHz 400 MHz e500 Core Complex eLBC 10 MHz 100 MHz DDRCLK 66 MHz 166 MHz Us CLKE SOHC CLKE TOM TX CLK TDM_RX_CLK div j 267 MHz 667 MHz USBDR eSDHC et tck gt SerDes x4 PCI Express User s Manual TQMP2020 UM 102 2012 by TQ Group Page 31 MCK 0 3 MCK 0 3 SD_REF_CLK 100 MHz Gr 125 MHz SD_REF_CLK 100 MHz or 125 MHz TSEC 1 3 _TX_CLK TSEC 1 3 _RX_CLK TSEC 1 3 _GTX_CLK EC_MDC EC_GTX_CLK125 TSEC_1588_CLK TSEC_1588_CLK_OUT Reduced because of 32 bit DDR Only for P1020 11 General Different clocks Illustration 5 P1020 1011 and P1021 1012 clock subsystem block diagram Source Freescale Page 32 User s Manual TQMP2020 UM 102 2012 by TQ Group 3 2 4 3 System clock SYSCLK In normal operation SYSCLK is generated on the module The Platform or Core Complex Bus clock see 3 2 4 4 is generated by multiplication from this The Memory bus clock see 0 can also be generated The frequency is 66 666 MHz Spread spectrum clocking is possibl
65. to 125 C Package temperature of the DDR3 SDRAMs 0 Cto 95 C Package temperature of the remaining ICs 0 Cto 70 C e _ Extended temperature range Chip temperature of CPU 40 C to 125 C Package temperature of the DDR3 SDRAMs 40 Cto 95 C Package temperature of the remaining ICs 40 Cto 85 C Detailed information to the thermal characteristics of the CPU can be found in 1 Information about example configurations with active and passive cooling can be obtained from the TQ Components support As an embedded module it is not protected against dust external impact and contact IP00 An adequate protection has to be guaranteed by the surrounding system 5 1 Reliability and service life The module is designed for a typical service life of 10 years It was designed to be insensitive to vibration and impact User s Manual TQMP2020 UM 102 2012 by TQ Group Page 63 5 2 Environment protection By environmentally friendly processes production equipment and products we contribute to the protection of our environment To be able to reuse the product it is produced in such a way a modular construction that it can be easily repaired and disassembled The energy consumption of this subassembly is minimised by suitable measures Printed pc boards are delivered in reusable packaging Modules and devices are delivered in an outer packaging of paper cardboard or other recyclable material Due to the fact that at pr
66. trol 0 X2 18 GPIO 11 USB PCTL1 D24 VO General Purpose I O 11 USB Port control 1 X2 19 GPIO 12 F23 VO General Purpose I O 12 X2 20 GPIO 13 E23 VO General Purpose I O 13 X2 21 GPIO 14 F24 VO General Purpose I O 14 X2 22 GPIO_15 E24 VO General Purpose I O 15 X2 23 CPU Pin Type Description Module Pin USB_NXT B26 l USB Next data USB_DIR A28 l USB Direction X2 43 USB_STP B29 O USB Stop X2 44 USB_PWRFAULT C29 l USB VBUS power fault X2 46 USB_CLK D27 l USB PHY clock X2 45 USB_D7 C28 1 0 USB Data 7 X2 55 USB_D6 C25 VO USB Data 6 X2 54 USB_D5 B28 VO USB Data 5 X2 53 USB_D4 B25 VO USB Data 4 X2 52 USB D3 D26 VO USB Data 3 X2 51 USB D2 A27 VO USB Data 2 X2 50 USB_D1 A26 VO USB Data 1 X2 49 USB_DO C26 VO USB Data 0 X2 48 Page 46 User s Manual TQMP2020 UM 102 2012 by TQ Group Table 17 Pinout according to functional groups continued Power Management Signal CPU Pin Type Description Module Pin ASLEEP U25 O Sleep State T 4k7 to VCC3V3 on module X1 82 low active signal pull up 4 pull down element in series Debug Test Signal CPU Pin Type Description Module Pin TCK V29 l Test Clock T 4k7 to VCC3V3 on module X2 102 TDI T25 l Test Data In X2 96 TDO V28 O CPU Test Data Out via CPLD see 3 4 2 X2 98 TMS U26 l Test Mode Select T 10k to VCC3V3 on module X2 100 TRST V26
67. ts to the component placement of the base board The RF suitability of the module plug connectors was verified with the stack height 5 mm The results indicate however that sufficient reserves are available to use higher plug connectors for the given data rates of up to 3 125 Gbit s 6mm possibly even 7 mm User s Manual TQMP2020 UM 102 2012 by TQ Group Page 59 3 6 2 Notes of treatment To avoid damages caused by mechanical stress the TQMP2020 may only be extracted from the baseboard by using the extraction tool MOZIP2020 It can also be obtained separately 3 6 3 Dimensions e Board dimensions 74 x 54 mm Illustration 9 e Stack height see Table 18 Table 18 Stack heights overview Expansion stage Stack height without heat sink max Free stack height under module min DDR SDRAM atb c a d All 10 3 mm 3 0 mm 2 5 mm should be kept free on the baseboard along the longitudinal edges on both sides of the module for the extraction tool MOZIP2020 respective the universal mount TQMP2020 HAL1 I a Illustration 8 Stack heights not to scale Page 60 User s Manual TQMP2020 UM 102 2012 by TQ Group Table 19 Stack heights detailed Dim Value mm Remark Combination module connector with mating plug 6 7 and 8 mm are also possible with different connectors on baseboard b 12 0 0 1 PC board 3 0 0 x Coil L2 highest stack height top side d 1 6 0 2 Ferrite L8
68. unction 1 TDO O Test Data Output 2 NC 3 TDI l Test Data Input 4 TRST l Test Reset 5 NC 6 VDD_SENSE O Voltage Sense of Debugger 3 3 V 10 mA max 7 TCK l Test Clock 8 CKSTP_IN l Checkstop In 9 TMS l Test Mode Select 10 NC 11 SRESET Soft Reset 12 NC Optional Ground 13 RESIN Reset In connects to HRESET on module 14 Key pin 15 CKSTP_OUT Checkstop Out 16 GND Ground on Starterkit STKP2020 or ed on the STKP2020 see 1 The wiring necessary on the baseboard can be taken from the circuit diagram of the STKP2020 The COP JTAG interface uses the same signals as the JTAG interface A CPLD type LCMXO256C is after the CPU in the JTAG chain on the module This information must be passed on to the debugger Lauterbach Trace32 SYStem CONFIG IRPRE 8 SYStem CONFIG DRPRE 1 Abatron BDI2000 SCANSUCC 18 1 device with instruction register length 8 for MachXO device A corresponding setting should also exist at all other usable debuggers Page 44 User s Manual TQMP2020 UM 102 2012 by TQ Group 3 4 3 External bus other interfaces The interfaces described here are routed to the plug connectors leading to the baseboard 2x 160 pins 1 x 40 pins 3 4 3 1 Treatment of unused pins The module is designed in such a way that only a minimum number of signals are required to run the module Therefore many signals do not need external wiring if their fu
69. z Platform clock 2300 MHz nn m User s Manual TQMP2020 UM 102 2012 by TQ Group Table 7 Reset configuration continued onfig signa O signal at the P2020 Registe e ea g P2020 ea g P1020 P10 cfg_core0_speed LA24 PORDEVSR2 12 Core 0 clock lt 1 GHz Core 0 clock lt 450 MHz 1 Core 0 clock gt 1 GHz Core 0 clock gt 450 MHz cfg_corel_speed LA25 PORDEVSR2 13 Core 1 clock lt 1 GHz Core 1 clock lt 450 MHz 1 Core 1 clock gt 1 GHz Core 1 clock gt 450 MHz cfg_ddr_speed LA26 PORDEVSR2 15 0 DDRclock lt 500 MHz DDR clock lt 450 MHz DDR clock 2500 MHz DDR clock 2450 MHz cfg_sys_speed LA28 PORDEVSR2 21 0 System clock lt 66 MHz Reserved System clock 266 MHz System clock 266 MHz cfg_cpu 0 1 _boot LA27 PORBMSRIO 1 00 CPU boot holdoff mode for both CPU boot holdoff mode for both cores The LA16 cores The e500 cores are prevented e500 cores are prevented from booting until from booting until configured by an configured by an external master external master 01 e500 core 1 is allowed to boot e500 core 1 is allowed to boot without without waiting for configuration by waiting for configuration by an external an external master while e500 core0 master while e500 core 0 is prevented from is prevented from booting until booting until configured by an external configured by an external master or master or the other core the other core 10 e500 core 0 is allowed

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