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User Manual DNMEG_AD-DA

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1. 12V F x C448 5A 10uF C174 16V 0 1uF c ae F9 CERAMIC 45V x H C451 5A L 150uF C175 6 3V O tuF 205 TANT Fi BN 7 Es T cam 7A L 150uF C446 P3 1 3V 0 1uF 20 P12VFUSED_DC_B EL CLK DC B 0p TANT Ki GCAP Fi CDC B On GCAN PSVFUSED DC B C1 Z E3 CLK DC B 1p VCCO DC B0 mie je GCBP r3 CIK DC B Tn o PBV2 e GCBN P3 3VFUSED DC B a CLK DC B 2j DCB B2 pasi e Gccp HEP erepe os D2 a F5 CDC B 2n BS kasi GS P3 3V 2 GCCN P3 3V 3 R250 DC RST AP 12 RST B3S 1000 1K Clock Power Reset p99 12 DC_RSTn 74390 101LF Figure 25 In System Daughter Card Header Power 10 2 Stand Alone Operation An external ATX power supply is used to supply power to the DNMEG_AD DA Daughter Card in stand alone mode see Figure 26 The external power supply connects to header J12 Tyco P N 171825 4 The user should connect the connector on the ATX power supply to this header The DNMEG_AD DA Daughter Card has the following power supplies they are generated from the 5V supply on the external power connector J12 e PSU4 3 3V e PSU2 2 5V DNMEG AD DA User Manual www dinigroup com 50 HARDWARE DESCRIPTION e PSU3 1 8V e PSU1 1 2V e U22 0 9V Any ATX type power supply is adequate The Dini Group recommends a power supply rated for 250W Note The switching regulators in the Power Supply may require and external load to operate within specifications the DN
2. M H 7 2 2 DDR2 Termination Scheme 7 2 3 Digitally Controlled Impedance DCI 7 2 4 On Die Termination ODT 7 2 5 Mpp Switching POWeb Supply i erecti eret tete Y SER COUR BER OUR PETERE EE E EEEE EEEE EXE Y MUR UD CIR Reo 7 2 6 VT T Emear Power Supply nere ett RUE Qu uu RENE e EH MERE e PNE aS aa eee rrr em ets 7 2 7 Serial Presence Detect Operation 7 2 8 JTAG connections to FPGA weii tann eet e eee dare ee Ue eee Q toa ye W Ca a aN eene denda dg 7 2 9 PCB Trace Lengths ananas 47 8 LED INDICATORS m 8 1 SOP BI A Bom 47 8 2 Configuration DONE LED exp 48 83 Power Supply Status LED s 48 9 RS232 PORT 49 9 1 1 Connections between FPGA and RS232 Port 49 10 POWER DISTRIBUTION Au ut 50 10 1 In System Operat On ieir oisi apayaq suede sve sess E NEEESE ESEE AE AEAEE EAEE EEE AAEE akawa wau Qiu CA RARESA 10 2 Stand Alone Operation 10 2 1 External Power Connector sorier retes oireet NT ETRA EVEEN EEEE TA EA n EESTE EEEE Ei e SANESE VRASE TA EES EISTE SENEESE ENRETE 11 DAUGHTER CARD HEADERS sorrir DA E S N TE E OE T IRE RR dee ERE A E Wu PE YER eee dee 11 1 Daughter Card clocking 11 2 Daughter Card Header Pin Assignments 11 2 1 Special Pins on the Daughter Card Header Aa Ase E 11 3 Veco Power Supply Re ERE 11 4 FPGA t
3. 5 1 1 Single Ended Input Mode The AD8351 U1 provides a moderately high input impedance of 5 kQ The input is terminated to GND with a 49 9 Q resistor R1 to impedance match to the driving source and then AC coupled with 0 1uF ceramic capacitors C2 C3 R4 and C3 provide an AC ground to the inverting input of the AD8351 U1 To balance the outputs an external feed back resistor R62 is required To select the gain resistor please reference the datasheet The factory configuration set the gain to 6 0dB and allows for a maximum input voltage of 650mVp p centered around GND at SMA connector J1 DNMEG AD DA User Manual www dinigroup com 29 HARDWARE DESCRIPTION iO Ec 1 142 0701 501 jair _ C3 n 0 1uF iC R4 iO J 49 9R 142 0701 501 Figure 15 Single Ended Input 5 1 2 Differential Input Mode The AD8351 U1 provides a moderately high input impedance of 5 kQ The input is terminated to GND with 24 9 Q resistors R5 R8 to impedance match to the driving source and then AC coupled with 0 1uF ceramic capacitors C5 C The factory configuration set the gain to 6 0dB and allows for a maximum input voltage of 650mVp p centered around GND at SMA connector J3 J4 J3 2 5 1 3 4 142 0701 501 I C6 L 0 1uF J4 p S 2 5 R8 3 3n 49 9R 142 0701 501 Figure 16 Differential Input 0 1uF 5 1 3 Gain Adjustment The differential gain of the AD8351 U1 is set using a single
4. Be 4 2 3 Connection between FPGA and ADC Clock Buffer 4 21 43 DAC Clocking sepe prede ilasa 21 4 3 1 DAC Oscillator Circuit EPA 4 3 2 External DAC Clock Circutt 4 22 4 3 3 Connection between FPGA and DAC Clock Buffer 5 23 44 DDR Glocking eoo er re tpe ome 23 4 4 1 DDR2 Differential Oscillator Circuit eese 023 4 4 2 Connections between FPGA and the DDR2 Differential Oscillator 23 4 4 3 DDR2 Differential Clock BUEL 7 0 rette ERE t TEETH UR OSes bas IR DS REVWEES REOR F EXE VENENIS S ER WT EHE Se SURE UIROS 24 4 4 4 Clocking Connections between DDR2 Clock Buffer and the SODIMM sse tenete tentent tenentes 24 4 5 Clock Synthesizer et 4 5 1 Clock Synthesizer Circus tenti dee te ee pp HH OR GP RP EET KE EE Er PE HIE AA OAY 25 4 5 2 Connections between FPGA and the Clock SynthesiIZer u n anu eterne entere teen tenete tenente tenete tnt 25 46 Daughter Card Clocks sess 4 6 1 Daughter Card Clock Circuit Bottom Header P3 4 6 2 Daughter Card Clock Circuit Top Header P2 sese tetntn Ao tetntnene tenete tn EEEE r eene tenete enin stetit Eos 4 6 3 Connections between the FPGA and the Daughter Card Header Clocks ANALOG TO DIGITAL CONVERTER ADC 5 1 Differential Input ADC Drivers renunsia contin eei We On AE ERARE FUE EDS AETERNE EXE De AAA RETETE ELATAS TER 5 1 1 Single Ended Input M
5. N aaa aywayaa nanaawan aaa yawa 1 3 PACKAGE CONTENTS esee 4 INSPECT THE BOARD noiire s E 5 ADDITIONALINFORMA TION aO a e aaa E EE E A aaa A AA A EEAS GETTING STARTED S a Ee qu a Sa ESA E E o a a D a Eeer E ier OS rS ASE ES S ES O EDE ES ETES S E EO SES iSo 5 1 ESD WARNING 8 a 5 USING THE REFERENCE DESIGN MAIN uuu anaqyasqa a asia EEE EE a aaa iiaeie ERA 5 2 1 HyperTerminal Setup idees re eere xe gg Ne aqha RATER Sua Dua u aiT EO EER AEE a 2 2 Configuring the FPGA 2 3 Running the Reference Design iriiria i Tina er i E EEATT ENEE EAEE 9 HARDWARE DESCRIPTION 1 OVERVIEW M M XILINX VIRTEX 4 FPGA a 2 1 Summary Of Virtex 4 FAMILY Features E 14 3 FPGA Grogdre DF vuol 15 3 1 Master Serial Configuration I 3 2 y Boundary Scan and JTAG Configur tion atten irt HS ERE ORE EO Y HER ORE ISAEV ETIEK SETEV OSEO EEE ERI EIE TH EREE St rarai 16 3 2 1 In System Programming PROM ITAG Header ou aaa mmn an nanaypas s 17 3 2 2 JTAG connections to the PROM FPGA 4 CLOCK GENERATION pM AS EEEE EEEE NEEVA AEAEE EEEE oa TENERE EEAO aE AA TENATA VAS KEETE Ea SEERE ASS akaqa 4 1 Clock Methodology mua ERU ee tte e e RP HERE EE OU AEE a E P SA E Geb PE eU irt dete eee 42 ADC Clocking 4 2 1 ADC Oscillator Circuit 4 2 2 External ADC Clock Circutt
6. 4 Power cycle the DNMEG AD DA Daughter Card and verify that the FPGA DONE blue LED DS9 is enabled indicating successful configuration of the FPGA 2 3 Running the Reference Design This section lists detailed instructions for executing the reference design After configuring the FPGA perform the following steps 1 Pres ENTER in the HyperTerminal window to display the DNMEG_AD DA Main Menu DNMEG_AD DA User Manual www dinigroup com 9 GETTING STARTED DNMEG_AD DA HyperTerminal File Edit View Call Transfer Help Dg oS 28 DDR2 Test SPI Flash Test ADCO Start Capture ADCO Start Capture DC1 Start Capture DC1 Start Capture DAC Menu Enter Option _ Connected 0 00 21 Auto detect 19200 8 N 1 2 Select test option a DDR2 Test in the HyperTerminal window and verify that the test PASS periods will be displayed as the memory locations are being tested if no DDR2 Module is present the test will display read write errors Press ENTER to stop the test 3 Select test option b SPI FLASH Test in the HyperTerminal window and verify that the test PASSED DNMEG AD DA User Manual www dinigroup com 10 GETTING STARTED DNMEG_AD DA Hyper Terminal File Edit View Call Transfer Help Enter Option selected B Data being written Test Data Written reading back Flash Test PASSED DDR2 Test SPI Flash Test ADCO Start Capture ADCO Start Capture ADC1 Start Capture AD
7. 7 2 9 PCB Trace Lengths The DDR2 traces on the DNMEG_AD DA Daughter card is routed to the following lengths refer to Table 19 Table 19 PCB Trace Lengths Signal Name Routed Length mm Description DDR2_CKp0 69 02 Clock group DDR2 A0 68 54 Control group DDR2 DQO 64 18 Data byte group CLK DDR2 FBp n 69 01 Clock group 8 LED Indicators The DNMEG AD DA provides various LED s to indicate that status of the board 8 1 User LED s Eight green LED s are provided to the user as a design aid during debugging The LED s can be turned ON by driving the corresponding pin LOW Table 20 describes the user LED s and their associated pin assignments on the FPGA U5 DNMEG AD DA User Manual www dinigroup com 47 HARDWARE DESCRIPTION Table 20 User LED s Signal Name FPGA pin FPGA_LEDn0 U15 H12 FPGA_LEDn1 U15 J11 FPGA_LEDn2 U15 B7 FPGA LEDn3 U15 C7 FPGA LEDn4 U15 A10 FPGA_LEDn5 U15 A9 FPGA_LEDn6 U15 F8 FPGA_LEDn7 U15 G8 8 2 Configuration DONE LED After the FPGA has received all the configuration data successfully it releases the DONE pin which is pulled high by a pull up resistor A low to high transition on the FPGA DONE signal indicates configuration is complete and initialization of the device can begin The DON LED is driven by a NFET and turns ON the blue LED DS9 when the DONE pin goes high Table 21 describes the DONE LED and its ass
8. Figure 19 Serial FLASH Figure 20 SSTL_18 Symmettrically Single Parallel Terminated Figure 21 Symmetrically Double Parallel Terminated Figure 22 VDD Switching Power Supply Figure 23 VIT Linear Power Supply Figure 24 RS232 Port Figure 25 In System Daughter Card Header Power Figure 26 ATX Power Supply Figure 27 External Power Connection Figure 28 Daughter Card Interconnect Diagram Figure 29 Daughter Card Header Pin Assignments Figure 30 VREF Signals Figure 31 VCCO Adjustable Linear Power Supplies Figure 32 Daughter Card Header Power amp RESET d Fipure 35 39 Pin Mictor Connector ies due stie men ied e eite date d eet tea ii caia bp ies e tesi tae diee A A List of Tables D D D D D D D D D D D D D D D D D D D D D D D D D D eT Virt x 4 Uncompressed thf File Size oio er EU OE ODORE UHUER EURO USO NOR UH TEUER e 2 JTAG connections to the PROM FPGA e 3 Clocking to from the FPGA e 4 External ADC Clock Interface Levels le 5 Connection between FPGA and ADC Clock Buffer e 6 External DAC Clock Interface Levels e 7 Connection between FPGA and DAC Clock Buffer e 8 Connections between FPGA and the DDR2 Differential Oscillator e 9 Connections between FPGA and the DDR2 Differential Clock Buffer e 10 Connections between
9. DDR2 Write PLL Circuit 4 4 4 Clocking Connections between DDR2 Clock Buffer and the SODIMM The clocking connections between the DDR2 Clock Buffer U23 SDRAM SODIMM 14 are shown in Table 9 DNMEG AD DA User Manual www dinigroup com 24 HARDWARE DESCRIPTION Table 9 Connections between FPGA and the DDR2 Differential Clock Buffer Signal Name DDR2 SODIMM DDR2 CKpO J14 30 DDR2 CKnO J14 32 DDR2 CKpO J14 164 DDR2 CKnO J14 166 CLK DDR2 FBp U15 AM17 CLK_DDR2_FBn 4 5 Clock Synthesizer The ICS8442 U21 is a general purpose dual output Crystal to Differential LVDS High Frequency Synthesizer available to the user 4 5 1 Clock Synthesizer Circuit The ICS8442 U21 has a selectable TEST_CLK or crystal input see Figure 11 The TEST CLK input accepts LVCMOS or LVTTL input levels and translates them to LVDS levels The VCO operates at a frequency range of 250MHz to 700MHz The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency The VCO and output frequency can be programmed using the serial U15 AM16 interface to the configuration logic driven by the FPGA U15 3V 43 C425 L 33pF U21 ans a gt Si XTAL1 EQUITO n Cl FOUTO CT 16 00MHz C424 33pF_ d 25 CLK SYNTH1p It XTAL2 FOUTI CLK_SYNTHin GND 28 o FOUTI 29 TP10 43 8V 30 M TEST CLK SYN T 31 M2 1 327 M3 TM z
10. MICTOR A0 J10 37 U15 B8 MICTOR A1 J10 35 U15 A8 MICTOR A2 J10 33 U15 K9 MICTOR A3 J10 31 U15 J9 MICTOR A4 J10 29 U15 B5 MICTOR A5 J10 27 U15 A5 MICTOR A6 J10 25 U15 E12 MICTOR A7 J10 23 U15 E13 MICTOR A8 J10 21 U15 A3 MICTOR A9 J10 19 U15 A4 MICTOR A10 J10 17 U15 E9 MICTOR A11 J10 15 U15 D9 MICTOR A12 J10 13 U15 D6 MICTOR A13 J10 11 U15 D7 MICTOR A14 J10 9 U15 A13 MICTOR A15 J10 7 U15 A14 MICTOR BO U15 H9 J10 38 MICTOR B1 J10 36 U15 H10 MICTOR B2 J10 34 U15 D10 MICTOR B3 J10 32 U15 D11 MICTOR B4 J10 30 U15 G10 MICTOR B5 J10 28 U15 F10 MICTOR B6 J10 26 U15 G11 MICTOR B7 J10 24 U15 G12 MICTOR B8 U15 C8 J10 22 MICTOR B9 J10 20 U15 C9 MICTOR B10 J10 18 U15 B11 MICTOR B11 J10 16 U15 A11 MICTOR B12 J10 14 U15 C10 MICTOR B13 J10 12 U15 B10 MICTOR B14 J10 10 U15 C12 MICTOR B15 J10 8 U15 D12 MICTOR CLK A J10 5 U15 B13 MICTOR CLK B DNMEG AD DA User Manual J10 6 U15 B12 www dinigroup com 67 HARDWARE DESCRIPTION 13 Mechanical 13 1 Dimensions The DNMEG_AD DA Daughter Card measures 220mm x 69mm pe j e I amp ce h ha e M e
11. The bitstream is loaded into the device through special configuration pins These configuration pins serve as the interface for a number of different configuration modes Master serial configuration mode Slave serial configuration mode Master SelectMAP parallel configuration mode Slave SelectMAP parallel configuration mode In addition the bitstream can be loaded through the JTAG interface JTAG Boundary scan configuration mode DNMEG AD DA User Manual www dinigroup com 15 HARDWARE DESCRIPTION The configuration mode is selected by setting the appropriate level on the dedicated configuration MODE pins The DNMEG_AD DA Daughter Card supports Master Serial and JTAG configuration modes The JTAG Boundaty scan configuration interface is always available regardless of the MODE pin settings The JTAG Boundary scan configuration mode disables all other configuration modes This prevents conflicts between configuration interfaces 3 1 Master Serial Configuration When the FPGA is in the Master Serial mode it generates a configuration clock that drives the configuration PROM These configuration devices are low cost devices with non volatile memory that feature a simple four pin interface and a small form factor These features make serial configuration devices an ideal low cost configuration solution Serial configuration devices provide a serial interface to access configuration data During device configuration Virtex 4 devices read
12. DP10 U15 M10 ADCO DP11 U15 N13 ADCO DP2 U15 H3 ADCO DP3 U15 P10 ADCO_DP4 U15 M7 ADCO DP5 U15 L5 ADC0_DP6 U15 R11 ADC0_DP7 U15 C4 ADC0_DP8 U15 F5 ADC0_DP9 U15 D4 ADC0_FS_ADJ U15 AD2 ADC0_ORN U15 F3 ADC0_ORP U15 F4 ADC1_CLK_SEL0 U15 Y14 ADC1_CLK_SEL1 U15 AA13 ADC1_DCLKOUTN U15 J19 ADC1_DCLKOUTP U15 K19 ADC1_DFRMT_SEL U15 AC5 ADC1 DNO U15 E2 ADC1 DN1 U15 J5 ADC1 DN10 U15 M5 ADC1 DN 11 U15 M2 ADC1 DN2 U15 H4 ADC1 DNS U15 N9 ADC1 DN4 U15 P11 ADC1 DN5 U15 G2 ADC1 DN6 U15 M8 ADC1 DN7 DNMEG AD DA User Manual U15 L6 www dinigroup com HARDWARE DESCRIPTION Signal Name FPGA Pin ADC1_DN8 U15 L3 ADC1_DN9 U15 K1 ADC1 DPO U15 E3 ADC1_DP1 U15 J6 ADC1 DP10 U15 M6 ADC1 DP11 U15 M3 ADC1_DP2 U15 H5 ADC1_DP3 U15 N10 ADC1_DP4 U15 P12 ADC1_DP5 U15 G3 ADC1_DP6 U15 L8 ADC1_DP7 U15 K6 ADC1_DP8 U15 K3 ADC1_DP9 U15 K2 ADC1 FS ADJ U15 AC4 ADC1_ORN U15 M1 ADC1 ORP U15 L1 6 Digital to Analog Converter DAC The DNMEG AD DA provides a dual 16 Bit 160 MSPS DAC U8 The AD9777 is the 16 bit member of the AD977x pin compatible high performance programmable 2x 4x 8x interpolating TxDAC family The AD977x family feature
13. FPGA Pin ADCO DCLKOUTp U6 64 U15 K18 ADCO DCLKOUTn U6 63 U15 K17 ADC1 DCLKOUTp U7 64 U15 K19 ADC1 DCLKOUTn U7 63 U15 J19 FPGA Pin Clock Multiplexer Pin CLK FPGA ADCOp U15 C2 U9 1 CLK FPGA ADCOn U15 D2 U9 2 CLK_FPGA_ADCip U15 P7 U10 1 CLK_FPGA_ADCin U15 P6 U10 2 4 3 DAC Clocking The DNMEG AD DA Daughter Card provides an onboard oscillator X3 as well as a single ended external clock input via an SMA connector J9 Clock Buffer U13 distributes these clocks to the DAC via clock multiplexer U12 U24 that are controlled from the FPGA U15 The quality of the clock and data input signals are important in achieving optimum performance The clock to the DAC is AC coupled and configured to be driven differentially R22 R97 and R98 R23 set the differential bias Please refer to the schematic 4 3 1 DAC Oscillator Circuit Oscillator X3 is powered from 2 5V and provides a LVDS clock to the Clock Buffer U13 refer to Figure 7 The EXT DAC CLK SEL signal is driven from the FPGA U15 and selects the clock source on the Clock Buffer U13 The Silicon Laboratories 1531 series of low jitter oscillators are recommended for this application DNMEG_AD DA User Manual www dinigroup com 21 HARDWARE DESCRIPTION and is available in 10 0MHz to 945MHz from 531FB160MO000BG factory default 160 MHz Silicon Laboratories part number 2 5V 2 5V 5 BLM18AG102SN1 100
14. Guide on how to use DCI 7 2 4 On Die Termination ODT On die termination ODT has been added to the DDR2 data signals to improve signal integrity in the system In a simple system with one DRAM load per DQ signal the DDR2 controller must ensure that termination is turned on for WRITEs and disabled for READs 7 2 5 Vpn Switching Power Supply The Artesyn PTH05050 POLA DC DC Converter is used to create the Vpp supply for the DDR2 SDRAM SODIMM set to 1 8V 6A see Figure 22 DNMEG AD DA User Manual www dinigroup com 41 HARDWARE DESCRIPTION C430 C427 EL 150uF 4 150uF 47uF C437 6 3V 6 3V 6 3V 0 1uF 5 20 20 20 TANT gt TANT CER TANT F CER TRACK VOUT ADJ R241 R242 6 49K 36 5K INHIBIT GND PTHO05050 R246 DNI 1K xem et Figure 22 VDD Switching Power Supply 7 2 6 VTT Linear Power Supply The National Semiconductor LP2996 Linear Regulator was designed to meet the JEDEC SSTL_18 specifications for termination of DDR2 SDRAM The device contains a high speed operational amplifier to provide excellent response to load transients The output stage prevents shoot through while delivering 1 5A continuous current and transient peaks up to 3A see Figure 23 5V TP13 VTT_900mV 1 8V m VTT 900mV Y 4 PVIN VIT I i J i AVIN VDDQ VSENSE ceos mod EEO C42 150uF gt 150uF C305 0 1uF 0 1uF 6 3V 6 3V 0 1uF 20 20
15. M5 3 M6 a M7 M8 NC 5 TP12 6_ NO B 1 CLK SYNTH_IN 23 est CLK SYNTH_SEL g12 SYNTH_SEL lt lt 2e XTAL SEL pgi2 SYNTH VCO SEL lt lt VCO SEL VCCA SYNTH R56 10 J lt _SYNTH_OSC_SCLK 18 VDDA T eis VN a ANNUM DeC SOAM SG SYNTH OSC SDATA 19 ATEA C152 10uF O80 SYNTH OSC SLOAD 20 O 0tuF 16V pgi2 SYNTH_OSC_SLOAD 2 SLOAD Loo 1 pg12 SYNTH PLOADn PLOAD I CERAMIC SYNTH_OSC_RST pg12 SYNTH_OSC_RST lt lt RE 1 ast 43 3V 3 fes eu m 16 GND vec 6144 6145 GND 0 1uF 0 1uF Figure 1 Clock Synthesizer Circuit 4 5 2 Connections between FPGA and the Clock Synthesizer The connections between the FPGA and the Clock Synthesizer are shown in Table 10 DNMEG_AD DA User Manual www dinigroup com HARDWARE DESCRIPTION Table 10 Connections between FPGA and Clock Synthesizer Signal Name Clock Synthesizer Pin FPGA Pin CLK_SYNTHOp U21 14 U15 M18 CLK_SYNTHOn U21 15 U15 L18 CLK_SYNTH1p U21 11 U15 AC19 CLK SYNTH1 n U21 12 U15 AB18 4 6 Daughter Card Clocks There are two daughter card headers on the DNMEG_AD DA Daughter Card The 400 pin MEG Array connector on the bottom of the PCBA is used to interface to the Dini Group products e g DN8000K10PCI The 400 pin MEG Array connector on the top of the PCBA can be used for IO expansion utilizing the DNMEG Obs The top and bottom daughter card headers ate connected together and share the same signals per pin The daughter card
16. U18 U19 and U20 on the DNMEG_AD DA Daughter Card refer to Figure 31 Refer to the datasheet for the LT1963A from Linear Technology on how to adjust the output voltages R225 R226 and R229 allow the user to remove the powers supplies if a VCCO of 3 3V is required since that is supplied by the system TPS 1 D 3 3V VCCO DC BO o U18 GND iwa VCCO DC B 8 curd l CCO DC BO m SHDN SENSE ADJ Ac C131 3 C117 10uF C125 6 ND NC 10uF C122 R225 16V 0 1uF 7 GND 16V 0 1uF DNI 0 20 R215 20 CERAMIC LTI963AES8 SO8 1K CERAMIC 3 3V VCCO DC B1 VCCO DC B1 E R226 DNI 0 20 CERAMIC alk ET i 43 3V 43 8V VCCO DC B2 U20 GND o 8 N GUT VCCO DC B2 5 SHDNSENSE ADJ C132 3 6 R229 7 16V DNI 0 20 CERAMIC 10uF C130 ey Ne GND 16V 0 1uF 20 OND CERAMIC LTI963AES8 SO8 Figure 31 VCCO Adjustable Linear Power Supplies 3 3V 11 4 FPGA to Daughter Card Header IO Connections Table 24 lists the input output interconnect between the FPGA and the Daughter Card Test Headers Table 24 FPGA to Daughter Card Header IO Connections Daughter Card Receptacle Daughter Card Signal Name FPGA Pin Bottom Pin Plug Top Pin U15 B22 P3 B4 P2 B4 U15 C24 P3 D4 P2 D4 U15 A21 P3 G4 P2 G4 DC_BON4 U15 J24 P3 J4 P2 J4 DNMEG_AD DA User Manual www dinigroup com 56 HARDWARE DESCRIPTION Daught
17. header provides three differential clock signals CLK DC B J0 2 p n refer to Figure 12 4 6 1 Daughter Card Clock Circuit Bottom Header P3 Differential signal pair DC_BOp n31 is buffered 1 2 LVDS and driven back out on the daughter card header P3 as CLK DC B 2p n The other pair of differential signals CLK DC FPGAp n is routed to the FPGA U15 This topology can be used to synchronize the clock on the motherboard to the clock on the daughter card Differential signals CLK DC B 0 1 p n is bidirectional and is connected between the daughter card test header P3 and the FPGA U15 DNMEG AD DA User Manual www dinigroup com 26 HARDWARE DESCRIPTION F7 12V p E BEZE 5A 10uF 0174 16V 0 1uF TROU Fa CERAMIC 45V i Fi C451 5A L 150uF C175 6 3V O 1uF 20 gt TANT F1 43V 7 k 88 C442 7A L 150uF C446 P3 1 6 3V 0 1uF 20 PI2VFUSED DC B J CLK DC B 0j EDS TI PBINFUSEB BE B RL Piv 1 acap FE CLK DC B Op pg14 P12V 2 GCAN CLK DC B On pg14 PSVFUSED DC B z CLK DC B 1 43 3V DOB ipsa GCBP HES CLK DC B 1p pg14 P PV g GCBN CLK DC B 1n pg14 P3 3VEUSED DC B B2 ES CLK DC B 2p 1 D2 F3 39V 1 jg GCCP r amp CLK DC B 2n ss Rost e P3 3V 2 GCCN 10K P3 3V 3 S R250 DC_RST stot en J2 RSTn 838 1000 1K Clock Power Reset
18. in a SNR of 58 79dB resulting in an ENOB 9 5 The SINAD was measured at 57 22dB DNMEG_AD DA User Manual www dinigroup com 31 HARDWARE DESCRIPTION SW FFTAData Date 06 28 2007 Time 10 47 07 Temp 25 C Encode 210 MSPS Analog 65 01 MHz SNR 58 79 dB SNRFS 58 82 dBFS UDSNR 0 dB NF 4381 dB SINAD 57 22 dB Fund 0 031 dBfs 2nd 66 38 dBc 3d 73 11 dBc 4th 80 16 dBe Sth 74 23 dBc Bes o dcs 300 HA W HU UN FI E Lin Ai i L T TON In VN WoSpur 67 69 dBc I n DEE ano UE AM A n i P Bd E Pu a ULM SFDR 68 38 dBc krl aa fp EP Ea A ftp eM L IT Bt pI a a Noise Floor 97 95 dB FS Samples 16384 Windowing Bh4 Figure 17 FFT of the ADC Output 5 2 8 ADC connections to the FPGA Table 13 shows the connection between the ADC devices and the Virtex 4 FPGA Table 13 ADC Connections to the FPGA Signal Name FPGA Pin ADCO_CLK_SELO U15 AC2 ADCO_CLK_SEL1 U15 Y11 ADCO_DCLKOUTN U15 K17 ADCO_DCLKOUTP U15 K18 ADCO_DFRMT_SEL U15 AA11 ADCO DNO U15 G1 ADCO DN1 U15 K4 ADCO DN10 U15 L9 ADCO DN11 U15 N12 ADCO DN2 U15 H2 ADCO DNS U15 P9 ADCO DN4 U15 N7 ADCO DN5 U15 L4 ADC0_DN6 U15 T11 ADC0_DN7 U15 C3 DNMEG_AD DA User Manual www dinigroup com 32 HARDWARE DESCRIPTION Signal Name FPGA Pin ADCO_DN8 U15 G5 ADCO_DN9 U15 E4 ADCO DPO U15 F1 ADCO DP1 U15 J4 ADCO
19. parallel termination scheme with 56 Q resistors see Figure 21 Ry is realized using Digitally Controlled Impedance DCI in the FPGA U15 R4 is realized with ODT in the DDR SODIMM module J14 and the 25 Q resistor in series is realized with On Chip termination on the SODIMM module DNMEG_AD DA User Manual www dinigroup com 40 HARDWARE DESCRIPTION Vrr 0 5 Vppo Vppo Vngr 0 5 Vppo R72 50Q Vrr 0 5 Vppo Figure 21 Symmettically Double Parallel Terminated 7 2 3 Digitally Controlled Impedance DCI To terminate a trace resistors are traditionally added to make the output and or input match the impedance of the receiver or driver to the impedance of the trace However due to increased device I Os adding resistors close to the device pins increases the board area and component count and can in some cases be physically impossible To address these issues and to achieve better signal integrity Xilinx developed the Digitally Controlled Impedance DCI technology DCI adjusts the output impedance or input termination to accurately match the characteristic impedance of the transmission line DCI actively adjusts the impedance of the I O to equal an external reference resistance This compensates for changes in I O impedance due to process variation It also continuously adjusts the impedance of the I O to compensate for variations of temperature and supply voltage fluctuations Refer to the UGO70 Virtex 4 User
20. program the PROM A Process Dialog box will indicate programming progress DNMEG AD DA User Manual www dinigroup com 8 GETTING STARTED iMPACT D DiniProductsIDN_BITFILESIDNMEG_AD DAWainRefML X40Mdefault ipf Boundary Scan File Edit View Operations Output Debug Window Help IPH 2BOX BRING Peo 2 9 malBoundary Scan alSlaveSerial ag SeleciMAP i F Exu i aDesktop Configuration 1 M ealDirect SPI Configuration B SystemACE xcf32p xc vix4 s PROM File Formatter prom_xcf32 mces bypass Right click device to select operations Available Operations are Operati perations E Boundary Scan PROGRESS END End Operation Elapsed time 0 sec BATCH CMD identifyMPM BATCH CMD assignFile p 1 file D DiniProducts DN BITFILES DNMEG D D MainRef LX40 1 Loading file D DiniProducts DN BITFILES DNMEG D DA MainRef LX40 prom xcf32 mcs done INFO iMPACT 1835 Loading CFI file D DiniProducts DN BITFILES DNMEG A D D MainRef LX40 prom xt CFI file not found proceed with device default setting BATCH CMD setAttribute position 1 attr packageName value null BATCH CMD copyDevice p 1 INFO iMPACT 1835 Loading CFI file D DiniProducts DN BITFILES DNMEG AD DA MainRef LX40 prom xi CFI file not found proceed with device default setting lt 3i s lt Output Error Warning Configuration Platform Cable USB 6 MHz usb hs
21. 15 AL19 U23 5 Signal Name DDR2 Clock Buffer Pin FPGA Pin CLK DDR2 FBp U23 3 U15 AM17 CLK DDR2 FBn U23 2 U15 AM16 Signal Name Daughter Card Header Pin FPGA Pin CLK DC B 0p P3 E1 P2 E1 U15 AF18 CLK DC B On P3 F1 P2 F1 U15 AE18 CLK DC B ip P3 E3 P2 E3 U15 AG16 CLK DC B 1n P3 F3 P2 F3 U15 AF16 CLK DC T 2p P2 E5 U15 AK18 CLK DC T 2n P2 F5 U15 AK17 Signal Name Clock Synthesizer Pin FPGA Pin CLK SYNTHOp U21 14 U15 M18 CLK SYNTHOn U21 15 U15 L18 CLK_SYNTH1p U21 11 U15 AC19 CLK SYNTH1n DNMEG AD DA User Manual U21 12 U15 AB18 www dinigroup com 19 HARDWARE DESCRIPTION 4 2 ADC Clocking The DNMEG_AD DA Daughter Card provides an onboard oscillator X2 as well as a single ended external clock input via an SMA connector J7 Clock Buffer U11 distributes these clocks to both ADC s via clock Multiplexers U9 U10 that are controlled from the FPGA U15 Please refer to the schematic 4 2 1 ADC Oscillator Circuit Oscillator X2 is powered from 2 5V and provides a LVDS clock to the Clock Buffer U11 refer to Figure 5 The EXT_ADC_CLK_SEL signal is driven from the FPGA U15 and selects the clock source on the Clock Buffer U11 The Silicon Laboratories 1531 series of low jitter oscillators are recommended for this application and is available
22. 2 and pulled up on the DNMEG_AD DA Daughter Card The signal is also routed to the FPGA U5 and can be used as a reset to the logic refer to Table 25 Table 25 Daughter Card Reset Signal DC RSTn Signal Name FPGA Pushbutton Switch DC RSTn U5 E14 2 4 11 6 Insertion Removal of Daughter Card Due to the high density MEG Array connectors the pins on the plug and receptacle of the MEG Array connectors are very delicate When plugging in a daughter card make sure to align the daughter card first before pressing on the connector Be absolutely certain that both the small and the large keys at the narrow ends of the MEG Array headers line up BEFORE applying pressure to mate the connectors DNMEG_AD DA User Manual www dinigroup com 63 HARDWARE DESCRIPTION Place it down flat then press down gently DNMEG_AD DA User Manual www dinigroup com 64 HARDWARE DESCRIPTION 11 7 MEG Array Specifications Manufacturer Part Number RoHS Compatible Lead Free Total Number Of Positions Contact Area Plating Mating Force Unmating Force Insulation Resistance Withstanding Voltage Current Rating Contact Resistance Temperature Range Trademark Approvals and Certification Product Specification Pick up Cap Housing Material Contact Material Durability Mating Cycles DNMEG_AD DA User Manual FCI 74390 101LF Bottom Receptacle P5 84520 102LF Top Plug P4 yes 400 0 76 um 30 uin
23. 4 15 AH33 J14 140 DDR2_DQ45 15 AH34 J14 142 DDR2_DQ46 15 AE32 J14 152 DDR2_DQ47 15 AD27 J14 154 DDR2_DQ48 15 AD29 J14 157 DDR2_DQ49 15 AC29 J14 159 DDR2_DQ50 15 AB23 J14 173 DDR2_DQ51 15 AA29 J14 175 DDR2_DQ52 15 AE34 J14 158 DDR2_DQ53 15 AD30 J14 160 DDR2_DQ54 15 AB25 J14 174 DDR2 DQ55 15 AA30 J14 176 DDR2_DQ56 15 AD32 J14 179 DDR2_DQ57 15 AC33 J14 181 DDR2_DQ59 DDR2_DQ60 DDR2_DQ61 DDR2 DQ62 DDR2 DQ63 DDR2 DQSNO DDR2_DQSN1 DDR2_DQSN2 DDR2_DQSN3 DDR2_DQSN4 DDR2_DQSN5 DDR2_DQSN6 DDR2_DQSN7 DDR2_DQSP0 15 W25 14 191 15 AC32 J14 180 15 AB28 J14 182 15 Y24 J14 192 15 W24 J14 194 15 AM22 ju 15 AL25 j14 29 15 AG28 J14 49 15 AM28 J14 68 15 AK32 J14 129 15 AF30 J14 146 15 AC34 J14 167 15 AA26 J14 186 15 AM21 J14 13 U U U U U U U U U U U U U U DDR2_DQ58 U15 AA23 J14 189 U U U U U U U U U U U U U U DNMEG_AD DA User Manual www dinigroup com 46 HARDWARE DESCRIPTION Signal Name FPGA IO Bank 7 amp 11 DDR2 SODIMM DDR2_DQSP1 15 AL24 J14 31 DDR2_DQSP2 15 AG27 J14 51 DDR2_DQSP3 15 AN28 J14 70 DDR2_DQSP4 15 AK31 J14 131 DDR2_DQSP5 15 AF29 J14 148 DDR2_DQSP7 15 AA25 J14 188 DDR2_ODT0 15 AC28 J14 114 DDR2 ODT1 15 AA28 J14 119 DDR2_RASN 15 AE31 J14 108 U U U U U DDR2_DQSP6 U15 AD34 J14 169 U U U U U DDR2_WEN 15 AE26 J14 109
24. 6A 38 Pin Probe All the signals are routed matched length and two resistors R165 R166 are provided to change the reference voltage for the trace debug tools refer to Figure 33 J10 2 x MICTOR_CLK_A 6 MICTOR_CLK PPC_TRC_CLK PPC_DBG_HALTn MICTOR AT5 8 MICTOR B15 MICTOR A14 8 10 MICTOR Bi4 PPC_JTAG_TDO MICTOR_A13 9 10 12 MICTOR B13 PPC_TRC_VSENSE MICTOR A12 T 12 44 MICTOR B12 PPC JTAG TCK MICTOR A11 13 14 16 MICTOR B11 PPC_JTAG_TMS MICTOR A10 15 16 18 MICTOR B10 PPC JTAG TDI MICTOR A 17 18 20 Bi PPC JTAG TRSTn _ MICTOR 19 20 99 MICTOR B8 MICTOR 22 24 MCTOR_ B7 PPC TRC TS10 24 26 MICTOR B6 PPC TROC TS20 26 53 MICTOR B5 PPC_TRC_TS1E 28 30 MICTOR B4 PPC TRC TS2E 30 32 C MICTOR B3 PPC TRC TS3 A 34 MICTOR B2 PPC TRC TS4 e 36 C MICTOR Bi PPC TRC TS5 B 38 MICTOR BO PPC TRC TS6 44 42 43 x 2 767004 2 Note All these signals must be matched lenght 1 50 mils 42 5V R166 DNI 1K MICTOR B13 VA 3 3V R165 VAM 1K Figure 33 38 Pin Mictor Connector 12 2 FPGA to Mictor Connections Table 24 shows the connections from the 38 pin Mictor connector and the Virtex 4 FPGA DNMEG AD DA User Manual www dinigroup com 66 HARDWARE DESCRIPTION Table 26 Connections between FPGA and Mictor Connector Signal Name Mictor Connector Pin FPGA Pin
25. 8 JTAG_PROM_TDI U15 W17 IDD J13 10 DNMEG_AD DA User Manual www dinigroup com 17 HARDWARE DESCRIPTION 4 Clock Generation 4 1 Clock Methodology The DNMEG_AD DA has a flexible and configurable clocking scheme Figure 4 is a block diagram showing the clocking resources and connections EXT CLK CLKO EXT ADCOp n CLK ADCOp n o ADC EXT CLK1 EXT ADCipin M ADCO ADCO DCLKOUTp n USER cLk2 EXT ADCtpin 180 MUX AD9430 CLK ICS854054 ADC OSC BUFFER ues IRL sa CLK FPGA ADCOp n 5x7 CLK3 EXT DACOp n CLK ADCip n ADC1 ADC DCLKOUTp n AD9430 MUX CLK FPGA ADCipin cS854054 Oly EXT CLK EXT CLK CLKO EXT DACip n CLK MUX DACp n gt gt gt o gt DAC EXT DAC USER MUX AD9777 ICS85411 CLK cLK2 EXT DACp n AU DAC OSC BUFFER LVDS ICS85214 5x7 CLK1 EXT DACip n CLK FPGA DACpm wy DC Bopindi DDR2 CKOp n en po Bopinst y CLK DC FPGAp n LVDS BUFFER ICS85411 DDR2 CKip n Br S08 LDDRz Kip DDR II SODIMM 2GB s 200PIN ca ev co x CLK DC B 2p i lt wz LOR Bap Virtex 4 FPGA Oss Ezg XC4VLX40 ess 528 LVDS OSC ug S lt CLK_DC_B_0p n DDR2 OSC OUTp n Eig 28 gt P
26. C1 Sart Capture DAC Menu Enter Option Connected 0 01 23 Auto detect 19200 8 N 1 4 Connect a Signal Generator IMHz Sine Wave 200mVptp OV Offset to the ADC channel 0 SMA J1 Select test option c ADCO Start Capture 1K in the Hyperlerminal window and verify that the digital data captured increments decrements to the amplitude of a sine wave 5 Connect a Signal Generator IMHz Sine Wave 500mVptp OV Offset to the ADC channel 1 SMA J3 Select test option d ADCI Start Capture in the HyperTerminal window and verify that the daa captured increments decrements to the amplitude of a sine wave 6 Connect an Oscilloscope to the DAC channel 1 SMA J5 Select test option v DAC Menu in the HyperTerminal window and verify that the data output is a sinusoidal waveform Please reference the CUST CD for code examples The next section describes the hardware in detail DNMEG AD DA User Manual www dinigroup com 11 HARDWARE DESCRIPTION Ci Hardware Description This chapter describes the functional blocks of the design and focuses on the 1 Overview The DNMEG_AD DA Daughter Card provides for a comprehensive collection of peripherals to use in creating a system around the Xilinx Virtex 4 FPGA A high level block diagram of the DNMEG AD DA Daughter Card is shown in Figure 2 followed by a brief description of each section DNMEG_AD DA User Manual www dinigroup com 12 HARDWARE DESCRIPTION EXT POW
27. ER SWITCHING PSU 4 5V_ STATUS LED S lt 1 8V 5A 20 PTH05050W lt 00000000 S Z N 2 x 5 x u amp m m u m LINEAR PSU LP2996 DDR II SODIMM 2GB 200PIN CHANNEL 1 O qa XT CLOCK CONVERTER EXT o gt 12 Bit 210MSPS MICTOR SJ AD9430 OOo o AID CONVERTER Oo 12 Bit 210MSPS AD9430 CLOCK circut CHANNEL 2 VIRTEX 4 CHANNEL 1 FPGA o XC4VSX55 FBGA1148 z gt go z B m O DAC 4 23 9 E CONVERTER Sz E 0 16 Bit 400MSPS API ADSI 21 Pl 5 AD9777 8 m ls w 2B 829 CONFIGURATION SERIALFLASH prz 82 PROM 4 Mbit S ism CHANNEL 2 8 385 XCF32P AT45DB041B waya G cae ag IOS EUER 8 ji 412V 4A E a 35338 45V Q 4A T p o JTAG RS232 PSU FPGA Options 1 2V 10A S LX40 YNS05S10 LX60 LX80 2 5V 5A LX100 PTH05050W LX160 SX55 3 8V 5A NC on Bank 2 of the Daughter Card Headers IO Bank 13 not available PTHO5050W Figure 2 DNMEG_AD DA Daughter Card Block Diagram 2 Xilinx Virtex 4 FPGA The Virtex 4 Family is the newest generation FPGA from Xilinx The innovative Advanced Silicon Modular Block or ASMBL column based architecture is unique in the prog
28. FPGA and Clock Synthesizer e 11 Connections between FPGA and Daughter Card Header Clocks 2 ADC Migration 13 ADC Connections to the FPG 14 DAC Connections to the FPGA 5 Connections between FPGA and the Serial FLASH 6 DDR2 Termination Scheme 17 Serial Presence Detect Connections 8 Connections between the FPGA and the DDR2 SODIMM e 19 PCB Trace Lengths e 20 User LED s e 21 DONE LED e 22 Power Supply Status LED s e 23 Connections between FPGA and the RS232 Port e 24 FPGA to Daughter Card Header IO Connections e 25 Daughter Card Reset Signal DC_RSTn e 26 Connections between FPGA and Mictor Connector 000000 INTRODUCTION Ci Introduction This User Manual accompames the DNMEG_AD DA Daughter Card For speajic information regarding the VirtexA parts please reference the datasheet on the Ilinc website 1 About the DNMEG AD DA Daughter Card The DNMEG_AD DA Daughter Card provides a complete development platform for designing and verifying DSP applications based on the Xilinx Virtex 4 FPGA family The DNMEG_AD DA provides dual 12 Bit 210 MSPS independent ADC channels and a dual 16 Bit 160 MSPS DAC The DNMEG_AD DA Daughter Card can operate in standalone mode or in conjunction with one of the Dini products that houses a 400 pin MEG Array Daughter card header e g DN8000K10PSX 2 DNMEG AD DA Daughter Card Features F
29. GA U15 Table 18 Connections between the FPGA and the DDR2 SODIMM Signal Name FPGA IO Bank 7 amp 11 DDR2 SODIMM DDR2_A0 15 AG30 j14 102 DDR2 A1 15 AH32 j14 101 DDR2 A2 15 AH30 J14 100 DDR2_A3 15 AJ29 J14 99 DDR2 A4 15 AL33 J14 98 DDR2_A5 15 AM33 J14 97 DDR2_AG 15 AM30 J14 94 DDR2_A7 15 AN30 J14 92 DDR2_A8 15 AN32 J14 93 DDR2_A9 15 AP30 J14 91 DDR2_A10 15 AF28 J14 105 DDR2_A11 15 AN29 J14 90 DDR2_A12 15 AP27 J14 89 DDR2_A13 15 AA24 J14 116 DDR2_A14 15 AN27 J14 86 DDR2_A15 15 AP25 J14 84 DDR2 BAO 15 AE29 J14 107 DDR2 BA1 15 AF31 J14 106 U U U U U U U U U U U U U U U U U U DNMEG_AD DA User Manual www dinigroup com 43 HARDWARE DESCRIPTION Signal Name FPGA IO Bank 7 amp 11 DDR2 SODIMM DDR2_BA2 15 AP26 J14 85 DDR2_CASN 15 AC27 J14 113 DDR2 CKEO 15 AP24 J14 79 DDR2_CKE1 15 AN23 J14 80 DDR2_CSNO 15 AE27 J14 110 DDR2 CSN1 15 AB22 14 115 DDR2 DMO 15 AG23 J14 10 DDR2_DM1 15 AM23 J14 26 DDR2_DM2 15 AK27 J14 52 DDR2_DM3 15 AL29 J14 67 DDR2_DM4 15 AK33 J14 130 DDR2_DM5 15 AF33 J14 147 DDR2_DM6 15 AC30 J14 170 DDR2_DM7 15 AB30 J14 185 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQ4 DDR2 DQ5 DDR2 DQ6 DDR2 DQ7 DDR2_DQ8 DDR2_DQ9 DDR2 DQ10 DDR2 DQ11 DDR2 DQ12 DDR2_DQ13 DDR2_DQ14 15 AN22 J147 15 AJ24 J1417 15 AG25 J14 19 15 AK21 J14 4 15 AK22 J146 15 AK23 J14 14 15 AF24 J14 16 15 AL23
30. J14 23 15 AK24 J14 25 15 AJ25 J14 35 15 AF26 J14 37 15 AP21 J14 20 15 AP22 J14 22 15 AN24 J14 36 U U U U U U U U U U U U U U DDR2 DQO U15 AL21 J14 5 U U U U U U U U U U U U U U DNMEG AD DA User Manual www dinigroup com 44 HARDWARE DESCRIPTION Signal Name FPGA IO Bank 7 amp 11 DDR2 SODIMM DDR2 DQ15 15 AM25 J14 38 DDR2 DQ16 15 AG26 J14 43 DDR2 DQ17 15 AH27 J14 45 DDR2_DQ18 15 AH28 J14 55 DDR2_DQ19 15 AK29 J14 57 DDR2 DQ20 15 AN25 J14 44 DDR2 DQ 1 15 AK26 J14 46 DDR2 DQ22 15 AL28 J14 56 DDR2_DQ23 15 AH29 J14 58 DDR2_DQ24 15 AM26 J14 61 DDR2_DQ25 15 AM27 J14 63 DDR2_DQ26 15 AJ30 J14 73 DDR2_DQ27 15 AP31 J14 75 DDR2_DQ28 15 AL26 J14 62 DDR2_DQ30 DDR2_DQ31 DDR2_DQ32 DDR2_DQ33 DDR2_DQ34 DDR2_DQ35 DDR2_DQ36 DDR2_DQ37 DDR2_DQ38 DDR2_DQ39 DDR2_DQ40 DDR2_DQ41 DDR2_DQ42 DDR2_DQ43 15 AP29 J14 74 15 AL30 J14 76 15 AM32 J14 123 15 AL34 J14 125 15 AJ31 J14 135 15 AG31 J14 137 15 AM31 J14 124 15 AL31 J14 126 15 AK34 J14 134 15 AJ34 J14 136 15 AG32 J14 141 15 AG33 J14 143 15 AF34 J14 151 15 AE33 J14 153 U U U U U U U U U U U U U U DDR2_DQ29 U15 AJ27 J14 64 U U U U U U U U U U U U U U DNMEG_AD DA User Manual www dinigroup com 45 HARDWARE DESCRIPTION Signal Name FPGA IO Bank 7 amp 11 DDR2 SODIMM DDR2_DQ4
31. MEG_AD DA Daughter Card may not meet the minimum load requirements The Dini Group recommends attaching an old disk drive to one of the spare connectors Figure 26 ATX Power Supply 10 2 1 External Power Connector Figure 27 indicates the connections to the external power connector This header is fully polarized to prevent reverse connection and is rated for 250VAC at 2A per contact DNMEG AD DA User Manual www dinigroup com 51 HARDWARE DESCRIPTION TP19 I ev O up l 12V 10uF 0449 16V 0 1uF 2096 CERAMIC TP18 1 y O up l 5V 20 CERAMIC Figure 27 External Power Connection 11 Daughter Card Headers The DNMEG_AD DA has two 400 pin MEG Array daughter card headers one on the TOP P2 of the PCB and one on the BOTTOM P3 of the PCB They share the same signals with the exception of pins E5 and F5 that is used as a differential clock signal pair All signals on the DNMEG_AD DA Daughter Card Headers are all routed as differential 50 Ohm transmission lines No length matching is done on the PCB for Daughter Card signals except within a differential pair because the Virtex 4 FPGA is capable of variable delay input using the built in IDELAY capabilities Other connections on the daughter card connector system include three dedicated differential clock connections for inputting global clocks from an external source power connections bank Veco power and a reset signal 11 1 Daughter Car
32. Micron example part number for a 512MB 46Meg x 64 200 pin SODIMM SDRAM module is MISHTF6464HDY 40E 7 2 1 DDR2 Clocking Refer to DDR2 Clocking in par 4 4 in this User Manual 7 2 2 DDR2 Termination Scheme The DDR2 SDRAM SODIMM interface has bi directional and uni directional signals and the termination scheme is different for both types of signals see Table 16 Reference the JESD8 15a JEDEC standard Stub Series Terminated Logic for 1 8V SSTL_18 for more information regarding output specifications DNMEG_AD DA User Manual www dinigroup com 39 HARDWARE DESCRIPTION Table 16 DDR2 Termination Scheme FPGA SODIMM Clock CK CKn SSTL_18 DIFF No Tetmination Address A BA SSTL_18_C1 DCI 56 Pull up to 0 9V Control RASn SSTL_18_C1 DCI 56 Pull up to 0 9V CASn WEn CSn CKE STTL1 8_Class1 For uni directional signals Le address and control signals transmitting from the Virtex 4 FPGA U15 to the SODIMM module J14 the board uses 25 Q resistor in series in conjunction with a 56 Q pull up to Vpr see Figure 20 The 25 Q resistor in series is realized with Digitally Controlled Impedance DCI on the FPGA U15 Vit 0 5 Vppo Device under test Vppa Vrer 0 5 Vppo Vout Rs 20Q Z 500 Vngr 9 5 Vppo Figure 20 SSTL 18 Symmetrically Single Parallel Terminated SSTL1 8 Class2 For bi directional signals i e DQ DOS DM and parity bit signals the board uses a dual
33. RE DESCRIPTION 11 2 1 Special Pins on the Daughter Card Header VREF Depending on the IO standard a reference voltage Vp may be required In order to accommodate this requirement it is possible to connect the Vg signals on the Daughter Card Header P2 P3 by installing the following resistors as listed in Figure 30 VCCO DC BO VREF DC BO VBEF DC BO DC BOn5 VCCO DC B1 DC B1 VBEF DC B1 DC Bin7 VCCO DC B2 VREF DC B2 o VBEF DC B2 DC B2n5 Figure 30 VREF Signals GCAp n GCBp n and GCCp n The daughter card pin out defines six bidirectional clock pins These clock signals are intended to be used as three differential clock signals These signals are clock capable and can be used for soutce synchronous clocking 11 3 Veco Power Supply On the Virtex 4 FPGA each IO bank has its own Veco pins Veco is determined by the IO standard for that particular IO bank Since a daughter card will not always be present on a daughter card connector a Vcco bias generator is used on the motherboard for each daughter card bank to keep the Vcco pin on the FPGA within its recommended operating range The Daughter Card drives Veco to the required level for the particular IO standard The Vcco impressed by the Daughter Card needs to DNMEG AD DA User Manual www dinigroup com 55 HARDWARE DESCRIPTION satisfy the Vimarnay of the FPGA on the host board There are three Adjustable Linear Power Supplies
34. S232 ENn EN FORCEOFF FORCEON INVALID C1 V C1 V C2 VCC L Co GND C405 C404 bis T 0 1uF 0 1uF 0 1uF 0 1uF 1CL3221 SSOP16 Figure 24 RS232 Port 9 1 1 Connections between FPGA and RS232 Port The RS232 port is connected to IO Bank6 on the FPGA U15 The connections between the FPGA and the RS232 Port ate shown in Table 23 Table 23 Connections between FPGA and the RS232 Port DNMEG_AD DA User Manual www dinigroup com 49 HARDWARE DESCRIPTION 10 Power Distribution The DNMEG_AD DA Daughter Card supports a wide range of technologies from legacy devices like serial ports to DDR2 SDRAM and ADC DAC converters This wide range of technologies including the various FPGA power supplies requires a wide range of power supplies These are provided on the DNMEG_AD DA Daughter Card using a combination of switching and linear power regulators 10 1 In System Operation Duting In System operation the DNMEG AD DA Daughter Card is powered from the daughter card header P3 see Figure 25 These power connections are protected using fast blow fuses to avoid damage to the motherboard or connector pins due to accidental short circuits Since 3 3V is available on the daughter card header the on board 3 3V power supply PSU1 will automatically be shut down during in system operation by pulling INHIBIT pin low on the power supply PSU4 F
35. TANT TANT VREF DDRII_VREF GND PKG GND c45 LP2996 PSOP 8 0 1uF 45V Figure 23 VIT Linear Power Supply 7 2 7 Serial Presence Detect Operation DDR2 SDRAM modules incorporate serial presence detect SPD The SPD function is implemented using a 2048 bit EEPROM This nonvolatile storage device contains 256 bytes The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters The remaining 128 bytes of storage are available for use by the customer System READ WRITE operations between the FPGA U15 and the slave EEPROM device occur via a standard I2C bus using the DIMMs SCL clock and SDA data signals together with SA 1 0 which provide four unique DIMM EEPROM addresses Write protect WP is tied to ground on the module permanently disabling hardware write protect VDDSPD is connected to 2 5V to meet IO standards of IO Bank 2 on the FPGA U15 DNMEG AD DA User Manual www dinigroup com 42 HARDWARE DESCRIPTION Table 17 Serial Presence Detect Connections Signal Name FPGA IO Bank 7 amp 11 DDR2 SODIMM DDR2 SA0 J14 198 Pull Down 100 ohm R49 2 DDR2 SA1 j14 200 Pull Down 100 ohm R48 2 DDR2 SCL U15 AB15 J14 197 Pull up 10K R44 DDR2 SDA U15 AC15 J14 195 Pull up 10K R45 7 2 8 JTAG connections to FPGA Table 18 shows the DDR2 SDRAM SODIMM connector J14 pinouts and the connection to the Virtex 4 FP
36. THE DINI GROUP LOGIC Emulation Source User Manual DNMEG AD DA LOGIC EMULATION SOURCE DNMEG AD DA User Manual Version 2 0 The Dini Group 7469 Draper Avenue La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1728 support dinigroup com www dinigroup com Copyright Notice and Proprietary Information Copyright 2006 The Dini Group All rights reserved No part of this copyrighted work may be reproduced modified or distributed in any form or by any means without the prior written permission of The Dini Group Right to Copy Documentation The Dini Group permits licensee to make copies of the documentation for its internal use only Each copy shall include all copyrights trademarks disclaimers and proprietary rights notices Disclaimer The Dini Group has made reasonable efforts to ensure that the information in this document is accurate and complete However The Dini Group assumes no liability for errors or for any incidental consequential indirect or special damages including without limitation loss of use loss or alteration of data delays or lost profits or savings arising from the use of this document or the product which it accompanies Table of Contents TINTRODUCTION REM 1 1 ABOUT THEDNMEG AD DA DAUGHTER CARD ierit esten e EKEN EE eH Ese ene EU SIR EPE eee EE dee Pres eene EI EEKE IPEE 1 2 DNMEG_AD DA DAUGHTER CARD FEATURES
37. al Name FPGA Pin DAC Pin DAC_BD14 U8 32 U15 AB10 DAC_BD15 U8 31 U15 AC10 DAC_DCLK U8 8 U15 E18 DAC FSADJ1 U8 60 R20 2 DAC FSADJ2 U8 59 R19 2 DAC IOUTA1 U8 69 T1 3 DAC IOUTA2 U8 73 T2 3 DAC IOUTB1 U8 68 T1 1 DAC IOUTB2 U8 72 T2 1 DAC RESET U8 57 U15 AF3 DAC_SPI_CLK U8 55 U15 AC8 DAC_SPI_SCN U8 56 U15 AG3 DAC_SPI_SDIO U8 54 U15 AC9 DAC_SPI_SDO U8 53 U15 H19 7 Memory 7 1 Serial FLASH The Atmel AT45DB041B U25 provides 4 Mbit of serial FLASH memory organized as 2048 pages of 264 bytes each The FLASH memory is connected to the FPGA U15 via an SPI interface see Figure 19 The FLASH does not require high input voltages for programming allowing for simple in system reprogrammability FLASH SI FLASH SCK FLASH CSn FLASH WPn FLASH RSTn 1K 1K C207 0 1uF Figure 19 Serial FLASH T 1 1 Connections between FPGA and Serial FLASH The Serial FLASH is connected to IO Bank6 on the FPGA U15 The connections between the FPGA and the Serial FLASH are shown in Table 15 DNMEG AD DA User Manual www dinigroup com 38 HARDWARE DESCRIPTION Table 15 Connections between FPGA and the Serial FLASH Signal Name FLASH SO FLASH SI FLASH SCK FLASH CSn FLASH WPn FLASH RSTn 7 2 DDR2 SDRAM DDR2 SDRAM is the latest generation of double data rate DDR SDRAM technology with impr
38. and bookmark http www dinigroup com Data Book Pages from Virtex 4 Databook which contains device specific information on Xilinx device characteristics E Mail You may direct questions and feedback to the Dini Group using this e mail address support dinigroup com Phone Support Call us at 858 454 3419 during the hours of 8 00am to 5 00pm Pacific Time FAQ The download section of the web page may contain a document called DNMEG_AD DA Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the Users Manual DNMEG_AD DA User Manual www dinigroup com 4 GETTING STARTED Ci Getting Started Congratulations on your purchase of the DNMEG_AD DA Daughter Card The remainder of this chapter describes the contents of the box and how to run the reference design that accompanies the DNMEG_AD DA Daughter Card 1 ESD Warning The DNMEG_AD DA Daughter Card is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGAs and circuit boards However if needed the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda org basics part1 cfm The DNMEG_AD DA Daughter Card has been factory tested and pre programmed to ensure correct operation You do not need to alter any jumpers or program anythin
39. atched clock dividers PMCD Differential global clocks e XtremeDSP Slice O O O 18 x 18 two s complement signed Multiplier Optional pipeline stages Built in Accumulator 48 bit and Adder Subtracter e Smart RAM Memory Hierarchy O O Distributed RAM Dual port 18 Kbit RAM blocks Optional pipeline stages Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals High speed memory interface supports DDR and DDR 2 SDRAM QDR IL and RLDRAM II e SelectlOTechnology o O 1 5V to 3 3V I O operation Built in ChipSync source synchronous technology DNMEG_AD DA User Manual www dinigroup com 14 HARDWARE DESCRIPTION 3 Digitally controlled impedance DCI active termination Fine grained I O banking configuration in one bank Flexible Logic Resources Secure Chip AES Bitstream Encryption 90 nm Copper CMOS Process 1 2V Core Voltage Hlip Chip Packaging including Pb Free Package Choices RocketIO 622 Mb s to 6 5 Gb s Multi Gigabit Transceiver MGT FX only IBM PowerPC RISC Processor Core FX only o PowerPC 405 PPC405 Core o Auxiliary Processor Unit Interface User Coprocessor Multiple Tri Mode Ethernet MACs FX only FPGA Configuration Virtex 4 devices are configured by loading application specific configuration data the bitstream into internal memory Because Xilinx FPGA configuration memory is volatile it must be configured each time it is powered up
40. board area the ADC s operating temperature is approximately 40 C This is hot to the touch Please supply external cooling if possible Table 12 ADC Migration Part Number Number of Bits AD9411 10 AD9430 210 12 DNMEG_AD DA User Manual www dinigroup com 28 HARDWARE DESCRIPTION 5 1 Differential Input ADC Driver The AD8351 U1 is a low cost differential amplifier useful in RF and IF applications up to 2 2 GHz The voltage gain can be set from unity to 26 dB using a single external gain resistor R59 and R The AD8351 U1 provides a nominal 150 Q differential output impedance The excellent distortion performance and low noise characteristics of this device allow for a wide range of applications The AD8351 U1 can also be used as a single ended to differential amplifier with similar distortion products as in the differential configuration The user can modify the daughter card for AC or DC coupled operation The values of C2 C3 C19 and C20 should be selected such that their reactance s are negligible at the desired frequency of operation refer to Figure 14 VCCA_ADCO_3V3 VCCA_ADCO_3V3 VCCA_ADCO_3V3 C15 C12 10uF R9 h 16V 1K 20 U1 CER ADCO_PWUP 1 10 ea ee E INHI OPHI INLO P OPLO TIE Leni COMM 2 3 4 5 R59 AD8351 MSOP10 em 620R R62 A 360R Figure 14 Differential Input Amplifier R2 gt AN 24 9R R11 AV 24 9R R3 p AN 24 9R Ri2 AA 24 9R
41. configuration data via the serial interface and configure their SRAM cells This scheme is referred to as the Master Serial configuration scheme because the Virtex 4 FPGA U15 controls the configuration interface The XCF32P U27 serial configuration PROM support CCLK up to 33MHz Table 1 shows the uncompressed configuration file size for the largest Virtex 4 devices that are supported and configured by the PROM Table 1 Virtex 4 Uncompressed tbf File Size Device Data Size Bits XC4VLX100 30 711 680 XCAVSX55 22 749 184 3 2 Boundary Scan and JTAG Configuration Virtex 4 devices support the new IEEE 1532 standard for In System Configuration ISC based on the IEEE 1149 1 standard The IEEE 1149 1 Test Access Port and Boundary Scan Architecture is commonly referred to as JTAG JTAG is an acronym for the Joint Test Action Group the technical subcommittee initially responsible for developing the standard This standard provides a means to ensure the integrity of individual components and the interconnections between them at the board level With multi layer PC boards becoming increasingly dense and more sophisticated surface mounting techniques in use boundary scan testing is becoming widely used as an important debugging standard The Virtex 4 family is fully compliant with the IEEE Standard 1149 1 Test Access Port and Boundary Scan Architecture The architecture includes all mandatory elements defined in the IEEE 1149 1 S
42. cuits T1 1T provides excellent rejection of common mode distortion that is even order harmonics and noise over a wide frequency range It also provides electrical isolation and the ability to deliver twice the power to the load Transformers with different impedance ratios may also be used for impedance matching purposes see Figure 18 Note that the lower band of operation for these transformers 1s 300 kHz to 500 kHz DNMEG AD DA User Manual www dinigroup com 35 HARDWARE DESCRIPTION 3 T 4 Py ees DAC IOUTA2 R280 5 D is DNI 49 9R 142 0701 501 DAC_IOUTB2 ia le T1 1T KK81 SE L J5 3 7 4 LYX EE DAC_IOUTA1 R281 e 5 4 5 DNI 49 9R e 142 0701 501 DAC IOUTB1 Tos cme T1 1T KK81 d Figure 18 DAC Channel 1 Single Ended Output A differential resistor R57 R58 can be inserted in applications where the output of the transformer is connected to the load Ri 545 via a passive reconstruction filter or cable Rpr is determined by the transformers impedance ratio and provides the proper source termination that results in a low VSWR Note that approximately half the signal power dissipates across Rp 6 4 Voltage Reference The AD9777 U8 uses the internal 1 2 V voltage reference 6 5 Full Scale Current Adjust Each 16 bit DAC provides two complementary current outputs whose full scale currents can be determined either from a single external resistor R20 in 1R mode or independently
43. d e e 2 2 e X xor EE 44 444 H _ M e e e T T rrt tere teeth Xx _ ow m co w o S e S e 5 S I npn in I fol bd sl at pp oe pew y waw n dt ig cau pb d eae VS I Mm pn UU 5 I oo gt 2 eo hM e X TO u punpa po panon unpa pou pnya p bey o oo o o e ec e e one wm m a lt w m ca DNMEG_AD DA User Manual www dinigroup com 68 APPENDIX Appendix 44 Appendix A UCF File See the reference CD for the Xilinx Universal Constraint File UCH file DNMEG_AD DA User Manual www dinigroup com 69
44. d clocking Refer to Daughter Card Clocks in par 4 6 in this User Manual 11 2 Daughter Card Header Pin Assignments The pin assignments of the DNMEG_AD DA Daughter Card Headers were designed to reduce cross talk to manageable levels while operating at full speed of the Virtex 4 LVDS standards The Daughter Card Header is divided into three banks refer to Figure 28 Bank 0 on the Daughter Card Header is routed to IO Bank 5 on the FPGA U15 etc DNMEG_AD DA User Manual www dinigroup com 52 HARDWARE DESCRIPTION A1 VIRTEX 4 FPGA XC4VSX55 FBGA1148 Figure 28 Daughter Card Interconnect Diagram The Virtex 4 IOBs support source synchronous interfacing with LVDS signaling at up to 1Gbps The ground to signal ratio of the connector is 1 1 refer to Figure 29 General purpose IO is arranged in a GSGS pattern to allow high speed single ended or differential use On the host these signals are routed as loosely coupled differential signals meaning when used differentially they benefit from the noise resistant properties of a differential pair but when used in a single ended configuration they do not interfere with each other excessively DNMEG_AD DA User Manual www dinigroup com 53 HARDWARE DESCRIPTION Figure 29 Daughter Card Header Pin Assignments DNMEG_AD DA User Manual A B CDE F GH JK L24P L25P B1 L24N 2 B2 L2P L26P o o 100 ON www dinigroup com 54 HARDWA
45. er Card Receptacle Daughter Card Signal Name FPGA Pin Bottom Pin Plug Top Pin DC_BON8 DC_BON11 P3 G8 P2 G8 DC_BON12 DC BONIS PaGi2 DC _B0P1 P3 A3 P2 A3 DC _B0P2 P3 C3 P2 C3 DC_BOP3 DC_BOP4 DC BOP5 DC BOP6 DC B0P7 DNMEG AD DA User Manual www dinigroup com 57 HARDWARE DESCRIPTION Daughter Card Receptacle Daughter Card Signal Name FPGA Pin Bottom Pin Plug Top Pin DC_BOP11 DC_BOP12 P3 K7 P2 K7 DC_BOP13 P3 A9 P2 A9 DC_BOP14 P3 C9 DC_BOP15 DC_BOP16 P3 K9 Dc B0P22 EIE Dc BIN ZI DC BiNS ZEIT DC B1N10 U15 M31 P3 J20 P2 J20 DNMEG_AD DA User Manual www dinigroup com 58 HARDWARE DESCRIPTION Daughter Card Receptacle Daughter Card Signal Name FPGA Pin Bottom Pin Plue Top Pin DNMEG_AD DA User Manual www dinigroup com 59 HARDWARE DESCRIPTION Daughter Card Receptacle Signal Name FPGA Pin Bottom Pin Daughter Card Plug Top Pin DC_B1P30 U15 K28 P3 E23 DC_B1P31 U15 M32 P3 E25 Note The following signals are NC on the LX40 LX60 and SX55 parts Dc eas P2 K23 P2 A25 P2 C25 P2 H25 P2 K25 P2 A27 P2 C27 P2 H27 P2 K27 P2 E17 P2 E19 P2 E21 P2 E23 P2 E25 P2 B30 P2 D30 P2 G30 P2 J30 P2 B32 P2 D32 P2 G32 P2 J32 P2 B34 P2 D34 P2 G34 P2 J34 P2 B36 P2 D36 DC_B2 U15 U25 P3 G36 P2 G36 DNMEG_AD DA User Manual www dinigroup com 60 HARDWARE DESCRIPTION Daughter Card Receptacle Dau
46. external resistor R59 which is connected between pins 2 and 5 The gain can be set to any value between 0 dB and 26 dB Reference the datasheet for more information Gain Ay R Ro 5 6 9 2 R Ri Re Ri 46 19 5 R R R 39 Ro 5 1 4 Common Mode Adjustment The output common mode voltage level is the dc offset voltage present at each of the differential outputs The ac signals are of equal amplitude with a 180 phase difference but are centered at the same common mode voltage level The common mode output voltage level can be adjusted from 1 2 V to 3 8 V by driving the desired voltage level into the VOCM pin The voltage supplied to the VOCM pin sets the common mode voltage at both the input and output Resistors R70 R61 allows for the adjustment of the output common mode voltage set to 1 65V DNMEG AD DA User Manual www dinigroup com 30 HARDWARE DESCRIPTION 5 2 ADC The AD9430 210 U7 is a 12 bit monolithic sampling analog to digital converter ADC optimized for high performance low power and ease of use The product operates up to a 210 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems All necessary functions including a track and hold T H and reference are included on the chip to provide a complete conversion solution 5 2 1 Clock Source Numerous clocking options are available please refer to par 4 2 5 2 2 Analog Inpu
47. from two separate resistors R19 R20 in ZR mode Please refer to the datasheet for more information 6 6 Serial Port Interface SPI The AD9777 U8 is configured via a synchronous serial communications port The interface allows read write access to al registers that configure the AD9777 Please refer to the datasheet for more information 6 7 DAC connections to FPGA Table 14 shows the connection between the DAC and the Virtex 4 FPGA DNMEG AD DA User Manual www dinigroup com 36 HARDWARE DESCRIPTION Table 14 DAC Connections to the FPGA Signal Name FPGA Pin DAC Pin DAC_ADO U8 30 U15 AG1 DAC AD1 U8 29 U15 AG2 DAC AD2 U8 28 U15 AH2 DAC_AD3 U8 27 U15 AH3 DAC_AD4 U8 24 U15 AD4 DAC_AD5 U8 23 U15 AE4 DAC_AD6 U8 22 U15 AA15 DAC_AD7 U8 21 U15 Y16 DAC_AD8 U8 20 U15 AB8 DAC_AD9 U8 19 U15 AC7 DAC_AD10 U8 16 U15 AD5 DAC AD11 U8 15 U15 AD6 DAC AD12 U8 14 U15 AE2 DAC AD13 U8 13 U15 AE3 DAC AD14 U8 12 U15 Y12 DAC AD15 U8 11 U15 Y13 DAC BDO U8 50 U15 AL3 DAC_BD1 U8 49 U15 AM3 DAC BD2 U8 48 U15 AG7 DAC BD3 U8 47 U15 AG8 DAC_BD4 U8 46 U15 AM1 DAC_BD5 U8 45 U15 AM2 DAC BD6 U8 42 U15 AB12 DAC BD7 U8 41 U15 AB13 DAC BD8 U8 40 U15 AH4 DAC_BD9 U8 39 U15 AH5 DAC BD10 U8 38 U15 AE8 DAC_BD11 U8 37 U15 AF8 DAC_BD12 U8 34 U15 AK2 DAC_BD13 U8 33 U15 AK3 DNMEG_AD DA User Manual www dinigroup com 37 HARDWARE DESCRIPTION Sign
48. g to see the board work A reference design is included on the CD provided The 400 pin daughter card connectors are not 5V tolerant Take care when handling the board to avoid touching the daughter card connectors 2 Using the Reference Design Main The Dini Group provides a reference design for the DNMEG_AD DA to help the user get familiar with the board and start building applications e MainRef Described in this document programs the PROM with a design that configures the FPGA and allows the user to test all the interfaces on the boatd DNMEG AD DA User Manual www dinigroup com 5 GETTING STARTED Attach an ATX Power Supply to the power header J12 on the DNMEG_AD DA Daughter Card Connect the Xilinx Platform Cable USB from the Test PC to the JTAG Header J13 Connect the RS232 serial cable from the Test PC to the RS232 Header P1 Ensure that pin 1 location of the cable aligns with pin 1 location on the PCB If the kit contains a Memory Module populate J14 with the SODIMM Module Do not insert the SODIMM module with the board powered 2 1 HyperTerminal Setup Connect the RS232 Serial cable to a COM port on the Test PC and configure HyperTerminal to the following settings DNMEG_AD DA User Manual www dinigroup com 6 GETTING STARTED COM1 Properties Port Settings Bits per second Data bits Parity Stop bits Flow control 2 2 Configuring the FPGA This section
49. ghter Card Signal Name FPGA Pin Bottom Pin Plug Top Pin DNMEG AD DA User Manual www dinigroup com 61 HARDWARE DESCRIPTION Daughter Card Receptacle Daughter Card Signal Name FPGA Pin Bottom Pin Plug Top Pin Note The highlighted signals DC_BOp n31 are used as a differential clock input to the Daughter Card refer to Daughter Card Clocks in par 4 6 The shaded signals are not available on the LX40 LX60 and SX55 parts 11 5 Power and Reset The 3 3V 5V and 12V power rails are supplied to the DNMEG_AD DA Daughter Card Headers from the host Dini Card eg DN8000K10PCI Each pin on the MEG Array connector is rated to tolerate 1A of current without thermal overload Each power rail supplied from the Daughter Card Header is fused refer to Figure 32 33V Y Br a P TA BA K 5A P5 1 P12VFUSED_DC_B A1 E1 CLK DC B 0p Kt E Tee GCAP Fy CLK DC B On P12V 2 acan 2 PBVFUSED DC B Ci ES CLK DC B 1p VCCO DC B0 1 H PPV 1 je GCBP F3 a n o r s GCBN P3 SVFUSED DC B B2 e ES CLK DC B 2p i D P3 3V_1 lt GCCP ES CIC E gt n 1 Rize Go P3 3V 2 GCCN TOE P3 3V 3 R173 DC_RST 2 RSTn B3S 1000 1K Clock Power Reset pg8 12 DC_ASTn 74390 101LF Figure 32 Daughter Card Header Power amp RESET DNMEG AD DA User Manual www dinigroup com 62 HARDWARE DESCRIPTION The DC_RSTn signal is driven by a pushbutton switch S
50. gold over 0 76 um 30 pin nickel 30 grams per contact average 20 grams per contact average 1000 M ohms 200 VAC 0 45 amps 20 to 25 m ohms max initial 10 m ohms max increase after testing 40 C to 85 C MEG Atray UL and CSA approved GSe 12 100 from FCI websit yes LCP Copper Alloy 50 www dinigroup com 65 HARDWARE DESCRIPTION 12 Mictor Header The DNMEG_AD DA provides a 38 pin Mictor Header J10 to allow debug trace access The Agilent E9524A Inverse Assembler for Xilinx MicroBlaze is designed to work with trace signals from the MicroBlaze core Agilent Technologies and Xilinx have developed a logic analysis trace solution for Xilinx s MicroBlaze embedded processor that overcomes the traditional difficulties of tracing software execution using a logic analyzer Combining the capabilities of a MicroBlaze inverse assembler with a specialized trace core simplifies measurement setup and reduces the number of pins required In addition the trace core overcomes the lack of visibility you encounter when you employ cache and pipelining and unlocks the power of the logic analyzer to make accurate measurements You get easy access to the insight you need to increase the quality of your design and ensure its timely completion See Agent E95224A Trace Toolset for Xilinx MicroBlaze Design Guide on the Agilent website 12 1 1 Mictor Header Circuit The Mictor header J10 is mapped to interface with the Agillent E534
51. he items If any of these items are missing contact The Dini Group before you proceed The DNMEG_AD DA Daughter Card kit includes the following e RS232 IDC header cable to female DB9 e RS232 serial cable DB9 e CD ROM containing o Virtex 4 Reference Design Verilog O User manual pdf format o Board Schematic pdf format o Component Datasheets pdf format Optional items that support development efforts not provided V Xilinx ISE software v Xilinx Platform Cable USB download cable Y DDR II SODIMM Available upon request 4 Inspect the Board Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment Verify that all components are on the board and appear intact DNMEG AD DA User Manual www dinigroup com 3 INTRODUCTION 5 Additional Information For additional information please visit http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL User Manual This is the main source of technical information The manual should contain most of the answers to your questions Demonstration Videos MEG Array Daughter Card header insertion and removal video Dini Group Web Site The web page will contain the latest user manual application notes FAQ articles and any device errata and manual addenda Please visit
52. igure 1 DNMEG_AD DA Daughter Card DNMEG_AD DA Daughter Card features the following e Single Xilinx Virtex 4 FPGA FF1148 DNMEG AD DA User Manual www dinigroup com 1 INTRODUCTION o XC4VLX40 60 80 100 160 10 11 12 o XC4VSX55 10 11 12 e Analog to Digital Converter ADC o 12 Bit 210 MSPS A D Converter AD9430 210 x2 e Digital to Analog DAC o 16 Bit 160 MSPS Interpolating Dual TxDAC D A Converter e Various clock sources o ADC DAC External Clock Inputs o ADC DAC Clock Oscillators o DDR2 Oscillator x1 o FPGA Clock Synthesizer x1 o Multiple clocks from the Daughter Card Headers e Memory o DDR2 512MB 32MB x 64 Bit 200MHz SODIMM PC2 3200 support up to 2GB o Serial FLASH Memory 4Mbit 2048 pages of 264 bytes per page e Status LED s x8 e Daughter Card Headers x2 LVDS MEG Array 400 pin interface to DN7000K10xxx DN8000K10xxx products e Onboard distributed Power Supplies e Full support for embedded Logic Analyzers o ChipScope from Xilinx o Identify from Synplicity o Mictor Interface 38 Pin DNMEG AD DA User Manual www dinigroup com 2 INTRODUCTION e RS232 Port MicroBlaze e FPGA Configuration via Xilinx Platform Cable USB e Stand Alone operation requires an external 5V 12V power supply ATX 3 Package Contents Before using the kit or installing the software be sure to check the contents of the kit and inspect the board to verify that you received all of t
53. in 10 0MHz to 945MHz from Silicon Laboratories part number 531FB210M000BG factory default 210 MHz 42 5V Q I 42 5V 5 VCG OSC ADC BLM18AG102SN1 100mA OSC ADCp OSC ADCn 531FB210M000BG Figure 5 ADC Oscillator Circuit 4 2 2 External ADC Clock Circuit The external clock input J7 is AC coupled C204 and biased by R130 and R131 refer to Figure 6 J7 is an Amphenol SMA tight angle PCB mounted jack P N 901 144 8RFX with an impedance rating of 50Q J7 2 5 1 3 4 901 144 8RFX Figure 6 External ADC Clock Circuit External ADC Clock Interface Levels The external ADC clock input must conform to the interface levels as specified in the in the datasheet the Diferential to HSTL Fanout Buffer 1585214 U11 see Table 4 below The maximum input clock frequency is limited by the ADC to 210MHz DNMEG_AD DA User Manual www dinigroup com 20 HARDWARE DESCRIPTION Table 4 External ADC Clock Interface Levels Fanout Buffer ICS85214 Symbol Min Max Vin 2 0 3 6 Vy 0 3 1 3 4 2 3 Connection between FPGA and ADC Clock Buffer There is no direct connection between the ADC input clock and the FPGA U15 The ADC provides a source synchronous clock with the LVDS data and this clock should be used for synchronization refer to Table 5 The FPGA U15 also configures the ADC Multiplexers U9 U10 Table 5 Connection between FPGA and ADC Clock Buffer Signal Name ADC Pin
54. lists detailed instructions for programming the Xilinx Virtex 4 FPGA using the Xilinx ISE Version 9 1 031 tools Ensure the Xilinx Platform Cable USB is connected to the JTAG header J13 on the DNMEG_AD DA Daughter Card Power the DNMEG_AD DA daughter card and verify that the Power LEDs DS12 DS11 DS14 DS13 are ON Note This User Manual will not be updated for every revision of the Xilinx tools so please be aware of minor differences 1 Open iMPACT and create a new default project Select Configure devices using Boundary Scan JTAG from the iMPACT welcome menu DNMEG AD DA User Manual www dinigroup com 7 GETTING STARTED iMPACT Welcome to iMPACT Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain v Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File Configure devices using Slave Serial mode 2 iMPACT will identify the devices in the JT AG chain Specify the file location for the PROM programming file based on the type of FPGA populated e g XC4VLX40 CUST_CD DN_BITFILES DNMEG_AD DA MainRef LX40 and open the PROM file fprom_xcf32 mcs Note The FPGA will be high lighted in the JTAG chain select Bypass since we intend to configure the FPGA with the PROM 3 Right click on the XCF32P device and select Program Click OK to
55. mA OSC DACn 530FB160M000BG Figure 7 DAC Oscillator Circuit 4 3 2 External DAC Clock Circuit The external clock input J9 is AC coupled C206 and biased by R137 and R138 refer to Figure 8 J7 is an Amphenol SMA tight angle PCB mounted jack P N 901 144 8RFX with an impedance rating of 50Q 3 3V R137 J9 100 2 5 EXT DAC CLK iO C OK A C206 O uF 4 cEXT DAC CLK 3 74 5 1 901 144 8RFX R159 R138 49 9 100 Figure 8 External DAC Clock Circuit External DAC Clock Interface Levels The external DAC clock input must conform to the interface levels as specified in the in the datasheet the Diferential to HSTL Fanout Buffer 1585214 U13 see Table 6 below The maximum input clock frequency is limited by the DAC to 160MHz Table 6 External DAC Clock Interface Levels Fanout Buffer ICS85214 Symbol Min Max Vin 2 0 3 6 Vy 0 3 1 3 DNMEG_AD DA User Manual www dinigroup com 22 HARDWARE DESCRIPTION 4 3 3 Connection between FPGA and DAC Clock Buffer The connection between the FPGA and the DAC Clock Buffer U13 is shown in Table 7 Please note that the DAC clock will be delayed by the propagation delays through the Multiplexers U12 U24 Table 7 Connection between FPGA and DAC Clock Buffer Signal Name DAC Clock Buffer Pin FPGA Pin CLK1_EXT_DAC1p U13 3 U15 AB17 CLK1_EXT_DACin U13 4 U15 AB16 4 4 DDR2 Clocking The DDR2 SDRAM module J14 use
56. o Daughter Card Header IO Connections 11 5 I ang Resets 11 6 Insertion Removal of Daughter Card essei tegit eti ata u aaa esee da ERES deletae o SE Rete ha saa Ra G asua 11 7 MEG Array Specifications 12 MICTOR HEADER intet IR e EINER HERR Uh n EO nan ERREUR ee REPRE UG E EAERERL I MINE EFT RHEIN ore ints IS PM Mictor Header CIC0IEu aaa M 12 2 FPGA to Mictor Connections 13 MECHANICAL E 13 1 BH KI 68 APPENDIX 69 14 APPENDIX AS UCE FICE D M 69 List of Figures JPigure D INNIEG AD DA Datighter Caid y ee tr RH RR UE Era entente entere ene ture 1 Figure 2 DNMEG_AD DA Daughter Card Block Diagram Figure 3 JTAG Header Figure 4 Clocking Block Diagram Figure 5 ADC Oscillator Circuit Figure 6 External ADC Clock Circuit Figure 7 DAC Oscillator Circuit Figure 8 External DAC Clock Circuit Figure 9 DDR2 Differential Oscillator Circuit Figure 10 DDR2 Write PLL Circuit Figure 11 Clock Synthesizer Circuit Figure 12 Daughter Card Header Clock Circuit Bottom Header Figure 13 Daughter Card Clock Circuit Top Header Figure 14 Differential Input Amplifier Figure 15 Single Ended Input Figure 16 Differential Input Figure 17 FFT of the ADC Output Figure 18 DAC Channel 1 Single Ended Output
57. ociated pin assignment on the FPGA U15 Table 21 DONE LED Signal Name FPGA LED FPGA_DONE U15 u15 DS9 8 3 Power Supply Status LED s LED s are provided to indicate the presence of various power supplies The power monitor U17 monitors the 3 3V 2 5V 1 8V and VCCINT 1 2V voltage levels and signals an under voltage condition by pulling SYS_RSTn signal low The status of this signal is indicated by DS10 Table 22 describes the power supply status LED s and their associated voltage source Table 22 Power Supply Status LED s Signal Name Power Supply VCCINT 1 2V PSU1 1 8V PSU3 2 5V PSU2 DNMEG_AD DA User Manual www dinigroup com 48 HARDWARE DESCRIPTION Signal Name Power Supply 3 3V PSU4 5V ATX 12V ATX Signal Name SYS RSIn 9 RS232 Port An RS232 serial port P1 is provided for low speed communication with the application on the FPGA U15 The RS 232 standatd specifies output voltage levels between 5V to 15V for logical 1 and 5V to 15V for logical 0 Input must be compatible with voltages in the range of 3V to 15V for logical 1 and 3V to 15V for logical 0 This ensures data bits are read correctly even at maximum cable lengths between DTE and DCE specified as 50 feet Figure 24 shows the implementation of the serial port on the DNMEG AD DA Daughter Card FPGA TXD FPGA_RXD 43 3V Oo FPGA RXD L FPGA R
58. ode 5 1 2 Differential Input Mode 5 1 3 GEEAE an aTe D ER S E E E EOR T BY E O E eg 5 1 4 Common Mode Adjustment VEL JU M M 31 5 2 1 gh S H M 31 5 2 2 An4los Inputs P a ER y a is ps aa fal enh eka tad Aan 31 5 2 3 Voltage Reference 5 2 4 Data Format 5 2 5 Data Outputs 5 2 6 ADC Power Dissipation asrini r teret eek ERIS ETE COGERET RE TAURUM Eaa EEA RV RAYS EIC X SUN aee qawawaq 5 2 7 ADC Characterizatio MO 5 2 8 ADC connections to the FPGA e 6 DIGITAL TO ANALOG CONVERTER DAC eee teint eene ette to nane ee eie pedea ke e an eye ee eet oan exe ee uen dee eei eee eee dia 34 6 1 CLOCK SS OUr Ce es sea T 34 62 Data Input zi 63 DAC Differential Outputs ioanen rr RO ROTETE A TEE RO E AEE EEE a TEE pO ride ett 35 6 4 Voltage Referenee upaya sr e iasi RAE EOE EAEEREN yaa EREVENT 65 Full Scale Current Adjust 6 6 Serial Port Interface SPI 6 7 DAC connections to FPGA 7 MEMORY Less ss encased ancaianceucoatiaessea resnswoasdaneaiasesncasatidokavaseanesatidndanssesacasatidek aaa Qs aussi aaa EEEIEE eia RENEE TeRi y ERES Nd AS E 7 1 1 Connections between FPGA and Serial FLASH PANI DII UTERE u musu sucess naqa ma EELE EC eave uss EET EENEN EENE OREST EEE AE 7 2 1 IB ASI
59. oup com 23 HARDWARE DESCRIPTION Table 8 Connections between FPGA and the DDR2 Differential Oscillator Signal Name DDR2 Diff OSC FPGA Pin DDR2_OSC_OUTp U4 4 U15 AN20 DDR2_OSC_OUTn U4 5 U15 AP20 Signal Name FPGA Pin DDR2 Clock Buffer Pin CLK_DDR2P U15 AM20 U23 4 CLK_DDR2N U15 AL19 U23 5 4 4 3 DDR2 Differential Clock Buffer The CDCU877 U23 is a high performance low jitter low skew zero delay buffer that distributes a differential clock input pair CK CK to ten differential pairs of clock outputs Yn Yn and to one differential pair of feedback clock outputs FBOUT FBOUT The feedback clock CLK_DDR2_FBp n is routed from the Clock Buffer U23 to a clock input on the FPGA U15 and is matched length to the data byte group VIT 900mV E i R235 49 9 CLK DDR2p C169 otuF J U23 Yo 38 DDR2 CKpO LK DDR2 CLK DDR2 CKn0 CLK DDR2n C168 O 1UE T ya r37 CKn y 39 DDR2 Ckp1 EIN Yl 40 DDR2 CKT FBIN yla CLK_DDR2_FBp 2 CLR DDR2 FBn DX ee Hia y 13 x 1 8V 1 8V R231 R232 x Las FB21 41 8V R54 1 5 VQCA DDR2 FIL1VB C163 BLM18AG102SN1 0152 100mA 0 1uF C161 33 L33 y L 2200pF 32 EE y s HS x Hx se 24 CLK DDR2 FBOUTp 25 CLK DDR2 FBOUTn 20 CERAMIC Place 2200pF capacitor close to the PLL AVDD pin Figure 10
60. ovements including lower power consumption higher data bandwidth enhanced signal quality and on die termination schemes The DDR2 SDRAM device uses the SSTL 1 8V I O standard and uses DDR architecture to achieve high speed operation The memory operates using a differential clock provided by the controller in the DDR2 Differential Clock Buffer U23 Commands are registered at every positive edge of the clock A bidirectional data strobe DOS is transmitted along with the data for use in data capture at the receiver DOS is transmitted by the DDR2 SDRAM device during reads and the controller transmits DQS during writes DOS is edge aligned with data for reads and is center aligned with data for writes Read and write accesses to the DDR2 SDRAM device ate burst oriented accesses begin with the registration of an active command and are then followed by a Read or Write command The address bits registered with the active command are used to select the bank and row to be accessed The address bits registered with the Read or Write command are used to select the bank and the starting column location for the burst access The DNMEG AD DA supports 64 Bit 200MHz SDRAM module PC2 3200 and allows addressing up to 2GB The interface is connected to IO Bank 7 and 11 of the Virtex 4 FPGA U15 and uses a 1 8V switching power supply for Vppo and Veco Vrr and Vper ate powered from a separate Linear Power Supply set at 0 9V DDR2 SDRAM modules are available from
61. p99 12 DC_RSTn lt gt 74380 101LF R35 100R U26 7 1 CLK DC B 2p 1 68 SLK Q0 5 CR DCE 2n CLK Q0 3 _ CLK DO FPGA Qi CLK_DC_FPGAp pgi4 at EK BE FP GAN CLK_DC_FPGAn pgi4 3 3V Slap voo 4 ICS85411 808 0349 Lot Figure 12 Daughter Card Header Clock Circuit Bottom Heade 4 6 2 Daughter Card Clock Circuit Top Header P2 On the top daughter card header P2 differential clock signals CLK_DC_T_2p n is bidirectional and connected to the FPGA U15 refer to Figure 13 3 3V 45V 12V o o o 2 F2 gt F8 2 F10 7A N BA X 5A P2 1 Pi2VFUSED DC T CLK DC B 0 asa P12V_1 GCAP E CIR DC E n CLK DC B 0p pgi4 P12V 2 GCAN ICLK_DC_B 0n pgi4 PSVFUSED DC T CLK DC B 1 El P5V 1 GCBP ES DCE TIn ICLK_DC_B 1p pgi4 P5V 2 GCBN ee ICLK DC B in pg14 P3 SVFUSED DO T B2 c LK DC T 2j 1 paj P33V 1 GCCP E ICLK_DC_T 2p pg14 G2 P3 3V 2 GCCN a ICLK_DC_T_2n pgi4 A PER PIN P3 3V 3 Ey RST DCn J2 usd RSTn voc Clock Power Reset pg8 12 DC_RSTn lt gt PORS 245 IS i 84520 102LF Liwc enn 7ALVC1G07 gt Figure 13 Daughter Card Clock Circuit Top Header 4 6 3 Connections between the FPGA and the Daughter Card Header Clocks The connections between the FPGA and the Daughter Card Header Clocks are shown in Table 11 Table 11 Connections between FPGA and Daughter Card Header Clocks Signal Nar FPGA s DNMEG_AD DA User Man
62. r channel This mode is not supported on the DNMEG_AD DA board Two Port Data Input Mode With the phase locked loop PLL enabled and the AD9777 in two port mode the speed of CLKIN is inherently that of the input data rate In two port mode Pin 8 DATACLK PLL_ LOCK can be programmed Control Register 01h Bit 0 to function as either a lock indicator for the internal PLL or as a clock running at the input data rate When Pin 8 is used as a clock output DATACLK its frequency is equal to that of CLKIN Data at the input ports is latched into the AD9777 on the rising edge of the CLKIN With the PLL disabled a clock at the DAC output rate must be applied to CLKIN Internal clock dividers in the AD9777 synthesize the DATACLK signal at Pin 8 DATACLK PLL LOCK which runs at the input data rate and can be used to synchronize the input data Data is latched into input Port 1 and Port 2 of the AD9777 U8 on the rising edge of DATACLK DATACLK speed is defined as the speed of CLKIN divided by the interpolation rate With zero stuffing enabled this division increases by a factor of 2 Refer to the component datasheet 6 3 DAC Differential Outputs RF transformers T1 T2 are used to perform a differential to single ended signal conversion A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer s pass band An RF transformer such as the Mini Cir
63. rammable logic industry Virtex 4 FPGAs contain three families platforms LX FX and SX Choice and feature combinations are offered for all complex applications A wide array of hard IP core blocks completes the system solution These cotes include the PowerPC processors with a new APU interface Tri mode Ethernet MACs 622 Mb s to 6 5 Gb s serial transceivers dedicated DSP slices high speed clock management circuitry and source synchronous interface blocks The basic Virtex 4 building blocks are an enhancement of those found in the popular Virtex based product families Virtex Virtex E Virtex IL Virtex II Pro and Virtex II Pro X allowing upward compatibility of existing designs Virtex 4 devices ate produced on a state of the art 90 nm copper process using 300 mm 12 inch wafer technology Combining a wide variety of flexible features the Virtex 4 family enhances programmable logic design capabilities and is a powerful alternative to ASIC technology DNMEG AD DA User Manual www dinigroup com 13 HARDWARE DESCRIPTION 2 1 Summary of Virtex 4 Family Features e Three Families LX SX FX o o Virtex 4 LX High performance logic applications solution Virtex 4 SX High performance solution for digital signal processing DSP applications Virtex 4 FX High performance full featured solution for embedded platform applications e Xesium Clock Technology O O O Digital clock manager DCM blocks Additional phase m
64. s DpR2 5 8 85 EG2121 Ss d CLK DC B 1pin Ze lt gt az CLK SYNTHOp g LES Qlock OUCBG Tap Synthesizer lt mE gt CLK_SYNTHipin It LQFP32 Figure 4 Clocking Block Diagram The clocking structures for the DNMEG_AD DA include the following features e ADC DAC External Clock Inputs J7 J9 e ADC DAC Clock Oscillators X1 X2 e DDR2 Oscillator U16 e FPGA Clock Synthesizer U21 e Multiple clocks from the Daughter Card Headers P2 P3 The connections between the FPGA and various clocking resources are documented in Table 3 covering the clocking inputs and outputs respectively Table 3 Clocking to from the FPGA DNMEG_AD DA User Manual www dinigroup com 18 HARDWARE DESCRIPTION Signal Name Clock Buffer Pin FPGA Pin CLK_DAC_FPGAp U24 3 U15 AG18 CLK_DAC_FPGAn U24 4 U15 AG17 Signal Name FPGA Pin Clock Buffer Pin CLK FPGA DACp U15 AF5 U12 1 CLK FPGA DACn U15 AF4 U12 2 Signal Name FPGA Pin Clock Buffer Pin CLK FPGA ADCOp U15 C2 U9 1 CLK FPGA ADCOn U15 D2 U9 2 CLK FPGA ADC1p U15 P7 U10 1 CLK FPGA ADC1n U15 P6 U10 2 Signal Name Clock Buffer Pin FPGA Pin CLK DC FPGAp U26 3 U15 AH19 CLK DC FPGAn U26 4 U15 AH18 Signal Name FPGA Pin DDR2 Clock Buffer Pin CLK DDR2p U15 AM20 U23 4 CLK DDR2n U
65. s a serial port interface SPI that provides a high level of programmability thus allowing for enhanced system level options These options include selectable 2x 4x 8x interpola tion filters fS 2 fS 4 or fS 8 digital quadrature modulation with image rejection a direct IF mode programmable channel gain and offset control programmable internal clock divider straight binary or twos complement data interface and a single port or dual port data interface Numerous clocking options are available to clock the DAC Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range Please refer to the schematic and individual component datasheets 6 1 Clock Source Numerous clocking options are available please refer to par DAC Clocking par 4 3 DNMEG_AD DA User Manual www dinigroup com 34 HARDWARE DESCRIPTION 6 2 Data Input The digital data input ports can be configured as two independent ports or as a single one port mode port One Port Mode In one port mode P2B14 and P2B15 from input data port two are redefined as IQSEL and ONEPORTCLK respectively The input data in one port mode is steered to one of the two inter nal data channels based on the logic level of IQSEL A clock signal ONEPORTCLK is generated by the AD9777 U8 in this mode for the purpose of data synchronization ONEPORTCLK runs at the input interleaved data rate which is 2X the data rate at the internal input to eithe
66. s the SSTL 1 8V I O standard and uses DDR architecture to achieve high speed operation The memory operates using a differential clock provided by the controller Commands are registered at every positive edge of the clock A bidirectional data strobe DQS is transmitted along with the data for use in data capture at the receiver DQS is transmitted by the DDR2 SDRAM device during reads and the controller transmits DOS during writes DOS is edge aligned with data for reads and is center aligned with data for writes Refer to XAPP702 DDR2 Controller Using Virte4 Devices for more information regarding the data path architecture 4 4 4 DDR2 Differential Oscillator Circuit The differential oscillator U16 is powered from 2 5V and provides a differential clock to the FPGA U15 see Figure 9 The Epson EG2102CA Series of low jitter 0 2ps LVDS oscillators is recommended for this application and is available in 53 125Hz to 700MHz They are available from Nu Horizons part number EG 2121CA200 0000M LGPN 2 5V M BLM18AG102SN1 100mA C115 1K 0 1uF DDR2 OSC OE 1 DDR2_OSC_OUTn DDR2 OSC OUTp EG 2121CA 53 125MHz to 700MHz 200MHz Factory Default Figure 9 DDR2 Differential Oscillator Circuit 4 4 2 Connections between FPGA and the DDR2 Differential Oscillator The connections between the FPGA the Differential Oscillator and the DDR2 Clock Buffer ate shown in Table 8 DNMEG AD DA User Manual www dinigr
67. tandard These elements include the Test Access Port TAP the TAP controller the instruction register the instruction decoder the boundary scan register and the bypass register The Virtex 4 family also supports a 32 bit identification register and a configuration register in full compliance with the DNMEG_AD DA User Manual www dinigroup com 16 HARDWARE DESCRIPTION standard A device operating in JT AG mode uses four required pins TDI TDO TMS and TCK The four JTAG input pins TDI TMS TCK and TRST have weak internal pull up resistors Do not begin JTAG configuration until all other configuration is complete 3 2 1 In System Programming PROM JTAG Header In System Programming is possible by daisy chaining the PROM and the FPGA Figure 3 shows the pin assignments for the JTAG programming header 43 3V o R270 1K JTAG_PROM_TMS JIAG JIAG PROM TDI Figure 3 JTAG Header 3 2 2 JTAG connections to the PROM FPGA Table 2 shows the connection between the JTAG connector and the Configuration PROM Vittex 4 FPGA Table 2 JTAG connections to the PROM FPGA Signal Name PROM Pin Name Connector JTAG_PROM_TMS U27 21 TMS J13 4 JTAG_PROM_TCK U27 20 TCHY J13 6 JTAG_PROM_TDO U27 22 TDO J13 8 JTAG_PROM_TDI U27 19 TDD J13 10 Signal Name FPGA Pin Name Connector JTAG_PROM_TMS U15 V13 TMS J13 4 JTAG_PROM_TCK U15 V14 TCK J13 6 JITAG_PROM_TDO U15 V18 TDO J13
68. ts The analog input is AC Coupled and driven by AD8351 a wideband differential amplifier U2 The analog signal can be low pass filtered by R16 C32 and R15 C31 5 2 3 Voltage Reference The SENSE input on the ADC selects the voltage reference The AD9430 210 U6 has been configured to use the internal 1 23 V voltage reference by floating the SENSE input 5 2 4 Data Format Data format select input S1 sets the output data format of the ADC Driving ADCO_DFRMT_SEL low sets the output format to be offset binary while driving ADCO_DFRMT_SEL high sets the output to twos complement 5 2 5 Data Outputs The ADC U6 LVDS digital outputs ADCO_Dp n 0 11 are routed directly to the FPGA U15 IO bank 10 Each output trace pair should be terminated differentially at the FPGA using LVDS_25_DCI 5 2 6 ADC Power Dissipation At 210MHz the datasheet indicates a power dissipation of 1 7W maximum The AD9430 has a conductive heat slug that is connected to the GND plane with multiple VIA s Due the lack of PCB board area this results in an operational temperature of approximately 40 C Please use external cooling fans if required 5 2 7 ADC Characterization A Hewlett Packard 8664A Signal Generator was used to generate a 65 MHz sinusoidal signal in order to characterize the ADC circuit The output of the Signal Generator was coupled to the ADC input via a TTE 65MHz Bandpass filter An FFT of the digital data refer to Figure 17 indicate
69. ual www dinigroup com 27 HARDWARE DESCRIPTION Signal Name Header Pin FPGA Pin CLK_DC_B_00 P3 E1 P2 E1 U15 AF18 CLK DC B 0n P3 F1 P2 F1 U15 AE18 CLK DC B 1p P3 E3 P2 E3 U15 AG16 U U U CLK DC B 1n P3 F3 P2 F3 15 AF16 CLK DC T 2p P2 E5 15 AK18 CLK DC T 2n P2 F5 15 AK17 Signal Name Bottom Header Pin Clock Buffer Pin CLK DC B 2P P3 E5 U26 1 CLK DC B 2N P3 F5 U26 2 Signal Name FPGA Pin Clock Buffer Pin CLK DC FPGAp U15 AH19 L3P GC U26 3 CLK DC FPGAn U15 AH18 L3N GO U26 4 5 Analog to Digital Converter ADC The DNMEG AD DA provides dual 12 Bit 210 MSPS independent ADC channels Each channel buffer the input signal and allows for either single ended or differential operation The buffered signal allows the user to adjust the gain and or offset voltage The signal is then fed to the ADC from where the digital output is fed to the FPGA These devices interface to a Virtex 4 FPGA via a dedicated LVDS bus Each ADC is powered from a separate linear power supply and additional filtering is provided for AVCC Numerous clocking options are available to clock the ADC s Since the two ADC channels are identical only Channel 0 component references will be used to describe circuit functions Please refer to the schematic and individual component datasheets Note Three products are available in pin compatible 10 14 and 16 bit vetsions Note Due to a lack of

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