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1 FM07I4A

1. Fig3 57 Delete Bar Dialog Box Fig 3 58 Delete a selected Bar 40 35 30 25 20 H LUO UT eee pee Fig 3 59 To Zoom In left click and drag the mouse point from left to right FMO7I4A PRE ESAS i ARAE Zeroplus Technology Co te When users activate the Zoom to zoom in zoom out the selected area the Tooltip on the right corner of the bottom will display the Time Clock or Address of the selected area When selecting the Zoom function and users are pressing and dragging the left key the information on the right corner of the bottom will be changed and updated with the width of the selected area And the information is displayed on the right corner of the bottom in the way of Tooltip When users loosen the mouse the information will disappear Tooltip Time Frequency Sample xxx time ns unit Address xxx There is no unit with the address o Hand H ESCAPE R Normal 49 The Zeroplus Logic Analyzer User s Manual V3 09 696 7 195 5 694 Address 4 A A _ ep 32973 2B175 23378 18 58 JOCQUUCC UO UUUUU UU UU UU 1 Fig 3 60 To Zoom Out left click and drag the mouse point from right to left ated m sait aigla lt tip aig x im ih 25MH2 SOK e Pa fT berme s E JERNE Ai is 4 E Height k Fes F osm 4 Uh w TIE fe 2 al SPECIE Fig 3 61 To display the Tooltip left click and drag the mouse point from
2. Type the numbers or select the number from the pull down menu of the Count Count 1 z on the Tool Bar or click the pull down menu of the Trigger Count on the Trigger Property dialog box as shown in Fig 4 6 The system will be triggered at the position where the Trigger Count is set as shown in Figs 4 6 4 7 and Fig 4 8 94 FMO7I4A P Re Tee ih BR eS The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 la x Trigger Count Count 1 Tr r hns 3 E 15004 ipr Rate Hh We ZEROPLUS LAP C 32128 S H 00000000001 LaDoci i File Bus Signal Trigger Run Stop Data Tools Window Help Dera BBB g b gt O 2K uE ia 5OMHz v ane ww 50 v ie Page fi A e ely E o allm pes e RI a Be Te eA le o o e Heien a0 Font Size 12 v Scale 8 Display Pos 0 A Pos 15 v A T 15 A B 30 v Total 2048 Display Range 200 200 B Pos 15 v B T 15 Compr Rate No 160 j ii ECOG pe il va TT A m Ra i a OO A a T i A Fig 4 7 Trigger Count Screen Shot 1 We ZEROPLUS LAP C 32128 S H 00000000001 LaDoci File Bus Signal Trigger pars Data Tools Window Help Demla at p peo faq z o Bi SomMHz wv ww 50 Page fi i CANANI alm pes R a BY Be Te BA le orl Height ao Font Siz ie Y Scale 8 Display Pos 0 A Pos 15 v A T 15 v A B 30 v Total 2048 Display Range 200 200 E Pos 15 v Ce T 15
3. a File Bus Signal Trigger Run Stop Data Tools Wii D amp S at FF EB gt b gt i Time Display i le Re ii S i e Frequency Display Display Pos 0 Display Range 25 Fig 3 148 Display Bar Detail Waveform Display Mode There are 3 display modes to determine the method of capturing data from sampling Sampling Site Display Time Display and Frequency Display 79 FMO7I4A REA AG i ARRES The Zeroplus Logic Analyzer Zeroplus Techneblogy Co Ltd User s Manual V3 09 3 4 2 Modify Ruler Mode Use the menu to modify the Ruler Mode Go to Tools and click Customize See Fig 3 142 x Common Setup Toolbars shortcut Key Auto Save Waveform Display Mode f Sampling Site Display Time Display Frequency Display Wavetormn Setting Waveform Height 40 Ruler Mode Regular Ruler Fort Size 12 f Timer Sampling Site Ruler Fig 3 149 Ruler Mode Regular Ruler Fig 3 150 Scales in Regular Ruler Time Sampling Site Ruler a aE Whe H Sis 10s B Ahs 2olhus hs 10s I I l l I st l l I l l Ist l l I I l l L I I l l i l l fl l l I I l l I st l l I Fig 3 151 Scales in Time Sampling Site Ruler Ruler Mode There are two styles of Ruler Regular Ruler Time Sampling Site Ruler Regular Ruler Presented in increments of 5 Time Sampling Site Ruler default Presented in increments of 50us 80
4. A Pos 41 E Pos 25 ULUUUUY UTU L JLU L n Fig 3 64 Result from Normal to Zoom In 13 AE R A Pos 1025 E Pos 1015 i 475 d dea Fig 3 65 Result from Normal to Zoom Out ii ama o a z Sm r Ped Die beii Bett pel Tee ir A 220 SSR Fs Bees fe Ss Slee ja amp hee i ea ft eee e D E ninr a E E r E Hu tr iom ie aT I Pat Stee fa Shas Bimi Fea paii ivite ees eS eee a 1 15 ba Ma Pas Fig 3 66 Show all Data FMO7I4A PRR GRAE The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 w Previous Zoom Ctrlti Return to the last zoom Binary Decimal v Hexadecimal Data Format d ASCII Fig3 67 Data Format Show numerical information in Binary Decimal Hexadecimal or ASCII format Add Bar ALtt A Delete Bar ALttE Bar be Zoom E ey Hand H p Hormal ESCAPE T Zoom In Fa Lf waveform Mode H _M Zoom Out F Show all Data F10 ey Previous Soom Ctrltz Data Format t Horra fnr nde nmm favetorm Mode Reverse List Data Mode iw Square Waveform Sawtooth Waveform Fig 3 68 Square Waveform Add Bar AlttA Delete Bar ALttB Bar mu Reverse Soke UL g Hand H e A R Normal ESCAPE v oguare Waveform n Zoom In m Zoom Out F8 Sawtooth Waveform am Om Show all Data F10 x gt Previous Zoom CtritZ Data Format b Waveform Mode b J Reverse List
5. FMM oe amp i535 x amp b g AB AS SATA amp Been BO B0 amp g Bi Bl EE 52 52 ion iW BS amp lon BA B4 amp ee g B5 55 ELE g BB B5 oe g BTT x LS g co co x amp gc ci x 8 C2 C2 oe amp ae ia G x amp 4 4 rii AIRE gt Ready End DEMO Le Fig 4 69 Waveform Analysis 124 FMO7I4A i PHRSR E The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 4 5 2 2 Protocol Analyzer I2C Timing Analysis x Configuration Timing Packet Data Format Register Waveform Image A gt lt Teu pat t BU sTO ra J Ji E r Tho sta 3 nE r Tuo pat Unnati i Time Format Settings Jw tH STA o 00 to jt 75 us S DAT f l4 to o co us tH DAT pia to p00 us SU STO foo to am He Cancel Default Help Fig 4 70 Protocol Analyzer 12C Timing Setup Waveform Image Describe the position of the setting time Time Format Settings When the Time Settings are activated the set time will become the condition to judge the decoding For example when you want to decode START you should judge whether the conditions of START is satisfied firstly and then judge whether the set time of tHD STA is suitable for the factual waveform if the two conditions are satisfied the START could be decoded the theory of START decoding is the same to that of other packet segments 125 FMO7I4A
6. When users input the Address in this Edit Box and click the Find icon it will go to the STEP 3 Display the Memory Analyzer function in the waveform window Tip The Packet is read the Address is 0X00A6 the Data are 0X0150 OX01FA in sequence 183 We ZEROPLUS LAP C 32128 S H 000000 0000 DEMO alc laj x i File Bus Signal Trigger Run fStop Data Tools Window Help 8 x E E S i i Be gk GT gt Db 128K v site 8 141 200MHz v au 10 ie ps Page fi Count fi aloma m IEA RRP ey iid 210 070411 HIER Ax Bo Te Bi FS ES 4s Height 28 v Trigger Delay A r gt i gt gt Reset Refresh Merge Import Export Option Display Alteration Alteration Bal Scale 210 070416ns Display Pos 391 473908us A Pos 60 49us v A T 60 49us v B 150ns v Total 655 36us Display Range 386 22214Tus 396 725668us60 34us v B T 60 34us v ee No Z a Bus Signal Filter EEA 387 272499us 38 388 322851us 389 373204us 390 423556us 391 473908us 392 52426us_ 393 57461 2us 394 624964us 395 675316us 396 r Se Bo PTA HPTA H OHS A ae g HENTI oe Ea HENTO g b BW Ag oe Z msi x yf COU ff oe g D2 Si HHIL a OATH Si g B0 B 2S rre f Bus1 HPT Address Write data Read data a SS C Unused 0X0000 0X009F oxooao
7. f High So enable level Low f Low Virtual 55 Condition Idling Time 5 us sf Dont care data bit Min Sus Max 1 327 6755 lt a Cancel Default Fig 4 85 Virtual SS Condition Setting 4 Type the idling time of the SCK signal on the tested SPI circuit The idling time is defined as the idling time as shown in Fig 4 86 begin ened T N N VN NUII a A i va r ddling fire hes lime SCK CPOL D ll Fig 4 86 Idling Time 5 Click on the Don t care data bit function The system will restart and count from the beginning of the data bits when the condition of the idling time setting is qualified 136 FMO7I4A 137 CD FRR EA i PR eS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 6 Click off the Don t care data bit function the system will decode the data stream until the bits of the data are received completely when the condition of the idling time setting is qualified 7 Press OK to confirm the setup of SPI Custom Setting and return to the dialog box of the SPI Setting Tip Press Default to reset the current setup Step5 Click OK to exit the dialog box of Protocol Analyzer SPI Setup Step6 Click Run to acquire the SPI signal from the tested SPI circuit Refer to the Fig 4 87 Tip Click icon to view all the data and then select the waveform analysis tools to analyze the waveforms gt ZEROPLUS LAP C 3
8. FMO7I4A 81 REA AG ih Bik eB The Zeroplus Logic Analyzer Zeroplus Techneblogy Co Ltd User s Manual V3 09 3 4 3 Modify Waveform Height amp Correlated Setting To modify Waveform Height click Tools gt Customize Waveform Height Set the height of waveform 18 100 in chosen items at toolbar that will show the amplitude of the waveform Ruler Mode Regular Ruler Wayetornmn Setting Waveform Height 40 Time Sampling Site Ruler Font Size Correlated Setting M Auto Close Open Close Compression Warning Show Gridline M Show Tooltip Open Close Double Warning Data Process What do pou want to show when vou press the Stop during the running Keep the Present Data Read the Captured Data Fig 3 152 Waveform Height Waveform Height 18 Waveform Height 40 Bua Si geal Trigger Fig 3 153 1 ee Fig 3 153 Examples of Waveform Height FMO7I4A PREM AG Blk ee The Zeroplus Logic Analyzer Zeroplus Techneblogy Co Ltd User s Manual V3 09 Correlated Setting Select Auto Close in the following figure Ruler Mode Regular Ruler Waveform Setting Waveform Height 40 Times Sampling Site Ruler Font Size Correlated Setting M Auto Close Open Close Compression Warning Show Gridline M Show Tooltip Open Close Double Warming Data Process What do you want to show when you press the Stop during the running C Keep the Fresent
9. Set the trigger condition as Rising Edge See Section 4 1 for detailed instructions Set the trigger condition as Falling Edge See Section 4 1 for detailed instructions Set the trigger condition as Either Edge See Section 4 1 for detailed instructions Reset Reset the trigger condition prscsccvegeocevecsesesccescnssscssesssveeccsecesee Trigger Level Port A Port B mm I Port C Port D TTL bd fi 5 Vv fis Vv fis w 5 w Trigger Count o a Min 1 Max 65535 See Section 4 1 for detailed instructions reach before the trigger circuit initiates a sweep Cancel Default Help Fig 3 33 Set Trigger Content Trigger Level The voltage level that a trigger source signal must There are 4 ports available each port has the ability to assign different voltages to meet the users requirements Use the pull down menu to choose between TTL default TTL CMOS 5V CMOS 3 3V ECL and User Defined choose the value of the Trigger Level 6 0V to 6 0 V 50 Eo 1 isi gt p Count 3 Fig 3 34 Trigger Position Trigger Page Trigger Count 1 Represents the Trigger Position of a memory page 2 Represents the Trigger Page 3 Represents the Trigger Count Trigger Property Trigger Content Trigger Delay Trigger Range gesoecessessoeessossooeeesecseseseseg CE A e Trigger Page 1 v M
10. Synchronous Channel AQ hal Synchronous Trigger Condition Rising Edge Cancel Help Fig 3 87 Multi stacked Logic Analyzer Settings Dialog Box See Section 4 12 for detailed instructions Analog Waveform The function of Analog Waveform means that the Display Mode of Bus Data is not the Pure Data Mode while it displays data change with the curve which looks like a waveform which in fact is a curve to describe the data change So it is called the Analog Waveform The Analog Waveform can be divided into two kinds namely Single Analog Display and Mixed Analog Display see the figures as below o ZEROTLUS LAP C 32128 S H G00000 0000 Laec 5 x m Tile Bys Sigal Triceer Bba Stop Dete Tools Wiadew Help 4 xj OG S RAK we b a fen sume mm 5096 e Pase I la GR BRS yh oS M fux See vee be 0 2i Heig Trigger Delay Font Size fiz fSalet Display Pos 0 A Pos 15 A T I5 A 3B Total 2045 Display Kenge 25 25 Bfos t5 BeT 15 Compr Bate Bo Dus Siqnal Trigger Tilto le 20 n 10 3 s 10 H 20 s E O ALARA Fig 3 88 Single Analog Display FMO7I4A User s Manual V3 09 The Zeroplus Logic Analyzer i P eroplus Technology Co Ltd O PRE RLSAD IRAE a a aa i EER ZE a Lie a al p z Fig 3 89 Mixed Analog Display FMO7I4A 60 PREHRA RAE Zeroplus Technology Co te 7 Window Menu Bar Windows Menu Ite
11. Anyone who uses this computer fall users only for me xxx Installshield lt Back Cancel The Zeroplus Logic Analyzer User s Manual V3 09 pes a az You must restart your system For the configuration changes made to LAP C 16128 Standard_ 3 08 to take effect Click Yes to restart now or Mo iF you plan to restart later ji LAP C 16128 Standard 3 08 InstallShield Wizard Ready to Install the Program The wizard is ready to begin installation Click Install to begin the installation TF you want to review or change any of your installation settings click Back Click Cancel to exit the wizard Installshield ji LAP C 16128 Standard 3 08 InstallShield Wizard Setup Type Choose the setup type that best suits your needs Please select a setup type All program features will be installed Requires the most disk space C Custom Choose which program features you want installed and where they will be installed Recommended for advanced users Installshield lt Back Cancel FMO7I4A A RARER ARZE Zeroplus Technology Co te 2 2 Hardware Installation The Zeroplus Logic Analyzer User s Manual V3 09 Hardware installation simply involves in connecting the Logic Analyzer to your computer with the included USB Cable as shown in Figures 2 4 and 2 5 Fig 2 2 18 1 Plug the fixed end of the cables into the LA Fig 2 1 2 Plug
12. CT d o S o y y o oxoiFA d A unused 0X0080 OX013F A BCT BC a 0x0148 xO1FO 0X OxO xO xoogs 0x0142 0X 0x0 XO1EA 0x013 OXO1E8 xO090 0x0088 Linseed Ny N1aNneNyn1 FE a 4 d Ready End DEMO Fig4 169 Memory Analyzer Display FMO7I4A O PRE RANA SIRO Zeroplus Technology Co H The Zeroplus Logic Analyzer User s Manual V3 09 Multi stacked Logic Analyzer Settings The function of the Multi stacked Logic Analyzer Settings is mainly for connecting the hardware of many Logic Analyzers which are the same type and then use the software to stack the Logic Analyzers which are working independently It can improve the functions of the Logic Analyzer which are mainly manifested in two aspects expanding the RAM Size and adding the number of the test channels Tip 1 The max number of the Multi stacked Logic Analyzers is four The RAM Size of the four Logic Analyzers can reach to 128K 4 and the test channels of the four Logic Analyzers can reach to 32 4 2 The function of the Multi stacked Logic Analyzer Settings is available for the LAP C 32128 LAP C 321000 and LAP C 322000 Modules and it is not available for the LAP C 16032 LAP C 16064 LAP C 16128 and LAP C 162000 Modules 4 12 1 Basic Software Setup of Multi stacked Logic Analyzer Settings STEP 1 Click Tools on the Menu Bar then select E to activate the function of Multi stacked Logic Analyzer Settings Customi
13. Conclusion The demonstrations in this User Manual will enhance users understanding of our products in future issues even though the manual ends here We thank you for choosing the Logic Analyzer Please contact us if you find anything that could be done better either in software or hardware We appreciate your feedback 204 FMO7I4A
14. this function It improves the efficiency of Knowing the conditions 4 11 1 Basic Software Setup of Memory Analyzer STEP 1 Click Tools on the Menu Bar then select am to activate the Memory Analyzer function Customize Show Time of Waveform Color Setting BUG Bus Property a9 Refresh Protocol Analyzer m Memory Analyzer Multi stacked Logic Analyzer Settings Analog Waveform Fig4 163 Memory Analyzer Interface STEP 2 Open the Memory Analyzer dialog box j Es gt gt gt Reset Refresh Merge Import Export Option Display Alteration Bus1 HPT Address write data Read data a Actress Wis cy a a a r A Unused 0X0000 0009F PS ES CSUR CN E Wnused 0X00B0 0X013F foxoio fT V Compact Mode fe Poxoiso oT o e o y ooo fm xos PO Sao A E T E E a A a Unused 0X0180 0X01EF g xoro o o o d ooo Unused 0X0200 0XFFFF DE L 2 Fig4 164 Memory Analyzer Dialog Box 1 Compact Mode and Complete Mode Click the Right Key in the memory analyzer dialog box there are two modes for selecting which are the Compact Mode and the Complete Mode See the two different figures 180 FMO7I4A PREP eho ih SIRAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 bx Bemory Analyzer Bie gt gt Reset Refresh Merge Import Export Option Display Alteration Bus1 HPT wri
15. Click f icon or click Trigger Property from the Trigger on the Menu Bar Then Click the Trigger Range the dialog box will appear as shown in Fig4 16 Tip This function is mainly for the range control for the saved files after triggering According to the procedures of the range control users can start the save of data according to the requirement of its time and times to get the standard of data statistic status Trigger Froperty f i x Trigger Content Trigger Delay Trigger Range Range Setting Time Sample r fi minute r Cancel Default Help Fig 4 16 Trigger Range 1 Trigger Range The default is not activated 2 There are Time Sample and Frequency Sample in the part of Range Setting the default is Time Sample The units of Time Sample are second minute hour and day The unit of Frequency Sample is times Users can set the value by themselves in the editor box FMO7I4A i PHRSR E The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Task 3 Bus Trigger and Trigger Mark Setup Step1 Click icon or click Bus Trigger Setup and Trigger Mark from the Trigger on the Menu Bar The menu is shown as Fig 4 17 ye Bus Trigger Setup rie Channel Trigger Setup ge Trigger Property iC Trigger Mark Jy Pulse Width Trigger Module Option if Rising Edge mi Falling Edge Either Edge Reset Fig 4 17 Trigge
16. Fig 3 73 List Data Mode All Data Sampling Changed Dot Compression and Data Changed Dot Compression FMO7I4A ODOODOGOOGOGODODPDOCDO OGOG OGD DOOCOCOOGOGOD D RARERHARAA The Zeroplus Logic Analyzer gt Zeroplus Technology Co Ltd User s Manual V3 09 Customize Fig 3 75 Show Time Height Tool Box 54 FMO7I4A D BRARERHAREA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Menu Bar Tools Menu Item Detail Menu amp Dialog Box Customize Fig 3 76 Customize Dialog box See Section 3 4 for detailed instructions Customize Trigger Content Set MlDisplay Mode Windows ShowT ime Height Trigger Delay Font Size Customize Fig 3 78 Shortcut Key Setting 55 FMO7I4A 56 PRR AG in BPRS aS i eroplus Technology Co Ltd The Zeroplus Logic Analyzer User s Manual V3 09 Customize Fy oema oo ffs Fig 3 79 Auto Save Setting See Section 3 5 for detailed instructions b00 0000 LaDoci Show Time of Waveform BUS Pue P ne SUS us Proyariy vt J Ca L D p 1 7 y hetresh frotocol Analyzer he 2f2l2f2l2hl2f danoi aalala 16 15 16 Fig 3 80 Show Time of Waveform under Sampling Site Display DO000 0000 LaDoci EZ Time of Waveform BUS Phe P T BUG Hug Pegyartg i fy Refresh Protocol Analyzer A PLE LIL ULL L 40ns 40ns 40n
17. Protocol Analyzer Color START CONTROL CRC ERROR END ID DATA OVERLOAD ACK and NACK 161 FMO7I4A fos SRAEHMOBIEAA The Zeroplus Logic Analyzer a Zeroplus Technology Co Ltd User s Manual V3 09 Operating Instructions Turn on the user interface of the Logic Analyzer W ZEROPLUS LAP C 32128 S H 00000000001 LaDoc3 rs nn in a Fig4 130 User Interface Sample the CAN 2 0B signal or open the sampled waveform fe ZEROPLUS LAP C 32128 S H 00000000001 LaDoc3 a fi UUU UUUU UUU LIL UU LIU LIU Fig4 131 CAN 2 0B Waveform 162 FMO7I4A DD RARBG ARE The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Group the signal channels into Bus W ZEROPLUS LAP C 32128 S H 00000000001 LaDoc3 a e r UUU Uuuu Uuuu L UU LIU LIL a re i a a e TCC lt om Rt ommected Fig4 132 Group into Bus Select the Bus Property to set up the Bus Property dialog box E ZEROPLUS LAP C 32128 S H 00000000001 LaDoc3 AAA A AY UUL UUUU UUUU LIL U LULU Ad ys iY i 7T L 5 4 Ee kd a El SERS EA EA Fig4 133 Bus Property 163 FMO7I4A 164 PRE BS AS i ARAE Zeroplus Techneablogy Coa Ltd The Zeroplus Logic Analyzer User s Manual V3 09 Select the decoding function of the protocol analyzer CAN 2 0B and select OK to confirm o File Bus Signal Trigge
18. T is the trigger label which cannot be removed when the waveform or the state is displayed which marks a pod When searching for or obtaining data the A and B labels can be set in any location Using the order of these markings you can return quickly to the desired position to analyze data This can also be a point to measure the interval between A B A T or B T What is a Trigger Gripper A gripper is the gathering point to collect the Logic Analyzer channels When a cable connector is not suitable for the test device a trigger gripper may be an alternative for connection What is a Channel The channel is the collection line of the input signal Each channel is responsible for linking the pin of the measured device Every channel is used to collect signals from the test equipment How can I display acquisition in the waveform captured by external sampling signal Select Waveform Display from the Window list What is an External Trigger An external trigger is a signal outside the Logic Analyzer It is used for the simultaneous test of 2 test tools For example one Logic Analyzer can be started by one signal from another test tool Or when it is triggered it can output one signal to another test tool The Logic Analyzer is often used for triggering an oscilloscope Why does Double Mode not coincide with Filter Delay In order to set out the perfect waveform from the Logic Analyzer and achieve optimal memory efficiency you can use
19. i SRABRRABRAA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 4 5 2 3 Protocol Analyzer I2C Packet Analysis xi Configuration Timing Facket Data Format Register Item Color Item Color Pawa o EY pm eae fv DATA a i DESCRIBE a I ACK a A M REG ADDR a Cancel Default Help Fig4 71 Protocol Analyzer I2C Packet Setup ADDRESS Start bit address or time display READ Read field displayed in packet WRITE Write field displayed in packet A ACK A NACK A ACK field has 2bit in all If it receives successfully it sends back 0 and 1 If it isn t 0 and 1 it displays A NACK DATA List the data field captured signal by Bus in the packet display D ACK D NACK D ACK has 2bit in all lf it receives successfuly it sends back 0 and 1 If it isn t 0 and 1 it displays D NACK DESCRIBE Error description to any field format or data bit It is a Bus Packet List view which includes 4 formats which I2C happens as follows E Refresh Export Synch Parameter Facket Hame TimeStamp ADDRESS WRITE A ACK DATA FEER Packet Name TimeStamp ADDRESS READ 4 ACK DATA D DATA Bo Bown O Packet Name Timestamp ADDRESS WRITE A MACK Describe Packet Mame TimeStamp ADDRESS READ 4 ACK DATA MACK DATA DE DATA DRAGER DATA PEAME Describe Fig4 72 Protocol Analyzer I2C Packet List Packett It is commonl
20. seal ahs ah j fa Ly pim Fig 3 95 Display Hot News Window on the Software Fig 3 96 Running Text Ads Interface Interface Fig 3 97 Navigator Window L a n Sw File figs Li peal kiga ine es mi finim Fr alk CEES ee ee o oa j er ae wt ee eee EE Jatiseeueins Bipi am Mam lar poe fort dim i Pial Belar Pox E Em C E Fei E i Die Tne ME Dag bam A Fag tle alt Slat Ts ee E Bes Ti el Trice Mia sjy a Fat i 7 1a H m Jh h a A A A eee EE Fig 3 98 Navigator Window under the waveform display area FMO7I4A PRE ESAS i BPR Zeroplus Techneblogy Coa Ltd Window users can click the Left Key of the mouse to select the waveform randomly The selected waveform keeps pace with the waveform in the waveform display area The size of the selection frame is in inverse proportion to the Zoom Rate the larger the Zoom Rate is the smaller the size of the selection frame is Users can also click the Right Key of the mouse to select the displayed channel 63 The Zeroplus Logic Analyzer User s Manual V3 09 we i i Me 7 im EH m d a a l cin abb ae rej o iS eee oo JAT J LFE AlE Bia ha a a Femi Sise i Ewi feo Lie be 1 g 8 reel fale len Ee Ob hyo 70 M u Cages b ai s ewe thee it res A PR ed MEEN n PS os DP PME PRY Fig3 99 Blue Frame in the Navigator Window There is a blue frame in the above Navigator Window Users can clic
21. which has 2 bits and the final is a delimiter whose default is 1 If receiving success Ack will send back 0 then the transmitter knows the Receiver has received the data End of Frame 1111111 denotes en Peli Data Frame In the Peli Data frame Data Frame as follows the frame of message is separated into Start of Frame SOB Arbitration Field Control Field Data Field CRC Field Ack Field End of Frame However the parts of Arbitration Field have much more than 18bits and the SRR and IDE are 1 Fig4 125 Peli Data Frame Remote Transmit Request Frame When RTR 1 it denotes Remote Transmit Request Frame at this time DLC3 DLCO are the Data bytes of return data And the frame doesn t have Data Field Fig4 125 Remote Transmit Request Frame 159 FMO7I4A LA FRABRRPARLA The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 Error Frame The Active Error Flag consists of six consecutive Data Field dominant bits Dominant bits violate the law of bit stuffing All bits can produce Error Frame after recognizing bit stuffing wrong the Error Frame called Error Corresponding Error Flag Field includes sequence bits from 6 to 12 which produces by 1 or more nodes Error Frame ends in Error Delimiter field After Error Flag sends out Bus actively to get the right state and the interrupted node tries its best to send abeyant message Error Delimiter Error Delimiter consists of eight recessive
22. 3 52 Pulse Width Find on the Waveform Window Go to the previous edge sweep of the indicated signal Go to the next edge sweep of the indicated signal Go To T A B or Go To More Dia L Dipli Binga 107 Mas 09 tee E Fen iSi E T 2 iim Cinpe Dal Fig 3 53 Go To T Bar T Bar will be displayed in the center of the waveform area FMO7I4A PRE ES AS i BPR Zeroplus Technabogy Co te The Zeroplus Logic Analyzer User s Manual V3 09 k l Select an Analytic Range er Noise Filter zz Bus Width Filter x Data Contrast Tip Press T go to T Bar Press A go to A Bar Press B go to B Bar Add Bar ALttA Bar Add user defined bars 1 Click the above menu item from Data menu or click Add Bar icon from Tool Bar 2 Give a Bar Name define a Bar Color and set a Bar Position 3 Define the Bar Key with the number between 0 and 9 Tip The number shortcut is set in the Add Bar dialog box Every new bar can be filled in one number which is used to find the required bar faster the default number of the new bar is 0 It is noticed that once the number key is set it can t be modified and each new bar can named with the same number that is to say one number can name many bars For example users can set the number 3 as the shortcut key When users press the number 3 key the C Bar will be displayed in the centre position of the screen 47 Fi Find Data Value Ctrl
23. 7 5 Contact Us Contact Us Copyright 1997 2010 ZEROPLUS TECHNOLOGY CO LTD Headquarter Taiwan Chung Ho City Instrument Division Business Department Taiwan Hsinchu City Taiwan Chung Ho City Other Service Departments China Shenzhen China Shanghai ZEROPLUS TECHNOLOGY CO LTD 3F No 121 Jian Ba Rd Chung Ho City Taipei County R O C Tel 886 2 6620 2225 Fax 886 2 6620 2226 ZIP Code 23585 ZEROPLUS TECHNOLOGY CO LTD 2F No 242 1 Nanya St North Dist Hsinchu City 30052 Taiwan R O C Tel 886 3 542 6637 Fax 886 3 542 4917 ZIP Code 30052 E Mail hunter zeroplus com tw ZEROPLUS TECHNOLOGY CO LTD Address 2F NO 123 Jian Ba Rd Chung Ho City Taipei Hsian R O C Tel 886 2 6620 2225 Ext 200 Fax 886 2 6620 2226 ZEROPLUS TECHNOLOGY DONG GUAN CO LTD Room 2821 B2 Section Building 1 Hong Rong Square District 80 Bao an Shenzhen City Guangdong Province China Mainland Tel 86 755 2955 6305 6 Fax 86 755 2955 6306 808 ZIP Code 518102 ZEROPLUS TECHNOLOGY DONG GUAN CO LTD 101 No 172 Alley 377 Chen Hui Road Zhang Jiang Pudong New Area Shanghai City Tel 86 21 50278005 6 Fax 86 21 50278006 ZIP Code 201203 Users can download the newest Software and User Manual ZEROPLUS is the brand of ZEROPLUS TECHNOLOGY CO LTD The other brands and products are the brand or registered trade mark of the individual company or organization
24. 7 Signal Filter and Filter Delay The function of the Signal Filter and Filter Delay allow the system to keep the required waveform and filter out the waveforms that aren t required 4 7 1 Basic Setup of Signal Filter and Filter Delay Software Basic Setup of Signal Filter and Filter Delay Step1 Set up RAM Size Frequency Trigger Level and Trigger Position as described in Section 4 1 Step2 Set up the trigger edge on the signal or the Bus to be triggered Step3 Click icon or click the Signal Filter Setup from the Sampling Setup dialog box and the Signal Filter Setup dialog box will appear Signal Filter Setup x Filter Condition Port gg a Filter Condition lt US LAP C 32128 S H 000000 0000 LaDoc5 bee Filter Condition Bus Signal Trigger Run Stop Data Tools Window Help z rigger Conditio ix 7 gt pb 2k z i fioomHz Port a fi Channels Filter Condition gt lt Group int Clock Source ms Uneroup Asynchronous Clock ie ee Collapse Frequency 100MHz x 4 Filter Delay Setup Seas Bo Synchronous Clock v Activate Filter Delay External Clock Select Filter Delay Mode Select Delay Start Point gt Delay Time Rising Edge Frequency l00KH2 According to Filter Condition Start Edge fi Falling Edge Min 0 001Hz Max 100MHz End Edge Min 1 Note The
25. Activate the Latch Function The picture of the waveform analysis We ZEROPLUS LAP C 321000 S H 000000 0000 LaDoc2 File Bus Signal Trigger RunfStop Data Tools Window Help Dealan 68 ee 2B gt pe fak z o Bi 200MHz 50 v ie S Page fi EE R OR ill 800 ee Ae Be Te ee Ble olla Trigger Delay 1 Font Size 12 v Scale 0 125 Display Pos 0 Pos 15 v Total 2048 Display Range 3 5 B Pos 15 Fig4 64 The Latch Function Displayed on the Waveform Area Illustration The selected channel is AO the analysis mode is Rising Edge it indicates that the data of the AO is read at the Rising Edge See the T Bar in the above figure the data of Bus1 is 0011 120 FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 4 5 2 12C Analysis I2C Introduction The I2C which stands for Inter Integrated Circuits is a serial synchronous half duplex communication protocol The 2C was first proposed by Philips Semiconductor Netherlands This I2C protocol consists of a very simple physical interface which has only two signal channels SDA Serial Data and SCL Serial Clock Most I2C devices consist of an independently sealed I2C chip and this I2C chip has direct connection to both SDA and SCL The data transmission is a byte base 8 bit base for every segment Since many oscilloscopes do not allow engineers to observe timing sequenc
26. Analysis Preface To increase the Protocol Analyzer feature in order to analyze the Protocol Analyzer 1 WIRE transmission protocol data Using LA analysis function the required serial data can be converted and presented in the form of Bus Therefore the software needs to add a dialog box so as to set up a Protocol Analyzer 1 WIRE dialog box 1 WIRE Introduction 1 Brief Introduction Features 1 WIRE is a non synchronic half duplex serial transmission which requires only one OWIO to transmit data The typical 1 WIRE transmission structure is illustrated in Figure 4 95 During the 1 WIRE transmission the OWIO can be used to transmit data and supply power to all devices connected to the 1 WIRE OWIO will link to a 4 7K Ohm Pull High electric resistance which is linked to the power supply 3V 5 5V The transmission speed for 1 WIRE can be divided into two types standard and high speed Every 1 WIRE has a unique 64 bit code for the device to recognize Therefore the maximum number of link devices is 1 8 almost unlimited J oe 5 54 Toast Micro Controller Fig4 95 Applications Applications 1 WIRE is commonly applied to the EEPROM and to certain sensor interfaces 2 Protocol Analyzer Signal Specifications Name of Protocol Analyzer 1 WIRE Required No of Channels Signal Frequency Not fixed around 10K Appropriate Sampling 1MHz Rate e Name of Syn Signals OW O Data Verification Point 90 US after the falling edge s
27. Be Be Te t BA Te OT Te Height fao Trigger Delay 1 Font Size v Scale 62 5 Display Pos 625 A Pos 1008 v T 1008 v A B 30 v Total 2048 2048 Display Range 0 2048 B Pos 1038 gt B T 1038 v Compr Rate No pa Sg hi 625 Ti a 7312 5 i 312 5 625 937 5 1250 1562 5 1875 2187 5 1 E T nee mo Page Start Page End Fig 4 13 Trigger Position 0 Display Pos 0 Display Range 203 A Pos 805 v 1565 B Pos 835 v A T 805 v B T 835 v A B 30 Compr Rate No a 1250 pee 5 625 malg i 312 5 625 937 5 1250 1562 IL k MAAU UUN LT TUT ul 90 _ _ 10 Fig 4 14 Trigger Position 10 FMO7I4A 98 Phe eee ih BR eS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 E ZEROPLUS LAP C 32128 S H 00000000001 LaDoci lol x 9 File Bus Signal Trigger Run Stop Data Tools Window Help l x Deman BW 2 BB gt peo eq ve h 50MH v as om J sr Pae h gt lelolalmmlelr i o alm s eile eB T A e oll Height 40 Trigger Delay 1 __ Font Size fiz Scale 62 5 Display Pos 0 A Pos 424 v A T 424 v A B 30 v Total 2048 2048 Display Range 1432 616 B Pos 394 v B T 3 4 v Compr Rate No Bus Signal Filter Fig 4 15 Trigger Position 70 Step6 Trigger Range Setup
28. Buses that have been hidden Highlight a signal or Bus and click Color to change the color Highlight a signal or Bus and click Rename to rename the Bus or signal FMO7I4A J gt RAERERGBESA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Bus Trigger Fig 3 30 Trigger Tool Box 36 FMO7I4A REA AG i ARRES The Zeroplus Logic Analyzer Zeroplus Techneablogy Co Ltd User s Manual V3 09 Menu Bar Tri Menu Item Detail Menu amp Dialog Box Bus Trigger i x Bus Trigger Protocol Analyzer Trigger Bus Name Operator Value oe Bus Trigger Setup faut E fi Data Format Binary C Decimal Hexadecimal ASCII Cancel Default Help Fig 3 31 Set Bus Trigger See Section 4 1 for detailed instructions Channel Trigger Setup f x pora fe Contton_ Filter Condition ee Trigger Condition Condition Filter Condition CRS Bae ee Ol e o Trigger Condition x x Pee Sd Fe Ba ive ie 4 Channel Trigger Setup ac fiterconation X OX X X OM X R Fiter Condition X X X X X X X R D Trigger Condition XS one a a BS XS a Dat Fig 3 32 The trigger action tells the Logic Analyzer when to send data to the PC The trigger conditions determine when the trigger point starts to record the information ease ae Open the Trigger Mark function I J
29. Clock s positive pulse width or negative pulse width signal x aii Hoise Filter Noise Filter None Fig3 43 Noise Filter See Section 4 8 for detailed instructions Bus Tidth Filter l x ac Bus Width Filter cmas Fig3 44 Bus Width Filter Select the check box to activate the function of the Bus Width Filter in the dialog box and then users can input the corresponding value of the width to be filtered in the right edit box Input the time value of the width when the display is in the Time Display or the Frequency Display and the unit is based on time such as s ms us etc if the inputted value is out of the range it will switch to the best time value in range Input the clock value of the width when the display is in the Sampling Site Display and the range of the input is from 1 to 65535 For example after activating this function and then input the value 5ns The Bus Data which is less than or equal to 5ns will be filtered as the figure below 42 FMO7I4A 2 FRARA HARA amp Zeroplus Techneblogy Co Ltd x Data Contrast FA Find Data Value The Zeroplus Logic Analyzer User s Manual V3 09 Fig3 45 Before and After Filtering x m Activate Data Contrast Contrast Files Basic File JLadoct Contrast File Ladocz X Contrask Beginning Point f T Bar Error Tolerance None Beginning of Data Contrast Result Error Stat a BIBI ii
30. Ctrl U Add Channel Copy Channel Delete Channel Al Delete All Channels Restore Default Channels Format Row d Eename 117 FMO7I4A J gt RAERERGBESA The Zeroplus Logic Analyzer i Zeroplus Technology Co Ltd User s Manual V3 09 4 5 1 Bus Analysis The Bus Analysis function enables the system to analyze the Bus Basic Software Setup for the Bus r Rising Edge kd Parameters Gong Use kme DsEp te Fig4 57 Bus Setting STEP 2 Click Color Configuration to set Bus Data Color Rising Edge kd Parameters Gomhig 1 M Use the Slee Fig4 58 Color Configuration 118 FMO7I4A i PHRSR E The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 Kus Data Color xX Bus Mame Busi Data Condition Data Min Data Max lo F Cancel Default Help Fig4 59 Bus Data Color Bus Name Display the selected Bus name Data Condition Select the Data Condition to change the Bus data color There are four options which are In Range and Not In Range Data Min Enter the min data that is required by users Data Max Enter the max data that is required by users The max data can be used only when the set is In Range or Not In Range Select Color Select the changed color according to the Bus condition set by users the default is Green STEP 3 Click Color Configuration to open the Bus Data Color dialog box and set the Data Condi
31. Data Poti f oftifot ifoyfy itftofyi fw j Fig4 45 Bus Packet List Packet Name TimeStamp 6 __ Busi us Packet Name TimeStamp Busi us 963 Packet Length and Packet Idle Length Packet s TimeStamp is the start of Bus Data the default length is controlled by the setting dialog box If the input packet length isn t the end of data The software will prolong the length of Packet to end the data automatically as the figure below 363 a Sea axon aaa Fig4 46 Auto Prolong Packet The Fig4 46 is a Bus its first data is 0x00 and its length is 1023 If users input 20 as the Bus length But 20xaddress is not the end of this data so the software will prolong the length of the Packet to 1023 automatically B T 27 F Bus Fig4 47 Packet End The Fig4 47 is a Bus If the Start of the packet is T bar and the set Bus length is 20 but the data 0x02 isn t the end at that time the Packet will be prolonged to the end dot automatically that is to say the Address 27 B bar is the End of the packet The above two data are made consecutively as the figure below 113 FMO7I4A Phe eee i BR eS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 4 Fos 102 A T 1023 BPos 27 B T 27 T 1023 B T 27 Fig4 48 Auto Prolong Packet The Packet List is displayed as the fi
32. Data Mode gt Square Waveform v Sawtooth Waveform Fig 3 69 Sawtooth Waveform e Add Bar Alt A Delete Bar Alt tE Ri Zoom E ay Hand H Ln R Normal ESCAPE n Zoom In Zoom Out F Show all Data F10 K Previous Zoom Bhar bd Data Format d Waveform Mode List Data Mode gt v Square Waveform Sawtooth Waveform Fig 3 70 Reverse FMO7I4A 52 Phe Aik ie i BPRS eroplus Technology Co Ltd Tip This function of Reverse is to reverse the collected signal Change the High Level into the Low Level change the Low Level into the High Level The Reverse of Waveform Mode displays with the dashed so it is easy to distinguish The Zeroplus Logic Analyzer User s Manual V3 09 ley an ey anes RNC NE HST ET eS T T bbb se Ee be be a e em aoe a as nN SANS Se aa aN Ne el a I Ee ey I ce NY a a ee eee Po Ee Be Tt Eo nb SB 2 a 3a Ee T oe EE Vee Ss Vee SE CEN ES om E EH eg a at a a ee he m eT Bee Se ie i i Se ee a E a a m Fig3 71 Reverse Dialog Box Select All Select all the signals to start the function of Reverse Clear All There is no signal to be reversed when clicking this button OK Start the function of Reverse ma Or TTET E weesen EE ak eain A ol H i varene i ELEY a dial Ce T I e e Fu Fig3 72 Reverse Function Displayed in the Waveform Window FMO7I4A 53 PR
33. Display Pos 39522 A amp A Pos 25205 v Total 131072 A T 25205 v Display Range 39302 39344 B Pos 25175 v B T 25175 v Fig4 39 Bus Packet List Packet List has a setup window users can set up the Packet List according to their requirements Setting Bus Packet Length in dialog box is only used for doing Bus Statistic Users can define how long the time is as a data packet to add the export function See the following figure 110 FMO7I4A PHHH BR eS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Settins x Bus Select Data Format WlEus1 Bus Bin Dec Hex ASCI Bus Facket Length Mini 1 fto Max 2048 Packet Item If Packet I Name Timestamp Length Data Text fe s Text Color Auto Fig4 40 Packet List Setting BUS Packet List xj Refresh Export Synch Parameter Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length E i leureus 1023 J o 1i oJ lo i Lo 1 1o 1 Packet Name TimeStamp Data Data Data Data Data 2 Busi us 1013 Data Jata Jata Data Data Length Packet Name TimeStamp Data Data Data Data jata ata Length o Packet Name TimeStamp Data Data Data Data Jata Jata Length o 1 o i _ Packet Name Timestamp Data Data Data Data Data Data Data Data Data Length Packet N
34. Filter CHANNEL Full Period Conditional Conditional Conditional Start Pos EndPos oO oO Oo ooocococcoccc 0c 0c 0c 0 ooooccc 0c 0c 0 00 oO oooococcocco ceo Fig 3 137 STAT VIEW E ZEROPLUS LAP C 32128 S H 000000 0000 LaDoci E ioj xj File Bus Signal Trigger rors Data Tools Window Help l8 x Demam at 2B dD p faq z o Bi 00MH v mw mw 509 ee s Page fi p Count fi ORIEK sit K fii rons s Rl ae Oe BY Je te Mb le oo Height Trigger Delay 10 Scale 10ns Display Pos Ons Pos aa v A T 150ns k B 300ns v Total 20 48us Display Range 250ns 250ns B Pos 150ns v B T 150ns Compr Rate No Filter Bus Si gnal Trigger 7200ns Tans ee 100ns 50ns 50ns 100ns 200ns Se ty UT sunt tn0 gii TOT TTT l a FLY LAL LS LL L aa T OL L ES a i A 1020 1020 1020 o o 0 Ds Dp al 514 514 514 0 o 0 Ds Dp A2 257 257 257 0 O o Ds Dp A3 128 128 129 0 o 0 Ds Dp A4 64 64 65 0 o 0 Ds Dp AS 32 32 33 0 o 0 Ds Dp A6 16 16 17 o o 0 Ds Dp A7 8 8 9 0 o 0 Ds Dp BO o o 1 0 o 0 Ds Dp 1 Bt O o 1 0 o 0 Ds Dp Ready End DEMO Ui Fig 3 138 Logic Analyzer with Statistics Enabled There are four options for adjusting how statistical information may be presented These four options are Channel Parameter Item Parameter Condition Parameter and Warning Par
35. High signals gt 3 Protocol Analyzer IO Description oe The sole I O transmits Host and BQ HDQ status and data 4 Protocol Analyzer Electrical Specifications Parameter Min Type Max Unit Note V Logic Input High Logic Input Low Protocol Analyzer HDQ Format Description The format changes according to the pulse width so the display must refer to the defined pulse width Protocol Analyzer HDQ is made up of 16 bits signals Firstly after the period of status signals a device will be installed for the 7 bits address through the Host so that 1 bit signals can be read or written After a response time of high signals data will be exported in 8 bits format with the data and location content from LSB to MSB The following is the Host to BQ HDQ analysis 150 FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Technology Ca User s Manual V3 09 Send Host to BQ HDQ Send Host to BQ HDQ or Receive fr rom BQ HDQ i Da j tRR L imminmmmnr Loe ot ooo iE ee Address Rw LSB MSB Break Bito Bit7 es gy ee ge EE oe es Le K tRsPs Address Bit K Start bit Data Bit Stop Bit i j _ Fig4 111 Host to BQ HDQ Analysis Protocol Analyzer Format Break This is the initial bit for the Protocol Analyzer HDQ after Low signal lasting a period of t B it is then converted to a High signal lasting a period of t BR The length of Low signal is no les
36. Pres will be limited to Apply Cancel Restore Defauts Help Fig 4 3 RAM Size Tips 1 The Double Mode is available for the LAP C 16128 LAP C 162000 LAP C 32128 LAP C 321000 LAP C 322000 Modules and it is not available for the LAP C 16032 LAP C 16064 Modules 2 The relationship between RAM Size Signal Filter Mode Compression Mode and Channels as shown in Table 4 1 and Fig 4 3 Table 4 1 RAM Size vs Signal Filter Mode and RAM Size vs Compression Mode and Channels Normal Mode Double Mode RAM Compression RAM Compression Model No Size Channels Mode amp Size Channels Mode amp Available Signal Filter e Available Signal Filter Mode Mode LAP C 16032 2K 32K _ 16 Available channels LAP C 16064 2K 64ak 16 Available channels Channels 2K 16 l 16 LAP C 16128 128K ands Available 256K channels Disable 16 16 LAP C 162000 2K 2M Available 4M Disable channels channels 2K 32 16 LAP C 32128 128K eels Available 256K lt a Disable LAP LAP C 921000 LAP C 921000 2K Available Disable PE oneei Piebe LAP C 322000 2K 2M Available 16 Disable PE channels FMO7I4A PREM AG Blk ee The Zeroplus Logic Analyzer Zeroplus Techneblogy Co Ltd User s Manual V3 09 Task 2 Trigger Property Setup Step1 Click E icon or click Trigger Property from the Trigger on the Menu Bar The dialog box will appear as shown in Fig 4 4 Trigger Run Stop Data To
37. RESET PRESENCE PULSE DATA Pin ssignment Protocol Analyzer Hame Bust Channel Protocol Analyzer Property Connect speed Data Direction Standard 1 us High 0 2 us MSB gt LSB LSB gt MSB Data Length fe bit blin 1 bit blan 32bit Fig4 103 Protocol Analyzer 1 WIRE Setup STEP 1 Select Channel 1 WIRE has only one IO Select the channel that it is to link the IO PROTOCOL ANALYZER 1 WIRE SETUP Bus1 j x Configuration Packet Register Pin ssignment Protocol 4nalyzer Hame Protocol Analyzer Property Connect speed Data Direction Standardi us High 0 2 us MSB gt LSB C LSB gt MSB Sampling position mou iis Toi blin Tus as 120us Min 1 bit Max 32bit Cancel Default Help Fig4 104 Protocol Analyzer 1 WIRE Channel Setup STEP 2 Set Connect Speed 1 WIRE has two modes standard and high speed The speed setup according to the specifications of the object to be tested and the default mode is standard 146 FMO7I4A i Phe Be Ae in ARARE The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 PROTOCOL ANALYZER 1 WIRE SETUP Busl x Configuration Facket Register Protocol Analyzer Color Protocol Analyzer Hame RESET PRESENCE PULSE DATA M Channel Pin Assignment Protocol Analyzer Property Connect speed Data Direction f Standardi us High 0 2 y f MSB gt LSB LSB gt MS
38. The functions of the right key menu on the le Zoom E waveform area are similar to those of the ey Hand H k Normal ESCAPE Data menu Show all Data F1 The menu adds the functions such as wy Previous Zoom CtrltZ Place Ds and Dp Add Bar in the waveform HSS AE i Wave Mode display area Color Bus Data Color Bus Single Data Color Fig3 119 Right Key Menu on the Waveform Area Place A Bar Flace E Bar Flace Ds Har Place Dp Bar Flace More Ti a ta Di Ilipa Ayam ern pem ere pre bi PTE p ar a de MaS Fan gt im aj ah 1p SA oe fe Pape fi E a OG a Sek be we ole tins The right key menu on the waveform ee ee ETN Toril Sl Sosi Biaphir kisja ET the 1 Ttan OTET T Trigger Febier a area adds the function of Place Ds and Place a LUUL L U eters te Dp However the functions are only used Pa after the Ds and Dp bars are activated otherwise they will be disable These n functions are the same as that of A Bar When the mouse is stopped at a special ee aL ast ah p J position click the right key on the mouse select the Place Ds or Place Dp the Ds or Dp bar will move to the special position FMO7I4A J PRAEHROBRAA The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 70 For example Open Select an Analytic Range select the special position is 10 and then select Place Ds See the figure in the ri
39. Urknow_Erd Flag UART RASTA Facket Length Stop a Data Length 1 1 5 bit Fig4 81 Packet Length If the STOP falls short of condition it isn t noted down in UART Packet Length From START Starts TimeStamp to STOP Unknow_End Flag TimeStamp Packet Idling Length Unknow_ End Flag TimeStamp to START TimeStamp 133 FMO7I4A O PRERSIG IRA Zeroplus Technology Co H 4 5 4 SPI Analysis SPI Introduction The Zeroplus Logic Analyzer User s Manual V3 09 SPI Synchronous Peripheral Interface is a parallel synchronous full duplex protocol with a Bus like physical interface This protocol was first developed by Motorola and was generally used for EEPROM ADC FRAM and display device drivers which are equipped with low data transmission speed The SPI data transmission is synchronous in both receiving and transmitting directions Although Motorola initially did not define the clocking impulse it is commonly seen that the clocking impulse is according to the master processor In practice there are two clocking impulses CPOL Clock Polarity and CPHA Clock Phase The configuration of both CPOL and CPHA decides the sampling rate When the SPI must transmit serial data it initiates the highest bit 134 Since SPI is a synchronous communication protocol and data transmission may not be in bytes a complete SPI signal Packet must consist of SCK MOSI MISO and SS segments with CPHA and CPOL They are as followi
40. Zeroplus Technology Go Ltd User s Manual V3 09 you can get this Protocol Analyzer plug and the register code STEP 1 Put the CAN2 0B Plug in the Plugins as the Fig4 35 ry T Fie Eo ema Pavorites Teds Hala Seba oh Sh Geen artin raay AS GX e Gi JARE Foxe Pu Fugit Pari dl Pagat di Fig4 35 PluginsA STEP 2 Select CAN2 0B in the Protocol Analyzer list Bus Property X Bus Setting f Bus Color Gong Activate the Latch Function 40 Rising Edge Protocol Analyzer Setting Protocol Analyzer Parameters Contig ZEROPLUS LA 12C MODULE 2 01 02 ZEROPLUS LA SPI MODULE 1 11 01 ZEROPLUS LA UART MODULE 2 10 01 ZEROPLUS LA 1 WIRE MODULE 1 09 01 QZEROPLUSLACAN Z 0BMODULEV131 00 5 ZEROPLUSLAHDQMODULEW2 06 01 0000 Find More Protocol Gnalyzer hkkp ww zeroplus com tw coca e IY Use the DsDp Fig4 36 Bus Property STEP 3 Click Parameters Configuration button select Register and enter the Register Code 108 FMO7I4A C DS gt REARERGBERSA The Zeroplus Logic Analyzer gt Zeroplus Technology Co Ltd User s Manual V3 09 PROTOCOL ANALTZER CAN 2 0B SETUP Busl a Fig4 37 Protocol Analyzer CAN 2 0B Setup 109 FMO7I4A PRR R iB PRE The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 4 4 Bus Packet List Bus Packet List is a graphics list which is used for
41. ack AD D Ack BE D Ack CF _ D AcK EO D AcK F1 D ACK D ACK DATA o DATA D ACK Packet Name TimeStamp SLAVE ADDR READ 4 ACK DATA DRACK DATA D gt ACK DATA SDL READ A ACK 27 D ack 38 D Ack 49 D Ack 5A D ACK 6B D ACK D ACK DATA D ACK a D ACK DATA DOACK DATA DPACK DATA DATA 7c D ack 80 D Ack 9 D AcK aF D ack co D ACK o w f oo 3 Fig 4 53 Waveform and Packet Synchronization Interface Ready 116 FMO7I4A i PRIA The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 4 5 Bus Analysis The setup is correlated to the Bus which needs to be made up for example Bus Protocol Analyzer Open the dialog box BUS STEP 1 Click Tools on the Menu Bar and then select Bus Property or select to set up Bus Property Customize E Show Time of Waveform Color Setting aiI Bus Property ae Refresh Protocol Analyzer gm Memory Analyzer Multi stacked Logic Analyzer Settings Analog Waveform d Fig4 54 Bus Property on Menu Bar Fig4 55 Bus Property on Tool Bar STEP 2 Click the Right Key on the Bus Signal column and then select Bus Property Tip The signals must be grouped into Bus or the Bus Property can not have effect me Ul Sampling Setup ey Channels Setup 2E Bus Property Analog Waveform Group into Bus CtrltG coe Ungroup from Bus
42. channel form the pull down menu The default synchronous channel is AO Synchronous Trigger Condition Select the synchronous trigger condition Users can select the Rising Edge Falling Edge High and Low from the pull down menu The default is the Rising Edge The function of the Synchronous Trigger Condition can only be used in the Channel Stack that is to say it is disabled in the Memory Stack STEP 3 Display the function of Multi stacked Logic Analyzer in the Memory Stack Tip There are two Logic Analyzers to do the Memory Stack the Synchronous Channel is AO the data on the left of A Bar is captured by the first Logic Analyzer the data on the right of A Bar is captured by the second Logic Analyzer E LE Lac Ore a CLades lt Ta Bebe Beye Ei gee Bei gee hafa haa eila fiala falf Cet amp ae wort Bee rek mhh ionize mjes se ose a race i aCe a a E E H rom J GT FEEFEE Ale g fright th Troga Ree mE Serie Eripler Pau nears iret am A Ta a asia N Peis EH Diiplar Fere D i pa HeFe HHE mprisia Fe d i msl a gt Fit ee i Lites mn Beuta ma Tip O Pilis HEFE EJ ae EE pATE y nes es 4 z CER ek eh See B cbo de ees l oe ed lm tee l LS m r n q STEP 4 Display the function of Multi stacked Logic Analyzer in the Channel Stack 185 Tip There are two Logic Analyzers for Channel Stack the Synchronous Channel is AO the Synchronous Trigger Condition is the Rising Edge the former 32 ch
43. channels The trigger lever can only be adjusted for an entire port H08 Does the Logic Analyzer use hardware or software compression technology A For time efficiency the Logic Analyzer uses hardware compression H09 Is planning an Analyzer that can handle more channels A Yes we are working in this direction H10 Does the memory page vary when the depth of the memory changes A Yes the depth of memory changes the memory page H11 Is the Logic Analyzer expandable How may I expand it A Yes the Logic Analyzer is expandable At this stage you can expand it with external module devices H12 Why must reinstall the driver every time use a different Logic Analyzer A Since each Logic Analyzer has unique serial numbers you must reinstall the driver every time you change the Logic Analyzer H13 Why is there no data Why does data sampling seem inconsistent A The reasons are varied but you may follow this checklist for troubleshooting 1 Always check the USB connection between the Logic Analyzer and your PC 2 We strongly recommend using USB ports in the rear panel of a PC these ports usually have better voltage stabilities than front panel ports However if front panel USB ports are directly soldered to the main board you can use them 3 Make sure the Logic Analyzer is directly connected with the PC without a USB hub 4 Inconsistent data display may indicate voltage irregularities in the main board examine
44. doing Statistics and showing Bus Packet List It is visual and direct especially for I2C USB and CAN 2 0B When there is a packet list it gets twice the result with half the effort to check the data Packet List has its startup button in Toolbar After starting it it will show a small window under the waveform window Users can alter its size to find more data Notice If you want to learn more about the Bus Packet List please refer to the Specification of the Protocol Analyzer E ZEROPLUS LAP C 32128 S H 000000 0000 LaDoc5 o x a File Bus Signal Trigger Run Stop Data Tools Window Help 18 x Deala Be S oe r ER b 1 128K rie 4 200MHz 20 s Page 1 E gt l 125 030527 s R a Be Be Ee de BM e o S Heier Trigger Delay 1 4 Font Size 12 X Scale 0 7998047 Display Pos 39322 Total 131072 A Pos 25205 v A T 25205 Display Range 39302 39344 B Pos 251T5 v TS ES E la 39306 00 33310 00 39314 00 39318 001 39322 39825 99 39329 9939333 3933337 99639341 BUA AA PU LU PLE LILI LI LU Le pot J pst E L a Fig 4 38 Packet Icon fe ZEROPLUS LAP C 32128 S H 000000 0000 LaDoc5 a File Bus Signal Trigger Run Stop Data Tools Window Help Oe e 46 amp amp le 2 Bll gt po aoma mla 128K sie 141 200MHz is Saw 125 03052 s Aw Be Te tu Bar Bar Bar Bar A ie gt FB BS oo Heigt Scale 0 T99S047T
45. export file automatically The export file can be popped up automatically Users can decide whether to activate the function the default is selected See the export file below ioi xi File Edit Format Yiew Help ZEROPLUS Logic Analyzer ff Version U3 68 Filename 11 txt File size 236 KB File created on 2669 12 17 Logic Analyzer setup information Sampling mode Standard Internal sampling frequency 1666666 Hz RAM size 2KB None Use Data Compression Fig 3 8 Export File FMO7I4A 2 O PRA SIRO A Zeroplus Techneblogy Co Ltd Export Packet List The Zeroplus Logic Analyzer User s Manual V3 09 2x Save in a My Documents e ex Fee My Recent Documents Desktop amp My Documents Fr My Computer My Network laces Save as type Text Files txt 7 Cancel Bus Output Parameter Data Format Yes No Hexadecimal 7 r Output range From First Packet To Final Packet 7 fe fe Export Format Report Form J Pop up an export file automatically Fig 3 9 Export Packet List Dialog Box Users can use paperwork register and analyze packet list data pop up an export file automatically The function of popping up an export file automatically in the Export Packet List dialog box is the same with that of the Export Waveform dialog box Export Format The Export Format is convenient for users to ues the ca
46. external clock voltage level is the same as the port A trigger level C Opposite of Filter Condition Period Delay Max 65535 aaron Display Bar Setup MRAM Size Compression Mode Signal Filter JV Show Bar RAM Size zx I Data Compression Bar Style Signal Filter Setup H Original x Channel number will be i limited to 32 Bar Width fi Apply IL Cancel Restore Defaults Help OK Cancel Restore Defaults _ tee Fig 4 141 Signal Filter Setup Set the high level as Filter Condition on the signal A1 Step4 Signal Filter Setup 1 Setup the Filter Condition as 2 Click OK then click Run to activate the signal from the tested circuit to the Logic Analyzer 3 The system will display only the waveforms of the signals which are qualified by the Filter Condition Bus Signal Trigger Filter 20 Saher oe a a a 5 10 15 20 311 795us 15 88 30 525us 20 4us 309 055us LIL ILILILIL 655 36us 655 36us 655 36us 655 36us 655 36us va as 655 sous 169 FMO7I4A O PRARRRARE The Zeroplus Logic Analyzer Zeroplus Technology Co User s Manual V3 09 Bus Signal Trigger Filter ra hk eee E es ee ee ee ee ee fe PEP Tisza POL Lt M 388 33us PR 388 33us SAA 2s 388 33us Fig 4 142 Without With Signal Filter Setup The first picture shows the result without any signal filter setup Th
47. file txt A This feature is available in this version SW12 Why is the text display covered by other text or outside the display width A At this stage our software interface program has missing code for multilingual support You will have to ensure your system default encoding is one of the following languages 1 any English Encoding en en XX 2 Traditional Chinese zh zh XX 3 Simplified Chinese zh zh CN in HZ GB2312 GB18030 Double check the language configuration in Regional and Language Options A Cocoa ibs W cai autock veusbor Ae BRP bei x o Regional amd Language Iptions i Scare p j MARRAN z Oh umibasrs berries ar kd dales betwee Gommoctons T Taon amd dorks manes LS Erhtes smc Fares E iF Speech i ey Dekbar and Siart Meru TA Stored leer Mames and Passwords Log OM kirg ge Syimenitec LiveUpdate 4a Sysinm a Sa Aas zi Taskbar md Start bkn igs nudos Frea Fig 6 5 Windows Regional and Language Options l Hep aid Soppi T Windows Sevversoca Enterprise Eder 194 FMO7I4A Customize settings for the dsplay of emquaces PREAH ih Bike Bl The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 SW13 Is there a Reset that restores the default color settings for signal output waveforms in the Position Signal Display Area A Yes there is Click Tools from the menu bar and select Color Setting click Defaults However this re
48. iliy T Ge ap f Fig4 122 Basic Data Frame Start of Frame Every Start of Frame must be 0 which means asking far data to come back Arbitration Field Identifier is 11bits its function is the sequence when transmitting signal numerical value is lower the priority is higher and the array is from ID 10 to ID 0 and the numerical value is not all from ID 10 to ID 4 finally RTR Remote Transmit Request is the judgment bit of transmission or Remote Transmit Request When RTR 0 it denotes that the data goes out when RTR 1 it means asking far data to come back Control Field Control Field consists of 6 bytes including Data Length Code and two Reserved Bits as Peli frame for future expansion The transmission reserved bit must be 0 Receiver receives all bits combining 1 with 0 As the below figure IDE and RBO of Control Field are Reserved Bits which must be 0 and the latter 4bits are only 0 8 which denotes the data behind will transmit several bytes data Fig4 123 Control Field Data Field The Data Field consists of the data to be transferred within a Data Frame It can contain from 0 to 8 bytes and each contains 8 bits which are transferred MSB first CRC Field 16bits CRC the last is a delimiter and the default is 1 158 FMO7I4A 2RARRGARLA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Fig4 124 CRC Field Ack Field That is the return signal of Receiver
49. items include the current color of Cursors Grid Unknow Line Default Bus Bus Text List Text and Time Text users can scroll the vertical wheel to view the selectable items Bus Error Users can configure the color of Bus Error Data from the Color Setting dialog box Bus Error Text Users can configure the color of Bus Error Text from the Color Setting dialog box Relating When users select one item to change the color of the item and users want to change other items into the same color they can select other items at the same time in the Relating column then the selected items will be changed into the same color So it is convenient for users to change many items into the same color once After the background is altered corresponding color automatically changes according to the contrast FMO7I4A i PHRSR E The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 ratio When users set the color for the workaround and select the option the system will switch other colors automatically to become the contrast color When being printed the background is white When being printed the background color is white Waveform Change the color of the Buses or signals on the waveform area Color Setting x Workaround Waveform Mame C Relating Linewidth i O EEE Cancel Default Help Fig 3 162 Waveform Color Interface Waveform The channel color can be varied by users Linewidth T
50. menu See Fig 6 3 and then select About ZEROPLUS Logic Analyzer See Figs 6 3 and 6 4 Help Logic Analyzer Help F1 keyboard Map Report a Problem kd About ZEROPLUS Logic Analyzer About ZEROPLUS More Protocol Analyzer Fig 6 3 About ZEROPLUS Logic Analyzer About ZEROPLUS Logic Analyzer x LOP Series P A 3 BS fh a PR E Version Standard 3 080CNO2 Zoroplus Technology C Ltd SiM 000000 0000 The Information of the Version New Feature Support the Wide Screen and Double Screen Display Fortified Functions Support the SDK for Data Contrast Support the Multi page Multi device and Multi sector Analysis For Memory Support more new Languages Support the Pulse Width Trigger Module For L4P Series Support the Protocol Analyzer Trigger For LAP C Series Bug Fixed Detailed description invites reference ReadMe Detailed description invites reference company website Copyrightil 1997 2010 ZEROPLUS TECHNOLOGY CO LTE Website http Sf zeroplus com tw Fig 6 4 The circled information is the version number SW10 How may I upgrade my software interface program A Visit our website at http www zeroplus com tw and follow the instructions for the English version You may also use the following address for English updates http www zeroplus com tw logic analyzer_en technical_support php SW11 Can I save my signal data to a separate pure text
51. of the product and fill in the registration form Call us and mail both picture and registration to us A customer representative will be happy to assist you How do register the protocol analyzer and buy protocols Every product is assigned and engraved with a unique serial number please print your S N number window as an example attachment and send it to our distributor or ZEROPLUS head office According to your S N we will provide passwords for your protocol registration FMO7I4A O PREP i Bee The Zeroplus Logic Analyzer T101 T102 TI03 T104 TI05 TI06 TI07 T108 TIO9 7110 TI11 198 Zeroplus Techneablogy Co el User s Manual V3 09 6 4 Technical Information What is the Logic Analyzer The Logic Analyzer is a tool that sieves out and shows the digital signal from test equipment by using a clock pulse The Logic Analyzer is like a digital oscilloscope However it only shows two voltage states the logic status 1 and 0 differing from many voltage levels of an oscilloscope The Analyzer has more channels than an oscilloscope to analyze the waveform Since the Logic Analyzers obtains only signals 1 and 0 its sampling frequency is slower than an oscilloscope which needs many voltage ranks Moreover the Logic Analyzer can receive many signals during a test How does the Logic Analyzer operate The Logic Analyzer reserves trigger requirement setting for users and uses them on the test eq
52. the Basic File Contrast Beginning Point It can set the beginning point of the contrast at Trigger Bar or Beginning of Data Error Tolerance It is the allowable time error when setting data contrast Contrast Result It displays the same contrasted result and the different contrasted result with PASS and FAIL respectively Error Stat It displays the number of discrepant parts Pin Assignment Users can select the contrastive channel Perform Contrast It can activate the Contrast at once Display files horizontal The waveform window of the two contrast files are displayed in horizontal Users can select it as their requirements and the default is non activated Roll the contrast waveforms synchronization The two contrast files roll synchronously Users can select it as their requirements and the default is non activated Display files the contrast differences It can line out the difference in the contrast waveform Users can FMO7I4A O PRARRRARE The Zeroplus Logic Analyzer Zeroplus Technology Co User s Manual V3 09 select it as their requirements and the default is non activated Tip For this function Data Contrast we provide the SDK Development Tool for users Users can customize the Data Contrast Interface according to their requirements We has packed the Data Contrast UI as the GUI DLL and designed an interface which is used for the communication between the GUI DLL and Main Program The GUI adopts the Non modal Interface
53. the Logic Analyzer Ext I O Module B Same as IOA Ext I O Module C Same as IOA GND Grud sd Ground external devices in sequence FMO7I4A Zeroplus Techneablogy Coa Ltd User s Manual V3 09 gt FRARROARAA The Zeroplus Logic Analyzer toe 1 3 Hardware Specifications Table 1 6 Hardware Specifications of LAP C Series LAP C LAP C LAP C LAP C LAP C LAP C LAP C Items Type 16032 16064 16128 162000 32128 321000 322000 Operating System Windows 2000 Windows XP Windows Vista Windows 7 Power Supply USB 1 1 USB 2 0 Recommended Internal Clock Rate 100Hz 100MHz 100Hz 200MHz asynchronous Max Rate External Clock synchronous Bandwidth 75MHz 912K Bits 1M Bits 4M Bits 64M Bits 4M Bits 32M Bits 64M Bits Memory Memory Depth Per 32KBits 64KBits 128K omBits 128K imBits 2MBits Bits Bits Channel Trigger 16 Channels 32 Channels Channel Trigger Pattern Edge Condition Trigger Pre Trigger Ves Post Trigger 1 Sampling Max 75MHz Max 100MHz Trigger Count 65535 Threshol Working 6V 6V Voltage Protocol SPL Free 7 SEGMEN Free T LED Increasing Operating Interface Chinese Si Chinese Tr English Language Time Base 10M Vertical 1 5 5 Sizing Compression Max Max Max Max Max Max Max P 8Mbits 16Mbits 32Mbits 512Mbits 32Mbits 255Mbits 512Mbits 10 FMO07I4A 11 OO PREHAROSRAE et Zeroplus Technabogy Co te Width Yes Fu
54. the Print Show the recently saved file Exit the program FMO7I4A P Re Tee ih BR eS The Zeroplus Logic Analyzer ne Zeroplus Technology Co Ltd User s Manual V3 09 2 Bus Signal j gt Sampling Setup ia Sampling Setup F Clock 5 i y Channels Setup ock Source Asynchronous Clack Group into Bus Ctrl Internal Clock Ungroup krom Bus Gh U Frequency 2D0KHZ Expand Collapse Synchronous Clock P mei I ml k Format For Abo Stee Rename ae Move Lefti Up dae Mowe Right gt Channels Setup ove Right Down See ee Hide Show All Color RAM Size Channel number will be limited to 32 Fig 3 18 Bus Signal Menu Dialog boxes of the Sampling Setup and Channels Setup are shown and indicated by arrows Fig 3 19 Trigger Tool Box 30 FMO7I4A The Zeroplus Logic Analyzer PREM RAh BRAE User s Manual V3 09 Zeroplus Technology Co te Menu Bar Bus Signal 31 Menu Item Menuttem Detail Menu amp Dialog Box __ _ _ _ i Sampling Setup i Sampling Setup x m Clock Source Asynchronous Clock Frequency 200KHz we Synchronous Clock External Clock Rising Edge Falling Edge Frequency 100KHz Min 0 001Hz Max 100MHz2 Note The external clock voltage level is the same as the port 4 trigger level Sampling RAM Size Compression Mode m Signal Filter RAM Size 2k D
55. the latch function Protocol Analyzer Activate the function of analyzing the Protocol Analyzer Use the DsDp Use the Ds and Dp to help analyze the Protocol Analyzer Find Find the desired Protocol Analyzer module Users can input the Protocol Analyzer name to quickly find the Protocol Analyzer module from many Protocol Analyzers After inputting the first character of the name in the Find box of Bus Property dialog box the corresponding module will be displayed in the Protocol Analyzer list box according to the input character See the figure below FMO7I4A PRE ESAS i ARAE Zeroplus Techneblogy Co Ltd ee Refresh Protocol Analyzer gue Memory Analyzer Benary amargar O O OOOO Egee sot t J pe pot op er me A The Zeroplus Logic Analyzer User s Manual V3 09 x Golor Gontig I activate the Latch Function AD Rising Edge Protocol Analyzer Setting f Protocol Analyzer Parameters Gonhig M 2EROPLUS LA Tal MODULE 2 01 02 EROPLUS LA SPI MODULE 1 11 01 5 ZEROPLUS LA UART MODULE 2 10 01 5O ZEROPLUS LA 1 WIRE MODULE 1 09 01 2EROPLUS LA CAN 2 06 MODULE 1 31 00 5 2EROPLUS LA HDQ MODULE 2 06 01 M Use the DsDp More Protocol Analyzer http jiv zeroplus com Ew comei e Fig 3 84 Find Editor Box When you input I in the Find editor box the Protocol Analyzer list displays all Protocol Analyzers with the initial character of I
56. there is no difference in the channels of the two files STEP 3 Display the contrast results in the waveform windows See the figure below Tip It contrasts the two data files in the waveform area The contrast waveform and the basic waveform are displayed horizontally we can roll the mouse to contrast the waveform files the difference of the waveforms will be lined out with the red wave line in the contrast files 176 FMO7I4A BARBARA The Zeroplus Logic Analyzer gt Zeroplus Technology Co Ltd User s Manual V3 09 Es ZEROPLUS LAP C 321000 S H 000000 0000 1 alc Fig4 157 Display the Contrast Results in the Waveform Windows Tip The Data Contrast function is available for the LAP C 162000 LAP C 321000 and LAP C 322000 Modules and it is not available for the LAP C 16032 LAP C 16064 LAP C 16128 and LAP C 32128 Modules 177 FMO7I4A PARAH ih Bee The Zeroplus Logic Analyzer f Zeroplus Technology Co Ltd User s Manual V3 09 4 10 Refresh Protocol Analyzer The Refresh Protocol Analyzer function enables the system to analyze the data between Ds and Dp again 4 10 1 Basic Software Setup of Refresh Protocol Analyzer STEP 1 Click Tools on the Menu Bar then select Sl or click ku on the Tool Bar directly to refresh Protocol Analyzer Multi stacked Logic Analyzer Settings Analog Waveform d Fig4 158 Refresh Protocol Analyzer STEP 2 Transmit the tested Protocol Analyz
57. to help distinguish them 4 Protocol Analyzer Color Set colors of the segment in the protocol analyzer Step7 Click Custom Setting to define the I2C Data to meet users requirements The dialog box as shown in 123 Fig 4 68 will be displayed OE Read f Write bit Data Area Active l T oF f High Low A The input must be between 1 and 26 T Don t Stop Analysis Ack Bit Conditions Ack Bit Low nee ae Noack Bit High Cancel Default Hek Ack Bik Fig 4 68 Inputting Data Bits 1 Read Write Bit Setup Click on Active to set the segment of Read Write Bit in the Protocol Analyzer I2C then select High or Low to set the condition of the Read Write Bit for the DUT Click off Active to remove the Read Write Bit segment from the Protocol Analyzer 12C 2 Ack Bit Setup Click on Don t Stop Analysis when NACK happens to continuously analyze the signals when the system says NACK Bit then select High or Low to set the condition of the NACK Bit for the tested Protocol Analyzer 12C Click off Don t Stop Analysis when NACK happens to stop analyzing the signals when the system reads NACK Bit 3 Give the names and the numbers of Bits to the Address Bit and Data Bit on the columns located in Data area for the tested Protocol Analyzer 12C The range for Number of Bit is from 1 to 28 bits 4 Click on Address left shift one b
58. 0us High Speed 48us for a period of time MASTER TX RESET PULSE MASTER RX PRESENCE PULSE i V PULLUP Vu LLUF MIN Vin MIN V L MAX OV eee RESISTOR ame VAS TER DS2432 Fig4 96 Master TX Reset Pulse and Master RX Presence Pulse 2 Then Master releases Protocol Analyzer and enters the RX mode Through high pull resistor 1 WIRE Protocol Analyzer is pulled back to the high status 3 Then Master detects a rising edge from the Data Line when every slave will wait for a period of time PDH standard speed 15 60us high speed 2 6us and send back a Presence Pulse to Master PDL standard speed 60 240us high speed 8 24us 4 Finally the 1 WIRE Protocol Analyzer will be pulled back to the high status through the resistor G Meanwhile Master can detect any online Slave O lt From Fig4 97 the low count Reset Pulse and Presence Pulse signals can be clearly seen 141 FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 eo ee a dennes a es i ao oI 7 J _ _ _ amas a S l n iil im 1 00 Y A Tous ChiX 4 52 Figure 2a You can clearly see the negative poing reset and the presence pulse Fig4 97 Reset Presence Detect Sequence 2 Write Data 1 To initialize Write Data Master will convert the Data Line from the high logic to the low 2 There are two types of Write time slot Write 1 time
59. 1 LaDoc2 aa aa a Fig4 115 Operation Interface Sample the HDQ signal or open the sampled waveform Ce ZEROPLUS LAP C 32128 S H 00000000001 LaDoc2 es a OOO Fig4 116 HDQ Waveform 153 FMO7I4A fos SRAHMOBIEAA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Arrange the signal channels into Bus P ZEROPLUS LAP C 32128 S H 00000000001 LaDoc2 er a E Fig4 117 Group into Bus Select Bus Property E gt ZEROPLUS LAP C 32128 S H 00000000001 LaDoc2 ne ee oe Fig4 118 Bus Property 154 FMO7I4A fos SRAHMOBIEAA The Zeroplus Logic Analyzer ik Zeroplus Technology Co Ltd User s Manual V3 09 Select the decoding function of the protocol analyzer HDQ and select OK to confirm ZEROPLUS LA SPI MODULE 1 11 01 ZEROPLUS LA UART MODULE 2 10 01 ZEROPLUS LA 1 WIRE MODULE 1 09 01 ZEROPLUS LA CAN 2 06 MODULE 1 31 00 ZEROPLUS LA HDQ MODULE 2 06 01 ZEROPLUS LA I2C MODULE 2 01 02 nn i A Fig4 119 Protocol Analyzer HDQ Setup Complete the protocol analyzer HDQ decoding gt ZEROPLUS LAP C 32128 S H 00000000001 LaDoc2 F lt a I I ERROR fees a oo es EE SS gt a OO re Fig4 120 Protocol Analyzer HDQ Decoding 155 FMO7I4A 156 E PHRSR E The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s
60. 1 O17 GM 4 31 2 110 71 6 514 312191017 6 5 4 31211 017 615 413 2111617 5141312110 7 6 5 4 3 2 1 0771 6 5 4 3 2 1 0 7 6 5 4 3 2 1 OMB 6 5 4 3 2 1 80 Tip OA EA 1 gt bay EE TR Wa rh Boa WA GG Ge rR F Reserve mevelorm data and show them if Channels Setup Fig 3 25 Channels Setup See details in Section 4 2 33 FMO7I4A O PRERHRGERA Zeroplus Technology Co H The Zeroplus Logic Analyzer User s Manual V3 09 Tip Add Bus Signal Delete Bus Signal Delete All Restore Defaults Reserve waveform data and show them Croup into Bus trlt ts Ungroup from Bus Ctrl U Expand Collapse Format Row 34 Click the Add Bus Signal button to add a channel This will appear as New0 Click the Bus or channel you want to delete and press the Delete Bus Signal button Press the Delete All button to delete all the Buses and channels Press Restore Defaults to return all channels and Buses to the system defaults Select this function when adding and deleting channels the software reserves the original waveform not select this function the waveforms in channel are cleaned up Signals can be grouped into Buses by pressing Ctrl G Signals can be added deleted copied and grouped into Bus using the mouse or the keyboard or right click and select the desired operations from the pull down menu The movement of a signal channel are Auto Size not available in waveform dis
61. 21000 S 000000 0000 SPI SET als a File Bus Signal Trigger Run Stop Data Tools Window Help Ax Be Te te Bar Bar Bar Bar Bar E l l Scale 4 4291174 Display Pos 111 Total 524288 Display Range 0 221 a 22 146 44 291 66 437 88 582 110 728 132 874 155 019 177 165 199 31 2 e pg fa gg E E E E ay eg poo ILL Fig 4 87 SPI Signal FMO7I4A SRRHRERGARAA The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 4 5 4 2 Protocol Analyzer SPI Packet Analysis FEOQTOCOL AHALTZEE SFI SETUP basl x Configuration Facket Register Cancel Default Help Fig4 88 Protocol Analyzer SPI Packet Setup DATA List Data field captured by Bus in the packet display BUS Packet List BUS Packet List E xj Setting Refresh Export Synch Parameter Packet Name TimeStamp 00 Packet Name TimeStamp Packet Name TimeStamp DATA Packet Name TimeStamp Bus SPI Fig4 89 Protocol Analyzer SPI Packet List Packet Length and Packet Idling Length 1 SS channel is activated SS Rising Edze iz the start of the packet S5 Falling Edea iz Unknow End Falg start of the packet Unknow Start rian SPI SCK SS DATA e Packet Length Fig4 90 Packet Length Packet Length From Unknow_Start_Flag TimeStamp to Unknow_ End Flag TimeStamp Packet Idling Length From Unknow_End F
62. 3 UART Analysis UART Introduction The UART which stands for Universal Asynchronous Receiver Transmitter is a serial asynchronous protocol The UART is often time integrated into PC communication devices and it usually equips an EEPROM Electronic Erasable Programmable Read Only Memory for error checking proposes with other chips There are two concepts about UART which must be understood before performing any further tasks The UART protocol will first translate a parallel data into serial data for the UART requiring only one wire to transmit signals The transmission starts at a triggered Low position and there are 7 or 8 bits of data following afterwards To halt a transmission it requires a signal or multiple bits of logic 1 Odd number bit transmission requires odd parity error checking and even number bit transmission requires even number error checking Following the parity check is another data translation from serial data to parallel data UART also generates an extra signal to indicate receiving and transmitting conditions Furthermore since UART is an asynchronous communication protocol and data transmission may not be in bytes a complete UART signal Packet must consist of START DATA PARITY STOP Baud and TXD segments They are as following START When TXD is changing from HIGH to LOW voltage 1 bit DATA Users must decide the size of signal Packet segment from 4 to 8bits PARITY This performs three types of parit
63. 9 D ACK ONSA D ACK GXG6B D ACK OA7C D ACK OX8D D ACK GA9E D ACK ONAF D ACK OXC 6 D ACK BAD1 D ACK ONE2 D ACK 3 Bus1 110 2 952ms 6818 WRITE A ACK 6818 D ACK 6829 D ACK GX3A D ACKS 4 Bus1 1IC 3 56ms 8447 READ A ACK 6X7 B D ACK OX81 D ACK 8X92 D ACK OXA3 D ACK BXB4A D ACK BAC5 D ACK BADG D ACK GXE7 D ACK GXF8 D ACK GX 89 D ACK OX1A D ACK OX2B D ACK BX3C D ACK OX4D D ACK OX5E D ACKS Fig 3 12 Pure Data Form Capir be Hed a Mi M iip hee Caner Organs Paice T jaan Alege a a Fom rrian Eee odo q a i oe te Hee bev goad ind Cae T gwrel Fig 3 13 Capture Window This feature is equivalent to Alt Print Screen or Print Screen Capture to File Save the captured image as either a jpeg or bmp Clipboard Copy the captured image to the clipboard for use in other applications MSPaint Directly start MSPaint to view the captured image Capture Region Full Screen Capture everything on the screen Select Region After pressing the capture button a cross hair will appear on the screen Left click the mouse button to drag an area to capture Selection Line Color Click the color box to change the color Opposite of color Click this check box to ensure that the note text will be the opposite of the line color Note text color Choose the color of the note text Note Type in a note to attach to the captured image Capture Click the bu
64. Analyzer toe Zeroplus Techneablogy Coa Ltd User s Manual V3 09 Table 1 2 List of Functional Pins in Each Model LAP C LAP C LAP C LAP C LAP C LAP C LAP C 16032 16064 16128 162000 32128 321000 322000 rr ee ee A0 A7 Port B ne X y y X V y l y So N y cK J o y N y O GND Ni N N doa J o y N y doB J o y Ny y IOC V V V e Table 1 3 Definitions and Functions of Pins for All Models Connect a given external module to be analyzed Two pins used for grounding the Logic Analyzer with a given external module to be analyzed When the Logic Analyzer is about to upload data from the Read Out memory to the PC the R_O will send a Rising Edge signal of DC3 3V When the upload is finished a Falling Edge signal is sent When a trigger condition is established the T_O will send a T_O Trigger Out Rising Edge signal of DC3 3V When the memory is full a Falling Edge signal is sent When a user initiates a sampling task by clicking the RUN icon in the window or clicking the START button on the Start Out device the R_O will send a Rising Edge signal of DC3 3V When the Logic Analyzer finishes uploading a Falling Edge signal is sent Table 1 5 Definitions and Functions of Pins for Advanced Models 2 VDD Voltage Drain Provide 3 3 V for external modules by draining Semiconductor voltage from the Logic Analyzer Ext 1 O Module A Lean signals between an external model or device and
65. B Sampling position Data Length ous ia E w Min Tus blas 120us ae Miri 1 bit Man 32bit Cancel Default Help Fig4 105 Protocol Analyzer 1 WIRE Connect Speed Setup STEP 3 Set Data Direction Set the Data Direction as either MSB gt LSB or LSB gt MSB PROTOCOL ANALYZER 1 WIRE SETUP Busl x Configuration Facket Register Protocol Analyzer Color RESET PRESENCE PULSE DATA Pin Assignment Protocol 4nalyzer Name Bus Channel Protocol Analyzer Property Connect speed Data Direction f Standardi us High 0 2 us f MSB LSB LSB M5B Data Length fe bit kiin 1 bit Wan 32bit Sampling position ane E a Min Tus Mas 12043 as Cancel Default Help Fig4 106 Protocol Analyzer 1 WIRE Data Direction Setup STEP 4 Set Sampling Position Users can slightly adjust the sampling position of 1 WIRE This feature is applicable when the signal cannot be decoded The default value is 30us 147 FMO7I4A J RARE HARSS The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 PROTOCOL ANALYZER 1 WIRE SETUP Bus1 Xj Configuration Packet Register Protocol Analyzer Color RESET PRESENCE PULSE DATA Pin Assignment Protocol Analyzer Name Buz Channel Protocol Analyzer Property Data Direction Connect speed 0 Standardi us High 0 2 us MSB sLSB LSB gt MSB Data Le
66. Channel AO g Obit start Use the reverse data level for decoding Protocol Analyzer Property Baud Rate fi 25000 Percentage sample ez z Min 1 bps Mas 1 OMbps Users can vary the baud rate and set up the value as your requirements After End of Frame happens just begin to analyze When CAN Data for expansion combined Basic ID and ID T AutoJudge Baud Aate suggest adopting high sampling rate to carry on data sampling Protocol Analyzer Color START CONTROL Cancel Default Help Fig4 129 Protocol Analyzer CAN2 0B Setup Pin Assignment CAN 2 0B signal can be divided into CANL and CANH and the default is CANL Use the reverse data level for decoding Reverse the data Data Start It can be divide into two forms 111 bit start and O bit start Protocol Analyzer Property Baud Rate Input the baud rate by hand directly and the baud rate is an integer the default is 125000 the list includes 5 10 20 40 50 80 100 125 200 250 400 500 666 800 1000 2000 125000 and the biggest one is 10M Users can vary the baud rate and set the value as their requirements Percentage Sampling Input the position of the sampling dot in baud rate the default is 60 the range is 25 75 And the default can be adjusted by 1 the list is one option of interval 5 If the below is selected the decoding function can work after the end of the frame Combination extends format Progress Basic ID and ID
67. Conditional Full Period Conditional Positive Period and Conditional Negative Period 76 FMO7I4A REEL BR ea The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 STAT IET xj Channel Parameter Item Parameter Condition Parameter Warning Parameter Refresh Statistics Filter CHANNEL Full Period Conditional Conditional Conditional Start Pos EndPos Oo oO Oo oooococococcc 0co cno ooocococcc cc ccc Fo 0 0 0 0 0 0 0 0 0 0 0 0 Fig 3 142 The Numbers of Data Qualified by Condition Parameter Warning Parameter Warning Parameter a M Activate Warning Setting Min Max IY 10u IY 100us Frequency J ioH B fiookHe e Fig 3 143 Warning Parameter Set the conditions which will be marked to call users attention Channel Parameter Item Parameter Condition Parameter Warning Parameter Refresh D Statistics Filter Co oC oC 0 a 0 a oO 0 a 0 0 oO oO oO 0 a 0 0 a 0 oO 0 0 a 0 oO 0 a 0 0 0 0 0 0 a oO oO 0 Fig 3 144 The numbers of data qualified by warning conditions are printed in black otherwise in red T1 FMO7I4A gt SREB SRAA The Zeroplus Logic Analyzer gt Zeroplus Technology Co Ltd User s Manual V3 09 3 4 Customize Interface Section 3 4 presents detailed instructions pertaining to how to modify the Waveform Display Mode how to modify the Ruler Mode how to modify the Waveform Height and how to mod
68. Currently only the LAP C 32128 LAP C 321000 and LAP C 322000 support many Logic Analyzers working in series Also make sure that the signal lines power lines and ground line are properly connected Refer to Fig 1 11 Table 1 2 Table 1 3 Table 1 4 and Table 1 5 Q4 Why should bother grounding Where can ground A Grounding will protect the Logic Analyzer and the test board A proper ground may improve the quality and accuracy of your data Since it is impossible to avoid unwanted interference you may ground the Logic Analyzer with the test board to ensure that unwanted interference will equally disturb both the testing and tested devices ensuring a set of data that is still accurate Conclusion Every user of a product is a potential writer for Chapters 5 7 in this User Manual In fact this chapter is a composition of many unnamed electronic professionals especially experts 189 FMO7I4A 190 C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 6 FAQ 6 1 6 2 6 3 6 4 6 5 Hardware software Registration Technical Information Others FMO7I4A O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 Objective In this chapter common problems and questions are roughly classified into five categories Hardware Software Registration Technical Information and Others This is a backup resource for users especially those
69. Data F Read the Captured Data Fig 3 154 Correlated Setting Bus Signal Trigger Filter 987 25 be 309 985 369 oxos 0x08 Fig 3 155 An Example for Auto Close Auto Close With the cursor in the channel when users try to drag a Bar the Bar will stop at the approaching edge of the channel Rising Edge or Falling Edge Tip In the above example when dragging the A Bar the A Bar will stop at the Falling Edge of A1 82 FMO7I4A REA AG i BPR eB The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 UULU UU UU LI JL LELI LL fF LJ 20 Toe i Fig 3 156 Gridlines Show Gridline The gridlines will be displayed on the waveform area EET Fig 3 157 Tooltips Show Tooltip Leave the mouse over a waveform and the description will be shown Check for Update The Logic Analyzer software will automatically check for updates when being started Restore Defaults The Waveform Display Mode Ruler Mode Waveform Setting Correlated Setting and Data Process will return to the default setting 83 FMO7I4A PRA RA Bike Bl The Zeroplus Logic Analyzer Zeroplus Techneablogy Co Ltd User s Manual V3 09 3 5 Auto Save To save the captured data for a long time users can use icons on the tool bar box or menu For the dialog box go to File menu to click Auto Save or go to Tools menu to select Custom
70. E A ain bacasacd om atte dap E E 75 OA GUSTOMIZE MCN ACS x iicsicsessccanscirsiaccacaneaapbussdanartasarantoesasuniecaeanelsndassaanansavananbosgasaelesaaanaiaceseaasabendanauaanuacsmaias 78 3 4 1 Modify Waveform Display MOde cccccceecceeeeeeeeeeeeeeseeeeeeeeeeeeseaeeeeseeeeesseeeeeseeeeeseneeesaeeeeaeseeeeeeas 79 34 2 Modify Ruler 11 010 lt n aa ee eae eee ere 80 3 4 3 Modify Waveform Height amp Correlated Setting cccccccccseeeeeseeeeeseeeeeseeeeeeseeeeeseeeeeseaeeessaeeeesaaeses 81 2a AUO AN Se ears cig Gece ecient Seana sienna a apsmeniessatantpatasnaueetutsieuenmaiutassantusetcaenateessarmeriiuas 84 2o COren cence aces ee nce earctec E E A E 85 3 6 1 Modify Workaround Color ccccccseccccssecccseeeceeececcaeeeeseeseesaaeeesseueeessaueeessaecesseueeesseeeesanseesesseeeeesaaes 87 3 6 2 Modify Waveform COlOM srssssisisciresiirsiseisiisir irissen raanei EEEE E EESTE Ea E 88 3 7 The Flow of Software Operation a1nnnnnnnnnnsnnnsnnnennnrnrnenrnenrrrrrnrrrnrrrnrrrnrrinnrrnnrrnnrrnrrrnnrrnnrrrrerreerrrerrnennn 90 4 INTFOGUCTION to Logic ANALY SIS ssai a ea a Ea aaa aaia 91 A AOS IY a E E E E E antmeinaceee tdagecen seas 92 42 Bus OIC VAY SS ie ote cet ch tte EEEE bnew ee EENE EE TEE EDA AE EEE aE 104 Ao PHO ANTAN ea EES E a a 107 da BUS i AC ICSU EIS e E E E E E 110 Aa PUS ANANSI aeea EE E E E E ele aeadeides deaee 117 4 5 1 BUSANA SS oe E E E 118 4 5 2 2G ANIN SIG a a E E E E AS 121 4S3 VARTANA
71. Edge and the Period Delay are listed as Figs 4 144 4 145 4 146 and 4 147 FMO7I4A O PRARRRARE The Zeroplus Logic Analyzer Zeroplus Technology Co User s Manual V3 09 time o Filter Condition 5 delay time start sl L Fig 4 144 Start Edge Filter Condition Filter Condition delay time Filter Condition mses delay time Fig 4 145 End Edge Filter Condition period delay time Jo EL Filter Condition period delay time Le L Fig 4 146 Period Delay 171 FMO7I4A CD FRR EA i PRS The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 30 b2us l20 395us 58 46us 20 3594 EN xj m Filter Condition m Select Filter Delay Mode Select Delay Start Point Delay Time According to Filter Condition Start Edge fis End Edge Min 5ns Opposite of Filter Condition Period Delay Max 327 675us Display Bar Setup I Show Bar Bar Style origina i Bar Width fns OK Cancel Restore Defaults __ ter Fig 4 147 Filter Delay Setup The delay time of signal AO is 1 us which is the condition of the Filter Delay Setup Step 7 Signal Filter Time Interval 1 Click Show Bar to know the length of the tested and deleted signal as shown in Fig4 148 below Display bar Setup Bar Style Original hi Bar width Ens OK Cancel Restore Default
72. G fn Ba PRB Zeroplus Technology Co te Asynchronous Clock Internal Clack Frequency 2okHz te Rising Ed SOEHZ Sampling RAM Size RAM Size Channel number limited to 32 Compression Tip Signal Filter Setup Tip Click to enter the signal filter setup dialog box The Zeroplus Logic Analyzer User s Manual V3 09 Choose the frequency of the clock on the board of the Logic Analyzer Select External Clock to acquire data through external sampling Choose either Rising Edge or Falling Edge to execute the analysis process According to the users input the value of external frequency in software the software can count the relevant value about signal mode and frequency For example the value of the message the time scale and the zoom in and out will be the value of time mode Connecting the Synchronous Clock Use one of the single connecting cables to put one end on the testing board and the other in the LA as shown in the diagram opposite Check the box to compress all the data Compression is used to compress acquired data through a lossless compressor The purpose of this compression is to place more data in a limited memory than in an actual memory The compression rate of the Logic Analyzer can be up to 255 times This means that the maximum acquisition can be 32M Bits 128Kx255 32M Bits for each channel The chosen capacity of the memory 1MB means that the ma
73. Manual V3 09 4 5 6 2 Protocol Analyzer HDQ Packet Analysis x Configuration Facket Register Item Color Item Color V BREAK E n I RECOVERY DESCRIBE O mams vu Cancel Default Help Fig4 121 Protocol Analyzer HDQ Packet Setup Item Select the content which needs to display in the Packet List which includes BREAK RECOVERY ADDRESS DATA READ WRITE and DESCRIBE Color Set color for items which needs to display in the packet list FMO7I4A gt FERRARS RAE The Zeroplus Logic Analyzer ee Zeroplus Techneablogy Coa Ltd User s Manual V3 09 4 5 7 CAN 2 0B Analysis Preface Add Protocol Analyzer function to analyze CAN 2 0B transport protocols data CAN 2 0B serial transmission there are two signal channels CANH and CANL which match with baud ratio judge serial data If you want to change serial data into Bus format you need to analyze this function with LA a dialog box needs to be added you should set up a Protocol Analyzer CAN 2 0B dialog box CAN 2 0B Introduction 1 Brief Introduction Features CAN 2 0B Controller Area Network is an Asynchronous Transmission Protocol It costs low sky high use rate far data transmission distance 10KM very high data transmission bit 1M bit s sending information without appointed devices according to message frame dependable error disposal and detection error rule message automatism renewal after damage and node can exit Bus function on t
74. P 2 Busl wiRE 6210 Packet Name Timestamp 3 Bus 1 VWIRE 11660 OXD Fig4 110 Protocol Analyzer 1 WIRE Packet List Packet 1 It is commonly normal DATA which includes 1 DATA Packet 2 It is commonly normal DATA which includes 1 DATA Packet 3 It is commonly normal DATA which includes 1 DATA Packet and Idling Length Packet s TimeStamp is Reset 149 FMO7I4A O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 4 5 6 HDQ Analysis Preface Increase the Protocol Analyzer feature to analyze the Protocol Analyzer HDQ transmission protocol data Using LA analysis function the required serial data can be converted and presented in the form of Protocol Analyzer Therefore the software needs to add a dialog box so as to set up a Protocol Analyzer HDQ dialog box HDQ Introduction 1 Brief Introduction Features Protocol Analyzer HDQ is a non synchronic half duplex serial transmission which requires only one HDQ and uses a quasi PWM Pulse Width Modulation to verify the serial data Applications HDQ is commonly applied to the display interface for battery management 2 Protocol Analyzer Signal Specifications Parameter Value Name of Protocol Analyzer HDQ Signal Frequency Not fixed around 12MHz 13MHz and 19 2MHz Appropriate Sampling Rate 100MHz Same Data Time Per Bit Yes aNo Name of Syn Signals HDQ Data Verification Point P 190us converts to
75. Phe HAAS i BR Bl The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 High Quality Professional lnstruments ZEROPLUS 152 Fi JFM User Manual POo BASED LOGIC ANALYZER LAP C SERIES FMO7I4A a O PREP hei Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 1 Features Of ZETODIUS LOGIC AN AlY ZEN yss AA 5 Lil Package Contents ccia a Ae eee ne ee eee eee ae 6 EA WMO USO arate se ae cpa A eens ene E E E E 8 1 3 Hardware Specifications ccccccccccceccccesceceeceeeeeeeceeeecececeaeessaeceseeeeseacessaeesseeeeseeessacessgseessaeessueeeseeeseas 10 14 System ROO UIFC TICS os sen secdecext nescutettantesnt aana nAn raa EE a ARA aaa TA ERa aa EAren i arakan 12 1 4 1 Operating System Requirements ccccseccccssececcesececceesecceescecsuececseseeeseaucecseseesseseeessueeessaneneeesas 12 1 4 2 Hardware System Requirements ccccccccccseceeceseeeeseeeeeeeeeeeeeseeeesseeeeeseeeeesseeeeessueeeseeeeesaeseesesaeees 12 1 5 Device Maintenance and Safety ccccccccccssscccceeeecceeseecceuececceeeeeseaecesseeeecsegeeesseeeeseuseessansgeeesseesesseass 13 2 M aaO e a a ace aces eden 15 Zale DOWA MSAA esse e aa e uediedcoaansncdamneddietudadeueracsene 16 Be FONG ANS LVS O E S 18 Z3 TP A antec E EE E EE EE E E E E E 20 3 User IN Era E siar RSE EE 21 ar Monu a TO Ba eE E E E 24 oA FEDA VA s E E ee 71 2a Alcs FINS artes teresa deucalcein
76. Pos 835 iy B T 835 Compr Rate No i 113 K 25 i 199 eh 355 75 A we 668 25 4 5 380 T3 1137 tiita eT eT nT TTT ini Trigger Property Trigger Content Trigger Delay tri gger Range C Delay Time and Clock Trigger Delay Time End Pos 1845 20ns Min 20ns Max 335 50744ms Start Pos 203 Trigger Position Win 1 Max 16775372 10 v p gger Delay Clock T Pos 0 Start Pos 203 End Pos 1845 Note When more than one trigger pages are selected the trigger bar disappears from the view Cancel Defelt Help Fig 4 10 Trigger Page and Screen 1 Es ZEROPLUS LAP C S2128 S H ouonesononss LaDoct s loj x Display Pos 1736 Pos 2033 v B 30 v Display Range 1025 2519 B Pos 2063 v Compr Rate Ho h 1579 25 1735 5 1891 75 2204 25 2360 5 2516 Ersecneapecensscsnensssenssesnesseses aca as 2 Min 1 Max 8192 Trigger Position C Delay Time and Clock Trigger Delay lim 20ns Start Pos 1025 End Pos 3073 Min Z0ns Max 335 52382ms Trigger Delay Clock fi Min 1 Max 16776191 SS 50 v T Pos 0 Start Pos 1025 End Pos 3073 Note When more than one trigger pages are selected the trigger bar disappears from the view Cancel Default Help Fig 4 11 Trigger Page and Screen 2 2 Delay Time and Clock Click the Delay Time and Clock
77. R AG ARRE Zeroplus Technology Co te List Data Mode d Tip The data for list mode are so many to be convenient for users that there is adding a List Data Mode function The formats for the List Data Mode are All Data Sampling Changed Dot Compression and Data Changed Dot Compression All Data It is the present display mode Sampling Changed Dot Compression Take the sampling changed dot as the compression data reference dot Data Changed Dot Compression Take the present data change dot as the compression data reference dot PSF Vcr SyivuaeuYyS j Tio the Next Edge Go To The Zeroplus Logic Analyzer pe User s Manual V3 09 AddBar Alt A J I I I T T 0 T T 5 Delete Bar Alt B olololololoaoflolfloaloa 0o o0 0 0 0 0 0 0 0 a Zoom E 0 0 0 0 0 0 0 0 0 o o 0 0 0 0 0 0 0 amp Hand H 0 o0 0 0 0 0 0 0 0 R Normal A x 0 0 0 0 0 0 0 00 g Zoom In Fg ololololololololo K zoom Out Fe 0 0 0 0 0 0 0 0 0 a o o 0 0 0 0 0 0 0 FR Show all Data Fig 0 0 0 0 0 0 0 00 x Previous zoom Gritz 7 Data Format Waveform Mode k 4 5 i i o i A A A A 0 List Data Mode v AllData 0 TTT T T od oO OU n al 4 1 1 1 o olo Sampling Changed Dot Compression i AET e a a e a E a Data Changed Dot Compression 0 Oo a0 1 1 1 0 00 0 ITDA 1 0 o0 0 0 0 0 0 0 0 0 0 0 0 1101 1 0o o 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
78. RIE lt i GM orars Rae ay Be Te 2 EEE Trigger Delay 1 Font Size 12 7 A Pos 261135 v A T 261135 v Scale 851 2793428 Display Pos 12144 Total 524288 Display Range 9138 33426 B Pos 261105 B T 261105 Bus Signal Trigger Filter 4881 555629 158 3631 238 7887 63512144 0316400 4220656 82 2491 3 2229169 61 334 I E us Sg fe ZEROPLUS LAP C 321000 S H 000000 0000 UART als A ag Fig 4 77 Waveform Analysis 131 FMO7I4A REA Ae i BR eB The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 4 5 3 2 Protocol Analyzer UART Packet Analysis xi Configuration Facket Register Item Color Ens Min 10ns Max 10s e Time gt im L a C ee Te Fig4 78 Protocol Analyzer UART Packet Setup DATA List Data field captured by Bus in the packet display PARITY Display parity check in packet DESCRIBE Error description to any field format or data bit Packet Idle Time When the check box is selected the default value is 5ms Specifically when the Packet Idle Time is activated the packet will be divided again according to the Packet Idle Time If the Time Length between the previous packet and the next packet is more than 5ms the two packets will still be divided or the two packets will be merged into one packet It is a Bus Packet List view which includes 4 formats which UART happens
79. Running Text Ads function News Activity Let users learn the activities of our company Production News Let users learn the latest products of our company Note If both News Activity and Production News are turned on The Running Text Ads will play News Activity prior to Production News and play the news in order the whole process plays repetitively Wavigator Tip The Navigator Window is displayed under the waveform display area when activating the Logic Analyzer The Navigator displays the waveform length of all the captured data it only can display the waveform of the data of four channels In the Navigator The Zeroplus Logic Analyzer User s Manual V3 09 Window Help f Waveform Display 4AQ0KHz nmu oon gaj Listing Display ETETE Ta ou Be Hot Hews Window Turn On ra Hews Activity ra Production Hews Warigator Cascade Horizontal Vertical screen Display 1 Lalloci 1 2 Lalloel 2 gt LaF ce TIF TE fa SOOO 1 DET ae E Sm Bids Byasa Tigger kagi Pane piala isim fely alt ed eee ee en ejo Sl fiom ea Bo ea ams LEAD A tons JT SRE A E b Hegt Trigger Belay line Fost Size H7 Saale liaa Bplay Pip Gua h Fa 1 See E A T EL 20 tun hier hags Pen Then D Foa a as B fit aw filie E iiss Hima hasard t Para Sri r Aake ayy ee ae ee aris Tas E dana E ET i LUIA HERNI IILI eed eee TELIT Hf Leek daa VURAL p a e o a e a t
80. S The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Step4 Choose the position to start the search by selecting one of the following Start At Ds T A B C etc End At Dp A B C etc Then click Next or Previous to search it When Found Choose a Bar to mark the result A B C etc Step5 Click Statistics to show the number of instances of the search results Note It is available only when searching through a Bus Seale 0 25 Display Pos 823 A Pos 823 Ae i e BES Total z048 Display Range 829 815 B Fos 15 ad id It S is DEE TEER va TERI z e24 BD ARS 5 TEZI Ta THe z TELS one xs oxa ons Y oxe Yor ox oxo Y oxa J owe m a P avefore Find Activate the Function of Chain Data Find Bus Signal Name Next Previous Close Main Max Value _ FRFFFFFF Statistics Fig 3 134 The A bar is placed at the 0X08 of Bus1 where the condition of the Waveform Find is set The Statistic of Waveform Find shows a 128 Scale 0 25 Display Fos 662 A Pos 662 A T 662 Total 2048 Display Range 666 654 E Pos 15 E T 15 F Taveform Find D Activate the Function of Chain Data Find Bus Signal Mame E_ usi Next Previous Close Start At End At When Found Arouet bs Dp Bus Item Min am Max Value Address 662 Fig 3 135 The A bar is placed at the OX6A of Bus1 where the condition o
81. Tools Window Help ee x fmn Hoi se Filter zz Bus Width Filter Tata Contrast Noise Filter None Pi Find Data Value CtrltF OK EA Find Pulse Width Fig4 150 Noise Filter STEP 2 Transmit the tested signal to the Logic Analyzer as the figure below EEE E FEPEFEREPEPEPEPE EEE EALEEP LILLE LP LEP Bus Signal Trigger Filter a I 1 1 i i lili i i l m Fig4 151 Tested Signal STEP 3 Filter waveforms that are not bigger than 5 clocks x Moise Filter None DR Noise Filter S Noise Filter 50an 127 OK Cancel Fig4 152 The condition of Noise Filter is 5clock STEP 4 After filtering the waveforms that are not bigger than 5 clocks are deleted 173 FMO7I4A l 1 peH ROSRAS The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 Bus Signal I 2 10 a a 5 10 15 20 1 e EE A 1 I I 1 1 i i i i 1 1 1 1 I I 1 1 i i i 1 1 1 I I I 2048 Fig4 153 Waveforms after Filtering STEP 5 Reserve the original waveform open the Noise Filter window and then select None the waveform will be restored Hoise Filter x Moise Filter None Fig4 154 Restore the Waveform 174 FMO7I4A O PRARRRARE The Zeroplus Logic Analyzer Zeroplus Technology Co User s Manual V3 09 4 9 Data Contrast In order to make users analyze the Data and contrast the differe
82. a Pulse Width Trigger Module Option Tip See Section 4 1 for detailed instructions Pulse Width Trigger Module Set a trigger condition for a single channel and the signal in this channel can be triggered in the predetermined range However this function is required to use with the hardware of the Pulse Width Trigger Module If you want to learn the detail please refer to the Specification of the Pulse Width Trigger It is an optional function That is to say this function can be used in the Modules LAP C 16032 LAP C 16064 LAP C 16128 LAP C 162000 LAP C 32128 and LAP C 321000 after registering And for the LAP C 322000 it is not name necessary to register as it can be used for free e a Set the trigger condition as Don t Care See Section 4 1 for detailed instructions High Set the trigger condition as High See Section 4 1 for detailed instructions eee Set the trigger condition as Low See Section 4 1 for detailed instructions 37 FMO7I4A PRE BS AS i ARAE Zeroplus Technology Co te Rising Edge c Falling Edge Either Edge ye Trigger Property Tip Tip T lt N A N A Trigger Content Setup Icon Description E Decrease trigger position Increase trigger position Trigger Page Trigger Count Trigger Delay Icon Description N A Trigger Delay 38 The Zeroplus Logic Analyzer User s Manual V3 09
83. a driver program that auto detects the chipset at the beginning of the installation Q2 Why does the installation software keep giving an error message saying that don t have enough memory A This kind of problem happens in many hardware installations Turn off multimedia programs such as Media Player media decoders media encoders and so on If there are any multimedia icons in the system tray see the far right end of the START menu taskbar remove them The Logic Analyzer software will run better in memory locations from 64 to 512 MB Q3 What should do if want to share this software interface with all users of my computer after installing it A The shortcut is removing the software interface and then reinstalling it By default the program is available for all users Q4 My HDD is modest which software components are absolutely necessary A Choose Custom as your setup type Next unselect items such as examples and tutorials You must install at least the Main App application Q5 My MS Windows system will not accept the driver what should I do A Double check that you run the correct Setup exe from the folder that corresponds to your hardware and MS Windows version Visit our website for the latest updated or debugged software If you are running this program on a virtual machine the virtual machine may not support the amount of hardware addressing In this case try it with a machine that is physically running a Win
84. aIYSIS iera a a a a a e aE aa 129 2 FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Technology Co User s Manual V3 09 Ao SPRATA ee ee een ee eee ee eee eee eee eee eee 134 4 5 5 ANWR Analysis coer cts Seen clea a seed ee die ds escalate eee cctce Sedge et acess ecg eee el 140 72163 Fo mm 00 07 2 9 gt LV gt en ee ene E ene nee eee ee eer eree eee 150 tOr MAIN 220 AW SS asec ecoe se ateccencaenntessaanseeccesnase cetanceavanseuensacncsenczevasseueseean cue areanabeccacatuessacatecseasaenees 157 7d 6 gummed 70 91 6 21 1 6 tee eee ee Ce ee ee ee ee ene ee ee en eee nee ee ee eee 167 4 6 1 Software Basic Setup Of COMPIeSSION ccccecccceeccceeceeeeececeececeueeeeeeeeseecesecessucessueeeseeeesensetsaeees 167 4 7 Signal Filter and Filter Delay va ssscsccciesecvexencecwanecceceeteacs vse biecestededceuedeeceiaeesecesec dudes teleretessestioicdeee ives 169 4 7 1 Basic Setup of Signal Filter and Filter Delay ccccceccccceeeeeeeeeeeeseeeeeeseeeeeeeeeeeeseeeeesseneeesaaneeees 169 BO WNOISS FT aspaece sere aencenconstanerd E E E E source wearersierdaccad 173 4 8 1 Basic Software Setup of Noise Filter cc ccccecccsecccceeeeceeeeseeceeeeeeeseecesecessaeesseeeeseeeeseusessnseessaees 173 Be WALA CO aS sere at crtcae N E E 175 4 9 1 Basic Software Setup of Data Contrast cccceccccccccceececeecececesaeeeeeeeeseecesseeeeseeeeseusesseesseeessanees 175 4 10 Refresh Protocol Analyzer eccecec
85. address for storage 6 The last byte MSB is used to store CRC FMO7I4A i PHRSR E The Zeroplus Logic Analyzer 145 Zeroplus Technology Go Ltd User s Manual V3 09 4 5 5 1 Software Basic Setup of Protocol Analyzer 1 WIRE PROTOCOL ANALYZER 1 WIRE SETUP Bus1 Configuration Packet Register Protocol Analyzer Color RESET PRESENCE PULSE DATA Pin Assignment Protocol Analyzer Name Bus Channel Protocol Analyzer Property Connect speed Data Direction f Standardi us High 0 2 us f MSB LSB 0 so Data Length fe bit biin Bit blan 32bit Sampling position 2 E Uae Sie Min Tus Max 1 20us ii Cancel Default Help Fig4 102 Protocol Analyzer 1 WIRE Setup Pin Assignment OWIO Because there is only one channel for a signal there are only two setup fields Protocol Analyzer Name Display the name of the selected Bus Channel Preset as AO Data Direction MSB gt LSB From High to Low bits LSB gt MSB From Low to High bits Connect Speed Standard 1us High 0 2us Protocol Analyzer Color RESET PRESENCE PULSE DATA FMO7I4A FEHR ARAE The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 User Interface Instructions Set up the Protocol Analyzer dialog box which is set as the steps of I2C PROTOCOL ANALYZER 1 WIRE SETUP Bus1 4 x Configuration Packet Register Protocol Analyzer Color
86. ame Timestamp Data Data Data Data Data Data Data Data Data Data Length 6 Busi us 973 J oO 1 o 1 o 1 o 1 o 1 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length po tet totyratotyratotato fs E Fig4 41 Bus Packet List 1 View Specifications Packet Name and TimeStamp can be selected to display from the Packet List Setting dialog box Packet List the order of Packet Name Display the name of Packet or the Filter Display Bar TimeStamp It is the starting point of the Packet Tip The rest name and content are supplied by Plug BUS Packet List l xj SLAVE ADDR READ A NACK Describe Packet Name TimeStamp 2 Bus1020 5231 SLAVE ADDR READ A NACK Describe READ A NACK ADDR NACK Packet Name TimeStamp SLAVE ADDR READ A NACK Describe 3 Bus 12c 9165 READ A NACK ADDR NACK Packet Name TimeStamp Bus1 2C 16367 Packet Name TimeStamp Bus1 2C 20290 SLAVE ADDR READ A NACK READ A NACK ADDR NACK SLAVE ADDR READ A NACK READ A NACK ADDR NACK Fig4 42 Protocol Analyzer I2C Packet List Setting It is used to open Packet List Setting dialog box 111 FMO7I4A P Re Tee ih BR eS The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 Refresh Press this button the list view can renew automatically Export Export the workspace into Text txt and CSV Files
87. ame Timestamp Data Data Data Data Data Data Data Data Data Data Length E o t o 1 o 1 o 1 o 1 Packet Name Timestamp Data Data Data Data Data Data Data Data Data Data Length o 1 21 o 1 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length 1 1 1 1 1 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length oO i 1 1 Packet Name TimeStamp Jata data Jata Jata jata Jata jata Er Jata Jata Length 1 1 1 1 1 Packet Name TimeStamp ata Jata Jata Jata Jata jata jata Jata Jata Jata Length 6 _ Busius 973 1 1 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length Poot t totyttotato tito 1 al Fig 4 50 Synch Parameter on the BUS Packet List At the same time a Synch Parameter Setting dialog box is added 114 FMO7I4A LD PRES i Bike ol Zeroplus Technology Co te Syuoch Parameter Setting x Synch Point of Packet List Synch Point of Waveform Area f Top eo Middle Middle Fig 4 51 Synch Parameter Setting Dialog Box Activate Packet and Waveform Synch The default is not activated Top When the Packet and Waveform Synch is activated the synch point in Packet List is the top packet segment which is displayed by list Middle When the Packet and Waveform Synch is activated the synch point in Packet List is the middle packet segment which is displayed by list Left When th
88. ameter 75 FMO7I4A FREH ARAE The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 Channel Parameter x my 6 5 4 3 2 1 0 Port fv fv vv fv fv fv fv Iv PortB V M fv Vv Ww Iv Pte V fv fv fv fv vw Ww Iv PotD M M fv Vw Ww Ww Iv Pere fo fe fe lei fs ey fe Pore apo eaten fc Jig FO Pcs cs fade ftp re is Nas a Fis es ie oe Fi partia pm SL Net a id a a a Poret Sae Ss a a a Gey Ef E E fg he oem odes E ope Le ss RQ LP ep LS Se eh om oo Oe lie lee EN IS Bf Sle SI Porem ee fe hee ie oe Joe is fs eis Paven Sp a fan fe Ped fice jee fo ed a porto mia m fo Mies seed use fg pas Portes he e fen ss oe e e ie Clear all OK Cancel Fig 3 139 Channel Parameter Allow the choice of pins in which port will be included in the statistical analysis of a test run ltem Parameter ten Paremeter x Barennnnnnnnnna W Full Period W Positive Period W Negative Period W Conditional Full Period W Conditional Positive Period W Conditional Negative Period J Start Pos W End Pos W Selected Data coel Fig 3 140 Item Parameter Allow the choice of items which will be considered in the statistical results Condition Parameter Condition Parameter l x Conditional Full Period e e a a Conditional Positive Period Sun i con Conditional Negative Period mo ete a cael Fig 3 141 Condition Parameter Allow the setting of time intervals for
89. annels AO A7 BO B7 CO C7 DO D7 change into the 64 channels AO A7 BO B7 CO C7 DO D7 EO E7 FO F7 HO H7 I0 I7 channels EOP LiP CHES Ooo oo CLs oa BT ta pli Feige pipar hiap pete faala fiski Hilf Dema mh ek iMh e e al fous ove de Fues fi 1 um 3 F i a aOR r Ga T Hecht fia f Tarar beer i haplar Fee i Pis mii E EERS H ijr s Png Sel ba cp Lap Hrg Fos Ft Pout pad Trapa File a ni he od ao i i AUF aw iD rE T FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 5 Troubleshooting 5 1 Installation Troubleshooting 5 2 Software Troubleshooting 5 3 Hardware Troubleshooting 186 FMO7I4A O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 Objective In this chapter troubleshooting is divided into installation software and hardware issues These troubleshooting questions and answers depend not only on our engineers but also on end users such as students engineers technical manual writers and others 5 1 Installation Troubleshooting Q1 Why itis not prompt when insert the driver CD into my CD ROM A At this stage the driver CD is not auto executable The primary issue here is a chipset problem Though these six Logic Analyzer models seem only different in model number they are quite different in firmware and chipsets Due to installation procedures see Chapter 2 we are unable to compile
90. ata Compression Signal Filter Setup Channel number will be limited to 32 Cancel Restore Defaults Help Fig 3 20 Sampling Setup See Section 4 1 for detailed instructions Tip i ooo Icon Description cK bii sOMHz2 t SRRA ra Decrease Fll4 RAM Size Fig3 21 RAM Size ha Increase Choose the RAM size and the internal clock frequency ah RAM Size from the pull down menus Decrease ae Internal Clock Frequency Increase Internal Clock Frequency RAM Size The amount of the acquired data that can be stored by the Logic Analyzer depends on the amount of the allocated RAM The total depth of the memory for the LAP C is 128K Bits in each probe If the Logic Analyzer starts gathering data with a 128K memory range it will take a long time to find the required information In order to avoid spending a lot of time gathering data select a smaller RAM size The RAM size options are 2K 16K 32K 64K 128K and 256K So if gathering data with 128K takes a long time why does 256K make sense The reason for this extra RAM size is to cope with the fact that a few of the 1 16 channels may have a large data input Tip Use the pull down menu to choose the speed of the clock Clock Source Asynchronous Clock on the board being tested The sampling frequency should be more than 4 times higher than the signal to be measured so that the waveform duty cycle depiction will be accurate FMO7I4A gt fie FA
91. ation of at least 6Ous and a recovery period of 1us 4 Typical 1 WIRE Conversation model can be summarized as below A typical 1 Wire conversation Roel Puk Presence Puks Moat Meit Pula ka JT TO SCALE Na Hi r Fa Reset Sequence LET ROS PUR VOR L E o MEMORY Comat Code Unique FURCTHOM Gevice E selecied Command Code Diagram L trpical 1 Wice coena sequence Fig4 101 A Typical 1 WIRE Conversion 1 Master keeps Protocol Analyzer at low signal standard speed 480us high speed 48us as the Reset Pulse 2 Then Master releases Protocol Analyzer and locates a Presence Pulse responded by any online Slave 3 The above two points are Reset Pulse and Presence Pulse which can be put together as a Reset Sequence 4 If Presence Pulse is detected the slave location will enable Master to access Slave using the Write 0 or Write 1 Sequence 143 FMO7I4A C O Phe eho in Blea The Zeroplus Logic Analyzer 144 5 Zeroplus Techneablogy Co el User s Manual V3 09 1 WIRE Serial Number 1 Every 1 WIRE Slave has a unique laser memory 2 The serial number is 64bits 3 The serial numbers are 8bytes in total located in three individual which are illustrated as below 64 bit Registration ROM number B hit CRC 48 bit Serial Number 8 bit Family Code MSB LSB SK S MSB LSB 4 Starting from LSB the first byte is for family code which is used to identify product categories 5 Next the 48bits is the only
92. below PARITY clews whether users start PARITY or not BUS Packet List Setting Refresh Export Synch Parameter Packet Name TimeStamp DATA PARITY Tx Bus UART OxCS ODD PARITY Packet Name TimeStamp DATA PARITY Tx Bus UART 1247 0X85 ODD PARITY Packet Name Timestamp DATA PARITY Describe Tx Bus UART 2392 0X7B ERROR 1 Parity Error should High Packet Name TimeStamp DATA PARITY Describe Tx Bus UART 3536 OxB6 ERROR O Parity Error should Low Fig4 79 UART Packet List Packett It is commonly normal Data which includes 1 DATA and 1 PARITY its parity is ODD PARITY Packetz2 It is commonly normal data which includes 1 DATA and 1 PARITY its parity is ODD PARITY Packets It is the state of PARITY ERROR the Describe is Parity Error should High Certainly EVEN and ODD are impossible to present to the same Bus It is used for exhibition here So EVEN and ODD appear at the same time Packet4 It is the state of PARTIY ERROR the Describe is Parity Error should Low Packet Length When judging to the start of UART it is the packet TimeStamp 132 FMO7I4A PREM AG Blk ee The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 State 1 Having Stop The data start is regarded as The Unknow Register f is Unknow_End Flag Packet Timestamp UART RIT X Packet Lenath Fig4 80 Packet Length State 2 No Stop de Unknow Register ia
93. bits and allows Bus node to restart Bus transmission after Error happens Fig4 127 Error Frame Overload Frame There are two kinds of Overload conditions which both lead to the transmission of an Overload Flag The internal conditions of a node which require a delay of the next Data Frame start during the first bit of Intermission Overload Flag can send six 0 which may damage Intermission format so that it makes the other nodes know node sending Overload Flag at this time When Overload Flag is sent out Overload Delimiter can send eight 1 others send seven 1 after finishing either Fig4 128 Overload Frame Interframe Space Interframe Space is divided into Intermission and Bus Idle Intermission is three 1 It is impossible to send any message during this time except Overload Frame The Bus is recognized to be free the period of BUS IDLE may be of arbitrary length And any station having something to transmit can access the Bus When a node is at the state of error passive the node will send eight O after INTERMISSION and other node have the chance to retransmit themselves information 160 FMO7I4A REA AG i ARRES The Zeroplus Logic Analyzer Zeroplus Techneablogy Co Ltd User s Manual V3 09 4 5 7 1 Software Basic Setup of Protocol Analyzer CAN 2 0B PROTOCOL ANALYZER CAN 2 06 SETUF Bus1 Pin Assignment Data start Protocol Analyzer Hame Bus i 111bit start
94. c Software Setup of the Logic Analysis Task 1 Clock Source Frequency and RAM Size Setup Step1 Click iM icon or click Sampling Setup from Bus Signal on the menu bar the dialog box as shown in Fig 4 1 will appear Bys Signel Trigger Run Stop Data Tools Window Help b bb i 2k i f100MHz 2 OO TT x Group int Clock Source Uneroup Asynchronous Clock preeeeeseseeseesesesoseeseeseesesg Expandi I a a Collapse Frequency 100MHz Format Ro Synchronous Clock Rename External Clock Rising Edge Frequency Falling Edge Min 0 001Hz Max 100MHz Note The external clock voltage level is the same as the port 4 trigger level Sampling RAM Size Compression Mode Signal Filter RAM Size 2K v Data Compression Signal Filter Setup Channel number will be limited to 32 foply ka Cancel Restore Defauts Help Fig 4 1 Clock Source Step 2 Clock Source Frequency Setup Internal Clock Asynchronous Clock Click on Internal Clock and then select the Frequency from the pull down menu to set up the frequency of the device under test DUT The frequency of the Internal Clock must be at least four times higher than the frequency of the Oscillator on the DUT Or select the frequency 2o0me2 from the pull down menu on Tool Bar as Fig 4 2 shows Tip Connect the output pin of the oscillator from the t
95. c3 loj x a File Bus Signal Trigger Run Stop Data Tools Window Help 8 x Dee So Re g ER E 120K MCM v nn mn 50 wv iq ps Page 1 M S ml mls r K Cialis o 1953125 mR oe Oe BY Te t FA le E Es 4 Heient 30 Trigger Delay 1 Font Size v Scale 512 Display Fos 10240 A Pos 6452T v A T 64527 v A B 30 v Total 131072 Display Range 2560 23042 B Pos 64497 nd B T 64497 v Compr Rate No E T rare iter a fe ear UL WUE UUUU LULIUUU LIU UU LIU U u UUL U a 15360 17920 20480 23040 f penen Pia Naa AN py i B gt Setting A Export T Synch Parameter zl ST EX RE OV PR Packet Name TimeStamp BASICID BAMA ID MARA REO oC ATA 249 SRR IDE 1564B8 RTR RB1 REO 8 DATA CRC ACK Describe D495 ack EXTEND gt Ready End Ic onnected Fig4 138 CAN 2 0B Packet List Displayed with the Waveform 166 FMO7I4A 167 PRE ESAS i BPR The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 4 6 Compression The compression function enables the system to compress the received signal and has more data stored in per channel 4 6 1 Software Basic Setup of Compression Step1 Set up RAM Size Frequency Trigger Level and Trigger Position as described in Section 4 1 Step2 Set up the trigger edge on the signal or the Bus to be triggered Step3 Click i icon or click the comp
96. capacitors on your main board or power supply 191 FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 5 If the problem is the power supply we strongly recommend purchasing a power supply with a hardwired voltage transformer rather than a voltage regulator For power supplies with the same output power those built with hardwired voltage transformers are usually much heavier than those relying on voltage regulators H14 What are the time settings for Setup and Hold A Setup Time 0 05ns 0 25ns Hold Time 0 02ns 0 08ns Clock High requires a minimum of 0 31ns Clock Low requires at least 0 47ns 192 FMO7I4A _ SRR SIRO The Zeroplus Logic Analyzer O Zeroplus Technobogy Co Ltd Users Manual V3 09 6 2 Software SW01 Why is the compression function not enabled by default A Mostly to avoid significant errors when testing signals with high variability or measuring a certain channel for a long time period SW02 What is the purpose of the compression function A The compression function measures signals that vary slightly over a long period SW03 Can I enable Trigger Page and Compression Function simultaneously A Yes you Can SW04 When should I use the Bar function A This function allows you to highlight a segment of a waveform so that you can have a closer view Depending on the configuration of Waveform Display Mode under Tools C
97. csv Synch Parameter Open the synch parameter setting dialog box and activate the packet and waveform synch function 2 Display Protocol Analyzer Packet in Order Tip The below view are Protocol Analyzer 12C the packet is determined by the position of the TimeStamp x Setting H i Export Synch Parameter fe Packet Name TimeStamp SLAVE ADDR READ PENAC Describe L 1 Busig2c 477 7F READ A NACK ADDR NACK Packet Name TimeStamp SLAYE ADDR READ A gt NACK Describe Busid2c 5231 7F READ A NACK ADDR NACK Packet Name TimeStamp 3 Busiq2c 9165 Packet Name TimeStamp Fo 4 Busiq2c 16357 Packet Name TimeStamp 5 Busig2c 20200 SLAVE ADDR READ A NACK Describe 7F READ A NACK ADDR NACK SLAVE ADDR READ A NACK Describe 7F READ A NACK ADDR NACK SLAVE ADDR READ A NACK Describe JFL READ A NACK ADDR NACK El Fig4 43 TimeStamp Tip When the Display Bar of Signal Filter is activated the Bar should be displayed in the Bus Packet List and also the TimeStamp ADDRESS and length of the Bar will be displayed 3 Packet Idle and Packet Length Packet Idle Packet interval time Packet Length Packet time length When those above two items are to be displayed it only chooses one of them to display which is controlled by Plug Because it is impossible that every Protocol Analyzer packet has registered timestam
98. d of device We made numerous enhancements and made it available to the public Conclusion This chapter is full of hard facts for engineers The contents of this version of the User Manual may look more different than the one on the web Every engineer finds new problems new solutions or other issues during real life applications Though there are dozens of questions here we look forward to your feedback which is important for future versions It may help us produce more efficient and accurate devices so that we will offer you much better service 199 FMO7I4A O PREHR IRA Zeroplus Technology Co H 7 Appendix 7 1 Hot Keys 7 2 Contact Us 200 The Zeroplus Logic Analyzer User s Manual V3 09 FMO7I4A O PRBS ALE PRA Zeroplus Technology Co H Objective The Zeroplus Logic Analyzer User s Manual V3 09 In this chapter users will learn the functions of all defined hot keys in the software interface of the Logic Analyzer 7 1 Hot Keys Table 7 1 Hot Keys 1 Statement Move the A bar to the center of the waveform area select A bar by the cursor Move the B bar to the center of the waveform area select B bar by the cursor Move the T bar to the center of the waveform area select T bar by the cursor Change the mouse mode to Zoom Change the mouse mode to Hand Table 7 2 Hot Keys 2 Hot Key Equivalent Orders A Go to A Bar B Go to B Bar T Go to T Bar E Change to Zoom mode H Change t
99. de Screen and Double Screen Display Fortified Functions Support the SDK for Data Contrast Support the Multi page Multi device and Multi sector Analysis For Memory Support more new Languages Support the Pulse Width Trigger Module for LAP C Series Support the Protocol Analyzer Trigger for LAP C Series Bug Fixed Detailed description invites reference ReadMe Detailed description invites reference company website Copyright C 1997 2010 ZEROPLUS TECHNOLOGY CO LTD Website http www zeroplus com tw Fig 3 110 Copyright About ZEROPLUS Logic Analyzer Open the website of Zeroplus Technology to know more modules ZEEOPLUS Logic Analyzer OQ ZEROPLUS LAP C Serial Standard V3 08 Welcome to use ZEROPLUS Logic Analyzer The document includes the version information of the software New Functions Enhanced Functions Modified Functions x SNIdOYZZ JV Show tips at Startup Close Fig3 111 Software Version Information Display Window FMO7I4A i PHRSR E The Zeroplus Logic Analyzer Zeroplus Techneabogy Co Ltd User s Manual V3 09 Right Key Menu Item Detail Menu amp Dialog Box Right Key Menu on the Bus Signal iM Sampling Setup Column if Channels Setup oe Bus Property Analog Waveform Tip Group inte Bus Pte tts The Right Key menu is added on the Unen mip GUE Cista basis of the Bus Signal menu So the ee Copy Charnel function of Sam
100. de can be selected There are four options Binary Decimal Hexadecimal and ASCII Step3 Trigger Mark Setup To find the item in the Bus better users can activate the Trigger Mark function after starting Bus Trigger the trigger mark is shown with T bar According to the number of the trigger position the T bar is displayed in order TO T1 T2 T3 T4 and the color is red as the image below 1 Bus The trigger condition is 0 the red T bar displays the trigger condition in order 100 FMO7I4A 101 PRE eee ih Bee The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 he Filter p N 3e se AP 78 100a oe ese 117 188 HA o 719 E 25 175 re rozo YX oxo XY oxo Xf oxo XX oxo X oxo Xf oxo Xf oxo _foxo Fig 4 20 General Bus Trigger Mark 2 Protocol Analyzer I2C The trigger condition is Data 0 the red T Bar displays the trigger condition in order CUI ee pp E S Fig 4 21 Protocol Analyzer Trigger Mark Tip The Trigger Mark function is available for the LAP C 162000 LAP C 322000 Modules and it is not available for the LAP C 16032 LAP C 16064 LAP C 16128 LAP C 32128 LAP C 321000 Modules FMO7I4A PREAH BhRe el The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Task 4 Bus Signal Trigger Condition Setup Highlight a designated signal and then set its required trigger condition 1 Left click to set the signa
101. design which can make the GUI Interface and Main Program Interface switch freely When users activate the Data Contrast function the software will search whether there is a GUI DLL or not then it can judge whether there is a user defined Interface If there is a user defined Interface the GUI DLL will take effect if there isn t the embedded Data Contrast Interface will be activated STEP 2 Display the contrast results in the Data Contrast dialog box Tip After pressing Perform Contrast it will display the contrast information in the contrast result The below contents of the box are the contrast information The information is relative simpleness if users don t want to understand more details you can know whether the signals of the two contrast files are completely the same or not Data Contrast Settings x w Activate Data Contrast Contrast Files Basic File tale Contrast File 2 a Error Tolerance None Contrast Beginning Point tf T Bar Beginning of Data Contrast Result Error Stak A BIBI ia Pass M Roll the contrast waveforms synchronization Pin Assignment M Display files the contrast differences I Display Files horizontal Perform Contrast Fig4 156 Display the Contrast Results in the Data Contrast Settings Dialog Box AO AO FAIL It indicates that there are differences in the channels of the two files BO BO PASS It indicates that
102. dows system 187 FMO7I4A Q1 A Q2 Q3 Q4 188 C O PRE eh in BR The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 5 2 Software Troubleshooting Can I run the program even if I don t have the Logic Analyzer hardware Yes you can You can run the program under the demo mode See Fig5 7 ZEROPLUS Logic Analyrer X Hardware Searching Failed ev Fig 5 1 Select Run Demo if you do not have the actual hardware I am running a graphing program and software at the same time Whenever I try to make a screenshot of my work it keeps telling me that I have insufficient memory space what is wrong A few users have reported similar problems We are not certain what causes it or how to fix it However we have found that if there is a defective address within 128 MB to 512 MB in your physical memory your software might signal End of memory Thus the program will warn you about insufficient memory Test your memory with a varied memory testing program Or take a screenshot close the program paste it to the graphing program and re open the program A part of the background picture remains within the Waveform Display Area especially when running the program in demo mode What s wrong with it Your machine may have a memory management problem with either your physical RAM onboard or the RAM on your video card Turn off any other multimedia of graphic programs and then re ru
103. e Merge It can merge with the different export files See the Merge dialog box below 181 FMO7I4A E PHRSR E The Zeroplus Logic Analyzer Zeroplus Technobogy Coa Ltd User s Manual V3 09 x 1 2 3 Object file fen 10 Ext Open File to merge ALL txt OK Cancel Fig4 16 7 Merge Dialog Box Object File 1 It is the covered file that is to say it is a new file 2 It can display the path of the Object File and the file name 3 It can open the Object File by clicking the Open option File to merge 1 It can create the new file with the object file 2 It can display the path of the File to merge and the file name 3 It can open the File to merge by clicking the Open option Import Export and The Export function can select the TXT or EXCEL format to store the Data of the List Window of the Memory Analyzer the Import function also can select the TXT or EXCEL formats to analyze the former export data Option Otin It is used to set the relative parameters for the List Window of the Memory Analyzer see the following Option dialog box x Bar 45signment Reaction Bar la Active Display Assignment Display Width Color dc ne Datat O Alteration Cancel Default Fig4 168 Option Dialog Box Reaction Bar The default is the A Bar the added Bar can be displayed and selected in the pull down menu if user
104. e Max Value a wb Ai a A Freer je when Found Statistics d when Found Statistics h z Statistics h z Statistics Bus2 I 4 ae _ Statistics Vt D Yv 4 vr _ Statistics BO fo A ACK B 1 Series Fig 3 127 Waveform Find Dialog Box of the Protocol Analyzer I2C FMO7I4A Phe eee i BR eS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Tavefora Find xj Tavefora Find x I Activate the function of Chain Data Find 7 Activate the function of Chain Data Find BHsSigral Name ye a Next Previous Close cm X Next Previous Close Br a Min Value Max Value Min value Max value on ae Es a 41 ae When Found Statistics Start At Statistics Statistics Statistics la Ds BO B1 Taveforme Find Taveforma Find Activate the function of Chain Data Find 3 Activate the function of Chain Data Find Next Previous Close Next Previous Close Min Yalue Max Value B em ind Min value Max Value FFFFFFFF FFFFFFFF meted Statistics STAR f FELRE Statistics Statistics eO E _Statistics_ p po Tavefora Find i ji faveform Find xj m Activate the Function of Chain Data Find 7 Activate the function of Chain Data Find Byatstqerabhrarrie Next _Previous Cose D Next Previous Close Min Value Max Value Bus Item Find Min Value Max Value H FFFFFFFF FFFFFFFF Statistics Stat
105. e Packet and Waveform Synch is activated the synch point in the waveform area is the left packet segment which is displayed by waveform Middle When the Packet and Waveform Synch is activated the synch point in the waveform area is the middle packet segment which is displayed by waveform Activate Packet and Waveform Synch select Top and Left 115 Syoch Parameter Setting x M Activate Packet and Waveform Synch Synch Point of Packet List Synch Point of Waveform 4rea Middle Middle Fig 4 52 Synch Parameter Setting Dialog Box FMO7I4A The Zeroplus Logic Analyzer User s Manual V3 09 The Zeroplus Logic Analyzer Phe ee in BPR E User s Manual V3 09 Zeroplus Techneablogy Co Ltd Display the corresponding waveform and packet as below image Ee ZEROPLUS LAP C 32128 S H 000000 0000 i2c als oe File Bus Signal Trigger Run Stop Data Tools Window Help ii 2 9 o amp FF E B D bd 1 128K z sie e 200MHz oo AY Be Ie 22 le aI Bar Bar Bar Bar 50 as i Page A B 150ns v DOD A Pos 83 87888ms v 172 1598TTus 83 878T3ms v Compr Rate 243 040 Display Pos 96 835918us Scale 3 012956us Display Range 21 51196us Total 159 278465ms Je Packet REWE TimeStamp EEN ADDR READ A4 ACK DATA ODRACK DATA DRACK DATA e DATA E DATA DEACK DATA Hipage DATA Ries DATA eee MES o O MWS O DATA ieee ME DATA ieee 7A D Ack s D Ack 9C_ D
106. e information directly from the screens of oscilloscopes this Logic Analyzer was created to help engineers resolve timing sequence issues during their circuit development I2C has a multi control Bus as its physical and firmware interfaces This protocol analyzer is basically a signal network that may connect to one or several control units The intention of inventing this protocol was in the application of designing television sets which allowed the central processing unit to quicken data communications with peripheral chips and devices The I2C interface is initiated with a SDA triggered High and SCL triggered Falling Edge Following the initiation there will be a set of 7 bits or 10 bits address space Beyond this point there will be Read Write ACK Acknowledgement and STOP or HALT HLT The signal information packet is transmitted in bytes If there are two or more devices trying to access the I2C protocol whichever device has SCL at logic high will gain access priority Furthermore since I2C is a synchronous communication protocol and data transmission must be in bytes a complete I2C signal packet must consist of START ADDRESS READ WRITE DATA ACK NACK and STOP segments They are as following START This is the initiation of SCL and SDA 1 bit only ADDRESS This identifies the device address 7 bits READ WRITE This is a data direction bit 0 Write 1 Read ACK NACK _ This is a confirmation bit following every data tran
107. e repetitive run Click icon to view all the data and then select the waveform analysis tools to analyze the waveforms W ZEROPLUS LAP C 32128 S H 000000 0000 LaDoc5 i 5 xj To File Bus Signal Trigger Run Stop Data Tools Window Help Dema BB 2B BB gt p o fizek oie ih 200mH2 z 20 i 4 Page 1 ORE fi Ba 0 030525 7 x oe Oe Be Te ke Mb le 9 OB gt Heigt Trigger Delay 1 Font Size fiz z Scale 3276 Display Pos 39322 A Pos 25205 v A T 25205 v a Total 131072 Display Range 26213 104859 B Pos 25175 v B T 25175 v Sc 7 E Bus Signal Trigger Filter ee 22942 39322 55702 T2082 88462 42 121222 v b End DEMO h Fig 4 25 Click Icon to View All the Data 3 Stop to end Run Click the Stop icon to end the Run If the status is Waiting with no signal outputting as shown in Fig 4 26 click the Stop icon to end the Run check the setup again and try the run process again Fig 4 26 Waiting Status FMO7I4A Phe eee i BR eS The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 4 2 Bus Logic Analysis Section 4 2 presents detailed instructions about logic analysis with a set of grouped signals which is known as Bus Logic Analysis Basic Software Setup of the Bus Logic Ana
108. e second picture shows the result which has set the high level on the Filter Condition of the signal A1 Only the waveform with the high status of A1 is displayed 170 Step5 Filter Delay Setup 1 Click on the Activate Filter Delay as shown in Fig 4 143 2 Click on the According to Filter Condition or the Opposite of Filter Condition to select the waveforms to be kept 3 Click on the Start Edge End Edge or Period Delay to set the Start Point of Filter Delay 4 Type the value of the Delay Time into the column of the Delay Time 5 Click OK then click Run to activate the signal from the tested circuit to the Logic Analyzer 6 The result will be displayed in the waveform display area as shown in Fig 4 142 Step6 Stop Signal Filter Filter Delay Click Stop then click Signal Filter Setup and select Cancel from the Signal Filter Setup dialog box to stop the Signal Filter or the Filter Delay Setup Tip Click Stop to check the conditions of the Signal Filter or the Filter Delay Setup if there aren t any results Tip Click icon to view all the data and then select the waveform analysis tools to analyze the waveforms Filter ma Setup Select Filter Delay Mode Select Delay Start Point Delay Time amp According to Filter Condition Start Edge Ens C End Edge Min 5ns5 Opposite of Filter Condition C Period Delay Max 327 675u5 Fig 4 143 Filter Delay Setup Tip Definitions of the Start Edge and the End
109. ect several Optional Items Step 2 Select the corresponding items in the relating Step 3 Choose a color by following the method shown in Fig 3 164 Step 4 Click OK to change their colors into the same for example A1 A2 A3 and A4 Here is a sample of an altered Logic Analyzer software interface which will be used for further demonstrations in subsequent chapters See Fig 3 165 88 FMO7I4A 89 fy SRHHMOBIEAA The Zeroplus Logic Analyzer gt Zeroplus Technology Co Ltd User s Manual V3 09 W ZEROPLUS LAP C 32128 S H 000000 0000 LaDoc5 rr ei ee eee Fig 3 165 An Altered Interface Sample to Be Used in Subsequent Chapters FMO7I4A P Re Tee ih BR eS The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 3 7 The Flow of Software Operation RAM Size 128K oa He Sample Rate MH Tela Tien Clock ee NO ee Trigger Page ee ie ik et Select Analysis Funcion Trager Postion 50 i Trigger Caii Tearc Be Pass Analysis HC Bus Arnal ye E rt ART Phas Analysis SPT Fus Analysis AS Ere Wave E ura Dm MC Bus Analysis B Focisto Ansiyee Dats nee fe oe de Mia UART Bus Analysis ES ec Gia alailk og SPL Bua Analysis 4 E Sns Ri eie 22 Fig 3 166 Software Flow Diagram Conclusion Information demonstrated in this chapter is only for entrance level There are more advanced approaches which
110. ee Fig 4 30 3 Set and Don t Care and type the value of the Bus into Value column to set the trigger condition 105 FMO7I4A 106 1 SRARBRPAIRAA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd Users Manual V3 09 of the Bus 4 Click OK to confirm the settings Step4 Click Run and activate the signal from the tested board to the system to get the result as shown in Fig 4 32 Tip Click icon to view all data and then select the waveform analysis tools to analyze the waveforms Set Value is 5E as Hexadecimal and set Operator equals to then click OK Click Run and activate the signal from the tested board to the system to get the result as the trigger happens on OX5E us Trigger x Bus Name Operator Bust Data Format Binary Decimal i Hexadecimal f ASCII Cancel Default Help Fig 4 32 Bus Trigger Setup FMO7I4A 1 SRR ABRLA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 4 3 Plug Analysis Plug Introduction Protocol Analyzer operates in the form of Plug every Protocol Analyzer has a plug per plug is independence modularization One Protocol Analyzer plug can analyze many Buses at the same time however because the independence of every plug the Protocol Analyzer plug only supports I2C UART SPI HDQ 1 WIRE CAN 2 0B at present In the future it will support more Buses and when the Protocol Analyzer renews i
111. er signal to the Logic Analyzer for example Protocol Analyzer SPI Bus Signal Fig4 159 Waveform before Refreshing STEP 3 Choose Select an Analytic Range to select the analysis range and drag Ds Bar to B Bar Yv 0 See a O o O n Nn Fig4 160 Drag Ds Bar to B Bar STEP 4 ZET the daii will see the data between Ds and Dp Fig4 161 Analyze the Data Between Ds and Dp STEP 5 Click Sl again the waveform return the original state 178 FMO7I4A l 1 SRRHRPABRLA The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 Bus Signal H Rem Trigger Filter Fig4 162 Restore the Original State Tip The Refresh Protocol Analyzer function can come into effect while the Ds and Dp are activated 179 FMO7I4A PREAH BELE The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 4 11 Memory Analyzer Memory Analyzer enables the system to divide the packet format in the Protocol Analyzer and display the Address and Data in an independent list It is better for understanding the relative relationship and status of the Address and Data in the operating process of the Protocol Analyzer Users will know the operation when they use
112. ested board to the signal connector of the Logic Analyzer to measure it by using the internal clock of the Logic Analyzer Clock Source 200MHz 1 Asynchronous Clock Internal Clock Frequency Ammin 500H m Synchronous Cloch kHz a 25KHz o Rising Edi SOKHz Sampling MRAM Size RAM Size Channel number wgs OnOMHe limited to 32 adila Fig 4 2 Clock Source Pull down Menu 92 FMO7I4A 93 C O Phe eho in Blea The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 External Clock Synchronous Clock Click on External Clock and then select Rising Edge or Falling Edge as the trigger condition of the DUT In the Frequency column type the frequency of the oscillator on the DUT Tip The External Clock is applied when the frequency of the oscillator on the tested board is exceeds the range of the internal clock of the Logic Analyzer Connect the output pin of the oscillator on the tested board to the CLK pin of the Logic Analyzer Step 3 RAM Size Setup Click on the RAM Size 128k 4 from the pull down menu on the Sampling Setup dialog box as shown in Fig 4 3 Rising Edge Information x te Falling Edge You have selected the Double Mode The Filter Delay Note The external Setup and the Display Bar Setup are not available under l 7 Don t show me this warning again Sampling OK RAM Size RAM Size 256k Channel
113. et these segments of channels 3 Click OK to get the result as shown in area 1 104 FMO7I4A Phe eee ih BR eS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Trigger Filter Bus Signal Ok Cancel Help Fig 4 29 Channels Setup Window Tip Channels Setup In the dialog box of Channels Setup there isn t only Add Bus Signal but also Delete Bus Signal Delete All Restore Defaults provided 1 Delete Bus Signal Firstly highlight the Bus or channels on area 6 of Fig 4 29 then click Delete Bus Signal to delete them 2 Delete All Click Delete All to delete all Bus signals on area 6 of Fig 4 29 3 Restore Defaults Click Restore Defaults to restore the dialog box of Channels Setup as shown in Fig 4 27 Step3 Trigger Condition Setup 1 Highlight the Bus which will be triggered then click icon or select Bus Trigger Setup from the Trigger of the Menu Bar the dialog box as shown in Fig 4 30 will appear Bus Trigger K Bus Hame Operator Bust Data Format Binary Decimal Hexadecimal ASCII Cancel Default Help Fig 4 30 Bus Trigger Setup Tip Left click on Trigger column of the Bus as shown in Fig 4 31 T F Busignal Tiger ii j Single Click on _ Parr rel the Left Key eal Dg Fig 4 31 Trigger Column 2 Set Binary Hexadecimal Decimal or ASCII as the Data Format of the Bus to represent the value s
114. f the Waveform Find is set FMO7I4A PRE eh in Blea The Zeroplus Logic Analyzer na Zeroplus Technology Co Ltd User s Manual V3 09 Scale 5 6539625 Display Fos 0 A Pos 104 A T 104 Total 32768 Display Range 141 143 E Fos 0 a jl 113 079 84 509 56 54 nani LI I 56 54 a4 809 28 2T I 2 aT LS 0 eS ATA TL j Tavefors Find x Activate the Function of Chain Data Find _ BusfSignal Name Next Previous Close i FFFFFFFF so BUS tem Find Min Value Max Value Stark At End at When Found Ds Dp Address 0 Fig 3 136 The B bar is placed at the 0X12 of Data of Protocol Analyzer SPI where the condition of the Waveform Find is set FMO7I4A hie PIS AG tt 3 PRE The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 3 3 Statistics Feature Section 3 3 presents detailed information on the Statistics feature in the software interface The Statistics feature presents user information pertaining to nine periodicities Full Period Positive Period Negative Period Conditional Full Period Conditional Positive Period Conditional Negative Period Start Pos End Pos and Selected Data Click on the Statistics icon fg and an interface like Fig 3 137 or Fig 3 138 will appear STAT IET f xj Channel Parameter Item Parameter Condition Parameter Warning Parameter Refresh J Statistics
115. fter t DW1 period of time the signal will rise and last throughout the period of t CYCD which is of 1 bit and ranges from 190us to 260us The t DW1 ranges from 32us to 50us and no more than 50us The t DW0O ranges from 80us to 145us neiii Eoad ees Tacr Fig4 113 Signal from BQ HDQ to Host 151 FMO7I4A l 1 SRRHRPABRLA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 4 5 6 1 Software Basic Setup of Protocol Analyzer HDQ x Pin AsSlgnment Protocol Analyzer Name Pusl Channel ao Timing S Break fioooooc Recovery ao to 100000 Host 1 jo o Device 1 fo Host 0 s0 Device O fo to feo Host bit 60 Device bit fao jw Response A070 to T to Protocol Analyzer Color BREAK RECOVERY ADDRESS REAL WRITE DATA Fig4 114 Protocol Analyzer HDQ Setup 1 Pin Assignment HDQ has only one signal channel therefore it only specifies the name of the channel and marks the selected channel Protocol Analyzer Name Display the name of the selected Bus Channel Preset as AO 2 Timing Set the time for BREAK ADDRESS READ WRITE DATA and RECOVERY 3 Protocol Analyzer Color BREAK RECOVERY ADDRESS READ WRITE DATA 152 FMO7I4A fo S gt RHHMOBIEAA The Zeroplus Logic Analyzer a Zeroplus Technology Co Ltd User s Manual V3 09 Operating Instructions Open the LA operation interface We ZEROPLUS LAP C 32128 S H 0000000000
116. gering Time of triggering success Time of sampling data Time transmitted to computer after sampling data finished and Time of Bus data overloading FMO7I4A J PRABREGARAA The Zeroplus Logic Analyzer j So Teeny a User s Manual V3 09 I 8 Help Logic Analyzer Help Fi Keyboard Map Report a Problem T About ZEROPLUS Logic Analyzer About ZEROPLUS More Protocol Analyzer Fig 3 107 Help Menu Menu Bar Help Menu Item Detail Menu amp Dialog Box Logic Analyzer Help Fi Keyboard Map j Fig 3 109 The Table of Keyboard Map Report a problem to the service e mail at service 2 zeroplus com tw Report a Problem g 66 FMO7I4A 67 PERS R iB PRE Zeroplus Techneablogy Co Ltd About ZEROPLUS Logic Analyzer i About ZEROPLUS More Protocol Analyzer Tip The function of Software Version Information Display for ZEROPLUS LA means that the software will open a small window which displays the software version new functions and bug modifications when activating the software It is convenient for users to know the information of the present software version The Zeroplus Logic Analyzer User s Manual V3 09 About ZEROPLUS Logic Analyzer oe xi L4P C Series PRR HARA A version Standard 3 08 CNO2 Zeroplus Technology Co Ltd _ y 000000 0000 m The Information of the Yersion New Feature Support the Wi
117. ght column Tip When the mouse is located at a special position on the waveform area click the right key to select the Add Bar function a bar will be added automatically in the special position according to the sequence of the word and color See the C Bar in the position 5 in the right column E Fig3 123 Add a Bar on the Waveform Area FMO7I4A 71 1 SRERHRBROARAA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 3 2 Find Data Value Find Data Value is a very useful tool to help the user to find data on the received signals Step1 Click the find data value pi icon the dialog box of Waveform Find will appear Step2 Using the pull down menu select the Bus Signal Name The Bus Signals listed on the pull down menu represent the status of the Bus Signal column as shown in Fig 3 124 Feim Activate Ube function off hain Bus Sayral Hames wou ow fal al FR ie ag e F Dat T4 T pi Bi a oh i A Dl EK vera E a ifs DE DT FH Bi Fig 3 124 Step3 Choose the character for Find The list of characters depends on whether it is a Bus Signal or the protocol analyzer such as I2C UART SPI etc which is being searched See Figs 3 125 3 126 3 127 3 128 3 129 3 130 3 131 3 132 and 3 133 Bus Choose among In Range and Not In Range Enter the Min Value or Max Value Protocol Analyzer Choose the segments bits of the prot
118. gure below BUS Packet List xj setting Refresh Export Synch Parameter Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length 1 _ Busigus 1023 ff oO 1 o 1 o 1 o j 1 o 1 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length 2 _ busi us 1013 o 1 o 1 o 1 o 1 o 1 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length Busi us 1003 o 1 o 1 21 o Packet Name Timestamp Data Data Data Data Data Data Data Data Data Data Length o o 1 o 1 o 1 o 1 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length 1 1 1 1 1 Packet Name TimeStamp Data Data Data Data Jata Data Data Length AT Bus1 us Name TimeStamp Data Data Data Data Data Data Data Data Data per Pesieus L Popa fot fo i oy fo 1 Fig4 49 Bus Packet List Tip The Protocol Analyzer Packet will be explained in the following plug 5 Packet and Waveform Synchronization For the convenience of fast corresponding between packet data and waveform data and what is more in order to make it easier for users to look up data we add the Packet and Waveform Synchronization function In order to operate conveniently we add a Synch Parameter button on the BUS Packet List as the image below BUS Packet List xj Refresh Export Synch Parameter Packet N
119. he b Low level ends SSus Bias spe Fig4 92 Packet Length il Packet Length From Unknow_Start_Flag TimeStamp to Unknow_End Flag TimeStamp Packet Idling Length From Unknow _End Flag TimeStamp to Unknow_ Start_Flag TimeStamp Virtual SS is activated 3 Data needs 8 bit the Idling Time is set as 3us Don t care data bit is activated That is the 3 675us is bigger than 3 155us is bigger than Idling Data a idling tine so the nest time however the data s end of the Ti packet rising edge is the information only capture to the packet lacst aap tinestaap of data sisth bit so the data is not accord with the virtual condition ofSPI ss the packet ends gt ee Ae B a le Ee f m m m m pm am 3K UUUUUUUL JUUUUU 3 ies UU ATA pe es o iws is y Packet Length Fig4 93 Packet Length Packet Length From Packet s TimeStamp Data to next Packet s TimeStamp Data Packet Idling Length It is O The End dot is Unknown ata s Timestaap Unknow is registered is Packet s Unknow_End_Flag Timestamp DATA 0X56 a a a D aaa E aa E aa G aaa Packet Length I Fig4 94 Packet Length Packet Length From Packet s TimeStamp Data to next Packet s TimeStamp Data Packet Idling Length It is 0 139 FMO7I4A gt FERRARS RAE The Zeroplus Logic Analyzer ee Zeroplus Techneblogy Co Ltd User s Manual V3 09 4 5 5 1 WIRE
120. he linewidth can be adjusted by the users requirements there are three options which are 1pixel 2 pixel and 3 pixel 86 FMO7I4A Phe eee i BR eS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 3 6 1 Modify Workaround Color To modify the workaround color click the color block shown in Fig 3 161 A Color panel shown in Fig 3 163 will appear Select a color shown on the panel or click on Define Custom Colors to create the desired color CN 21x Basic colors ai E eee Hi CS See Define Custom Colors gt gt Hue jeo Red jo OF E alc Sak jo Green jo Define Gustom Colors gt gt Lum p Blue jo isn f pmi fF ie gee GG OF Cancel Add to Custom Colors Fig 3 163 Color Panel with Its Advanced View Custom colors E a ug ip ip i E a U ip ip g i 87 FMO7I4A PREM A Blk ee The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 3 6 2 Modify Waveform Color Foreground color refers to the color of the output signal lines in the Waveform Display Area Fig3 157 presents how to change colors of a signal or some signals Repeat the following procedures if users need to change colors of many signals Step 2 Step 3 Step 1 Color Setting Workaround Waveform ix M N Name Tf Relatip Corf Linewidth l AQ m i Taqaqaqqqqaqaaqa Fig 3 164 Stepwise Illustration of Changing Waveform Colors Step 1 Sel
121. he min pulse width Cancel Default Help Fig 4 74 UART Setup Step4 Protocol Analyzer UART Setup 1 Set the Channel of the Transmitter Signal Select Pin Assignment then choose the given Protocol Analyzer name for Bus 1 Next select the signal which is connected to the pin of Bus 1 of the tested board from the pull down menu to analyze the data of the transmitter signal 2 Set the Baud Rate Select the rate from the pull down menu of the Baud Rate to meet the specifications of the tested UART board Baud Rate may be set and equal to 300 600 1200 2400 4800 9600 19200 38400 57600 or 115200 3 Set the Bits for the Data Bit Select the number from the pull down menu of the Data Bit to meet the specification of the tested UART board Data Bit may be set to 4 5 6 7 or 8 4 Set the Data Direction Select MSB gt LSB or LSB gt MSB from the pull down menu of the Data Direction to meet the specifications of the tested UART board T P da au eee 1 so amp F H i 8 f T ee ee ee O O ima ania Fig 4 75 Data Waveforms MSB gt LSB and LSB gt MSB 5 Set the Parity Select none parity odd parity or even parity from the pull down menu of Parity to meet the specifications of 130 FMO7I4A The Zeroplus Logic Analyzer Phe AFAR ih ARAE Zeroplhus Technebooy Co Ltd User s Manual V3 09 the tested UART board 6 Set the Bits for the Stop Bit Select the nu
122. he serious error Applications CAN 2 0B is used for automotive electronics correlation systems connection 2 Protocol Analyzer Signal Specifications 100MHz S Appropriate Sampling Rate 100MHz Same Data Time Per Bit Name of Syn Signals CAN 2 0B Data Verification Point ileal 190us converts to High signals gt 3 Protocol Analyzer IO Description CANL The main signal source of transmission data CANH Signal is opposite to the signal source of transmission data 4 Protocol Analyzer Electrical Specifications Parameter in Logic Input High Logic Input Low CAN 2 0B Frame Specification CAN 2 0B can separate into frames as follows Data Frame Remote Transmit Request Frame Error Frame Overload Frame Because CAN2 0B is transmitted by the format of different signals the signal can separate into CANL and CANH and the signal direction of CANH is opposite to that of CANL Next we analyze CAN 2 0B signal with the standard of CANL Basic Data Frame Data frame can be divided into Basic CAN and Peli CAN Data Frame of Basic CAN transmission As follows 157 FMO7I4A PREAH AG i ARRES The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 message data can be separated into Start of Frame SOB Arbitration Field Control Field Data Field CRC Field Ack Field End of Frame z u Ge Be SEFERE Ril ER a SS eee Te ea PT e a cape ERHI HEEE EE HE F JEE Baa 1 HEI HE El RE o fa E ey A S
123. i r eT Vere fer a e gay py LL ps yay E wal End Connected a FMO7I4A Phe eee ie BR eS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 i File Bus Signal Trigger RunfStop Data Tools Window Help x De el S Bo amp ELD gt p i28k z sie o S0MHz x am am 50 s Page fi jelom mm K e l o foozaarats me Rl oe Oe Be Te ke Ble 9 o gt Height 30 Trigger Delay 1 Font Size 12 r Display Pos 0 A Pos 16775642 v A T 16775642 v A B 30 Display Range 102400 102402Pos 16775612 v B T 16775612 v Compr Rate 255 748 81920 6i440 40960 20480 i 20480 40960 61440 81920 fener on en i Ten 1 Gt ti a 102400 1 i UUT UUUT T UUUU vr gt End Connected 7 Fig 4 140 Before and After Compression Using 128K memory depth before Compression has been applied the total of the data was 131072 after the Compression had been applied the total of the data was 33521362 therefore the compression rate is 255 748 Tip Click icon to view all data and then select the waveform analysis tools to analyze the waveforms Step5 Click the compression icon again or click off the compression function to stop compression Tip Compression cannot be applied with the signal filter function at the same time 168 FMO7I4A PRARE ARAE The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 4
124. ialog Box Click to run once b See ue as See Section 4 1 for detailed instructions Click to run continuously until the Stop button is gt gt Repetitive Run F pressed See Section 4 1 for detailed instructions Click to stop the repetitive run at FT o P See Section 4 1 for detailed instructions 40 FMO7I4A H SRABRRBRee The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 5 Data ad Select an Analytic Range nai Noise Filter ne Bus Width Filter x Data Contrast P Find Data Value Ctrl F Fo Find Pulse Width l To the Previous Edge Fil Io the Hext Edge He Go Ta Add Bar Bar Delete Bar Bar 1 Zoom vz Zoom In Binary a Zoom Out Fa Show aia lata FiO HEL TEL cS Freyvyious Soom Crelre iw need uiel ASCII Data Format eae Reverse favetorm Mode F ra Square Waveform List Data Mode Sawtooth Tareform All Data Sampling Changed Dot Compression Data Changed Dot Compression Fig 3 41 Data Menu Ak Bo Te BA le l Bar Bart Bar Ear Gar Fig 3 42 Data Tool Box 4 FMO7I4A PREM AG Blk ee The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 Menu Bar Data Menu Item Detail Menu amp Dialog Box Check the box to enable the Analytic Range to be p Select an Analytic Range changed by dragging the Ds and Dp bars with the left mouse button Noise Filter It can filter 0 10
125. ify the Correlated Setting Ee ZEROPLUS LAP C 32128 S H 000000 0000 LaDoc5 ta i ec Kij pila a gt ea o l ee Fig 3 145 The Interface Layout Shown in Default Settings 78 FMO7I4A PREIS AG Blk ee The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 3 4 1 Modify Waveform Display Mode To modify the display mode users can use icons on the tool bar box or menu For the menu go to Tools and click Customize See Fig 3 1175 I j x Common Setup Show Time of Waveform m Color Setting eee Di soed Mode pereesesessseesssessesesssessesssesssesssessssssssesssesseseseeg BUS Bus Property Refresh Protocol Analyzer gue Memory Analyzer Multi stacked Logic Analyzer Settings Analog Waveform gt Time Display C Frequency Display Waveform Height fao Font Size 12 C Regular Ruler Time Sampling Site Ruler Correlated Setting V Auto Close V Open Close Compression Warning Show Gridline JV Show Tooltip Open Close Double Warning Data Process What do you want to show when you press the Stop during the running Keep the Present Data Read the Captured Data V Check for Update Racer eieraniite Fig 3 146 Customize the Display Mode by Using the Tool Bar fut Sampling Site Display E gt ZEROPLUS LAP C 32128 S H 000000 0000 LaD
126. ign Workspace s Horizontally FMO7I4A i PHRSR E The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Hes gt ah ioe ow me S oe ae Pace 1 RED IG tes hacian Display Pea Oage A To A Bo Xima Hia Hian poo aie ba as Bangler Peactnia 1a Fe 1A Bt Wee bec kDa Display P wy Benge Hia Se ol BS ei eplay bunge alii eo op 1 Buia ls 20 dilar Tafil Trigger Pilie aiima e etet S ili wie me rot et Vertical a i ou jaa E FE wi I Er snm B Fig 3 105 Align Workspace s Vertically Screen Display When there are two displayers connecting users can select Screen Display we Double Screen Display to display waveforms on both Ea Double Sereen Display E First Screen Display ie Second creen lisplay two displayers it is convenient for displaying more waveforms First Screen Display or e Second Screen Display can also be selected to display waveforms on the first displayer or the second displayer Stopwatch Function The function will show at right corner of the bottom of the screen while sampling data It times from users pressing the ensured key at the Bus Property dialog box to Bus insert sending back analyzed data Please look iaiting Normal ie at the left figure It has five functions as following Fig3 105 Stopwatch Function Time of waiting for trig
127. ignals 3 Protocol Analyzer IO Description OWIO The only I O transmits Reset signals and data 4 Protocol Analyzer Electrical Specifications O Parameter min Typ max Unt noe Every IC varies High count Voltage 2 8 5 2 V according to the Pull High voltage ow countvottage 0 Vv 140 FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer aeroplus Techneabogy Co f User s Manual V3 09 Protocol Analyzer 1 WIRE Format Description Two speed types of 1 WIRE Standard 1MHz 1us High 5MHz 0 2us Four types of 1 WIRE Signals 1 Reset Every communications period starts with Reset signal Master will send a Reset Pulse so that all the Slave devices on the 1 WIRE Protocol Analyzer enter into recognition status When one or many Slaves receive Reset Pulse a Presence Pulse signal will be sent back from Slave indicating receipt of the signal 2 Write 0 Send a 0 bit to Slave Write 1 time slot Write 1 Send a 1 bit to Slave Write 1 time slot 4 Read Data Read data sequences resembles Write time slot However when Master releases BUS and reads data from Slave devices Master creates samples from BUS status In this way Master can read any 0 or 1 bit from Slave devices oa Four signal types are described respectively in the following 1 Reset 1 When Master starts communicating with Slave Master first sends a low count Reset Pulse TX t of STL Standard speed 48
128. in PASS T Roll the contrast waveforms synchronization Pin Assignment Display files the contrast differences Perform Contrast Close Help Fig3 46 Data Contrast Data Contrast It is used to contrast the difference for the two files of the same style One is the Basic File and the other is the Contrast File The contrast file can display the difference between the Basic File and the Contrast File Taveforme Find i x Tl Activate the function of Chain Data Find Bus Signal Name oust Next Previous close Bus Item Find Min Value Max Yalue Data lo F Start t End t When Found Statistics b be Bho H Statistics fo Fig 3 47 Waveform Find Dialog Box without FMO7I4A PRR AG ARRE Zeroplus Technology Co te Tip Remember the final conditions When the find function is used the function of displaying the final conditions is added When you have closed the Waveform Find dialog box and you want to find the set conditions you can open the Waveform Find dialog box again for the system has saved the last set conditions 44 The Zeroplus Logic Analyzer User s Manual V3 09 Activating the Function of Chain Data Find Use the pull down menu to select the Bus Signal Name The list of Find depends on whether it is a Bus or Signal that is being searched in Bus Choose among In Range and Not In Range enter the value for Min Value and Max Value Signa
129. in 1 Max 8192 Trigger Position 50 C Delay Time and Clock Trigger Delay Time 20us Min 20us Max 335 524s Trigger Delay Clock 1 Min 1 Max 16776191 T Pos 0 Start Pos 1023 End Pos 1025 Note When more than one tr igger pages are selected the trigger bar disappears from the view x Cancel Default Help Fig 3 35 Set Trigger Delay FMO7I4A 39 A FERRNA REE Zeroplus Technology Co Lt Tip Trigger Range Icon Description N A Trigger Range The Zeroplus Logic Analyzer User s Manual V3 09 See Section 4 1 for detailed instructions Fig 3 36 Set up Trigger Delay clock under time display Trigger Delay 1000 Fig 3 37 Set up Trigger Delay clock under sampling site display The Trigger Delay setting in Tool Box equals to that in the above dialog box Trigger Property x Trigger Content Trigger Delay Trigger Range goeeseeeeeseceessceessoeossooesseoeessceessoeessseeesecessseeessses n a R A Range Setting Time Sample fi minute x Cancel Default Help Fig 3 38 Set Trigger Range FMO7I4A PREAMP Bike Bl The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 4 Run Stop p single Eun F5 HE Repetitive Run Foe E r Er Fig 3 39 Run Stop Menu D gt b Fig 3 40 Run Stop Tool Box Menu Bar Run Stop Menu Item Detail Menu amp D
130. in Pulse Width and Max Pulse Width between 1 and 65535 and find the Pulse Width in range When users select the Min Value they can find the Min Pulse Width for the present single channel When FMO7I4A FRE PAR i BPR J Zeroplus Technology Co Ltd Tip This function is mainly used for finding the pulse width in a single channel and the single channel of a Bus It improves the efficiency of finding the Pulse Width for engineers and strengthens the Find function of the Logic Analyzer l To the Previous Edge Fli 4 To the Next Edge Fl tro To 46 The Zeroplus Logic Analyzer User s Manual V3 09 users select the options gt lt and they can input the value of the Pulse Width between 1 and 65535 and find the Pulse Width in range Start At Select the Start point of Find The selectable items are all Bars the default is the Ds Bar End At Select the End point of Find The selectable items are all Bars the default is the Dp Bar When Found Select a Bar to mark the found Pulse Width The selectable items are all Bars the default is A Bar Statistics It can count the number of Pulse Width in the present range Next It can find the next Pulse Width Previous It can find the previous Pulse Width For example Find in the A1 channel the Pulse Width is equal to 40us take the A Bar as the mark See the below figure E a q i for a eT j T sk b er Fig
131. ing will appear as shown in Fig 4 84 1 Select High or Low to define the SS enable level of the tested SPI circuit 2 Then type a number in Bit of the Data for the Bus signal 3 Press OK to confirm the setup of SPI Custom Setting and return to the dialog box of the SPI Setting Tip Press Default to give up the current setup 135 FMO7I4A PREP eho ih Bee The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 PROTOCOL ANALYZER SPISETUP Busi Configuration Facket Register Protocol Analyzer Setting Pin Assignment Protocol Analyzer Name Bust Mode CPHA 0 CPOL 0 Fallow MSB gt LSB Y Protocol Analyzer Color kw O Custom Setting Data Ag SCR AQ ASPI Custom Setting o H Select Device Level i High 55 enable level Low E Low virtual 55 Gondition Idling Time 5 us Dont care data bit Min Sus Mari 2er Erais Fig 4 84 SPI Custom Setting B SS Setting is not Activated Click the Custom Setting then the dialog box of the SPI Custom Setting will appear as shown in Fig 4 85 PROTOCOL ANALYZER SPI SETUF Bus1 k X Configuration Facket Register Protocol Analyzer Setting Protocol Analyzer Name Bust Pin Assignment Data Ag Mode CPHA 0 CPOL 0 SCE AD Fallow MSB gt LSB Protocol Analyzer Color aw Custom Setting LIT x Select Device Level Data
132. ion FMO7I4A PREAMP Bike Bl The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 Objective Chapter 3 presents detailed information on the Logic Analyzer software interface in four sections Menu Bar Tool Bar Statistical Function and Interface Customization Basic Layout The layout of the Logic Analyzer software interface can be divided into nine sections as shown in the following figure We ZEROPLUS LAP C 32128 S H 000000 0000 LaDocil i lol x 7 ignalf Trigger Run Stop Data Tools Window Help x eH a m AN B p Ol 2K vjes Bi toKH2 v am mw 50 v ie He Page i gourt Slk ia allm oo s Bie ee T A e orll Height 40 J tri Size 112 A Pos 15 v A T 15 A B 3 y E B Pos 15 v B T 15 wv Compr Rate No Bus Signal Y Triceer a eee T 2h 4 UU LU WU LIU ZU UU UU UU N t sa o oooO OO G ee A 7 Fig 3 1 Software Interface 1 Menu Bar 22 All operations are performed directly from the menu bar including configure label rename execute and stop Pull down menus allow easy navigation through the measurement panel Tool Bar The tool bar is the graphical user interface which can make you work with some of the more common applications From these icons you can change settings and operate the Logic Analyzer easi
133. ion does not meet the filter conditions it won t gather and store data Tip 1 r4 Don t Care means that the Logic Analyzer captures all signals from sampling Filter Condition delay time EERE FT start edge d LY Filter Condition delay time start edge Fig 3 23 High and Low Levels It is the system default There are three modes of Signal Filter configuration for each channel captures and displays the input signals satisfying the high level 3 Low Level means that the Logic Analyzer captures and displays the input signals satisfying the low level Filter Condition delay time ees a end edge Filter Condition e end edge delay time Fig 3 24 High and Low Levels Signal Filter Delay Setup Filter Delay According to the filter condition Start Edge Show the waveform from the start edge to the delay time interval See details in Section 4 1 AT A x l r T Tat TEAT T IYA Js ani Satan Mme tae va Ve ve TEN ae eA ee PDS DDS is MEA AA ea ea SA ie Channels setup 716 5 41 3 2121 017 6 5 4 3 2 1 017 65 4 3 2 1 0 7 6 8 4 3 2 1 ae 7161814131 2 91 01716 4 32 71 0 7 6 4 31211 O17 6 51432 E 9 7654321017 6 4321 017 6 654321 617 65 4 315 1 716 5 413 2 9 077 6 5 4 3 2 11 017 6 5 4 32 211 017 6 5 42 1 0 7 6 5 4 3 2 1 017 6 5 4 3 2 1 017 6 5 413 2 11 01 7 6 5 3 2 1 0 7 615 4 3 2 91 0171 6 5 413 211 01716 14 3 21
134. istics Statistics fo When Found UNKNOW when Found po Taveform Find x Taveform Find i x E Activate the function of Chain Data Find ignal Name Next Previous Close Activate the Function of Chain Data Find gnal Name sce Next Previous Close Min Value Max Value ind Min Value Max Value FFFFFFFF FFFFFFFF Statistics icti When Found UNKNOW At When Found RAE Statistic fo A z Statistics v aa las DATACA2 MISO SCK A0 Taveforme Find x Tavefore Find xj Activate the Function of Chain Data Find E sedet the function of Chain Data Find Next Previous Close Previous Close Min Yalue Max Value Max Value FFFFFFFF FFFFFFFF When Found Co ae Statistics fo If DATAA2 MISO SCK A0 Tavefora Find xj 7 Activate the function of Chain Data Find Next Previous Close Taveform Find xj 7 Activate the function of Chain Data Find BusiSignal Name m x Next Previous Close Bus Item Find Min value Max Value Bus Item Min value Max Value foo Freeper Fer When Fand Statistics Statistics In Range Statistics Not In Range Statistics fo Address 600 Fig 3 133 Waveform Find Dialog Box of the Bus Item of the SPI Signal FMO7I4A PRE eee i BR e
135. it then AND Read Write Bit to have an additional 1 bit on the right side of the Address Data content FMO7I4A PREP i Bee The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 5 Press OK to confirm the setup of I2C Custom Setting and return to Protocol Analyzer 12C Setup dialog box Tip Press Default to give up the current setup Step8 Press OK to exit the dialog box of Protocol Analyzer I2C Setup Step9 Click Run to acquire I2C signal from the tested 12C circuit Refer to Fig 4 69 Tip Click the I2C icon then press Stop to exit I2C analysis mode Tip Click El icon to view all data and then select the waveform analysis tools to analyee the waveforms W ZEROPLUS LAP C 32128 S H 000000 0000 i2c als Mme o File Bus Signal Trigger Run Stop Data Tools Window Help lj x Denai A cea Elp b i28k z ie o f200MHz aw 50 s Page fi Count fi z BH glr E e 3 012958u R ae Oy Be Te te Bb le 4g es Height 26 Trigger Delay _5ns Scale 3 012956us Display Pos 96 8359165us A Pos 83 8T888ms v A T 83 87888ms v A B 150ns v 2 LAr Trigger 35 576751us 51 641543us 66 706335us 81 771126us 36 53591905 111 90071us 126 965501us 142 030293us 157 095085us 172 g 2 ee Se a Se ee 2 12 2S S B AS x amp
136. ize and select Auto Save See Fig 3 158 SE x Common Setup Toolbars Shortcut Key Auto Save O Hew Ctrl tN File Name La Open Ctr1 0 Close CtrltF4 Save Path r ET c my Documents LA Data ave tr ela Los Repetitive Run Auto Save Time Interval Data Display Menu Renewal Mode ime Interval fen Export Waveform Ctrlt Shi fttE Every Renewal E Export EPT List cq Open the first file after Tail Capture Window Ctrltct stopping the Run Language b amp Print CtrltP Print Preview Recent File cancer an Fig 3 158 1 Auto Save on File Menu Fig 3 158 2 Auto Save Item of Customize Fig 3 158 Auto Save Auto Save The default is not activated after activating it keeps working and users also can choose Cancel to close it Activate The default is not activated after activating it keeps active and users also can choose Cancel to close it File Name Before users name the file the file name is defaulted as LA In fact the saved file name can add a serial number for the file automatically Save Path Name Users can enter the path directly or choose the path from the selected path button m Time Interval When the auto save function is activated the time interval from one finished sampling to the next activated sampling can be set according to users requirements the default is 1s and the unit can be selected from s second m minute and hr hour Every Rene
137. k the Left Key of the mouse to select the waveform randomly Te TELS LEPC CE OD Lakai a Eile PuwfSignil Tricor besau Beta Tesla Tisbe Bale al x Deh B84 A polj ian SEE a l fo 9 a Bey S Height Trigger r bela 1 Fem Sine IE rn Dinpler Fas Te A Be Teta 2048 Desay Kenge 200 218 Te mle Tais Compe Buta N Fig3 100 Select Channel button After clicking the Right Key of the mouse the Select Channel dialog box will pop up as below Select Channel x Destes ba EA Fig3 101 Select Channel dialog box In the Select Channel dialog box users can select the FMO7I4A 64 A FRA ARS oS ia Packet List Tip Setting Set up the packet list Refresh Click it the content in the packet list will be refreshed Export Users can use the fragment to work record and analyze the packet list data As Export according to the packet list arrangement it exports the text file and csv file Synch Parameter Open the Synch Parameter Setting dialog box Cascade l Horizontal The Zeroplus Logic Analyzer User s Manual V3 09 channel which users want to display users can select four channels at most the defaulted channels are AO A1 A2 and A3 there are four channels in total Ept f iLa k i i tha i i tha i i rege a luorath Pet PP oa oa a ae Ronde ee Fig3 102 Display Packet List oe eee patel Salata a A Fig 3 104 Al
138. l Choose among Rising Edge Falling Edge Either Edge High and Low Start At Choose the position to start our search by selecting one of the following Ds T A B ect select from the pull down menu When Found Choose A B or other bars to mark the position where it is coincident with the set conditions Statistics Show the number of instances of the search results Note It is available only when searching through a Bus Taveform Find J x MV Activate the function of Chain Data Find Bus Signal Name Bust Next Previous Close Please key in a chain of data with a comma to compart them for example 0x32 0x45 0x50 0x66 01 02 03 Start At End at When Found m Statistics Statistics Ds r Dp v la v _Statistics fo Fig3 48 Waveform Find Dialog Box with Activating the Function of Chain Data Find Tip The function of Chain Data Find is mainly for finding the data in the packets of Bus and Protocol Analyzer which have some serial data For example it can start finding with the serial packet segments there are 0X01 0X02 and 0X03 in the Bus It improves the efficiency of Data Find See the following process Activate the function of Chain Data Find Bus Signal Name Bust i Previous Close Bus Item Find Min Yalue Max Value Data 7 lo fF Start At End t when Found Statistics pum Address 1003 FMO7I4A 45 PERS R in AIRA Zero
139. l IMMON ial OMe sscstencaves gra caeaisemates tease iire aa EEE EE E EE ENE EEEE EE E EE 198 Oo OE a E E E 199 APPONI sssi ia a aaa eiai 200 E RON Yoe E E E E E E E E E E 201 P LONA TU e S E N E E one Maemcedesoal 204 FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 Preface This Quick Start Guide is designed to help new and intermediate users navigate and perform common tasks with the Zeroplus Logic Analyzer Despite its simple packaging and interface the Logic Analyzer is a sophisticated measurement and analysis tool It is also a highly sensitive electrical current sensing device Users must carefully read instructions and procedures pertaining to installation and operation Any instrument connected to the unit should be properly grounded A pair of anti static gloves is strongly recommended when performing a task with the device To ensure accuracy and consistency of output data use of the bundled components is strongly recommended Users opinions are very important to Zeroplus Please contact our engineering team by telephone fax or email with your questions or feedback Thank you for choosing the Zeroplus Logic Analyzer Notice We will not have additional notice for you when there is any modification of the User Manual If there is some unconformity caused by the software version upgrade users should take the software as the standard 4 FMO7I4A O PREP i Bee The Ze
140. l U a F Ad EEE Leann m Rising Edge nee was Copy Channel Protocol Analyzer Setting Ping Delete charnel TT Saeerrarceeeeereererereereeereerre Melara fi Gerea ei oe AT Resta WaGa Eea i ZEROPLUS LA SPI MODULE 1 11 01 N 0 _ lt sv M ZEROPLUS LA UART MODULE 2 10 01 Format Row M ZEROPLUS LA 1 WIRE MODULE 1 09 01 ws Fil Rename M ZEROPLUS LA CAN 2 06 MODULE 1 31 00 i M 2EROPLUS LA HOQ MODULE 2 06 01 M 2EROPLUS LA Tac MODULE Y2 01 02 I Use the DsDp Find More Protocol Analyzer http fiv zeroplus cam tw cme oeo Fig4 66 Bus Property Step5 For Protocol Analyzer Setting select Protocol Analyzer Then choose ZEROPLUS LA I2C MODULE V2 01 02 Next click Parameters Configuration The following image will appear 122 FMO7I4A REA ee i ARRES The Zeroplus Logic Analyzer Zeroplus Techneblogy Coa Ltd User s Manual V3 09 PROTOCOL ANALYZER IZC SETUP Bus1 Pin Assignment Pte Anaon None Buel SDA AQ se SCL Al Protocol Analyzer Setting Custom Setting Protocol 4nalyzer Color START DATA SLAVE ADDR READ WRITE REG ADDR A ACK A MACK D ACK D MACK STOP Cancel Default Help Fig 4 67 Protocol Analyzer I2C Setup Step6 Set the Pin Assignment Tip 1 Pin Assignment Set the display name of 12C in Bus1 2 SDA Choose SDA channel for I2C 3 SCL Choose SCL channel for 12C It is recommended that SDA and SCL channels are named as SDA and SCL
141. l trigger condition as shown in Fig 4 22 2 Right click f to set the signal trigger condition as shown in Fig 4 23 3 Click Trigger on the Menu Bar and choose a trigger condition from the list of triggers as shown in Fig 4 24 Bus Signal p EMD 40 a 4 i g bus Trigger Setup EAS Shl A Re or Channel Trigger Setup uss Signal Trigger gil Properties left click we AAR WC a M AD gt O 8 Pia is oe Fal Al jf Rising Edge ees eM MoM x i Falling Edge ioe F a h Either Edge oe 75S Color Ferrers 5 AG Ag eee ra Ad A4 Fig 4 22 Left Click on Trigger Trigger Run Stop Data Tools Window Help Fi Bus Trigger Setup ae Channel Trigger Setup mi Trigger Property i Trigger Mark Ja Pulse Width Trigger Module Option Either Edge Reset Fig 4 24 Trigger Menu 102 FMO7I4A FREAR ARAE The Zeroplus Logic Analyzer Task 5 Tip Tip 103 Zeroplus Technology Co Ltd User s Manual V3 09 Run to Acquire Data 1 Single Run Click the Single Run icon from the Tool Bar or press START button on the top of the Logic Analyzer or press F5 then activate the signal from the DUT to the Logic Analyzer to acquire the data shown in the waveform display area 2 Repetitive Run Click the Repetitive Run icon from the Tool Bar then activate continuous signal to the Logic Analyzer to acquire the repetitive data and then click the Stop icon to end th
142. lag TimeStamp to Unknow_ Start_Flag TimeStamp 2 SS channel is not activated Virtual SS is activated 1 Data needs 8 bit the Idling Time is set as 3us 138 FMO7I4A l 1 peH ROSRAS The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 ae is the packet Idling time so the Unknow End Flag linformation after 2 355us isn t data 2 355us is less than Unknow registers p se f i If the time length of SCK low Level is bigger than idling time it is the timestamp of data and the timestamp of next data Packet T ensth 3 S7Sus is bigger than Idling Time so it is data s timestamp Fig4 91 Packet Length Packet Length Unknow_ Start_Flag TimeStamp to Unknow_ End Flag TimeStamp Packet Idling Length Unknow_End Flag TimeStamp to Unknow_ Start_Flag TimeStamp Virtual SS is activated 2 Data needs 8 bit the Idling Time is set as 3us Don t care data bit is not activated Although 3 155us is bigger The Unknow than i i ata s t ang tine dat registers information only capture Unknow_End_F the sixth bit and doesnot i i lag 6 S7Sus is bigger than apture to the cighth bit idling time next so the da is thought rising edge is hi the data bit timestamp of the data m m IT JUUL TU Packet Length Because the low level only has 196ns less atte as tas x than Idling time 7 L packet ends when t
143. logy Co Ltd User s Manual V3 09 Ff ae a i E 3 ee n ZEROPLUS ioe ta ey Ara i hae j i i i ni J y i 3 l iA L F i i y I ti p Lar g 16 Pin x 1 8 Pin x 2 Fig 1 2 Testing Cable Fig 1 1 Logic Analyzer o oT RUG F ES Ti p ig Fig 1 3 Probe varied depending on models a om Busy i I ee N i i i i l Utar Fig 1 8 2 Pin Ground Cable Fig 1 7 1 Pin External Clock Cable Black White FMO7I4A PREAMP Bike Bl The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 1 2 Introduction Zeroplus Logic Analyzer LAP C Series share the same external features as illustrated in the following figures Sel LEI Ne RUN READ TRIGGER POWER p m Fig 1 9 A View of the Zeroplus Logic Analyzer LAP C Series See Fig 1 11 for detailed information on the Signal Connectors Fig 1 10 Side View of the Zeroplus Logic Analyzer the power of the Logic Analyzer is drawn from the USB connection PortA A0 A7 gt Port B BO B7 Port C CO C7 Port D DO D7 lt or external modules or devices not designated to be analyzed For transmitting signals ta_ activate other instruments For connecting the Ean eee 4 For grounding test circuits External Clock ie Fig 1 11 Side View of the Zeroplus Logic Analyzer LAP C Series FMO7I4A gt FRARROARAA The Zeroplus Logic
144. ly Note The prompting information of the shortcut keys has been added in the tooltips of the Tool Bar that is to say when users place the cursor on the icons the corresponding shortcut key information will appear For example the prompting information of the New button is New Ctrl N Ctrl N is the Shortcut Key of the function of New Information Bar The Information Bar displays information about the grids in the waveform such as Address Time Frequency Trigger Bar A Bar B Bar and other Bar Details of the labels are below Scale Define the acquisition clock that controls the data sampling Total The period of time when Logic Analyzer captures data Display Pos The middle tip means the middle position of the waveform Display Range Display the waveform time range of the current waveform display area A Pos The main function is to set A Bar or the other Bar B Pos The main function is to set B Bar or the other Bar A B Press the under arrow to exchange and become the other Bar Moreover you also can execute this function from the other Bar Ruler Waveform Display Listing Display Ruler shows the time position of the waveform shown in the waveform display area or the listing display area FMO7I4A 23 a O PREP hei Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 Bus Signal Waveform Display Listing Display Edit names of the measured channels color shown
145. lysis Step1 Set up the RAM Size Frequency Trigger Level and Trigger Position as described in Section 4 1 Step2 Group signals into a Bus Click Channels Setup on Bus Signal of the menu bar or click i icon The dialog box shown in Fig 4 27 will appear PLUS LAP C 32128 S N 000000 0000 Lal Bus Signal Trigger Run Stop Data Tools Ww ia Sampling Setup 2 l channels Setup a G Group LAUS EET ET X Unare Add Bus Signal Delete Bus Signal Delete All Restore Defaults Expal Golla f PA OS DE DE DE DE OG DE DE OG OY OG DE DE DE OG OG OG OG DA OG OG OG Form 2S DEDE 2S OG BS 29 OG OY OY OG OY DE BG DEDEDE DE OG OG OY OG OG L Rena SSS mnono m za el Po a a ralrolrolrolpolro polne OA ey Wl E Baolololololololo mA a a a nononono n in an an an an an an nlala aala w w w w w w ww VINN ER ET A E iE S 2 625 2 Ze FAERIE Jabanna alz Sie SiS a m ale w w w w w w w w Serp EHE E EA PAE E A A E clelelolololelo ae eee eS S H 4 JV Reserve waveform data and show them Fig 4 27 Channels Setup Rename the Bus and set up the channels of the Bus as shown in Fig 4 28 Fig 4 28 Rename Bus 1 Click the column with blue then type the given name of the Bus and then press Enter to confirm it 2 Go to the relative channels as shown in the example and go to numbers O 1 2 3 which are located on column A and row Bus1 Click them to become purple then s
146. lyzer Zeroplus Technology Co Ltd User s Manual V3 09 hi Find Data Value Ctrl F EJ Find Pulse Width Ga To Flace Add Bar Bar re Zoom E any Hand H B Hormal ESCAPE E Show all Data Fig ck Previous oom Ciel Data Format W eee ye ade a Sut Waveform Mode Reverse Color ra Square Waveform Bus Wate kolor Bus Single Data Color Sawtooth faveform Fig 6 8 Waveform Mode SW15 Can I change the Signal Display Mode into the Timing Mode A Yes you can SW16 Why does not Filter Delay work when the Double Mode is enabled A 196 To optimize signal output quality and maximize memory efficiency the Signal Filter Setup function may work under the Double Mode However the Filter Delay function doesn t work under the Double Mode at this stage FMO7I4A O Phe Tele in BR The Zeroplus Logic Analyzer RGO1 RG02 RGO3 RG04 RGO5 RGO6 RGO07 RGO8 197 Zeroplus Techneablogy Co el User s Manual V3 09 6 3 Registration What is the significance of the hardware serial number Every product is assigned and engraved with a unique serial number which allows us to trace the original manufacturing date of a specific product How do register online Visit our homepage at http www zeroplus com tw Choose the Instrument Department and click on English Once you finish membership registration proceeding with product registration After finishing product regi
147. m Waveform Display Listing Display 61 The Zeroplus Logic Analyzer fHavetoarm Display Listing Display Hot Hews Window Havigator Cascade Horizontal Vertical Screen Display w 1 Lallocl Fig 3 90 Window Menu a 2 Fig 3 91 Window Tool Box User s Manual V3 09 Detail Menu amp Dialog Box File Bus Signal Trigger Run Stop Data Tools Window Help S i T AE Holm e E O lE zale 2 Sus otal 5 12ms Display Pos Ons Display Range 62 Navigator m Listing Display Hot Hews Window gt reform Display Bus Signal Filter A g Al SR rE JM 35 Trigger AO Cascade Horizontal Vertical Screen Display Y 1 LaDocl Fig 3 92 Display Signals in Waveform File Bus Signal Trigger Run Stop Data Tools ata Help EDELE ey 8 1B gt Holaa mar e il E Waveform Display sie Display Hot News Window ting Havi gator Cascade Horizontal Vertical Screen Display d 1 2 LaDoci 2 LaDocl 1 zale 2 Sus Display Pos Ons stal 5 12ms Address Povo Jo ai tai i Fig 3 93 Display Signals in Listing FMO7I4A 62 PRE ESAS i BPR Zeroplus Techneablogy Co Ltd Hot Hews Window d Tip To let online users learn the latest news we add the Running Text Ads Function Turn On Start the
148. matches the trace color Trigger Column Trigger Column allows users to adjust signal trigger conditions Filter Column Filter Column allows users to set Bus or signal filter conditions Display Area Acquired data is displayed as a waveform or in a list format Waveform Display This interface shows the digital signals When the signal is logic 0 the waveform will be displayed as If the signal is logic 1 the wav IS as An unknown signal waveform is displayed in gray between the high and low levels e There are sixteen channels in LAP C 16032 LAP C 16064 LAP C 16128 and LAP C 162000 and thirty two channels in LAP C 32128 LAP C 321000 and LAP C 322000 Listing Display This interface shows the digital signals as 1 and 0 Logic 1 is displayed as 1 and logic 0 is displayed as 0 Status Area Display Logic Analyzer status The function name is also indicated here FMO7I4A C O PREP eh in Blea The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 3 1 Menu amp Tool Bars Section 3 1 presents detailed information on the eight menu and thirteen tool items shown in the menu bar The eight menu items are File Bus Signal Trigger Run Stop Data Tools Window and Help The thirteen tool items are Standard Trigger Run Stop Sampling Trigger Content Set Display Mode Windows Mouse Pattern Zoom Data Show Time Height Trigger Delay and Font Size 1 File F Hew CtrlitH g
149. may require fewer steps than those shown in this chapter This chapter is meant to equip users with sufficient grounding of the Logic Analyzer s software interface 90 FMO7I4A O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 4 Introduction to Logic Analysis 91 4 1 4 2 4 3 4 4 4 5 4 6 4 1 4 8 4 9 Logic Analysis Bus Logic Analysis Plug Analysis Bus Packet List Bus Analysis Compression Signal Filter and Filter Delay Noise Filter Data Contrast 4 10 Refresh Protocol Analyzer 4 11 Memory Analyzer 4 12 Multi stacked Logic Analyzer Settings FMO7I4A PREM A Blk ee The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 Objective Chapter 4 gives detailed instructions on performing two basic analysis operations and other advanced analysis applications with the Logic Analyzer These two basic analysis operations are the Logic Analysis and the Bus Logic Analysis which are fundamental to all further applications The other advanced analysis applications are the I2C Inter Integrated Circuit Analysis and the UART Universal Asynchronous Receiver Transmitter Analysis the SPI Synchronous Peripheral Interface Analysis Compression Signal Filter Setup and Filter Delay Setup etc 4 1 Logic Analysis Logic Analysis is meant for a single signal analysis Section 4 1 gives detailed instructions on the software s basic setup Basi
150. mber from the pull down menu of the Stop Bit to meet the specifications of the UART DUT Stop Bit may be set to 1 1 5 or 2 7 Set Use the reverse data level for decoding Click on Use the reverse data level for decoding to decode the received data into the negative logic which a Baj voltage represents the 1 state and which a positive voltage represents the 0 state ZOD ae ee Eb B vi 0 elfi UNKNOW START E DATA 10000000 pen n O Using the reverse data level to decode Fig 4 76 Without With the Reverse Data Level for Decoding UNKNOW DATA 10110000 EA rmi Without using the reverse data level to decode E UART f 8 Find the baud rate automatically based on the min pulse width Selecting the option can help to find the baud rate automatically based on the min pulse width 9 Set Protocol Analyzer Color Click the color of the segment as the DATA START STOP and PARITY to select the required color Step5 Press OK to exit the dialog box of Protocol Analyzer UART Setup Step6 Click Run to acquire the UART signal from the tested UART circuit Refer to Fig 4 77 Tip Click icon to view all data and then select the waveform analysis tools to analyze the waveforms 10 x i File Bus Signal Trigger Run Stop Data Tools Window Help x D EREI i BS ot oT e D gt DD 512K v site 18 141 10MHz e au nw 50 vip ps Page to SIL
151. n the software If this does not work restart your system This should temporarily fix the problem However we highly recommend terminating all irrelevant programs while working with the Logic Analyzer Try not to burn DVDs not listen to music or watch movies while working with the Logic Analyzer The default color setting of the Waveform Display Area is very cool but don t see anything when print my work out with my black and white laser printer What can I do Refer to Section 3 6 it should have clear understandable instructions about changing the color of the user interface See Fig 3 153 this color setting should give a clear view of the Waveform Display Area even with an old black and white laser printer FMO7I4A C O PHARD Bee The Zeroplus Logic Analyzer aeroplus Tochnolbegy Co f User s Manual V3 09 5 3 Hardware Troubleshooting Q1 Why are no lights on when I hook the USB cable to the Logic Analyzer A Double check whether the other end is properly connected to your PC There may also be a defect in your USB cable Try another cable Q2 Why can t I read any signals from my Logic Analyzer A Check whether you have correctly connected the signal cables to the activated pin on your test board and check the power supply of your test board The Logic Analyzer does not supply any electricity to a test board via signal lines Q3 I get a signal from only one Logic Analyzer when I have two connected what is wrong A
152. nce of Data easily there are adding the function of Data Contrast The function of Data Contrast is used to compare the difference of two signal files of the same type One is the Basic File and the other is the Contrast File It can line out the different waveform segments of the basic file in the contrast file Meanwhile it can count the number of the difference 4 9 1 Basic Software Setup of Data Contrast STEP 1 Click Data on the Menu Bar then select zi to open the Data Contrast Settings dialog box 175 Data Contrast Settings X W Activate Data Contrast Contrast Files Basic File JLaboct Contrast File JLabocz Contrast Beginning Point i T Bar Error Tolerance More Beginning of Data Contrast Result Error Stat a ASLAS aen FASS Data Iools Window Help a n Pi Select an Analytic Range ASTAS oren PASS BEJAB aen FASS nari Hoise Filter ATAF csr Hae BOLBO ioris PASS sez Bus Width Filter TE PASS E Zz Data Contrast Roll the contrast waveforms synchronization Pin Assignment _ Display files the contrast differences fi Find Data Value Ctrl tF I Display files horizontal Perform Contrast FA Find Pulse Width Close Hep J Io the Previous Edge Hil Fig4 155 Data Contrast Interface Activate Data Contrast Click the checkbox to activate the function of Data Contrast Basic File It is the standard contrast file Contrast File It is used to compare with
153. nction Display Trigger Page 1 8192Page Pulse Width Trigger Double Mode No The Zeroplus Logic Analyzer User s Manual V3 09 Latch No No Yes No Yes Function Data No No No Yes No Yes Contrast Multi stacked Logic Analyzer Settings Protocol Analyzer Trigger Safety Certification FCC CE WEEE RoHS FMO7I4A O PREP hei Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 1 4 System Requirements This section discusses basic operating system and hardware requirements for the Logic Analyzer Software and hardware capabilities may vary depending on PC configuration This manual assumes proper installation of a supported operating system as listed below 1 4 1 Operating System Requirements Windows 2000 Windows NT 4 0 Professional Server Family Workstation amp Server Service Pack 6 Windows XP Windows Server 2003 Operating System Home Professional Editions 32 Bit version Name Windows VISTA 32 Bit and 64 Bit version Windows 7 32 Bit version 1 4 2 Hardware System Requirements Hardware Name Lowest Configuration Recommended Configuration CPU 166 MHz 900 MHz VGA Display Capability with VGA Display Capability with 1024x768 resolution or higher 1024x768 resolution or higher Display Device At least 100MB available space At least 100MB available space USB USB1 1 supported USB2 0 recommended 12 FMO7I4A 13 gt FERRARS RAE The Zeropl
154. ng SCK Serial Clock Line SCL MOSI Master data output Slave data input MOSI stands for Master Out Slave In MISO Master data input Slave data output MISO stands for Master In Slave Out SS SS stands for Signal Selector of the master device which is to select signals for the Slave devices CPHA The clock phase CPHA control bit selects one of the two fundamentally different transfer formats CPOL The clock polarity is specified by the CPOL control bit which selects an active high or active low clock Dor rere el ieee l eg ema Fhe ht Faba D shere hang colo hc em Chak Pine Oe epe ae yes e art fhe dba mo ghlae T aHa g ag ag Giggi Folarity 1 where Hng edgen ha ey Clink PRraee Q where wee osteo estore cl uu ce T amela F gt i Tp al 7 TUF er We io Sigaek kiiri SU ara riging edga Happ ers Gieck Frame whitia wave 2 yecle ri Mi duha ame ee ml s argie LE 4 Dig Zk Peder j wiere Halny Sa gies KAANAA Gieck Frage s where wore Cycle end Fig 4 82 Clock Polarity and Clock Phases FMO7I4A PREAH ih Bike Bl The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 4 5 4 1 Software Basic Setup of Protocol Analyzer SPI Step1 Set up RAM Size Frequency Trigger Level and Trigger Position as described in Section 4 1 Step2 Set up the Falling Edge on the signal of SS which connected to the Signal Selector SS pin of the SPI tested board Ste
155. ngth fe bit biin Bit blan 32bit Sampling position Cancel Default Help Fig4 107 Protocol Analyzer 1 WIRE Sampling Position Setup STEP 5 Set Data Length This function decides how many bits of data can be combined as one set of figures The default is 8 bits and the maximum is 32bits PROTOCOL ANALYZER 1 WIRE SETUP Bus1 xX Configuration Packet Register Protocol Analyzer Color RESET PRESENCE PULSE DATA Pin Assignment Protocol Analyzer Name Bus Channel Protocol Analyzer Property Data Direction Connect speed f MSB gt LSB LSB gt MSB f Standardi us High 0 2 us Data Length E bit biin bit blas 32bit Sampling position m r ie lel here Min Tus Max 120us Cancel Default Help Fig4 108 Protocol Analyzer 1 WIRE Data Length Setup 148 FMO7I4A PRE ESAS i BPR Zeroplus Technology Co te The Zeroplus Logic Analyzer User s Manual V3 09 4 5 5 2 Protocol Analyzer 1 WIRE Packet Analysis FEOTOCOL AHALTZEE 1 TIRE SETUP Basil x Item Color vouc N Cancel Default Help Fig4 109 Protocol Analyzer 1 WIRE Packet Setup That is the new View the below View includes several formats that 1 WIRE can happen it describes Data number and their positions BUS Facket List i Setting Refresh Export Synch Parameter Facket Mame Timestamp Pt eusicewirey 700 Packet Name Timestamp WAT
156. nish to complete the installation Step 10 Click Yes to restart the PC 16 FMO7I4A 17 PRE ESAS i BPR Zeroplus Techneablogy Coa Ltd e LA CETTE Donii FIAN ted oni Th thee neta hbk Ward for LAPSE 6128 Standard _ se The Del hehe Ed eal shall Lab OGL Seared 37 25 gi r enre Ta omiin kk Hoi The hentvare shoud se cotnari ng Ih jhh LAB cibh wher inataliig c a alsin ar Tha program Cor ba reslated surcmlicals mee Das pacar SS hen a cee grl bia gnd Tier raira rari E LAP C 16128 _Standard_ 3 08 InstallShield Wizard License Agreement Please read the following license agreement carefully LICENSE AGREEMENT IMPORTANT READ CAREFULLY This LICENSE AGREEMENT is entered into effect between ZEROPLUS Technology Co Ltd hereinafter ZEROPLUS and Customer Individual or Registered Company Whereas ZEROPLUS owns a software product including computer software as a package product for certain computer products relevant intermediary product information electronic file and internet on line downloadable software electronic file and service known as ZEROPLUS Bl 3 Print Ido not accept the terms in the license agreement InstallShield lt Back Cancel ji LAP C 16128 _Standard_ 3 08 InstallShield Wizard Customer Information Please enter your information User Name boxed Organization XXX Install this application For
157. nment Data start Protocol Analyzer Name Bus f 111bit start Channel AQ im C Obit start Use the reverse data level for decoding Protocol Analyzer Property Baud Aate fi S5 000 Min bps Mas 10Mbpa Users can vary the baud rate and set up the value as your requirements e0 Percentage sample After End of Frame happens just begin to analyze When CAN Data for expansion combined Basic ID and ID Auto Judge Baud Aate suggest adopting high sampling rate to cary on data sampling Protocol 4nalyzer Color START CONTROL Cancel Default Help Fig4 135 Protocol Analyzer CAN 2 0B Setup FMO7I4A J PREHROHRAA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Click OK in the Protocol Analyzer CAN2 0B Setup dialog box to complete the CAN 2 0B Setting W ZEROPLUS LAP C 32128 S H 00000000001 LaDoc3 tT is pa Fig4 136 CAN 2 0B Decoding 165 FMO7I4A Phe eee i BR eS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 4 5 7 2 Protocol Analyzer CAN 2 0B Packet Analysis x Configuration Facket Register Item Color m ID CONTROL jv WACK jw DESCRIBE Cancel Default Help Fig4 137 Protocol Analyzer CAN 2 0B Packet Setup Packet color can be varied by users The Packet displays with the waveform as below We ZEROPLUS LAP C 32128 S H 00000000001 LaDo
158. nstallation 2 3 Tips and Advice 15 FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zerophus Technebooy Co re User s Manual V3 09 Objective This chapter describes the installation of the Logic Analyzer hardware and software Software installation steps must be followed precisely to ensure successful installation 2 1 Software Installation In this section users will learn how to install the software interface and drivers As with proper installation of many USB devices the Logic Analyzer application and driver software must be installed prior to the connection of the hardware The following steps illustrate an installation of a Zeroplus LAP C 16128 Logic Analyzer The other six models mentioned in Chapter 1 would follow identical procedures Step 1 Insert the driver CD ROM in the PC CD drive Step 2 Execute the installation program Go to the START menu click START Run Browse in sequence select Setup exe file in the appropriate model folder and then click OK It is recommended that all other programs are closed while the installation proceeds Step 3 Choose the desired language Step 4 Click Next to proceed with the Install Wizard Step 5 Select I accept the terms in the license agreement and click Next Step 6 Enter User and Organization name Step 7 Choose the setup type We recommend Complete for most users Step 8 Click Install to confirm settings and begin the actual installation Step 9 Click Fi
159. o Hand mode Hot Key Equivalent Orders Ctrl A Go to A Bar Ctrl B Go to B Bar Ctrl C File gt Capture Window Ctrl E Data gt Zoom Ctrl F Data gt Find Data Value Bus Signal gt ALEG Group into Bus Ctrl N File gt New Ctrl O File gt Open Ctrl P File gt Print Ctrl S File gt Save Bus Signal gt ws Ungroup from Bus Ctrl Z Data gt Previous Zoom Ctrl Shift E File gt Export Waveform Statement Center A bar Center B bar Open Capture Graph dialog box Change Mouse mode to Zoom mode Search specific data with predetermined conditions Group selected signals into a Bus Create a new file Open a saved file Print an active file Save an active file with its current name location and file format Ungroup signals Pins from a Bus Reverse the last Zoom Open Export Waveform dialog box FMO7I4A 202 O Pe ESIC IRA Zeroplus Technology Co H Hot Key Page Down Page Up Home End Up Down Left Right ESC Space The Zeroplus Logic Analyzer User s Manual V3 09 Table 7 3 Hot Keys 3 Equivalent Orders Operate the position shown Operate the position shown Operate the position shown Operate the position shown Operate the position shown Operate the position shown Operate the position shown Operate the position shown Operate the position shown Change the trigger conditions Statement Go to next page of the da
160. ocol analyzer Select the protocol analyzer item and enter the value for Min Value or Max Value Signal Choose among Rising Edge Falling Edge Either Edge High or Low xi xi 7 Activate the function of Chain Data Find Activate the Function of Chain Data Find B ignal Name 5 ignal Name Tas F Next Previous Close Tas Next Previous Close Tn Min Value Max Value Bus Item Find in Value Max Value a FFFFFFFF Data FFFFFFFF az Statistics ed Statistics A when Found Start At h n Found Statistics v Statistics BO la 7 B1 B2 B3 Fig 3 125 Waveform Find Dialog Box of the Logic Signal Tavefora Find x Tavefora Find x Activate the function of Chain Data Find Bus Signal Name Tl Activate the Function of Chain Data Find E ignal Name eusz_ Next Previous Close iw X Next Previous Close Bus1 a Min Value Max Value Bus Item i Min value Max Value Ao b fo FFF Data o0 FFFFFFFF 41 lt EEA Statistics Start At As Statistics faz Ja _Statistcs Ds Y Op Not In Range B0 J fo B1 Fig 3 126 Waveform Find Dialog Box of the Logic Bus Taveforme Find x Taveform Find x Activate the function of Chain Data Find Activate the Function of Chain Data Find Bus Signal Name Name Tous v Next Previous Close Ka Next Previous Close Gi Busi a Min Yalue Max value ind Min valu
161. ols ge Bus Trigger Setup Channel Trigger Setup van AH Trigger Property I Trigger Mark Trigger Property x S Dont Care HETER CGE Trigger Delay Trigger Range me Hi ch bie L Trigger Level Trigger Count REREH oy if Rising Edge Fort A a i Falling Edge 11 fis M se Either Edge Fort E Min 1 Max 65535 m a Reset T TTL fis vv Fort D TTL j5 w Cancel Default Help Fig 4 4 Trigger Property Step2 Trigger Level Setup Click the pull down menu of Trigger Level on Port A B C and D to select the Trigger Level as the voltage level that a trigger source signal must reach before the trigger circuit initiates a sweep Tip There are four commonly used preset voltages for Trigger Level TTL CMOS 5V CMOS 3 3V and ECL Users also can define their own voltage from 6 0V to 6 0V to fit with their DUT Port A represents the pins from AO A7 on the signal connector of the Logic Analyzer and so do Port B C and D The voltage of each port can be configured independently Trigger Property 7 x Trigger Content Trigger Delay Trigger Range Trigger Level Trigger Count Fort i emos Gv 5 w Fort E Min 1 Max 65535 User Defi ZEROPLUS Logic Analyzer x Fort C TTL r A Flease enter a mmber between 6 0 and 6 0 Fort I User Defi Ok Cancel Default Help Fig 4 5 Trigger Level Error Step3 Trigger Count
162. p and end we add two special Unknow Flag to judge the timestamp and end of the packet which are Unknow _Start_Flag and Unknow_End_Flag This Data Start is regarded as Packet Timestamp This Unknow register is Unknow_End Flag 12C a E E SDA ALU Uo A SCL l Packet Length Fig4 44 Protocol Analyzer I2C Packet Length Tip Because I2C has started as the Packet TimeStamp it does not need to use Unknow _Start_Flag as the start 4 Bus 112 FMO7I4A l 1 peH ROSRAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 BUS Packet List 7 xj Refresh Export Synch Parameter Packet Name Timestamp Data Data Data Data Data Data Data Data Data Data Length E Busius 1023 o 1 o o o o 1 Packet Name Timestamp Data Data Data Data Data Data Data Data Data Data Length 2 Busi us 1013 0 o 1 10 Packet Name Timestamp Data Data Data Data Data Data Data Data Data Data Length o 1 o 1 o 1 o 1 o 1 Data Data Data Data Data Data Data Data Data Data o i o 1 o 1 o 1 o 1 10 10 10 1 o o Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Poof i fotijtyotrttTotiftoatsi 10 Data Data Data Data Data Data Data Data Data Data Length SS ET Packet Name TimeStamp 983 Data Data Data Data Data Data Data Data Data
163. p3 Set up the Protocol Analyzer SPI dialog box the Protocol Analyzer SPI dialog box is set as the steps of I2C PROTOCOL ANALYZER SPI SETUP Bus1 Configuration Packet Register Protocol Analyzer Setting Protocol Analyzer Hame Bus Mode CPHA 0 CPOL 0 Follow MSB gt LSB Protocol Analyzer Color Custom Setting 55 Pin Assignment IY Activate 55 Channel 41 Cancel Default Help Fig 4 83 Protocol Analyzer SPI Setup Step4 SPI Setup 1 Protocol Analyzer Setting Select the Mode from pull down menu of Bus 1 Then Select MSB gt LSB or LSB gt MSB from the pull down menu of the Follow to meet the specifications of the tested SPI circuit Then click the _ to set the Protocol Analyzer Color Tip Select MSB gt LSB to arrange data from left to right eg 0 0 0 1 0001 select LSB gt MSB to arrange data from right to left eg 1 0 0 0 0001 2 Pin Assignment Setting Select channels to set the Data and SCK channel Choose one channel from the pull down menu of the Data to set the data channel Then choose one channel from the pull down menu of SCK to set the SCK channel 3 SS Pin Assignment Click Activate on SS Signal Selector Then select the signal which connects to the Signal Selector pin of the SPI DUT from the pull down menu of SS 4 Custom Setting A SS Setting is Activated Click the Custom Setting then the dialog box of the SPI Custom Sett
164. play Move Left Up Move Right Down Hide Show All and Color Ungroup signals from Buses by pressing Ctrl U A Bus contains at least 1 channel In order to see these channels click the symbol before the name of the Bus Bus Signal Trigg Filter ene g Al A 22 is mM x 735 48 Fig 3 26 Expand If the Bus has been expanded click the symbol before the Bus name to Collapse the Bus Fig 3 27 Collapse Aube Size Move Leftiup Move Right Down Hide Shaw All Color Fig 3 28 Click to change the Bus or signal display FMO7I4A 35 O Pe ELSIC IRA Zeroplus Technology Co H Tip Format Row Auto Size it is not available in Waveform Display mode Move Left Up change to Move Left in Listing Display Move Right Down change to Move Right in Listing Display Hide Show All Color Fename The Zeroplus Logic Analyzer User s Manual V3 09 Change the display of a Bus or a signal Size the signal columns automatically Highlight a signal or Bus and click Move Left Up to move the signal or Bus up left through the list of the Bus signal Highlight a signal or Bus and click Move Right Down to move the signal or Bus down right through the list of the Bus signal Highlight a signal or Bus and click Hide to hide it Click to show all signals and
165. pling Setup Channels Setup Dakara Chanal Bus Property Analog Waveform Group into U a en Restore Default Channels Bus Ungroup from Bus Format Row and Format Row Rename are the same as those in the Rename Busoignal Menu Fig 3 112 Right Key Menu on the Bus Signal Column Add Channel x Channel fan Cancel Fig 3 114 Add the required channel in the Add Channel Bus Signal column 7EROPLUS Logic Analyzer X AN Do you want to copy the channel Copy Channel Cancel Fig 3 115 Copy the selected channel in Bus Signal column ZEROPLUS Logic Analyzer x AN Do you want to delete the channel Delete Channel Cancel Fig3 116 Delete the selected channel in Bus Signal column 68 FMO7I4A PREM AG Blk ee The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 ZEROPLUS Logic Analyzer xX Delete All Ch 1 nes we A All the Buses and channels will be deleted Do you want to continue i Cancel Fig 3 117 Delete all Buses and channels in Bus Signal column ZEROPLUS Logic Analyzer x A All the Buses and channels will restore to the default Do you want to continue Cancel Restore Default Channels Fig3 118 Restore the deleted Buses and channels in Bus Signal Column Right Key Menu on the Waveform Area fj Find Data Value __ CtrltF fo Find Pulse Width ro To d Tip Flace Add Bar
166. plus Techneblogy Co Ltd fol Find Pulse Width Taveform Find JV Activate the Function of Chain Data Find Bus Signal Name Bust Next Previous Close Please key in a chain of data with a comma to compart them for example 0x32 0x45 0x50 0x66 Start At bs Hoe He x End t when Found Statistics 129 Address 1006 Taveform Find JV Activate the Function of Chain Data Find Bus Signal Name Bust Please key in a chain of data with a comma to compart them for example 0X32 0 45 0 50 0 66 01 02 03 Start At End t When Found Statistics ps E b Sti i d ho zx Statistics Address 990 The Zeroplus Logic Analyzer User s Manual V3 09 x x Previous Close 129 Fig 3 49 Process of Activating the Function of mE i FAM d d pmm ije fma jtm de 1 m ni Chain Data Find Fig3 50 Function of Chain Data Find Displayed on the Waveform Window x Signal Name AD Next Previous Close Find Min Pulse Width Max Pulse Width isti fin Range x fi e5535 Start At End t When Found Ds Dp Tn a Fig3 51 Pulse Width Find Dialog Box Signal Name It can select the single channel for Find Find It can select the Find conditions which are In Range Min Value gt lt and When users select the option of In Range they can input the value of the M
167. ptured data in the following process There are two formats for selecting Report Form and Pure Data Form See the following picture r Bus Output Parameter Data Format Yes No Hexadecimal Output Range From First Packet To Final Packet x fp fp Export Format Pure Data Form Option Pure Data Form F7 pop up an export file automatically Fig 3 10 Export Format Pull down Menu In the part of the Export Format when the users select the Report Form the Option button can t be used when users select the Pure Data Form the Option button can be used The Option pops up the Option dialog box as follows where users can customize the export data items in the dialog box which are Packet Name TimeStamp Length and DESCRIBE FMO7I4A 28 C2 PRE i ike ol Zeroplus Technology Co te ig Capture Window Ctrltct The Zeroplus Logic Analyzer User s Manual V3 09 Options IW Packet W Length M Name I DESCRIBE rj Timestamp Fig 3 11 Option Dialog Box For instance all the export options are selected entirely See the below picture 1 Bus1 1IC 3 1us 6X6E READ A ACK B425 D ACK B436 D ACK X47 D ACK X58 D ACK 6X69 D ACK OX7A D ACK OX8B D ACK GX9C D ACK GXAD D ACK GABE D ACK OXCF D ACK GXE B D ACK OXF 1 D ACK OX 82 D ACK OX13 D ACKS 2 Bus1 11C 1 7 64ms OS5D READ A ACK 644
168. r Menu Step2 Bus Trigger Setup 1 Bus Trigger Setup Bus Trigger l x Bus Hame Operator Bust Data Format Binary f Decimal f Hexadecimal f ASCII Cancel Default Help Fig 4 18 Bus Trigger Dialog Box Tip The Bus Name item can be selected from the pull down menu It only displays the general Bus name and also the ASCII mode is added 2 Protocol Analyzer Trigger Setup Tip This function can be used in the Modules LAP C 16032 LAP C 16064 LAP C 16128 LAP C 162000 LAP C 32128 and LAP C 321000 after registering And for the LAP C 322000 it is not necessary to register as it can be used for free Before registering the button OK in the Protocol Analyzer Trigger dialog box is the button Register when users press this button Register a Register dialog box will pop up Then users need to enter the correct Register Code so that they can use this function Protocol Analyzer Trigger Bus Trigger f x Allow Protocol Analyzer Trigger Protocol Analyzer Frotocol Facket Decimal f Hexadecimal f ASCII Cancel Default Help Fig 4 19 1 Before Registering 99 FMO7I4A SRP RABIES The Zeroplus Logic Analyzer Zeroplus Techneablogy Co Ltd User s Manual V3 09 Register Dialog Box Ee i x The Function is an optional purchased item Welcome to purchase its serial key to activate this Function for your necessary Enter serial key IF you ordered software or have questions abo
169. r Run Stop Data Tools Ee ZEROPLUS LAP C 32128 S H 000000 0000 LaBoc3 Window Help 5 x 18 x Denai a te Bl gt b gt izek sis i SoMHz nu ww 509 v e S Pace 1 x je Er i o ilm or953125 ay oy By Te FB BS lt gt Heient 30 Trigger Delay __ Font pop A ge il Seale 512 Display Pos A B 30 Total 131072 Display Ran Bus Setting Compr Rate No Bus Signal Trigger Filter Bus 5120 7680 10240 12800 ta t ADA rl BS O AAY es Ret ot Activate the Latch Function 40 POCO E T Protocol Analyzer Setting ANAL AP re Protocol Analyzer Parameters Config ZEROPLUS LA SPI MODULE 1 11 01 AZ A ZEROPLUS LA UART MODULE 2 10 01 ZEROPLUS LA 1 WIRE MODULE V1 09 01 FMM Q ZEROPLUS LA CAN 2 08 MODULE 1 31 00 S ZEROPLUS LA HOQ MODULE 2 06 01 gN ZEROPLUS LA I2C MODULE 2 01 02 JAB AE 2 AT AT BO ED V Use the DsDp Find s BiB More Protocol Analyzer http jwww zeroplus com tw cm vob B2 E2 le BBS bem S BA BA mp 4 gt 4 F gt Ready End Connected A Fig4 134 CAN 2 0B Bus Property Setup Double click the ZEROPLUS LA CAN 2 0B MODULE V1 31 00 to set the Protocol Analyzer CAN 2 0B Setup dialog box PROTOCOL ANALYZER CAN 2 068 SETUP Bus1 _ Configuration Packet Register Pin Aseig
170. ression function from the Sampling Setup dialog box then click Apply and OK to run US LAP C 327128 G H 000000 0000 LaDocS Set eel Trigger RunfStop Data Tools Window Help a L ea Fe Channels I x Group int clock Source Ungroup Asynchronous Clock Expand Collapse Frequency room Format Ro Synchronous Clack External Clock i Rising Edge Frequency rook Falling Edge Min 0 001Hz2 Max 100MHz Note The external clock voltage level is the same as the port 4 trigger level Rename Compression Mode Signal Filter RAM Size z Data Compression Signal Filter Setup Channel number vill be limited to 32 Apply x Cancel Restore Defaults Help Fig 4 139 Compression Mode Step4 Click Run and then activate the signal from the tested circuit to acquire the result on the waveform display area Fig 4 140 shows the result before and after compression has been applied o File Bus Signal Trigger Run Stop Data Tools Window Help 18 x Oe BS at ELB p Ol frzek z s th i0 a mr 50 ze 4h Pace ft Bo Bh Gal BB fo o2zaaiais ae Qe Bo Te BA le Height 30 Bar Bar Bar Bar Bar Trigger Delay 1 Fort Size fiz z ATAI Display Pos 0 A Pos 6452T v A T 64527 v Total 131072 Display Range 65535 65537B Pos 64497 z B SUiv i440 40960 20480 20480 40960 61 81920 102400 AE
171. right to left or from left to right Fig 3 62 Click Hand and then depress and hold the left mouse button to drag Reset the mouse function to the system default FMO7I4A 50 PRE ESAS i ARAE Zeroplus Techneablogy Coa Ltd TE Zoom In FY a4 Zoom Out Fs Tip Zoom In and Out can be switched by changing the percentage value in the pull down list 1 The system can set the value of Zoom In and Out The default unit is wus When zooming in it will be automatically changed to ns When zooming out it will be changed to ms s or ks 2 Pull down Menu There are thirty scales The maximum zoom in and out is the cycle of each grid 0 0001piece The minimum zoom in and out is the cycle of each grid 1 000 000 000 Zoom in and out the proportion with each grid being the cycle the zoom in and out is 100 The time of Zoom In and Out counts by the clock of each grid sample frequency For example 1 Each grid is being a cycle the zoom in and out is 100 The time of Zoom In and Out will be presented by the clock of each grid X 1 sample frequency 2 Each grid stands for the clock of 100 pieces the zoom in and out is 1 and the time of Zoom In and Out will be displayed by the cycle of each grid X 1 sample frequency l Show all Data Fio The Zeroplus Logic Analyzer User s Manual V3 09 10 ae on A Pos 396 Fos 399 Ao MO Fig 3 63 Normal Status 100 Geir
172. roplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 1 Features of Zeroplus Logic Analyzer 1 1 1 2 1 3 1 4 1 5 Package Contents Introduction Hardware Specifications system Requirements Device Maintenance and Safety FMO7I4A O PHARD Bee The Zeroplus Logic Analyzer Zeroplus Technobogy Co el User s Manual V3 09 Objective In this chapter users will learn about the package contents description hardware specifications system requirements and safety issues of the Zeroplus Logic Analyzer Although this chapter is purely informative we highly recommend reading this carefully to ensure safety and accuracy when performing any operation with the Zeroplus Logic Analyzer 1 1 Package Contents Verify the package contents before discarding packing materials The following components should be included in your product For assistance please contact our nearest distributor Table 1 1 Parts List for Retail Packages LAP C LAP C LAP C LAP C LAP C LAP C LAP C 16032 16064 a 6128 a 62000 BPN 28 PE 000 mara a a Analyzer 16 Pin Testing Cable 8 Pin Testing Cable Esvabarenavarare Probe USB CADIE E C a E E Cp 1 Pin Testing Cable White 2 Pin Testing Cable Black 1 1 1 1 1 1 1 This Driver CD consists of a multilingual software interface program as well as a multilingual User Manual 6 FMO7I4A 1 SRARHRPAIRAA The Zeroplus Logic Analyzer Zeroplus Techno
173. s Fig4 148 Display Bar Setup 2 The bar has two styles which are Original and Bar the default is Original style which denotes the bar function cannot be used When selecting Bar style the bar function can be activated 3 Bar Width when Bar style is selected the bar width can be set by users Tip The minimum bar width is 1 the maximum bar width is 65535 If the value exceeds the range or the font is not according to the requirement a tip window will appear Signal Filter Time Interval is denoted by Bar Fig4 149 Signal Filter Time Interval Tip The Signal Filter Time Interval is limited under the following situations A The Filter Delay and Display Bar of Signal Filter are not available under the compression mode B The Filter Delay and Display Bar of Signal Filter are not available under the double mode C The final two data are NULL D Logic Analyzer supports the Signal Filter Time Interval function on condition that the time interval between signal filter must be more than two clocks 172 FMO7I4A i SRARRABRAA The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 4 8 Noise Filter The Noise Filter function enables the system to filter the waveform that doesn t meet users requirements 4 8 1 Basic Software Setup of Noise Filter STEP1 Click Data on the Menu Bar then select Noise Filter to activate the noise filter function as the figure below Data
174. s 40ns 40ns 40ns 40ns 4L 80ns Ons 7Ons 40ns 80ns 310ns Fig 3 81 Show Time of Waveform under Time Display FMO7I4A E PHRSR E The Zeroplus Logic Analyzer Zeroplus Technobogy Coa Ltd User s Manual V3 09 x Workaround Waveform Hame E Rela aveform Background L ist Background 1 L ist Background 2 E B E L L Color Setting z B F E Preview After the background is altered A o fof ofa Vv corresponding color automatically changes i according to the Vv When being printed the background is white Fig 3 82 Color Setting See Section 3 6 for detailed instructions Bus Property i x Bus Setting AE Galor contig I activate the Lateh Function 40 3 Rising Edge Protocol Analyzer Setting 0 Protocol Analyzer Parameters Conkig M ZEROPLUS L4 Tal MODULE Y2 01 02 M 2EROPLUS LA SPI MODULE 1 11 01 M EROPLUS L UART MODULE 2 10 01 M 2EROPLUS L4 1 WIRE MODULE 1 09 01 M EROPLUS L4 CAN 2 06 MODULE 1 31 00 M 2 EROPLUS L4 HOO MODULE 2 06 01 St Bus Property Find More Protocol Analyzer http tivan zeroplus com tw M Use the DsDp ms ree _ Fig 3 83 Bus Property Bus Activate the function of analyzing the Bus See Section 4 5 for detailed Color Configuration Open the Color Configuration dialog WStRICHOnS box to set the conditions for the Bus Activate the Latch Function Activate
175. s C This is a Class A product which may cause radio interference in a domestic environment Note EN 61010 1 2001 specify degrees of pollution and their requirements Logic Analyzer falls under Level 2 Pollution refers to addition of foreign matter solid liquid or gaseous ionized gases which may produce a reduction of dielectric strength or surface resistivity Pollution Degree 1 No pollution or only dry non conductive pollution occurs This pollution has no effect Pollution Degree 2 Normally only non conductive pollution occurs Occasionally however temporary conductivity caused by the condensation must be expected Pollution Degree 3 Conductive pollution occurs or dry non conductive pollution which becomes conductive due to the condensation occurs In such conditions the equipment is normally protected against exposure to direct sunlight precipitation and wind but neither temperature nor humidity is controlled Storage Relative Humidity lt 80 Environment Temperature 0 50 Degrees C Conclusion After reading this section users should have a basic grasp of the Logic Analyzer A complete understanding of the section Device Maintenance and Safety is a critical prerequisite of any further operation as presented in the User Manual 14 FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 2 Installation 2 1 Software Installation 2 2 Hardware I
176. s have added a new Bar The data position of the Reaction Bar will be displayed in the List 182 FMO7I4A PHHH BR eS The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 Window of the Memory Analyzer Note The Ds Dp Bar and T Bar can t be displayed in the pull down menu Display Width It is used to set the display width of the List Window of the Memory Analyzer the default is 16 Users can select the 4 8 16 and 32 from the pull down menu and they also can input a value between 1 and 100 Color Users can vary the color of Addr Data R Data W and Alteration as their requirements The default color of the Addr is black the default color of the Data R is blue the default color of the Data W is red and the default color of the Alteration is gray Display Alteration l l l l l l The Data in the List Window of the Memory Analyzer will be cleared by pressing this button and the List Window will display the alteration status of each cell If the same Address has been written or read repetitively the background of the cell will be gray and the list window will display the Data of the last packet If the Address doesn t have any alteration the Address Data will display the data of the Address without the background color If it is the first time that the Address has been read we confirm that the data of the packet has been altered 1 corresponding position which is highlighted by the Blue frame
177. s than 190us whereas the High signal is no less than 40us kea _ tem Fig4 112 Pulse from Low to High Address The Address comprises 7 bits The initial Low signal lasts a period of t HW1 and if the write 0 status continues through the end of the t HWO period the signal will convert to High and last throughout the period of t CYCH as shown by the dotted line in the following figure Conversely if it is the write 1 status after t HW1 period of time the signal will convert to High and last throughout the period of t CYCH which is of 1 bit and no less than 190 us The t HW1 range is from 0 5us to 17us and no more than 50us The t HWO0 range is from 86us to 100us and no more than 145us Read Write Read Write is 1 bit 0 and 1 are displayed in the same way as the above description T RSPS The High signal lasts a period of 190us 320us The following 8 bit data is Send Host to BQ HDQ or Receive from BQ HDQ Data Data Made up by 8 bits and it is Send Host to BQ HDQ or Receive from BQ HDQ Data It operates in the same way as in 2 2 and the data is from LSB to MSB BQ HDQ To Host If the data transmission is read by BQ HDQ To Host the initial Low signal lasts a period of t DW1 and if the write 0 status continues through to the end of the t DW1 period the signal will convert to high and last throughout the period of t CYCD as shown by the dotted line in the following figure Conversely if it is the write 1 status a
178. see the below picture Bus Property xi Bus Setting i Bus olor Contig I Sctivate the Latch Function 40 Rising Edge Protocol 4nalyzer Setting f Protocol Analyzer Parameters Gontig ZEROFPLUS LA Izo MODULE 2 01 02 More Protocol Analyzer http jwa Taa es e j e Fig 3 85 Find Result Refresh Protocol Analyzer data See Section 4 10 for detailed instructions Adris Air ite Riad dat SS A A E E A E E E Une mi0 0E Cin giaa C a aone e e e dagleg owa ooo gapira N LOSI ee ca a ed ONA ONF Pi Fig 3 86 Memory Analyzer Interface See Section 4 11 for detailed instructions FMO7I4A 59 O FRARRARAA Zeroplus Techneblogy Co Ltd Multi stacked Logic Analyzer Settings Analog Waveform gt fu Single Analog Display Mixed Analog Display Tip When the function of Analog Waveform is activated the Analog Waveform will be displayed in the waveform area of the Bus s sub channel and take the space of four channels And four sub channels won t draw the waveform It notes that the sub channel of the Bus must be more than four channels The Zeroplus Logic Analyzer User s Manual V3 09 Multi stacked Logic Analyzer Settings l X f Memory Stack Channel Stack Please select the Logic Analyzer for stacking OMI S N 000000 0000 OM2 54N 000000 0000 OM3 3 N 00000 0000 M4 S N 000000 0000
179. slot and Write O time slot 3 During a write cycle all Write time slots must have duration of at least 6Ous and a recovery period of ius 4 When the I O line goes down Slave devices create samples from 15 60 us A Write 0 If the sampling is low 0 is generated as in Fig4 98 Write zero Time Slot Veuttur Veuwup MIN Vig MIN RES ISTOR MASTER Fig4 98 Write zero Time Slot B Write 1 If the sampling is high 1 is generated Note Read 1 is of a similar waveform pattern as in Fig4 99 Write one Time Slot Vuur V PULLUP MIN IH MIN Vie MAX 0V meee RESISTOR mmm ASTER Fig4 99 Wrote one Time Slot 142 FMO7I4A PREAMP Bike Bl The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 3 Read Data 1 When Slave reads data Master will generate a Read time slot 2 To initialize Read Data Master has to convert Data line from the high logic to the low 3 Data line must be kept as low as us 4 The Output Data of Slave must be 14us at most 5 To read from 15us where Read slot starts Master must stop driving I O Read data Time Slot PULLUP V PULLUP MIN VHN MASTER lt 4 SAMPLING WINDOW a RDV gt RESISTOR ASTER DS2432 Fig4 100 Read data Time Slot 6 When Read Time Slot ends I O Pin will be pulled back to the high count through the external resistor 7 During a write cycle all Write time slots must have dur
180. smission segment DATA The actual signal data transmitted by byte STOP This appears when SCL High and SDA Low bit only 121 FMO7I4A SRR PBhRe E The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 4 5 2 1 Software Basic Setup of Protocol Analyzer I2C Step1 Set up RAM Size Frequency Trigger Level and Trigger Position as described in Section 4 1 Step2 Set up the Falling Edge as the trigger condition on the signal which connects to the tested I2C data pin SDA Step3 Group the analytic channels into Bus1 Puss Signal Trigger Filter f La Hott tt pora Fi a Da RA l E Sampling Setup srann ri i Channels Setup aus Bus Property Analog Waveform Bus Signal Trigger Filter Group into Bus Ungroup from Bus Ctrl al Add Channel 7 eee Copy Channel o gh Delete Channel Delete All Channels Restore Default Channels a FE Format Row F Rename Fig4 65 Group into Bus Step4 Select Bus 1 then press Right Key on the mouse to list the menu Next click Bus Property or click Tools and the select Bus Property or click to open Bus Property dialog box eee er I I I I RE mex ae a a Pus ill Sampling Setup sean a izp Channels Setup Bus Property x Bus Property Bus Setting Analog Waveform f Bus Color Config RC BE ieee I Activate the Latch Function AO Bei k Ungroup from Bus Ctr
181. stores everything in this window You must make a further adjustment if the color setting is the only thing you want to restore See Fig 6 6 LE x Wor kar ound taveforn aveform Background List Background 1 List Background 2 Pus Text List Text ime Text Pus Error Bus Error Text a D GLEE AMi LEELEEELL EEL After the background 1s altered C corresponding color automatically changes according to the contrast ratio mi then being printed the background is white Fig 6 6 Restore Color Defaults SW14 Can I change the displayed waveform mode A 195 Yes you can There are two ways to do this First go through Data gt Waveform Mode and choose a waveform See Fig 6 7 I Select an Analytic Range ir Noise Filter nen Bus fidth Filter w Data Contrast E Find Data Value CtrltF El Find Pulse Width l To the Previous Edge Fil To the Next Edge Flz wo To Fa Add Bar ALttA si Delete Har ALttE Fe Zoom E ey Hand H Normal ESCAPE T Zoom In Fd ff Zoom Out F E Show all Data Fi eo Previous Zoom Etrit Data Format ee ade a nnmn Waveform Mode Reverse List Data Mode ra Square Waveform Sawtooth Waveform Fig 6 7 Waveform Mode The second alternative is to right click any place in the Waveform Display Area Then a menu will pop up Click Waveform Mode and choose a waveform See Fig 6 8 FMO7I4A PREM HABE The Zeroplus Logic Ana
182. stration you will receive an email consisting of your product registration information A password may be required for further customer services and other inquiries What should I do if online registration fails Do a screen grab of the window including the error message and email our customer service dept A customer service representative will be glad to assist you as soon as possible once the email is correctly received How may register if the purchasing date was more than one month ago In this case fill in the registration card and send it via post fax or email to our customer service dept and a representative will process the registration for you What is the warranty length for my product A two year FACTORY WARRANTY is offered in which you will have to send the defective product to the closest branch an authorized service site or our headquarters The in store warranty may vary and many require extra charges for various extended warranty policies The company is not being responsible for an in store warranty that exceeds our factory warranty Why should I register this product If you do not register this product the warranty will be counted from the manufacturing date indicated by the serial number of your product Thus we strongly recommend registering your product for your own benefit What should I do if the hardware serial number is previously registered In this case take a picture of the decal on the rear side
183. t Open Ctrlt0 Close Close the file being worked on Close Ctrl F4 Auto Save Save the required file automatically See Section 3 5 for me a detailed instructions Sa Export Waveform Export files into Text Auo ete txt and CSV Files csv an Export Waveform Ctrltihifttk Export Packet List Export the active E Export Packet List packet list E Mader Ctre Language Allow users to change the language interface of menus tool boxes Language d etc a crisp Print Preview Show three options PEA piewuan Bus Signal amp Trigger amp Filter Position e Display Area and Waveform Display Area Recent File See Fig 3 17 Exit Exit the program Exit Fig 3 2 File menu De S Fig 3 3 Standard Tool Bar 24 FMO7I4A J RARROSBRAA Zeroplus Technobogy Co Ltd Menu Bar File Menu Item C New Ctrl H Open Ctrl 0 Close Ctrl F4 Ej Save Ctrlts Save As Auto Save 25 The Zeroplus Logic Analyzer User s Manual V3 09 Detail Menu amp Dialog Box Open a New file ee ete oe Pr ce a aih i Er tal ois ee Mier reo Ls fe he i Sit ee lope Sanpa LAPS flat atc Peed Lae mhen teen ote Fig 3 6 Save As Dialog Box Save Save the current file Save As Specify the name of the file to be saved Auto Save Save the required file automatically FMO7I4A O PREHR DS PROS Zeroplus Techneblogy Co L
184. t it into the clip Fig 2 8 ee amp eee at _ ri T o ig 7 Fig 2 8 SX ENa a 3 2 Compress the probe as shown to aor eye ul A reveal two metal prongs Fig 2 8 wy he m 3 3 Place the metal prongs on a metal EE yf connector on the testing board and DA h release the fingers so that the prongs i rio Bm can grip the metal connector Fig i 3 2 9 N id sitios Fig 2 9 4 The Logic Analyzer will connect to the Zeroplus server for software updates if an internet connection is available 5 Unwanted signals can be filtered out using the Signal Filter or Filter Delay functions When measuring for a long period Compression makes memory more efficient 7 Trigger condition depends on the testing board If triggering does not work well try to narrow the trigger conditions and optimize them repeatedly 8 Ifa testing board has a lower frequency than Logic Analyzer sample signals according to the external clock 9 When sampling from an external clock filter extra signals with the Signal Filter function 10 Unused channels may be removed from the Bus Signal display using Bus Signal Menu gt Channels Setup 20 FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 3 User Interface 21 3 1 3 2 3 3 3 4 3 5 3 6 3 7 Menu amp Tool Bars Find Data Value Statistics Feature Customize Interface Auto Save Color Setting The Flow of Software Operat
185. t only needs to download the new Protocol Analyzer plug to cover the old Protocol Analyzer plug the speed is very fast Operating Instructions There are Plugins data file in the position of installing LA software All Protocol Analyzer plugs which are used at present are put in the data file the DLL file can be added or deleted in the content and in the Bus property all Protocol Analyzer plugs that can be used at present can be seen as the figure below CEE 3 EEs ia EE ww Prha Teal Hig debe eh uy Dee Creire fetter fe eK aal Re nae kl i amp 5 ie s amp a Of i PITRE Co PM ge gd RT Fig4 33 PluginsA Bus Property x Color Gontig s Activate the Latch Function 40 ee Rising Edge Protocol Analyzer Setting f Protocol Analyzer Parameters Gonhig 2EROPLUS LA lal MODULE 2 01 02 fT EROPLUS LA SPI MODULE 1 11 01 2EROPLUS L4 UART MODULE 2 10 01 2EROPLUS LA 1 WIRE MODULE 1 09 01 Z2EROPLUS L4 CAM 2 06 MODULE 1 31 00 ZEROPLUS L4 HDG MODULE 2 06 01 Find More Protocol Qnalyzer 9 Atkps ff zeroplus com tw IW Use the DsDp cael e Fig4 34 Bus Property Every Logic Analyzer Module can provide some basic Protocol Analyzer plugs When users need to use the analysis which is not provided by the basic Protocol Analyzer plugs you can purchase from our company and then 107 FMO7I4A i PARAH BRAS The Zeroplus Logic Analyzer
186. tF EJ Find Pulse Width l To the Previous Edge Wi Io the Next Edge Elz Te Go To T Bar T ti Add Bar ALttTA A Eo To fe Ber A Delete Bar ALttE By GoTo B Bar B FS Zoom E Go To More any Hand H R Hormal ESCAPE R Zoom In Fg Zoom Out Fa Show all Data F10 wo Previous Zoom Ctrltz Data Format Waveform Mode List Data Mode Fig 3 54 The selected bar will be shifted to the center of the waveform area s ete es Mia 1 fee tf alae ar Mind ugs mie Ba be pe Hi EEEE ae enho pe D eo o o re fe fee jara en AE an ee ee E S L E Banya Wiron eir Me Le Le G de oo Bpap he a heta amirim bard Ii limig kp Fe F Geri fe Sein am fat go a Fm rE H carck diid j Fig3 56 Add a Bar with the number between 0 and 9 FMO7I4A PRE ESAS i ARAE Zeroplus Technology Co te Delete Bar ALtt E Bar Delete a user defined bar 1 Click the above menu item from Data menu or click Delete Bar icon from Tool Bar 2 Select a user defined bar and click on Delete 3 Delete the selected Bar with the Delete key on the Keyboard Use the mouse to select the added bar and press the Delete key on the keyboard to delete the bar fs Zoom E hi Tip A Zoom In or a Zoom Out view will be centered in the Waveform Display Area and the new zoomed view will be sized according to the available space on the display 48 The Zeroplus Logic Analyzer User s Manual V3 09 xl Close
187. ta or the waveform Go to previous page of the data or the waveform Go to the beginning of the data or the waveform Go to the end of the data or the waveform Move the cursor up a grid Move the cursor down a grid Move the selected Bar or display left to prior the waveform or data Move the selected Bar or display right to posterior the waveform or data Release all selected bars and change Mouse mode to Normal Change trigger conditions FMO7I4A 203 O Pe IC IRA Zeroplus Technology Co H Hot Key F1 F2 F3 F5 F6 F7 F8 F9 F11 F12 The Zeroplus Logic Analyzer User s Manual V3 09 Table 7 4 Hot Keys 4 Equivalent Orders Help gt Logic Analyzer Help Decrease the sampling rate Increase the sampling rate Run Stop gt Single Run Run Stop gt Repetitive Run Run Stop gt Stop Data gt Zoom Out Data gt Zoom In Data gt To the Previous Edge Data gt To the Next Edge Statement Logic Analyzer Help Decrease the sampling rate Increase sampling rate Execute the acquirement once Execute the acquirement continuously Stop acquiring data Zoom out the waveform Zoom in the waveform Move forward to the prior variation waveform and center that location Move forward to the next variation waveform and center that location FMO7I4A O 2 Be AG 4 FS PR Zeroplus Technology Co H The Zeroplus Logic Analyzer User s Manual V3 09 7 2 Contact Us Table
188. td fx Export Waveform Ctrlt ShifttE The Zeroplus Logic Analyzer User s Manual V3 09 Export Taveform 2 x Savein jMyDocuments e fl ek Exe My Recent Documents Desktop My Documents ae My Computer My Network File name fi 111 Places Save as type Text Files txt v Cancel mBus Output Parameter Data Information Bus Item G Yes No b ta stye far SCS iY m Perform Model Data Model Ja Data ne Vertical Data Format i Peete Hexadecimal Output Range From Beginning of Data To End of Data V Pop up an export file automatically Fig 3 7 Export Waveform Dialog Box Export Waveform Export a file into text txt or CSV csv formats Bus Output Parameter Decide whether or not to display the parameters of the file to be exported Perform Model Choose whether to export the data either vertical or horizontal Data Style Include ALL ALL BUS PROTOCOL HAS CHANNELS PROTOCOL NO CHANNELS Data Model Export data changed function the selected items include All Data Sampling Changed Dot Compression Data Changed Dot Compression Some of the data value for the signal channels of sampling position are the same for example view the data changed and decrease export capacity this function will be good for users Output Range Choose the range of the data to export from the pull down menus Pop up an
189. te data Read data a oOo i 2 3 4 5 6 7 8 9 A Unused 0x0000 0x009F oxooao Unused 0X00B0 0X013F oxoi4o a es SS ce oxoiso o o O o O O O O oxoi7a TT S S S S S O Unused 0X0180 0X01EF oxoiro CT o d S S S Unused 0X0200 0XFFFF a Fig 4 165 Compact Mode Bemory Analyzer xj R4 lt gt gt gt Reset Refresh Merge Import Export Option Display Alteration Bus1 HPI write data Read data a Address Data Address Data Address Data Address Data Address Data Address Data oxooao oxooai oxooa2 oxo0a3 0x004 ox00A5 oxorso oxori ide oxoi43 Od 0x0145 oxoiso oxoisi oxors2 oxoisa oxois4 0x055 oxorso oxori oxois2 Koss oxore4 0x0165 oxorzo oxori oxorz2 ox0o173 oa 0x0175 oxorro oxori oxorr2 oxoirFs oxoiF4 0x01F5 Fig 4 166 Complete Mode 2 Buttons d It is used to find the first packet E It is used to find the previous packet E It is used to find the next packet gt l It is used to find the last packet Reset Ress The data status of each Address will be cleaned out and returned to the original status by pressing the button Refresh _Refresh_ Pressing this button can refresh the data status of each Address data when there are some alterations in the Bus Data Merg
190. the Signal Filter when using Double Mode the system doesn t support the function of Filter Delay How do update software The software will automatically check for and download updates This function deletes old software first and then downloads and installs the latest version FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 6 5 Others OT01 How was the Logic Analyzer developed A It took us more than two years to develop this product We envision Everyone carrying the Logic Analyzer and we would like to make some contributions to the electronics industry in return We also wish to transform the stereotypical OEM factory into a world class R amp D center OT02 Why is there a rich information database for game chips rather than the Logic Analyzer A First of all we apologize for any inconvenience caused by the lack of information pertaining to Logic Analyzers We are currently working very hard on multilingual information and documentations pertaining to the Logic Analyzer Visit our website for the latest drivers software and manuals http www zeroplus com tw logic analyzer en technical_support php In the meantime we will have updates ready when verified error free OT03 What was the original intention of developing this item A Originally the Logic Analyzer was just for use by our engineering department Later on we saw the greater need for this kin
191. the loose ends into the connectors on the circuit board to be analyzed Fig 2 2 Note The following sequence must be observed when connecting the connectors into the circuit board AO Brown A1 Red A2 Orange A3 Yellow A4 Green A5 Blue A6 Purple and A7 Gray 3 The circuit board must be grounded to the Logic Analyzer with the black Ground Cable Fig 2 3 4 Plug the square end of the USB cable into the Logic Analyzer Fig 2 4 5 Plug the thin end into the computer Fig 2 5 FMO7I4A FRARERGARAA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 At this point the computer should be able to detect the Logic Analyzer and finalize the installation for hardware connection For further information refer to the Troubleshooting and Frequently Asked Questions FAQ chapters in the User Manual Fig 2 6 An Assembly of Laptop Logic Analyzer and Testing Board 19 FMO7I4A O PRARRRARE The Zeroplus Logic Analyzer Zeroplus Technology Co User s Manual V3 09 2 3 Tips and Advice 1 When testing a circuit board make sure that the internal sampling frequency within the Logic Analyzer is at least four times higher than the external board frequency 2 Ifthe signal connector does not work well with the pins on the test board try to use the supplied probes ZEROPLUS 3 Usages of probes er 3 1 Take the loose end of the cable and ste A inser
192. then type the numbers into the column of the Trigger Delay Time or type numbers into the Trigger Delay Clock at the Trigger Delay page of the Trigger Property dialog box as shown in Fig 4 11 Or type the numbers into the column of Trigger Delay risser Delay 5 on the Tool Bar The system will display the Start of the waveform 96 FMO7I4A O REA AG i ABRES The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Tip The formula of Delay Time and Clock is Trigger Delay Time Trigger Delay Clock 1 Frequency To use the compression mode the lt Delay Time and Clock gt will be unavailable Step5 Trigger Position Setup Type the percentages or select the percentages from the pull down menu of the 20 on the Tool Bar or click the pull down menu of the Trigger Position on the Trigger Delay page of the Trigger Property dialog box as shown in Figs 4 12 4 13 4 14 and 4 15 The selected Trigger Position percentages will be displayed on the right side of the screen of the system Trigger Property Trigger Content Trigger Delay tri Trigger Page jam Page 1 v Min 1 Max 128 Trigger Position Pos 26213 han one trigger om the view W ZEROPLUS LAP C 32128 S H 00000000001 LaDoci lol x File Bus Signal Trigger Run Stop Data Tools Window Help lj x Dealan atl a alpy veo ek z o 50M4 J Ss Page fi o EA E fie w e R a
193. tion 0 and Select Color is Orange Kus Data Color x Bus Mame Busi Data Condition Data Min Data Max ea lo F Cancel Default Help Bus Signal Trigger Fig4 62 After the Bus Data Color Setting Tip Reserve the original state by the above steps STEP4 Activate the Latch Function Activate the Latch Function The default is not activated When the Latch function is activated the default channel is AO and there are three conditions for selecting Rising Edge Falling Edge and Either Edge the default 119 FMO7I4A PRE ESAS i ARAE The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 is Rising Edge Tip The Latch function is available for the LAP C 162000 LAP C 321000 and LAP C 322000 Modules and it is not available for the LAP C 16032 LAP C 16064 LAP C 16128 and LAP C 32128 Modules Set the Latch function for one Bus The setting of the Latch channel is AO the analysis function adopts Rising Edge Bus Property xj Bus Setting AD r Rising Edge Protocol Analyzer Setting Protocol Analyzer Parameters Gontig C EROPLUS LA T2C MODULE 2 01 02 C ZEROPLUS LA SPI MODULE 1 11 01 C ZEROPLUS L UART MODULE VW2 10 01 ZEROPLUS LA 1 WIRE MODULE 1 09 01 C EROPLUS LA CAN 2 068 MODULE 1 31 00 C ZEROPLUS LA ADO MODULE 2 06 01 IY Use the DsDp Find More Protocol Qnalyzer 9 Abpea zeroplus carm tws coed ee Fig4 63
194. ttcsnieeschedendnatondusead odexteeceteedud ladeadnatnslateadegenteancdiedaefedertnetsendntiedeceed sadness 178 4 10 1 Basic Software Setup of Refresh Protocol AnalyZer cccccccseccceceeeeeeeeeeeeeseeeeesaeeeeesaeeeesseneeesaees 178 4 11 Mem ry PUAIVIZSN a siceitcasiranectcsbhovt nce tacienutecs Ftnceduudebstiaiihtovstcdsu auteur lade ch Ee a Er ES CEA Eri ENE Ep teumtbanecudoransiceesbat 180 4 11 1 Basic Software Setup of Memory Analyzer ccccccseeececeeeeeceeeeeeaeeeeesaeeeeeseeeeeeaeeeesaeeeeesaeeeesaaees 180 4 12 Multi stacked Logic Analyzer SettingS ccccccccccseeeeeceeeeeeseeeeeeseeeeeeeeeeeeeeeeesseeeeesaaeeeesaeeeessgeeeesaaeees 184 4 12 1 Basic Software Setup of Multi stacked Logic Analyzer SettingS cccccccseeeeeeeeeeeeeeeeeeeeeeeeeaees 184 MROUDICSHOOUING ctectexeste sees setecs E a E E E ee dsanestectoctedes 186 Sl INSTANIATION TVOUDIESMOOUNG essensa Ara A EE EAA EAE EEN AAEE AARAA ORASE aN 187 5 2 Software Troubleshooting ig eccscccconcaczicassnccedarsneeadetaduesoendindvines secs dacseenduesanensdueedenanesinesdvededantunexstn dedesnenseedet 188 5 3 Hardware MrOUDISSMOOUING scicpa cin taiiestececundiadshaerdaadinacteadadvatdensunacadatanseevndaatGnadeaiedbuniadeaua tues dhwchadssdaebatiedanne take 189 aaa tits eee cseaee ston EE E E E sane coceuetecoseucteveesecterecex 190 O HVC WANS a A E E 191 Oe ONAN e E E E E E 193 Oo TRIS ea ON ar EE EEEE ape EA EEE dels etic E EE A AEAEE 197 64 Technica
195. tton to capture the image Cancel Click Cancel to end the capture FMO7I4A 29 PRE ES RAAR E Zeroplus Technobogy Coa Ltd Lancuage Tip The software will add other new languages besides the Chinese Simplified Si Chinese Traditional Tr and English And the new languages will be issued by way of the independent Installation File When users install the program of other new language the software will inspect the program automatically and supply the language for users to switch amp Print Ctrl P Tip This function has been enhanced now users can select the pages which they want to print or only the Current Page Print Preview Recent File Exit The Zeroplus Logic Analyzer User s Manual V3 09 Chinese Si Chinese Tr y English Fig 3 14 Choose among Chinese Simplified Si Chinese Traditional Tr and English ZEROPLUS Logic Analyzer The program needs to restart o Do wou want bo sawe khe current document Fig 3 15 When changing languages the above screen will be displayed and the program will need to be restarted Name Microsoft Office Document Image Writer 7 Properties Status Ready Type Microsoft Office Document Image Writer Driver Where Microsoft Document Imaging Writer Port Comment Copies Number of copies fi H pi elel Bu T Collate Pages from fi to ai C Curent Page rreren d Fig 3 17 Click to show a Preview of
196. uipment for the value of the sampling signals and puts them into the internal memory The software of the Logic Analyzer will read out the value from the memory and switch it to the waveform or status shown for users analysis What is the asynchronous Timing Mode Since the sampling clock and tested objects are not directly related to each other and the former won t be controlled by the latter the sampling clock and the tested signals will not be done at the same time We call this Timing Mode which means that in the same time interval you can get sampling data from the test equipment at one time such as every 10 seconds The internal clock the Logic Analyzer s inner confirmed one is often for sampling in Timing Mode as is the logic waveform What is the synchronous State Mode Because the sampling clock and measured object can be directly related and are controlled by the latter signals of the former and the latter can proceed simultaneously We call this State Mode In this mode the measured object provides the sampling clock State Mode is when the Logic Analyzer can obtain sampling data from the test equipment synchronously In other words when the test equipment has a signal or signal group this is the time to get the signal For example while the test equipment is sending out one rising edge the Logic Analyzer can start to obtain one signal What are A bar B bar and T bar The T bar A bar and B bar are labels
197. us Logic Analyzer ee Zeroplus Techneablogy Coa Ltd User s Manual V3 09 1 5 Device Maintenance and Safety Follow these instructions for proper operation and storage of the Logic Analyzer Table 1 7 General Advice Do not place heavy objects on the Zeroplus Logic Analyzer Avoid hard impacts and rough handling Protect the Logic Analyzer from static discharge Do not disassemble the Zeroplus Logic Analyzer this will void the warranty and could affect its operation Use a soft damp cloth with a mild detergent to clean Do not spray any liquid on the Zeroplus Logic Analyzer or immerse it in any liquid Do not use harsh chemicals or cleaners containing substances such as benzene toluene xylene or acetone Table 1 8 Electrical Specifications Minimum Typical Maximum Working Voltage DC 4 5 V DC 5 0 V DC 5 5 V Current at Rest a CurrentatWork Powerat Rest O J o PoweratWork J o DC 30V__ po DC 30V Veeterence SC BV _Input Resistance 500KQ 10pF_ Working Temperature 5C Storage Temperature 40C Refer to the User Manual for error analysis calculation V Reference FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 Table 1 9 Operating Environment WARNING Avoid direct sunlight Use in a dust free non conductive environment see Note Relative Humidity lt 80 Altitude lt 2000m Temperature 0 40 Degree
198. ustomize a more accurate numeric value of sampling site time or frequency difference will be calculated and displayed as shown in Fig 6 7 4 Pos O7Ous 4 T 69 s46us B 19 846v E Pos 060us B T 50uz Compr Rate 1 000 Fig 6 1 Bar Function SW05 Can triggers be differentiated in Pre Trigger and Post Trigger A Yes they can SWO6 Are all setup parameters and configurations saved as save my work A Yes everything in your work space except signal graph will be saved SW07 If have the wheel feature with my mouse or other pointing devices may adjust the waveform display zoom in the Waveform Display Mode by scrolling A This feature has been enhanced since V1 03 If your program version is prior to this version visit our website for the latest update at http www zeroplus com tw logic analyzer en technical_support php SW08 What are the extremes for Delay Time and Clock amp Trigger Delay Clock A The interface will inform you of the interval you may use However it varies from case to case depending on your test devices See Fig 6 2 Trigger Delay Time STS Min Sns Max 83 881ms Trigger Delay Clock m Min l Max 16776191 Fig 6 2 Delay Time and Clock 193 FMO7I4A gt PRB TARAE The Zeroplus Logic Analyzer Zeroplus Techneablogy Co Ltd User s Manual V3 09 SW09 How do I know the version number of my software interface program A Click Help from the
199. ut ordering software please Follow the appropriate instructions below Our sales team will respond to your enquiry as soon as possible gt gt By phone Tel 886 2 66202225 gt Applications through EMail service _2i zeroplus com tw gt gt Website Akko iiem 2eroplus com Ew Copyright C 1997 2009 ZEROPLUS TECHNOLOGY CO LTD cna Bus Trigger x Bus Trigger Protocol Analyrer Trigger W Allow Protocol Analyzer Trigger Frotocol Analyzer Frotocol Facket Data Format Binary Decimal ie Hexadecimal ASCII Cancel Default Help Fig 4 19 2 After Registering Allow Protocol Analyzer Trigger When it is selected the Protocol Analyzer Trigger function is activated And then users can set Protocol Analyzer Protocol Packet Value and Data Format Protocol Analyzer It only displays the name of Protocol Analyzer and only one name can be selected Protocol Packet It is displayed according to the packet in every protocol analyzer Value The value needs to be entered in the frame and the data mode can be selected by users according to their requirements the default is Hexadecimal When a value can be input in the selected protocol analyzer data the frame can be enabled Or the frame will be disabled For example Protocol Analyzer I2C when the protocol packet is DATA the frame can be used to the contrary when the protocol packet is START the frame is disabled Data Format The displayed value mo
200. v Compr Rate Ho ho en fs Sd _ L J MEL MUI a rer LL m ml B rp B O T egma i a en i 8 A o 2 Fig 4 8 Trigger Count Screen Shot 2 Step4 Trigger Page Delay Time and Clock The Trigger Page and the Delay Time and Clock can t be applied at the same time 1 Trigger Page Click Trigger Page then type the numbers or select the numbers from the pull down menu of the Page Page 1 gt on the Tool Bar or click the pull down menu of the Trigger Page on the Trigger Delay page of the Trigger Property dialog box as shown in Figs 4 9 4 10 and 4 11 The selected page numbers will be displayed on the screen Tip The Trigger bar T bar will not be displayed when the setup of the Trigger Page is more than 1 95 FMO7I4A P REEL TaAS ft BRAE The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 Trigger Property X Trigger Content Trigger Delay tri gger Range Trigger Page Delay Time and Clock Trigger Delay Time 100ns Min 100ns Max 1 671s Trigger Delay Clock m Win 1 Max 16711679 T Pos 0 Start Pos 65535 End Pos 65537 Note When more than one trigger pages are selected the trigger bar disappears from the view loj x 18 x 10 v i x Page a a at Ax B Bar Tx ie is l gt B lt gt Height Display Pos 512 A Pos 805 v A T 805 v A B 30 Display Range 203 1293 B
201. wal When the repetitive run is activated the waveform image or the state image will renew again and again Open the first file after stopping the Run When the repetitive run function is activated the waveform only displays the first file and it isn t renewed when the repetitive run is stopped the waveform still displays the first file Pa Fig3 159 Auto Save 84 FMO7I4A PREAH ih Bike Bl The Zeroplus Logic Analyzer Zeroplus Techneablogy Co Ltd User s Manual V3 09 3 6 Color Setting To modify Color click Tools gt Color Setting LE j x Wor kar ound taveform aveform Background List Background 1 List Backzround 2 List Text ime Text Pus Error Bus Error Text LA A LEED Ta After the background 1s altered E corresponding color automatically changes according to the contrast ratio lw When being printed the background is white Fig 3 160 Workaround and Waveform Color Setting Workaround Set the workaround color of the Logic Analyzer and the text Work around Waveform Name C Relating aveform Background List Background 1 List Background 2 OO LELLE qma Fig 3 161 Workaround Color Interface Waveform Background The Logic Analyzer s Waveform Viewer Background Color List Background 1 The Logic Analyzer s First Listing Viewer Background Color List Background 2 The Logic Analyzer s Second Listing Viewer Background Color All optional
202. without Internet access Most references refer to English web links 6 1 Hardware H01 Is it ok to substitute stock items for bundled cables and connectors A Yes users may use any compatible connectors and cables However to ensure consistency and accuracy in measurements and data we strongly recommend using the bundled connectors and cables Each of the Logic Analyzer s is calibrated with the bundled cables and connectors before packing H02 Does Zeroplus manufacture grippers How may purchase grippers A Yes we have a production line dedicated to grippers Contact our sales department and a sales representative will be happy to assist you H03 Is the memory size fixed If I just use one of the ports can expand the memory size A The Logic Analyzer s memory is fixed at 4 megabits Due to current hardware limitations the memory size cannot be modified even as the number of ports used changes H04 Are different external sampling frequencies for different channels possible A No there is only one external sampling frequency available H05 Can I disable or set a certain port to don t care while during compression A No during compression D Port will be set to be disabled H06 Why does the Logic Analyzer feature negative voltage calibration A This allows users to analyze any given signal H07 How do l adjust the Trigger Level A The adjustment of the trigger level is done with a port which consists of 8
203. ximum data being sieved out arrives at 1MB 255 255M Bits Per Channel Note The rate will change depending on the data being analyzed Signal Filter Setup k x m Filter Condition Trigger Condition PorntA Filter Condition i Trigger Condition PortB Filter Condition i Trigger Condition Pote Filter Condition Trigger Condition Filter Condition m Filter Delay Setup IV Activate Filter Delay r Select Filter Delay Mode Select Delay Start Point 5 r Delay Time According to Filter Condition Start Edge 1 C End Edge Min 1 Opposite of Filter Condition C Period Delay Max 65535 Display Bar Setup Bar Style Joriginal x Bar Width 1 OK Cancel Restore Defaults Ler Fig 3 22 Signal Filter Setup Dialog Box The function of Signal Filter is to use an alterable judgment circuit which can filter undesired signals in order to capture and store valuable data in the memory When the 32 FMO7I4A Phe PRA i Re The Zeroplus Logic Analyzer Zeroplus Technology Go Ltd User s Manual V3 09 combination of input signals from each channel meets the filter conditions the section of acquired data will be gathered by the Logic Analyzer and stored in the memory After storing the data it will return to the Logic Analyzer s system and be displayed as a waveform If the combinat
204. y checks odd parity even parity and none parity STOP This occurs when TXD is at high voltage This is adjustable this is commonly set to 1 or 2 Baud This is the data transmission speed according to the initial condition of START TXD This is the transmission direction It is MSB LSM by default 129 FMO7I4A PREAH ih Bike Bl The Zeroplus Logic Analyzer Zeroplus Techneblogy Co Ltd User s Manual V3 09 4 5 3 1 Software Basic Setup of Protocol Analyzer UART Step1 Set up RAM Size Frequency Trigger Level and Trigger Position as described in Section 4 1 Tip The Setup of the Frequency should be higher but not too far away from the Baud Rate of the test board Step2 Set up Either Edge as the trigger condition on the signals which are connected to the Tx pin or the Rx pin of the tested UART board Step3 Set up the Protocol Analyzer UART dialog box The Protocol Analyzer UART dialog box is set as the steps of I2C PROTOCOL ANALYZER UART SETUP Busl Pin Assignment Protocol Analyzer Color Protocal Analyzer Hame START DATA PARITY STOR Bus mt fo l LO a Protocol Analyzer Property Parity none parity Data Bit E Data Direction MSB gt LSE Baud Aate 9600 Stop Bit fi Sample Rate 70 Min 1 bp Max 1 UMbps Users can vary the baud rate and set up the value as your requirements Use the reverse data level for decoding Find the baud rate automatically based on t
205. y normal data which includes 1 ADDRESS and 1 DATA 126 FMO7I4A PREAH ih Bike Bl The Zeroplus Logic Analyzer Zeroplus Techneablogy Coa Ltd User s Manual V3 09 Packetz2 It is commonly normal data which includes 1 ADDRESS and 4 DATA Packet3 The data includes 1 ADDRESS Packet4 The data includes 1 ADDRESS and 4 DATA Packet Length When judging the start of I2C it is the Packet TimeStamp This Data Start is regarded as Packet Timestamp This Unknow register is Unknow_End Flag Packet Length Fig4 73 Packet Length Packet Length From START Start s TimeStamp to STOP Unknow_End Flag TimeStamp Packet Idling Length From Unknow_End Flag TimeStamp to Starts TimeStamp This Unknow register is Unknow_End Flag 127 FMO7I4A J gt RAERERGBESA The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 09 4 5 2 4 Protocol Analyzer I2C Data Format Analysis FEOTOCOL ABALTZEE I2C SETUP Busi Protocol Analyzer I2C Data Format Setup Dialog Box Users can set the Data Format of the DATA SLAVE ADDR and REG ADDR as their requirements When Activate is selected the data formats are decided by the settings in the Protocol Analyzer when Activate is not selected the data formats are decided by the settings in the main program 128 FMO7I4A C O PREP i Bee The Zeroplus Logic Analyzer Zeroplus Techneablogy Co el User s Manual V3 09 4 5
206. ze Show Time of Waveform Color Setting aus Bus Property an Refresh Frotacol Analyrer ome Memory Analyzer Multi stacked Logic Analyzer Settings Analog Waveform Fig4 170 Multi stacked Logic Analyzer Settings Interface STEP 2 Click E to open Multi stacked Logic Analyzer Settings dialog box 184 Bulti stacked Logic Analyzer Setting V Activate Stack Stack Type Memory Stack Please select the Logic Analyzer for stacking Mi 8 000000 0000 M2 3 8 000000 0000 IMS 3 8 000000 0000 CiM 3 8 000000 0000 Synchronous Channel oe aj Synchronous Trigger Condition Rising Edze Cancel Help Fig4 171 Multi stacked Logic Analyzer Settings Dialog Box FMO7I4A PRARE GARE Al The Zeroplus Logic Analyzer Zeroplus Techneablogy Co Ltd User s Manual V3 09 Activate Stack Click the checkbox to activate the function of the Multi stacked Logic Analyzer the default is non activated Stack Type Users can select the Memory Stack and Channel Stack the default is the Channel Stack Please select the Logic Analyzer for stacking It can display all the connected Logic Analyzers and the S N code of them The M1 indicates the first Logic Analyzer and the M2 indicates the second Logic Analyzer M3 and M4 are similar to the previous Users should select two or more Logic Analyzers but the most analyzers users can select is four Synchronous Channel Select the synchronous

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