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AT E Series User Manual

1. Data 16 Calibration 6 DACs i Configuration O Memory m Q IRQ lant uo 2 DMA lant 8 E c T T oO 8 PFI Trigger Trigger Analog Input eid i y ges 1 Timing Control 1 Analog IEEPROM DMA gt o Ss cane pag ste on ur g Counter Bus inasre atid Timing vo DAQ STC interface PASus DAQPnP and Oo AUN oe Ot man Se a A BP DATAS Interface Play x Analog Output RTSI Bus Analog 8255 Bus Digital VO 8 j Digital VO Timing Control Interface Son cono 19e KC L PA lt AT MIO 16DE 10 ONLY lt x 8255 lt PB 8 DIO AO Control Port PC 8 lt Ses Y Figure 3 3 AT MIO 16E 10 and AT MIO 16DE 10 Block Diagram The primary differences between the AT MIO 16E 10 and the AT MIO 16DE 10 are in the 8255 DIO port which is not present on the AT MIO 16E 10 and the I O connector National Instruments Corporation 3 3 AT E Series User Manual Chapter 3 Hardware Overview Figure 3 4 shows a block diagram for the AT MIO 16XE 10 REF Voltage Calibration DACs REF Buffer 16 Bit Selection Programmable Sampling ADC Data Switches Gain AD FIFO Transceivers Amplifier Converter EEPROM Configuration Memory Al Control Trigger Level Analo e IRQ g A 5 D
2. 2 2 ura iu ar darc iar uu AT E Series User Manual Figure 4 14 Typical Pretriggered Acquisition SCANCLK Signal SCANCLK is an output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external analog input multiplexers indicating when the input signal has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 15 shows the timing for the SCANCLK signal CONVERT j NEC SCANCLK lt gt lt gt i m tg 50 to 100 ns tw 400 to 500 ns Figure 4 15 SCANCLK Signal Timing 4 32 National Instruments Corporation Chapter 4 Signal Connections EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode software controls the level of the EXTSTROBE signal A 10 us and a 1 2 us clock are available for generating a sequence of eight pulses in the hardware strobe mode Figure 4 16 shows the timing for the hardware strobe mode EXTSTROBE signal ty 7 600 ns or 5 us Figure 4 16
3. Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias DACOOUT AO 0 1 Q Short circuit 5at 10 5at 10 20 to ground V us DACIOUT AO 0 1 Short circuit 5at 10 5at 10 20 to ground V us EXTREF AI 10 kQ 25 15 AOGND AO DGND DO VCC DO 0 10 Short circuit 1A to ground DIO lt 0 7 gt DIO Nos 40 5 13 at Voc 0 4 24 at 0 4 1 1 50 KQ pu SCANCLK DO 3 5 at Vic 0 4 5at0 4 1 5 50 KQ pu EXTSTROBE DO 3 5at Voc 0 4 5 at 0 4 1 5 50 kQ pu PFIO TRIGI ADIO 10kQ Voc 0 5 35 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PHII TRIG2 DIO Vee 0 5 3 5 at Va 0 4 5at0 4 1 5 50 KQ pu PFI2 CONVERT DIO Voc 10 5 3 5at Vc 0 4 5at0 4 1 5 50 KQ pu PFI3 GPCTRI SOURCE DIO Vex 0 5 3 5 at Voc 0 4 5 at 0 4 1 5 50 KQ pu PFI4 GPCTR1_GATE DIO Veg 0 5 3 5 at Ve 0 4 5at0 4 1 5 50 kQ pu GPCTRI OUT DO 3 5 at Voc 0 4 5 at 0 4 1 5 50kQ pu PFIS UPDATE DIO Ve 0 5 3 5 at Voc 0 4 5 at 0 4 1 5 50 kQ pu PFI6 WFTRIG DIO Veg 0 5 3 5 at Voc 0 4 5at0 4 1 5 50 kQ pu PHI7 STARTSCAN DIO Voc 0 5 3 5 at Voc 0 4 5 at 0 4 1 5 50kQ pu PFI8 GPCTRO_SOURCE DIO ME 40 5 3 5 at Vs 0 4 5at0 4 1 5 50 kQ pu PFI9 GPCTRO GATE DIO Vic 40 5 3 5 at Voc 0 4 5at0 4 1 5 50 kQ pu National Instruments Corporation 4 9 AT E Series User Manual
4. 16 single ended or 8 differential software selectable Type of ADG temere Successive approximation Resolution sseeesseeeeeeee 16 bits 1 in 65 536 Maximum sampling rate 100 kS s guaranteed Input signal ranges Board Range Software Selectable Board Gain Software Selectable Bipolar Unipolar 1 10 0 V 0to 10 V 2 5 0 V 0to 5 V 5 2 0 V 0to2 V 10 1 0 V Otol V 20 0 5 V 0 to 0 5 V 50 0 2 V 0 to 0 2 V 100 0 1 V 0 to 0 1 V National Instruments Corporation A 21 ATE Series User Manual Appendix A AT E Series User Manual Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Input coupling 0 0 eee eee DC Maximum working voltage Each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH lt 0 15 gt AISENSE FIFO buffer size oo aasan 512 samples Data transfers cccccceecceeeeceeeceee sees DMA interrupts programmed I O DMA modes xvn teen Single transfer demand transfer Configuration memory size 512 words Transfer Characteristics Relative accuracy eese 0 75 LSB typ 1 LSB max DINI EEEE E ROME 0 5 LSB typ 1 LSB max No missing codes seeeeeese 16 bits guaranteed Offset error Pregain error aft
5. 2 000 ppm max Voltage Output RAN G6 5 05 Gees Secdsseoes o iere 10 V 0to 10 V software selectable Output coupling 0 eee eee DC Output impedance eee 0 1 0 Current drive eee ceeeeeseeneeeees 5 mA Protection one Short circuit to ground Power On state eeeessesseeeee 0 V 4 20mV Dynamic Characteristics Settling time for full scale step 10 us to 1 LSB accuracy Slew Late ciet pee et 5 V us NOISG sitter Oe OR e IRE ER IRSE 60 uVrms DC to 1 MHz National Instruments Corporation A 25 AT E Series User Manual Appendix A Digital 1 0 Timing 1 0 AT E Series User Manual Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Stability Offset temperature coefficient 50 uV C Gain temperature coefficient 7 5 ppm C Number of channels 8 input output Compatibility esee TTL CMOS Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current 320 uA Input high current 10 pA Output low voltage 0 4 V pz 24 mA Output high voltage 4 35 V lop 13 mA Power on state ereere Input High Z Data transfers sseeee Programmed I O Number of channels 2 up down counter timers frequency scaler Resolution Counter timers esses 24 bits
6. 15 min Calibration interval year External calibration reference gt 6 and 9 999V National Instruments Corporation A 35 AT E Series User Manual Appendix A Bus Interface Physical Environment AT E Series User Manual Specifications for AT MIO 16XE 50 Onboard calibration reference Temperature coefficient Long term stability Power Requirement 43 VDE 5426 tette Power available at I O connector Dimensions not including connectors I O connector eeeeeee Operating temperature Storage temperature Relative humidity 4 36 5 000 V 42 mV actual value stored in EEPROM 2 ppm C max 15 ppm J1 0007 Slave 0 75 A 4 65 VDC to 5 25 VDC at 1 A 33 8 by 9 9 cm 13 3 by 3 9 in 68 pin male SCSI II type 0 to 55 C 55 to 150 C 5 to 90 noncondensing National Instruments Corporation Appendix Optional Cable Connector Descriptions This appendix describes the connectors on the optional cables for the AT E Series boards Figure B 1 shows the pin assignments for the 68 pin MIO connector This connector is available when you use the SH6868 or R6868 cable assemblies with the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 It is also one of the two 68 pin
7. AT E Series User Manual 4 10 National Instruments Corporation Chapter 4 Signal Connections Table 4 3 1 0 Signal Summary AT MIO 16E 10 and AT MIO 16DE 10 Continued Impedance Protection Sink Rise Input Volts Source mAat Time Signal Name Drive Output On Off mA at V V ns Bias VCC DO 0 10 Short circuit 1A to ground DIO lt 0 7 gt DIO N oe 0 5 13 at V 0 4 24at04 11 50kQ pu PA lt 0 7 gt DIO Nic 40 5 2 5 at 3 9 2 5 at 0 4 5 100 kQ pu PB lt 0 7 gt DIO b 40 5 2 5 at 3 9 2 5 at 0 4 5 100 KQ pu PC 0 7 DIO Vec 70 5 2 5 at 3 9 2 5 at 0 4 5 100 KQ pu SCANCLK DO 3 5 at V 0 4 5at 0 4 1 5 50 KQ pu EXTSTROBE DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFIO TRIGI DIO Vee t0 5 35at V 0 4 Sat 0 4 1 5 50 KQ pu PFI1 TRIG2 DIO Voc 799 3 5 at V 0 4 5at0 4 1 5 50 KQ pu PFI2 CONVERT DIO Nac 40 5 3 5 at V 0 A 5at0 4 1 5 50 KQ pu PFI3 GPCTRI SOURCE DIO Voc 799 3 5at V 0 4 5 at0 4 1 5 50 KQ pu PFI4 GPCTR1_GATE DIO Voc 795 3 5 at V 0 4 5at0 4 1 5 50 KQ pu GPCTRI OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFIS UPDATE DIO Voc 799 3 5 at Voc 04 5at0 4 1 5 50 KQ pu PFI6 WFTRIG DIO Vec 05 3 5at Voc 04 5at0 4 1 5 50 KQ pu PFI7 STARTSCAN DIO Voe 0 5 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFIS GPCTRO SOURCE DIO
8. Trigger Figure 3 10 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the high Value highVal e 2205 cione ced cen eie ec EN Urb dele ies lowValue LH dr Figure 3 11 Inside Region Analog Triggering Mode In high hysteresis analog triggering mode the trigger is generated when the signal value is greater than highValue with the hysteresis specified by lowValue highValue lowValue Trigger Figure 3 12 High Hysteresis Analog Triggering Mode National Instruments Corporation 3 17 AT E Series User Manual Chapter 3 Hardware Overview Digital 1 0 In low hysteresis analog triggering mode the trigger is generated when the signal value is less than lowValue with the hysteresis specified by highValue highValue ioci oasis Se e L fy 4 a fa a lowValue ____ END UD CN PTS UAA i Trigger Figure 3 13 Low Hysteresis Analog Triggering Mode The analog trigger circuit generates an internal digital trigger based on the analog input signal and the user defined trigger levels This digital trigger can be used by any of the timing sections of the DAQ STC including the analog input analog output and general purpose counter timer sections For example the analog input section can be
9. 3 1 AT MIO 64E 3 Block Diagram eee 3 2 AT MIO 16E 10 and AT MIO 16DE 10 Block Diagram 3 3 AT MIO 16XE 10 Block Diagram eene 3 4 AT AI 16XE 10 Block Diagram eene 3 5 AT MIO 16XE 50 Block Diagram esee 3 6 Dither i bentur m omit 3 11 Analog Trigger Block Diagram eee 3 16 Below Low Level Analog Triggering Mode sess 3 16 Above High Level Analog Triggering Mode sssse 3 17 Inside Region Analog Triggering Mode esses 3 17 High Hysteresis Analog Triggering Mode sss 3 17 Low Hysteresis Analog Triggering Mode sss 3 18 viii National Instruments Corporation Figure 3 14 Figure 3 15 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 4 11 Figure 4 12 Figure 4 13 Figure 4 14 Figure 4 15 Figure 4 16 Figure 4 17 Figure 4 18 Figure 4 19 Figure 4 20 Figure 4 21 Figure 4 22 Figure 4 23 Figure 4 24 Figure 4 25 Figure 4 26 Figure 4 27 Figure 4 28 Figure 4 29 Figure 4 30 Figure 4 31 Figure 4 32 Figure 4 33 Figure 4 34 Figure 4 35 Figure 4 36 Figure 4 37 Contents CONVERT Signal Routing eese 3 19 RTSI Bus Signal Connection
10. Board Range Software Selectable Board Gain Software Selectable 5 V 0 10 V 0 5 10 V 1 5 V 0 to 10 V 2 42 5 V 0to5V 5 1 V 0to2 V 10 500 mV Otol V 20 250 mV 0 to 500 mV 50 100 mV 0 to 200 mV 100 50 mV 0 to 100 mV AT E Series User Manual A 12 National Instruments Corporation Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Input coupling Max working voltage signal common mode Each input should remain within 11 V of ground Overvoltage protection 35 V powered on 25 V powered off Inputs protected ACH lt 0 15 gt AISENSE FIFO buffer size 512 samples Data transfers DMA interrupts programmed I O DMA modes Single transfer demand transfer Configuration memory size 512 words Transfer Characteristics Relative accuracy eee 0 2 LSB typ dithered 1 5 LSB max undithered NIS iain dle Be Aiea 0 2 LSB typ 1 0 LSB max No missing codes 12 bits guaranteed Offset error National Instruments Corporation Pregain error after calibration Pregain error before calibration Postgain error after calibration Postgain error before calibration After calibration Gain 1 Before calibration Gain 1 with gain error adjusted to O at gain 1 4 13 2 uV max 24 mV max 0 5 mV max 100 mV max Gain error relative to calibration
11. All timing values are in nanoseconds National Instruments Corporation Figure 4 38 Mode 1 Input Timing 4 53 AT E Series User Manual Chapter 4 Signal Connections Mode 1 Output Timing Figure 4 39 details the timing specifications for an output transfer in Mode 1 T8 WR i ie OBF i i Ti a i 4 INTR ow ACK i T5 DATA T2 Name Description Minimum Maximum T1 WR 0 to INTR 0 250 T2 WR 1 to Output 200 T3 WR 1 to OBF 0 150 T4 ACK 0 to OBF 1 150 T5 ACK Pulse Width 100 T6 ACK 1 to INTR 1 150 All timing values are in nanoseconds Figure 4 39 Mode 1 Output Timing AT E Series User Manual 4 54 National Instruments Corporation Chapter 4 Signal Connections Mode 2 Bidirectional Timing Figure 4 40 details the timing specifications for bidirectional transfers in Mode 2 tOT o3 T6 OBF Em c lum INTR r i T7 i lt ACK i T3 i pe i i STB T T P i P T10 i IBF i RD i i T2 iTS T8 i1 T9 d pe rw i _ Name Description Minimum Maximum Tl WR 1 to OBF 0 150 T2 Data before STB 1 20 T3 STB Pulse Width 100 E T4 STB 0 to IBF 1 150 T5 Data aft
12. gt tgsu lt tgh I q tow tout Source Clock Period tse 50 ns minimum Source Pulse Width tsp 23 ns minimum Gate Setup Time tosu 10ns minimum Gate Hold Time tgh Ons minimum Gate Pulse Width tow 10 ns minimum Output Delay Time tout 80 ns maximum National Instruments Corporation 4 49 Figure 4 37 GPCTR Timing Summary The GATE and OUT signal transitions shown in Figure 4 37 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal would apply when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on your AT E Series board Figure 4 37 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or AT E Series User Manual Chapter 4 Signal Connections AT E Series User Manual low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by tosu and tgh in Figure 4 37 The gate signal is not required to be held after the active edge of the source signal If an internal timebase clock is used the gate signal cannot be synchronized with the clock In this
13. Duration tenerte Stability Offset temperature coefficient Gain temperature coefficient Internal reference National Instruments Corporation A 7 Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 10 V 0 to 10 V EXTREF 0 to EXTREF software selectable DC 0 1 max 5 mA max Short circuit to ground OV 11 V 25 V powered on 15 V powered off 200 mV 30 mV 1 5 us 50 uV C 25 ppm C AT E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Digital 1 0 Timing 1 0 AT E Series User Manual Number of channels Compatibility External reference Digital logic levels 25 ppm C 8 input output TTL CMOS Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vi 0 V 320 uA Input high current Vi 5 V 10 uA Output low voltage 0 4 V oz 24 mA Output high voltage 4 35 V lop 13 mA Power on state Data transfers Number of channels Compatibility Resolution Counter timers eese Frequency scalers Base clocks available Counter timers ees Frequency scalers A 8 Input High Z Programmed I O 2 up down counter timers 1 frequency scaler 24 bits 4 bits TTL CMOS 20 MHz
14. cccccceecceeeeceeeseee sees DMA interrupts programmed I O DMA modes eene Single transfer demand transfer Transfer Characteristics Relative accuracy INL After calibration 0 3 LSB typ 0 5 LSB max Before calibration 4 LSB max DNL After calibration 0 3 LSB typ 1 0 LSB max Before calibration 3 LSB max Monotonicity eeeeeeeeeeeeeeeeeees 12 bits guaranteed after calibration Offset error After calibration sss 1 0 mV max Before calibration 200 mV max Gain error relative to internal reference After calibration 0 01 of output max Before calibration 0 5 of output max Gain error relative to external reference 0 to 0 5 of output max not adjustable A 6 National Instruments Corporation Appendix A Voltage Output Ranges 2o ERES er e E UURHUN Output coupling Output impedance eee Current driver ca estre Protection Power on state External reference input Range etes Overvoltage protection Input impedance Bandwidth 3 dB Dynamic Characteristics Settling time for full scale step Slew rate Glitch energy at midscale transition Magnitude Reglitching disabled Reglitching enabled
15. seen 3 21 VO Connector Pin Assignment for the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 esee 4 2 T O Connector Pin Assignment for the AT MIO 64E 3 4 3 T O Connector Pin Assignment for the AT MIO 16DE 10 4 4 AT E Series PGIA uia eadeni e rete e Eti ERES 4 16 Summary of Analog Input Connections eesseeeeeeeee 4 18 Differential Input Connections for Ground Referenced Signals 4 20 Differential Input Connections for Nonreferenced Signals 4 21 Single Ended Input Connections for Nonreferenced or Floating Sign ls e Rep eee reete 4 24 Single Ended Input Connections for Ground Referenced Signal 4 25 Analog Output Connections eese nennen 4 27 Digital I O Connections sese 4 28 Timing I O Connections oett tienen te ettet te 4 30 Typical Posttriggered Acquisition eere 4 31 Typical Pretriggered Acquisition esee 4 32 SCANCLK Signal Timing essent rennen nennen 4 32 EXTSTROBE Signal Timing eene 4 33 TRIGI Input Signal Timing eese 4 34 TRIG1 Output Signal Timing eee 4 34 TRIG2 Input Signal Timing eese 4 35 TRIG2 Output Signal Timing serene 4 35 STARTSCAN Input Signal Timing
16. PFIO TRIG1 PFI2 CONVERT TRIG1 CONVERT Source Source DGND CT I O Connector E Series Board Figure 4 12 Timing 1 0 Connections Programmable Function Input Connections AT E Series User Manual There are a total of 13 internal timing signals that you can externally control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the board I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector software can turn on the output driver for the PFI2 CONVERT pin You must be careful not to drive a PFI signal externally when it is configured as an output 4 30 National Instruments Corporation Chapter 4 Signal Connections As an input you can individually configure each PFI for edge or level detection and for polarity selection as well You can use the polarity selection for any of the 13 timing signals but the edge or level detection will depend upon the particular timing signal being controlled The detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse widt
17. Rising edge polarity i Falling edge polarity J tw 10 ns minimum Figure 4 35 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_0UT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC board general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 36 shows the timing requirements for the GPCTR1_OUT signal GPCTR1_SOURCE GPCTR1 OUT Pulse on GPCTR1 OUT Toggle output on TC TC AT E Series User Manual Figure 4 36 GPCTR1 OUT Signal Timing 4 48 National Instruments Corporation Chapter 4 Signal Connections GPCTR1 UP DOWN Signal This signal can be externally input on the DIO7 pin and is not available as an output on the I O connector General purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and leave the DIO7 pin free for general use Figure 4 37 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of your AT E Series board V SOURCE H V IL GATE IH IL O Von UT V OL
18. Chapter 4 Signal Connections Table 4 2 1 0 Signal Summary AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Continued Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias GPCTRO OUT DO 3 5 at V e 0 4 5 at 0 4 1 5 50kQ pu FREQ_OUT DO 3 5 at Voc tA 5 at 0 4 1 5 50 KQ pu IDIO lt 6 7 gt are also pulled down with a 50 kQ resistor AI Analog InputDIO Digital Input Outputpu pullup AO Analog OutputDO Digital OutputADIO Analog Digital Input Output 2Also pulled down with a 10 kQ resistor The tolerance on the 50 kQ pullup and pulldown resistors is very large Actual value may range between 17 kQ and 100 kQ Table 4 3 shows the I O signal summary for the AT MIO 16E 10 and AT MIO 16DE 10 Table 4 3 1 0 Signal Summary AT MIO 16E 10 and AT MIO 16DE 10 Impedance Protection Sink Rise Input Volts Source mA at Time Signal Name Drive Output On Off mA at V V ns Bias ACH lt 0 15 gt Al 100 GQ in 35 25 200 pA parallel with 50 pF AISENSE AI 100 GO in 35 25 200 pA parallel with 50 pF AIGND AO DACOOUT AO 0 10 Short circuit 5 at 10 5 at 10 15 to ground V us DACIOUT AO 0 10 Short circuit 5 at 10 5 at 10 15 to ground V us EXTREF AI 10kQ 35 25 AOGND AO DGND DO
19. Before calibration 2250 ppm of reading max With gain error adjusted to 0 at gain 1 Gam 2 T0 inest es 100 ppm of reading Gam 100 eode 250 ppm of reading Amplifier Characteristics Input impedance Normal powered on 7 GQ in parallel with 100 pF Powered off ssssssss 820 O min Overload eem es 820 O min Input bias current eeesees 10 nA Input offset current 0 0 eee 20 nA CMRR DC to 60 Hz Gan 1 sisse 80 dB National Instruments Corporation A 31 AT E Series User Manual Appendix A Specifications for AT MIO 16XE 50 Dynamic Characteristics Bandwidth 50 us max to 1 LSB all gains and ranges System noise including quantization noise Gain 1 2 10 Gain 100 Crosstalk Stability Offset temperature coefficient PREG alts sess oic RR i naa t Postin i siete renes Gain temperature coefficient Analog Output Output Characteristics Number of channels Resolution Max update rate Type of DAC FIFO buffer size AT E Series User Manual A 32 0 5 LSB rms 0 8 LSB rms bipolar 1 4 LSB rms unipolar 85 dB max DC to 20 kHz 1 uV C 12 uV C 5 ppm C 2 voltage 12 bits 1 in 4 096 20 kS s Double buffered National Instruments Corporation Appendix A Specifications for AT MIO 16XE 50 Data transfers eeeeeeI DMA interrupts programme
20. Board Gain Software Selectable Bipolar Unipolar 0 5 10 V 1 5 V 0 to 10 V 2 z2 5V 0to5 V 5 1V 0to2V 10 500 mV Otol V 20 250 mV 0 to 500 mV 50 100 mV 0 to 200 mV 100 50 mV 0 to 100 mV Input coupling 0 00 eee eeee DC Max working voltage signal common mode Each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH lt 0 63 gt AISENSE AISENSE2 FIFO buffer size AT MIO 16E 1 8 192 samples AT MIO 16E 2 AT MIO 64E 3 sess 2 048 samples Data transfers eeeeeemI DMA interrupts programmed I O AT E Series User Manual A 2 National Instruments Corporation Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 DMA modes seen Single transfer demand transfer Configuration memory size 512 words Transfer Characteristics Relative accuracy eeeeeeee 0 5 LSB typ dithered 1 5 LSB max undithered DNEZ5uuvIBISeed 0 5 LSB typ 1 0 LSB max No missing codes sssee 12 bits guaranteed Offset error Pregain error after calibration 12 uV max Pregain error before calibration 2 5 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibr
21. Multifunction 1 0 Boards for the PC AT AT E Series User Manual January 1999 Edition Part Number 320517G 01 Copyright 1994 1999 National Instruments Corporation All rights reserved Internet Support support natinst com E mail info natinst com FTP Site ftp natinst com Web Address http www natinst com Bulletin Board Support BBS United States 512 794 5422 BBS United Kingdom 01635 551422 BBS France 01 48 65 15 59 Ju Fax on Demand Support 512 418 1111 CS o gt COOK lt C gt Telephone Support U S Tel 512 795 8248 Fax 512 794 5678 Os lt C gt International Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 5734815 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 520 2635 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 United Kingdom 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 78730 5039 Tel 512 794 0100 Important Information Warranty Copyright Trademarks The AT E Series boards are warranted against defects in materials and workmanship for a period of one year from the d
22. PB4 DGND 24 74 GND DIOO0 25 75 PB3 DIO4 26 76 GND DIO1 27 77 PB2 DIOS 28 78 GND DIO2 29 79 PBI DIO6 30 80 GND DIO3 31 81 PBO DIO7 32 82 GND DGND 33 83 PA7 45V 34 84 GND 5V 35 85 PAG SCANCLK 36 86 GND EXTSTROBE 37 87 PAS PFIO TRIG1 38 88 GND PFM TRIG2 39 89 PA4 PFI2 CONVERT 40 90 GND PFIJ GPCTR1 SOURCE 41 91 PA3 PFI4 GPCTR1_GATE 42 92 GND GPCTR1_OUT 43 93 PA2 PFI5 UPDATE 44 94 GND PFIG WFTRIG 45 95 PA1 PFIZ STARTSCAN 46 96 GND PFIB GPCTRO SOURCE 47 97 PAO PFIJ GPCTRO GATE 48 98 GND GPCTRO OUT 49 99 5V FREQ OUT 50 100 GND Figure 4 3 1 0 Connector Pin Assignment for the AT MIO 16DE 10 AT E Series User Manual 4 4 National Instruments Corporation Chapter 4 Signal Connections 1 0 Connector Signal Descriptions Table 4 1 1 0 Signal Summary AT E Series Signal Name Reference Direction Description AIGND Analog Input Ground These pins are the reference point for single ended measurements and the bias current return point for differential measurements All three ground references AIGND AOGND and DGND are connected together on your AT E Series board ACH lt 0 15 gt AIGND Input Analog Input Channels 0 through 15 Each channe
23. This calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possible to calibrate the analog output gain error when using an external reference In this case it is advisable to account for the nominal gain error of the analog output channel either in software or with external hardware See Appendix A Specifications for analog output gain error information National Instruments Corporation 5 3 AT E Series User Manual Specifications Appendix This appendix lists the specifications of each board in the AT E Series These specifications are typical at 25 C unless otherwise noted AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Analog Input Input Characteristics Number of channels AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 Type of ADC Resolution Max sampling rate AT MIO 16E 1 eeen AT MIO 16E 2 AT MIO 64E 3 Throughput to system memory EISA machines ISA machines National Instruments Corporation 16 single ended or 8 differential software selectable 64 single ended or 32 differential software selectable Successive approximation 12 bits 1 in 4 096 1 25 MS s guaranteed 500 kS s guaranteed 1 0 1 25 MS s 600 900 kS s AT E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Input signal ranges Board Range Software Selectable
24. Voc 799 3 5 at V 0 4 5 at0 4 1 5 50 KQ pu PFI9 GPCTRO_GATE DIO Vec 799 3 5 at V 0 4 5at 0 4 1 5 50 KQ pu GPCTRO OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu FREQ_OUT DO 3 5at Voc 04 5at0 4 1 5 50 KQ pu IDIO lt 6 7 gt are also pulled down with a 50 kQ resistor AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output The tolerance on the 50 kQ pullup and pulldown resistors is very large Actual value may range between 17 kQ and 100 kQ National Instruments Corporation 4 11 AT E Series User Manual Chapter 4 Signal Connections Table 4 4 shows the I O signal summary for the AT MIO 16XE 10 and AT AI 16XE 10 Table 4 4 1 0 Signal Summary AT MIO 16XE 10 and AT AI 16XE 10 Impedance Protection Sink Rise Input Volts Source mAat Time Signal Name Drive Output On Off mA at V V ns Bias ACH lt 0 15 gt Al 100 GQ in 25 15 1 nA parallel with 100 pF AISENSE AI 100 GQ in 25 15 1 nA parallel with 100 pF AIGND AO DACOOUT AO 0 10 Short circuit 5 at 10 5 at 10 5 to ground V us DACIOUT AO 0 1 Short circuit 5at 10 5at 10 5 to ground V us AOGND AO DGND DO VCC DO 0 1 Q Short circuit 1A to ground DIO lt 0 7 gt DIO Voc 0 5 13 at Voc 0 4 24 at 0 4 1 1 50 KQ pu SCANCLK DO 3 5 a
25. eee 4 36 STARTSCAN Output Signal Timing eee 4 37 CONVERT Input Signal Timing eese 4 38 CONVERT Output Signal Timing eerte 4 39 SISOURCE Signal Timing esee 4 40 WFTRIG Input Signal Timing seen 4 41 WFTRIG Output Signal Timing eseeeeeeee 4 41 UPDATE Input Signal Timing eee 4 43 UPDATE Output Signal Timing eee 4 43 UISOURCE Signal Timing eese 4 44 GPCTRO SOURCE Signal Timing esee 4 45 GPCTRO GATE Signal Timing in Edge Detection Mode 4 46 GPCTRO OUT Signal Timing eee 4 46 GPCTRI SOURCE Signal Timing eee 4 47 GPCTR1_GATE Signal Timing in Edge Detection Mode 4 48 GPCTRI OUT Signal Timing eene 4 48 GPCTR Timing Summary sees 4 49 National Instruments Corporation ix AT E Series User Manual Contents Figure 4 38 Figure 4 39 Figure 4 40 Figure B 1 Figure B 2 Figure B 3 Figure B 4 Figure B 5 Figure B 6 Tables Table 2 1 Table 2 2 Table 2 3 Table 3 1 Table 3 2 Table 3 3 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 AT E Series User Manual Mode 1 Input Timing esee enne 4 53 Mode 1 Output Timing entertain ree retient 4 54 Mode 2 Bidirectional Timi
26. unipolar input polarity is best However if the signal is negative or equal to zero inaccurate readings will occur if you use unipolar input polarity When you enable dither you add approximately 0 5 LSB rms of white Gaussian noise to the signal to be converted by the ADC This addition is useful for applications involving averaging to increase the resolution of your AT E Series board as in calibration or spectral analysis In such applications noise modulation is decreased and differential linearity is improved by the addition of the dither When taking DC measurements such as when checking the board calibration you should enable dither and average about 1 000 points to take a single reading This process removes the effects of quantization and reduces measurement noise resulting in improved resolution For high speed applications not 3 10 National Instruments Corporation Chapter 3 Hardware Overview involving averaging or spectral analysis you may want to disable the dither to reduce noise You enable and disable the dither circuitry through software Figure 3 7 illustrates the effect of dither on signal acquisition Figure 3 7a shows a small 4 LSB sine wave acquired with dither off The quantization of the ADC is clearly visible Figure 3 7b shows what happens when 50 such acquisitions are averaged together quantization is still plainly visible In Figure 3 7c the sine wave is acquired with dither on There is a consi
27. 1 channels 0 through 3 Note EISA computers also have channels 0 3 available as 16 bit DMA channels National Instruments Corporation 2 7 AT E Series User Manual Chapter Hardware Overview This chapter presents an overview of the hardware functions on your AT E Series board Figure 3 1 shows the block diagram for the AT MIO 16E 1 and AT MIO 16E 2 Voltage Calibration REF DACs 12 Bit Sampling ADC Data AD FIFO Transceivers Converter Selection Switches Mux Circuitry 3 EEPROM Configuration Memory Al Control g Trigger Level 2 DACs Analog FTN gt Trigger Tt 8 Trigger Circuitry lt T Mais DMA Y Y i nalog Input i Interrupt nalog 1 1 input EEPROM DMA Control DAQ STC Bus Interface Analog 8255 Output DIO Control Control 1 terface A Control Interface 1 1 PFI Trigger Trigger Timing Control Hequest Counter Bus MEE Timing vo DAQ STC interface lt R 1 Analog Output RTSI Bus Digital VO Timing Control Interface l O Connector Digital 1 0 8 AT I O Channel AO Control Data 16 Figure 3 1 AT MIO 16E 1 and AT MIO 16E 2 Block Diagram National Instruments Corporation 3 1 AT E Series User Manual Chapter 3 Hardware Overview Figure 3 2 sh
28. 4 48 GPCTRI1 SOURCE signal 4 47 GPCTRI1 UP DOWN signal 4 49 to 4 50 programmable function input connections 4 30 to 4 31 waveform generation timing connections 4 40 to 4 44 UISOURCE signal 4 44 UPDATE signal 4 42 to 4 43 WFTRIG signal 4 41 types of signal sources 4 17 floating 4 17 ground referenced 4 17 single ended connections description 4 23 floating signal sources RSE 4 24 grounded signal sources NRSE 4 24 when to use 4 23 SISOURCE signal 4 40 software programming choices National Instruments application software 1 3 NI DAQ driver software 1 4 to 1 5 register level programming 1 5 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 analog input A 1 to A 5 amplifier characteristics A 3 dynamic characteristics A 4 to A 5 input characteristics A 1to A 3 AT E Series User Manual Index stability A 5 transfer characteristics A 3 analog output A 5 to A 7 dynamic characteristics A 7 output characteristics A 5 to A 6 stability A 7 to A 8 transfer characteristics A 6 voltage output A 7 bus interface A 10 digital I O A 8 environment A 11 physical A 11 power requirements A 10 timing I O A 8 to A 9 triggers analog trigger A 9 to A 10 digital trigger A 10 RTSI A 10 AT MIO 16E 10 and AT MIO 16DE 10 analog input A 12 to A 15 amplifier characteristics A 14 dynamic characteristics A 14 input characteristics A 12 to A 13 stability A 15 transfer characteristics
29. EXTSTROBE Signal Timing TRIG1 Signal Any PFI pin can externally input the TRIGI signal which is available as an output on the PFIO TRIGI pin Refer to Figures 4 13 and 4 14 for the relationship of TRIGI to the data acquisition sequence As an input the TRIGI signal is configured in the edge detection mode You can select any PFI pin as the source for TRIGI and configure the polarity selection for either rising or falling edge The selected edge of the TRIGI signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions The AT MIO 16E 1 AT MIO 16E 2 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 64E 3 support analog triggering on the PFIO TRIGI pin See Chapter 3 Hardware Overview for more information on analog triggering As an output the TRIGI signal reflects the action that initiates a data acquisition sequence This is true even if the acquisition is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup National Instruments Corporation 4 33 AT E Series User Manual Chapter 4 Signal Connections AT E Series User Manual Figures 4 17 and 4 18 show the input and output timing requirements for the TRIGI signal Rising edge polarity Falling edge polarity tw 2 10 ns minimum Figure 4 17 TRIG1 Input Signal Timing l lt gt 1 if i ty 5
30. NRSE A channel configured in NRSE mode uses one analog channel input line which connects to the positive input of the PGIA The negative input of the PGIA connects to the analog input sense AISENSE input For more information about the three types of input configuration refer to the Analog Input Signal Connections section in Chapter 4 Signal Connections which contains diagrams showing the signal paths for the three configurations Input Polarity and Input Range AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 These boards have two input polarities unipolar and bipolar Unipolar input means that the input voltage range is between 0 and Vef where Vef s a positive reference voltage Bipolar input means that the input voltage range is between V ef 2 and V 2 The AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 have a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 10 V 5 V You can program polarity and National Instruments Corporation 3 7 AT E Series User Manual Chapter 3 Hardware Overview range settings on a per channel basis so that you can configure each input channel uniquely The software programmable gain on these boards increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate The AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 have
31. The AIGATE signal can mask off scans in a data acquisition sequence You can configure the PFI pin you select as the source for the AIGATE signal in either the level detection or edge detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur In the edge detection mode the first active edge disables the STARTSCAN signal and the second active edge enables STARTSCAN National Instruments Corporation 4 39 AT E Series User Manual Chapter 4 Signal Connections Waveform Generat AT E Series User Manual The AIGATE signal can neither stop a scan in progress nor continue a previously gated off scan in other words once a scan has started AIGATE does not gate off conversions until the beginning of the next scan and conversely if conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan SISOURCE Signal Any PFI pin can externally input the SISOURCE signal which is not available as an output on the I O connector The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal You must configure the PFI pin you select as the source for the SISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Th
32. This is the other 68 pin connector available when you use the SH1006868 cable assembly with the AT MIO 16DE 10 GND PC6 PC5 GND PC3 PC2 GND PCO PB7 GND PB5 PB4 GND GND PB1 PBO GND PA6 PA5 GND PA3 PA2 GND PAO 45V N C N C N C N C N C N C N C N C N C wo R 68 99 49 67 wo N 66 wo 65 Cc eo 64 n2 Oo 63 nv co 62 N 61 Dv o 60 n2 oa 59 m BR 58 N 99 57 N N 56 Dv 55 DS e 54 E o 53 oo 52 zs N 51 o 50 Aa oa 49 a A 48 wo 47 Dv 46 45 EN eo 44 o 43 42 41 40 39 38 37 36 P oO A OH MD N o 35 PC7 GND GND PC4 GND GND PC1 GND GND PB6 GND GND PB3 PB2 GND GND PA7 GND GND PA4 GND GND PA1 GND GND N C N C N C N C N C N C N C N C N C National Instruments Corporation Figure B 2 68 Pin DIO Connector Pin Assignments B 3 AT E Series User Manual Appendix B Optional Cable Connector Descriptions AT E Series User Manual Figure B 3 shows the pin assignments for the 68 pin extended analog input connector This is the other 68 pin connector available when you use the SH1006868 cable assembly with the AT MIO 64E 3 ACH 24 ACH 17 ACH
33. configured to acquire n scans after the analog input signal crosses a specific threshold As another example the analog output section can be configured to update its outputs whenever the analog input signal crosses a specific threshold AT E Series User Manual The AT E Series boards contain eight lines of digital I O for general purpose use You can individually configure each line through software for either input or output The AT MIO 16DE 10 has 24 additional DIO lines configured as three 8 bit ports PA lt 0 7 gt PB lt 0 7 gt and PC lt 0 7 gt You can configure each port for both input and output in various combinations with some handshaking capabilities At system startup and reset the digital I O ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines 3 18 National Instruments Corporation Chapter 3 Hardware Overview Timing Signal Routing The DAQ STC provides a very flexible interface for connecting timing signals to other boards or external circuitry Your AT E Series board uses the RTSI bus for interconnecting timing signals between boards and the Programmable Function Input PFI pins on the I O connector for connecting to external circuitry These con
34. differential inputs Tie the shield for each signal pair to the ground reference at the source You should route the analog lines separately from the digital lines When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals 1 6 National Instruments Corporation Chapter 1 Introduction The following list gives recommended part numbers for connectors that mate to the I O connector on your AT E Series board Mating connectors and a backshell kit for making custom 68 pin cables are available from National Instruments part number 776832 01 AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 and the AT MIO 16XE 50 Honda 68 position solder cup female connector part number PCS E68FS Honda backshell part number PCS E68LKPA AT MIO 64E 3 and AT MIO 16DE 10 AMP 100 position IDC male connector part number 1 750913 9 AMP backshell 50 max O D cable part number 749081 1 AMP backshell 55 max O D cable part number 749854 1 Unpacking Your AT E Series board is shipped in an antistatic package to prevent electrostatic damage to the board Electrostatic discharge can damage several components on the board To avoid such damage in handling the board take the following precautions e Ground yourself via a grounding strap or by holding a grounded object e
35. external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config CTR Mode Config and CTR Pulse Config advanced level VIs to indicate which function the connected signal will serve Use the Route Signal VI to enable the PFI lines to output internal signals C 7 AT E Series User Manual Appendix C Common Questions N Caution AT E Series User Manual If you enable a PFI line for output do not connect any external signal source to it if you do you can damage the board the computer and the connected equipment 26 What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the board circuitry is not actively driving the output either high or low However these lines may have pull up or pull down resistors connected to them as shown in Tables 4 1 to 4 4 I O Signal Summary These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 will be in the high impedance state after power on and Table 4 1 shows that there is a 50 kQ pull up resistor This pull up resistor will set the DIO 0 pin to a logic high when the output is in a high impedance state C 8 National Instruments Corporation Appendix Customer Communication For your convenience this appendix contains forms to
36. lists the specifications of each board in the AT E Series e Appendix B Optional Cable Connector Descriptions describes the connectors on the optional cables for the AT E Series boards e Appendix C Common Questions contains a list of commonly asked questions and their answers relating to usage and special features of your AT E Series board e Appendix D Customer Communication contains forms you can use to request help from National Instruments or to comment on our produets The Glossary contains an alphabetical list and description of terms used in this manual including acronyms abbreviations metric prefixes mnemonics and symbols e The Index alphabetically lists topics covered in this manual including the page where you can find the topic Conventions Used in This Manual cP Ax bold bold italic italic AT E Series User Manual The following conventions are used in this manual This icon to the left of bold italicized text denotes a note which alerts you to important information This icon to the left of bold italicized text denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash Bold text denotes parameters Bold italic text denotes a note caution or warning Italic text denotes emphasis on a specific board in the AT E Series or on other important information a cross reference or an introduction to a key concept This font also denotes text
37. software programming choices NI DAQ driver software 1 4 to 1 5 register level programming 1 5 unpacking 1 7 base I O address selection 2 3 bipolar input AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 3 7 to 3 8 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 3 8 to 3 10 mixing bipolar and unipolar channels note 3 9 bipolar output 3 14 block diagrams AT AI 16XE 10 3 5 AT MIO 16E 1 and AT MIO 16E 2 3 1 AT MIO 16E 10 and AT MIO 16DE 10 3 3 AT MIO 16XE 10 3 4 AT MIO 16XE 50 3 6 AT MIO 64E 3 3 2 board configuration See configuration bus interface specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 20 National Instruments Corporation Index AT MIO 16XE 10 and AT AI 16XE 10 A 28 AT MIO 16XE 50 A 36 C cables See also I O connectors field wiring considerations 4 56 optional equipment 1 6 calibration 5 1 to 5 3 adjusting for gain error 5 3 external calibration 5 2 to 5 3 loading calibration constants 5 1 to 5 2 self calibration 5 2 charge injection 3 12 clocks board and RTSI 3 20 commonly asked questions See questions about AT E series boards common mode signal rejection 4 25 configuration See also input configurations base I O address selection 2 3 bus interface 2 3 to 2 7 common questions about C 2 to C 3 DMA channel selection 2 4 interrupt channel selection PC AT 16 bit DMA channel assignment
38. 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 PFI2 CONVERT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 PFI3 GPCTR1_SOURCE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 National Instruments Corporation AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 PFI4 GPCTR1_GATE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 PFIS UPDATE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 7 PFI6 WFTRIG signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 7 PFI7 STARTSCAN signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT M
39. 100 kHz 10 MHz 100 kHz National Instruments Corporation Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Base clock accuracy 0 01 Max source frequency Min source pulse duration Min gate pulse duration Data transfers esee DMA modes eeeee HH Triggers Analog Trigger SOULECE rroen e Eoin Ea I cnin testet a Resolution eise Hyst resiS 2n ttem ani Bandwidth 3 dB External input PFIO TRIG1 Impedance eeeeeeeeeeeeceeeeeeeeees Coupling eene Protection ssseeeeseeseesresrererrsesee National Instruments Corporation A 9 20 MHz 10 ns in edge detect mode 10 ns in edge detect mode DMA interrupts programmed I O Single transfer ACH lt 0 63 gt PFIO TRIG1 full scale internal 10 V external Positive or negative software selectable 8 bits 1 in 256 Programmable 1 5 MHz internal 7 MHz external 10 ko DC 0 5 to Vec 0 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off AT E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Digital Trigger Compatibility Response Pulse width RTSI Trigger lines Calibration Recommended warm up time Calibration interval External calibration reference Onboard calibration refer
40. 17 differential connections 4 21 to 4 22 single ended connections RSE configuration 4 24 AT E Series User Manual Index FREQ OUT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 10 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 8 waveform generation timing connections 4 50 frequently asked questions See questions about AT E series boards fuse 4 6 G general purpose timing signal connections 4 44 to 4 55 FREQ OUT signal 4 50 GPCTRO GATE signal 4 45 to 4 46 GPCTRO OUT signal 4 46 GPCTRO SOURCE signal 4 44 to 4 45 GPCTRO UP DOWN signal 4 46 GPCTR1_GATE signal 4 47 to 4 48 GPCTR1_OUT signal 4 48 GPCTR1_SOURCE signal 4 47 GPCTR1_UP_DOWN signal 4 49 to 4 50 GPCTRO_GATE signal 4 45 to 4 46 GPCTRO_OUT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 10 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 8 waveform generation timing connections 4 46 AT E Series User Manual l 6 GPCTRO SOURCE signal 4 44 to 4 45 GPCTRO UP DOWN signal 4 46 GPCTRI GATE signal 4 47 to 4 48 GPCTRI OUT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 descri
41. 18 ACH 27 ACH 20 ACH 21 ACH 30 ACH 23 ACH 32 ACH 41 ACH 34 ACH 35 AIGND ACH 44 ACH 37 ACH 38 ACH 47 ACH 48 ACH 49 ACH 58 ACH 51 ACH 52 ACH 61 ACH 54 ACH 55 N C N C N C N C N C N C N C N C N C wo BR 68 C2 oo 67 C2 N 66 C5 ak 65 ao eo 64 n2 Oo 63 hv co 62 M 61 Dv o 60 n2 oa 59 Dv BR 58 N 99 57 N N 56 Dv A 55 Dv eo 54 c 53 co 52 ae N 51 o 50 m oa 49 a A 48 E wo 47 N 46 ak 45 eo 44 c 43 42 41 40 39 38 37 36 PMP oO A OH MD N o 35 ACH 16 ACH 25 ACH 26 ACH 19 ACH 28 ACH 29 ACH 22 ACH 31 ACH 40 ACH 33 ACH 42 ACH 43 AISENSE2 ACH 36 ACH 45 ACH 46 ACH 39 ACH 56 ACH 57 ACH 50 ACH 59 ACH 60 ACH 53 ACH 62 ACH 63 N C N C N C N C N C N C N C N C N C Figure B 3 68 Pin Extended Analog Input Connector Pin Assignments B 4 National Instruments Corporation Appendix B Optional Cable Connector Descriptions Figure B 4 shows the pin assignments for the 50 pin MIO connector This connector is available when you use the SH6850 or R6850 cable assemblies with the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16
42. 27 to 4 28 digital timing connections 4 29 DIFF differential input mode definition table 3 7 description 4 19 ground referenced signal sources 4 20 nonreferenced or floating signal sources 4 21 to 4 22 single ended connections 4 23 floating signal sources RSE 4 24 grounded signal sources NRSE 4 24 when to use 4 19 digital I O common questions about C 5 to C 8 operation 3 18 signal connections 4 27 to 4 28 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 8 AT MIO 16E 10 and AT MIO 16DE 10 A 17 to A 18 AT MIO 16XE 10 and AT AI 16XE 10 A 26 AT MIO 16XE 50 A 34 digital ports A B and C timing specifications 4 51 to 4 55 mode input timing 4 53 mode output timing 4 54 mode 2 bidirectional timing 4 55 Port C signal assignments table 4 51 timing signals table 4 52 digital trigger specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 19 AT MIO 16XE 10 and AT AI 16XE 10 A 28 National Instruments Corporation AT MIO 16XE 50 A 35 DIO lt 0 7 gt signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 digital I O connections 4 27 to 4 28 dither enabling 3 10 to 3 12 DMA channels configuring 2 4 PC AT 16 bit DMA channel assignment map table 2 7 documentation about the
43. 56 AIGND DAC1OUT 21 55 AOGND EXTREF 20 54 AOGND DIO4 19153 DGND DGND 18 52 DIO0 DIO1 17 51 pios DIO6 16 50 DGND DGND 15 49 DIO2 5V 14 48 DIO7 DGND 13 47 DIO3 DGND 12 46 SCANCLK PFIo TRIG1 11 45 EXTSTROBE PFM TRIG2 10 44 DGND DGND 9 43 PFI2 CONVERT 5V 8 42 PFIS GPCTR1 SOURCE DGND 7 41 PFM GPCTR1 GATE PFIS UPDATE 6 40 GPCTR1 OUT PFIG WFTRIG 5 39 DGND DGND 4 38 PFI7 STARTSCAN PFIS GPCTRO GATE 3 37 PFIB GPCTRO SOURCE GPCTRO OUT 2 36 DGND FREQ OUT 7 35 DGND Not available on AT AI 16XE 10 Not available on AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 Figure 4 1 1 0 Connector Pin Assignment for the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 AT E Series User Manual 4 2 National Instruments Corporation Chapter 4 Signal Connections AIGND 1 51 ACH16 AIGND 2 52 ACH24 ACHO 3 53 ACH17 ACH8 4 54 ACH25 ACH1 5 55 ACH18 ACH9 6 56 ACH26 ACH2 7 57 ACH19 ACH10 8 58 ACH27 ACH3 9 59 ACH20 ACH11 10 60 ACH28 ACH4 11 61 ACH21 ACH12 12 62 ACH29 ACHS 13 63 ACH22 ACH13 14 64 ACH30 ACH6 15 65 ACH23 ACH14 16 66 ACH31 ACH7 17 67 ACH32 ACH1
44. 7 shows how to connect a floating signal source to an AT E Series board channel configured in DIFF input mode Floating Bias Current Return Paths l O Connector ACH lt 0 7 gt L4 O OO Bias resistors so see text A s ul Signal J S Source s oot s o Instrumentation Amplifier ACH 8 15 70 oo o So o So le so Measured AIGND Input Multiplexers o __ NY AISENSE Voltage Selected Channel in DIFF Configuration Figure 4 7 Differential Input Connections for Nonreferenced Signals Figure 4 7 shows two bias resistors connected in parallel with the signal leads of a floating signal source If you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA and the PGIA will saturate causing erroneous readings You must reference the source to AIGND The easiest way is simply to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well as to the negative input of the PGIA without National Instruments Corporation 4 21 AT E Series User Manual Chapter 4 Signal Connections AT E Series User Manual any resistors at all This connection works well for DC coupled sources with low source impedan
45. 8 input output Compatibility eee TTL CMOS Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current 320 uA Input high current 10 pA Output low voltage 0 4 V lor 24 mA Output high voltage 4 35 V log 13 mA Power on state Data transfers es Number of channels Resolution Counter timers Frequency scaler 4 34 jesse Input High Z grietas is Programmed I O Miseni qe vs 2 up down counter timers frequency scaler National Instruments Corporation Triggers Calibration Appendix A Specifications for AT MIO 16XE 50 Compatibility 00 0 0 eees TTL CMOS Base clocks available Counter timers eseeeee 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode Data transfers DMA interrupts programmed I O DMA modes ierni A reri Single transfer Digital Trigger Compatibility sseseeeee TTL Respons ensinei ae eet Rising or falling edge Pulse width e enee 10 ns min RTSI Trigger Lines eene 7 Recommended warm up time
46. All 3 us typ 2 us typ 1 8 us typ 5 us max 3 us max 2 us max A 4 National Instruments Corporation Analog Output Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 System noise LSBrms not including quantization Noise Noise Gain dither off dither on AT MIO 16E 1 0 5 to 10 0 25 0 5 20 0 4 0 6 50 0 5 0 7 100 0 8 0 9 AT MIO 16E 2 0 5 to 20 0 15 0 5 AT MIO 64E 3 50 0 3 0 6 100 0 5 0 7 Crosstalk isset ode Ace E 80 dB DC to 100 kHz Stability Offset temperature coefficient Pr g imn ute ettet 5 uV C Postg ain xe Us 240 uV C Gain temperature coefficient 20 ppm C Output Characteristics Number of channels 2 voltage R sol tion oie Berge 12 bits 1 in 4 096 Max update rate FIFO mode waveform generation Internally timed 1 MS s per channel Externally timed 950 kS s per channel Non FIFO mode waveform generation National Instruments Corporation A 5 AT E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 AT E Series User Manual I channel 600 950 kS s system dependent 2 channel 300 625 kS s system dependent Py pe of DAC eere Double buffered multiplying FIFO buffer size 00 eee eee 2 048 samples Data transfers
47. E Series Board AT E Series User Manual Figure 4 11 Digital 1 0 Connections Figure 4 11 shows DIO lt 0 3 gt configured for digital input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the figure Digital output applications include sending TTL signals and driving external devices such as the LED shown in the figure 4 28 National Instruments Corporation Chapter 4 Signal Connections Power Connections N Caution Two pins on the I 0 connector supply 5 V from the PC power supply via a self resetting fuse The fuse will reset automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and can be used to power external digital circuitry The combined total power rating for both pins should be between 4 65 VDC to 5 25 VDC at 1 A Under no circumstances should you connect these 5 V power pins directly to analog or digital ground or to any other voltage source on the AT E Series board or any other device Doing so can damage the AT E Series board and the PC National Instruments is NOT liable for damages resulting from such a connection Timing Connections N Caution Exceeding the maximum input voltage ratings which are listed in Tables 4 2 through 4 5 can damage the AT E Series board and the PC National Instruments
48. Frequency scaler 4 bits Compatibility eene TTL CMOS A 26 National Instruments Corporation Appendix A Specificatio Base clocks available Counter timers Frequency scaler ns for AT MIO 16XE 10 and AT AI 16XE 10 20 MHz 100 kHz 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency eeeeeeeeeeeeee Min source pulse duration Min gate pulse duration Data transfers iesnas DMA modes Triggers Analog Trigger SOUICE TAE EE EE ERT Levele eano bie eaaet te etu vec Resolution eeeeeen Hysteresis Bandwidth 3 dB External input PFIO TRIG1 National Instruments Corporation Impedance eeee Coupling Protection uet A 27 10 ns edge detect mode 10 ns edge detect mode DMA interrupts programmed I O Single transfer ACH lt 0 15 gt PFIO TRIGI Full scale internal 10 V external Positive or negative software selectable 12 bits 1 in 4 096 Programmable 255 kHz internal 4 MHz external 10 kQ DC 0 5 to Vcc 40 5 V when configured as a digital signal 35 V when configured as an AT E Series User Manual Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 ACCULACY drole iipce ORE Digital Trigger Compatibility esses Response ec eterne ense Pulse width eee RTSI Tr
49. Instruments Corporation Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 External reference input Range t De Ei 11 V Overvoltage protection 35 V powered on 25 V powered off Input impedance 10 ko Bandwidth 3 dB 300 kHz Dynamic Characteristics Settling time for full scale step 10 us to 0 5 LSB accuracy Slew Tate 1 24 10 V us INOISG tee REDE S 200 uVrms DC to 1 MHz Glitch energy at midscale transition Magnitude oo ie 100 mV DULALION ite pee eye tee 3 us Stability Offset temperature coefficient 50 uV C Gain temperature coefficient Internal reference 25 ppm C External reference 25 ppm C Digital 1 0 Number of channels AT MIO 16E 10 8 input output AT MIO 16DE 10 32 input output Compatibility seeeeeee TTL CMOS Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V National Instruments Corporation A 17 AT E Series User Manual Appendix A Timing 1 0 AT E Series User Manual Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Level Min Max Input low current Vin 0 V 320 uA Input high current Vi 5 V 10 uA Output low voltage 0 4 V IoL 24 mA Ou
50. Load E AO GND VOUT 1 Load DAC1OUT LIBI Channel 1 Analog Output Channels AT E Series Board Figure 4 10 Analog Output Connections The external reference signal can be either a DC or an AC signal The board multiplies this reference signal by the DAC code divided by the full scale DAC code to generate the output voltage Digital 1 0 Signal Connections The digital I O signals are DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs The AT MIO 16DE 10 has 24 additional DIO lines configured as three 8 bit ports PA lt 0 7 gt PB lt 0 7 gt and PC lt 0 7 gt You can configure each port for both input and output in various combinations with some handshaking capabilities National Instruments Corporation 4 27 AT E Series User Manual Chapter 4 Signal Connections AN Caution Exceeding the maximum input voltage ratings which are listed in Tables 4 2 through 4 5 can damage the AT E Series board and the PC National Instruments is NOT liable for any damages resulting from such signal connections Figure 4 11 shows signal connections for three typical digital I O applications 45V LED Po d DIO lt 4 7 gt JL LIL gt TTL Signal DIO lt 0 3 gt 5 V A 1 Switch S I O Connector AT
51. Q oo Input Multiplexers eAISENSE Measured Voltage m l O Connector at V Selected Channel in RSE Configuration AIGND AT E Series User Manual Figure 4 8 Single Ended Input Connections for Nonreferenced or Floating Signals Single Ended Connections for Grounded Signal Sources NRSE Configuration To measure a grounded signal source with a single ended configuration you must configure your AT E Series board in the NRSE input configuration The signal is then connected to the positive input of the AT E Series PGIA and the signal local ground reference is connected to the negative input of the PGIA The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the AT E Series ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the PGIA and this difference is rejected by the amplifier If the input circuitry of an AT E Series board were referenced to ground in this situation as in the RSE input configuration this difference in ground potentials would appear as an error in the measured voltage 4 24 National Instruments Corporation Chapter 4 Signal Connections Figure 4 9 shows how to connect a grounded signal source to an AT E Series board channel configured for NRSE mode ACH lt 0 15 gt o OO 64 64 o So Instru
52. Series User Manual vi National Instruments Corporation Contents Power Connections cosses once dap ence pee eee Pre dite ori de baee oes 4 29 Timing Connections oue pneter e UT E PE RET pei 4 29 Programmable Function Input Connections sees 4 30 Data Acquisition Timing Connections eseseeeeeeeneee 4 31 SCANCLK Signal ne ee He Eee reus 4 32 EXTSTROBE Signal oeueneneseeoiee nee 4 33 TRIG Signal eps bem gegocend pies 4 33 TRIG Signal nnn PEOREREHITGI Or DE Pe INN 4 34 STARTSCAN Signal nece ete ecce ie caes 4 36 CONVERT Sign l beendet eren 4 38 AIGATE Signal ettet ette tene Raster ERE 4 39 SISOURCGE Sign l 45 pite dece e terree gis 4 40 Waveform Generation Timing Connections sss 4 40 WETRIG Signal rere 4 41 UPDATE Signal eee ve epe 4 42 UISOURCE Signal reiten ith ere thes 4 44 General Purpose Timing Signal Connections see 4 44 GPCTRO SOURCE Signal nee mote 4 44 GPCTRO GATE Signal eies iori tentent 4 45 GPCTRO OUT Signal tete peret prre 4 46 GPCTRO UP DOWN Signal eene 4 46 GPCTRI SOURCE Signal eee 4 47 GPCTR1_GATE Signal eee teretes 4 47 GPCTRI OUT Sign l oir tete iet eris 4 48 GPCTRI UP DOWN Signal eene 4 49 FREQ QUT Signal ote eripere eiae eaaa EE RO ee 4 50 Timing Specifications for Digi
53. Touch the antistatic package to a metal part of your computer chassis before removing the board from the package e Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer e Never touch the exposed pins of connectors National Instruments Corporation 1 7 AT E Series User Manual Chapter Installation and Configuration This chapter explains how to install and configure your AT E Series board Software Installation You may need to install your software before you install your AT E Series board Refer to the appropriate release notes indicated below for specific instructions on the software installation sequence If you are using NI DAQ refer to the NI DAQ Release Notes Find the installation section for your operating system and follow the instructions given there If you are using LabVIEW refer to your LabVIEW release notes After you have installed LabVIEW refer to the NI DAQ release notes and follow the instructions given there for your operating system and LabVIEW If you are using LabWindows CVI refer to your LabWindows CVI release notes After you have installed LabWindows CVI refer to your NI DAQ release notes and follow the instructions given there for your operating system and LabWindows CVI If you are using other National Instrum
54. a calibration that you subsequently performed National Instruments Corporation 5 1 AT E Series User Manual Chapter 5 Calibration This method of calibration is not very accurate because it does not take into account the fact that the board measurement and output voltage errors can vary with time and temperature It is better to self calibrate when the board is installed in the environment in which it will be used Self Calibration Your AT E Series board can measure and correct for almost all of its calibration related errors without any external signal connections Your National Instruments software provides a self calibration method you can use This self calibration process which generally takes less than a minute is the preferred method of assuring accuracy in your application You should initiate self calibration to ensure that the effects of any offset gain and linearity drifts particularly those due to warmup are minimized Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration AT E Series User Manual Your AT E Series board has an onboard cal
55. allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTRO_SOURCE signal unless you select some external source GPCTRO_GATE Signal Any PFI pin can externally input the GPCTRO_GATE signal which is available as an output on the PFI9 GPCTRO_GATE pin As an input the GPCTRO_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTRO_GATE signal reflects the actual gate signal connected to general purpose counter 0 This is true even if the gate is being externally generated by another PFI This output is set to tri state at startup National Instruments Corporation 4 45 AT E Series User Manual Chapter 4 Signal Connections Figure 4 32 shows the timing requirements for the GPCTRO GATE signal Rising edge polarity Falling edge polarity tw 2 10 ns minimum Figure 4 32 GPCTRO GATE Signal Timing in Edge Detection Mode GPCTRO OUT Signal This signal is available only as an output on the GPCTRO OUT pin The GPCTRO_OUT signal reflects the terminal
56. board to the back panel rail of the computer 7 Check the installation 8 Replace the cover 9 Plug in and turn on your computer The AT E Series board is installed You are now ready to install and configure your software Board Configuration AT E Series User Manual Due to the DAQ PnP features the AT E Series boards are completely software configurable Two types of configuration must be performed on the AT E Series boards bus related configuration and data acquisition related configuration Bus related configuration includes setting the base I O address DMA channels and interrupt channels Data acquisition related configuration explained in the next chapter includes such settings as analog input polarity and range analog output reference source and other settings For more information about data acquisition related configuration refer to your NI DAQ user manual 2 2 National Instruments Corporation Chapter 2 Installation and Configuration Bus Interface The AT E Series boards work in either a Plug and Play mode or a switchless mode These modes dictate how the base I O address DMA channels and interrupt channels are determined and assigned to the board Plug and Play The AT E Series boards are fully compatible with the industry standard Plug and Play ISA specification A Plug and Play system arbitrates and assigns resources through software freeing you from manually setting switches and jumpers These
57. case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the AT E Series boards Figure 4 37 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal FREQ OUT Signal This signal is available only as an output on the FREQ OUT pin The FREQ OUT signal is the output of the AT E Series board frequency generator The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is set to tri state at startup 4 50 National Instruments Corporation Chapter 4 Signal Connections Timing Specifications for Digital 1 0 Ports A B and C AT MIO 16DE 10 only In addition to its function as a digital I O port digital port C PC lt 0 7 gt can also be used for handshaking when performing data transfers with ports A and B The signals assigned to port C depend on the mode in which it
58. connectors available when you use the SH1006868 cable assembly with the AT MIO 16DE 10 or AT MIO 64E 3 National Instruments Corporation B 1 AT E Series User Manual Appendix B Optional Cable Connector Descriptions AcHe 34 68 ACHO ACHi 33 67 AIGND AIGND 3266 ACH9 ACH10 31 65 ACH2 ACH3 30 64 AIGND AIGND 29 63 ACH11 ACH4 28 62 AISENSE AIGND 27 61 ACH12 ACH13 26 60 ACHS ACH6 25 59 AIGND AIGND 24 58 ACH14 ACH15 23 57 ACH7 DACOOUT 22 56 AIGND DAC1OUT 21 55 AOGND ExTREF 20 54 AOGND DIO4 19 53 DGND DGND 18 52 DIOO DIO1 17 51 DIO5 DIO6 16 50 DGND DGND 15 49 DIO2 5V 14 48 DIO7 DGND 13 47 DIOS DGND 12 46 SCANCLK PFIO TRIG1 11 45 EXTSTROBE PFHM TRIG2 10 44 DGND DGND 9 43 PFI2 CONVERT 5 V 8 42 PFI3 GPCTR1_SOURCE DGND 7 41 PFl4 GPCTR1_GATE PFI5 UPDATE 6 40 GPCTR1_OUT PFI6 WFTRIG 5 39 DGND DGND 4 38 PFI7 STARTSCAN PFIS GPCTRO GATE 3 37 PFIS GPCTRO SOURCE GPCTRO OUT 2 36 DGND FREQ OUT 1 35 DGND Not available on AT AI 16XE 10 2 Not available on AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 Figure B 1 68 Pin MIO Connector Pin Assignments AT E Series User Manual B 2 National Instruments Corporation Appendix B Optional Cable Connector Descriptions Figure B 2 shows the pin assignments for the 68 pin DIO connector
59. counter 0 output signal general purpose counter 1 output signal general purpose counter 0 clock source signal general purpose counter 1 clock source signal hour hexadecimal hertz input output current output high current output low Industry Standard Architecture last channel bit least significant bit G 4 National Instruments Corporation NRSE OUT PC PFI PGIA ppm rms RSE RTD RTSI Glossary megabytes of memory minimum minutes multifunction I O most significant bit nonreferenced single ended mode output personal computer Programmable Function Input Programmable Gain Instrumentation Amplifier parts per million root mean square referenced single ended mode resistive temperature device Real Time System Integration National Instruments Corporation G 5 AT E Series User Manual Glossary S S S SCANCLK SCXI SE SISOURCE STARTSCAN T TC THD TRIG TTL U UI UISOURCE UPDATE AT E Series User Manual seconds samples scan clock signal Signal Conditioning eXtensions for Instrumentation single ended inputs SI counter clock signal start scan signal terminal count total harmonic distortion trigger signal transistor transistor logic update interval update interval counter clock signal update signal volts volts direct current volts input high G 6 National Instruments Corporation WFTRIG volts input low volts
60. detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints e Your DAQ hardware user manuals These manuals have detailed information about the DAQ hardware that plugs into or is connected to your computer Use these manuals for hardware installation and configuration instructions specification information about your DAQ hardware and application hints e Software documentation Examples of software documentation you may have are the LabVIEW and LabWindows CVI documentation sets and the NI DAQ documentation After you set National Instruments Corporation xiij AT E Series User Manual About This Manual up your hardware system use either the application software LabVIEW or LabWindows CVI or the NI DAQ documentation to help you write your application If you have a large and complicated system it is worthwhile to look through the software documentation before you configure your hardware Accessory installation guides or manuals lIf you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making your connections SCXI Chassis Manual 1f you are using SCXI read this manual for maintenance information on the chassis and installation instructions Related Documentation The
61. following documents contain information you may find helpful Application Note 025 Field Wiring and Noise Considerations for Analog Signals DAQ STC Technical Reference Manual Customer Communication AT E Series User Manual National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix D Customer Communication at the end of this manual xiv National Instruments Corporation Chapter Introduction This chapter describes the AT E Series boards lists what you need to get started describes the optional software and optional equipment and explains how to unpack your AT E Series board About the AT E Series Thank you for buying a National Instruments AT E Series board The AT E Series boards are the first completely Plug and Play compatible multifunction analog digital and timing I O boards for the PC AT and compatible computers This family of boards features 12 bit and 16 bit ADCs with 16 and 64 analog inputs 12 bit and 16 bit DACs with voltage outputs eight and 32 lines of TTL compatible digital I O and two 24 bit counter timers for timing I O Because the AT E Series boards have no DIP switches jumpers or potentiometers they are e
62. from channel 1 then 100 points from channel 2 and so on Analog Output AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MIO 16DE 10 The AT E Series boards supply two channels of analog output voltage at the I O connector You can select the reference and range for the analog output circuitry through software The reference can be either internal or external whereas the range can be either bipolar or unipolar AT MIO 16XE 50 The AT MIO 16XE 50 supplies two channels of analog output voltage at the I O connector The range is fixed at bipolar 10 V AT MIO 16XE 10 The AT MIO 16XE 10 supplies two channels of analog output voltage at the I O connector The range is software selectable between unipolar 0 to 10 V and bipolar 10 V Analog Output Reference Selection AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MIO 16DE 10 only You can connect each D A converter DAC to the AT E Series board internal reference of 10 V or to the external reference signal connected National Instruments Corporation 3 13 AT E Series User Manual Chapter 3 Hardware Overview to the external reference EXTREF pin on the I O connector This signal applied to EXTREF should be between 10 and 10 V You do not need to configure both channels for the same mode Analog Output Polarity Selection AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MIO 16DE 10 only You can configure each a
63. from which you supply the appropriate word or value as in Windows 3 x Xii National Instruments Corporation NI DAQ PC SCXI lt gt About This Manual NI DAQ refers to the NI DAQ software for PC compatibles unless otherwise noted PC refers to the PC AT series computers SCXI stands for Signal Conditioning eXtensions for Instrumentation and is a National Instruments product line designed to perform front end signal conditioning for National Instruments plug in DAQ boards The indicates that the text following it applies only to specific AT E Series boards Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit port or signal name for example ACH lt 0 7 gt stands for ACHO through ACH7 The Glossary lists abbreviations acronyms metric prefixes mnemonics symbols and terms National Instruments Documentation The AT MIO AI E Series User Manual is one piece of the documentation set for your DAQ system You could have any of several types of manuals depending on the hardware and software in your system Use the manuals you have as follows e Getting Started with SCXI If you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software e Your SCXI hardware user manuals If you are using SCXI read these manuals next for
64. ground and is therefore already connected to a common ground point with respect to the AT E Series board assuming that the PC is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Input Configurations You can configure your AT E Series board for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources National Instruments Corporation 4 17 AT E Series User Manual Chapter 4 Signal Connections Figure 4 5 summarizes the recommended input configuration for both types of signal sources Signal Source Type Floating Signal Source Not Connected to Building Ground Examples Ungrounded Thermocouples Signal conditioning with isolated outputs Battery devices Differential DIFF See text for informatio
65. is NOT liable for any damages resulting from such signal connections All external control over the timing of your AT E Series board is routed through the 10 programmable function inputs labeled PFIO through PFI9 These signals are explained in detail in the next section Programmable Function Input Connections These PFIs are bidirectional as outputs they are not programmable and reflect the state of many data acquisition waveform generation and general purpose timing signals There are five other dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control any data acquisition waveform generation and general purpose timing signals The data acquisition signals are explained in the Data Acquisition Timing Connections section later in this chapter The waveform generation signals are explained in the Waveform Generation Timing Connections section later in this chapter The general purpose timing signals are explained in the General Purpose Timing Signal Connections section later in this chapter All digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 12 which shows how to connect an National Instruments Corporation 4 29 AT E Series User Manual Chapter 4 Signal Connections external TRIGI source and an external CONVERT source to two of the AT E Series board PFI pins
66. is programmed In mode 0 port C is considered two 4 bit I O ports In modes 1 and 2 port C is used for status and handshaking signals with two or three additional I O bits Table 4 6 summarizes the signal assignments of port C for each programmable mode Table 4 6 Port C Signal Assignments Group A Group B Programming Mode PC7 PC6 PCS PC4 PC3 PC2 PCI PCO Mode 0 IO IO T O T O IO IO IO T O Mode 1 Input T O IO IBF A STB AC INTR A STB IBFB INTR Mode 1 Output OBF A ACK AS T O T O INTR A ACK OBF INTR Mode 2 OBF ACK IBF STBA INTRA IO IO T O Indicates that the signal is active low This section lists the timing specifications for handshaking with the AT MIO 16DE 10 port C circuitry The handshaking lines STB and IBF synchronize input transfers The handshaking lines OBF and ACK synchronize output transfers National Instruments Corporation 4 51 AT E Series User Manual Chapter 4 Signal Connections Table 4 7 summarizes the port C signals used in the timing diagrams that follow Table 4 7 Port C Signal Descriptions Name Type Description STB input Strobe Input A low signal on this handshaking line loads data into the input latch IBF output Input Buffer Full A high signal on this handshaking line indicates that data has been loaded into the input latch This is an input acknowledge signal ACK input Acknowledge Input A low signal on this handshaking line indic
67. map table 2 7 PC AT I O address map table 2 4 to 2 6 PC AT interrupt assignment map table 2 6 to 2 7 Plug and Play systems 2 3 switchless data acquisition 2 3 connectors See I O connectors CONVERT signal signal routing 3 19 to 3 20 timing connections 4 38 to 4 39 customer communication xiv D 1 AT E Series User Manual Index D DACOOUT signal analog output connections 4 26 to 4 27 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 DACIOUT signal analog output connections 4 26 to 4 27 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 DAQ STC C 1 data acquisition timing connections 4 31 to 4 40 AIGATE signal 4 39 to 4 40 CONVERT signal 4 38 to 4 39 EXTSTROBE signal 4 33 SCANCLK signal 4 32 SISOURCE signal 4 40 STARTSCAN signal 4 36 to 4 37 TRIGI signal 4 33 to 4 34 TRIG signal 4 34 DATA signal table 4 52 DGND signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT E Series User Manual l 4 AT MIO 16XE 50 table 4 14 description table 4 6 digital I O connections 4
68. point with other signals DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions You can software configure the AT E Series board channels for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the AT E Series board provides the reference ground point for the external signal The NRSE input configuration is used for ground referenced signal sources in this case the external signal supplies its own reference ground point and the AT E Series board should not supply one In single ended configurations more electrostatic and magnetic noise couples into the signal connections than in differential configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors National Instruments Corporation 4 23 AT E Series User Manual Chapter 4 Signal Connections Single Ended Connections for Floating Signal Sources RSE Configuration Figure 4 8 shows how to connect a floating signal source to an AT E Series board channel configured for RSE mode ACH lt 0 15 gt Oo Oo Oo So d 9 co Instrumentation Floating I Amplifier Signal Source
69. register level programming and can save weeks of development time National Instruments Corporation 1 5 AT E Series User Manual Chapter 1 Introduction Optional Equipment Custom Cabling National Instruments offers a variety of products to use with your AT E Series board including cables connector blocks and other accessories as follows Cables and cable assemblies shielded and ribbon Connector blocks shielded and unshielded 50 68 and 100 pin screw terminals Real Time System Integration RTSI bus cables Signal condition eXtension for instrumentation SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3072 channels Low channel count signal conditioning modules boards and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For more specific information about these products refer to your National Instruments catalogue or call the office nearest you AT E Series User Manual National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change board interconnections If you want to develop your own cable however the following guidelines may be useful For the analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that you use
70. rere an ie Single transfer Digital Trigger Compatibility eene TTL RESPONSE iet pe Peers Rising or falling edge Pulse width sseeeeeeess 10 ns min RTSI Trigger lines roeie e erp ia 7 Recommended warm up time 15 min Calibration interval 1 year External calibration reference gt 6 and 10V National Instruments Corporation A 19 AT E Series User Manual Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Onboard calibration reference Temperature coefficient Long term stability Bus Interface Power Requirement 45 VDC 590 Power available at I O connector Physical Dimensions not including connectors I O connector AT MIO 16E 10 AT MIO 16DE 10 Environment Operating temperature Storage temperature Relative humidity AT E Series User Manual A 20 5 000 V 42 5 mV actual value stored in EEPROM 5 ppm C max 15 ppm 1 000h Slave 0 7 A 4 65 VDC to 5 25 VDC atl A 17 45 by 10 56 cm 6 87 by 4 16 in 68 pin male SCSI II type 100 pin female 0 050 D type 0 to 55 C 55 to 150 C 5 to 90 noncondensing National Instruments Corporation Appendix A Specifications for AT MIO 16XE 10 and AT Al 16XE 10 AT MIO 16XE 10 and AT AI 16XE 10 Analog Input Input Characteristics Number of channels
71. resources include the board base I O address DMA channels and interrupt channels Each AT E Series board is configured at the factory to request these resources from the Plug and Play Configuration Manager The Configuration Manager receives all of the resource requests at start up compares the available resources to those requested and assigns the available resources as efficiently as possible to the Plug and Play boards Application software can query the Configuration Manager to determine the resources assigned to each board without your involvement The Plug and Play software is installed as a device driver or as an integral component of the computer BIOS Switchless Data Acquisition You can use an AT E Series board in a non Plug and Play system as a switchless DAQ board A non Plug and Play system is a system in which the Configuration Manager has not been installed and which does not contain any non National Instruments Plug and Play products You use a configuration utility to enter the base address DMA and interrupt selections and the application software assigns them to the board iP Note Avoid resource conflicts with non National Instruments boards For example do not configure two boards for the same base address Base 1 0 Address Selection The AT E Series boards can be configured to use base addresses in the range of 20 to FFEO hex Each AT E Series board occupies 32 bytes of address space and must be located on a 32 by
72. signal e The signal leads travel through noisy environments Differential signal connections reduce picked up noise and increase common mode noise rejection Differential signal connections also allow input signals to float within the common mode limits of the PGIA National Instruments Corporation 4 19 AT E Series User Manual Chapter 4 Signal Connections Differential Connections for Ground Referenced Signal Sources Figure 4 6 shows how to connect a ground referenced signal source to an AT E Series board channel configured in DIFF input mode ACH lt 0 7 gt 0 0 3 4 Ground So Referenced o So Signal Instrumentation Source Amplifier Oo Co ACH lt 8 15 gt ob Measured Common Voltage Mode M do c Noise and 64 6 o Ground Potential Input Multiplexers AISENSE ge AIGND 1 O Connector Selected Channel in DIFF Configuration Figure 4 6 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the AT E Series board ground shown as V4 in Figure 4 6 AT E Series User Manual 4 20 National Instruments Corporation Chapter 4 Signal Connections Differential Connections for Nonreferenced or Floating Signal Sources Figure 4
73. start of the scan PFIS GPCTRO SOURCE DGND Input PFI8 Counter 0 Source As an input this is one of the PFIs Output As an output this is the GPCTRO_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTRO_GATE DGND Input PFI9 Counter 0 Gate As an input this is one of the PFIs Output As an output this is the GPCTRO_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 0 GPCTRO_OUT DGND Output Counter 0 Output This output is from the general purpose counter 0 output FREQ OUT DGND Output Frequency Output This output is from the frequency generator output Table 4 2 shows the I O signal summary for the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Table 4 2 1 0 Signal Summary AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias ACH lt 0 63 gt Al 100 GQ 25 15 200 pA in parallel with 100 pF AISENSE AISENSE2 AI 100 GO 25 15 200 pA in parallel with 100 pF AIGND AO AT E Series User Manual 4 8 National Instruments Corporation Chapter 4 Signal Connections Table 4 2 1 0 Signal Summary AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Continued
74. the PFIs can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously This flexible routing scheme reduces the need to change physical connections to the I O connector for different applications You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector software can turn on the output driver for the PFIS UPDATE pin Board and RTSI Clocks Many functions performed by the AT E Series boards require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector An AT E Series board can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the board to use the internal timebase you can also program the board to drive its internal timebase over the RTSI bus to another board that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the board as the primary frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal You select this timebase through software AT E Series User Manual 3 20 National Instruments Corporation RTSI Triggers Chapter 3 Hardware Overview The seve
75. the DAQ STC Will the counter timer applications that I wrote previously work with the DAQ STC If you are using NI DAQ with LabVIEW some of your applications drawn using the CTR VIs will still run However there are many differences in the counters between the AT E Series and other boards the counter numbers are different timebase selections are different the DAQ STC counters are 24 bit counters unlike the 16 bit counters on boards without the DAQ STC If you are using NI DAQ language interface LabWindows or LabWindows CVI the answer is no the counter time applications that you wrote previously will not work with the DAQ STC You must use the GPCTR functions ICTR and CTR functions will not work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must rewrite the application with the GPCTR function calls C 6 National Instruments Corporation 23 24 25 National Instruments Corporation Appendix C Common Questions I m using one of the general purpose counter timers on my AT E Series board but I do not see the counter timer output on the I O connector What am I doing wrong If you are using NI DAQ language interface or LabWindows CVI you must configure the output line to output the signal to the I O connector Use the Select Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are tri state
76. the frequency spectrum Each analog output of the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitions This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum Notice that this reglitch circuit does not eliminate the 3 14 National Instruments Corporation Chapter 3 Hardware Overview glitches it only makes them more uniform in size Reglitching is normally disabled at startup and can be independently enabled for each channel through software Analog Trigger i Note AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 and AT AI 16XE 10 only In addition to supporting internal software triggering and external digital triggering to initiate a data acquisition sequence the AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 and AT AI 16XE 10 also support analog triggering You can configure the analog trigger circuitry to accept either a direct analog input from the PFIO TRIG1 pin on the I O connector or a postgain signal from the output of the PGIA as shown in Figure 3 8 The trigger level range for the direct analog channel is 10 V in 78 mV steps for the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 and 10 V in 4 9 mV steps for the AT MIO 16XE 10 and AT AI 16XE 10 The range for the post PGIA trigger selection is simply the full scale range of the sele
77. timing requirements for the WFTRIG signal Rising edge polarity Falling edge polarity tw 10 ns minimum Figure 4 26 WFTRIG Input Signal Timing I i tw 250 100 ns i I Figure 4 27 WFTRIG Output Signal Timing National Instruments Corporation 4 41 AT E Series User Manual Chapter 4 Signal Connections AT E Series User Manual UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFIS UPDATE pin As an input the UPDATE signal is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs This is true even if the updates are being externally generated by another PFI The output is an active low pulse with a pulse width of 300 to 350 ns This output is set to tri state at startup When using an external UPDATE signal you must apply at least one more external update pulse than the number of points that you want to generate This is necessary for proper hardware operation otherwise the board will not indicate that the waveform generation is complete 4 42 National Instrum
78. 0 100 ns l l I Figure 4 18 TRIG1 Output Signal Timing The board also uses the TRIGI signal to initiate pretriggered data acquisition operations In most pretriggered applications the TRIGI signal is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIG and TRIG2 in a pretriggered data acquisition operation TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFI1 TRIG2 pin Refer to Figure 4 13 for the relationship of TRIG2 to the data acquisition sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG2 signal initiates the posttriggered phase of a pretriggered 4 34 National Instruments Corporation Chapter 4 Signal Connections acquisition sequence In pretriggered mode the TRIGI signal initiates the data acquisition The scan counter indicates the minimum number of scans before TRIG2 can be recognized After the scan counter decrements to zero it is loaded with the number of posttrigger scans to acquire while the acquisition continues The board ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIG2 is received the board will acquire a fixed number of scans a
79. 0 52 uV 10 0 0to 1 V 15 26 uV 20 02 0 to 500 mV 63 uV 50 02 0 to 200 mV 3 05 uV 100 0 0 to 100 mV 1 53 uV National Instruments Corporation 3 9 AT E Series User Manual Chapter 3 Hardware Overview Dither AT E Series User Manual Table 3 3 Actual Range and Measurement Precision AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 Continued Range Configuration Gain Actual Input Range Precision 10 to 10 V 1 0 10 to 10 V 305 18 uV 2 0 5 to 45 V 152 59 uV 5 02 2 to 42 V 61 04 uV 10 0 to 1V 30 52 uV 20 02 500 to 500 mV 15 26 uV 50 02 200 to 200 mV 6 10 uV 100 0 100 to 100 mV 3 05 uV The value of 1 LSB of the 16 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 16 bit count 2 AT MIO 16XE 10 and AT AI 16XE 10 only Note See Appendix A Specifications for absolute maximum ratings Considerations for Selecting Input Ranges Which input polarity and range you select depends on the expected range of the incoming signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For best results you should match the input range as closely as possible to the expected range of the input signal For example if you are certain the input signal will not be negative below 0 V
80. 0 kS s or two channels at 250 kS s per channel illustrates the relationship Notice however C 1 AT E Series User Manual Appendix C Common Questions that some AT E Series boards have settling times that vary with gain and accuracy See Appendix A for exact specifications 4 What type of 5 V protection do the AT E Series boards have The AT E Series boards have 5 V lines equipped with a self resetting 1 A fuse Installation and Configuration 5 How do I configure an AT E Series board on an EISA computer You must configure the board with the NIDAQ Configuration Utility you cannot use an EISA configuration utility to configure the board 6 How do you set the base address for an AT E Series board For Windows NT or Windows 3 1x use the NI DAQ Configuration Utility to type in the desired base I O address For Windows 95 the base address can be changed in the Device Manager Note that for Windows 95 or 3 1x the operating system detects the board and preassigns a base address 0x180 200 220 240 280 and 300 are typical base addresses 7 What jumpers should I be aware of when configuring my AT E Series board The AT E Series boards do not contain any jumpers they are also switchless 8 Which National Instruments manual should I read first to get started using DAQ software If you are using LabVIEW Chapter 1 of the LabVIEW Data Acquisition VI Reference Manual is the best place to get started If you are program
81. 0346 3 ppm or 1 80 LSB of the 4 V step It may take as long as 100 us for the circuitry to settle this much For a 16 bit board to settle within 0 001546 15 ppm or 1 LSB of the 100 mV full scale range on channel 1 the input circuitry has to settle within 0 00004 0 4 ppm or 1 400 LSB of the 4 V step It may take as long as 200 us for the circuitry to settle this much In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling times can also increase when scanning high impedance signals due to a phenomenon called charge injection where the analog input multiplexer injects a small amount of charge into each signal source 3 12 National Instruments Corporation Chapter 3 Hardware Overview when that source is selected If the impedance of the source is not low enough the effect of the charge a voltage error will not have decayed by the time the ADC samples the signal For this reason you should keep source impedances under 1 KQ to perform high speed scanning Due to the previously described limitations of settling times resulting from these conditions multiple channel scanning is not recommended unless sampling rates are low enough or it is necessary to sample several signals as nearly simultaneously as possible The data is much more accurate and channel to channel independent if you acquire data from each channel independently for example 100 points from channel 0 then 100 points
82. 15 signal connections 4 26 to 4 27 analog output specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 5 to A 8 AT E Series User Manual l 2 dynamic characteristics A 7 output characteristics A 5 to A 6 stability A 7 to A 8 transfer characteristics A 6 voltage output A 7 AT MIO 16E 10 and AT MIO 16DE 10 dynamic characteristics A 17 output characteristics A 15 stability A 17 transfer characteristics A 16 voltage output A 16 to A 17 AT MIO 16XE 10 dynamic characteristics A 25 output characteristics A 24 stability A 26 transfer characteristics A 25 voltage output A 25 AT MIO 16XE 50 dynamic characteristics A 33 to A 34 output characteristics A 32 to A 33 stability A 34 transfer characteristics A 33 voltage output A 33 analog trigger 3 15 to 3 18 block diagram 3 16 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 9 specifications AT MIO 16XE 10 and AT AI 16XE 10 A 27 to A 28 AOGND signal analog output connections 4 26 to 4 27 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 National Instruments Corporation description table 4 5 ATE series boards See also hardware overview common questions about C 1 to C 8 custom cabling 1 6 to 1 7 features 1 1 to 1 2 getting started 1 2 optional equipment 1 6
83. 422 Up to 9 600 baud 8 data bits 1 stop bit no parity France 01 48 65 15 59 Up to 9 600 baud 8 data bits 1 stop bit no parity FTP Support To access our FTP site log on to our Internet host ftp natinst com as anonymous and use your Internet address such as joesmith anywhere com as your password The support files and documents are located in the support directories National Instruments Corporation D 1 AT E Series User Manual Fax on Demand Support Fax on Demand is a 24 hour information retrieval system containing a library of documents on a wide range of technical information You can access Fax on Demand from a touch tone telephone at 512 418 1111 E Mail Support currently U S only You can submit technical support questions to the applications engineering team through e mail at the Internet address listed below Remember to include your name address and phone number so we can contact you with solutions and suggestions support natinst com Telephone and Fax Support National Instruments has branch offices all over the world Use the list below to find the technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 900 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Canada Ontario 905 785 0085 905 785 0086 Canada Q
84. 5 18 68 ACH40 AISENSE 19 69 ACH33 DACOOUT 20 70 ACH41 DAC1OUT 21 71 ACH34 EXTREF 22 72 ACH42 AOGND 23 73 ACH35 DGND 24 74 ACH43 DIOO 25 75 AISENSE2 DIO4 26 76 AIGND DIO1 27 77 ACH36 DIO5 28 78 ACH44 DIO2 29 79 ACH37 DIO6 30 80 ACH45 DIO3 31 81 ACH38 DIO7 32 82 ACH46 DGND 33 83 ACH39 45V 34 84 ACH47 45V 35 85 ACH48 SCANCLK 36 86 ACH56 EXTSTROBE 37 87 ACH49 PFIO TRIG1 38 88 ACH57 PFH TRIG2 39 89 ACH50 PFIZ CONVERT 40 90 ACH58 PFI3 GPCTR1_SOURCE 41 91 ACHS51 PFIA GPCTR1 GATE 42 92 ACH59 GPCTR1_OUT 43 93 ACH52 PFI5 UPDATE 44 94 ACH60 PFI6 WFTRIG 45 95 ACH53 PFI7 STARTSCAN 46 96 ACHe1 PFIB GPCTRO SOURCE 47 97 ACH54 PFI9 GPCTRO_GATE 48 98 ACH62 GPCTRO_OUT 49 99 ACH55 FREQ OUT 50 100 ACH63 Figure 4 2 1 0 Connector Pin Assignment for the AT MIO 64E 3 National Instruments Corporation 4 3 AT E Series User Manual Chapter 4 Signal Connections AIGND 1 51 PC7 AIGND 2 52 GND ACHO 3 53 PC6 ACH8 4 54 GND ACH1 5 55 PC5 ACH9 6 56 GND ACH2 7 57 PC4 ACH10 8 58 GND ACH3 9 59 PC3 ACH11 10 60 GND ACH4 11 61 PC2 ACH12 12 62 GND ACH5 13 63 PC ACH13 14 64 GND ACH6 15 65 PCO ACH14 16 66 GND ACH7 17 67 PB7 ACH15 18 68 GND AISENSE 19 69 PB6 DACOOUT 20 70 GND DACiOUT 21 71 PBS EXTREF 22 72 GND AOGND 23 73
85. 6 timing I O A 34 to A 35 triggers digital trigger A 35 RTSI A 35 stability analog input specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 5 AT MIO 16E 10 and AT MIO 16DE 10 A 15 AT MIO 16XE 10 and AT AI 16XE 10 A 24 AT MIO 16XE 50 A 32 analog output specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 7 to A 8 AT MIO 16E 10 and AT MIO 16DE 10 A 17 AT MIO 16XE 10 A 26 AT MIO 16XE 50 A 34 STARTSCAN signal timing connections 4 36 to 4 37 STB signal table 4 52 switchless data acquisition 2 3 T theory of operation See hardware overview ACH lt 0 63 gt signal National Instruments Corporation I 13 Index description table 4 5 timebases board and RTSI clocks 3 20 timing connections 4 29 to 4 55 common questions about C 5 to C 8 data acquisition timing connections 4 31 to 4 40 AIGATE signal 4 39 to 4 40 CONVERT signal 4 38 to 4 39 EXTSTROBE signal 4 33 SCANCLK signal 4 32 SISOURCE signal 4 40 STARTSCAN signal 4 36 to 4 37 TRIGI signal 4 33 to 4 34 TRIG2 signal 4 34 digital ports A B and C 4 51 to 4 55 mode 1 input timing 4 53 mode 1 output timing 4 54 mode 2 bidirectional timing 4 55 Port C signal assignments table 4 51 timing signals table 4 52 general purpose timing signal connections 4 44 to 4 55 FREQ OUT signal 4 50 GPCTRO_GATE signal 4 45 to 4 46 GPCTRO OUT signal 4 46 GPCTRO SOURCE signal 4 44 to 4 45 GPCTRO UP
86. 6XE 10 EXTREF is not available on the AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 DACOOUT is the voltage output signal for analog output channel 0 DACIOUT is the voltage output signal for analog output channel 1 EXTREF is the external reference input for both analog output channels You must configure each analog output channel individually for external reference selection in order for the signal applied at the external reference input to be used by that channel If you do not specify an external reference the channel will use the internal reference iP Note You cannot use an external analog output reference with the AT MIO I6XE 10 AT AI 16XE 10 or AT MIO I6XE 50 Analog output configuration options are explained in the Analog Output section in Chapter 3 Hardware Overview The following ranges and ratings apply to the EXTREF input e Usable input voltage range 11 V peak with respect to AOGND e Absolute maximum ratings 15 V peak with respect to AOGND AOGND is the ground reference signal for both analog output channels and the external reference signal AT E Series User Manual 4 26 National Instruments Corporation Chapter 4 Signal Connections Figure 4 10 shows how to make analog output connections and the external reference input connection to your AT E Series board EXTREF TOT DACOOUT External 4 ze Channel 0 Reference y Signal ret Optional VOUT 0
87. A 13 analog output A 15 to A 17 dynamic characteristics A 17 output characteristics A 15 stability A 17 transfer characteristics A 16 voltage output A 16 to A 17 bus interface A 20 digital I O A 17 to A 18 environment A 20 physical A 20 power requirements A 20 timing I O A 18 to A 19 AT E Series User Manual I 12 triggers digital trigger A 19 RTSI A 19 AT MIO 16XE 10 and AT AI 16XE 10 analog input A 21 to A 24 amplifier characteristics A 23 dynamic characteristics A 23 to A 24 input characteristics A 21 to A 22 stability A 24 transfer characteristics A 22 analog output AT MIO 16XE 10 only A 24 to A 26 dynamic characteristics A 25 output characteristics A 24 stability A 26 transfer characteristics A 25 voltage output A 25 bus interface A 28 digital I O A 26 environment A 29 physical A 29 power requirements A 28 timing I O A 26 to A 27 triggers analog trigger A 27 to A 28 digital trigger A 28 RTSI A 28 AT MIO 16XE 50 analog input A 30 to A 32 amplifier characteristics A 31 to A 32 dynamic characteristics A 32 input characteristics A 30 to A 31 stability A 32 transfer characteristics A 31 analog output A 32 to A 34 National Instruments Corporation dynamic characteristics A 33 to A 34 output characteristics A 32 to A 33 stability A 34 transfer characteristics A 33 voltage output A 33 bus interface A 36 digital I O A 34 environment A 36 physical A 3
88. ACs Trigger DMA D gt o Trigger Circuitry T T Y 5 DMA 0 Trigger i Analog Input i Interrupt Cc PFI Trigger 99 1 Timing Control R Analog IEEPROM DMA equest input FE gt oO c irl 4 SL Control Control Interface 7 o Counter z Bus DAQ STC Plug amp oio DAQ STC menaco Re nane 23 Q ere tuto e e Tr AUI Interface Play E Analog Output 1 RTSI Bus Analog 1 Bus Q Digital I O 8 j Digital O i Timing Control Interface QUE e 1 Interface C 3 E AO Control lt LL oic FIFO 2 Calibration 4 DACs Data 16 C AT E Series User Manual Figure 3 4 AT MIO 16XE 10 Block Diagram 3 4 National Instruments Corporation Chapter 3 Hardware Overview Figure 3 5 shows a block diagram for the AT AI 16XE 10 Calibration Voltage DACs REF Buffer m Y Mux Mode 16 Bit Selection grammes Sampling ADC Data Switch FIFO witches Amplifier Gerivert r Transceivers Calibration Mux EEPROM D Configurati 9 Mere Al Control c ofr 2 QD Trigger Level Analog a l IRQ oc DACs Trigger DMA 8 Circuitry Trigger Q ae Analog Input PM Y o i Interrupt gt o PFI Trigger Trigger 1 Timing Control Hei Analog iEgpROMI DMA 9 i camer pa src an oth a Counter Bus DAQ STO Plug Timing vo DAQ STC interfac
89. CONVERT DIO V9 3 5 at V 0 4 5at0 4 1 5 50 KQ pu PFI3 GPCTRI SOURCE DIO Voc 195 3 5 at V 0 4 5at0 4 1 5 50 KQ pu PFI4 GPCTR1_GATE DIO Vatta 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu GPCTR1_OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFI5 UPDATE DIO Voc 25 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFI6 WFTRIG DIO Veg 0 5 3 5 at V 0 4 5 at 0 4 1 5 50 KQ pu PFI7 STARTSCAN DIO Vec 05 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFIS GPCTRO SOURCE DIO Voc 195 3 5 at Vi 0 4 5at0 4 1 5 50 KQ pu PFI9 GPCTRO_GATE DIO Vetts 3 5 at Voc 0 4 5at0 4 1 5 50 kQ pu GPCTRO OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu FREQ OUT DO 3 5 at V0 4 5 at 0 4 1 5 50 KQ pu IDIO lt 6 7 gt are also pulled down with a 50 kQ resistor AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output The tolerance on the 50 KQ pullup and pulldown resistors is very large Actual value may range between 17 kQ and 100 KQ AT E Series User Manual 4 14 National Instruments Corporation Chapter 4 Signal Connections Analog Input Signal Connections ZN Caution AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16DE 10 AT MIO 16XE 10 AT AI 16XE 10 AT MIO 16XE 50 The analog input signals are ACH lt 0 15 gt AISENSE and AIGND The ACH lt 0 15 gt signals are tied to the 16 analog input channels of your AT E Series board In single ended mode signal
90. DOWN signal 4 46 GPCTRI GATE signal 4 47 to 4 48 GPCTRI OUT signal 4 48 GPCTRI SOURCE signal 4 47 GPCTRI UP DOWN signal 4 49 to 4 50 programmable function input connections 4 30 to 4 31 waveform generation timing connections 4 40 to 4 44 UNISOURCE signal 4 44 UPDATE signal 4 42 to 4 43 AT E Series User Manual Index WFTRIG signal 4 41 timing I O specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 8 to A 9 AT MIO 16E 10 and AT MIO 16DE 10 A 18 to A 19 AT MIO 16XE 10 and AT AI 16XE 10 A 26 to A 27 AT MIO 16XE 50 A 34 to A 35 timing signal routing 3 19 to 3 21 board and RTSI clocks 3 20 programmable function inputs 3 20 RTSI triggers 3 21 transfer characteristics analog input AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 3 AT MIO 16E 10 and AT MIO 16DE 10 A 13 AT MIO 16XE 10 and AT AI 16XE 10 A 22 AT MIO 16XE 50 A 31 analog output AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 6 AT MIO 16E 10 and AT MIO 16DE 10 A 16 AT MIO 16XE 10 A 25 AT MIO 16XE 50 A 33 TRIGI signal timing connections 4 33 to 4 34 TRIG2 signal timing connections 4 34 triggers analog 3 15 to 3 18 block diagram 3 16 RTSI triggers 3 21 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 analog trigger A 9 digital trigger A 10 RTSI A 10 AT E Series User Manual AT MIO 16E 10 and AT MIO 16DE 10 digital trigger A 19 RTSI A 19 AT MIO 16XE 10 and AT AI 16XE 10 analog trigger A 27 t
91. E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 20 AT MIO 16XE 10 and AT AI 16XE 10 A 28 pretriggered data acquisition 4 31 programmable function inputs PFIs See PFIs programmable function inputs programmable gain instrumentation amplifier See PGIA programmable gain instrumentation amplifier Q questions about AT E series boards C 1 to C 8 analog input and analog output C 4 to C 5 general information C 1 to C 2 installation and configuration C 2 to C 3 timing and digital I O C 5 to C 8 R RD signal table 4 52 reference selection analog output 3 13 referenced single ended input RSE See RSE referenced single ended input register level programming 1 5 reglitch selection 3 14 RSE referenced single ended input description table 3 7 AT E Series User Manual single ended connections for floating signal sources 4 24 RTSI clocks 3 20 RTSI triggers overview 3 21 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 19 AT MIO 16XE 10 and AT AI 16XE 10 A 28 AT MIO 16XE 50 A 35 S SCANCLK signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 timing connections 4 32 settling time 3 12 to 3 13 C 1 to C 2 signal connections analog input 4 15 to 4 16 analog out
92. I3 Counter 1 Source As an input this is one of the PFIs Output As an output this is the GPCTR1_SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_GATE DGND Input PFIA Counter 1 Gate As an input this is one of the PFIs Output As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTRI OUT DGND Output Counter 1 Output This output is from the general purpose counter 1 output PFIS UPDATE DGND Input PFI5 Update As an input this is one of the PFIs Output As an output this is the UPDATE signal A high to low edge on UPDATE indicates that the analog output primary group is being updated PFI6 WFTRIG DGND Input PFI6 Waveform Trigger As an input this is one of the PFIs Output As an output this is the WFTRIG signal In timed analog output sequences a low to high transition indicates the initiation of the waveform generation National Instruments Corporation AT E Series User Manual Chapter 4 Signal Connections Table 4 1 1 0 Signal Summary AT E Series Continued Signal Name Reference Direction Description PFI7 STARTSCAN DGND Input PFI7 Start of Scan As an input this is one of the PFIs Output As an output this is the STARTSCAN signal This pin pulses once at the start of each analog input scan in the interval scan A low to high transition indicates the
93. IO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 National Instruments Corporation Index description table 4 8 PFIS GPCTRO SOURCE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 8 PFI9 GPCTRO_GATE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 8 PFIs programmable function inputs 4 30 to 4 31 common questions about C 7 C 8 overview 4 29 signal routing 3 19 to 3 20 PGIA programmable gain instrumentation amplifier common mode signal rejection 4 25 differential connections floating signal sources 4 21 to 4 22 ground referenced signal sources 4 20 physical specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 11 AT MIO 16E 10 and AT MIO 16DE 10 A 20 AT MIO 16XE 10 and AT AI 16XE 10 A 29 AT MIO 16XE 50 A 36 pin assignments See I O connectors Plug and Play systems configuring 2 3 AT E Series User Manual Index polarity input polarity and range 3 7 to 3 10 output polarity selection 3 14 Port C signal assignments table 4 51 posttriggered data acquisition 4 31 power connections 4 29 power requirement specifications AT MIO 16E 1 AT MIO 16
94. ND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Figure B 5 50 Pin DIO Connector Pin Assignments B 6 National Instruments Corporation Appendix B Optional Cable Connector Descriptions Figure B 6 shows the pin assignments for the 50 pin extended analog input connector This is the other 50 pin connector available when you use the R1005050 cable assembly with the AT MIO 64E 3 ACH16 ACH17 ACH18 ACH19 ACH20 ACH 1 ACH22 ACH23 ACH32 ACH33 ACH34 ACH35 AISENSE2 ACH36 ACH37 ACH38 ACH39 ACH48 ACH49 ACH50 ACH51 ACH52 ACH53 ACH54 ACH55 O AJN 8 OO Ny oO j 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ACH24 ACH25 ACH26 ACH27 ACH28 ACH29 ACH30 ACH31 ACH40 ACH41 ACH42 ACH43 AIGND ACH44 ACH45 ACH46 ACH47 ACH56 ACH57 ACH58 ACH59 ACH60 ACH61 ACH62 ACH63 National Instruments Corporation Figure B 6 50 Pin Extended Analog Input Connector Pin Assignments B 7 AT E Series User Manual Common Questions Appendix This appendix contains a list of commonly asked questions and their answers relating to usage
95. NRSE configuration 4 24 l input polarity and range 3 7 to 3 10 I O connectors 4 1 to 4 14 AT MIO 16E 1 AT MIO 16E 2 exceeding maximum ratings caution AT MIO 643 3 AT MIO 16E 10 and 4 15 4 28 AT MIO 16DE 10 3 7 to 3 8 I O signal summary table actual range and measurement AT MIO 16E 1 AT MIO 16E 2 precision able i gt and AT MIO 64E 3 4 8 to 4 10 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16E 10 and AT MIO 16XE 50 3 8 to 3 10 AT MIO 16DE 10 4 10 to 4 11 AT MIO 16XE 10 AT MIO 16XE 50 AT MIO 16XE 10 and actual range and measurement AT AI 16XE 10 4 12 to 4 13 precision table 3 9 to 3 10 AT MIO 16XE 50 4 13 to 4 14 mixing bipolar and unipolar channels note 3 9 signal descriptions table 4 5 to 4 8 IBF signal table 4 52 selection considerations 3 10 Bays installation See also configuration input characteristics AT MIO 16E 1 AT MIO 16E 2 and common questions about C 2 to C 3 AT MIO 64E 3 A 1 to A 3 hardware installation 2 2 AT MIO 16E 10 and AT MIO 16DE 10 unpacking AT E series boards 1 7 A 12 to A 13 interrupt channel selection AT MIO 16XE 10 and AT AI 16XE 10 overview 2 4 A 21 to A 22 PC AT 16 bit DMA channel assignment AT MIO 16XE 50 A 30 to A 31 map table 2 7 input configurations 4 17 to 4 25 PC AT I O address map table 2 4 to 2 6 available input modes 3 6 to 3 7 PC AT interrupt assignment map table DIFF table 3 7 2 6 to 2 7 INTR signal table 4 52 National Inst
96. XE 50 It is also one of the two 50 pin connectors available when you use the R1005050 cable assembly with the AT MIO 16DE 10 or AT MIO 64E 3 AIGND 1 2 AIGND ACHO 3 4 ACH8 ACH1 5 6 ACH9 ACH2 7 8 ACH10 ACH3 9 10 ACH11 ACH4 11 12 ACH12 ACH5 13114 ACH13 ACH6 15 16 ACH14 ACH7 17 18 ACH15 AISENSE 19 20 DACOOUT DAC1OUT 21 22 EXTREF AOGND 23 24 DGND DIOO 25 26 DIO4 DIO1 27 28 DIO5 DIO2 29 30 DIO6 DIO3 31 32 DIO7 DGND 33 34 45V 5V 35 36 SCANCLK EXTSTROBE 37 38 PFIO TRIG1 PFM TRIG2 39 40 PFI2 CONVERT PFIS GPCTR1 SOURCE 41 42 PFI4 GPCTR1 GATE GPCTR1 OUT 43 44 PFI5 UPDATE PFIG WFTRIG 45 46 PFI7 STARTSCAN PFIB GPCTRO SOURCE 47 48 PFIS GPCTRO GATE GPCTRO OUT 49 50 FREQ OUT Figure B 4 50 Pin MIO Connector Pin Assignments National Instruments Corporation B 5 AT E Series User Manual Appendix B Optional Cable Connector Descriptions AT E Series User Manual Figure B 5 shows the pin assignments for the 50 pin DIO connector This is the other 50 pin connector available when you use the R1005050 cable assembly with the AT MIO 16DE 10 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO PA7 PA6 PA5 PA4 PAS PA2 PA1 PAO 5 V GND G
97. and special features of your AT E Series board General Information 1 National Instruments Corporation What are the AT E Series boards The AT E Series boards are switchless and jumperless enhanced MIO boards that use the DAQ STC for timing What is the DAQ STC The DAQ STC is the new system timing control ASIC application specific integrated circuit designed by National Instruments and is the backbone of the AT E Series boards The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into three groups e Analog input two 24 bit two 16 bit counters e Analog output three 24 bit one 16 bit counters e General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 us With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate are possible How fast is each AT E Series board The last numeral in the name of an AT E Series board specifies the settling time in microseconds for that particular board For example the AT MIO 16E 2 has a 2 us settling time which corresponds to a sampling rate of 500 kS s These sampling rates are aggregate one channel at 50
98. ard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps reproduce the problem AT E Series Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products AT E Series Board AT E Series Board Serial Number Interrupt Level of AT E Series Board DMA Channels of AT E Series Board Base I O Address of AT E Series Board Programming Choice NI DAQ LabVIEW LabWindows CVI or other Software Version Other Products Computer Model Microprocessor Clock Frequency Type of Video Board Installed Operating System DOS or Windows Operating System Version Operating System Mode Programming Language Programming Language Version Other Boards in System Base I O Address of Other Boards DMA Channels of Other Boar
99. are ComponentWorks provides a higher level programming interface for building virtual instruments through standard OLE controls and DLLs With ComponentWorks you can use all of the configuration tools resource management utilities and interactive control utilities included with NI DAQ LabVIEW features interactive graphics a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to NI DAQ software LabWindows CVI features interactive graphics state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisition Library is functionally equivalent to the NI DAQ software VirtualBench features virtual instruments that combine DAQ products software and your computer to create a stand alone instrument with the added benefit of the processing display and storage capabilities of your computer VirtualBench instruments load and save waveform data to disk in the same forms that can be used in popular spreadsheet programs and word processors Using ComponentWorks LabVIEW LabWindows CVI or Virt
100. are Installation s sete eese Here re eee tee etie e coe ee never coves 2 1 Hardware Installation 2 eee erre Pr er eee eR ERI ET ve Eee ere ER TS ES 2 2 Board Configuration ceti steve tn des oe e RUE ice erepto 2 2 Bus Interface sre Reddere RB A eas 2 3 Plug and Play o Tree e eese eee eR deee eir i eee pO Rx 2 3 Switchless Data Acquisition esee 2 3 Base I O Address Selection eese 2 3 DMA Channel Selection seeeeseeeeeneene nne 2 4 Interrupt Channel Selection seen 2 4 National Instruments Corporation V AT E Series User Manual Contents Chapter 3 Hardware Overview Analog Input Ste RERO Dree E E E oe ihe 3 6 Input Mode ioni ee e Pete ete na cede Bawah ae aes 3 6 Input Polarity and Input Range eene 3 7 Considerations for Selecting Input Ranges sessse 3 10 Dithet i ieoanimeteea Puro DR ee EE HOUR 3 10 Multiple Channel Scanning Considerations esses 3 12 Analog Output guten he eee eee rp rne ete 3 13 Analog Output Reference Selection sse 3 13 Analog Output Polarity Selection esses 3 14 Analog Output Reglitch Selection essere 3 14 Analog Trigget roten n e pee PUE e Tre DER ea TEES IOE EEEE h 3 15 Digital IO o Rete Re tete UI IIO ERE 3 18 Timing Signal Routing itte ertet e eere e ttp repre ie iSS 3 19 Pro
101. asily configured and calibrated using software The AT E Series boards are the first completely switchless and jumperless data acquisition boards This feature is made possible by the National Instruments DAQ PnP bus interface chip that connects the board to the AT I O bus The DAQ PnP implements the Plug and Play ISA Specification so that the DMA interrupts and base I O addresses are all software configurable This allows you to easily change the AT E Series board configuration without having to remove the board from your computer The DAQ STC makes possible such applications as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate The AT E Series boards use the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control analog input analog output and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns A common problem with DAQ boards is that you cannot easily synchronize several measurement functions to a common trigger or National Instruments Corporation 1 1 AT E Series User Manual Chapter 1 Introduction timing event The AT E Series boards have the Real Time System Integration RTSI bus to solve this problem The RTSI bus consists of our RTSI bus interface and a ribbon cable to route timing and trigger sig
102. ate of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should cons
103. ates that the data written from the selected port has been accepted This signal is a response from the external device that it has received the data from the AT MIO 16DE 10 OBF output Output Buffer Full A low signal on this handshaking line indicates that data has been written from the selected port INTR output Interrupt Request This signal becomes high to request service during a data transfer The appropriate interrupt enable bits must be set to generate this signal and to allow it to interrupt your computer RD internal Read Signal This signal is the read signal generated by the host computer WR internal Write Signal This signal is the write signal generated by the host computer DATA input Data Lines at the Selected Port PA or PB This signal indicates when the data on the or output data lines at a selected port is or should be available AT E Series User Manual 4 52 National Instruments Corporation Mode 1 Input Timing Figure 4 38 details the timing specifications for an input transfer in Chapter 4 Signal Connections Mode 1 i T i gd T2 74 lt gt STB o4 i 1 a NE eom INTR T3 PEE DATA Name Description Minimum Maximum TI STB Pulse Width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 150 T5 Data after STB 1 50 T6 RD 0 to INTR 0 200 T7 RD 1 to IBF 0 150
104. ation reference After calibration gain 1 0 02 of reading max Before calibration 2 5 of reading max Gain 1 with gain error adjusted to 0 at gain 1 0 02 of reading max Amplifier Characteristics Input impedance Normal powered on 100 GQ in parallel with 100 pF Powered off 820 Q min Overload eere 820 Q min Input bias current esesses 200 pA Input offset current 100 pA CMRR DC to 60 Hz Gain 0 5 4 ssi 95 dB Gain o l 3uoneeprs ees 100 dB Gain 2 pedes eR 106 dB National Instruments Corporation A 3 ATE Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 AT E Series User Manual Dynamic Characteristics Bandwidth Small signal 3dB Large signal 1 THD AT MIO 16E 1 1 6 MHz 1 MHz AT MIO 16E 2 1 MHz 300 kHz AT MIO 64E 3 Setting time for full scale step Accuracy 0 012 Gain 40 5 LSB 0 024 0 098 1 LSB 4 LSB AT MIO 16E 1 0 5 2 us typ 1 5 us typ 1 5 us typ 3 us max 2 us max 2 us max 1 2 us typ 1 5 us typ 1 3 us typ 3 us max 2 us max 1 5 us max 2to50 2ustyp 1 5 us typ 0 9 us typ 3 us max 2 us max 1 us max 100 2 us typ 1 5 us typ 1 us typ 3 us max 2 us max 1 5 us max AT MIO 16E 2 All 2 us typ 1 9 us typ 1 8 us typ 4 us max 2 us max 2 us max AT MIO 64E 3
105. ce less than 100 2 However for larger source impedances this connection leaves the differential signal path significantly out of balance Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground Hence this noise appears as a differential mode signal instead of a common mode signal and so the PGIA does not reject it In this case instead of directly connecting the negative line to AIGND connect it to AIGND through a resistor that is about 100 times the equivalent source impedance The resistor puts the signal path nearly in balance so that about the same amount of noise couples onto both connections yielding better rejection of electrostatically coupled noise Also this configuration does not load down the source other than the very high input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 7 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 kQ and each of the two resistors is 100 kQ the resistors load down the source with 200 kQ and produce a 1 gain error Both inputs of the PGIA require a DC path to ground in order for the PGIA to work If the source is AC coup
106. count TC of general purpose counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 33 shows the timing of the GPCTRO OUT signal GPCTRO SOURCE GPCTRO OUT Pulse on TC GPCTRO OUT Toggle output on TC TC i AT E Series User Manual Figure 4 33 GPCTRO OUT Signal Timing GPCTRO UP DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 will count down when this pin is at a logic low and count up when itis ata logic high You can disable this input so that software can control the up down functionality and leave the DIOG pin free for general use 4 46 National Instruments Corporation Chapter 4 Signal Connections GPCTR1 SOURCE Signal Any PFI pin can externally input the GPCTR1 SOURCE signal which is available as an output on the PFI3 GPCTR1 SOURCE pin As an input the GPCTR1 SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRI SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTR1 SOURCE monitors the actual clock connected to general purpose counter 1 This is true even if the source clock is bei
107. cted channel and the resolution is that range divided by 256 for the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 and divided by 4 096 for the AT MIO 16XE 10 and AT AI 16XE 10 The PFIO TRIGI pin is a high impedance input Therefore it is susceptible to cross talk from adjacent pins which can result in false triggering when the pin is left unconnected To avoid false triggering make sure this pin is connected to a low impedance signal source less than 10 kQ source impedance if you plan to enable this input via software National Instruments Corporation 3 15 AT E Series User Manual Chapter 3 Hardware Overview Analog Input Channels PFIO TRIG1 AT E Series User Manual PGIA ADC Analog Mux Trigger DAQ STC Circuit Figure 3 8 Analog Trigger Block Diagram There are five analog triggering modes available as shown in Figures 3 9 through 3 13 You can set lowValue and highValue independently in software In below low level analog triggering mode the trigger is generated when the signal value is less than lowValue HighValue is unused lowValue Trigger es ee ee Lb Figure 3 9 Below Low Level Analog Triggering Mode In above high level analog triggering mode the trigger is generated when the signal value is greater than high Value LowValue is unused 3 16 National Instruments Corporation Chapter 3 Hardware Overview highValue
108. d How does NI DAQ treat bogus missed data transfer errors that can arise during DMA driven GPCTR buffered input operations When doing buffered transfers using GPCTR function calls with DMA you can call GPCTR Watch to indicate dataTransfer errors NI DAQ takes a snapshot of transfers and counts how many points have been transferred If all the points have been transferred and the first instance of this error occurs NI DAQ returns a gpctrDataTransfer Warning indicating that the error could be bogus If all the points have not been transferred NI DAQ returns the genuine error The error continues to be returned until the acquisition completes The above error occurs because NI DAQ disarms the counter from generating any more requests in the interrupt service routine Due to interrupt latencies it is possible that the counter may have generated some spurious requests which the DMA controller may not satisfy because it has already transferred the required number of points What are the PFIs and how do I configure these lines PFIs are Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using NI DAQ language interface LabWindows or LabWindows CVI use the Select_Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect
109. d DMA channels than I have available in my PC What should I do By using the proper configuration utility NI DAQ Configuration Utility you can disable interrupt and DMA channels for the board you are using You may be more limited in the functionality of the board usually regarding high speed acquisition but you should at least be able to use basic functionality for all boards in the system How can I select an AT E Series board as my device type in the NI DAQ Configuration Utility First make sure your board is plugged into your computer The NI DAQ Configuration Utility can scan your system for any AT E Series devices If no AT E Series boards are found the AT E Series device types are not given as choices C 3 AT E Series User Manual Appendix C Common Questions Analog Input and Output AT E Series User Manual 14 15 16 17 I m using my board in differential analog input mode and I have connected a differential input signal but my readings are random and drift rapidly What s wrong Check your ground reference connections Your signal may be referenced to a level that is considered floating with reference to the board ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the board reference There are various methods of achieving this while maintaining a high common mode rejection ratio CMRR These methods are outlined in Chapter 4 Signa
110. d I O DMA nodes eteenceeRue Single transfer Transfer Characteristics Relative accuracy INL 0 5 LSB max DNE EIU 1 LSB max Monotonicity e cee eeeeeeeeeceeeceeeeeeeeees 12 bits guaranteed Offset error After calibration cccccceeeee ees 0 5 mV max Before calibration 85 mV max Gain error relative to calibration reference After calibration 0 01 of output max Before calibration 1 of output max Voltage Output Ranges eisai 10 V Output coupling 0 eee eee DC Output impedance eee 0 1 Q max Current drive esssssseeeee 5 mA Protection ite Short circuit to ground Power On state eeesssseeeee 0 V 4 85 mV Dynamic Characteristics Settling time for full scale step 50 us to 0 5 LSB accuracy Slew Late xo RR ee 2 V us NOISE sessssussszensedecssnocsseotenceshstsdessesete sites 40 uVrms DC to MHz Glitch energy at midscale transition Magnitude oo eee eee 30 mV National Instruments Corporation A 33 AT E Series User Manual Appendix A Specifications for AT MIO 16XE 50 Digital 1 0 Timing 1 0 AT E Series User Manual Duration seeeee 10 us Stability Offset temperature coefficient 25 uV P C Gain temperature coefficient 15 ppm C Number of channels
111. derable amount of noise visible But averaging about 50 such acquisitions as shown in Figure 3 7d eliminates both the added noise and the effects of quantization Dither has the effect of forcing quantization noise to become a zero mean random variable rather than a deterministic function of the input signal LSBs LSBs 6 0 6 0 4 0 4 0 2 0 d 2 0 0 0 0 0 2 0 H 2 0 4 0 4 0 6 0 6 0 4 0 100 200 300 400 500 0 100 200 300 400 500 a Dither disabled no averaging b Dither disabled average of 50 acquisitions LSBs LSBs 610 6 0 4 0 4 0 2 0 2 0 0 0 0 0 L 2 0 2 0 4 0 4 0 6 0 T E E E E 80 __ __ __ _ _ 0 100 200 300 400 500 0 100 200 300 400 500 c Dither enabled no averaging d Dither enabled average of 50 acquisitions Figure 3 7 Dither National Instruments Corporation 3 11 AT E Series User Manual Chapter 3 Hardware Overview You cannot disable dither on the AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 This is because the resolution of the ADC is so fine that the ADC and the PGIA inherently produce almost 0 5 LSB rms of noise This is equivalent to having a dither circuit that is always enabled Multiple Channel Scanning Considerations AT E Series User Manual All of the AT E Series boards can
112. ds Interrupt Level of Other Boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title AT E Series User Manual Edition Date Part Number January 1999 320517G 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Fax Mail t0 Technical Publications National Instruments Corporation 6504 Bridge Point Parkway Austin TX 78730 5039 Fax to Technical Publications National Instruments Corporation 512 794 5678 Glossary Prefix Meaning Value p pico s n nano 10 u micro fore m milli 10 k kilo 10 M mega 10 G giga 10 Symbols percent plus or minus 8 degrees per positive of or plus negative of or minus Q ohms m square root of 45V 5 VDC source signal National Instruments Corporation G 1 AT E Series User Manual Glossary A A AC ACH A D ADC AIGATE AIGND AISENSE AISENSE2 ANSI AOGND ASIC BIOS C C CalDAC CMOS CMRR CONVERT AT E Series User Manual amperes alternating cur
113. e adjustments take the form of writing values to onboard calibration DACs CalDACs Some form of board calibration is required for all but the most forgiving applications If no board calibration were performed your signals and measurements could have very large offset gain and linearity errors Three levels of calibration are available to you and these are described in this chapter The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants Your AT E Series board is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACS to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the board is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM NI DAQ software determines when this is necessary and does it automatically If you are not using NI DAQ you must load these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This means that you can load the CalDACs with values either from the original factory calibration or from
114. e eee 100 kS s Type of DAC oreorern Double buffered multiplying FIFO buffer size siisii eens None Data transfers DMA interrupts programmed I O DMA Mod s teer tede ntt Single transfer National Instruments Corporation A 15 AT E Series User Manual Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 AT E Series User Manual Transfer Characteristics Relative accuracy INL After calibration 0 3 LSB typ 0 5 LSB max Before calibration 4 LSB max DNL After calibration 0 3 LSB typ 1 0 LSB max Before calibration 3 LSB max Monotonicity eese 12 bits guaranteed after calibration Offset error After calibration ss 1 0 mV max Before calibration 200 mV max Gain error relative to internal reference After calibration 0 01 of output max Before calibration 0 5 of output max Gain error relative to external reference 0 to 40 596 of output max not adjustable Voltage Output Ranges 55i en e 10 V 0 to 10 V 4EXTREF 0 to EXTREF software selectable Output coupling eee eee DC Output impedance sss 0 1 max Current drive 5 mA max Protection iue Rie Short circuit to ground Power on state nininini OV A 16 National
115. e maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source Figure 4 25 shows the timing requirements for the SISOURCE signal tp 50 ns minimum ty 23 ns minimum Figure 4 25 SISOURCE Signal Timing ion Timing Connections The analog group defined for your AT E Series board is controlled by WFTRIG UPDATE and UISOURCE 4 40 National Instruments Corporation Chapter 4 Signal Connections WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFIG WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UI counter is started if you select internally generated UPDATE As an output the WFTRIG signal reflects the trigger that initiates waveform generation This is true even if the waveform generation is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 26 and 4 27 show the input and output
116. e us DAQPmP and E enki eta vo Analog Output RTS Bus AH z 1 Analog Output RTSI Bus Analog 8255 Bus Digital l O 8 Digital YO imingiControl Interface Girltol contro 1 tertace be Data 16 National Instruments Corporation Figure 3 5 AT Al 16XE 10 Block Diagram 3 5 AT E Series User Manual Chapter 3 Hardware Overview Figure 3 6 shows a block diagram for the AT MIO 16XE 50 Voltage Calibration REF ES DACs 2 Mux Mode 16 Bit P Selection Frogrammable Sampling ADC Data Switches en SD er FIFO Transceivers 7 EEPROM Configurati ea Al Control x fea 5 i o DMA 8 c g c B PFI Trigger Analoginput DM g i Trigger Interrupt c gg 1 Timing Control Request et EEPROM I DMA c c Eumene Mdh Contro Control interface EPALE Counter us Baas Plug 8 Timing l O DAQ STC interface Asus pAQenP Sand O ee SS lt Interface Play 1 Analog Output 1 RTSI Bus Analog 8255 o Bus Q Digital VO 8 Digital VO Timing Control Interface Qutput DIO Interface lt 5 AO Control pee egi e eines 1 1 i DACO Data 16 1 1 1 1 lt _1_ DAC1 1 Calibration 4 DACs Figure 3 6 AT MIO 16XE 50 Block Diagram Analog Input The analog input section of each AT E Series board is software configurable You can select diff
117. ence Temperature coefficient Long term stability Bus Interface Power Requirement 5 VDC 45 Power available at I O connector AT E Series User Manual A 10 Rising or falling edge 10 ns min 5 000 V 42 5 mV actual value stored in EEPROM 5 ppm C max 15 ppm 1 0007 Slave 1 0A 4 65 VDC to 5 25 VDC at1 A National Instruments Corporation Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in I O connector AT MIO 16E 1 AT MIO 16E 2 00 68 pin male SCSI II type AT MIO 64E 3 eese 100 pin female 0 050 D type Environment Operating temperature 0 to 55 C Storage temperature 0 0 0 eee 55 to 150 C Relative humidity 5 to 90 noncondensing National Instruments Corporation A 11 AT E Series User Manual Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 AT MIO 16E 10 and AT MIO 16DE 10 Analog Input Input Characteristics Number of channels Type of ADC ee Resolution cccccceeceeeeee eee Max sampling rate Input signal ranges 16 single ended or 8 differential software selectable Successive approximation 12 bits 1 in 4 096 100 kS s guaranteed
118. ended or 8 differential software selectable Successive approximation 16 bits 1 in 65 536 20 kS s guaranteed Board Range Software Selectable Board Gain Software Selectable Bipolar Unipolar 1 10 V 0to10 V 2 5 V 0to5V 10 1 V Otol V 100 0 1 V 0 to 0 1 V Input coupling 0 0 eee anes DC Maximum working voltage signal common mode Overvoltage protection Inputs protected FIFO buffer size AT E Series User Manual A 30 The average voltage of each differential pair should remain within 8 V of ground 25 V powered on 15 V powered off ACH lt 0 15 gt AISENSE 512 samples National Instruments Corporation Appendix A Specifications for AT MIO 16XE 50 Data transfers eeeI DMA interrupts programmed I O DMA modes seen Single transfer demand transfer Configuration memory size 512 words Transfer Characteristics Relative accuracy eeeeeeeese 0 5 LSB typ 1 LSB max DNE inte tees 0 5 LSB typ 1 LSB max No missing codes seeen 16 bits guaranteed Offset error Pregain error after calibration 3 uV max Pregain error before calibration t1 mV max Postgain error after calibration 76 uV max Postgain error before calibration 44 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max
119. ents Corporation Chapter 4 Signal Connections Figures 4 28 and 4 29 show the input and output timing requirements for the UPDATE signal Rising edge polarity Falling edge polarity ty 10 ns minimum Figure 4 28 UPDATE Input Signal Timing tw tw 300 350 ns Figure 4 29 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The AT E Series board UI counter normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate National Instruments Corporation 4 43 AT E Series User Manual Chapter 4 Signal Connections UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE signal You must configure the PFI pin you select as the source for the UISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Figure 4 30 shows the timing requirements for the UISOURCE s
120. ents application software refer to the appropriate release notes and follow the instructions given there for your operating system and application software If you are a register level programmer refer to the A7 MIO E Series Register Level Programmer Manual and the DAQ STC Technical Reference Manual for software configuration information National Instruments Corporation 2 1 AT E Series User Manual Chapter 2 Installation and Configuration Hardware Installation You can install an AT E Series board in any available expansion slot in your PC However to achieve best noise performance you should leave as much room as possible between the AT E Series board and other boards and hardware The following are general installation instructions but consult your PC user manual or technical reference manual for specific instructions and warnings 1 Write down the AT E Series board serial number in the AT E Series Hardware and Software Configuration Form in Appendix D Customer Communication at the back of this manual You will need this serial number when you install and configure your software 2 Turn off and unplug your computer 3 Remove the top cover or access port to the I O channel 4 Remove the expansion slot cover on the back panel of the computer 5 Insertthe AT E Series board into an EISA or 16 bit ISA slot It may be a tight fit but do not force the board into place 6 Screw the mounting bracket of the AT E Series
121. er STB 1 50 T6 ACK 0 to OBF 1 150 T7 ACK Pulse Width 100 T8 ACK 0 to Output 150 T9 ACK 1 to Output Float 20 250 T10 RD 1 to IBF 0 150 All timing values are in nanoseconds Figure 4 40 Mode 2 Bidirectional Timing National Instruments Corporation 4 55 AT E Series User Manual Chapter 4 Signal Connections Field Wiring Considerations AT E Series User Manual Environmental noise can seriously affect the accuracy of measurements made with your AT E Series board if you do not take proper care when running signal wires between signal sources and the board The following recommendations apply mainly to analog input signal routing to the board although they also apply to signal routing in general You can minimize noise pickup and maximize measurement accuracy by taking the following precautions e Use differential analog input connections to reject common mode noise e Use individually shielded twisted pair wires to connect analog input signals to the board With this type of wire the signals attached to the CH and CH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference e Route signals to the board carefully Keep cabling away from noise sources The most commo
122. er calibration 3 uV max Pregain error before calibration 2 2 mV max Postgain error after calibration 76 uV max Postgain error before calibration After calibration gain 1 Before calibration Gain z 1 A 22 102 mV max Gain error relative to calibration reference 30 5 ppm of reading max 2 150 ppm of reading max With gain error adjusted to 0 at gain 1 200 ppm of reading National Instruments Corporation Appendix A Specifications for AT MIO 16XE 10 and AT Al 16XE 10 Amplifier Characteristics Input impedance Normal powered on 100 GQ in parallel with 100 pF Powered off 820 Q min Overload eoe es 820 Q min Input bias current eeeees nA Input offset current ssss 2 nA CMRR DC to 60 Hz Gam HV eee sdb he act 92 dB GAIT 232 esee ee 97 dB Gait Joe icine 101 dB Gam 2 103 tomen 104 dB Gam 20 icutueeets 105 dB Gain a 50 seeriana en 105 dB Gain 100 0 ceeeeeeecceeeeeeeeee 105 dB Dynamic Characteristics Bandwidth Albgains pee 255 kHz Settling time for full scale step all gains and ranges LOO LSB aet is 40 us typ To I LS Bonnis innnan 20 us typ To 4 LSB ees 10 us typ System noise including quantization noise Gain 1 2 5 10 ween 0 6 LSB rms bipolar 0 8 LSB rms unipolar Gam S20 5 ent tete us 0 7 LSB rms bipolar 1 1 LSB rms unipo
123. erent analog input configurations through application software designed to control the AT E Series boards The following sections describe in detail each of the analog input categories Input Mode The AT E Series boards have three different input modes nonreferenced single ended NRSE input referenced single ended RSE input and differential DIFF input The single ended input configurations use up to 16 channels 64 channels on the AT MIO 64E 3 The DIFF input configuration uses up to eight AT E Series User Manual 3 6 National Instruments Corporation Chapter 3 Hardware Overview channels 32 channels on the AT MIO 64E 3 Input modes are programmed on a per channel basis for multimode scanning For example you can configure the circuitry to scan 12 channels four differentially configured channels and eight single ended channels Table 3 1 describes the three input configurations Table 3 1 Available Input Configurations for the AT E Series Configuration Description DIFF A channel configured in DIFF mode uses two analog channel input lines One line connects to the positive input of the board programmable gain instrumentation amplifier PGIA and the other connects to the negative input of the PGIA RSE A channel configured in RSE mode uses one analog channel input line which connects to the positive input of the PGIA The negative input of the PGIA is internally tied to analog input ground AIGND
124. es User Manual Chapter 4 Signal Connections Table 4 1 1 0 Signal Summary AT E Series Continued Signal Name Reference Direction Description DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply All three ground references AIGND AOGND and DGND are connected together on your AT E Series board DIO lt 0 7 gt DGND Input or Digital I O signals DIO6 and 7 can control the up down Output signal of general purpose counters 0 and 1 respectively PA lt 0 7 gt DGND Input or Port A These pins are port A of the extra digital I O signals Output on the AT MIO 16DE 10 PB lt 0 7 gt DGND Input or Port B These pins are port B of the extra digital I O signals Output on the AT MIO 16DE 10 PC lt 0 7 gt DGND Input or Port C These pins are port C of the extra digital I O signals Output on the AT MIO 16DE 10 5 V DGND Output 5 VDC Source These pins are fused for up to 1 A of 5 V supply The fuse is self respecting SCANCLK DGND Output Scan Clock This pin pulses once for each A D conversion in the scanning modes when enabled The low to high edge indicates when the input signal can be removed from the input or switched to another signal EXTSTROBE DGND Output External Strobe This output can be toggled under software control to latch signals or trigger events on external devices PFIO TRIGI DGND Input PFIO Trig
125. gains of 0 5 1 2 5 10 20 50 and 100 and are suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 2 shows the AT E Series User Manual overall input range and precision according to the input range configuration and gain used Tahle 3 2 Actual Range and Measurement Precision Range Configuration Gain Actual Input Range Precision 0 to 10 V 1 0 0 to 10 V 2 44 mV 2 0 0to45 V 1 22 mV 5 0 0to 42V 488 28 uV 10 0 Oto 1 V 244 14 uV 20 0 0 to 500 mV 122 07 uV 50 0 0 to 200 mV 48 83 uV 100 0 0 to 100 mV 24 41 uV 5to 45 V 0 5 10 to 10 V 4 88 mV 1 0 5 to 45 V 2 44 mV 2 0 2 5 to 42 5 V 1 22 mV 5 0 to 1 V 488 28 uV 10 0 500 to 500 mV 244 14 u V 20 0 250 to 250 mV 122 07 uV 50 0 100 to 100 mV 48 83 uV 100 0 50 to 50 mV 24 41 uV The value of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 12 bit count Note See Appendix A Specifications for absolute maximum ratings AT MIO 16XE 10 AT AI 16XE 10 AT MIO 16XE 50 These boards have two input polarities unipolar and bipolar Unipolar input means that the input voltage range is between 0 and V ef where Vef s a positive reference voltage Bipolar input means that the input 3 8 National Instruments Corporation UP Note Chapter 3 Hardware Overview volta
126. ge range is between V c and V ef The AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 have a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 20 V 10 V You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely You can calibrate your AT MIO 16XE 10 AT AI IGXE 10 and AT MIO 16XE 50 analog input circuitry for either a unipolar or bipolar polarity If you mix unipolar and bipolar channels in your scan list and you are using NI DAQ then NI DAQ will load the calibration constants appropriate to the polarity for which analog input channel 0 is configured The software programmable gain on these boards increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate The AT MIO 16XE 10 and AT AI 16XE 10 have gains of 1 2 5 10 20 50 and 100 and the AT MIO 16XE 50 has gains of 1 2 10 and 100 These gains are suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 3 shows the overall input range and precision according to the input range configuration and gain used Table 3 3 Actual Range and Measurement Precision AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 Range Configuration Gain Actual Input Range Precision 0 to 10 V 1 0 0to 10V 152 59 uV 2 0 0to 5 V 76 29 uV 5 02 0 to 2 V 3
127. ger 1 As an input this is either one of the Programmable Function Inputs PFIs or the source for the hardware analog trigger PFI signals are explained in the Timing Connections section later in this chapter The hardware analog trigger is explained in the Analog Trigger section in Chapter 2 Analog trigger is available only on the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16XE 10 AT AI 16XE 10 and the AT MIO 64E 3 Output As an output this is the TRIGI signal In posttrigger data acquisition sequences a low to high transition indicates the initiation of the acquisition sequence In pretrigger applications a low to high transition indicates the initiation of the pretrigger conversions AT E Series User Manual 4 6 National Instruments Corporation Chapter 4 Signal Connections Table 4 1 1 0 Signal Summary AT E Series Continued Signal Name Reference Direction Description PFI1 TRIG2 DGND Input PFI1 Trigger 2 As an input this is one of the PFIs Output As an output this is the TRIG2 signal In pretrigger applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in posttrigger applications PFI2 CONVERT DGND Input PFI2 Convert As an input this is one of the PFIs Output As an output this is the CONVERT signal A high to low edge on CONVERT indicates that an A D conversion is occurring PFI3 GPCTR1_SOURCE DGND Input PF
128. grammable Function Inputs eese 3 20 Board and RTSI Clocks etre Rn ruine 3 20 RTSETriggets see EE REO RU ER pH RE 3 21 Chapter 4 Signal Connections VO Connector ieu eae iste secant erected eee SL RR ee TUR 4 1 T O Connector Signal Descriptions essere 4 5 Analog Input Signal Connections ener nre 4 15 Types ot Signal SOULCES ts oh etc i Fo edt e ede ee egt 4 17 Floating Signal Sources eesessssssseeeeeeee ener nennen 4 17 Ground Referenced Signal Sources esee 4 17 Input Configurations eseeeeseeseeeeeen nennen nennen treten retenti en nennen 4 17 Differential Connection Considerations DIFF Input Configuration 4 19 Differential Connections for Ground Referenced Signal SOULCES i eiie Soo iios ele tis negem bert teeny 4 20 Differential Connections for Nonreferenced or Floating Signal SOUFCES iere ed Re eee denen eto 4 21 Single Ended Connection Considerations sse 4 23 Single Ended Connections for Floating Signal Sources RSE Configuration eese enne ener 4 24 Single Ended Connections for Grounded Signal Sources NRSE Configuration secre i rii i 4 24 Common Mode Signal Rejection Considerations ssss 4 25 Analog Output Signal Connections eese ener nennen 4 26 Digital I O Signal Connections sese enesenn ire Apae imeen EER oE PES enne nnne 4 27 AT E
129. h required is 10 ns This applies for both rising edge and falling edge polarity settings There is no maximum pulse width requirement in edge detect mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but there may be limits imposed by the particular timing signal being controlled These requirements are listed later in this chapter Data Acquisition Timing Connections The data acquisition timing signals are SCANCLK EXTSTROBE TRIG1 TRIG2 STARTSCAN CONVERT AIGATE and SISOURCE Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered data acquisition sequence is shown in Figure 4 13 Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 14 shows a typical pretriggered data acquisition sequence The description for each signal shown in these figures is included later in this chapter TRIG1 CONVERT LO Scan Counter STARTSCAN 4 3 1 Figure 4 13 Typical Posttriggered Acquisition National Instruments Corporation 4 31 AT E Series User Manual Chapter 4 Signal Connections TRIG1 TRIG2 STARTSCAN CONVERT Scan Counter Don t Care
130. help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation When you contact us we need the information on the Technical Support Form and the configuration form if your manual contains one about your system configuration to answer your questions as quickly as possible National Instruments has technical assistance through electronic fax and telephone systems to quickly provide the information you need Our electronic services include a bulletin board service an FTP site a fax on demand system and e mail support If you have a hardware or software problem first try the electronic support systems If the information available on these systems does not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information call 512 795 6990 You can access these services at United States 512 794 5422 Up to 14 400 baud 8 data bits 1 stop bit no parity United Kingdom 01635 551
131. ibration reference to ensure the accuracy of self calibration Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using your board at an extreme temperature or if the onboard reference has not been measured for a year or more you may wish to externally calibrate your board An external calibration refers to calibrating your board with a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate your board by calling the NI DAQ calibration function 5 2 National Instruments Corporation Chapter 5 Calibration To externally calibrate your board be sure to use a very accurate external reference The reference should be several times more accurate than the board itself For example to calibrate a 12 bit board the external reference should be at least 0 00596 50 ppm accurate To calibrate a 16 bit board the external reference should be at least 0 001 10 ppm accurate Other Considerations The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel
132. ical and mechanical aspects of each board in the AT E Series product line and contains information concerning their operation and programming Unless otherwise noted text applies to all boards in the AT E Series The AT E Series includes the following boards AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MIO 16DE 10 AT MIO 16XE 10 AT AI 16XE 10 AT MIO 16XE 50 The AT E Series boards are high performance multifunction analog digital and timing I O boards for the PC AT series computers Supported functions include analog input analog output digital I O and timing I O Organization of This Manual The AT MIO AI E Series User Manual is organized as follows National Instruments Corporation Chapter 1 Introduction describes the AT E Series boards lists what you need to get started describes the optional software and optional equipment and explains how to unpack your AT E Series board Chapter 2 Installation and Configuration explains how to install and configure your AT E Series board Chapter 3 Hardware Overview presents an overview of the hardware functions on your AT E Series board Xi AT E Series User Manual About This Manual e Chapter 4 Signal Connections describes how to make input and output signal connections to your AT E Series board via the board I O connector e Chapter 5 Calibration discusses the calibration procedures for your AT E Series board e Appendix A Specifications
133. igger LiNE Seiken Calibration Recommended warm up time Calibration interval sesee External calibration reference Onboard calibration reference Bus Interface Power Requirement Temperature coefficient Long term stability 5 VICES RENE RR EM Power available at I O connector AT E Series User Manual A 28 analog trigger signal or disabled 35 V powered off 1 of full scale range TTL Rising or falling edge 10 ns min 15 min 1 year gt 6 and lt 9 999V 5 000 V 40 5 mV actual value stored in EEPROM 0 6 ppm C max 6 ppm A1 0007 Slave 12A 4 65 VDC to 5 25 VDC at 1 A National Instruments Corporation Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in I O connector eeeeenenee 68 pin male SCSI II type Environment Operating temperature 0 to 55 C Storage temperature 0 0 0 55 to 150 C Relative humidity 5 to 90 noncondensing National Instruments Corporation A 29 AT E Series User Manual Appendix A Specifications for AT MIO 16XE 50 AT MIO 16XE 50 Analog Input Input Characteristics Number of channels Type of ADC Resolution Maximum sampling rate Input signal ranges 16 single
134. ignal tp 50 ns minimum ty 23 ns minimum Figure 4 30 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 KHz internal timebase normally generates the UISOURCE signal unless you select some external source General Purpose Timing Signal Connections AT E Series User Manual The general purpose timing signals are GPCTRO SOURCE GPCTRO GATE GPCTRO OUT GPCTRO UP DOWN GPCTRI SOURCE GPCTR1_GATE GPCTRI OUT GPCTRI UP DOWN and FREQ OUT GPCTRO SOURCE Signal Any PFI pin can externally input the GPCTRO SOURCE signal which is available as an output on the PFIS GPCTRO SOURCE pin As an input the GPCTRO SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO SOURCE and configure the polarity selection for either rising or falling edge 4 44 National Instruments Corporation Chapter 4 Signal Connections As an output the GPCTRO SOURCE signal reflects the actual clock connected to general purpose counter 0 This is true even if another PFI is externally inputting the source clock This output is set to tri state at startup Figure 4 31 shows the timing requirements for the GPCTRO SOURCE signal tp 50 ns minimum tw 23 ns minimum Figure 4 31 GPCTRO_SOURCE Signal Timing The maximum
135. in volts output high volts output low reference voltage waveform generation trigger signal National Instruments Corporation G 7 Glossary AT E Series User Manual Symbols 5 V signal description 4 6 power connections 4 29 A ACH lt 0 15 gt signal analog input connections 4 15 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 ACH lt 0 63 gt signal analog input connections 4 15 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 ACK signal table 4 52 addresses base I O address selection 2 3 PC AT I O address map table 2 4 to 2 6 AIGATE signal 4 39 to 4 40 AIGND signal analog input connections 4 15 to 4 16 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 National Instruments Corporation Index description table 4 5 differential connections for floating signal sources 4 21 to 4 22 AISENSE signal analog input connections 4 15 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 AISENSE2 signal analog input connections 4 15 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 de
136. ion to the usual steps for data acquisition and waveform generation configuration C 4 National Instruments Corporation Timing and Digital 1 0 18 19 National Instruments Corporation Appendix C Common Questions a Enable the PFI5 line for output as follows If you are using NI DAQ call Select Signal deviceNumber ND PFI 5 ND OUT UPDATE ND HIGH TO LOW If you are using LabVIEW invoke Route Signal VI with signal name set to PFI5 and signal source set to AO Update b Setup data acquisition timing so that the timing signal for A D conversion comes from PFI5 as follows If you are using NI DAQ call Select Signal deviceNumber ND IN CONVERT ND PFI 5 ND HIGH TO LOW If you are using LabVIEW invoke AI Clock Config VI with clock source code set to PFI pin high to low and clock source string set to 5 c Initiate analog input data acquisition which will start only when the analog output waveform generation starts For example if you are using NI DAQ you can call DAQ Start With appropriate parameters Similarily if you are using LabVIEW you can invoke AI Control VI with control code set to O start d Initiate analog output waveform generation If you are using NI DAQ call WFM Group Control with operation set to 1 start If you are using LabVIEW you can invoke AO Control VI with control code set to O start What types of triggering can be implemented in hardware on my AT E Series b
137. l Connections Can I sample across a number of channels on an AT E Series board while each channel is being sampled at a different rate NI DAQ for PC compatibles version 4 5 1 or later features a new function called SCAN Sequence Setup which allows for multirate scanning of your analog input channels Refer to the NI DAQ Function Reference Manual for PC Compatibles for more details I m using the DACS to generate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When it switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of your output signal The AT MIO 16E 1 AT MIO 16E 2 and the AT MIO 64E 3 boards have built in reglitchers which can be enabled through software on their analog output channels See the Analog Output Reglitch Selection section in Chapter 3 Hardware Overview for more information about reglitching Can I synchronize a one channel analog input data acquisition with a one channel analog output waveform generation on my AT E Series board Yes One way to accomplish this is to use the waveform generation timing pulses to control the analog input data acquisition To do this follow steps a through d below in addit
138. l pair ACH lt i i 8 gt i 0 7 can be configured as either one differential input or two single ended inputs ACH lt 16 63 gt AIGND Input Analog Input Channels 16 through 63 AT MIO 64E 3 only Each channel pair ACH lt i i 8 gt i 16 23 32 39 48 55 can be configured as either one differential input or two single ended inputs AISENSE AIGND Input Analog Input Sense This pin serves as the reference node for any of channels ACH lt 0 15 gt in NRSE configuration AISENSE2 AIGND Input Analog Input Sense AT MIO 64E 3 only This pin serves as the reference node for any of channels ACH lt 16 63 gt in NRSE configuration DACOOUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 This pin is not available on the AT AI 16XE 10 DACIOUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 This pin is not available on the AT AI 16XE 10 EXTREF AOGND Input External Reference This is the external reference input for the analog output circuitry This pin is not available on the AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 AOGND Analog Output Ground The analog output voltages are referenced to this node All three ground references AIGND AOGND and DGND are connected together on your AT E Series board National Instruments Corporation 4 5 AT E Seri
139. lar Gan 3505 etaed 1 1 LSB rms bipolar 2 0 LSB rms unipolar Gain 100 sss 2 0 LSB rms bipolar 3 8 LSB rms unipolar National Instruments Corporation A 23 AT E Series User Manual Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Dynamic range Crosstalk Stability Offset temperature coefficient Pregador edere Postg ln iere Rctn Gain temperature coefficient Analog Output AT MIO 16XE 10 only Output Characteristics Number of channels Resolution Max update rate Type of DAC FIFO buffer size Data transfers DMA modes AT E Series User Manual A 24 91 7 dB full scale input with gain to 10 70 dB max DC to 100 kHz 5 uV C 120 uV C 7 ppm C 2 voltage 16 bits 1 in 65 536 100 kS s Double buffered 2 048 samples DMA interrupts programmed I O Single transfer demand transfer National Instruments Corporation Appendix A Specifications for AT MIO 16XE 10 and AT Al 16XE 10 Transfer Characteristics Relative accuracy INL 0 5 LSB typ 1 LSB max PDN eite ease 1 LSB max Monotonicity 0 eee ee ceeeeeeseeeeeees 16 bits guaranteed Offset error After calibration 305 uV max Before calibration 20 mV max Gain error relative to internal reference After calibration 30 5 ppm max Before calibration
140. led capacitively coupled the PGIA needs a resistor between the positive input and AIGND If the source has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 kO to 1 MQ In this case you can tie the negative input directly to AIGND If the source has high output impedance you should balance the signal path as previously described using the same value resistor on both the positive and negative inputs you should be aware that there is some gain error from loading down the source 4 22 National Instruments Corporation Chapter 4 Signal Connections Single Ended Connection Considerations A single ended connection is one in which the AT E Series board analog input signal is referenced to a ground that can be shared with other input signals The input signal is tied to the positive input of the PGIA and the ground is tied to the negative input of the PGIA When every channel is configured for single ended input up to 16 analog input channels are available up to 64 channels on the AT MIO 64E 3 You can use single ended input connections for any input signal that meets the following conditions e The input signal is high level greater than 1 V e The leads connecting the signal to the AT E Series board are less than 10 ft 3 m e The input signal can share a common reference
141. llup and pulldown resistors is very large Actual value may range between 17 kQ and 100 kQ Table 4 5 shows the I O signal summary for the AT MIO 16XE 50 Table 4 5 1 0 Signal Summary AT MIO 16XE 50 Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias ACH lt 0 15 gt AI 20 GQ in 25 15 3 nA parallel with 100 pF AISENSE Al 20 GQ in 25 15 3 nA parallel with 100 pF AIGND AO DACOOUT AO 0 1 Short circuit 5at 10 5at 10 2 to ground V us DACIOUT AO 0 10 Short circuit 5 at 10 5 at 10 2 to ground V us National Instruments Corporation 4 13 AT E Series User Manual Chapter 4 Signal Connections Table 4 5 1 0 Signal Summary AT MIO 16XE 50 Continued Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias AOGND AO DGND DO VCC DO 0 12 Short circuit 1A to ground DIO lt 0 7 gt DIO Voc 25 13 at V 0 4 24at 0 4 11 50kQ pu SCANCLK DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu EXTSTROBE DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFIO TRIGI DIO Voc 25 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFI1 TRIG2 DIO Veg 05 3 5 at V 0 4 5 at 0 4 1 5 50 KQ pu PFI2
142. ly to the ground tie point on the AT E Series boards You can use this signal for a general analog ground tie point to your AT E Series board if necessary Connection of analog input signals to your AT E Series board depends on the configuration of the analog input channels you are using and the National Instruments Corporation 4 15 AT E Series User Manual Chapter 4 Signal Connections AT E Series User Manual type of input signal source With the different configurations you can use the PGIA in different ways Figure 4 4 shows a diagram of your AT E Series board PGIA Instrumentation Amplifier Vins O Measured Voltage Vin Vins Vin J Gain Figure 4 4 AT E Series PGIA The PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to your AT E Series board Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the board The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to the ground for the board Your AT E Series board A D converter ADC measures this output voltage when it performs A D conversions You must reference all signals to ground either at the source device or at the board If you have a floating source you should reference the signal to gr
143. manual xi conventions used in manual xii to xiii customer communication xiv National Instruments documentation xiii to xiv organization of manual xi to xii related documentation xiv dynamic characteristics analog input AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 4 to A 5 AT MIO 16E 10 and AT MIO 16DE 10 A 14 AT MIO 16XE 10 and AT AI 16XE 10 A 23 to A 24 AT MIO 16XE 50 A 32 analog output AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 7 AT MIO 16E 10 and AT MIO 16DE 10 A 17 AT MIO 16XE 10 A 25 AT MIO 16XE 50 A 33 to A 34 National Instruments Corporation Index E EEPROM storage of calibration constants 5 1 environment specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 11 AT MIO 16E 10 and AT MIO 16DE 10 A 20 AT MIO 16XE 10 and AT AI 16XE 10 A 29 AT MIO 16XE 50 A 36 environmental noise avoiding 4 56 equipment optional 1 6 EXTREF signal analog output reference connections 4 26 to 4 27 analog output reference selection 3 13 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 description table 4 5 EXTSTROBE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 timing connections 4 29 F field wiring considerations 4 56 floating signal sources description 4
144. mentation Amplifier Ground Referenced Signal s Source o co Input Multiplexers o Measured Common 4 NGNE AISENSE Voltage Mode Vom o Noise and Ground 4 N Potential JF Selected Channel in NRSE Configuration l O Connector Figure 4 9 Single Ended Input Connections for Ground Referenced Signal Common Mode Signal Rejection Considerations Figures 4 6 and 4 9 show connections for signal sources that are already referenced to some ground point with respect to the AT E Series board In these cases the PGIA can reject any voltage caused by ground potential differences between the signal source and the board In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the board The PGIA can reject common mode signals as long as V and V are both within 11 V of AIGND The AT MIO 16XE 50 has the additional restriction that V u V added to the gain times V i V i must be within 26 V of AIGND At gains of 10 and 100 this is roughly equivalent to restricting the two input voltages to within 8 V of AIGND National Instruments Corporation 4 25 AT E Series User Manual Chapter 4 Signal Connections Analog Output Signal Connections The analog output signals are DACOOUT DACIOUT EXTREF and AOGND iP Note DACOOUT and DACIOUT are not available on the AT AI 1
145. ming with NI DAQ function calls or using LabWindows CVI the NI DAQ User Manual for PC Compatibles is the best starting place 9 What version of NI DAQ must I have to program my AT E Series board You must have version 4 9 0 or higher for the AT MIO 16XE 10 and AT AI 16XE 10 version 4 8 0 or higher for the AT E Series User Manual C 2 National Instruments Corporation 10 11 12 13 National Instruments Corporation Appendix C Common Questions AT MIO 16E 1 and version 4 6 1 or higher for all other AT E Series boards For AT MIO 16E 10 and AT MIO 16DE 10 users you must have version 5 04 for Windows 3 1x or 5 1 for Windows 95 and Windows NT to use boards after and including board N Previous boards before N require NI DAQ 4 6 1 or higher What special calls must be made in DOS or LabWindows to use AT E Series boards To link in the AT E Series function calls you must call USE E Series or one of its subsets What is the best way to test my board without having to program the board If you are using Windows the NI DAQ Configuration Utility has a Test menu with some excellent tools for doing simple functional tests of the board such as analog input and output digital I O and counter timer tests Also the Test Configuration option will verify that the base address interrupt and DMA settings for the board are functioning properly I have several DAQ boards that use more total interrupt an
146. n RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for any AT E Series board sharing the RTSI bus These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals This signal connection scheme is shown in Figure 3 15 ZN RTSI Bus Connector NU Trigger RTSI Switch DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTRO SOURCE GPCTRO GATE GPCTRO OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1 SOURCE GPCTR1 GATE RTSI OSC 20 MHz Figure 3 15 RTSI Bus Signal Connection Refer to the Timing Connections section of Chapter 4 Signal Connections for a description of the signals shown in Figure 3 15 National Instruments Corporation 3 21 AT E Series User Manual Chapter Signal Connections This chapter describes how to make input and output signal connections to your AT E Series board via the board I O connector The I O connector for the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 has 68 pins that you can connect to 68 pin accessories with the SH6868 shielded cable or the R6868 ribbon cable With the SH6850 shielded cable or R6850 ribbon cable you can connect your board to 50 pin signal conditioning modules and terminal blocks The I O connector for the AT MIO 64E 3 and AT MIO 16DE 10 has 100 pins that you can con
147. n noise source in a PC data acquisition system is the video monitor Separate the monitor from the analog signals as much as possible The following recommendations apply for all signal connections to your AT E Series board e Separate AT E Series board signal lines from high current or high voltage lines These lines are capable of inducing currents in or voltages on the AT E Series board signal lines if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other e Do not run signal lines through conduits that also contain power lines e Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the application note Field Wiring and Noise Consideration for Analog Signals available from National Instruments 4 56 National Instruments Corporation Chapter Calibration This chapter discusses the calibration procedures for your AT E Series board If you are using the NI DAQ device driver that software includes calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments On the AT E Series boards thes
148. n on bias resistors Grounded Signal Source Examples Plug in instruments with nonisolated outputs NOT RECOMMENDED Single Ended Ground Referenced RSE Single Ended Nonreferenced NRSE AT E Series User Manual 4 18 6 2 Ground loop losses Vg are added to measured signal National Instruments Corporation Chapter 4 Signal Connections Differential Connection Considerations DIFF Input Configuration A differential connection is one in which the AT E Series board analog input signal has its own reference signal or signal return path These connections are available when the selected channel is configured in DIFF input mode The input signal is tied to the positive input of the PGIA and its reference signal or return is tied to the negative input of the PGIA When you configure a channel for differential input each signal uses two multiplexer inputs one for the signal and one for its reference signal Therefore with a differential configuration for every channel up to eight analog input channels are available up to 32 channels on the AT MIO 64E 3 You should use differential input connections for any channel that meets any of the following conditions e The input signal is low level less than 1 V e The leads connecting the signal to the AT E Series board are greater than 10 ft 3 m e The input signal requires a separate ground reference point or return
149. nalog output channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to Vyer at the analog output A bipolar configuration has a range of V ref to V ef at the analog output V efis the voltage reference used by the DACs in the analog output circuitry and can be either the 10 V onboard reference or an externally supplied reference between 10 and 10 V You do not need to configure both channels for the same range Selecting a bipolar range for a particular DAC means that any data written to that DAC will be interpreted as two s complement format In two s complement mode data values written to the analog output channel can be either positive or negative If you select unipolar range data is interpreted in straight binary format In straight binary mode data values written to the analog output channel range must be positive AT MIO 16XE 10 You can configure each analog output channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to 10 V at the analog output A bipolar configuration has a range of 10 to 10 V at the analog output You do not need to configure both channels for the same range Analog Output Reglitch Selection AT E Series User Manual AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 only In normal operation a DAC output will glitch whenever it is updated with a new value The glitch energy differs from code to code and appears as distortion in
150. nals between several functions on as many as five DAQ boards in your PC The AT E Series boards can interface to an SCXI system so that you can acquire over 3 000 analog signals from thermocouples RTDs strain gauges voltage sources and current sources You can also acquire or generate digital signals for communication and control SCXI is the instrumentation front end for plug in DAQ boards Detailed specifications of the AT E Series boards are in Appendix A Specifications What You Need to Get Started To set up and use your AT E Series board you will need the following 0 One of the following boards AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MIO 16DE 10 AT MIO 16XE 10 AT AI 16XE 10 AT MIO 16XE 50 Q ATE Series User Manual C One of the following software packages and documentation BridgeVIEW ComponentWorks LabVIEW for Windows LabWindows CVI for Windows LookOut Measure NI DAQ for PC Compatibles VirtualBench QC Your computer AT E Series User Manual 1 2 National Instruments Corporation Chapter 1 Introduction Software Programming Choices There are several options to choose from when programming your National Instruments DAQ and SCXI hardware You can use National Instruments application software NI DAQ or register level programming National Instruments Application Software ComponentWorks contains tools for data acquisition and instrument control built on NI DAQ driver softw
151. nd the acquisition will stop This mode acquires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence This is true even if the acquisition is being externally triggered by another PFI The TRIG2 signal is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 19 and 4 20 show the input and output timing requirements for the TRIG2 signal Rising edge polarity 1 i Falling edge polarity tw 10 ns minimum Figure 4 19 TRIG2 Input Signal Timing ty 50 100 ns Figure 4 20 TRIG2 Output Signal Timing National Instruments Corporation 4 35 AT E Series User Manual Chapter 4 Signal Connections AT E Series User Manual STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 13 and 4 14 for the relationship of STARTSCAN to the data acquisition sequence As an input the STARTSCAN signal is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter is started if you select internally triggered CONVERT A
152. nect to 100 pin accessories with the SH100100 shielded cable With the SH1006868 shielded cable you can connect your board to 68 pin accessories and with the R1005050 ribbon cable you can connect your board to 50 pin accessories 1 0 Connector Figure 4 1 shows the pin assignments for the 68 pin I O connector on the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 Figure 4 2 shows the pin assignments for the 100 pin I O connector on the AT MIO 64E 3 Figure 4 3 shows the pin assignments for the 100 pin I O connector on the AT MIO 16DE 10 Refer to Appendix B Optional Cable Connector Descriptions for the pin assignments for the 50 pin connectors A signal description follows the connector pinouts N Caution Connections that exceed any of the maximum ratings of input or output signals on the AT E Series boards can damage the AT E Series board and the PC Maximum input ratings for each signal are given in Tables 4 2 through 4 5 in the Protection column National Instruments is NOT liable for any damages resulting from such signal connections National Instruments Corporation 4 1 AT E Series User Manual Chapter 4 Signal Connections AcH8 34 68 ACHO ACH1 33 67 AIGND AIGND 32 66 ACH9 ACH10 31 65 ACH2 ACH3 30 64 AIGND AIGND 29 63 ACH11 ACH4 28 62 AISENSE AIGND 27 61 ACH12 ACH13 26 60 ACH5 ACH6 25 59 AIGND AIGND 24 58 ACH14 ACH15 23157 ACH7 DACOOUT 22
153. nections are designed to enable the AT E Series board to both control and be controlled by other boards and circuits There are a total of 13 timing signals internal to the DAQ STC that can be controlled by an external source These timing signals can also be controlled by signals generated internally to the DAQ STC and these selections are fully software configurable For example the signal routing multiplexer for controlling the CONVERT signal is shown in Figure 3 14 RTSI Trigger lt 0 6 gt CONVERT PFI lt 0 9 gt lt Sample Interval Counter TC 3 9 GPCTRO OUT best Figure 3 14 CONVERT Signal Routing National Instruments Corporation 3 19 AT E Series User Manual Chapter 3 Hardware Overview This figure shows that CONVERT can be generated from a number of sources including the external signals RTSI lt 0 6 gt and PFI lt 0 9 gt and the internal signals Sample Interval Counter TC and GPCTRO OUT Many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTI Triggers section later in this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections Programmable Function Inputs The 10 PFIs are connected to the signal routing multiplexer for each timing signal and software can select one of the PFIs as the external source for a given timing signal It is important to note that any of
154. ng eene 4 55 68 Pin MIO Connector Pin Assignments seeeee B 2 68 Pin DIO Connector Pin Assignments esses B 3 68 Pin Extended Analog Input Connector Pin Assignments B 4 50 Pin MIO Connector Pin Assignments eee B 5 50 Pin DIO Connector Pin Assignments esee B 6 50 Pin Extended Analog Input Connector Pin Assignments B 7 PC AT I O Address Mapin onret eesriie erete erik iyt 2 4 PC AT Interrupt Assignment Map seen 2 6 PC AT 16 bit DMA Channel Assignment Map eee 2 7 Available Input Configurations for the AT E Series 3 7 Actual Range and Measurement Precision esee 3 8 Actual Range and Measurement Precision AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 see 3 9 I O Signal Summary AT E Series sese 4 5 I O Signal Summary AT MIO 16E 1 AT MIO 16E 2 and AI MIQ 64E 3 i ite etre ue ie iet eee peres e Senses 4 8 T O Signal Summary AT MIO 16E 10 and AT MIO 16DE 10 4 10 T O Signal Summary AT MIO 16XE 10 and AT AI 16XE 10 4 12 T O Signal Summary AT MIO 16XE 50 sseseeeene 4 13 Port C Signal Assignments essent enne 4 51 Port C Signal Descriptions esses enne 4 52 X National Instruments Corporation This manual describes the electr
155. ng externally generated by another PFI This output is set to tri state at startup Figure 4 34 shows the timing requirements for the GPCTR1I SOURCE signal L1 tp 2 50 ns minimum ty 10 ns minimum Figure 4 34 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source GPCTR1_GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform such National Instruments Corporation 4 47 AT E Series User Manual Chapter 4 Signal Connections actions as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTR1_GATE signal monitors the actual gate signal connected to general purpose counter 1 This is true even if the gate is being externally generated by another PFI This output is set to tri state at startup Figure 4 35 shows the timing requirements for the GPCTR1_GATE signal
156. o A 28 digital trigger A 28 RTSI A 28 AT MIO 16XE 50 digital trigger A 35 RTSI A 35 troubleshooting See questions about AT E series boards U UISOURCE signal 4 44 unipolar input AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 3 7 to 3 8 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 3 8 to 3 10 mixing bipolar and unipolar channels note 3 9 unipolar output 3 14 unpacking AT E series boards 1 7 UPDATE signal timing connections 4 42 to 4 43 V VCC signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 National Instruments Corporation voltage output AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 7 AT MIO 16E 10 and AT MIO 16DE 10 A 16 to A 17 AT MIO 16XE 10 A 25 AT MIO 16XE 50 A 33 W waveform generation timing connections 4 40 to 4 44 UISOURCE signal 4 44 UPDATE signal 4 42 to 4 43 WFTRIG signal 4 41 WFTRIG signal timing connections 4 41 wiring considerations 4 56 WR signal table 4 52 National Instruments Corporation l 15 Index AT E Series User Manual
157. oard Digital triggering is supported by hardware on every AT E Series MIO board In addition the AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 and AT AI 16XE 10 support analog triggering in hardware What added functionality does the DAQ STC make possible in contrast to the Am9513 The DAQ STC incorporates much more than just 10 Am9513 style counters within one chip In fact the DAQ STC has the complexity C 5 AT E Series User Manual Appendix C Common Questions 20 21 22 AT E Series User Manual of more than 24 chips The DAQ STC makes possible PFI lines analog triggering selectable logic level and frequency shift keying The DAQ STC also makes buffered operations possible such as direct up down control single or pulse train generation equivalent time sampling buffered period and buffered semiperiod measurement What is the difference in timebases between the Am9513 counter timer and the DAQ STC The DAQ STC based MIO boards have a 20 MHz timebase The Am9513 based MIO boards have a 1 MHz or 5 MHz timebase The counter timer examples supplied with NI DAQ are not compatible with an AT E Series board Where can I find examples to illustrate the use of the DAQ STC as a general purpose counter timer If you are using the NI DAQ language interface and a C compiler under DOS a new subdirectory called GPCTR which lies beneath the examples directory contains 16 examples of the most common uses of
158. other events outside reasonable control Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation BridgeView ComponentWorks CVI DAQCard DAQPad DAQ PnP DAQ STC LabVIEW LookOut Measure NI DAQ NI PGIA RTSI and SCXI VirtualBench are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death
159. ound by using the RSE input mode or the DIFF input configuration with bias resistors See the Differential Connections for Nonreferenced or Floating Signal Sources section later in this chapter If you have a grounded source you should not reference the signal to AIGND You can avoid this reference by using DIFF or NRSE input configurations 4 16 National Instruments Corporation Chapter 4 Signal Connections Types of Signal Sources When configuring the input channels and making signal connections you must first determine whether the signal sources are floating or ground referenced The following sections describe these two types of signals Floating Signal Sources A floating signal source is one that is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers An instrument or device that has an isolated output is a floating signal source You must tie the ground reference of a floating signal to your AT E Series board analog input ground to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is one that is connected in some way to the building system
160. ows the block diagram for the AT MIO 64E 3 Voltage Calibration DACs 12 Bit Selection Sampling ADC Data Switches ND FIFO Transceivers Converter Calibration Dither gt Mux Circuitry EEPROM Configuration I Memory Al Control E Trigger Level 2 S ar space Analog IRQ gt oO ka gt O Trigger DMA 8 c m Trigger Circuitry f c 9 Analog Input i DM fS i 1 1 c PFI Trigger Trigger Timing Control 1 cu Analog teepROM DMA O CIEN TESE LL equest_ Input 1 Control interi c Como Control Interface Oo s Counter Bus DAG STC Pug Oo Timing Timing O DAQ STC Interface Bus DAQ PnP and O ree abre mR ee BM ene at OS Interface Play Analog Output 1 RTSI Bus Analog 8255 mus o Digital VO 8 Digital 1 0 Timing Control Interface Qutput DIO Interface Calibration DACs AO Control DAC FIFO Data 16 C AT E Series User Manual Figure 3 2 AT MIO 64E 3 Block Diagram 3 2 National Instruments Corporation Chapter 3 Hardware Overview Figure 3 3 shows the block diagram for the AT MIO 16E 10 and AT MIO 16DE 10 Voltage Calibration REF DACs Mux Mode esis Selecti election A D Switches Converter Data Transceivers
161. ption table 4 7 waveform generation timing connections 4 48 GPCTR1_SOURCE signal 4 47 GPCTR1_UP_DOWN signal 4 49 to 4 50 ground referenced signal sources description 4 17 differential connections 4 20 single ended connections NRSE configuration 4 24 H hardware installation 2 2 hardware overview analog input 3 6 to 3 13 considerations for selecting input ranges 3 10 dither 3 10 to 3 12 input modes 3 6 to 3 7 input polarity and range 3 7 to 3 10 multiple channel scanning considerations 3 12 to 3 13 analog output 3 13 to 3 15 output polarity selection 3 14 reference selection 3 13 reglitch selection 3 14 analog trigger 3 15 to 3 18 block diagram 3 16 National Instruments Corporation Index AT AI 16XE 10 block diagram 3 5 NRSE table 3 7 AT MIO 16E 1 and AT MIO 16E 2 RSE table 3 7 block diagram 3 1 common mode signal rejection 4 25 AT MIO 16E 10 and AT MIO 16DE 10 differential connections block diagram 3 3 DIFF input configuration 4 19 AT MIO 16XE 10 block diagram 3 4 floating signal sources 4 21 to 4 22 AT MIO 16XE 50 block diagram 3 6 ground referenced signal sources AT MIO 64E 3 block diagram 3 2 4 20 digital I O 3 18 nonreferenced signal sources 4 21 to timing signal routing 3 19 to 3 21 4 22 board and RTSI clocks 3 20 single ended connections 4 23 programmable function inputs 3 20 floating signal sources RSE RTSI triggers 3 21 configuration 4 24 grounded signal sources
162. put 4 26 to 4 27 digital I O 4 27 to 4 28 field wiring considerations 4 56 I O connector 4 1 to 4 14 exceeding maximum ratings caution 4 1 4 15 4 28 I O signal summary table AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 4 8 to 4 10 National Instruments Corporation AT MIO 16E 10 and AT MIO 16DE 10 4 10 to 4 11 AT MIO 16XE 10 and AT AI 16XE 10 4 12 to 4 13 AT MIO 16XE 50 4 13 to 4 14 signal descriptions table 4 5 to 4 8 input configurations 4 17 common mode signal rejection 4 25 differential connections DIFF input configuration 4 19 floating signal sources 4 21 to 4 22 ground referenced signal sources 4 20 nonreferenced signal sources 4 2 to 4 22 single ended connections 4 23 to 4 25 floating signal sources RSE configuration 4 24 grounded signal sources NRSE configuration 4 24 power connections 4 29 timing connections 4 29 to 4 55 data acquisition timing connections 4 31 to 4 40 AIGATE signal 4 39 to 4 40 CONVERT signal 4 38 to 4 39 EXTSTROBE signal 4 33 SCANCLK signal 4 32 SISOURCE signal 4 40 STARTSCAN signal 4 36 to 4 37 TRIGI signal 4 33 to 4 34 TRIG signal 4 34 general purpose timing signal connections 4 44 to 4 55 FREQ OUT signal 4 50 GPCTRO GATE signal 4 45 to 4 46 National Instruments Corporation I 11 Index GPCTRO OUT signal 4 46 GPCTRO_SOURCE signal 4 44 to 4 45 GPCTRO_UP_DOWN signal 4 46 GPCTRI GATE signal 4 47 to 4 48 GPCTRI OUT signal
163. reference 0 01 of reading max 2 0 of reading max 0 05 of reading max AT E Series User Manual Specifications for AT MIO 16E 10 and AT MIO 16DE 10 AT E Series User Manual Amplifier Characteristics Input impedance Normal powered on 100 GQ in parallel with 50 pF Powered off sssssss 3 KQ min Ove rload ees 3 KQ min Input bias current esses 200 pA Input offset current eee 100 pA CMRR all input ranges 90 dB DC to 60 Hz Dynamic Characteristics Bandwidth Small signal 3 dB 150 kHz Large signal 1 THD 120 kHz Settling time for full scale step 10 us max to 0 5 LSB accuracy System noise not including quantization Gain Noise Dither Off Noise Dither On 0 5 to 10 0 07 LSB rms 0 5 20 0 12 LSB rms 0 5 50 0 25 LSB rms 0 6 100 0 5 LSB rms 0 7 Crosstalk E E E 70 dB DC to 100 kHz A 14 National Instruments Corporation Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Stability Offset temperature coefficient Presa tei ee eee 15 uV C Postgain is eet 240 uV C Gain temperature coefficient 20 ppm C Analog Output Output Characteristics Number of channels 2 voltage Resolution sseeeseseeeeeee 12 bits 1 in 4 096 Max update rate ee
164. rent analog input channel signal analog to digital A D converter analog input gate signal analog input ground signal analog input sense signal analog input sense 2 signal American National Standards Institute analog output ground signal application specific integrated circuit basic input output system or built in operating system Celsius calibration DAC complementary metal oxide semiconductor common mode rejection ratio convert signal G 2 National Instruments Corporation D D A DAC DACOOUT DACIOUT DAQ DC DGND DIFF DIO DMA DNL E EEPROM EISA EXTREF EXTSTROBE F FIFO FREQ OUT ft National Instruments Corporation G 3 Glossary digital to analog D A converter analog channel 0 output signal analog channel 1 output signal data acquisition direct current digital ground signal differential mode digital input output direct memory access differential nonlinearity electrically erasable programmable read only memory Extended Industry Standard Architecture external reference signal external strobe signal first in first out frequency output signal feet AT E Series User Manual Glossary G GPCTRO GATE GPCTR1 GATE GPCTRO OUT GPCTRI OUT GPCTRO SOURCE GPCTRI SOURCE H h hex Hz I O Ion Io ISA L LASTCHAN LSB AT E Series User Manual general purpose counter 0 gate signal general purpose counter 1 gate signal general purpose
165. rollers NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using conventional programming languages LabVIEW or LabWindows CVI your application uses the NI DAQ driver software as illustrated in Figure 1 1 1 4 National Instruments Corporation Chapter 1 Introduction Conventional Programming LabVIEW LabWindows CVI Environment PC Macintosh or PC or PC Macintosh or Sun SPARCstation Sun SPARCstation Sun SPARCstation NI DAQ Driver Software DAQ Personal or 4r Computer SCXI Hardware ko Workstation Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware You can use your AT E Series board together with other PC AT EISA DAQCard and DAQPad Series DAQ and SCXI hardware with NI DAQ software for PC compatibles Register Level Programming The final option for programming any National Instruments DAQ hardware is to write register level software Writing register level programming software can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer consider using NI DAQ LabVIEW or LabWindows CVI to program your National Instruments DAQ hardware Using the NI DAQ LabVIEW or LabWindows CVI software is as easy and as flexible as
166. ruments Corporation I 7 AT E Series User Manual Index manual See documentation mode 1 input Port C signal assignments table 4 51 timing specifications 4 53 mode 1 output Port C signal assignments table 4 51 timing specifications 4 54 mode 2 bidirectional transfers Port C signal assignments table 4 51 timing specifications 4 55 multiple channel scanning 3 12 to 3 13 NI DAQ driver software 1 4 to 1 5 noise avoiding 4 56 NRSE nonreferenced single ended input description table 3 7 differential connections 4 21 to 4 22 single ended connections NRSE configuration 4 24 0 OBF signal table 4 52 operation of AT E series boards See hardware overview optional equipment 1 6 output characteristics AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 5 to A 6 AT MIO 16E 10 and AT MIO 16DE 10 A 15 AT MIO 16XE 10 A 24 AT MIO 16XE 50 A 32 to A 33 AT E Series User Manual l 8 P PA lt 0 7 gt signal AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 description table 4 6 PB 0 7 signal AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 description table 4 6 PC lt 0 7 gt signal table 4 6 PFIO TRIGI signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 PFI1 TRIG2 signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E
167. s an output the STARTSCAN signal reflects the actual start pulse that initiates a scan This is true even if the starts are being externally triggered by another PFI You have two output options The first is an active high pulse with a pulse width of 50 to 100 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last conversion in the scan which indicates a scan in progress STARTSCAN will be deserted toft after the last conversion in the scan is initiated This output is set to tri state at startup Figures 4 21 and 4 22 show the input and output timing requirements for the STARTSCAN signal Rising edge polarity Falling edge polarity ty 2 10 ns minimum Figure 4 21 STARTSCAN Input Signal Timing 4 36 National Instruments Corporation Chapter 4 Signal Connections i ty i lt gt STARTSCAN LL i tw 50 100 ns i a Start of Scan Start Pulse CONVERT STARTSCAN ____ t top 10 ns minimum tof i b Scan in Progress Two Conversions per Scan Figure 4 22 STARTSCAN Output Signal Timing The CONVERT pulses are masked off until the board generates the STARTSCAN signal If you are using internally generated conversions the first CONVERT will appear when the onboard sample interval counter reaches zero If you select an external CONVERT the first e
168. s connected to ACH lt 0 15 gt are routed to the positive input of the board PGIA In differential mode signals connected to ACH lt 0 7 gt are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 gt are routed to the negative input of the PGIA AT MIO 64E 3 The analog input signals are ACH lt 0 63 gt AISENSE AISENSE2 and AIGND The ACH lt 0 63 gt signals are tied to the 64 analog input channels of the AT MIO 64E 3 In single ended mode signals connected to ACH lt 0 63 gt are routed to the positive input of the AT MIO 64E 3 PGIA In differential mode signals connected to ACH O 7 16 23 32 39 48 55 gt are routed to the positive input of the PGIA and signals connected to ACH 8 15 24 31 40 47 56 63 gt are routed to the negative input of the PGIA Exceeding the differential and common mode input ranges distorts your input signals Exceeding the maximum input voltage rating can damage the AT E Series board and the PC National Instruments is NOT liable for any damages resulting from such signal connections The maximum input voltage ratings are listed in Tables 4 2 through 4 5 in the Protection column In NRSE mode the AISENSE and AISENSE2 signals are connected internally to the negative input of the AT E Series board PGIA when their corresponding channels are selected In DIFF and RSE modes these signals are left unconnected AIGND is an analog input common signal that is routed direct
169. scan multiple channels at the same maximum rate as their single channel rate however you should pay careful attention to the settling times for each of the boards The settling time for most of the AT E Series boards is independent of the selected gain even at the maximum sampling rate The settling time for the high channel count and very high speed boards is gain dependent which can affect the useful sampling rate for a given gain No extra settling time is necessary between channels as long as the gain is constant and source impedances are low Refer to Appendix A Specifications for a complete listing of settling times for each of the AT E Series boards When scanning among channels at various gains the settling times may increase When the PGIA switches to a higher gain the signal on the previous channel may be well outside the new smaller range For instance suppose a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1 and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1 When the multiplexer switches to channel 1 and the PGIA switches to a gain of 100 the new full scale range is 100 mV if the ADC is in unipolar mode The approximately 4 V step from 4 V to 1 mV is 4 000 of the new full scale range For a 12 bit board to settle within 0 01296 120 ppm or 1 2 LSB of the 100 mV full scale range on channel 1 the input circuitry has to settle to within 0 00
170. scription table 4 5 amplifier characteristics AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 3 AT MIO 16E 10 and AT MIO 16DE 10 A 14 AT MIO 16XE 10 and AT AI 16XE 10 A 23 AT MIO 16XE 50 A 31 to A 32 analog input 3 6 to 3 13 common questions about C 4 to C 5 considerations for selecting input ranges 3 10 dither 3 10 to 3 12 input modes 3 6 to 3 7 input polarity and range 3 7 to 3 10 l 1 AT E Series User Manual Index multiple channel scanning considerations 3 12 to 3 13 signal connections 4 15 to 4 16 analog input specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 1 to A 5 amplifier characteristics A 3 dynamic characteristics A 4 to A 5 input characteristics A 1 to A 3 stability A 5 transfer characteristics A 3 AT MIO 16E 10 and AT MIO 16DE 10 amplifier characteristics A 14 dynamic characteristics A 14 input characteristics A 12 to A 13 stability A 15 transfer characteristics A 13 AT MIO 16XE 10 and AT AI 16XE 10 amplifier characteristics A 23 dynamic characteristics A 23 to A 24 input characteristics A 21 to A 22 stability A 24 transfer characteristics A 22 AT MIO 16XE 50 amplifier characteristics A 31 to A 32 dynamic characteristics A 32 input characteristics A 30 to A 31 stability A 32 transfer characteristics A 31 analog output 3 13 to 3 15 common questions about C 4 to C 5 output polarity selection 3 14 reference selection 3 13 to 3 14 reglitch selection 3 14 to 3
171. should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Contents About This Manual Organization of This Manual itr eth Ee uec discat xi Conventions Used in This Manual sese ener xii National Instruments Documentation esssessssseseseeeeee eee enne nnns xiii Related Documentation cccccessccessceceseceseeceesseceseaseccseceeessueecseneeeceeeecesnesecssueeenenaes XIV Customer Communication esses esent nnne nein nennen xiv Chapter 1 Introduction About the AT E Series sie sesh niece riter Er di a ee 1 1 What You Need to Get Started sess esee 1 2 Software Programming Choices 20 00 eects ceseeeeceeceeeeeeceeeeeneeseecaecaaecaecsaeeaesnsenseeneeees 1 3 National Instruments Application Software essen 1 3 NI DAQ Driver Software sssssssessseseeseeeeee eene ener enn 1 4 Register Level Programming sseeseseeeeeeeeeeeneen eee enne 1 5 Optional Equipment 2 iret rete eere re RR RE ERR e Eee re eene ROE OS 1 6 Custom Cabling 2 05 26 ei ih at a ie Diete tace D etre steers ne e 1 6 Unpacking abet Ee PROC Oe a ee eR a 1 7 Chapter 2 Installation and Configuration Softw
172. t Voc 0 4 Sat 0 4 1 5 50 kQ pu EXTSTROBE DO 3 5 at Vis 0 4 5at0 4 1 5 50 KQ pu PFIO TRIGI DIO Veg 0 5 3 5 at Ving 0 4 5 at0 4 15 4 75kQ pu PFI1 TRIG2 DIO Vie 0 5 3 5 at Voc 0 4 5at 0 4 1 5 50 kO pu PFI2 CONVERT DIO Nac 40 5 3 5 at Vec 0 4 5at0 4 1 5 50 KQ pu PFI3 GPCTR1_SOURCE DIO Voc 0 5 3 5 at oo 0 4 5at0 4 1 5 50 KQ pu PFI4 GPCTR1_GATE DIO Voe 0 5 3 5 at Voc 0 4 Sat 0 4 1 5 50 kO pu GPCTR1_OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu AT E Series User Manual 4 12 National Instruments Corporation Chapter 4 Signal Connections Table 4 4 1 0 Signal Summary AT MIO 16XE 10 and AT AI 16XE 10 Continued Impedance Protection Sink Rise Input Volts Source mAat Time Signal Name Drive Output On Off mA at V V ns Bias PFIS UPDATE DIO Vec 195 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFI6 WFTRIG DIO Voc 105 3 5 at Voc 0 4 5 at0 4 1 5 50 KQ pu PFI7 STARTSCAN DIO Voc 105 3 5 at Voc 0 4 5 at0 4 1 5 50 KQ pu PFI8 GPCTRO_SOURCE DIO Vec 195 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFI9 GPCTRO GATE DIO Voc 05 3 5 at Voc 0 4 5 at0 4 1 5 50 KQ pu GPCTRO OUT DO 3 5 at Voc 0 4 5 at0 4 1 5 50 KQ pu FREQ OUT DO 3 5at V 0 4 5at0 4 1 5 50 KQ pu AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output The tolerance on the 50 kQ pu
173. tal I O Ports A B and C 4 51 Mode 1 Input Timing ie nseoee eet eg 4 53 Mode 1 Output Timing essent 4 54 Mode 2 Bidirectional Timing eeeeeeeeeeeeree 4 55 Field Wiring Considerations eee ener ene 4 56 Chapter 5 Calibration Loading Calibration Constant eese enne ener enne 5 1 Self Calibration uoo eee stent Eee ette e Seton c ieee 5 2 External Calibration retener tege eme vie tenete 5 2 Other Considerations teet tre ie e Rete E EREE A ESR 5 3 National Instruments Corporation Vii AT E Series User Manual Contents Appendix A Specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 sese A 1 AT MIO 16E 10 and AT MIO 16DE 10 esses A 12 AT MIO 16XE 10 and AT AI 16XE 10 enne A 21 AT MIO I6XE 50 bre I UR a en occa ce ee eoe eite deed A 30 Appendix B Optional Cable Connector Descriptions Appendix C Common Questions Appendix D Customer Communication Glossary Index Figures Figure 1 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 AT E Series User Manual The Relationship between the Programming Environment NI DAQ and Your Hardware ide eed ete get de 1 5 AT MIO 16E 1 and AT MIO 16E 2 Block Diagram
174. te boundary Therefore valid addresses include 100 120 140 3CO 3E0 hex This selection is software configured and does not require you to manually change any settings on the board National Instruments Corporation 2 3 AT E Series User Manual Chapter 2 Installation and Configuration DMA Channel Selection The AT E Series boards can achieve high transfer rates by using up to three 16 bit DMA channels You can use these DMA channels for data transfers with the analog input analog output and general purpose counter sections of the board The AT E Series boards can use only 16 bit DMA channels which correspond to channels 5 6 and 7 in an ISA computer and channels 0 1 2 3 5 6 and 7 in an EISA computer These selections are all software configured and do not require you to manually change any settings on the board Interrupt Channel Selection The AT E Series boards can increase bus efficiency by using an interrupt channel You can use an interrupt channel for event notification without the use of polling techniques AT E Series boards can use interrupt channels 3 4 5 7 10 11 12 and 15 These selections are all software configured and do not require you to manually change any settings on the board The following tables provide information concerning possible conflicts when configuring your AT E Series board Table 2 1 PC AT I O Address Map I O Address Range Hex Device 100 to 1EF
175. to 3BF Monochrome Display Parallel Printer Adapter 0 3C0 to 3CF Enhanced Graphics Adapter VGA 3D0 to 3DF Color Graphics Monitor Adapter VGA 3E0 to 3EF 3F0 to 3F7 Diskette Controller 3F8 to 3FF Serial Port 1 COMI A79 Reserved for Plug and Play operation Table 2 2 PC AT Interrupt Assignment Map IRQ Device 15 Available 14 Fixed Disk Controller 13 Coprocessor 12 AT DIO 32F default 11 AT DIO 32F default 10 AT MIO 16 default 9 PC Network default PC Network Alternate default 8 Real Time Clock 7 Parallel Port 1 LPT1 6 Diskette Drive Controller Fixed Disk and Diskette Drive Controller 2 6 National Instruments Corporation Chapter 2 Installation and Configuration Table 2 2 PC AT Interrupt Assignment Map Continued IRQ Device 5 Parallel Port 2 LPT2 PC DIO 24 default Lab PC PC default 4 Serial Port 1 COM1 BSC BSC Alternate 3 Serial Port 2 COM2 BSC BSC Alternate Cluster primary PC Network PC Network Alternate WD EtherCard default 3Com EtherLink default 2 IRQ 8 15 Chain from interrupt controller 2 1 Keyboard Controller Output Buffer Full 0 Timer Channel 0 Output Table 2 3 PC AT 16 bit DMA Channel Assignment Map Channel Device 7 AT MIO 16 series default 6 AT MIO 16 series default AT DIO 32F default 5 AT DIO 32F default 4 Cascade for DMA Controller
176. tput high voltage 4 35 V oy 13 mA PA lt 0 7 gt PB lt 0 7 gt PC lt 0 7 gt AT MIO 16DE 10 only Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vi 0 V 60 pA Input high current Vin 5 V 10 uA Output low voltage 0 4 V oL 2 5 mA Output high voltage 3 9 V oy 2 5 mA Handshaking AT MIO 16DE 10 only 3 wire Power on state Data transfers AT MIO 16E 10 AT MIO 16DE 10 Number of channels 4 18 Programmed I O Interrupts programmed I O 2 up down counter timers frequency scaler National Instruments Corporation Triggers Calibration Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Resolution Counter timers eeeeeee 24 bits Frequency scalers 4 bits Compatibility ee ceeeceeeeeeeeees TTL CMOS Base clocks available Counter timers 0 0 0 0 eee 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns in edge detect mode Min gate pulse duration 10 ns in edge detect mode Data transfers eeeee DMA interrupts programmed I O DMA modes
177. ualBench software will greatly reduce the development time for your data acquisition and control application National Instruments Corporation 1 8 AT E Series User Manual Chapter 1 Introduction NI DAQ Driver Software AT E Series User Manual The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ is not packaged with signal conditioning or accessory products NI DAQ has an extensive library of functions that you can call from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation timed D A conversion digital I O counter timer operations SCXI RTSI calibration messaging and acquiring data to extended memory NI DAQ has both high level DAQ I O functions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ device NI DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak performance NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA cont
178. uebec 514 694 8521 514 694 4399 Denmark 45 76 26 00 45 76 26 02 Finland 09 725 725 11 09 725 725 55 France 01 48 14 24 24 01 48 14 24 14 Germany 089 741 31 30 089 714 60 35 Hong Kong 2645 3186 2686 8505 Israel 03 5734815 03 5734816 Italy 02 413091 02 41309215 Japan 03 5472 2970 03 5472 2977 Korea 02 596 7456 02 596 7455 Mexico 5 520 2635 5 520 3282 Netherlands 0348 433466 0348 430673 Norway 32 84 84 00 32 84 86 00 Singapore 2265886 2265887 Spain 91 640 0085 91 640 0533 Sweden 08 730 49 70 08 730 43 70 Switzerland 056 200 51 51 056 200 51 55 Taiwan 02 377 1200 02 737 4644 United Kingdom 01635 523545 01635 523154 United States 512 795 8248 512 794 5678 Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system include version number Clock speed MHz RAM MB Display adapter Mouse yes no Other adapters installed H
179. ult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or
180. with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 23 and 4 24 show the input and output timing requirements for the CONVERT signal Rising edge polarity Falling edge polarity ty 7 10 ns minimum Figure 4 23 CONVERT Input Signal Timing 4 38 National Instruments Corporation Chapter 4 Signal Connections gt I i tw 50 100ns i I I Figure 4 24 CONVERT Output Signal Timing The ADC switches to hold mode within 60 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next Separate the CONVERT pulses by at least one conversion period The sample interval counter on the AT E Series board normally generates the CONVERT signal unless you select some external source The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished It then reloads itself in readiness for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a data acquisition sequence Scans occurring within a data acquisition sequence may be gated by either the hardware AIGATE signal or software command register gate AIGATE Signal Any PFI pin can externally input the AIGATE signal which is not available as an output on the I O connector
181. x 1F0 to 1F8 IBM PC AT Fixed Disk 200 to 20F PC and PC AT Game Controller reserved 210 to 213 PC DIO 24 default 218 to 21F 220 to 23F Previous generation of AT MIO boards default 240 to 25F AT DIO 32F default 260 to 27F Lab PC PC default 278 to 28F AT Parallel Printer Port 2 LPT2 AT E Series User Manual 2 4 National Instruments Corporation Chapter 2 Installation and Configuration Table 2 1 PC AT I O Address Map Continued I O Address Range Hex Device 279 Reserved for Plug and Play operation 280 to 29F WD EtherCard default 2A0 to 2BF 2E2 to 2F7 2F8 to 2FF PC AT Serial Port 2 COM2 300 to 30F 3Com EtherLink default 310 to 31F 320 to 32F ICM PC XT Fixed Disk Controller 330 to 35F 360 to 363 PC Network low address 364 to 367 Reserved 368 to 36B PC Network high address 36C to 36F Reserved 370 to 366 PC AT Parallel Printer Port 1 LPT1 380 to 38C SDLC Communications 380 to 389 Bisynchronous BSC Communications alternate 390 to 393 Cluster Adapter 0 394 to 39F 3A0 to 3A9 BSC Communications primary 3AA to 3AF National Instruments Corporation 2 5 AT E Series User Manual Chapter 2 Installation and Configuration AT E Series User Manual Table 2 1 PC AT I O Address Map Continued I O Address Range Hex Device 3B0
182. xternal pulse after STARTSCAN will generate a conversion The STARTSCAN pulses should be separated by at least one scan period A counter on your AT E Series board internally generates the STARTSCAN signal unless you select some external source This counter is started by the TRIGI signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a data acquisition sequence Scans occurring within a data acquisition sequence may be gated by either the hardware AIGATE signal or software command register gate National Instruments Corporation 4 37 AT E Series User Manual Chapter 4 Signal Connections AT E Series User Manual CONVERT Signal Any PFI pin can externally input the CONVERT signal which is available as an output on the PFI2 CONVERT pin Refer to Figures 4 13 and 4 14 for the relationship of CONVERT to the data acquisition sequence As an input the CONVERT signal is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVERT signal initiates an A D conversion As an output the CONVERT signal reflects the actual convert pulse that is connected to the ADC This is true even if the conversions are being externally generated by another PFI The output is an active low pulse

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