Technical Data Sheet
Contents
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3. 2 8 Schematic Diagram of the Debug LED Interface 2 11 Block Diagram of the Parallel JTAG 2 13 Schematic Diagram of the User Interrupt Interface 2 15 Schematic Diagram of the Reset Interface 2 16 Schematic Diagram f th Power Supply aasan asas aaa waaka was 2 17 PWM Group A Interface and LEDS 2 22 C N THA o rem 2 23 2 25 dod o doi b ERE e dare d 2 26 Typical Analog Inu BO Lad ae nau 2 33 List of Figures Rev 2 Freescale Semiconductor iii Preliminary MC56F8367EVM User Manual Rev 2 Freescale Semiconductor Preliminary LIST OF TABLES 1 1 56F8367EVM Default Jumper 1 4 2 1 SCIT A0 mper OPUONS anew oes TTE 2 7 2 2 RS 232 Serial Cosnector Description iiu es dad cao Shae KROES 2 8 2 3 Operating Mode Selection 2 9 2 4 EMI Operating Mode Selection 2 9 2 5 EMI Operating Mode ida acc dens ed sasa 2 10 2 6 LED oid add dos Rd 2 10 2 7 JTAG Connector Description 2 12 2 8 Parallel JTAG Interface Disable
4. SHVMILJOS Nos ET 07 CIN anyo 880 D E lt on os lt lt 1 lt lt E lt k 25 vor stor ONI ved NorrngHsnd m zx sog Ag e ON LOOH n A ION 1008 L zor lt lt 99r LS zHW00 8 m 050 250 zu ASNA 4 L aces 4 AGOW M20 1O ACC Tor a 8 v 56F8367EVM Schematics Rev 2 Appendix A 3 Freescale Semiconductor Preliminary 750 150 eg 062 Freescale Semiconductor Preliminary jeeus ubiseq 95 ueuBiseg 7005 20 Jequiejdes Aepsiny JequunN NSQ INA349 8439SOIN 9 9TCTSAITOSLI AYOWAW 750 150 81 VLVG pue 0S9 QHOAA dIV9llvLSD 9 8 diV9rrtcLso psc 0192 17 087 xv3 812 868 218 IEEE ED 2 78208 euozuy 10119 1523 0012 91225924 _
5. MC56F8367EVM User Manual Rev 2 Freescale Semiconductor Appendix A 14 Preliminary S10312ede ssed g 3 q 0 JO 19945 0054 ueufiseq 7002 20 ejeq NSCIWAGZ9E8H99OW 926 SHOllDVdvO SSVdAg 0192 10 089 XV4 912 968 ZLS 78298 euozuy 10113 1883 0012 uoge1edo euBis 40 5 226994 2 HOILOSNNOO er AOS A0 S VVCXOTlVL 6n HOILOSNNOO ee eS Wr o see sgg rA LE E ES n anyo anro anyo Se SY Ste anyo SE SE 1 960 Sto 55 12 l l NR Acte ats HOLOHNNOO HOLOSNNOO WOLOSNNOO snd sna 33 MR oF I cere It 1 Na s CET Ik xe tor rU eei rre eR A E jr ys
6. J1 Pin Signal Pin Signal 81 VREFH 82 VREFH 83 GNDA 84 GNDA 85 ANO 86 AN1 87 AN2 88 AN3 89 AN4 90 AN5 91 AN6 92 AN7 93 AN8 94 AN9 95 AN10 96 AN11 97 AN12 98 AN13 99 AN14 100 AN15 2 11 2 Memory Daughter Card Connector The processor s external memory bus signals are connected to the memory daughter card connector J2 Table 2 12 shows the port signal to pin assignments Table 2 12 Memory Daughter Card Connector Description J2 Pin Signal Pin Signal 1 aupa 2 3 11 4 5 A2 PA10 6 A7 PE3 7 A11 9 8 RD 9 GND 10 GND 11 PA8 12 DS CS1 13 PS CSO 14 PDO CS2 2 TX MC56F8367EVM User Manual Rev 2 2 20 Freescale Semiconductor Preliminary Daughter Card Connectors Table 2 12 Memory Daughter Card Connector Description Continued J2 Pin Signal Pin Signal 15 00 16 015 17 01 10 18 014 7 19 GND 20 GND 21 GND 22 GND 23 02 11 24 013 25 03 PF12 26 012 27 04 PF13 28 D11 PF4 29 05 14 30 010 31 GND 32 GND 33 GND 34 GND 35 06 PF15 36 09 37 07 PFO 38 08 PF1 39 WR 40 PD1 CS3 2 41 A15 42 8 PAO 43 GND 44 GND 45 A14 PA6 46 A9 47 A13 5 48 10 2 49 12
7. J4 Pin Signal Pin Signal 1 AO 2 1 9 3 2 PA10 4 PA11 5 A4 PA12 6 A5 PA13 7 A6 2 8 9 A8 10 A9 PA1 11 A10 12 A11 13 12 4 14 A13 PA5 15 A14 PA6 16 15 17 16 18 1 A17 19 2 18 20 19 21 4 20 22 5 21 23 PB6 A22 24 PB7 A23 19 GND 20 3 3V MC56F8367EVM User Manual Rev 2 2 28 Freescale Semiconductor Preliminary 2 15 2 Data Bus Expansion Connector Peripheral Expansion Connectors The data bus expansion connector contains the 56F8367 s 16 external memory data signal lines Refer to Table 2 17 for the data bus connector information Data lines DO D15 can also be used as GPIO Port F lines bits 0 15 Table 2 17 External Memory Address Bus Connector Description J5 Pin Signal Pin Signal 1 00 9 2 D1 PF10 3 D2 PF11 4 D3 PF12 5 D4 PF13 6 05 PF14 7 D6 PF15 8 D7 PFO 9 D8 PF1 10 D9 PF2 11 010 12 D11 PF4 13 D12 PF5 14 013 15 014 7 16 015 17 GND 18 3 3V Technical Summary Rev 2 Freescale Semiconductor Preliminary 2 29 2 15 3 External Memory Control Signal Expansion Connector The external memory control signal connector contains the 56F8367 s external memory control signal lines CS2 and CS3 are MPIO sig
8. asn 11 ozz 5 b 5 lt lt 7 2 Q31MOTI3A o vOOVYvA C31 gsn 022 T gt lt lt Q31MOTIJA 98 vsn Ag e a3 a 8 56F8367EVM Schematics Rev 2 Appendix A 7 Freescale Semiconductor Preliminary 8 NWO p ds uBIH 4 Jo 1 S ODSA 7002 ZO Jequiejdeg Aepsunu NSG NA349 83982IN L LHOd NYO Q33dS HO9IH 0192 17 089 4 912 568 219 78208 euozuy 10119 1523 0012 2 40 5 295994 19 S NOLLVNINWHSL 2 241 7 sna HNVOg ber ocr eror AOLOANNOD 5 NWO NIVHO ASIVG HOLOZSNNOO 5 NWO 33075 Y v Y 1 HNVO o 8 MC56F8367EVM User Manual Rev 2 Freescale Semiconductor Appendix A 8 Preliminary o2ejioju 28 Jod NWO 8 1614 3 oL vl JO 8 jeeus 95 ueuBiseq 7005 Zo Jequejdes Aepsuny eje
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12. 0 nva 1 Ag e O SNS SVINMd lt lt vVVINMd E m 08d EYN Md lt lt 0 LYNMd Ov Md ey M oe 97 Sy 2 eaLinva 28429 gu 77 m 44 ranya AS an Od oi emoes 2 aw fet ENS va Md LEW Md lt lt lt gt gt gt lt eld za LOXL L3INOH ofa FGHSVHdA amp Trsow THi TO4 Sd 2 ov 4 0V3SVHd LW o 6 IN _ 8 y 9v 9 5 O A0 S Sv v z L a V Preliminary Freescale Semiconductor MC56F8367EVM User Manual Rev 2 Appendix A 10 40 9 05 uoisuedx3 106592014 0L V 911614 Appendix A 11
13. 9 8 050 9 8 a a 9 V MC56F8367EVM User Manual Rev 2 Appendix A 4 S10 99UUO9 19 pue 262 564 1614 I 5 01 vl JO v 95 7005 20 Jequejdes Aepsunu eje v NSC WA3298849SOIN TE ezis SHOLOSNNOO 105 ANY 222 54 ORL 8298 euozuy 1 peoy 10119 1se3 0012 0188 6109 089 4 912 968 219 2 0 2 jeubis 225994 7 A e 5 4 olor HIgVSIG cec sa ATAVNA 2 2 54 NMOGLNHS 222 54 HOLO3NNOO Svan S 4 c c SH nose OF IDS NISH nov noes 1nozu NI LH 1nolW ainozu pho SLA axa 1noeL NIEL 810 1nozL be NOLL NILL 201 9 NI XL eod dno ano t 019 qos 56F8367EVM Schematics Rev 2 Appendix A 5 Freescale Semiconductor Preliminary 6441 1955 4 JO yeeus ODSA 7005 20 Aepsunu NSQ IN 3Z49 8H39SOIN JequinN 0192 17
14. s E 1 j ed j i E Eo lp Thu Sls 1 anvo anyo anvo anvo Imoo SL anro loo anro SL eco b que l 959 119 1 90 620 l E 9 9 o 1 ACE ACE 1 AC Act MEM i Ace MEM 1 ira Ajo bs ui 000VTL 02 7 00 SVCEXVN 9TTZLSD 9112150 80 Ln 9n sn 30100 Se 45400 Se anyo Se ao 822 422 755 559 250 929 522 veo 622 4 5 H33SA Ag L9c8439S0W 56F8367EVM Schematics Rev 2 Appendix A 15 Freescale Semiconductor Preliminary MC56F8367EVM User Manual Rev 2 Appendix A 16 Freescale Semiconductor Preliminary Appendix B 56F8367EVM Bill of Material Qty Description Ref Designators Vendor Part Integrated Circuits 1 MC56F8367 U1 Freescale MC56F8367VPY60 2 128K x 16 Bit SRAM U2 U3 GSI GS72116ATP 8 1 RS 232 Transceiver U4 Maxim MAX3245EEAI 2 74AC04 U5 U6 ON Semiconductor MC74ACO4AD 1 74ACOO 07 Fairchild 74 5 1 244 U8 ON Semiconductor MC74LHC44AADW 1 TALCX244 U9 ON Semiconductor MC74
15. 4 50 A11 54 16 52 GND 53 GND 54 GND 55 3 3V 56 3 3V 57 GND 58 GND 59 5 0V 60 5 0V Technical Summary Rev 2 Freescale Semiconductor Preliminary 2 21 2 12 Motor Control PWM Signals and LEDs The 56F8367 has two independent groups of dedicated PWM units Each unit contains six PWM three phase current sense inputs and four fault input lines PWM group A s PWM lines are connected to set of six PWM LEDs via inverting buffers The buffers are used to isolate and drive the Processor s PWM group A s outputs to the PWM LEDs PWM LEDs indicate the status of PWM group A signals refer to Figure 2 10 PWM Group A and B signals are routed out to headers J7 and J8 respectively and to the peripheral daughter card connector for easy use by the end user 56F8367 PWMAO gt PWMAO PWMA1 gt 1 PWMA2 PWMA2 9 4 9 gt PWMA4 PWMA5 _ _ __ _____ 5 3 3V Yellow LED LED7 9 Phase Green LED LED8 Phase A Bottom Yellow LED LED9 Phase B Top Phase B Bottom Green LED 4 LED10 Yellow LED LED11 Phase C Top Green LED LED12 Phase C Bottom Figure 2 10 PWM Group A Interface and LEDs MC56F8367EVM User Manual Rev 2 2 22 Freescale Semiconductor Preliminary CAN Interfaces 2 13 CAN I
16. 99 00 VNV lt lt 92 00 095 00 LINY lt 680 624 00 9NV SNV NV LNY ONY 56F8367EVM Schematics Rev 2 Appendix A 13 Freescale Semiconductor Preliminary seiddng Ef a E 8 v m JO PAS 0250 7002 20 jequieydeg Kepsunu ejeq ez jueuinooq E 2 5 5 1 i 0192 61 089 912 968 219 u z 941 edi ae ee 9 295994 poo INIOd 1591 1591 1591 ISAL 1591 1541 LNIOd 1581 ANNON AE E j ubis Tehbid A 0 OWD 50 OW iv ec pa mr
17. 56 8367 Evaluation Module User Manual 56F8300 16 bit Digital Signal Controllers MC56F8367EVMUM Rev 2 07 2005 freescale com freescale semiconductor Document Revision History Version History Description of Change Rev 1 0 Initial Public Release Rev 2 0 Updated look and feel TABLE OF CONTENTS Preface Preface vii Chapter 1 Introduction Jj S6F8367EVNI CRAT deo 0455 45 1 2 LZ 56F8367EVM Configuration Jumpers 1 3 LJ eS eae ed 1 5 Chapter 2 Technical Summary 444 25 dada d 4dAad dude 2 4 22 Data Memory od EE Hon Oe ER C RN 2 4 24 1 SRAM CRED eroi ades 2 5 2 2 2 SAM BIB 2 6 23 ee Soral OT ace c 2 7 I Oo dada 2 8 Opek ne MOE gt 2 9 FANE roe 2 9 2 3 2 EMI MODEB eee a Idee 2 9 Bd 2 10 NN le pep oan ease od nee eens esa gt _ ores 2 10 25 22 hg ee 2 11 CN JP OPZ Oo 2 12 kek Parallel JTAG Interface Connector 2 13 28 Boo gt pd 2 15
18. rem 2 16 __ ___ RA EVI KE E 2 17 241 Danghter Card Connectors ag oy ____ 2 18 Pernpheral Daughter Card 00803407 ids dicks had ced aed 2 18 2112 Memory Dausbler Card Concer lt lt weas was 2 20 2 12 Motor Control PWM SignalsandLEDS 2 22 Table of Contents Rev 2 Freescale Semiconductor i Preliminary CAN IMEC 2 23 24181 2 5 2 23 ALAS 2 24 2 18 Software Feature UIDES La pid cen 2 26 2 19 Peripheral Expansion Connectors SPARE EA RE ES ERE 2 27 215 1 Address Bus Expansion UNCC oo oss qucd aen cA d FEX aus pasa sasa 2 28 2152 Data Bus Expansion ome et Rud 2 29 2 15 3 External Memory Control Signal Expansion 2 30 2 154 Encoder 0 Quad Timer Channel Expansion 2 30 2153 Encoder 1 SPI Expansion Connector 2 31 2455 Timer Channel C Expansion Connector 2 31 2 15 7 Timer Channel D Expansion Connectot 2 32 2155 A D Port A Expansion Connector 2 33 2 15 9 A D Port B Expansion Conngector ssssqasasa wawawa saa 2 34 2 15
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20. E SS ev 125 624 6 0044 08 80d 0VSI E ov 08 lt VINMd T SVAMd LINE EE 99 V VIAM 6 r 4 Md 0014 OVIAMd amp Ovid vin MC56F8367EVM User Manual Rev 2 Freescale Semiconductor Appendix A 2 iminary Prel SONI 9 42019 pow josey 72 4 NOLLINGHSNd LASHA 7 V JO 3945 oosa ueuBisegq 7005 Zo Aepsunu v a OL z I Jequun NSC WAAZ9E849SON iude 215 23 1 1 sI 50419 13584 5 0188 6109 089 XV4 911 968 219 JojonpuooIures euozuy dunt 91295294 2 101119 5 0012 uogejedo te IVNOILdO 2 v TH E aedump z a Koss lt lt 5 Sor 55 Sor NOLLNGHSNd MOL a T Stw ow AE o 2 72
21. J11 SPI 1 expansion connector to allow the user to connect his own SPI 1 MPIO compatible peripheral J12 expansion connector to allow the user to connect his own PWMA compatible peripheral J7 PWMB expansion connector to allow the user to connect his own PWMB compatible peripheral J8 CAN 1 expansion connector to allow the user to connect his own CAN physical layer peripheral J18 CAN 2 expansion connector to allow the user to connect his own CAN physical layer peripheral J19 Timer A expansion connector to allow the user to connect his own Timer A Encoder 0 compatible peripheral J15 Timer C expansion connector to allow the user to connect his own Timer C compatible peripheral J16 Timer D expansion connector to allow the user to connect his own Timer D compatible peripheral J17 ADC A expansion connector to allow the user to attach his own A D Port A compatible peripheral J9 ADC B expansion connector to allow the user to attach his own A D Port B compatible peripheral J10 MC56F8367EVM User Manual Rev 2 2 2 Freescale Semiconductor Preliminary Address bus expansion connector to allow the user to monitor the external address bus J4 Data bus expansion connector to allow the user to monitor the external data bus J5 External memory bus control signal connector to allow the user to monitor the external memory bus J6 On board power regulation provide
22. The user can select between a 64K address space or an 8M address space Refer to the 56F8300 Peripheral User Manual and the 56F8367 Technical Data Sheet for a complete description of the chip s operating modes Table 2 4 shows the two EMI operation modes available on the 56F8367 Table 2 4 EMI Operating Mode Selection Operating Mode JG5 Comment V1 1 2 A15 64K available for external memory bus GND V2 No Jumper A23 8M available for external memory bus 3 3 Technical Summary Rev 2 Freescale Semiconductor 2 9 Preliminary 2 5 3 CLKMODE The 56F8367EVM provides clock boot mode jumper JG6 This jumper is used to select the type of clock source being provided to the processor as it exits reset The user can select between the use of a crystal or an oscillator as the clock source for the processor Refer to the 56F8300 Peripheral User Manual and the 56F8367 Technical Data Sheet for a complete description of the chip s operating modes Table 2 5 shows the two CLKMODE operation modes available on the 56F8367 Table 2 5 EMI Operating Mode Selection Operating Mode JG6 Comment Crystal 1 2 Enables the external clock drive logic so an external crystal can be used as the input clock source GND Oscillator No Jumper Disables the external clock drive logic Use oscillator input on XTAL and Ground on EXTAL 3 3V 2 6 Debug LEDs Six on board Light Emitting Dio
23. 089 4 9161 9568 219 78208 euozuy 10119 1523 0012 4 4 AASA 40 5 225994 022 gt 045 gt Ve 022 ro Jon lt TT 3en aen oen gt az MOTIN 694 Ole gt 23 AG E 894 L asvHd 89 4 Tr oa MC56F8367EVM User Manual Rev 2 Freescale Semiconductor Appendix A 6 Preliminary 8081 93638 v WMd 9 V 1614 I 5 01 vl JO 9 jeeus 95 ueuBiseq 7005 Zo Jequejdes Aepsunu eje v NSQ INA349 849S80IN 9215 6041 1 lt LHOd 2 0 2 JeuBis 089 XV4 9 2 968 219 8288 1 10119 1se3 0012 91295984 _ 7 e odd l LV LS WMd 1450 474 022 TT lt 194 480 vOOVYvA Ole IT aJ MOTI 2
24. 15 External Memory Control General Purpose Port D bits 0 5 8 amp 9 Quadrature Decoder 0 Quad Timer Channel A Quadrature Decoder 1 Serial Peripheral Interface Port 1 Quad Timer Channel B General Purpose Port C bits 0 3 Quad Timer Channel C General Purpose Port E bits 8 amp 9 Quad Timer Channel D General Purpose Port E bits 10 13 A D Input Port A A D Input Port B Serial Communications Port 0 General Purpose Port E bits 0 and 1 Serial Communications Port 1 General Purpose Port D bits 6 and 7 Serial Peripheral Interface Port 0 General Purpose Port E bits 4 7 PWM Port A General Purpose Port C bits 8 10 PWM Port General Purpose Port C bits 0 3 CAN Port 1 CAN Port 2 Technical Summary Rev 2 Freescale Semiconductor 2 27 Preliminary 2 15 1 Address Bus Expansion Connector The address bus expansion connector contains the 56F8367 s 24 external memory address signal lines Address lines A6 and A7 can optionally be used as GPIO Port E lines bits 2 and 3 Address lines A8 A15 can optionally be used as GPIO Port A lines bits 0 7 Address lines AO A5 can optionally be used as GPIO Port A lines bits 8 13 Address lines A16 A23 are MPIO signals which can be configured as A16 A23 or GPIO Port B bits 0 7 Refer to Table 2 16 for the address bus connector information Table 2 16 External Memory Address Bus Connector Description
25. 2 8 v MC56F8367EVM User Manual Rev 2 Freescale Semiconductor Appendix A 12 Preliminary 49314 yndul 1614 vl JO 19945 ubiseg oosa 7002 ZO Jequiajdes epsunu ejeq v Jequunw ezis NSQ INA3Z79 839SOIN 5431714 0188 6109 087 Xv4 912 968 219 8298 euozuy eduie peoy 10119 18 39 0012 jeublis WaND 107 e eso ALON ANZZO0 0 blo 00 18NV lt lt 3122000 820125 00L 98Nv lt lt 3122000 elo 00L lt 0 _s so s 6 A 149 00 lt lt lt A4ol9npuooluu s P2S931 A 20070 0 0 00 lt lt A 20070 690 ool e lt lt OLNV 890 00 e lt lt Jjnzzooo 499 ool lt lt y 984 A anzzo0 0 999 00 ANNV lt lt 372200 0 890 00 9VNV 799 00 95 00
26. Freescale Semiconductor Preliminary Appendix A 56F8367EVM Schematics 56F8367EVM Schematics Rev 2 Freescale Semiconductor Appendix A 1 Preliminary 105399044 79684296 L V 4 3 q m JO PAS 5 0054 7002 20 19qui d s ejeq NSC WASZ9 849SON 2215 208590014 96849 9 0188 619 089 4 912 968 ZLS 78298 euozuy eduie 301119 0012 296994 7 gt aiio 3SN3S T 1 WI LANA s LANA A dal inva Ovi Atddng As z wyo 0 esn esn zh uuo 0 09 44 968 960 1 117155 ONC E sid E SS anro 501 55 910 Sio T 206 T LL quz GIWJSSA 2 zz ZW 90 OdVO e toS A H338A H33HA EIN Feo Finn
27. Phase Locked Loop PLL Preface ix PLL Preface ix Printed Circuit Board PCB Preface ix Pulse Width Modulation Preface ix PWM Preface ix PWMA compatible peripheral 2 2 PWMB compatible peripheral 2 2 Q QuadDec Preface ix Quadrature Decoder interface port 2 30 QuadDec Preface ix R R C Preface x RAM Preface x Random Access Memory RAM Preface x Read Only Memory ROM Preface x real time debugging 2 10 Resistor Capacitor Network R C Preface x ROM Preface x RS 232 2 1 level converter 2 7 schematic diagram 2 7 s SCI Preface x SCI MPIO compatible peripheral 2 2 Serial Communications Interface SCI Preface x Serial Peripheral Interface SPI Preface x SPI Preface x SPI MPIO compatible peripheral 2 2 SRAM Preface x external data 2 1 external program 2 1 Static Random Access Memory SRAM Preface x T Timer compatible peripheral 2 2 W Wait State WS Preface x WS Preface x MC56F8367EVM User Manual Rev 2 Index 2 Freescale Semiconductor Preliminary How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 Englis
28. found at URL www freescale com Preface Rev 2 Freescale Semiconductor vii Preliminary Notation Conventions This manual uses the following notational conventions paths emphasis Term or Value Symbol Examples Exceptions Active High Signals No special symbol Logic One attached to the signal CLKO name Active Low Signals Noted with an WE In schematic drawings Logic Zero overbar in text and in OE Active Low Signals may be most figures noted by a backslash WE Hexadecimal Values Begin with sym 580 Decimal Values No special symbol 10 attached to the 34 number Binary Values Begin with the letter b b1010 attached to the number b0011 Numbers Considered positive 5 Voltage is often shown as unless specifically 10 positive 3 3V noted as a negative value Blue Text Linkable on line efer to Chapter 7 License Bold Reference sources 5 www freescale com MC56F8367EVM User Manual Rev 2 viii Freescale Semiconductor Preliminary Definitions Acronyms and Abbreviations Definitions acronyms and abbreviations for terms used in this document are defined below for reference A D Analog to Digital a method of converting Analog signals to Digital values ADC Analog to Digital Converter a peripheral on the 56F8367 part CAN Controller Area Network serial communications peripheral and method CiA CAN in Automation an
29. information There is a Resistor Connector R C network on each of the Analog Port A input signals see Figure 2 14 Peripheral Expansion Connectors Table 2 23 A D Port A Connector Description J9 Pin Signal Pin Signal 1 ANO 2 AN1 3 AN2 4 5 6 AN5 7 AN6 8 7 9 GNDA 10 VnEFH 100 ohm Analog Input A 0 0022uF To Processor s Analog Port Figure 2 14 Typical Analog Input RC Filter Technical Summary Rev 2 Freescale Semiconductor Preliminary 2 33 2 15 9 A D Port B Expansion Connector The eight channel Analog to Digital conversion Port B 15 attached to this connector Refer to Table 2 24 for connection information There is an R C network on each of the Analog Port B input signals see Figure 2 14 Table 2 24 A D Port B Connector Description J10 Pin Signal Pin Signal 1 AN8 2 AN9 3 AN10 4 AN11 5 AN12 6 AN13 7 AN14 8 AN15 9 GNDA 10 VnEFH 2 15 10 Serial Communications Port 40 Expansion Connector The Serial Communications Port 0 is an MPIO port attached to the SCI 0 expansion connector This port can be configured as a Serial Communications Interface or as a General Purpose I O port Refer to Table 2 25 for connection information Table 2 25 SCI 0 Connector Description J13 Pin Signal Signal 1 TXDO PEO RXDO PE1 MC56F8367EV
30. international CAN user s group that coordinates standards for CAN communications protocols D A Digital to Analog a method of converting Digital values to an Analog form S6F8367 Controller with motor control peripherals EOnCE Enhanced On Chip Emulation a debug bus and port was created to enable a designer to create a low cost hardware interface for a professional quality debug environment EVM Evaluation Module a hardware platform which allows a customer to evaluate the silicon and develop his application FlexCAN Flexable CAN Interface Module a peripheral on the 56F8367 part GPIO General Purpose Input and Output port on Freescale s family of controllers does not share pin functionality with any other peripheral on the chip and can only be set as an input output or level sensitive interrupt input IC Integrated Circuit JTAG Joint Test Action Group a bus protocol interface used for test and debug LED Light Emitting Diode LQFP Low profile Quad Flat Package MPIO Multi Purpose Input and Output port on Freescale s family of controllers shares package pins with other peripherals on the chip and can function as a GPIO On Chip Emulation debug bus and port created to allow a means for low cost hardware to provide a professional quality debug environment PCB Printed Circuit Board PLL Phase Locked Loop PWM Pulse Width Modulation QuadDec Quadrature Decoder a peripheral on the 56F8367 part Preface Rev 2 Freescale Semicon
31. is attached to this connector Refer to Table 2 29 for connection information Table 2 29 CAN 2 Connector Description J19 Pin Signal Pin Signal 1 CAN2 TX 2 GND 3 CAN2 RX 4 GND MC56F8367EVM User Manual Rev 2 2 36 Freescale Semiconductor Preliminary 2 15 15 PWM Port A Expansion Connector Peripheral Expansion Connectors The PWM Port A 15 attached to this connector Refer to Table 2 30 for connection information 2 15 16 PWM Port B Expansion Connector Table 2 30 PWM Port A Connector Description J7 Pin Signal Pin Signal 1 PWMAO 2 PWMA1 3 PWMA2 4 5 4 6 5 7 FAULTAO 8 FAULTA1 9 FAULTA2 10 FAULTA3 11 ISAO PC8 12 ISA1 PC9 13 ISA2 PC10 14 GND The is attached to this connector Refer to Table 2 31 for connection information Table 2 31 PWM Port B Connector Description J8 Pin Signal Pin Signal 1 PWMBO 2 PWMB1 3 PWMB2 4 PWMB3 5 PWMB4 6 PWMB5 7 FAULTBO 8 FAULTB1 9 FAULTB2 10 FAULTB3 11 ISBO PD10 12 ISB1 PD11 13 ISB2 PD12 14 GND Technical Summary Rev 2 Freescale Semiconductor Preliminary 2 37 2 16 Test Points The 56F8367EVM board has a total of seven test points Analog Ground AGND Three Digital Grounds GND 3 3V 3 3 5 0 MC56F8367EVM User Manual Rev 2 2 38
32. 10 Serial Communications Port 0 Expansion Connector 2 34 2 15 11 Serial Communications Port 1 Expansion 2 35 2 15 12 Serial Peripheral Interface 0 Expansion Connector 2 35 21513 FIexCAN 1 Expansion pues a dev dd Ex RP YA 2 36 2 15 14 2 Expansion 2 36 21215 PWM Port A Expansion 2 37 2 45 5 PWM Port B Expansion 2 226 vis 2 37 55058455 595 or 8545S Re 2 38 56F8367EVM Schematics Appendix B 56F8367EVM Bill of Material MC56F8367EVM User Manual Rev 2 ii Freescale Semiconductor Preliminary id i id 2 1 22 2 2 4 2 5 2 6 23 2 8 2 9 2 10 sji 2 13 215 213 LIST OF FIGURES Block Diagram ol the OD PS ded rb Rd dd cd 1 2 MC56F8367 Default Jumper OptionS s ass sasana 1 3 Connecting the 56F8367EVM Cables 1 5 Schematic Diagram of the External CSO Memory Interface 2 5 Schematic Diagram of the External CS1 CS4 Memory Interface 2 6 Schematic Diagram of the RS 232 2 7 Schematic Diagram gf the Clock
33. 12 GND 13 14 PHASEBO 1 5 15 INDEXO 2 PC6 16 7 17 GND 18 GND 19 1 PCO SCLK1 20 PHASEB1 PC1 TB1 MOSI 21 INDEX1 PC2 TB2 MISO1 22 HOME1 PC3 551 23 TXDO PEO 24 TXD1 25 TXDO PEO 26 TXD1 PD6 27 RXDO PE1 28 RXD1 PD7 MC56F8367EVM User Manual Rev 2 2 18 Freescale Semiconductor Preliminary Table 2 11 Peripheral Daughter Card Connector Description Continued J1 Pin Signal Pin Signal 29 IRQA 30 IRQB 31 RXDO PE1 32 RXD1 PD7 33 PWMBO 34 PWMB1 35 PWMB2 36 PWMB3 37 PWMB4 38 5 39 GND 40 GND 41 ISBO PD10 42 ISB1 PD11 43 ISB2 PD12 44 GND 45 FAULTB1 46 FAULTBO 47 FAULTB3 48 FAULTB2 49 GND 50 GND 51 PWMAO 52 PWMA1 53 PWMA2 54 PWMA3 55 4 56 5 57 GND 58 GND 59 FAULTAO 60 FAULTA1 61 FAULTA2 62 MISOO PEG 63 ISAO PC8 64 15 1 65 ISA2 10 66 RSTO 67 MOSIO PES 68 550 PE7 69 PE10 70 TD1 PE11 71 SCLKO PE7 72 73 74 75 MOSIO 76 MISOO PEG 77 SCLKO PE4 78 550 PE7 79 GND 80 GND Technical Summary Rev 2 Daughter Card Connectors Freescale Semiconductor Preliminary Table 2 11 Peripheral Daughter Card Connector Description Continued
34. 5 0V DC CAN Regulat Condition Input egulator T L Rectifier 1 9 3 3V 3 3V DC 56F8367 Regulator amp PLL 56F8367EVM 5 424 R67 R70 425V DC 1 56F8367 Ext In 2 Vpp Core Power On 4 3 3V 3 3VA DC 56F8367 Regulator ADC U15 3 3V 3 3VA DC 56F8367 Regulator VREFH Figure 2 9 Schematic Diagram of the Power Supply Technical Summary Rev 2 Freescale Semiconductor 2 17 Preliminary 2 11 Daughter Card Connectors The EVM board contains two daughter card connectors One connector J1 contains the processor s peripheral port signals The second connector J2 contains the processor s external memory bus signals 2 11 1 Peripheral Daughter Card Connector The processor s peripheral port signals are connected to the peripheral daughter card connector The peripheral daughter card connector is used to connect a daughter card or a user specific daughter card to the processor s peripheral port signals The peripheral port daughter card connector is a 100 pin high density connector with signals for the IRQs reset SPI SCI PWM ADC and Quad Timer ports Table 2 11 shows the peripheral daughter card connector s signal to pin assignments Table 2 11 Peripheral Daughter Card Connector Description Pin Signal Pin Signal 1 12V 2 12 3 GND 4 GND 5 5 0V 6 5 0V 7 GND 8 GND 9 3 3V 10 3 3V 11 GND
35. 5 High selected on User Jumper 80 1 2 16 High selected on User Jumper 1 1 2 17 CAN termination selected 1 2 18 Analog Ground to Digital Ground not reconnected NC JG19 Use 3 3V for Printer Interface to on board Parallel JTAG Host Target 1 2 MC56F8367EVM User Manual Rev 2 Freescale Semiconductor Preliminary 56F8367EVM Connections 1 3 56F8367EVM Connections An interconnection diagram is shown in Figure 1 3 for connecting the PC and the external 12 0V DC AC power supply to the 56F8367EVM board Parallel extension cable MC56F8367EVM PC compatible computer Y 221 Connect cable to parallel printer port External with 2 1mm 12V receptacle power connector Figure 1 3 Connecting the 56F8367EVM Cables Perform the following steps to connect the 56F8367EVM cables 1 Connect the parallel extension cable to the parallel port of the host computer 2 Connect the other end of the parallel extension cable to shown in Figure 1 3 on the 56F8367EVM board This provides the connection which allows the host computer to control the board 3 Make sure that the external 12V DC 1 2A power supply is not plugged into a 120V AC power source 4 Connect the 2 1mm output power plug from the external power supply into shown in Figure 1 3 on the 56F8367EVM board 5 Apply power to the external power supply The green Power On LED LED13 will ill
36. DIODES DF02S 1 52 401 2 Vishay DLA001DICT 0 52 401 03 04 Optional Vishay DLA001DICT Capacitors 1 470uF 16V DC C1 ELMA RV 16V471MH10R 4 47uF 16V DC 2 5 ELMA RV2 16V470M R 4 2 2uF 25V DC C6 C9 TAIYO YUDEN CELMK212BJ225MG T Low ESR 4 1 25V DC C10 C13 5 MCCE105K3NR T1 37 0 1uF C14 C32 C35 C51 C77 SMEC MCCE104K2NR T1 6 0 01 uF C52 C56 C76 SMEC MCCE103K2NR T1 MC56F8367EVM User Manual Rev 2 Appendix B 2 Freescale Semiconductor Preliminary Qty Description Ref Designators Vendor Part Capacitors Continued 1 0 001 57 5 MCCE102K2NR T1 1 100pF C58 SMEC MCCE101K2NR T1 16 0 0022uF C59 C74 SMEC MCCE222K2NR T1 1 10 10V DC C75 KEMET T494B106M010AS Jumpers 4 3 x 1 Bergstick JG1 JG15 JG16 JG19 SAMTEC TSW 103 07 S S 12 1 x 2 Bergstick JG2 JG7 JG10 JG13 JG17 SAMTEC TSW 102 07 S S JG18 3 2 x 2 Bergstick JG8 9 14 TSW 102 07 S D Test Points 3 GND Test Point TP1 TP2 TP3 KEYSTONE 5001 BLACK 1 3 3V Test Point 4 KEYSTONE 5000 RED 1 3 3V A Test Point TP5 KEYSTONE 5004 YELLOW 1 GNDA Test Point TP6 KEYSTONE 5002 WHITE 1 5 0V Test Point TP7 KEYSTONE 5003 ORANGE Crystals 1 8 00MHz Crystal Y1 CTS ATS08ASM T Connectors 1 DB25M Connector P1 AMPHENOL 617 C025P AJ121 1 DE9S Connector P2 AMPHENOL 617 0095 120 1 2 1mm coax P3 Swit
37. G11 as a jumper but could be implemented using uncommitted GPIO signals The SCI port 0 signals can be isolated from the RS 232 level converter by removing the jumpers in JG9 see Table 2 1 The pin out of connector P2 is listed in Table 2 2 The RS 232 level converter transceiver can be disabled by placing a jumper at JG10 RS 232 MC56F8367 Level Converter Interface R2 out T2 out FORCEOFF Jumper Removed JG10 Enable RS 232 Jumper Pin 1 2 Disable RS 232 Figure 2 3 Schematic Diagram of the RS 232 Interface Table 2 1 SCI 0 Jumper Options JG9 Pin Signal Pin Signal 1 TXDO 2 5 232 TXD 3 RXDO 4 RS 232 RXD Technical Summary Rev 2 Freescale Semiconductor Preliminary 2 7 Table 2 2 RS 232 Serial Connector Description P2 Pin Signal Pin Signal 1 Jumper to 6 amp 4 6 Jumper to 1 amp 4 2 TXD 7 CTS 3 RXD 8 RTS 4 Jumper to 1 amp 6 9 NC 5 GND 2 4 Clock Source The 56F8367EVM uses an 8 00MHz crystal Y 1 connected to its external crystal inputs EXTAL and XTAL To achieve its maximum internal operating frequency the 56F8367 uses its internal PLL to multiply the input frequency An external oscillator source can be connected to the processor by using the oscillator bypass connectors JG1 and JG2 see Figure 2 4 If the input frequency is above 8MHz then the EXTAL input should be jumpered to ground by ad
38. Jumper 2 12 2 9 Parallel JTAG Interface Connector Description 2 14 2 10 Parallel JTAG Interface Voltage Jumper 2 14 2 11 Peripheral Daughter Card Connector Description 2 18 2 12 Memory Daughter Card Connector Description 2 20 2 13 Header gt 2 24 2 14 2 Header Lu usus 2 25 2 15 CAN 2 Pass Through Jumper 2 25 2 16 External Memory Address Bus Connector 2 28 2 17 External Memory Address Bus Connector 2 29 2 18 External Memory Control Signal Connector Description 2 30 2 19 Timer A Signal Connector Description 2 30 2 20 SPI 1 Signal Connector Description 2 31 2 21 Timer Channel C Connector Description 2 31 2 22 Timer Channel D Lonnector Description 2 32 2 23 A D Post Connector Description 2 33 2 24 A D Port B Connector Description 2 2 34 2 25 SCI 0 Connector Description 2 34 List of Tables Rev 2 Freescale Semiconducto
39. LCX244ADW 2 CAN Transceiver U10 U11 Philips Semiconductor PCA82C250T 1 5 0V Voltage Regulator U12 ON Semiconductor MC33269DT 5 2 3 3V Voltage Regulator U13 U14 ON Semiconductor MC33269DT 3 3 1 3 3V Voltage Regulator U15 Burr Brown REG113NA 3 3 0 Power On Reset U16 Optional Dallas Semiconductor DS1818 Resistors 1 1MQ R1 SMEC RC73L2A1050HMJT 13 10KQ R2 R14 5 RC73L2A103OHMJT 13 47 R15 R27 SMEC RC73L2A473OHMJT 12 R28 R38 R94 5 RC73L2A103OHMJT 0 1KQ R95 Optional 5 RC73L2A103OHMJT 2 1200 1 4W R40 R41 YAGEO CFR 120QBK 56F8367EVM Bill of Material Rev 2 Freescale Semiconductor Preliminary Appendix B 1 Qty Description Ref Designators Vendor Part Resistors Continued 7 5 1KO R42 R48 SMEC RC73L2A5120HMJT 2 510 R50 R51 5 RC73L2A51OHMJT 13 2700 R52 R64 SMEC RC73L2A2710HMJT 1 100 R65 SMEC RC73L2A1000HMJT 7 00 R66 R72 R77 SMEC RC73JP2A 0 00 R67 R71 Optional SMEC RC73JP2A 16 1000 R78 R93 SMEC RC73L2A1010HMJT Inductors 5 1 0mH FERRITE BEAD L1 L5 Panasonic EXC ELSA35V 2 CAN Bus Filter L6 L7 EPCOS 82790 50513 201 LEDs 2 Red LED LED1 LED4 Hewlett Packard HSMS C650 5 Yellow LED LED2 LED5 LED7 LEDS9 Hewlett Packard HSMY C650 LED11 6 Green LED LED3 LED6 LED8 LED10 Hewlett Packard HSMG C650 LED12 LED13 Diode 1 50V 1A BRIDGE RECT D1
40. M User Manual Rev 2 2 34 Freescale Semiconductor Preliminary Peripheral Expansion Connectors 2 15 11 Serial Communications Port 44 Expansion Connector The Serial Communications Port 1 is an MPIO port attached to the SCI 1 expansion connector This port can be configured as a Serial Communications Interface or as a General Purpose I O port Refer to Table 2 26 for connection information Table 2 26 SCI 1 Connector Description J14 Pin Signal Pin Signal 1 TXD1 PD6 2 RXD1 PD7 3 GND 4 3 3V 5 GND 6 5 0V 2 15 12 Serial Peripheral Interface 0 Expansion Connector The Serial Peripheral Interface 0 is an MPIO port attached to this connector This port can be configured as a Serial Peripheral Interface or as a General Purpose I O port Refer to Table 2 27 for the connection information Table 2 27 SPI 0 Connector Description J11 Pin Signal Pin Signal 1 MOSIO PE5 2 MISOO 3 SCLKO PE4 4 550 7 5 GND 6 3 3V Technical Summary Rev 2 Freescale Semiconductor 2 35 Preliminary 2 15 13 FlexCAN 1 Expansion Connector The FlexCAN Port 1 is attached to this connector Refer to Table 2 28 for connection information Table 2 28 CAN 1 Connector Description J18 Pin Signal Pin Signal 1 CAN1 TX 2 GND 3 CAN1 RX 4 GND 2 15 14 FlexCAN 2 Expansion Connector The FlexCAN Port 2
41. M bank 1 which is controlled by CS1 and CS2 uses a 128K x 16 bit Fast Static RAM GSI 572116 labeled U3 for external memory expansion see the FSRAM schematic diagram in Figure 2 2 Using CSI and 54 this memory bank can be configured as byte 8 bit or word 16 bit accessable Program memory Data memory or both Additionally 51 and CS4 can be configured to assign this memory s size and starting address to any modulo address space This memory bank will operate with zero wait state access while the 56F8367 is running at 60 and can be disabled by removing the jumpers at JG8 MC56F8367 GS72116 A16 A16 D15 DQO DQ15 RD OE WR WE JG8 05 51 12 LB 2 CS4 4 HB CE Jumper Pin 1 2 Enable SRAM Low Byte Jumper Pin 3 4 Enable SRAM High Byte Figure 2 2 Schematic Diagram of the External CS1 54 Memory Interface MC56F8367EVM User Manual Rev 2 2 6 Freescale Semiconductor Preliminary 2 3 RS 232 Serial Communications RS 232 Serial Communications The 56F8367EVM provides an RS 232 interface by the use of an RS 232 level converter Maxim MAX3245EEAI designated as U4 Refer to the RS 232 schematic diagram in Figure 2 3 The RS 232 level converter transitions the SCI port s 3 3V signal levels to RS 232 compatible signal levels and connects to the host s serial port via connector P2 RTS CTS flow control is provided on J
42. Y 8 1 NV 8 1 8 1 081114 8 1 0 1 0 3 ELNY 9 s SNY 9Y 9 5 S NV 9 s pad 9 S VWMd LINY D OLNY Env oo D 2 t D EYNMd ZVWMd 6NV 2 D 8 2 ONV 2 V 2 L OVWMd or or 17 sna 8 Sz 5 E lz Hag ES sna 04 ow TONINOO Sis edi 80 01 nd OL S OL S OL S wot e tad 43 e 1550 6 989 o 6 0 6 2 18 oad 8 1 90 8 1 g ae Sd 9 5 9 5 D za H 2 2 9r Sr 2 8 v 56F8367EVM Schematics Rev 2 Freescale Semiconductor Prel iminary J0 D9UUOD 9 1 pue 3soH SV1T 191161 3 q m JO L 19945 59 0050 Jeufiseq 00 20 19qui d s l eq NSQ IWA349 8980W 975 HOLO3NNOO ANY 1591 15 TATIVeWd 96 A1O93NNOO 1 0 AL
43. cal layer peripheral 2 2 CiA Preface ix Controller Area Network CAN Preface ix D D A Preface ix Daughter Card Expansion interface 2 1 Debugging 2 10 Digital to Analog D A Preface ix DSP56800E Reference Manual 2 4 E Enhanced On Chip Emulation EOnCE Preface ix EOnce Preface ix Evaluation Module EVM Preface ix EVM Preface ix External oscillator frequency input 2 1 INDEX F FlexCAN Preface ix FlexCAN Interface Module FlexCAN Preface ix FSRAM 2 1 2 5 2 6 G General Purpose Input and Output GPIO Preface ix GPIO Preface ix 2 28 H Host Parallel Interface Connector 2 11 Host Target Interface 2 11 IC Preface ix Integrated Circuit IC Preface ix J Joint Test Action Group JTAG Preface ix JTAG Preface ix 2 1 JTAG Enhanced OnCE EOnCE 1 1 Jumper Group 1 4 101 1 4 10 1 4 JG11 1 4 12 1 4 JG13 1 4 1014 1 4 15 1 4 JG16 1 4 17 1 4 JG18 1 4 19 1 4 JG2 1 4 JG3 1 4 104 1 4 5 1 4 JG6 1 4 JG7 1 4 768 1 4 769 1 4 Index Rev 2 Freescale Semiconductor Preliminary Index 1 L LED Preface ix Light Emitting Diode LED Preface ix Low profile Quad Flat Package LQFP Preface ix LQFP Preface ix MPIO Preface ix 2 31 Multi Purpose Input and Output MPIO Preface ix O On board power regulation 2 3 OnCE Preface ix On Chip Emulation OnCE Preface ix P Parallel JTAG Host Target Interface 2 1 PCB Preface ix peripheral port signals 2 18
44. ce the jumper at JG3 should be removed as shown in Table 2 8 The printer port interface voltage of 3 3V 5 0 can be selected by jumper on 19 as shown in Table 2 10 DB 25 Connector Parallel JTAG Interface MC56F8367 TDI IN OUT TDI TDO OUT IN TDO P TRST IN OUT TRST TMS IN OUT TMS TCK IN OUT TCK P RESET IN OUT RESET IN DE 3 3V EN Ve Jumper Removed 163 Enable JTAG 1 1019 2 1 3 3V Jumper Pin 1 2 2 Disable JTAG I F 3 5 0V Figure 2 6 Block Diagram of the Parallel JTAG Interface Technical Summary Rev 2 Freescale Semiconductor 2 13 Preliminary Table 2 9 Parallel JTAG Interface Connector Description P1 Pin Signal Pin Signal 1 NC 14 NC 2 PORT RESET 15 PORT IDENT 3 PORT TMS 16 NC 4 PORT TCK 17 NC 5 PORT TDI 18 GND 6 PORT TRST 19 GND 7 PORT DE 20 GND 8 PORT IDENT 21 GND 9 PORT VCC 22 GND 10 NC 23 GND 11 PORT TDO 24 GND 12 NC 25 GND 13 PORT CONNECT Table 2 10 Parallel JTAG Interface Voltage Jumper Selection JG19 Comment 1 2 Interface with the PC s printer port using 3 3V signals 2 3 Interface with the PC s printer port using 5 0 signals MC56F8367EVM User Manual Rev 2 Freescale Semiconductor Preliminary External Interrupts 2 8 External Interrupts Two on board push button s
45. chcraft RAPC 722 Power Connector 1 Peripheral Daughter Card J1 HRS FX6 100P 0 8SV2 Connector 1 Memory Bus Daughter J2 HRS FX6 60P 0 8SV2 Card Connector 1 7 x 2 JTAG Header J3 SAMTEC TSW 106 07 S D 1 13 x 2 Header SAMTEC TSW 106 13 S D 56F8367EVM Bill of Material Rev 2 Freescale Semiconductor Preliminary Appendix B 3 Qty Description Ref Designators Vendor Part Connectors Continued 1 9 x 2 Header J5 SAMTEC TSW 106 09 S D 1 8 x 2 Header J6 SAMTEC TSW 106 08 S D 2 7 x 2 Header J7 J8 SAMTEC TSW 106 07 S D 6 5 x 2 Header J9 J10 J20 J23 SAMTEC TSW 106 05 S D 6 3 x 2 Header J11 J15 J17 SAMTEC TSW 106 03 S D 3 2 x 2 Header J16 J18 J19 SAMTEC TSW 106 02 S D Switches 3 SPST Push button 51 53 Panasonic EVQ PADOSR Transistors 1 2N2222A Q1 ZETEX 2222 Miscellaneous 18 Shunt SH1 SH13 Samtec SNT 100 BL T 4 Rubber Feet RF4 SJ5018BLKC MC56F8367EVM User Manual Rev 2 Appendix B 4 Freescale Semiconductor Preliminary Numerics 1 2 Amp power supply 2 17 56F8300 Peripheral User Manual 2 4 56F8357 Technical Data Sheet 2 4 8 00MHz crystal oscillator 2 1 A A D Preface ix ADC Preface ix Analog to Digital A D Preface ix Analog to Digital Converter ADC Preface ix C CAN Preface ix bus termination 2 1 2 2 bypass 2 1 2 2 interface 2 1 CAN in Automation Preface ix CAN physi
46. d from an external 12V DC supplied power input P3 Light Emitting Diode LED power indicator LED13 Six on board real time user debugging LEDs LEDI 6 Six on board Port PWM monitoring LEDs LED7 12 nternal external EXTBOOT boot mode selector 764 Address range EMI MODE boot mode selector JG5 Clock mode CLKMODE boot selector JG6 Temperature sense diode to ANA7 selector JG12 Manual reset push button S1 Manual interrupt push button for IRQA S2 Manual interrupt push button for S3 General purpose jumper on GPIO JG15 General purpose jumper on GPIO 7 JG16 Technical Summary Rev 2 Freescale Semiconductor 2 3 Preliminary 2 1 MC56F8367 The 56F8367EVM uses a Freescale MC56F8367VPY 60 part designated U1 on the board and in the schematics This part will operate at a maximum external bus speed of 60MHz A full description of the 56F8367 including functionality and user information is provided in these documents 56F8367 Technical Data Sheet MC56F8367 Electrical and timing specifications pin descriptions device specific peripheral information and package descriptions this document 56F8300 Peripheral User Manual MC56F8300UM Detailed description of peripherals of the 56F8300 family of devices DSP56800E Reference Manual DSP56800ERM Detailed description of the 56800E family architecture 16 bit core processor and the i
47. des LEDs are provided to allow real time debugging for user programs These LEDs will allow the programmer to monitor program execution without having to stop the program during debugging refer to Figure 2 5 Table 2 6 describes the control of each LED Table 2 6 LED Control Controlled by User LED Color Signal LED1 RED Port C Bit 0 PCO LED2 YELLOW Port C Bit 1 PC1 LED3 GREEN Port C Bit 2 PC2 LED4 RED Port C Bit 3 PC3 LED5 YELLOW Port D Bit 6 PD6 LED6 GREEN Port D Bit 7 PD7 MC56F8367EVM User Manual Rev 2 2 10 Freescale Semiconductor Preliminary Debug Support Setting PCO PC1 PC2 PD6 or PD7 to a Logic One value will turn on the associated LED MC56F8367 PCO PC2 PC3 PD6 PD7 INVERTING BUFFER s RED LED YELLOW LED S 4 GREEN LED A 4 RED LED YELLOW LED NOU 4 GREEN LED D 3 3 Figure 2 5 Schematic Diagram of the Debug LED Interface 2 7 Debug Support The 56F8367EVM provides an on board parallel JT AG host target interface and a JTAG interface connector for external target interface support Two interface connectors are provided to support each of these debugging approaches These two connectors are designated the JTAG connector and the host parallel interface connector Technical Summary Rev 2 Freescale Semiconductor Preliminary 2 11 2 7 1 JTAG Connector Th
48. ding jumper between JG1 pins 2 and 3 The input frequency would then be injected on JG2 s pin 2 If the input frequency is below 4MHz then the input frequency can be injected on JG1 s pin 2 External Oscillator Headers MC56F8367 JG1 P EXTAL 3 8 00MHz 7 462 1 2 XTAL Figure 2 4 Schematic Diagram of the Clock Interface MC56F8367EVM User Manual Rev 2 2 8 Freescale Semiconductor Preliminary 2 5 Operating Mode The 56F8367EVM provides three boot mode selection jumpers EXTBOOT EMI MODE and CLKMODE to provide boot up mode options 2 5 1 EXTBOOT The 56F8367EVM provides an external internal boot mode jumper JG4 This jumper is used to select the internal or external memory operation of the processor as it exits reset Refer to the S6F8300 Peripheral User Manual and the 56F8367 Technical Data Sheet for a complete description of the chip s operating modes Table 2 3 shows the two external boot operation modes available on the 56F8367 Table 2 3 EXTBOOT Operating Mode Selection Operating Mode JG4 Comment 0 1 2 Bootstrap from internal memory GND 3 No Jumper Bootstrap from external memory 3 3V 2 5 2 EMI MODE The 56F8367EVM provides an EMI boot mode jumper JG5 This jumper is used to select the external memory addressing range operating mode of the processor as it exits reset
49. ductor ix Preliminary Random Access Memory R C Resistor Capacitor Network ROM Read Only Memory SCI Serial Communications Interface a peripheral on Freescale s family of controllers SPI Serial Peripheral Interface a peripheral on Freescale s family of controllers SRAM Static Random Access Memory WS Wait State References The following sources were referenced to produce this manual 1 DSP56800E Reference Manual DSP56800ERM Freescale Semiconductor 2 56 8300 Peripheral User Manual MC56F8300UM Freescale Semiconductor 3 56F8367 Technical Data 56 8367 Freescale Semiconductor 4 CiA Draft Recommendation DR 303 1 Cabling and Connector Pin Assignment Version 1 0 CAN in Automation 5 CAN Specification 2 0B BOSCH or CAN in Automation MC56F8367EVM User Manual Rev 2 x Freescale Semiconductor Preliminary Chapter 1 Introduction The 56F8367EVM is used to demonstrate the abilities of the 56F8367 controller and to provide a hardware tool allowing the development of applications The 56F8367EVM is an evaluation module board that includes a 56F8367 part peripheral expansion connectors a CAN interface 512KB of external memory and a pair of daughter card connectors The daughter card connectors are for signal monitoring and user feature expandability The 56F8367EVM is designed for the following purposes Allowing new users to become familiar with the features of the 56800E architecture The t
50. e and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved MC56F8367EVMUM Rev 2 07 2005
51. e JTAG connector on the 56F8367EVM allows the connection of an external host target interface for downloading programs and working with the 56F8367 s registers This connector is used to communicate with an external host target interface which passes information and data back and forth with a host processor running a debugger program Table 2 7 shows the pin out for this connector Table 2 7 JTAG Connector Description J3 Pin Signal Pin Signal 1 TDI 2 GND 3 TDO 4 GND 5 TCK 6 GND 7 NC 8 KEY 9 RESET 10 TMS 11 3 3V 12 NC 13 DE 14 TRST When this connector is used with an external host target interface the parallel JTAG interface should be disabled by placing a jumper in jumper block JG3 Reference Table 2 8 for this jumper s selection options Table 2 8 Parallel JTAG Interface Disable Jumper Selection JG3 Comment No jumpers Enables On board Parallel JTAG Interface 1 2 Disables on board Parallel JTAG Interface MC56F8367EVM User Manual Rev 2 2 12 Freescale Semiconductor Preliminary Debug Support 2 7 2 Parallel JTAG Interface Connector The Parallel JTAG Interface Connector P1 allows the 56F8367 to communicate with a parallel printer port on a Windows PC reference Figure 2 6 Using this connector the user can download programs and work with the 56F8367 s registers Table 2 9 shows the pin out for this connector When using the parallel JTAG interfa
52. emonstrate the functionality of that software and interface with the user s application specific device s The 56F8367EVM is flexible enough to allow a user to fully exploit the 56F8367 s features to optimize the performance of his product as shown in Figure 1 1 DSub 25 Pin 56F8367 Program Memory Address FlexCAN 1 128K x 16 bit I e Data 4 SRAM Control SCI 0 Data Memory 128K 16 bit SRAM Memory Expansion SPI 0 Connector SCI 1 Memory Timer C Daughter 7 Connector Timer D PWMA ADCA Reset Logic RESET QuadDec 0 PWMB Mode IRQ Logic MODE IRQ ADCB QuadDec 1 2 Connector JTAG EOnCE Parallel 1 1 Interface 8 00 2 XTAU 3 3V amp GND Crystal EXTAL 3 3 amp 3 3Vner CAN 1 Bus DaisyChain CAN 1 Interface CAN 1 Bus Header RS 232 DSub Interface 9 Pin Peripheral Peripheral Expansion Daughter Card Connectors Connector CAN 2 Bus CAN 42 Interface Header Debug LEDs CAN 82 Bus DaisyChain PWM LEDs Power Supply 3 3V 3 3V A 5V amp 3 3VREF Figure 1 1 MC56F8367EVM User Manual Rev 2 Block Diagram of the 56F8367EVM 1 2 Freescale Semico
53. h 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including wi
54. he EVM The remaining current is available for custom control applications when connected to the daughter card connectors The 56F8367EVM provides 5 0V DC regulation for the CAN interface and additional regulators The 56F8367EVM provides 3 3 DC voltage regulation for the processor memory D A ADC parallel JTAG interface and supporting logic refer to Figure 2 9 Additional voltage regulation logic provides a low noise 3 3V DC voltage reference to the processor s A D jumper JG18 and resistor R66 are provided to allow the analog and digital grounds to be isolated on the 56F8367EVM board This allows the analog ground reference point to be provided on a custom board attached to the 56F8367EVM daughter card connectors By removing R66 the AGND reference is disconnected from the 56F8367EVM s digital ground By placing a jumper on JG18 the AGND is reconnected to the 56F8367EVM s digital ground Power applied to the 56F8367EVM is indicated with a power on LED referenced as LED13 Optionally the user can provide the 2 5 DC voltage needed by the processor s core on connector J24 and disable the on chip core voltage regulator by moving the resistor at R72 to R71 Additonally four zero ohm resistors or shorting wires must be added at R67 R68 R69 and R70 to allow the external 2 5V DC to pass to the 56F8367 12 DC AC 2 Br 5 0V Power
55. in Signal Pin Signal 1 NC 2 NC 3 CANL 4 CANH 5 GND 6 NC 7 NC 8 NC 9 NC 10 NC 2 13 2 FlexCAN 2 Interface The 56F8367EVM board contains a second FlexCAN port the CAN2 RX and CAN2 TX pins on the 56F8367 These signals pass through an isolation jumper JG14 before going to the CAN physical layer interface The EVM board uses a Phillips high speed 1 0Mbps physical layer interface chip PCA82C250 Due to the 5 0V operating voltage of the CAN interface chip a pull up to 5 0V is required to level shift the transmit data output line from the 56F8367 The CAN2H and CANAL signals pass through inductors before attaching to the CAN bus connectors A primary J22 and daisy chain J23 CAN connector are provided to allow easy daisy chaining of CAN devices CAN bus termination of 120 ohms can be provided by adding a jumper to JG17 Refer to Figure 2 12 for a connection diagram and to Table 2 14 and Table 2 15 for the CAN connector signals MC56F8367EVM User Manual Rev 2 2 24 Freescale Semiconductor Preliminary MC56F8367 2 TX 1 2 9614 5 0V 1K CAN Transceiver 2 TXD 4 RXD PCA82C250 120 Figure 2 12 CAN 2 Interface Table 2 14 CAN 2 Header Description CAN Interfaces CAN 2 Bus Connector Daisy Chain CAN 2 Connector CAN 2 B
56. l Connector Description J12 Pin Signal Pin Signal 1 1 TB1 PC1 2 INDEX1 MISO1 TB2 PC2 3 SCLK1 PCO 4 1 SS1 PC3 5 GND 6 3 3V 2 15 6 Timer Channel C Expansion Connector The Timer Channel C port is a Quad Timer port attached to the Timer C expansion connector This port can be configured as a Quad Timer port or a General Purpose I O port Refer to Table 2 21 for the signals attached to the connector Table 2 21 Timer Channel C Connector Description J16 Pin Signal Pin Signal 1 PE8 2 TC1 PE9 3 GND 4 3 3V Technical Summary Rev 2 Freescale Semiconductor Preliminary 2 15 7 Timer Channel D Expansion Connector The Timer Channel D port is a Quad Timer attached to the Timer D expansion connector This port can be configured as a Quad Timer port or a General Purpose I O port Refer to Table 2 22 for the signals attached to the connector Table 2 22 Timer Channel D Connector Description J17 Pin Signal Pin Signal 1 TDO PE10 2 TD1 PE11 3 TD2 PE12 4 PE13 3 GND 4 3 3V MC56F8367EVM User Manual Rev 2 2 32 Freescale Semiconductor Preliminary 2 15 8 A D Port A Expansion Connector The eight channel Analog to Digital conversion Port A is attached to this connector Refer to Table 2 23 for connection
57. nal external oscillator frequency input connectors JG1 and JG2 Joint Test Action Group JT AG port interface connector for an external debug Host Target Interface J3 On board parallel JTAG host target interface with a connector for a PC printer port cable P1 including a disable jumper JG3 and a printer port voltage selection jumper JG19 RS 232 interface for easy connection to a host processor U4 and P2 including a disable jumper JG10 RTS and CTS RS 232 control signal access JG11 CAN interface for high speed 1 0Mbps FlexCAN communications U10 and J20 CAN bypass and bus termination J21 and JG13 Technical Summary Rev 2 Freescale Semiconductor 2 1 Preliminary CAN 2 interface for high speed 1 0Mbps FlexCAN communications 011 and J22 CAN 2 bypass and bus termination J23 and JG17 CAN 2 interface signal isolation JG14 Peripheral Daughter Card connector to allow the user to connect his own SCI SPI or GPIO compatible peripheral to the controller 11 Memory Daughter Card connector to allow the user to connect his own memory or memory device to the device J2 SCI 0 expansion connector to allow the user to connect his own SCI 0 MPIO compatible peripheral J13 SCI 1 expansion connector to allow the user to connect his own SCI 1 MPIO compatible peripheral J14 SPI expansion connector to allow the user to connect his own SPI MPIO compatible peripheral
58. nals which can be configured as GPIO Port D lines bits 0 and 1 Refer to Table 2 18 for the names of these signals Table 2 18 External Memory Control Signal Connector Description J6 Pin Signal Pin Signal 1 RD 2 IRQA 3 WR 4 IRQB 5 PS CS0 6 DS CS1 7 52 CAN2 TX 8 1 CS3 2 2 CS4 PD3 CS5 PD4 CS6 PD5 CS7 9 CLKO 10 RESET 11 GND 12 RSTO 2 15 4 Encoder 40 Quad Timer Channel A Expansion Connector The Encoder 0 Quad Timer Channel A port is an MPIO port attached to the Timer A expansion connector This port can be configured as a Quadrature Decoder interface port or as a Quad Timer port Refer to Table 2 19 for the signals attached to the connector Table 2 19 Timer A Signal Connector Description J15 Pin Signal Pin Signal 1 2 PHASEBO TA1 3 INDEXO TA2 4 TA3 5 GND 6 3 3V MC56F8367EVM User Manual Rev 2 2 30 Freescale Semiconductor Preliminary Peripheral Expansion Connectors 2 15 5 Encoder 1 SPI 1 Expansion Connector The Encoder 1 SPI 1 port is an MPIO port attached to the SPI 1 expansion connector This port can be configured as a Quadrature Decoder interface port a Serial Peripherial Interface Quad Timer port or General Purpose I O port Refer to Table 2 20 for the signals attached to the connector Table 2 20 SPI 1 Signa
59. nductor Preliminary 56F8367EVM Configuration Jumpers 1 2 56F8367EVM Configuration Jumpers Ninteen jumper groups JG1 JG19 shown in Figure 1 2 are used to configure various features on the 56F8367EVM board Table 1 1 describes the default jumper group settings JG6 464 5 467 Figure 1 2 MC56F8367 Default Jumper Options Introduction Rev 2 Freescale Semiconductor 1 3 Preliminary Table 1 1 56F8367EVM Default Jumper Options pud Comment 461 Use on board EXTAL crystal input for oscillator 1 2 2 Use on board XTAL crystal input for oscillator 1 2 Enable on board Parallel JTAG Host Target Interface NC JG4 Enable Internal Boot Mode 1 2 5 Enable A23 for external memory accesses NC JG6 Enable Crystal Mode 1 2 JG7 Enable SRAM Memory Bank 0 use CSO 1 2 JG8 Enable SRAM Memory Bank 1 use CS1 amp CS4 1 2 amp 3 4 JG9 Pass RXDO amp TXDO to RS 232 level converter 1 2 amp 3 4 JG10 Enable RS 232 output NC JG11 Pass RS 232 RST to CTS 1 2 JG12 Pass Temperature Diode to 7 1 2 JG13 CAN 1 termination selected 1 2 14 Pass CAN2 TX amp 2 to CAN tranceiver 1 2 amp 3 4 JG1
60. nstruction set Refer to these documents for detailed information about chip functionality and operation They can be found on this URL www freescale com 2 2 Program and Data Memory The 56F8367EVM contains two 128K x 16 bit Fast Static RAM banks SRAM bank 0 is controlled by CSO and SRAM bank 1 is controlled by CS1 and CS4 This provides total of 256K x 16 bits of external memory MC56F8367EVM User Manual Rev 2 2 4 Freescale Semiconductor Preliminary Program and Data Memory 2 2 1 SRAM Bank 0 SRAM bank 0 which is controlled by 50 uses a 128K x 16 bit Fast Static RAM GSI GS72116 labeled U2 for external memory expansion see the FSRAM schematic diagram in Figure 2 1 50 can be configured to use this memory bank 16 bits of Program memory Data memory or both Additionally CSO can be configured to assign this memory s size and starting address to any modulo address space This memory bank will operate with zero wait state access while the 56F8367 is running at 60MHz and can be disabled by removing the jumper at JG7 56 8367 0572116 A16 A16 D15 000 0015 RD OE WR WE PS CS0 3 3V Jumper Pin 1 2 487 Enable SRAM Jumper Removed AL Disable SRAM 5 Figure 2 1 Schematic Diagram of the External 50 Memory Interface Technical Summary Rev 2 Freescale Semiconductor 2 5 Preliminary 2 2 2 SRAM Bank 1 SRA
61. nterfaces The 56F8367EVM board contains two FlexCAN interfaces The primary CAN interface uses the CANI RX and CANI TX pins on the 56F8367 The secondary CAN interface uses the CAN2 RX and CAN2 TX pins on the 56F8367 2 131 FIexCAN 1 Interface The 56F8367EVM board contains a CAN physical layer interface chip that is attached to the FIexCAN port S CANI RX and CANI TX pins on the 56F8367 The EVM board uses a Phillips high speed 1 0Mbps physical layer interface chip PCA82C250 Due to the 5 0V operating voltage of the CAN interface chip pull up to 5 0V is required to level shift the transmit data output line from the 56F8367 The CANH and CANL signals pass through inductors before attaching to the CAN bus connectors A primary J20 and daisy chain J21 CAN connector are provided to allow easy daisy chaining of CAN devices CAN bus termination of 120 ohms can be provided by adding a jumper to JG13 Refer to Table 2 14 for the CAN connector signals and Figure 2 12 for a connection diagram 5 0V MC56F8367 1K CAN Transceiver CAN1_TX 420 CANH 1 Bus CANL xp 4 3 Connector CAN1 RX RXD J21 PCA82C250 4 Daisy Chain CAN 1 5 Connector 3 JG13 1 CAN Bus 1 2 Terminator 120 Figure 2 11 CAN 1 Interface Technical Summary Rev 2 Freescale Semiconductor 2 23 Preliminary Table 2 13 1 Header Description 420 21 P
62. ools and examples provided with the 56F8367EVM facilitate evaluation of the feature set and the benefits of the family Serving as a platform for real time software development The tool suite enables the user to develop and simulate routines download the software to on chip or on board RAM run it and debug it using a debugger via the JTAG Enhanced OnCE EOnCE port The breakpoint features of the EOnCE port enable the user to easily specify complex break conditions and to execute user developed software at full speed until the break conditions are satisfied The ability to examine and modify all user accessible registers memory and peripherals through the EOnCE port greatly facilitates the task of the developer Serving as a platform for hardware development The hardware platform enables the user to connect external hardware peripherals The on board peripherals can be disabled providing the user with the ability to reassign any and all of the processor s peripherals The EOnCE port s unobtrusive design means that all memory on the board and on the processor is available to the user Introduction Rev 2 Freescale Semiconductor 1 1 Preliminary 1 4 56 8367 Architecture The 56F8367EVM facilitates the evaluation of various features present in the 56F8367 part The 56F8367EVM can be used to develop real time software and hardware products The 56F8367EVM provides the features necessary for a user to write and debug software d
63. r V Preliminary 2 26 SCI 1 Connector Description 2 35 2 27 SPI 0 Connector Description a 5 RR URS 2 35 2 28 CAN 1 Connector Description 2 36 2 29 CAN 2 Connector Description 2422422 2 36 2 30 PWM Pott A Connector Description 2 37 2 31 PWM Port B Connector ses cn csc dnd dass 2 37 MC56F8367EVM User Manual Rev 2 vi Freescale Semiconductor Preliminary This reference manual describes in detail the hardware the 56F8367 Evaluation Module Audience This document is intended for application developers who are creating software for devices using the Freescale 56F8367 part or a member of the 56F8300 family that is compatible with this part Examples would include the 56F8346 and the 56F8357 devices Organization This manual is organized into two chapters and two appendices Chapter 1 Introduction provides an overview of the EVM and its features Chapter 2 Technical Summary describes in detail the 56F8367 hardware Appendix A 56F8367EVM Schematics contains the schematics of the MC56F8367EVM Appendix B 56F8367EVM Bill of Material provides a list of the materials used on the MC56F8367EVM board Suggested Reading More documentation on the 56F8367 and the MC56F8367EVM kit may be
64. thout limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part 7 Z freescale semiconductor Freescal
65. uminate when power is correctly applied Introduction Rev 2 Freescale Semiconductor 1 5 Preliminary MC56F8367EVM User Manual Rev 2 Freescale Semiconductor Preliminary Chapter 2 Technical Summary The 56F8367EVM is designed as a versatile development card using the 56F8367 processor allowing the creation of real time software and hardware products to support a new generation of applications in servo and motor control digital and wireless messaging digital answering machines feature phones modems and digital cameras The power of the 16 bit 56F8367 processor combined with the on board 128K x 16 bit external Program Data Static RAM SRAM 128K x 16 bit external Data Program SRAM RS 232 interface CAN interface daughter card interface peripheral expansion connectors and parallel JTAG interface makes the 56F8367EVM ideal for developing and implementing many motor controlling algorithms as well as for learning the architecture and instruction set of the 56F8367 processor The main features of the 56F8367EVM with board and schematic reference designators include e MC56F8367VPY60 16 bit 3 3V 2 5V controller operating at G0MHz 01 External Fast Static RAM FSRAM memory configured as 128 x 16 bit of memory U2 with 0 wait state at 60MHz CSO 128K 16 bit of memory U3 with 0 wait state at 60MHz via CS1 CS4 8 00MHz crystal oscillator for base processor frequency generation 1 Optio
66. us Terminator J22 and J23 Pin Signal Pin Signal 1 NC 2 NC 3 CAN2L 4 CAN2H 5 GND 6 NC 7 NC 8 NC 9 NC 10 NC Table 2 15 CAN 2 Pass Through Jumper Description JG14 Pin Signal Pin Signal 1 PDO 2 CAN2_TX 3 PD1 4 CAN2_RX Technical Summary Rev 2 Freescale Semiconductor Preliminary 2 25 2 14 Software Feature Jumpers The 56F8367EVM board contains two software feature jumpers that allow the user to select user defined software features Two GPIO port pins 4 and 7 are pulled high or low with 10K ohm resistors JG15 and JG16 Attaching a jumper between pins 1 and 2 will place a high or 1 on the port pin Attaching a jumper between pins 2 and 3 will place low or 0 on the port pin see Figure 2 13 MC56F8367 5010 550 User Jumper 0 User Jumper 1 Figure 2 13 Software Feature Jumpers MC56F8367EVM User Manual Rev 2 2 26 Freescale Semiconductor Preliminary Peripheral Expansion Connectors 2 15 Peripheral Expansion Connectors The EVM board contains a group of peripheral expansion connectors used to gain access to the resources of the 56F8367 The following signal groups have expansion connectors External Memory Address Bus A0 A23 General Purpose Port A bits 0 13 General Purpose Port E bits 2 amp 3 General Purpose Port B bit 0 7 External Memory Data Bus DO D15 General Purpose Port F bits 0
67. v NSC WA3298849SOIN 9715 AOVAYALNI LHOd 9 0188 6109 089 4 9122968 219 8288 1 10119 1se3 0012 2 0 2 JeuBis 25994 TENVOE 0 8 9 v 4 nyono TENVOE 0 8 9 v 2 TENVOE sna NWD 219 HOLOSNNOO NWO HOLOHNNOO SNA NWO 38075 ved INYO t Yyy 5 H NVSS T H 41 x 1 LEA AO S AO S 3 a n 56F8367EVM Schematics Rev 2 Appendix A 9 Freescale Semiconductor Preliminary sio 9 uuoo 1o3uBneq 6 1614 JO 6 ODSA 005 20 Aepsiny JequinN NSQ IWN gZ9 8H9SDIAN SHOLOHNNOO QHVO 0192 17 089 4 9161 9568 219 vazan 21205294 WL 1523 00 2 lt 2 de Sons gt gt olsow XL NWO 0719 OISOW VEI A0 S O
68. witches are provided for external interrupt generation as shown in Figure 2 7 S2 allows the user to generate a hardware interrupt for signal line IRQA S3 allows the user to generate a hardware interrupt for signal line IRQB These two switches allow the user to generate interrupts for his user specific programs 3 3V MC56F 8367 40K S2 E e IRQA 0 1 3 3V gt 10K 0 1uF Figure 2 7 Schematic Diagram of the User Interrupt Interface Technical Summary Rev 2 Freescale Semiconductor 2 15 Preliminary 2 9 Reset Logic is provided on the 56F8367 to generate an internal power on reset Additional reset logic is provided to support the reset signals from the JTAG connector the parallel JTAG interface and the user reset push button S1 refer to Figure 2 8 RESET _ _ RESET RESET PUSHBUTTON a MANUAL RESET 4 81 RESET Xe Figure 2 8 Schematic Diagram of the Reset Interface MC56F8367EVM User Manual Rev 2 2 16 Freescale Semiconductor Preliminary Power Supply 2 10 Power Supply The main power input to the 56F8367EVM 12 DC at 1 2A 15 through 2 1mm coax power jack This input power is rectified to provide a DC supply input This allows a user the option to use a 12V AC power supply 1 2 Amp power supply is provided with the 56F8367EVM however less than 500mA is required by t
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