FleaFPGA User Manual Rev 0.15
Contents
1. 32MByte SDRAM Organised as 16M x 16bit data width based on the Etron EM63A165BM DRAM Refer to the schematics on Appendix B for pin out details or the manufacturer s datasheet for detailed device info 64KByte SRAM New for FleaFPGA V2 5 Based on Microchip s 23LC512 Serial Quad SRAM Refer to the schematics on Appendix B for pin out details or the manufacturer s datasheet for detailed device info PS 2 Keyboard and mouse combo port Provides user input from keyboard and mouse devices with a PS 2 interface Both keyboard and mouse can be utilized at the same time though the use of a Y splitter cable PS 2 Keyboard clock data signals are connected to FPGA pins 94 and 95 while secondary mouse clock data signals are connected to FPGA pins 92 and 93 respectively USB Slave port Enables either of the following functions to be performed 1 Programming of the on board FPGA via JTAG 2 Virtual COM port Where TX out and RX in pins connected to FPGA pins 78 and 77 respectively In addition to the above USB slave port also serves as the main power supply feed for FleaFPGA Current consumption by FleaFPGA with all peripherals connected should not exceed 750mA continuous current Attention Due to the shared nature of the USB slave design users must NOT have the COM port open while performing JTAG operations on FleaFPGA Please close any open terminal programs to FleaFPGA s slave COM port before connecting to FleaFPGA using the JTA2. please skip this step and only come back when you can confirm that you have successfully load a bit file into Flash ROM fat MachXO 2 LCMXO2 000HE Device Properties Device Operation Access Mode Static RAM Cell Mode Operation SRAM Fast Program Programming Options Programming File diamond 2_x64 examples blinky blinky_blinky bit m Device Options Reinitialize part on program error vi FPGA Flash ROM programming mode In the following child window please select the Correct Access Mode Operation and Programming File options as shown below Note that for Flash ROM programming Lattice Diamond uses the jed extension bd MachXO2 LCMXO2 DOOHE Device Properties Device Operation Access Mode Flash Programming Mode Operation FLASH Program Programming Options Programming File diamond 2_x64 examples blinky blinky_blinky jed A Device Options Reinitialize part on program error FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 22 Section 7 Using Lattice Diamond Continued vii Save the current JTAG configuration by clicking on the related icon in the top menu as shown Lattice Diamond Programmer blini File Edit View Project Design P Sve NFE E m EO E save binya El E ale List viii Now we will go back to our Source tree Frame 1 and enable use of the FleaFPGA JTAG utility for use within Lattice Diamond With the mouse cursor
3. 15 Page 7 Section 5 Software Installation This section covers the basic steps needed to setup your Windows based PC for use with pre built FPGA configuration files i e files specifically compiled for FleaFPGA use using the VME file format or for end user FPGA development Software drivers Install Essentially this includes all the software drivers and utilities needed to allow the user to upload FPGA files i e VME bit files which must be specific to FleaFPGA that may be downloaded from our fleasystems com website to be programmed into their FleaFPGA platform 1 Installation of the FTDI D2XX driver as needed by the PC to recognize FleaFPGA on board JTAG interface FT230x interface chip 2 Installation of the FleaFPGA JTAG utility allowing suitable bit files to be uploaded to FleaFPGA FPGA development tools Install Essentially this includes all the elements of the basic installation as well as the ability for users to create their own custom logic designs i e user custom VME bit file on FleaFPGA This is accomplished by installing Lattice Diamond Development and configuring it for use with the FleaFPGA platform Please Note All examples contained in this guide are screenshots from a Windows7 based installation Windows 8 installation processes should be almost identical however Before you begin You will need the following e Modern PC with windows7 Ideally 64 bit version but not essential or newer in
4. Hierarchy Parsin 2 Implementation C lscc diamond 2 2 x64 examples blinky d Analysis Files Run BKM Check 2 2 p y E 3p de Programming Files 5 PIO DRC Project File C lscc diamond 2 2 x64 examples blinky ldf l Frame 1 Source tree and I Process management L Frame 2 Source Editor and reports browser File List Process Hierarchy Output Warning C lscc diamond 2 2_x64 examples blinky FleaFPGA 2v4_top vhd 18 8 18 20 INFO VHDL 1012 analyzing entity fleafpga 2v4 C lscc diamond 2 2 x64 examples blinky FleaFPGA 2v4 top vhd 94 14 94 18 INFO VHDL 1010 analyzing architecture arch C lscc his 20 INFO VHDL 10 rd FrameH3 Process status l A Frames 4 amp 5 Warning amp Error VHDL d sign 1 console messaging iS DEMOCRACIA C Iscc diamond 2 2 x64 examples blinkfuck ldf Mem Usage 124 656 K For the remainder of this section we will be referring to the numbered frames shown above to help emphasize which frame within Lattice Diamond that we re covering FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 17 Section 7 Using Lattice Diamond Continued Section 7 3 Editing HDL source files within Lattice Diamond i From the source tree Frame 1 double click on a source file of interest i e blinky vhd You should see the source contained within that file appear in the source editor Frame 2 as shown Y blinky
5. R6 T bi GPIO HEADER Dai JE oe _ AUDIO JACKPTH S c2 C15 C16 C18 C20 C22 C24 C25 C26 C27 C28 C29 C30 Nm 12nF F Page 31 0 15 ISION 7 11 2015 Rev Date e LO Xo co d I Ir p 1 I KC DICE ololo lo ololololo Ww R13 0 tuF O duF O tuF O duF O duF O 1uF O 4uF O 4uF O 4uF O 1uF 0 duF O 1uF PA EEFE SERERE v ri aa o lolo Jo jo Ofojofoje Js EMS 3 a 1036 e USB JTAG EXTRN BATT m o sala V_REG_LM141750T1223_3V3 POWER SUPPLY o o of al st ay U2 s A N ol S a AAA NI 12nF S cae x A lt OOOOO0O00000000 NE 31 iN Apo Wal J d CONN 13X2 ares 4 E S JTAG_TMS TXD caus3 46 OOOO O 0 O00 0 oO m HES STTAG TD0 TAG TDI 2 ms causo fX a mf of of f sn sa NA bel JTAG TDI VCCID CBUS1 z 1uF 10uF 1nF 250 UART RX amp axi U6 END 13 3 JTAG TCK B cNp wc v ARRE LR gt V o6 cTSi RESETA tt sn NN olola AN JTAG TCK x CBUS2 3V30UT io ds z la la la la o lolo la AP T eRT eke 8 useop usgpM 19 mE o oo jojo c oppo 4x560R Ww
6. Using Lattice Diamond Continued Section 7 4 Compiling a HDL project i Select the Process tab located at the bottom of source tree frame 1 Hierarchy C lsec diamond 2 2 x64 examples E ii You will then see new information appear in Frame 1 Process Tree Information Please tick the option boxes as they appear in the following figure synthesize Design lt Synplify Pro Translate Design Map Design Map Trace Venlog Simulation File VHDL Simulation File Place amp Route Design v Place amp Route Trace e VO Timing Analysis Export Files IBIS Model Verilog Simulation File VHDL Simulation File JEDEC File Bitstream File th t t f4 Te Please Note While Place amp Route Trace option may not be needed for this project it is critical this report be generated because it will be needed for more complex projects iii Double click on the Export Files option as highlighted in the above figure This will commence the HDL compilation process FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 19 Section 7 Using Lattice Diamond Continued iv Lattice Diamond will now compile the project Depending on the complexity of the HDL source as well as available PC resources this may take from 20 seconds or so to well over a few minutes in very complex projects If the project completed with no errors you should see the following in the process status console Frame s Outpu
7. tool Select Synplify Pro and then click Next vii Diamond will now provide you with a summary of the settings you ve made for your new project Make sure the summary matches this guide and then click Finish Congratulations You have just created your first Lattice Diamond project FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 16 Section 7 Using Lattice Diamond Continued If your new project was created successfully you should now see the following source tree appear in your Lattice Diamond project Lattice Diamond Reports File Edit View Project Design Process Tools Window Help 2 4 448 me xim BRaaaa EB E BGOts mg BEG IA usUGemom HAE File List 8 X 5 Start Page 4 blinky blinky i id LEMNO2 7000HE TGTAAE Desin Sammars 4 k ig 4 ii Project blinky project summary ial E gt Quick 4 E Process Reports Strategyl 5 Place amp Route Target Device LCMX02 7000HE 4 ER blinky 5 Signal Pad 4TG144C s pem Bevice per roam nput Files i eie e conditions Ma blinky FleaFPGA_2v4_top vhd work D Map Trace O a Je Synthesis Constraint Files 55 Place amp Route Tr Logic preference file 2v4 top lpf i ARE Physical Preference blinky blinky_blinky prf 4 ij LPF Constraint Files en e 4 E Tool Reports blinky FleaFPGA 2v4 top Ipf Product Version 2 2 0 101 Patch Version Version J Debug Files 5 VO SSO Analysis E J Script Files
8. vhd a gx w w FPleatiny FPGA Blinky LED example module vw wo deve seso Very simple example of how to create a custom logic module using HDL Following VHDL code describes an up counter with a count range of 25 millio Counter value is incremented by the external system clock which is 50MHz oi LED1 on FleaFPGA will be toggled every time the counter value reaches 25 m and reset back to zero Creation Date 15th December 2013 Author Valentin Angelovski 111 library IEEE use IEEE STD LOGI C 1164 ALL use IEEE numeric std ALL entity blinky is C port clk in STD LOGIC blink LED BUFFER STD LOGIC END blinky CJARCHITECTURE behavior OF blinky IS CJBEGIN ii Once you ve modified the source file in the source editor frame Save your work as shown in the following figure Lattice Diamond Source Editor C I File Edit View Project Design Pr A Ej qa RA eg aj 5 dal um FIERE CU g a E Save blinky vhd File List EM Please Note Any obvious errors in the source file will be reported by Lattice Diamond in the error messaging console frames 4 amp 5 Please refer to the Lattice Diamond User Manual for a detailed explanation of the topics covered in this section Next we will compile the project and then upload the resultant bit file to FleaFPGA FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 18 Section 7
9. CTION 9 ejpccc 27 SECTION 10 eji 28 SECTION 11 NOTES sisissssissossiseasessisdseisresivassissssiorroisrosasroiskrik okiti n N brna Anaa h k PDk DSa S SKN DA kN ORN DARNE aiaa 29 APPENDIX A FLEAFPGA SPECIFICATIONS siicccsvsccciscsncssssacssnnsssnscvandesaiucsowissawessewsceonddsededsoadanssdessncesunsestucedansesine 30 APPENDIX B FLEAFPGA BOARD SCHEMATICS iier oaa seo nk re S Ro citen 31 FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 2 Section 1 Warranty and legal information Product Warranty and Liability FleaFPGA Experimenters Board is warranted against defects in materials and workmanship for a period of 90 days from the date of purchase At its discretion Fleasystems will repair or replace a FleaFPGA Experimenters Board where it has found defective due to quality control or manufacturing error In the case of a valid warranty claim Fleasystems will cover the repair cost of a defective FleaFPGA Experimenters board and only pay for return shipping via standard mail In all other instances the user shall pay all shipping and repair costs This warranty does not cover product damage or destruction due to improper use i e operating FleaFPGA beyond stated electrical and thermal limits or through physical abuse The user assumes all responsibility and liability for proper and safe handling of the
10. E FT230x SSOP16 d i SE Usi MINIB SPIN RES z DEUS di ae PS 2 KEYBOARD C9 alee c17 cto cat c23 a AND MOUSE E 0 1u 1uF Your O tuF O 1uF O 1uF O 1uF File Fleatiny color sch Sheet Title Fleatiny FPGA Preliminary Valentin Angeloyski Size A3 Date 2 mar 2014 Rey 1 4 KiCad E D A eeschema 2012 01 19 BZR 3256 stable ld 1 1 i 2 3 G 5 6 Fi FleaFPGA Quick Start Guide
11. FleaFPGA Experimenters Board Quick Startup Guide Revision 0 15 PELLI iniu in M ba ri a d om P i Bl LI I Bo IND CH Pfi E XTE L emi peer din m om me hi ali PE Ex tr Mo 31113 PGA gt PCB Rev 2 4 fal 7 b p SA UT Pe oe at js Wal ZH a ls soe 1141111 141 fa p Li m r n e LL sud A A n y y om r r W E E P Lodi Li O L zl a m ir m PAE com copas cas cs CL AS Es tii eels cipes fel PT E cy E www fleasystems com Contents SECTION 1 WARRANTY AND LEGAL INFORMATION cecccceccscsccecsccecsccecssceccssecessecessesesensesensesessesssesonees 3 SECTION 2 INTRODUCTION cotorra e 4 SECTION 3 FLEAFPGA CONNECTIVITY AND BLOCK DIAGRAMS cesse eee eee eene nennen nnne nsns nennen 5 SECTION 4 FLEAFPGA HARDWARE OVERVIEW 555555555556 E aoo o ae PR ER ba Ee PER Ee t eREe P PRPRCORERCORER SOROR PPPIAPPRIN PROS FER Se FR Os euEEES 6 SECTION 5 SOFTWARE INSTALLATIQN i i o s iau rab eaae bus ee E SK Eo pp EE o EF Re SFr a onus n og aV EORR FERE EOS bir EDI S UFEFR CF SER UP aa 8 SECTION 6 LOADING PRE BUILT FIRMWARE INTO FLEAFPGA eeeeeee eee enne nennen nnn nnn nnns etse nns 13 SECTION 7 USING LATTICE DIAMOND diseuu soe s ass ha ao casts EY eR iii 14 SECTION 8 WHERE TO FROM HERE 5 i serv FEYR alcorcon 25 SE
12. G loader utility and vice versa O FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 6 Section 4 FleaFPGA hardware overview continued Peripheral Hardware details Stereo audio out Left and Right audio outputs are connected to FPGA pins 97 and 96 respectively via a low pass filter Each audio channel is designed to be driven by a PWM Pulse Width Modulated waveform from within the FPGA Analog Video Out Provides a 4bit per color RGB analog video signal out as well as the separate horizontal and vertical sync pins as per the VGA standard Can also output RGB component or even composite video out through the appropriate adapter cable and suitable user written HDL source code for the FPGA USB Host Port Uses CH376T Host interface chip Enables connection of USB mass storage as well as human interface devices to FleaFPGA USB 2 0 full speed compatible CH376T can be accessed from the FPGA side via 1 CH376T UART TX and RX pins connected to pins 107 and 89 on the FPGA respectively or 2 Through a dedicated SPI channel Please refer to Appendix B as well as the CH376T device datasheet for further details MMC SD Card Slot Supports both SPI 1 bit and 4 bit data access modes Pin 25 User GPIO Expansion Header Top View FPGA pin connections in grey Pin1 To FPGA 50 5V out FPGA 52 55 5 59 63 6 69 oin gt Pin 26 Pin 2 FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0
13. M Do R2 31 to 5 VGA_HSYNC ea P PR2A 8 5 yest LEZ x y pres hx1K2 xo 10014 VGA VSYNC 351 DRAM_CLK 24 cc cso PE2 DRAM CS s ERA KE dee 4 51 o 10 ME MAO P VCCIO1 R3 Tal D A ORAM FCAS H cas 333 933 p GND 5 i pm T ann anna S DRAM_ RAS pus gee 26 hn AE P PR5B 46Mx16 SDR DRAM 3 33 3 ae p PR7A 1 a V PR7B se MS 1 os P PROA oie G PROB x LATTICE MACHXO2 7000 e R12 E P Ut PR12A P PR12B P GND x x C3 P PR15A USB RXD h4x4K7 RESET xm CLOCK p VCCIO1 o tuF i P PR15B s FLEATINY RESET a Master_CLK FLERTINY RESET vec E out Master_CLK i C10 yy O tuF C11 yy O tuF USB HOST carsi cn cho LES G PR17A L tJ vccio3 PR17B Ne SE Q iur 9MD 05E DMRZ PL23D PR1BA u amp J PL24A PR18B 2 Y 3 p PL24B GND gt 2 p PL25A VCCIO1 amp o COR 1 veus NE PL25B PR21A R7 GND vec PR21B ES diam m USB SHIELD PR23B LL PR24A T PR24B 22uF TSSOP20 XI AUS Appendix B FleaFPGA Board Schematics i QPI SRAM Flash a ON BOARD 1 0 aja U La a 4 LED 4 2 SRAM_CS 1 C34 _ CS HOLD SI03 L 2 SRAM SIO3 pe HOG LED DNF DNF SRAM SIO1 2 S0 SI01 SCK 9 SRAM CLK 51 LED 4x270R ip SWITCH 1 we ONE SRAM SIO2 SIO2 SI SIOO SRAM SIOO Y syitcl MONENTARY 2SMD 23LC512 ere 3 SWITCH_2 SWITCH MOMENTARY 2SMD A i AUDIO OUT 2
14. MSOCache nasm PerfLogs Program Files Program Files x86 Recovery SysGCC System Volume Information tcc temp k d Lk k h h ProgramData a A h k h temp_sw ES File name FleaFPGA 2v4 top blinky FleaFPGA 2v4 top Y All Files FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 15 Section 7 Using Lattice Diamond Continued v Next you will be asked to enter in the actual Lattice FPGA you will be using in this project As FleaFPGA uses the Lattice MachXO2 7000HE 4 FPGA part in the TQFP 144 IC package style please select the options as shown in the figure below and then click Next New Project Select Device S Specify a target device for the project T Select Device Device Information Family Device Voltage 1 2V LatticeECP LCMXO2 20007E is um LatticeECP2 LCMXO2 4000HC Registers 6864 LatticeXP LCMXO2 4000HE EBR Bits 239 6K LatticeXP2 _ LCMXO2 4000ZE EBR Blocks 26 MachXO LCMXO2 7000HC Dist RAM 34912 MachXO2 LCMXO2 7000HE DSP Platform Manager LCMXO2 7000ZE z PLL 2 4 m j 4 T gt os T PCS Performance grade Package type PIO Cells 336 4 TQFP144 x APIO Operating conditions PIO Pins 115 Commercial y r Part Names LCMXO2 7000HE 4TG144C Online Data Sheet for Device vi You will now be asked to select a synthesis
15. aFPGA flash program cycle approximately 20 seconds with or over 2 minutes without a USB hub has completed successfully with a PS 2 keyboard and VGA monitor plugged in you should be able to play video pong To play use Keys A and Z control paddle 1 while Keys K and M control paddle 2 If you got this far then all JTAG support and if Section 5 2 was not skipped suitable development software for FleaFPGA should be now installed and ready for use FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 12 Section 6 Loading firmware examples into FleaFPGA Currently two methods are available to program FleaFPGA from MS Windows 1 Using the FleaFPGA JTAG utility to load suitable firmware files VME extension 2 Loading custom firmware files using Lattice Diamond which then calls our FleaFPGA JTAG utility to program the FPGA Only method 1 will be discussed in this section For users interested in custom FPGA experiments please refer to Section 7 and up Pre built vme example files can be found on the FleaFPGA projects page of our site Please Note Ensure that a suitable USB cable is plugged into your FleaFPGA board s slave USB port from the host PC Also recommended but not essential is that connection be made via a USB hub as it cuts the Flash ROM programming time from 2 minutes to 20 seconds or so i With FleaFPGA JTAG installed on your system firmware image may be loaded by 1 Double c
16. aximum allowable current draw from FleaFPGA s USB host port is 200mA e Maximum allowable current draw from FleaFPGA s GPIO header supply is 200mA e FleaFPGA Input poly fuse rated for a maximum continuous current of 750mA Mechanical e Overall dimensions 57 x 65mm overall e Two 3 3mm diameter mounting holes in opposing corners of FleaFPGA e System rated for 0 50deg c temperature ambient FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 30 33V ud o SDRAM Als TOO Ak o be U5 if i J e l gt A 3t PT sia 383 2383 x A sE eng 8238 gags F E Vadis 0 1dF 22uF AA SERES is e DATO E B zo wi SA tom DU SD MMC Ado p12 4 Y 12 A9 Dii A CD DAT3 GND4 bs 1 4 21 cMD DbI GNb2 H 4 AB Di0 GND3 14 i MMC CLK 5 CLK SCLK cno 454 A5 D7 Y A4 D6 x4 A3 D5 4x560R i2 DA VGA RED3 4 sf T x VG OUTPUT Ad D3 VGA_GRN3 51 e P VGA_BLUS n 2 op 2x Di ee x x ec UDQ
17. ck Start Guide Date 7 11 2015 Revision 0 15 Page 24 Section 8 Where to from here Once you ve followed the previous sections of this guide i e installing software tools loading firmware via JTAG using lattice Diamond etc you may want to do more with your FleaFPGA than blink an LED Developing your own HDL projects from scratch For those who are interested in developing their own HDL projects using FleaFPGA you will require the following minimum 1 Some background in digital electronics i e Boolean Algebra state machines understanding timing diagrams as well as a good understanding of logic elements i e gates flip flops tri state buffers etc are required 2 If you are not familiar with VHDL or Verilog then you will need to learn it Several reference guides are included for further study i http www ashenden com au vhdl book SG2E html li http www doulos com content products golden reference guides php Anchor Th 61209 3 It is essential that your custom HDL project knows what external hardware is connected to the FPGA Therefore your project must include both FleaFPGA_Top_level vhd and FleaFPGA Top level lpf files These can be found on www fleasystems com in the FleaFPGA projects page 4 Better understanding of the Lattice MachXO2 FPGA and Diamond tools including the in built HDL simulator i e where you can test out your project before programming the FPGA It is recommended the reade
18. e in order to be able to download the Lattice Diamond tools as well as obtain a related freeware license keyfile LICENSE DAT file via email It is recommended that you do this before installing Lattice Diamond Attention It is strongly advised to download and install the 64 bit version of this software due to the fact that all FleaFPGA example projects were built in a 64 bit operating environment hence all relevant file paths will have a x64 string added to them i Once you ve received an email from Lattice containing a freeware LICENSE DAT file You may now proceed to download the installer that matches your Windows OS version from the following link If the link is broken please navigate from www latticesemi com to find the relevant support page http www latticesemi com Products DesignSoftwareAndlP FPGAandLDS LatticeDiamond aspx li Run the Lattice Diamond installation wizard Follow the installation steps as per the wizard recommended or default settings iii Once the installation process is complete copy the LICENSE DAT file you received from Lattice Semiconductor and save it in the following directory on your computer C lscc diamond 2 2_x64 License Your Lattice Diamond software is now installed and ready to use All that remains now is installation of the FleaFPGA JTAG programming utility FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 10 Section 5 Software installation Continued Sec
19. er the overall specifications and circuit schematics respectively 2 Provide the steps needed to load firmware files into FleaFPGA via the on board USB JTAG interface 3 Provide insight into how new firmware files are created using FPGA development tools I e Lattice Diamond Please Note This document is NOT a how to guide on VHDL programming nor is it an introduction to electronics engineering It is essential that the reader already has a good understanding of basic electronics particularly of digital electronics and logic theory Many tutorials exist in print form and online for VHDL basic electrical electronic and digital logic theory Should you have any questions or feedback about this guide you may either register on our support forums http www fleasystems com forums or drop us an email from the contacts section on our site Thanks again and happy experimenting amp oincerely Valentin Angelovski www fleasystems com FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 4 Section 3 FleaFPGA connectivity and block diagrams SYSTEM CONNECTIVITY OPTIONS 12 bit Analog video out VGA or RGB component out PEEL MOSTE eee ee La JVIDEO otitis pnmo ea Pa gt gt iss mom om bere E Ss Rk Ho LES n N 4 FleaF PG EE TT PCB Rev 2 4 _ I et pbi PB2 User Programmable Push Buttons E 29 7 A E EHE ELE Fr AAMAMM 0 41441 AEREA MEE SD slot unders
20. figure below 2 Lattice Diamond Start Page Fite Edit View Project Design Process Tools Window Help New 14 File Ctrl N il m een B Project Ctri Shift N G ix Implementat A Close Ctrl F4 Strategy i Close All i T 7 Project Close Project Open PE hiria ii You should see a new project child window appear Click Next FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 14 Section 7 Using Lattice Diamond Continued iii Diamond will now ask for a project name Please enter the name Blinky in the text box as shown in the figure below and then click Next L New Project Project Name gt Enter a name for your project and specify a directory where the project EP data files will be stored Project Name blinky s Location C Iscc diamond 2 2 x64 examples bd Browse iv Next you will be asked to add any VHDL source files to the project Please tick the copy source to implementation directory box Next Click Add source and then a file import window will appear Select All files in the file extension selection and then select all the files contained within the example blinky zip file Once all the files are selected as shown below click Open Import File Gor I Organize New folder L Isc env Name Iscc 2 blinky FleaFPGA 2v4 top 5 FleaFPGA 2v4 top 16 12 2013 12 51 VHD File
21. goods Further the user indemnifies Supplier from all claims arising from the handling or use of the goods This warranty also does not cover instances where the user has JTAG programmed a firmware application into their FleaFPGA Experimenters Board that does not specifically include the following official project HDL source files FleaFPGA top 2v5 vhd and FleaFPGA top 2v5 Ipf as downloaded from the www fleasystems com FleaFPGA support page It is the responsibility of the user to ensure their custom HDL applications include these two critical source files Through the purchase of FleaFPGA Experimenters Board you agree to indemnify and hold harmless Fleasystems from any consequential damages or claims arising from or associated with use of FleaFPGA Experimenters Board If you do not agree to any of the abovementioned terms please return your FleaFPGA Experimenters Board within 90 days of purchase to obtain a full refund Legal Notice FleaFPGA experimenter board is intended to be treated as an electronic module for evaluation purposes only For commercial products intended for sale that include FleaFPGA it is the responsibility of the user to ensure their final system meets overall regulatory and compliance requirements The FleaFPGA is NOT to be used as a solution for applications deemed to be Safety critical or life support related The user shall assume all responsibility for any consequences arising from such use While every effo
22. ide ttis d Gs E qua A 1151 e Y m e vi oe fe 3 iP e 3 l 8 PY i lad x 5V DN 63 User Programmable LEDs cis INIT E issus ES ta y ER E MIS O av a 8 PR LJ H Y LEDA E LEDZ 4 MEELED 30 bs Te leis cia AN Im User programmable uL input output pins V2 5 PCB SYSTEM BLOCK DIAGRAM UART PORT USB Slave JTAG PORT VGA or TV Remote PC 12 bit resistive USB Host display USB slave mass storage HID VOP etc USB Host Interface CH376T FPGA Keyboard 4 x user LED Lattice MachX02 7000 Mouse a Y splitter 2xuser buttons Tia MMC SD MMC SD Low pass m Ere Flash drive Interface Filters T Audio out FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 5 External devices Analog Digital I O etc required Section 4 FleaFPGA hardware overview Following table describes the function of each of the FleaFPGA peripherals in further detail Please refer to the FleaFPGA schematics in Appendix B for information on electrical connection details Peripheral Hardware details User Buttons 1 and 2 are connected directly to FPGA pins 43 and 44 respectively They provide a logic low signal to the FPGA whenever a user presses a button User LEDs 1 thru 4 are connected to FPGA pins 45 47 48 and 49 respectively Each LED can be turned on by driving the related FPGA I O pin low
23. licking on a desired vme file to load from Windows Explorer 2 Starting FleaFPGA JTAG utility and then selecting a desired vme file to load Either method will work though method 1 is quicker ii FleaFPGA JTAG will now proceed to program the on board FPGA with your selected prebuilt_xyz vme bit file Program upload status screen should appear as per the following if x Ex FleaFPGA JTAG M m SA x Requesting file to process Searching for FleaFPGA found FT230X Basic UART IJTAG method bit bang write CBUS read RTS TDI TX TMS CTS TCK CB1 TDO Processing UME file C temp FleaFPGA_test ume JTAG bits clocked out in 287744 1852 time 0 26 0 bps 13325 ill Once the FleaFPGA flash program cycle is complete and a successful status message appear in the JTAG console window you should see your FleaFPGA board running the desired firmware Nothing to it really FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 13 Section 7 Using Lattice Diamond In this section you will be introduced to Lattice semiconductor s Diamond FPGA Development Environment for use with FleaFPGA Diamond allows the user to configure FleaFPGA with a custom logic functions All FPGA based logic designs are created by using a Hardware Description Language HDL of which two VHDL and Verilog are most relevant and popular Programs written using this language tell the FPGA exactly how to behave
24. ngs Use Default I O Settings J Use Custom I O Settings Cable and I O Settings Please Note Following page covers the two primary programming modes for FleaFPGA 1 Loading user firmware into the FPGA configuration SRAM User firmware can be updated an infinite number of times with a very quick upload time of 3 seconds However user firmware uploaded in this mode is NOT permanenily stored and will be lost upon power off 2 Loading user firmware into the FPGA configuration Flash ROM User firmware may be permanently committed to the FPGA using this mode However programming time is considerably longer i e 20 seconds to over 2 minutes depending whether a USB hub is used or not In addition programming cycles are limited to 100 000 times or so before the Flash ROM begins to wear out FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 21 Section 7 Using Lattice Diamond Continued v FPGA SRAM programming mode In the following child window please select the Correct Access Mode Operation and Programming File options as shown below Note that for SRAM programming Lattice Diamond uses the bit extension Warning Before you can successfully access the fast SRAM programming mode you MUST first program the FleaFPGA with a valid bit file to Flash ROM Any attempt to program FleaFPGA s configuration SRAM will simply not work otherwise If you have not yet programmed your FleaFPGA s Flash ROM
25. over the file blinky xcf in the source tree hit right click and then select Open With from the right click menu as shown below ee E blinky FleaFPGA 2v4 top Ipf J Debug Files de Script Files Li Analysis Files 4 Programming Files Open With Open Containing Folder ix Select the FleaFPGA JTAG utility from the following list as shown Click Set as Default and then Click Ok Open With Choose the program you want to use to open this file blinky xcf Programs u Add m FleaFPGA JTAG Default dd Programmer Edit Remove Set As Default Close FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 23 Section 7 Using Lattice Diamond Continued x You should now see the FleaFPGA JTAG utility console appear and begin to load FleaFPGA with the blinky LED example xi Once the programming cycle has completed and FleaFPGA JTAG has reported no errors you should now see a slow blinking LED1 on the FleaFPGA board of around once per second If you got to this point without any problems your Lattice Diamond software is now ready to create digital designs with FleaFPGA Please Note To initiate successive programming cycles to FleaFPGA via Lattice Diamond simply double click on blinky xcf or myproject xcf etc in the source tree to trigger a custom firmware file upload to FleaFPGA FleaFPGA Qui
26. r read the Lattice Diamond and MachXO2 User Guides available from www latticesemi com Exploring further HDL examples Further HDL project examples are available for FleaFPGA These can be found in the FleaFPGA project page on www fleasystems com Example projects include e USB Host CH376T to USB serial FT230x bridge test e Pong video game e 68000 CPU based System on chip e More to follow Attention Though you re free to view modify and upload these files to your FleaFPGA you need to make sure that you understand the underlying theory as outlined above It is recommended that interested readers download unzip and then copy each of the above examples into the following path on your local machine C lscc diamond 2 2_x64 examples Once you ve copied the project files start Lattice Diamond Open the desired project by selecting open project from the file menu from the abovementioned path Lattice project files use the Idf extension FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 25 Section 8 Where to from here Continued What if get stuck Users with any questions relating to FleaFPGA may 1 Read through the FAQ on the FleaFPGA project page on http www fleasystems com 2 Register on our forum http www fleasystems com forums and ask a question there 3 Send an email using the address provided in the contacts section of our site FleaFPGA Quick Start Guide Date 7 11 2015 Revi
27. rt is made to ensure the information presented is accurate Fleasystems make no such guarantee Fleasystems reserve the right to update this document without prior notice FleaFPGA PCB layout logo and related documentation are the copyright of Valentin Angelovski All trademarked product names listed herein belong to their respective trademark owners Copyright O 2013 2014 Valentin Angelovski FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 3 Section 2 Introduction Dear Experimenter Thank you for purchasing the FleaFPGA experimenters board As its name suggests FleaFPGA is built around the relatively new and exciting world of FPGA Field Programmable Gate Array Technology Unlike traditional microprocessor or microcontroller based boards FleaFPGA uses hardware oriented languages like VHDL or Verilog to describe custom digital hardware that the user may potentially wish to create inside the FPGA Through the power of FPGA a wide variety of digital circuit functions may be realized e from Counters and simple controllers through to Microprocessors Digital radio modulators Video etc Within the physical limits of the on board FPGA FleaFPGA is built around Lattice s MachXO2 7000 product Refer to the Lattice MachXO2 Datasheet for further information The aims of this startup guide are three fold 1 To provide a useful reference for the FleaFPGA platform hardware Appendices A and B cov
28. sion 0 15 Page 26 Section 9 Notes FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 27 Section 10 Notes FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 28 Section 11 Notes FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 29 Appendix A FleaFPGA V2 5 Specifications Peripheral set e Lattice MachXO2 7000HE FPGA e 32MByte 16Mx16 bit 143MHz SDR SDRAM e 64KByte 1bit SPI or 4bit Quad SPl accessible SRAM e 4096 Color VGA Component composite out e PS 2 Keyboard and mouse combo port e 3 5mm stereo audio out e USB 2 0 Host port via CH376 host interface e Separate USB slave serial port via FTDI interface Also serves as a JTAG interface for easy programming of the FPGA e 18 GPIO lines via breakout header e User push buttons x 2 e User LED x 4 e MMC SD card slot e 50MHz onboard oscillator e Optional additional serial SRAM or ROM options e Can be either USB or 3 6V battery powered if PS 2 devices are not needed e PCB Dimensions 57 x 65 mm Electrical Ratings e Typical current draw Depending on the uploaded FPGA user configuration as well as active peripherals if any Generally around 50mA 200mA range This estimate does not include power drawn from the USB host port or GPIO header e GPIO Header pins 3 3V CMOS compatible with 8mA current source sink capability Please refer to the Lattice MachXO2 datasheet for more detailed information e M
29. stalled and also web enabled Must have at least 4GBytes RAM as well as 30GBytes of free Hard Disk space minimum and one free USB port e FleaFPGA experimenters board e USB Type A to Mini B Male adapter cable e USB Hub is recommended but not essential Allows for JTAG Flash ROM programming time to be reduced from 150 seconds to 20 Reason it is not essential however is that JTAG programming of FPGA configuration SRAM is extremely quick 3 seconds in either case FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 8 Section 5 Software installation Continued Section 5 1 PC Installation of the FTDI D2XX driver i Download the driver file that matches your Windows OS version from the following link Note If the link is broken please navigate from www ftdichip com to find the relevant support page http www ftdichip com Drivers D2XX htm li Once it has downloaded unzip and run the executable installer Follow the prompts as given by the installer application FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 9 Section 5 Software installation Continued Section 5 2 Installation of Lattice Diamond FPGA Development software Please Note Users who only wish to load pre built FleaFPGA firmware files and not create their own custom digital logic designs may skip this process and proceed on to Section 5 5 Additional Note Following requires the user to register on the Lattice Semiconductor websit
30. t UFM Summary UFM Size 2046 Pages 128 2046 Bits UFM Utilization General Purpose Flash Memory Available General Purpose Flash Memory 2046 Pages Page 0 to Page 2045 Initialized UFM Pages 0 Page Done completed successfully Daadiu Section 7 5 Setting up Diamond programmer for use with FleaFPGA Please Note his section only needs to be completed once at project creation time i Make Sure your FleaFPGA s USB slave port is connected to the PC ideally via a hub but not essential ii From the small icons list in the top menu Click on the programmer icon as shown sign Process Tools Window Help GERAS T BG gsQqemnogso RER Programmer E 5B Mart age tet blink Design Summary ii You now see a child window titled Programmer Getting Started appear Select the Create a New Blank Project option and Click Ok FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 20 Section 7 Using Lattice Diamond Continued iv Now in the source editor frame you will see some FPGA programming related information see below Please scroll across until you see a column marked Operation Double click on the cell immediately below it as shown 5 Start Page Reports x 3 Programmer blinky xcf EJ 5 Device Operation Cable Settings YN o e Detect cable Cable USB2 Port FTUSB 0 Custom Port HEX Y O Setti
31. tion 5 3 Installation of the FleaFPGA JTAG programming utility In the shipping confirmation email of your FleaFPGA order you will have received the following attachment FleaFPGA JTAG Setup 7z You will see two files contained within the zip file where one of these is named FleaFPGA test vme This file is basically a pre built test firmware image to be uploaded to FleaFPGA please save the file in a temporary directory i e c temp Unzip and run FleaFPGA JTAG Setup exe installation wizard Follow the installation steps as per the wizard recommended or default settings until you arrive at the following window amp Setup FleaFPGA JTAG Utility pa Completing the FleaFPGA JTAG Utility Setup Wizard Setup has finished installing FleaFPGA JTAG Utility on your computer The application may be launched by selecting the installed icons Click Finish to exit Setup V Launch FleaFPGA JTAG Utility TENTE Make sure the Launch FleaFPGA JTAG Utility option is ticked and then click finish FleaFPGA utility will now run and request the path of ddtemd exe This file can typically be found in the following path assuming you ve installed the 64 bit version of lattice Diamond here C lscc diamond 2 2_x64 bin nt64 Please Note You only need to select the relevant file and then click Open if you have Diamond installed and plan on using it to create your own custom FPGA based logic designs If you only wish
32. to play with pre built FPGA firmware examples and do NOT have Lattice Diamond installed just click Cancel FleaFPGA Quick Start Guide Date 7 11 2015 Revision 0 15 Page 11 V vi vii re FleaFPGA JTAG Select FleaFPGA JTAG file for processing Requesting file to process Section 5 Software installation Continued FleaFPGA JTAG utility will then ask for a programming file VME file to be uploaded to the FleaFPGA board Please locate the previously saved FleaFPGA_test vme select it and then click Open e gt Computer gt Local Disk C gt temp Organize v New folder MSOCache ist ke FleaFPGA test Program Files Program Files x86 ProgramData Recovery SysGCC System Volume Information a k h k h k d k a h tcc Ll temp L temp sw 99 File name FleaFPGA_test v JTAG file xcf vme eme sa 3 TT eee FleaFPGA JTAG will now proceed to program the on board FPGA with the ready made FleaFPGA test vme bit file Program upload screen should appear as follows Hm ke FleaFPGA JTAG Tooo Requesting file to process Searching for FleaFPGA found FT230X Basic UART IJTAG method bit bang write CBUS read RTS TDI TX TMS CTS TCK CB1 TDO Processing UME file C temp FleaFPGA_test ume E 2 X JTAG bits clocked out in 287744 1852 time 0 26 0 bps 13325 Once the Fle
33. when power is applied to it Examples that are provided for use on FleaFPGA are written in VHDL Please Note Following is NOT a substitute for Lattice s own Diamond User Guide This guide only provides the reader with an insight into the steps involved in building a HDL project using Lattice software tools Interested readers are also encouraged to read through the Lattice Diamond User Guide as suggested in Section 8 By the end of this section you will hopefully gain some idea around how to create a new VHDL project within Lattice Diamond and then synthesizing i e compiling the project source into a suitable binary file to be loaded into the FPGA Programming the FPGA from within Lattice Diamond is also covered Section 7 1 Download example project source files I Download and unzip the blinky example project blinky zip from the FleaFPGA project page of www fleasystems com Contained in the zip file will be the following files FleaFPGA top 2v4 vhd Contains FleaFPGA specific interface code FleaFPGA top 2v4 lpf Contains FleaFPGA specific FPGA pinout information Blinky vhd Contains user level VHDL project source Attention When creating your own projects you must always include the first two files as they are needed to help tell Lattice Diamond what physical hardware is connected to the FPGA on FleaFPGA Section 7 2 Create a new HDL project I Start Lattice Diamond and create a new project file as shown in the
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