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CC2500 - Texas Instruments

1. PO tene 1 6 5 I 1 2 202 ceded 1 LOW POWER FEATURES 2226 ede vedere Ee 2 550 REID 2 ABBREVIATIONS 3 TABLE OF CONTENTS 4 1 ABSOLUTE MAXIMUM RATINGS 1 oreet ite saot ed eed et esee east ies veas este oot eate usi etes cesi esae endo 6 2 OPERATING CONDITIONS cccccccseeesesesesesevecesecevesesesesesevesesesesssereceseseseseveseresevesesesesesenecesecereseseserenenens 6 3 GENERAL CHARACTERISTICS cccccscsesesesesesesesesecesesesecesesesesereseseseseseseseseceseseseseseseseserssesecereseseseresenens 6 4 ELECTRICAL SPECIFICATIONS 0 ccccceeeseseseseseseceseseveseseseseseseseseseseseseseseseseseseseseseeeseseseseseseseseseresenens 7 4 1 CURRENT CONSUMPTION caen euo eso v eaae e doa euet eoo aeuo e eoo eae seva nee edes eae cde venqe edes eae serene Us 7 4 2 REREGEIVE SECTIONS eot e aes ciet ceo tese
2. 22 10 3 5 23 10 4 COMMAND STROBES 050 24 10 5 FIFO ACCESS LEN dr er 24 106 PATABLE 565 24 MICROCONTROLLER INTERFACE AND PIN 4 4 25 111 CONFIGURATION INTERFACE A E OE 25 11 2 GENERAL CONTROL AND 5 nn ren a pna ae a 25 11 3 OPTIONAL RADIO CONTROL FEATURE 2200 1 01 26 12 DATA PROGRAMMING rer tetto Qux vov cbe Eve qus 26 13 RECEIVER CHANNEL FILTER 6440040 ne mene 27 14 DEMODULATOR SYMBOL SYNCHRONIZER AND DATA DECISION ccce 27 14 1 FREQUENCY OFFSET COMPENSATION eric one sorte be nore 27 14 2 BIESYNCHRONIZATION etre 27 14 3 BYTESYNCHRBONIZATION eese dene leri REUS 28 15 PACKET HANDLING HARDWARE SUPPORT 4 28 15 41 DATA WHITENING eee tere ede
3. 8 54 30 2 SYNCHRONOUS SERIAL 8 54 31 SYSTEM CONSIDERATIONS AND GUIDELINES 00 00ssscssscsssssssssnscssesnscssseeeseeeseseeuscsuseseseeeseenseaneeees 54 31 1 SRD REGULATIONS eee eere de epe teet cde ee vc d eh Ee d dedere E e ee EVER OUR 54 31 2 FREQUENCY HOPPING AND MULTI CHANNEL 5 5 8 55 31 3 WIDEBAND MODULATION NOT USING SPREAD SPECTRUM 55 214 DATABURST TRANSMISSIONS cene emt Ue ue deae eye PE eue Que 55 31 5 CONTINUOUS TRANSMISSIONS Ue De 55 31 6 CRYSTAL DRIFT 5 eset ases a setas esas esas esas stesse 56 31 7 SPECTRUM EFFICIENT sse ese esee sees ess eue 56 31 8 TOW COST SYSTEMS eee reete ettet ree eee PvE eee heec pe ee eve euin ee e OPEN ee 56 31 9 BATTERY OPERATED SYSTEMS eeeeseeeeee e ee 56 31 10 INCREASING OUTPUT 8 8 56 32 CONFIGURATION REGISTERS 00004 000 57 32 1 CONFIGURATION REGISTER DETAILS REGISTERS WITH PRESERVED VALUES IN SLEEP STATE 61 32 2 CONFIGURATION REGISTER DETAILS REGISTERS THAT LOSE PROGRAMMING IN SLEEP 80 32 3 STATUS REGISTER DETAI 5 81 33 PACKAGE
4. If the received address matches a valid address when using infinite packet length mode and address filtering is enabled OxFF will be written into the RX FIFO followed by the address byte and then the payload data 15 3 2 Maximum Length Filtering In variable packet length mode PKTCTRLO LENGTH_CONFIG 1 the PKTLEN PACKET_LENGTH register value is used to set the maximum allowed packet length If the received length byte has a larger value than this the packet is discarded and 9 TEXAS INSTRUMENTS SWRS040C receive mode restarted regardless of the MCSM1 RXOFF_MODE setting 15 3 3 CRC Filtering The filtering of a packet when CRC check fails is enabled by setting PKTCTRL1 CRC_AUTOFLUSH 1 The CRC auto flush function will flush the entire RX FIFO if the CRC check fails After auto flushing the RX FIFO the next state depends on the MCSM1 RXOFF MODE setting PKTCTRL0 CC2400 EN must be 0 default for the CRC auto flush function to work correctly When using the auto flush function the maximum packet length is 63 bytes in variable packet length mode and 64 bytes in fixed packet length mode Note that the maximum allowed packet length is reduced by two bytes when PKTCTRL1 APPEND STATUS is enabled to make room in the RX FIFO for the two status bytes appended at the end of the packet Since the entire RX FIFO is flushed when the CRC check fails the previously received packet mus
5. Bit Field Name Reset R W Description 7 6 BS_PRE_KI 1 0 1 01 R W clock recovery feedback loop integral gain to be used before sync word is detected used to correct offsets in data rate Setting Clock recovery loop integral gain before sync word 0 00 1 01 2K 2 10 3K 3 11 4 5 4 BS_PRE_KP 1 0 2 10 R W The clock recovery feedback loop proportional gain to be used before a sync word is detected Setting Clock recovery loop proportional gain before sync word 0 00 Kp 1 01 2Kp 2 10 3Kp 3 11 4Kp 3 BS POST 1 R W The clock recovery feedback loop integral gain to be used after a sync word is detected Setting Clock recovery loop integral gain after sync word 0 Same as BS PRE 1 2 2 5 5 1 R W clock recovery feedback loop proportional gain to be used after a sync word is detected Setting Clock recovery loop proportional gain after sync word 0 Same as BS PRE KP 1 Kp 1 0 BS LIMIT 1 0 0 00 R W The saturation point for the data rate offset compensation algorithm Setting Data rate offset saturation max data rate difference 0 00 0 No data rate offset compensation performed 1 01 3 125 data rate offset 2 10 6 25 data rate offset 3 11 12 5 data rate offset SWRS040C Page 74 of 89 TEXAS INSTRUMENTS 62900 0x1B AGCCTRL2 AGC C
6. e debite leri REUS 29 15 2 exer dee ie US 29 15 3 PACKET FILTERING IN RECEIVE a n nn 31 15 4 CRGO CHECK wicca 31 15 5 PACKET HANDLING IN TRANSMIT MODE eene e e ee 32 15 6 PACKET HANDLING IN RECEIVE MODE eeeeeeen 32 15 7 PACKET HANDLING IN r E EEr essa s 33 16 MODULATION FORMATS 0s0ssssessvsossesonsovscdevsovecsbvsossesdvsosdedbesosecsevsevesdbvsdebestscsestevsossddevsssvessvesssesevsess 33 16 1 FREQUENCY SHIFT KEYING w ccccesescccccecseseecceececeesesececececeeseseeececsesesenseaececececsesnsaecececeecessaeeeeeeeees 33 16 2 MINIMUM SHIFT KEYING Q occ cccceceseececce cece eeeeeseeeeeeeeeeeeeeeueeseseeeuseusesusesusesuaueuseauseauauauaeauauauaeauenanaea 33 SWRS040C Page 4 of 89 TEXAS INSTRUMENTS 62900 16 3 AMPLITUDE pasa 34 17 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY 414 4 2 0 00000 ene 34 17 1 SYNC WORD QUALIFIER cccssssecessssceceeuececsecsececseeeceesaeeecsesaececseeeeeseueeecseaaececseseesessaeeecseaaeeeesesaeens 34 17 22 PREAMBLE QUALITY THRESHOLD sess
7. 6 0 101 6 0 R The Link Quality Indicator estimates how easily a received signal can be demodulated Calculated over the 64 symbols following the sync word 0x34 0 4 RSSI Received Signal Strength Indication Bit Field Name Reset R W Description 7 0 RSSI R Received signal strength indicator 0x35 5 MARCSTATE Main Radio Control State Machine State Bit Field Name Reset R W Description 7 5 Reserved RO 4 0 MARC STATE 4 0 R Main Radio Control FSM State Value State name State Figure 15 page 39 0 0x00 SLEEP SLEEP 1 0x01 IDLE IDLE 2 0x02 XOFF XOFF 3 0x03 VCOON MC MANCAL 4 0x04 REGON MC MANCAL 5 0x05 MANCAL MANCAL 6 0x06 VCOON FS WAKEUP 7 0x07 REGON FS WAKEUP 8 0x08 STARTCAL CALIBRATE 9 0x09 BWBOOST SETTLING 10 0x0A FS LOCK SETTLING 11 Ox0B IFADCON SETTLING 12 0x0C ENDCAL CALIBRATE 13 0x0D RX RX 14 Ox0E RX END RX 15 0x0F RX RST RX 16 0x10 TXRX SWITCH TXRX SETTLING 17 0x11 OVERFLOW OVERFLOW 18 0x12 FSTXON FSTXON 19 0x13 TX TX 20 0x14 TX END TX 21 0x15 RXTX SWITCH RXTX SETTLING 22 0x16 TXFIFO UNDERFLOW UNDERFLOW Note it is not possible to read back the SLEEP or XOFF state numbers because setting CSn low will make the chip enter the IDLE mode from the SLEEP or XOFF states SWRS040C Page 82 of 89 TEXAS INS
8. Address Register Description anne Gr 0x00 IOCFG2 GDO2 output pin configuration Yes 61 0x01 IOCFG1 GDO1 output pin configuration Yes 61 0x02 IOCFGO GDOO output pin configuration Yes 61 0x03 FIFOTHR RX FIFO and TX FIFO thresholds Yes 62 0x04 SYNC1 Sync word high byte Yes 62 0x05 SYNCO Sync word low byte Yes 62 0x06 PKTLEN Packet length Yes 62 0x07 PKTCTRL1 Packet automation control Yes 63 0x08 PKTCTRLO Packet automation control Yes 64 0x09 ADDR Device address Yes 64 0x0A CHANNR Channel number Yes 64 0x0B FSCTRL1 Frequency synthesizer control Yes 65 0x0C FSCTRLO Frequency synthesizer control Yes 65 0x0D FREQ2 Frequency control word high byte Yes 65 0 0 FREQ1 Frequency control word middle byte Yes 65 OxOF FREQO Frequency control word low byte Yes 65 0x10 MDMCFGA Modem configuration Yes 66 0x11 MDMCFG3 Modem configuration Yes 66 0x12 MDMCFG2 Modem configuration Yes 67 0x13 MDMCFG1 Modem configuration Yes 68 0x14 Modem configuration Yes 68 0x15 DEVIATN Modem deviation setting Yes 69 0x16 MCSM2 Main Radio Control State Machine configuration Yes 70 0x17 5 1 Main Radio Control State Machine configuration Yes 71 0x18 MCSMO Main Radio Control State Machine configuration Yes 72 0x19 FOCCFG Frequency Offset Compensation configuration Yes 73 Ox1A BSCFG Bit Synchronization configuration Yes 74 Ox1B AGCTRL2 AGC control Yes 75 0x1C AGCTRL1 AGC control Yes 76 0x1D AGCTRLO AGC control Yes 77 Ox1E W
9. RTK S PVQFN N20 PLASTIC QUAD FLATPACK NO LEAD le gt 4 gt Pin 1 Identifier v ing Plane gt MES Mi UUUUUIN E ES d Exposed 2n NOTES All linear dimensions are in millimeters Dimensioning and tolerancing per ASME 14 5 1994 B This drawing is subject to change without notice C QFN Quad Flatpack No Lead Package configuration The package thermal pad must be soldered to the board for thermal and mechanical performance See the Product Data Sheet for details regarding the exposed thermal pad dimensions X Texas INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products also referred to herein as are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance o
10. genio 280 t EVENTO 25 RES XOSC SWRS040C Page 77 of 89 TEXAS INSTRUMENTS 62900 0x1F WOREVTO Low Byte Event0 Timeout Bit Field Name Reset R W Description 7 0 EVENTO 7 0 107 Ox6B R W Low byte of Event 0 timeout register The default Event 0 value gives 1 0 s timeout assuming a 26 0 MHz crystal 0x20 WORCTRL Wake On Radio Control Bit Field Name Reset R W Description 7 RC_PD 1 R W Power down signal to RC oscillator When written to 0 automatic initial calibration will be performed 6 4 EVENT1 2 0 7 111 R W Timeout setting from register block Decoded to Event 1 timeout RC oscillator clock frequency equals 750 which is 34 7 36 kHz depending on crystal frequency The table below lists the number of clock periods after Event 0 before Event 1 times out Setting t eventi 0 000 4 0 111 0 115 ms 1 001 6 0 167 0 173 ms 2 010 8 0 222 0 230 ms 3 011 12 0 333 0 346 ms 4 100 16 0 444 0 462 ms 5 101 24 0 667 0 692 ms 6 110 32 0 889 0 923 ms 7 111 48 1 333 1 385 ms 3 CAL 1 R W Enables 1 or disables 0 the RC oscillator calibration 2 Reserved RO 1 0 WOR_RES 1 0 0 00 R W Controls the Event 0 resolution as well as maximum timeout of the WOR module and maximum timeout under normal RX operation Setting Resolution
11. low e Pull CSn low and wait for so to go low CHIP_RDYn e Issue the SRES strobe on the 51 line e When so goes low again reset is complete and the chip is in the IDLE state 9 TEXAS INSTRUMENTS SWRS040C 62900 XOSC and voltage regulator switched 40 us CSn Oo Figure 17 Power On Reset with SRES Note that the above reset procedure is only required just after the power supply is first turned on If the user wants to reset the 662500 after this it is only necessary to issue an SRES command strobe 19 2 Crystal Control The crystal oscillator XOSC is either automatically controlled or always if MCSMO XOSC_FORCE_ON is set In the automatic mode the XOSC will be turned off if the SXOFF or SPWD command strobes are issued the state machine then goes to XOFF or SLEEP respectively This can only be done from the IDLE state The XOSC will be turned off when is released goes high The XOSC will be automatically turned on again when goes low The state machine will then go to the IDLE state The so pin on the SPI interface must be pulled low before the SPI interface is ready to be used as described in Section 10 1 on page 22 If the XOSC is forced on the crystal will always stay on even in the SLEEP state Crystal oscillator start up time depends on crystal ESR and load capacitances The electrical specification for the crystal oscillator can be found in Section 4
12. 1 h gt o MO 7 7 2 TXDATA gt 6 H 5 H 4 2 gt 1 gt o The first TX_DATA byte is shifted in before doing the XOR operation providing the first TX_OUT 7 0 byte The second TX DATA byte is then shifted in before doing the XOR operation providing the second TX_OUT 7 0 byte TX OUTI 7 0 Figure 10 Data Whitening in TX Mode 15 2 Packet Format The format of the data packet can be configured and consists of the following items see Figure 11 e Preamble e Synchronization word e Length byte or constant programmable packet length Optional address byte e Payload e Optional 2 byte CRC data whitening _5 lt encoded decoded _ Legend Optional CRC 16 calculation Inserted automatically in TX processed and removed in RX 3 1 S e Optional user provided fields processed in TX P p p processe 2 Data field 9 processed but not removed RX gt Z o 2 ee e Unprocessed user data apart from FEC and or whitening lt 8 n bits 16 82 bits lt 8 3 8 x n bits 3 16 bits Figure 11 Packet Format SWRS040C TEXAS INSTRUMENTS Page 29 of 89 The preamble pattern is alternating sequence of ones and ze
13. Some of the sections have been re written to be easier to read without having any new info added Absolute maximum supply voltage rating increased from 3 6 V to 3 9 V FSK changed to 2 FSK throughout the document Updates to the Abbreviation table Updates to the Electrical Specifications section Added ACP OBW and blocking performance Maximum output power changed from 0 dBm to 1 dBm Added information about reduced link performance at n 2 crystal frequency Added info about RX and TX latency in serial mode Changes to the maximum RC oscillator frequency accuracy after calibration Added info about default values after reset versus optimum register settings in the Configuration Software section Changes to the SPI Interface Timing Requirements Info added about tsp pa The following figures have been changed Configuration Registers Write and Read Operations SRES Command Strobe and Register Access Types In the Register Access section the address range is changed Changes to PATABLE Access section In the Packet Format section preamble pattern is changed to 10101010 and info about bug related to turning off the transmitter in infinite packet length mode is added Added info to the Frequency Offset Compensation section Added info about the initial value of the PN9 sequence in the Data Whitening section Added info about TX FIFO underflow state in the Packet Handling in Transmit Mode section Added section Packet Handling in Firmwar
14. 1 LSB Max timeout 0 00 1 period 28 29 us 1 8 1 9 seconds 1 01 2 periods 0 89 0 92 ms 58 61 seconds 2 10 10 periods 28 30 ms 31 32 minutes 3 11 2 periods 0 91 0 94 s 16 5 17 2 hours Note that WOR RES should be 0 or 1 when using WOR because WOR RES gt 1 will give a very low duty cycle In normal RX operation all settings of WOR 5 be used 0x21 FREND1 Front End RX Configuration Bit Field Name Reset R W Description 7 6 CURRENTT 1 0 1 01 RAW Adjusts front end LNA PTAT current output 5 4 LNA2MIX_CURRENT 1 0 1 01 RAW Adjusts front end PTAT outputs 3 2 LODIV BUF CURRENT RX 1 0 1 01 R W Adjusts current in RX LO buffer LO input to mixer 1 0 MIX CURRENTT1 0 2 10 R W Adjusts current in mixer SWRS040C Page 78 of 89 TEXAS INSTRUMENTS 62900 0x22 FRENDO Front End TX configuration Bit Field Name Reset R W Description 7 6 Reserved RO 5 4 LODIV_BUF_CURRENT_TX 1 0 1 01 R W Adjusts current TX LO buffer input to PA The value to use in this field is given by the SmartRF Studio software 5 3 Reserved RO 2 0 PA POWER 2 0 0 000 R W Selects PA power setting This value is an index to the PATABLE In OOK mode this selects the PATABLE index to use when transmittin
15. Read or write n 1 bytes 62900 access is a write access R W 0 or a read access R W 1 If one byte is written to the PATABLE and this value is to be read out then must be set high before the read access in order to set the index counter back to zero Note that the content of the PATABLE is lost when entering the SLEEP state except for the first byte index 0 See Section 24 on page 46 for output power programming details Headerneg Data i Combinations xX Headergeg x Data XX Headerneg XxX Data X XK Headetiro XK X Datapyte 1 gt Figure 9 Register Access Types 11 Microcontroller Interface and Pin Configuration In a typical system 662500 will interface to a microcontroller This microcontroller must be able to e Program 202500 into different modes e Read and write buffered data e Read back status information via the 4 wire SPl bus configuration interface SI So SCLK and CSn 11 1 Configuration Interface The microcontroller uses four I O pins for the SPI configuration interface SI SO SCLK and CSn The SPI is described in Section 10 on page 21 9 TEXAS INSTRUMENTS SWRS040C 11 2 General Control and Status Pins The 002800 has two dedicated configurable pins GDOO and 2 and one shared GbO1 that can output internal status information useful for control software These pins can be used to generate interrupt
16. When RX is activated the chip will remain in receive mode until a packet is successfully received or the RX termination timer expires see Section 19 7 Note the probability that a false sync word is detected can be reduced by using PQT CS maximum sync word length and sync word qualifier mode as describe in Section 17 After a packet is successfully received the radio controller will then go to the state indicated by the MCSMI RXOFF MODE setting The possible destinations are e IDLE e FSTXON Frequency synthesizer on and ready at the TX frequency Activate TX with STX e Start sending preambles e RX Start search for a new packet Similarly when TX is active the chip will remain in the TX state until the current packet 9 TEXAS INSTRUMENTS SWRS040C 62900 has been successfully transmitted Then the state will change indicated by the MCSM1 TXOFF MODE setting The possible destinations are the same as for RX The MCU can manually change the state from RX to TX and vice versa by using the command strobes If the radio controller is currently in transmit and the SRX strobe is used the current transmission will be ended and the transition to RX will be done If the radio controller is in RX when the STX or SFSTXON command strobes are used the TX if CCA function will be used If the channel is not clear the chip will remain in RX The MCSM1 CCA MODE setting controls the conditions for clear chann
17. 28 Left Top Solder Resist Mask negative Right Top Paste Mask Circles are Vias 9 TEXAS INSTRUMENTS SWRS040C Page 51 of 89 62900 29 General Purpose Test Output Control Pins The three digital output pins GDO1 and GDO2 are general control pins configured with IOCFGO GDOO_CFG 01 IOCFG2 GDO2 respectively Table 33 shows the different signals that can be monitored on the GDO pins These signals can be used as inputs to the MCU 1 is the same pin as the So pin on the SPI interface thus the output programmed on this pin will only be valid when is high The default value for GDO1 is 3 stated which is useful when the SPI interface is shared with other devices The default value for is 135 141 kHz clock output XOSC frequency divided by 192 Since the XOSC is turned on at power on reset this can be used to clock the MCU in systems with only one crystal When the MCU is up and running it can change the clock frequency by writing to IOCFGO GDOO An on chip analog temperature sensor is enabled by writing the value 128 0x80 to the 9 TEXAS INSTRUMENTS SWRS040C IOCFGO GDOO_CFG register The voltage on the GDOO pin is then proportional to temperature See Section 4 7 on page 14 for temperature sensor specifications If the TOCFGx GDOO CFG setting is less than 0x20 and IOCFGx_GDOx_INV is 0 1 the GDOO and GDO2 pins will be hardwired
18. 7 6 Reserved RO 5 4 FS AUTOCAI 1 0 0 00 R W Automatically calibrate when going to RX or TX or back to IDLE Setting When to perform automatic calibration 0 00 Never manually calibrate using SCAL strobe 1 01 When going from IDLE to RX or TX or FSTXON When going from RX or TX back to IDLE 200 automatically Every 4 time when going from RX or TX to IDLE 3011 automatically In some automatic wake on radio WOR applications using setting 3 11 can significantly reduce current consumption 3 2 PO TIMEOUT 1 01 R W Programs the number of times the six bit ripple counter must expire after XOSC has stabilized before CHP_RDYn goes low If XOSC is on stable during power down PO TIMEOUT should be set so that the regulated digital supply voltage has time to stabilize before CHP_RDYn goes low PO TIMEOUT 2 recommended Typical start up time for the voltage regulator is 50 us If XOSC is off during power down and the regulated digital supply voltage has sufficient time to stabilize while waiting for the crystal to be stable PO TIMEOUT can be set to 0 For robust operation it is recommended to use PO TIMEOUT 2 Setting Expire count Timeout after XOSC start 0 00 1 Approx 2 3 2 4 us 1 01 16 Approx 37 39 us 2 10 64 Approx 149 155 us 3 11 256 Approx 597 620 us Exact timeout depends on crystal frequency 1 PIN
19. AE e edo vase e eae esee esu eese edet eedi tuse 9 4 3 RE TRANSMIT SECTION 1 4 4 CRYSTAL 2 0 eee tae eso tes neo dose aet ceo aos e oe east eso cesse deseas ceo 12 4 5 Low POWER RC OSCILLATOR 0 cc0cceseseeeseseseeecesesesesesecesesesesesseesesececeeesesesecesereeereeeseseseserecesesererens 12 4 6 FREQUENCY SYNTHESIZER CHARACTERISTICS ccccccecsesssceceecceesenseaececececeessaesesececsessaseeeeeecsenenteaeees 13 4 7 ANALOG TEMPERATURE SENSOR 4 0 14 4 8 DC CHARACTERISTICS T 14 4 9 POWER ONURESET 14 5 PIN CONFIGURATION 15 6 CIRCUM DESCRIPTION 17 7 APPLICATION 17 8 CONFIGURATION OVERVIEW 4 19 9 CONFIGURATION SOFTWARE 4 44 2 20 10 4 WIRE SERIAL CONFIGURATION AND DATA INTERFACE eee eene emen nennen nnne 21 CHIP STATUS BYTE acs lene et ten peer ient 22 1022 REGTER ACCESS
20. CTRL EN 0 R W Enables the pin radio control option 0 XOSC FORCE ON 0 R W Force the XOSC to stay on in the SLEEP state SWRS040C Page 72 of 89 TEXAS INSTRUMENTS 62900 0x19 FOCCFG Frequency Offset Compensation Configuration Bit Field Name Reset R W Description Reserved RO FOC_BS_CS_GATE R W If set the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the CARRIER_SENSE signal goes high 4 3 FOC_PRE_K 1 0 2 10 R W The frequency compensation loop gain to be used before a sync word is detected Setting Freq compensation loop gain before sync word K 2K 3K 4K FOC_POST_K R W The frequency compensation loop gain to be used after a sync word is detected Setting Freq compensation loop gain after sync word 0 Same as FOC_PRE_K 1 2 1 0 FOC LIMIT 1 0 2 10 R W The saturation point for the frequency offset compensation algorithm Setting Saturation point max compensated offset 0 00 01 2 10 3 11 0 no frequency offset compensation BW cuan 8 BW cuan 4 BWuan 2 Frequency offset compensation is not supported for OOK Always use FOC_LIMIT 0 with this modulation format TEXAS INSTRUMENTS SWRS040C Page 73 of 89 62900 0x1A BSCFG Bit Synchronization Configuration
21. DC Characteristics Tc 25 if nothing else stated Digital Inputs Outputs Min Max Unit Condition Note Logic 0 input voltage 0 0 7 V Logic 1 input voltage VDD 0 7 VDD V Logic 0 output voltage 0 0 5 V For up to 4 mA output current Logic 1 output voltage VDD 0 3 VDD V For up to 4 mA output current Logic 0 input current N A 50 Input equals 0 V Logic 1 input current N A 50 nA Input equals VDD Table 11 DC Characteristics 4 9 Power On Reset When the power supply complies with the requirements in Table 12 below proper Power On Reset functionality is guaranteed Otherwise the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface See Section 19 1 on page 39 for further details Parameter Min Typ Max Unit Condition Note Power ramp up time 5 ms From 0 V until reaching 1 8 V Power off time 1 ms Minimum time between power on and power off Table 12 Power on Reset Requirements SWRS040C Page 14 of 89 TEXAS INSTRUMENTS 62900 5 Pin Configuration a T o aS _ 2 2 20 19 18 17 16 O SCLK 1 15 AVDD SO GDO1 2 14 AVDD GDO2 3 13 RF_N DVDD 4 12 DCOUPL 5 11 AVDD GND N 2 5 gt x o attach pa o g7 6 8 2 R 3 Figure 1 Pinout Top View Note The exposed die attach pad must be connected to a solid ground plane as th
22. Errata Notes 1 when using SPI polling there is a small but finite probability that a single read from registers PKTSTATUS RXBYTES and TXBYTES is being corrupt The same is the case when reading the chip status byte Refer to the TI website for SW examples 6 and 7 L 8 DEVIATION _ M 2PEVIATION E The symbol encoding is shown in Table 23 Format Symbol Coding 2 FSK GFSK 0 Deviation he Deviation Table 23 Symbol Encoding for 2 FSK GFSK Modulation 16 2 Minimum Shift Keying When using MSK the complete transmission preamble sync word and payload will be MSK modulated Phase shifts are performed with a constant transition time 1 Identical to offset QPSK with half sine shaping data coding may differ Page 33 of 89 The fraction of a symbol period used to change the phase can be modified with the DEVIATN DEVIATION M setting This is equivalent to changing the shaping of the symbol The MSK modulation format implemented in 662500 inverts the sync word and data compared to e g signal generators 662300 16 3 Amplitude Modulation The supported amplitude modulation On Off Keying OOK simply turns on or off the PA to modulate 1 and 0 respectively 17 Received Signal Qualifiers and Link Quality Information 002500 has several qualifiers that can be used to increase the likelihood that a valid sync word is detected 17 1 Sync Word Q
23. External Components excluding supply decoupling capacitors 1 8V 3 6V power supply 2 a CSn Folded dipole PCB si 1 ES 2 2 2 Antenna 8 50 1 SCLK AVDD 15 e i 59 50 AVDDi4L i ano 2500 i 10131 C132 optional 39092 CC 90 H C121 5 4 DVDD DIE ATTACH PAD RF_P 12 i 1122 a 5 DCOUPL 7 Savootite Liat C123 0124 PT 122 L ES C51 8 8 925 Alternative optional Figure 3 Typical Applicati TEXAS INSTRUMENTS antenna no external AL components needed on and Evaluation Circuit excluding supply decoupling capacitors SWRS040C Page 18 of 89 62900 Component Value Manufacturer C51 100 nF 10 0402 X5R Murata GRM15 series C81 27 pF 5 0402 NPO Murata GRM15 series C101 27 pF 5 0402 NPO Murata GRM15 series C121 100 pF 5 0402 NPO Murata GRM15 series C122 1 0 pF 0 25 pF 0402 NPO Murata GRM15 series C123 1 8 pF 0 25 pF 0402 NPO Murata GRM15 series C124 1 5 pF 0 25 pF 0402 NPO Murata GRM15 series C131 100 pF 5 0402 NPO Murata GRM15 series C132 1 0 pF 30 25 pF 0402 NPO Murata GRM15 series 1121 1 2 nH 0 3 nH 0402 monolithic Murata LQG15HS series L122 1 2 nH 0 3 nH 0402 monolithic Murata LQG15HS series L131 1 2 nH 0 3 nH 0402 monolithic Murata LQG15HS series R171 5
24. GDO2 fields Preamble and sync word insertion detection may or may not be active dependent on the sync mode set by the MDMCFG2 SYNC MODE If preamble and sync word is disabled all other packet handler features and FEC should also be disabled The MCU must then handle preamble and sync word insertion detection in software If preamble and sync word insertion detection is left on all packet handling features and FEC can be used One exception is that the address filtering feature is unavailable in synchronous serial mode When using the packet handling features in synchronous serial mode the 602900 will insert and detect the preamble and sync word and the MCU will only provide get the data payload This is equivalent to the recommended FIFO operation mode 31 System Considerations and Guidelines 31 1 SRD Regulations International regulations and national laws regulate the use of radio receivers and transmitters The most important regulations for the 2 4 GHz band are EN 300 440 and EN 300 328 Europe FCC CFR47 part 15 247 and 15 249 USA and ARIB STD T66 Japan A summary of the most important 9 TEXAS INSTRUMENTS SWRS040C aspects of these regulations can be found in Application Note ANOS2 2 Please note that compliance with regulations is dependent on complete system performance It is the customer s responsibility to ensure that the system complies with regulations Page 54 of 89 31 2 F
25. OE 42 197 RX TERMINATION 0030000 43 20 25 0 43 21 FREQUENCY PROGRAMMING 2 212 2 1 1 01010000000000000000000000000000 0 44 22 4e 45 221 VCO ANDPLL SBEF CALIBRATION cccccccsccscsscccscceecocsavadeccdeccscdcesossdececceseodsacsdeceneces coceausteeneceecocssentece 45 23 55 ore ood 46 24 OUTPUT POWER PROGRAMMING cccccccsesesesesesesesecesesevesesesesecesesereseseserecesesereseseseseceseeeseceresereceresens 46 25 SELECTIVE Y o elem nce dec aces 48 26 CRYSTAL OSCILLATOR 50 260 1 REFERENCE SIGNA I 50 27 EXTERNAL RE MATCH tace eua ver 50 28 PCB LAYOUT RECOMMENDATIONS cce nene ne nene n nennen tetr reren rt ertr ener eene eene enne eene 51 29 GENERAL PURPOSE TEST OUTPUT CONTROL PINS eene eee 52 30 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION ccce eene hehehe eene nennen 54 30 1 ASYNCHRONOUS
26. R W Selects between two different strategies for LNA and LNA2 gain adjustment When 1 the LNA gain is decreased first When 0 the LNA2 gain is decreased to minimum before decreasing LNA gain 5 4 CARRIER SENSE REL THR 1 0 0 00 R W Sets the relative change threshold for asserting carrier sense Setting Carrier sense relative threshold 0 00 Relative carrier sense threshold disabled 1 01 6 dB increase RSSI value 2 10 10 dB increase in RSSI value 3 11 14 dB increase in RSSI value 3 0 CARRIER SENSE ABS THR 3 0 0 R W Sets the absolute RSSI threshold for asserting carrier 0000 sense The 2 s complement signed threshold is programmed in steps of 1 dB and is relative to the MAGN TARGET setting Setting Carrier sense absolute threshold Equal to channel filter amplitude when AGC has not decreased gain 8 1000 Absolute carrier sense threshold disabled 7 1001 7 dB below MAGN TARGET setting 1 1111 1 dB below MAGN TARGET setting 0 0000 At MAGN TARGET setting 1 0001 1 dB above MAGN TARGET setting 7 0111 7 dB above MAGN TARGET setting SWRS040C Page 76 of 89 TEXAS INSTRUMENTS 62900 0x1D AGCCTRLO AGC Control Bit Field Name Reset R W Description 7 6 HYST LEVEL 1 0 2 10 R W Sets the level of hysteresis on the magnitude deviation internal AGC signal that determines gain changes Settin
27. Supply voltage coefficient 3 Frequency drift when supply voltage changes after calibration Initial calibration time 2 ms When the RC oscillator is enabled calibration is continuously done in the background as long as the crystal oscillator is running TEXAS INSTRUMENTS Table 8 RC Oscillator Parameters SWRS040C Page 12 of 89 62900 4 6 Frequency Synthesizer Characteristics Tc 25 C VDD 3 0 V if nothing else stated All measurement results obtained using the CC2500EM reference design 4 Min figures are given using a 27 MHz crystal Typ and max figures are given using a 26 MHz crystal tolerance Parameter Min Typ Max Unit Condition Note Programmed 397 Fxosc 412 Hz 26 27 MHz crystal frequency resolution 2 Synthesizer frequency 40 ppm Given by crystal used Required accuracy including temperature and aging depends on frequency band and channel bandwidth spacing RF carrier phase noise 78 dBc Hz 50 kHz offset from carrier 78 dBc Hz 100 kHz offset from carrier 81 dBc Hz 200 kHz offset from carrier 90 dBc Hz 500 kHz offset from carrier 100 dBc Hz 1 2 offset from carrier 108 dBc Hz 2 2 offset from carrier 114 dBc Hz 5 2 offset from carrier 118 dBc Hz 10 MHz offset from carrier PLL turn on hop time 85 1 88 4 88 4 us Time from leaving the IDLE state until arriving in the RX FSTXON or TX state whe
28. com www ti com clocks interface ti com logic ti com microcontroller ti com www ti rfid com www ti com omap Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Video and Imaging E2E Community www ti com wirelessconnectivity www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com video Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2015 Texas Instruments Incorporated
29. power TX states 15 0 mA Transmit mode 6 dBm output power 21 2 mA Transmit mode 0 dBm output power 21 5 mA Transmit mode 1 dBm output power Table 4 Current Consumption SWRS040C Page 8 of 89 TEXAS INSTRUMENTS 4 2 RF Receive Section 62900 25 C VDD 3 0 V if nothing else stated All measurement results obtained using the CC2500EM reference design i4 Min Max Parameter Typ Unit Condition Note Digital channel filter 58 812 bandwidth kHz User programmable The bandwidth limits are proportional to crystal frequency given values assume a 26 0 MHz crystal 2 4 kBaud data rate sensitivity optimized 2 DEM_D CFILT_OFF 0 2 FSK 1 packet error rate 20 bytes packet length 203 kHz digital channel filter bandwidth Receiver sensitivity 104 dBm The RX current consumption be reduced by approximately 1 7 mA by setting MDMCFG2 DEM DCFILT OFF 1 The typical sensitivity is then 102 dBm and the temperature range is from 0 to 85 C The sensitivity can be improved to typically 106 dBm with MDMCFG2 DEM DCFILT 0 by programming registers TEST2 and TEST1 see page 82 The temperature range is then from 0 C to 85 C Saturation 13 dBm Adjacent channel 23 dB Desired channel 3 dB above the sensitivity limit 250 rejection kHz channel spacing Alternate channel 31 dB Desired channel 3 dB above the sensi
30. the centre of the received data This value is available in the FREQEST status register Writing the value from FREQEST into FSCTRLO FREQOFF the frequency synthesizer automatically adjusted according to the estimated frequency offset The tracking range of the algorithm is selectable as fractions of the channel bandwidth with the FOCCFG FOC_LIMIT configuration register 9 TEXAS INSTRUMENTS SWRS040C If the FOCCFG FOC_BS_CS_GATE bit is set the offset compensator will freeze until carrier sense asserts This may be useful when the radio is in RX for long periods with no traffic since the algorithm may drift to the boundaries when trying to track noise The tracking loop has two gain factors which affects the settling time and noise sensitivity of the algorithm FOCCFG FOC_PRE_K sets the gain before the sync word is detected and FOCCFG FOC_POST_K selects the gain after the sync word has been found Note that frequency offset compensation is not supported for OOK modulation 14 2 Bit Synchronization The bit synchronization algorithm extracts the clock from the incoming symbols The algorithm requires that the expected data rate is programmed as described in Section 12 on page 26 Re synchronization is performed continuously to adjust for error in the incoming symbol rate Page 27 of 89 14 3 Byte Synchronization Byte synchronization is achieved by a continuous sync word se
31. the register field PKTCTRL1 PQT A threshold of 4 for this counter is used to gate sync word detection By setting the value to zero the preamble quality qualifier of the sync word is disabled A Preamble Quality Reached signal can be observed one of the GDO pins by setting IOCFGx GDOx_CFG 8 It is also possible to determine if preamble quality is reached by checking the PQT_REACHED bit in the PKTSTATUS register This signal bit asserts when the received signal exceeds the PQT 17 3 RSSI The RSSI value is an estimate of the signal level in the chosen channel This value is based on the current gain setting in the RX chain and the measured signal level in the channel In RX mode the RSSI value can be read continuously from the RSSI status register until the demodulator detects a sync word when sync word detection is enabled At that point the RSSI readout value is frozen until the next time the chip enters the RX state The RSSI value is in dBm with resolution The RSSI update rate fass depends on the receiver filter bandwidth BW defined in Section 13 and AGCCTRLO FILTER LENGTH 2 BW f channel RSSI 8 2 FILTER _ LENGTH lf PKTCTRL1 APPEND STATUS is enabled the RSSI value at sync word detection is Page 34 of 89 automatically added to the first byte appended after the data payload The RSSI value read from the RSSI status register is a 2 s complem
32. to O 1 and the 1 pin will be hardwired to 1 0 in the SLEEP state These signals will be hardwired until the CHIP_RDYn signal goes low If the IOCFGx GDOO_CFG setting is 0x20 or higher the GDO pins will work as programmed also in SLEEP state As an example GDO1 is high impedance in all states if IOCFG1 GDO0_CFG 0x2E Page 52 of 89 62900 GDOx CFG 5 0 Description Associated to the RX FIFO Asserts when RX FIFO is filled at or above the RX FIFO threshold De asserts when RX 0 0x00 FIFO is drained below the same threshold 1 0x01 Associated to the RX FIFO Asserts when RX FIFO is filled at or above the RX FIFO threshold or the end of packet is reached De asserts when the RX FIFO is empty 2 0x02 Associated to the TX FIFO Asserts when the TX FIFO is filled at or above the TX FIFO threshold De asserts when the TX FIFO is below the same threshold Associated to the TX FIFO Asserts when TX FIFO is full De asserts when the TX FIFO is drained below theTX FIFO 3 0x03 threshold 4 0x04 Asserts when the RX FIFO has overflowed De asserts when the FIFO has been flushed 5 0x05 Asserts when the TX FIFO has underflowed De asserts when the FIFO is flushed 6 0x06 Asserts when sync word has been sent received and de asserts at the end of the packet In RX the pin will de assert when the optional address check fails or the RX
33. with the MCSMO PIN CTRL EN configuration bit 12 Data Rate Programming The data rate used when transmitting or the data rate expected in receive is programmed by the MDMCFG3 DRATE and the MDMCFG4 DRATE E configuration registers The data rate is given by the formula below As the formula shows the programmed data rate depends on the crystal frequency _ 256 DRATE _M 2 DRATE E R para T 2 J xosc The following approach can be used to find suitable values for a given data rate 20 DRATE 5 28 2 2 DRATE _E 256 DRATE M XOSC 9 TEXAS INSTRUMENTS 6202500 State changes are commanded as follows When is high the SI and SCLK is set to the desired state according to Table 18 When CSn goes low the state of sr and SCLK is latched and a command strobe is generated internally according to the control coding It is only possible to change state with this functionality That means that for instance RX will not be restarted if SI and SCLK are set to RX and toggles When is low the SI and SCLK has normal SPI functionality All pin control command strobes are executed immediately except the SPWD strobe which is delayed until CSn goes high CSn SCLK SI Function 1 X X Chip unaffected by SCLK SI 0 0 Generates SPWD strobe 0 1 Generates strobe 1 0 Generates SIDLE strobe 1 1 G
34. 002200 662300 Low Cost Low Power 2 4 GHz RF Transceiver Applications e 2400 2483 5 MHz ISM SRD band systems e Consumer electronics e Wireless game controllers Product Description The 002800 is a low cost 2 4 GHz transceiver designed for very low power wireless appli cations The circuit is intended for the 2400 2483 5 MHz ISM Industrial Scientific and Medical and SRD Short Range Device frequency band The RF transceiver is integrated with a highly configurable baseband modem The modem supports various modulation formats and has a configurable data rate up to 500 kBaud 662500 provides extensive hardware support for packet handling data buffering burst transmissions clear channel assessment link quality indication and wake on radio The main operating parameters and the 64 byte transmit receive FIFOs of 662500 can be Key Features RF Performance e High sensitivity 104 dBm at 2 4 kBaud 1 packet error rate e Low current consumption 13 3 mA in RX 250 kBaud input well above sensitivity limit e Programmable output power up to 1 dBm e Excellent receiver selectivity and blocking performance e Programmable data rate from 1 2 to 500 kBaud e Frequency range 2400 2483 5 MHz Analog Features e OOK 2 FSK GFSK and MSK supported e Suitable for frequency hopping and multi channel systems due to a fast settling 9 TEXAS INSTRUMENTS SWRS040C e Wireless audio e Wireless keyboard a
35. 0x39 0 9 VCO VC DAC Current setting from PLL calibration module 83 Ox3A OxFA TXBYTES Underflow and number of bytes in the TX FIFO 83 Ox3B OxFB RXBYTES Overflow and number of bytes in the RX FIFO 84 0x3C RCCTRL1 STATUS Last RC oscillator calibration result 84 Ox3D OxFD RCCTRLO STATUS Last RC oscillator calibration result 84 Table 36 Status Registers Overview SWRS040C Page 59 of 89 62900 Write Read Single byte Burst Single byte Burst 0x00 0x40 0x80 40xCO 0x00 2 0x01 IOCFG1 0x02 IOCFGO 0x03 FIFOTHR 0x04 SYNC1 0x05 SYNCO 0x06 PKTLEN 0x07 PKTCTRL1 0x08 PKTCTRLO 0x09 ADDR 0 0 CHANNR 0x0B FSCTRL1 0x0C FSCTRLO 0 FREQ2 FREQ 0 0 FREQO 0x10 4 0 11 MDMCFG3 2 0 12 MDMCFG2 8 0 13 MDMCFG1 0 14 MDMCFGO 8 0x15 DEVIATN 5 0x16 MCSM2 0 17 MCSM1 g 0x18 MCSMO 2 0x19 FOCCFG 8 Ox1A BSCFG 5 0 1 AGCCTRL2 5 0 1 AGCCTRL1 Ox1D AGCCTRLO 8 WOREVT1 Ox1F WOREVTO E 0x20 WORCTRL 0x21 FREND1 0x22 FRENDO 0x23 FSCAL3 0x24 FSCAL2 0x25 FSCAL1 0x26 FSCALO 0x27 RCCTRL1 0x28 RCCTRLO 0x29 FSTEST 2 PTEST 0x2B AGCTEST 0x2C TEST2 0x2D TESTI Ox2E TESTO 0 2 0 30 SRES SRES PARTNUM 0x31 SFSTXON SFSTXON VERSION 0x32 SXO
36. 15 4 2 PKTCTRLO CC2400_EN 1 If PKTCTRLO CC2400_EN 1 the CRC can be checked outlined 1 in Section 15 4 1 as well as by reading the CRC_OK flag available inthe PKTSTATUS 7 register the 7 status register from one of the GDO pins if GDOx CFG is 0x07 or 0x15 The PKTCTRL1 CRC AUTOFLUSH or data whitening cannot be used when PKTCTRLO CC2400_EN 1 15 5 Packet Handling in Transmit Mode The payload that is to be transmitted must be written into the TX FIFO The first byte written must be the length byte when variable packet length is enabled The length byte has a value equal to the payload of the packet including the optional address byte If address recognition is enabled on the receiver the second byte written to the TX FIFO must be the address byte If fixed packet length is enabled then the first byte written to the TX FIFO should be the address if the receiver uses address recognition 9 TEXAS INSTRUMENTS SWRS040C 62900 The modulator will first send the programmed number of preamble bytes If data is available in the TX FIFO the modulator will send the two byte optionally 4 byte sync word and then the payload in the TX FIFO If CRC is enabled the checksum is calculated over all the data pulled from the TX FIFO and the result is sent as two extra bytes following the payload data If the TX FIFO runs empty before the complete packet has been transmitted the radio will enter TXFIF
37. 2 Q3 Q4 Q4 User Direction of Feed Pocket Quadrants All dimensions are nominal Device Package Package SPQ Reel Reel AO BO KO P1 Pin1 Type Drawing Diameter Width mm mm mm mm Quadrant mm W1 mm CC2500RGPR QFN RGP 20 3000 330 0 12 4 4 3 4 3 1 5 8 0 12 0 Q2 Pack Materials Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 5 Jun 2015 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Drawing Pins SPQ Length mm Width mm Height mm CC2500RGPR QFN RGP 20 3000 338 1 338 1 20 6 Pack Materials Page 2 MECHANICAL DATA 5 20 PLASTIC QUAD FLATPACK NO LEAD 4 gt gt A 15 11 H 4 10 16 6 i Seating Heig is gt AD x C E x mm y 16 E v Bottom View 4203555 G 07 11 NOTES All linear dimensions are in millimeters Dimensioning and tolerancing per ASME Y14 5M 1994 This drawing is subject to change without notice QFN Quad Flatpack No Lead package configuration The package thermal pad must be soldered to the board for thermal and mechanical performance See the additional figure in the Product Data Sheet for details re
38. 250 kBaud If the threshold is set high i e only strong signals are wanted the threshold should be adjusted upwards by first reducing the MAX LNA GAIN value then the DVGA GAIN value This will reduce power consumption in the receiver front end since the highest gain settings are avoided 17 4 8 CS Relative Threshold The relative threshold detects sudden changes in the measured signal level This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor The register field AGCCTRL1 CARRIER SENSE REL is used to enable disable relative CS and to select threshold of 6 dB 10 dB or 14 dB RSSI change Page 36 of 89 17 5 Clear Channel Assessment CCA The Clear Channel Assessment CCA is used to indicate if the current channel is free or busy The current CCA state is viewable on any of the GDO pins by setting IOCFGx GDOx_ CFG 0x09 MCSM1 CCA_MODE selects the mode to use when determining CCA When the STX or SFSTXON command strobe is given while 002900 is in the RX state the TX or FSTXON state is only entered if the clear channel requirements are fulfilled The chip will otherwise remain in RX if the channel becomes available the radio will not enter TX or FSTXON state before a new strobe command is sent on the SPI interface This feature is called TX if CCA Four CCA requirements can be programmed
39. 255 OxFF broadcast SWRS040C Page 63 of 89 TEXAS INSTRUMENTS 62900 0x08 PKTCTRLO Packet Automation Control Bit Field Name Reset R W Description Reserved RO WHITE DATA R W Turn data whitening on off 0 Whitening off 1 Whitening on Data whitening can only be used when PKTCTRLO CC2400 EN O default 5 4 _ 1 0 0 00 R W Format of RX and TX data Setting Packet format 0 00 Normal mode use FIFOs for RX and TX Synchronous serial mode used for backwards 1 01 compatibility Data in on Random TX mode sends random data using PN9 2 10 generator Used for test Works as normal mode setting 0 00 in RX 3 11 Asynchronous serial mode Data in on GDOO and data out on either of the GDOO pins CC2400_EN R W Enable CC2400 support Use same CRC implementation as CC2400 PKTCTRL1 CRC_AUTOFLUSH must be 0 if PKTCTRLO CC2400 EN 1 PKTCTRLO WHITE DATA must be 0 if PKTCTRLO CC2400 EN 1 CRC EN R W 1 CRC calculation in TX and CRC check in RX enabled 0 CRC disabled for TX and RX 1 0 LENGTH CONFIG 1 0 R W Configure the packet length Setting Packet length configuration 0 00 Fixed packet length mode Length configured in PKTLEN register 1 01 Variable packet length mode Packet length configured by the first byte after sync word 2 10 Infinite packet len
40. 3 2 Soldering Information The recommendations for lead free reflow in IPC JEDE J STD 020D should be followed SWRS040C Page 85 of 89 TEXAS INSTRUMENTS 62900 34 Ordering Information Orderable Status Package Package Pins Package Eco Plan 2 Lead MSL Peak Device 1 Type Drawing Qty Finish Temp 3 CC2500RTKR Active QFN RTK 20 3000 Green RoHS amp Cu NiPdAu LEVEL3 260C no Sb Br 1 YEAR CC2500RTK Active QFN RTK 20 92 Green ROHS amp Cu NiPdAu LEVEL3 260C no Sb Br 1 YEAR Orderable Evaluation Module Description Minimum Order Quantity 662500 CC2550DK 662500 002550 Development Kit 1 CC2500EMK 601101 Development Kit 1 Figure 31 Ordering Information 1 The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free ROHS Exempt or Green ROHS amp no Sb Br please check http www ti com productcontent for the latest availabili
41. 34 E deese tere EE 34 17 4 CARRIER SENSE 35 17 5 CLEAR CHANNEL ASSESSMENT nns 37 17 6 LINK QUALITY INDICATOR LOD ccccccecssscecssscececsneeeceesaeeecsesaececeeeecsesaeeecsesaececeeseeeessaeeecsesaeeeenseaeens 37 18 FORWARD ERROR CORRECTION WITH 04 enne eene ener neni 37 18 1 FORWARD ERROR CORRECTION FEC cccesssecessesceceesseeececsaececenececeeaeeecsesaececseceeceeaeeecsesaeeeesenaeens 37 18 20 INTERLEAVING 37 19 RADIO CONTR OD cete 39 19 1 POWER ON START UP SEQUENCE cccccesessssssceeececsesseesecececeeseseeeseecceeseseeeaeecsecesesneaeeeeececeeseaseeeeeeens 39 19 2 CRYSTAL CONTROL 555556 eu etetesteeto ted vts teret eet cede 40 19 3 VOLTAGE REGULATOR 40 19 4 TD 41 19 5 WAKE ON 2020 220200000 0 011000000000000000000000000 EEESC Esera EEE NESS SEES EErEE sinets 41 19 6 TIMING roeie
42. 4 on page 12 19 3 Voltage Regulator Control The voltage regulator to the digital core is controlled by the radio controller When the chip enters the SLEEP state which is the state with the lowest current consumption the voltage regulator is disabled This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface The chip is now in the SLEEP state Setting low again will turn on the regulator and crystal Page 40 of 89 oscillator and make the chip enter the IDLE state When wake on radio is enabled the WOR module will control the voltage regulator as described in Section 19 5 19 4 Active Modes 662500 has two active modes receive and transmit These modes are activated directly by the MCU by using the SRX and STX command strobes or automatically by Wake on Radio The frequency synthesizer must be calibrated regularly 662500 has one manual calibration option using the SCAL strobe and three automatic calibration options controlled by the MCSMO FS AUTOCAL setting e Calibrate when going from IDLE to either RX or TX or FSTXON e Calibrate when going from either RX or TX to IDLE automatically e Calibrate every fourth time when going from either RX or TX to IDLE automatically If the radio goes from TX or RX to IDLE by issuing an SIDLE strobe calibration will not be performed The calibration takes a constant number of XOSC cycles see Table 28 for timing details
43. 6 1 0402 Koa RK73 series XTAL 26 0 MHz surface mount crystal NDK AT 41CD2 Table 15 Bill Of Materials for the Application Circuit Measurements have been performed with multi layer inductors from other manufacturers e g Wurth and the measurement results were the same as when using the Murata part The Gerber files for the CC2500EM reference design 4 are available from the 1 website 8 Configuration Overview 662500 can be configured to achieve optimum performance for many different applications Configuration is done using the SPI interface The following key parameters be programmed Power down power up mode Crystal oscillator power up power down Receive transmit mode RF channel selection Data rate Modulation format RX channel filter bandwidth RF output power Data buffering with separate 64 byte receive and transmit FIFOs SWRS040C TEXAS INSTRUMENTS Chipcon 258 1 8 Figure 4 CC2500EM Reference Design 41 Packet radio hardware support Forward Error Correction FEC with interleaving Data Whitening Wake On Radio WOR Details of each configuration register can be found in Section 32 starting on page 57 Figure 5 shows a simplified state diagram that explains the main 662500 states together with typical usage and current consumption For detailed information on controlling the 662500 state machine and a complete state diagr
44. 7 Reserved 0 RO 6 0 RCCTRLO 6 0 0 R W RC oscillator configuration 0x00 32 2 Configuration Register Details Registers that Lose Programming in SLEEP State 0x29 FSTEST Frequency Synthesizer Calibration Control Bit Field Name Reset R W Description 7 0 FSTEST 7 0 89 R W For test only Do not write to this register 0x59 0 2 PTEST Production Test Bit Field Name Reset R W Description 7 0 PTEST 7 0 127 R W Writing OxBF to this register makes the on chip temperature sensor 7 available in the IDLE state The default 7 value should then be written back before leaving the IDLE state Other use of this register is for test only TEXAS INSTRUMENTS SWRS040C Page 80 of 89 62900 0 2 AGCTEST AGC Test Bit Field Name Reset R W Description 7 0 AGCTEST 7 0 63 R W For test only Do not write to this register Ox3F Ox2C TEST2 Various Test Settings Bit Field Name Reset R W Description 7 0 TEST2 7 0 136 0x88 R W Set to 0x81 for improved sensitivity at data rates 3100 kBaud The temperature range is then from 0 C to 85 0x2D TEST1 Various Test Settings Bit Field Name Reset R W Description 7 0 TEST1 7 0 49 0x31 R W Set to 0x35 for improved sensitivity at data rates 3100 kBaud The temperature range is then from 0 C to 85 C Ox2
45. 85 CC2500 amp no Sb Br Samples CC2500RTK OBSOLETE VQFN RTK 20 TBD Call TI Call TI 40 to 85 CC2500 CC2500RTKR OBSOLETE VQFN RTK 20 TBD Call TI Call TI CC2500 CC2500RTKRG3 OBSOLETE VQFN RTK 20 TBD Call TI Call TI CC2500 0 The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component ha
46. Analog I O Crystal oscillator pin 2 11 AVDD Power Analog 1 8 3 6 V analog power supply connection 12 RF P RF I O Positive RF input signal to LNA in receive mode Positive RF output signal from PA in transmit mode 13 RF_N RF I O Negative RF input signal to LNA in receive mode Negative RF output signal from PA in transmit mode 14 AVDD Power Analog 1 8 3 6 V analog power supply connection 15 AVDD Power Analog 1 8 3 6 V analog power supply connection 16 GND Ground Analog Analog ground connection 17 RBIAS Analog I O External bias resistor for reference current 18 DGUARD Power Digital Power supply connection for digital noise isolation 19 GND Ground Digital Ground connection for digital noise isolation 20 SI Digital Input Serial configuration interface data input TEXAS INSTRUMENTS Table 13 Pinout Overview SWRS040C Page 16 of 89 6 Circuit Description RADIO CONTROL RF_P RF_N RBIAS XOSC Q1 5 Q2 DEMODULATOR MODULATOR 662300 SCLK SO GDO1 GDOO ATEST GDO2 FEC INTERLEAVER PACKET HANDLER DIGITAL INTERFACE TO MCU Figure 2 662500 Simplified Block Diagram A simplified block diagram of 202900 is shown in Figure 2 662500 features low IF receiver The received RF signal is amplified by the low noise amplifier LNA and down converted in quadrature and Q to the intermediate frequency IF At IF the I Q signal
47. DESCRIPTION QFN 20 cc cccsssseceesseeeeecssececeesaececseaaececaeeeceesaececseaaececseeeecessaeeeesesaeeeesenaeees 85 33 1 RECOMMENDED PCB LAYOUT FOR PACKAGE QFN 20 85 33 2 SOLDERING INFORMATION ccccccccscscscscececececsceceeecececeeeeeeecececeeeceeeceeecueeeueecueeeuaeauauauaeauaesuaeauauauananees 85 34 ORDERING INFORMATION 0 0s00csceeeseeeseseseseseseseseseseseseseseseseseseseeesesesesesesesesesesereseceseseseseeesesereseresens 86 35 E 86 36 GENERAL INFORMATION cccccccscceeseseseseseseceseseseseseseseseseeeseseseeeseceeeseseseeesesesesesereseseeeseceseseseseseseeesens 88 36 1 DOCUMENT HISTORY 88 SWRS040C Page 5 of 89 9 TEXAS INSTRUMENTS 62900 1 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 1 be violated Stress exceeding one or more of the limiting values may cause permanent damage to the device Caution ESD sensitive device Precaution should be used when handling the device in order to prevent permanent damage Parameter Min Max Unit Condition Note Supply voltage 0 3 3 9 V All supply pins must have the same voltage Voltage on any digital pin 0 3 VDD 0 3 V max 3 9 Voltage on the pin
48. E TESTO Various Test Settings Bit Field Name Reset R W Description 7 2 TESTO 7 2 2 0x02 R W The value to use in this register is given by the SmartRF Studio software 5 1 VCO SEL CAL EN 1 R W Enable VCO selection calibration stage when 1 0 TESTO 0 1 R W The value to use in this register is given by the SmartRF Studio software 5 32 3 Status Register Details 0x30 PARTNUM Chip ID Bit Field Name Reset R W Description 7 0 PARTNUM 7 0 128 0 80 R Chip part number 0x31 0xF1 VERSION Chip ID Bit Field Name Reset R W Description 7 0 VERSION 7 0 3 0x03 R Chip version number 0x32 0 2 FREQEST Frequency Offset Estimate from Demodulator Bit Field Name Reset R W Description 7 0 FREQOFF_EST R The estimated frequency offset 2 s complement of the carrier Resolution is 2 1 59 1 65 kHz range is 202 kHz to 210 kHz dependent of XTAL frequency Frequency offset compensation is only supported for 2 FSK GFSK and MSK modulation This register will read 0 when using OOK modulation TEXAS INSTRUMENTS SWRS040C Page 81 of 89 62900 0x33 0xF3 Demodulator Estimate for Link Quality Bit Field Name Reset R W Description 7 CRC_OK R The last CRC comparison matched Cleared when entering restarting RX mode Only valid if PKTCTRLO CC2400_EN 1
49. FF SXOFF FREQEST 5 0x33 SCAL SCAL Lal E 0x34 SRX SRX RSSI 0x35 STX STX MARCSTATE 5 0x36 SIDLE SIDLE WORTIME1 D 0x37 WORTIMEO 2 0x38 SWOR SWOR PKTSTATUS zo 0x39 SPWD SPWD VCO VC DAC 7 E SFRX SFRX TXBYTES 9 0x3B SFTX SFTX RXBYTES 22 0x3C SWORRST SWORRST _ RCCTRL1 STATUS 2 Ox3D SNOP SNOP ROCTRLO STATUS E Ox3E PATABLE PATABLE PATABLE PATABLE 3 g 0x3F TX FIFO TX FIFO RX FIFO RX FIFO Table 37 SPI Address Space SWRS040C Page 60 of 89 TEXAS INSTRUMENTS 62900 32 1 Configuration Register Details Registers with Preserved Values in SLEEP State 0x00 IOCFG2 2 Output Pin Configuration Bit Field Name Reset R W Description 7 Reserved RO 6 GDO2 0 R W Invert output i e select active low 1 high 0 5 0 GDO2 CFG 5 0 41 0x29 R W Default is CHIP RDYn see Table 33 on page 53 0x01 IOCFG1 1 Output Pin Configuration Bit Field Name Reset R W Description 7 GDO DS 0 R W Set high 1 or low 0 output drive strength on the GDO pins 6 GDO1 0 R W Invert output i e select active low 1 high 0 5 0 GDO1 CFG 5 0 46 OX2E R W Default is 3 state see Table 33 on page 53 0x02 IOCFGO Output Pin Configuration Bit Field Name Reset R W Description 7 TEMP SENSOR ENABLE 0 R W Enable analog temperature sensor Write 0 in all other register bits when using temp
50. FIFO overflows In TX the pin will de assert if the TX FIFO underflows 7 0x07 Asserts when a packet has been received with CRC OK De asserts when the first byte is read from the RX FIFO Only valid if PKTCTRLO CC2400_EN 1 8 0x08 Preamble Quality Reached Asserts when the PQI is above the programmed value 9 0x09 Clear channel assessment High when RSSI level is below threshold dependent on the current MODE setting 10 Lock detector output The PLL is in lock if the lock detector output has a positive transition or is constantly logic high To check for PLL lock the lock detector output should be used as an interrupt for the MCU Serial Clock Synchronous to the data in synchronous serial mode 11 0x0B In RX mode data is set up on the falling edge by 662800 when Gbox_INv 0 In TX mode data is sampled by CE2500 on the rising edge of the serial clock when 0 12 0x0C Serial Synchronous Data Output DO Used for synchronous serial mode 13 0 00 Serial Data Output Used for asynchronous serial mode 14 OxOE Carrier sense High if RSSI level is above threshold 15 OxOF OK The last CRC comparison matched Cleared when entering restarting RX mode Only valid if PKTCTRLO CC2400_EN 1 16 0x10 to Reserved used for test 21 0x15 22 0x16 HARD DATA 1 Can be used together with RX_SYMBOL_TICK for alternative serial RX output 23 0x17 HARD DATA O C
51. Four CCA requirements can be programmed e Always CCA disabled always goes to TX e f RSSI is below threshold 62900 e Unless currently receiving a packet e Both the above RSSI below threshold and not currently receiving a packet 17 6 Link Quality Indicator The Link Quality Indicator is a metric of the current quality of the received signal If PKTCTRL1 APPEND_STATUS 15 enabled the value is automatically added to the last byte appended after the payload The value can also be read from the LOI status register The LQI gives an estimate of how easily a received signal can be demodulated by accumulating the magnitude of the error between ideal constellations and the received signal over the 64 symbols immediately following the sync word LQI is best used as a relative measurement of the link quality a high value indicates a better link than what a low value does since the value is dependent on the modulation format 18 Forward Error Correction with Interleaving 18 1 Forward Error Correction FEC 002500 has built in support for Forward Error Correction FEC To enable this option set MDMCFG1 FEC_EN to 1 FEC is only supported in fixed packet length mode PKTCTRLO LENGTH_CONFIG 0 is employed on the data field and CRC word in order to reduce the gross bit error rate when operating near the sensitivity limit Redundancy is added to the transmitted data in such a way that the receiver can restore
52. L1 FREQ_IF register setting based on channel spacing and channel filter bandwidth If any frequency programming register is altered when the frequency synthesizer is running the synthesizer may give undesired response Hence the frequency programming should only be updated when the radio is in the IDLE state Note that the calibration values are maintained in SLEEP mode so the calibration is still valid after waking up from SLEEP mode unless supply voltage or temperature has changed significantly To check that the PLL is in lock the user can program register IOCFGx GDOx CFG to and use the lock detector output available on the GDOx pin as an interrupt for the MCU x 0 1 or 2 A positive transition on the GDox pin means that the PLL is in lock As an alternative the user can read register FSCAL1 The PLL is in lock if the register content is different from Ox3F Refer also to the 662500 Errata Notes 1 For more robust operation the source code could include a check so that the PLL is re calibrated until PLL lock is achieved if the PLL does not lock the first time Page 45 of 89 23 Voltage Regulators 002500 contains several on chip linear voltage regulators which generate the supply voltage needed by low voltage modules These voltage regulators are invisible to the user and can be viewed as integral parts of the various modules The user must however make sure that the absolute maximum ratings and
53. M reference design i4 Parameter Min Typ Max Unit Condition Note Current consumption in 400 nA Voltage regulator to digital part off register values retained power down modes SLEEP state All GDO pins programmed to 0x2F HW to 0 900 nA Voltage regulator to digital part off register values retained low power RC oscillator running SLEEP state with WOR enabled 92 uA Voltage regulator to digital part off register values retained XOSC running SLEEP state with 5 0 05 FORCE ON set 160 uA Voltage regulator to digital part on all other modules in power down XOFF state Current consumption 8 1 uA Automatic RX polling once each second using low power RC oscillator with 460 kHz filter bandwidth and 250 kBaud data rate PLL calibration every 4 wakeup Average current with signal in channel below carrier sense level MCSM2 RX TIME RSSl 1 35 Same as above but with signal in channel above carrier sense level 1 95 ms RX timeout and no preamble sync word found 1 4 uA Automatic RX polling every 15 second using low power RC oscillator with 460 kHz filter bandwidth and 250 kBaud data rate PLL calibration every 4 wakeup Average current with signal channel below carrier sense level MCSM2 RX_TIME_RSSI 1 34 uA Same as above but with signal in channel above carrier sense level 29 3 ms RX timeout and no preamble sync w
54. OREVT1 High byte Event 0 timeout Yes 77 Ox1F WOREVTO Low byte Event 0 timeout Yes 78 0x20 WORCTRL Wake On Radio control Yes 78 0x21 FREND1 Front end RX configuration Yes 78 0x22 FRENDO Front end TX configuration Yes 79 0x23 FSCAL3 Frequency synthesizer calibration Yes 79 0x24 FSCAL2 Frequency synthesizer calibration Yes 79 0x25 FSCAL1 Frequency synthesizer calibration Yes 80 0x26 FSCALO Frequency synthesizer calibration Yes 80 0x27 RCCTRL1 RC oscillator configuration Yes 80 0x28 RCCTRLO RC oscillator configuration Yes 80 0x29 FSTEST Frequency synthesizer calibration control No 80 0 2 PTEST Production test No 80 0x2B AGCTEST AGC test No 81 0 2 TEST2 Various test settings No 81 Ox2D TEST1 Various test settings No 81 Ox2E TESTO Various test settings No 81 Table 35 Configuration Registers Overview SWRS040C Page 58 of 89 62900 TEXAS INSTRUMENTS Details on Address Register Description Page Number 0x30 PARTNUM 662500 part number 81 0x31 OxF1 VERSION Current version number 81 0x32 OxF2 FREQEST Frequency offset estimate 81 0x33 0 Demodulator estimate for Link Quality 82 0x34 OxF4 RSSI Received signal strength indication 82 0x35 OxF5 MARCSTATE Control state machine state 82 0x36 OxF6 WORTIME1 High byte of WOR timer 83 0x37 7 WORTIMEO Low byte of WOR timer 83 0x38 OxF8 PKTSTATUS Current status and packet status 83
55. O_UNDERFLOW state The only way to exit this state is by issuing SFTX strobe Writing to the TX FIFO after it has underflowed will not restart TX mode If whitening is enabled everything following the sync words will be whitened This is done before the optional FEC Interleaver stage Whitening is enabled by setting PKTCTRLO WHITE_DATA 1 If FEC Interleaving is enabled everything following the sync words will be scrambled by the interleaver and FEC encoded before being modulated FEC is enabled by setting MDMCFG1 FEC_EN 1 15 6 Packet Handling in Receive Mode In receive mode the demodulator and packet handler will search for a valid preamble and the sync word When found the demodulator has obtained both bit and byte synchronism and will receive the first payload byte If FEC Interleaving is enabled the FEC decoder will start to decode the first payload byte The interleaver will de scramble the bits before any other processing is done to the data If whitening is enabled the data will be de whitened at this stage When variable packet length mode is enabled the first byte is the length byte The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte If fixed packet length mode is used the packet handler will accept the programmed number of bytes Next the packet handler optionally checks the address and only continues the reception if th
56. One of the following two sequences must be followed Automatic power on reset POR or manual reset Power On Start Up Sequence Page 39 of 89 19 1 1 Automatic POR A power on reset circuit is included in the 662500 The minimum requirements stated in Section 4 9 must be followed for the power on reset to function properly The internal power up sequence is completed when CHIP_RDYn goes low CHIP_RDYn is observed on the 50 pin after CSn is pulled low See Section 10 1 for more details on CHIP_RDYn When the 662500 reset is completed the chip will be in the IDLE state and the crystal oscillator will be running If the chip has had sufficient time for the crystal oscillator to stabilize after the power on reset the 50 pin will go low immediately after taking CSn low If CSn is taken low before reset is completed the SO pin will first go high indicating that the crystal oscillator is not stabilized before going low as shown in Figure 16 t__ XOSC Stable Figure 16 Power On Reset 19 1 2 Manual Reset The other global reset possibility on 662500 the SRES command strobe By issuing this strobe all internal registers and states are set to the default IDLE state The manual power up sequence is as follows see Figure 17 e Set SCLK 1 51 0 to avoid potential problems with pin control mode see Section 11 3 on page 26 e Strobe low high e Hold cSn high for at least 40 us relative to pulling
57. TRUMENTS 0x36 0 6 WORTIME1 High Byte of WOR Time 62900 Bit Field Reset R W Description 7 0 TIME 15 8 R High byte of timer value in WOR module 0x37 0xF7 WORTIMEO Low Byte of WOR Time Bit Field Name Reset R W Description 7 0 TIME 7 0 R Low byte of timer value in WOR module 0x38 OxF8 PKTSTATUS Current Status and Packet Status Bit Field Name Reset R W Description 7 CRC_OK R The last CRC comparison matched Cleared when entering restarting RX mode Only valid if PKTCTRLO CC2400 EN 1 6 CS R Carrier sense 5 PQT REACHED R Preamble Quality reached 4 CCA R Channel is clear 3 SFD R Sync word found 2 GDO2 R Current GDO2 value Note the reading gives the non inverted value irrespective what IOCFG2 GDO2 is programmed to It is not recommended to check for PLL lock by reading PKTSTATUS 2 with GDO2_CFG 0x0A 1 Reserved RO 0 GDOO R Current GDOO value Note the reading gives the non inverted value irrespective what IOCFGO GDOO INV is programmed to It is not recommended to check for PLL lock by reading PKTSTATUS 0 with GDOO_CFG 0x0A 0x39 OxF9 VCO VC DAC Current Setting from PLL Calibration Module Bit Field Name Reset R W Description 7 0 VCO VC DAC 7 0 R Status register for test only 0x3A OxFA TXBYTES Underflow and Number of B
58. X switch 48 0x30 CLK XOSC 1 49 0x31 CLK XOSC 1 5 50 0x32 XOSC 2 51 0x33 CLK_XOSC 3 52 0x34 CLK 5 4 53 0x35 CLK XOSC 6 54 0x36 CLK XOSC 8 Note There are 3 GDO pins but only one CLK XOSO n can be selected as an output at any 55 0x37 CLK XOSC 12 time If CLK_XOSC n is to be monitored on one of the pins the other two pins must 56 0x38 CLK XOSC 16 be configured to values less than 0x30 The GDOO default value is CLK XOSC 192 57 0x39 CLK XOSC 24 58 XOSC 32 59 0x3B CLK_XOSC 48 60 0x3C XOSC 64 61 0x3D XOSC 96 62 Ox3E XOSC 128 63 CLK XOSC 192 Table 33 Signal Selection x 0 1 or 2 SWRS040C Page 53 of 89 TEXAS INSTRUMENTS 62900 30 Asynchronous and Synchronous Serial Operation Several features and modes of operation have been included in the 002900 to provide backward compatibility with previous Chipcon products and other existing RF communication systems For new systems it is recommended to use the built in packet handling features as they can give more robust communication significantly offload the microcontroller and simplify software development 30 1 Asynchronous Operation For backward compatibility with systems already using the asynchronous data transfer from other Chipcon products asynchronous transfer is also included in 662500 When asynchronous
59. YTES being corrupt assuming the maximum data rate is used is approximately 80 ppm Refer to the 662500 Errata Notes 1 for more details 10 4 Command Strobes Command strobes may be viewed as single byte instructions to 202500 By addressing command strobe register internal sequences will be started These commands are used to disable the crystal oscillator enable receive mode enable wake on radio etc The 13 command strobes are listed in Table 34 on page 57 The command strobe registers are accessed by transferring a single header byte no data is being transferred That is only the R W bit the burst access bit set to 0 and the six address bits in the range 0x30 through Ox3D are written The R W bit can be either one or and will determine how the FIFO_BYTES_AVAILABLE field in the status byte should be interpreted When writing command strobes the status byte is sent on the So pin A command strobe may be followed by any other SPI access without pulling CSn high However if an SRES strobe is being issued one will have to wait for so to go low again before the next header byte can be issued as shown in Figure 8 The command strobes are executed immediately with the exception of the sPWD and the sxorr strobes that are executed when CSn goes high 50 Figure 8 SRES Command Strobe 10 5 FIFO Access The 64 byte TX FIFO and the 64 byte RX FIFO are accessed through the Ox3F add
60. alues corresponding to the next RF frequency The PLL turn on time is approximately 90 us The blanking interval between each frequency hop is then approximately 90 us The VCO current calibration result is available in FSCAL2 and is not dependent on the RF frequency Neither is the charge pump current calibration result available in FSCAL3 The same value can therefore be used for all frequencies 3 Run calibration on a single frequency at startup Next write 0 to FSCAL3 5 4 to disable the charge pump calibration After writing to FSCAL3 5 4 strobe SRX or STX with MCSMO FS_AUTOCAL 1 for each new frequency hop That is VCO current and VCO capacitance calibration is done but not charge pump current calibration When charge pump current calibration is disabled the calibration 9 TEXAS INSTRUMENTS SWRS040C 62900 time is reduced from approximately 720 us to approximately 150 us The blanking interval between each frequency hop is then approximately 240 us There is a trade off between blanking time and memory space needed for storing calibration data in non volatile memory Solution 2 above gives the shortest blanking interval but requires more memory space to store calibration values Solution 3 gives approximately 570 us smaller blanking interval than solution 1 31 3 Wideband Modulation not Using Spread Spectrum Digital modulation systems under FCC part 15 247 includes 2 FSK and GFSK modulation A maximum peak outp
61. am see Section 19 starting on page 39 Page 19 of 89 62900 Lowest power mode Most i i M register values are retained E o Typ current consumption Sleep 400nA or g00nA when SIDLE SPWD or wake on radio WOR wake on radio WOR is 4 enabled Default state when the radio is not gt receiving or transmitting Typ BN CSn 0 current consumption 1 5mA Idle a SXOFF Used for calibrating frequency PETER MET 9 synthesizer upfront entering 7 in CSn 0 P EEG receive or transmit mode can Manual freq d Crystal N RT 22 then be done quicker synth calibration SRX or STX or SFSTXON or wake on radio wor oscillator off m consumption 0 16mA Transitional state Typ current consumption 7 4mA Frequency w synthesizer startup Frequency synthesizer is turned on can optionally be SFSTXON optional calibration calibrated and then settles to the correct frequency Frequency synthesizer is on EN settling Transitional state Typ current consumption 7 4mA ready to start transmitting a Transmission starts very Frequency quickly after receiving the synthesizer on STX command strobe Typ bM _ SK current consumption 7 4mA 2 of SRX or wake on radio WOR STX 01 E N SFSTXON or RXOFF MODE 01 N 2 l
62. an be used together with RX_SYMBOL_TICK for alternative serial RX output 24 0x18 Reserved used for test 25 0x19 Reserved used for test 26 Ox1A Reserved used for test 27 0 1 PA PD Note PA PD will have the same signal level in SLEEP and TX states control an external PA or RX TX switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx 0x2F instead 28 0x10 LNA PD Note LNA PD will have the same signal level in SLEEP and RX states To control an external LNA or RX TX switch in applications where the SLEEP state is used it is recommended to use crGx 0x2F instead 29 0 10 SYMBOL TICK Can be used together with HARD DATA for alternative serial RX output 30 to Reserved used for test 35 0x23 36 0x24 WOR EVNTO 37 0x25 EVNT1 38 0x26 Reserved used for test 39 0x27 CLK 32k 40 0x28 Reserved used for test 41 0x29 CHIP RDYn 42 2 Reserved used for test 43 0 2 XOSC STABLE 44 0x2C Reserved used for test 45 0x2D GDOO 2 EN When this output is 0 is configured as input for serial TX data 46 0 2 High impedance 3 state 47 0 2 HW to 0 achieved by setting 1 Can be used to control an external LNA PA or RX T
63. arch The sync word is a 16 bit configurable field can be repeated to get a 32 bit that is automatically inserted at the start of the packet by the modulator in transmit mode The demodulator uses this field to find the byte boundaries in the stream of bits The sync word will also function as a system identifier since only packets with the correct predefined sync word will be received if the sync word detection in RX is enabled in register MDMCFG2 see Section 17 1 The sync word detector correlates against the user configured 16 or 32 bit sync word The 15 Packet Handling Hardware Support The 662500 has built in hardware support for packet oriented radio protocols In transmit mode the packet handler can be configured to add the following elements to the packet stored in the TX FIFO e programmable number of preamble bytes e A two byte synchronization sync word Can be duplicated to give a 4 byte sync word recommended It is not possible to only insert preamble or only insert a sync word e ACRC checksum computed over the data field The recommended setting is 4 byte preamble and 4 byte sync word except for 500 kBaud data rate where the recommended preamble length is 8 bytes In addition the following can be implemented on the data field and the optional 2 byte CRC checksum e Whitening of the data with a PN9 sequence e Forward error correction by the use of interleaving and coding of the data convolutio
64. art up and keeps the drive level to a minimum The ESR of the crystal should be within the specification in order to ensure a reliable start up see Section 4 4 on page 12 XOSC_Q1 XOSC_Q2 XTAL csi Figure 27 Crystal Oscillator Circuit Component C 10 pF 13 Pf C 16 pF C81 15 pF 22 pF 27 pF C101 15 pF 22 pF 27 pF Table 32 Crystal Oscillator Component Values 26 1 Reference Signal The chip can alternatively be operated with a reference signal from 26 to 27 MHz instead of a crystal This input clock can either be a full swing digital signal O V to VDD or a sine wave of maximum 1 V peak peak amplitude The reference signal must be connected to the 27 External RF Match The balanced RF input and output of 662500 share two common pins and are designed for a simple low cost matching and balun network on the printed circuit board The receive and transmit switching at the 662500 front end is controlled by a dedicated on chip function eliminating the need for an external RX TX switch A few passive external components combined with the internal RX TX switch termination 9 TEXAS INSTRUMENTS SWRS040C XOSC_Q1 input The sine wave must be connected to xosc Q1 using serial capacitor When using a full swing digital signal this capacitor can be omitted The 5 Q2 line must be left un connected C81 and C101 can be omitted when using a reference signal circu
65. ation registers can be both written to and read The R W bit controls if the register should be written to or read When writing to registers the status byte is sent on the So pin each time a header byte or data byte is transmitted on the SI pin When reading from registers the status byte is sent on the 50 pin each time a header byte is transmitted on the pin Registers with consecutive addresses can be accessed in an efficient way by setting the 9 TEXAS INSTRUMENTS SWRS040C burst bit B in the header byte The address bits As set the start address internal address counter This counter is incremented by one each new byte every 8 clock pulses The burst access is either a read or a write access and must be terminated by setting CSn high For register addresses in the range 0x30 Ox3D the burst bit is used to select between status registers burst bit is one and command strobes burst bit is zero see Section 10 4 below Because of this burst access is not available for status registers and they must be accessed one at a time The status registers can only be read 10 3 SPI Read When reading register fields over the SPI interface while the register fields are updated Page 23 of 89 by the radio hardware e g MARCSTATE or TXBYTES there is small but finite probability that a single read from the register is being corrupt As an example the probability of any single read from TXB
66. ble 31 contains recommended PATABLE settings for various output levels frequency bands See Section 10 6 on page 24 for PATABLE programming details The SmartRF Studio software 5 should be used to obtain optimum PATABLE settings for various output powers PATABLE must be programmed in burst mode if writing to other entries than PATABLE 0 OOK modulation Note that all content of the PATABLE except for the first byte index 0 is lost when entering the SLEEP state Page 46 of 89 2 FSK GFSK MSK PATABLE 7 7 0 PATABLE 9 7 0 Not used PATABLE 5 7 0 Not used PATABLE 4 7 0 Not used PATABLE 3 7 0 Not used PATABLE 2 7 0 Not used PATABLE 1 7 0 Not used PATABLE OJ 7 0 Not used Index into PATABLE 7 0 Output power setting 000 OOK 62900 Not used Not used Not used Not used Not used Not used Output power setting for logic 1 lt q Output power setting for logic FRENDO PA POWER 2 0 001 Figure 21 PA_POWER and PATABLE Default power setting Output power typical dBm Current consumption typical mA 0xC6 12 11 1 Table 30 Output Power and Current Consumption for Default PATABLE Setting O
67. calibrate frequency synthesizer if MCSMO FS_AUTOCAL 1 If in RX with CCA Go to a wait state where only the synthesizer is running for quick RX TX turnaround 0x32 SXOFF Turn off crystal oscillator 0x33 SCAL Calibrate frequency synthesizer and turn it off SCAL can be strobed from IDLE mode without setting manual calibration mode MCSMO FS_AUTOCAL 0 0x34 SRX Enable RX Perform calibration first if coming from IDLE and MCSMO FS_AUTOCAL 1 0x35 STX In IDLE state Enable TX Perform calibration first if MCSM0 FS AUTOCAL 1 If in RX state and CCA is enabled Only go to TX if channel is clear 0x36 SIDLE Exit RX TX turn off frequency synthesizer and exit Wake On Radio mode if applicable 0x38 SWOR Start automatic RX polling sequence Wake on Radio as described in Section 19 5 if WORCTRL RC_PD 0 0x39 SPWD Enter power down mode when goes high Ox3A SFRX Flush the RX FIFO buffer Only issue SFRX in IDLE or RXFIFO_OVERFLOW states Ox3B SFTX Flush the TX FIFO buffer Only issue 5 in IDLE or UNDERFLOW states Ox3C SWORRST Reset real time clock to Event1 value Ox3D SNOP No operation May be used to get access to the chip status byte Table 34 Command Strobes SWRS040C TEXAS INSTRUMENTS Page 57 of 89 62900 TEXAS INSTRUMENTS
68. e In the PQT section a change is made as to how much the counter decreases The RSSI value is in dBm and not dB The whole CS Absolute Threshold section has been re written and the equation calculating the threshold has been removed Added info in the CCA section on what happens if the channel is not clear Added info to the section for better understanding Removed all references to the voltage regulator in relation with the CHP_RDYn signal as this signal is only related to the crystal Removed references to the voltage regulator in the figures Power On Reset and Power On Reset with SRES Changes to the SI line in the Power On Reset with SRES figure Added info on the three automatic calibration options Added info about minimum sleep time and references to App Note 047 together with info about calibration of the RC oscillator The figure Event 0 and Event 1 Relationship is changed for better readability Info added to the RC Oscillator and Timing section related to reduced calibration time The Output Power Programming section has been changed Only 1 PATABLE entry used for 2 FSK GFSK MSK and 2 PATABLE entries used for OOK Added info about PATABLE when entering SLEEP mode New POWER and PATABLE figure Added section on PCB Layout Recommendations In section General Purpose Test Output Control Pins Added info on GDO pins in SLEEP state Asynchronous transparent mode is called asynchronous serial mode throughout the docu
69. e MDMCFG2 DEM DCFILT OFF 0 MDMCFG2 DEM DCFILT OFF 1 cannot be used for data rates 5250 kBaud MSK 196 packet error rate 20 bytes packet length 812 kHz digital channel filter bandwidth Receiver sensitivity 83 dBm Saturation 18 dBm Adjacent channel rejection 14 dB Desired channel 3 dB above the sensitivity limit 1 MHz channel spacing Alternate channel rejection 25 dB Desired channel 3 dB above the sensitivity limit 1 MHz channel spacing See Figure 26 for plot of selectivity versus frequency offset Blocking Wanted signal 3 dB above sensitivity level 10 MHz offset 40 dB Compliant with ETSI EN 300 440 class 2 receiver 20 MHz offset 48 requirements 50 MHz offset 50 dB General Spurious emissions 25 MHz 1 GHz 57 dBm Above 1 GHz 47 dBm RX latency 9 bit Serial operation Time from start of reception until data oes on the receiver data output pin is equal to 9 Table 5 RF Receive Section SWRS040C Page 10 of 89 TEXAS INSTRUMENTS 62900 4 3 RF Transmit Section Tc 25 C VDD 3 0 V 0 dBm if nothing else stated All measurement results obtained using the CC2500EM reference design 4 Parameter Min Typ Max Unit Condition Note Differential load 80 74 Q Differential impedance as seen from the RF port RF_P and impedance RF_N towards the antenna Follow the CC2500EM reference design 4 available from the TI w
70. e address matches If automatic CRC check is enabled the packet handler computes CRC and matches it with the appended CRC checksum At the end of the payload the packet handler will optionally write two extra packet status Page 32 of 89 bytes that contain CRC status link quality indication and RSSI value 15 7 Packet Handling in Firmware When implementing a packet oriented radio protocol in firmware the MCU needs to know when a packet has been received transmitted Additionally for packets longer than 64 bytes the RX FIFO needs to be read while in RX and the TX FIFO needs to be refilled while in TX This means that the MCU needs to know the number of bytes that can be read from or written to the RX FIFO and TX FIFO respectively There are two possible solutions to get the necessary status information a Interrupt driven solution In both RX and TX one can use one of the GDO pins to give an interrupt when a sync word has been received transmitted and or when a complete packet has been received transmitted IOCFGx 0x06 In addition there are two configurations for the IOCFGx register that are associated with the RX FIFO rocFGx 0x00 and 0 01 and two that are associated with the TX FIFO 0 02 and 0 03 that can be used as interrupt sources to provide 16 Modulation Formats 662500 supports amplitude frequency and phase shift modulation formats The desired modulation format is s
71. e on radio functionality for automatic low power RX polling e Separate 64 byte RX and TX data FIFOs enables burst mode data transmission SWRS040C TEXAS INSTRUMENTS 62900 Few external components Complete on chip frequency synthesizer no external filters or RF switch needed Green package RoHS compliant and no antimony or bromine Small size QLP 4x4 mm package 20 pins Suited for systems compliant with EN 300 328 and EN 300 440 class 2 Europe FCC CFR47 Part 15 US and ARIB STD T66 Japan Support for asynchronous and synchronous serial receive transmit mode for backwards compatibility with existing radio communication protocols Page 2 of 89 Abbreviations Abbreviations used in this data sheet are described below ACP ADC AFC AGC AMR ARIB BER BT CCA CFR CRC CS CW DC DVGA ESR FCC FEC FIFO FHSS 2 FSK GFSK VQ ISM LBT LC LNA LO LSB MCU Adjacent Channel Power MSB Analog to Digital Converter MSK Automatic Frequency Offset Compensation NA Automatic Gain Control NRZ Automatic Meter Reading OOK Association of Radio Industries and Businesses PA Bit Error Rate PCB Bandwidth Time product PD Clear Channel Assessment PER Code of Federal Regulations PLL Cyclic Redundancy Check POR Carrier Sense Continuous Wave Unmodulated Carrier PQT Direct Current RCOSC Digital Variable Gain Amplifier QPSK Equivalent Series Resistance QLP Federal Communications Com
72. e packet length is defined as the payload data excluding the length byte and the optional CRC The PKTLEN register is used to set the maximum packet length allowed in RX Any packet received with a length byte with a value greater than PKTLEN will be discarded With PKTCTRLO LENGTH_CONFIG 2 the packet length is set to infinite and transmission and reception will continue until turned off manually As described in the next section this can be used to support packet formats with different length configuration than natively supported by 002800 One should make sure that TX mode is not turned off during the transmission of the first half of any byte Refer 9 TEXAS INSTRUMENTS SWRS040C 62900 to the 002000 Errata Notes 1 for more details Note that the minimum packet length supported excluding the optional length byte and CRC is one byte of payload data 15 2 1 Arbitrary Length Field Configuration The packet length register PKTLEN can be reprogrammed during receive and transmit In combination with fixed packet length mode PKTCTRLO LENGTH_CONFIG 0 this opens the possibility to have a different length field configuration than supported for variable length packets in variable packet length mode the length byte is the first byte after the sync word At the start of reception the packet length is set to a large value The MCU reads out enough bytes to interpret the length field in the packet Then t
73. e sets the desired signal level in the channel into the demodulator Increasing this value reduces the headroom for blockers and therefore close in selectivity It is strongly recommended to use SmartRF Studio 5 to generate the correct MAGN_TARGET setting Table 26 and Table 27 show the typical RSSI readout values at the CS threshold at 2 4 kBaud and 250 kBaud data rate respectively The default CARRIER_SENSE_ABS_THR 0 0 dB and MAGN_TARGET 3 33 dB have been used For other data rates the user must generate similar tables to find the CS absolute threshold 9 TEXAS INSTRUMENTS 662300 DVGA GAIN 1 0 00 01 10 11 000 99 93 87 81 5 001 97 905 85 78 5 010 93 5 87 82 76 01 91 5 86 80 74 lt 100 90 5 84 78 72 5 x 101 88 82 5 76 70 110 845 78 5 73 67 111 825 76 70 64 Table 26 Typical RSSI Value in dBm at CS Threshold with Default MAGN_TARGET at 2 4 kBaud MAX DVGA GAIN 1 0 00 01 10 11 000 96 90 84 78 5 g 001 94 5 89 83 77 5 amp 010 925 87 81 75 5 85 785 73 3 100 87 5 82 76 70 x 101 85 79 5 73 5 67 5 110 83 76 5 70 5 65 111 78 72 66 60 SWRS040C Table 27 Typical RSSI Value in dBm at CS Threshold with Default MAGN_TARGET at
74. ebsite Output power 1 dBm Output power is programmable and full range is available highest setting across the entire frequency band Delivered to a 50 single ended load via CC2500EM reference design 4 RF matching network Output power 30 dBm Output power is programmable and full range is available lowest setting across the entire frequency band Delivered to a 50 single ended load via CC2500EM reference design 4 RF matching network It is possible to program less than 30 dBm output power but this is not recommended due to large variation in output power across operating conditions and processing corners for these settings Occupied bandwidth 91 kHz 2 4 kBaud 38 2 kHz deviation 2 FSK 99 117 kHz 10 kBaud 38 2 kHz deviation 2 FSK 296 kHz 250 kBaud MSK 489 kHz 500 kBaud MSK Adjacent channel 28 dBc 2 4 kBaud 38 2 kHz deviation 2 FSK 250 kHz channel power ACP spacing 27 dBc 10 kBaud 38 2 kHz deviation 2 FSK 250 kHz channel spacing 22 dBc 250 kBaud MSK 750 kHz channel spacing 21 dBc 500 kBaud MSK 1 MHz channel spacing Spurious emissions 25 MHz 1 GHz 36 dBm 47 74 87 5 118 174 54 dBm 230 470 862 MHz 1800 1900 MHz 47 dBm Restricted band in Europe At 2 RF and 3 RF 41 dBm Restricted bands in USA Otherwise above 1 30 dBm GHz TX latency 8 bit Serial operation Time from sampling the data on the transmitter data input pin until it is observed on the RF output por
75. een 1 symbols is 8 or less If RX terminates due to no carrier sense when the MCSM2 RX TIME RSSI function is used or if no sync word was found when using the MCSM2 RX TIME timeout function the chip will always go back to IDLE if WOR is disabled and back to SLEEP if WOR is enabled Otherwise the MCSM1 RXOFF MODE Setting determines the state to go to when RX ends This means that the chip will not automatically go back to SLEEP once a sync word has been received It is therefore recommended to always wake up the microcontroller on sync word detection when using WOR mode This can be done by selecting output signal 6 see Table 33 on page 53 on one of the programmable GDO output pins programming the microcontroller to wake up on an edge triggered interrupt from this GDO pin The number of bytes in the RX FIFO and TX FIFO can also be read from the status registers RXBYTES NUM RXBYTES and TXBYTES NUM TXBYTES respectively If a received data byte is written to the RX FIFO at the exact same time as the last byte in the RX FIFO is read over the SPI interface the RX FIFO pointer is not properly updated and the last read byte is duplicated To avoid this problem one should never empty the RX FIFO before the last byte of the packet is received For packet lengths less than 64 bytes it is recommended to wait until the complete packet has been received before reading it out of the RX FIFO If the packe
76. el assessment See Section 17 5 on page 37 for details The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state 19 5 Wake On Radio WOR The optional Wake Radio WOR functionality enables 262500 to periodically wake up from SLEEP and listen for incoming packets without MCU interaction When the SWOR strobe command is sent on the SPI interface the 222900 will go to the SLEEP state when is released The RC oscillator must be enabled before the WOR strobe can be used as it is the clock source for the WOR timer The on chip timer will set 022800 into the IDLE state and then the RX state After a programmable time in RX the chip goes back to the SLEEP state unless a packet is received See Figure 18 and Section 19 7 for details on how the timeout works Set the 202500 into the IDLE state to exit WOR mode 0022800 be set up to signal the MCU that a packet has been received by using the GDO pins If packet is received the MCSM1 RXOFF MODE will determine the behaviour at the end of the received packet When the MCU has read the packet it can put the chip back into SLEEP with the SWOR strobe from the IDLE state The FIFO will lose its contents in the SLEEP state The WOR timer has two events Event 0 and Event 1 In the SLEEP state with WOR activated reaching Event O will turn on the digital regulator and start the crystal oscillator Page 41 of 89 E
77. ency is given by From FREQ CHAN 256 CHANSPC _ M 2 216 With a 26 MHz crystal the maximum channel spacing is 405 kHz To get e g 1 MHz channel spacing one solution is to use 333 kHz channel spacing and select each third channel in CHANNR CHAN The preferred IF frequency is programmed with the FSCTRL1 FREQ_IF register The IF frequency is given by fe FREQ IF 22 VCO The VCO is completely integrated on chip 22 1 VCO and PLL Self Calibration The VCO characteristics will vary with temperature and supply voltage changes as well as the desired operating frequency In order to ensure reliable operation 002200 includes frequency synthesizer self calibration circuitry This calibration should be done regularly and must be performed after turning on power and before using a new frequency or channel The number of XOSC cycles for completing the PLL calibration is given in Table 28 on page 42 The calibration can be initiated automatically or manually The synthesizer can be automatically calibrated each time the synthesizer is turned on or each time the synthesizer is turned off automatically This is configured with the MCSM0 FS_AUTOCAL register setting In manual mode the calibration is initiated when the SCAL command strobe is activated in the IDLE mode 9 TEXAS INSTRUMENTS SWRS040C Note that the SmartRF Studio software 5 automatically calculates the optimum FSCTR
78. enerates SRX strobe 0 SPI SPI SPI mode wakes up into mode mode IDLE if in SLEEP XOFF Table 18 Optional Pin Control Coding If DRATE M is rounded to the nearest integer and becomes 256 increment DRATE E and use DRATE_M 0 The data rate can be set from 1 2 kBaud to 500 kBaud with the minimum step size of Min Data Typical Max Data Data Rate Rate Data Rate Rate Step Size kBaud kBaud kBaud kBaud 0 8 1 2 2 4 3 17 0 0062 3 17 4 8 6 35 0 0124 6 35 9 6 12 7 0 0248 12 7 19 6 25 4 0 0496 25 4 38 4 50 8 0 0992 50 8 76 8 101 6 0 1984 101 6 153 6 203 1 0 3967 203 1 250 406 3 0 7935 406 3 500 500 1 5869 SWRS040C Table 19 Data Rate Step Size Page 26 of 89 13 Receiver Channel Filter Bandwidth In order to meet different channel width requirements the receiver channel filter is programmable The MDMCFG4 CHANBW E and MDMCFG4 CHANBW_M configuration registers control the receiver channel filter bandwidth which scales with the crystal oscillator frequency The following formula gives the relation between the register settings and the channel filter bandwidth BW fxosc 8 4 CHANBW M 20 Nw E For best performance the channel filter bandwidth should be selected so that the signal bandwidth occupies at most 80 of the channel filter bandwidth The channel centre tolerance due to crystal accuracy should also be subtracted fr
79. ent number The following procedure can be used to convert the RSSI reading to an absolute power level RSSI_dBm 1 Read the RSSI status register 2 Convert the reading from a hexadecimal number to a decimal number RSSI dec 3 If RSSI dec gt 128 then RSSI_dBm RSSI dec 256 2 RSSI offset 4 Else if RSSI dec 128 then RSSI dBm RSSI dec 2 RSSI offset 602500 Table 25 provides typical values for the RSSI_ offset Figure 13 shows typical plots of RSSI readings as a function of input power level for different data rates Data Rate kBaud RSSI offset dB 2 4 71 10 69 250 72 500 72 Table 25 Typical RSSI offset Values 0 0 10 0 20 0 30 0 40 0 50 0 60 0 70 0 80 0 RSSI readout dBm 90 0 100 0 4 110 0 120 0 T 120 110 100 90 80 70 60 50 40 30 20 10 0 Input power dBm 2 4 kBaud 10 kBaud 250 kBaud 250 kBaud reduced current 500 kBaud Figure 13 Typical RSSI Value vs Input Power Level for Some Typical Data Rates 17 4 Carrier Sense CS The Carrier Sense CS flag is used as a sync word qualifier and for CCA The CS flag can be set based on two conditions which can be individually adjusted e CS is asserted when the RSSI is above programmable absolute threshold and de asserted when RSSI is below the same
80. er byte This indicates that the crystal is running Unless the chip was in the SLEEP or XOFF states the so pin will always go low immediately after taking CSn low Page 21 of 89 62900 1 gt f 5d 1 x SU PU SCLK CSn Write to register d ae c o c E ans PPRA E Hi Z SI so Real register SI so Parameter Description Min SCLK frequency 100 ns delay inserted between address byte and data byte single access or between address and data and between each data byte burst access SCLK frequency single access No delay between address and data byte SCLK frequency burst access No delay between address and data byte or between data bytes lsp pd CSn low to positive edge on SCLK in power down mode 150 tsp CSn low to positive edge on SCLK in active mode 20 ton Clock high 50 ta Clock low 50 tise Clock rise time tra Clock fall time tsa Setup data negative SCLK edge to Single access 55 positive edge on SCLK tsa applies between address and data bytes and Burst access 76 between data bytes tha Hold data after positive edge on SCLK 20 ths Negative edge on SCLK to high 20 Table 16 SPI Interface Timing Requirements Note The minimum figure in Table 16 be used in cases where the user does not read the CHIP RDYn signal CSn low to positive edge on SCLK when the chip is wo
81. erature sensor 6 GDOO INV 0 R W Invert output i e select active low 1 high 0 5 0 GDOO CFG 5 0 63 R W Default is CLK XOSC 192 see Table 33 on page 53 TEXAS INSTRUMENTS SWRS040C Page 61 of 89 0x03 FIFOTHR RX FIFO and TX FIFO Thresholds 62900 Bit Field Name Reset R W Description 7 4 Reserved 0 RO Write 0 for compatibility with possible future extensions 3 0 THR 3 0 7 0111 R W Set the threshold for the TX FIFO and RX FIFO The threshold is exceeded when the number of bytes in the FIFO is equal to or higher than the threshold value Setting Bytes in TX FIFO Bytes in RX FIFO 0 0000 61 4 1 0001 57 8 2 0010 53 12 3 0011 49 16 4 0100 45 20 5 0101 41 24 6 0110 37 28 7 0111 33 32 8 1000 29 36 9 1001 25 40 10 1010 21 44 11 1011 17 48 12 1100 13 52 13 1101 9 56 14 1110 5 60 15 1111 1 64 0x04 SYNC1 Sync Word High Byte Bit Field Name Reset R W Description 7 0 SYNC 15 8 211 0 03 R W 8 MSB of 16 bit sync word 0x05 SYNCO Sync Word Low Byte Bit Field Name Reset R W Description 7 0 SYNC 7 0 145 0x91 R W 8LSB of 16 bit sync word 0x06 PKTLEN Packet Length Bit Field Name Reset R W Description 7 0 PACKET LENGTH 255 OxFF R W Indicates the packet length when fixed packet length
82. es how easily a received signal can be demodulated SWRS040C Table 22 Received Packet Status Byte 2 second byte appended after the data Note that register fields that control the packet handling features should only be altered when 662500 is in the IDLE state Page 28 of 89 15 1 Data Whitening From a radio perspective the ideal over the air data are random and DC free This results in the smoothest power distribution over the occupied bandwidth This also gives the regulation loops in the receiver uniform operation conditions no data dependencies Real world data often contain long sequences of zeros and ones Performance can then be improved by whitening the data before transmitting and de whitening the data in the receiver With 002000 this can be done 62900 automatically by setting PKTCTRLO WHITE DATA 1 All data except the preamble and the sync word are then XOR ed with a 9 bit pseudo random PN9 sequence before being transmitted as shown in Figure 10 At the receiver end the data are XOR ed with the same pseudo random sequence This way the whitening is reversed and the original data appear in the receiver The PN9 sequence is reset to all 1 s Data whitening can only be used when PKTCTRLO CC2400_EN 0 default E 7 H 6 h 5 DL 4 2 L
83. esents TI s knowledge and belief as of the date that it is provided bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 2 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 5 Jun 2015 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS Diameter Dimension designed to accommodate the component width BO Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness y Overall width of the carrier tape Y Pitch between successive cavity centers Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q
84. et the MDMCFG2 MOD FORMAT register Optionally the data stream can be Manchester coded by the modulator and decoded by the demodulator This option is enabled by setting MDMCFG2 MANCHESTER EN 1 Manchester encoding is not supported at the same time as using the FEC Interleaver option 16 1 Frequency Shift Keying 2 FSK can optionally be shaped by a Gaussian filter with BT 1 producing a GFSK modulated signal The frequency deviation is programmed with the DEVIATION M and DEVIATION E values in the DEVIATN register The value has an exponent mantissa form and the resultant deviation is given by 9 TEXAS INSTRUMENTS SWRS040C 62900 information on how many bytes in the RX FIFO and TX FIFO respectively See Table 33 b SPI polling The PKTSTATUS register can be polled at a given rate to get information about the current GDO2 and GDOO values respectively The RXBYTES and TXBYTES registers can be polled at a given rate to get information about the number of bytes in the RX FIFO and TX FIFO respectively Alternatively the number of bytes in the RX FIFO and TX FIFO can be read from the chip status byte returned on the MISO line each time a header byte data byte or command strobe is sent on the SPI bus It is recommended to employ interrupt driven solution as high rate SPI polling will reduce the RX sensitivity Furthermore as explained in Section 10 3 and the 662500
85. f its components to the specifications applicable at the time of sale in accordance with the warranty Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques are used to the extent deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed Tl assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which components or services are used Information published by TI regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if repr
86. frequency hop calibration can be replaced by writing the FSCAL3 FSCAL2 1 register values corresponding to the next RF frequency TEXAS INSTRUMENTS SWRS040C Page 79 of 89 62900 0x25 FSCAL1 Frequency Synthesizer Calibration Bit Field Name Reset R W Description 7 6 Reserved RO 5 0 FSCAL1 5 0 32 R W Frequency synthesizer calibration result register Capacitor array 0x20 setting for VCO coarse tuning Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3 FSCAL2 FSCAL1 register values Between each frequency hop calibration can be replaced by writing the FSCAL3 FSCAL2 and FSCAL1 register values corresponding to the next RF frequency 0x26 FSCALO Frequency Synthesizer Calibration Bit Field Name Reset R W Description 7 Reserved RO 6 0 FSCALO 6 0 13 0x0D R W Frequency synthesizer calibration control The value to use in this register is given by the SmartRF Studio software 5 0x27 RCCTRL 1 RC Oscillator Configuration Bit Field Name Reset R W Description 7 Reserved 0 RO 6 0 RCCTRL1 6 0 65 R W oscillator configuration 0x41 0x28 RCCTRLO RC Oscillator Configuration Bit Field Name Reset R W Description
87. g 1 PATABLE index zero is used in OOK when transmitting a 0 0x23 FSCAL3 Frequency Synthesizer Calibration Bit Field Name Reset R W Description 7 6 FSCAL3 7 6 2 10 R W Frequency synthesizer calibration configuration The value to write in this register before calibration is given by the SmartRF Studio software 5 5 4 CURR CAL EN 1 0 2 10 R W Disable charge pump calibration stage when 0 3 0 FSCAL3 3 0 9 R W Frequency synthesizer calibration result register Digital bit vector 1001 defining the charge pump output current on an exponential scale 1 278 318 1 4 Fast frequency hopping without calibration for each hop be done by calibrating upfront for each frequency and saving the resulting FSCAL3 FSCAL2 and FSCAL1 register values Between each frequency hop calibration can be replaced by writing the FSCAL3 FSCAL2 FSCAL1 register values corresponding to the next RF frequency 0x24 FSCAL2 Frequency Synthesizer Calibration Bit Field Name Reset R W Description 7 6 Reserved RO 5 VCO CORE H EN 0 R W Choose high 1 low 0 VCO 4 0 FSCAL2 4 0 10 R W Frequency synthesizer calibration result register VCO current 0x0A calibration result and override value Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3 FSCAL2 and FSCAL1 register values Between each
88. g Description 0 00 No hysteresis small symmetric dead zone high gain 1 01 Low hysteresis small asymmetric dead zone medium gain 2 10 Medium hysteresis medium asymmetric dead zone medium gain 3 11 Large hysteresis large asymmetric dead zone low gain 5 4 WAIT_TIME 1 0 1 01 R W Sets the number of channel filter samples from a gain adjustment has been made until the AGC algorithm starts accumulating new samples Setting Channel filter samples 0 00 8 1 01 16 2 10 24 3 11 32 3 2 AGC_FREEZE 1 0 0 00 R W Controls when the AGC gain should be frozen Setting Function Normal operation Always adjust gain when 0 00 required 1 01 The gain setting is frozen when a sync word has been found 2 10 Manually freezes the analog gain setting and continue to adjust the digital gain Manually freezes both the analog and the digital 3 11 gain settings Used for manually overriding the gain 1 0 FILTER LENGTH 1 0 1 01 R W Sets the averaging length for the amplitude from the channel filter Sets the OOK decision boundary for OOK reception Setting Channel filter samples OOK decision 0 00 8 4 dB 1 01 16 8 dB 2 10 32 12 dB 3 11 64 16 dB 0x1E WOREVT1 High Byte EventO Timeout Bit Field Name Reset R W Description 7 0 EVENTO 15 8 135 0x87 R W High byte of Event 0 timeout register
89. g the default value After a reset all registers that performance and functionality A screenshot of shall be different from the default value the SmartRF Studio user interface for 0029200 therefore needs to be programmed through is shown in Figure 6 the SPI interface SWRS040C Page 20 of 89 TEXAS INSTRUMENTS 0 0323 CC2500 SmartRF Studio Eile Settings Help 62900 Current chip values fee LO CFG 2 0x00 0x29 IOCFG1 0x01 0 2 IDCFGOD 0x02 Normal View Register View Notes 71 Chip revision Correlation IDCFGOAT 002 0x3F t IDCFGOA2 0x02 Dx3F FIFOTHR 0x03 0x07 SYNC1 0x04 0 03 SYNCO 0x05 0x91 PKTLEN 0x06 OxFF 0x07 0x04 PKTCTRLO 0x08 0245 ADDR 0x09 0x00 J EHANNR 0x04 0x00 FSCTRL1 0x08 2 4 kbps FSCTRLO 00 0x00 24 kbps 4 FREQ2 000 Ox5E 10 kbps H 1 Ox0E OxC4 250 kbps 1 FREQO 0x0F 250 kbps MDMCFG4 0x10 0x8C 10 t MDMCFG3 0x11 0x22 J MDMCFG2 0x12 0x02 MDMCFG1 0x13 0x22 Crystal accuracy Xtal frequency 40 ppm 26 000000 Datarate 2 398968 kbps Channel 199 951172 Deviation 38 085338 kHz RF frequency 2432 999908 MHz Preferred settings kHz 8 kHz Em 203 kHz 203 kHz 232 kHz 232 kHz 540 kHz 540 kHz 2FS 2FSK 2 FSK 2 FSK AF ou
90. garding the exposed thermal pad features and dimensions room Check thermal pad mechanical drawing in the product datasheet for nominal lead length dimensions Texas INSTRUMENTS www ti com THERMAL PAD MECHANICAL DATA RGP 5 20 PLASTIC QUAD FLATPACK NO LEAD THERMAL INFORMATION This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink The thermal pad must be soldered directly to the printed circuit board PCB After soldering the PCB be used as a heatsink addition through the use of thermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC For information on the Quad Flatpack No Lead QFN package and its advantages refer to Application Report QFN SON PCB Attachment Texas Instruments Literature No 5104271 This document is available at www ti com The exposed thermal pad dimensions for this package are shown in the following illustration PIN 1 INDICATOR C 0 30 2 40 0 10 Bottom View Exposed Thermal Pad Dimensions 4206346 7 AA 11 13 NOTES A All linear dimensions are in millimeters 5 INSTRUMENTS www ti com MECHANICAL DATA
91. gth mode 3 11 Reserved 0x09 ADDR Device Address Bit Field Name Reset R W Description 7 0 DEVICE ADDR 7 0 0 0x00 R W Address used for packet filtration Optional broadcast addresses are 0 0x00 and 255 OxFF 0x0A CHANNR Channel Number Bit Field Name Reset R W Description 7 0 CHAN 7 0 0 0x00 R W The 8 bit unsigned channel number which is multiplied by the channel spacing setting and added to the base frequency TEXAS INSTRUMENTS SWRS040C Page 64 of 89 62900 0x0B FSCTRL1 Frequency Synthesizer Control Bit Field Name Reset R W Description 7 5 Reserved RO 4 0 FREQ IF 4 0 15 R W The desired IF frequency to employ in RX Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator 10 f FREQ IF The default value gives an IF frequency of 381 kHz assuming a 26 0 MHz crystal 0 0 FSCTRLO Frequency Synthesizer Control Bit Field Name Reset R W Description 7 0 FREQOFF 7 0 0 0x00 R W Frequency offset added to the base frequency before being used by the FS 2 s complement Resolution is 2 1 59 1 65 kHz range is 202 kHz to 210 kHz dependent of XTAL frequency 0x0D FREQ2 Frequency Control Word High Byte Bi
92. have started when enabling the receiver the MCSM2 RX TIME RSSI function can be used The radio controller will then terminate RX if the first valid carrier sense sample indicates no carrier RSSI below threshold See Section 17 4 on page 35 for details on Carrier Sense 20 Data FIFO The 662500 contains two 64 byte FIFOs one for received data and one for data to be transmitted The SPI interface is used to read from the RX FIFO and write to the TX FIFO Section 10 5 contains details on the SPI FIFO access The FIFO controller will detect overflow in the RX FIFO and underflow in the TX FIFO When writing to the TX FIFO it is the responsibility of the MCU to avoid TX FIFO overflow A TX FIFO overflow will result in an error in the TX FIFO content Likewise when reading the RX FIFO the MCU must avoid reading the RX FIFO past its empty value since an RX FIFO underflow will result in an error in the data read out of the RX FIFO The chip status byte that is available on the so pin while transferring the SPI header contains the fill grade of the RX FIFO if the access is a read operation and the fill grade of the TX FIFO if the access is a write operation Section 10 1 on page 22 contains more details on this 9 TEXAS INSTRUMENTS SWRS040C 62900 For OOK modulation lack of carrier sense is only considered valid after eight symbol periods Thus the MCSM2 RX TIME RSSI function can be used in OOK mode when the distance betw
93. he PKTLEN value is set according to this value The end of packet will occur when the byte counter in the packet handler is equal to the PKTLEN register Thus the MCU must be able to program the correct length before the internal counter reaches the packet length 15 2 2 Packet Length gt 256 bytes Also the packet automation control register PKTCTRLO can be reprogrammed during TX and RX This opens the possibility to transmit and receive packets that are longer than 256 bytes and still be able to use the packet handling hardware support At the start of the packet the infinite packet length mode PKTCTRLO LENGTH CONFIG 2 must be active On the TX side the PKTLEN register is set to mod length 256 On the RX side the MCU reads out enough bytes to interpret the length field in the packet and sets the PKTLEN register to mod length 256 When less than 256 bytes remains of the packet the MCU disables infinite packet length mode and activates fixed packet length mode When the internal byte counter reaches the PKTLEN value the transmission or reception ends the radio enters the state determined by TXOFF MODE RXOFF MODE Automatic CRC appending checking can also be used by setting PKTCTRLO CRC_EN 1 When for example a 600 byte packet is to be transmitted the MCU should do the following see also Figure 12 e Set PKTCTRLO LENGTH CONFIG 2 Page 30 of 89 e Pre p
94. he data to be interleaved is an even number Note that these extra bytes are invisible to the user as they are removed before the received packet enters the RX FIFO When FEC and interleaving is used the minimum data payload is 2 bytes Interleaver Read buffer Engine Packet FEC tH Encoder p gt Modulator gt Interleaver Write buffer Interleaver Read buffer Demodulator D FEC Packet gt q gt Decoder Engine q gt Figure 14 General Principle of Matrix interleaving 9 TEXAS INSTRUMENTS SWRS040C Page 38 of 89 19 Radio Control 62900 SWOR m CAL_ COMPLETE oe P a lt C MANCAL 7 IDLE 4 0 wGR 3 4 5 1 At SXOFF PO SORES E E e ERN N CSn 0 f XOFE 5 STX SFSTXON WOR A 8 x y Z di a m FS WAKEUP 97 77 FS AUTOCAL 01 5 SRX STX SFSTXON WOR FS AUTOCAL 00 10 11 Fa EN amp CALIBRATE SRX STX SFSTXON WOR 5 P SETTLING CAL COMPLETE 9 10 11 Va Nee EN mu FSTXON P 18 S Ne F lt _ ST SRX WOR a M o a ri 9 5 gt SFSTXON RXOFF_MODE 01 TXOFF MODE 01 uA ue
95. his design A HC 49 type SMD crystal is used in the CC2500EM reference design 4 Note that the crystal package strongly influences the price In a size constrained PCB design a smaller but more expensive crystal may be used 31 9 In low power applications the SLEEP state with the crystal oscillator core switched off should be used when the 662500 is not active It is possible to leave the crystal oscillator core running in the SLEEP state if start up time is Critical Battery Operated Systems The WOR functionality should be used in low power applications 31 10 In some applications it may be necessary to extend the link range Adding an external power amplifier is the most effective way of doing this Increasing Output Power The power amplifier should be inserted between the antenna and the balun and two T R switches are needed to disconnect the PA in RX mode See Figure 29 P d Filter PA T R switch 002200 Balun T R switch Figure 29 Block Diagram of 662500 Usage with External Power Amplifier 9 TEXAS INSTRUMENTS SWRS040C Page 56 of 89 32 Configuration Registers The configuration of 662500 is done by programming 8 bit registers The optimum configuration data based on selected system parameters are most easily found by using the SmartRF Studio software 5 Complete descriptions of the registers are given in the following
96. in a frequency hopping spread spectrum or a multi channel protocol the calibration time can be reduced from 721 us to approximately 150 us This is explained in Section 31 2 Description XOSC 26 MHz Periods Crystal IDLE to RX no calibration 2298 88 4 us IDLE to RX with calibration 21037 809 us IDLE to TX FSTXON no calibration 2298 88 4 us IDLE to TX FSTXON with calibration 21037 809 us TX to RX switch 560 21 5 us RX to TX switch 250 9 6 us RX or TX to IDLE no calibration 2 0 1 us RX or TX to IDLE with calibration 18739 721 us Manual calibration 18739 721 us SWRS040C Table 28 State Transition Timing Page 42 of 89 19 7 RX Termination Timer 002500 has optional functions for automatic termination of RX after a programmable time The main use for this functionality is wake on radio WOR but it may be useful for other applications The termination timer starts when in RX state The timeout is programmable with the MCSM2 RX TIME setting When the timer expires the radio controller will check the condition for staying in RX if the condition is not met RX will terminate The programmable conditions are e MCSM2 RX TIME QUAL 0 Continue receive if sync word has been found MCSM2 RX TIME QUAL Continue receive if sync word has been found or preamble quality is above threshold PQT If the system can expect the transmission to
97. integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis 35 References CC2500 Errata Notes swrz002 pdf 2 2 2 4 GHz Regulations swra060 pdf 3 047 CC1100 CC2500 Wake On Radio swra126 pdf 4 CC2500EM Reference Design 1 0 swrr016 zip SWRS040C Page 86 of 89 TEXAS INSTRUMENTS 62900 5 SmartRF Studio swrc046 zip 6 CC1100 CC2500 Examples Libraries swrc021 zip 7 CC1100 CC1150DK amp CC2500 CC2550DK Development Kit Examples amp Libraries User Manual swru109 pdf 8 CC25XX Folded Dipole Reference Design swrc065 zip 9 03004 Folded Dipole Antenna for CCC25xx swra118 pdf SWRS040C Page 87 of 89 TEXAS INSTRUMENTS 62900 36 General Information 36 1 Document History Revision Date Description Changes SWRS040C SWRS040B 2008 05 04 2007 05 09 Updated package and ordering information kbps replaced by kBaud throughout the document
98. is enabled If variable length packets are used this value indicates the maximum length packets allowed SWRS040C Page 62 of 89 TEXAS INSTRUMENTS 62900 0x07 PKTCTRL1 Packet Automation Control Bit Field Name Reset R W Description 7 5 PQT 2 0 0 000 R W Preamble quality estimator threshold The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit and decreases the counter by 8 each time a bit is received that is the same as the last bit A threshold of 4 PQT for this counter is used to gate sync word detection When PQT 0 a sync word is always accepted 4 Reserved 0 RO 3 CRC_AUTOFLUSH 0 R W Enable automatic flush of RX FIFO when CRC is not OK This requires that only one packet is in the RX FIFO and that packet length is limited to the RX FIFO size PKTCTRLO CC2400 EN must be 0 default for the CRC autoflush function to work correctly 2 APPEND_STATUS 1 R W When enabled two status bytes will be appended to the payload of the packet The status bytes contain RSSI and LQI values as well as the CRC OK flag 1 0 ADR_CHK 1 0 0 00 R W Controls address check configuration of received packages Setting Address check configuration 0 00 No address check 1 01 Address check no broadcast 2 10 Address check and 0 0x00 broadcast 3 11 Address check and 0 0x00 and
99. is is the main ground connection for the chip SWRS040C Page 15 of 89 TEXAS INSTRUMENTS 62900 Pin Pin Name Pin Type Description 1 SCLK Digital Input Serial configuration interface clock input 2 so Gpo1 Digital Output Serial configuration interface data output Optional general output pin when is high 3 GDO2 Digital Output Digital output pin for general use e Test signals e FIFO status signals e Clear Channel Indicator e Clock output down divided from XOSC e Serial output RX data 4 DVDD Power Digital 1 8 3 6 V digital power supply for digital l O s and for the digital core voltage regulator 5 DCOUPL Power Digital 1 6 2 0 V digital power supply output for decoupling NOTE This pin is intended for use with the 662500 only It can not be used to provide supply voltage to other devices 6 GDOO ATEST Digital Digital output pin for general use e Test signals e FIFO status signals e Clear Channel Indicator e Clock output down divided from XOSC e Serial output RX data e Serial input TX data Also used as analog test I O for prototype production testing 7 CSn Digital Input Serial configuration interface chip select 8 XOSC 01 Analog I O Crystal oscillator pin 1 or external clock input 9 AVDD Power Analog 1 8 3 6 V analog power supply connection 10 xosc o2
100. ition Note 250 kBaud data rate sensitivity optimized MDMCFG2 DEM_DCFILT_OFF 0 MSK 1 packet error rate 20 bytes packet length 540 kHz digital channel filter bandwidth Receiver sensitivity 89 Saturation 13 dBm Adjacent channel rejection 21 dB Desired channel 3 dB above the sensitivity limit 750 kHz channel spacing Alternate channel rejection 30 dB Desired channel 3 dB above the sensitivity limit 750 kHz channel spacing See Figure 24 for plot of selectivity versus frequency offset Blocking Wanted signal 3 dB above sensitivity level 10 MHz offset 46 dB Compliant with ETSI EN 300 440 class 2 receiver 20 MHz offset 53 requirements 50 2 offset 55 dB 250 kBaud data rate current optimized MDMCFG2 DEM DCFILT OFF MSK 196 packet error rate 20 bytes packet length 540 kHz digital channel filter bandwidth Receiver sensitivity 87 Saturation 12 dBm Adjacent channel rejection 21 dB Desired channel 3 dB above the sensitivity limit 750 kHz channel spacing Alternate channel rejection 30 dB Desired channel 3 dB above the sensitivity limit 750 kHz channel spacing See Figure 25 for plot of selectivity versus frequency offset Blocking Wanted signal 3 dB above sensitivity level 10 MHz offset 46 dB Compliant with ETSI EN 300 440 class 2 receiver 20 MHz offset 52 requirements 50 MHz offset 55 dB 500 kBaud data rat
101. itry ensures match in both RX and TX mode Although 002800 has a balanced RF input output the chip can be connected to a single ended antenna with few external low cost capacitors and inductors The passive matching filtering network connected to 002800 should have the following differential impedance as seen from the RF port P and RF N towards the antenna Page 50 of 89 Zou 80 74 To ensure optimal matching of the 002000 differential output it is highly recommended to 28 PCB Layout Recommendations The top layer should be used for signal routing and the open areas should be filled with metallization connected to ground using several vias The area under the chip is used for grounding and shall be connected to the bottom ground plane with several vias for good thermal performance and sufficiently low inductance to ground In the CC2500EM reference designs 4 5 vias are placed inside the exposed die attached pad These vias should be tented covered with solder mask on the component side of the PCB to avoid migration of solder through the vias during the solder reflow process The solder paste coverage should not be 100 If it is out gassing may occur during the reflow process which may cause defects splattering solder balling Using tented vias reduces the solder paste coverage below 100 See Figure 28 for top solder resist and top paste masks See Figure 30 for recommended PCB layo
102. k GDO2 output pin configuration File dump a MDMCFG1 0420 Forward Error Correction gt FEC_EN MDMCFG2 0x03 Sync mode gt SYNC M DE 2 0 IPKTCTRLO 0x05 Packetformat gt PKT_FORMAT 1 0 CRC operation gt CRC EN Packet config gt LENGTH_CONFIG 1 0 PKTETRL1 004 Address check gt _ 1 0 FIFO autoflush gt CRC_AUTOFLUSH el Start buffered RX Stop R Device 10 0x0323 Last executed command Date 26 04 2006 Time 11 06 20 Figure 6 SmartRF Studio 5 User Interface 10 4 wire Serial Configuration and Data Interface 662500 is configured via a simple 4 wire SPI compatible interface 51 50 SCLK and CSn where 202500 is the slave This interface is also used to read and write buffered data All transfers on the SPI interface are done most significant bit first All transactions on the SPI interface start with a header byte containing a RW bit a burst access bit B and a 6 bit address A The pin must be kept low during transfers on the SPI bus If goes high during the SWRS040C TEXAS INSTRUMENTS transfer of a header byte or during read write from to a register the transfer will be cancelled The timing for the address and data transfer on the SPI interface is shown in Figure 7 with reference to Table 16 When is pulled low the MCU must wait until 662500 so pin goes low before starting to transfer the head
103. ken from power down depends on the start up time of the crystal being used The 150 us in Table 16 is the crystal oscillator start up time measured on CC2500EM reference design 4 using crystal AT 41CD2 from NDK 10 1 Chip Status Byte When the header byte data byte or command before the first positive edge of SCLK The CHIP RDYn signal indicates that the crystal is strobe is sent on the SPI interface the chip status byte is sent by the 662500 on the so pin The status byte contains key status signals useful for the MCU The first bit s7 is the CHIP RDYn signal this signal must go low SWRS040C TEXAS INSTRUMENTS running Bits 6 5 and 4 comprise the STATE value This value reflects the state of the chip The XOSC and power to the digital core is on in the IDLE state but all other modules are in power down The frequency and channel Page 22 of 89 configuration should only be updated when the chip is in this state The RX state will be active when the chip is in receive mode Likewise TX is active when the chip is transmitting The last four bits 3 0 in the status byte contains FIFO BYTES AVAILABLE For read operations the R W bit in the header byte is set to 1 the FIFO_BYTES_AVAILABLE field contains the number of bytes available for 62900 reading from the RX FIFO For write operations the R W bit in the header byte is set to 0 the FIFO BYTES AVAILABLE field contains the number of bytes
104. l number CHAN and added to the base frequency It is unsigned and has the format Af NEL Pur 256 CHANSPC M Q CHANSPC _ 18 The default values give 199 951 kHz channel spacing the closest setting to 200 kHz assuming 26 0 MHz crystal frequency SWRS040C Page 68 of 89 TEXAS INSTRUMENTS 62900 0x15 DEVIATN Modem Deviation Setting Bit Field Name Reset R W Description 7 Reserved RO 6 4 DEVIATION_E 2 0 4 100 R W Deviation exponent 3 Reserved RO 2 0 DEVIATION M 2 0 7 111 R W When MSK modulation is enabled Sets fraction of symbol period used for phase change Refer to the SmartRF Studio software 5 for correct DEVIATN setting when using MSK When 2 FSK GFSK modulation is enabled Deviation mantissa interpreted as a 4 bit value with MSB implicit 1 The resulting deviation is given by fiw fay 8 DEVIATION 22819 8 The default values give 47 607 kHz deviation assuming 26 0 MHz crystal frequency SWRS040C Page 69 of 89 TEXAS INSTRUMENTS 0x16 MCSM2 Main Radio Control State Machine Configuration 662300 Bit Field Name Reset R W Description 7 5 Reserved RO Reserved 4 RX TIME RSSI 0 R W Direct RX termination based on RSSI measurement carrier sense 3 RX TIME QUAL 0 RAN When the RX TIME timer expires the chip stays in RX mode if sync word is found when RX TIME QUAL O or either s
105. le customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No TI components are authorized for use in FDA Class III or similar life critical medical equipment unless authorized officers of the parties have executed a special agreement specifically governing such use Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of Tl components which have not been so designated is solely at the Buyer s risk and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements mainly for automotive use In any case of use of non designated products TI will not be responsible for any failure to meet ISO TS16949 Products Applications Audio www ti com audio Automotive and Transportation www ti com automotive Amplifiers amplifier ti com Communications and Telecom www ti com communications Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity dataconverter ti com www dlp
106. ment Removed comments about having to use NRZ coding in synchronous serial mode Added info that Manchester encoding cannot be used in asynchronous serial mode Changed number of commands strobes from 14 to 13 Added two new registers ROCTRL1 STATUS and RCCTRLO STATUS Changed field name and or description of the following registers MCSM2 MCSMO WORCTRL FSCAL3 FSCAL2 FSCAL1 TEST2 TEST1 and TESTO Added references TEXAS INSTRUMENTS SWRS040C Page 88 of 89 62900 Revision Date Description Changes 1 2 SWRS040A 2006 06 28 Added figures to table on SPI interface timing requirements Added information about SPI read Updates to text and included new figure in section on arbitrary length configuration Updates to section on CRC check Added information about CRC check when PKTCTRLO CC2400_EN 1 Added information on RSSI update rate in section RSSI Updates to text and included new figures in section on power on start up sequence Changes to wake on radio current consumption figures under electrical specifications Updates to text in section on data FIFO Added information about how to check for PLL lock in section on VCO Better explanation of some of the signals in table of GDO signal selection Also added some more signals Added section on wideband modulation not using spread spectrum under section on system considerations and guidelines Changes to timeout for sync word search in RX in registe
107. mission RC Forward Error Correction RF First In First Out RSSI Frequency Hopping Spread Spectrum RX Frequency Shift Keying SMD Gaussian shaped Frequency Shift Keying SNR Intermediate Frequency SPI In Phase Quadrature SRD Industrial Scientific and Medical T R Listen Before Transmit TX Inductor Capacitor VCO Low Noise Amplifier WLAN Local Oscillator WOR Link Quality Indicator XOSC Least Significant Bit XTAL Microcontroller Unit TEXAS INSTRUMENTS SWRS040C 62900 Most Significant Bit Minimum Shift Keying Not Applicable Non Return to Zero Coding On Off Keying Power Amplifier Printed Circuit Board Power Down Packet Error Rate Phase Locked Loop Power on Reset Preamble Quality Indicator Preamble Quality Threshold RC Oscillator Quadrature Phase Shift Keying Quad Leadless Package Resistor Capacitor Radio Frequency Received Signal Strength Indicator Receive Receive Mode Surface Mount Device Signal to Noise Ratio Serial Peripheral Interface Short Range Device Transmit Receive Transmit Transmit Mode Voltage Controlled Oscillator Wireless Local Area Networks Wake on Radio Low power polling Crystal Oscillator Crystal Page 3 of 89 62900 Table of Contents APPLICA TIONS 1 PRODUCT DESCRIPTION 1 KEY FEATURES TE E siisi 1 RE PERFORMANCE
108. n RX when using setting 1 001 or 5 101 The values 3 011 and 7 111 enables repeated sync word transmission in TX and 32 bits sync word detection in RX only 30 of 32 bits need to match Setting Sync word qualifier mode 000 No preamble sync 15 16 sync word bits detected 16 16 sync word bits detected 30 32 sync word bits detected No preamble sync carrier sense above threshold 5 101 15 16 carrier sense above threshold 6 110 16 16 carrier sense above threshold 7 111 30 32 carrier sense above threshold TEXAS INSTRUMENTS SWRS040C Page 67 of 89 62900 0x13 1 Modem Configuration Bit Field Name Reset R W Description 7 FEC EN 0 R W Enable Forward Error Correction FEC with interleaving for packet payload 0 Disable 1 Enable Only supported for fixed packet length mode i e PKTCTRLO LENGTH_CONFIG 0 64 NUM_PREAMBLE 2 0 2 010 R W Sets the minimum number of preamble bytes to be transmitted Setting Number of preamble bytes 0 000 2 1 001 3 2 010 4 3 011 6 4 100 8 5 101 12 6 110 16 7 111 24 3 2 Reserved RO 1 0 CHANSPC_E 1 0 2 10 R W 2 bit exponent of channel spacing 0x14 MDMCFGO Modem Configuration Bit Field Name Reset R W Description 7 0 CHANSPC 7 0 248 OxF8 R W 8 bit mantissa of channel spacing The channel spacing is multiplied by the channe
109. n SRX pr 10 cca N TX A t E 19 20 E b ERES SRX MODE 11 SETTLING m 16 N EN p TXFIFO_ UNDERFLOW A FS AUTOCAL 10111 Me TXOFF MODE 00 ER Y TXOFF MODE 00 amp FS AUTOCAL 00 01 ho TXFIFO UNDERFLOW Berri STX RXOFF MODE 10 CSi a N CALIBRATE STX SFSTXON amp CCA d RXOFF MODE 01 10 7 RXOFF MODE 11 csi RXOFF_MODE 00 amp RXFIFO OVERFLOW FS AUTOCAL 10 11 MODE 00 Y amp pet FS AUTOCAL 00 01 RxFIFO_OVERFLOW i N ES ES SFTX a E a N IDLE 1 7 Figure 15 Complete Radio Control State Diagram 002500 has a built in state machine that is used to switch between different operation states modes The change of state is done either by using command strobes or by internal events such as TX FIFO underflow simplified state diagram together with typical usage and current consumption is shown in Figure 5 on page 15 The complete radio control state diagram is shown in Figure 15 The numbers refer to the state number SWRS040C TEXAS INSTRUMENTS readable in the MARCSTATE status register This register is primarily for test purposes 19 1 When the power supply is turned on the system must be reset
110. n not performing calibration Crystal oscillator running PLL RX TX settling 9 3 9 6 9 6 us Settling time for the 1 IF frequency step from RX to TX time PLL TX RX settling 20 7 21 5 21 5 us Settling time for the 1 IF frequency step from TX to RX time PLL calibration time 694 721 721 us Calibration can be initiated manually or automatically before entering or after leaving RX TX TEXAS INSTRUMENTS Table 9 Frequency Synthesizer Parameters SWRS040C Page 13 of 89 62900 4 7 Analog Temperature Sensor The characteristics of the analog temperature sensor at 3 0 V supply voltage are listed in Table 10 below Note that it is necessary to write OxBF to the PTEST register to use the analog temperature sensor in the IDLE state Parameter Min Typ Max Unit Condition Note Output voltage at 40 C 0 654 V Output voltage at 0 0 750 V Output voltage at 40 0 848 V Output voltage at 80 0 946 V Temperature coefficient 2 43 mV C Fitted from 20 C to 80 C Error in calculated 2 0 2 From 20 C to 80 C when using 2 43 mV C temperature calibrated after 1 point calibration at room temperature The indicated minimum and maximum error with 1 point calibration is based on measured values for typical process parameters Current consumption 0 3 mA increase when enabled Table 10 Analog Temperature Sensor Parameters 4 8
111. nal coding In receive mode the packet handling support will de construct the data packet by implementing the following if enabled e Preamble detection e Sync word detection e CRC computation and CRC check 9 TEXAS INSTRUMENTS 62900 correlation threshold can be set to 15 16 16 16 or 30 32 bits match The sync word can be further qualified using the preamble quality indicator mechanism described below and or a carrier sense condition The sync word is configured through the SYNC1 and SYNCO registers In order to make false detections of sync words less likely mechanism called preamble quality indication POI can be used to qualify the sync word A threshold value for the preamble quality must be exceeded in order for a detected sync word to be accepted See Section 17 2 on page 34 for more details e One byte address check e Packet length check length byte checked against a programmable maximum length e De whitening e De interleaving and decoding Optionally two status bytes see Table 21 and Table 22 with RSSI value Link Quality Indication and CRC status can be appended in the RX FIFO Bit Field Name Description 7 0 RSSI RSSI value Table 21 Received Packet Status Byte 1 first byte appended after the data Bit Field Name Description 7 CRC OK 1 CRC for received data OK or CRC disabled 0 CRC error in received data 6 0 Lal The Link Quality Indicator estimat
112. ncy offset MHz Figure 25 Typical Selectivity at 250 kBaud IF Frequency is 457 kHz MDMCFG2 DEM_DCFILT_OFF 1 E Selectivity dB lee Frequency offset MHz Figure 26 Typical Selectivity at 500 kBaud IF Frequency is 304 7 kHz MDMCFG2 DEM DCFILT OFF SWRS040C Page 49 of 89 TEXAS INSTRUMENTS 26 Crystal Oscillator A crystal in the frequency range 26 27 MHz must be connected between the xosc o1 and XOSC Q2 pins The oscillator is designed for parallel mode operation of the crystal In addition loading capacitors C81 and C101 for the crystal are required The loading capacitor values depend on the total load capacitance C specified for the crystal The total load capacitance seen between the crystal terminals should equal C for the crystal to oscillate at the specified frequency 1 1 1 C ous The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance Total parasitic capacitance is typically 2 5 pF 62900 The crystal oscillator circuit is shown in Figure 27 Typical component values for different values of are given in Table 32 The crystal oscillator is amplitude regulated This means that a high current is used to start up the oscillations When the amplitude builds up the current is reduced to what is necessary to maintain approximately 0 4 signal swing This ensures a fast st
113. nd mouse e HF enabled remote controls controlled via an SPI interface In a typical system the 662500 will be used together with a microcontroller and a few additional passive components O gt cemo HAH frequency synthesizer with 90 us settling time e Automatic Frequency Compensation AFC can be used to align the frequency synthesizer to the received centre frequency e Integrated analog temperature sensor Digital Features e Flexible support for packet oriented systems On chip support for sync word detection address check flexible packet length and automatic CRC handling e Efficient SPI interface All registers can be programmed with one burst transfer e Digital RSSI output e Programmable channel filter bandwidth e Programmable Carrier Sense CS indicator Page 1 of 89 e Programmable Preamble Quality Indicator PQI for improved protection against false sync word detection in random noise e Support for automatic Clear Channel Assessment CCA before transmitting for listen before talk systems e Support for per package Link Quality Indication e Optional automatic whitening and de whitening of data Low Power Features e 400 nA SLEEP mode current consumption e Fast startup time 240 us from SLEEP to RX or TX mode measured on EM design e Wak
114. ng Together with an appropriate LC network the balun components also transform the impedance to match a 50 Q antenna or cable Suggested values are listed in Table 15 The balun and LC filter component values and their placement are important to keep the performance optimized It is X highly recommended to follow the CC2500EM 62900 Crystal The crystal oscillator uses an external crystal with two loading capacitors C81 and C101 See Section 26 on page 50 for details Power Supply Decoupling The power supply must be properly decoupled close to the supply pins Note that decoupling capacitors are not shown in the application circuit The placement and the size of the decoupling capacitors are very important to achieve the optimum performance reference design 4 CC2500EM reference design 4 should be followed closely Component Description C51 Decoupling capacitor for on chip voltage regulator to digital part C81 C101 Crystal loading capacitors see Section 26 on page 50 for details 0121 0131 RF balun DC blocking capacitors 122 132 RF balun matching capacitors 0123 0124 RF LC filter matching capacitors L121 L131 RF balun matching inductors inexpensive multi layer type L122 RF LC filter inductor inexpensive multi layer type R171 Resistor for internal bias current reference XTAL 26 27 MHz crystal see Section 26 on page 50 for details Table 14 Overview of
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116. of Bytes in FIFO 0 00 RX and GDOx_CFG 0x02 in TX 21 Frequency Programming The frequency programming 002200 is designed to minimize the programming needed in a channel oriented system To set up a system with channel numbers the desired channel spacing is programmed with the MDMCFGO CHANSPC M and 9 TEXAS INSTRUMENTS SWRS040C 62900 FIFO THR Bytes TX FIFO Bytes in RX FIFO 0 0000 61 4 1 0001 57 8 2 0010 53 12 3 0011 49 16 4 0100 45 20 5 0101 41 24 6 0110 37 28 7 0111 33 32 8 1000 29 36 1001 25 40 0 1010 21 44 1 1011 17 48 2 1100 13 52 3 1101 9 56 4 1110 5 60 5 1111 1 64 Table 29 FIFO_THR Settings and the Corresponding FIFO Thresholds Overflow margin FIFO 13 56 bytes FIFO THR 13 Underflow margin 8 bytes RXFIFO TXFIFO Figure 20 Example of FIFOs at Threshold MDMCFG1 CHANSPC_E registers The channel spacing registers are mantissa and exponent respectively The base or start frequency is set by the 24 bit frequency word located in the FREQ2 FREQ1 and FREQO registers This word will typically Page 44 of 89 be set to the centre of the lowest channel frequency that is to be used The desired channel number is programmed with the 8 bit channel number register 62900 CHANNR CHAN which is multiplied by the channel offset The resultant carrier frequ
117. om the signal bandwidth The following example illustrates this With the channel filter bandwidth set to 600 kHz the signal should stay within 80 of 600 62900 kHz which is 480 kHz Assuming 2 44 GHz frequency and 20 ppm frequency uncertainty for both the transmitting device and the receiving device total frequency uncertainty is 40 ppm of 2 44 GHz which is 98 kHz If the whole transmitted signal bandwidth is to be received within 480 kHz the transmitted signal bandwidth should be maximum 480 kHz 2 98 kHz which is 284 kHz The 202500 supports the following channel filter bandwidths MDMCFGA MDMCFG4 CHANBW E CHANBW M 00 01 10 11 00 812 406 203 102 01 650 325 162 81 10 541 270 135 68 11 464 232 116 58 Table 20 Channel Filter Bandwidths kHz assuming a 26 MHz crystal 14 Demodulator Symbol Synchronizer and Data Decision 662500 contains an advanced and highly configurable demodulator Channel filtering and frequency offset compensation is performed digitally To generate the RSSI level see Section 17 3 for more information the signal level in the channel is estimated Data filtering is also included for enhanced performance 14 1 Frequency Offset Compensation When using 2 FSK GFSK or MSK modulation the demodulator will compensate for the offset between the transmitter and receiver frequency within certain limits by estimating
118. only be issued in the IDLE TXFIFO_UNDERLOW or RXFIFO_OVERFLOW states Both FIFOs are flushed when going to the SLEEP state Figure 9 gives a brief overview of different register access types possible 10 6 PATABLE Access The address is used to access the PATABLE which is used for selecting PA power control settings The PATABLE is an 8 byte table but not all entries into this table are used The entries to use are selected by the 3 bit value FRENDO PA POWER e When using 2 FSK GFSK or MSK modulation only the first entry into this table is used index 0 Page 24 of 89 e When using OOK modulation the first two entries into this table are used index 0 and index 1 Since the PATABLE is an 8 byte table the table is written and read from the lowest setting 0 to the highest 7 one byte at a time An index counter is used to control the access to the table This counter is incremented each time a byte is read or written to the table and set to the lowest index when is high When the highest value is reached the counter restarts at The access to the PATABLE is either single byte or burst access depending on the burst bit When using burst access the index counter will count up when reaching 7 the counter will restart at 0 The R W bit controls whether the Read or write register s X lt Headerreg x Read or write consecutive registers burst Header n Data
119. ontrol Bit Field Name Reset R W Description 7 6 MAX DVGA GAIN 1 0 0 00 R W Reduces the maximum allowable DVGA gain Setting Allowable DVGA settings 0 00 All gain settings can be used 1 01 The highest gain setting can not be used 2 10 The 2 highest gain settings can not be used 3 11 The 3 highest gain settings can not be used 5 3 MAX LNA GAIN 2 0 0 000 R W Sets the maximum allowable LNA LNA 2 gain relative to the maximum possible gain Setting Maximum allowable LNA LNA 2 gain 0 000 Maximum possible LNA LNA 2 gain 1 001 Approx 2 6 dB below maximum possible gain 2 010 Approx 6 1 dB below maximum possible gain 3 011 Approx 7 4 dB below maximum possible gain 4 100 Approx 9 2 dB below maximum possible gain 5 101 Approx 11 5 dB below maximum possible gain 6 110 Approx 14 6 dB below maximum possible gain 7 111 Approx 17 1 dB below maximum possible gain 2 0 MAGN TARGET 2 0 3 011 R W These bits set the target value for the averaged amplitude from the digital channel filter 1 LSB 0 dB TEXAS INSTRUMENTS Setting Target amplitude from channel filter 0 000 24 dB 1 001 27 dB 2 010 30 dB 3 011 33 dB 4 100 36 dB 5 101 38 dB 6 110 40 dB 7 111 42 dB SWRS040C Page 75 of 89 62900 0x1C AGCCTRL1 AGC Control Bit Field Name Reset R W Description 7 Reserved RO 6 AGC_LNA_PRIORITY 1
120. ord found 1 5 mA Only voltage regulator to digital part and crystal oscillator running IDLE state 7 4 mA Only the frequency synthesizer is running FSTXON state This current consumption is also representative for the other intermediate states when going from IDLE to RX or TX including the calibration state Current consumption 17 0 mA Receive mode 2 4 kBaud input at sensitivity limit RX states MDMCFG2 DEM DCFILT OFF 0 14 5 mA Receive mode 2 4 kBaud input well above sensitivity limit MDMCFG2 DEM_DCFILT_OFF 0 17 3 Receive mode 10 kBaud input at sensitivity limit MDMCFG2 DEM_DCFILT_OFF 0 14 9 mA Receive mode 10 kBaud input well above sensitivity limit MDMCFG2 DEM_DCFILT_OFF 0 18 8 mA Receive mode 250 kBaud input at sensitivity limit MDMCFG2 DEM_DCFILT_OFF 0 15 7 mA Receive mode 250 kBaud input well above sensitivity limit MDMCFG2 DEM_DCFILT_OFF 0 16 6 mA Receive mode 250 kBaud current optimized input at sensitivity limit MOMCFG2 DEM_DCFILT_OFF 1 13 3 Receive mode 250 kBaud current optimized input well above sensitivity limit MDMCFG2 DEM DCFILT OFF 19 6 mA Receive mode 500 kBaud input at sensitivity limit MDMCFG2 DEM_DCFILT_OFF 0 17 0 Receive mode 500 kBaud input well above sensitivity limit MDMCFG2 DEM_DCFILT_OFF 0 SWRS040C Page 7 of 89 TEXAS INSTRUMENTS 62900 Current consumption 11 1 mA Transmit mode 12 dBm output
121. p is not in the SLEEP state When the power and XOSC is enabled the clock used by the WOR timer is a divided XOSC 9 TEXAS INSTRUMENTS 6202500 clock When the chip goes to the SLEEP state the RC oscillator will use the last valid calibration result The frequency of the RC oscillator is locked to the main crystal frequency divided by 750 In applications where the radio wakes up very often typically several times every second it is possible to do the RC oscillator calibration once then turn off calibration WORCTRL RC_CAL 0 to reduce the current consumption This requires that RC oscillator calibration values are read from registers RCCTRLO_STATUS and RCCTRL1_STATUS and written back to RCCTRLO and RCCTRLO respectively If the RC oscillator calibration is turned off it will have to be manually turned on again if temperature and supply voltage changes Refer to Application Note 047 3 for further details 19 6 Timing The radio controller controls most timing in 662500 such as synthesizer calibration PLL lock time and RX TX turnaround times Timing from IDLE to RX and IDLE to TX is constant dependent on the auto calibration setting RX TX and TX RX turnaround times are constant The calibration time is constant 18739 clock periods Table 28 shows timing in crystal clock cycles for key state transitions Power on time and XOSC start up times are variable but within the limits stated in Table 7 Note that
122. r MCSM2 Changes to wake on radio control register WORCTRL RES 1 0 settings 10 and 11 changed to Not Applicable NA Added more detailed information on PO TIMEOUT in register MCSMO Added description of programming bits in registers FOCCFG BSCFG AGCCTRLO FREND1 Changes to ordering information 1 1 2005 10 20 MDMCFG2 7 used 26 27 MHz crystal range Chapter 15 description of the 2 optional append bytes Added matching information Added information about using a reference signal instead of a crystal CRC can only be checked by append bytes or AUTOFLUSH Added equation for calculating RSSI in dBm Selectivity performance graphs added 1 0 2005 01 24 First preliminary release TEXAS INSTRUMENTS Table 38 Document History SWRS040C Page 89 of 89 TEXAS INSTRUMENTS www ti com PACKAGING INFORMATION PACKAGE OPTION ADDENDUM 26 Oct 2015 Orderable Device Status Package Type Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Op Temp Device Marking Samples Drawing Qty 2 6 3 4 5 CC2500 RTR1 OBSOLETE VQFN RTK 20 TBD Call TI Call TI 40 to 85 CC2500 CC2500 RTY1 OBSOLETE VQFN RTK 20 TBD Call TI Call TI 40 to 85 CC2500 CC2500RGP ACTIVE QFN RGP 20 92 Green RoHS CU NIPDAU Level 3 260C 168 HR 40 to 85 CC2500 amp no Sb Br Samples CC2500RGPR ACTIVE QFN RGP 20 3000 Green RoHS CU NIPDAU Call Tl Level 3 260C 168 HR 40 to
123. requency Hopping Multi Channel Systems The 2 400 2 4835 GHz band is shared by many systems both in industrial office and home environments It is therefore recommended to use frequency hopping spread spectrum FHSS or a multi channel protocol because the frequency diversity makes the system more robust with respect to interference from other systems operating in the same frequency band FHSS also combats multipath fading 662500 is highly suited for FHSS or multi channel systems due to its agile frequency synthesizer effective communication interface Using the packet handling support and data buffering is also beneficial in such systems as these features will significantly offload the host controller Charge pump current VCO current and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for 662500 There are 3 ways of obtaining the calibration data from the chip 1 Frequency hopping with calibration for each hop The PLL calibration time is approximately 720 us The blanking interval between each frequency hop is then approximately 810 us 2 Fast frequency hopping without calibration for each hop can be done by calibrating each frequency at startup and saving the resulting FSCAL3 FSCAL2 and FSCALI register values in MCU memory Between each frequency hop the calibration process can then be replaced by writing the FSCAL3 FSCAL2 and FSCAL1 register v
124. required pin voltages in Table 1 and Table 13 are not exceeded The voltage regulator for the digital core requires external decoupling capacitor Setting the CSn pin low turns on the voltage regulator to the digital core and starts the crystal oscillator The so pin on the SPI interface must go low before the first positive edge of SCLK setup time is given in Table 16 24 Output Power Programming The RF output power level from the device has two levels of programmability as illustrated in Figure 21 The RF output power level from the device is programmed through the PATABLE register e f 2 FSK GFSK or modulation is used the desired output power is programmed to index 0 in the PATABLE register PATABLE 0 7 0 The 3 bit FRENDO PA POWER value shall be set to 0 reset default value e f OOK modulation is used the desired output power for the logic 0 and logic 1 power levels are programmed to index 0 and index 1 in the PATABLE register respectively PATABLE 0 7 0 PATABLE 1 7 0 The 3 bit 9 TEXAS INSTRUMENTS SWRS040C 62900 If the chip is programmed to enter power down mode SPWD strobe issued the power will be turned off after goes high The power crystal oscillator will be turned on again when CSn goes low The voltage regulator output should only be used for driving the 662500 FRENDO PA POWER value shall be set to 1 Ta
125. ress When the R W bit is zero the TX FIFO is accessed and the RX FIFO is accessed when the R W bit is one 9 TEXAS INSTRUMENTS SWRS040C 62900 The TX FIFO is write only while the RX FIFO is read only The burst bit is used to determine if the FIFO access is a single byte access or a burst access The single byte access method expects a header byte with the burst bit set to zero and one data byte After the data byte a new header byte is expected hence CSn can remain low The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high The following header bytes access the FIFOs e Ox3F Single byte access to TX FIFO e Ox7F Burst access to TX FIFO e OxBF Single byte access to RX FIFO e OxFF Burst access to RX FIFO When writing to the TX FIFO the status byte see Section 10 1 is output for each new data byte on So as shown in Figure 7 This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO When the last byte that fits in the TX FIFO is transmitted on 51 the status byte received concurrently on So will indicate that one byte is free in the TX FIFO The TX FIFO may be flushed by issuing a SFTX command strobe Similarly a SFRX command strobe will flush the RX FIFO A SFTX SFRX command strobe can
126. rogram the PKTLEN register to mod 600 256 88 e Transmit at least 345 bytes for example by filling the 64 byte TX FIFO six times 384 bytes transmitted 62900 e Set PKTCTRLO LENGTH _CONFIG 0 e The transmission ends when the packet counter reaches 88 A total of 600 bytes are transmitted Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again Infinite packet length enabled Fixed packet length x 600 bytes transmitted and enabled when less than received 256 bytes remains of packet Length field transmitted and received Rx and Tx PKTLEN value set to mod 600 256 88 Figure 12 Packet Length gt 256 15 3 Packet Filtering in Receive Mode 002800 supports three different types of packet filtering address filtering maximum length filtering and CRC filtering 15 3 1 Address Filtering Setting PKTCTRL1 ADR CHK to any other value than zero enables the packet address filter The packet handler engine will compare the destination address byte in the packet with the programmed node address in the ADDR register and the 0x00 broadcast address when PKTCTRL1 ADR 10 or both 0x00 and OxFF broadcast addresses when PKTCTRLI ADR CHK 11 If the received address matches a valid address the packet is received and written into the RX FIFO If the address match fails the packet is discarded and receive mode restarted regardless of the MCSM1 RXOFF MODE setting
127. ros 101010101 The minimum length of the preamble is programmable When enabling TX the modulator will start transmitting the preamble When the programmed number of preamble bytes has been transmitted the modulator will send the sync word and then data from the TX FIFO if data is available If the TX FIFO is empty the modulator will continue to send preamble bytes until the first byte is written to the TX FIFO The modulator will then send the sync word and then the data bytes The number of preamble bytes is programmed with the MDMCFG1 NUM PREAMBLE Value The synchronization word is a two byte value set in the SYNC1 and SYNCO registers The sync word provides byte synchronization of the incoming packet A one byte sync word can be emulated by setting the svNC1 value to the preamble pattern It is also possible to emulate a 32 bit sync word by using MDMCFG2 SYNC MODE 3 or 7 The sync word will then be repeated twice 662500 supports both fixed packet length protocols and variable packet length protocols Variable or fixed packet length mode can be used for packets up to 255 bytes For longer packets infinite packet length mode must be used Fixed packet length mode is selected by setting PKTCTRLO LENGTH_CONFIG 0 The desired packet length is set by the PKTLEN register In variable packet length mode PKTCTRLO LENGTH_CONFIG 1 the packet length is configured by the first byte after the sync word Th
128. s RF P RF N 0 3 2 0 V and DCOUPL Voltage ramp up rate 120 kV us Input RF level 10 Storage temperature range 50 150 Solder reflow temperature 260 C According to IPC JEDEC J STD 020D ESD lt 500 V According to JEDEC STD 22 method A114 Human Body Model Table 1 Absolute Maximum Ratings 2 Operating Conditions 262500 operating conditions are listed in Table 2 below Parameter Min Max Unit Condition Note Operating temperature 40 85 Operating supply voltage 1 8 3 6 V All supply pins must have the same voltage Table 2 Operating Conditions 3 General Characteristics Parameter Min Typ Max Unit Condition Note Frequency range 2400 2483 5 MHz There will be spurious signals at n 2 crystal oscillator frequency n is an integer number RF frequencies at n 2 crystal oscillator frequency should therefore be avoided e g 2405 2418 2431 2444 2457 2470 and 2483 MHz when using a 26 MHz crystal Data rate 1 2 500 kBaud 2 FSK 1 2 250 kBaud GFSK and OOK 26 500 kBaud Shaped MSK also known as differential offset QPSK Optional Manchester encoding the data rate in kbps will be half the baud rate Table 3 General Characteristics SWRS040C Page 6 of 89 TEXAS INSTRUMENTS 4 Electrical Specifications 4 1 Current Consumption 62900 25 C VDD 3 0 V if nothing else stated All measurement results obtained using the CC2500E
129. s a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the industry standard classifications peak solder temperature There may be additional marking which relates to the logo the lot trace code information or the environmental category on the device 6 Multiple Device Markings will be inside parentheses Only one Device Marking contained in parentheses and separated by a will appear on a device If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device Addendum Page 1 H PACKAGE OPTION ADDENDUM TEXAS INSTRUMENTS www ti com 26 Oct 2015 9 Finish Orderable Devices may have multiple material finish options Finish options are separated by a vertical ruled line Lead Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width Important Information and Disclaimer The information provided on this page repr
130. s are digitised by the ADCs Automatic gain control AGC fine channel filtering demodulation bit packet synchronization are performed digitally The transmitter part of 662500 is based on direct synthesis of the RF frequency The frequency synthesizer includes completely on chip LC VCO and a 90 degrees phase shifter for generating the and Q LO 7 Application Circuit Only a few external components are required for using the 0028900 The recommended application circuit is shown in Figure 3 The external components are described in Table 14 and typical values are given in Table 15 9 TEXAS INSTRUMENTS SWRS040C signals to the down conversion mixers receive mode A crystal is to be connected to xosc o1 and XOSC Q2 The crystal oscillator generates the reference frequency for the synthesizer as well as clocks for the ADC and the digital part A 4 wire SPI serial interface is used for configuration and data buffer access The digital baseband includes support for channel configuration packet handling and data buffering Bias Resistor The bias resistor R171 accurate bias current Balun and RF Matching is used to set an The components between the N RF P pins and the point where the two signals are joined together C122 C132 L121 and L131 form a Page 17 of 89 balun that converts the differential RF signal on 662500 to a single ended RF signal C121 and C131 are needed for DC blocki
131. s on the MCU See Section 28 on page 51 for more details on the signals that can be programmed GDO1 is shared with the So pin in the SPI interface The default setting for 1 50 is 3 state output By selecting any other of the programming options the 01 50 pin will become a generic pin When is low the pin will always function as a normal so pin In the synchronous and asynchronous serial modes the pin is used as a serial TX data input pin while in transmit mode Page 25 of 89 The GDOO can also be used for an on chip analog temperature sensor By measuring the voltage on the GDoO pin with an external ADC the temperature be calculated Specifications for the temperature sensor are found in Section 4 7 on page 14 With default PTEST register setting Ox7F the temperature sensor output is only available when the frequency synthesizer is enabled e g the MANCAL FSTXON RX and TX states It is necessary to write OxBF to the PTEST register to use the analog temperature sensor in the IDLE state Before leaving the IDLE state the PTEST register should be restored to its default value 0x7F 11 3 Optional Radio Control Feature The 662500 has an optional way of controlling the radio by reusing SI SCLK and CSn from the SPI interface This feature allows for a simple three pin control of the major states of the radio SLEEP IDLE RX and TX This optional functionality is enabled
132. solution see Table 9 This feature can be used to compensate for frequency offset and drift The frequency offset between an external transmitter and the receiver is measured in the 662500 and can be read back from the FREQEST status register as described in Section 14 1 The measured frequency offset can be used to calibrate the frequency using the external transmitter as the reference That is the received signal of the device will match the receiver s channel filter better In the same way the centre frequency of the transmitted signal will match the external transmitter s signal 31 7 Spectrum Efficient Modulation 662500 also has the possibility to use Gaussian shaped 2 FSK This spectrum shaping feature improves adjacent channel power ACP and occupied bandwidth In true 2 FSK systems with abrupt frequency shifting the spectrum is inherently broad By making the frequency shift softer the spectrum can be made significantly narrower Thus higher data rates can be transmitted in the same bandwidth using GFSK 31 8 A differential antenna will eliminate the need for a balun and the DC biasing can be achieved in the antenna topology see Figure Low Cost Systems Antenna 62900 3 The 25 Folded Dipole reference design 8 contains schematics and layout files for a CC2500EM with a folded dipole PCB antenna Please see DNOO4 9 for more details on t
133. t Typ current consumption lt S EN Typ 11 1mA at 12dBm output st STX or RXOFF MODE 10 _ x Consumption 15 1mA at 6dBm output Transmit mode Receive mode _ from 13 3mA strong 21 2mA at 0dBm output g Ss an input signal to 16 6mA SRX or TXOFF MODE 11 S weak input signal TXOFF MODE 00 RXOFF MOD 00 Optional transitional state j In FIFO based modes Y M Current consumption 7 4mA In FIFO based modes transmission is turned off UN EN Pd reception is turned off and and this state entered if the f TX FIFO Optional freq a RX FIFO N this state entered if the RX TX FIFO becomes empty in underflow synth calibration overflow FIFO overflows Typ the middle of a packet Typ Tak ___ current consumption current consumption 1 5mA B 1 5mA X bs e i we M sra S Idle mi Figure 5 Simplified State Diagram with Typical Usage and Current Consumption at 250 kBaud Data Rate and MDMCFG2 DEM_DCFILT_OFF 1 current optimized 9 Configuration Software 0022800 can be configured using the SmartRF After chip reset all the registers have default Studio software 5 The SmartRF Studio values as shown in the tables in Section 32 software is highly recommended for obtaining The optimum register setting might differ from optimum register settings and for evaluatin
134. t Field Name Reset R W Description 7 6 FREQ 23 22 1 01 R FREQ 23 22 is always binary 01 the FREQ register is in the range 85 to 95 with 26 27 MHz crystal 5 0 FREQ 21 16 30 R W FREQ 23 0 is the base frequency for the frequency synthesiser in increments of Fxosc 2 6 p 23 0 6 0x0E FREQ1 Frequency Control Word Middle Byte Bit Field Name Reset R W Description 7 0 15 8 196 0 4 R W Ref FREQ register 0x0F FREQO Frequency Control Word Low Byte Bit Field Name Reset R W Description 7 0 FREQ 7 0 236 OxEC R W Ref FREQ register SWRS040C Page 65 of 89 TEXAS INSTRUMENTS 62900 0x10 MDMCFG4 Modem Configuration Bit Field Name Reset R W Description 7 6 CHANBW E 1 0 2 10 R W 5 4 CHANBW_M 1 0 0 00 R W Sets the decimation ratio for the delta sigma ADC input stream and thus the channel bandwidth fxosc W 7 8 4 CHANBW _ 2 lt The default values give 203 kHz channel filter bandwidth assuming a 26 0 MHz crystal 3 0 DRATE_E 3 0 12 1100 R W The exponent of the user specified symbol rate 0x11 MDMCFG3 Modem Configuration Bit Field Name Reset R W Description 7 0 DRATE M 7 0 34 0x22 R W The mantissa of the user specified symbol rate The symbol rate is config
135. t be read out of the FIFO before receiving the current packet The MCU must not read from the current packet until the CRC has been checked as OK 15 4 CRC Check There are two different CRC implementations PKTCTRLO CC2400_EN selects between the 2 options The CRC check is different for the 2 Page 31 of 89 options Refer also to the 662500 Errata Notes 1 15 4 1 PKTCTRLO CC2400_EN 0 If PKTCTRLO CC2400_EN 0 it is possible to read back the CRC status in 2 different ways 1 Set PKTCTRL1 APPEND_STATUS 1 and read the CRC_OK flag in the MSB of the second byte appended to the RX FIFO after the packet data This requires double buffering of the packet i e the entire packet content of the RX FIFO must be completely read out before it is possible to check whether the CRC indication is OK or not 2 To avoid reading the entire RX FIFO another solution is to use the PKTCTRL1 CRC_AUTOFLUSH feature If this feature is enabled the entire RX FIFO will be flushed if the CRC check fails If GDOx_CFG 0x06 the GDox pin will be asserted when a sync word is found The pin will be de asserted at the end of the packet When the latter occurs the MCU should read the number of bytes in the RX FIFO from the RXBYTES NUM RXBYTES status register If RXBYTES NUM RXBYTES 0 the CRC check failed and the FIFO is flushed f RXBYTES NUM_RXBYTES gt 0 the CRC check was OK and data can be read out of the FIFO
136. t length is larger than 64 bytes the MCU must determine how many bytes can be read from the RX FIFO RXBYTES NUM RXBYTES 1 and the following software routine can be used Page 43 of 89 1 Read RXBYTES NUM RXBYTES repeatedly at a rate guaranteed to be at least twice that of which RF bytes are received until the same value is returned twice store value in n 2 If n lt of bytes remaining in packet read n 1 bytes from the RX FIFO 3 Repeat steps 1 and 2 until n of bytes remaining in the packet 4 Read the remaining bytes from the RX FIFO The 4 bit FIFOTHR FIFO_THR setting is used to program threshold points in the FIFOs Table 29 lists the 16 FIFO_THR settings and the corresponding thresholds for the RX and TX FIFOs The threshold value is coded in opposite directions for the RX FIFO and TX FIFO This gives equal margin to the overflow and underflow conditions when the threshold is reached A signal will assert when the number of bytes in the FIFO is equal to or higher than the programmed threshold The signal can be viewed on the GDO pins see Section 28 on page 51 Figure 20 shows the number of bytes in both the RX FIFO and TX FIFO when the threshold flag toggles in the case of FIFO THR 13 Figure 19 shows the signal as the respective FIFO is filled above the threshold and then drained below GDO rxevres 6 7 8 9 10 e 8 7 e GDO Figure 19 FIFO_THR 13 vs Number
137. tables After chip reset all the registers have default values as shown in the tables The optimum register setting might differ from the default value After a reset all registers that shall be different from the default value therefore needs to be programmed through the SPI interface There are 13 command strobe registers listed in Table 34 Accessing these registers will initiate the change of an internal state or mode There are 47 normal 8 bit configuration registers listed in Table 35 Many of these registers are for test purposes only and need not be written for normal operation of 662500 662300 There are also 12 status registers which are listed in Table 36 These registers which are read only contain information about the status of 662500 The two FIFOs are accessed through one 8 bit register Write operations write to the TX FIFO while read operations read from the RX FIFO During the header byte transfer and while writing data to a register or the TX FIFO a status byte is returned on the so line This status byte is described in Table 17 on page 23 Table 37 summarizes the SPI address space The address to use is given by adding the base address to the left and the burst and R W bits on the top Note that the burst bit has different meaning for base addresses above and below Ox2F Address Strobe Description Name 0x30 SRES Reset chip 0x31 SFSTXON Enable and
138. that can be written to the TX FIFO When FIFO BYTES AVAILABLE 15 15 or more bytes are available free Table 17 gives a status byte summary Bits Name Description 7 CHIP RDYn the SPI interface Stays high until power and crystal have stabilized Should always be low when using 6 4 STATE 2 0 Indicates the current main state machine mode Value State Description 000 IDLE Idle state Also reported for some transitional states instead of SETTLING or CALIBRATE 001 RX Receive mode 010 TX Transmit mode 011 FSTXON Frequency synthesizer is on ready to start transmitting 100 CALIBRATE Frequency synthesizer calibration is running 101 SETTLING PLL is settling 110 RXFIFO OVERFLOW RX FIFO has overflowed Read out any useful data then flush the FIFO with SFRX 111 TXFIFO UNDERFLOW TXFIFO has underflowed Acknowledge with SFTX 3 0 BYTES AVAILABLE 3 0 The number of bytes available in the RX FIFO or free bytes in the TX FIFO Table 17 Status Byte Summary 10 2 Register Access The configuration registers of the 662500 are located on SPI addresses from 0x00 to Ox2E Table 35 on page 58 lists all configuration registers It is highly recommended to use SmartRF Studio 5 to generate optimum register settings The detailed description of each register is found in Section 32 1 starting on page 61 All configur
139. the original data in the presence of some bit errors The use of FEC allows correct reception at a lower SNR thus extending communication range Alternatively for a given SNR using FEC decreases the bit error rate BER As the packet error rate PER is related to BER by PER 1 E 1 _ 2 length a lower BER can be used to allow longer packets or a higher percentage of packets of a given length to be transmitted successfully Finally in realistic ISM radio environments transient and time varying phenomena will 9 TEXAS INSTRUMENTS SWRS040C produce occasional errors even in otherwise good reception conditions FEC will mask such errors and combined with interleaving of the coded data even correct relatively long periods of faulty reception burst errors The FEC scheme adopted for 202500 convolutional coding in which n bits are generated based on k input bits and the m most recent input bits forming a code stream able to withstand a certain number of bit errors between each coding state the m bit window The convolutional coder is a rate 1 2 code with a constraint length of m 4 The coder codes one input bit and produces two output bits hence the effective data rate is halved l e to transmit at the same effective data rate when using FEC it is necessary to use twice as high over the air data rate This will require a higher receiver bandwidth and thus reduce sensitivity In o
140. ther words the improved reception by using FEC and the degraded sensitivity from a higher receiver bandwidth will be counteracting factors 18 2 Interleaving Data received through radio channels will often experience burst errors due to Page 37 of 89 interference and time varying signal strengths In order to increase the robustness to errors spanning multiple bits interleaving is used when FEC is enabled After de interleaving a continuous span of errors in the received stream will become single errors spread apart 662500 employs matrix interleaving which is illustrated Figure 14 The on chip interleaving and de interleaving buffers are 4 x 4 matrices In the transmitter the data bits from the rate gt convolutional coder are written into the rows of the matrix whereas the bit sequence to be transmitted is read from the columns of the matrix Conversely in the receiver the received symbols are written into the rows of the matrix whereas the data passed onto the convolutional decoder is read from the columns of the matrix Interleaver Write buffer 62900 When FEC and interleaving is used at least one extra byte is required for trellis termination In addition the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer two bytes The packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet so that the total length of t
141. threshold with hysteresis e CS is asserted when the RSSI has increased with a programmable number of dB from one RSSI sample to the next and 9 TEXAS INSTRUMENTS SWRS040C de asserted when RSSI has decreased with the same number of dB This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor Carrier Sense can be used as a sync word qualifier that requires the signal level to be higher than the threshold for a sync word search to be performed The signal can also be observed on one of the pins by setting Page 35 of 89 IOCFGx GDOx_CFG 14 and in the status register bit PKTSTATUS CS Other uses of Carrier Sense include the TX if CCA function see Section 17 5 on page 37 and the optional fast RX termination see Section 19 7 on page 43 CS can be used to avoid interference from e g WLAN 17 4 1 CS Absolute Threshold The absolute threshold related to the RSSI value depends on the following register fields e AGCCTRL2 MAX LNA GAIN AGCCTRL2 MAX DVGA GAIN e AGCCTRLI CARRIER SENSE ABS e AGCCTRL2 MAGN TARGET For a given AGCCTRL2 MAX LNA GAIN and AGCCTRL2 MAX DVGA GAIN setting the absolute threshold can be adjusted 7 dB in steps of 1 dB using CARRIER SENSE ABS THR The MAGN TARGET setting is a compromise between blocker tolerance selectivity and sensitivity The valu
142. tivity limit 250 rejection kHz channel spacing See Figure 22 for plot of selectivity versus frequency offset Blocking Wanted signal 3 dB above sensitivity level 10 MHz offset 64 dBm Compliant with ETSI EN 300 440 class 2 receiver 20 MHz offset 70 dBm equirements 50 MHz offset 71 dBm 10 kBaud data rate sensitivity optimized MDMCFG2 DEM DCFILT 2 FSK 196 packet error rate 20 bytes packet length 232 kHz digital channel filter bandwidth Receiver sensitivity 99 dBm The RX current consumption be reduced by approximately 1 7 mA by setting MDMCFG2 DEM_DCFILT_OFF 1 The typical sensitivity is then 97 dBm The sensitivity can be improved to typically 101 dBm with MDMCFG2 DEM_DCFILT_OFF 0 by programming registers TEST2 and TEST1 see page 82 The temperature range is then from 0 C to 85 C Saturation 9 Adjacent channel 18 dB Desired channel 3 dB above the sensitivity limit 250 rejection kHz channel spacing Alternate channel 25 dB Desired channel 3 dB above the sensitivity limit 250 rejection kHz channel spacing See Figure 23 for plot of selectivity versus frequency offset Blocking Wanted signal 3 dB above sensitivity level 10 MHz offset 59 dB Compliant with ETSI EN 300 440 class 2 receiver 20 MHz offset 65 requirements 50 MHz offset 66 dB SWRS040C Page 9 of 89 TEXAS INSTRUMENTS 62900 Parameter Min Typ Max Unit Cond
143. tput power 0 X Modulation 2F5K Channel number RX fiterbandwidth Reset 2500 and write settings Copy settings to Register View Register Attributes Components T PA ramping value OxFB RF output power gt PATABLE FREQ2 050 RF Frequency gt FREGQ 23 15 FREQ1 093 RF Frequency gt 15 8 FREQO 0x81 RF Frequency gt FREG 0 FSCTRL1 0x08 IF Frequency gt FREG_IF 4 0 gt 203 13 kHz FSCTALO 0x00 RF Frequency offset gt FREQOFF 0 MOMCFG4 0x86 Data rate exponent gt DRATE_E Channel bandwidth exponent gt CHANBW_E Channel bandwidth mantissa gt CHANBW MDMCFG3 0x83 Data rate mantissa gt DRATE M MOMCFG2 0x03 T Manchester Rx filterbandwidth 203125000 kHz Sensitiv rity Curent Sensitivity Current Sensitivity Current z MDMCFGO 0x14 OxF8 DEVIATN 0x15 0x47 9 MCSM2 015 0x07 MCSM1 0x17 0x30 MCSMO 0x18 0x04 29 FOCCFG 0x19 0x76 Length config varise 71 Packet lenath 255 Packet count 200 Simple RX Simple TX Packet RX Packet TX PER test Sync ward 30 22 71 RE Mt FEG Address config No addre Address Manual Init FIFO Autoflush J BSCFG 0x14 Ox6C l ABCCTAL 2 1711 MARCSTATE 1 IDLE 7 IDLE Frequency offset 0 0 kHz RSSI OBW 93 6 kHz H View format Hex X CRCOK Sync RX Loc
144. transfer is enabled several of the support mechanisms for the MCU that are included 262500 will be disabled such as packet handling hardware buffering in the FIFO and so on The asynchronous transfer mode does not allow the use of the data whitener interleaver and FEC and it is not possible to use Manchester encoding Note that MSK is not supported for asynchronous transfer Setting PKTCTRLO PKT_FORMAT to 3 enables asynchronous serial mode In TX the pin is used for data input TX data Data output be on GDOO GDO1 or GDO2 This is set by the TOCFGO GDOO IOCFG1 GDO1 and IOCFG2 GDO2 fields 662500 modulator samples the level of the asynchronous input 8 times faster than the programmed data rate The timing requirement for the asynchronous stream is that the error in the bit period must be less than one eighth of the programmed data rate 30 2 Synchronous Serial Operation Setting PKTCTRLO PKT FORMAT to 1 enables synchronous serial mode In the synchronous serial mode data is transferred on a two wire serial interface The 662500 provides a clock that is used to set up new data on the data input line or sample data on the data output line Data input TX data is the GDOO pin This pin will automatically be configured as an input when TX is active The data output pin can be any of the pins this is set by the IOCFGO GDOO IOCFG1 GDO1 and IOCFG2
145. ts Table 6 RF Transmit Section SWRS040C Page 11 of 89 TEXAS INSTRUMENTS 44 Crystal Oscillator Tc 25 C VDD 3 0 V if nothing else stated 62900 Parameter Min Typ Max Unit Condition Note Crystal frequency 26 26 27 MHz Tolerance 40 ppm This is the total tolerance including a initial tolerance b crystal loading c aging and d temperature dependence The acceptable crystal tolerance depends on RF frequency and channel spacing bandwidth ESR 100 Q Start up time 150 us Measured CC2500EM reference design 4 using crystal AT 41CD2 from NDK This parameter is to a large degree crystal dependent Table 7 Crystal Oscillator Parameters 4 5 Low Power RC Oscillator Tc 25 C VDD 3 0 V if nothing else stated All measurement results obtained using the CC2500EM reference design i4 Parameter Min Typ Max Unit Condition Note Calibrated frequency 34 7 34 7 36 kHz Calibrated RC oscillator frequency is XTAL frequency divided by 750 Frequency accuracy after 1 The RC oscillator contains an error in the calibration 10 calibration routine that statistically occurs in 17 3 of all calibrations performed The given maximum accuracy figures account for the calibration error Refer also to the 662500 Errata Notes Temperature coefficient 0 4 95 Frequency drift when temperature changes after calibration
146. ty information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material a MSL Peak Temp The Moisture Sensitivity Level rating according to the industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better
147. ualifier If sync word detection in RX is enabled in register MDMCFG2 the 202900 will not start filling the RX FIFO and perform the packet filtering described in Section 15 3 before a valid sync word has been detected The sync word qualifier mode is set by MDMCFG2 SYNC MODE and is summarized in Table 24 Carrier sense in Table 24 is described in Section 17 4 MDMCFG2 Sync Word Qualifier Mode SYNC_MODE 000 No preamble sync 001 15 16 sync word bits detected 010 16 16 sync word bits detected 011 30 32 sync word bits detected 100 No preamble sync carrier sense above threshold 101 15 16 carrier sense above threshold 110 16 16 carrier sense above threshold 111 30 32 carrier sense above threshold Table 24 Sync Word Qualifier Mode 17 2 Preamble Quality Threshold PQT The Preamble Quality Threshold PQT sync word qualifier adds the requirement that the received sync word must be preceded with a preamble with a quality above a programmed threshold Another use of the preamble quality threshold is as a qualifier for the optional RX termination timer See Section 19 7 on page 43 for details 9 TEXAS INSTRUMENTS SWRS040C The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit and decreases the counter by 8 each time a bit is received that is the same as the last bit The threshold is configured with
148. ured using an unsigned floating point number with 9 bit mantissa and 4 bit exponent The 9 bit is a hidden 1 The resulting data rate is _ 256 DRATE 29 Rpara 228 4 f XOSC The default values give a data rate of 115 051 kBaud closest setting to 115 2 kBaud assuming a 26 0 MHz crystal SWRS040C Page 66 of 89 TEXAS INSTRUMENTS 62900 0x12 MDMCFG2 Modem Configuration Bit Field Name Reset R W Description DEM DCFILT OFF 0 R W Disable digital DC blocking filter before demodulator 0 Enable better sensitivity 1 Disable current optimized Only for data rates lt 250 kBaud The recommended IF frequency changes when the DC blocking is disabled Please use SmartRF Studio 5 to calculate correct register setting 6 4 MOD_FORMAT 2 0 0 000 R W The modulation format of the radio signal Setting Modulation format 2 FSK GFSK OOK MSK MANCHESTER_EN R W Enables Manchester encoding decoding 0 Disable 1 Enable 2 0 SYNC_MODE 2 0 2 010 R W Combined sync word qualifier mode The values 0 000 and 4 100 disables preamble and sync word transmission in TX and preamble and sync word detection in RX The values 1 001 2 010 5 101 and 6 110 enables 16 bit sync word transmission in TX and 16 bits sync word detection in RX Only 15 of 16 bits need to match i
149. ut counts RC oscillator periods WOR mode does not need to be enabled The timeout counter resolution is limited With RX TIME O the timeout count is given by the 13 MSBs of EVENTO decreasing to the 7 MSBs of EVENTO with RX TIME 6 TEXAS INSTRUMENTS SWRS040C Page 70 of 89 0x17 MCSM1 Main Radio Control State Machine Configuration 662300 Bit Field Name Reset R W Description 7 6 Reserved RO 5 4 1 0 3 11 R W Selects CCA MODE Reflected in CCA signal Setting Clear channel indication 0 00 Always 1 01 If RSSI below threshold 2 10 Unless currently receiving a packet 3 11 If RSSI below threshold unless currently receiving a packet 3 2 RXOFF_MODE 1 0 0 00 R W Select what should happen when a packet has been received Setting Next state after finishing packet reception 0 00 IDLE 1 01 FSTXON 2 10 TX 3 11 Stay in RX It is not possible to set RXOFF MODE to be TX or FSTXON and at the same time use CCA 1 0 MODET 1 0 0 00 R W Select what should happen when a packet has been sent TX Setting Next state after finishing packet transmission 0 00 IDLE 1 01 FSTXON 2 10 Stay in TX start sending preamble 3 11 RX SWRS040C Page 71 of 89 TEXAS INSTRUMENTS 62900 0x18 MCSMO Main Radio Control State Machine Configuration Bit Field Name Reset R W Description
150. ut for QLP 20 package Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple Each decoupling J 62900 follow the 2500 reference designs 4 as closely as possible Gerber files for the reference designs are available for download from the website capacitor should be connected to the power line by separate vias The best routing is from the power line to the decoupling capacitor and then to the 662500 supply pin Supply power filtering is very important Each decoupling capacitor ground pad should be connected to the ground plane using a separate via Direct connections between neighboring power pins will increase noise coupling and should be avoided unless absolutely necessary The external components should ideally be as small as possible 0402 is recommended and surface mount devices highly recommended Please note that components smaller than those specified may have differing characteristics Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry CC2500 2550DK Development Kit with a fully assembled CC2500EM Evaluation Module is available It is strongly advised that this reference layout is followed very closely in order to get the best performance The schematic BOM and layout Gerber files are all available from the TI website 4 EE j Figure
151. ut power of 1 W 430 dBm is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz In addition the peak power spectral density conducted to the antenna shall not be greater than 8 dBm in any 3 kHz band Operating at high data rates high frequency separation the 662500 is suited for systems targeting compliance with digital modulation systems as defined by FCC part 15 247 An external power amplifier is needed to increase the output above 1 dBm 31 4 Data Burst Transmissions The high maximum data rate of 662500 opens up for burst transmissions A low average data rate link e g 10 kBaud can be realized using a higher over the air data rate Buffering the data and transmitting in bursts at high data rate e g 500 kBaud will reduce the time in active mode and hence also reduce the average current consumption significantly Reducing the time in active mode will reduce the likelihood of collisions with other systems e g WLAN 31 5 Continuous Transmissions In data streaming applications the 002000 opens up for continuous transmissions at 500 kBaud effective data rate As the modulation is done with a closed loop PLL there is no limitation in the length of transmission Open loop modulation used in some transceivers often prevents this kind of continuous data streaming and reduces the effective data rate Page 55 of 89 31 6 Crystal Drift Compensation The 662500 has a very fine frequency re
152. utput Power PATABLE Current Consumption Typical 25 3 0 V dBm Value Typical mA 55 or less 0x00 8 4 30 0 50 9 9 28 0x44 9 7 26 0xCO 10 2 24 0x84 10 1 22 0x81 10 0 20 0x46 10 1 18 0x93 11 7 16 0x55 10 8 14 0x8D 12 2 12 0xC6 11 1 10 0x97 12 2 8 Ox6E 14 1 6 Ox7F 15 0 4 0 9 16 2 2 OxBB 17 7 0 OxFE 21 2 1 OxFF 21 5 Table 31 Optimum PATABLE Settings for Various Output Power Levels TEXAS INSTRUMENTS SWRS040C Page 47 of 89 62900 25 Selectivity Figure 22 to Figure 26 show the typical selectivity performance adjacent and alternate rejection hs 22290 40 L INL EC Selectivity dB Frequency offset MHz Figure 22 Typical Selectivity at 2 4 kBaud IF Frequency is 273 9 kHz MDMCFG2 DEM DCFILT OFF 40 49 gt A 20 Selectivity dB Frequency offset MHz Figure 23 Typical Selectivity at 10 kBaud IF Frequency is 273 9 kHz MDMCFG2 DEM_DCFILT_OFF 1 SWRS040C Page 48 of 89 TEXAS INSTRUMENTS 62900 Selectivity dB 5 34 Frequency offset MHz Figure 24 Typical Selectivity at 250 kBaud IF Frequency is 177 7 kHz MDMCFG2 DEM_DCFILT_OFF 0 AT Selectivity dB 5 29 Freque
153. vent 1 follows Event 0 after a programmed timeout The time between two consecutive Event 0 is programmed with a mantissa value given by WOREVT1 EVENTO and WOREVTO EVENTO and an exponent value set by WORCTRL WOR_RES The equation is Evento EVENTO _ RES XOSC The Event 1 timeout is programmed with WORCTRL EVENT1 Figure 18 shows the timing relationship between Event O timeout and Event 1 timeout Rx timeout see SEEP DE RX See DENR EventO X Eventi EventO Event tevento Figure 18 Event 0 and Event 1 Relationship The time from the 662500 enters SLEEP state until the next Event 0 is programmed to appear ts_cep in Figure 18 should be larger than 11 08 ms when using a 26 MHz crystal and 10 67 ms when a 27 MHz crystal is used If is less than 11 08 10 67 ms there is chance that the consecutive Event 0 will occur E 128 seconds XOSC too early Application Note ANO47 3 explains in detail the theory of operation and the different registers involved when using WOR as well as highlighting important aspects when using WOR mode 19 5 1 RC Oscillator and Timing The frequency of the low power RC oscillator used for the WOR functionality varies with temperature and supply voltage In order to keep the frequency as accurate as possible the RC oscillator will be calibrated whenever possible which is when the XOSC is running and the chi
154. ync word is found or PQT is set when RX TIME QUAL 1 2 0 RX TIME 2 0 7 111 R W Timeout for sync word search in RX for both WOR mode and normal RX operation The timeout is relative to the programmed EVENTO timeout The RX timeout in us is given by EVENTO C RX TIME WOR RES 26 X where C is given by the table below and Xis the crystal oscillator frequency in MHz RX TIME 2 0 WOR RES 0 RES 1 WOR RES 2 WOR RES 3 0 000 3 6058 18 0288 32 4519 46 8750 1 001 1 8029 9 0144 16 2260 23 4375 2 010 0 9014 4 5072 8 1130 11 7188 3 011 0 4507 2 2536 4 0565 5 8594 4 100 0 2254 1 1268 2 0282 2 9297 5 101 0 1127 0 5634 1 0141 1 4648 6 110 0 0563 0 2817 0 5071 0 7324 7 111 Until end of packet As an example EVENT0 34666 WOR RES 0 and RX TIME 6 corresponds to 1 95 ms RX timeout 1 s polling interval and 0 195 duty cycle Note that WOR RES should be 0 or 1 when using WOR because using WOR RES gt 1 will give a very low duty cycle In applications where WOR is not used all settings of WOR RES can be used The duty cycle using WOR is approximated by RX TIME 2 0 WOR RES 0 RES 1 0 000 12 50 1 95 1 001 6 250 9765 ppm 2 010 3 125 4883 ppm 3 011 1 563 2441 ppm 4 100 0 781 NA 5 101 0 391 NA 6 110 0 195 NA 7 111 NA Note that the RC oscillator must be enabled in order to use setting 0 6 because the timeo
155. ytes Bit Field Name Reset R W Description 7 TXFIFO UNDERFLOW 6 0 NUM TXBYTES Number of bytes in TX FIFO TEXAS INSTRUMENTS SWRS040C Page 83 of 89 62900 0x3B OxFB RXBYTES Underflow and Number of Bytes Bit Field Name Reset R W Description 7 RXFIFO_OVERFLOW 6 0 NUM_RXBYTES Number of bytes in RX FIFO 0x3C OxFC RCCTRL1 STATUS Last RC Oscillator Calibration Result Bit Field Name Reset R W Description 7 Reserved RO 6 0 RCCTRL1_STATUSJ 6 0 R Contains the value from the last run of the RC oscillator calibration routine For usage description refer to 047 3 0x3D OxFC RCCTRLO STATUS Last RC Oscillator Calibration Result Bit Field Name Reset R W Description 7 Reserved RO 6 0 RCCTRLO STATUS 6 0 R Contains the value from the last run of the RC oscillator calibration routine For usage description refer to 047 3 TEXAS INSTRUMENTS SWRS040C Page 84 of 89 62900 33 Package Description QFN 20 33 1 Recommended PCB Layout for Package QFN 20 2 4ldmm B 20mm 2 BDBmm 0 76mm 4 Smm 0 28mm Figure 30 Recommended PCB Layout for QFN 20 Package Note The figure is an illustration only and not to scale There are five 10 mil diameter via holes distributed symmetrically in the ground pad under the package See also the CC2500EM reference design 4 3

CC2500 - Texas Instruments

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