SETHER - Electrocomponents
Contents
1. Page 12 Arcom Control Systems Ltd Section 4 Circuit Description J193 SETHER Section 4 Circuit Description The core of the SETHER is the DP8390 Network Interface Chip IC20 which handles all the media access control to the Eth ernet The NIC interchanges packets of information via dual port memory IC14 using an on chip DMA controller The SETHER also includes 28 pin EPROM socket IC9 for network BIOS software a PROM socket IC11 for the Ethernet burned in address and a control register IC7 The control register is used to set the base address of the RAM buffer control the local reset and enable or disable the RAM bit assignments shown below Bit 7 SETHER board reset high Bit6 RAM Enabled high Bit5 18 Bit4 17 Bit3 16 Bit2 15 Bit 1 14 A13 The base addresses for the I O registers and EPROM space are decoded by 74 688 IC21 and IC6 respectively and Link areas 12 and 6 A part of the RAM buffer base address A18 A13 is selected by the value written to the control register and compared by IC4 Bit A19is selected by Bit 7 of the control register serves as a software invoked reset The board is reset when this bit is set high this board reset will also clear the control register thus removing the local reset Bit 6 is used to enable access when high to the RAM from the STEbus A2. r r r r 11 4 ADe OnT 10 t t 63 ro Je 1 10nF DISC CER ATNROS LKSF ATNRQ4 LKSE ATNRO3 LKSD ATNRQS amp ATNRGZX LKSC BTNRQeEX ATNROL LKSB ATNRAI X Lk ATNRGOX CONTROL SYSTEMS LTD 2N7000 This drawing is the 14 5 GND OP eoMHz XSTAL MODULE Title property of Arcom Control Systems Ltd and must not a 2 SETHER DC DC CONUERTER be copied or disclosed without written consent C 1990 Rx DATA Arcom Control Systems Ltd LAST ACCESSED 23 Nov 1994 Page 30 J193 SETHER ircuit Diagrams Appendix E C CONTROL SYSTEMS LTD GND C32 45 C31 12 C30 ces ice ATNRQTK C28 ATNRQSX ce5 ATNRQ3X C24 ATNROLK C23 SYSRSTK 22 GND czl DATSTB 20 GND 18 CM1 18 amp 18 17 amp 1 C18 32 45 630 SYSCLK h28 Res A27 GN
3. 0x20 Monitor mode eputb TCR 0 eputb PSTOP STOP PG eputb PSTART STRT Mem stop start eputb BNRY STRT PG Mem boundary eputb ISR 1 eputb IMR 0 Clear amp mask all interrupts rpage 1 Reg page 1 for 1 0 i i eputb PARO i 5 1 Set Phys addr for i 0 i i eputb MARO i 0 Set Mcast addr to 0 eputb CURR STRT 1 Current page start l 0 eputb CMDR 0x22 Reg page 0 start 8390 eputb RCRW promisc 0x14 0x04 Accept Bcast also promiscuous Get packet into buffer return length 0 if none received getpack buff Length includes dest addr srce addr type unsigned char buff unsigned curr bdry raddr unsigned stat plen pl p2 rpage 1 curr egetb CURR Page after the incoming data rpage 0 bdry egetb BNRY Page of data already read wrapp bdry 1 Move up to unread page if curr bdry return 0 Return 0 if nothing received raddr bdry lt 8 Calculate addr of unread page stat peekb raddr RSEG Get status and length of packet plen peekw raddr 2 RSEG HWB Deduct 4 hardware bytes from len if stat amp 1 plenMAXPACK If error in packet ignore it plen 0 else No error in packet copy it if plen raddr RAM If packet wraps around end of RAM pl STOP RAM raddr HWB copy it in 2
4. Link 3 RAM base address A19 LK3 Insert to respond if A19 low The RAM can appear at any multiple of its size in STEbus memory space A18 13 are software programmable but this link defines A19 On reset the base address is set to80000H and the RAM is disabled By default the software will generally set the RAM base address to be D0000H and RAM will be enabled Link 5 ATNRQ select LK5A Interrupt on ATNRQO LK5B Interrupt on ATNRQ1 LK5C Interrupt on ATNRQ2 LK5D Interrupt on ATNRQ3 LK5E Interrupt on ATNRQ4 LK5F Interrupt on ATNRQ5 LK5G Interrupt on ATNRQ6 LK5H Interrupt on ATNRQ7 Link 6 ROM socket base address LK6A Respond if A14 low LK6B Respond if A15 low LK6C Respond if A16 low LK6D Respond if A17 low LK6E Respond if A18 low LK6F Respond if A19 low The ROM can be mapped to any 16K boundary The default link settings map the ROM at address D8000H Page 8 Arcom Control Systems Ltd Section 3 Hardware Installation Note Arcom Control Systems Ltd J193 SETHER Link 7 Disable ROM space LK7 Insert to disable ROM Link 8 Ethernet burned in address PROM high low select LK8 select the top half of the Ethernet burned in address PROM This link should be inserted to make the boards compatible with the standard drivers supplied on the distribution disk Link 9 and 10 ROM device size select LK9 LK10 B B 2764 8k B B 27128
5. 16k B A 27258 32k A A 27512 64k Link 11 RAM device size select LK11 Insert for 62256 32k Omit for 6264 8k Link area 12 l O base address LK12A Respond if A5 low LK12B Respond if A6 low LK12C Respond if A7 low LK12D Respond if A8 low LK12bE Respond if A9 low LK12F Respond if A10 low LK12G Respond if A11 low The I O address can be mapped to any 32 byte boundary of the STEbus space 000 to FEO Inserting a link in this area sets the corresponding register base address bit low The default link settings map the I O at address 280H Link 13 Connect 12V to AUI cable LK13 Insert to connect 12v to an external transceiver unit MAU Link 14 Enable Thin Wire Ethernet Transceiver Interface 4 LK 14A TX LK 14B TX LK 14C RX LK 14D RX LK 14E CD LK 14F CD Page 9 J193 SETHER Installation Section 3 Hardware Installation These links transfer the outputs from the Serial Network Inter face chip DP8391 to the isolation transformer and on to the Coaxial Transceiver Interface DP8392 If the D15 connector is used to drive an external thick thin wire transceiver unit all LK14 links should be removed Link 15 Network Segment Length Option LK15 Insert for standard IEEE 802 3 networks Omit for extended segment lengths Each standard Ethernet segment has a maximum length of 185m If itis necessary to expand this up to 300m then Link 15 should be in
6. ACTOO DP8391 Ethernet Serial Network Interface ACT373 DP8392 Ethernet Co axial Transceiver Interface for thin wire networks 2N7000 N channel Enhancement MOSFET 1N4148 0 1 inch Red LED 0 1 inch Green LED 820K 10k 330R 130R 1MO 39R 1k0 270R 4k7 C SIL 510R 22uF 16V Tantalum 100nF 25V Ceramic 47uF 16V Aluminium 10nF 25V Ceramic 10nF 1kV Ceramic Quad 1 1 DIL package isolation transformers 20MHz Oscillator Module Page 17 J193 SETHER Appendix B STE Bus Connections Appendix B STE Bus Connections Page 18 PL1 is the 64 way STEbus connector Pin Row A GND 45V DO D2 D4 D6 AO A2 A4 A6 A8 A10 A12 A14 A16 A18 CMO CM2 ADRSTB DATACK TRFERR ATNRQO ATNRQ2 ATNRQ4 ATNRQ6 GND BUSRQO BUSAKO SYSCLCK 12V 45V GND A13 A15 A17 A19 CM1 GND DATSTB GND SYSRST ATNRQ1 ATNRQ3 ATNRQ5 ATNRQ7 BUSRQI BUSAK1 VSTBY 412V 5V GND Arcom Control Systems Ltd Appendix C Specification Arcom Control Systems Ltd J193 SETHER Appendix C Specification Operating temperature Power consumption Bus Interrupts 5 C to 55 C 5v 1 0A typical 12v depends on the MAU transceiver STEbus 32 bytes 8K 32K RAM packet buffer 8K 16K 32K 64K BIOS extension EPROM Recommended EPROM type 27128 Maximum access time 250ns ATNRQO 7 no bus vectored acknowledge Page 19
7. J193 SETHER Appendix D Example Program Appendix D Example Program SETHMON C Simple Written in Aztec Borland C For use on an Arcom PC with SETHER card Compile amp link using Aztec Ethernet Monitor JPB 9 8 91 This utility takes in packets from the network and displays them small model low level drivers in ETHER C c sethmon c ether c Borland bcc sethmon c ether c replace while kbhit with while 1 and To use on a target system link in the standard target files Copyright c Arcom Control Systems Ltd 1991 define ADRLEN 6 No of bytes in ethernet address define MAXDATA 1500 Maximum Ethernet data size Data type definitions typedef unsigned long uint32 32 bit unsigned typedef unsigned short uintl6 16 bit unsigned typedef unsigned char uint8 8 bit unsigned Data structures struct dlinkh Datalink Ethernet header uint8 dadr ADRLEN Destination Enet addr ADRLEN Source Enet addr uint16 type Enet packet type length field MOST SIGNIFICANT BYTE IS FIRST typedef struct dlinkh DHEAD struct dlinkp Datalink Ethernet packet DHEAD uint8 typedef struct dlinkp DPKT DPKT rxd extern int promisc extern unsigned char myeth Prototypes void swap uintl6 p void Pr6byt uint8 str void hexdump uint8
8. Joo Jr fon jun s co fra Je ZACK DATSTB ZMRD NADD I P 170 ZRAMOE 1 0 2N7000 Title SETHER OE DUAL PORT RAM ARBITRATION 1 RDO RD 9 PAGE2 Drawing No This drawing is the property of Arcom Control Systems Ltd and must not be copied or disclosed without written consent C LAST ACCESSED 23 Nov 1994 Page 29 Arcom Control Systems Ltd ircuit Diagrams Appendix E J193 SETHER RDO RD i 1 24 4ACTOO ces 2 4ACT373 30 70 50 5a 50 4Q 4D 3Q 3D eD ro co js ejm Joo 1Q EN 10 OE RAe RA15 1 ZACK NIC_GNT BREQ ADSO cs MWR MRD SUR SRD RAL RAZ INT RESET PUR READY PRD ACK PRQ ADS1 BACK BREG ATNRO LKSH ATNRQ LK ATNRQ6 LKSG WACK RACK GND ENABLE TX IDLE VOLTAGE e IC22 8391 SEL RxD CRS RXC LBK TXD TXC TXE 1 ucc ucc Tx DATA CRED NM1600 Ti 16 15 14 13 12
9. base address Only the higher image should be used I O base 08H to I O base 0FH for compatibility with comparable PC bus boards The format of the burned in address is shown by the following I O register map Offset Write Read 0 Board Control Register Do Not Use 1 7 Do Not Use 8 Burned in address byte 0 9 Burned in address byte 1 A Burned in address byte 2 B Burned in address byte 3 C Burned in address byte 4 D Burned in address byte 5 E Type Byte F Checksum Byte 10 1F 8390 Controller Registers The DP8390 NIC and DP8391 SNI both require a 20MHz clock input to drive the 10 Mbits s Ethernet transmission The clock has a high specification in order to comply with the IEEE 802 3 limit of 0 0196 absolute accuracy The tolerance must be 0 001 25deg C with a stability of 0 005 in the range 0 70 deg C This is achieved by using the crystal module XL1 The 8391 SNI provides the Manchester data encoding and decoding for the IEEE802 3 Ethernet The device includes the differential Tx data line drivers with 270R pull down resistors on the outputs R1 R4 and differential line receivers for the Rx and collision detect CD signals These input lines must be terminated if used with the standard 78 ohm AUI cable with 78 ohm loads This is provided by two 39R resistors in series which are then by passed to GND Arcom Control Systems Ltd Section 4 Cir
10. buff int getpack void buff void main uintl6 type len printf Simple promisc 1 Page 20 data MAXDATA Datalink header Data area Rx datalink packet buffer Promiscuous physical addr flag My ether addr from ROM int len Ethernet Monitor Wn Enable promiscuous mode Arcom Control Systems Ltd Appendix D Example Program J193 SETHER if etinit Initialise hardware printf ERROR can t access Ethernet card Wn exit 0 printf My Ethernet address is Print Burned In Addr pr byt myeth printf nWaiting for packet press any key to exit n while kbhit Loop until key hit if len getpack amp rxd 0 If packet recd printf From pr byt rxd d sadr Print header printf to pr byt rxd d dadr type rxd d type swap amp type Byte swap type printf type len 04X hex n type before printing hexdump rxd data len sizeof DHEAD Dump rest of packet void swap Swap bytes in int uintl6 p uint8 c q q uint8 p q 9 1 1 void pr byt str Print a 6 byt thernet address uint8 str int i if str 5 Oxff printf BROADCAST return printf 02x str t for i 1 i ADRLEN i printf 02x strt t ifndef BO
11. extern int _dsval Data seg value from linker endif define MAXPACK 1514 Maximum packet size excl hardware bytes define MINPACK 60 Minimum packet size unsigned char myeth 6 My Ethernet addr from ROM int promisc 0 Flag to enable promiscuous mode Prototypes void etopen unsigned char s unsigned addr int getpack unsigned char buff int putpack unsigned char pack unsigned len int egetb int port void eputb int port int byt void rpage int n int wrapp int page int etinit Initialise card return 0 if error int i sum 0 for i20 i itt Get 6 byte h ware addr sum myeth i egetb AROM ti keeping sum of bytes sum egetb AROM 6 Add on 7th 8th bytes sum egetb AROM 7 if sum amp Oxff Oxff return 0 total should be FF eputb W83CREG MSK RESET Reset card eputb W83CREG 0 etopen myeth RSEG Set up card return 1 Arcom Control Systems Ltd Page 23 J193 SETHER Appendix D Example Program void etopen s addr Set up hardware unsigned char s Ethernet addr unsigned addr Mem addr IDE 3 4 eputb W83CREG addr gt 9 Set dual port RAM addr rpage 0 Reg page 0 abort remote DMA eputb DCR 0x48 FIFO 8 bytes no loopback eputb RBCRO 0 eputb RBCR1 0 Clear remote byte count eputb RCRW
12. high performance interface between STEbus based processor systems and the IEEE 802 3 Ethernet network Ethernet is a 10 Mbits s high performance networking system allowing many different types of computer PCs STEbus VMEbus to interchange messages and share files hard disks and other peripherals This manual provides a brief overview of Ethernet and shows how the SETHER board is implemented The SETHER utilises the National Semicon ductor DP8390 Ethernet chip set which consists of the DP8390 Network Interface Chip NIC DP8391 Serial Network Interface SNI and DP8392 Coaxial Transceiver Interface CTI A number of network driver packages are available from Arcom for DOS based OS 9 systems and standalone target systems For detailed hardware and programming information relating to the 8390 chip set refer to the National Semiconductors Data Comms Local Area Network UART Handbook The board includes two useful LED s to indicate when data is being received or transmitted by the 8390 NIC Features include Full STEbus slave interface Full Ethernet interface e Thin wire Ethernet Cheapernet interface e National Semiconductors DP8390 controller chip e Software compatible with PCbus Ethernet board e Ethernet BIOS ROM socket e Dual port RAM with local DMA e LED indication of Ethernet Rx and Tx traffic e Interrupts on any level ATNRQO 7 e SETHER board network burned in address stored in PROM Complete TCP IP pro
13. int page if page STOP PG return if page STRT PG return return page Arcom Control Systems Ltd n lt 6 0x20 Read byte from card register Write byte to card register Select 8390 register page Abort remote DMA Return a wrapped value of Rx memory page STRT_PG STOP_PG 1 Wrap if overflow Wrap if underflow Page 25 J193 SETHER Copyright Equates for SETHER WD8003 c SETHER 8003E 8003 define W83CREG 0 define MSK RESET 0x80 define MSK ENASH 0x40 define MSK DECOD Ox3Fh On board 1 define AROM To keep compatibility with all 3 boards 8390 define CM CL PS CL define PS define B define define define define define define define define FI define define define define define define define define define define define define define define C T define C D E define 8390 define define define PA CU MA Page 26 DR DAO TART DA1 TOP RY RO RR RO 8 0x10 0x11 0 11 0 12 0 12 0 13 0 14 0 14 0 15 0 15 0 16 0 16 0 17 0 18 0 18 0 19 0 19 1 Ox1B Ox1C Ox1C Ox1D Ox1D 1 1 1 1 0 11 0 17 0 18 E WD8003EB Arcom Control Systems Append
14. intervention The 8390 treats the RAM area as a Page 5 J193 SETHER Page 6 Section 2 Ethernet IEEE 802 3 circular buffer and will only cease reception if the buffer is full The format of the received packet is as described above but with a 4 byte hardware header 1 byte packet status 1 byte next hardware page 2 bytes packet length The status byte mirrors the Receive Status Register at the time of reception if bit O is set the packet is error free The next hardware page refers to the next 256 byte block of dual port RAM used by the 8390 The packet length is in low high byte order and includes the length of the 4 byte hardware header A simple Ethernet monitor program written in Aztec C has been included in Appendix D of this manual It uses promiscu ous mode which means that all network packets are received irrespective of destination address This mode is useful for network diagnosis though it will result in a very high data throughput if used on a heavily loaded network Arcom Control Systems Ltd Section 3 Hardware Installation J193 SETHER Section 3 Hardware Installation Storage and Handling The SETHER is supplied in static protective packing It is important that normal precautions against static should be observed at all times The boards should always be kept in dry conditions at a con trolled temperature Under the terms of Arcom s warranty any boards returned with damage
15. missed pkt for rd interrupt mask reg for wr LAN Controller pagel register offset for read and write physical addr reg 0 for rd and wr current page reg for rd and wr multicast addr reg 0 for rd and WR Arcom Control Systems Ltd Appendix D Example Program J193 SETHER Buffer Length and Field Definition Info define HWB 4 define STRT PG 6 define STOP PG 32 define STRT RAM STRT PG 8 define STOP RAM STOP PG 8 Arcom Control Systems Ltd Number of bytes in hardware header Receive buffer start page Receive buffer end page Receive buffer start addr Receive buffer end addr Page 27 J193 SETHER Appendix E AUI Connector Pin Assignments Appendix E AUI Connector Pin Assignments 15 GND 14 12V 13 RX 12 GND 11 PL2 AUI Connector PL2 AUI Connector GND n c GND RX GND TX CD GND NUAR ODN 28 Arcom Control Systems Ltd J193 SETHER ircuit Diagrams Appendix E C it Diagrams Appendix E C ico 74HCT244 BAO BA1S 2A4 ev4 2A3 ev3 leae eva 2A1 evi 1794 1Y4 163 1Y3 182 1Y2 tal 1Y1 1G 26 1 j Ice 4HCTZ4 lea4 2Y4 ev3 2A2 evel 281 evi 174 1Y4 163 1Y3 182 ive 161 1Y1 1G 26 1 8 Ics T4HCT24
16. 2A4 2Y4 BAS 13 2A3 v3 BA4 11 eve BA3 2A1 evi BAZ 1A4 1Y4 BAL 163 1Y3 182 1Y2 171 1Y1 16 26 1 ZSRAEN SRDEN 1 1 s SDBEN 1 0 DATSTB 16 SRD i 2 I P 1 0 BA4 15 PROM 1 9 IC18 PALL BR4 BA13 co oo n ZROMOE ZROMADD A14 gr WR 26 avs 2113 Aiz ALL A10 AS AS AS A4 le AL jo ZR amp MOE ZRAMCE IC16 74ACT245 BD RD RAO RA1S BDE Wd Ba RDG A PAGE 2 BDS Bo RDS BD4 AS B5 RD4 BD3 ps BS RD3 P4 RDZ BD1 bis RDL A2 un BDO Be RDO AL AB EN BL SDBEN ZRAMADD CLK 1 0 170 I P 14 LATCH BREG 1 0 ZRAMCE 1 ZRAMUR BCM ZIOADD 13 NIC ZSRAEN O7P ZSRDEN 170 ZSYSRST 12 MRST ZROMADD LATCH_ST DATSTB OP STE_GNT n Jen fs co no I P OP 1l SRST ZSTE GNT RAMADD IvP NIC GNT I DATSTB Set ADRSTBX DATACK I I ZADRSTB rcom CONTROL SYSTEMS LTD TRL _ eo
17. 4 a2 lea4 ev4 lea3 ev3 AL BAL ao zaz evel SYSRST eaters SYSRST cme 1A4 1Y4 ACCESS OF ADDRESS PROM IC11 SETHER BOARD ADDRESS PROM CATCH LKS 745288 ADDRESS DUAL PORT RAM Ic 74HCT273 BD L ud 07 4 A4 06 8D BDG 05 BDS 7D ipei RAM ADD A19 HI BAO BA1S EPROM SIZE IC4 SELECT 4HCT688 LK10 17 18 ate Q 15 BA19 LK 9 ao 13 IPs as BA18 gt DE BDA 60 BAL Bez az 04 1 BD3 5D 59 lla 04 8 P3 BA16 BAL 02 BDZ 4D 40 BAIS x BDI 30 fon v Joo Bee 01 20 20 BDO Beis B 18 BAL BAIG BAIS Qn B 17 Ice ROM BASE ADDRESS 74HcT688 DEFAULT 08099 P 0718 LK4 az 15 ae Pe 0518 EKSE BA14 B 13 e 11 14 LKED PS 05 3 P4 0412 LKRC LK2 8 0313 93 LKGB ROM SIZE SELECT be 92 Pi 015 5 4 2 Po 003 Q7H 1 CS2H 4 ZADRS EN P a T f fis TB ROMADD P6H Pa4a LK I DISABLE RP2 T ROM 1 0 BA
18. D 26 ATNROBX h25 ATNRO4X h24 ATNROZX h 23 ATNROOX h22 21 2 ADRSTB ALS cuzg Al8 1 18316 16 115 A14 Al4 al2z Al3 a1g Ale amp 8 R11 LK13 tle vc CONNECT 120 TO MaU MODULE Title SETHER 900206 This drawing is the property of Arcom Control Systems Ltd and must not be copied or disclosed without written consent C 1990 LAST ACCESSED 23 Nov 1994 Page 31 Arcom Control Systems Ltd
19. J193 SETHER SETHER STEbus Ethernet Network Board User s Manual Contents Section Page 1 Introduction 3 The SETHER Board and Ethernet 3 Features 3 2 Ethernet IEEE 802 3 4 Introduction 4 Ethernet Packet Structure 5 3 Hardware Installation 7 Storage and Handling 7 Links and Options 7 Installation 10 Network Cabling and Connectors 10 4 Circuit Description 13 5 Troubleshooting 16 Appendix A Component List 17 B STEbus Connector Pin Assignments 18 C Specification 19 D Example Program 20 E AUI Connector Pin Assignments 28 F Circuit Diagrams 29 Arcom Control Systems Ltd 1991 Arcom Control Systems Ltd Page 1 J193 SETHER Revision History Revision History Manual PCB Comments V1 Iss 2 V1 Iss 2 900807 First Full Release V2 Iss 1 V2 Iss 1 910807 Released in new format ECO 418 Various edits New example program V2 Iss 1a 920809 ECO837 915 V2 Iss 1b 940809 New AUI Connector Diagram Arcom Control Systems Ltd Cambridge England 1991 The choice of boards or systems is the responsibility of the buyer and the use to which they are put cannot be the liability of Arcom Control Systems Ltd However Arcom s sales team is always available to assist you in making your decision Page 2 Arcom Control Systems Ltd Section 1 Introduction J193 SETHER Section 1 Introduction The SETHER board and Ethernet Arcom Control Systems Ltd The SETHER board provides a
20. RLANDC kbhit Return true if key hit return bdos 0xb 0 0 fendif void hexdump buff len Print hex dump of buffer uint8 buff int len int i J m n uint8 c str 17 n len 16 for i120 i n att if 1 gt 0 printf 04x i 16 for j 0 j 16 j if 1 gt 0 if j 8 printf Arcom Control Systems Ltd Page 21 J193 SETHER Appendix D Example Program printf 02x c buff i 16 j str j gt amp amp c lt Po else printf str j 0 len str j 0 printf Ss n str Page 22 Arcom Control Systems Ltd Appendix D Example Program J193 SETHER SETHER WD8003E WD8003EB Ethernet hardware drivers JPB 9 8 91 Suitable for Aztec or Borland C compilers small model Copyright c Arcom Control Systems Ltd 1991 include ETHER H define IOBASE 0x280 I O base address for Ethernet card define RSEG 0xd000 Segment for dual port RAM buffer ifdef BORLANDC If Borland C all segments and offsets in opposite order to Aztec unsigned char peekb unsigned seg unsigned off define peekb off seg peekb seg off define peekw off seg peek seg off define movblock o1 s1 02 s2 1en movedata sl ol1 s2 02 1len define dsval DS else Otlo define peekb peekb define peekw peekw
21. SE ADDRESS 17 DEFAULT 249 BALL 15 re ag LK12G s 06 CMI 163 1Y3 1 2 1Y2 161 1Y1 16 eG 1 SYSCLK BA1Q 13 LkKi2r e Bes 11 95 12 acs a4 BAS LK1eD e P3 LK12C s BAG P2 _ 128 o s 8 BA 6 4jP1 01 BAS eee wf mt _ Po EN 0 E ZADRSTB Ici 4ACT245S As Bg B6 AS BS A4 B4 A3 B3 Az B2 Joa un f oo Joo D 2 IORDD ADDRESS DECODE AND CONTROL BDO BD DATACK FUNCTIONS Ici2 PAL16LS 15 ZROMOE AL Bl amp 3B EN Eu dn 18 ROMADD 1 70 BCMO 17 SWR 1D 19 CK cL b 1 LATCH STI P2 92 BA14 E 6 pi 01 2 BA13 Ino D EN P ro ey 19 ZRAMADD E ZADRSTB len BA14 ZMRST Bk 32K RAM SELECT IC13 e B813 BAO BA1S 4HCT244 BA1S BA14 za4 2v4 BA13 2A3 ev3 12 eve BALL 2A1 2Y1 BA19 1794 1Y4 BAS 163 1Y3 Bes 182 172 181 1Y1 iG 26 1 ZSRAEN IC19 244 1 S 17 BAG 15
22. attributed to incorrect handling or storage will not be repaired nor replaced free of charge See also the specifications in Appendix C Links and Options This section describes how to set the link defined features The link positions are shown below indicates a standard setting Note that all links are viewed with the pcb edge connector to the right Link Position Diagram 1015 o e D LK3 QA O ciz _ LK16 A Is A B 2 LA LK8 18 ecd sgg Ons LK13 OOs 1013 4 eu pee C oe e LK4 LK2 D LK11 n z E A A A A 53 i 5 X NIE LK7 e nlla 1C11 coo E OU AUS ACH B ala LK12 gt eg G LK6 55 mit Ir foo C 5 n n f rj AN Od fA 1023 R5R3 1021 1C19 ici7 ARCOM CONTROL SYSTEMS LTD cg 0 106 B Default Link Position Arcom Control Systems Ltd Page 7 J193 SETHER Section 3 Hardware Installation Links 1 and 16 RAM buffer size select LK1 LK16 B A 8K RAM A B 32K RAM Links 2 and 4 ROM decode size select LK2 LK4 A A 2764 8k A A 27128 16k B A 27256 32k B B 27512 64k
23. bled The source address is normally the sender s Burned In Address copied from the on board PROM into the 8390 chip This en sures that every Ethernet card has a unique identity no matter how large the network The type length field is used by some protocols to indicate packet length in others it serves as an identifier of the protocol used e g 0806H for ARP 0800H for IP When creating a new protocol it is advisable to choose a unique value for this field to try to avoid clashes with other protocols In accordance with Ethernet standards this field is in high low byte order The user data may be in any format and will be passed across the network unaltered If it is less than 46 bytes long it must be padded with dummy bytes The hardware performs automatic CRC generation and check ing this operation is transparent to the programmer To transmit the packet it is placed at the base of the SETHER dual port RAM and a transmit command is sent to the 8390 Ethernet chip The 8390 will then put the packet onto the network The 8390 returns error codes if it is unable to send the packet e g the retry limit has been exceeded There is no built in mechanism for checking whether the packet has arrived at its destination the higher level protocols are responsible for ensuring an acknowledgement is returned When receive has been enabled the 8390 will automatically stack up incoming packets in the dual port RAM without any processor
24. ccess to the EPROM PROM and control register is inde pendent of NIC accesses to dual port memory The RAM is double buffered and is accessed under the control of the dual port arbiter The arbitration is performed by the 16R4 PAL IC18 and is programmed to give priority to the NIC in preference to a STEbus access Access to the I O registers with in the NIC are arbitrated by the NIC ie when CS and SRD or SWR are asserted the control circuit will wait for an ACK to be asserted by the NIC At this time the data buffers from STEbus to the NIC are enabled and the STEbus access is terminated Device decodes strobe signals and STEbus DATACK are generated by the 22V 10 PAL IC10 and 16L8 PAL IC12 These also use the arbitration signals STE GNT and NIC GNT to enable the appropriate buffers and direction controls STEbus DATACK is driven by NMOS FET TR1 Arcom Control Systems Ltd Page 13 J193 SETHER Page 14 Section 4 Circuit Description The EPROM base address is set by Link area 6 and compared with the STEbus address lines using IC6 Similarly the base address PROM control reg and NIC registers is selected by Link area 12 and IC 21 The base address of RAM set in the control register is compared by IC4 The burned in address PROM 748288 IC11 is a 32byte one time programmable device which is programmed by ARCOM with a valid IEEE Ethernet address This information is mapped twice into the 16 bytes above the I O
25. cuit Description DP8390 Network Controller DP8391 PL1 Ethernet Interface Isolation Transformer DP8392 Thin PL2 Ethernet Transceiver Arcom Control Systems Ltd J193 SETHER The AUI cable output can be used to power the external MAU transceiver unit This 12v 300mA typ supply is connected if Link 13 is made The two LED s are useful for monitoring Ethernet traffic through the board LED1 red and LED2 green indicate activity on the Tx and Rx data lines respectively The RxD and TxD lines of the NIC are connected to two pulse stretching monostables IC24 configured from four high drive current nand gates In order to satisfy the IEEE 802 3 specification for Cheapernet the 8392 Coaxial Transceiver Interface must be fully isolated from the main Ethernet interface This is achieved using pulse transformers T1 to connect the signal lines CD Tx and Tx and a DC DC converter IC15 to provide the isolated 9v supply This device is a 2W 5V to 9V converter Functional Block Diagram Identity PROM STEbus slave Arbiter and interface controller for local RAM ATNRQO 7 Page 15 J193 SETHER Section 5 Troubleshooting Section 5 Troubleshooting Board does not ap pear in memory or ap pears at the wrong address Interrupts do not work correctly Network will not con figure Network configures but board does not appear on the net work Page 16 Chec
26. ix D Example Program Ethernet cards JPB 23 6 90 Ltd 1990 EB control register operations offset from base to reset LAN controller bit to enabl set mem address lines A18 A13 line A19 assumed to be 1 Control reg Control bit Control shared mem Bits to Address Ethernet address ROM ROM offset from I O base addr do not use ROM image at 0 LAN Controller page0 register offset for read and write command register for read amp write current local dma addr 0 for read page start register for write current local dma addr 1 for read page stop register for write boundary reg for rd and wr tx status reg for rd for wr for rd wr tx start page start reg number of collision reg tx byte count 0 reg for FIFO for rd tx byte count 1 reg for wr interrupt status reg for rd and wr current remote dma address 0 for rd remote start address reg 0 for wr current remote dma address 1 for rd remote start address reg 1 for wr remote byte count reg 0 for wr remote byte count reg 1 for wr rx status reg for rd rx configuration reg for wr tally cnt 0 for frm alg err for rd tx configuration reg for wr tally cnt 1 for crc err for rd data configuration reg for wr tally cnt 2 for
27. k address jumpers LK 12 locates the block LK 3 defines the 8K RAM A19 LK6 7 locates the 8K ROM socket LK2 4 9 10 defines the ROM size Ensure that the correct RAM base address has been written to the control register When setting the address jumpers Install a jumper for a zero address bit Remove a jumper for a one address bit Check that the interrupt links are correctly set note that SETHER does not support vectored interrupts 1 Check that at least one other node is connected to the network and itis switched on 2 Check that the network cabling is not faulty 3 Check that 500 terminators are fitted at both ends of the network Check that the node ID is correctly set The identify PROM IC11 can be read I O SPACE Arcom Control Systems Ltd Appendix A Component List IC1 16 1C2 5 8 13 19 24 IC3 IC7 1C6 4 21 IC12 IC10 IC9 IC11 IC18 IC14 IC15 IC20 IC24 IC22 IC17 IC23 TR1 2 D1 LED1 LED2 R6 15 R14 R13 R17 R16 R7 8 10 11 R2 R1 4 RP1 4 R3 5 9 12 C1 2 9 14 18 C3 8 10 13 15 17 19 21 25 29 C12 C20 26 27 28 C16 Ti XL1 Arcom Control Systems Ltd J193 SETHER Appendix A Component List ACT245 HCT244 HCT14 HCT273 HCT688 Comparators PAL16L8 PAL22V10 DATACK functions BIOS ROM Socket 745288 Ethernet Identity PROM PAL16R4 6264 55257 8K 32K RAM 32K fitted as standard NMB0509 45V to 9V DC DC converter DP8390 Ethernet Network Interface Controller
28. ld be noted Arcom Control Systems Ltd Section 3 Hardware Installation Arcom Control Systems Ltd J193 SETHER Minimum separation between nodes 500mm Minimum bend radius of cable 30mm Maximum length of any one segment 185m Maximum number of nodes per segment 30 IMPORTANT NOTE the network cable screen is independent from chassis ground and that ALL CONNECTORS BULK HEAD or LINE MUST BE ISOLATED FROM CHASSIS GROUND Failure to observe this requirement may result in loss of noise immunity Also the BNC pieces should be connected directly onto the SETHER board BNC connector ie do not use any drop cable between these two Thick wire Ethernet uses special multi wire co axial Ethernet cable and can be up to 500m long The SETHER board should be connected to a transceiver unit via a multiple twisted pair 78 ohm impedance drop cable such as Belden 9892 or similar fitted with D15 connectors This cable should be a maximum of 50m long The network should also be terminated with 50 ohm terminators Page 11 J193 SETHER User Configuration Record Sheet User Configuration Record Sheet This sheet may be duplicated LC TS 1 ue i Sem u cy c21 1291 6191 9191 1 35 41 011 V 6 017 13155 1081409 WO2UV BI dU 90 gg 691
29. le with BNC connectors The SETHER board supports interfaces for both Cheapernet and a D15 AUI cable connector for connection to standard Ethernet A comparison of performance characteristics is shown below Parameter Ethernet Cheapernet Data Rate 10 Mbits 10 Mbits Segment Length 500m 185m Network Span 2500m 925m Nodes per Segment 100 30 Node Spacing 2 5m cable marked 0 5m Cable Type Belden 9880 Cheapernet 500 50Q RG58A U Double Shielded Single Shielded Rugged Flexible N Series Connectors BNC Connectors Transceiver Drop Cable Belden 9892 multi way Not needed due to high cable with D15 flexibility of RG59A U connectors max drop cable length 50m Arcom Control Systems Ltd Section 2 Ethernet IEEE 802 3 J193 SETHER Each Ethernet board has a unique 6 byte identifying code stored in PROM and referred to as the burned in address which is issued by the IEEE This identifier is used to indicate the source and the destination of packets transferred on the network the Arcom burned in addresses start at 008066000001 Ethernet Packet Structure Arcom Control Systems Ltd The structure of an Ethernet packet is as follows 6 bytes destination address 6 bytes source address 2 bytes type length field 46 1500 bytes user data If the destination address has all bits set the packet is broadcast and will be received by all nodes that have broadcast reception ena
30. parts p2 plen pl Only 1st part has hardware bytes movblock raddr HWB RSEG buff dsval pl movblock STRT RAM RSEG buff pl _dsval p2 else If no wrap copy whole packet movblock raddr HWB buff _dsval plen wrapp peekb raddr 1 RSEG 1 Move pointer to next packet eputb BNRY return plen Return packet length or 0 Page 24 Arcom Control Systems Ltd Appendix D Example Program Send J193 SETHER return 0 if error putpack pack len unsigned char pack unsigned len Lengt Ethernet packet See above for packet format addr h includes dest srce addr type unsigned timout 60000 Arbitrary timout value while egetb CMDR amp 4 Ensure transmitter is idle if timout return 0 return 0 if timout if len MAXPACK return 0 Error if packet too long movblock pack dsval 0 RSEG len Copy packet into RAM page 0 if len MINPACK len MINPACK Must be gt 60 bytes eputb TBCRO len eputb TBCR1 len gt gt 8 Set length regs eputb TPSR 0 Select transmit page 0 eputb CMDR 0x24 Transmit return len return inportb IOBASE port egetb port v REE outportb byt void eputb port by void rpage n outportb CMDR IOBASE wrapp
31. serted IMPORTANT If this option is selected then the network is limited to a single segment ie no repeaters may be used and also all other SETHER cards on the segment must be set with Link 15 made This configuration does not comply with the electrical specification of IEEE 802 3 The state of Link 15 is only relevant if Thin Wire Ethernet is used ie all Link area 14 are made Link 17 Network Version Select Omit for Ethernet Version 2 IEEE 802 3 networks Cheapernet Insert for older version 1 networks The network version is de termined by the MAU transceiver used for the network This will be indicated on the MAU It is important to follow normal good practice associated with the installation and removal of boards from the backplane Make sure all power to the backplane is off Follow standard anti static precautions including earthed wrist straps and conductive car pets when installing the board If in doubt consult your supplier Network Cabling and Connectors Page 10 Thin wire Ethernet Cheapernet requires RG58A U co axial cable and 50 Ohm BNC connectors Each BNC connector should be fitted with a BNC piece such that the network cabling can continue to the next node If the SETHER board is the last node in the network chain one side of the T piece should be fitted with a 50 ohm terminator The network will not work without terminations fitted at both ends A few important parameters shou
32. tocol package available e Software drivers available from Arcom for various operating systems such as OS 9 Page 3 J193 SETHER Section 2 Ethernet IEEE 802 3 Section 2 Ethernet IEEE 802 3 Introduction Page 4 The DP8390 chip set is designed to provide the physical and media access control layer functions of the local area network as defined by the IEEE 802 3 standard The standard is based on the access method known as carrier sense multiple access with collision detect CSMA CD The operational principle is such that if a network node wants to transmit it first listens to the network for other transmitted traffic If the medium is quiet the network controller will begin transmission while monitoring for a possible collision with another transmitter If two or more stations should simultaneously transmit they will detect the collision and back off for a random amount of time before making another attempt The physical layer of Ethernet may be implemented in two forms according to the performance required from the system Thick wire Ethernet referenced as 10BASE5 uses high specification coaxial cable which is connected to the network node via a transceiver unit Medium Attachment Unit MAU and drop cable Attachment Unit Interface AUI The AUI cable consists of four individually shielded twisted pairs fitted with D15 connectors Thin wire Ethernet or Cheapernet referenced as 10BASE2 uses a more flexible coaxial cab
Download Pdf Manuals
Related Search