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Quartus Reference Manual Vol. 3

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1. clk 1 clk 1 _1 o clk 2 You can set the Quartus Il Timing Analyzer to use these two edges for setup checks You can assign multicycle paths in your designs to instruct the Quartus II Timing Analyzer to relax its measurements thus avoiding incorrect setup or hold time violation reports These assignments are made in the Assignment Editor Assignments menu Multicycle Hold Assignment A Multicycle Hold assignment shown in Figure 4 16 specifies the minimum number of clock cycles required before a register should latch a value If no Multicycle Hold value is specified the Multicycle Hold value defaults to the value of the Multicycle assignment Altera Corporation 4 17 June 2004 Quartus Il Handbook Volume 3 Figure 4 16 Multicycle Hold Assignment Setup b Hold gt Multicycle 2 Multicycle Hold 2 default Offset 0 Source Multicycle Assignment The Source Multicycle assignment shown in Figure 4 17 is useful when the source and destination registers are clocked by related clocks at different frequencies It is used to extend the required delay by adding periods of the source clock rather than the destination clock 4 18 Altera Corporation June 2004 Quartus Il Timing Analysis Figure 4 17 Source Multicycle Assignment Setup _ gt
2. CLK1 5 a CLK2 CLK1 dl DL S a DN a CLK2 Aa A Source Multicycle 2 Offset 0 Source Multicycle Hold Assignment The Source Multicycle Hold assignment is useful when the source and destination registers are clocked by related clocks at different frequencies This assignment allows you to increase the required hold delay by adding source clock cycles Typical Applications of Multicycle Assignments The following examples describe how to use multicycle assignments in your designs Simple Multicycle Paths Figure 4 18 shows the measurement of tsy and ty for a standard path with a multicycle of 1 Altera Corporation 4 19 June 2004 Quartus II Handbook Volume 3 Figure 4 18 tsy and ty Standard Measurement Paths Setup _ gt Hold pe CK re CLK2 CLK1 CLK2 0 12 24 Clock Period 12 ns Multicycle 1 In the example shown in Figure 4 18 both c1k1 and c1k2 have the same period and zero offset In this figure where the clocks have a period of 12 ns the data delay between the source and destination registers must be between 0 ns and 12 ns in order for the circuit to operate If the data delay is longer than one clock period and the circuit is intended to operate as a multicycle circuit you must add a Multicycle assignment of 2 When you make Multicycle or Source Multicyc
3. Figure 9 12 Enabling the Trigger In Signal Status LES 478 Memory 1408 Not running 262 cells 1280 bite Not running 216 cells 128 bits trigger 2003 12 02 10 38 05 3 Lock mode S Allow all changes T Signal Configuration Clock ok Es Data Sample depth Nodes allocated 18 Auto Manuat 1 a ope MK m Buffer acquisition mode Circular amp Pre trigger position la gmeni L C Segmented Trigger Ta Trigger levels 1 Nodes allocated 1 v C Auto Manuat f1 ource tiigger_out_analyzert E TT High TT Trigger out Target JU Level e Hig Latency Delay 4 cycles 9 19 Quartus II Handbook Volume 3 9 20 Embedding Multiple Analyzers in One FPGA The SignalTap II Logic Analyzer includes support for multiple logic analyzers in an FPGA device This feature allows you to create a unique logic analyzer for each clock domain in the design As multiple instances of the analyzer are added to the STP file the LE count increases proportionally In addition to debugging multiple clock domains this feature allows you to apply the same SignalTap II settings to a group of signals in the same clock domain For example if you have a set of signals that must use a sample depth of 64K while another set of signals in the same cloc
4. After the Quartus II software successfully generates the power estimation report file a message will be displayed See Figure 6 7 Figure 6 7 Generate Power Estimation File Message i Generated power estimation file C TEMP qdesigns_v2 0 misc_ex dFff_top_pwr_cal txt Import this file to the Power Calculator that you downloaded from the Altera web site The power estimation report file is named lt name of Quartus II project gt _pwr_cal txt Figure 6 8 is an example of the contents of a power estimation file generated by the Quartus II software version 4 1 Altera Corporation 6 7 June 2004 Quartus Il Handbook Volume 3 Conclusion References 6 8 Figure 6 8 Example of Power Estimation File Power Estimation File for dff_top Do not edit this line lt name DEVICE value EP1525F780C5 gt lt name fmax RC1 value 100 gt lt name ff RC1 value 984 gt lt name fmax LEl value 100 gt lt name tot LEl value 1700 gt lt name totwcc _LEl value 1400 gt lt name fmax GIO1l value 50 gt lt name NumbOB GIO1 value 80 gt lt name avgCLoad_GIO1 value 20 gt lt name iostd_GIO1 value 3 3 LVTTL LVCMOS 24 gt lt name iodatarate GIO1 value SDR gt The Stratix Power Calculator v3 0 Stratix GX Power Calculator v1 3 and Cyclone Power Calculator v1 2 power calculation spreadsheets include the Import Data macro that parses the information in the power estimation file and
5. Quartus Il Software N SHAH QUARTUS oi ye pe KTEREEEREGEFERETEERTERITARITAR Quartus Il Handbook Volume 3 Including the SignalTap Il Logic Analyzer in Your Design 9 2 This handbook chapter discusses the following topics Including the SignalTap II Logic Analyzer in your design Programming the device for SignalTap II analysis Advanced features of the SignalTap II Logic Analyzer Design examples The SignalTap II Logic Analyzer supports the following device families Stratix II Stratix Stratix GX Cyclone II Cyclone APEX II APEX 20KE APEX 20KC APEX 20K Excalibur Mercury There are two ways to build the SignalTap II Logic Analyzer The first method involves creating a SignalTap Il file stp and then defining the details of the STP file The second method involves creating and configuring the STP file with the MegaWizard Plug In Manager and then instantiating the HDL output module from the MegaWizard in your HDL code Figure 9 2 illustrates the process of setting up and using the SignalTap II Logic Analyzer using both methods The diagram shows the flow of operations from the initial MegaWizard custom variation to the final device configuration Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Figure 9 2 SignalTap Il Flow Using the STP File to Create an Embedded Logic Analyzer Creating an STP File The STP file contai
6. Total IO Power 241 14 mw Total 10 Buffer Power 241 14 mw Total Power 476 64 mw Simulation based power estimation reports a more accurate toggle percentage of your design since it calculates the toggle rate based on the simulation waveforms you provide Hence the power estimated by the Quartus II Simulator is more accurate than the Microsoft excel based power calculator The power calculator is explained in the Early Power Estimation chapter in Volume 3 of the Quartus II Handbook It is important to remember that Simulator power results can be only as accurate as the simulation waveforms you provide To achieve the most accurate results your simulation waveforms should mimic the behavior of your design You can use other EDA simulation tools such as Model Technology ModelSim software to perform a simulation that includes power estimation data To do this you must instruct the Quartus II software to include power estimation data in the Verilog Output File vo or VADL Output File vho When you are performing a simulation in another EDA simulation tool the tool uses the power estimation data to generate a Power Input File pwf The PWF file is used in the Quartus II software to estimate the power consumption of your design For more information about how to perform simulations in other EDA simulation tools see the relevant documentation for that tool To perform power estimation using the Quartu
7. FPGA Resources Used by SignalTap II II Using SignalTap II in a Lab Environment Remote Debugging Using SignalTap IT Signal Preservation Tappable Signals Timing Preservation with SignalTap II Logic Analyzer Using SignalTap Il Logic Analyzer to Simultaneously Debug Multiple Designs Locating a Node in the Chip Editor Preserving FPGA Memory You can configure the SignalTap II Logic Analyzer to store captured data in the device RAM or route captured data to I O pins to analyze with an external Logic Analyzer The following factors can affect the mode of operation you choose E The availability of device RAM and I O pins E The number of trigger levels being used in analysis m Whether the SignalTap II Logic Analyzer is used in conjunction with external test equipment When device RAM is limited the software can route internal signals to unused I O pins for capture by an external Logic Analyzer This method is useful for data intensive applications in which the amount of saved data exceeds the available sample buffer depth provided by the device RAM In this signal the Quartus II software automatically generates debugging port signals that connect internal FPGA signals to output pins You must assign these signals to I O pins To use the SignalTap II Logic Analyzer debugging port configuration follow these steps 1 Right click on a signal in the Debug Port Out column 2 Choose Enabl
8. Total IO Power 241 14 mw Total 10 Buffer Power 241 14 mw Total Power 476 64 mw You can run the procedures and make the settings described in this chapter in a Tcl script For detailed information about specific scripting command options and Tcl API packages type quartus sh qhelp at a system command prompt to run the Quartus II Command Line and Tcl API Help utility For more information and examples on Quartus II scripting support refer to the Tel Scripting and Command Line Scripting chapters in Volume 2 of the Quartus II Handbook Simulation Based Power Estimation Settings Use the following Tcl command to turn on the power estimation feature set global assignment name ESTIMATE POWER CONSUMPTION ON For more information on power estimation settings refer to Power Estimation in the Quartus II Software on page 7 2 Use the following Tcl commands to set the power estimation start and end times Specify the start and end times with quotes such as 100 ns for start time and end time set global assignment name POWER ESTIMATION START TIME lt start_time gt set_global assignment name POWER ESTIMATION END TIME lt end_time gt Altera Corporation June 2004 Quartus Il Handbook Volume 3 Generate a Power Input File Use the following Tcl command to cause the Quartus II software to generate a PWF for use with third party EDA simulation sof
9. Figure 6 1 Device and Icc Standby Sections in the Stratix Power Calculator g Lu Altera Stratix Device Power Calculator Spreadsheet Version 3 0 JN DTE pYA Aters does noi guarantee arimah the relabity senviceabity or function of fils Li Program ce othar itara provided as pari ofthis Program The fies comaned heren are prod ded WS I7 ALTERA DISCLAING ALL WARRANTES EXPRESS OR MPUED INCLUDING THE NPLIED WARRANTIES OF MERCHANTABLITY yoyr altera com AND FITNESS FOR A PARTICULAR PURPOSE Comeight Atera Corporation Al rights resared Power Up loc mA Tht prett ap LANA it oter ca bea ad ik Br ached to thee tod carnet bresar independent of he BAWA CORRE deg Gr tet ai ad For freer Moran bot prono murari in Eire bracet Oe tit pirati COMME DTA ire Mio en ASSE e em Nea td ed Figure 6 2 Clock Network Section in the Stratix Power Calculator Clock Network o o o 2800 i 5o 7 59 Altera Corporation June 2004 Estimating Power in the Design Cycle Figure 6 3 Logic Elements Section in the Stratix Power Calculator Logic Elements LEs 200 lt 86 06 129 08 esw 23 53 3530 1 100 o 8 12 50 20 ROM bi 4 63 9 00 4 63 6 94 S3 3_LYTTLILYCMOS_24 v Gaves Estimati ng You can estimate power at different stages of y
10. Table 2 3 Altera Gate Level Simulation Libraries Library Files apex20k atoms v Description Atom libraries for APEX 20K designs apex20ke atoms v Atom libraries for APEX 20KE APEX 20KC and Excalibur designs apexii atoms v Atom libraries for APEX II designs cyclone atoms v Atom libraries for Cyclone designs flex6000 atoms v Atom libraries for FLEX 6000 designs flex10ke atoms v Atom libraries for FLEX 10KE and ACEX 1K designs max atoms v Atom libraries for MAX 3000 and MAX 7000 designs mercury atoms v Atom libraries for Mercury designs stratix atoms v Atom libraries for Stratix designs stratixgx atoms v stratixgx hssi atoms v Atom libraries for Stratix GX designs stratixii atoms v Atom libraries for Stratix Il designs maxii atoms v Atom libraries for MAX II designs cycloneii atoms v Atom libraries for Cyclone Il designs hc_stratix atoms v Atom libraries for HardCopy Stratix designs Altera Corporation June 2004 2 7 Quartus Il Handbook Volume 3 Common VCS Compile Switches Transport Delays VCS filters out all pulses that are shorter than the propagation delay between elements Enabling the transport delay switches in VCS prevents the simulation tool from filtering out these pulses Use the following switches to ensure that all signal pulses are seen in the simulation results tran
11. 4 Click Program Device To capture and view data samples follow these steps 1 Select the Run button 2 Run the SignalTap II Logic Analyzer by clicking Run or AutoRun in the SignalTap II window Data capture begins when the trigger event evaluates to TRUE c For more information on triggering see the Triggering the Analyzer section The SignalTap II toolbar has four options for running the analyzer E Run SignalTap II Logic Analyzer runs until the trigger event occurs When the trigger event occurs data capture stops E Stop SignalTap II analysis stops The acquired data does not appear if the trigger event has not occurred M AutoRun SignalTap II Logic Analyzer continuously captures data until the Stop button is clicked M Read Data Captured data is displayed This button is useful if you want to view the acquired data even if the trigger has not occurred This section describes the following advanced features Preserving FPGA Memory Creating Complex Triggers Using External Triggers Embedding Multiple Analyzers in One FPGA Faster Compilations Time Bars and Next Transition Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Altera Corporation June 2004 Saving Captured Data Converting Captured Data to Other File Formats Creating Mnemonics for Bit Patterns Capturing Data to a Specific RAM Type
12. Analysis amp Synthesis Settings VHDL Input Verilog HDL Input Default Parameters Synthesis Netlist Optimizations Fitter Settings Physical Synthesis Optimizations Timing Analyzer Design Assistant SignalT ap Il Logic Analyzer SignalProbe Settings Simulator Software Build Settings Stratix GX Registration HardCopy Settings Cancel Note to Figure 12 2 1 The Quartus II software allows up to six EDA tools to be selected in the EDA tools list 4 Choose Analysis and Synthesis in the Category list of the Settings dialog box 5 Under Analysis and Synthesis select Synthesis Netlist Optimizations On the Synthesis Netlist Optimizations page ensure that Perform gate level register retiming is turned off Figure 12 3 Altera Corporation 12 3 June 2004 Quartus II Handbook Volume 3 Figure 12 3 Synthesis Netlist Optimizations Settings topEccGenerator134 x Category General Files User Libraries Device Timing Requirements amp Options EDA Tool Settings Design Entry amp Synthesis Simulation Timing Analysis Board Level Formal Verification Resynthesis Compilation Process E Analysis amp Synthesis Settings VHDL Input Verilog HDL Input Default Parameters Synthesis Netlist Optimize Fitter Settings Physical Synthesis Optimizations Timing Analyzer Design Assistant SignalT ap Il Logic Analyzer Sig
13. If you want to use the best case delay values for PrimeTime analysis you must perform a Minimum Timing Analysis in the Quartus II software This is a two step process as follows 1 Select Start gt Start Minimum Timing Analysis Processing menu Altera Corporation June 2004 Files Generated for the PrimeTime Environment Altera Corporation June 2004 2 Select Start gt Start EDA Netlist Writer Processing menu This will create a lt project_name gt _v_min sdo or lt project_name gt _vhd_min sdo file which contains the best case delay values for each timing arch I gt Itis up to you to point to either best case or worst case delay values during the PrimeTime processing by specifying the appropriate file name in the Tool Command Language Tcl script file described below M lt project_name gt _pt_v tcl or lt project_name gt _pt_vhd tcl files These files contain the search path to and the names of the PrimeTime database library files provided by Altera A file referred to in this Tcl file device_all_pt v or device_all_pt vhd contains the Verilog VHDL description of each library cell The search path and link path are defined at the beginning of the Tcl file The search path must be modified depending on where these libraries are stored The link path contains the names of all database files and it does not need to be modified Here is an example of the search path and link path defined in the Tcl file s
14. 1 Start Compilation Choose Start gt Start Compilation Processing menu 2 When compilation has completed successfully set the Tool name to VCS Choose Settings Assignments menu In the Category list select EDA Tool Settings expand if necessary gt Simulation In the Simulation section of the window choose VCS in the Tool name list as shown in Figure 2 2 3 Run the EDA Netlist Writer Choose Start gt Start EDA Netlist Writer Processing menu Altera Corporation June 2004 Using VCS in the Quartus Il Design Flow During the EDA Netlist Writer stage the Quartus II software produces a Verilog output vo netlist file and a Standard Delay Output sdo file used for a gate level timing simulation in the VCS software This netlist file is mapped to architecture specific primitives The SDO file contains timing delay information for each architecture primitive Together these files provide an accurate simulation of the design in the Altera FPGA architecture The resulting files will be located in the lt project folder gt simulation VCS directory These files along with the device family library listed in Table 2 3 can be used to perform a gate level timing simulation in VCS The following VCS command describes the command line syntax to perform a post synthesis simulation with the device family library ves R lt testbench v gt lt gate level timing netlist vo gt v lt altera device family library v gt
15. INCLUDE lt path to another cds lib gt or SOFTINCLUDE lt path to another cds lib gt ll For the Windows operating system enclose the path to an included cds lib file in quotation marks if there are spaces in any directory names Altera Corporation August 2004 Functional RTL Simulation Altera Corporation August 2004 For VHDL or mixed language simulation you must use an INCLUDE or SOFTINCLUDE statementin the cds lib file to include your default cds lib in addition to the DEFINE statements The syntax is INCLUDE lt path to NC installation gt tools inca files cds lib or INCLUDE CDS_INST_DIR tools inca files cds lib The default cds lib file provided with NC tools contains a SOFTINCLUDE statement to include another cds lib files such as cdsvhdl lib and cdsvlog lib These files contain library definitions for IEEE libraries Synopsys libraries etc Create cds lib Command Line Mode To edit cds lib from the command line perform the following steps 1 Create a directory for the work library and any other libraries you need using the command mkdir lt physical directory gt For example mkdir worklib 2 Usingatexteditor create a cds lib file and add the following line to it DEFINE lt library name gt lt physical directory path gt For example DEFINE worklib worklib Create cds lib GUI Mode To create cds lib using the GUI perform the following steps 1
16. Ss QUARTUS II Quartus Il Handbook Volume 3 Verification A DTE RA 101 Innovation Drive San Jose CA 95134 408 544 7000 http www altera com gii5v3_2 1 Copyright 2004 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device des ignations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Al tera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service described herein except as expressly agreed to in writing by Altera NSAI Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published in formation and before placing orders for products or services DI Printed on recycled paper LS EN ISO 9001 Altera Corporation N D TE RYN Contents Chapter Revi
17. 10 Clock 1 Period 6ns Clock 2 Period 12 ns Offset 2ns Multicycle 2 Multicycle Hold 2 4 26 The Multicycle Hold Value of 2 relaxes the hold time requirement by moving the reference edge one destination clock cycle earlier for the hold time calculation The first check illustrated with the dashed line requires a minimum data delay of 4 ns 2 ns 6 ns The second check illustrated with the dotted line requires a minimum data delay of 10 ns 0 10 ns Data must have a maximum delay of 14 ns and a minimum delay of 4 ns to meet the Multicycle and Multicycle Hold requirements Figure 4 26 is a timing diagram representing data going from a slow clock domain to a fast clock domain with an offset between the clock edges The Multicycle assignment of 4 relaxes the setup requirement by extending it to the fourth destination clock edge but the hold requirement is unchanged Altera Corporation June 2004 Quartus Il Timing Analysis Figure 4 26 Multicycle Hold Checks gt Setup gt Hold Check 1 v cues B Hold Check 2 eaen Lc CLKI at LTT CLK2 Clock 1 Period 12 ns Clock 2 Period 6 ns Offset 2ns Multicycle 4 Figure 4 27 illustrates hold time checks for a Multicycle Hold assignment of 1 Figure 4 27 Multicycle Hold of 1 gt Setup gt Hold Check 1 M D Hold Check 2
18. 10C_X52 Y 10C_X52 Y 10C_X52 Y IOC_X52_ 21 Itestlout2 Current Strength 24m 16m 16m 16m 3 Itestlin2 Location Index IOC_x52_v IDC_x52_Y IDC_x52_v IOC_x52_ 4 Itestlint Location Index IOC_X52_Y 10C_x52_Y IDC Be IOC X82 Target Value Current Value Disk Value Table 10 6 describes the values that appear in the Status column of the Change Manager Table 10 6 Status Values in the Change Manager Value Description Applied A change has been made and saved but Check amp Save All Netlist Changes has not been performed Committed A change has been made saved and Check amp Save All Netlist Changes has been performed Not Valid A change has been made and saved A new change to the same element that supersedes the original change results in the status being set to Not Valid Not Applied A change has been made and saved However if the original value has been restored the newly created entry appears as Not Applied Co mmon The Chip Editor can be used in a number of ways to help build your system as quickly as possible The list below shows some of the ways you Applications can use the Chip Editor Gate level register retiming Routing an internal signal to an output pin Adjust the phase shift of a PLL to meet I O timing Correct a functional flaw in a design Gate Level Register Retiming Retiming your design
19. Meaning Part 1 of 2 Command names dialog box titles checkbox options and dialog box options are shown in bold initial capital letters Example Save As dialog box bold type External timing parameters directory names project names disk drive names filenames filename extensions and software utility names are shown in bold type Examples fmax qdesigns directory d drive chiptrip gdf file Italic Type with Initial Capital Letters 75 High Speed Board Design Document titles are shown in italic type with initial capital letters Example AN Altera Corporation xiii Typographic Conventions Quartus Il Handbook Volume 3 Visual Cue Italic type Meaning Part 2 of 2 Internal timing parameters and variables are shown in italic type Examples tpa n 1 Variable names are enclosed in angle brackets lt gt and shown in italic type Example lt file name gt lt project name gt pof file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix n e g resetn Anything that m
20. Revised root module is set to mi2c Parsing file apps2 home users schandra design_examples ip_designs mi2c mi2c_syn vam s Warning RTL1 5 Assignment with RHS bit width greater than LHS bit width occurrence 744 Warning RTL12 Variable signal referenced not on sensitivity list occurrence 4 Warning HRC3 1 Module instance has different number of arguments occurrence 527 Warning There are 328 undriven nets in Golden design Warning There are 1085 undriven pins in Golden design SETUP gt read design apps2 home users schandra design_examples ip_designs mi2c mi2c vqm Verilog Revis Command read design apps2 home users schandra design_examples ip_designs mi2c mi2c vqm Verilog Parsing file apps2 home users schandra design_examples ip_designs mi2c mi2c vom Warning RTL1 5 Assignment with RHS bit width greater than LHS bit width occurrence 1156 gt Warning RTL12 Variable signal referenced not on sensitivity list occurrence 14 Warning IGN2 2 Illegal defparam ignored occurrence 129 Warning HRC3 1 Module instance has different number of arguments occurrence 528 gt Warning There are 505 undriven nets in Revised design Warning There are 1111 undriven pins in Revised design fapps2 home users schandra fv_lib lpms v SS fapps2 home users schandra fv_lib lpms_bbox v AA fapps2 home users schandra fv_lib mfs_bbox v SS fapps2 home users schandra
21. Right click on the DATAIN port of out and select Remove Connection Connect RI EGOUT to DATAIN of the output pin out 10 31 Quartus Il Handbook Volume 3 To perform this step you must run the Check amp Save All Netlist Changes command in the Change Manager to ensure that the newly created REGOUT from step 6 for xx 0 190 appears in the Node Finder a Right click in the Change Manager and select Check amp Save All Netlist Changes b Open the Resource Property Editor for out c Right click on the DATAIN port of out and select Edit Connections In the Edit Connections dialog box find the REGOUT port for xx 0 190 use the Node Finder See Figure 10 22 Figure 10 22 Select Edit Connections Do at HaT DE D a 7 pe J OEE ee CRE aT Fr ii L gt GERESET D gt en BRESET PAR pe mb i bo QE x n A Signal name Al a LA fetiming_smallix 0 180_REGOUT El 0K Cancel ae R al n oa gt a ES K gt Ea ar 8 Check and save netlist Right click in the Change Manager and sel
22. The Quartus II software version 4 1 supports register duplication to improve timing results The formal verification tool also supports register duplication and can be used during the formal verification flow Figure 12 4 Figure 12 4 Setting Parameters for Netlist Optimizations Settings topEccGenerator134 a x Category General Files User Libraries Device Timing Requirements amp Options EDA Tool Settings Compilation Process Analysis amp Synthesis Settings VHDL Input Verilog HDL Input Default Parameters Synthesis Netlist Optimizations Fitter Settings Physical Synthesis Optimizations Timing Analyzer Design Assistant SignalT ap Il Logic Analyzer SignalProbe Settings Simulator Software Build Settings HardCopy Settings Physical Synthesis Optimizations Specify options for performing physical synthesis optimizations during fitting Note The availability of these options depends on the current device family IV Perform physical synthesis for combinational logic Physical synthesis for registers I Perform register duplication TT Perform register retiming r Physical synthesis effort Normal default effort level average of 2 to 3 times compile time Extra more compile time than Normal should improve performance gains Fast less compile time than Normal may reduce performance gains a To
23. These changes enable run time configuration without changing the functionality of your design For a list of run time configurable megafunctions refer to Table 11 1 To enable your memory or constant to be configurable perform the following steps 1 Choose MegaWizard Plug In Manager Tools menu 2 Ifyou are creating a new Megafunction select Create a new custom megafunction variation If you have an existing megafunction select Edit an existing custom megafunction variation 3 In addition to the characteristics required by your design turn on Allow In System Memory Content Editor to capture and update content independently of the system clock and type a value for Instance ID These parameters can be changed on the last page of the wizards for megafunctions that support in system updating 4 Click Finish 5 Choose Start Compilation Processing menu If you instantiate a memory or constant megafunction directly using ports and parameters in VHDL or Verilog HDL add or modify the 1pm hint parameter as shown below In VHDL code add the following lpm hint gt ENABLE RUNTIME MOD YES INSTANCE NAME lt instantiation name gt 11 3 Running the In System Memory Content Editor Running the In System Memory Content Editor In Verilog HDL code add the following lt megafunction gt component lpm hint ENABLE RUNTIME MOD YES INSTANCE NAME lt instantiati
24. Using a PLL in your design should help I O timing However if your 1 0 timing requirements are still unmet you can adjust the PLL phase shift to try to meet the I O timing requirements of your design Shifting the clock backwards will give a better tco at the expense of the tsy while shifting it forward will give a better tsy at the expense of tco and ty Use the equations shown in the PLL section to set the new phase shift value to optimize your I O Timing Correcting a Design Flaw You may find functional flaws while you are debugging your design Traditionally these flaws bugs are corrected by modifying the RTL code and going through the entire design flow again This process can be very time consuming because the process of synthesis and place and route may take a significant amount of time However with the Chip Editor you can make a change to your design without having to repeat the synthesis and place and route process To make a change with the Chip Editor you can modify the LUT equation or the LUT mask of an LE with the Resource Property Editor Meeting the timing requirements of a design can be a difficult task There are anumber of proven methods that you can use to correct timing issues however the most efficient method will vary depending on a number of factors The following example demonstrates how using the Chip Editor can help you to meet the timing requirements in a design To download the design files go to
25. amp Synthesis Debug Settings Summary em SignalTap II Logic Analyzer Settings em In System Memory Content Editor Setting E Hierarchy gm Analysis amp Synthesis Resource Utilization by Entity xb Analysis amp Synthesis Equations EE Analysis amp Synthesis Source Files Read SE Analysis amp Synthesis Resource Usage Summary SE Analysis amp Synthesis RAM Summary i Analysis amp Synthesis Messages 0 Fitter 0 Assembler H A Timing Analyzer 11 6 Making Changes To read the contents of in system memory click Read Data from In System Memory or Continuously Read Data from In System Memory in the Instance Manager You can also run these commands by right clicking in the Instance Manager or Hex Editor and choosing from the right button pop up menu To edit data before writing it back to the device place the insertion point at the desired location in the Hex Editor and begin typing Editing always overwrites data in the hex editor Modified data appears in blue until it is written when it appears red To prepare data type or paste changes into the Hex Editor or import a memory file The In System Memory Content Editor supports importing of hexadecimal hex and memory initialization file mif formats Altera Corporation August 2004 In System Updating of Memory amp Constants To import a file right click the target instance in the Instance Manager or a specific location in the Hex Editor and c
26. and tsy in the Quartus II software is the data delay from the input pin to clock edge tsy is subtracted from the clock period to calculate the set input delay Table 5 1 shows the automatically generated PrimeTime contraints and their Quartus II software equivalents Table 5 1 Equivalent Quartus Il amp PrimeTime Constraints PrimeTime Constraint Quartus Il Equivalent create_clock period 10 000 waveform Clock defined on input pin clock of 0 5 000 get_ports clk name clk 10 ns period 50 duty cycle set_input_delay max add_delay tsy of 1 ns on input pin din 9 000 clock get_clocks clk get_ports din set_input_delay min add_delay 1 000 t of 1 ns on input pin din clock get_clocks clk get_ports din set_output_delay max add_delay tco of 3 ns on output pin out 7 000 clock get_clocks clk get_ports out This section describes the timing reports that the PrimeTime tool generates and the Tcl script commands that control each report s contents E report timing nworst 100 gt file timing This command which can be inserted at the end of the Tcl file to report timing paths in PrimeTime will generate a list of the 100 worst paths and place this data into a file called file timing Timing paths in PrimeTime are listed in the order of most negative slack to most positive slack Failing paths are not reported under each constraint s category as they are in the
27. domains when there are no timing requirements set or only the default required fmax is specified This option cuts paths between unrelated clock domains if individual clock assignments are set but there is no defined relationship between the clock assignments See Figure 4 31 Figure 4 31 Cut Paths Between Unrelated Clock Domains inst10 DEF LCELL PRN D af inst5 CLAN i om HOSE CR iinstt I DFF i DFF g DSS i AND2 LGELL PRN LGELL PRN D Q D Q inst11 inst6 n i 4 30 CLRN finte Ti SC Pri For the circuit shown in Figure 4 31 the path between inst1 and inst4 is not measured or reported by the Timing Analyzer If you turn off Cut timing paths between unrelated clock domains the Timing Analyzer includes these paths as part of timing analysis Cut Timing Path You can make Cut Timing Path assignments to paths that are not used under normal operation such as paths through test logic Figure 4 32 shows an example of a false path Altera Corporation June 2004 Quartus Il Timing Analysis Figure 4 32 False Path Signal Clock CLRN f Test Enable In Figure 4 32 the path from inst1 through the multiplexer to inst2 is used only for design testing This false path is not used under normal operation and should not
28. you should back annotate the design to constrain it to a portion of the FPGA This is done by selecting Back Annotate Assignments Assignments menu After you have back annotated your design it is safe to insert SignalTap II Logic Analyzer to your project Compile the design and you will see the results shown in Table 9 6 Table 9 6 Fyax Results from the Quartus Il Timing Analysis with SignalTap Il Logic Analyzer After Back Annotation Actual F Slack MAX From To Clock ns MHz Source 0 053 125 83 state m instl filter 22 acc inst3 result 11 clk 0 196 128 14 taps inst xn 0 reg0 acc inst3 result 11 clk 0 171 127 89 state m instl filter 22 acc inst3 result 6 clk 0 171 127 89 state m instl filter 22 acc inst3 result 7 clk By back annotating your original design the register to register delay decreased significantly and the original timing requirements have been met 9 34 Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Design Example Using SignalTap Il Logic Analyzers in SOPC Builder Systems Conclusion Altera Corporation June 2004 Figure 9 26 shows the timing closure floorplan editor Figure 9 26 Timing Closure Floorplan Editor Application Note 323 Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems describes how to use the SignalTap II Logi
29. 15 NativeLink Using with ModelSim 1 19 NC Simulation Flow 3 4 NC Sim Generated Simulation Output Files 3 29 Netlist Generating for Other EDA Tools 10 33 Nodes Select Nodes Reserved for Incremental Routing 9 21 Set Number Allocated 9 20 nopli v Compiling 1 11 2 4 0 Output Files Quartus II Simulation 3 18 P Phase Shift Adjusting 10 22 of PLL Adjusting to Meet I O Timing 10 27 Pin to Pin Delay 4 3 Pipelining Adding Registers 8 4 8 11 PLI Routines Incorporating 3 23 VCS Software 2 10 PLL Mode External Feedback 10 23 Normal 10 22 Post Synthesis Simulation 2 4 Generating Netlist 2 5 Power Calculator Excel Based 6 1 Estimation Index 3 Quartus Il Handbook Volume 3 Quartus II Software 7 2 Simulation Based Settings 7 7 Input File Generate 7 8 Report File 6 6 Preserving Timing 9 32 PrimeTime Environment Generated Files 5 2 Format Specified Constraint Samples 5 4 Quartus II Settings to Generate Files 5 1 Running 5 6 Sample Timing Report 5 5 Timing Reports 5 4 Programming File 10 33 Properties Cyclone 10 20 Max II 10 21 PLL 10 21 Stratix and Stratix GX 10 19 Stratix II 10 19 Q Quartus II Megafunction Simulation Models 1 4 R Register Retiming Gate Level 10 24 Remote PC Software Setup 9 26 Resource Property Editor 10 9 Routing Internal Signal to Output Pin 10 26 S Sample Depth Specifying 9 6 Scripting Support 2 10 3 29 7 7 8 9 SDF Command File 3 22 Signal Preservation
30. Analyzer M Automatically add pins to simulation output waveforms Design Assistant T Check outputs SignalT ap Il Logic Analyzer I Setup and hold time violation detection SignalProbe Settings es n Simulator T Glitch detection fi 0 ns La E Software Build Settings M Simulation coverage reporting Stratix GX Registration D Overwrite simulation input file with simulation results HardCopy Settings uPCore Transaction Model File Name JE Power Estimation Ok Cancel PA 11 12 In the Quartus II software perform a timing simulation of your design View the estimated power consumption in the Simulator Summary section of the Simulation Report see Figure 7 6 Altera Corporation June 2004 Scripting Support Scripting Support Figure 7 6 Simulator Summary E Simulation Report Simulator Summary SE Legal Notice SEB Flow Summary Simulation Start Time 0 ps SE Flow Settings Simulation End Time 10 0 us E SII Simulator Simulation Netlist Size 20212 nodes SE Simulator Summary 4 Simulation Coverage 0 25 EE Simulator Settings Sb Simulation Waveforms Total Number of Transitions 42416 EQ Logical Memories Power estimation start time Ops SE Simulator INI Usage Power estimation end time i 0 0 us i Simulator Messages Total Internal Power 235 49 mw Total Standby Internal Power 105 00 mw Total M4K RAM Internal Power 4 26 mw Total Clocktree Internal Power 126 23 mw
31. Cadence NC simulators you use your design files Verilog HDL or VHDL and the models provided with the Quartus II software These Quartus II models are required if your design uses library of parameterized modules LPM functions or Altera specific megafunctions See Functional RTL Simulation on page 3 5 for more information on how to perform this simulation 3 2 Altera Corporation August 2004 Simulation Flow Overview Altera Corporation August 2004 Gate Level Timing Simulation After performing place and route in the Quartus II software the software generates a Verilog Output File vo or VADL Output File vho and a Standard Delay Format SDF Output File sdo for gate level timing simulation The netlist files map your design to architecture specific primitives The SDO contains the delay information of each architecture primitive and routing element specific to your design Together these files provide an accurate simulation of your design with the selected Altera FPGA architecture See Gate Level Timing Simulation on page 3 18 for more information on how to perform this simulation Operation Modes You can use either the command line mode or graphical user interface GUI mode to simulate your design with NC simulators To simulate in command line mode use the files shown in Table 3 2 You can launch the NC GUI in UNIX or PC environments by typing nclaunch at a command prompt TS This chapter describes
32. Corporation June 2004 Chip Editor Overview Each resource is shown in a different color making it easier to distinguish between resources The Chip Editor uses a gradient color scheme the color becomes darker as the utilization of a resources increases For example as more LEs are used in the LAB the color of the LAB becomes darker When you place the mouse pointer over a resource at this level a tooltip appears that describes at a high level the utilization of the resource see Figure 10 4 Figure 10 4 Tooltip Message First Level View LI Block utilization 5 of 10 Second Level View As you continue to zoom in you see an increase in the level of detail Figure 10 5 shows the Chip Editor s second level view Figure 10 5 Chip Editor s Second Level View Altera Corporation 10 7 June 2004 Quartus Il Handbook Volume 3 10 8 At this level you can see the contents of LABs and I O banks You also see the routing channels that are used to connect resources together When you place the mouse pointer over an LE at this level a tooltip is displayed that describes the name of the LE the location of the LE and the number of resources that are used with that LAB When you place the mouse pointer over an interconnect the tooltip shows the routing channels that are used by that interconnect Figure 10 6 shows the level 2 tooltip information Figure 10 6 Tooltip Message Second Lev
33. Design Meeting I O Timing the register to pin delay thereby reducing the tco It should be noted that by moving the register the fmax of the overall circuit may decrease Also to use the manual gate level retiming process you must ensure that moving the register does not alter the functionality of the circuit In general this method should only be used when you understand the design completely If you are unsure about altering functionality it is best to use the Perform gate level register retiming option in the Quartus II software To reduce the register to pin delay you need to move the register to the other side of the combinational logic Perform this operation manually by following the steps shown below 1 Locate the failing path in Chip Editor Floorplan see Figure 10 19 Right click in the tco section of the Timing Analysis Report use the entry where the source register is outff_a 9 and select Locate in Chip Editor right button pop up menu Figure 10 19 Failing Path in Chip Editor 2 Open the Resource Property Editor and locate the source register Altera Corporation 10 29 June 2004 Quartus Il Handbook Volume 3 Right click on the source register outff_a 9 and select Locate in Resource Property Editor right button pop up menu Create the COMBOUT port for outff_a 9 Right click the COMBOUT port and select Create COMBOUT right button pop up menu See Figure 10 20 Figure 10 20 Sel
34. HDL netlist file reads the SDF file using the system task call sdf_annotate When NC Verilog elaborates the netlist ncelab recognizes the system task and automatically calls nsdfc However the sdf_annotate system task call does not specify the path Therefore you must copy the SDO file from the Quartus II created simulation directory to the NC working directory in which you run the ncelab program After you update the path you can elaborate the design See Elaborate Your Design on page 3 13 for step by step instructions on elaboration For VHDL the Quartus Il generated VHDL netlist file has no system task calls to locate your SDF file Therefore you must compile the SDO file manually See Compiling the Standard Delay Output File VHDL Only Command Line and Compiling the Standard Delay Output File VHDL Only GUI on page 3 22 for information on compiling the SDO file 3 21 Quartus Il Handbook Volume 3 Compiling the Standard Delay Output File VHDL Only Command Line To annotate the SDO timing data from the command line perform the following steps 1 Compile the SDO file using the nesdfc program by typing the following command at the command prompt ncsdfc lt project name gt vhd sdo output lt output name gt The nesdfc program generates a lt output name gt sdf X compiled SDF Output File IL Ifyou do not specify an output name nesdfc uses lt project name gt sdo X Specify the compiled
35. Logic Analyzer Altera Corporation June 2004 Figure 9 13 Nodes Allocated Data Sample depth Nodes allocated 128 xl Auto Manual 20 RAM type MAK v Select Nodes Reserved for Incremental Routing As shown in Figure 9 14 the SignalTap II Setup window shows pre synthesis nodes and post fitting nodes and an Incremental Route column Post fitting nodes are displayed in blue with the Incremental Route option enabled and dimmed so it cannot be edited By turning on Incremental Routing for pre synthesis nodes you preserve the signal to the post fitting stage of the compilation You can later delete the incrementally routed pre synthesis node and replace it with a post fitting node You cannot replace this node with a SignalTap II pre synthesis node Figure 9 14 The SignalTap Il Setup Window Note 1 Debug Port Data Enable Trigger Enable Trigger Levels Out 68 Auto 68 Auto 11 Advanced _ Incremental Route AA lt lt lt lt lt lt lt lt 4 lt lt Note to Figure 9 14 1 Post fitting nodes are displayed in blue and Incremental Route is always turned on The next time you add a SignalTap II post fitting node to the STP file and start a compilation the Quartus II software incrementally routes only the new nodes When the Quartus II software performs incremental routing the existing placement and routing of your design is not modified If
36. Quartus II software Timing setup tsy and timing hold ty times are not listed separately In PrimeTime there is a start and end point given with each path to identify for example if it is a register to register or input to register type of path If you only use the report timing part of the command without adding a delay option only the setup time related timing paths are reported Altera Corporation June 2004 PrimeTime Timing Reports Altera Corporation June 2004 E report timing delay min This command can be used to create a minimum timing report or a list of hold time related violations It is up to you to define what type of SDO file is being used Both minimum delay and maximum delay SDO files can be generated from the Quartus II software Sample PrimeTime Timing Report This section presents a sample timing report Table 5 2 Sample PrimeTime Timing Report Startpoint I out reg rising edge triggered flip flop clocked by clk Endpoint out output port clocked by clk Path Group clk Path Type max Point Incr Path clock clk rise edge 0 00 0 00 clock network delay propagated 2 362 2 362 out I out reg clk 0 00 2 362 r stratix io register out I out reg regout 0 162 2 524 r stratix io register out I out mux3 MO mux21 0 000 2 524 r out I and2 22 Y AND2 0 000 2 524 r out I out mux1 MO mux21 0 000 2524 E out I instl padio 2 7
37. Quartus II software for place and route Quartus Il Handbook Volume 3 Gate Level Timing Simulation Place and route in the Quartus II software produces a design netlist vo or vho file and a Standard Delay Format SDF output sdo file used for a gate level timing simulation in the ModelSim Altera software The design netlist output file is a netlist of the design mapped to architecture specific primitives such as logic elements and I O elements The SDF file contains delay information for each architecture primitive and routing element specific to the design Together these files provide an accurate simulation of the design for the selected Altera FPGA architecture Fu neti on al RTL A functional RTL simulation is performed before a gate level simulation i and verifies the functionality of the design before place and route This Si mu lati on section provides detailed instructions on how to perform a functional RTL simulation in the ModelSim Altera software and highlights some of the differences in performing similar steps in the Model Technology ModelSim software versions for VHDL and Verilog HDL designs Functional RTL Simulation Libraries LPM and Altera Megafunction Functional RTL Simulation Models To simulate designs containing LPM functions or MegaWizard Plug In Manager generated functions use the following Altera functional simulation models Mm 220model v for Verilog HDL E 220pack vhd and 220model vhd for V
38. Register Mode OE Register Reset Mode OE Register Synchronous Reset Mode OE Powers Up Input Clock Enable Delay Output Clock Enable Delay Output Enable Clock Enable Delay Input Pin to Logic Array Delay Output Pin Delay Input Pin to Input Register Delay Output Enable Register tco Delay Output tzx Delay Logic Array to Output Register Delay Stratix Il Properties You can use the Resource Property Editor to view the following properties of Stratix II device I O cells Bus Hold Weak Pull Up Slow Slew Rate Open Drain 10 19 Quartus Il Handbook Volume 3 I O Standard Current Strength Extend OE Disable PCI I O On Chip Termination Input Register Mode Input Register Reset Mode Input Register Synchronous Reset Mode Input Powers Up Output Register Mode Output Register Reset Mode Output Register Synchronous Reset Mode Output Powers Up OE Register Mode OE Register Reset Mode OE Register Synchronous Reset Mode OE Powers Up Output Enable Clock Enable Delay Input Pin to Logic Array Delay Output Pin Delay Input Pin to Input Register Delay Output Enable Register tco Delay Cyclone Properties You can use the Resource Property Editor to modify the following properties of Cyclone device I O cells Bus Hold Weak Pull Up Slow Slew Rate Open Drain I O Standard Current Strength Extend OE Disable PCI I O On Chip Termination Input Register Mode Input Register Reset Mode Input Register Synchronous
39. The shortest register to memory delay is 3 503 ns and the micro hold delay of the destination register is 0 106 ns As a result the clock skew is longer than the data path and the circuit does not operate normally Altera Corporation June 2004 Quartus Il Timing Analysis Figure 4 13 Clock Skew 2 302 ns 3 503 ns 9 bits X 4096 words i wren rdaddress 11 0 CLRN fins Pi i DFFQ O PRN D 9 251 ns Clock 2 i CLAN tinst6 Pi Inst4 clock in incorrect data data value Name Value at 15 0 ns gt clock_a BO lt gt clock_b BO gt A BO gt B B1 1 847 4 258 7 141 Altera Corporation June 2004 Multiple Clock Domains Multiclock circuits are designs that have more than one clock After you specify clock settings the Quartus II software analyzes timing for register to register paths controlled by different clocks and reports the slack results The Timing Analyzer disregards any paths between unrelated clock domains by default See Cut Paths Between Unrelated Clock Domains on page 4 30 for more information To correctly perform multiclock timing analysis you must define the absolute clock specify a desired fmax or clock period and define other clocks and their relationships if any to the absolute clock Then assign these settings to the cloc
40. Type nclaunch at the command line to launch the GUI 2 Ifthe NCLaunch window is not in multiple step mode switch to multistep mode by selecting Switch to Multiple Step File menu 3 Change your design directory by selecting Set Design Directory File menu 3 7 Quartus Il Handbook Volume 3 3 8 The Set Design Directory window opens as shown in Figure 3 2 4 Click on the Browse button to navigate to your project directory 5 Click Create cds lib File and choose the appropriate libraries to be included in the New cds lib File dialog box 6 Click New under Work Library 7 Enter your new work library name e g worklib 8 Click OK The new library is displayed under Work Library Figure 3 2 shows an example using the directory name worklib Figure 3 2 Creating a Work Directory in GUI Mode Set Design Directory Design Directory apps2 home users alchang NCSIM Ip se r Library Mapping File appsz nome users alchang NCSIMAp Create cds lib File Work Library worklib New 9 Click OK a gt Youcan edit cds lib by right clicking the cds lib filename in the right pane and choosing Edit from the pop up menu LPM Function amp Altera Megafunction Libraries Altera provides behavioral descriptions for LPM functions and Altera specific megafunctions You can implement the megafunctions in a design using the Quartus II MegaWizard Plug In Manager or
41. Updating of Memory amp Constants Revised August 2004 Part number qii53012 1 0 Chapter 12 Cadence Incisive Conformal Support Revised June 2004 Partnumber gii53011 2 0 xii Altera Corporation Preliminary About this Handbook How to Contact Altera This handbook provides comprehensive information about the Altera Quartus II design software version 4 0 For the most up to date information about Altera products go to the Altera world wide web site at www altera com For technical support on this product go to www altera com mysupport For additional information about Altera products consult the sources shown below Information Type Technical support Product literature USA amp Canada www altera com mysupport 800 800 EPLD 3753 7 00 a m to 5 00 p m Pacific Time www altera com All Other Locations altera com mysupport 408 544 7000 7 7 00 a m to 5 00 p m Pacific Time www altera com Altera literature services lit_req altera com 1 lit_req altera com 1 Non technical customer service 800 767 3753 408 544 7000 7 30 a m to 5 30 p m Pacific Time FTP site Note to table ftp altera com ftp altera com 1 You can also contact your local Altera sales office or sales representative Typographic Conventions Visual Cue Bold Type with Initial Capital Letters This document uses the typographic conventions shown below
42. a bitwise AND operation has been performed with bus outc and bus outa and all bits of the result of that operation are 0 see Figure 9 9 Figure 9 9 Bitwise AND Operation Result outa gt outb ELD enable amp outc amp outd E outa al outb 4 S n logical0 re data n datal result result enable de a ES Result EDGE amp LEVEL e DETECTOR LOGICAL OR E bitwise E reduction 0 afn E ote Gaji tal result SN ETTR So hag REDUCTION BITWISE AND AND The advanced triggering capability can only be used with pre synthesis nodes Post fitting nodes can only be used for basic trigger operations However you can create an advanced trigger that uses the results of the 9 16 Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Altera Corporation June 2004 basic trigger created with post fitting nodes as an element of an advanced trigger condition When your STP file contains post fitting nodes the symbol as shown in Figure 9 10 appears in the advanced trigger panel Figure 9 10 Symbol for STP File Containing Post Fitting Nodes CONDITION FOR INCREMENTALLY ROUTED NODES The output of this symbol can be combined with the operators listed in Table 9 2 Using External Triggers You can create a trigger input that allows you to trigger the SignalTap II Logic Analyzer from an externa
43. a specific Quartus II software version Table 3 1 Compatibility between Software Versions Cadence NC Simulators UNIX Version 5 0 s005 Version 5 1 s012 Simulation Flow Overview Altera Corporation August 2004 Cadence NC Simulators Version 5 0 s006 Version 5 0 p001 Version 4 0 Version 5 1 s010 Version 5 0 p001 Version 4 1 Cadence NC Simulators Quartus il Software PC Linux See the Quartus II Installation amp Licensing for PCs or Quartus II Installation amp Licensing for UNIX and Linux Workstations manuals for more information on installing the software and the directories that are created during the Quartus II installation The Cadence NC software supports the following simulation flows E Functional RTL simulation M Gate level timing simulation Figure 3 1 shows the Quartus IT Cadence design flow 3 1 Quartus Il Handbook Volume 3 Figure 3 1 Altera Design Flow with Cadence NC Simulators KE Altera IP Design Entry ce Testbench Functional Simulation te Se Synthesis Place and Route ry Verilog Output Standard Delay File vo or VHDL Format Output Output File vho File sdo Gate Level Simulation Gate Level Models Functional RTL Simulation Functional RTL simulation verifies the functionality of your design When you perform a functional simulation with
44. acc inst3 result 8 clk 2 Compilation with SignalTap II Logic Analyzer You are debugging this design with SignalTap II Logic Analyzer so you must compile it with an STP file To enable SignalTap II Logic Analyzer the STP file included in the project archive stp1 stp must be correctly set in the Quartus II software Do this by enabling the STP file in the SignalTap II Logic Analyzer page of the Settings dialog box Assignments menu as shown in Figure 9 24 9 32 Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Figure 9 24 Enabling the STP File in the SignalTap Il Logic Analyzer Page x Category General SignalT ap Il Logic Analyzer Files User Libraries Specify compilation options for the SignalT ap Il Logic Analyzer Note the availability of these options Device depends on the current device family Timing Requirements amp Options I EDA Tool Settings FW Enable SignalT ap Il Logic Analyzer Design Entry amp Synthesis smi Signalfapil Fenne fa Timing Analysis o Automatically tum on smart compilation if conditions exist in which SignalT ap Il with Board Level incremental routing is used The Compiler uses more disk space to save extra data to Formal Verification facilitate incremental routing Resynthesis Compilation Process E Analysis amp Synthesis Settings VHDL Input Verilog HDL Input Default Parameters Synthesis Net
45. ap Il Logic Analyzer C End simulation at n z SignalProbe Settings Simulator Simulation options Software Build Settings F Automatically add pins to simulation output waveforms Stratix GX Registration HardCopy Settings EASES EES TT Setup and hold time violation detection I Glitch detection ni E IV Simulation coverage reporting I Overwrite simulation input file with simulation results uPCore Transaction Model File Name A DK Cancel ZA 3 Inthe Simulator Settings window select Timing in the Simulation mode list Altera Corporation June 2004 Power Estimation in the Quartus Il Software 4 Click Power Estimation to open the Power Estimation window 5 Inthe Power Estimation dialog box turn on the Estimate power consumption see Figure 7 2 The Simulator calculates and reports the internal power I O power and total power in mW consumed by the design during the simulation period 6 Power estimation can be performed for the entire simulation time or for a portion of the entire simulation time This allows you to look at the power consumption at different points in your overall simulation without having to rework your test benches You can specify the start time and end time in the Power Estimation dialog box under Power estimation period If no power estimation end time is specified power estimation ends at the simulation end time Figure 7 2 Power Estimation Window Power Est
46. be considered during timing analysis You can remove a false path from timing analysis with a Cut Timing Path assignment from register inst1 to register inst2 Fixing Hold Time Violations Hold time violations usually occur when clock skew is greater than data delay between two registers Clock skew between registers can occur if you use gated clocks in your design It can also occur if some clocks are inferred from flip flops or other logic You can use any of the following guidelines to address reported hold time violations Make Multicycle Hold Assignments Depending on your design functionality you can relax the hold relationship with Multicycle Hold or Source Multicycle Hold assignments Reduce Clock Skew Using global buffers for clock distribution minimizes clock skew but these buffers do not necessarily provide the shortest delay path You can route gated clocks using non global buffers to access faster clock trees because the skew is already caused by the clock gating logic You can also use a PLL to divide a clock signal instead of using other logic which may cause clock skew Because gated clocks are common causes of clock skew Altera recommends using clock enables instead of gated clocks in your design although this may not always be possible Altera Corporation 4 31 June 2004 Quartus Il Handbook Volume 3 Increase Data Delay You can increase data delay until it is greater than clock skew to resolve hold time
47. by instantiating them directly from your design file If your design uses LPM functions or Altera megafunctions you must set up resource libraries so that you can simulate your design in NC tools Altera Corporation August 2004 Functional RTL Simulation cS Many LPM functions and Altera megafunctions use memory files You must convert the memory files for use with NC tools before simulating To convert these files into a format the NC tools can read follow the instruction in section Simulating a Design with Memory on page 3 10 Altera provides megafunction behavioral descriptions in the files shown in Table 3 1 These library files are located in the lt Quartus II installation gt eda sim lib directory For more information on LPM functions and Altera megafunctions see the Quartus II Help Table 3 3 Megafunction Behavioral Description Files Megafunction Verilog HDL VHDL LPM 220model v 220model vhd 7 220model_87 vhd 2 220pack vhd Altera altera_mf v altera_mf vhd 7 Megafunction altera_mf_87 vhd 2 altera_components vhd ALTGXB 3 stratixgx_mf v 4 stratixgx_mf vhd 4 stratixgx_mf_components vhd 4 IP Functional sgate v sgate vhd Simulation Model sgate_pack vhd Notes to Table 3 3 1 Use this model with VHDL 93 2 Use this model with VHDL 87 3 As an alternative you can map to the precompiled library lt Quartus II installation gt eda sim lib modelsim lt verilo
48. drives adder0 of the next ALM in the LAB ALMs in arithmetic mode can drive out registered and or unregistered versions of the adder outputs c For more information on Shared Arithmetics Mode refer to the Stratix II Device Handbook FPGA 1 0 Stratix Stratix GX and Stratix Il 1 0 Elements E ements The I O element in Stratix devices contains a bidirectional I O buffer six registers and a latch for a complete bidirectional single data rate or DDR transfer Figure 10 10 shows the Stratix I O element structure The I O element contains two input registers plus a latch two output registers and two output enable registers Altera Corporation 10 15 June 2004 Quartus II Handbook Volume 3 Figure 10 10 Stratix Device 1 0 Element E E aT All TE D o D y aT aT xk gt ome tal q Pd FIT i A Tt a
49. flow signalprobe The execute flow command is in the flow package Command prompt quartus fit lt project name gt signalprobe Enable or Disable All SignalProbe Routing Use this Tcl code to enable or disable all SignalProbe routing For more information about enabling or disabling SignalProbe routing see page 8 5 Inthe set instance assignment command specify ON to enable all SignalProbe routing or OFF to disable all SignalProbe routing 8 11 Quartus Il Handbook Volume 3 set spe get all assignments name SIGNALPROBE ENABLE foreach in collection asgn spe set signalprobe pin name lindex asgn 2 set instance assignment name SIGNALPROBE ENABLE to signalprobe pin name lt ON OFF gt Conclusion 8 12 Running SignalProbe with Smart Compilation Use the following Tcl command to turn on Smart Compilation For more information see Running SignalProbe with Smart Compilation on page 8 7 set_global_assignment name SPEED DISK USAGE TRADEOFF SMART Allow SignalProbe to Modify Fitting Results Use the following Tcl command to turn on Modify latest fitting results For more information see Understanding SignalProbe Routing Failures on page 8 7 set_global_assignment name SIGNALPROBE ALLOW OVERUSE ON Using the SignalProbe incremental routing feature can significantly reduce the time required for a full recompilation You can use the SignalProbe incremental routing feature to
50. following provides step by step instructions on performing gate level timing simulation for Verilog HDL designs in the ModelSim Altera software cS The following steps assume you have already created a ModelSim project For additional information see Altera Design Flow with ModelSim Altera Software on page 1 3 Create Simulation Libraries gt This process is not required for the ModelSim Altera version because a set of pre compiled libraries are created when you install the software If you are using the Model Technology ModelSim software version you need to create the simulation libraries and correctly link them to your design 1 Choose New Library File menu 2 Inthe Create a New Library dialog box select a new library and a logical linking to it 3 Enter the name of the newly created library in the Library Name 4 Click OK vlib stratixii vmap stratixii stratixii Compile Simulation Models into Simulation Libraries ll This process is not required for the ModelSim Altera version because a set of pre compiled libraries are created when you install the software 1 17 Quartus Il Handbook Volume 3 1 18 1 Select Add to Project File menu and select Existing File 2 Browse to the lt quartus installation folder gt eda sim_lib gt and add the necessary simulation model files to your project 3 Select the simulation model file and select Properties View menu 4 Set the Compile to Library to th
51. generated by the compiler and elaborator US If you are running the NC Verilog simulator with the single step invocation method ncverilog and want to compile your source files and elaborate the design with one command use the elaborate option to stop the simulator after elaboration For example ncverilog elaborate test v Elaboration Command Line Mode To elaborate your Verilog HDL or VHDL design from the command line use the following command ncelab options lt library gt lt cell gt lt view gt For example ncelab worklib lpm ram dp test entity TS In verilog if a timescale has been specified the TIMESCALE option is not necessary You can set your simulation timescale using the TIMESCALE lt arguments gt option For example ncelab TIMESCALE lps lps worklib lpm ram dp test entity isa To view the elements in your library and which views are available use the ncls program For example the command ncls library worklib displays all of the cells and their views in your current worklib directory For more information on the ncls program see the Cadence NC Verilog Simulator Help or Cadence NC VHDL Simulator Help 3 13 Quartus Il Handbook Volume 3 3 14 IS If you are running the NC Verilog simulator using multistep invocation run ncelab with command line options as shown above You can specify the arguments in any order but parameters to options must immediately follow th
52. how to perform simulation using both the command line and the GUI Table 3 2 Command Line Programs Program Function ncvlog or NC Verilog ncvlog compiles your Verilog HDL code into a Verilog nevhdl Syntax Tree vst file nevlog also performs syntax and static semantics checks NC VHDL nevhdl compiles your VHDL code into a VHDL Syntax Tree ast file ncvhdi also performs syntax and static semantics checks ncelab NC Elab ncelab elaborates the design ncelab constructs the design hierarchy and establishes signal connectivity This program also generates a Signature File sig and a Simulation SnapShot File sss nesim NC Sim nesim performs mixed language simulation This program is the simulation kernel that performs event scheduling and executes the simulation code 3 3 Quartus Il Handbook Volume 3 Quartus II NC Simulation Flow Overview The Quartus II Cadence NC simulation flow is described below A more detailed set of instructions are given in Functional RTL Simulation on page 3 5 and Gate Level Timing Simulation on page 3 18 1 Setup your working environment UNIX only For UNIX workstations you must set several environment variables to establish an environment that facilitates entering and processing designs 2 Create user libraries Create a file that maps logical library names to their physical locations These library mappings include your working dire
53. learn more about register duplication see the Physical Synthesis for Registers Register Duplication section in the Netlist Optimization amp Physical Synthesis chapter in Volume 2 of the Quartus II Handbook Altera Corporation June 2004 12 5 Quartus II Handbook Volume 3 7 Perform full compilation of the design either by selecting Start Compilation Processing menu or by clicking the Start Compilation icon in the tool bar If your project includes any of the following design entities the synthesized VOM netlist file from the Synplify software contains black boxes and their boundary interface must be preserved e Altera library of parameterized modules LPMs functions The black box property is applied to only those LPM modules for which an equivalent Incisive Conformal model does not exist e Encrypted intellectual property IP cores e Entities that are defined in the design format other than Verilog HDL or VHDL The Quartus II software version 4 1 can identify black boxes automatically and set the Preserve Hierarchical Boundary logic option to Firm to preserve the boundary interfaces of the black boxes to aid in the formal verification Users can also set the black box property on the entities that need not be compared by the formal verification tool To do so make the following assignments for the entities in question E An EDA Formal Verification Hierarchy assignment with the value BLACKBOX mA Preserve
54. maxii lt ModelSim Altera installation directory gt altera vhdl maxii stratixii lt ModelSim Altera installation directory gt altera vhdl stratixii stratix lt ModelSim Altera installation directory gt altera vhal stratix stratixgx lt ModelSim Altera installation directory gt altera vhdl stratixgx stratixgx_gxb lt ModelSim Altera installation directory gt altera vhdl stratixgx_gxb cyclone lt ModelSim Altera installation directory gt altera vhdl cyclone apexii lt ModelSim Altera installation directory gt altera vhdl apexii apex20ke lt ModelSim Altera installation directory gt altera vhdl apex20ke apex20k lt ModelSim Altera installation directory gt altera vhdl apex20k flex10ke lt ModelSim Altera installation directory gt altera vhdI flex1Oke flex6000 lt ModelSim Altera installation directory gt altera vhdl flex6000 mercury lt ModelSim Altera installation directory gt altera vhdl mercury max lt ModelSim Altera installation directory gt altera vhdl max Altera Corporation June 2004 1 13 Quartus II Handbook Volume 3 Table 1 8 shows the location of the timing simulation libraries in the ModelSim Altera software for Verilog HDL for UNIX Table 1 8 Location of Timing Simulation Libraries for ModelSim Altera for Verilog HDL with UNIX Library Verilog HDL maxii lt ModelSim Altera installation directory gt modeltech altera verilog maxii strat
55. necessary modules during compilation However a full compilation is required if any design files Analysis and Synthesis settings or Fitter settings have changed To turn on Smart compilation turn on Use Smart compilation in the Compilation Process page in the Settings dialog box Assignments menu If you run a SignalProbe compilation with smart compilation on and there are changes to a design file or settings related to the Analysis and Synthesis or Fitter modules then you will get the following message Error Can t perform SignalProbe compilation because design requires a full compilation c Altera recommends turning on smart compilation so that you are always working with the latest settings and design files If the SignalProbe compilation starts and fails it could be because of one of the following reasons M The SignalProbe compilation failed to find a route from the SignalProbe source to the SignalProbe pin because of routing congestion M You entered a SignalProbe source that does not exist or is an invalid SignalProbe source M The output pin selected is found to be unusable Routing failures can occur if the SignalProbe pin s I O standard conflicts with other I O standards in the same I O Bank If routing congestion is preventing a successful SignalProbe compilation you can turn on Modify latest fitting results during SignalProbe compilation in the SignalProbe Settings page in the Settings dialog box Assignme
56. operation LUT equation LUT mask Synchronous mode Register cascade mode Mode of Operation An LE can operate in either normal or arithmetic mode For more information on the modes of operation see Volume 1 of the Stratix Device Handbook Volume 1 of the Cyclone Device Handbook or the MAX II Device Handbook When configured in normal mode the LUT can implement a function of four inputs When configured in arithmetic mode the LUT is divided into 2 three input LUTs The first LUT generates the signal that drives the output of the LUT while the second LUT is used to generate the carry out signal The carry out signal can drive only a carry in signal of another LE LUT Equation The LUT equation allows you to change the logic equation that is currently implemented by the LUT When the LE is configured in normal mode you can only change the SUM equation When the LE is configured in arithmetic mode you can change both the SUM and the CARRY equation When a change is made to the LUT equation the Quartus II software automatically changes the LUT mask To change the function implemented by the LUT you must first understand how the LUT works A LUT contains storage cells that implement small logic blocks as a function of the inputs Each storage cell is capable of holding a logic value either a 0 or a 1 The Stratix Stratix GX and Cyclone device families use a four input LUT and have 16 storage cells The LUT can store 16 output v
57. pin 4 11 Quartus Il Handbook Volume 3 Timing Analysis Reporting in the Quartus Il Software 4 12 ty Requirement Individual ty assignments have priority over global assignments You can make ty assignments to either the pin the input register from the pin to the input register or from the clock pin to the input register tpp Requirement Individual tpp assignments have priority over global assignments You can make tpp assignments from input pins to output pins from input pins to registers from registers to registers from registers to output pins and as a single point assignment to an input pin tsy Requirement Individual tsy assignments have priority over global assignments You can make tsy assignments to either the input pin the input register from the input pin to the input register or from the clock pin to the input register Timing Wizard The Timing Wizard helps you make global timing assignments Choose Wizards gt Timing Wizard Assignments menu to start it You can use either the Timing Wizard or the Timing Requirements amp Options page of the Settings dialog box to specify global timing requirements The Quartus II timing analysis report is displayed as sections in the Compilation report The timing report includes an fmax and slack for all clock pins US If there are no timing assignments for the design the Timing Analyzer does not generate slack reports for the clock pins The report
58. rati n g the The following steps describe how to set up the Quartus II software environment to generate the post fit VO netlist file and Incisive VO Fi I e amp Conformal script for use in formal verification Incisive If you have not yet done so create a new Quartus II project or open 1 Conformal Script an existing project 2 Choose EDA Tools Settings Assignments menu 3 On the EDA Tool Settings page of the Settings dialog box under EDA tools for Design entry synthesis specify Synplify or Synplify Pro Specify Conformal LEC for Formal verification Figure 12 2 12 2 Altera Corporation June 2004 Generating the VO File amp Incisive Conformal Script Figure 12 2 EDA Tools Selection Note 1 Category General EDA Tool Settings Files User Libraries Specify the other EDA tools in addition to the Quartus Il software used on this project Device Double click on a Tool Type below or select a page under EDA Tool Settings in the Category list to Timing Requirements amp Options change the EDA Tool or to specify options EDA Tool Settings Design Entry amp Synthesis EDA tools Simulation Tool type Tool name Run tool automatically Timing Analysis Design entry synthesis Synplify BoardLevel Simulation lt None gt Formal Verification Timing analysis lt None gt Resynthesis Board level lt None gt Compilation Process C Conformal LEC Resynthesis lt None gt
59. select NC verilog Click Next In the Select Components page turn on the PLI 1 0 Applications option select static In the Select PLI 1 0 Application Input page select Existing VERIUSER source object file Select Source File and click the browse button to locate the veriuser c file that is provided with the Quartus II software The veriuser c can be found in the following location lt Quartus II installation gt eda cadence verilog x1 Click Next In the PLI 1 0 Application page click Browse under PLI Source Files to locate the convert_hex2ver c file 11 12 13 14 15 Click Next In the Select Compiler page choose your C compiler from the Select Compiler list box An example of a C compiler would be gcc To allow the PLIWIZ to find your C compiler ensure your Path variable is set correctly Click Next Click Finish To build your targets now click Yes Altera Corporation August 2004 Scripting Support Compilation generates ncelab and ncsim executables into your local directory These executables replace the original ncelab and ncsim executables For ncverilog users you can use the following command to perform your simulation with the newly generated ncelab and ncsim executables ncverilog ncelabexe lt path to ncelab gt ncsimexe lt path to ncelab gt lt design files gt Example ncverilog ncelabexe ncelab ncsimexe ncsim my ram vt my ram v v altera mf v Scri
60. that SignalTap Il uses to capture data trigger in Input No This signal is used to trigger SignalTap Il trigger out Output No This signal is enabled when the trigger event has occurred Altera Corporation June 2004 Instantiating the SignalTap Il Logic Analyzer in your HDL The process of instantiating the Logic Analyzer in your HDL is similar to instantiating any other Verilog HDL or VHDL megafunction in your design You can instantiate as many analyzers in your design as will physically fit in the FPGA Once you have instantiated the SignalTap II file in your HDL compile your Quartus II project to fit the Logic Analyzer in the target FPGA To capture and view the data you must create an STP file from your SignalTap II MegaWizard output file The STP file is automatically created for you when you select Create SignalTap II File from Design Instance s from the Create Update Menu File menu 9 11 Quartus Il Handbook Volume 3 Programming the Device for SignalTap Il Analysis View Data Samples Advanced Features 9 12 When the compilation is complete you must program the FPGA To program a device for use with the SignalTap II Logic Analyzer follow these steps In the JTAG Chain Configuration panel in the STP file select the SRAM Object File sof that includes the SignalTap II Logic Analyzer 2 Click Scan Chain 3 In the Device list select the device to which you want to download the design
61. the Quartus II Handbook section of the Altera web site and find the retiming zip link in Volume 3 Chapter 10 Scenario The tco requirement for a particular design is 7 0 ns This requirement must be met to ensure that the output data is latched correctly before being sent to a receiving device Based on the Quartus II place and route results the timing analysis data is shown in Table 10 7 Table 10 7 Timing Analysis Data Part 1 of 2 Slack Required tco Actual te From To From CLK 0 317 ns 7 000 ns 7 317 ns outff_a 7 Out clk 0 204 ns 7 000 ns 7 204 ns outff_a 6 Out clk Altera Corporation 10 27 June 2004 Quartus II Handbook Volume 3 Table 10 7 Timing Analysis Data Part 2 of 2 Slack Required tco Actual tco From To From CLK 0 136 ns 7 000 ns 7 136 ns outff_a 8 Out clk 0 008 ns 7 000 ns 7 008 ns outff_a 9 Out clk The equation for tco is defined as tco lt clock to source register delay gt lt micro clock to output delay gt lt register to pin delay gt To meet the tco requirement either the lt clock to source register delay gt or the lt register to pin delay gt or both need to be reduced Solution Use the Chip Editor to manually perform gate level retiming to correct the tco If we examine one of the four failing paths in the timing analysis report we see the following results Info Slack time is 318 ps for clock clk between s
62. the allocated memory The number of cycles that are captured varies depending on the number of segments that you have specified through the Signal Configuration settings To enable and configure buffer acquisition select Segmented in the SignalTap II window and then choose the number of segments to use Selecting sixty four 64 bit segments allows you to capture 64 read cycles when the RADDR signal is H OFOFOFOF For more information on the buffer acquisition mode see Setting the Buffer Acquisition Mode in the Quartus II Help Capturing Data to a Specific RAM Type When using the SignalTap II Logic Analyzer with a Stratix device you can select the RAM type that is used to store the acquisition data RAM selection allows you to preserve a specific memory block for your design and allocate another portion of memory for SignalTap II data acquisition For example if your design implements a large buffering application such as a system cache it may be ideal to place this application into M RAM blocks so that the remaining M512 or M4K blocks can be used for SignalTap II data acquisition Use this feature when the acquired data as reported by the SignalTap II resource estimator is not larger than the available memory of the memory type that you have selected in the Stratix FPGA For example there are 94 M512 RAM blocks in a Stratix EP1S10 device For 94x576 RAM bits if you set the RAM type to M512 then you should make sure that your Sig
63. the software and the directories created during the Quartus II software installation The VCS software supports the following types of simulation M Functional RTL simulations M Post synthesis simulations M Gate level timing simulations 2 1 Preliminary Quartus II Handbook Volume 3 2 2 Figure 2 1 shows the VCS and Quartus II software design flow Figure 2 1 Altera Design Flow with the VCS amp Quartus Il Software ca Altera ip _ Design Entry Vi sel fe Testbench __ Functional RTL Simulation T y Synthesis Post Synthesis Simulation y Place and Route y Y Standard Delay Format Output File sdo Functional Models Post Synthesis Models Verilog Output File vo i Gate Level Timing Simulation Gate Level Models Functional RTL Simulations Functional RTL simulations verify the functionality of the design before synthesis and place and route These simulations are independent of any Altera FPGA architecture implementation Once the HDL designs are verified to be functionally correct the next step is to synthesize the design and use the Quartus II software for place and route To functionally simulate an Altera FPGA design in the VCS software that uses Altera IP megafunctions or library of parameterized modules LPM functions you must include certain libraries during
64. total device current should be verified during device operation as this measurement is sensitive to the actual implementation in the device and to the environmental operating conditions 7 1 Quartus II Handbook Volume 3 Power Estimation in the Quartus Il Software 7 2 The Quartus II Simulator has a power estimation feature that uses your design simulation vector files to estimate the device power consumption based on typical device operating conditions This feature enables you to identify and optimize system level power consumption in the design cycle For more information about how to perform simulations in the Quartus II software see Quartus II Help The power estimation is based on simulation vectors entered in the VWF or VEC and is estimated when performing a timing simulation To turn on the power estimation feature follow the steps below 1 Choose Settings Assignment menu 2 Inthe Settings dialog box under the Category list select Simulator see Figure 7 1 Figure 7 1 Simulator Settings x Category Files User Libraries Select options for simulations Device Timing Requirements amp Options ua E H EDA Tool Settings Simulation mode Timing Compilation Process Simulation input D data Power my_design my_design vwf E Analysis amp Synthesis Settings E Fitter Settings r Simulation period i Psa Run simulation until all vector stimuli are used lesign Assistant SignalT
65. vector files or a Power Input File pwf from a third party 4 Quartus Il Simulator reports the Quartus Il Power Report File 6 6 When filling out the Excel based power calculator you enter the device resources operating frequency toggle rates and other parameters in the power calculator This requires familiarity with the design If you do not have an existing design then you must estimate the number of device resources used in your design If you already have an existing design or a partially completed design the power estimation report file that is generated by the Quartus II software version 4 1 can aid in filling out the power calculator To generate the power estimation file you must first compile your design in the Quartus II software version 4 1 After compilation is complete choose Generate Power Estimation File Project menu which instructs the Quartus II software to write out a power estimation report text file See Figure 6 6 Altera Corporation June 2004 Quartus Il Power Report File Figure 6 6 Generate Power Estimation File Option Project Assignments Processing Tools Add Current File to Project Add Remove Files in Project Revisions Archive Project Restore Archived Project Generate Tcl File for Project Generate Power Estimation File HardCopy Utilities Locate Set as Top Level Entity Gtrl 3 Hierarchy
66. view a specific ALM in the Resource Property Editor right click on the ALM in the Timing Closure Floorplan Last Compilation Floorplan or Node Finder and select Locate in Resource Property Editor from the right button pop up menu Altera Corporation June 2004 Resource Property Editor For a detailed description of the ALM refer to the Stratix II device family handbook Figure 10 9 ALM Architecture f 3 5 a ox Supported Changes for an LE ALM Table 10 2 shows which operations are supported for various device families Table 10 2 Supported Operations for an LE ALM Operation Stratix Stratix GX Stratix Il Cyclone MAX Il View the LEs ALMs in the Resource Va 7 7 7 7 Property Editor Edit properties of the LEs ALMs 7 7 7 7 Placement changes the LEs ALMs v V4 VA VA Create new LEs ALMs Y VA 7 Y Altera Corporation 10 11 June 2004 Quartus II Handbook Volume 3 Properties of the Logic Element 10 12 This section discusses the following properties of the logic element that can be examined using the Resource Property Editor Mode of
67. vo v lt path to Quartus II installation gt eda sim_lib lt device family gt _atoms v compsdf For more information on using VirSim see the VirSim User Manual included in the VCS installation The VCS software has an interactive non graphical debugging capability that is very similar to other UNIX debuggers such as GNU debugger GDB The VCS CLI can be used to halt simulations at user defined break points force registers with values and display values of registers To enable the non graphical capability you must use the cli run time switch To use the VCS CLI to debug your Altera FPGA design use the following command ves R lt test bench gt v lt design name gt vo v lt path to Quartus II installation gt eda sim lib lt device family gt atoms v compsdf cli 2 9 Quartus Il Handbook Volume 3 Using PLI Routines with the VCS Software Scripting Support 2 10 The cli command takes an optional number argument that specifies the level of debugging capability As the optional debugging capability is increased the overhead incurred by the simulation is increased resulting in an increase in simulation times For more information on the cli switches see the VCS User Guide included in the VCS installation The VCS software can interface your custom defined C code with Verilog source code This interface is known as PLI This interface is extremely useful because it allows advanced users to define their
68. with Chip Editor Introduction alla aaa NE 10 1 Background uil 10 1 Using the Chip Editor in Your Design Flow ss 10 2 Chip Editor Overview Chip Editor Floorplani utilita lea Bird S Eye VIEW seepe ii rail First Highest Level View Second Level View i Third Level View ciricianica delie Resource Property Editor sssini nrar esis an ia Altera Corporation vii Quartus Il Handbook Volume 3 The L gic Element LE sn iii The Adaptive Logic Module ALM Supported Changes for an LE ALM ss 10 11 Propertiesof the Logic Element ilarit 10 12 Mode of Operation LUT Equationi ricalcare aan dere acess EUT Mask aisi ella ariana Synchronous Mode Register Cascade Mode sisi unies aaa 10 14 Properties of an ALM piii a 10 14 LUT Mask Extended LUT MOC saves cscess cassis tria lait Shared Arithmetic Mode FPGA I O Elements sisi Stratix Stratix GX and Stratix II I O Elements Cyclone I O Elements MAX TE T OS ciccia isernia ei iii Supported Changes for an I O Element Editable Properties of I O Elements Modifying the PLL Using the Chip Editor Properties of the PLL Adjusting the Duty Cycle Adjusting the Phase Shift Adjusting the Output Clock Frequency ss Adjusting the Spread Spectrum Change Managetiziciaranii lire init Common Applications natalizi Gate Level Registe
69. 15H 54 239 2 stratix asynch io out I padio stratix io 0 000 Ds 239 E out out 0 00 52239 E data arrival time 5239 clock clk rise edge 10 000 10 000 clock network delay propagated 0 000 10 000 output external delay 7 000 3 000 data required time 3 000 data required time 3 000 data arrival time 5 5239 slack VIOLATED 2 239 5 5 Quartus Il Handbook Volume 3 Running PrimeTime Conclusion 5 6 The start point in this report is a register clocked by clock clk Endpoint is an output pin out This is equivalent to either a tco or a Minimum tco path in the Quartus II software depending on the delay option At the end of the report Violated is listed which means that the constraint was not met A negative slack is also given as it is in the Quartus II software PrimeTime is only available to run on Unix systems The three files created by the Quartus II software must be transferred to a Unix machine PrimeTime runs in shell mode by accepting scripts in Tcl format The lt project_name gt _pt_v tcl script file for example is executed in the following way Type the following command at the UNIX command line prompt and press the Return key pt_shell f project name pt v tcl After all commands in the Tcl script file are executed pt_shell gt prompt appears More pt_shell commands can be executed at that prompt including the following E man report timing This command will list details of how to us
70. 527 A_in_O_ apex20ke_io_reg_source_mode18527 A_in_1_ apex20ke_io_reg_source_mode18527 A_in_1_ apex20ke_io_reg_source_mode18527 A A_in_2_ apex20ke_io_reg_source_moc amp 18527 E A_in_2_ apex20ke_io_reg_source_mode18527 B CLk_in apex20ke_io_reg_source_mode 1985279 B CLk_infapex20ke_io_reg_source_mode 195279 E DA_out_0_ apex20ke_io_reg_source_mode185 E DA_out_0_ apex20ke_io_reg_source_mode185 E DA_out_1_ apex20ke_io_reg_source_mode185 E DA_out_1_ apex20ke_io_reg_source_mode185 E DA_out_2_ apex20ke_io_reg_source_mode185 E DA_out_2_ apex20ke_io_reg_source_mode185 E DA_out_3_ apex20ke_io_reg_source_mode185 E DA_out_3_ apex20ke_io_reg_source_mode185 E DA_out_4_ apex20ke_io_reg_source_mode185 E DA_out_4_ apex20ke_io_reg_source_mode185 E D _out_5_ apex 0ke_io_reg_source_mode1852 E DA_out_5_ apex20ke_io_reg_source_mode185 E DA_out_6_ apex20ke_io_reg_source_mode185 E DA_out _6_ apex20ke_io_reg_source_mode185 E DA_out_7_ apex20ke_io_reg_source_mode185 E DA_out_7_ apex20ke_io_reg_source_mode185 B DI_in_0_ apex20ke_io_reg_source_mode1852 B DI_in_0_ apex20ke_io_reg_source_mode1852 B DI_in_1_ apex20ke_io_reg_source_mode1852 B DI_in_1_ apex20ke_io_reg_source_mode1852 B DI_in_2_ apex20ke_io_reg_source_mode1852 B DI_in_2_ apex20ke_io_reg_source_mode1852 ere ee TT a ep NOM eae ZI lt lt b 8 Check out vlg 3 0 license Golden root module is set to mi2c Note Read VERILOG design successfully ed sensitive Revised sensitive
71. 9 28 SignalProbe Adding Sources 8 3 8 10 Index 4 Compilation Performing 8 5 Fitting Results Modification 8 12 Pins Reserving 8 2 8 10 Results Compilation 8 8 Routing Enable or Disable All 8 11 Routing Failures 8 7 Run Automatically 8 11 Run Manually 8 11 Running with Smart Compilation 8 7 8 12 Using 8 1 SignalTap II Analysis Programming Device 9 12 Logic Analyzer Compiling Design 9 8 Creating HDL Representation 9 8 Debug Multiple Designs 9 29 Including in Design 9 2 Instantiating in HDL 9 11 Timing Preservation 9 29 Logic Analyzers SOPC Builder Systems 9 35 SignalTap II Local PC Setup 9 28 Megafunction Ports 9 11 Remote Debugging 9 25 Used FPGA Resources 9 24 Using in Lab Environment 9 25 Simulate Design 3 23 Design 3 17 Simulation Flow 3 1 Libraries Gate Level 1 12 Slack 4 4 Hold Time 4 4 Spread Spectrum Adjusting 10 23 Standard Delay Output File Compiling 3 22 Statically Link 3 28 STP File Assigning Signals 9 5 Altera Corporation Creating 9 3 Using to Create Analyzer 9 3 Embedded Logic T Tappable Signals 9 29 Tcl Commands 2 11 commands 3 29 Executing Script Based Commands 4 6 tCO Requirement 4 11 Testbench Compile into Work Library 1 18 tH Requirement 4 12 Time Bars and Next Transition 9 22 Timing Analysis Advanced 4 13 Asynchronous Domains 4 32 Basics 4 1 Third Party Software 4 34 Analysis Reporting 4 12 Analyzer 4 6 Running 10 33 Assignments Setting Global 4 7 Setting Other
72. 9 _4_ MN spread 1 MN sa For a detailed description of the settings see Quartus II Help For more information on Stratix device PLLs see the Stratix Architecture chapter in Volume 1 of the Stratix Device Handbook The Change Manager allows you to track all the design changes made with the Chip Editor Table 10 5 summarizes the information shown by the Change Manager Table 10 5 Change Manager Information Column Name Description Node name Name of the node modified with the Chip Editor Change type Type of change made to the node Old value Value previous to the change Target value Value of the change that you want to set before a Check and Save has been performed Current value Value in the currently viewed netlist This value is not necessarily ready for POF generation Disk value Current value of the node as contained within the assembler netlist Value available for use in the Assembler Timing Analysis Simulation Status Current state of the change made to the node specified Comments User comments The current state of your change can be viewed in the Change Manager When the Check amp Save All Netlist Changes function is performed you will see the status of the change in the Change Manager See Figure 10 14 10 23 Quartus Il Handbook Volume 3 Figure 10 14 Change Manager Results Node Name Change Type Old Value Status 1 Itestlout2 Location Index
73. Advanced Trigger Options MegaWizard Plug In Manager SLD_SIGNALTAP page 2 of 4 signaltapll X aca_ck X aca_data_in 7 0 Y aca_trigger_in 7 0 Select Advanced from the Trigger level options list for each trigger that you want to use as an Advanced trigger Trigger level options Trigger level 1 Trigger level 2 Trigger level 3 Trigger level 4 Trigger level 5 Trigger level 6 Trigger level 7 Trigger level 8 Trigger level 9 Trigger level 10 Basic advanced id X M Cancel lt Back Next gt Finish Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer 9 Click Finish to complete the process of creating an HDL representation of the SignalTap II Logic Analyzer SignalTap Il Megafunction Ports Table 9 1 provides information on the SignalTap II megafunction ports isa Refer to the latest version of the Quartus II software Help for the most current information on the ports and parameters for this megafunction Table 9 1 SignalTap Il Megafunction Ports Port Name Type Required Description acq data in Input No These set of signals represent the signals that are monitored in SignalTap Il acq_trigger_ Input No This set of signals represent the set of signals in that are used to trigger the analyzer acq_clk Input Yes This port represents the sampling clock
74. Altera installation directory gt modeltech altera vhdl stratixii stratix lt ModelSim Altera installation directory gt modeltech altera vhdl stratix stratixgx lt ModelSim Altera installation directory gt modeltech altera vhdl stratixgx stratixgx_gxb lt ModelSim Altera installation directory gt modeltech altera vhdl stratixgx_gxb cyclone lt ModelSim Altera installation directory gt modeltech altera vhdl cyclone apexii lt ModelSim Altera installation directory gt modeltech altera vhdl apexii apex20k lt ModelSim Altera installation directory gt modeltech altera vhdl apex20k apex20ke lt ModelSim Altera installation directory gt modeltech altera vhdl apex20ke mercury lt ModelSim Altera installation directory gt modeltech altera vhdl mercury flex10ke lt ModelSim Altera installation directory gt modeltech altera vhdl flex 1 Oke 1 14 Altera Corporation June 2004 Gate Level Timing Simulation Table 1 9 Location of Timing Simulation Libraries for ModelSim Altera for VHDL with UNIX Part 2 of 2 Library VHDL flex6000 lt ModelSim Altera installation directory gt modeltech altera vhdl flex6000 max lt ModelSim Altera installation directory gt modeltech altera vhdl max Altera Corporation June 2004 If you are using the ModelSim Modeltech version for your timing simulation libraries are available in the Quartus II software at the following location lt Quartu
75. C Verilog or NC VHDL software interface For UNIX workstations only The information presented here assumes that you are using the C shell and that your Quartus II system directory is usr quartus If not you must use the appropriate syntax and procedures to set environment variables for your shell 1 For UNIX workstations only Add the following environment variables to your cshrc file setenv QUARTUS ROOTDIR usr quartus setenv CDS INST DIR lt NC installation directory gt 2 Add CDS_INST_DIR tools bin directory to the PATH environment variable in your cshre file Make sure this path are placed before the Cadence hierarchy path 3 Add usr dt lib and usr ucb lib to the LD_LIBRARY_PATH environment variable in your cshre file 4 Source your cshre file by typing source cshrc at the command prompt Following is an example setting these environment variables Setting Environment Variables setenv QUARTUS ROOTDIR usr quartus setenv CDS_INST_DIR lt NC installation directory gt setenv PATH PATH lt NC installation directory gt tools sun4v bin setenv LD LIBRARY PATH usr ucb lib usr lib usr dt lib usr bin X11 lt NC installation directory gt tools sun4v lib LD_LIBRARY PATH setenv QUARTUS INIT PATH lt NC installation directory gt tools sun4v bin Altera Corporation 3 5 August 2004 Quartus Il Handbook Volume 3 3 6 Create Libraries Before simulating with NC simulators you must set up librarie
76. CK signal through two flip flops and then de asserts the REQ signal This technique guarantees that the data is transferred correctly and there is no meta stability due to asynchronous signals Figure 4 33 shows the interaction across asynchronous boundaries 4 32 Altera Corporation June 2004 Quartus Il Timing Analysis Figure 4 33 Interaction Across Asynchronous Boundaries n REQ Data Bus Block B Block A ACK 33Mhz 21Mhz Minimum Minimum timing analysis measures and reports minimum tco sla F minimun tpp ty and clock hold Minimum Timing analysis is performed Ti min g Ana lysis by checking for minimum delay requirements with best case timing models delay models Best case timing models characterize device operation at the highest voltage fastest process and lowest temperature conditions Worst case timing models delay models characterize device operation based on the slowest process lowest voltage and highest temperature conditions Minimum delay checks like ty are also reported during regular timing analysis using worst case delay models Minimum Timing Analysis Settings You can make global minimum ty minimum tco and minimum tpp assignments in the Minimum Delay Requirements section of the Timing Requirements amp Options page of the Settings dialog box Assignments menu You can also make individual m
77. CLK1 CLK2 0 2 8 14 18 24 Clock 1 Period 12 ns Clock 2 Period 6ns Offset 2ns Multicycle 4 Multicycle Hold The first check illustrated with the dashed line requires a minimum data delay of 10 ns 24 ns 14 ns The second check illustrated with the dotted line requires a minimum data delay of 16 ns 18 ns 2 ns Data must have a maximum delay of 22 ns and a minimum delay of 16 ns to meet the Multicycle and Multicycle Hold requirements Altera Corporation 4 27 June 2004 Quartus II Handbook Volume 3 False Paths A false path is any path that is not relevant to a circuit s operation You can make a variety of assignments to exclude false paths from timing analysis Global assignments excluding common false paths are turned on in the Timing Requirements amp Options page of the Settings dialog box by default You can make separate Cut Timing Path assignments to cut individual false paths Cut Off Feedback from 1 0 Pins This option which is on by default cuts off feedback paths from I O pins as shown in Figure 4 28 Figure 4 28 Cut Off Feedback from 1 0 Pins 4 28 The paths marked with arrows are not measured by timing analysis when this option is turned on Turn off Cut off feedback from I O pins to measure these paths during timing analysis Cut Off Clear and Preset Signal P
78. Clock signal Clock Skew Clock skew is the difference in arrival time of a clock signal at two different registers Figure 4 6 Clock skew occurs when two clock signal paths have different lengths Clock skew is common in designs that contain clock signals that are not routed globally The Quartus II Timing Analyzer reports clock skew for all clocks within the design Figure 4 6 Clock Skew DFFJ ne i DEF on PRN i PRN D Qp i D Q CLRN inst Altera Corporation 4 5 June 2004 Quartus II Handbook Volume 3 Executing Tcl Script Based Timing Commands Setting up the Timing Analyzer 4 6 You can make timing assignments perform timing analysis and analyze results in the Quartus II software GUI or with Tcl commands You can use simple Tcl commands to perform customized timing reporting and you can write scripts with advanced timing analysis commands to perform complex timing analysis and reporting You can use the command based timing analyzer in an interactive shell mode where you can run timing analysis Tcl scripts To run the timing analyzer in interactive shell mode type the following command quartus tan s To run a Tcl script type the following command quartus tan t lt tel file gt The following commands are frequently needed for executing timing related scripts M Package require quartus lt advanced_timing gt Different packages are required for a different set of commands E project open lt pr
79. EDA Simulation Tools Scripting SUPppoft uu Simulation Based Power Estimation Settings ui Generate a Power Input File Conelusioni sisi aa IRA li re References utilita aaa aaa Section IV On Chip Debugging Revision History gii iaia Section IV 2 Chapter 8 Quick Design Debugging Using SignalProbe INETOALUCHON sticitrtiara terne E EEEE E N iena lieti Using SignalProbe Reserving SignalProbe pins Adding SignalProbe Sources Assigning I O Standards ia Adding Registers for Pipelining uccida lil Performing a SignalProbe Compilation Running SignalProbe with Smart Compilation ss Understanding SignalProbe Routing Failures ss Understanding the Results of a SignalProbe Compilation Seripung SUpport 22e a e leale dr Reserving SignalProb Pins ipt ica Adding SignalProbe Sources Assigning O Standards 3 iniinuzianionie ibi eninsnenenreninienins Adding Registers for Pipelining iui ii Run SignalProbe Automatically Run SignalProb Manually 100 0a vi Altera Corporation Contents Enable or Disable All SignalProbe Routing ss Running SignalProbe with Smart Compilation Allow SignalProbe to Modify Fitting Results ii Conclusioni siii ani aeneon Chapter 9 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Introduction il Lease all 9 1 Including the SignalTap II Logi
80. GA design flow You can perform functional and timing simulation of your design by using the Quartus II Simulator The Quartus II software also provides a wide range of features for performing simulation of designs in EDA simulation tools This section includes the following chapters m Chapter Mentor Graphics ModelSim Support E Chapter 2 Synopsys VCS Support m Chapter 3 Cadence NC Sim Support Revision Histo ry The table below shows the revision history for Chapters 1 to 3 Chapter s Date Version Changes Made 1 June 2004 v2 0 e Updates to tables figures e New functionality for Quartus 4 1 Feb 2004 v1 0 Initial release 2 June 2004 v2 0 e Updates to tables figures e New functionality for Quartus 4 1 Feb 2004 v1 0 Initial release 3 Aug 2004 v2 1 e New functionality for Quartus 4 1 SP1 June 2004 v2 0 Updates to tables figures e New functionality for Quartus 4 1 Feb 2004 v1 0 Initial release Altera Corporation Section I 1 Simulation Quartus Il Handbook Volume 3 Section l 2 Altera Corporation JA DTE RYA 1 Mentor Graphics ModelSim Support qii53001 2 0 Introduction Background An Altera software subscription includes a license for the ModelSim Altera software on a PC or UNIX platform The ModelSim Altera software can be used to perform funtional RTL and gate level timing simulations for either VHDL or Verilog HDL designs targeti
81. HDL IS When you are simulating a design that uses VHDL 1987 use 220model_87 vhd For more information on LPM functions see the Quartus II Help Altera Megafunction Simulation Models To simulate a design that contains Altera Megafunctions use the following simulation models M altera_mf v for Verilog HDL M altera mf vhd and altera_mf_components vhd for VHDL Is When you are simulating a design that uses VHDL 1987 use altera_mf_87 vhd 1 4 Altera Corporation June 2004 Functional RTL Simulation Table 1 3 shows the location of the simulation model files in the Quartus II software and the ModelSim Altera software Table 1 3 Location of LPM Simulation Models Software Location Quartus Il lt Quartus Il installation directory gt eda sim_1lib 1 ModelSim Altera lt ModelSim Altera installation directory gt altera lt HDL gt 220mode1 2 PC ModelSim Altera lt ModelSim Altera installation directory gt modeltech altera lt HDL gt 220mode1 1 UNIX Note to Table 1 3 1 For Model Technology s ModelSim use the files provided with the Quartus II software 2 Compile 220pack vhd before 220model vhd Table 1 4 shows the location of these files in the Quartus II software and the ModelSim Altera software Table 1 4 Location of Altera Megafunction Simulation Models Software Location Quartus Il lt Quartus Il installation directory gt eda sim_lib 1 Mode
82. Hierarchical Boundary assignment with the value Firm Figure 12 5 12 6 Altera Corporation June 2004 Generating the VO File amp Incisive Conformal Script Figure 12 5 Setting the Black Box Property on a Module 4 Quartus II C erplex bassilio fpga_risc8 quartus_fv risc8 risc8 File Edit View Project Assignments Processing Tools Window Help p d e s amp Be oe x fisc SPA LEA AAA 21xl idec idec ii regsrego EHE dram dram Gb risc8_cell_stacklevel_2_0__h_1 s Full Compilation Analysis amp Synthesis Fitter Assembler Timing Analyzer EDA Netlist Writer M Show assignments for specific nodes regs regsidram dram Check All oe ll l D YS fue a ESS Uncheck All This cell specifies the value of the assignment lt regs regs dram d EDA Formal Verification Hierarchy BLACKBOX lt regs regs dram d Preserve Hierarchical Boundary Firm regs regs dramid Altera Corporation June 2004 The Quartus II software compiler generates A VO file lt design_name gt vo A Script file lt design_name gt ctc used with Incisive Conformal software referencing lt design_name gt clg and lt design_name gt clr to read the library files and black box descriptions A blackboxes directory containing all the user defined black box entities in the des
83. Il software version 3 0 ModelSim Altera software version 5 7e Quartus Il software version 4 0 ModelSim Altera software version 5 8c Quartus Il software version 4 1 Note to Table 1 2 1 ModelSim Altera precompiled libraries are updated with Quartus II release and service packs and are generally available for download on Altera s web site 1 2 Altera Corporation June 2004 Altera Design Flow with ModelSim Altera Software Altera Design Flow with ModelSim Altera Software Altera Corporation June 2004 Figure 1 1 illustrates an Altera design flow using the ModelSim Altera software or ModelSim Full Version E Functional RTL simulations M Gate level timing simulations Figure 1 1 Altera Design Flow with ModelSim Altera and Quartus II Software cs Aleralp _ gt Design Entry __ Testbench c Functional Simulation at w Synthesis Place and Route i Verilog Standard Delay Output Format Output File vo File sdo c K Gate Level Simulation Gate Level Models Functional RTL Simulation Functional RTL simulations verify the functionality of the design before synthesis and place and route These simulations are independent of any Altera FPGA architecture implementation Once the HDL designs are verified to be functionally correct the next step is to synthesize the design and use the
84. Individual 4 8 Simulation Gate Level 1 4 1 11 2 6 Generating Gate Level Netlist 2 6 Simulation Netlist Gate Level for VCS 2 11 Timing Simulation Gate Level 3 3 3 18 Wizard 4 12 tPD Requirement 4 12 Transport Delays 2 8 Trigger Creating Complex 9 14 In 9 17 Levels Number of 9 7 Out 9 17 Altera Corporation Using as Trigger In of Another Analyzer 9 18 Position Specifying 9 7 Type Basic or Advanced 9 6 Using External 9 17 tSU Requirement 4 12 V Variable LM_LICENSE_FILE 1 20 VCS Compile Switches Common 2 8 Debugging VCS Command Line Interface 2 9 Netlist Generating Post Synthesis Simulation 2 11 Using in Quartus II Design Flow 2 1 Verilog Code Preparing amp Linking C Programs 2 10 Functional RTL Simulation with Altera Mem ory Blocks 1 10 Simulating Designs 1 7 Simulation Designs 1 17 Verilog HDL 3 11 Code 3 15 veriuser c Modified 3 26 Original 3 25 VHDL 3 11 Simulating Designs 1 5 1 15 View First Level View 10 6 Second Level View 10 7 Third Level View 10 8 VirSim Using 2 9 Index 5 Quartus II Handbook Volume 3 Index 6 Altera Corporation
85. NPUT _ i i OUTPUT i VC Ho of a ar INPUT i i clk VCC o gt CLRN inst Po 4 10 Altera Corporation June 2004 Quartus Il Timing Analysis In the example shown in Figure 4 10 when the enable is active the clock is inverted Under these circumstances you should make an inverted clock assignment to the register inst1 to ensure that the Timing Analyzer recognizes the inverted clock Not a Clock The Timing Analyzer automatically identifies any pin that feeds through to the clock input of a register as a clock An example is shown in Figure 4 11 Figure 4 11 Not a Clock Diagram Altera Corporation June 2004 In Figure 4 11 the Timing Analyzer identifies three clock pins for the design clock gatea and gateb The pins gatea and gateb are identified as clock pins because they feed through an OR gate and an AND gate to the clock inputs of registers inst1 and inst 3 If you do not want to view these pins as clocks you can remove them from timing analysis with the Not a Clock assignment For example you can use the following Tcl command to explicitly remove a clock from timing analysis set instance assignment name NOT A CLOCK to clk tco Requirement Individual tco assignments have priority over global assignments You can make tco assignments to either the pin the output register or from the output register to the
86. OR Reduction Reduction XOR Reduction Left Shift Shift Right Shift Shift Bitwise Complement Bitwise Bitwise AND Bitwise Bitwise OR Bitwise Bitwise XOR Bitwise Edge and Level Detector Signal Detection Note to Table 9 2 1 For more information on each of these operators see Quartus II Help Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Altera Corporation June 2004 Some of the operators have the ability to be configured at run time This allows you to change one operator type to another operator type without recompiling your design Operators that have a white background are run time configurable The following examples show how to use Advanced Triggering M Trigger when bus outa is greater than or equal to outb see Figure 9 7 Figure 9 7 Bus Out a is Greater Than or Equal to Out b Advanced Trigger Condition Editor Level 1 Result outa gt outk GREATER THAN OR EQUAL TO M Trigger when bus outa is greater than or equal to outb and when the enable signal has a rising edge see Figure 9 8 9 15 Quartus II Handbook Volume 3 Figure 9 8 Enable Signal Has a Rising Edge Result outa gt outb sELD enable E comparison_O E logical0 LOGICAL AND DETECTOR E Trigger when bus outa is greater than or equal to bus outb or when the enable signal has a rising edge Or when
87. Reset Mode Input Powers Up Output Register Mode Output Register Reset Mode Output Register Synchronous Reset Mode Output Powers Up OE Register Mode OE Register Reset Mode 10 20 Altera Corporation June 2004 Modifying the PLL Using the Chip Editor Modifying the PLL Using the Chip Editor Altera Corporation June 2004 OE Register Synchronous Reset Mode OE Powers Up Input Pin to Logic Array Delay Output Pin Delay Input Pin to Input Register Delay Max II Properties You can use the Resource Property Editor to modify the following properties of MAX II device I O cells Bus Hold Weak Pull Up Slow Slew Rate Open Drain I O Standard Current Strength Extend OE Disable PCII O Input Pin to Logic Array Delay PLLs are used to modify and generate clock signals to meet design requirements Additionally PLLs are used for distributing clock signals to different devices in a design reducing clock skew between devices improving I O timing and generating internal clock signals Properties of the PLL You can change many of the PLL properties with the Resource Property Editor You can modify the following internal parameters of the PLL The in loop parameters that can be modified include M initial M Counter Time Delay M M VCO Tap N Counter Time Delay N M2 N2 Loop filter resistance Loop filter capacitance Charge pump current The post loop parameters that can be modified include 10 21 Qua
88. SDO file for the project by adding the following lines to an ASCII SDF command file for the project COMPILED SDF FILE lt project name gt sdf X SCOPE lt instance path gt Example SDF Command File SDF command file sdf file COMPILED SDF FILE lpm ram dp test vhd sdo X SCOPE tb MTM CONTROL TYPICAL SCALE FACTORS 1 0 1 0 1 0 SCALE TYPE FROM MTM After you compile the SDO file execute the following command to elaborate the design ncelab worklib lt project name gt entity SDF CMD FILE lt SDF Command File gt Compiling the Standard Delay Output File VHDL Only GUI To annotate the SDO timing data in the GUI perform the following steps 1 2 3 3 22 Choose SDF Compiler Tools menu In the SDF File box specify the name of the SDO file for the project Click OK Altera Corporation August 2004 Incorporating PLI Routines When you have finished compiling the SDO file you can elaborate the design See Elaboration GUI Mode on page 3 14 for step by step instructions however before clicking OK to begin elaboration perform the following additional steps to create the SDF command file 1 Click Advanced Options in the Elaborate dialog box 2 Click Annotation in the left pane 3 Turn on the Use SDF File option in the right pane 4 Click Edit 5 Browse to the location of the SDF Command File Name 6 Browse to the loc
89. Script on page 12 2 the netlist synthesized by the Quartus II software contains black boxes if your project includes any of the following M LPM functions M Encrypted IP functions M Entities not implemented in Verilog HDL or VHDL Every LPM function is treated as a black box by the Synplify software If a corresponding Incisive Conformal verification model exists however the LPM function is replaced by logic cells in the VOM netlist file generated by the Quartus II software For example if the design has references to the functions 1pm mult and lpm_rom only lpm_romis treated as a black box because the corresponding Incisive Conformal verification model is not available Altera Corporation June 2004 Comparing Designs Using Incisive Conformal Software Altera Corporation June 2004 VO netlist files written by the Quartus II software also contain the black box hierarchy when the user makes the following assignments for a module E An EDA Formal Verification Hierarchy assignment with the value BLACKBOX mA Preserve Hierarchical Boundary assignment with the value Firm Figure 12 3 If the above two assignments are not made for a module the Quartus II software replaces the black box with logic cells and the VO netlist file no longer contains the black box hierarchy or preserves the port interface resulting in a mismatch within the Incisive Conformal software Running the Incisive Conformal Software Run Incisive Conformal
90. UI Mode 3 12 Compile Project Files amp Libraries 3 21 Source Code amp Testbenches 3 11 Cut Off Clear and Preset Signal Paths 4 28 Feedback I O Pins 4 28 Read During Write Signal Paths 4 29 Cut Paths Between Unrelated Clock Domains 4 30 Cut Timing Path 4 30 Index 1 Quartus Il Handbook Volume 3 Data Capturing to Specific RAM Type 9 24 Data Delay Increase 4 32 Data Samples View 9 12 Design Cycle Estimating Power Elaborate 3 21 Flaw Correcting 10 27 Simulating with Memory 3 10 Device amp Megafunction Support 11 2 Duty Cycle Adjusting 10 22 Dynamically Link 3 24 Dynamically Load 3 25 6 3 E EDA Simulation Tools Estimating Power 7 4 Elaborate Design 3 13 Elaboration Command Line Mode 3 13 GUI Mode 3 14 Elements Cyclone I O 10 17 Editable Properties ofI O 10 19 FPGA I O 10 15 Stratix Stratix GX amp Stratix II O 10 15 Supported Changes for anI O 10 18 Embedded Logic Analyzer Creating with MegaWizard Plug In Manager 9 8 Embedding Multiple Analyzers in One FPGA 9 20 Environment Setting Up 3 5 3 20 Setting Variables 3 5 Equipment Setup 9 26 Equivalence Checking 12 1 Index 2 F False Paths 4 28 File Conversion HEX 1 10 2 4 FPGA Memory Preserving 9 13 Functional RTL Simulation 1 3 1 4 2 2 Altera Memory Blocks 2 3 Command Line Mode 3 18 GUI Mode 3 18 Libraries 1 4 Functional RTL Simulation 3 2 3 5 H Hex Editor Viewing Memory amp Constants Hold Time Violati
91. a Corporation June 2004 Output Maximum Delay Use this timing assignment to specify the maximum allowable delay of a signal from the specified output pin to an external register outside the device The value of this assignment usually represents the tsy of the external register fed by the output pin of the Altera device plus the actual board delay Conversely you can set the minimum allowable delay with the Output Minimum Delay assignment Figure 4 9 shows a block diagram of the external output delay 4 9 Quartus Il Handbook Volume 3 Script usage of output minimum delay set output delay clk ref lt clock gt to lt output pin gt min lt value gt Figure 4 9 Quiput Delay Altera Device External Device External Output Delay DFF DFF J CERRI CT AA pin_niame BR cs iii ance gt CLRN int Inverted Clock The Quartus II Timing Analyzer automatically detects registers with inverted clocks and uses the inversion in the timing analysis report This functionality applies to both clocks that use globals and clocks that do not use globals However the Timing Analyzer can fail to automatically detect inverted clocks when the inversion is part of a complex logic structure An example of a complex logic structure is shown in Figure 4 10 Figure 4 10 Complex Logic Structure DFF DEF reg PRN i i PRN picca wa I
92. a verilog maxii stratixii lt ModelSim Altera installation directory gt altera verilog stratixii stratix lt ModelSim Altera installation directory gt altera verilog stratix stratixgx lt ModelSim Altera installation directory gt altera verilog stratixgx stratixgx_gxb lt ModelSim Altera installation directory gt altera verilog stratixgx_gxb 1 12 Altera Corporation June 2004 Gate Level Timing Simulation Table 1 6 Location of Timing Simulation Libraries for ModelSim Altera for Verilog HDL on a PC Part 2 of 2 Library Verilog HDL cyclone lt ModelSim Altera installation directory gt altera verilog cyclone apexii lt ModelSim Altera installation directory gt altera verilog apexii apex20k lt ModelSim Altera installation directory gt altera verilog apex20k apex20ke lt ModelSim Altera installation directory gt altera verilog apex20ke mercury lt ModelSim Altera installation directory gt altera verilog mercury flex10ke lt ModelSim Altera installation directory gt altera verilog flex 1 Oke flex6000 lt ModelSim Altera installation directory gt altera verilog flex6000 max lt ModelSim Altera installation directory gt altera verilog max Table 1 7 shows the location of the timing simulation libraries in the ModelSim Altera software for VHDL for PCs Table 1 7 Location of Timing Simulation Library Files for ModelSim Altera for VHDL on a PC Library VHDL
93. alues in its storage cells The output from the LUT depends on the signal that is driven into the input ports of the LUT Assume that you need to build the following logic function A XOR B OR C AND D Altera Corporation June 2004 Properties of the Logic Element Altera Corporation June 2004 LUT Mask To generate the LUT mask the truth table for an equation must be computed Table 10 3 lists the truth table for logic equation from the section above Table 10 3 LUT Mask Truth Table D Input C Input B Input A Input Output 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 The LUT mask is the hexadecimal representation of the LUT output For example the LUT output of A XOR B OR C AND D is represented by the following binary number 1111011001100110 The LUT mask in hexadecimal for this binary number is F666 When the LE is set to arithmetic mode the first eight bits in the LUT mask represent the SUM equation output The second eight bits represent the CARRY equation When a change is made to the LUT mask the Quartus II software automatically computes the LUT equation 10 13 Quartus Il Handbook Volume 3 Properties of an ALM 10 14 Synchronous Mode When an LE is in synchronous mode the synchronous load s
94. ames To avoid this issue you may need to use the synthesis attributes to preserve signals during synthesis and place and route When the Quartus II software encounters these synthesis attributes it does not perform any optimization on the specified signals Therefore you may see an increase in resource utilization and or a decrease in timing performance The two attributes you may be able to use are M Keep This attribute ensures that combinational signals do not get removed M Preserve This attribute ensures that registers do not get removed Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Altera Corporation June 2004 For more information on using these attributes see the Quartus II Integrated Synthesis chapter in Volume 1 of the Quartus II Handbook Tappable Signals Not all of the post fitting signals in your design are available in the SignalTap II post fitting in the Node Finder The types of signals that cannot be tapped are listed below M Signals that are part of a Carry Chain You cannot tap the carry out cout0 or cout1 signal of a logic element Due to architectural restrictions the carry out signal can only feed the carry in of another LE E PILclkout You cannot tap the output clock of a PLL Due to architectural restrictions the clock out signal can only feed the clock port of a register M JTAG Signals You cannot tap the JTAG TCK TDI TDO and TMS signa
95. an create up to ten trigger levels SignalTap II Logic Analyzer first evaluates the trigger patterns associated with trigger level 1 When the expression for trigger level 1 evaluates to TRUE SignalTap II Logic Analyzer evaluates the expression for trigger level 2 This process continues until all trigger levels have been processed and the final trigger level evaluates to TRUE The multiple trigger level feature can be used with Basic Triggers or Advanced Triggers You can configure the SignalTap II Logic Analyzer to use up to ten trigger levels Select the desired number of trigger levels in the Trigger Levels list You can disable the ability to trigger for a signal by turning off that trigger enable This option is useful when you only want to see captured data for a signal and are not using that signal as a trigger You can disable the ability to view data for signal by turning off the data enable column This option is useful when you want to trigger on a signal but do not care about viewing data for that signal Specifying the Trigger Position You can specify the amount of data that is acquired before the trigger event Select the desired ratio of pre trigger data to post trigger data by selecting one of the following ratios M Pre This selection saves signal activity that occurred after the trigger 12 pre trigger 88 post trigger Mm Center This selection saves 50 pre trigger and 50 post trigger data M Post This s
96. at fO F F RAM type F F M4K F F r Buffer acquisition mode _____ Circular 2 Pre trigger position ki Figure 9 23 STP File for the Third Device in the JTAG Chain Instance Manager A E Ready to acquire Q x JTAG Chain Configuration Tag ready Q Instance Status LEs 842 Memory 8192 auto_signaltap_0 Not running 842 cells 8192 bits ardware USB Blaster US 7 sf C trigger 20031248 17 07 50 1 Lock mode E Allow all changes v amp Signal Configuration Clock clock sl Data 000000000600 Sample depth Nodes allocated F F nst2 SHIFT_PB 63 oD Ww F _nst2 SHIFT_PB 62 m F 5 x au CMa nst2ISHFT_PBI6I 7 UR F RAM ype Nst2 SHIFT_PB 60 O Vv F Eg Mk nst2ISHIFT_PB 59 O F F nstASHFT_PE S8 7 F F E Buffer acquisition mode NSt2 SHIFT_PB 57 na F F fsa M Circular 2 Pre trigger position EI gt ee E Go Locating a Node in the Chip Editor Once you have found the source of a bug in your design using SignalTap II Logic Analyzer you can locate that signal in the Chip Editor Then you can change your design to correct the flaw that was found using SignalTap II Logic Analyzer To locate a signal from the SignalTap II Logic Analyzer in the Chip Editor right click on a signal in the STP file and select Locate in Chip Editor Altera Corporation 9 31 June 2004 Quartus II Handbook V
97. aths This option is turned on by default and cuts the register s clear and preset paths during timing analysis as shown in Figure 4 29 Altera Corporation June 2004 Quartus Il Timing Analysis Figure 4 29 Cut Off Clear and Preset Signal Paths i BRED i PERS i i i i PPN i align e __0 al o Ai NO CLRN inst Di o AND2 inst4 7 i PRN i o iD Q i cr i inse Ti AND2 I Ly inst3 The paths marked with arrows are cut from timing analysis when this setting is turned on Turn off Cut off clear and preset signal paths to include these paths in the timing analysis report Cut Off Read During Write Signal Paths This option is turned on by default and cuts the path from the write enable register through the embedded system block ESB to a destination register as shown in Figure 4 30 Figure 4 30 Cut Off Read During Write Signal Paths WE address 7 0 gt inclock Altera Corporation 4 29 June 2004 Quartus Il Handbook Volume 3 The path marked with an arrow between the we input to the memory block pram and the register inst 4 is not reported by the Timing Analyzer This path is reported if Cut off read during write signal paths is turned off Cut Paths Between Unrelated Clock Domains By default the Quartus II software cuts paths between unrelated clock
98. ation is a post place and route simulation to verify the operation of the design after the worst case timing delays have been calculated This section provides detailed instructions on how to perform gate level timing simulation in the ModelSim Altera software and highlights differences in performing similar steps in the Model Technology ModelSim software versions for VHDL and Verilog HDL designs Quartus Il Software Output Files for use in the ModelSim Altera Software To perform gate level timing simulation the ModelSim Altera software requires information on how the design was placed into device specific architectural blocks The Quartus II software provides this information in the form of vo for Verilog HDL and vho for VHDL output files The accompanying timing information is stored in the sdf file which annotates the delay for the elements found in the vo or vho output file To generate the VO or VHO output files perform the following steps 1 Choose EDA Tool Settings Assignments menu 2 Inthe Simulation Tool box a If you are using ModelSim Altera select ModelSim OEM VHDL Verilog HDL output from Quartus IT b If you are using Model Technology s ModelSim select ModelSim VHDL Verilog HDL output from Quartus IT 3 Click OK 1 11 Quartus II Handbook Volume 3 4 Compile the project 5 The Quartus II output files are located in the lt full path to project gt simulation ModelSim directory Gate Lev
99. ation of the SDO file in the Compiled SDF File Box and click OK 7 Click OK to save and exit the SDF Command File dialog box Add Signals to View If you want to add signals to view see the steps in Add Signals to View on page 3 15 Simulate Your Design Simulate your design using the ncsim program as described in Simulate Your Design on page 3 17 nco rp or ati n g Designers frequently use programming language interface PLI routines in Verilog HDL testbenches to perform user or design specific functions PLI Ro uti nes that are beyond the scope of the Verilog HDL language Cadence NC simulators include the PLI wizard which helps you incorporate your PLI routines For example if you are using a HEX file for memory you can convert it for use with NC tools using the Altera provided convert_hex2ver function However before you can use this function you must build it and place it in your project directory using the PLI wizard Altera Corporation 3 23 August 2004 Quartus Il Handbook Volume 3 3 24 This section describes how to dynamically link dynamically load and statically link a PLI library using the convert_hex2ver function as an example The following convert_hex2ver source files are located in the lt Quartus II installation gt eda cadence verilog x1 directory M convert hex2ver c E veriuser c M convert hex2ver obj Dynamically Link To create a PLI dynamic library so sl perform the f
100. ator Specify vhdl or verilog for the format quartus eda lt project name gt simulation on format lt format gt tool vcs Altera Corporation 2 11 June 2004 Quartus Il Handbook Volume 3 Conclusion You can use the VCS software in your Altera FPGA design flow easily and accurately perform simulations post synthesis simlulations gate level functional and timing simulations 2 12 Altera Corporation June 2004 3 Cadence NC Sim Support N DERYN qii53003 2 1 Introduction Software Requirements This chapter is a getting started guide to using the Cadence NC family of simulators in Altera FPGA design flows The NC family is comprised of the NC Sim NC Verilog NC VHDL Verilog and VHDL Desktop simulators This chapter provides step by step explanations of the basic NC Sim NC Verilog and NC VHDL functional and gate level timing simulations It also describes the location of the simulation libraries and how to automate simulations This document contains references to features available in the Altera Quartus II version 4 1 software See the Altera web site at www altera com for information on the Quartus II version 4 1 software You must first install the Quartus II software before using it with Cadence NC simulators The Quartus II Cadence interface is automatically installed when the Quartus II software is installed on your computer Table 3 1 shows which Cadence NC simulator version is compatible with
101. ble ASCII characters are represented by a period The color of the data changes in color as you perform reads and writes Data displayed in black indicates the data in the Hex Editor was the same as the data read from the device If the data in the Hex Editor changes color to red the data previously shown in the Hex Editor was different from the data read from the device 11 7 Running the In System Memory Content Editor 11 8 As you analyze the data you can use the cursor and the status bar to quickly identify the exact location in memory The status bar is located at the bottom of the In System Memory Content Editor and displays the selected instance name word position and the bit offset Figure 11 5 Figure 11 5 Status Bar in the In System Memory and Content Editor Instance 2 ACAC Word 0x000001 Bit 0x00000F The bit offset is the bit position of the cursor within the word In the following example a word is set to be 8 bits wide With the cursor in the position shown in Figure 11 7 the word location is 0x0000 and the bit position is 0x0007 Figure 11 6 Hex Editor Cursor Positioned at Bit 0x0003 qm 1 CNST 000000 BE With the cursor in the position shown in Figure 11 6 the word location remains 0x0000 but the bit position is 0x0003 Figure 11 7 Hex Editor Cursor Positioned at Bit 0x0007 sm 1 CNST 000000 AB Programming the Device Using t
102. book Volume 3 Figure 8 2 Available SignalProbe Sources in the Node Finder Node Finder xj Named fi z Filter SignalProbe Customize List g Look in fElock11 H M Include subentities Stop Cancel Nodes Found Unassigned Output Ss lt Block1 inst4 Unassigned Input Unassigned Combinato lt Unassigned Selected Nodes Registered lt lt Assigning 1 0 Standards Adding Registers for Pipelining 8 4 4 Click Add for a new SignalProbe pin or Click Change for an existing SignalProbe pin 5 Click OK The I O standard of each SignalProbe pin must be compatible with the I O bank the pin is in You can use the following two methods to assign I O standards for your SignalProbe pins 1 Click Assign SignalProbe Pins on the SignalProbe Settings page of the Settings dialog box Assignments menu select your SignalProbe output and select an I O standard from the I O standard list in the Assignment box in the Assign Pins dialog box 2 Choose Assignment Editor Assignments menu select I O Standard in the Category list type the SignalProbe pin name in the To column and select the I O standard in the I O Standard column of the spreadsheet You can specify the number of registers to be placed between a SignalProbe source and a SignalProbe pin to synchronize the data with respect to a clock and control the latency The SignalProbe incremental routing feat
103. by six inputs the LUT output is represented by a 64 bit binary number or a 16 digit hexadecimal number The following examples illustrate the use of the LUT Mask of an ALM Example 1 If the ALM implements a logical AND function in the top LUT using the DATAE and DATAF you will get the following LUT Mask 000000000000FFFF COMBOUT Equation DATAE amp DATAF Example 2 Altera Corporation June 2004 FPGA VO Elements If the ALM implements a logical XOR function in the top LUT using the DATAE and DATAF you will get the following LUT Mask 0000FFFFFFFF0000 COMBOUT Equation DATAE amp DATAF DATAF amp DATAE Extended LUT Mode When the extended LUT mode is used the ALM creates a specific set of seven input functions The Quartus IT software automatically recognizes the applicable 7 input function and fits them into an ALM The top and bottom LUTs are both a function of five inputs where four of the inputs are shared The other input of the ALM is used to control the MUX which selects which LUT is used to drive the COMBOUT port cS For more information on Extended Mode refer to the Stratix II Device Handbook Shared Arithmetic Mode When an ALM is in arithmetic mode it uses two sets of two four input LUTs along with two dedicated full adders The carry in signal that feeds the ALM drives adder0 The carry out from adder0 feeds the carry in of adder1 The carry out from adder1
104. c Analyzer in Your Design iii 9 2 Using the STP File to Create an Embedded Logic Analyzer iii 9 3 Using the MegaWizard Plug In Manager to Create your Embedded Logic Analyzer 9 8 Programming the Device for SignalTap II Analysis iii 9 12 View Data Samples criar cia Advanced Features Preserving FPGA Memory Creating Complex Triggers Using External Triggers Embedding Multiple Analyzers in One FPGA sise 9 20 Faster Compilations rail aes Time Bars and Next Transition Saving Captured Data i aaa Converting Captured Data to Other File Formats ui Creating Mnemonics for Bit Patterns Buffer Acquisition i Capturing Data to a Specific RAM Type FPGA Resources Used by SignalTap II Using SignalTap II in a Lab Environment Remote Debugging Using SignalTap II n Signal Preservation ciali ail Tappable Signals uc Ru ii illa Timing Preservation with SignalTap II Logic Analyzer Using SignalTap Il Logic Analyzer to Simultaneously Debug Multiple Designs 9 29 Locating a Node in the Chip Editor ari Design Example Preserving Timing ss Design Example Using SignalTap II Logic Analyzers in SOPC Builder Systems Conclusioni aaa lea Chapter 10 Design Analysis and Engineering Change Management
105. c Analyzer to monitor signals located inside a system module generated by SOPC Builder The system in this example contains many components including a Nios processor a DMA controller an on chip memory and an interface to external SDRAM memory In this example the Nios processor executes a simple C program from on chip memory and waits for a button push After a button is pushed the processor initiates a DMA transfer which you analyze using the SignalTap II Logic Analyzer For more information on this example see Application Note 323 Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems As the FPGA industry continues to make technological advancements outdated methodologies need to be replaced with a new set of technologies that maximize productivity The SignalTap II Logic Analyzer gives you the same benefits as a traditional logic analyzer without the many shortcomings of a piece of dedicated test equipment This version of SignalTap II Logic Analyzer provides many new and innovative features allowing you to capture and analyze internal signals in your FPGA thereby allowing you to find the source of a design flaw in the shortest amount of time 9 35 Quartus II Handbook Volume 3 9 36 Altera Corporation June 2004 N E RYN 10 Design Analysis and Engineering Change Management with Chip Editor qii53010 2 0 Introduction Background Altera Corporation June 2004 One of the toughest challen
106. calltf misctf Stfname forwref Vtool ErrMsg Example usertask 0 my check 0 my func my misctf my task XXX add user entries here This Handles Binary bit patterns usertask 0 0 0 convert hex2ver 0 Sconvert_hex2ver 1 0 final entry must be 0 return my_tfs 1 Run the PLI wizard by typing pliwiz at the command prompt or by selecting PLI Wizard Utilities menu in the NC Launch window 2 Inthe Config Session Name and Directory page type the name of the session in the Config Session Name box and type the directory in which the file should be built in the Config Session Directory box 3 Click Next 4 Inthe Select Simulator Dynamic Libraries page select the Dynamic Libraries Only option 5 Click Next 6 Inthe Select Components page turn on the PLI 1 0 Applications option select loadpli1 7 Click Next 8 Type in a name into the Bootstrap Function s box For example type inmy bootstrap into the Bootstrap Function s box 3 26 Altera Corporation August 2004 Incorporating PLI Routines 10 11 12 13 14 15 Type in a name into the Dynamic Library box The name entered will be the name of your generated dynamic library For example typein convert dyn lib into the Dynamic Library box to generate a dynamic library named convert_dyn_lib so In the PLI 1 0 Application page click browse under PLI Source Files to lo
107. cate the convert_hex2ver c file and the modified veriuser c file Click Next In the Select Compiler page choose your C compiler from the Select Compiler list box An example of a C compiler would be gcc To allow the PLIWIZ to find your C compiler ensure your Path variable is set correctly Click Next Click Finish When asked if you want to build your targets now click Yes Compilation generates your dynamic library cmd_file nc and cmd_file xl into your local directory The cmd_file nc and cmd_file xl files contain command line options that should be used with your newly generated dynamic library file Use the cmd_file nc command file with ncelab to perform your simulations ncelab worklib mylpmrom FILE cmd file nc Use the cmd_file xl1 command file with verilog xl or neverilog to perform you simulations ncverilog f cmd file xl verilog f cmd file xl Altera Corporation August 2004 3 27 Quartus Il Handbook Volume 3 3 28 Statically Link To statically link the PLI library with NC Sim perform the following steps IL 9 10 Run the PLI wizard by typing pliwiz at the command prompt or by selecting PLI Wizard Utilities menu in the NC Launch window In the Config Session Name and Directory page type the name of the session in the Config Session Name box and type the directory in which the file should be built in the Config Session Directory box Click Next Select NC Simulators and
108. ch Select OK in the Simulate dialog box vsim work lt my_testbench gt Running the Simulation 1 Choose Signals and Wave View menu view signals view wave 2 Drag signals to monitor from the Signals window and drop them into the Wave window add wave lt signal name gt 3 At the prompt type the following run lt time period gt Simulating Verilog Designs The following instructions provide step by step instructions on performing functional RTL simulation for Verilog designs in the ModelSim Altera software Ls The following steps assume you have already created a ModelSim project Quartus II Handbook Volume 3 Create Simulation Libraries DS Creating a simulation library is not required for the ModelSim Altera software Simulation libraries are needed to properly simulate a design that contains an LPM function or an Altera megafunction If you are using the Model Technology ModelSim software version you need to create the simulation libraries and correctly link them to your design 1 2 Choose New gt Library File menu In the Create a New Library dialog box select a new Library and a logical linking to it Enter the name of the newly created library in the Library Name box Click OK vlib altera mf vmap altera mf altera mf vlib lpme vmap lpm lpm LE The name of the libraries should be altera _ mf for Altera megafunctions and 1pm for LPM and Megawizard generated enti
109. cification verifying that the RTL code performs the correct functionality verifying that the fitted design satisfies the design s timing constraints and ends with successfully programming the targeted FPGA Unfortunately similar to most difficult processes the ideal design flow rarely occurs Often you find bugs in the RTL code or worse the design specifications change midway through the design cycle The challenge lies in efficiently accommodating these types of design issues Traditionally you have to go back to the source RTL code make the appropriate changes and then go through the entire design flow again With the Altera Chip Editor you can significantly shorten the design cycle time and ultimately the time to market for your product You can make changes directly to the post place and route netlist generate a new programming file and test the revised design without ever modifying the RIL code Figure 10 1 describes how the Chip Editor can be used in your design flow Altera Corporation June 2004 Chip Editor Overview Figure 10 1 Chip Editor Design Flow Design Specification Design Entry Synthesis Place amp Route PCB Implementation Chi p Editor The Chip Editor contains many advanced features that enable you to quickly and efficiently make design changes The Chip Editor s Overview integrated tool set provides the following f
110. computer must have a connected Altera programming hardware for example USB Blaster or ByteBlaster 2 On the local PC install the full version of the Quartus II software This local PC must be connected to the remote PC across a LAN with the TCP IP protocol Software Setup Remote PC 1 Select Hardware Setup from the Quartus II programmer 2 Select the JTAG Settings tab See Figure 9 16 3 Click the Configure local JTAG server button Figure 9 16 Configure Hardware Settings x Hardware Settings JTAG Settings Specify JTAG servers to add and remove from the JTAG Servers list Spec y the password used by remote clients to access the local JTAG server by configuring your local JTAG server m JTAG Servers Add Server Server ConnecionStaus OK Server Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer 4 In the Configure Local JTAG Server dialog box see Figure 9 17 turn on Enable remote clients to connect to the local JTAG server and type in your password Type your password again in the Confirm Password box and click OK Figure 9 17 Configure Local JTAG Server Configure Local JTAG Server A x IV Enable remote clients to connect to the local JTAG server Password Pg Confirm Password OK Cancel Software Setup Local PC 1 Launch the Quartus II programmer 2 Click Hardware Setup 3 Click the JTAG setting
111. cquisition Clock You must assign a clock signal to control the acquisition of data by the SignalTap II Logic Analyzer The acquisition clock samples data on every rising edge You can use any signal in your design as the acquisition clock For best results Altera recommends using a global clock not a gated clock Using a gated clock as your acquisition clock may result in unexpected data that does not accurately reflect your design The Quartus II Timing Analyzer displays the maximum acquisition clock frequency To assign an acquisition clock perform the following steps 1 Inthe SignalTap II Logic Analyzer window click the Setup tab 2 Click Browse next to the Clock list to open the Node Finder p Select SignalTap II pre synthesis in the Filter list 4 Inthe Named box enter the name of the signal that you would like to use as your sample clock Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer 8 9 To start the node search click List In the Nodes Found list select the node representing the design s global clock signal To copy the selected node name to the Selected Nodes list click ae Click OK The node is now specified as the clock in the SignalTap II window If you do not assign an acquisition clock in the SignalTap II window the Quartus II software automatically creates a clock pin called auto stp external clk You must make a pin assignment
112. cro tco Data Delay Micro tsy Figure 4 4 shows a slack calculation diagram Figure 4 4 Slack Calculation Diagram Slack i Clock Period Launching Edge ni clk1 clk2 Capturing Edge Combinatorial Logic Register 1 Register 2 t t ae Data C Lou clki P clk2 lt Data Delay Hold Time Slack Hold time slack is the margin by which the minimum hold time requirement is met or not met for a register to register path Figure 4 5 Data is required to remain stable after the rising edge of a destination register s clock for at least the time equal to the micro hold time of the destination register The primary cause of a hold time violation is excessive clock skew B A As long as the data delay is greater than clock skew B A no hold time violation occurs Since the Quartus II software only reports hold time slack for paths that have hold time violations only negative slacks are reported Altera Corporation June 2004 Quartus Il Timing Analysis Figure 4 5 Hold Time Slack Clkatregi uta OK X X Clk at reg2 l tco l i data i ar Clock skew is B A a Reg 1 Reg 2 i B A t CO hold i hold lt gt es
113. ctory and any design specific libraries e g for Altera LPM functions or megafunctions 3 Compile source code and testbenches You compile your design files at the command line using ncvlog Verilog HDL files or ncvhdl VHDL files or by using the GUI During compilation the NC software performs syntax and static semantic checks If no errors are found compilation produces an internal representation for each HDL design unit in the source files By default these intermediate objects are stored in a single packed library database file in your working directory 4 Elaborate your design Before you can simulate your model the design hierarchy must be defined in a process called elaboration Use ncelab in command line mode or choose Elaborator Tools menu in GUI mode to elaborate the design 5 Add signals to your waveform Before simulating specify which signals to view in your waveform using a simulation history manager SHM database 6 Simulate your design Run the simulator with the nesim program command line mode or by clicking Run in the SimVision Console window 3 4 Altera Corporation August 2004 Functional RTL Simulation Fu neti ona RTL The following sections provide detailed instructions for performing functional RTL simulation using the Quartus II software and Cadence Simulation NC tools Set Up Your Environment This section describes how to set up your working environment for the Quartus II N
114. d on the timestamp that shows when the data was acquired It is a good idea to rename the data log with a more meaningful name The logs are organized in a hierarchical manner similar logs of captured data are grouped together in trigger sets To enable data logging turn on the Data Log option To recall a data log for a given trigger set and make it active double click on the name of the data log in the list c This feature is useful for organizing different sets of trigger conditions and different sets of signal configurations Converting Captured Data to Other File Formats You can export captured data in the following industry standard file formats some of which can be used with other EDA simulation tools Comma Separated Values csv File Table tbl File Value Change Dump vcd File Vector Waveform File vwf Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Altera Corporation June 2004 To export SignalTap II Logic Analyzer s captured data choose Export File menu and select the File Name the Export Format and the Clock Period Creating Mnemonics for Bit Patterns The mnemonic table feature allows you to assign a meaningful name to a set of bit patterns To create a mnemonic table right click in the Setup view of an STP file and select Mnemonic Setup To assign a group of signals to a mnemonic value right click on the group and select Bus Display Setup B
115. e Stratix II Architecture chapter in Volume 1 of the Stratix II Device Handbook For a detailed description of the Cyclone device I O element see the Cyclone Architecture chapter in Volume 1 of the Cyclone Device Handbook For a detailed description of the MAX II device I O element see the MAX II Architecture chapter in the MAX II Device Handbook Supported Changes for an 1 0 Element Table 10 4 shows which operations are supported by the different device families Table 10 4 Supported Operations for an 1 0 Element Operation Stratix Stratix GX Stratix Il Cyclone MAX Il View the I O elements in the Resource Y Y 7 7 Y Property Editor Edit properties of the I O elements Y 7 VA Vv Placement changes the I O elements v V4 VA Y Create new I O elements Y 7 7 Y 10 18 Altera Corporation June 2004 FPGA I O Elements Altera Corporation June 2004 Editable Properties of 1 0 Elements Stratix and Stratix GX Properties You can use the Resource Property Editor to modify the following properties of Stratix and Stratix GX device I O cells Bus Hold Weak Pull Up Slow Slew Rate Open Drain I O Standard Current Strength Extend OE Disable PCI I O On Chip Termination Input Register Mode Input Register Reset Mode Input Register Synchronous Reset Mode Input Powers Up Output Register Mode Output Register Reset Mode Output Register Synchronous Reset Mode Output Powers Up OE
116. e Debug Port Edit menu If you want to rename the debugging port pin type the new name in the Out column The default signal name for the debugging ports is auto stp debug out lt m gt lt n gt where m refers to the instance number and n refers to the signal number 3 Manually assign the debugging port signal name to an unused I O pin 9 13 Quartus II Handbook Volume 3 9 14 Creating Complex Triggers The most crucial feature of an analyzer is the triggering capability If you do not have the ability to create a trigger condition that allows you to capture relevant data your logic analyzer may not help you debug your design With the SignalTap II Logic Analyzer you can build very complex triggers that allow you to capture data when a set of trigger conditions exist Advanced triggers are built with a simple graphical interface You can drag and drop operators into the Advanced Trigger window to build the complex trigger condition in an expression tree The operators that you can use are listed in Table 9 2 Table 9 2 Advanced Triggering Operators Note 1 Name of Operator Type Less Than Comparison Less Than or Equal To Comparison Equality Comparison Inequality Comparison Greater Than Comparison Greater Than or Equal To Comparison Logical NOT Logical Logical AND Logical Logical OR Logical Logical XOR Logical Reduction AND Reduction Reduction
117. e SwiteheS roseira aieiaiee e enean ra a aaa Using VirSim The VCS Graphical Interface VCS Debugging Support VCS Command Line Interface iiii 2 9 Using PLI Routines with the VCS Software sn Preparing amp Linking C Programs to Verilog Code Scripting SUppo t iiiiii aaa Generating a Post Synthesis Simulation Netlist for VCS ss Generating a Gate Level Timing Simulation Netlist for VCS Conclusioni ira aa Chapter 3 Cadence NC Sim Support Introduetioni infa nine iaia ee eR ES Software Requirements Simulation Flow Overview iiiiiiisiieeeneensensennesnnesnnesneseeseennsenneesneennesnennenee Functional RTL Simulation Gate Level Timing Simulation Op ration Mod s ssh rca Quartus II NC Simulation Flow Overview 3 4 Functional RTL Simulation Set Up Your Environment seisis iaia Create Libraries ila EE RTE ATA Simulating a Design with Memory Compile Source Code amp Testbenches Elaborate Your Design Add Signals to View Simulate Your Design Gate Level Timing Simulation Quartus II Simulation Output Files Quartus II Timing Simulation Libraries ss Set Up Your Environment LA De NE 2 2 LE atea ra Compile the Project Files amp Libraries i i iii Elaborate the Design Add Signals to View Simulate Your Design ca Incorporating PLI Routines Dynamically Link 110 IGOR aaa Dy
118. e Timing Closure Floorplan Last Compilation Floorplan Node Finder or Chip Editor and select Locate in Resource Property Editor from the menu Quartus Il Handbook Volume 3 For a detailed description of the LE for a particular device family refer to the Handbook or data sheet for the device family Figure 10 8 Stratix LE Architecture 2 m TEGTASTI i 10 10 The Adaptive Logic Module ALM The basic building block of logic in the Stratix II architecture is the Adaptive Logic Module see Figure 10 9 The ALM provides advanced features with efficient logic utilization Each ALM contains a variety of LUT based resources that can be divided between two adaptive LUTs ALUTs With up to eight inputs to the two ALUTs each ALM can implement various combinations of two functions This adaptability allows the ALM to be completely backward compatible with four input LUT architectures One ALM can also implement any function with up to six inputs and certain seven input functions In addition to the adaptive LUT based resources each ALM contains two programmable registers two dedicated full adders a carry chain a shared arithmetic chain and a register chain Through these dedicated resources the ALM can efficiently implement various arithmetic functions and shift registers You can view any ALM in a Stratix II device with the Resource Property Editor To
119. e correct library vlog work stratixii lt quartus installation folder eda sim_lib startixii_atoms v gt Compile Testbench and VO into Work Library 1 Select Compile All Compile menu or click the Compile All toolbar icon 2 Resolve any compile time errors before proceeding to Loading the Design vlog work work lt my_testbench v gt lt my_verilog_output_file vo gt Loading the Design 1 Select Simulate Simulate menu 2 Inthe Load Design dialog box click the Libraries tab 3 In the Search Libraries box click Add 4 Specify the location to the gate level simulation library US If you are using the ModelSim Altera version refer to Tables 1 5 and 1 6 for the location of the precompiled simulation libraries Ly If you are using the ModelSim Modeltech version browse to the library that was created earlier 5 Inthe Load Design dialog box click the Design tab 6 Expand the work library in the Simulate dialog box 7 Select the top level design unit your testbench and select OK in the Simulate dialog box vsim L lt location of the gate level simulation library gt work lt my_testbench gt Running the Simulation 1 Choose Signals and Wave View menu Altera Corporation June 2004 Using the NativeLink Feature with ModelSim Using the NativeLink Feature with ModelSim Altera Corporation June 2004 view signals view wave 2 Drag signals to monitor from the Signals window and drop th
120. e memory blocks with the Quartus II MegaWizard Plug In Manager which can be initialized with power up data via a hexidecimal hex or Memory Initialization File mif The 1pm file parameter included in the MegaWizard generated file points to the path of the HEX file or MIF that is used to initialize the memory block You can create a HEX file or MIF through the Quartus II software However the VCS software cannot read a HEX file or MIF format Therefore in order to perform functional simulation of Altera memory blocks in the VCS software you must perform the following steps 1 Convert a HEX file or MIF to a RAM Initialization File rif 2 3 Quartus II Handbook Volume 3 2 4 2 Modify the MegaWizard generated file 3 Compile the nopli v file For more information on creating a MIF see Quartus II Help Converting a HEX File or MIF to a RIF A RIF is an ASCII text file that you can use with tools from electronic design automation EDA vendors You can create a RIF by converting an existing MIF or HEX file using the Export Current File As command in the Quartus II software This option is available through the File menu while the Quartus II memory editor is open Modifying the MegaWizard Generated File You must modify the MegaWizard generated file so that it includes the path to the newly created RIF You must modify the 1pm file parameter The following example shows the entry that you must change
121. e minimum length of time that data must be stable before the active clock edge Figure 4 1 shows a diagram of clock setup time Quartus Il Handbook Volume 3 Figure 4 1 Clock Setup Time tsy Data Delay Micro toy data a 0078 Clock Delay Micro tsy is the internal setup time of the register i e it is a characteristic of the register and is unaffected by the signals feeding the register The following equation calculates the tsy of the circuit shown in Figure 4 1 tsy Data Delay Clock Delay Micro tsy Clock Hold Time ty Data that feeds a register via its data or enable inputs must be held at an input pin after the register s clock signal is asserted at the clock pin Clock hold time is the minimum length of time that this data must be stable after the active clock edge Figure 4 2 shows a diagram of clock hold time Figure 4 2 Clock Hold Time ty Data Delay Micro ty gt 6 0 vis TO Clock Delay Micro ty is the internal hold time of the register The following equation calculates the ty of the circuit shown in Figure 4 2 ty Clock Delay Data Delay Micro ty 4 2 Altera Corporation June 2004 Quartus Il Timing Analysis Altera Corporation June 2004 Clock to Output Delay tco Clock to output delay is the maximum time required to obtain a valid output at an output pin fed by a register after a clock transitio
122. e options they modify Elaboration GUI Mode To elaborate using the GUI perform the following steps 1 Expand your current working library in the right panel 2 Select and open the entity module name you want to elaborate 3 Right click the view you want to display 4 Choose NCElab The Elaborate dialog box opens Or you can choose Elaborator from the Tools menu 5 Set the simulation timescale using the command TIMESCALE lt arguments gt under Other Options See Figure 3 4 Figure 3 4 Elaborating the Design Design Unit _1 Snapshot Name D Work Library Ri Error Limit _ Update if needed W Access Visibility Other Options Overwrite log file ncelab log 1 Executable Filename Elaborate worklib Ipramtest lib cell view 15 Default ncelab TIMESCALE 1ps 1pg Advanced Options Cancel Apply 6 Click OK in the Elaborate dialog box to begin elaboration The dialog box closes and returns you to NCLaunch Altera Corporation August 2004 Functional RTL Simulation Add Signals to View You use a SHM database which is a Cadence proprietary waveform database to store the selected signals you want to view Before you can specify which signals to view you must create this database by adding commands to your code Alternately you can create a Value Change Dump File vcd to store the simulation history For more infor
123. e the report timing command and all related options E help Entering this command at the pt_ shell prompt lists all the commands available in the pt_shell E quit Entering this command at the pt_shell prompt closes the pt_shell You can also activate pt_shell without a script file by entering pt_shell at the UNIX command line prompt The Quartus II generated netlist constraints and timing information can be exported into the PrimeTime environment seamlessly PrimeTime can be used to do worst case and best case timing analysis just as in the Quartus II software PrimeTime timing reports show any violations and slacks Altera Corporation June 2004 Section Ill Power JN DTS RYA Estimation amp Analysis Revision History Altera Corporation As FPGA designs grow larger and processes continue to shrink power becomes an ever increasing concern When designing a printed circuit board the power consumed by a device needs to be accurately estimated to develop an appropriate power budget and to design the power supplies voltage regulators heat sink and cooling system The Quartus II software allows you to estimate the power consumed by your current design during timing simulation The power consumption of your design can be calculated using the Microsoft Excel based power calculator or the Simulation Based Power Estimation features in the Quartus II software This section explains how to use both This section includ
124. eatures Altera Corporation 10 3 June 2004 Quartus Il Handbook Volume 3 10 4 Mm Chip Editor Floorplan Allows you to examine FPGA resources used by your design M Resource Property Editor Allows you make modifications to your post place and route design E Change Manager Allows you to track all design changes Chip Editor Floorplan The Chip Editor allows you to quickly and easily view post compilation placement and routing information You can start the Chip Editor in any of the following ways Choose Chip Editor Tools menu Right button pop up menu from the Compilation Report Right button pop up menu from the RTL source code Right button pop up menu from the Timing Closure Floorplan Right button pop up menu from the Node Finder Right button pop up menu from the Simulation Report The Chip Editor uses a hierarchical zoom viewer that shows various abstraction levels of the targeted Altera device As you increase the zoom level the level of abstraction decreases thus revealing more detail about your design Table 10 1 gives a summary of the Chip Editor features These features are easily accessible from the Chip Editor Toolbar Table 10 1 Chip Editor Floorplan Features Feature Description Birds Eye View Gives a high level picture of resource usage at the chip level allows you to specify which elements of the Chip Editor are displayed and assists you in rapidly navigating the floorplan Fan I
125. ect Check amp Save All Netlist Changes You have now manually retimed your system to meet the tco requirements for one of the four failing paths You must perform the same procedure on the other three paths to ensure the entire system meets the timing requirements Once the other paths are fixed you can run the 10 32 Altera Corporation June 2004 Example Design Meeting I O Timing Altera Corporation June 2004 Quartus II Timing Analyzer to verify the timing results and the Quartus II Simulator or another EDA tool vendor s simulator to verify the functionality of the design Table 10 8 describes the Timing Analysis report after the changes have been made Table 10 8 Timing Analysis Report After Changes Have Been Made Slack Required tco Actual tco From To From CLK 0 405 ns 7 000 ns 6 595 ns Outff a 14 Out Clk Running the Quartus Il Timing Analyzer After you have made a change with the Chip Editor you should perform timing analysis of your design with the Quartus II Timing Analyzer to ensure that your changes have not adversely affected your design s timing performance For example when you enable one of the delay chain settings for a specific pin you change the I O timing Therefore to ensure that all timing requirements are still met you need to perform timing analysis Once you make a change to your design using the Chip Editor you should perform timing simulation on your de
126. ect Create COMBOUT 10 30 Connect COMBOUT of outff_a 9 to DATA input of xx 0 190 To perform this step you must perform a Check amp Save All Netlist Changes from the Change Manager to ensure that the newly created COMBOUT port for outff_a 9 appears in the Node Finder a Right click in the Change Manager and select Check amp Save All Netlist Changes b Open the Resource Property Editor for xx 0 190 c Right click on the DATA port of xx 0 190 and select Edit Connections In the Edit Connections dialog box find the COMBOUT port outff_a 9 with the Node Finder Altera Corporation June 2004 Example Design Meeting I O Timing We have now removed the register from outff_a 9 and created a COMBOUT connection to xx 0 190 The next step is to create the register in Create the a Right xx 0 190 register in xx 0 190 click on the CLK port and select Edit Connections In the Edit Connections dialog box type in clk the name of the system clock in the design b Right click on the REGOUT port and select Create REGOUT see Figure 10 21 Figure 10 21 Select Create REGOUT ac ald gt amp Altera Corporation June 2004 Remove connection between COMBOUT of xx 0 190 and DATAIN of out a Right click on the COMBOUT of xx 0 190 and select Go To Destination atom out b
127. ed functional models The following commands shows examples of each Verilog HDL ncvlog WORK lpm 220model v ncvlog WORK altera mf altera mf v If your design also uses a memory initialization file compile the nopli v file which is located in the lt Quartus II installation gt eda sim lib directory before you compile your model For example ncvlog WORK lpm nopli v 220model v ncvlog WORK altera mf nopli v altera mf v Or use the NO_PLI command during compilation ncvlog DEFINE NO PLI 1 WORK lpm 220model v ncvlog DEFINE NO_PLI 1 WORK altera mf altera mf v ha VHDL ncvhdl V93 WORK lpm 220pack vhd ncvhdl V93 WORK lpm 220model vhd ncvhdl V93 WORK altera mf altera mf components vhd ncvhdl V93 WORK altera mf altera mf vhd 3 11 Quartus Il Handbook Volume 3 Compilation GUI Mode To compile using the GUI perform the following steps 1 Right click a library filename in the NCLaunch window 2 Choose NCVlog Verilog HDL or NCVhdl VHDL The Compile Verilog or Compile VHDL dialog boxes open as shown in Figure 3 3 Alternatively you can choose NC Vlog or NCVhdl Tools menu Figure 3 3 Compiling Verilog HDL amp VHDL Files M Error Limit 1514 M Update if needed M Enable line debug 1 Define Macro J Include Directories a _j Other Options Advanced Options File File f M Work Library fworkiio Work Libra
128. either ModelSim software version can directly read a HEX file or MIF format Therefore to allow functional simulation of Altera memory blocks in the ModelSim software you must perform the following steps 1 Convert a HEX file or MIF to a RAM Initialization File rif 2 Modify of the MegaWizard generated file 3 Compile the nopli v file Converting a HEX File or MIF to a RIF A RIF is an ASCII text file that you use with tools from electronic design automation EDA vendors Create a RIF by converting an existing MIF or HEX file using the Export command in the Quartus II software This option is available through the File menu Modifying the MegaWizard Generated File You must modify the MegaWizard generated file so that it includes the path to the newly created RIF You must modify the LPM_FILE parameter The following example shows the entry that you must change Altera Corporation June 2004 Gate Level Timing Simulation Gate Level Timing Simulation Altera Corporation June 2004 lpm ram dp component lpm outdata UNREGISTERED lpm ram dp component lpm file lt path to RIF gt lpm ram dp component use eab ON Compiling nopli v The nopli v file is included in the s lt path to Quartus II installation gt eda sim lib directory This file contains the following definition define NO PLI 1 This basic definition instructs the ModelSim compile to read in the RIF Gate level timing simul
129. el Simulation Libraries Table 1 5 provides a description of the various ModelSim Altera precompiled device libraries Table 1 5 Various ModelSim Altera Precompiled Device Libraries Library Description maxii Precompiled library for MAX II devices stratixii Precompiled library for Stratix Il devices stratix Precompiled library for Stratix device designs stratixgx Precompiled library for Stratix GX device designs stratixgx_gxb Precompiled library for Stratix GX device designs using the Gigabit Transceiver Block altgxb Megafunction cyclone Precompiled library for Cyclone device designs apexii Precompiled library for APEX Il device designs apex20k Precompiled library for APEX 20K device designs apex20ke Precompiled library for APEX 20KC APEX 20KE devices and ARM based Excalibur designs mercury Precompiled library for Mercury device designs flex10ke Precompiled library for FLEX 10KE and ACEX 1K device designs flex6000 Precompiled library for FLEX 6000 device designs max Precompiled library for MAX 7000 and MAX 3000 device designs Table 1 6 shows the location of the timing simulation libraries in the ModelSim Altera software for Verilog HDL for PCs Table 1 6 Location of Timing Simulation Libraries for ModelSim Altera for Verilog HDL on a PC Part 1 of 2 Library Verilog HDL maxii lt ModelSim Altera installation directory gt alter
130. el View Resource LC_X1_Y22 NO Node Idmuxreglregcen reg_gldataout 6 Third Level View Figure 10 7 shows the level of detail at the third and lowest level At this level you can see within the FPGA You can see each routing resource that is used with a LAB You also have the ability to move LEs and I Os from one physical location to another You can move a resource by selecting dragging and dropping it into the desired location At this level you also have the ability to create new LEs and I Os To create a resource right mouse click at the location you want to create the resource and select Create Atom Altera Corporation June 2004 Resource Property Editor Figure 10 7 Chip Editor s Third Level View Resource Property Editor Altera Corporation June 2004 You can view the following elements with the Resource Property Editor E LEs E ALMs E I O elements E PLIs The Logic Element LE An Altera logic element contains a four input LUT which is a function generator that can implement any function of four variables In addition each LE contains a register that can be fed by the output of the LUT or by an independent function generated in a separate LE Figure 10 8 shows what the LE looks like in the Resource Property Editor Any LE that is placed in the FPGA can be viewed and edited using the Resource Property Editor To launch the Resource Property Editor for an LE right mouse click on an LE in th
131. election saves signal activity that occurred before the trigger 88 pre trigger 12 post trigger Mm Continuous This selection saves signal activity indefinitely until stopped manually After you configure the STP file you must compile it with your Quartus II project before you can use it to analyze your design 9 7 Quartus Il Handbook Volume 3 Compiling Your Design with SignalTap Il Logic Analyzer The first time you create and save an STP file the Quartus II software automatically adds the file to your project However you can add an STP file manually by performing the following steps 1 Choose Settings Assignments menu 2 Inthe Category list select SignalTap II Logic Analyzer 3 Turn on Enable SignalTap II Logic Analyzer 4 Inthe SignalTap II File Name box type the name of the STP file you want to compile or select a file name with Browse 5 Click OK sox To begin the compilation select Start Compilation Processing menu c When you compile your design with an STP file the sld_signaltap and sld_hub entities are added in the compilation hierarchy These two entities are the main components of the SignalTap II Logic Analyzer Using the MegaWizard Plug In Manager to Create your Embedded Logic Analyzer Alternatively you can create a SignalTap II Logic Analyzer by using the MegaWizard Plug In Manager If you use this method you do not need to create an STP file and include it in your Quartus II
132. em into the Wave window add wave lt signal name gt 3 At the prompt type the following run lt time period gt The NativeLink feature in the Quartus II software facilitates the seamless transfer of information between the Quartus II software and EDA tools and allows you to run ModelSim within the Quartus II software To run an EDA simulation or timing analysis tool automatically after a compilation in the Quartus II software 1 Select EDA Tool Settings Assignments menu and set the Simulation Tool Name to one of the following ModelSim Verilog Output from Quartus IT ModelSim VHDL Output from Quartus II ModelSim Altera Verilog Output from Quartus II ModelSim Altera VHDL Output from Quartus II gt Make sure you turn on Run this tool automatically after compilation in the Simulation page under EDA Tool Settings in the Settings dialog box Assignments menu 2 Compile the design The Quartus II software creates a simulation work directory compiles the appropriate design files and simulation libraries and launches the EDA simulation tool UNIX workstations only to run ModelSim automatically from the Quartus II software using the NativeLink feature you must add the following environment variables to your cshrc QUARTUS INI PATH lt ModelSim installation directory gt 1 19 Quartus II Handbook Volume 3 Software Licensing amp Licensing Set Up Conclusion 1 20 License the ModelSim Al
133. es the following chapters m Chapter 6 Early Power Estimation m Chapter 7 Simulation Based Power Estimation The table below shows the revision history for Chapters 6 and 7 Chapter s Date Version Changes Made 6 June 2004 v2 0 Updates to tables figures e New functionality for Quartus 4 1 Feb 2004 v1 0 Initial release 7 June 2004 v2 0 Updates to tables figures e New functionality for Quartus 4 1 Feb 2004 v1 0 Initial release Section III 1 Power Estimation amp Analysis Quartus Il Handbook Volume 3 Section III 2 Altera Corporation N DTE RYA 6 Early Power Estimation qii53006 2 0 Introduction Excel Based Power Calculator Altera Corporation June 2004 As designs grow larger and processes continue to shrink power becomes an ever increasing concern When designing a printed circuit board PCB the power consumed by a device needs to be accurately estimated to develop an appropriate power budget and to design the power supplies voltage regulators heat sink and cooling system Stratix Stratix GX and Cyclone device power consumption can be calculated using the Microsoft Excel Excel based power calculator or the Simulation Based Power Estimation feature in the the Quartus II software which is described in the Simulation Based Power Estimation chapter in Volume 3 of the Quartus II Handbook You can use the Excel based power calculator du
134. esis Settings Fitter Settings Timing Analyzer Design Assistant SignalT ap Il Logic Analyzer SignalProbe Settings Simulator Software Build Settings Stratix GX Registration HardCopy Settings Specify options for generating output files for use with other EDA tools HDL output from Quartus I TT Run this tool aut Time scale 1 ps v Reset gt Map ilegal VHDL characters this option creates VHDL 1987 complient names TT Map illegal Verilog HDL characters TT Truncate long hierarchy paths TT Flatten buses into individual nodes TT Output Excalibur stripe as a single module Bavaneed BA H This section describes the three files that the Quartus II software creates for the PrimeTime tool M lt project_name gt vo or lt project_name gt vho files This is the netlist file written in either Verilog vo or VHDL vho format depending on the format selected in the EDA settings This file contains the flat netlist representing the entire design M lt project_name gt _v sdo or lt project_name gt _vhd sdo files These files contain the timing information for each timing arc in the design Like the netlist files these files are written in either Verilog _v or VHDL _vhd format depending on the selection made in the EDA settings This file corresponds to the worst case delay values of the timing arcs if regular timing analysis is performed in the Quartus II software
135. et quartus root appsl altera quartus II 3 0 set search path list quartus root appsl altera quartus II13 0 eda synopsys primetime lib set link path list stratix_asynch_io_lib db stratix io register lib db stratix lvds receiver lib db stratix asynch lcell lib db stratix lvds transmitter lib db stratix core mem lib db stratix lcell register lib db stratix mac out internal lib db stratix mac mult internal lib db stratix mac register lib db stratix memory register lib db stratix pll lib db alt vtl db read verilog stratix all pt v This Tcl file also contains equivalent constraints in PrimeTime format converted automatically by the Quartus II software from constraints in Quartus II format Additional PrimeTime commands can be placed in the Tcl file to report on or analyze timing paths This Tcl file also has a command to read the SDO file generated by the Quartus II software Depending on which SDO file is desired either with best case or worst case delays the appropriate SDO file name should be specified 5 3 Quartus II Handbook Volume 3 Sample of Constraints Specified in PrimeTime Format PrimeTime Timing Reports 5 4 The PrimeTime constraints shown in Table 5 1 are automatically generated by the Quartus II software The set input delay max command is equivalent to the tsy constraint in the Quartus II software Since input _delayinPrimeTime is defined as the data delay from clock edge to the input pin
136. f your signals and you are now ready to simulate your testbench design Figure 3 7 Selecting Signals in the Design Browser Window 0 x File Edit View Select Explore Simulation Windows Help Sie Br gt Na A N He ED A D yq Timed 0 ns 5 p Search Times Value a4 DR Y 0 Simulation Time 0 0 Browse All Available Data Signals variables of scope simulator accum 7 219 Sa simulator Signal Variable Value ii accum ii ipm add sub_component iF o De Copy Sendto Souce Browser LU Send to Schematic Tracer Send to new Break on Change Create Force Release Force Deposit Value Create Probe Describe Leaf Filter B gt F ED Je Filter i li 4 objects selected Simulate Your Design After you have compiled and elaborated your design you can simulate using ncsim The ncsim program loads the ncelab generated snapshot as its primary input It then loads other intermediate objects referenced by the snapshot If you enable interactive debugging it may also load HDL 3 17 Quartus Il Handbook Volume 3 Gate Level Timing Simulation 3 18 source files and script files The simulation output is controlled by the model or debugger The output can include result files generated by the model SHM database or VCD Functional RTL Simulation Command Line Mode To perform functional RTL simulation of y
137. fv_lib prims v SETUP gt fapps2 home users schandra fv_lib mfs_hssi_bbox v 4A SETUP gt read design apps2 home users schandra design_examples ip_designs mi2c mi2c_syn vqm Verilog Gc SETUP gt read design apps2 home users schandra design_examples ip_designs mi2c mi2c vqm Verilog Revise Read VERILOG design successfully To investigate verification results click the Mapping Manager icon in the toolbar or choose Mapping Manager Tools menu The Incisive Conformal software reports the mapped unmapped and compared 12 10 points in the Mapped Points Unmapped Points and Compared Points windows respectively For more information on how to diagnose non equivalent points refer to the user documentation for the Incisive Conformal software Altera Corporation June 2004 Known Issues amp Limitations Known Issues amp The following known issues and limitations may be encountered when dp ye using the formal verification flow described in this chapter Limitations Mm Unused logic optimized within a black box by the Quartus II software can result in an interface different from the interface in the synthesized VOM netlist M In designs with combinational feedback loops the Incisive Conformal software may incorrectly insert extra unmapped cut points in the revised netlist Concl usion Formal verification software enables verification of the design during all stages from RTL to place
138. g Y option Y Altera Corporation June 2004 Quartus II Handbook Volume 3 Table 1 1 Comparison of ModelSim Versions Part 2 of 2 Verilog PLI 1 support Interfaces Verilog 7 7 7 designs to customer C code and third party software VHDL FLI 2 support Interfaces VHDL 7 designs to customer C code and third party software Advanced debugging features and language V4 neutral licensing Customizable user expandable graphical user interface GUI and integrated simulation performance analyzer Integrated code coverage analysis and SWIFT support Accelerated VITAL 3 and Verilog primitives 3 times faster and register transfer level RTL acceleration 5 times faster Platform support PC UNIX Linux PC only PC UNIX Linux Note to Table 1 1 1 See www altera com products software pld products partners eda ms html Software Table 1 2 shows which specific ModelSim Altera software version is page compatible with the specific Quartus IT software version ModelSim Co mpati bil ity versions provided directly from Model Technology do not correspond to specific Quartus II software versions For help on ModelSim Altera licensing set up see Software Licensing amp Licensing Set Up on page 1 20 Table 1 2 Compatibility Between Software Versions ModelSim Altera Software Quartus Il Software 7 ModelSim Altera software version 5 7c Quartus
139. g menu Enable the Generate Netlist for Functional Simulation Only Choose Settings Assignments menu In the Category list select EDA Tool Settings expand if necessary gt Simulation In the Simulation section of the window choose VCS in the Tool name list as shown in Figure 2 2 Figure 2 2 Setting the Tool Name to VCS in the Settings Window Settings ddr2_sdram Category General Files User Libraries Device Timing Requirements amp Options EDA Tool Settings Design Entry amp Synthesis Simulation Timing Analysis Board Level Formal Verification Resynthesis Compilation Process Analysis amp Synthesis Settings VHDL Input Verilog HDL Input Default Parameters Synthesis Netlist Optimizations Fitter Settings Physical Synthesis Optimizations Timing Analyzer Design Assistant SignalT ap Il Logic Analyzer SignalProbe Settings Simulator Software Build Settings Stratix GX Registration HardCopy Settings Specify options for generating output files for use with other EDA tools xl Tool name VCS z iasi NC Verilog Verilog HDL output from Quartus II SP I ESNC vHDL VHDL output from Quartus II Scirocco VHDL output from Quartus II Custom Verilog HDL T Truncat Custom VHDL TT Flatten buses into individual nodes TT Output Excalibur stripe as a single module IT Generate Power Input File TT Bring out device wide set reset signals as ports TT Maintain hierarchy TT Generate netlist for f
140. g topics E Formal verification M Setting up the Quartus II software to generate the VOM file and Incisive Conformal script E Comparing designs using Incisive Conformal software E Known issues and limitations Formal verification uses exhaustive mathematical techniques to verify design functionality There are two types of formal verification equivalence checking and model checking This chapter discusses equivalence checking cS The formal verification flow can be used for designs targeting the Cyclone Stratix GX and Stratix device families Equivalence Checking Equivalence checking is used to compare the functional equivalence of the original design with the revised design by using mathematical techniques rather than by performing simulation using test vectors greatly decreasing the time to verify the design Altera supports formal verification of the post synthesis netlist from Synplify and Synplify Pro and the post place and route netlist from Quartus II software as shown in Figure 12 1 12 1 Quartus II Handbook Volume 3 Figure 12 1 Formal Verification Flow Using Synplify amp Incisive Conformal Software Synplicity Synplify vhd Software V Synthesis Yy Golden Netlist vqm iaia Formal Verificatic y Library Conformal LEC Software Quartus Il Software Equivalence Place amp Route Checking A Vv Revised Netlist vam AANA Gene
141. g vhdl gt altgxb 4 The ATGXB library files require the LPM and SGATE libraries To set up a library for LPM functions create a new directory and add the following line to your cds lib file DEFINE lpm lt path gt lt directory name gt To set up a library for Altera Megafunctions add the following line to your cds lib file DEFINE altera_mf lt path gt lt directory name gt Altera Corporation 3 9 August 2004 Quartus Il Handbook Volume 3 Simulating a Design with Memory Many Altera functional models 220model v and altera_mf v use a memory file which is a Hexadecimal Intel Format File hex or a Memory Initialization File mif However NC tools cannot read a HEX or MIF Perform the following steps to convert these files into a format the tools can read 1 Convert your HEX or MIF into a RAM Initialization File rif by performing the following steps in the Quartus II software US You can also use the hex2rif exe and mif2rif exe programs located in the lt Quartus II installation directory gt bin directory to convert the files at the command line Use the option to view their usage a Open the HEX or MIF file b Choose Export File menu c Ifnecessary in the Export dialog box select a target directory in the Save in list d Select a file to overwrite in the Files list or type the file name in the File name box e If necessary in the Save as type list select RAM Initialization File r
142. ges that FPGA designers must face is implementing incremental engineering change orders ECOs late in the design cycle while maintaining timing closure With the Quartus II software s new Chip Editor you can view the internal structure of Altera devices and incrementally edit device resource functionality and parameter settings The Chip Editor can also help you document and manage ECOs The Chip Editor works directly on design netlists so you can implement device changes in minutes without performing a design compilation Changes are restricted to a particular device resource to maintain timing closure in the remaining portions of the design Design rule checks are performed on all changes to prevent you from making illegal edits This chapter describes how to use the Chip Editor and includes coverage of the following topics Mm Chip editor floorplan M Resource property editor Mm Common applications With the Chip Editor you can view the following architecture specific information related to your design E FPGA routing resources used by your design For example you can visually examine how blocks are physically connected as well as the signal routing that connects the blocks Mm LE utilization information You can view how a logic element LE is configured within your design For example you can view which LE inputs are used if the LE utilizes the register or the look up table LUT or both as well as the signal flow through
143. get quick access to internal design signals to perform system level debugging Altera Corporation June 2004 9 Design Debugging Using JNO E RYA the SignalTap Il Embedded Logic Analyzer qii53009 2 0 Introduction Altera Corporation June 2004 Debugging today s FPGA designs can be a difficult task As your design continues to increase in complexity the time and money you invest in verifying your design continues to rise To get your product to market as quickly as possible you must minimize the design verification time To help alleviate the time to market pressure you need a set of verification tools that are powerful and easy to use The Altera SignalTap II Logic Analyzer can be used to evaluate the state of the signals in your Altera FPGA helping you to quickly find the cause of design flaws in your system The SignalTap II Logic Analyzer in the Quartus II software is non intrusive scalable easy to use and free with your Quartus II subscription This logic analyzer helps you debug your FPGA design by allowing you to probe the state of the internal signals in your design It is equipped with many new and innovative features allowing you to find the source of a design flaw in a short amount of time Figure 9 1 shows the SignalTap II Logic Analyzer block diagram Figure 9 1 SignalTap Il Logic Analyzer Block Diagram SignalTap 11 ELA oO HELE e CREER HI ao SignalTap Il ELA TE amp Stratix
144. he icon next to the Snapshots directory to expand it b Right click the lib cell view you want to simulate and choose NC Sim right button pop up menu c Click OK in the Simulate dialog box After you load the design the SimVision Console and SimVision Design Browser windows appear as shown in Figure 3 5 and Figure 3 6 Figure 3 5 SimVision Console fm console simvision o File Edit Simulation Windows Help F ex Cl 5 nm Simulation Time 0 0 nesim gt source tools cadence LDY51 tools inca files ncsimre nesim gt SimVision Figure 3 6 SimVision Design Browser EB Design Browser 1 SimVision E 101 x Fie Edt View Select Explore S eip ulation Windows Hel a as SOS Es DIECI BH simao Time e Browse Al Avalabie Data teste 2 SE Re fa mo RM nef a 3 16 Altera Corporation August 2004 Functional RTL Simulation Altera Corporation August 2004 2 Inthe Design Browser window select a module in the left panel and select the signals you want to view in the waveform by selecting the signal names in the Signals Variable list 3 To send the selected signals to the Waveform Viewer Select the Send to Waveform Viewer icon in the Send To area the upper right area of the Design Browser window or Choose the Send to Waveform Window item in the right mouse click menu as shown in Figure 3 7 A waveform window appears with all o
145. he Excel based power calculator you can edit the power calculator to reflect the device resource estimates for the final design For more information about how to generate the power estimation file in the Quartus II software see Quartus IIT Power Report File on page 6 6 For more information about how use the Import Data macro to import the power estimation file information into the Excel based power calculator see the Estimating Power in Stratix Stratix GX and Cyclone Devices User Guide Altera Corporation June 2004 Estimating Power in the Design Cycle Table 6 2 shows the power estimation flow for the Excel based power calculator when the FPGA design is partially complete Table 6 2 Power Estimation When FPGA Design Is Partially Complete Steps to Follow in the Quartus Il software 1 Compile the partial FPGA design Power Estimation can be done early Accuracy is dependent on user Advantages Disadvantages in the FPGA design cycle input and estimate of the final File in the Quartus Il software 2 Generate the Power Estimation design device resources Provides the flexibility to 3 Download the Excel based calculator from the Altera website compilation in the Quartus Il automatically fill the power power calculator based on results of 4 Run the import data macro automatically populate the Ex based power calculator to software cel design 5 Optionally edits to
146. he In System Memory Content Editor If you make changes to your design you can program the device from within the In System Memory Content Editor To program the device follow these steps 1 Choose In System Memory Content Editor Tools menu 2 Inthe JTAG Chain Configuration panel of the In System Memory Content Editor select the SOF file that includes the modifiable memories and constants Altera Corporation August 2004 In System Updating of Memory amp Constants Conclusion Altera Corporation August 2004 3 Click Scan Chain 4 In the Device list select the device you want to program 5 Click Program Device The In System Updating of Memory and Constants feature and In System Memory Content Editor provides access into a device for efficient debug in a hardware lab You can use In System Memory Updating of Memory and Constants with SignalTap II to maximize the visibility into an Altera FPGA The more visibility and access to the internal logic of the device that you have the quicker problems can be identified and resolved 11 9 Conclusion 11 10 Altera Corporation August 2004 Section V Formal AND E RYA Verification Revision History Altera Corporation The Quartus II software easily interfaces with EDA formal design verification tools such as the Cadence Incisive Conformal and Synplicity Synplify software In addition the Quartus II software has built in support for verifying the l
147. he maximum clock speed However it does not check design functionality and should be used together with simulation to verify the overall design operation The Quartus II software provides the features necessary to perform advanced timing analysis for today s system on a programmable chip SOPC designs During compilation the Quartus II software automatically performs timing analysis so that you don t have to launch a separate timing analysis tool after each successful compilation The Quartus II Timing Analyzer reports timing analysis results in the compilation reports giving you immediate access to this data This chapter explains the basic principles of static timing analysis and the advanced features supported by the Quartus II Timing Analyzer using TCL scripts and the Quartus II graphical user interface GUI A comprehensive timing analysis involves observing the setup times hold times clock to output delays maximum clock frequencies and slack times for the design With this information you can validate circuit performance and detect possible timing violations Undetected timing violations could result in incorrect circuit operation This section describes the basic timing analysis measurements used by the Quartus II Timing Analyzer Clock Setup Time tsy Data that feeds a register s data or enable inputs must arrive at the input pin before the register s clock signal is asserted at the clock pin Clock setup time is th
148. he new features in the Chip Editor allow you to perform gate level register retiming to optimize the timing of your design The overall effect of using the Chip Editor shortens the verification cycle and brings timing closure to your design in a shorter period of time Altera Corporation June 2004 11 In System Updating of JNO E RYA n Memory amp Constants Overview Altera Corporation August 2004 FPGA designs are growing larger in density and are becoming more complex Designers and verification engineers require more access to the design that is programmed in the device to quickly identify test and resolve issues The in system updating of memory and constants capability of the Quartus II software provides read and write access to in system FPGA memories and constants through the JTAG interface making it easier to test changes to memory contents This chapter explains how to use the Quartus II In System Memory Content Editor as part of your FPGA design and verification flow The ability to update memory and constants in a programmed device provides more insight into and control over your design The Quartus II In System Memory Content Editor gives you access to device memories and constants When used in conjunction with the SignalTap II logic analyzer this feature provides you the visibility required to debug your design in the hardware lab For more information on SignalTap II see the Design Debugging Using the S
149. hese options depends on the current device family To enable the Assign SignalProbe Pins button a specific target device needs to be selected in the Device page FN Automatically route SignalProbe signals during compilation T Modify latest fitting results during SignalProbe compilation Assign SignalProbe Pins 8 6 To run a SignalProbe compilation manually after a full compilation choose Start SignalProbe Compilation Processing menu Is You must run the Fitter before a SignalProbe compilation The Fitter generates a list of all internal nodes that can be used as SignalProbe sources You can enable and disable each SignalProbe pin by turning on and off the SignalProbe enable option in the Assignment box in the Assign SignalProbe Pins dialog box You can also enable or disable all Altera Corporation June 2004 Running SignalProbe with Smart Compilation Running SignalProbe with Smart Compilation Understanding SignalProbe Routing Failures Altera Corporation June 2004 SignalProbe pins by clicking Enable All SignalProbe Routing and Disable All SignalProbe Routing respectively in the Assignment box in the Assign SignalProbe Pins dialog box The Enable All SignalProbe Routing and Disable All SignalProbe Routing options are disabled until you turn on Show current and potential SignalProbe pins in the Assign SignalProbe Pins dialog box Smart compilation reduces compilation times by running only
150. his technique the total clock insertion delay for each register is computed from the input reference clock pin including the PLL offset At the end each register name its associated clock name and the the total clock network delay w r t the input clock pin for each register is printed Altera Corporation June 2004 Quartus Il Timing Analysis out Being able to print out clock insertion delays for each register in the design helps figure out minimum and maximum clock skews between different clock domains even when more than one PLLs are involved Conclusion Evolving design and aggressive process technologies require larger and higher performance FPGA designs Increasing design complexity demands enhanced timing analysis tools that aid designers in verifying design timing requirements Without advanced timing analysis tools you risk circuit failure in complex designs The Quartus II Timing Analyzer incorporates a set of powerful timing analysis features that are critical in enabling system on a programmable chip designs Altera Corporation 4 37 June 2004 Quartus II Handbook Volume 3 4 38 Altera Corporation June 2004 5 Synopsys PrimeTime JN OTS RYA m Support qii53005 2 0 introduction PrimeTime is an industry standard sign off tool used to perform static timing analysis on most ASIC designs The Quartus II software provides a path to enable users to run PrimeTime on their Quartus designs exporting netlist co
151. hoose Import Data from File in the Instance Manager The file data overwrites the data displayed at the chosen location in the Hex Editor After reading data from in system memory export it to a file by right mouse clicking the instance in the Instance Manager or the data in the Hex Editor and choosing Export Data to File You can export data to HEX MIF Value Change Dump ved or RAM Initialization file rif format Viewing Memory amp Constants in the Hex Editor For each instance of an in system memory or constant the Hex Editor displays data in hexadecimal numbers and ASCII characters if the word size is a multiple of 8 bits The arrangement of the hexadecimal numbers depends on the dimensions of the memory For example if the word width is 16 bits the Hex Editor displays data in columns of words that contain columns of bytes Figure 11 4 Figure 11 4 Editing 16 bit Memory Words Using the Hex Editor Index Instance ID Status Not running Not running Not running EEE Instance Manager t 3 M EL HET E x JTAG Chain Configuration JTAG ready 2 Mode RAM ROM Read v Hardware ByteBlasterM LPT1 Constant T pesa S RAM ROM A 1 EP1C20 0x020840DD Scan Chain 000000 00 EE 00000B 00 00 000016 00 00 s CNST 000000 EE mm2 ACAC 000000 000008 OO AB 000016 00 96 Instance 2 ACAC Word 0x000001 Bit 0x00000F Altera Corporation August 2004 Unprinta
152. hould include a Simulation based power estimation The power estimation provides an accurate way to estimate the power consumed by your design because it is based on the simulation stimuli that reflects the actual design behavior In addition to providing design verification the Simulator supports simulation based power estimation for Stratix Stratix GX Cyclone HardCopy Stratix MAX 7000AE MAX 7000B and MAX 3000A devices Since simulation typically happens later in the design cycle simulation based power estimation is generally used to verify the power consumption of a device already on board However simulation based power estimation is also a useful tool to estimate power in portions of a larger design when integrating smaller designs into larger FPGAs The device power consumption can be estimated before the simulation stage To use the power estimation feature you must provide a Vector Waveform File vwf or Power Input File pwf to the Quartus II Simulator and perform a timing simulation For more information about how to perform an early power estimation of your design see the Early Power Estimation chapter in Volume 3 of the Quartus II Handbook This chapter explains how to use the simulation based power estimation feature in the Quartus II software to estimate device power consumption gt Itis important to remember that these results should only be used as an estimation of power not as a specification The
153. ibpli so libpli dll for PCs which is your PLI dynamic library in your session directory When you elaborate your design the elaborator looks through the path specified in the LD LIBRARY PATH UNIX or PATH PCs environment variable searches for the so dll file and loads them when needed L gt You must modify LD_LIBRARY_PATH or PATH to include the directory location of your so dll file Dynamically Load To create a PLI library to be loaded with NC Sim perform the following steps 1 Modify the veriuser c file located in the following directory lt Quartus II installation gt eda cadence verilog x1l The following two examples are sections of the original and modified veriuser c file Original veriuser c packaged with the Quartus Il software s_tfcell veriusertfs Template for an entry usertask userfunction data checktf sizetf calltf misctf Stfname forwref Vtool ErrMsg Example usertask 0 my check 0 my func my misctf my task XXX add user entries here This Handles Binary bit patterns 3 25 Quartus Il Handbook Volume 3 usertask 0 0 0 convert hex2ver 0 convert hex2ver 1 0 final entry must be 0 Modified veriuser c for dynamic loading p_tfcell my bootstrap static s_tfcell my tfs s_tfcell veriusertfs Template for an entry usertask userfunction data checktf sizetf
154. if f Click Export 2 Using a text editor modify the 1pm_ file parameter in the megafunction s wizard generated file to point to the RIF Alternatively you can rerun the wizard and point to the RIF as the memory initialization file The following example shows the entry that you must change lpm ram dp component lpm outdata UNREGISTERED lpm ram dp component lpm file lt path to RIF gt lpm ram dp component use eab ON 3 10 Altera Corporation August 2004 Functional RTL Simulation Altera Corporation August 2004 Compile Source Code amp Testhenches When using NC simulators you compile files with ncvlog for Verilog HDL files or ncvhdl for VHDL files Both ncvlog and ncvhdl perform syntax checks and static semantic checks If no errors are found compilation produces an internal representation for each HDL design unit in the source files By default these intermediate objects are stored in a single packed library database file in your working library directory Compilation Command Line Mode To compile from the command line use one of the following commands You must specify a work directory before compiling Verilog HDL ncvlog lt options gt work lt library name gt lt design files gt VHDL nevhdl lt options gt work lt library name gt lt design files gt If your design uses LPM or Altera megafunctions you also need to compile the Altera provid
155. ign at lt project directory gt fv conformal blackboxes The script file contains the setup constraints to be used along with the formal verification tool Following is the sample setup constraints generated by the Quartus II software add renaming rule rl al revised add renaming rule r2 a golden add renaming rule r3 a revised 12 7 Quartus Il Handbook Volume 3 Comparing Designs Using Incisive Conformal Software 12 8 add ignored inputs data b 3 data b 2 data b 1 address b 3 address b 2 address b 1 module altsyncram width a8 widthad a7 revised set mapping method unreach set mapping method phase The file lt entity gt v in the blackboxes directory contains the module description of only those entities that are not defined in the formal verification library For example if there is a reference to a black box for an instance of the altdpram megafunction in the design the blackboxes directory does not contain a module description for the altdpram megafunction as it is defined in the altdpram v file of the formal verification library This section discusses using the Incisive Conformal software to compare designs Black Boxes in the Incisive Conformal Flow A module must be treated as a black box by the Incisive Conformal software if the corresponding formal verification model is not available As discussed in Generating the VO File amp Incisive Conformal
156. ignalTap II Embedded Logic Analyzer chapter of the Quartus II Handbook The ability to read data from memories and constants allows you to quickly identify the source of problems In addition the write capabilities allow you to bypass functional issues by writing expected data For example if a parity bit in your memory is incorrect you can use the In System Content Editor to write the correct parity bit values into your RAM allowing your system to continue functioning You can also intentionally write incorrect parity bit values into your RAMs to check your design s error handling functionality 11 1 Device amp Megafunction Support Device amp Megafunction Support The following tables list the devices and types of memories and constants that are currently supported by the Quartus II software version 4 1 Table 11 2 lists the types of memory supported by the MegaWizard Plug In Manager and the In System Memory Content Editor Table 11 1 MegaWizard Plug In Manager Support Installed Plug Ins Category Megafunction Name Gates LPM_CONSTANT Memory Compiler RAM 1 PORT ROM 1 PORT Storage ALTSYNCRAM LPM_RAM DQ LPM_ROM Table 11 2 lists support for in system updating of memory and constants for the APEX 20K APEX II Mercury Stratix and Cyclone device families Table 11 2 Supported Megafunctions Stratix Stratix Strat
157. imation Select options for power estimation Power estimation period Start time oo ns End time ns z Cancel 7 After the timing simulation is performed the estimated power consumption for your design is reported in the Summary section of the Simulation Report The Simulator Reports the Total Power which is the sum total of Total Internal Power and the Total I O power The internal power includes the internal standby power and dynamic power In the example shown in Figure 7 3 the M4K RAM and the clocktree components contribute to the dynamic power consumed by the design Altera Corporation 7 3 June 2004 Quartus Il Handbook Volume 3 Estimating Power with EDA Simulation Tools 7 4 Figure 7 3 Simulator Summary 9 Simulation Report Simulator Summary SE Legal Notice i Type Value SEI Flow Summary Simulation Start Time Ops ES Flow Settings Simulation End Time 10 0us ses Simulator Simulation Netlist Size 120212 nodes sE Simulator Summary Simulation Coverage 0 25 EE Simulator Settings S Simulation Waveforms 5 Total Number of Transitions 42416 I Logical Memories 6 Power estimation start time Ops SEB Simulator INI Usage Power estimation end time 10 0 us Total Internal Power 235 49 mw Total Standby Intemal Power 105 00 mw Total M4K RAM Internal Power 4 26 mw Total Clocktree Internal Power 126 23 mw i Simulator Messages
158. imulator T Maintain hierarchy Software Build Settings TT Generate netlist for functional simulation only Stratix GX Registration HardCopy Settings ica 5 Compile the design in the Quartus II software 6 Perform a timing simulation with the other EDA simulation tool The simulation tool generates the PWF file and places it in the project directory 7 Inthe Quartus II software choose Settings Assignment menu 8 Inthe Settings dialog box under the Category list open Fitter Settings and select Simulator 9 Inthe Simulator window select Timing in the Simulation mode list Altera Corporation 7 5 June 2004 Quartus II Handbook Volume 3 7 6 10 Specify the PWF file in the Simulation input box see Figure 7 5 You can browse to the appropriate PWF file by clicking the Browse button Figure 7 5 Simulator Settings Dialog Box Settings standard x Category General Files User Libraries Select options for simulations Device Timing Requirements amp Options RR 1 Fig EDA Tool Settings sosie Ti Design Entry amp Synthesis Simulation input i m Simulation Timing Analysis r Simulation period Board Level Bun simulation until all vector stimuli are used Formal Verification Resynthesis End simulation at rs z Compilation Process E Analysis amp Synthesis Settings nous E Fitter Settings Timing
159. in the source code 2 8 Altera Corporation June 2004 Using VirSim The VCS Graphical Interface Table 2 4 Device Family Library Files Library y lt library directory gt Description Specifies a Verilog library directory The VCS software looks for library files in this folder that contain module definitions that are instantiated in the source code compsdf Indicates that the VCS compiler includes the back annotated SDF file in the compilation cli After successful completion of compilation Command Line Interface CLI Mode is entered race Specifies that the VCS software generate a report that indicates all of the race conditions in the design Default report name is race out P Compiles user defined Programming Language Interface PLI table files q Indicates the VCS software runs in quiet mode All messages are suppressed Using VirSim The VCS Graphical Interface VCS Debugging Support VCS Command Line Interface Altera Corporation June 2004 For more information on any VCS switch refer to the VCS User Guide VirSim is the graphical debugging system for the VCS software This tool is included with the VCS software and can be invoked by using the I compile time switch when compiling a design The following VCS command describes the command line syntax for compiling and loading a timing simulation in VirSim ves RI lt test bench gt v lt design name gt
160. inimum timing settings to pins and registers in your design Performing Minimum Timing Analysis To perform minimum timing analysis with the best case timing models delay models choose Start gt Start Minimum Timing Analysis Processing menu If you use the quartus tan command line executable specify the min option The following tcl example will read the project netlist and generate a Minimum timing report Quartus tan min lt project_name gt Altera Corporation 4 33 June 2004 Quartus Il Handbook Volume 3 Third Party Timing Analysis Software Advanced Timing Analysis amp Reports Using Tcl Scripts 4 34 Minimum Timing Analysis Reporting You can examine the results of minimum timing analysis in the Timing section of the compilation report in the Quartus IT GUI The text based report generated during timing analysis is called lt project name gt tan rpt The same name is used is used for the report file generated during regular timing analysis so that previous timing analysis results is overwritten Even when you perform regular worst case timing analysis there can be reports in the Timing Analysis section of the compilation report listing minimum delay checks These results are generated by reporting the minimum delay checks using the worst case timing models delay models You can also use the PrimeTime software to perform timing analysis Select PrimeTime as the Timing Analysis tool in the Timing Analy
161. involves moving registers to balance the combinational delay across a data path while preserving the overall functionality of the circuit Figure 10 15 illustrates this point 10 24 Altera Corporation June 2004 Common Applications Figure 10 15 Gate Level Register Retiming Diagram Vo For information on how Quartus II Physical Synthesis can automatically perform gate level retiming without altering functionality see the Netlist Optimizations and Physical Synthesis chapter in Volume 2 of the Quartus II Handbook Figure 10 16 shows a design with unbalanced combinational delay To balance the logic on either side of the combinational logic follow the steps listed below Figure 10 16 Combinational Logic Before Using Chip Editor LE1 LUT LE2 LUT LE3 LUT LE4 LUT lt a D gt p gt DD gt o __ gt gt gt gt gt REGOUT COMBOUT COMBOUT COMBOUT Vv 1 Create a new LE using the Chip Editor LE NEW 2 Connect the COMBOUT port of LE2 to the DATAIN port of LE NEW 3 Connect the REGOUT port of LE NEW to the input of LE3 Figure 10 17 shows the design with balanced combinational delay Altera Corporation 10 25 June 2004 Quartus Il Handbook Volume 3 Figure 10 17 Combinational L
162. is shown in Figure 4 12 Figure 4 12 Derived Clocks Example 2 411 ns P DEFE G DEL i ye O PRN A PRN i PRN D G D ali HD a iB ims CLAN i CLRN i cLRN 7 141 ns Altera Corporation 4 13 June 2004 Quartus Il Handbook Volume 3 4 14 In Figure 4 12 the longest clock path is 7 141 ns from clock_a to destination register inst 4 The shortest clock path is 1 847 ns from clock a to the source register inst 5 This creates a clock skew of 5 294 ns The shortest register to register data path between the source and destination register is 2 411 ns The micro hold delay of the destination register is 0 710 ns Thus the clock skew is longer than the data path 5 294 ns gt 2 411 ns This results in incorrect circuit functionality To remove the clock skew error path B must be lengthened so that it is longer than the clock skew This is achieved by adding cells to the path or through the placement of the source and destination registers Asynchronous Memory With asynchronous memory the memory element acts as a latch and you must check the setup and hold time on the latch An example is shown in Figure 4 13 The longest clock path from c1k6 to destination memory is 9 251 ns The shortest clock path from c1k6 to source register is 2 302 ns Thus the largest clock skew is 6 949 ns
163. ix MegaFunction APEX 20K APEX II Mercury M512 M4K MegaRAM Cyclone blocks blocks blocks LPM CONSTANT Read Read Read Write Read Read Read Read Write Write Write Write Write Write LPM_ROM Write Read Read Write Write Read N A Read Write Write Write LPM RAM DQ N A 7 Read Read Write Read Read Read Read Write Write Write Write Write ALTSYNCRAM N A N A N A N A Read Read Read ROM Write Write Write ALTSYNCRAM N A N A N A Read Read Read Read Single Port RAM Write Write Write Write Mode Note to Table 11 2 1 Only write only mode is applicable for this single port RAM In read only mode use LPM_ROM instead of LPM RAM DO 11 2 Altera Corporation August 2004 In System Updating of Memory amp Constants Using In System Updating of Memory amp Constants with Your Design Creating In System Configurable Memory and Constants Altera Corporation August 2004 Using the In System Updating of Memory and Constants feature requires the following steps 1 Identify the memories and constants that you want to access 2 Edit the memories and constants to be run time configurable 3 Perform a full compilation 4 Program your device When you enable a memory or constant to be run time configurable the Quartus II software changes the default implementation A single port RAM is converted to dual port RAM and a constant is implemented in registers instead of look up tables LUTs
164. ixii lt ModelSim Altera installation directory gt modeltech altera verilog stratixii stratix lt ModelSim Altera installation directory gt modeltech altera verilog stratix stratixgx lt ModelSim Altera installation directory gt modeltech altera verilog stratixgx stratixgx_gxb lt ModelSim Altera installation directory gt modeltech altera verilog stratixgx_gxb cyclone lt ModelSim Altera installation directory gt modeltech altera verilog cyclone apexii lt ModelSim Altera installation directory gt modeltech altera verilog apexii apex20k lt ModelSim Altera installation directory gt modeltech altera verilog apex20k apex20ke lt ModelSim Altera installation directory gt modeltech altera verilog apex20ke mercury lt ModelSim Altera installation directory gt modeltech altera verilog mercury flex10ke lt ModelSim Altera installation directory gt modeltech altera verilog flex10ke flex6000 lt ModelSim Altera installation directory gt modeltech altera verilog flex6000 max lt ModelSim Altera installation directory gt modeltech altera verilog max Table 1 9 shows the location of the timing simulation libraries in the ModelSim Altera software for VHDL for UNIX Table 1 9 Location of Timing Simulation Libraries for ModelSim Altera for VHDL with UNIX Part 1 of 2 Library VHDL maxii lt ModelSim Altera installation directory gt modeltech altera vhdl maxii stratixii lt ModelSim
165. k domain need a sample depth of 1K you can create two instances to meet these needs To create multiple analyzers select Create Instance Edit menu or right click in the Instance Manager window and select Create Instance US You can start all instances at the same time by clicking Run on the SignalTap II toolbar Faster Compilations The incremental routing feature allows you to add new nodes to your STP file without having to perform a full recompilation Adding these new nodes to your STP file does not affect the existing placement and routing of your design Before using the SignalTap II incremental routing feature you must perform the following steps 1 Set the number of nodes allocated 2 Select any nodes reserved for incremental routing Set the Number of Nodes Allocated Before you can fully utilize the incremental routing feature you must first select Manual under Nodes allocated as shown in Figure 9 13 and enter a value that includes the number of nodes you currently want to analyze plus any extra nodes you may want to incrementally route later in the verification process The extra allocated nodes act as place holders for nodes that you will add later Setting Nodes Allocated to Auto causes the Quartus II software to build the SignalTap II Logic Analyzer to accommodate only the number of channels that were selected in the STP file Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded
166. k borders CRLEREL LL LIL bet El The Bird s Eye View is displayed as a separate window that is linked to the Chip Editor When you select an area of interest in the Bird s Eye View the Chip Editor automatically refreshes the window as necessary to display the selected area in greater detail in accordance with whatever zoom factor is in effect For example when you zoom in or zoom out in the Bird s Eye View window the main Chip Editor window will also zoom in or zoom out You have the option of setting the amount of detail that you see when you use the zoom in feature To adjust the default values specify the appropriate values on the Chip Editor page of the Options dialog box Tools menu 10 5 Quartus Il Handbook Volume 3 10 6 The Bird s Eye View is particularly useful when the parts of your design that you are interested in are at opposite ends of the chip and you want to quickly navigate between resource elements without losing your frame of reference First Highest Level View The first highest zoom level provides a high level view of the entire device floorplan This view provides a similar level of detail as the Quartus II Timing Closure floorplan You can easily locate and view the placement of any node in your design Figure 10 3 shows the Chip Editor s first level view Figure 10 3 Chip Editor s First Highest Level View Altera
167. k pins that supply the design s clock signals Upon successful compilation the Quartus II Timing Analyzer automatically verifies circuit operability 4 15 Quartus II Handbook Volume 3 Multicycle Assignments Multicycle paths are paths between registers that intentionally require more than one clock cycle to become stable For example a register may need to trigger a signal on every second or third rising clock edge Figure 4 14 shows an example of a design with a multicycle path between the multiplier s input registers and output register Figure 4 14 Example Diagram of a Multicycle Path lt D Q id D Q ni ENA D x I D Q e ENA UE ENA 2 cycles Multicycle Assignment A Multicycle assignment specifies the number of clock cycles required before a register should latch a value Multicycle assignments delay the latch edge relaxing the required setup relationship Figure 4 15 shows a timing diagram for a multicycle path that exists in a design with related clocks with a small offset between the clocks 4 16 Altera Corporation June 2004 Quartus Il Timing Analysis Figure 4 15 Multicycle Paths with Offset Between Clocks Due to the offset the Timing Analyzer uses these two edges for setup checks by default
168. l De TETE ali o E al RIR H D EI a p m gt gt p aT E p gt al E AT D p Oa cer ET o Io RE o Ea Fan la L gt ce H Figure 10 11 shows the Stratix II I O element structure Figure 10 11 Stratix Il Device 1 0 Element a DI GT D a gt core 1 A o o a a ee E GEEET TI Al OE D EI a ZII H o E o D al H OH a ama oi IDATA D ET ol D E al D a 17 gt A a A NCIEENA 10 16 Altera Corporation June 2004 FPGA I O Elements Cyclone 1 0 Elements The I O element in Cyclone device contain a bidirectional I O buffer and three registers for complete bidirectional single data rate transfer Figure 10 12 shows the Cyclone I O element structure The I O element contains one input register one output register and one output enable register Figure 10 12 Cyclone Device 1 0 Elemnent MAX II 1 0s MAX II device I O elements contain a bidirectional I O buffer Figure 10 13 shows the MAX II I O element structure Registers from adjacent LABs can drive to or be driven from the I O element s bidirectional I O buffers Altera Corporation 10 17 June 2004 Quartus Il Handbook Volume 3 Figure 10 13 MAX Il Device 1 0 Elemnent For a detailed description of the Stratix device I O element see the Stratix Architecture chapter in Volume 1 of the Stratix Device Handbook For a detailed description of the Stratix II device I O element see th
169. l source The analyzer can also be operated in the trigger output configuration in which it supplies an external signal to trigger other devices These features allow you to synchronize the internal Logic Analyzer with external logic analysis equipment Trigger In To use Trigger In perform the following steps 1 In the SignalTap II window click the Setup tab 2 Inthe Signal Configuration window turn on Trigger In 3 Inthe Pattern pull down list select the condition you would like to act as your trigger event 4 Click on the Browse button next to the Trigger In When the Node Finder window appears select an input pin in your design by setting the Trigger In source Trigger Out To use Trigger Out perform the following steps 1 In the SignalTap II window click the Setup tab 9 17 Quartus II Handbook Volume 3 9 18 2 Inthe Signal Configuration window turn on Trigger Out 3 In the Level list select the condition you would like to signify that the trigger event is occurring 4 Click Browse next to the Trigger Out When the Node Finder window appears select an output pin in your design Using the Trigger Out of One Analyzer as the Trigger In of Another Analyzer One advanced feature of the SignalTap II Logic Analyzer is the ability to use the Trigger Out of one analyzer as the Trigger In to another analyzer This feature allows you to synchronize and debug events that occur across multiple clock do
170. lSim Altera lt ModelSim Altera installation directory gt altera lt HDL gt altera_mf PC ModelSim Altera lt ModelSim Altera installation directory gt modeltech altera lt HDL gt altera_mf UNIX Note to Table 1 4 1 For Model Technology s ModelSim use the files provided with the Quartus II software Simulating VHDL Designs The following instructions will help you to perform a functional RTL simulation for VHDL designs in the ModelSim Altera software c The following steps assume you have already created a ModelSim project Fa Creating a simulation library is not required if you are using the ModelSim Altera software Create Simulation Libraries IL Altera Corporation June 2004 Quartus Il Handbook Volume 3 Simulation libraries are needed to simulate a design that contains an LPM function or an Altera megafunction If you are using the Model Technology ModelSim software version you need to create the simulation libraries and correctly link them to your design 1 Choose New gt Library File menu 2 Inthe Create a New Library dialog box select a new Library and a logical linking to it 3 Enter the name of the newly created library in the Library Name box 4 Click OK vlib altera mf vmap altera mf altera mf vlib lpmt vmap lpm lpm Ls The name of the libraries should be altera_mf for Altera megafunctions and 1pm for LPM and Megawizard generated entities Compile Si
171. le assignments the Timing Analyzer sets the Default Multicycle Hold setting to the value of the Multicycle setting 4 20 Altera Corporation June 2004 Quartus Il Timing Analysis Figure 4 19 Timing Analysis Setup gt Hold gt TY Ne 7 CLK1 ff CLK2 ok L i i da CLK2 0 12 24 Clock Period 12 ns Multicycle 2 Multicycle Hold 1 In Figure 4 19 the data delay between the two registers is longer than one clock cycle but is less than two clock cycles This circuit requires two clock cycles for a change at the input of the source register to appear at the destination register The tsy check on c1k2 is performed at the second clock period at 24 ns and the ty check is performed at the next period at 12 ns This analysis ensures that the data delay is between 12 ns and 24 ns The minimum data delay is 12 ns and the maximum delay is 24 ns Figure 4 20 illustrates a design that has two data paths between the registers One data delay is shorter than one clock period and the other data delay is longer than one clock period but shorter than two clock periods The circuit is intended to operate as a multicycle path Altera Corporation 4 21 June 2004 Quartus Il Handbook Volume 3 Figure 4 20 Data Path Delay Example Setup _ Hod gt a Nena CLK re CLK2 CLK1 ari d
172. list Optimizations Fitter Settings Timing Analyzer Design Assistant SignalT ap Il Logic Analyzer SignalProbe Settings Simulator E Software Build Settings Stratix GX Registration HardCopy Settings amp Once the compilation is complete the results shown in Table 9 5 are reported by the Quartus II Timing Analyzer Altera Corporation June 2004 Table 9 5 fyay Results from the Quartus Il Timing Analysis with SignalTap Il Logic Analyzer Added Slack ns ie From To de 0 266 120 98 state m instl filter 22 acc inst3 result 11 clk 0 177 122 29 state m instl filter 22 acc inst3 result 6 clk 0 076 123 82 state m instl filter 22 acc inst3 result 7 clk 0 076 123 82 state m instl filter 22 acc inst3 result 8 clk Notice that when you added the SignalTap II Logic Analyzer to your design the longest register to register path changed The delay increased by approximately 8 This increase results in the system not meeting the timing requirements Figure 9 25 shows a failing path in the timing closure floorplan editor 9 33 Quartus II Handbook Volume 3 Figure 9 25 Failing Path in the Timing Closure Floorplan Editor 8 067 ns LIT 3 Back annotate the original design To minimize the effect that SignalTap II Logic Analyzer has on the original design
173. load and synchronous clear sclr signals are used You can change the synchronous mode of an LE by connecting or disconnecting the sload and sclr You cannot remove VCC connections to the sload however if you want to change the synchronous mode of the LE to off you can connect the sload and sclr to a valid GND signal in your design You can invert either the sload or sclr signal feeding into the LE The sload signal if used in an LE must be the same for all other LEs in the same LAB This includes the inversion state of the signal For example if two LEs in a LAB have the sload signal connected both LEs must have the sload signal set to the same value This is also true for the sclr signal Register Cascade Mode When register cascade mode is enabled the cascade in port feeds the input to the register The register cascade mode is used most often when the design implements a series of shift registers You can change the register cascade mode by connecting or disconnecting the cascade in However if you are creating this port you must ensure that the source LE is directly above the destination LE LUT Mask As mentioned in the section above the LUT mask is the hexadecimal representation of the LUT output Each ALM is broken down into a top LUT and a bottom LUT The LUT mask for each LUT is computed in the same manner as the above example However instead of four inputs six inputs are used Since the LUTs are driven
174. lpm ram dp component lpm outdata UNREGISTERED lpm ram dp component lpm file lt path to RIF gt lpm ram dp component use eab ON Compiling nopli v The nopli v file is included in the lt path to Quartus II installation gt eda sim_ lib directory This file contains the following definition define NO PLI 1 This basic definition instructs the VCS compile to read in the RIF The following VCS command simulates a design that includes Altera RAM blocks that require memory initialization ves R lt path to Quartus installation gt eda sim lib nopli v lt test bench gt v lt design name gt v v lt Altera library file gt v Post Synthesis Simulation A post synthesis simulation verifies the functionality of a design after synthesis has been performed You can create a post synthesis netlist in the Quartus II software and use this netlist to perform a post synthesis Altera Corporation June 2004 Using VCS in the Quartus Il Design Flow Altera Corporation June 2004 simulation in VCS Once the post synthesis version of the design has been verified the next step is to place and route the design in the target architecture using the Quartus II Fitter Generating a Post Synthesis Simulation Netlist The following steps describe the process of generating a post synthesis simulation netlist in the Quartus II software Perform Analysis amp Synthesis Choose Start gt Start Analysis amp Synthesis Processin
175. ls m LVDS You cannot tap the data out of a SERDES block Timing Preservation with SignalTap Il Logic Analyzer In addition to verifying functionality timing closure is one the most crucial processes in successfully completing a design When you compile a project with SignalTap II Logic Analyzer you are adding IP to your existing design therefore you could potentially affect the existing placement and routing and the timing of your design To minimize the effect that SignalTap II Logic Analyzer has on your design Altera recommends that you back annotate your design prior to inserting the SignalTap II Logic Analyzer This allows you to run your design at the desired frequency For an example of timing preservation with SignalTap II see the Design Optimization for Altera Devices chapter in Volume 2 of the Quartus II Handbook Using SignalTap Il Logic Analyzer to Simultaneously Debug Multiple Designs You can simultaneously debug multiple designs using one instance of the Quartus II software To perform this operation follow these steps 1 Create configure and compile the STP file for each design 2 Open each individual STP file Note a Quartus II project does not have to be open to open an STP file 9 29 Quartus II Handbook Volume 3 3 Use the JTAG Chain controls to select the target device in each STP file 4 Program each FPGA 5 Run each analyzer independently Figures 9 20 through 9 23 show a JTAG chai
176. mains To perform this operation first enable the Trigger Out of the first analyzer and set the name for the Trigger Out signal see the colored portion of Figure 9 11 Next you must enable the Trigger In of the second analyzer and set the name of the Trigger In of the second analyzer as the Trigger Out of the first analyzer see the colored portion of Figure 9 12 Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Altera Corporation June 2004 Figure 9 11 Enabling the Trigger Out Signal Dire Merger D gt ERTS ga TT Instar Status Les 478 Memory 1408 Not running 262 cells 1280 bits analyzer Not running 216 cells 128 bits trigger 2003 12 02 10 38 05 1 Lock made 2 Allow all changes X Signal Configuration Node incremental Debug Port Data Enable Trigger Enable Trigger Levels goy oj Type Alias lame Route out 55 55 M Basic SI nz _ attin m F F al a Sample depth Nodes allocated gt dftout a F F E inst D F F 256 x C Auo Manual 5 4 gt inste r F F RAM type gt insta G F F MK Buffer acquisition mode Circular F Pre trigger position Segmented 256 1 bit segment L r Trigger Trigger levels Nodes allocated 1 z Auto Manat T Trigger In Source ET Pattern 2i et tigger _out_analyzer
177. mation on using a VCD see the NC Sim user manual Adding Signals Command Line Mode To create an SHM database you specify the system tasks described in Table 3 4 in your Verilog HDL code c For VHDL you can use the Tcl command interface or C function calls to add signals to a database See Cadence documentation for details System Task Table 3 4 SHM Database System Tasks Description shm_open lt filename gt shm Open database You can provide a filename if you do not specify one the default is waves shm You must create a database before you can open it if one does not exist the tools create it for you shm_probe A S C Probe signals You can specify the signals to probe if you do not specify signals the default is all ports in the current scope A probes all nodes in the current scope S probes all nodes below the current scope C probes all nodes below the current scope and in libraries Sshm_save Save the database Sshm_close Close the database Altera Corporation August 2004 Following shows a simple example Example SHM Verilog HDL Code initial begin shm open waves shm shm probe AS end For more information on these system tasks see the NC Sim user manual 3 15 Quartus II Handbook Volume 3 Adding Signals GUI Mode To add signals in GUI mode perform the following steps 1 Load the design a Click t
178. ment and routing Verifying designs takes more times as designs get bigger Formal verification is a technique that helps reduce the time needed for your design verification cycle Altera Corporation 12 11 June 2004 Quartus II Handbook Volume 3 12 12 Altera Corporation June 2004 PN DTE RIA Index transport_int_delays 2 8 transport_path_delays 2 8 A Acquisition Clock Assigning 94 Adaptive Logic Module 10 10 Add Signals Command Line Mode 3 15 GUI Mode 3 16 to View 3 23 to View 3 15 Advanced Timing Analysis Reports Using Tcl Scripts 4 34 ALM Properties 10 14 Altera Megafunction 3 8 Analyzer Triggering 9 6 Applications Common 10 24 Assigning Data Signals 9 5 Assignments Multicycle 4 16 Multicycle Hold 4 17 Multicycle Source 4 18 Source Multicycle Hold 4 19 Asynchronous Memory 4 14 Bird s Eye View 10 5 Buffer Acquisition 9 23 c Captured Data Converting to Other File Formats 9 22 Saving 9 22 cds lib 3 6 Command Line Mode 3 7 Altera Corporation GUI Mode 3 7 Change Manager 10 23 Chip Editor 10 3 Floorplan 10 4 Locating a Node 9 31 Using in Design Flow 10 2 Clock Derived Clocks 4 13 Frequency Maximum 4 3 Hold Time 4 2 Inverted Clock 4 10 Nota Clock 4 11 Output Clock Frequency Adjusting 10 22 Requirements Specifying Individual 4 7 Settings 4 8 Setup Time 4 1 Skew 4 5 4 13 Reduce 4 31 to Output Delay 4 3 Command Prompt 2 11 3 30 Compilation Command Line Mode 3 11 Faster 9 20 G
179. mulation Models into Simulation Libraries LS The following steps are not required for the ModelSim Altera software 1 Choose Add to Project File menu and select Existing File 2 Browse to the lt quartus installation folder gt eda sim_lib gt and add the necessary simulation model files to your project 3 Select the simulation model file and select Properties View menu 4 Set the Compile to Library to the correct library LS The altera_mf vhd should be compiled into the altera_mf library The 220model vhd should be compiled into the lpm library vcom work altera mf lt quartus installation directory gt eda sim_lib altera_mf_components vhd gt vcom work altera mf lt quartus installation folder eda sim_lib altera_mf vhd gt Altera Corporation June 2004 Functional RTL Simulation Altera Corporation June 2004 vcom work lpm lt quartus installation folder eda sim_lib 220pack vhd gt vcom work lpm lt quartus installation folder eda sim_lib 220model vhd gt Compile Testbench and Design Files into Work Library 1 Select Compile All Compile menu or click the Compile All toolbar icon 2 Resolve compile time errors before proceeding to Loading the Design below vcom work work lt my_testbench vhd gt lt my_design_files ohd gt Loading the Design 1 Select Simulate Simulate menu 2 Expand the work library in the Simulate dialog box 3 Select the top level design unit your testben
180. n Connections Displays the connections to the selected resource Fan Out Connections Displays the connections away from the selected resource Immediate Fan In Highlights the resource that directly feeds the selected element Immediate Fan Out Highlights the resource that is directly fed by the selected element Show Delays Displays the time delay between the two selected resources Altera Corporation June 2004 Chip Editor Overview Altera Corporation June 2004 For more information on the Chip Editor Toolbar refer to the Quartus II on line help Bird s Eye View The Bird s Eye View see Figure 10 2 displays a high level picture of resource usage for the entire chip It provides a fast and efficient means of navigating between areas of interest in the Chip Editor In addition it provides controls that allow you to specify which graphic elements are displayed The controls apply to both the Bird s Eye View and the main Chip Editor window Figure 10 2 Bird s Eye View Main window Logic Background Logic Details Local Routing Global Routing M Ports Unused Resources Connection Lines Connection Labels and Arrows Selection Selection Disregarding Detail DO Block borders Bird s eye view Logic Background O Logic Details O Local Routing O Global Routing O Ports Unused Resources Connection Lines C Connection Labels and Arrows Selection Selection Disregarding Detail O Bloc
181. n an I O standard to a pin For more information about assigning I O standards see Assigning I O Standards on page 8 4 set instance assignment name IO STANDARD lt I O standard gt to lt SignalProbe pin name gt For a list of valid I O standards refer to the I O Standards general description in the Quartus II Help Altera Corporation June 2004 Scripting Support Adding Registers for Pipelining Use the following Tcl commands to add registers for pipelining For more information about adding registers for pipelining see Adding Registers for Pipelining on page 8 4 set instance assignment name SIGNALPROBE CLOCK lt clock name gt to lt SignalProbe pin name gt set_instance assignment name SIGNALPROBE NUM REGISTERS lt number of registers gt to lt SignalProbe pin name gt Run SignalProbe Automatically Use the following Tcl command to cause SignalProbe to run automatically after a full compile For more information about running SignalProbe automatically see Performing a SignalProbe Compilation on page 8 5 set global assignment name SIGNALPROBE DURING NORMAL COMPILATION ON Altera Corporation June 2004 Run SignalProbe Manually You can run SignalProbe manually with a Tcl command or witha command run at a command prompt For more information about running SignalProbe manually see Performing a SignalProbe Compilation on page 8 5 Tcl command execute
182. n and its associated STP files Figure 9 20 JTAG Chain Communication Cable Stratix FPGA1 Stratix FPGA2 Stratix FPGA3 Figure 9 21 STP File for the First Device in the JTAG Chain x JTAG Chain Configuration JTAGready Instance Manager PQ D E Ready to acquire 2 Instance Status LEs 281 Memory 640 auto_signaltap_0 Not running 281 cells 640 bits APE Setup essa sea C Signal Configuration Lock mode Allow all changes X Data Enable Trigger Enable Trigger Levels Clock o El Debug Port Out S Auto SiAuto 1W Basc D clear F lata Sample depth cnt_enable F Z F ob x E ht Manuat 5 RAM type la D t D digit M4K Buffer acquisition made Circular 2 Pre trigger position trigger 2003128 16 59 59 1 Node Name Nodes allocated Type lt lt alal i Altera Corporation June 2004 9 30 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Figure 9 22 STP File for the Second Device in the JTAG Chain Instance Manager Ma gt E Ready to acquire JTAG Chain Configuration JTAG ready Q Inst Stat ___LEs 328 Memory 1280 AI an NNS gaue E bits adware Setup top_level sof trigger 2003218 17 03 56 Lock mode Ef Allow all changes 5 Clock ek al F F Data F F Sample depth Nodes allocated F F Auto C Man
183. n on the input pin that clocks the register Micro tco is the internal clock to output delay of the register Figure 4 3 shows a diagram of clock to output delay Figure 4 3 Clock to Output Delay tco Micro co OTO VIN Data Delay Clock Delay The following equation calculates the tco of the circuit shown in Figure 4 3 tco Clock Delay Micro tco Data Delay Pin to Pin Delay tpp Pin to pin delay tpp is the time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin In the Quartus II software you can also make tpp assignments between an input pin and a register a register and a register and a register and an output pin Maximum Clock Frequency fmax Maximum clock frequency is the fastest speed at which the design clock can run without violating internal setup and hold time requirements The Quartus II software performs timing analysis on both single and multiple clock designs 4 3 Quartus II Handbook Volume 3 4 4 Slack Slack is the margin by which a timing requirement e g fmax is met or not met Positive slack indicates the margin by which a requirement is met Negative slack indicates the margin by which a requirement was not met The Quartus II software determines slack with the following equations Slack Required clock period Actual clock period Slack Slack clock period Mi
184. n the settings to input clock signals with the Assignment Organizer Tools menu TT Include extemal delays to and from device pins in fmax calculations m Specify circuit frequency as Settings for individual clock signals Existing clock settings Name Type fmax Period Offset Edit i TT Cut paths between unrelated clock domains Default External Delays You can set global tsy tco and tpp requirements as well as minimum ty tco and tpp requirements You can set a global fmax requirement or assign timing requirements and relationships for individual clocks e For more information about path cutting options in the Timing Requirements amp Options page see False Paths on page 4 28 Specifying Individual Clock Requirements Apply clock requirements to each clock in your design You can define clocks as absolute clocks independent of other clocks or derived clocks dependent on other clocks To define an absolute clock you must specify the required fmax and the duty cycle A derived clock is based on a previously defined clock For a derived clock you can specify the phase shift offset and multiplication and division factors relative to the absolute clock You must define clock requirements and relationships with the Timing Wizard or by clicking Clocks in the Timing Altera Corporation 4 7 June 2004 Quartus II Handbook Volume 3 4 8 Requirements am
185. nalProbe Settings Simulator Software Build Settings Stratix GX Registration HardCopy Settings Synthesis Netlist Opti tions Specify options for performing netlist optimizations during synthesis Note The availability of these options depends on the current device family MW Perform WYSIWYG primitive resynthesis using optimization technique specified in Analysis amp Synthesis settings TT Perform gate level register retiming IV Allow register retiming to trade off Tsu Tico with Fray Cancel 72 12 4 Choose Fitter Settings in the Category list of the Settings dialog box Under Fitter Settings select Physical Synthesis Optimizations On the Physical Synthesis optimizations page ensure that Perform register retiming is turned off Figure 12 4 2 Retiminga design usually results in moving and merging registers along the critical path and is not very well supported by equivalence checking tools Because equivalence checkers compare the cones of logic terminating at registers it is necessary that registers not be moved during Quartus II optimization If the options described in this section are not selected the Incisive Conformal script may be presented with a different set of compare points and the resulting netlist would be difficult to compare against the reference netlist file Altera Corporation June 2004 Generating the VO File amp Incisive Conformal Script
186. nalTap II configurations do not need more than the number of RAM bits that are available for that type of memory FPGA Resources Used by SignalTap Il SignalTap II Logic Analyzer has a built in resource estimator that dynamically calculates the number of LEs and the amount of memory that each SignalTap II analyzer uses This feature is useful when device resources are limited and you must know what device resources the SignalTap II analyzer uses The value reported in the resource usage estimator may vary by as much as 5 from the actual resource usage The following tables provides an estimate of the number of LEs and the amount of memory that are required to add SignalTap II Logic Analyzer to your design Table 9 3 shows the SignalTap II Logic Analyzer M4K memory block resource usage for these devices per signal width and sample depth Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Altera Corporation June 2004 Table 9 3 SignalTap Il Logic Analyzer M4K Block Utilization for Cyclone Stratix GX and Stratix Devices Note 1 Signals Samples Width Width 256 512 2 048 8 192 8 lt 1 1 4 16 16 1 2 8 32 32 4 16 64 64 8 32 128 256 16 32 128 512 Note to Table 9 3 1 When configuring a SignalTap II Logic Analyzer the Instance Manager reports an estimate of the memory bits and logic elements required to implement the given configura
187. namically Load anale Statically Link Scripting Support Generate NC Sim Simulation Output Files ss Conclusion References Altera Corporation Contents Section II Timing Analysis Revision History ipa rale load aaa Section II 1 Chapter 4 Quartus Il Timing Analysis Introduetioni s rna tania aaa Rara 4 1 Timing Analysis Basics urla ai 4 1 Clock Setup Time 1SU i aaa 4 1 Clock Hold Time tH Clock to Output Delay CO ee aa eiaa eea illa Pineto Pin Delay PO eses lidia Maximum Clock Frequency fMAX Slack a ai Hold Time Slack nn nan ils terra Neale Clock Skew Executing Tcl Script Based Timing Commands ss Setting up the Timing Analy Zeer vi cc s cccssccssesiesccsicicesissicsasssesesseasvtvacsescacsuticeisetetsisradsetsisecscaseaseiesetsteees Setting Global Timing Assignment cccsseeseeseeeeeeeees Specifying Individual Clock Requirements Setting Other Individual Timing Assignments Timing Wizard simpa et sise Timing Analysis Reporting in the Quartus II Software Advanced Timing Analysis Clock SOW seis cic sedssxoascetuctalissuti savsdedsvsdedapiasuaesdaceandaietenietbaniartvaetiasiasieseesdas EAEE Sra TEES Multiple Clock Domains irritare Multicycle Assignments Typical Applications of Multicycle Assignment cccccssesesseseseseenessesesiessseseesseseseeeessenens 4 19 Fal
188. nd displays it in the Hex Editor M Continuously Read Data from In System Memory Continuously reads the data asynchronously from the device and displays it in the Hex Editor M Stop Stops the current read or write operation m Write Data to In System Memory Asynchronously writes data present in the Hex Editor to the device 11 5 Running the In System Memory Content Editor The status of each instance is also displayed beside each entry in the Instance Manager The status indicates if the instance is Not running Offloading data or Updating Data The health monitor provides useful information about the status of the editor The Quartus II software assigns a different index number to each in system memory and constant to distinguish between multiple instances of the same memory or constant function View the In System Memory Content Editor Setting section of the compilation report to match an index with the corresponding instance ID Figure 11 3 Figure 11 3 Compilation Report In System Memory Content Editor Setting Section new_ver16 Compilation Report 4 lol xj In System Memory Content Editor Setting Depth Mode __ Hierarchy Location Compilation Report E Legal Notice SEZ Flow Summary SEE Flow Settings EB Flow Elapsed Time E Flow Log ES Analysis amp Synthesis 40 Analysis amp Synthesis Summary S amp D Settings 8a Analysis amp Synthesis Optimization Results E Sa Analysis
189. ng an Altera FPGA This chapter provides step by step explanations of how to simulate your design in the ModelSim Altera version or the ModelSim full version This chapter gives you details on the specific libraries that are needed for a functional simulation or a gate level timing simulation This document describes ModelSim Altera software version 5 8c and the ModelSim PE software version This document contains references to features available in the Altera Quartus II software version 4 1 Please visit the Altera web site available at www altera com quartus for information on this Quartus II software version The ModelSim Altera software version 5 8c is included with your Altera software subscription and can be licensed for the PC Solaris HP UX or Linux platforms to support either VHDL or Verilog hardware description language HDL simulation The ModelSim Altera tool supports VHDL or Verilog functional simulations and gate level timing simulations for all Altera devices Table 1 1 describes the differences between the ModelSim Modeltech and ModelSim Altera versions Table 1 1 Comparison of ModelSim Versions Part 1 of 2 Product Feature ModelSim SE ModelSim PE ModelSim Altera 100 VHDL Verilog mixed HDL support option option Supports only single HDL simulation Complete HDL debugging environment V4 v V4 Optimized direct compile architecture 7 Y 7 Industry standard scripting Y Va Y Flexible licensin
190. ns the SignalTap II Logic Analyzer settings and the captured data for viewing and analysis To create a new STP file follow these steps 1 In the Quartus II software choose New File menu 2 Click on the Other Files tab and select SignalTap II File 3 Click OK To open an existing STP file select SignalTap II Logic Analyzer Tools menu This method can also be used to create a new STP file Both of these methods bring up the SignalTap II window Figure 9 3 Altera Corporation 9 3 June 2004 Quartus Il Handbook Volume 3 9 4 Figure 9 3 SignalTap Il Window Add nodes to the cumentinsance 0 uso Memory 0 Ocels Obits 5 Device t EP1S25 0 v Scan Chain Fe El auto _signatap_0 Lock mode af Atow al changes z Signal Configuration x Tode incrementat Debug Port ata Enable Trigger Enable Trigger Levels Type aiias Tame Route out omo omo elesse 04 n a project to add no Semple depth Nodes allocated 12 Auo Manat a RAM ype me Butfer acquisition mode Croda 5 C Segmented Tigger Tigger levels Nodes located j Auto C Manu Tage in Source E Pater z T Trigger out Taget A Levet Latency delay lt gt Bal Data fg setup Hierarchy Display x F Daalog BI td auto signaltap 0 E auto signa 0 Assigning an A
191. nstraints specified in Quartus format and libraries to the PrimeTime environment Figure 5 1 shows the PrimeTime flow diagram Figure 5 1 PrimeTime Flow Diagram Design Netlist Constraints in SDO File Verilog or PrimeTime Timing VHDL Format Format Information DB lib HDL lib Timing Reports Generated Qu artus Il To set the Quartus II software to generate PrimeTime files choose i Settings Assignments menu Choose EDA Tool Settings gt Timing Setti ngs to Analysis in the Category dialog box to display the Timing Analysis Generate window In the Timing Analysis window click on the Tool name pull i x P down menu and select PrimeTime Verilog HDL output from Pri meTi me Fi les Quartus II or PrimeTime VHDL output from Quartus II as shown in Figure 5 2 This setting enables the Quartus II software to produce three files for the PrimeTime tool which are then written into the timing primetime directory of the current project Altera Corporation 5 1 June 2004 Quartus II Handbook Volume 3 Files Generated for the PrimeTime Environment 5 2 Figure 5 2 Setting the Quartus Il Software to Generate PrimeTime Files Settings standard xj Category General Files User Libraries Device Timing Requirements amp Options E EDA Tool Settings Design Entry amp Synthesis Simulation Timing Analysis Board Level Formal Verification Resynthesis Compilation Process Analysis amp Synth
192. nts menu to allow the compiler to modify the routing to the specified SignalProbe source see Figure 8 4 This setting allows the Fitter to modify the existing routing channels used by your design 8 7 Quartus Il Handbook Volume 3 Is Turning on Modify latest fitting results during SignalProbe compilation may change the performance of your design Figure 8 4 SignalProbe Settings Page in the Settings Dialog Box Settings block1 User Libraries Device Timing Requirements amp Options EDA Tool Settings Design Entry amp Synthesis Simulation Timing Analysis Board Level Formal Verification Resynthesis Compilation Process Analysis amp Synthesis Settings Fitter Settings Timing Analyzer Design Assistant SignalT ap Il Logic Analyzer Simulator Software Build Settings Stratix GX Registration HardCopy Settings Physical Synthesis Optimizations SignalProbe Settings Understanding the Results of a SignalProbe Compilation 8 8 Use the Messages window to view the results of the SignalProbe compilation This window lists successfully routed SignalProbe pins In addition it displays slack information for each successfully routed SignalProbe pin Altera Corporation June 2004 Scripting Support You can view the status and delays of each SignalProbe pin by viewing the Status column in the Assign SignalProbe Pins dialog box Table 8 1 describes the possible value
193. obe Pins on the SignalProbe Settings page of the Settings dialog box Assignment menu See Figure 8 1 2 Turn on Show current and potential SignalProbe pins in the Assign SignalProbe Pins dialog box 3 Select a pin Number from the Available Pins amp Existing Assignments list 4 Type your SignalProbe pin name into the Pin name box 5 Select As SignalProbe output from the Reserve pin list 6 Turn on Reserve pin 7 Click Add for a new SignalProbe pin or Click Change for an existing SignalProbe pin 8 Click OK 8 2 Altera Corporation June 2004 Using SignalProbe Figure 8 1 Reserving a Pin for SignalProbe in the Assign SignalProbe Pins Dialog Box Assign SignalProbe Pins xj Select a device pin and the type of assignment you wish to make You can also make pin assignments in the Assignment Editor and the Floorplan Editor You can reserve unused pins on a device wide basis with the Unused Pins tab in the Device amp Pin Options dialog box You must perform a smart compilation on the design before routing SignalProbe signals T Show no connect pins Available Pins amp Existing Assignments Name 0 Bank 1 0 Standard Type G27 SignalProbe_pin_1 2 RARE tow 1 0 DIFFIO_RX21p G28 LYTTL Row 1 0 DIFFIO_RX21n Row 1 0 DIFFIO_TX21p Row 1 0 DIFFIO_TX21n Row 1 0 DIFFIO_RX20p RUP2 Row 1 0 DIFFIO_RX20n RDN2 A 5 FN Show current and potential SignalProbe pins Assignment 1 0
194. off tool used to perform static timing analysis on most ASIC designs The Quartus II software provides a path to enable you to run Prime Time on your Quartus designs and export a netlist timing constraints and libraries to the Prime Time environment This section explains the basic principles of static timing analysis the advanced features supported by the Quartus II Timing Analyzer and how you can run Prime Time on your Quartus designs This section includes the following chapters Mm Chapter 4 Quartus II Timing Analysis Mm Chapter 5 Synopsys PrimeTime Support The table below shows the revision history for Chapters 4 and 5 Chapter s Date Version Changes Made 4 June 2004 v2 0 Updates to tables figures e New functionality for Quartus 4 1 Feb 2004 v1 0 Initial release 5 June 2004 v2 0 No changes to document Feb 2004 v1 0 Initial release Section II 1 Timing Analysis Quartus Il Handbook Volume 3 Section Il 2 Altera Corporation N D E PYA 4 Quartus Il Timing Analysis qii53004 2 0 Introduction Timing Analysis Basics Altera Corporation June 2004 As designs become more complex the need for advanced timing analysis capability grows Static timing analysis is a method of analyzing debugging and validating the timing performance of a design Timing analysis measures the delay of every design path and reports the performance of the design in terms of t
195. ogic After Using Chip Editor LE1 LUT LE2 LUT LE NEW LUT LE3 LUT LE4 LUT Db Db gt i Lap SE bl Oo lb gt r REGOUT Y COMBOUT Y COMBOUT COMBOUT COMBOUT vi J J Yy gt gt l Routing an Internal Signal to an Output Pin You can use the capabilities in the Chip Editor to route internal signals to unused output pins This capability allows you to capture signals that are internal to the FPGA with an external logic analyzer The process of routing these signals is straightforward and requires very little time allowing you to spend less time on the setup and more time on debugging The following steps will help you understand the process required to route an internal signal to an output pin see Figure 10 18 Figure 10 18 Routing an Internal Signal to an Output Pin LE1 LUT Output Pin DO COMBOUT 1 Create an output pin 2 Create the REGOUT or COMBOUT of Source LE 3 Connect the DATAIN of the output pin to the REGOUT or the COMBOUT of the Source LE 4 Optional Connect a clock to the CLK port of the output pin 10 26 Altera Corporation June 2004 Example Design Meeting I O Timing Example Design Meeting 1 0 Timing Adjust the Phase Shift of a PLL to Meet 1 0 Timing
196. ogical equivalence between the synthesized netlist from Synplicity Synplify and the post fit Verilog Quartus Mapped vqm files using Incisive Conformal software This section discusses formal verification how to set up the Quartus II software to generate the VQM file and Incisive Conformal script and how to compare designs using Incisive Conformal software This section includes the following chapter m Chapter 12 Cadence Incisive Conformal Support The table below shows the revision history for Chapter 12 Chapter s Date Version Changes Made 12 June 2004 v2 0 e Updates to tables figures e New functionality for Quartus 4 1 e This chapter was formerly chapter 11 in the previous section Feb 2004 v1 0 Initial release Section V 1 Formal Verification Quartus Il Handbook Volume 3 Section V 2 Altera Corporation 12 Cadence Incisive JNO E RYA Conformal Support qii53011 2 0 Introduction Formal Verification Altera Corporation June 2004 The Altera Quartus II software version 4 1 easily interfaces with EDA tools such as the Cadence Incisive Conformal software and Synplicity Synplify software In addition the Quartus II software has built in support for verifying the logical equivalence between the synthesized vqm netlist from Synplicity Synplify and the post fit Verilog vo files using the Incisive Conformal software This chapter discusses the followin
197. oject_name gt Open the project in the project directory M create timing netlist Timing information is created in the memory for analysis E project close This command should be executed at the end of every script The remainder of this chapter includes Tcl command examples for making timing assignments and performing timing analysis Refer to the Quartus II Command Line and Tcl API Help for complete information about the above commands other Tcl commands related to timing analysis and reporting and the complete Tcl command reference To run the Tcl API Help type the following command quartus_sh qhelp You can make certain timing assignments globally for a project and you can make timing assignments to individual entities in a project If a project has global and individual timing assignments the individual timing assignments take precedence over the global timing assignments Altera Corporation June 2004 Quartus Il Timing Analysis Setting Global Timing Assignments You can make global timing assignments in the Timing Requirements amp Options page of the Timing Settings dialog box Assignments menu shown in Figure 4 7 Figure 4 7 Timing Settings Dialog Box Clock Settings Other Requirements amp Options Timing Analysis Reporting Specify an overall default frequency for the project or the settings for each clock that is part of the Project If you create settings for each clock you must assig
198. ollowing steps 1 Run the PLI wizard by typing pliwiz at the command prompt 2 Inthe Config Session Name and Directory page type the name of the session in the Config Session Name box and type the directory in which the file should be built in the Config Session Directory box 3 Click Next 4 Inthe Select Simulator Dynamic Libraries page select the Dynamic Libraries Only option 5 Click Next 6 Inthe Select Components page turn on the PLI 1 0 Applications option select libpli 7 Click Next 8 Inthe Select PLI 1 0 Application Input page select Existing VERIUSER source object file 9 Select Source File and click Browse to locate the veriuser c file that is provided with the Quartus II software The veriuser c file is located in the following location lt Quartus II installation gt eda cadence verilog x1 10 Click Next 11 In the PLI 1 0 Application page click browse under PLI Source Files to locate the convert_hex2ver c file Altera Corporation August 2004 Incorporating PLI Routines Altera Corporation August 2004 12 Click Next 13 In the Select Compiler page choose your C compiler from the Select Compiler list box An example of a C compiler would be gcc To allow the PLIWIZ to find your C compiler ensure your path variable is set correctly 14 Click Next 15 Click Finish 16 When you are asked if you want to build your targets now click Yes 17 Compilation creates the file l
199. olume 3 Design Example Preserving Timing For more information on using the Chip Editor see the Design Analysis amp Engineering Change Management with Chip Editor chapter in Volume 3 of the Quartus II Handbook The following example shows the importance of back annotating your design prior to inserting SignalTap II Logic Analyzer The design files that are used for this example vary slightly from the FIR filter design that is included in the qdesigns directory To follow this example you should first restore the compile_fir_filter_original qar design file Scenario After programming your FPGA you notice incorrect behavior with your circuit Because you are using a fine pitch package using a traditional logic analyzer is not possible To debug this design you need to use the SignalTap II embedded Logic Analyzer The design calls for an fmax requirement of 125 MHz to be met 1 Initial compilation without SignalTap II Logic Analyzer When you run the Quartus II Timing Analyzer you see the following results for the main clock in the design see Table 9 4 Table 9 4 fmax Results from the Quartus Il Timing Analysis Actual fmax Clock lack n Slack ns MHz From To Source 0 167 127 67 state m instl filter 22 acc inst3 result 11 clk 0 256 129 13 state m instl filter 22 acc inst3 result 6 clk 0 144 127 29 state m instl filter 22 acc inst3 result 7 clk 0 144 127 29 state m instl filter 22
200. on name gt The In System Memory Content Editor is separated into the Instance Manager JTAG Chain Configuration and the Hex Editor Figure 11 1 Figure 11 1 In System Memory Content Editor Index Instance ID Not running Not running Not running qa 0 ACAC BE Instance Manager Et m El Ready to acquire JTAG Chain Configuration fra ready x T 8 RAM ROM Read wiite Hardware ByteBlasterM LPT1 Setup Constant Read Write pay er erican DINO RAM ROM Read Wiite Device 1 EP1C20 0x020840DD Scan Chain File a GG Si s l CNST 000000 00 00 00 0O 00 00 00 00 OO 00 00 00 00 OO 00 00 00 00 00 OO 00 00 00 00 000018 00 00 00 00 00 00 00 00 000000 AB m2 ADAC 000000 3D 41 6C 74 65 72 61 20 43 6F 72 70 6F 72 61 74 69 6F 6E 00 00 00 00 00 000018 3D 00 00 00 00 00 00 00 a Altera Corporation instance 1 CNST Word 0x000000 Bit 0x000007 4 11 4 The Instance Manager displays all available run time configurable memories and constants in your FPGA device The JTAG Chain Configuration section allows you to program your FPGA and select the Altera device in the chain to update Enter and evaluate data in the Hex Editor Using the In System Memory Content Editor does not require you to open a project The In System Memory Content Editor retrieves all instances of run time configurable memories and constants by scanning the JTAG chain and sending a
201. ons Fixing 4 31 11 7 I O Elements MAXI 10 17 I O Standards Assigning 8 4 8 10 Incisive Conformal 12 8 Black Boxes in Flow 12 8 Running 12 9 Running from Command Prompt 12 9 Running from GUI 12 9 Script amp VO File 12 2 Instance Manager 11 5 In System Configurable Memory and Constants Memory Content Editor 11 4 11 8 Updating 11 3 11 3 L LE ALM Supported Changes Libraries Create 3 6 3 20 LPM Function 3 8 Libraries Quartus II Timing Simulation 3 20 10 11 Altera Corporation Library Setup 3 6 Licensing 1 20 Local PC Software Setup 9 27 Logic Element 10 9 Properties 10 12 LPM Functional RTL Simulation Models 1 4 LUT Equation 10 12 Mask 10 13 LUT Mask 10 14 Maximum Delay Input 4 9 Output 4 9 Meeting I O Timing 10 27 MegaWizard Generated File Modifying 1 10 2 4 MIF to RIF 1 10 2 4 Minimum Timing Analysis 4 33 Performing 4 33 Reporting 4 34 Settings 4 33 Mnemonics Creating for Bit Patterns 9 23 Mode Extended LUT Mode 10 15 External Feedback 10 22 of Operation 10 12 Register Cascade Mode 10 14 Shared Arithmetic Mode 10 15 Synchronous Mode 10 14 ModelSim Altera Software 1 3 Quartus II Software Output Files 1 11 Modes Operation 3 3 Modifying the PLL Using the Chip Editor 10 21 Multicycle Assignments Typical Applications 4 19 Multicycle Hold Assignments 4 31 Multicycle Paths Multi Frequency Domains 4 24 Altera Corporation Offsets 4 23 Simple 4 19 Multiple Clock Domains 4
202. ook Volume 3 Command prompt Use the following command to generate a simulation output file for the Cadence NC Sim simulator Specify Vhdl or Verilog HDL for the format quartus_eda lt project name gt simulation format lt vwerilog vhdl gt tool ncsim Conclusion References 3 30 The Cadence NC family of simulators work within an Altera FPGA design flow to perform functional RTL and gate level timing simulation easily and accurately Altera provides functional models of LPM and Altera specific megafunctions that you can compile with your testbench or design For timing simulation you use the atom netlist file generated by Quartus II compilation The seamless integration of the Quartus II software and Cadence NC tools make this simulation flow an ideal method for fully verifying an FPGA design E Cadence NC Verilog Simulator Help E Cadence NC VHDL Simulator Help Mm Cadence NC Launch User Guide Altera Corporation August 2004 Section Il Timing AND E RYA a Analysis Revision History Altera Corporation As designs become more complex the need for advanced timing analysis capability grows Static timing analysis is a method of analyzing debugging and validating the timing performance of a design The Quartus II software provides the features necessary to perform advanced timing analysis for today s system on a programmable chip SOPC designs Synopsys Prime Time is an industry standard sign
203. or altera_mf simulation libraries I gt Ifyou are using the ModelSim Altera version see Table 1 3 and Table 1 5 for the location of the precompiled simulation libraries If youare using the ModelSim Modeltech version browse to the library that was created earlier In the Load Design dialog box click the Design tab Expand the work library in the Simulate dialog box Select the top level design unit your testbench Select OK in the Simulate dialog box vsim L lt location of the altera_mf library gt L lt location of the lpm library gt work lt my_testbench gt Running the Simulation I Choose Signals and Wave View menu Quartus Il Handbook Volume 3 1 10 view signals view wave 2 Drag signals to monitor from the Signals window and drop them into the Wave window add wave lt signal name gt 3 At the prompt type the following run lt time period gt Verilog Functional RTL Simulation with Altera Memory Blocks You can simulate your design containing complex memory blocks such as LPM_RAM_DP and ALTSYNCRAM using either ModelSim software version These memory blocks can be configured with power up data via a hexidecimal hex or Memory Initialization File mif The LPM_FILE parameter included in the MegaWizard generated file points to the path of the HEX file or MIF that is used to initialize the memory block You can create a HEX file or MIF through the Quartus II software N
204. or more information about command Altera Corporation June 2004 Scripting Support line scripting see theCommand Line Scripting chapter in the Quartus IT Handbook Volume 2 For detailed information about scripting command options see the Qhelp utility Type this command to start it quartus sh qhelp Generating a Post Synthesis Simulation Netlist for VCS You can use the Quartus II software to generate a post synthesis simulation netlist with Tcl commands or with a command at a command prompt Tcl Commands Use the following Tcl commands set_global_assignment name EDA OUTPUT DATA FORMAT VERILOG set global assignment name EDA SIMULATION TOOL VCS set global assignment name EDA GENERATE FUNCTIONAL NETLIST ON 3 Command Prompt Use the following command to generate a simulation output file for the VCS simulator specify vhdl or verilog for the format quartus eda lt project name gt simulation on format lt format gt tool vcs functional Generating a Gate Level Timing Simulation Netlist for VCS You can use the Quartus II software to generate a gate level timing simulation netlist with Tcl commands or with a command at a command prompt Tel Commands set global assignment name EDA OUTPUT DATA FORMAT VERILOG set global assignment name EDA SIMULATION TOOL VCS Command Prompt Use the following command to generate a simulation output file for the VCS simul
205. oration June 2004 Conclusion Altera Corporation 1 21 June 2004 Quartus II Handbook Volume 3 1 22 Altera Corporation June 2004 2 Synopsys VCS Support JAN DTS RA qgii53002 2 0 Introduction Software Requirements Using VCS in the Quartus II Design Flow Altera Corporation June 2004 This chapter is a getting started guide to using the Synopsys VCS software to simulate designs targeting Altera FPGAs It provides a step by step explanation of how to perform functional simulations post synthesis simulations and gate level timing simulations using the VCS software This document contains references to features available in the Altera Quartus II software version 4 1 For more information on the Quartus II software version 4 1 go to the Altera web site at www altera com In order to properly simulate your design using VCS you must first install the Quartus II software Table 2 1 shows the supported Quartus II VCS version compatibility Table 2 1 Supported Quartus Il amp VCS Software Version Compatibility Synopsys Altera VCS software version 7 0 Quartus II software version 3 0 VCS software version 7 0 1 Quartus II software version 4 0 VCS software version 7 1 1 Quartus II software version 4 1 See the Quartus II Installation amp Licensing for PCs or the Quartus II Installation amp Licensing for UNIX and Linux Workstation manuals for more information on installing
206. our Verilog HDL or VHDL design from the command line use the following command ncsim options lt library gt lt cell gt lt view gt For example ncsim worklib lpm ram _dp syn Table 3 5 shows some of the options you can use with nesim Table 3 5 nesim Options Options Description gui Launch GUI mode batch Used for non interactive mode tcl Used for interactive mode not required when gui is used Functional RTL Simulation GUI Mode You can run and step through simulation of your Verilog HDL or VHDL design in the GUI Select Run from the Simulation menu to begin simulation UE Ifyou skipped Add Signals to View on page 3 15 you must load the design before simulating See step 1 Load the design on page 3 16 for instructions The following sections provide detailed instructions for performing timing simulation using Quartus II output files and simulation libraries and Cadence NC tools Quartus Il Simulation Output Files When you compile your Quartus II design the software generates VO or VHO files and a SDO file that are compatible with Cadence NC simulators To generate these files perform the following steps in the Quartus II software Altera Corporation August 2004 Gate Level Timing Simulation 6 Choose EDA Tool Settings Assignments menu Click on the plus to the left of EDA Tool Settings in the Category list This will expand the EDA Tool Se
207. our design cycle Depending where you are in your design cycle you can either use the Power in the Excel based power calculator or the simulation based power estimation De sig n Cycle feature in Quartus II Since FPGAs provide the convenience of a shorter design cycle and faster time to market the board design often takes place during the FPGA design cycle which means the power planning for the device can happen before the FPGA design is complete If the FPGA design has not yet Altera Corporation 6 3 June 2004 Quartus Il Handbook Volume 3 begun or is not complete an estimate of the power consumption for the design can be made using the Excel based power calculator Table 6 1 shows the power estimation flow when using the Excel based power calculator when the FPGA design has not begun Table 6 1 Power Estimation Before FPGA Design Has Begun Steps to Follow Advantages Disadvantages 1 Download the Excel based power Power Estimation can be done Accuracy is dependent on user calculator from the Altera website before any FPGA design is input and estimate of the device 2 Manually fill in the power complete TSSOUICeS calculator Can be time consuming 6 4 When the FPGA design is partially complete the power estimation file generated by the Quartus II software can help to fill in the Excel based power calculator After using the Import Data macro to import the power estimation file information into t
208. ource register outff a 9 and destination pin out Info tco from clock to output pin is 7 318 ns Info Longest clock path from clock clk to source register is 2 684 ns Info 1 IC 0 000 ns CELL 0 619 ns 0 619 ns Loc Pin L2 Fanout 100 CLK Node clk nfo 2 IC 1 523 ns CELL 0 542 ns 2 684 ns Loc LC_X32_Y30_N2 Fanout 1 REG Node outff a 9 nfo Total cell delay 1 161 ns 43 26 Info Total interconnect delay 1 523 ns 56 74 Info Micro clock to output delay of source is 0 156 ns Info Longest register to pin delay is 4 478 ns Info 1 IC 0 000 ns CELL 0 000 ns 0 000 ns Loc LC_X32_Y30_N2 Fanout 1 REG Node outff a 9 Info 2 IC 0 400 ns CELL 0 366 ns 0 766 ns Loc LC X32 Y30 N8 Fanout 1 COMB Node xx 0 190 nfo 3 IC 1 093 ns CELL 2 619 ns 4 478 ns Loc Pin J9 Fanout 0 PIN Node out nfo Total cell delay 2 985 ns 66 66 Info Total interconnect delay 1 493 ns 33 34 There are several methods that you can use to meet the tco requirement However further investigation shows that the most efficient method is to reduce the register to pin delay using gate level retiming Based on the analysis just performed you can see that the data passes from the register through the combinational logic to the pin You can move the register between the combinational logic and the pin to reduce 10 28 Altera Corporation June 2004 Example
209. own system tasks that currently may not exist in the Verilog language Preparing amp Linking C Programs to Verilog Code When compiling the source code the C code must include a reference to the vesuser h file This file defines PLI constants data structures and routines that are necessary for the PLI interface This file is included with the VCS installation and can be found in the VCS_HOME lib directory Once the C code is complete you must create an object file 0 Create the object file by using the following command gcc c my custom function c Next you must create a PLI table file tab This file maps the C program task to the matching task task in the Verilog source code You can create the TAB file using a standard text editor The following is an example of an entry in the TAB file my custom function call my custom function acc rw The Verilog code can now include a reference to the user defined task To compile an Altera FPGA design that includes a reference to a user defined system task type the following at the command line prompt ves R lt test bench gt v lt design name gt v v lt Altera library file gt v P lt my_tabfile tab gt lt my_custom_function o gt Run procedures and create settings described in this chapter in a Tcl script You can also run some procedures at a command prompt For more information about Tcl scripting see the Tcl Scripting chapter in the Quartus II Handbook Volume 2 F
210. p Options page of the Settings dialog box Assignments menu Altera recommends that you define all clock requirements and relationships in your design to ensure accurate timing analysis results Clocks can also be specified by executing tcl scripts Mm Usage for absolute clocks create base clock fmax lt fmax gt duty cycle lt duty cycle gt target lt name gt no target entity lt entity gt disable lt clock_name gt m Example for absolute clock create base clock fmax 50ns duty cycle 50 clk50 m Usage for relative clocks create relative clock base clock lt Base clock gt duty cycle lt duty cycle gt multiply lt number gt divide lt number gt offset lt offset gt invert target lt name gt no target entity lt entity gt disable lt clock name gt M Example for relative clock C1k2 3 is created based on predefined clock c1k10 create relative clock base clock multiply 2 divide 3 clk10 clk2_3 Setting Other Individual Timing Assignments You can use the Assignment Editor to make other individual timing assignments to pins and nodes in your design For detailed information about how to use the Assignment Editor see the Assignment Editor chapter in Volume 2 of the Quartus II Handbook For more detailed information about individual timing assignments or for information about timing assignments not listed below see Quartus II Help Clock Settings Use this timing as
211. pport adding registers to a SignalProbe pin You can start a SignalProbe compilation manually or automatically after a full compilation A SignalProbe compilation performs the following steps 1 Validate SignalProbe pins 2 Validate your specified SignalProbe sources 3 If applicable add registers into SignalProbe paths 4 Attempt to route from SignalProbe sources through registers to SignalProbe pins 8 5 Quartus Il Handbook Volume 3 To make the SignalProbe compilation run automatically after a full compile turn on Automatically route SignalProbe sources during compilation in the SignalProbe Settings page in the Settings dialog box Assignments menu see Figure 8 3 Figure 8 3 SignalProbe Settings Page in the Settings Dialog Box F E Settings block1 x Category General Files User Libraries Device Timing Requirements amp Options EDA Tool Settings Design Entry amp Synthesis Simulation Timing Analysis Board Level Formal Verification Resynthesis Compilation Process Analysis amp Synthesis Settings Fitter Settings Physical Synthesis Optimizations Timing Analyzer Design Assistant SignalT ap Il Logic Analyzer SignalProbe Settings Simulator Software Build Settings Stratix GX Registration HardCopy Settings SignalProbe Settings Specify options for SignalProbe Note The availability of some of t
212. project The MegaWizard Plug In Manager generates an HDL file that you instantiate in your design You can also use a hybrid approach in which you instantiate the MegaWizard file in your HDL along with using the method described in Using the STP File to Create an Embedded Logic Analyzer on page 9 3 Creating the HDL Representation of the SignalTap Il Logic Analyzer The Quartus II software allows you to easily create your SignalTap II Logic Analyzer using the MegaWizard Plug In Manager To implement the SignalTap II megafunction follow these steps 1 Launch the MegaWizard Plug In Manager by choosing MegaWizard Plug In Manager Tools menu in the Quartus II software Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer 2 Select Create a new custom megafunction variation 3 Click Next 4 Choose the SignalTap II Logic Analyzer Select an output file type and enter the desired name of the SignalTap II megafunction You can choose AHDL tdf VHDL vhd or Verilog HDL v as the output file type 5 Click Next See Figure 9 4 Figure 9 4 Select an Output File and Enter the Selected SignalTap Il Name MegaWizard Plug In Manager page 2a Which megafunction would you like to customize Which device family will you be Stratix inc Z Select a megafunction from the list below To Installed Plug Ins Which type of output file do you want to create 2 Altera SOPC B
213. pting Support You can run procedures and make settings described in this chapter in a Tcl script You can also run some of these procedures at a command prompt For detailed information about specific scripting command options and Tcl API packages type quartus_sh qhelpata system command prompt to run the Quartus II Command Line and Tcl API Help utility For more information on Quartus II scripting support including examples refer to the Tcl Scripting and Command Line Scripting chapters of the Quartus II Handbook Generate NC Sim Simulation Output Files You can generate VO and SDO simulation output files with Tcl commands or at a command prompt For more information about generating VO and SDO simulation output files refer to Quartus II Simulation Output Files on page 3 18 Tel commands The following three assignments cause a Verilog HDL netlist to be written out when you run the Quartus II netlist writer The netlist has a 1ps timing resolution for the NC Sim Simulation software set global assignment name EDA OUTPUT DATA FORMAT VERILOG section id eda simulation set global assignment name EDA TIME SCALE 1 ps section id eda simulation set global assignment name EDA SIMULATION TOOL NC Verilog Verilog HDL output from Quartus II Altera Corporation August 2004 Use the following Tcl command to run the Quartus II netlist writer xecute module tool eda 3 29 Quartus II Handb
214. query to the specific device selected in the JTAG Chain Configuration section Altera Corporation August 2004 In System Updating of Memory amp Constants The In System Memory Content Editor can modify the contents of memory in a single device If you have more than one device containing in system configurable memories or constants in a JTAG chain you can launch multiple In System Memory Content Editors within the Quartus II software to access the memories and constants in each of the devices Instance Manager Scan the JTAG chain to update the Instance Manager with a list of all run time configurable memories and constants in the design The Instance Manager displays the Index Instance Status Width Depth Type and Mode of each element in the list You can read and write to in system memory using the Instance Manager as shown in Figure 11 2 Figure 11 2 Instance Manager Controls qe 0 ACAC lem 1 CNST m2 ACAC Read Data from In System Memory Continuously Read Data from In System Memory Stop In System Analysis Write Data to In System Memory Instance Manager Instance ID Not running 8 32 RAM ROM Read write Not running 8 il Constant Read Write Not running 8 32 RAM ROM Read Write Altera Corporation August 2004 The following buttons are provided in the Instance Manger M Read data from In System Memory reads the data from the device independently of the system clock a
215. r Retiming Routing an Internal Signal to an Output Pin ss Adjust the Phase Shift of a PLL to Meet I O Timing ss Correcting a Design Flaw Example Design Meeting I O Timing sisi Running the Quartus II Timing Analyzer Generating a Netlist for Other EDA Tools Generating a Programming Files sinus Conclusioni ai Chapter 11 In System Updating of Memory amp Constants OVERVIEW scita ira air ii 11 1 Device amp Megafuriction SUPPOSE E A aat 11 2 Creating In System Configurable Memory and Constants ii 11 3 Running the In System Memory Content Editor Instance Manager Making Changes viii Altera Corporation Contents Viewing Memory amp Constants in the Hex Editor ss 11 7 Programming the Device Using the In System Memory Content Editor 11 8 Conclusioni la 11 9 Section V Formal Verification RevisionElistory ana neha eatin ie E A E alien Section V 1 Chapter 12 Cadence Incisive Conformal Support Introduction siriani dalia nali saci dels oiddaa gives sale seriali 12 1 Formal Verification nia anale AA RI alive 12 1 Equivalence Checking s sisien naeia einai toys hein 12 1 Generating the VO File amp Incisive Conformal Script ss 12 2 Comparing Designs Using Incisive Conformal Software c cccccsessessseseesessesessessseseereesseeteneis 12 8 Black Boxes in the Incisive Conformal FloW 12 8 Running the Incisive Conformal Softwa
216. r and the SignalProbe features analyze internal device nodes and I O pins while operating in system and at system speeds The SignalTap II Logic Analyzer uses an embedded logic analyzer to route the signal data through the JTAG port to either the SignalTap II Logic Analyzer or an external logic analyzer or oscilloscope The SignalProbe feature uses incremental routing on unused device routing resources to route selected signals to an external logic analyzer or oscilloscope A third Quartus II software feature the Chip Editor can be used in conjunction with the SignalTap II and SignalProbe debugging tools to speed up design verification and incrementally fix bugs uncovered during design verification This section explains how to use each of these features This section includes the following chapters m Chapter 8 Quick Design Debugging Using SignalProbe m Chapter 9 Design Debugging Using the SignalTap II Embedded Logic Analyzer m Chapter 10 Design Analysis and Engineering Change Management with Chip Editor E Chapter 11 In System Updating of Memory amp Constants Altera Corporation Section IV 1 On Chip Debugging Quartus Il Handbook Volume 3 Revision Histo ry The table below shows the revision history for Chapters 8 to 11 Chapter s Date Version Changes Made 8 June 2004 v2 0 e Updates to tables figures e New functionality for Quartus 4 1 Feb 2004 v1 0 Initial release 9 June 2004 v2 0 e Update
217. ra A 12 24 CLK2 0 Clock Period 12 ns Multicycle 2 Multicycle Hold 2 In Figure 4 20 the circuit is intended to operate with a multicycle path of two however one of the data paths between the registers is less than one clock cycle tsy is measured at the second clock edge and ty is measured on the launch edge The data delay must be between 0 ns and 24 ns for circuit operation 4 22 Altera Corporation June 2004 Quartus Il Timing Analysis Multicycle Paths with Offsets In the example shown in Figure 4 21 c1k2 is offset from clk1 by 2 ns Figure 4 21 Multicycle Paths with Offsets Setup gt Hold gt CLK1 CLK2 CLK1 a a CLK2 12 24 Clock Period 12 ns Multicycle sa Offset 2 ns Altera Corporation June 2004 The setup time for c1k2 is 2 ns and the hold time is 10 ns Therefore the data delay must be between 10 ns and 2 ns It is unlikely that the design is intended to latch the data within 2 ns but it is probably intended to latch the data on the second c1k2 edge i e operate as a multicycle path of two If you set a Multicycle of 2 and Multicycle Hold assignment of 1 the setup requirement is 14 ns and the hold requirement is 2 ns as shown in Figure 4 22 The circuit operates as a multicycle path of two assuming the data delay between the registe
218. re Known Issues Limitations eat Conclusioni siasi diranno se negee NE Index Altera Corporation ix Quartus II Handbook Volume 3 x Altera Corporation N D TE YA Chapter Revision Dates The chapters in this book the Quartus II Handbook Volume 3 were revised on the following dates Where chapters or groups of chapters are available separately part numbers are listed Chapter 1 Mentor Graphics ModelSim Support Revised June 2004 Part number gii53001 2 0 Chapter 2 Synopsys VCS Support Revised June 2004 Part number gii53002 2 0 Chapter 3 Cadence NC Sim Support Revised August 2004 Partnumber qii53003 2 0 Chapter 4 Quartus IT Timing Analysis Revised June 2004 Part number gii53004 2 0 Chapter 5 Synopsys PrimeTime Support Revised June 2004 Part number gii53005 2 0 Chapter 6 Early Power Estimation Revised June 2004 Part number qii53006 2 0 Chapter 7 Simulation Based Power Estimation Revised June 2004 Part number gii53007 2 0 Chapter 8 Quick Design Debugging Using SignalProbe Revised June 2004 Part number gii53008 2 0 Chapter 9 Design Debugging Using the SignalTap II Embedded Logic Analyzer Revised June 2004 Part number gii53009 2 0 Altera Corporation xi Chapter Revision Dates Quartus Il Handbook Volume 3 Chapter 10 Design Analysis and Engineering Change Management with Chip Editor Revised June 2004 Part number qii53010 2 0 Chapter 11 In System
219. reports 3 worst paths of the t constraint only report timing clock filter clk0 This command will report one timing path per constraint related to clock domains whose names end with _c1k0 only The filtering can be further restricted by using more descriptive string matching like p110 c1k0 These clock names are not limited to absolute of relative clocks defined by the user but also include outputs of the PLLs report timing from inl to utopia This command will list all timing paths starting from input in1 to any registers or outputs that have utopia as part of their name report timing to out 4 This command will list all timing paths that end at bit 4 of the output bus out 4 0 Back slash has to preceed every bracket character and the string has to be enclosed in braces for proper interpretation Advanced scripting examplel package require quartus advanced timing project open lt project_name gt create timing netlist create p2p delays foreach in collection node get timing nodes type reg set reg name get timing node info info name node set location get timing node info info location node puts register reg name location location project_close This script reports all the registers in a design along with their respective locations on the chip 4 35 Quartus II Handbook Volume 3 4 36 Advanced scripting example2 package require quartus advanced timing proc spli
220. ring the board design and layout phase to estimate power and design for proper power management The simulation based power estimation feature in the Quartus II software when simulation vectors are available can verify that your design is within your power budget An Excel based power calculator which provides a current Icc and power P estimation based on typical conditions room temperature and nominal Vcc is available on the Altera websites for the Stratix Stratix GX and Cyclone devices under Design Utilities The power calculator is divided into sections with each section representing an architectural feature of the device including the clock network RAM blocks and digital signal processing DSP blocks You must enter the device resources operating frequency toggle rates and other parameters in the power calculator to estimate the device power consumption The sub total of the Icc and power consumed by each architectural feature is reported in each section in milliamps mA and milliwatts mW respectively Before reading this chapter you should be familiar with the Excel based Stratix Stratix GX or Cyclone power calculators available on the Altera website For more information about how to use the Excel based power calculator see the Estimating Power in Stratix Stratix GX and Cyclone Devices User Guide Figures 6 1 through 6 5 show sections of the Stratix power calculator 6 1 Quartus II Handbook Volume 3
221. routing resources are limited the Quartus II software may not be able to incrementally route your SignalTap II signal If you are running into a situation where the Quartus II software is not able to route your signal 9 21 Quartus II Handbook Volume 3 9 22 you can turn on the Modify latest fitting result during a SignalProbe Compilation option When this option is turned on the placement and routing of your existing design may change Time Bars and Next Transition Time bars enable you to calculate the number of clock cycles between two transitions for captured data in your system There are two types of time bars M Master Time Bar The Master Time Bar s label displays the absolute time of its location The captured data has only one master time bar however you can create an unlimited number of reference time bars that display the time relative to the master time bar M Reference Time Bar The Reference Time Bar s label displays time relative to the master time bar You can create an unlimited number of reference time bars To help you find a transition of a signal you can use either the Next Transition or the Previous Transition button Saving Captured Data The data log shows the history of captured data that is acquired with the SignalTap II Logic Analyzer and the triggers used to capture the data The analyzer acquires data stores it in a log and displays it as waveforms The default name for the log is base
222. rs is between 2 ns and 14 ns The following Tcl commands can be used to specify the multi cycle assignments shown in Figure 4 22 set multicycle assignment setup from clkl to clk2 end 2 set multicycle assignment hold from clkl to clk2 end 1 4 23 Quartus Il Handbook Volume 3 Figure 4 22 Hold Requirements Setup _ gt Hold gt CLK2 2 Multicycle Hold 1 Multicycle 4 24 Multicycle Paths Across Multi Frequency Domains Figure 4 23 is a timing diagram representing data traveling from a fast clock domain to a slow clock domain with an offset between the clock edges Since data is transferring from a fast clock domain to a slow clock domain it has to stay stable for at least two source clock cycles otherwise the data is lost Without a Multicycle assignment the Timing Analyzer calculates a data setup requirement of 2 ns the value of the offset between the two clocks The Multicycle assignment of 2 relaxes the setup requirement by extending it to the next destination clock edge Figure 4 23 Multicycle Hold Checks Setup gt Hold Check 1 D Hold Check 2 CLK1 SE dre CLK2 Clock 1 Period 6 ns Clock 2 Period 12 ns Offset 2ns Multicycle There are two hold relationships that the Timing Analyzer checks for multicycle paths in m
223. rtus Il Handbook Volume 3 Counter high Counter low Counter PH Counter initial Counter time delay Adjusting the Duty Cycle Use the following equations to adjust the duty cycle of individual output clocks High Counter High Counter High Counter Low Low Counter Low Counter High Counter Low Adjusting the Phase Shift Use the following equations to adjust the phase shift of an output clock of a PLL Phase Shift VCO Period 1 8 VCO Tap VCO Init VCO Period Normal Mode VCO Tap Counter PH M VCO Tap VCO Init Counter Initial M Initial VCO Period In Clock Period N M External Feedback Mode VCO Tap Counter PH M VCO Tap VCO Init Counter Initial M Initial VCO Period In Clock Period N M Counter High Counter Low Adjusting the Output Clock Frequency Use the following equations to adjust the output clock of a PLL Normal Mode OUTCLK INCLK M N Counter High Counter Low 10 22 Altera Corporation June 2004 Change Manager Change Manager Altera Corporation June 2004 External Feedback Mode OUTCLK INCLK M Counter High Counter Low N Counter High Counter Low You can adjust all the output clocks by modifying the M and N values You can adjust individual output locks by modifying the Counter High and Counter Low values Adjusting the Spread Spectrum Use the following equation to adjust the spread spectrum for your PLL
224. s II installation directory gt eda sim lib Model Technology ModelSim software users must use the files provided with the Quartus II software Simulating VHDL Designs The following provides step by step instructions for performing gate level timing simulation for VHDL designs Le The following steps assume you have already created a ModelSim project For additional information see Altera Design Flow with ModelSim Altera Software on page 1 3 Create Simulation Libraries If you are using the Model Technology ModelSim software version create the gate level simulation libraries and correctly link them to your design Ls This process is not required for the ModelSim Altera version because a set of pre compiled libraries are created when you install the software 1 Select New Library File menu 2 Inthe Create a New Library dialog box select a new Library and a logical linking to it 3 Enter in the name of the newly created library in the Library Name box 4 Click OK vlib stratixii vmap stratixii stratixii 1 15 Quartus II Handbook Volume 3 Compile Simulation Models into Simulation Libraries gt This process is not required for the ModelSim Altera version because a set of pre compiled libraries are created when you install the software 1 Select Add to Project File menu then select Existing File 2 Browse to the lt quartus installation folder gt eda sim_lib gt and add the necessary ga
225. s II software and other EDA simulation tools follow the steps below 1 Choose EDA tool settings Assignments menu 2 Inthe EDA tools Settings dialog box under the Category list open EDA Tool Settings and select Simulation Altera Corporation June 2004 Estimating Power with EDA Simulation Tools 3 In the Simulation dialog box choose the appropriate EDA simulation tool from the Tool name list 4 Turn on Generate Power Input File see Figure 7 4 Figure 7 4 EDA Tool Settings Window x Category Files f User Libraries Specify options for generating output files for use with other EDA tools Device Timing Requirements amp Options l El E EDA Tool Settings Tool name NC Verilog Verilog HDL output from Quartus II Design Entry amp Synthesis JT Run this tool automatically after compilation Simulation Timing Analysis E Board Level Time scale 1 ps hd Formal Verification F Ma DIL characters this option creates VHDL 1587 complent names Resynthesis TT Map illegal Verilog HDL characters Compilation Process z I Truncate long hierarchy paths E Analysis amp Synthesis Settings E Fitter Settings T Flatten buses into individual nodes Timing Analyzer T Dutput Excalibur stripe as a single module Design Assistant SignalT ap ll Logic Anal M Generate Power Input File ignalT ap Il Logic Analyzer 3 dai SignalProbe Settings TT Bring out device wide set reset signals as ports S
226. s for the Status column Table 8 1 Status Values Status Description Routed Connected and routed successfully Not Routed Not enabled Failed to Route Failed routing during last SignalProbe compilation Need to Compile Assignment changed since last SignalProbe compilation You can find source to output delays for each routed SignalProbe pin in the SignalProbe Source to Output Delays page under Timing Analyzer in the Compilation Report window see Figure 8 5 Figure 8 5 SignalProbe Source to Output Delays Page in the Compilation Report Window Compilation Report alPr Output De SE Legal Notice Source Name Pin Location Pin Name Enable Status Delay ns GE Flow summary Me Png Tectpont _ On Fouted SES Flow Settings inst5 7 Test_point3 On Routed 5 265 ns oe Mme inst5 4 Pin_11 Test_point2 On Routed 5 214 ns AI 00 Analysis amp Synthesis 0 Fitter 0 Assembler SX Timing Analyzer 4s Timing Analyzer Settings am Timing Analyzer Summary EB Clock Settings Summary ER Clock Setup clk SEA tsu SER tco SEA tod 4h SignalProbe Source to Output Delays SER th El E E u Scri pti ng You can run procedures and make settings described in this chapter in a Tcl script You can also run some of these procedures at a command Su p p 0 rt prompt For detailed information about specific scripting command options and Tcl API packages type quartus
227. s tab Click Add server 4 Inthe Add Server dialog box see Figure 9 18 type the network name or IP address of the server you want to use and the password for the JTAG server created on the Remote PC Figure 9 18 Add Server Dialog Box CESSE x Server Name labcomputer altera com ro Server Password Cancel 5 Click OK Altera Corporation 9 27 June 2004 Quartus Il Handbook Volume 3 9 28 SignalTap Il Setup Local PC 1 Select the hardware by clicking the Hardware Setup tab and choosing the hardware on the Remote PC See Figure 9 19 Figure 9 19 SignalTap Il Hardware Setup x Hardware Settings staG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window Currently selected hardware ByteBlaster on sj mmac2000 LPT1 Available hardware items Select Hardware Hardware Sever Port ByteBlaster Local LPT1 Add H ByteBlaster simmac2000 LPTI _AddHerdware _ Remove Hardware 2 Click Close 3 Program the PCB in the remote location using the TCP IP link and the hardware on the remote PC Signal Preservation Many of your RTL signals may be optimized during the process of synthesis and place and route This may lead to issues when you are attempting to debug your design because the post fitting signal names differ significantly from your RTL n
228. s to tables figures e New functionality for Quartus 4 1 Feb 2004 v1 0 Initial release 10 June 2004 v2 0 e Updates to tables figures e New functionality for Quartus 4 1 Feb 2004 v1 0 Initial release 11 Aug 2004 v1 1 Minor typographical corrections June 2004 v1 0 Initial release Section IV 2 Altera Corporation 8 Quick Design Debugging AND E RYA Using SignalProbe qii53008 2 0 Introduction Using SignalProbe Altera Corporation June 2004 Hardware verification can be a lengthy and expensive process The SignalProbe incremental routing feature can help reduce the hardware verification process and time to market for System On a Programmable Chip SOPC designs Easy access to internal device signals is important in the debugging of a design The SignalProbe feature enables efficient design verification by allowing you to quickly route internal signals to I O pins without affecting the design Starting with a fully routed design you can select and route signals for debugging to either previously reserved or currently unused I O pins The SignalProbe feature supports the MAX II Stratix Stratix GX Cyclone APEX II APEX 20KE APEX 20KC APEX 20K and Excalibur devices You can accomplish the same functionality with the Chip Editor as with SignalProbe For more information about using the Chip Editor to perform SignalProbe functionality see the De
229. s using a file named cds lib The cds lib file is an ASCII text file that maps logical library names e g your working directory or the location of resource libraries such as models for LPM functions to their physical directory paths When you launch an NC tool the tool reads cds lib to determine which libraries are accessible and where they are located NC tools include a default cds lib file which you can modify for your project settings You can use more than one cds lib file For example you can have a project wide cds lib file that contains library settings specific to a project e g technology or cell libraries and a user cds lib file The following sections describe how to create edit a cds lib file including M Basic Library Setup m LPM Function amp Altera Megafunction Libraries Basic Library Setup You can create cds lib with any text editor The following examples show how you use the DEFINE statement to bind a library name to its physical location The logical and physical names can be the same or you can select different names The DEFINE statement usage is DEFINE lt library name gt lt physical directory path gt For example a simple cds lib for Verilog HDL contains the lines DEFINE lib std usrl libs std lib DEFINE worklib worklib Using Multiple cds lib Files Use the INCLUDE or SOFTINCLUDE statements to reference another cds lib file within a cds lib file The syntax is
230. se Paths caio alora Fixing Hold Time Violations Timing Analysis Across Asynchronous Domains i 4 32 Minimum Timing Analysis iii iaia Minimum Timing Analysis Settings Performing Minimum Timing Analysis ss 4 33 Minimum Timing Analysis Reporting ss 4 34 Third Party Timing Analysis Software Advanced Timing Analysis amp Reports Using Tcl Scripts iii 4 34 CONCLUSIONI sissi E E EEEE A E EN E aa 4 37 Chapter 5 Synopsys PrimeTime Support MVE C OCC 1101 0 eea a A CR CT aa 5 1 Quartus II Settings to Generate PrimeTime Files ss 5 1 Files Generated for the PrimeTime Environment psican A E E EE E Eaa E aE 5 2 Sample of Constraints Specified in PrimeTime Format 5 4 PrimeTime Timing Reports siasi al dn el e wala Bie EEEE EES 5 4 Sample PrimeTime Timing Report 5 5 Running Primetime sith ae ana 5 6 Altera Corporation v Quartus II Handbook Volume 3 Conclusioni ascii aaa 5 6 Section III Power Estimation amp Analysis Revision History aaa Section IH 1 Chapter 6 Early Power Estimation Introductioni afai eta ea aa Excel Based Power Calculator asian Estimating Power in the Design Cycle Q artus il Power Report File i liana Conclusioni siii iano iaia References crei Chapter 7 Simulation Based Power Estimation Introduction ss E T EEE Power Estimation in the Quartus II Software i Estimating Power with
231. selected node names to the Selected Nodes list click gt 8 To insert the selected nodes in the STP file click OK Specifying the Sample Depth The sample depth specifies the number of samples that are stored for each signal To set the sample depth select the desired number of samples in the Sample Depth list The sample depth ranges from 0 zero to 128K samples Triggering the Analyzer To control how the analyzer is triggered set the trigger type and number of trigger levels Trigger Type Basic or Advanced If Trigger Type is set to Basic you must set the Trigger Pattern for each signal in the STP file The Trigger Pattern can be set to any of the following Don t Care Low High Falling Edge Rising Edge Either Edge Data capture begins when the logical AND of all the signals for a given level evaluates to TRUE If Trigger Type is set to Advanced you must build an expression that will be used to trigger the analyzer 9 6 Altera Corporation June 2004 Design Debugging Using the SignalTap Il Embedded Logic Analyzer Altera Corporation June 2004 For more information on trigger types see Creating Complex Triggers on page 9 14 Number of Trigger Levels The multiple Trigger Level feature gives you precise accuracy over the trigger condition that you build This allows for more complex data capture commands to be given to the logic analyzer providing greater accuracy and problem isolation You c
232. sh qhelp at a system command prompt to run the Quartus IT Command Line and Tcl API Help utility Altera Corporation 8 9 June 2004 Quartus II Handbook Volume 3 8 10 For more information on Quartus II scripting support including examples refer to the Tcl Scripting and Command Line Scripting chapters of the Quartus IT Handbook Reserving SignalProbe Pins Use the following Tcl commands to reserve a SignalProbe pin For more information about reserving SignalProbe pins see Reserving SignalProbe pins on page 8 2 set location assignment lt location gt to lt SignalProbe pin name gt set instance assignment name RESERVE PIN AS SIGNALPROBE OUTPUT to lt SignalProbe pin name gt Valid locations are pin location names such as Pin_A3 Adding SignalProbe Sources Use the following Tcl commands to add SignalProbe sources For more information about adding SignalProbe sources see Adding SignalProbe Sources on page 8 3 The following command assigns the node name to a SignalProbe pin set instance assignment name SIGNALPROBE SOURCE lt node name gt to lt SignalProbe pin name gt The next command enables the SignalProbe routing You can disable individual SignalProbe pins by specifying OFF instead of ON set instance assignment name SIGNALPROBE ENABLE ON to lt SignalProbe pin name gt Assigning 1 0 Standards Use the following Tcl command to assig
233. shows tco for all output pins tsy and ty for all input pins and tpp for any pin to pin combinational paths in the design A positive slack indicates the margin by which the path surpasses the clock timing requirements A negative slack indicates the margin by which the path fails the clock timing requirements If a design contains individual tsy ty or tco assignments and does not contain global tsu ty or tco assignments only the individual assignments are reported in the timing analysis reports If a design contains individual tsy ty Or tco assignments and you need a timing report for tsy ty or tco Altera Corporation June 2004 Quartus Il Timing Analysis on all I O pins you must set global tsy ty or tco assignments to generate a timing report on the pins not specified by the individual timing assignments Advanced The Quartus II software performs timing analysis of designs containing s paths that cross clock domains and designs that contain multicycle paths Ti ming Analysis This section describes these advanced features arr For detailed instructions on how to use these or any of the Quartus II Timing Analyzer features see the Quartus II Help Clock Skew This section describes some common cases in which clock skew may result in incorrect circuit operation Derived Clocks Clock skew error reporting may occur in designs containing derived clocks and very short register to register data paths An example of this
234. sign Analysis and Engineering Change Management with Chip Editor chapter in Volume 3 of the Quartus IT Handbook You can use the SignalProbe compilation to incrementally route internal signals to reserved output pins This process completes in a fraction of the time required by a full design recompilation The incremental routing does not affect source behavior or design operation Follow the steps below to use the SignalProbe incremental routing feature 1 Reserve SignalProbe pins prior to initial compilation 2 After initial compilation determine which nodes you want to route to the reserved SignalProbe pins 3 Assign an I O standard to the SignalProbe pins 4 Add registers for pipelining of signals if necessary 5 Perform a SignalProbe compilation 8 1 Quartus Il Handbook Volume 3 6 Understand the results of the SignalProbe compilation Reserving SignalProbe pins You can reserve an unused pin as a SignalProbe pin before you route an internal signal out of your device You can reserve your SignalProbe pins before or after a compilation To ensure that a pin is available for your SignalProbe pin and not to another unassigned user I O pin reserve the SignalProbe pin before a compilation You may only need a few SignalProbe pins since you can easily reassign different sources to your SignalProbe pins To reserve an unused I O pin as a SignalProbe pin perform the following steps 1 Click Assign SignalPr
235. sign with either the Quartus II Simulator or another EDA vendor s simulation tool Generating a Netlist for Other EDA Tools When you use the Chip Editor it may be necessary to verify the functionality using an Altera supported simulation tool and or verify timing using an Altera supported timing analysis tool You can run the Netlist Writer to generate a gate level netlist that allows you to perform simulation or timing analysis in an EDA simulation or timing analysis tool of your choice Generating a Programming File Once you have performed simulation and timing analysis and are confident that the changes meet your design requirements you can generate a programming file with the Quartus II Assembler You use the programming file to implement your design in an Altera device 10 33 Quartus Il Handbook Volume 3 Conclusion 10 34 As the time to market pressure mounts it is increasingly important to be able to produce a fully functional design in the shortest amount of time To address this challenge Altera developed the Quartus II Chip Editor The Chip Editor enables you to modify the post place and route properties of your design Specifically you can change certain key properties of the LE I O element and PLL resources Most importantly changes made with the Chip Editor do not require a full recompilation eliminating the lengthy process of RTL modification resynthesis and another place and route cycle In summary t
236. signment to assign a previously created individual clock requirement to a pin or node in the design The Timing Wizard makes this assignment automatically Altera Corporation June 2004 Quartus Il Timing Analysis Input Maximum Delay Use this timing assignment to specify the maximum allowable delay of a signal from an external register outside the device to a specified input or bidirectional pin The value of this assignment usually represents the tco of the external register feeding the input pin of the Altera device plus the actual board delay Conversely you can set the minimum allowable delay with the Input Minimum Delay assignment Figure 4 8 shows a block diagram of the input delay For example input maximum delay of 2ns can be set on a predefined group called input_pins by using max option Timegroup command is used to gather signal names by using wild card into a group for timing assignment purpose as shown in the example timegroup input pins add member i add exception ibus set_input delay clk ref clk to input pins max 2ns The assignments created or modified during an open project are not committed to qsf file unless the export assignments command is explicitly executed Ifa close project command is executed the assignments are committed into the qsf also Figure 4 8 External Input Delay External Device Altera Device tinal External Input Delay Alter
237. sion Dates xi About this Handbook Li xiii How to Contact Altera mbare a A RAEE A A a xiii Typographic Conventions ulcera xiii Section Simulation Revision History laid Section I 1 Chapter 1 Mentor Graphics ModelSim Support INTTOAUCHoni scialli aiar BACKETOUNE EE nn aa Software Compatibility u iii Altera Design Flow with ModelSim Altera Software Functional RTL Simulation i Gate Level Timing Simulation n Functional RTL Simulation iii Functional RTL Simulation Libraries Simulating VHDL Designs Simulating Verilog Designs Gate Level Timing Simulation cuccia Quartus II Software Output Files for use in the ModelSim Altera Software Gate Level Simulation Libraries Simulating VHDL Designs Simulation Verilog Designs iui Using the NativeLink Feature with ModelSim ss 1 19 Software Licensing amp Licensing Set Up LM LICENSE FILE Variable 2 55 E al nua Conclusioni uan ea ansia Chapter 2 Synopsys VCS Support Introduction lac lA aiar 2 1 Software Requirements iii 2 1 Using VCS in the Quartus II Design FlOW sens 2 1 Functional RTL Simulations Post Synth sis Simulation aci Gate Level Timing Simulation cca 2 6 Altera Corporation iii Quartus Il Handbook Volume 3 C mmon VCS Compil
238. sis page of the Settings dialog box Assignment menu The Quartus II Timing Analyzer generates a Verilog or VHDL netlist a sdo file and a Tel script that you can specify in the PrimeTime software to perform timing analysis Two frequently used commands are E project open lt project_name gt To open the project in the project directory create timing netlist To generate timing information from a compiled design in the project directory report timing command gives you more control over how you want to report your timing analysis results Usage report timing reuse delays npaths lt number gt tsu th tco tpd min tco min tpd clock setup clock hold clock setup io clock hold io clock setup core clock hold core dqs read capture stdout file lt name gt append from lt names gt to lt names gt clock filter lt names gt longest paths shortest paths all failures Examples report timing file lt file_name gt Altera Corporation June 2004 Quartus Il Timing Analysis Altera Corporation June 2004 This command writes out worst timing path one for each of the tt too minimum t o clock setup and clock hold timing reports based on worst case delay models into a text file called file_name report timing npaths 2 file file name This command writes out 2 timing paths for each of the constraints in file name report timing tsu npaths 3 This command
239. software from either a system command prompt or using the graphical user interface GUI using the CTC script generated by the Quartus II software Running the Incisive Conformal Software From a System Command Prompt To run the Incisive Conformal Software from a system command prompt type the following lec dofile lt path to project directory gt v conformal lt design_name gt ctc nogui Running the Incisive Conformal Software from the GUI To run the Incisive Conformal software using the GUI do the following 1 Select Do Dofile File menu 2 Select the file lt path to project directory gt fv conformal lt design gt cte The Incisive Conformal GUI displays results as shown in Figure 12 6 The original VOM netlist is displayed in the Golden window and the Quartus II generated VOM netlist is displayed in the Revised window The status bar at the bottom of the window reports verification results including the number of compared D Type Flip Flops DFFs and Primary Outputs POs as well as the number of DFFs and POs that are equivalent and non equivalent respectively 12 9 Quartus II Handbook Volume 3 Figure 12 6 Incisive Conformal Software GUI Display of Functional Comparisons x Eile Setup Report Tools LTX Preferences Window Help aa E Setup LEC Golden miZc Revised miZc mi2c a mi2c E3 primitives E 10 primitives 5 A_in_O_ apex20ke_io_reg_source_mode18
240. sport_path_delays Use this switch when the pulses in your simulation may be shorter than the delay within a gate level primitive For this option to work you must also include the pulse_e number and pulse_r number compile time options transport_int_delays Use this switch when the pulses in your simulation may be shorter than the interconnect delay between gate level primitive For this option to work you must also include the pulse_int_e number and pulse_int_r number compile time options cS For more information on either of these switches refer to the VCS User Guide installed with the tool The following VCS command describes the command line syntax to perform a post synthesis simulation with the device family library vcs R lt testbench v gt lt gate level netlist vo gt v lt altera device family library v gt transport int delays pulse int e 0 pulse int r 0 transport path delays pulse e 0 pulse r 0 The VCS software has a set of switches that help you simulate your design Table 2 4 lists some of the switches that are available Table 2 4 Device Family Library Files Library Description R Runs the executable file immediately RI Once the compile has completed instructs the VCS software to automatically launch VirSim v lt library filename gt Specifies a Verilog library file i e 220model v or alteramf v The VCS software looks in this file for module definitions that are found
241. standard LVTTL Pinname SignaFrobe pnt OOOO El SimaPrbesouce El MW Reserve pin even if it does not exist in the design file s SignalProbe output El Registers TT SignalProbe enable tek SL Change Delete Enable All SignalProbe Routing Disable All SignalProbe Routing DK Cancel Adding SignalProbe Sources A SignalProbe source is a signal in the post compilation design database with a possible route to an output pin You can assign a SignalProbe source to a SignalProbe pin an unused output pin or a reserved output pin by performing the following steps 1 Altera Corporation June 2004 Click Assign SignalProbe Pins on the SignalProbe Settings page of the Settings dialog box Assignments menu In the Available Pins amp Existing Assignments list select the pin number for the pin to which you want to add a SignalProbe source The pin must be a reserved SignalProbe pin an unused output pin or a reserved output pin Browse to a SignalProbe source The Node Finder dialog box appears when you click Browse and automatically selects SignalProbe in the Filter list see Figure 8 2 Click List to view all the available SignalProbe sources If you cannot find a specific node with the SignalProbe filter then the node has been either removed by the Quartus II software during optimization or placed somewhere in the device where there are no possible routes to a pin 8 3 Quartus Il Hand
242. t time a set pieces split a if string equal ps lindex pieces 1 set time expr 1000 lindex pieces 0 else set time lindex pieces 0 return time project_open lt project_name gt create_timing_netlist create p2p delays foreach_in_collection node get_timing_nodes type reg set reg name get timing node info info name node set delays from clock list get delays from clocks node set delays from clock lindex delays from clock list 0 set clock node id lindex delays from clock 0 set fanin get timing node fanin type clock clock node id set pll delay list lindex fanin 0 set pin to pll list lindex get timing node fanin type clock lindex pll delay list 0 0 set sum of delays expr split time lindex pll delay list 1 split time lindex pll delay list 2 split time lindex pin to pll list 2 set clock name get timing node info info name lindex delays from clock 0 set longest lindex delays from clock 1 set shortest lindex delays from clock 2 puts gt clock is clock name puts gt register name reg name puts gt total clock pin to reg delay expr sum of delays split time longest ns project_close This script starts with traversing through a list of all the registers in a design by using get_timing nodes type reg command The script then uses a for each loop to trace the clock path back to the input clock pin Using t
243. te level simulation files to your project 3 Select the simulation model file and select Properties View menu 4 Set the Compile to Library to the correct library vcom work altera mf lt quartus installation folder eda sim_lib stratixii_components vhd gt vcom work altera mf lt quartus installation folder eda sim_lib stratixii vhd gt Compile Testbench and VHO into Work Library 1 Choose Compile All Compile menu or click the Compile All toolbar icon 2 Resolve any compile time errors before proceeding to Loading the Design vcom work work lt my_testbench vhd gt lt my_vhdl_output_file vho gt Loading the Design 1 Select Simulate Simulate menu 2 Click the SDF tab and click Add 3 Specify the location of the SDF file and click OK 4 Inthe Library list Design tab select the work library 5 Expand the work library in the Simulate dialog box 6 Select the top level design unit your testbench and select OK in the Simulate dialog box vsim sdftyp work lt my_testbench gt Running the Simulation 1 Choose Signals and Wave View menu 1 16 Altera Corporation June 2004 Gate Level Timing Simulation Altera Corporation June 2004 view signals view wave 2 Drag signals to monitor from the Signals window and drop them into the Wave window add wave lt signal name gt 3 At the prompt type the following run lt time period gt Simulation Verilog Designs The
244. tera software through a parallel port software guard T guard FIXEDPC license or a network FLOATNET or FLOATPC license Each Altera software subscription includes a license to either VHDL or Verilog HDL Network licenses with multiple users may have their licenses split between VHDL and Verilog HDL in any ratio USB is not supported Obtain licenses for ModelSim Altera software from the Altera web site at www altera com Get licensing information for Model Technology s ModelSim directly from Model Technology See Figure 1 2 for the set up process sa For ModelSim Altera versions prior to 5 5b use the PCLS utility included with the software to set up the license Figure 1 2 ModelSim Altera Licensing Set up Process Initial installation ModelSim Altera properly licensed Set the LM_LICENSE_FILE variable Y gt Finish LM_LICENSE_ FILE Variable Altera recommends setting the LM LICENSE FILE environment variable to the location of the license file Using the ModelSim Altera simulation software within the Altera FPGA design flow enables Altera software users to easily and accurately perform functional and timing simulation on their designs Proper verification of designs at the functional and post place and route stages using the ModelSim Altera software helps ensure design functionality and success and ultimately a quick time to market Altera Corp
245. the LE Mm ALM utilization information You can view how an adaptive logic module ALM is configured within your design For example you can view which ALM inputs are used if the ALM utilizes the registers the upper LUT the lower LUT or all of them You can also view the signal flow through the ALM Mm I O utilization information You can view how the device I O resources are used For example you can view what components of the I O are used if the delay chain settings are enabled and the signal flow through the I O 10 1 Quartus II Handbook Volume 3 Using the Chip Editor in Your Design Flow 10 2 Mm PLL utilization information You can view how a phase locked loop PLL is configured within your design For example you can view which control signals of the PLL are used along with the settings for your PLL With the Chip Editor you can modify the following elements within the Altera device M Logic elements M I O cells E Phase locked loops PLL Le With the Chip Editor you can view the contents of an ALM and its implementation but you cannot edit its properties For more information on the Change Manager see Change Manager on page 10 23 The Chip Editor can be used with the following device families Stratix II Stratix Stratix GX Cyclone MAX I An ideal design flow starts by developing the design specification creating register transfer level RTL code that describes the design spe
246. the compilation Altera Corporation June 2004 Using VCS in the Quartus Il Design Flow Altera Corporation June 2004 Table 2 2 summarizes the Verilog library files that are required to compile library of parameterized modules LPM functions and Altera megafunctions Table 2 2 Altera Verilog Functional Behavioral Simulation Library Files Library File Description altera_mf v Libraries that contain simulation models for Altera megafunctions stratixgx_mf v 1 Libraries that contain simulation models for Stratix GX devices 220model v Libraries that contain simulation models for Altera LPM functions version 2 2 0 sgate v Libraries that contain simulation models for Altera IP Note to Table 2 2 1 When performing a functional RTL simulation of StratixGX design you will need to compile the stratixgx_mf v sgate v amp 220model v The files in Table 2 2 are installed with a Quartus II installation You can find these files in the lt path to Quartus II installation gt eda sim_lib directory The following VCS command describes the command line syntax to perform a functional simulation with a pre existing library ves R lt test bench gt v lt design name gt v v lt Altera library file gt v Functional RTL Simulation with Altera Memory Blocks The VCS software supports functional simulation of complex Altera memory blocks such as 1pm_ram dp and altsyncram You can create thes
247. the power calculator can be made to reflect the device resources used in the final Altera Corporation June 2004 When the FPGA design is complete the device power consumption can be estimated with the simulation based power estimation feature in Quartus II The Quartus IT Simulator provides simulation based power estimation for Stratix Stratix GX Cyclone HardCopy Stratix MAX 7000AE MAX 7000B and MAX 3000A devices To use the power estimation feature you must provide a Vector Waveform File vwf or Power Input File pwf to the Quartus IT Simulator and perform a timing simulation For more information about how to use the simulation based power estimation feature in the Quartus II software see the Simulation Based Power Estimation chapter in Volume 3 of the Quartus II Handbook 6 5 Quartus Il Handbook Volume 3 Table 6 3 shows the power estimation flow for the simulation based power estimation feature in the Quartus II software when the FPGA design is complete Table 6 3 Power Estimation When FPGA Design Is Complete Steps to follow Advantages Disadvantages 1 Compile the FPGA design in Provides the most accurate power Power Estimation done later in the Quartus Il estimation since the simulation FPGA design cycle 2 Create the stimulus for simulation stimuli reflect actual device behavior 3 Simulate the design using simulation tool power estimation results Quartus Il
248. ties Ls This process is not required for the ModelSim Altera version because a set of pre compiled libraries are created when you install the ModelSim Altera software Compile Simulation Models into Simulation Libraries Ls The following steps are not required for the ModelSim Altera software Choose Add to Project File menu and select Existing File Browse to the lt quartus installation folder gt eda sim_lib gt and add the necessary simulation model files to your project Select the simulation model file and select Properties View menu Set the Compile to Library to the correct library Altera Corporation June 2004 Functional RTL Simulation Altera Corporation June 2004 sa The altera_mf v should be compiled into the altera_mf library Compile the 220model v into the lpm library vlog work altera mf lt quartus installation folder eda sim_lib altera_mf v gt vlog work lpm lt quartus installation folder eda sim_lib 220model v gt Compile Testbench and Design Files into Work Library 1 Select Compile All Compile menu or click the Compile All toolbar icon 2 Resolve compile time errors before proceeding to Loading the Design below vlog work work lt my_testbench v gt lt my_design_files u gt Loading the Design 1 Select Simulate Simulate menu 2 Click the Libraries tab in the Load Design dialog box 3 In the Search Libraries box click Add 4 Specify the location to the lpm
249. tion Using SignalTap Il in a Lab Environment You can install a stand alone version of the SignalTap II Logic Analyzer This version of SignalTap II is particularly useful in lab environments where you may not have a workstation that meets the requirements for a complete Quartus II installation or you do not have a license for a full installation of the Quartus II software The stand alone version of the SignalTap II Logic Analyzer is included with the Quartus II stand alone Programmer and is available from the Downloads page of the Altera web site Another useful feature that is part of the SignalTap II interface in the Quartus II software is the SRAM Object File SOF Manager This feature allows you to archive multiple SOFs that have different SignalTap II configurations into one STP file For more information on how to use this feature refer to the Quartus II help Remote Debugging Using SignalTap Il You can use a SignalTap II Logic Analyzer to debug a design that is running on a PCB in a remote location To perform this debugging session you need the following setup Quartus II software installed on the local PC Stand alone SignalTap II installed on the remote PC Programming hardware connected to the PCB at the remote location TCP IP connection 9 25 Quartus Il Handbook Volume 3 9 26 Equipment Setup 1 On the PC in the remote location install the stand alone version of the SignalTap II Logic Analyzer This remote
250. to this pin independently from the design You must ensure that a clock signal on your PCB drives the acquisition clock Assigning Signals to the STP File You can assign the following two types of signals to your STP file Pre synthesis A pre synthesis signal exists after design elaboration but before any synthesis optimizations are done by physical synthesis This set of signals should reflect your Register Transfer Level RTL signals Post fitting A post fitting signal exists after physical synthesis optimizations and place and route I To add only pre synthesis signals to your STP file select Start Analysis amp Elaboration Processing menu This is particularly useful if you want to quickly add a new node name after you have made design changes Assigning Data Signals To assign data signals follow these steps 1 2 Altera Corporation June 2004 Perform analysis and elaboration or analysis and synthesis or compile your design In the SignalTap II Logic Analyzer window click the Setup tab 9 5 Quartus Il Handbook Volume 3 3 Double click in the STP window to launch the Node Finder 4 Select SignalTap II pre synthesis or SignalTap II post fitting in the Filter list 5 Inthe Named box enter a node name partial node name or wildcard characters To start the node name search click List 6 Inthe Nodes Found list select the node or bus you want to add to the STP file 7 To copy the
251. transfers it into the Excel based power calculator If you do not want to use the macro you can also transfer the data into the Excel based power calculator manually If your existing Quartus II project represents only a portion of your full design you should manually enter in the additional resources that are used in the final design Therefore after importing the power estimation file information into the Excel based power calculator you can edit it to add in additional device resources For completed designs see the Simulation Based Power Estimation chapter in Volume 3 of the Quartus II Handbook The power calculator is an easy and useful tool to estimate the power consumption for your designs based on typical conditions The power estimation file generated by the Quartus II software helps to fill in the Excel based power calculator available on the Altera website Board level and FPGA designers can benefit from the power estimation report file generated by the Quartus II software to more accurately estimate power Estimating Power in Stratix Stratix GX and Cyclone Devices User Guide Altera Corporation June 2004 qii53007 2 0 7 Simulation Based Power Estimation Introduction Altera Corporation June 2004 After completing the design synthesis and place and route steps in the design cycle you should use the Simulator in the Quartus II software to perform a simulation to verify design functionality The simulation s
252. ttings branch to show the settings Choose the Simulation setting The Simulation page appears as shown in Figure 3 8 In the Simulation page select NC Verilog Verilog HDL output from Quartus II or NC VHDL VHDL output from Quartus II in the Tool name list See Figure 3 8 Click OK Choose Start Compilation Processing menu During compilation the Quartus II software automatically creates the directory simulation ncsim which contains the VO VHO and SDO files for timing simulation Figure 3 8 Quartus Il EDA Tool Settings Category Lo x Files User Libraries Specify options for generating output files for use with other EDA tools Device im DA 2 Timing Requirements amp Options EDA Tool Settings Design Entry amp Synthesis Tool name KS I Run this tool automatically after compilation g HDL output from Quartus Il Simulation Timing Analysis Board Level Time scale 1 ps X Formal enastar IT Map ilegal VHDL characters this option cre ie Resynthesis Compilation Process Analysis amp Synthesis Settings Fitter Settings Physical Synthesis Optimizations Timing Analyzer Design Assistant SignalT ap Il Logic Analyzer SignalProbe Settings Simulator Software Build Settings HardCopy Settings IT Map illegal Verilog HDL characters TT Truncate long hierarchy paths T Flatten buses into individual nodes I Output Excalibur stripe as a single module I Generate Po
253. tware For more information on estimating power with EDA simulation tools refer to Estimating Power with EDA Simulation Tools on page 7 4 set global assignment name EDA GENERATE POWER INPUT FILE ON section id eda simulation Use the following Tcl command to specify the PWF to be used as an input by the Quartus II software to estimate the power consumption of the design set global assignment name VECTOR INPUT SOURCE lt file name gt pwf Conclu si on The simulation based power estimation feature in the Quartus II software is an easy and useful tool to estimate the power consumption for your designs based on typical conditions You can use this feature in the Quartus II software and other EDA simulation tools to estimate power and verify that their design is within their power budget References Mm Estimating Power in Stratix Stratix GX and Cyclone Devices User Guide 7 8 Altera Corporation June 2004 Section IV On Chip JANOS RYA Debugging Debugging today s FPGA designs can be a daunting task As your product requirements continue to increase in complexity the time you spend on design verification continues to rise To get your product to market as quickly as possible you must minimize design verification time To help alleviate the time to market pressure you need a set of verification tools that are powerful yet easy to use The Quartus II software SignalTap II Logic Analyze
254. uffer Acquisition The Buffer Acquisition feature in SignalTap II Logic Analyzer allows you to significantly reduce the amount of memory that is required for SignalTap II data acquisition This feature makes it easier to debug systems that contain relatively infrequent periodic events An example of this type of system is shown in Figure 9 15 Figure 9 15 Example System Generating Periodic Events Stratix Device Reference Design Top Level File SRAM Interface Signals 1 A 17 0 WADDR 17 0 li i 117 0 RADDR 17 0 LD e ipeli i Za WDATA 35 0 gt E si N 5 QDR RDATA 35 0 lt gt Optional QDR SRAM CMD 1 0 fi Controller D i WPSn i 3 P K Kn Lr INCLK _____ km _ K_FB_OUT C Cn t K_FB_IN DE SignalTap II Logic Analyzer can be used to verify functionality of the design shown in Figure 9 15 and ensure that the correct data are written to the SDRAM controller The buffer acquisition in SignalTap II Logic Analyzer allows you to monitor the RDATA port when H OFOFOFOF is sent into the RDADDR port You have the ability to monitor multiple read transactions from the SDRAM device without re running SignalTap II Logic Analyzer The buffer acquisition feature allows you to segment the memory so that you can capture the same event multiple times without 9 23 Quartus Il Handbook Volume 3 9 24 wasting
255. uilder AHDL a arithmetic C VHDL A ARM Based Excalibur A gates Verilog HDL fa 1 0 a memory compiler Je A nt le Ariane What name do you want for the output file Browse a storage C mp_design 8 IP MegaStore TT Return to this page for another create operation Note To compile a project successfully in the Quartus Il software your design files must be in the project directory or a user library you specify in the User Libraries page of the Settings dialog box Assignments menu Your current user library directories are Cancel lt Back Next gt 6 Configure the analyzer by specifying the Sample Depth Memory Type Data Input Width Trigger Input Width and Number of Trigger Levels 7 Click Next See Figure 9 5 Altera Corporation 9 9 June 2004 Quartus Il Handbook Volume 3 9 10 Figure 9 5 Select the Parameters for the Analyzer MegaWizard Plug In Manager SLD_SIGNALTAP page 1 of 3 x Currently selected device family Stratix Zl Data options Sample depth Data input port width v al 18 z f signaltapll RAM type Xaca_ek Bu XY acq_data_in 7 0 Dr options Trigger levels Trigger input port width 3 aca_trigger in 7 0 n em I Trigger in TT Trigger out Cancel lt Back Next gt Finish 8 Set the Trigger level options by choosing Basic or Advanced See Figure 9 6 Figure 9 6 Basic and
256. ulti frequency clock domain analysis One check ensures that data clocked out of the source register after the launch edge is not latched by the destination register This is illustrated by the dashed Altera Corporation June 2004 Quartus Il Timing Analysis line in Figure 4 23 The other check ensures that data is not captured at the destination by the clock edge before the latch edge This is illustrated by the dotted line in Figure 4 23 Figure 4 24 illustrates hold time checks for a Multicycle Hold assignment of 1 Figure 4 24 Multicycle Hold of 1 gt Setup gt Hold Check 1 Rn D Hold Check 2 CLK1 a L CLK2 Clock 1 Period 6ns Clock 2 Period 12 ns Offset 2ns Multicycle 2 Multicycle Hold 1 The first check illustrated with the dashed line requires a minimum data delay of 8 ns 14 ns 6 ns The second check illustrated with the dotted line requires a minimum data delay of 2 ns 2 ns 0 ns Data must have a maximum delay of 14 ns and a minimum delay of 8 ns to meet the Multicycle and Multicycle Hold requirements Figure 4 25 illustrates hold time checks for the Default Multicycle Hold value of 2 Altera Corporation 4 25 June 2004 Quartus Il Handbook Volume 3 Figure 4 25 Multicycle Hold of 2 P Setup gt Hold Check 1 na D Hold Check 2 CLK1 _T CLK2 1 amp 12
257. unctional simulation only Run the EDA Netlist Writer 2 5 Quartus Il Handbook Volume 3 2 6 Choose Start gt Start EDA Netlist Writer Processing menu During the EDA Netlist Writer stage the Quartus II software produces a Verilog output vo file that can be used for the post synthesis simulations in the VCS software This netlist file is mapped to architecture specific primitives No timing information is included at this stage The resulting netlist is located in the lt project folder gt simulation VCS directory This netlist along with the device family library listed in Table 2 3 on page 2 7 can be used to perform a post synthesis simulation in VCS The following VCS commands describes the command line syntax used to perform a post synthesis simulation with the appropriate device family library listed in Table 2 3 on page 2 7 ves R lt testbench v gt lt post synthesis netlist vo gt v lt altera device family library v gt Gate Level Timing Simulation A gate level timing simulation verifies the functionality of the design after place and route has been performed You can create a post place and route netlist in the Quartus II software and use this netlist to perform a gate level timing simulation in VCS Generating a Gate Level Timing Simulation Netlist in Quartus Il The following steps describe the process of generating a gate level timing simulation netlist in the Quartus II software
258. ure automatically inserts the number of registers specified in the SignalProbe path Altera Corporation June 2004 Performing a SignalProbe Compilation Performing a SignalProbe Compilation Altera Corporation June 2004 For example you can add a single register between the SignalProbe source and the SignalProbe output pin to reduce the propagation time tco You can add multiple registers to your SignalProbe output pins to synchronize the data with other output pins in your design US When you add one register to a SignalProbe pin the SignalProbe compilation always attempts to place the register into the I O element If it is unable to place the register into the I O element it places the register as close to the SignalProbe pin as possible to reduce clock to output delays tco You can add registers to your SignalProbe pin by performing the following steps 1 Click Assign SignalProbe Pins on the SignalProbe Settings page of the Settings dialog box Assignments menu 2 Inthe Available Pins amp Existing Assignments list select the pin number for the SignalProbe output pin you want to register 3 Under Assignment type a new Clock name in the Clock box 4 Under Assignment type the number of registers necessary to pipeline your SignalProbe source in the Register box ll Altera strongly recommends using global clock signals to clock the added registers The MAX II Stratix Stratix GX and Cyclone devices su
259. us II installation gt eda sim lib nesim lt verilog vhdl gt stratixgx_gxb or create a new library altgxb using the following files in the lt Quartus II installation gt eda sim lib directory stratixgx hssi atoms v stratixgx hssi atoms vhd stratixgx hssi components vhd Altera Corporation August 2004 Gate Level Timing Simulation Altera Corporation August 2004 The altgxb library uses the LPM and SGATE libraries You can use the following files in the lt Quartus II installation gt eda sim lib directory to create the LPM and SGATE libraries 220model v 220model vhd 220pack vhd sgate v sgate vhd sgate_pack vhd See Basic Library Setup on page 3 6 and LPM Function amp Altera Megafunction Libraries on page 3 8 for step by step instructions on creating libraries Compile the Project Files amp Libraries Compile the project files and libraries into your work directory using the ncvlog or ncvhdl programs or the GUI including the following files Testbench file Your Quartus II output netlist file VO or VHO Atom library file for the device family lt device family gt _atoms lt v vhd gt For VHDL lt device family gt _components vhd See Compile Source Code amp Testbenches on page 3 11 for instructions on compiling Elaborate the Design When you elaborate your design you must include the SDO file For Verilog HDL this process happens automatically The Quartus II generated Verilog
260. ust be typed exactly as it appears is shown in Courier type For example c qdesigns tutorial chiptrip gdf Also sections of an actual file such as a Report File references to parts of files e g the AHDL keyword SUBDESIGN as well as logic function names e g TRI are shown in Courier 1 2 3 and Numbered steps are used in a list of items when the sequence of the items is a b c etc important such as the steps listed in a procedure Bee Bullets are used in a list of items when the sequence of the items is not important Va The checkmark indicates a procedure that consists of one step only IS The hand points to information that requires special attention The caution indicates required information that needs special consideration and A understanding and should be read prior to starting or continuing with the procedure or process The warning indicates information that should be read prior to starting or continuing the procedure or processes t The angled arrow indicates you should press the Enter key dt The feet direct you to more information on a particular topic xiv Altera Corporation Section I Simulation ANDTERVA As the design complexity of FPGAs continues to rise verification engineers are finding it increasingly difficult to simulate their system on a programmable chip SOPC designs in a timely manner The verification process is now the bottleneck in the FP
261. violations One way to do this is with the Logic Cell Insertion assignment You can specify a number of LCELL primitives to automatically insert in the failing path These primitives do not change the functionality of your design Another way to increase data delay is to assign nodes to LogicLock regions in separate areas of the device This increases the routing delay along the path The Quartus II software attempts to meet the following timing requirements on I O paths by default E Hold time tp from I O pins to registers E Minimum tco from registers to I O pins E Minimum tpp from I O pins or registers to I O pins or registers You can change the setting to direct the Quartus II software to also attempt to meet register to register hold time requirements Timing Analysis Across Asynchronous Domains In cases in which source and destination clocks are unrelated timing analysis across unrelated clock domains is not very useful because cross domain paths are asynchronous You can make Cut Timing Path assignments to cross domain paths and use special design techniques to make sure that asynchronous signals do not cause meta stability One of the most common techniques used is to enforce a full handshake protocol between the asynchronous boundaries Block A asserts the REQ signal when data is ready Block B synchronizes the REQ signal through two flip flops and then asserts the ACK signal when it has latched the data Block A synchronizes the A
262. wer Input File TT Bring out device wide set reset signals as ports TT Maintain hierarchy TT Generate netlist for functional simulation only Altera Corporation August 2004 3 19 Quartus II Handbook Volume 3 3 20 Quartus Il Timing Simulation Libraries Altera device simulation library files are provided in the lt Quartus II installation gt eda sim lib directory The VO or VHO file requires the library for the device your design targets For example the Stratix family has the following libraries E stratix_atoms v M stratix_atoms vhd M stratix components vhd If your design targets a Stratix device you must set up the appropriate mappings in your cds lib See Create Libraries on page 3 20 for more information Set Up Your Environment Set up your working environment for the Quartus II NC Verilog or NC VHDL software interface See the instructions in Set Up Your Environment on page 3 5 for details Create Libraries Create the following libraries for your simulation Mm A working library Mm The library for the device family your design targets using the following files in the lt Quartus II installation gt eda sim lib directory lt device_family gt atoms v lt device_family gt atoms vhd lt device_family gt components vhd m If your design contains the altgxb megafunction map to the precompiled Stratix GX timing simulation model libraries using the mapping lt Quart
263. worklib hd m 2 F Overwrite log file nevhal log z Overwrite log file ncvlog log m E Eror Limit 154 Ji Update if needed M Enable VHDL 93 features M Enable line debug Order Independent Compilation _ Enable order independent compilation _j Generate compilation script 1 _j Other Options Advanced Options OK Cancel Apply Help OK Cancel Apply Help 3 Select the files and click OK in the Compile Verilog or Compile VHDL dialog box to begin compilation The dialog box closes and returns you to NCLaunch Le The command line equivalent argument displays at the bottom of the NCLaunch window 3 12 Altera Corporation August 2004 Functional RTL Simulation Altera Corporation August 2004 Elaborate Your Design Before you can simulate your design you must define the design hierarchy in a process called elaboration With NC simulators you use the language independent ncelab program to elaborate your design The ncelab program constructs a design hierarchy based on the design s instantiation and configuration information establishes signal connectivity and computes initial values for all objects in the design The elaborated design hierarchy is stored in a simulation snapshot which is the representation of your design that the simulator uses to run the simulation The snapshot is stored in the library database file along with the other intermediate objects

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