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Curtiss-Wright CHAMP

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1. TABLE A 11 J11 Connector Description Pn1 Jn1 64 bit PCI Continued Pin No Signal Direction Description Electrical Characteristics 32 AD 17 1 0 PCI Address Data Bus PCI PCI X 33 FRAME y o PCI Cycle Frame Signal PCI PCI X 34 GND N A GND GND 35 GND N A GND GND 36 IRDY y o PCI Initiator Ready Signal PCI PCI X 37 DEVSEL 1 0 PCI Device Select Signal PCI PCI X 38 5V N A Positive Supply 5V 39 PCIXCAP VO PCI X Mode select 66 vs 100 MHz operation PCI PCI X 40 LOCK yo PCI Lock Signal y o 41 RESERVED N A RESERVED N A 42 RESERVED N A RESERVED N A 43 PAR 1 0 PCI Parity Signal PCI PCI X 44 GND N A GND GND 45 VIO N A VIO Power see Note 1 5V or 3 3V 46 AD 15 1 0 PCI Address Data Bus PCI PCI X 47 AD 12 VO PCI Address Data Bus PCI PCI X 48 AD 11 1 0 PCI Address Data Bus PCI PCI X 49 AD 09 V0 PCI Address Data Bus PCI PCI X 50 5V N A Positive Supply 5V 51 GND N A GND GND 52 C BE 0 V0 PCI Command Byte Enable Bus PCI PCI X 53 AD 06 VO PCI Address Data Bus PCI PCI X 54 AD 05 V0 PCI Address Data Bus PCI PCI X 55 AD 04 VO PCI Address Data Bus PCI PCI X 56 GND N A GND GND 57 VIO N A VIO Power see Note 1 5V or 3 3V 58 AD 03 VO PCI Address Data Bus PCI PCI X 59 AD 02 V0 PCI Address Data Bus PCI PCI X 60 AD 01 V0 PCI Address Data Bus PCI PCI X 61 AD 00 VO PCI Address Data Bus PCI PCI X 62 5V N A Positive Supply 5V 63 GND N A GND GND 64 REQ64 1 0 PCI 64 bit Request PCI PCI X
2. Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TABLE 4 1 Compact CHAMP AV IV Memory Map Address Range Size Processor Processor Processor Processor Processor PMC DMA A B C D E 0000 0000 1FFF FFFF 512 MB local mem local mem local mem local mem local mem illegal 2000 0000 2FFF FFFF 256 MB mem D mem D mem D illegal mem D mem D 3000 0000 3000 FFFF 64KB bridge D bridge D bridge D illegal bridge D bridge D 3010 0000 3010 FFFF 65 KB OBIC D OBIC D OBIC D illegal OBIC D OBIC D 4000 0000 5FFF FFFF 512 MB PMC 1 PMC 1 PMC 1 PMC 1 PMC 1 PMC 1 6000 0000 6FFF FFFF 256 MB mem C mem C illegal mem C mem C mem C 7000 0000 7000 FFFF 64KB _ bridge C bridge C illegal bridge C bridge C bridge C 7010 0000 7010 FFFF 65 KB OBICC OBIC C illegal OBIC C OBIC C OBIC C 8000 0000 8FFF FFFF 256 MB mem B illegal mem B mem B mem B mem B 9000 0000 9000 FFFF 64KB bridge B illegal bridge B bridge B bridge B bridge B 9010 0000 9010 FFFF 65KB OBICB illegal OBIC B OBIC B OBIC B OBIC B A000 0000 BFFF_FFFF 512 MB PMC 2 PMC 2 PMC 2 PMC 2 PMC 2 PMC 2 C000_0000 CFFF_FFFF 256 MB illegal memA memA memA memA memA D000 0000 D000 FFFF 64KB illegal bridge A bridge A bridge A bridge A bridge A D010 0000 D010 FFFF 65KB illegal OBIC A OBIC A OBIC A OBIC A OBIC A E000 0000 E7FF_FFFF 128 MB mem E mem E mem E mem E illegal mem E ECOO 0000 ECOF FFFF 64KB E pe
3. TABLE A 3 J2 Connector Pin Assignments Pin Number RowE Row D Row C Row B Row A 22 GAO GA1 GA2 GA3 GA4 21 NC NC NC NC NC 20 NC GND NC NC NC 19 NC NC NC NC NC 18 NC GND NC NC NC 17 NC NC NC GND NC 16 NC GND NC NC NC 15 NC NC NC GND NC 14 NC GND NC NC NC 13 NC NC V I O GND NC 12 NC GND NC NC NC 11 NC NC V I O GND NC 10 NC GND NC NC NC 9 NC NC V I O GND NC 8 NC GND NC NC NC 7 NC NC V I O GND NC 6 NC GND NC NC NC 5 NC NC V I O GND NC 4 NC GND NC NC V I O 3 NC NC NC GND NC 2 NC NC NC NC NC 1 NC NC NC GND NC ELECTRICAL CHARACTERISTICS OF J2 SIGNALS Table A 4 provides the electrical characteristics of the J2 signals TABLE A 4 J2 Connector Description Signal Name Direction Description Electrical Characteristics GA 4 0 Input Signals are pulled to 3 3v on board Geographical GND or floating on Address signals are used to provide a unique slot ID for every slot in a cPCI backplane backplane 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A 5 COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING J3 CONNECTOR PIN ASSIGNMENTS Table A 5 lists the J3 pin assignments for the basecard Figure A 3 shows the location of contacts on the J3 connector FiGURE A 3 J3 Connector F E DC B A DD OANDADM 9 ODD DO COE SE VECO IC BID A J4 v 000000 VU INCUN N
4. A rtisan Artisan Technology Group is your source for quality TecmoogyGroup new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment EQUIPMENT DEMOS HUNDREDS OF InstraV ea REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com 7 information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED yop aed Contact us 888 88 SOURCE sales artisantg com www artisantg com Document Number 814256 Version 2 Date February 2006 CoMPACT CHAMP AV IV QUAD POWERPC SCP 424 USER S MANUAL Curtiss Wright Controls Embedded Computing 333 Palladium Drive Ottawa Ontario Canada K2V 1A6 613 599 9199 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING REVISION HISTORY Rev By Date Description 1 JP August 2005 Fi
5. 1 connection to cPCI J5 connector Depends on module 8 VO PMC 1 connection to cPCI J5 connector Depends on module 9 VO PMC 1 connection to cPCI J5 connector Depends on module 10 VO PMC 1 connection to cPCI J5 connector Depends on module 11 VO PMC 1 connection to cPCI J5 connector Depends on module 12 VO PMC 1 connection to cPCI J5 connector Depends on module 13 VO PMC 1 connection to cPCI J5 connector Depends on module 14 VO PMC 1 connection to cPCI J5 connector Depends on module 15 VO PMC 1 connection to cPCI J5 connector Depends on module 16 VO PMC 1 connection to cPCI J5 connector Depends on module 17 VO PMC 1 connection to cPCI J5 connector Depends on module 18 VO PMC 1 connection to cPCI J5 connector Depends on module 19 VO PMC 1 connection to cPCI J5 connector Depends on module 20 VO PMC 1 connection to cPCI J5 connector Depends on module 21 VO PMC 1 connection to cPCI J5 connector Depends on module 22 VO PMC 1 connection to cPCI J5 connector Depends on module 23 VO PMC 1 connection to cPCI J5 connector Depends on module 24 VO PMC 1 connection to cPCI J5 connector Depends on module 25 VO PMC 1 connection to cPCI J5 connector Depends on module 26 VO PMC 1 connection to cPCI J5 connector Depends on module 27 VO PMC 1 connection to cPCI J5 connector Depends on module 28 VO PMC 1 connection to cPCI J5 connector Depends on module 29 VO PMC 1 connection to cPCI J5 connector Depends on module 30 VO PMC 1 connection to cPCI J5 conn
6. Interface 16 bit An Internal Interrupt Module e Twenty One internal interrupts e Interrupt detection and steering e Interrupt masking An External Interrupt Module e Twenty Four external interrupts supplied to the cOBIC e Interrupt detection and steering e Interrupt masking An Inter Processor Module e Mailbox Interrupts supported by five FIFOs one per processor Only the processor that owns a FIFO can read it while all processors can write it Device Bus E Interface 16 bit e Dedicated inter processor interrupts e Sixteen semaphore registers e Five Watchdog timers one per processor General Board Support Clocks LED Control As seen in Figure 1 3 above the cOBIC incorporates the following features 814256 VERSION 2 FEBRUARY 2006 1 9 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING General Purpose I O e Eight general purpose I O signals to rear panel J4 connector GPIO 0 through GPIO 7 e Two may be used for interrupts or GPIO GPIO 1 and GPIO 2 General Board Support Module e Provides the hardware for the control of miscellaneous board resources Internal and Figure 1 4 on page 1 10 provides an overview of the interrupt routing on the board while External Interrupt Table 1 1 and Table 1 2 list the internal and external interrupt sources respecti
7. Note 1 PMC site 1 can be factory configured to provide 3 3 V or 5 V PCI signaling See PMC Module Voltage Types on page 2 4 VIO will supply 3 3V power when configured for 3 3 V signaling and 5 V power when configured for 5 V signaling A 14 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING J12 CONNECTOR Table A 12 lists the pin assignments for the connector referenced J12 This connector is part of PMC site 1 and is referenced as Pn2 Jn2 in the PMC specification IEEE 1386 1 2001 TABLE A 12 J12 Connector Description Pn2 Jn2 64 bit PCI Pin No Signal Direction Description Electrical Characteristics 1 12V N A 12V Supply 12V 2 TRST O JTAG Reset PCI PCI X 3 TMS l JTAG Test Mode Select PCI PCI X 4 TDO O JTAG Test Data Out PCI PCI X 5 TDI JTAG Test Data In PCI PCI X 6 GND N A GND GND 7 GND N A GND GND 8 RESERVED N A RESERVED N A 9 RESERVED N A RESERVED N A 10 RESERVED N A RESERVED N A 11 BUSMODE2 O Basecard indicates PCI protocol used for PMC PMC PPMC interface by driving this line high 12 3 3V N A Positive Supply 3 3V 13 RST O PCI Reset Signal PCI PCI X 14 BUSMODE3 O Basecard indicates PCI protocol used for PMC PMC PPMC interface by driving this line low 15 3 3V N A Positive Suppl
8. W weight 1 25 814256 VERSION 2 FEBRUARY 2006 Guaranteed 888 88 SOURCE www artisantg com A rtisan Artisan Technology Group is your source for quality TecmoogyGroup new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment EQUIPMENT DEMOS HUNDREDS OF InstraV ea REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com 7 information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED yop aed Contact us 888 88 SOURCE sales artisantg com www artisantg com
9. ee Vi YONG A eMe LUN o P J JN y LR FON OR ES ANA Fi ENE F NA V 24 s XE CN ils 23 WP Mee es oP Nu NEMUS NP A 8 aan ia CX FK he c Ac mra a P C NON A AOO ae Le OE NUR at Arr A 20 s d YOO YOO 19 LIX ee Nu ee a 18 OOO000 MAYO 17 OU J rT MV oN EXON LoL x CY F Noar J3 AN TTE AD db d A DIDI VOOOOC MN Aa OOO AO AO CII SOO VOL FNIT COO O6 9690 SANA I DOOOAOAO TID DD OD J N T gt Jl S ANN EG 4 d iu V di UN Ng PND Nop Neuf J2 Ne T e dl oN FKO8N EON C DX Se 6 39 A NA NE N NA I Ns T 7 XC E N N FN VN KCN a Y ae PAS CX LI Ne mu YC A Sat a ef NTN CN A S J1 and J4 Connector Rear View J1 Tables A 7 and A 11 show which signals are available from the J4 connector of the Compact CHAMP AV IV A 8 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE A 7 J4 Connector Pin Assignments Pin No Row E Row D Row C Row B Row A 25 GPIO3 GPIO2 GND GPIO1 GPIOO 24 GPIO7 GPIO6 GND GPIO5 GPIO4 23 NC 12V GND NC 12V 22 GND GND GND GND GND 21 EDO TRX2 EDO TRX2 GND EDO TRXO EDO TRX0
10. if not observed could result in damage to the hardware Cautions include specific The caution icon indicates non catastrophic incidents complex practices or procedures instructions for avoiding or minimizing these incidents Caution D The note icon highlights exceptions and special information Note nl m Tips provide extra information on the subject matter This could include hints about how to use your current CWCEC card to its maximum potential Tip XII 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING REFERENCE DOCUMENTATION Refer to the following standards for information about the specifications the Compact CHAMP AV IV is designed for compliance with e IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC IEEE Std 1386 1 2001 June 14 2001 e IEEE Standard for a Common Mezzanine Card CMC Family IEEE Std 1386 2001 June 14 2001 e PCI Local Bus Specification PCI SIG Revision 2 3 March 29 2002 e PCI X Electrical and Mechanical Addendum to the PCI Local Bus Specifications PCI SIG Rev 2 0 Nov 4 2002 e PCI X Protocol Addendum to the PCI Local Bus Specification PCI SIG Rev 2 0 July 29 2002 e Interface Between Data Terminal Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange ANSI TIA EIA 232 F 1997
11. is used to select the PCI bus frequency If the PMC grounds the signal 33 MHz operation is selected If not grounded by the PMC pulled up on the baseboard then 66 MHz operation is selected PCIXCAP PCIXCAP Jn1 pin 39 is a 3 level signal that is utilized to select between conventional PCI PCI 33 and PCI 66 PCI X 66 and PCI X 100 When the PMC grounds PCIXCAP conventional PCI mode is selected When the PMC connects PCIXCAP to ground through a 10 KOhm 5 resistor in parallel with a 0 01 uF 10 capacitor PCI X 66 MHz mode is selected When the PMC connects PCIXCAP to ground through a 0 01 uF 10 capacitor PCI X 100 MHz mode is selected IDSELB The IDSELB Jn2 pin 34 is used to select an optional second PCI agent REQB The REQB signal Jn2 pin 52 is a request issued by the optional second PCI agent requesting the ownership of the PCI bus GNTB The GNTB signal Jn2 pin 54 is a grant issued to the optional second PCI agent requesting the owner ship of the PCI bus via the corresponding REQB signal RESETOUT The RESETOUT signal Jn2 pin 60 is an active low open drain output from the PMC When asserted by the PMC the Compact CHAMP AV IV will perform a board reset same as pushing the reset switch on the Compact CHAMP AV IV board EREADY The EREADY signal Jn2 pin 58 is an open drain output on non monarch PMCs that indicates the PMC has completed its on board initialization and can respond to PCI bus enumera
12. www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING CoMPACT CHAMP AV IV MEMORY MAP 4 2 The resources on the Compact CHAMP AV IV are connected via four unique PCI buses Since all nodes of the Compact CHAMP AV IV are connected together by the PCI buses all memory on the board is globally accessible Each processor has a specific view of the board Differences from one processor s view to the next are due to the fact that each processor views its own memory bridge and FPGA port as starting at zero and extending through the first 512 MB of address space while the PCI address space for these assets never starts at zero PMC devices will view board resources using the PCI memory map where all processors start at a nonzero memory address Table 4 1 on page 4 3 shows the physical memory maps for all processors and for PMC initiated transfers No device may select itself using its own PCI address space Entries designated illegal result in a PCI transfer error Unlisted entries also result in errors The logical address map imposed by an operating system may result in further limitations 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PROGRAMMING INTERFACE
13. 0 oo om 0 00 UD 00 DO CU DD QD OD QC o 0 nb 0 oo ong aa a MES 000 DD DUDDD DD 00000 QDUDU ab ahom oof o ooo 00 DDODU 00 DOUOD onnnn ml fn on o m s l DDDDODODUDDD 100010 T EE NN ep mum fgg EX CEST 1 ea 000000 000000 11 1 o f mwm ig oS 1 2 0M a pm 1 000 0 zh 1 27 5 eo poe SS l RU EE E DES r BY zl g DOnmun 2j m E _ em 88 a om ale SIE p mos E gles Sj m l S Ee els 1 Ex E 2 Spi i pS L 0 00 mu a J J g M rs Si S A 2100005 E IB BiU 6 pz Soke uem s S E Z 2 Lu BE 1000 DDDOC 3 amp ls ef Bron DoD ooooootoot ou D TET gi T m pt 1 Ise 5255 Z ur M E M0000 oou ooog 1 Sigea RES innaDng ODOICCD Sess dorm m2228 eee sec Que 0 10000 CAUDO 2 Ssseq 7 oS BIEI gt ij i 2e E polis longo E 5 i a eee PME 1000 00 D D 0009 e 1 pl IOo p jesese E 0 DDDDUDDUD QT y P e HE 0D D m sl nu 1 n E S E DU pss F oo Sw 0 fm 21 0 i i S n Son i poe 1 dy 8 l l EA 3 res 055 og moron I 2 of E Exin lores al s Sm Jia 1 i s S PEDES 200 un gg 8 2500 07 7 Sp 1 i3 sl ile EI 8 size s gei sts ldi egz EE Dum me m BB BTs Sue sS 8mns EE S S ST ma e Boe 2 BS 13 mp 17 2 L Emi oo o1 S ws B 1 EPI ic eso Ont nonoo 000000 nogoo onoono hes ee Ol MET D non btnDD n 1 DOQODDDONNO 0000 0 l So 1 E E I pu UW oS Use Sa Tivoogocoa ooog t D O00000 c cupp 00 ze DEDOS isa 2 i 0D
14. 0000 through 07FF FFFF DATA FLOW DIRECTIONS 4 4 All memory mapped resources can access all other memory mapped resources on the Compact CHAMP AV IV board However because each PCI interface on a particular Discovery controller must be assigned unique PCI address ranges this is so that when the processor connected to the Discovery produces a PCI address that address will go out one and only one PCI interface a resource will be able to get to another resource either clockwise or counter clockwise around the ring Figure 4 1 on page 4 5 and Figure 4 2 on page 4 6 provide diagrams that show the Discovery PCI interface used to access a particular resource For instance the A Node diagram in Figure 4 1 shows that Node A can get to either PMC1 or Node D counter clockwise while it can get to all other resources clockwise 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PROGRAMMING INTERFACE FiGURE 4 1 Data Access Directions for Processor Nodes Resource Access Resource Access Directions for Node A Directions for Node B Resource Access Resource Access Directions for Node C Directions for Node D 814256 VERSION 2 FEBRUARY 2006 4 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED C
15. 1 16 for additional information There is an additional red LED on the front panel used to indicate a failure determined by the on board diagnostic firmware FiGURE 1 6 LED Control Red System LED Green Status LEDs Green Status LEDs 10 Green Processor LEDs Global LED Register 5 Green Processor LED Green Processor LEDs Green S Processor A us LEDs LED Register LEDs are turned on by either of the LED control OR registers Green Processor LED Processor B Green Status LEDs 2 LED Register 4 Green Processor LED Processor C Green Status LEDs LED Register Green Processor LED a a E Green Status LEDs Processor D LED Register Green Processor LED Processor E Green Status LEDs LED Register 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW COMPACT PCI INTERFACE SERIAL PORTS TABLE 1 5 Nodes A and E Serial Port 0 EIA 232 Asynchronous Mode 814256 VERSION 2 FEBRUARY 2006 The Compact CHAMP AV IV does not have an interface to the Compact PCI backplane The only signals on J1 and J2 that are used are reset BDSEL HEALTHY and geographical addressing The Compact CHAMP AV IV provides two EIA 232 asynchronous
16. 2 T DVE_INT_ INT 88E1145 Q2 T Bridge xt PowerPC A A x2 x4 B B MPC8540 MPC8540 GPIO_INT x2 lt cPCI User I O gt 1 10 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW TABLE 1 1 Internal Interrupt Sources Interrupt Input Detection Mode Location for Description Clearing FIFO Not Empty A E N A cOBIC There is a 16 bit 32 Deep FIFO associated with each processor When one of these FIFO s receives data it produces an interrupt Watchdog A E N A cOBIC An Avionics style watchdog timer is associated with each node If the watchdog is kicked too soon or too late an interrupt is generated Inter Processor N A cOBIC Each processor can generate up to 8 interrupts to another Int 7 0 processor PMC1 INT A D PMC2 INT A D FIGURE 1 5 Interrupt Structure DVA PCI INT 1 0 39 DVB PCI INT 1 0 gt DVC PCI INT 1 0 DVD PCI INT 1 0 DVE PCI INT 1 0 gt CPCI GPIO 2 1 B TEMP VOLT 1 0 b Interrupt Status Register Discovery MPC8540 INT 88E1111 P 3 0 INT 88E1145 Interrupts 4 AND OR gt DVX_INT_ Register Interrupt Pending Registers Description Interrupt Status Read Wri
17. 4 see Note 4 see Note 4 Notes 1 Power Dissipation is dependant on the application executed by the processors The values in this column were measured from a board running a stress test designed to emulate a typical user s application under fairly heavy load For more information please consult technical sup port Values measured at 25 C ambient 2 Power Dissipation is dependant on the application executed by the processors The values in this column were measured from a board running a stress test designed to draw the maximum current For more information please consult technical support Values measured at 25 C ambient 3 Values available 1Q06 4 The 12V supplies are not used by the Compact CHAMP AV IV circuitry however they are routed to the PMC sites on the board therefore the current drawn from these supplies is PMC module dependent The voltage tolerances and power requirements for each supply are summarized in Table 2 2 Missing or below level voltages will cause the power detection circuitry on the board to hold the board in a powered down state The power detection circuitry does not monitor the 12V supplies since these power rails are used only to provide 12V to the PMC sites no on board circuitry uses these voltages In order to ensure proper operation of the Compact CHAMP AV IV board the remote voltage sense lines for the 5V and 3 3V power must be connected from the power supplies to the vo
18. 5 INTB l PMC Interrupt Request Line PCI PCI X 6 INTC l PMC Interrupt Request Line PCI PCI X 7 PRSNT1 l BUSMODE1 signal used to indicate presence ofa PMC PPMC PMC module in site 1 8 5V N A Positive Supply 5V 9 INTD l PMC Interrupt Request Line PCI PCI X 10 RESERVED N A RESERVED N A 11 GND N A GND GND 12 NC 3 3 V AUX N A No Connect 3 3 V Auxiliary Supply 3 3 V 13 PCICLK1 O PCI Clock Signal PCI PCI X 14 GND N A GND GND 15 GND N A GND GND 16 PMC1_GNT O Arbitration Grant Signal to PMC site 1 PCI PCI X 17 PMC1_REQ l Arbitration Request Signal from PMC site 1 PCI PCI X 18 5V N A Positive Supply 5V 19 VIO N A VIO Power see Note 1 5V or 3 3V 20 AD 31 1 0 PCI Address Data Bus PCI PCI X 21 AD 28 y o PCI Address Data Bus PCI PCI X 22 AD 27 VO PCI Address Data Bus PCI PCI X 23 AD 25 1 0 PCI Address Data Bus PCI PCI X 24 GND N A GND GND 25 GND N A GND GND 26 C BE 3 VO PCI Command Byte Enable Bus PCI PCI X 27 AD 22 VO PCI Address Data Bus PCI PCI X 28 AD 21 y o PCI Address Data Bus PCI PCI X 29 AD 19 1 0 PCI Address Data Bus PCI PCI X 30 5V N A Positive Supply 5V 31 VIO N A VIO Power see Note 1 5V or 3 3V 814256 VERSION 2 FEBRUARY 2006 A 13 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING
19. 5V or 3 3V 58 AD 32 VO PCI Address Data Bus PCI PCI X 59 RESERVED N A RESERVED N A 60 RESERVED N A RESERVED N A 61 RESERVED N A RESERVED N A 62 GND N A GND GND 63 GND N A GND GND 64 RESERVED N A RESERVED N A Note 1 PMC site 1 can be factory configured to provide 3 3 V or 5 V PCI signaling See PMC Module Voltage Types on page 2 4 VIO will supply 3 3V power when configured for 3 3 V signaling and 5 V power when configured for 5 V signaling A 18 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING J14 CONNECTOR Table A 14 lists the pin assignments for the connector referenced J14 This connector is part of PMC site 1 and is referenced as Pn4 Jn4 in the PMC specification IEEE 1386 1 2001 TABLE A 14 J14 Connector Description Pn4 Jn4 User Defined I O J14Pin cPCI J5 Pin Number Direction Description Electrical No Characteristics 1 VO PMC 1 connection to cPCI J5 connector Depends on module 2 VO PMC 1 connection to cPCI J5 connector Depends on module 3 VO PMC 1 connection to cPCI J5 connector Depends on module 4 VO PMC 1 connection to cPCI J5 connector Depends on module 5 VO PMC 1 connection to cPCI J5 connector Depends on module 6 VO PMC 1 connection to cPCI J5 connector Depends on module 7 VO PMC
20. B block diagram 1 3 bottom view Compact CHAMP AV IV PWB 1 22 Built In Test BIT firmware 1 26 C CHAMP AV IV memory map 4 2 chassis requirements 2 2 2 5 Checking Hardware Requirements 2 2 Compact CHAMP AV IV board layout 1 21 Compact CHAMP AV IV dimensions 1 24 Compact CHAMP AV IV functional block diagram 1 3 Compact CHAMP AV IV weight 1 25 configuring switches 2 8 connecting a terminal 3 5 D data flow directions 4 4 dimensions 1 24 Display the Initial Screen Message 3 6 Double Data Rate SDRAM 1 6 E electrical characteristics of J1 Signals A 3 electrical characteristics of J2 Signals A 5 electrical characteristics of J5 Signals A 11 Ethernet interfaces 1 18 F feature summary 1 4 Flash memory 1 7 G general description 1 1 General Purpose I O and interrupt inputs 1 16 814256 VERSION 2 FEBRUARY 2006 Index H hardware requirements 2 2 high speed SRAM 1 7 indicator LEDs 1 16 initial screen message 3 6 Initiate the Power Up Sequence 3 6 insert basecard in chassis 3 5 installation procedure summary 3 1 installing PMC modules 3 3 internal interrupt sources 1 11 interrupt routing 1 10 interrupt structure 1 11 J J1 connector description A 3 Ji connector pin assignments A 3 J12 Connector A 15 J13 Connector A 17 J14 Connector A 19 J2 connector A 4 description A 5 J21 Connector A 21 J23 Connector A 25 J3 connector A 6 description A 7 J4 connector pin assignments A 9 J5 connec
21. Es ET sssses le sssess lE IESSSTN ng ja f E oo ii wn todo i i 1 B noon 1000000 TTE CENSO SoS SSS 800000 1000000 EE mE zi 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW SCP 424 An illustration showing the front panel that is mounted on the Compact CHAMP AV IV also known as the SCP 424 is provided below along with a brief description of the indicators and Front Panel connectors it provides LJ E UP C PMC Slots Two openings are provided on the SCP 424 front panel to provide access to connectors that may be incorporated on optional PMC modules that may be installed on the basecard PWB If there are no PMC modules mounted the openings are filled with bezels Reset Pushbutton This button can be used to initiate a card reset Processor Status LEDs A B C D E Each of the processors has a processor LED a AOCOSB register that controls the green processor status LEDs seen opposite and two of the surface cOOn mount status LEDs on the PWB OOF Crews F LED The FLED is the red Fail LED used to indicate a failure determined by the on board b diagnostic firmware Q Iu z Oy STAT LED The STAT LED on the front panel is the blue hot swap event LED 814256 VERSION 2 FEBRUARY 2006 1 23 Artisan Technology Gro
22. Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW General Purpose O and Interrupt Inputs Each timer has a 24 bit minimum and a 24 bit maximum read write register see the CHAMPtools Software User s Manual If the watchdog is kicked by writing to the Watchdog Kick Register before the minimum timer expires or if it is not kicked before the maximum timer expires a fault is generated A fault can be selected to cause a reset of the processor associated with that watchdog a board reset or an interrupt to any of the four processors Each watchdog timer is enabled by setting the WDT_EN bit in its associated control register see the CHAMPtools Software User s Manual If a fault occurs the watchdog timer is halted Also the minimum and maximum registers may be locked by setting the WDT_LOCK bit in the associated control register A reset of the associated processor will generate an active LOW pulse 3 84us wide on CPX RESET where X A B C D or E It will also reset the minimum and maximum registers to their default values A board reset will hold BB RESET in a LOW state until FPGA RST is received or the watchdog timer is disabled by clearing WDT EN An interrupt will be held until WDT EN is cleared As an example let s say you wanted to set up the watchdog timer so that the software could kick it between 5ms and 12ms without generating a fault Thus a fault would be ge
23. On position which selects the alternate SPROM see Table 2 5 on page 2 8 for details Power up the chassis Please see the CHAMPtools Software User s Manual to determine how to query results of the power on self test If the red Fail LED does not illuminate at power up or board reset the board has been damaged or one of the required power supply voltages is missing If this occurs be sure to check the 3 3V and 5V supplies SIGN ON MESSAGE GARBLED If the sign on message is garbled check that your terminal settings match 57600 8 N 1 57600 baud 8 data bits no parity 1 stop bit Also ensure that you are using a compatible serial cable THE NEXT STEP Once the hardware is correctly configured and installed in the chassis the next step is to install the CHAMPtools software See the section Software Installation in Chapter 2 of your CHAMPtools Software User s Manual which is included in Acrobat pdf format on your Cross Reference CHAMPtools CD ROM 3 10 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com PROGRAMMING INTERFACE IN THIS CHAPTER This chapter contains the following information e Compact CHAMP AV IV Memory Map on page 4 2 Data Flow Directions on page 4 4 814256 VERSION 2 FEBRUARY 2006 4 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE
24. PCI Address Data Bus PCI PCI X 44 GND N A GND GND 45 GND N A GND GND 46 AD 40 1 0 PCI Address Data Bus PCI PCI X 47 AD 39 y o PCI Address Data Bus PCI PCI X 48 AD 38 VO PCI Address Data Bus PCI PCI X 49 AD 37 1 0 PCI Address Data Bus PCI PCI X 50 GND N A GND GND 51 GND N A GND GND 52 AD 36 VO PCI Address Data Bus PCI PCI X 53 AD 35 VO PCI Address Data Bus PCI PCI X 54 AD 34 1 0 PCI Address Data Bus PCI PCI X 55 AD 33 VO PCI Address Data Bus PCI PCI X 56 GND N A GND GND 57 VIO N A VIO Power see Note 1 5 V or 3 3V 58 AD 32 V0 PCI Address Data Bus PCI PCI X 59 RESERVED N A RESERVED N A 60 RESERVED N A RESERVED N A 61 RESERVED N A RESERVED N A 62 GND N A GND GND 63 GND N A GND GND 64 RESERVED N A RESERVED N A Note 1 PMC site 2 can be factory configured to provide 3 3 V or 5 V PCI signaling See PMC Module Voltage Types on page 2 4 VIO will supply 3 3V power when configured for 3 3 V signaling and 5 V power when configured for 5 V signaling Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING J24 CONNECTOR Table A 18 lists the pin assignments for the connector referenced J24 This connector is part of PMC site 2 and is referenced as Pn4 Jn4 in the PMC specification IEEE 1386 1 2001 TABLE A 18 J24 Connector Description Pn4
25. PCI Command Byte Enable Bus PCI PCI X 53 AD 06 VO PCI Address Data Bus PCI PCI X 54 AD 05 VO PCI Address Data Bus PCI PCI X 55 AD 04 VO PCI Address Data Bus PCI PCI X 56 GND N A GND GND 57 VIO N A VIO Power see Note 1 5 V or 3 3V 58 AD 03 VO PCI Address Data Bus PCI PCI X 59 AD 02 VO PCI Address Data Bus PCI PCI X 60 AD 01 VO PCI Address Data Bus PCI PCI X 61 AD 00 VO PCI Address Data Bus PCI PCI X 62 5V N A Positive Supply 5V 63 GND N A GND GND 64 REQ64 N A Interfaces 64 bit PMC Module PCI PCI X Note 1 PMC site 2 can be factory configured to provide 3 3 V or 5 V PCI signaling See PMC Module Voltage Types on page 2 4 VIO will supply 3 3V power when configured for 3 3 V signaling and 5 V power when configured for 5 V signaling A 22 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING J22 CONNECTOR Table A 16 lists the pin assignments for the connector referenced J22 This connector is part of PMC site 2 and is referenced as Pn2 Jn2 in the PMC specification IEEE 1386 1 2001 TABLE A 16 J22 Connector Description Pn2 Jn2 64 bit PCI Pin No Signal Name Direction Description Electrical Characteristics 1 12V N A 12V Supply 12V 2 TRST O JTAG Reset PCI PCI X 3
26. TMS l JTAG Test Mode Select PCI PCI X 4 TDO O JTAG Test Data Out PCI PCI X 5 TDI l JTAG Test Data In PCI PCI X 6 GND N A GND GND 7 GND N A GND GND 8 RESERVED N A RESERVED N A 9 RESERVED N A RESERVED N A 10 RESERVED N A RESERVED N A 11 BUSMODE2 O Basecard indicates PCI protocol used for PMC PMC PPMC interface by driving this line high 12 3 3V N A Positive Supply 3 3V 13 RST O PCI Reset Signal PCI PCI X 14 BUSMODE3 O Basecard indicates PCI protocol used for PMC PMC PPMC interface by driving this line low 15 3 3V N A Positive Supply 3 3V 16 BUSMODE4 O Basecard indicates PCI protocol used for PMC PMC PPMC interface by driving this line low 17 RESERVED N A RESERVED N A 18 GND N A GND GND 19 AD 30 VO PCI Address Data Bus PCI PCI X 20 AD 29 1 0 PCI Address Data Bus PCI PCI X 21 GND N A GND GND 22 AD 26 1 0 PCI Address Data Bus PCI PCI X 23 AD 24 1 0 PCI Address Data Bus PCI PCI X 24 3 3V N A Positive Supply 3 3V 25 IDSEL O PCI Initialisation Device Select for PMC Site 2 PCI PCI X 26 AD 23 1 0 PCI Address Data Bus PCI PCI X 27 3 3V N A Positive Supply 3 3V 28 AD 20 1 0 PCI Address Data Bus PCI PCI X 29 AD 18 1 0 PCI Address Data Bus PCI PCI X 30 GND N A GND GND 31 AD 16 1 0 PCI Address Data Bus PCI PCI X 814256 VERSION 2 FEBRUARY 2006 A 23 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANU
27. WRIGHT CONTROLS EMBEDDED COMPUTING VIII 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PREFACE PURPOSE This manual describes the cPCI based Compact CHAMP AV IV After explaining the capabilities of the Compact CHAMP AV IV the manual provides the procedure for correctly installing it and checking its operation AUDIENCE This document is aimed at readers with a technical understanding of hardware engineering fundamentals as well as a basic understanding of the cPCI PCI and digital signal processing hardware and software DOCUMENTATION ROADMAP The figure below will help you understand what documentation is available for the Compact CHAMP AV IV These documents are delivered in Adobe Acrobat pdf format on CD ROM or may be obtained via our TechNet web site at http www technet dy4 com Compact Compact Ca Mle Y CHAMP AV IV User s Manual Product Release Notes 814256 Booo Contents Contents hardware functional description information describing the installation instructions exact hardware configuration of programming interface your Compact CHAMP AV IV board detailed connector pinout info Compact CHAMP AV IV Hardware Documentation eR CHAMPtools CHAMPtools Son
28. efficient buffer management schemes and checksum calculations for TCP IP and UDP The MPC8540 Gig E interface is physically connected to a Marvell MV88E1111 Gigabit Ethernet Physical layer device PHY The 8540 also has a management interface to the PHY to control the device and read status The MV88E1111 is a one channel version of the MV88E1145 and has similar features The MPC8540 uses a GMII Gigabit Media Independent Interface to transfer data between itself and the PHY The Compact CHAMP AV IV has the following power distribution monitoring capabilities e Power monitoring of backplane 3 3 and 5 Volts If a low voltage condition is detected on either of the backplane voltages then the on board power planes will be disabled The cPCI interface power is not disabled e Power sequencing 5V 3 3V and all on board power supply outputs are sequenced to protect components They power up at the same time as the backplane power e The Compact CHAMP AV IV includes monitoring circuitry that activates board reset upon the following conditions Low voltage condition all on board power rails are monitored Power up Front panel reset Software generated reset cPCI system reset 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW RESET The Compact CHAMP AV IV
29. electrical characteristics of signals refer to Appendix A of this manual Cross Reference Windows utility generates the PO and P2 pinouts based on the I O configuration of the C The Technical Documentation CD ROM includes a pinout configurator utility This 32 bit Compact CHAMP AV IV and the PMC modules installed on it Tip DIMENSIONS Table 1 8 lists the physical dimensions of the Compact CHAMP AV IV TABLE 1 8 Compact CHAMP AV IV Dimensions Parameter Dimensions Height 233 2 mm 9 181 in Depth 159 8 mm 6 293 in PWB Thickness 1 63 mm 0 064 in 1 24 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW WEIGHT Table 1 9 lists the weight of the Compact CHAMP AV IV TABLE 1 9 Compact CHAMP AV IV Weight Card Type Weight Compact CHAMP AV IV est 1 3 Ibs TBD 814256 VERSION 2 FEBRUARY 2006 1 25 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING OVERVIEW OF AVAILABLE SOFTWARE The following sections outline the various software components associated with the Compact CHAMP AV IV BuiLT IN TEST BIT FIRMWARE The Compact CHAMP AV IV hosts a firmware package that performs both board init
30. enable signal Reserved for furture use LVCMOS FL RDYBSY Output Flash Ready Flash Busy signal Reserved for future use LVCMOS BCFG 1 0 Input Tied to SW 8 7 SeeTable 2 5 on page 2 8 for details LVCMOS 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A 9 COMPACT CHAMP AV IV USER S MANUAL J5 CONNECTOR PIN ASSIGNMENTS A 10 E D C B A CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Table A 9 lists the J5 pin assignments for the basecard Figure A 5 shows the location of contacts on the J5 connector FIGURE A 5 J5 Connector J3 J2 J1 J5 J4 i i F D C B A ra if NESE O78 hat a ee NA NON s NA Ned NA Nl Nf c MOOD O Cie Se O OA OOOOOO OGOOGO Ne NANA NA NA COYOGO0 OC IW Nol Nd NC Nf KSCS E S SR XCS SA CID QOOQ00O Net NP RS Ro S LRM UPS ERR IER eni OOOOOO zi NOVO O00000 OCO OOOOOO KYC ST C V ey Ny V NOOODC QOO V Q SO IS PIS NI OOOOOO S NOL OQOOOOO CY O a a er as Y ai O00000 oy NOOO ARIAT DDD FKON S NCOSINCS NN UP LA CUP LUPA CO9CO9COCOCYC Ns No ouf Neu Meu S rans a a Y QOOOOO f X em 7 OOOOOO NONIS IS eS CO OOOO OO J2 and J5 Connector Rear View Note The pinout tables are presented in the order of the rows when looking from the backplane i e 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentatio
31. for details Power up the chassis If the Quick Installation procedure described above works as expected you may want to try moving the S3 4 switch to the OFF position then pressing the reset button to enable the Normal Boot Mode which will prepare the card to boot an OS Please refer to the CHAMPtools Software User s Manual for detailed software installation procedures 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING HARDWARE INSTALLATION DETAILED INSTALLATION PROCEDURE INSERT THE BASECARD IN THE CHASSIS Ensure that the chassis power is turned off before inserting the card An SCP basecard is equipped with a faceplate compliant with IEEE 1101 10 The large ejectors on this faceplate facilitate insertion of the basecard into the cPCI chassis Once the basecard is inserted in the chassis secure it by tightening the screws at the top and bottom of the faceplate CONNECT A TERMINAL In order to access the features available within the embedded firmware on the Compact CHAMP AV IV you ll need to attach a terminal or PC emulated equivalent to the Serial Port A interface on the Rear Transition Module RTM Default serial communication parameters are 57 600 N 8 1 57600 baud no parity 8 bits 1 stop bit Flow control is via software xon xoff CONNECT ETHERNET PORT E Connect Et
32. loading due to Ethernet traffic These include dedicated DMA engines support for Jumbo packets up to 9 Kbytes automatic retransmission following a collision efficient buffer management schemes and checksum calculations for TCP IP and UDP The Gig E interface for each processor is physically connected to a Marvell MV88E1145 Quad Gigabit Ethernet Physical layer device Quad PHY Each processor also has a management interface to the Quad PHY to control the device and read status The MV88E1145 has a number of useful features such as auto negotiation MDI MDIX crossover and polarity reversal Auto negotiation enables the Ethernet interface to negotiate to highest speed 10 100 1000 Mbps supported by all devices on an Ethernet segment The Quad PHY can automatically determine whether or not it needs to cross over between pairs so that an external crossover cable is not required The Quad PHY also detects and corrects for polarity reversal on receive pairs in 1000Base T and 10Base T modes in 100Base T polarity reversal does not matter Each Discovery III uses an RGMII Reduced Gigabit Media Independent Interface to transfer data between itself and the Quad PHY Processor E MPC8540 uses its internal Gigabit Ethernet MAC interface The 8540 Ethernet controller also implements a number of features that are designed to minimize processor loading due to Ethernet traffic These include dedicated DMA engines automatic retransmission following a collision
33. module 46 V0 PMC 1 connection to cPCI J5 connector Depends on module 47 VO PMC 1 connection to cPCI J5 connector Depends on module 48 1 0 PMC 1 connection to cPCI J5 connector Depends on module 49 VO PMC 1 connection to cPCI J5 connector Depends on module 50 1 0 PMC 1 connection to cPCI J5 connector Depends on module 51 VO PMC 1 connection to cPCI J5 connector Depends on module 52 y o PMC 1 connection to cPCI J5 connector Depends on module 53 VO PMC 1 connection to cPCI J5 connector Depends on module 54 VO PMC 1 connection to cPCI J5 connector Depends on module 55 V0 PMC 1 connection to cPCI J5 connector Depends on module 56 VO PMC 1 connection to cPCI J5 connector Depends on module 57 1 0 PMC 1 connection to cPCI J5 connector Depends on module 58 VO PMC 1 connection to cPCI J5 connector Depends on module 59 V0 PMC 1 connection to cPCI J5 connector Depends on module 60 VO PMC 1 connection to cPCI J5 connector Depends on module 61 V0 PMC 1 connection to cPCI J5 connector Depends on module 62 VO PMC 1 connection to cPCI J5 connector Depends on module 63 1 0 PMC 1 connection to cPCI J5 connector Depends on module 64 VO PMC 1 connection to cPCI J5 connector Depends on module A 20 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING J21 CONNECTOR Table A 15 lists the pin assignments for the connector ref
34. off the on board power and the power will remain off until the backplane power is cycled The OVERT signal is only asserted in response to a High Temperature condition Each sensor has three programmable OVERT thresholds consisting of a high temperature threshold for each sensor The default threshold temperature is 127 C The OVERT feature is designed to help prevent or minimize board damage in the event of a catastrophic over temperature condition During normal operation the board temperatures will never approach 127 C COP INTERFACE The Compact CHAMP AV IV COP signals utilize 3 3 V signaling and are available on the J4 connector When connecting an emulator to these signals the emulator must be configured for 3 3 V signaling The COP interface is accessible via the Improper connection of the emulator can damage the Compact CHAMP AV IV board and or the emulator Observe orientation indicators on the emulator header Only 3 3V signaling is supported Warning 1 20 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW PHYSICAL CHARACTERISTICS Figure 1 8 shows the location of the major components and the mating connectors on the top side of the Compact CHAMP AV IV All ruggedization levels of the board have a thermal shunt that covers some of the components FIGURE 1 8 Compact
35. on BUSMODE1 this signal has been renamed PRESENT Z in the PPMC specification and is used to indicate the presence of a PMC card Note that the Compact CHAMP AV IV receives the BUSMODE1 signal from each PMC 814256 VERSION 2 FEBRUARY 2006 2 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PPMC Processor In addition to meeting the signaling standards of PMC cards the Compact CHAMP AV IV PMC and PCI X provides support for th PPMC Processor PMC standard and the PCI X standard The signals Support used to support these standards are listed in the table below TABLE 2 3 PPMC and PCI X Support Signal Name Description MONARCH The MONARCH signal Jn2 pin 64 is used to enable or disable the monarch feature on a Processor PMC PPMC The PPMC specification defines two states for the MONARCH signal float to disable the monarch feature and drive low to enable the monarch feature Since the Compact CHAMP AV IV baseboard performs the monarch PCI enumeration and interrupt functions for the respective PCI buses the baseboard allows the MONARCH signal to float to disable the monarch feature on PPMCs Standard PMCs non PPMC function properly since the PPMC specification defines an unused PMC pin for the MONARCH signal M66EN In conventional PCI mode PCIXCAP grounded the M66EN signal Jn2 pin 47
36. on page 2 2 have been met before you install the Compact CHAMP AV IV CHASSIS REQUIREMENTS The SCP 424 is a PCIMG 2 16 compliant card that is designed to be used in a PICMG 2 16 or standard cPCI backplane Refer to the Ruggedization Guidelines data sheet included on the Technical Documentation CD ROM and also available on www dy4 com for more information Cross Reference POWER REQUIREMENTS The Compact CHAMP AV IV requires 5 V and 3 3 V power supplies in order to operate Table 2 1 shows the power requirements for the Compact CHAMP AV IV 2 2 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE 2 1 Power Requirements PRE INSTALLATION TASKS Voltage 7447A 1 1 V core 1064 MHz 7447A 1 0 V core 998 MHz 7448 1 0 V core 1000 MHz Typical Power see Note 1 Maximum Power see Note 2 Typical Power see Note 1 Maximum Power Typical Power see Note 3 Maximum Power see Note 3 Total 64 9 77 1 54 7 TBD TBD TBD 5 V 34 5 52 3 24 6 TBD TBD TBD 3 3 V 30 4 24 8 30 1 TBD TBD TBD 12 V see Note 4 see Note 4 see Note 4 see Note 4 see Note 4 see Note 4 12 V see Note 4 see Note 4 see Note 4 see Note
37. rotary switch on the RTM If the target processor is PPC A configure S3 3 and S3 4 to either of the Normal Boot Modes S3 3 and S3 4 both Off or both On Please note that if the board is in Boot Inhibit Mode or Recovery Mode processors B C and D are not automatically released from reset at power up or board reset since the startup code does not per form this function for these processors this is left to the application With the proces sors in reset the emulator will not connect to them However if S3 3 and S3 4 are both on or both off the board will boot application code thereby releasing the proces sors from reset and allowing emulation If it is desired to use the emulator with the board in either of the two other modes the user should contact CWCEC technical sup port to determine the proper procedure for releasing B C and or D from reset 5 Disable auto voltage detection on the emulator and set it for 3 3V See Chapter 2 Sec tion 7 in the Wind Power ICE for Wind Power IDE User s Guide Please contact CWCEC technical support if there are any questions regarding this procedure 6 Connect the emulator to the RTM 7 Power up the Compact CHAMP AV IV board 8 Run the Wind Power IDE software and follow the procedures outlined in the associated Wind River documentation for opening communication with the emulator Bh WN HL 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation G
38. the needs of their application and achieve the best possible efficiency of the memory subsystem Each Discovery III bridge provides four DMA controller engines which are capable of transfering data between any of the bridges interfaces The DMA capability is particularly useful for managing transfers between processor node memory banks and transfers to and from PMC devices In addition the Discovery III bridge provides two XOR DMA controller engines that can read from up to eight sources perform bitwise XOR between the eight sources and write the result to a destination These architectural advantages of the Compact CHAMP AV IV will simplify and speed the process of application development Developers can focus on the problem rather than optimizing for board architectures that restrict data flow to one or two simultaneous transactions The memory map of the Compact CHAMP AV IV allows any processor to access the memory of any other processor and both PMC sites Any PMC module can access any of the processor node memories NODE E PROCESSOR The Compact CHAMP AV IV includes a fifth processor called Node E This processor an MPC8540 is a highly integrated device that contains a DDR SDRAM controller PCI X interface local bus similar to Disco III device bus Gigabit Ethernet MAC and UART on chip The 8540 can be used in a wide variety of applications as a control and management interface traffic manager or other function This capability
39. to write low level code to control the cOBIC please contact Customer Support for additional cOBIC information A customer upgradeable serial PROM is used to configure the cOBIC On power up the cOBIC automatically loads its configuration from this PROM 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW The Compact CHAMP AV IV also contains an alternate serial PROM which can be used to configure the cOBIC in the event that there is a problem with the main PROM This PROM is not upgradeable by the customer and puts the cOBIC into a known working state Switch SWA is used to select the main PROM and the alternate PROM see Configuring Switches on page 2 8 A block diagram of the cOBIC is shown below in Figure 1 3 32 bit FIGURE 1 3 cOBIC Block Diagram 32 bit 16 bit Flash Interrupt Output Internal Interrupts Device Bus A Interface Device Bus B Interface Internal Data Bus FIFO EMPTY FIFO EMPTY FIFO EMPTY Device A FIFO Device B FIFO Device C FIFO FIFO EMPTY Device D FIFO FIFO EMPTY Semaphores Watchdogs Device E FIFO O I esoding External Interrupts BJeuec 1 cOBIC Feature Summary Device Bus C Interface 6 bit Device Bus D
40. www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRE INSTALLATION TASKS FIGURE 2 2 Configuration Switch Locations e S2 1 4 Ww S3 1 4 id Lar 0000000000000 e e d e e 814256 VERSION 2 FEBRUARY 2006 2 9 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING 2 10 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 3 HARDWARE INSTALLATION IN THIS CHAPTER This chapter provides the following information and procedures e Installation Prerequisites on page 3 2 Installation Checklist on page 3 2 Unpack and Configure the Card on page 3 2 Install the PMC Modules on the Basecard on page 3 3 Choose a cPCI Slot Location on page 3 3 e Quick Installation and Power Up Procedure on page 3 4 e Detailed Installation Procedure on page 3 5 Insert the Basecard in the Chassis on page 3 5 Connect a Terminal on page 3 5 Connect Ethernet Port E on page 3 5 Cable Connections on page 3 5 Running the Boot Monitor on page 3 6 Initiate the Power Up Sequence on page 3 6 Dis
41. 2 1 4 and S3 1 4 on the Compact CHAMP AV IV that reside at the rear of the board see Figure 2 2 on page 2 9 Switches are available for selecting various board operational modes Switches identified as Reserved must be left in the default setting and only changed under the direction of Customer Support Please make sure that the board is not powered on when configuring board switches and that you observe proper static control procedures when handling the card Warning TABLE 2 5 Switch Definition Switch On Off Default S2 1 S2 3 User defined Switches are read by software on the Compact CHAMP AV IV and left up to the On application S2 4 Alternate FPGA PROM is used to program FPGA Main FPGA PROM is used program FPGA Off S3 1 User Defined readable by applications software User Defined readable by applications software Off 3 2 Boot alternate files Boot primary files Off S3 3 amp S3 4 These two switches are used to select the boot mode for the board see Note below Off Off S3 3 S3 4 Mode Off Off Normal Boot Mode loads OS or other application Off On Recovery Mode On Off Boot Inhibit Mode On On Normal Boot Mode with Flash Locked Note See the CHAMPtools Software User s Manual for additional information describing the various boot modes 2 8 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE
42. 2 8 814256 VERSION 2 FEBRUARY 2006 2 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING UNPACKING THE CARD To avoid personal injury or damage to this Circuit Card Assembly disconnect the chassis from its power source before removing or installing any cards This Circuit Card Assembly uses components that are sensitive to electrostatic Warning discharges It must be kept sealed in its conductive package until just before you install it Remove the card from its protective package only at a grounded workstation while wearing an approved grounding wrist strap Avoid touching any metal contacts on the card Static discharges can damage integrated circuits To unpack the card from its protective package follow these steps 1 Unpack the Circuit Card Assembly from the shipping carton in a suitable work area If the shipping carton appears to be damaged request that an agent of the shipper or carrier be present during unpacking and inspection 2 Find the packing list Make sure all the items on the list are present 3 Save the packing material for storing or reshipping the card 4 If your Compact CHAMP AV IV was shipped with PMC modules installed make sure they are firmly attached to the basecard CHECKING HARDWARE REQUIREMENTS Make sure the various hardware requirements summarized beginning
43. 2 connection to cPCI J3 connector Depends on module 23 VO PMC 2 connection to cPCI J3 connector Depends on module 24 V0 PMC 2 connection to cPCI J3 connector Depends on module 25 VO PMC 2 connection to cPCI J3 connector Depends on module 26 V0 PMC 2 connection to cPCI J3 connector Depends on module 27 VO PMC 2 connection to cPCI J3 connector Depends on module 28 V0 PMC 2 connection to cPCI J3 connector Depends on module 29 VO PMC 2 connection to cPCI J3 connector Depends on module 30 VO PMC 2 connection to cPCI J3 connector Depends on module 31 V0 PMC 2 connection to cPCI J3 connector Depends on module 32 VO PMC 2 connection to cPCI J3 connector Depends on module 33 VO PMC 2 connection to cPCI J3 connector Depends on module 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A 27 COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE A 18 J24 Connector Description Pn4 Jn4 User Defined I O Continued J24 Pin No cPCI J5 J3 Pin Direction Description Electrical Number Characteristics 34 VO PMC 2 connection to cPCI J3 connector Depends on module 35 lo PMC 2 connection to cPCI J3 connector Depends on module 36 VO PMC 2 connection to cPCI J3 connector Depen
44. 20 EDO TRX3 EDO TRX3 GND EDO TRX1 EDO TRX1 19 GND GND GND GND GND 18 DDO TRX2 DDO TRX2 GND DDO TRX0 DDO TRX0 17 DDO TRX3 DDO TRX3 GND DDO TRX1 DDO TRX1 16 CDO TRX2 CDO TRX2 GND CDO TRXO CDO TRXO 15 CDO TRX3 CDO TRX3 GND CDO TRX1 CDO TRX1 14 13 Key Area 12 11 XTMS VIO GND JP_TCK JP_TDI 10 XTDI 5V GND 3 3V JP_TRST 9 XTDO GND GND JP_SRST JP_TDO 8 XTCK 5V GND JP_QACK JP_HRST 7 JTSEL GND GND 5V JP_CKSTPIN 6 NC GND GND JP_QREQ JP_TMS 5 JPROC2 3 3V GND NC JP_CKSTPO 4 JPROCO 3 3V GND 5V FL_WE 3 JPROC1 GND GND NC FL RDYBSY 2 GND NC GND NC BCFGO 1 F ALTPROM PBRST GND 3 3V BCFG1 ELECTRICAL CHARACTERISTICS OF J4 SIGNALS Note V I O can be 3 3 or 5v to allow this to go into any slot 3 3v 5v universal Table A 8 provides the electrical characteristics of the basecard J4 signals TABLE A 8 J4 Connector Description Signal Name Direction Basecard Signal Description Electrical Characteristics CDxx DDxx Eexx Input Output Gigabit Ethernet signals comprised of Port C Port D and IEEE 802 3 Port E differential pairs JP xx Input Output Processor COP signals JTAG signals LVTTL XTxx EPLD JTAG Chain signals Use text from AV4 manual GPIOx Input Output OBIC General Purpose I O LVTTL or Open Collector JPROC 0 2 Input COP Target Processor Select Ground or Open JTSEL PBRST Input Pushbutton Reset Active Low Ground or Open F ALTPROM Input FL WE Input Flash Write
45. A9 B9 25 49 51 D8 E8 26 50 52 A8 B8 27 53 55 D7 E7 28 54 56 A7 B7 29 57 59 D6 E6 30 58 60 A6 B6 31 61 63 D5 E5 32 62 64 A5 B5 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com cPCI Connector J5 A 29 CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC TO CPCI CONNECTOR MAPPING FOR SINGLE ENDED SIGNALING TABLE A 20 PMC to cPCI Connector Mapping for Single Ended Signaling J14 J24 cPCI J5 Pins cPCI J3 J5 Pins J14 J24 cPCI J5 Pins cPCI J3 Pins Pin PMC Site 1 PMC Site 2 Pin PMC Site 1 PMC Site 2 1 D20 D 33 D12 2 A20 A 34 A12 3 E20 E 35 E12 4 B20 B 36 B12 5 D19 D 37 D11 6 A19 A 5 3g A11 7 E19 E 2 s9 E11 8 B19 B E 40 B11 9 D18 D 8 D40 o 10 A18 A e 42 A10 11 E18 E S43 E10 12 B18 B amp faa B10 13 D17 D 45 D9 14 A17 A 46 AQ 15 E17 E 47 E9 16 B17 B 48 B9 17 D16 D8 18 A16 A8 19 E16 E8 20 B16 B8 21 D15 D7 22 A15 A7 23 E15 E7 24 B15 B7 25 D14 D6 26 A14 A6 27 E14 E6 28 B14 B6 29 D13 D5 30 A13 A5 31 E13 E5 32 B13 B5 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com
46. AL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE A 16 J22 Connector Description Pn2 Jn2 64 bit PCI Continued Pin No Signal Name Direction Description Electrical Characteristics 32 C BE 2 1 0 PCI Command Byte Enable Bus PCI PCI X 33 GND N A GND GND 34 IDSELB O IDSELB for second PCI agent PCI PCI X 35 TRDY y o PCI Target Ready PCI PCI X 36 3 3V N A Positive Supply 3 3V 37 GND N A GND GND 38 STOP y o PCI Transaction Stop Signal PCI PCI X 39 PERR y o PCI Data Parity Signal PCI PCI X 40 GND N A GND GND 41 3 3V N A Positive Supply 3 3V 42 SERR y o PCI System Error PCI PCI X 43 C BE 1 1 0 PCI Command Byte Enable Bus PCI PCI X 44 GND N A GND GND 45 AD 14 1 0 PCI Address Data Bus PCI PCI X 46 AD 13 1 0 PCI Address Data Bus PCI PCI X 47 M66EN 1 0 33 66 MHz PCI operation PCI PCI X 48 AD 10 1 0 PCI Address Data Bus PCI PCI X 49 AD 08 VO PCI Address Data Bus PCI PCI X 50 3 3V N A Positive Supply 3 3V 51 AD 07 1 0 PCI Address Data Bus PCI PCI X 52 REQB l arbitration request signal for second PCI agent PCI PCI X 53 3 3V N A Positive Supply 3 3V 54 GNTB O arbitration grant signal for second PCI agent PCI PCI X 55 RESERVED N A RESERVED N A 56 GND N A GND GND 57 RESERVED N A RESERVED N A 58 EREADY l PMC ready signal PPMC 59 GND N A GND GND 60 RESETOUT l Reset signal from PMC to
47. All other brand and product names are trademarks or registered trademarks of their respective owners 814256 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE OF CONTENTS 1 Product Overview emo 1 1 General DescriptiOl asiria eniri nadan nen hoe sk aed E ue a EE EEA EEEE ANEAN EEA IRE KRA YE 1 2 xz a aa a EE a a a a a E E a aai 1 4 TECHNICAL DESCHIPEION cis a ae E a aE E AA Satire 1 4 QuadFlow Architecture 5 ore oa sade ade bee E e ma E DIE ora a Aa a a a aa 1 5 Processor Nodes wise niece cnaiciinerce cinta Verntu suite an hie vaca OEE eh Midi nite ek Aaa bd aED a Eaei 1 5 N de E Processor eee e cap cdadeadmd Ourada A ns eataeiiad a E a rena 1 6 Double Data Rate SDRAM eiceea nisu kun nan an anh snaeessitgecn teas ti i aA ANUTA at aUe RE EE E ASAREE 1 6 Flash MEMORY e P 1 7 High Speed SRAM certo r esae ues ir kk sesh AR XR URIR Rag G G7 a EENE EEEREN RS 1 7 PMG X Scr 1 7 eme icq 1 8 On Board Interrupt and Control COBIC sssssssssssssseme nemen enemies nnns 1 8 Compact PCL Interface ie csceackxe est x tenga dri es a ni AERE EEE EREDE IXRCRREYX DIES ATEN EDE T ada Ya 1 17 SeriabPOLte eicere Ge cine n pube ve cathe E d MI tame mem EP E LIMEN I LC M nd
48. BRUARY 2006 3 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING CONFIGURING AN EMULATOR FOR USE WITH COMPACT CHAMP AV IV Procedure for using the Wind River Emulator 3 8 A PowerPC 74xx or 8540 emulator may be used to interact with each processor and the board hardware on the Compact CHAMP AV IV card A COP connection is provided on the RTM for this purpose When connecting an emulator to the RTM make sure that pin one of the emulator pod aligns with pin one on the RTM connector The emulation capabilities of the Compact CHAMP AV IV with a Wind River Wind Power ICE in combination with the Wind Power IDE software has been tested Therefore the information in this section is based on the use of these tools The COP connector is shared between the five processors and can be used to control one processor at a time i e the COP connection is multiplexed The target processor is chosen via the rotary switch on the RTM Table 3 1 on page 3 9 shows the mapping bewteen the rotary switch and the processor The steps for using the Wind River emulator with the 74xx 8540 processors are outlined below For other emulators follow a similar procedure Turn off the board chassis power Connect to the COP interface of the Compact CHAMP AV IV via the RTM Select the processor to emulate via the
49. CHAMP AV IV Board Layout e e e J23 le 9 J21 e le EI wl je J24 e e J22 e e le eg L jr 1100 1020000001 iginto toio e J1 J2 J3 J4 J5 814256 VERSION 2 FEBRUARY 2006 1 21 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING FIGURE 1 9 Bottom View of Compact CHAMP AV IV PWB 1 22 IE E fo non mo DT UN eaten nop yoo ion a 0000 ok 00 1 EVO 100 A 0 0 Ces i Fo 4 1 00 0 0 D fo of m 101 a B 0 NE 1 Em es B Dn 1 ES i c umm m Up opo Or QD 00 OO D 0 DUM
50. DRAM 5 SDRAM 256 MB 256 MB 512 MB 512 MB MPC8540 8 bit General Purposel O GA 4 0 SGA 4 0 64 bit Compact PCI User I O 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 1 3 CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING FEATURE SUMMARY e PICMG 2 16 multi processor card CompactPCI form factor no cPCI interface e Four PowerPC 7448 7447A AltiVec Technology enhanced CPUs operating at up to 1 0 GHz 7447A or 1 5 GHz 7448 64 Kbyte L1 and 1 Mbyte 7448 512 Kbyte 7447A L2 internal caches operating at core processor speed 32 GFLOPs 176 SPECint95 132 SPECfp95 peak computational power 7447A 48 GFLOPs 264 SPECint95 198 SPECfp95 peak computational power 7448 e Up to 512 Mbytes DDR 266 SDRAM per processor 2 Gbyte total e PowerPC 8540 at 500 800 MHz for control functions 256 or 512 Mbytes DDR SDRAM e QuadFlow architecture with up to 3 2 GB s peak on board throughput e Five Gigabit Ethernet GbE ports one per processor e PICMG 2 16 compliance e Support for two 64 bit 100 MHz PCI X mezzanine modules PMC X e Two EIA 232 serial ports e Support for switch fabric PMC modules with differential routing to backplane e VxWorks9 Board Support Package e IXLibs AV optimized AltiVec DSP function library e Verari VSI Pro Image VSIPL DSP library e air cooled leve
51. I Address Data Bus PCI PCI X 19 AD 57 1 0 PCI Address Data Bus PCI PCI X 20 GND N A GND GND 21 VIO N A VIO Power see Note 1 5 V or 3 3V 22 AD 56 V0 PCI Address Data Bus PCI PCI X 23 AD 55 VO PCI Address Data Bus PCI PCI X 24 AD 54 V0 PCI Address Data Bus PCI PCI X 25 AD 53 V0 PCI Address Data Bus PCI PCI X 26 GND N A GND GND 27 GND N A GND GND 28 AD 52 1 0 PCI Address Data Bus PCI PCI X 29 AD 51 1 0 PCI Address Data Bus PCI PCI X 30 AD 50 VO PCI Address Data Bus PCI PCI X 31 AD 49 1 0 PCI Address Data Bus PCI PCI X 814256 VERSION 2 FEBRUARY 2006 A 25 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE A 17 J23 Connector Description Pn3 Jn3 64 bit PCI Continued Pin No Signal Name Direction Description Electrical Characteristics 32 GND N A GND GND 33 GND N A GND GND 34 AD 48 1 0 PCI Address Data Bus PCI PCI X 35 AD 47 1 0 PCI Address Data Bus PCI PCI X 36 AD 46 VO PCI Address Data Bus PCI PCI X 37 AD 45 1 0 PCI Address Data Bus PCI PCI X 38 GND N A GND GND 39 VIO N A VIO Power see Note 1 5 V or 3 3V 40 AD 44 V0 PCI Address Data Bus PCI PCI X 41 AD 43 yo PCI Address Data Bus PCI PCI X 42 AD 42 VO PCI Address Data Bus PCI PCI X 43 AD 41 yo
52. IGHT CONTROLS EMBEDDED COMPUTING TROUBLESHOOTING VERIFY INSERTION IN CHASSIS Power down the chassis Make sure that the card is properly seated in the cPCI chassis Because of the five row backplane a considerable amount of insertion force is required FAIL LED BEHAVIOR The front panel Fail LED indicates the health of the Compact CHAMP AV IV board The illumination pattern of this LED at power up or reset will differ depending upon the boot mode of the board If the board is in either of the Normal Boot Modes the Fail LED will illuminate and stay illuminated until the board is successfully initialized and tested the power on self tests will run if they are enabled see the description of PBIT in the CHAMPtools Software User s Manual If there is an error during initialization or testing the red Fail LED will stay on If PBIT detects an error the Fail LED will illuminate but the boot sequence will continue depending on the setting of the environment variable PBIT IGNORE ERRORS if possible In Recovery Mode or Boot Inhibit Mode the Fail LED will turn on and stay on until board initialization and testing is complete It will then begin to blink regardless of the success or failure of the power on self tests indicating that the card is ready to accept input at the Boot Monitor prompt If the green Processor LEDs do not turn off it is possible the cOBIC FPGA has not loaded properly Power off the card then move switch S2 4 to the
53. Jn4 User Defined I O J24 Pin No cPCI J5 J3 Pin Direction Description Electrical Number Characteristics 1 VO PMC 2 connection to cPCI J5 connector Depends on module 2 VO PMC 2 connection to cPCI J5 connector Depends on module 3 VO PMC 2 connection to cPCI J5 connector Depends on module 4 VO PMC 2 connection to cPCI J5 connector Depends on module 5 VO PMC 2 connection to cPCI J5 connector Depends on module 6 VO PMC 2 connection to cPCI J5 connector Depends on module 7 VO PMC 2 connection to cPCI J5 connector Depends on module 8 VO PMC 2 connection to cPCI J5 connector Depends on module 9 VO PMC 2 connection to cPCI J5 connector Depends on module 10 VO PMC 2 connection to cPCI J5 connector Depends on module 11 VO PMC 2 connection to cPCI J5 connector Depends on module 12 VO PMC 2 connection to cPCI J5 connector Depends on module 13 V0 PMC 2 connection to cPCI J5 connector Depends on module 14 VO PMC 2 connection to cPCI J5 connector Depends on module 15 V0 PMC 2 connection to cPCI J5 connector Depends on module 16 VO PMC 2 connection to cPCI J5 connector Depends on module 17 V0 PMC 2 connection to cPCI J3 connector Depends on module 18 1 0 PMC 2 connection to cPCI J3 connector Depends on module 19 VO PMC 2 connection to cPCI J3 connector Depends on module 20 V0 PMC 2 connection to cPCI J3 connector Depends on module 21 VO PMC 2 connection to cPCI J3 connector Depends on module 22 VO PMC
54. ME Y Ri EUER E NES A 7 J4 Connector Pin Assignments 2 ini err Rex e Ux IRR eR I REA RR E E E RI RM U E E DR A 9 J4 Connector Description esse cies cies hanh enm a aa gales den RENE nia eb sar ER Mis A 9 J5 Connector Pin Asslgniments eoi cse reo concn oie set pence d ue ke dc une etgntasamen re EDEN Kex pais A 11 B izEeorjpr TeosdDI i reisiolu oep en A 11 J11 Connector Description Pn1 Jn1 64 bit PCI sesssseeseeeemm mee A 13 J12 Connector Description Pn2 Jn2 64 bit PCI cece eect eee eee mne A 15 J13 Connector Description Pn3 Jn3 64 bit PCI sssessesee ene A 17 J14 Connector Description Pn4 Jn4 User Defined I O sssssssessrssrrsrrrsrrrrrrerrrrerrerees A 19 J21 Connector Description Pn1 Jni 64 bit PCI seseseseem eme A 21 J22 Connector Description Pn2 Jn2 64 bit PCI cece eee eect eee eee eee eee eee eeeeee A 23 J23 Connector Description Pn3 Jn3 64 bit PCI cece eee eee eee eee eee eee eee me A 25 J24 Connector Description Pn4 Jn4 User Defined I O ccececeeeeeee sees eee eeeeeeeeaees A 27 PMC to cPCI Connector Mapping for Differential Signaling sees A 29 PMC to cPCI Connector Mapping for Single Ended Signaling ecseeeeeeeeee teens eee es A 30 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Vil CoMPACT CHAMP AV IV UsER S MANUAL CURTISS
55. N 1 27 Software Development TO0ls cii serine treu eni re pa Peas va ra pares PARE elites EUR EE N PPM Sain 1 27 2 Pre 4nstallation Tasks inconnu enean an ann p nk Rn RxRR C ENEEx aU uN Enn S nans RxRMRDSl DD EC FLUFIUN M DUM AME UE 2 1 Unpacking th Card 2 orent Deua te Ma cveeta near senenae podene nee se SIRE DR RA IA TA M VRIP REA EAT 2 2 Checking Hardware Requirements cesses sese sess nena nnn haha a a iura suat u se sus nouas ausa kan sae ka 2 2 Chassis Requirements iuis eoe de etta ce dbs sa enun vk x eager ea uasa re e x ep E c geri eben ced aueh sixes 2 2 Power ReguWlre mellbs das nenihute stc indi nds tenter xDD DU NN xD e LDIV E dc EPMU INE nae ERU RT RU E DEI 2 2 Flash Configuration ParaMeters cece cece eee een eee rene e enne sene 2 4 PMC PMC X Module Installation Requirements csse nenne 2 4 Se aiieriio oreieci deo m 2 8 3 Hardware Installation llseeeseeeeeeeeeeeeeeeeeeeeeeeseeeee nennen nnn nnn 3 1 Installation Prerequisit s uiro xus pin exa a aint ea sd ee Rina A EA e ePstRa aaa e EE RENE DE E prx PIRE T RIER ahs ERN 3 2 Installation Checklist e 3 2 Unpack and Configure the Cardosses irnar innne nn hne er ktu nua sooner AANE TENTEN NEREDEN pide caer 3 2 Install the PMC Modules on the BaSeCard cccececeeeee cece eee eee eee eee saaneina ia eee eee eens tates nnns 3 3 Choose a CPCI Slot L ocatiotm r
56. NI ISIN n ERE Meee 1 17 Ethernet Interfaces i isse repe a ns E anna E A E EEUN UA ETERNA UEAEUUE 1 18 doi Cele 1 18 allg EEEUTUTEUTUMU MTM 1 19 Mni cet Emm 1 19 Temperature Voltage Sensors nrnna re kan nnne a aa a B4 R4 HR A Rau Ra Ragga R sana kar ient 1 19 COP Interface exei seen e tekkeadale EE EENE EAA A ME MERE RRRIAREFEF TURAKTZRNDAIE dada RR TRIN MERDA 1 20 Physical Characteristics 2e diede a a der ek sida c ice usse deg EN PRAE ka re fag E ERE D EE ara E aaa 1 21 SCP 424 Front Panel scaorecuneisu cuim nin son voc w alee Feu Ea aiaa Pra Resim ee ud rumeur e A inta saw ne 1 23 Mating CONNECLOLS ais iiesntscinsteiiiuihiakschanateetwtidutadeadebe isis nanehiumetedahicdandteatmetithediteutinceaanetains 1 24 DIMENSIONS iain s vsasussvux sae xeta sa E REIHEERUREEPRSKERRERETRCRRRTERIWETEYRPERKRIRREE IVRNK CR cst ENRE RENER ENDE 1 24 Weight m M 1 25 Overview of Available Software eeeseesesseseseeeeae sain naa sua ena ka n RR RR RR RRRRRENRR RRRRRRRR RA ARRRR RR RERRRRA dud 1 26 Built In Test BIT FIFEnWare secu diets ranis nter era n rbde nen eset uei Rana NR bdka sek KaaE Exe a E Ta REN REDE KE 1 26 Operating System SoftWare isisisi inana a eT ingrate Ea CREAR FEN Ru E OhE EINEN RETE e ERATES 1 26 Optimized DSP Libraries cinia terne nete rn e RR nndis xpeidnabodactiGaind cadet E E
57. O RB TXPO 4 RA RXN3 RA RXP3 GND RA TXN3 RA TXP3 3 RA RXN2 RA RXP2 GND RA TXN2 RA TXP2 2 RA RXN1 RA RXP1 GND RA TXN1 RA TXP1 1 RA RXNO RA RXPO GND RA TXNO RA TXPO ELECTRICAL CHARACTERISTICS OF J3 SIGNALS Table A 6 provides the electrical characteristics of the basecard J3 signals TABLE A 6 J3 Connector Description Signal Name Direction Description Electrical Characteristics SGA 4 0 Input Signals are pulled to 3 3v on board Shelf Geographical GND or floating on Address signals are used to provide a unique shelf ID backplane for multiple shelf systems ADxx BDxx Input Output Gigabit Ethernet signals comprised of Port A and Port IEEE 802 3 B differential pairs RAxx RBxx RCxx PMC PMC I O Signals PMC dependent dependent Note Signal details are for the basecard signals only PMC I O lines depend on the PMC modules installed and are beyond the scope of this document 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A 7 COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING J4 CONNECTOR PIN ASSIGNMENTS The pinout tables are presented in the order of the rows when looking from the backplane i e E D C B A Figure A 4 shows the location of the contacts on the J4 connector FIGURE A 4 J4 Connector J5 NO M 0 oh 25 N Xm
58. OM also provides a copy of the Adobe Acrobat Reader software version 4 0 including the Acrobat Search plug in to enable you to get the most out of your CD ROM by enabling full text searches of the information 814256 VERSION 2 FEBRUARY 2006 XIII Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV UsER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING XIV 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 1 PRODUCT OVERVIEW IN THIS CHAPTER This chapter discusses the high level features of the Compact CHAMP AV IV product The following topics are discussed e General Description on page 1 2 e Feature Summary on page 1 4 e Technical Description on page 1 4 814256 VERSION 2 FEBRUARY 2006 QuadFlow Architecture on page 1 5 Processor Nodes on page 1 5 Double Data Rate SDRAM on page 1 6 Flash Memory on page 1 7 High Speed SRAM on page 1 7 PMC X Sites on page 1 7 PCI Local Bus on page 1 8 On Board Interrupt and Control COBIC on page 1 8 Serial Ports on page 1 17 Ethernet Interfaces on page 1 18 Power on page 1 18 Reset on page 1 19 Timers on page 1 19 Temperature Voltage Sensors on page 1 19 1 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAM
59. OMPUTING FiGURE 4 2 Data Access Directions for PMCs Resource Access Resource Access Directions for PMC2 Directions for PMC1 gt Resource Access Directions for Processor E 4 6 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CONNECTOR PIN ASSIGNMENTS IN THIS APPENDIX This appendix provides the interface pinout information for each of the connectors on the Compact CHAMP AV IV The following connectors are described J1 Connector Pin Assignments on page A 2 J2 Connector Pin Assignments on page A 4 J3 Connector Pin Assignments on page A 6 J4 Connector Pin Assignments on page A 8 J5 Connector Pin Assignments on page A 10 PMC Connectors on page A 12 J11 Connector on page A 13 J12 Connector on page A 15 J13 Connector on page A 17 J14 Connector on page A 19 J21 Connector on page A 21 322 Connector on page A 23 323 Connector on page A 25 J24 Connector on page A 27 PMC to cPCI Connector Mapping for Differential Signaling on page A 29 PMC to cPCI Connector Mapping for Single Ended Signaling on page A 30 814256 VERSION 2 FEBRUARY 2006 A 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONT
60. OURCE www artisantg com XI CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Signal Table 2 lists symbols that can follow a signal name For example the Hash is used with a Conventions PCI or cPCI signal name such as FRAME TABLE 2 Signal Conventions Symbol Description The signal is active LOW no symbol The signal is active HIGH Abbreviations Table 3 lists the abbreviations used to describe the size of a memory device or a range of addresses TABLE 3 Abbreviations Abbreviation Convention 1 Kbyte 1 024 bytes 1 Mbyte 1 024 Kbytes 1 Gbyte 1 024 Mbytes Memory Unless otherwise stated all memory addresses are shown in hexadecimal notation Addresses Icons The following icons are used throughout the documentation package Cross references to other documents are used when a subject being discussed is addressed in depth by another more authoritative document Cross references are also used for document chapters and sections Cross Reference incorrectly could cause physical injury electrical damage to equipment or a non recoverable corruption of data Warnings include instructions for preventing such damage Please observe warning icons and read the accompanying text completely before Warning carrying out the procedure e The warning icon indicates procedures in the manual that if not carried out or if carried out which
61. P AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING COP Interface on page 1 20 e Physical Characteristics on page 1 21 SCP 424 Front Panel on page 1 23 Mating Connectors on page 1 24 Dimensions on page 1 24 Weight on page 1 25 e Overview of Available Software on page 1 26 Built In Test BIT Firmware on page 1 26 Operating System Software on page 1 26 Optimized DSP Libraries on page 1 27 Software Development Tools on page 1 27 GENERAL DESCRIPTION 1 2 The Compact CHAMP AV IV is a cPCI variant of our fourth generation VME based quad PowerPC AltiVec DSP board The Compact CHAMP AV IV introduces an architecture based on the latest PowerPC and PCI X bridge devices to provide a very high bandwidth platform that maximizes the processing potential of four Freescale PowerPC MPC7448 or 7447A processors The Compact CHAMP AV IV also has a powerful fifth processor the Freescale MPC8540 PowerQUICC III The Compact CHAMP AV IV is particularly well suited to large multi slot systems This is by virtue of its four 800 MB sec peak PCI buses and its five Gigabit Ethernet connections one per processor which together provide very high I O throughput and switching bandwidth This together with its four altivec enabled 7447A processors and fifth PowerPC processor allow the computing power and data movement to be well matched The Compact CHAMP AV IV has a rich set of features design
62. ROLS EMBEDDED COMPUTING J1 CONNECTOR PIN ASSIGNMENTS The pinout tables are presented in the order of the rows when looking from the backplane i e E D C B A Figure A 1 shows the location of the contacts on the J1 connector J5 J4 J3 J2 J1 FiGURE A 1 J1 Connector 25 24 23 22 21 20 F E D C B A SC V NO WEN NANI UNIX OOOOO0OQ Nu Nf Nat Naot Nou Sf Wi VIO COS CN EON OOOOOO CSC SECSCSCS DA NDA YI NA CONCSEE KuC CS Aou No ALI PX UA UJ AGOGO Nod Nod No ad RPS C NCYCNCSCYC CENA RIND RD Ns uf YC CC WC IYO WANS NANANA N CNCMCSMCY C C NA Nau Nu Nou Neh Nah DOOOOOD Mos NA Nep NA Mod V SAGAO KA NANANA NA NA C CY PI C I PYCVOV OTIS NANA NA NA RAY CSCC SEYN GP Nt RP RPS he CVO VEY VOC IRS NC NAP NC Neuf CVC VE VO VG 3093 KAP KAKA NS SY CONCONACON C WC NE X NU NC Nod Nd Nel Ned alimini OS COYOY E fet SS j 265 NAS CVC NCC Y YE YN a Ac NS DO LIU OO P oe GO Nu Nh J1 and J4 Connector Rear View Table A 1 on page A 3 shows which signals are available from the J1 connector of the Compact CHAMP AV IV A 2 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE A 1 J1 Connector Pin Assignments Pin No
63. Row E Row D Row C Row B Row A 25 5V 3 3V NC NC 5V 24 NC NC V I O 5V NC 23 NC EP5V NC NC 3 3V 22 NC NC EP3 3V GND NC 21 NC NC NC NC 3 3V 20 NC NC V I O GND NC 19 NC GND NC NC 3 3V 18 NC NC 3 3V GND NC 17 NC GND NC NC 3 3V 16 NC NC V I O GND NC 15 NC BD_SEL NC NC 3 3V 14 13 Key Area 12 11 NC GND NC NC NC 10 NC NC 3 3V GND NC 9 NC GND NC NC NC 8 NC NC V I O GND NC 7 NC GND NC NC NC 6 NC NC EP3 3V PCI PRES Z NC 5 NC GND CPCI RST RSV NC 4 NC NC V I O HEALTHY NC 3 NC EP5V NC NC NC 2 NC NC NC 5V NC 1 5V 12V NC 12V 5V Note V I O can be 3 3 or 5v to allow this to go into any slot 3 3v 5v universal ELECTRICAL CHARACTERISTICS OF J1 SIGNALS Table A 2 provides the electrical characteristics of the basecard J1 signals TABLE A 2 J1 Connector Description s Direction Basecard Signal Description MAL PCI PRES Input Pull up on PWB tied low or left floating on backplane When low indicates GND or floating on that the backplane supports a Compact PCI bus Signal is not currently backplane used on the Compact CHAMP AV IV HEALTHY Output Active low signal indicates that on board power is up and within open drain specification BD SEL Input Active low signal indicates that cPCI board is fully inserted into chassis 3 3v pull up on board and that on board power up may begin Signal is either grounded on backplane or actively driven low by an open drain driver CPCI_RST Input Active low signal
64. SER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Semaphore Registers Register information is provided for reference only Use the BSL functions to manipulate the semaphore registers There are sixteen 16 bit semaphore registers in the cOBIC Any of the five processors may clear the semaphore by writing 0x0000 Any of the five processors may claim the semaphore by writing a non zero value However the write will be ignored unless the semaphore value is 0x0000 prior to the write Thus once a processor has written a non zero value no other writes are allowed except a write of 0x0000 This functionality ensures that only one device will own the semaphore at a time and that any device is able to clear the semaphore This scheme is backwards compatible with earlier software which writes a zero to bit 7 to clear the register and cannot write to the register unless bit 7 of the register is a zero and the present write has bit 7 1 These semaphore registers are typically used to coordinate the sharing of hardware resources between multiple tasks The hardware solution provides a faster alternative to traditional software memory techniques and avoids the use of shared memory and PCI buses to access the semaphores TABLE 1 4 Semaphore Register Format 15 14 13 12 11 10 9 8 Semaphore Semaphore Semaphore Semaphore Semaphore Semaphore Semaphore Semaphore owned tag owned tag owned tag owned tag owned tag owned tag owned tag ow
65. September 30 1997 e MPC7447 A RISC Microprocessor User s Manual Rev 0 8 2003 e PowerPC Microprocessor Family The Programming Environments for 32 Bit Microproc essors Motorola e MV64460 MV64461 MV64462 System Controller for PowerPC Processors Part 1 of 2 Hardware Specification Doc Number MV S101286 01 Revision B Marvell July 22 2004 e MV64460 MV64461 MV64462 System Controller for PowerPC Processors Part 2 of 2 User Manual Doc Number MV S101286 00 Revision B Marvell July 22 2004 e Double Data Rate DDR SDRAM Spec JEDEC Standard No 79 Release 2 Feb 2002 e Stub Series Terminated Logic for 2 5V SSTL 2 JESD8 9A Dec 2000 e MPC8540 Integrated Processor Hardware Specification Rev 3 1 12 2004 e MPC8540 PowerQUICC III Integrated Host Processor Reference Manual Rev 1 7 2004 e PICMG 2 0 R 3 0 CompactPCI Specification October 1 1999 e PICMG 2 1 R2 0 CompactPCI Hot Swap Specification January 17 2001 e PCIMG 2 16 R1 0 CompactPCI Packet Switching Backplane PSB Specification Septem ber 5 2001 Please refer to DPK TechDoc CD for additional reference information supplied in Portable Document Format PDF files readable by Adobe Acrobat Reader software This Technical Documentation CD ROM includes useful weblinks an I O pinout configurator utility and a helpful guide to the VMEbus among other things You ll also find copies of the relevant cable assembly drawings on the CD The DPK TechDoc CD CD R
66. X MODULE INSTALLATION REQUIREMENTS PMC Module Voltage Types 2 4 The Compact CHAMP AV IV provides two PCI PCI X Mezzanine Card PMC PMC X sites PMC Site 1 and PMC site 2 PMC Site 1 is located between Nodes A and D while PMC Site 2 is located between Nodes B and C See Figure 1 8 on page 1 21 for an illustration of the Compact CHAMP AV IV board layout Each PMC site can be independently configured at the factory to support either 3 3V or 5V signaling on their PCI bus The PMC sites are designed to conform to the following specifications e PCI Local Bus Specification PCI SIG Revision 2 3 March 29 2002 e Draft Processor PMC Standard For Processor PCI Mezzanine Cards VITA 32 2003 Rev 1 0a April 29 2003 e IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC IEEE Std 1386 1 2001 June 14 2001 e IEEE Standard for a Common Mezzanine Card CMC Family IEEE Std 1386 2001 June 14 2001 e PCI X Auxiliary Standard for PMCs and Processor PMCs VITA39 2002 Draft 0 9a Sep tember 17 2002 e PCI X Electrical and Mechanical Addendum to the PCI Local Bus Specifications PCI_SIG Rev 2 0 Nov 4 2002 e PCI X Protocol Addendum to the PCI Local Bus Specification PCI SIG Rev 2 0 July 29 2002 A PMC can be a 3 3V board uses 3 3V signaling a 5V board uses 5V signaling or a Universal board auto selects and configures for the signaling level used by the PMC host Each PMC card is required to have a
67. a ie 3 10 giUMBPEIIIUER UD 3 10 Sign on Message Garbled 5 eise te sinsannie detest da N E hyeweh ae Kx ADR URDCURDA RATE DNE 3 10 TMG Seco 3 10 4 Programming Interface sce coe criss sss cs pe tiene anui nu usu sas EUxeHEE aM nM Do eR IR RAN DAN REA MMMGEC 4 1 Compact CHAMP AV IV Memory Map 5 oeste xe ne Eu Dx xen NAE I D DuDUF AT KU UND VE MUR PANE RR EE 4 2 Data Flow plezteu e p M M 4 4 A Connector Pin Assignments eeeeseeeeeeeeeeeeee eene enn nnnnnn nnn n anna nnn A 1 JT Connector Pin Assignimerits soso erue retorno esa ern ox nine tenne a Pian Ru RR a In IRR 4A E ra ROaRDA A 2 Electrical Characteristics of J1 Signals esee sehen hene ha nena nanus a kan hus nan aan A 3 J2 Connector Pin Assignments 5 uoescr iet e sitsceud acs x esr ia cen ER AE Ra bidian ia ERR RE RU MEE EE Ea FUE A 4 Electrical Characteristics of J2 Signals cccccecesececesseseeneeeeeeeenaeeseeeeeceneeenaenseseanaeeeeesaennenees A 5 J3 Connector Pin Assignimetts dossi sanse dss he rule tek heap RuxsRuna n max ERR EPART eR ER a KIA ERR RUM E rA ADR dE A 6 Electrical Characteristics of J3 Signals csesssssssssssssssssseseeenneneene senem A 7 J4 Connector Pin ASSIGNMENTS arses viata cese essere oes usta merce ated E Dx DMUD IINE DN RM DULDNDEME IUE MP DKET wE one ganas A 8 Electrical Characteristics of J4 Signals c
68. act CHAMP AV IV into a cPCI chassis and verify that it is operating correctly Chapter 4 Programming Interface Describes the memory maps for the Compact CHAMP AV IV Appendix A Connector Pin Assignments This appendix lists the interface connector pinouts for the Compact CHAMP AV IV RELATED SOFTWARE DOCUMENTS Wind River Systems Doumentation For information on installing the Compact CHAMP AV IV software refer to the CHAMPtools Software User s Manual document number 811489 Information describing the operation of the version 1 2 WIND POWER ICE and visionPROBE II emulators is provided in the following Wind River Systems publications e WIND POWER ICE for WIND POWER IDE User s Guide part DOC 15149 NN 00 e WIND POWER IDE Getting Started part DOC 15146 ZD 00 e WIND POWER IDE Release Notes e visionPROBE II for WIND POWER IDE User s Guide part DOC 15145 ND 00 CONVENTIONS USED IN THIS MANUAL Company Name Product Naming Conventions Typographic Conventions This document and the accompanying documents in the documentation package use various icon conventions and abbreviations to make the documents clearer and easier to read These conventions cover typography for such elements as sample software code and keystrokes signal meanings and graphical elements for important information such as warnings or cautions The abbreviation CWCEC seen in this document is used to represent the company name Curtiss Wrigh
69. allows the other nodes to focus on more processing intensive applications The 8540 can access all the memory of the other nodes and both PMCs over the PCI X bus It also has its own interface into the cOBIC so that all the features of the cOBIC are available to this device as well DOUBLE DATA RATE SDRAM Each 7448 7447A processor node on the Compact CHAMP AV IV consists of either 256 or 512 Mbytes of Double Data Rate DDR SDRAM The instantaneous peak data transfer rate to the DDR 266 SDRAM is over 2 0 GB s at 133 MHz The DDR SDRAM is accessible from the processor and from both PCI buses 1 6 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW Processor Node E has either 256 or 512 Mbytes of DDR SDRAM This memory operates at DDR 200 which gives an instantaneous peak data transfer rate of 1 6 GB s at 100 MHz Processor E memory is accessible from the processor and from the PCI bus FLAsH MEMORY The Compact CHAMP AV IV provides 32 64 128 or 256 MBytes of 32 bit Flash memory on node A The Flash devices are specified for 100 000 erase cycles per sector typical and a data retention time of 20 years typical For security against inadvertent Flash programming set Switches S2 3 and S2 4 both to the ON position Note switch is ON when the slide bar is moved towards the car
70. ammable high and low voltage and temperature thresholds The Board Support Library functions will allow the user to read the sensors at any time and to program the sensor s threshold values The Compact CHAMP AV IV has two temperature voltage sensor Integrated Circuits ICs installed on the back of the board Maxim MAX6656 The ICs are located at locations U225 and U229 see Figure 1 9 on page 1 22 In revision A of the Compact AV IV baseboard the sensors are connected to Node A of the Discovery III bridge In revision B and later of the Compact AV IV baseboard the sensors are connected to both Node A of the Discovery III bridge as well as to the MPC8540 Each sensor IC is capable of measuring three temperatures one local temperature and two remote temperatures The local temperature is the temperature of the card at the IC s location The remote temperatures are the die temperatures of the 7448 7447A PowerPC processors Sensor U225 can measure its own temperature and the die temperature of processors A and D Sensor U229 can measure its own temperature and the die temperature of processors B and C The local and remote 814256 VERSION 2 FEBRUARY 2006 1 19 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING temperature sensors can measure temperatures in the range of 55 C to 125 C and have an accuracy of appr
71. as the PMC Review your PMC module s power requirements carefully to ensure that you do not install an incorrect PMC in a Compact CHAMP AV IV PMC site FIGURE 2 1 Position of 5V and 3 3V Keying Holes on a PMC Board e 9 9joH Bulkey Age s Q O ol lt A 2 Q I o9 oO O O PMC I O The Compact CHAMP AV IV board supports front panel user I O and backplane user I O through the J3 and J5 cPCI bus connectors The backplane I O for PMC Site 1 mounted between Nodes A and D is routed out the Compact CHAMP AV IV cPCI bus J5 connector The backplane I O for the PMC Site 2 mounted between Nodes B and C is routed out the Compact CHAMP AV IV cPCI J3 connector Table A 5 on page A 7 and Table A 9 on page A 11 show the backplane I O connections for PMC sites 1 and 2 The I O signals are routed differentially 100 ohm differential impedance as noted in Table A 19 on page A 29 but may also be used in a single ended mode as seen in Table A 20 on page A 30 The differential routes are provided so that the I O will support standard PMCs as well as high speed differential PMCs PMC BUSMODE On the Compact CHAMP AV IV the PMC BUSMODE 4 2 signals are hardwired and Signals constantly drive the following values in accordance with the Common Mezzanine Card specification BUSMODE 4 2 ObOO1 This signals the PMC card that it is connected to a PMC site If the card is a PMC card it will drive a logic 0
72. baseboard PPMC 61 ACK64 N A 64 bit transfer acknowledge signal PCI PCI X 62 3 3V N A Positive Supply 3 3V 63 GND N A GND GND 64 MONARCH O enable disable MONARCH feature on Processor PPMC PMCs Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING J23 CONNECTOR Table A 17 lists the pin assignments for the connector referenced J23 This connector is part of PMC site 2 and is referenced as Pn3 Jn3 in the PMC Specification IEEE 1386 1 2001 TABLE A 17 J23 Connector Description Pn3 Jn3 64 bit PCI Pin No Signal Name Direction Description Electrical Characteristics 1 PCI RSVD N A Reserved N A 2 GND N A GND GND 3 GND N A GND GND 4 C BE 7 VO PCI Command Byte Enable Bus PCI PCI X 5 C BE 6 1 0 PCI Command Byte Enable Bus PCI PCI X 6 C BE 5 1 0 PCI Command Byte Enable Bus PCI PCI X 7 C BE 4 VO PCI Command Byte Enable Bus PCI PCI X 8 GND N A GND GND 9 VIO N A VIO Power see Note 1 5 V or 3 3V 10 PAR64 V0 PCI Parity Signal PCI PCI X 11 AD 63 VO PCI Address Data Bus PCI PCI X 12 AD 62 V0 PCI Address Data Bus PCI PCI X 13 AD 61 1 0 PCI Address Data Bus PCI PCI X 14 GND N A GND GND 15 GND N A GND GND 16 AD 60 V0 PCI Address Data Bus PCI PCI X 17 AD 59 y o PCI Address Data Bus PCI PCI X 18 AD 58 1 0 PC
73. d edge HIGH SPEED SRAM PMC X SITES Incorporated into the Discovery III system controller the Compact CHAMP AV IV provides 256 Kbytes of high speed SRAM per processor node While useful as a general purpose high performance memory area that offloads traffic to SDRAM the SRAM is particularly beneficial for holding descriptors for Discovery III peripheral devices allowing DMA units to simultaneously access data from SDRAM while descriptors are accessed from the SRAM The Compact CHAMP AV IV is equipped with two mezzanine sites compatible with the PCI PMC and PCI X PMC X standards The PMC X interfaces support 64 bit PCI X100 transfers 100 MHz PCI X with a resulting peak rate of 800 MB s The board is backward compatible with PCI X66 66 MHz PCI X PCI 66 66 MHz conventional PCI and PCI 33 33 MHz conventional PCI The interfaces are mapped to all five processor nodes allowing transfers between any node and any interface All four PMC interrupt signals may be routed under software control to any of the processors allowing the developer the choice of which processor hosts the PMC control software PMC I O is supported on both the front panel as well as the P3 and P5 backplane connectors The routing of I O signals from PMC to P3 and P5 is arranged in differential pairs with careful impedance control and matching of trace lengths This technique supports the latest generation of high performance digital interfaces included on som
74. d with or without an operating system For additional information about the Board Support Library functions please refer to the CHAMPtools Software User s Manual which provides a table of all Board Support Library functions The Software Update Utility is a Windows program that communicates with the Compact CHAMP AV IV board through the Ethernet port It is used to display and modify board configuration information upgrade board software and load application code Wind River The Compact CHAMP AV IV supports the use of the Wind Power ICE emulator or equivalent Systems Vision via COP signals which are presented on the backplane connectors Probe II Wind Power ICE Emulators 814256 VERSION 2 FEBRUARY 2006 1 27 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING 1 28 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 2 PRE INSTALLATION TASKS IN THIS CHAPTER This chapter discusses the following topics e Unpacking the Card on page 2 2 e Checking Hardware Requirements on page 2 2 Chassis Requirements on page 2 2 Power Requirements on page 2 2 Flash Configuration Parameters on page 2 4 PMC PMC X Module Installation Requirements on page 2 4 e Configuring Switches on page
75. ds on module 37 1 0 PMC 2 connection to cPCI J3 connector Depends on module 38 VO PMC 2 connection to cPCI J3 connector Depends on module 39 1 0 PMC 2 connection to cPCI J3 connector Depends on module 40 VO PMC 2 connection to cPCI J3 connector Depends on module 41 VO PMC 2 connection to cPCI J3 connector Depends on module 42 1 0 PMC 2 connection to cPCI J3 connector Depends on module 43 VO PMC 2 connection to cPCI J3 connector Depends on module 44 y o PMC 2 connection to cPCI J3 connector Depends on module 45 VO PMC 2 connection to cPCI J3 connector Depends on module 46 1 0 PMC 2 connection to cPCI J3 connector Depends on module 47 VO PMC 2 connection to cPCI J3 connector Depends on module 48 y o PMC 2 connection to cPCI J3 connector Depends on module 49 VO PMC 2 connection to cPCI J3 connector Depends on module 50 lo PMC 2 connection to cPCI J3 connector Depends on module 51 VO PMC 2 connection to cPCI J3 connector Depends on module 52 y o PMC 2 connection to cPCI J3 connector Depends on module 53 VO PMC 2 connection to cPCI J3 connector Depends on module 54 1 0 PMC 2 connection to cPCI J3 connector Depends on module 55 Jo PMC 2 connection to cPCI J3 connector Depends on module 56 VO PMC 2 connection to cPCI J3 connector Depends on module 57 1 0 PMC 2 connection to cPCI J3 connector Depends on module 58 VO PMC 2 connection to cPCI J3 connector Depends on module 59 1 0 PMC 2 connection
76. e Inter Processor Module also contains the Inter Processor Interrupt generation registers Typically the external interrupts are not latched in cOBIC since they are latched at the source However the interrupts generated from Inter Processor Interrupt generation registers IPI are latched The IPI generation register has two primary fields to consider see Table 1 3 A three bit Processor ID field defines the processor to be interrupted and a three bit field that defines the Processor Interrupt Identification value To use the register 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW a six bit value is written to the IPI register This causes the Inter Processor Interrupt Status register to be updated for the target processor The Inter Processor Interrupt Status register for the target processor reflects the decoded Processor Identification value For instance processor A writing a binary 0001 0011 to its IPI register causes Processor Identification bit 3 to be set in Processor B Interrupt Status register Note that the processor that originated the interrupt is not evident by the value in the Inter Processor Interrupt Status Register Since the Inter Processor interrupts are latched the target processor application must clear these interrupts by writing to the appropriate Inter Processor In
77. e PMCs such as the StarLink switch fabric PMC the PMC 643 Fibre Channel and the PMC 706 and PMC 708 Graphics PMCs With a pair of StarLink PMCs the Compact CHAMP AV IV can act as a combined StarFabric node and switch with a massive 3 2 GB sec of I O including switching throughput between the PMCs and the I O connectors 814256 VERSION 2 FEBRUARY 2006 1 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PCI LocAL Bus The Compact CHAMP AV IV contains four local PCI buses The four buses are interconnected through the PCI X to PCI X bridging capability of the Discovery III bridges The PCI buses connect Nodes A B C and D in a ring architecture and operate at a maximum rate of 100 MHz 64 bits 800 MBytes s Each node connects into the ring via two PCI PCI X buses This feature provides maximum data throughput on the board since each processor can access both sides of the ring simultaneously Node E is connected to the PCI PCI X segment between Nodes A amp B On reset the Compact CHAMP AV IV startup code automatically scans the PCI PCI X devices and assigns bus numbers to these segments Since the bus numbers are dynamically allocated after board reset the bus numbers may differ between power on cycles if different PMCs are installed between these events For instance if a PMC X PMC site is populated
78. ear the backplane J4 connector its I O signals are available on the backplane J5 connector When the PMC module is mounted in slot 2 near the backplane J2 connector its I O signals are available on the backplane J3 connector CHOOSE A CPCI SLoT LOCATION A Caution The Compact CHAMP AV IV does not support cPCI System Slot capability therefore it cannot be installed in the System Slot usually marked off by different color card guides Additionally in a PICMG 2 16 chassis the Compact CHAMP AV IV is considered a Node board and must be installed in a PCIMG 2 16 Node slot Ensure that the chassis your Compact CHAMP AV IV is installed in is capable of generating a minimum of 4 CFM air flow before you apply power to the board 814256 VERSION 2 FEBRUARY 2006 3 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING QUICK INSTALLATION AND POWER UP PROCEDURE Cross Reference 3 4 The following steps must be performed to get the Compact CHAMP AV IV card operational 1 Move switch S3 3 to the ON position This position is when the switch is slid towards the upper board edge It is also marked on the switch itself This selects Boot Inhibit mode which prevents the board from loading the operating system but allows it to interact with the serial port 2 With power o
79. ector Depends on module 31 VO PMC 1 connection to cPCI J5 connector Depends on module 32 VO PMC 1 connection to cPCI J5 connector Depends on module 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE A 14 J14 Connector Description Pn4 Jn4 User Defined I O Continued J14Pin cPCI J5 Pin Number Direction Description Electrical No Characteristics 33 V0 PMC 1 connection to cPCI J5 connector Depends on module 34 VO PMC 1 connection to cPCI J5 connector Depends on module 35 V0 PMC 1 connection to cPCI J5 connector Depends on module 36 VO PMC 1 connection to cPCI J5 connector Depends on module 37 V0 PMC 1 connection to cPCI J5 connector Depends on module 38 VO PMC 1 connection to cPCI J5 connector Depends on module 39 V0 PMC 1 connection to cPCI J5 connector Depends on module 40 VO PMC 1 connection to cPCI J5 connector Depends on module 41 VO PMC 1 connection to cPCI J5 connector Depends on module 42 V0 PMC 1 connection to cPCI J5 connector Depends on module 43 VO PMC 1 connection to cPCI J5 connector Depends on module 44 V0 PMC 1 connection to cPCI J5 connector Depends on module 45 VO PMC 1 connection to cPCI J5 connector Depends on
80. ed to accelerate multi processing application performance and speed the software development process A diverse offering of peripherals enable the Compact CHAMP AV IV to be readily integrated into many types of systems such as benign military signal intelligence command control and communications as well as telecommunications systems The architecture of the Compact CHAMP AV IV is illustrated in Figure 1 1 on page 1 3 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW FIGURE 1 1 Compact CHAMP AV IV Functional Block Diagram Local DDR SDRAM Local DDR SDRAM 256 MB 256 MB ZHI L 3a v9 MPC7447 t St MPC7447 A48 ios MV64460 MV64460 oz a Bridge N PCI Local Bus 2 Bridge D C PowerPC C PowerPC D PCI 0 PCI 0 64 bit xA 6t up to fe up to 64 bit 99 MHz 5 99 MHz up to 64 bit PCI X Bus g PCI X Bus 99 MHz up to e w 64 bit 99 MHz 2 On Board 5 64 bit User I O PMC1 PCI X Bus Interrupt User I O 8 and Control o cOBIC 32 bit 64 bit J 64 bit up to up to 99 MHz 99 MHz PCI X Bu PCI X Bus P pcre FLASH MPC7447 5 amp 5 S5 MPC7447 133MHz MV64460 32 128 MB AI7448 MaxBus Bridge E PCI Locd MaxBus AI7448 PowerPC PowerPC A 64 bit A Go MH B PCI X Bus Local Local DDR E DDR S
81. edere ska de edere E e a Neu A 9 JS Connector PINcASSIQHIME DES secs eiae sentier una sina Sentus me nequa EAEE utn UU noDPE Isque RAM QE N A 10 Electrical Characteristics of J5 Signals 2 2 2 iiec ia eset pe pne du e radar ai a aX FEAR Aaa gaius A 11 PMC CONNECTS oaia EE A 12 JLIP OMIMESCEO Prosan EL DE A 13 J12 CONMECON rronin der a a a aE eE Ea a EE a A 15 JAS CONNECO tis suni ieemia sure nie aerciale tule ava dieitiad vosr es san ia aana iae iaaa Die iaaa aN i i A 17 J14 COD ctor eerie yu oix orna SEA RS E E IR AE O EON a RET NEEN A 19 J21 CONMOCUON E A 21 SrPASO cg M A 23 J23 CONNE CUOT isnin isse sexe ase caasa essa VIA RR XE REA RR CAR AIPRRRRIRR RXPRSRGA A GR RGR EEE INERI Rama Y RR Sai A 25 J24 COMMECEO Fas wiria c Em A 27 PMC to cPCI Connector Mapping for Differential Signaling sseeeeeemm A 29 PMC to cPCI Connector Mapping for Single Ended Signaling esses A 30 ij et P I 1 IV 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING LisT OF FIGURES Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 Figure 1 6 Figure 1 7 Figure 1 8 Figure 1 9 Figure 2 1 Figure 2 2 Figure 4 1 Figure 4 2 Figure A 1 Figure A 2 Fi
82. endent dependent RDxx PMC Right PMC Site 2 I O Signals PMC dependent dependent Note Signal details are for the basecard signals only PMC I O lines depend on the PMC modules installed and are beyond the scope of this document 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC CONNECTORS The Compact CHAMP AV IV PMC connectors are described in the following sections The direction of the signals in the tables describing the PMC Jn1 through Jn4 connectors is from the point of view of the baseboard 814256 VERSION 2 FEBRUARY 2006 A 12 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING J11 CONNECTOR Table A 11 lists the pin assignments for the connector referenced J11 This connector is part of PMC site 1 and is referenced as Pn1 Jn1 in the PMC specification IEEE 1386 1 2001 TABLE A 11 J11 Connector Description Pn1 Jn1 64 bit PCI Pin No Signal Direction Description Electrical Characteristics 1 TCK l JTAG Test Clock PCI PCI X 2 12V N A 12V Supply 12V 3 GND N A GND GND 4 INTA l PMC Interrupt Request Line PCI PCI X
83. epending on the particular application and configuration various conditions can occur that could adversely affect and possibly damage the baseboard PMC s or chassis These conditions include but are not limited to excessive current drawn from the cPCI connectors excessive heating of baseboard and PMC components and reduction in board voltages that can cause board resets to occur Factors affecting this include but are not limited to maximum operating temperature of the board air temperature for air cooled boards and card edge temperature for conduction cooled boards airflow air cooled boards baseboard power dissipation application specific total PMC current drawn by both PMC sites from each power supply rail and the location and density of the hot components on the PMC s and or the baseboard The PMC VIO voltage can be factory configured for 5V or 3 3V signaling Please consult the user s manual for the PMC that will be installed on the baseboard to determine the VIO voltage necessary TABLE 2 4 Recommended Maximum Supply Current per PMC Site Supply Maximum Supply Current 5V 1 5A 3 3V 23A 412 V 500 mA 12 V 100 mA 814256 VERSION 2 FEBRUARY 2006 2 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING CONFIGURING SWITCHES Table 2 5 defines the switches S
84. erenced J21 This connector is part of PMC site 2 and is referenced as Pn1 Jn1 in the PMC Specification IEEE 1386 1 2001 TABLE A 15 J21 Connector Description Pn1 Jn1 64 bit PCI Pin No Signal Name Direction Description Electrical Characteristics 1 TCK JTAG Test Clock PCI PCI X 2 12V N A 12V Supply 12V 3 GND N A GND GND 4 INTA l PMC Interrupt Request Line PCI PCI X 5 INTB l PMC Interrupt Request Line PCI PCI X 6 INTC l PMC Interrupt Request Line PCI PCI X 7 PRSNT2 l BUSMODE1 signal used to indicate presence ofa PMC PPMC PMC module in site 2 8 5V N A Positive Supply 5 V 9 INTD l PMC Interrupt Request Line PCI PCI X 10 RESERVED N A RESERVED N A 11 GND N A GND GND 12 NC 3 3 V AUX N A No Connect 3 3V Auxiliary Supply 3 3 V 13 PCICLK2 O PCI Clock Signal PCI PCI X 14 GND N A GND GND 15 GND N A GND GND 16 PMC2_GNT O Arbitration Grant Signal to PMC site 2 PCI PCI X 17 PMC2_REQ l Arbitration Request Signal from PMC site 2 PCI PCI X 18 5V N A Positive Supply 5 V 19 VIO N A VIO Power see Note 1 5 V or 3 3V 20 AD 31 y o PCI Address Data Bus PCI PCI X 21 AD 28 y o PCI Address Data Bus PCI PCI X 22 AD 27 VO PCI Address Data Bus PCI PCI X 23 AD 25 1 0 PCI Address Data Bus PCI PCI X 24 GND N A GND GND 25 GND N A GND GND 26 C BE 3 0 PCI Command Byte Enable Bus PCI PCI X 27 AD 22 VO PCI Address Da
85. ff install the Compact CHAMP AV IV into the chassis Ensure the cPCI connectors are fully engaged 3 Install CWCEC or custom RTM in the back of the cPCI chassis The RTM must be installed in the same slot as the Compact CHAMP AV IV 4 Connect serial port cable between RTM connector J11 and the PC 5 Run the terminal emulation program Set the serial port for 57 6K baud 8 data bits no parity one stop bit and Xon Xoff flow control 6 Apply power to the chassis The board will initialize displaying configuration informa tion The red FAIL LED will be flashing The green LEDs will come on and then turn off to indicate a successful load of the cOBIC FPGA 7 Confirm two way RS 232 communication by entering help CR on the terminal emulator This command displays other commands supported by the boot monitor If the red LED flashes continuously but no information is displayed check the serial port configuration parameters and connection The flashing indicates the board has completed initialization and is in Boot Inhibit mode If the red LED fails to flash the board firmware is unable to complete board initialization Check board seating chassis power and observe any messages displayed via the serial port If the green LEDs do not turn off it is possible the cOBIC FPGA has not loaded properly Power off the card then move switch S2 4 to the ON position which selects the alternate SPROM see Configuring Switches on page 2 8
86. fication IEEE 1386 1 2001 TABLE A 13 J13 Connector Description Pn3 Jn3 64 bit PCI Pin No Signal Name Direction Description Electrical Characteristics 1 PCI RSVD N A Reserved N A 2 GND N A GND GND 3 GND N A GND GND 4 C BE 7 V0 PCI Command Byte Enable Bus PCI PCI X 5 C BE 6 0 PCI Command Byte Enable Bus PCI PCI X 6 C BE 5 I O PCI Command Byte Enable Bus PCI PCI X 7 C BE 4 0 PCI Command Byte Enable Bus PCI PCI X 8 GND N A GND GND 9 VIO N A VIO Power see Note 1 5V or 3 3V 10 PAR64 VO PCI Parity Signal PCI PCI X 11 AD 63 I O PCI Address Data Bus PCI PCI X 12 AD 62 1 0 PCI Address Data Bus PCI PCI X 13 AD 61 1 0 PCI Address Data Bus PCI PCI X 14 GND N A GND GND 15 GND N A GND GND 16 AD 60 1 0 PCI Address Data Bus PCI PCI X 17 AD 59 VO PCI Address Data Bus PCI PCI X 18 AD 58 1 0 PCI Address Data Bus PCI PCI X 19 AD 57 1 0 PCI Address Data Bus PCI PCI X 20 GND N A GND GND 21 VIO N A VIO Power see Note 1 5V or 3 3V 22 AD 56 VO PCI Address Data Bus PCI PCI X 23 AD 55 VO PCI Address Data Bus PCI PCI X 24 AD 54 y o PCI Address Data Bus PCI PCI X 25 AD 53 1 0 PCI Address Data Bus PCI PCI X 26 GND N A GND GND 27 GND N A GND GND 28 AD 52 1 0 PCI Address Data Bus PCI PCI X 29 AD 51 1 0 PCI Address Data Bus PCI PCI X 30 AD 50 VO PCI Address Data Bus PCI PCI X 31 AD 49 1 0 PCI Address Data Bu
87. gh TALERAD Active low cOBIC Overtemperature alarm from Nodes AD sensor not cur rently implemented TALERBC Active low cOBIC Overtemperature alarm from Nodes BC sensor not cur rently implemented INT_88E1111 Ethernet interrupt from node E Phy not currently imple mented P 3 0 INT 88E1145 Ethernet interrupts from nodes A D Phy not currently implemented Inter Processor Module The DVx PCI INT 1 0 interrupts from each node are actually the PCI interrupts from the Discovery part Through interrupt steering registers in the Discovery interrupts from various MV64460 resources DMA Timers etc can be mapped to these outputs TALERAD and TALERBC provide over temperature alarm information to the cOBIC The sensors that generate these alarms are located at U225 and U229 TALERBC originates from U229 while TALERAD originates from U225 see Figure 1 9 on page 1 22 Each temperature sensor monitors three separate temperatures TALERBC monitors the temperature of processor B processor C and the temperature of the board at the location of U23 location of itself TALERAD monitors the temperature of processor A processor D and the temperature of the board at the location of U19 location of itself In multi processor applications software designers implement message passing schemes between the various processors in the system The most common implementation is for the transmitting processor to cause an interru
88. gure A 3 Figure A 4 Figure A 5 Compact CHAMP AV IV Functional Block Diagram ccceceeee eee eee teeta mmm 1 3 Processor Node Block Diagram c ety each ta nnns inh N a ka saga x ER YREW A ER ERR KA E EEA 1 5 cOBIC Block Diagram 2 cesset nete bested agcvcused rx atero aa vases EXE Decir Di AEEA 1 9 Interr pt ROUELIFIQ suse s voess Sint nie ohio sites deles nie E tite TESE E EEA nie rua E RADO 1 10 Interm pt SUFUGEUIFE S is icesiste plac nbn De ID etes etn tiD e Ea die a A Rn uu DA dida iT Edu 1 11 LED CONTEO leer 1 16 Nodes A and E Serial Port 0 EIA 232 Asynchronous Mode ssesesssseeeeee 1 17 Compact CHAMP AV IV Board Layout ccececeeeee este ee eee e tees nemen emen esee enne 1 21 Bottom View of Compact CHAMP AV IV PWB cceeeeeee eens ee ee eee eee meme 1 22 Position of 5V and 3 3V Keying Holes on a PMC Board cccecccceeeeeeeeeeeeaeeeeeeeaeeaeeaeeeeae 2 5 Configuration Switch Locations cc cceee eee eee eee emnes memes 2 9 Data Access Directions for Processor Nodes eceeeeeee este eee ee eens teens mener 4 5 Data Access Directions for PMCS ssicssssccacsuieenadece tinta nuin imr dee cR ak ve EXER ERR ERO RR YEXRE RE Neue 4 6 Bien MrR A 2 BrAGOecp A 4 Scene E A 6 JA CODBeCtOF icoeccecesorscetusezexete ssezhessscrtae Vra g
89. has the following reset capabilities e front panel reset button e capability to be reset via software front panel reset emulation e J4 reset pin PBRST on J4 Row D pin 1 Grounding this pin is equivalent to activating the front panel reset e Individual processor reset through the Boot Monitor e cPCI system reset TIMERS The Compact CHAMP AV IV board provides a large number of timing resources to facilitate precise timing and control of system events A list of available timers is given in Table 1 5 below TABLE 1 6 Timing Resources Timer Facility Implementation Type Size Tick Rate Period Maximum Duration PowerPC Free running counter 64 bit 33 25 MHz 30 ns 17 548 years at 133 MHz Bus Speed Time Base Implementation Type Size Tick Rate Period Maximum Duration Register PowerPC Presettable readable 32 bit 33 25 MHz 30 ns 128 8 seconds counts up Decrementers Implementation Type Size Tick Rate Period Maximum Duration General Purpose Discovery IIl Presettable readable 32 bit 125 0 MHz 8 ns 34 3 seconds 0 3 counts down Watchdog Timers one per CPU cOBIC FPGA Presettable readable 24 bit 1 MHz 1 uS 16 7 seconds counts down TEMPERATURE VOLTAGE SENSORS The Compact CHAMP AV IV provides sensors to monitor board temperatures and voltage levels The sensors allow six temperatures and six voltages to be measured The sensors can generate an interrupt based on progr
90. hernet Port E of the Compact CHAMP AV IV to your Ethernet LAN via the connector labelled ENET E on the RTM Ethernet Port E is used in conjunction with the CHAMPtools Software Update Utility to burn programs into Flash memory on the Compact CHAMP AV IV See the CHAMPtools Software User s Manual for additional details Cross Reference CABLE CONNECTIONS The following cables are required by the Compact CHAMP AV IV board e Cat 5 5E Shielded Twisted Pair Ethernet Cable with RJ 45 connectors on both ends e DB 9 Female to DB 9 male serial cable These cables may be purchased through most electronics components retailers The Compact CHAMP AV IV EIA 232 serial channels are configured as DCE Data Communications Equipment The EIA 232 serial channels on personal computers and terminals are configured as DTE therefore a null modem is NOT required for communication between the Compact CHAMP AV IV and a PC terminal 814256 VERSION 2 FEBRUARY 2006 3 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING RUNNING THE BOOT MONITOR Cross Reference The Boot Monitor is a special embedded program that runs on Processor A after hardware reset Two copies of the Boot Monitor reside in Flash memory These are named bootMon and bootMon2 exe The secondary boot monit
91. ialization as well as Power up Built In Test PBIT PBIT consists of a set of essential tests that provide confidence that the hardware is operating correctly as well as test sequencing which is stored in Flash memory and is tailorable For more information see the PBIT Diagnostic Tool section of the CHAMPtools Software User s Manual as well as the CHAMPtools IBIT CBIT User s Manual Cross Reference OPERATING SYSTEM SOFTWARE The Compact CHAMP AV IV is supported with an extensive array of software items which cover all facets of developing application code for the board Users have the option of choosing to develop with a variety of operating systems and development tools The following operating systems are supported on the Compact CHAMP AV IV e A VxWorks Board Support Package BSP is available with support for the Tornado development environment The BSP supports the VxWorks Shared Memory Networking feature This allows the user to share a single network connection between multiple processors In development users can connect to a single Ethernet port and then make TCP IP connections to any processor in the system For deployed systems the shared network is especially beneficial as only a single Ethernet port must be cabled in the chassis to support in system upgrades of software e A monolithic no operating system runtime environment 1 26 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Qua
92. iii eec nnt tn nes ase ve a Ea dae e eda cu EXER DEDKE Ra EUER IS dad ERR TERRE 3 3 Quick Installation and Power Up Procedure ssssssssssseen eee eee ee eaten ene nee emen eene 3 4 Detailed Installation Procedure 1 iiri oreet ek d Iebx esas iaeano euch ba d aegRu ee MER NR ERE MER ERI KA NS 3 5 Insert the Basecard in the Chassis eeeeeseeeiiese eene nennen nenne natn nta hes nak an na kan a nana R ausu 3 5 Connect a Termirial 2 i inier cody teins tie DERE UTR Y IRR MER DENEN RIA ASTU UN E DEDE LA 3 5 Connect Ethernet Port E cecus ers desea eux uuo masks ber Deia Era uu Edu UE EANAN EAEn dt arin RENT ENDE RE 3 5 Cable CONMEOCtONS wiiisct sured E Pm 3 5 RUNNING the Boot Monitor nonna nne onn dr eek phi ni nen e kie x RE ER AT UN LR RIA he npn na tang atn RE 3 6 Initiate the Power p Sequence iiiiiisie etit stenetr t t bda ke ca gu hlaia a kra P3a Ga Ra id ie RARSR sage KR RR REN 3 6 Display the Initial Screen Message serene ne naga nu kx gea a RR saci vewatadatvedesstaes aaa RS 3 6 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Configuring an Emulator for use with Compact CHAMP AV IV ssssssse menn 3 8 Troubleshoot RR 3 10 Verify Insertion in Chassis iere rur reete ri peines hn dign bao ara aua t dog ra xa lade a Cu Etn
93. k VERE SRYK NVEFER UTR EURE CERO EE IRR ERNEEPISRTRRND NES A 8 BizXennhir celme E A 10 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV UsER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING VI 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING LisT OF TABLES Table 1 1 Table 1 2 Table 1 3 Table 1 4 Table 1 5 Table 1 6 Table 1 7 Table 1 8 Table 1 9 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 3 1 Table 4 1 Table A 1 Table A 2 Table A 3 Table A 4 Table A 5 Table A 6 Table A 7 Table A 8 Table A 9 Table A 10 Table A 11 Table A 12 Table A 13 Table A 14 Table A 15 Table A 16 Table A 17 Table A 18 Table A 19 Table A 20 Internal INterrupt SOUPCES 3 uiii itae tete dated ee qaia ta ia Eaa Ee eqar a Rs 1 11 External Interrupt SOUFCes cicer esee nce aE na add Pra EYE ARGR SXYRXI NIRE ERA EIER ANE 1 11 Inter Processor Interrupt Generation Register esessesseseee nnn 1 13 Semaphore Register Format iisise cea cuiua ea nina E eeaae Hu PERERPRRRRAXEIRRERI REF ERE 1 14 Serial Port SUMMARY sisiane inna a ania i REP GP Ga P LPa upon AE 1 17 TAMING RES OUNCES sires oragon rinii UE pde num
94. keying hole to indicate the type of PCI signaling it utilizes If the PMC s PCI bus utilizes 3 3V PCI signaling it should provide a 3 3V keying hole If the PMC s PCI bus utilizes 5V PCI signaling it should provide a 5V keying hole If both voltages can be supported then both keying holes should be provided Unfortunately not all PMCs conform to the PMC standard Figure 2 1 shows the position of the keying holes on a PMC When ordering the Compact CHAMP AV IV board the I O signaling voltage must be specified for each PMC site Each PMC site can be factory configured to support 3 3 V or 5 0 V I O signaling voltage When a PMC site is configured for 3 3 V operation the PMC site will operate properly with a 3 3 V PMC or a Universal PMC When PMC site is configured for 5 0 V operation the PMC site will operate properly with a 5 0 V PMC or a Universal PMC Note that the PMC specification requires all 5 0 V PCI buses to operate at a maximum frequency of 33 MHz 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRE INSTALLATION TASKS Please note that in either the 5V or 3 3V configuration the Compact CHAMP AV IV does not provide a keying pin due to board real estate restrictions Installing a PMC with incompatible signaling levels can cause permanent damage Warning to the Compact CHAMP AV IV baseboard as well
95. l O ruggedization TECHNICAL DESCRIPTION The operation of the Compact CHAMP AV IV is described in the following sections with reference to the high level block diagram illustrated in Figure 1 1 1 4 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW QUADFLOW ARCHITECTURE The Compact CHAMP AV IV architecture is suited to DSP applications that place a high premium on processor to memory processor to processor and PMC I O to memory bandwidth The data flow capabilities of the Compact CHAMP AV IV ensure that applications can extract the most from the raw computing performance of the four AltiVec engines The Compact CHAMP AV IV architecture encompasses three key attributes that contribute to maximizing DSP performance e The performance of the processor I O and memory subsystems e High bandwidth low latency connections between processor nodes e A non blocking bridge architecture with added data paths for simultaneous data trans fers PROCESSOR NODES The Compact CHAMP AV IV provides four high performance processing nodes connected in a ring via high speed PCI X buses Each node consists of a 1 GHz PowerPC 7448 7447A processor with 1 Mbyte 7448 512 Kbytes 7447A of internal L2 cache and its own dedicated bank of DDR 266 SDRAM Each processor node incorporates a Marvell MV64460 Di
96. lity Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRODUCT OVERVIEW OPTIMIZED DSP LIBRARIES Several DSP processing options are provided IXLibs AV is a library of fully optimized DSP functions that take advantage of the AltiVec instruction unit By using IXLibs AV the user is spared the complexity of programming the Altivec instruction unit For customers with AltiVec expertise the library includes assembly language macros and an open vector data storage format to support the mixing of user and library functions in an application See the IXLibs AV data sheet for detailed information VSI Pro a VSIPL compliant library is available from Verari Systems Scientific Subroutine Library is an SAL Scientific Algorithm Library compliant package that also features support for Standard Math legacy libraries SOFTWARE DEVELOPMENT TOOLS Board Support Library Cross Reference Software Update Utility An extensive array of software development tools utilities and libraries is available to aid in software development Some of these utilities are listed below The Board Support Library contains C functions to access hardware features of the Compact CHAMP AV IV such as interrupts semaphores VME Flash read write Watchdog Timer Multiboard Synchronization Timer indicator LEDs etc The Board Support Library is self contained code that be can use
97. ltage rails on the backplane Chassis units with built in power supplies furnished by most vendors should already have these lines connected However if the chassis is powered from a user supplied power source these lines must be connected Consult the power supply user manual if you have questions concerning the proper connection of these lines TABLE 2 2 cPCI Voltage Specifications Power Supply 5 V 3 3 V 12 V 12 V Required Tolerance 4 75 to 5 25 V 3 00 to 3 60 V 11 4 V to 12 6 V 13 2 V to 11 8 V 5V and 3 3 V power must be supplied to the board through the cPCI backplane A The cPCI chassis power supplies must be properly sized for the system and must utilize Caution remote backplane sensing to properly regulate the backplane voltages 814256 VERSION 2 FEBRUARY 2006 2 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING FLASH CONFIGURATION PARAMETERS The on board Flash contains configuration parameters that are used to configure certain features of the board These parameters are explained in the CHAMPtools Software User s Manual As explained in the CHAMPtools manual the Software Update Utility or Boot Monitor can be used to modify these parameters For initial power up of the board there should be no need to modify these parameters PMC PMC
98. m Uns dd a DuPSNES E a RenU E DNI VID DUNT UN RGE 1 19 Summary of Compact CHAMP AV IV Connectors Functions Supported 1 24 Compact CHAMP AV IV Dimensions ssssesese Hmmm nen nnn 1 24 Compact CHAMP AV IV Weight ssssssssessseemee enemies menie emen enne 1 25 Power Requ irermfierntsic ii xor ree there nena en Xe ence iR UUira DRSUGR DER Re EN 2 3 CPCI Voltage SpecificatiOris cien ent ee xa eret tenuia rhmt3 AA nne an Dane ET nc kK una nain dd cians 2 3 PPMC and PCI X SUpDpOLFE e eret neither Rat eo pPARRDRER a irn Cre Rap ERR REEEUE DUE 2 6 Recommended Maximum Supply Current per PMC Site sesssssssse 2 7 SWItCH DETINIMON LE 2 8 Selection of Target Processor via RTM Rotary SWItCHh cceeeeeeeee ee ee eee e eens eaeaeee eae 3 9 Compact CHAMP AV IV Memory Map 2 cece teeter ener 4 3 Ji Connector PIN ASSIGHIMENES 25 5 cs veces morne aaa a a E RU FRRENATUROUNIEA ERUDITUS xq Rd A A 3 Jd Connector DescripHODdmsz sie scat vedete AE aera un ae fusus salade copaR Peleo tpm vdd A 3 J2 Connector Pin ASSIQNMENUS iioii rtr orn ier aps er rok ka kn RR E S Ra gn ER Rr RE Ea A 5 J2 Connector Description eiie ce eoe enata nux nne anain ct tenes beatae Br mk sees NO ER od aaa ER Mi A 5 J3 Connector Pin Assignments x iecit peu ex teenies Ex DepERIR IRKE ug R needed ae e x DR a PE NDA ERE DU A 7 J3 Connector Description i sese eeu cag nce nune tanen Rn Rx nr aee REA ER seb teat Pau Da RANA Na
99. n Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE A 9 J5 Connector Pin Assignments Pin Number RowE Row D Row C Row B Row A 22 A 232TX A 232RX GND E 232TX E 232RX 21 GND GND GND GND GND 20 LD RXN3 LD RXP3 GND LD TXN3 LD_TXP3 19 LD_RXN2 LD RXP2 GND LD TXN2 LD TXP2 18 LD RXN1 LD RXP1 GND LD TXN1 LD TXP1 17 LD RXNO LD RXPO GND LD TXNO LD TXPO 16 LC RXN3 LC RXP3 GND LC TXN3 LC TXP3 15 LC RXN2 LC RXP2 GND LC TXN2 LC TXP2 14 LC RXN1 LC RXP1 GND LC TXN1 LC TXP1 13 LC RXNO LC RXPO GND LC TXNO LC TXPO 12 LB RXN3 LB RXP3 GND LB TXN3 LB TXP3 11 LB RXN2 LB RXP2 GND LB TXN2 LB TXP2 10 LB RXN1 LB RXP1 GND LB TXN1 LB TXP1 9 LB RXNO LB RXPO GND LB TXNO LB TXPO 8 LA RXN3 LA RXP3 GND LA TXN3 LA TXP3 7 LA RXN2 LA RXP2 GND LA TXN2 LA TXP2 6 LA RXN1 LA RXP1 GND LA TXN1 LA TXP1 5 LA RXNO LA RXPO GND LA TXNO LA TXPO 4 RD RXN3 RD RXP3 GND RD TXN3 RD TXP3 3 RD RXN2 RD RXP2 GND RD TXN2 RD TXP2 2 RD RXN1 RD RXP1 GND RD TXN1 RD TXP1 1 RD RXNO RD RXPO GND RD TXNO RD TXPO ELECTRICAL CHARACTERISTICS OF J5 SIGNALS Table A 10 provides the electrical characteristics of the J5 signals TABLE A 10 J5 Connector Description Signal Name Dir Description Electrical Characteristics E 232xx A 232xx Input Output Serial port RS 232 Signals EIA 232 LDxx LOxx LBxx LAxx PMC Left PMC Site 1 I O Signals PMC dep
100. ned tag 7 6 5 4 3 2 1 0 Semaphore Semaphore Semaphore Semaphore Semaphore Semaphore Semaphore Semaphore owned tag owned tag owned tag owned tag owned tag owned tag owned tag owned tag Avionics Style Watchdog Tim er The Compact CHAMP AV IV provides five watchdog timers one for each processor Each watchdog timer is a presettable up counter with a resolution of approximately 970 ns Time out periods from 1 us to 16 seconds can be programmed Initialization software can select whether a watchdog exception event causes an interrupt a local processor reset or a card reset The watchdog can be locked so that once enabled to cause a reset the watchdog cannot be disabled The watchdog timer can be used in two ways As a standard watchdog timer a single time period is programmed which defines a maximum interval between writes to the watchdog register For increased system integrity the watchdog can optionally be configured to operate in Avionics mode whereby a minimum interval between writes to the watchdog register is also enforced In other words writing to the watchdog register too soon or too late causes an exception event If a fault occurs the timer is stopped The following resources are provided for each Watchdog Timer e 24 bit Minimum timer e 24 bit Maximum timer e Watchdog Enable bit e Watchdog Kick register 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation
101. nerated if software kicked it less than 5ms or more than 12ms following the previous kick or from the original start When a fault occurs you want the processor associated with that watchdog timer to be reset To set up this scenario first clear the WDT EN bit in the Watchdog Control Register This disables the watchdog timer Then set the WDT RST EN bit in the Watchdog Control Register to allow a reset of the processor if a fault occurs Then write 0x0000 3053 to the Watchdog Maximum Register and 0x0000 1423 to the Watchdog Minimum Register To enable the watchdog timer set the WDT EN bit As another example suppose you wanted an interrupt generated on a fault instead of a reset This is accomplished by setting the associated bit in the Mask3 register A watchdog timer fault will then generate an interrupt At this point the watchdog timer will halt To clear the interrupt clear the WDT EN bit The Compact CHAMP AV IV provides eight additional general purpose LVTTL I O lines which are accessible at the J4 connector The GPIO signals may be configured individually to be inputs or outputs Outputs may be configured to be open drain or LVTTL Each signal is pulled up to 3 3V through a 4 7 K pull up resistor Note that 3 3V LVTTL is interoperable with 5V TTL logic Two of the GPIO lines may be configured to act as interrupt inputs either edge or level sensitive This flexibility can save a user from building custom logic to condition signal
102. o Nu E OX Br a s OOOOOO N s OOOOOO ataata ata 1 NAA A A AA AA C WCC CS 83 CO CI DOD J OOC WA 12 AAAA NA NA AA AA QOQODADADD MO X UN SS SS O ON ONION ION ON 0 DODD PONTOON GONE NON TION 9D DO AT VOC BRP UN UN UN ON 7 di P amr aa T di T di P di TID DODO O YODA OLD 6 ODO DD OOOO BIN ANAN ANAN X 4lC9C9C9C9YCSYC Ne Ne d d ld SN OODO0 3JOOOOOO gt ry 20000000 COC 112 I2 I2 AY OD J2 J3 Connector Rear View J1 Note The pinout tables are presented in the order of the rows when looking from the backplane i e E D C B A A 6 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE A 5 J3 Connector Pin Assignments Pin Number RowE Row D Row C Row B Row A 19 SGAO SGA1 SGA2 SGA3 SGA4 18 ADO TRX2 ADO TRX2 GND ADO TRXO ADO TRXO 17 ADO TRX3 ADO TRX3 GND ADO TRX1 ADO TRX1 16 BDO TRX2 BDO TRX2 GND BDO TRXO BDO TRX0 15 BDO TRX3 BDO TRX3 GND BDO TRX1 BDO TRX1 14 RPMPRES GND GND GND GND 13 NC NC NC NC 12 RC_RXN3 RC_RXP3 GND RC_TXN3 RC_TXP3 11 RC_RXN2 RC_RXP2 GND RC_TXN2 RC_TXP2 10 RC_RXN1 RC_RXP1 GND RC_TXN1 RC_TXP1 9 RC_RXNO RC_RXPO GND RC_TXNO RC_TXPO 8 RB_RXN3 RB_RXP3 GND RB_TXN3 RB_TXP3 7 RB_RXN2 RB_RXP2 GND RB_TXN2 RB_TXP2 6 RB RXN1 RB RXP1 GND RB TXN1 RB TXP1 5 RB RXNO RB RXPO GND RB TXN
103. on Stop Signal PCI PCI X 39 PERR 1 0 PCI Data Parity Signal PCI PCI X 40 GND N A GND GND 41 3 3V N A Positive Supply 3 3V 42 SERR 1 0 PCI System Error PCI PCI X 43 C BE 1 VO PCI Command Byte Enable Bus PCI PCI X 44 GND N A GND GND 45 AD 14 1 0 PCI Address Data Bus PCI PCI X 46 AD 13 1 0 PCI Address Data Bus PCI PCI X 47 M66EN 1 0 33 66 MHz PCI operation PCI PCI X 48 AD 10 1 0 PCI Address Data Bus PCI PCI X 49 AD 08 V0 PCI Address Data Bus PCI PCI X 50 3 3V N A Positive Supply 3 3V 51 AD 07 1 0 PCI Address Data Bus PCI PCI X 52 REQB l arbitration request signal for second PCI agent PCI PCI X 53 3 3V N A Positive Supply 3 3V 54 GNTB O arbitration grant signal for second PCI agent PCI PCI X 55 RESERVED N A RESERVED N A 56 GND N A GND GND 57 RESERVED N A RESERVED N A 58 EREADY l PMC ready signal PPMC 59 GND N A GND GND 60 RESETOUT l Reset signal from PMC to baseboard PPMC 61 ACK64 N A 64 bit transfer acknowledge signal PCI PCI X 62 3 3V N A Positive Supply 3 3V 63 GND N A GND GND 64 MONARCH O enable disable MONARCH feature on Processor PPMC PMCs A 16 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING J13 CONNECTOR Table A 13 lists the pin assignments for the connector referenced J13 This connector is part of PMC site 1 and is referenced as Pn3 Jn3 in the PMC Speci
104. or bootMon2 exe is field upgradeable This approach allows the secondary boot monitor to be upgraded errors in the upgrade process can be remedied by reverting to the primary boot monitor The Boot Monitor configures all on board resources and brings the board to an operational state Once the resources are configured the application named pbit exe PBIT is executed if it is present PBIT validates operation of the hardware devices present on the board After completing initialization with a satisfactory result from PBIT the Boot Monitor either transitions to an application program loaded in Flash memory or interacts with the serial port accepting and processing maintenance commands The decision to load and start an application is based on switch settings see the descriptions of S2 3 and S2 4 found in Configuring Switches on page 2 8 By setting the PBIT IGNORE ERRORS environment variable the user can force the board to continue booting even if PBIT finds an error The Boot Monitor has four modes of operation Normal Mode Boot Inhibit Mode Recovery Mode and Flash Write Protect Mode Please refer to the CHAMPtools Software User s Manual for more detailed information describing the Boot Monitor and the PBIT functions An example of the initial screen message you will see once Boot Monitor has run is shown in Display the Initial Screen Message on page 3 6 INITIATE THE POWER UP SEQUENCE This section describes the normal p
105. ower up behavior of the Compact CHAMP AV IV The Compact CHAMP AV IV Flash memory is managed by the A processor As a result processor A plays a unique role during board boot up After power on or board reset processor A loads and executes the Boot Monitor program stored in Flash memory The Boot Monitor has four modes of operation Normal Mode Normal Mode with Flash Write Protection Boot Inhibit Mode and Recovery Mode The mode selected is determined by switch settings see Table 2 5 on page 2 8 and affects the degree of board initialization and startup Please see the CHAMPtools Software User s Manual for a detailed description of these modes The Boot Monitor outputs progress messages through Processor A s rear panel serial port It also logs these messages in memory for later review These messages display configuration information switch settings and other information regarding the board initialization process DISPLAY THE INITIAL SCREEN MESSAGE 3 6 After a hardware reset the Boot Monitor in Boot Inhibit Mode will display an initial sign on message similar to the following 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING HARDWARE INSTALLATION CHAMPtools Boot Monitor Version 3 0000 Feb 18 2005 13 28 41 Copyright 2002 2004 Dy 4 Systems Inc JMP Transiti Boot inhibit mode oning to boo
106. oximately 3 C over the temperature range of 0 C to 100 C The temperatures are digitized with 11 bit resolution providing a resolution of 0 125 C The conversion time for a single measurement is 125 ms typical and 155 ms max Each sensor can measure three voltages Sensor U229 measures the following voltages 5 V voltage supplied to PMC1 3 3 V and 2 5 V Sensor U225 measures the following voltages 5 V voltage supplied to PMC2 3 3 V and 1 8 V The voltage accuracy is 1 5 over the range of 30 to 120 of its nominal value The voltage is digitized with 8 bit resolution The conversion time for a single measurement is 62 5 ms typical Each sensor has an open drain SMBus ALERT output that is connected to the cOBIC see Figure 1 4 on page 1 10 The cOBIC treats these signals as interrupt sources The ALERT interrupts are generated in response to one or more of the following conditions High or Low Temperature or High or Low Voltage Once the ALERT interrupt is asserted it remains asserted latched until it is cleared through software Each sensor has twelve programmable ALERT thresholds consisting of a high and low threshold for each temperature sensor and each voltage sensor Each sensor has an open drain over temperature OVERT output The OVERT output from both sensors are wire ored together and connected to the on board power control circuitry If either sensor s OVERT output is asserted the on board power control circuitry will turn
107. play the Initial Screen Message on page 3 6 Configuring an Emulator for use with Compact CHAMP AV IV on page 3 8 e Troubleshooting on page 3 10 814256 VERSION 2 FEBRUARY 2006 Verify Insertion in Chassis on page 3 10 FAIL LED Behavior on page 3 10 3 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Sign on Message Garbled on page 3 10 Please refer to the CHAMPtools Software User s Manual for more detailed information describing the Boot Monitor and the PBIT capabilities Cross Reference INSTALLATION PREREQUISITES Before installing the Compact CHAMP AV IV in your chassis please take a moment to review the following items and planning considerations INSTALLATION CHECKLIST Make sure you have the following items before proceeding with the installation e the Compact CHAMP AV IV board e standard cPCI chassis or PICMG 2 16 cPCI chassis e DB9 to DB9 serial cable not provided attached to a computer with a terminal emula tor program capable of operating at 57 600 baud e a standard Ethernet cable having RJ 45 connectors e the CHAMPtools CD e A Rear Transition Module RTM or custom cable for the Compact CHAMP AV IV is required in order to access the Ethernet ports and serial ports directly off the back of the board CWCEC offers an RTM fo
108. pt to occur on the receiving processor with a pre agreed protocol between the pair to define the location and content of the message The problem with this mechanism is that many board architectures suffer latencies and other slowdowns because the same PCI bus that is used for inter processor data transfers is also used for passing these interrupts The Compact CHAMP AV IV has special purpose hardware to accelerate inter processor messaging This hardware is contained in the inter processor module and consists of processor to processor mailbox interrupts and hardware controlled interrupt routing facilities The inter processor module consists of five FIFOs for support of mailbox interrupts five inter processor interrupt registers sixteen semaphore registers five watchdog timers and a multi board synchronous timer These features are described below Mailbox Interrupts The cOBIC provides mailbox interrupts whereby a processor can interrupt another processor and deliver a 16 bit value Each processor has a 16 bit 32 deep FIFO Any processor can write to the FIFO of any other processor An entry in the FIFO causes an interrupt to the associated processor if enabled The software can use the 16 bit value to include a message with the interrupt The combination of a separate data path and the inclusion of a 16 bit message can significantly reduce the latency of using interrupts to send messages between processors Inter processor Interrupts Th
109. r the Compact CHAMP AV IV CWCEC PN TBD A custom RTM may be developed as well If you design your own RTM please contact CWCEC Technical Support first to make sure that your RTM design is compatible with the Compact CHAMP AV IV product This card uses components that are sensitive to electrostatic discharges It must be kept in its conductive package until the installation begins Remove the card from its protective package only at a grounded workstation while wearing an approved grounding wrist strap Avoid touching any metal contacts on the card Warning static discharge can damage integrated circuits Turn the power off before inserting or removing cards from the cPCI chassis Failure to do so could damage the card circuitry or cause personal injury UNPACK AND CONFIGURE THE CARD Ensure that you complete the pre installation tasks described in Chapter 2 of this manual and the pre installation tasks described in the User s Manuals for any PMC modules you need to install on the Compact CHAMP AV IV 3 2 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING HARDWARE INSTALLATION INSTALL THE PMC MODULES ON THE BASECARD If the PMC modules are not already installed on the basecard install them in a PMC slot of your basecard using the appropriate CWCEC mounting kits When the PMC module is mounted in slot 1 n
110. resets boards Open drain input 3 3v pull up on board Note Signal details are for the basecard signals only PMC I O lines depend on the PMC modules installed and are beyond the scope of this document 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A 3 COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING J2 CONNECTOR PIN ASSIGNMENTS The pinout tables are presented in the order of the rows when looking from the backplane i e E D C B A Figure A 2 shows the location of the contacts on the J2 connector FiGURE A 2 J2 Connector J4 OOOOC d ww A m ON 2000 Yo Jd X UM Ss DO QG A EN PAN NYC I Nh Mt 3OQ C S OOOO JOC AAAA KANA NAN KONCNK N S e O O A FONS OOO O C Z J3 8 C N eof at C Meow O O Na bm C V C VJ N DOOQ 200OQ C Ld QOOOCO AJ CVC Mu NF V N CV ES XN OOOOQO J2 J2 and J5 Connector Rear View J1 Table A 3 on page A 5 shows which signals are available from the J2 connector of the Compact CHAMP AV IV A 4 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING
111. riph E periph E periph E periph illegal E periph EC10_0000 EC10_FFFF 65 KB OBICE OBIC E OBIC E OBIC E illegal OBIC E F000 0000 F7FF FFFF Flash illegal illegal illegal illegal illegal FEO0 0000 FEO00 FFFF 64 KB PMC 11 0 PMC 1 I O PMC 1 I O PMC 1 I O PMC 11 0 illegal FE10 0000 FE10 FFFF 64 KB PMC 21 0 PMC 2 I O PMC 2 I O PMC 2 I O PMC 21 0 illegal FE20 0000 FE20 FFFF 64 KB local bridge local bridge local bridge local bridge local bridge illegal FE40_0000 FE40_FFFF 64 KB local OBIC local OBIC local OBIC local OBIC local OBIC illegal FE60 0000 FE63 FFFF 256 KB local SRAM local SRAM local SRAM local SRAM illegal illegal FE70_0000 FF7F_FFFF 64 KB illegal illegal illegal illegal Lcl periph FFFO 0000 FFFO OFFF 4 KB illegal mem A mem A mem A illegal mem A 0000 0000 0000 0000 0000 0000 0000 0000 814256 VERSION 2 FEBRUARY 2006 4 3 COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING 1 The Compact CHAMP AV IV supports up to 512 MB of local SDRAM memory per node When ordered with less than 512 MB of local SDRAM memory the local memory space always begins at address 0000 0000 2 Only the first 256 MB of local memory is accessible by other PCI devices on the PCI bus This corresponds to local SDRAM space 0000 0000 through OFFF FFFF 3 Only the first 128 MB of local memory for node E is accessible by other PCI devices on the PCI bus This corresponds to local SDRAM space 0000
112. rst release 2 BC February 2006 Removed warning label from Chapter 2 page 5 COPYRIGHT NOTICE The information in this document is subject to change without notice and should not be construed as a commitment by Curtiss Wright Controls Inc While reasonable precautions have been taken Curtiss Wright Controls Inc assumes no responsibility for any errors that may appear in this document No part of this document may be copied or reproduced without the prior written consent of Curtiss Wright Controls Inc The proprietary information contained in this document must not be disclosed to others for any purpose nor used for manufacturing purposes without written permission of Curtiss Wright Controls Inc The acceptance of this document will be construed as an acceptance of the foregoing condition Copyright 2006 Curtiss Wright Controls Inc All rights reserved TRADEMARKS Acrobat is a trademark of Adobe Systems Incorporated Altivec is a trademark of Motorola Inc Ethernet is a trademark of Xerox Corporation PowerPC is a trademark of International Business Machines Corporation UNIX is a registered trademark in the U S and other countries exclusively licensed through X Open Company Ltd VxWorks and Tornado are registered trademarks of Wind River Systems Inc Verari Systems is a trademark and VSI Pro is a registered trademark of Verari Systems Inc Wind River is a trademark of Wind River Systems Inc
113. s PCI PCI X 32 GND N A GND GND 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A 17 COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE A 13 J13 Connector Description Pn3 Jn3 64 bit PCI Continued Pin No Signal Name Direction Description Electrical Characteristics 33 GND N A GND GND 34 AD 48 1 0 PCI Address Data Bus PCI PCI X 35 AD 47 1 0 PCI Address Data Bus PCI PCI X 36 AD 46 VO PCI Address Data Bus PCI PCI X 37 AD 45 1 0 PCI Address Data Bus PCI PCI X 38 GND N A GND GND 39 VIO N A VIO Power see Note 1 5V or 3 3V 40 AD 44 VO PCI Address Data Bus PCI PCI X 41 AD 43 VO PCI Address Data Bus PCI PCI X 42 AD 42 VO PCI Address Data Bus PCI PCI X 43 AD 41 VO PCI Address Data Bus PCI PCI X 44 GND N A GND GND 45 GND N A GND GND 46 AD 40 1 0 PCI Address Data Bus PCI PCI X 47 AD 39 VO PCI Address Data Bus PCI PCI X 48 AD 38 VO PCI Address Data Bus PCI PCI X 49 AD 37 1 0 PCI Address Data Bus PCI PCI X 50 GND N A GND GND 51 GND N A GND GND 52 AD 36 VO PCI Address Data Bus PCI PCI X 53 AD 35 1 0 PCI Address Data Bus PCI PCI X 54 AD 34 1 0 PCI Address Data Bus PCI PCI X 55 AD 33 VO PCI Address Data Bus PCI PCI X 56 GND N A GND GND 57 VIO N A VIO Power see Note 1
114. s a separate 16 bit port into the On Board Interrupt and Control c OBIC FPGA except for Node A which has a 32 bit port see On Board Interrupt and Control COBIC on page 1 8 for details With each PowerPC having a dedicated bus to its own memory application performance does not degrade as it does in shared memory designs The processor bus between the MPC7448 MPC7447A and the Discovery III bridge operates at a bus speed of 133 MHz and utilizes the PowerPC MPX mode of operation providing higher memory bus performance compared with the 60x bus Each processing node has two independent 64 bit 100 MHz PCI X connections one to each of the adjacent nodes Separate simultaneous transfers can occur on all four QuadFlow of the PCI X segments resulting in a peak aggregate bandwidth of 3 2 GB s The peak PCI bandwidth into any one node is 1600 MB sec High throughput translates to lower latencies in application performance Another advantage of the dual PCI X connections at each node is that transfers between adjacent nodes do not traverse a PCI PCI bridge and thus only one PCI segment is used This requires only a single PCI arbitration cycle once again providing minimum latency for data transfers The Discovery III bridge features a highly programmable arbitration controller which allows priority allocation between the processor PCI and DMA engines for access to the DDR SDRAM memory Users can fine tune the priority of these devices to suit
115. s to be used as interrupt sources At the present time there is no support in the Board Support Library for these General Purpose I O and Interrupt inputs 814256 VERSION 2 FEBRUARY 2006 1 15 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING General Board Support The General Board Support module provides the features below e Readable and writable test registers to facilitate Discovery device interface testing e Processor ID information associated with each Discovery device interface e COBIC Device Revision Register e Global LED control registers e Local LED control registers e Jumper status information read from eight input pins e Software controlled independent processor resets included with a standard board reset Indicator LEDs The Compact CHAMP AV IV provides fifteen user controllable LEDs Five of these are the green processor status LEDs which are visible on the front panel of the air cooled version and ten more are surface mount LEDs located on the back of the board see Figure 1 9 on page 1 22 All of the Compact CHAMP AV IV surface mount LEDs can be controlled by any of the processors writing to the Global LED register Further each of the processors has a processor LED register that controls the green processor status LED and two of the surface mount status LEDs See Figure 1 6 on page
116. scovery III bridge which acts as a non blocking crossbar interface between the MPC7448 7447A processor the DDR SDRAM two 64 bit 100 MHz PCI X buses and Gigabit Ethernet See Figure 1 2 for additional details FIGURE 1 2 Processor Node Block Diagram PowerPC 7447A 7448 1 0 1 5 GHz MV64460 Bridge PMA i A N PCI X 100 64 Crossbar N PCI X 100 64 7 V Fabric N Serial A Device Bus to cOBIC see Figure 1 3 Gigabit y Ethernet DDR SDRAM 256 MB In multi processing applications problems are either addressed by spreading the data set across many processors or by utilizing the processors in a pipeline with each processor performing a stage of the algorithm In either case the application requires the transfer of data between processors The data movement is often the limiting feature of board performance rather than raw computing power The QuadFlow architecture solves the processing and data flow requirements of high performance embedded systems 814256 VERSION 2 FEBRUARY 2006 1 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING Each node connects to two adjacent nodes via a pair of PCI X interfaces and provides an off board high bandwidth Gigabit Ethernet connection Each node ha
117. serial ports one on Node A and the other on Node E The serial port for Node A is implemented using the Discovery III Multi Protocol Serial Controller MPSC while the serial port for Node E is implemented in the 8540 On board EIA 232 transceivers are used to convert the electrical signals between EIA 232 and LVTTL levels Serial Port Summary PORT SIGNAL NAME FUNCTION Node A A 232 TX Transmit Data Serial Port 0 A_232_RX Receive Data Node E E 232 TX Transmit Data Serial Port 0 E 232 RX Receive Data Figure 1 7 illustrates the signal names and direction input or output associated with Serial Port 0 on Nodes A and E FIGURE 1 7 Nodes A and E Serial Port 0 EIA 232 Asynchronous Mode TXDO A 232 TX MV64460 Port 0 Node A X CEIVER TXDO E_232 TX MPC8540 Port 0 Node E X CEIVER Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING ETHERNET INTERFACES POWER The Compact CHAMP AV IV has five Gigabit Ethernet interfaces one per processor Processors A D MPC7447A 7448 use the Gigabit Ethernet MAC located in their associated MV64660 Discovery III bridge There are two Ethernet interfaces per Discovery III Ethernet 0 and Ethernet 1 Only Ethernet 0 is used The Discovery III bridge implements a number of features that are designed to minimize processor
118. t Controls Embedded Computing which is a division of Curtiss Wright Controls Inc The generic product name Compact CHAMP AV IV is used throughout this manual to represent the SCP 424 commercial version of the Compact CHAMP AV IV Table 1 lists the typographical conventions used in this documentation package 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE 1 Typographic Conventions Item Convention Example Keystrokes Keys are listed as they appear on most keyboards Type Ctrl Alt C gt to return to the previous menu surrounded by marks Combinations of key Type Esc gt to exit strokes appear within a single set of brackets File Names File names are set in italics Copy the file named bootA exe Directory Names Directory names show the full directory path The last directory in the path does not have a trailing slash following it Go to the c windows temp backup directory Monitor Displays Prompts and other text appearing on monitors is set in bold monospace type BootMon gt Firmware Code Firmware code and any informtion you need to type in response to a prompt is set in monospace type bootMon2 exe 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 S
119. tMon2 exe CHAMPtools Boot Monitor Version 3 0000 Feb 18 2005 13 28 41 Copyright 2002 2004 Dy 4 Systems Inc Board Board Proc Reset SDRAM Flash L2CR OBIC SIO Bridge Bridge Bridge Bridge Bridge PCI PCI PCI PCI Pole PBIT Compact CHAMP AV IV rev A 1 s n 3022232 MAC Address 00 80 7f 64 f0 10 PowerPC 7447A 1066 MHz core PVR 0x80030101 HIDO 0x8490812c Bus 133 MHz Power Up 256 MB commercial temp range 1 937 uS refresh 258 count addr config 0x00000002 config 0xd8200102 timing hi 0x0000000a timing 1o 0x01502220 64MB 0x00001000 1066 MHz OBIC NG revision 0 c Using default options configuring A configuring B configuring C configuring D configuring E Bus 0 mode is 64 bit 66MHz PCI Bus 1 mode is 64 bit 66MHz PCI Bus 2 mode is 64 bit 66MHz PCI Bus 3 mode is 64 bit 66MHz PCI Scanning for devices delay 1000 mS cannot find pbit exe skipped Boot Inhibit jumper installed BootMon gt Note that in Normal Boot Mode a similar sign on message to that shown above will be displayed followed by the following additional information Transiti Copyrigh CPU Dy4 Version oning to bootA exe VxWorks System Boot t 1984 2002 Wind River Systems Inc CompactChamp AV IV VxWorks5 5 BSP version 1 2 4 Creation Press an 7 date February 20 2004 15 56 27 y key to stop auto boot VxWorks Boot 814256 VERSION 2 FE
120. ta Bus PCI PCI X 28 AD 21 y o PCI Address Data Bus PCI PCI X 29 AD 19 y o PCI Address Data Bus PCI PCI X 30 5V N A Positive Supply 5V 31 VIO N A VIO Power see Note 1 5 V or 3 3V 814256 VERSION 2 FEBRUARY 2006 A 21 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE A 15 J21 Connector Description Pn1 Jn1 64 bit PCI Continued Pin No Signal Name Direction Description Electrical Characteristics 32 AD 17 y o PCI Address Data Bus PCI PCI X 33 FRAME VO PCI Cycle Frame Signal PCI PCI X 34 GND N A GND GND 35 GND N A GND GND 36 IRDY yo PCI Initiator Ready Signal PCI PCI X 37 DEVSEL VO PCI Device Select Signal PCI PCI X 38 5V N A Positive Supply 5V 39 PCIXCAP y o PCI X Mode select 66 vs 100 MHz operation PCI PCI X 40 LOCK y o PCI Lock Signal y o 41 RESERVED N A RESERVED N A 42 RESERVED N A RESERVED N A 43 PAR VO PCI Parity Signal PCI PCI X 44 GND N A GND GND 45 VIO N A VIO Power see Note 1 5 V or 3 3V 46 AD 15 1 0 PCI Address Data Bus PCI PCI X 47 AD 12 VO PCI Address Data Bus PCI PCI X 48 AD 11 1 0 PCI Address Data Bus PCI PCI X 49 AD 09 VO PCI Address Data Bus PCI PCI X 50 5V N A Positive Supply 5V 51 GND N A GND GND 52 C BE 0 0
121. te to clear Interrupt Mask Read and Write Interrupt Pending Read Interrupt Mask Register DVX INT 0 is the logical OR of ProcX_IP1 bits DVX INT 1 is generated by ORing the bits of ProcX IP2 and ProcX IP3 More information describing the operation of the various external interrupts seen in Figure 1 5 is provided below in Table 1 2 TABLE 1 2 External Interrupt Sources Interrupt Input Detection Mode Location for Description Clearing PMCA D C B A Active low Source Interrupts A D from PMC in Site 1 PMC2LID C B A Active low Source Interrupts A D from PMC in Site 2 DVA PCI INT 1 0 Active low Source PCI Interrupts from MV64460 Node A DVB PCI INT 1 0 Active low Source PCI Interrupts from MV64460 Node B DVC PCI INT 1 0 Active low Source PCI Interrupts from MV64460 Node C DVD PCI INT 1 0 Active low Source PCI Interrupts from MV64460 Node D DVE PCI INT 1 0 Active low Source PCI Interrupts from MPC8540 Node E 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE 1 2 External Interrupt Sources Continued Interrupt Input Detection Mode Location for Description Clearing GPIO 2 1 Edge Rising or Source User Interrupts from cPCI connector J4 pins B25 and Falling or Level D25 Active Low or Hi
122. terrupt Status IPIS register For the example described above processor B receives an interrupt from processor A with a status value reflecting INT3 asserted in the Inter Processor Interrupt Status register The user must write a one to this bit to clear the interrupt TABLE 1 3 Inter Processor Interrupt Generation Register Processor Identification Bits Interrupt Identification Bits 7 6 5 4 3 2 1 0 Not Used Not Used Processor Identification Bits 5 3 Definition 000 Reserved 001 Interrupt Processor A 010 Interrupt Processor B 011 Interrupt Processor C 100 Interrupt Processor D 101 Interrupt Processor E 110 Reserved 111 Interrupt Processors A B C D E Interrupt Identification Bits 2 0 Definition 000 Interrupt 0 INTO is passed to the target processor 001 Interrupt 1 INT1 is passed to the target processor 010 Interrupt 2 INT2 is passed to the target processor 011 Interrupt 3 INT3 is passed to the target processor 100 Interrupt 4 INT4 is passed to the target processor 101 Interrupt 5 INT5 is passed to the target processor 110 Interrupt 6 INT6 is passed to the target processor 111 Interrupt 7 INT7 is passed to the target processor 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV U
123. tion The Compact CHAMP AV IV configuration software will not perform enumeration on the respective PMC until the PMC releases this signal The Compact CHAMP AV IV provides support for an optional second PCI Agent Non monarch PPMCs may include an optional second PCI agent The Compact CHAMP AV IV only supports one load per PMC PCI signal Per the PMC specification the Compact CHAMP AV IV only allows a PMC to place one load on each PCI signal Failure to adhere to this requirement can cause timing violations on the affected signals resulting in data loss and or corruption Warning 2 6 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PRE INSTALLATION TASKS PMC Module Power Considerations A Caution The Compact CHAMP AV IV supplies 5V 3 3V VIO 12V and 12V power to the PMC sites According to the PMC specification the maximum power dissipation allowed for each PMC site is 7 5 Watts see Table 2 4 The Compact CHAMP AV IV is designed to follow this specification and in some cases exceed it Other combinations of PMCs i e an 8 Watt PMC on Site 1 a 7 Watt PMC on Site 2 may be possible Please consult CWCEC technical support before installing a PMC that exceeds the 7 5 Watt PMC standard to determine if it can be safely supported in your specific application and configuration D
124. to cPCI J3 connector Depends on module 60 VO PMC 2 connection to cPCI J3 connector Depends on module 61 y o PMC 2 connection to cPCI J3 connector Depends on module 62 VO PMC 2 connection to cPCI J3 connector Depends on module 63 y o PMC 2 connection to cPCI J3 connector Depends on module 64 VO PMC 2 connection to cPCI J3 connector Depends on module A 28 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING PMC To CPCI CONNECTOR MAPPING FOR DIFFERENTIAL SIGNALING TABLE A 19 PMC to cPCI Connector Mapping for Differential Signaling J14 to cPCI J14Pins cPCI J5 Pins J24to cPCI J24 Pins cPCI J3 J5 Pins Pair PMC Site 1 Pair PMC Site 2 1 1 3 D20 E20 33 1 3 D4 E4 2 2 4 A20 B20 34 2 4 A4 B4 3 5 7 D19 E19 35 57 D3 E3 4 6 8 A19 B19 36 6 8 A3 B3 5 9 11 D18 E18 37 9 11 D2 E2 6 10 12 A18 B18 38 10 12 A2 B2 7 13 15 D17 E17 39 13 15 D1 E1 8 14 16 A17 B17 40 14 16 A1 B1 9 17 19 D16 E16 10 18 20 A16 B16 11 21 23 D15 E15 12 22 24 A15 B15 13 25 27 D14 E14 14 26 28 A14 B14 15 29 31 D13 E13 16 30 32 A13 B13 17 33 35 D12 E12 18 34 36 A12 B12 19 37 39 D11 E11 20 38 40 A11 B11 21 41 43 D10 E10 22 42 44 A10 B10 23 45 47 D9 E9 24 46 48
125. tor A 10 description A 11 JTAG COP interface 1 20 L LED control 1 16 mating connectors 1 24 memory map 4 2 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL N Nodes A and E Serial Port 0 EIA 232 Asynchronous Mode 1 17 O OBIC block diagram 1 9 On Board Interrupt and Control OBIC 1 8 Operating System software 1 26 optimized DSP libraries 1 27 ordering cables 3 5 P PCI local bus 1 8 physical characteristics 1 21 PMC Connectors A 12 PMC slots 1 23 PMC X sites 1 7 power 1 18 power requirements 2 2 pre installation tasks 2 1 processor node block diagram 1 5 processor nodes 1 5 Q QuadFlow architecture 1 5 R reset 1 19 S serial communications connecting a terminal 3 5 serial port summary 1 17 serial ports 1 17 Sign on Message Garbled 3 10 slot location 3 3 software development tools 1 27 software overview 1 26 summary of Compact CHAMP AV IV connectors 1 24 SVME 424 Front Panel 1 23 T technical description 1 4 temperature voltage sensors 1 19 terminal settings 3 10 The Next Step 3 10 timers 1 19 timing resources 1 19 Troubleshooting 3 10 Artisan Technology Group Quality Instrumentation CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING U Unpack and Configure the Cards 3 5 unpacking the card 2 1 V Verify Insertion in Chassis 3 10 VME memory 4 4 VME slave memory map 4 4
126. uaranteed 888 88 SOURCE www artisantg com CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING HARDWARE INSTALLATION 9 Type inn to get into BKM mode do not type in as this command will attempt to ini tialize the Discovery III bridge 10 Communication with the board should now be established Because the inn com mand performs a processor reset the PC counter of the target processor will be reset to location OXFFF00100 the PPC reset vector Therefore typing go from the BKM prompt without loading a program will cause the processor to lose connection with the emulator 11 In order to execute user code on any of the processors load a program into the target using the emulator and then set the PC counter to the start address of the program To execute the code type go Make sure that the signaling level on the emulator pod connected to the COP interface on the Compact CHAMP AV IV is set to 3 3V Failure to do so could cause damage to the baseboard or the emulator Warning TABLE 3 1 Selection of Target Processor via RTM Rotary Switch Target Processor Rotary Switch Position PowerPC A PowerPC B PowerPC C PowerPC D PowerPC E Serial COP JTAG Mode Reserved Qo No oO A oc DY Reserved 814256 VERSION 2 FEBRUARY 2006 3 9 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WR
127. up Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING MATING CONNECTORS Table 1 7 summarizes these connectors providing a brief description and an indication of what functions interfaces are supported by each TABLE 1 7 Summary of Compact CHAMP AV IV Connectors Functions Supported Connector Designation Description Supported I O Configurations J11 J12 J13 connectors for PMC module site 1 compliant with Connectors used for interconnection with optional 32 J14 IEEE P1386 bit or 64 bit PMC module All 64 PMC module site 1 I O signals are accessible via the basecard PO con nector J21 J22 J23 connectors for PMC module site 2 compliant with Connectors used for interconnection with optional 32 J24 IEEE P1386 bit or 64 bit PMC module All 64 PMC module site 2 I O signals are accessible via the basecard P2 con nector rows A and C J3 95 pin 5 x 19 2mm connector PMC Site 2 I O signals Gigabit Ethernet interfaces forn processors A and B J4 125 pin 5 x 25 2mm connector Gigabit Ethernet interfaces for processors C D and E GPIO signals PowerPC COP emulator interface signals J5 110 pin 5 x 22 2mm connector PMC Site 1 I O signals EIA 232 serial ports for Nodes A and E For complete descriptions of all the basecard mating connectors including detailed pinout listings and
128. vely Figure Modules 1 5 notes how these interrupts are routed to the interrupt outputs connected to each processor Interrupt Routing As can be seen from Figure 1 4 and Figure 1 5 the cOBIC provides an interrupt routing function In a single processor system it is obvious where all interrupt processing tasks are handled In a multi processor system a fixed mapping of hardware interrupts to specific processors is likely to be less then optimum The Compact CHAMP AV IV allows the hardware to adapt to the needs of the software All of the internal and external interrupt sources PMC modules GPIO PCI etc are routed into a software configurable multiplexer that allows any processor to receive interrupts from any device This feature speeds interrupt response time by routing the interrupt directly to the intended processor Since the interrupt status registers are within the accelerator the application avoids using the PCI bus during the interrupt service routine thus reducing the incurred latency FIGURE 1 4 Interrupt Routing Temp Volt 88E1111 MPC7447 MV64460 MV64460 MPC7447 PowerPC CPUE Bridge DUNS E Pye Bridge Cru PowerPC x1 x2 TALERT x2 x1 D D x2 INT_88E1111 Cc Cc DVD PCI INT DVC PCI INT x2 x2 On Board Interrupt PMC1 mS and Control FPGA dii ue PMC2 cOBIC DVA PCI INT DVB PCI INT x2 x2 DVE_PCI_INT_ MPC7447 BUE MV64460 DA INT x2 BYEINT MV64460 Piin MPC7447 n PowerPC x1 Bridge
129. ware Users Software User s Manual Manual Release Notes Compact SHAME tools CHAMP AV IV VSP Release VxWorks BSP Notes included on and Driver Suite CHAMPtools 811489 CD ROM 814454 Contents Contents Contents Contents Software architecture information regarding the Installation Instructions information regarding overview most recent CHAMPtools Building Applications the most recent BootMon description release Device Drivers CHAMPtools VSP Board Support Library Memory Map release description Debugging ANSI C Library description BSL Flash programming details Extended Shell Commands Software Update Utility Software Update Utility Memory Map PBIT information CHAMPtools Software Documentation 814256 VERSION 2 FEBRUARY 2006 IX Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV UsER s MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING SCOPE This manual contains the following chapters Chapter 1 Product Overview This chapter provides an overview of the features and functions of the Compact CHAMP AV IV This includes a technical description of the block diagram Chapter 2 Pre Installation Tasks This chapter discusses tasks that must be performed before installing the Compact CHAMP AV IV in a system including checking power requirements Chapter 3 Hardware Installation This chapter explains how to install the Comp
130. with a device that further segments the PCI PCI X bus the bus numbers assigned will differ compared to those that would be assigned for a device that did not contain the additional buses The PCI X bus between Nodes A and B and between Nodes C and D will always operate in PCI X100 mode PCI X mode at 100 MHz 64 bit However the speed of PCI PCI X buses between Nodes B and C and between Nodes A and D will depend upon the PMC X PMC that is installed on those buses A 33 or 66 MHz PMC will drop the speed of the bus on which it is installed to PCI33 or PCI66 PCI mode at 33 or 66 MHz respectively A signalling voltage of 5 volts VIO will also drop the speed of the PCI bus to PCI33 ON BoARD INTERRUPT AND CONTROL COBIC 1 8 The Compact CHAMP AV IV has special purpose hardware to accelerate inter processor messaging and control as well as to provide other important board capabilities such as watchdog timers semaphores and LED control Each node has a unique connection into the COBIC through the Device Interface on the Discovery controller except the 8540 which has a connection through its local bus interface This allows the user to access the feature set of the cOBIC without having to use a PCI bus The board support library in CHAMPtools contains functions to support the cOBIC features Because these functions are provided detailed information regarding the cOBIC registers and bit format is not provided in this manual If the user desires
131. y 3 3V 16 BUSMODE4 O Basecard indicates PCI protocol used for PMC PMC PPMC interface by driving this line low 17 RESERVED N A RESERVED N A 18 GND N A GND GND 19 AD 30 y o PCI Address Data Bus PCI PCI X 20 AD 29 1 0 PCI Address Data Bus PCI PCI X 21 GND N A GND GND 22 AD 26 1 0 PCI Address Data Bus PCI PCI X 23 AD 24 1 0 PCI Address Data Bus PCI PCI X 24 3 3V N A Positive Supply 3 3V 25 IDSEL O PCI Initialisation Device Select for PMC Site 2 PCI PCI X 26 AD 23 1 0 PCI Address Data Bus PCI PCI X 27 3 3V N A Positive Supply 3 3V 28 AD 20 1 0 PCI Address Data Bus PCI PCI X 29 AD 18 1 0 PCI Address Data Bus PCI PCI X 30 GND N A GND GND 31 AD 16 1 0 PCI Address Data Bus PCI PCI X 814256 VERSION 2 FEBRUARY 2006 A 15 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CoMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING TABLE A 12 J12 Connector Description Pn2 Jn2 64 bit PCI Continued Pin No Signal Direction Description Electrical Characteristics 32 C BE 2 V0 PCI Command Byte Enable Bus PCI PCI X 33 GND N A GND GND 34 IDSELB O IDSELB for second PCI agent PCI PCI X 35 TRDY 1 0 PCI Target Ready PCI PCI X 36 3 3V N A Positive Supply 3 3V 37 GND N A GND GND 38 STOP V0 PCI Transacti

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