User Manual - Hytec Electronics Ltd
Contents
1. Page 18 of 27 Hytec Electronics Ltd 2530 UTM G 19 1 0 5 16 Sliding Scale Test register Read Write Address Base lE os ois Foz pos Ds 09r 0 5510 sso sss 557 sse sss 554 583 552 SS so o DAC 12 bits first 2 bit must be zero and last 2 bits must be zero these are control bits This register is used for testing of the Sliding Scale function 5 17 User ID register Read Write Address Base 20 vis vos or oos os om v 000 o fo y o jJ o jojo um 95 ups UID2 UID UIDO The user can enter an 8bit ID which will be appended to the Header D16 D23 in List mode 6 VME System Reset 6 1 A VME system reset will clear the following registers e CSRCB Memory Offset Register e IP Interrupt Select register 7 Sliding Scale Correction If ARM 1 and SS 0 then sliding scale counters for each channel will increment If ARM 0 or SS 1 then sliding scale counters are cleared to zero The sliding scale value of each channel is loaded every time the channel flag is set 8 FPGA OPERATION The controlling firmware is implemented in a Field Programmable Gate Array FPGA The code has been written in VHDL and consist of a number of state m2. o o m Page 16 of 27 Hytec Electronics Ltd 2530 UTM G 17 1 0 5 4 Memory Offset Read Write Address Base 06 DIS D14 D12 DII DIO Dos Do A31 a30 A29 A28 A27 A26 A25 A24 A23 A22 A21 X X X X The memory offset sets the memory base address in pages of 128K words 200 and D01 are ignored 5 5 List Mode Memory Address Counter LS Read Write Address Base 08 Dis DI4 D12 DIO Do9 Dos Do7 Dos Do4 Do2 DO DOO In this version of the firmware removing ARM List mode does not clear memory address counter 5 6 List Mode Memory Address Counter MS Read Write Address Base 0A Dis DI4 D12 DIO Do9 Dos Do7 Dos Do4 002 DO DOO x xup oe qox x 18618 5 7 Interrupt Vector Read Write Automatically read by operation Address Read Base Write Base DI5 DI4 D12 DIO Do9 Do7 Dos Dos Do4 Do2 DOO The interrupt vector register can be overwritten and read The vector is generated during cycle when the module has interrupted This allows 208 writes as well as reads 5 8 Calibration And Test Regis
3. Hytec Electronics Ltd 2530 UTM G 25 1 0 APPENDIXC Jumper Identification NADC253 JUMPER IDENTIFICATION GATE M S BAS BUSY DRTR R lt 000 e ES L GATE1 GATE8 w Moa m e NN GEORG 24 INPUT RMPLIFIER Set0 8v GRIN INV NON INV 52ohm Tremination AGND J REND AGN D Vcc Page 25 of 27 Hytec Electronics Ltd 2530 UTM G 26 1 0 APPENDIX D Digital Signals NIM Nuclear Instrument Module Terminated Signals The characteristic impedance for terminated signals 1s 50 ohms as set out in the table below Logic 0 Logic 1 Outputs into 50 ohms 2 to 2 mA 4 to 18 mA Inputs 4 to 20 mA 12 to 36 mA ECL Emitter coupled logic ECL running on negative supply 1 00V Viow 1 80V Page 26 of 27 Hytec Electronics Ltd 2530 UTM G 27 1 0 APPENDIXE Modification to Allow Operation on Non VME64 Backplanes This modification is required if there is no 3 3V supplied via the back plane i e a non VME 64 backplane The diagram below shows the wire modification to connect the on board 3 3V to the fuse F3 The bottom of the wire is attached to the underside of the 3V3 test pin The top end of the wire is attached to the fuse F3 top holder To check the mod there should be continuity
4. Board Serial Number OxCB OxCF 0xD3 0x001000 Offset to SN 0xD7 OxDB OxDF 0x001003 Offset to END SN Data Access Width 0x103 0x84 Accepts 032 D16 or DO8 EO cycles AM code mask 0x123 Ox13F 0x2200A2000000BB00 AM codes 3D 39 2F 2D 29 OF 0D 0C 0B 09 08 Page 21 of 27 Hytec Electronics Ltd 2530 UTM G 22 1 0 APPENDIX B PCB Jumper and Link Settings MGATE INPUT 00 socket Jumper d s Causes conversion of input pulses coincident with Gate Master Gate applies to all inputs in List mode For ECL input put jumper IN And if MGATE input is not driven J8 For input jumper OUT No termination jumper OUT J7 Jumper IN puts 51ohm termination on MGATE input And if MGATE input 15 not driven FAST CLEAR inner Jumper FAST CLR INPUT Lemo 00 socket p setting Clears all peak detectors to zero within 50ns For ECL input put jumper IN And if Fast Clear input is not driven J10 o For NIM input jumper OUT No termination jumper OUT J9 Jumper IN puts 51ohm termination on Fast Clear input And if Fast Clear input is not driven Page 22 of 27 Hytec Electronics Ltd 2530 UTM G 23 1 0 MBUSY MBUSY OUTPUT 00 socket Jumper de ud Output signal NIM ECL generated when a pulse is accepted and remains true until all circuits are free to accept a new input 1 3
5. D27 D26 D25 024 D23 D22 D21 D20 D19 D18 D17 D16 Header 031 230 D29 D28 D27 D26 D25 D24 p23 D22 D21 D20 D19 pis pi7 Di6 p D 1 847 7546 545 S45 TS42 TS41 1540 and Top Byte Fors Tos oz T Dos DO Jrimestamp Top rss rsse sss 1821 1890 129 rs 1827 1996 25 22 orc Post 530 229 28 927 026 ps 022 is DIT JTimestamp Header es pr9 1819 818 787 1516 Bottom Byte Eois Tos Tos o o Dos por Dos bos 99s 02 T 999 Bottom Word 029 Tz pes To oz zr T T9 Tos DIT J DIG Number Es perro TIL Legere je puse per event Fors Toi oi o2 Dor 5 0o oz or 99 19 An 9 ab os AD 07 Ap olan 05 AD 62 AD 1 AD 09 DIS of Block and rois Tos Tos os on Tos bor ove Ts po DOT DOO ecis ecu ec 11 c 10 o ec os ec o7 zc oc ec os ec sc 03 zc oz ec or FEC two bytes denote the number o
6. 000 Hist 2 0002 0 000 Hist 1 0 000 Hist 0 0000 MA 0 1 MA 0 0 BD63 Page 15 of 27 Hytec Electronics Ltd 2530 UTM G 16 1 0 5 Firmware Registers 5 1 Manufactures Device ID Read Address Base 00 Value 0x 1F7F DI5 D12 DII DIO Do9 Dos Do7 Doe Dos Do4 DOO 0 00 ee a 5 2 Address Base 02 0x09E2 2530dec DIS D14 D12 DIO Do9 Dos Do4 DO2 Lo 5 3 Control amp Status Register CSR Control Write Address Base 04 Note NU Not Used DIS D14 D12 DIT DIO DO9 Do7 Dos Do4 Do2 pol DOO HE GE ZE IT m ro arm LE 5 aov FFCLRJ SC iDR SS Rst Status Read Address Base 04 Note NU Not Used DIS D14 D12 DIO Do9 Dos Do7 Dos Do4 D02 DOO HE GE z IT I2 ro LE IS an SC SS Bsy HE Enables histogram mode GE Enables Gate mode ZE Enables zero conversion an input registers 0 if not in coincidence with Gate IT This sets the Interrupt source IT 0 interrupt from Full and
7. 3 Non Inverted Channel Input Range 74 Chans 1 8 0 to 8 0V place link in J4 1 2 0 to 2 0V place link in J4 2 3 not yet tested FPGA Boot J20 Master Made when Master FPGA IC22 IC23 SPROM installed 124 Must be IN Factory set bottom ejector handle over ride Grounds LK1 GND to AGND When made connects Analogue Ground to Digital Ground NOTE Do not remove this link as component damage may result Pre charge voltage pins LK2 Fit for VME creates with out Pre charge voltage pins Set Base Address 115 119 Base address To use VME64 geographical addressing lines all jumpers should be inserted in to position 1 2 To use the user set base address removing all Base address jumpers from positions 1 2 and insert the required jumpers in to positions 2 3 With no jumpers in position 2 3 for J19 to J15 the address is 0x0000 A16 or 0x000000 A24 With one jumpers in position 2 3 for 115 the address 15 0x0800 A16 or 0x080000 A24 With all jumpers in position 2 3 for J19 to J15 the address is OXF800 A16 or OxF80000 A24 Base Addrs Hex J19 2 3 J18 2 3 J17 2 3 J16 2 3 J15 2 3 16 A24 A15 A14 A13 A12 A11 0000 000000 OUT OUT OUT OUT OUT 0800 080000 OUT OUT OUT OUT IN 1000 100000 OUT OUT OUT IN OUT 1800 180000 OUT OUT OUT IN IN E000 00000 IN IN IN OUT OUT E800 E80000 IN IN IN OUT IN F000 F00000 IN IN IN IN OUT F800 F80000 IN IN IN IN IN Page 24 of 27
8. For ECL output put jumper across 1 and 2 712 must be OUT l 3 For NIM output put jumper across 2 and 3 J12 must be IN For ECL jumper OUT no termination J12 For NIM put jumper IN This puts 51ohm termination on MBUSY output DATA RDY DATA RDY OUTPUT Lemo 00 socket Tan Jumper Asserted when any Half full or Full flag is set and can be cleared by setting writing to Full or Half Full flags in Fullness register Or it can be set by a number of events 1 3 For ECL output put jumper across 1 and 2 712 must be OUT J13 l 3 For NIM output put jumper across 2 and 3 J12 must be IN For ECL jumper OUT termination 14 For put jumper IN This puts 51ohm termination on DATA output GATE Chan Individual Channel Input GATE Chan Nos INPUT Lemo 00 socket Jumper Individual channel Gates allow conversions on coincident channels in Histogram mode and List mode For ECL input put jumper IN J6 And if GATE X input is not driven Chans lt 9 For NIM input jumper OUT 15 No termination jumper OUT Chans 1 to 8 Jumper IN puts 51ohm termination on GATE X input And if GATE X input is not driven Page 23 of 27 Hytec Electronics Ltd 2530 UTM G 24 1 0 Channel Input Terminations J1 Chans 1 8 When made 56R is connected across the respective input Channel Input Inverted non inv J2 and J3 Chans 1 8 2 2 3 J3 1 2 Inverted J2 1 2 J3 2
9. Half full flags IT l interrupt when the event count is greater than the value in the Number Events to Data Ready Flag register IP0 2 Sets interrupt priority level ARM Start acquisition according to mode Automatically cleared on memory full in List Mode IE Interrupt Enable An IRQ is generated if IS is set and interrupts are enabled The IRQ number is determined by 2 This bit 15 cleared during interrupt cycle ROAK IS Read only Interrupt status set by any mask enabled fullness flag or by number of events CLTS Write only This clears the Timestamp counter when ARM is not asserted FFCLR Write only This forces a fast clear on all channels FFCLR bit auto cleared after approx 100ns SC Set calibration ON see Calibration Register oDR Data Ready set by any mask enabled fullness flag or by a set number of events iDR 0 Data Ready set when any of the channel flags are set iDR 1 Data Ready set when a programmed number of events occurs SS Sliding scale set to 0 enabled and set 1 disabled Busy Set when an input pulse pulses have been accepted and are being converted This remains true until all inputs are free to accept new input Rst Clears status register to zero GE MODE Test mode convert no gate not put into memory Histogram mode Gate mode using front panel Master Gate data put in to memory in list mode Histogram were individual gates on front panel are used
10. Vidiv 2870 927 927 imebase 8 72 200 108 200 10GS s Edge _ List Mode gate left open 0 1 ZE 0 UserID 0xAA Input to channel I P3 In this case where a double pulse occurs only the first peak is captured Vertical Timebase Trigger Disp List Mode Data File 0x02AA0100 0x05004289 0x0698B7D6 0x100212BC 0x04000001 Measure Math Analysis Utilities Help Trigger E iebase 8 00 2 00 psidiv 10 GS s ns AX 0018 2 50ns 1 for Trigger Normal 108V Edge ositivi Page 13 of 27 Hytec Electronics Ltd 2530 UTM G 14 1 0 4 3 2 Memory Data Histogram mode Spectra for each input are stored in memory in Histogram mode as shown Memory top Base 64K 32 bit words D31 D16 115 D00 Spectrum 8 8K channels x 32 Counts number of times a conversion value occurs input 8 0 000 OxDFFF Spectrum 7 8K channels x 32 Counts the number of times a conversion value occurs for input 7 0xC000 OxBFFF Spectrum6 8K channels x 32 Counts the number of times a conversion value occurs for input 6 0xA000 Ox9FFF Spectrum 5 8K channels x 32 Counts the number of times a conversion value occurs for input 5 0x8000 Ox7FFF Spectrum 4 8K channels x 32 Counts the number of times a conversion value o
11. pulse starts to rise at some point it exceeds a programmed voltage which determines the lower level discriminator setting This is set to be above the noise threshold When this voltage is exceeded the discriminator output opens a linear gate This gates the pulse to a capacitor which charges up to the peak voltage This stored voltage is compared with the input pulse and when it exceeds the amplitude of the input pulse because the input tails away the linear gate 1s closed and the peak voltage is held on the capacitor The voltage stored on the capacitor is then buffered and switched to an ADC for conversion to a binary value 2 4 Why is good integral and differential non linearity important The measured voltage is proportional to the energy of the detected particle The spectrum of energies present needs to be measured and it is important that there is a linear relationship between the different energies This is defined by the integral linearity of the ADC The ADC converts the input voltages to 8K different values The input voltage is a continuous variable and many voltages may have the same converted value This range is termed a bin and the width of the bin is determined by the differential non linearity of the ADC A pulse derived from a radiation detector will be subject to statistical variation and its value may be spread across several bins Therefore if a number of pulses derived from the same energy are converted and the conversions w
12. ED blue indicates that the module is powered and configured Page 5 of 27 Hytec Electronics Ltd 2530 UTM G 6 1 0 1 5 Signal Specifications 1 5 1 Pulse Inputs 1 8 Connector type Lemo 00 socket isolated from panel Centre pin Signal Outer AGND Signal Pulse with rounded top Span 0 to 8 191V ImV per channel Polarity jumper selectable Rise time 100ns 20us for accurate peak detection Input impedance 1K 50R jumper selectable ADC resolution 13 bits 8000 channels with sliding scale correction Diff non linearity 2 over 99 of range Int non linearity 0 025 over 99 of range Offset error 1LSB Gain Error 1LSB Gain Drift 20ppm per deg C Offset Drift 2ppm per deg C ADC conversion 3uS per input Dead time lus 20us depending on mode and input usage Gate period 20ns 20us 1 5 2 Gate Input Gates 1 8 and Master Gate Connector type Lemo 00 socket Signal NIM ECL Causes conversion when the peak of the input pulse is coincident with Gate Master Gate applies to all inputs in List mode Individual gates allow conversions on coincident channels in Histogram mode and List mode 1 5 3 Fast Clear Input Connector type Lemo 00 socket Signal NIM ECL Clears all peak detectors to zero within 50ns 1 5 4 Busy Output Connector type Lemo 00 socket Signal NIM ECL Output signal generated when a pulse is accepted and remains true until all circuits are free to accept a new
13. HYTEC ELECTRONICS Ltd 5 CRADOCK ROAD READING BERKS RG2 UK Telephone 44 0 118 9757770 Fax 44 0 118 9757566 E mail sales hytec electronics co uk Copyright 2008 Hytec Electronics Ltd Data and specifications are subject to change without notice NADC2530 8 CHANNEL 13 BIT VME NUCLEAR ADC USER MANUAL PCB Issue 3 FPGA Version 2530V307 Document Nos 2530 UTM G x 1 0 Date 12 10 2009 Author AB MRN 6 Hytec Electronics Ltd 2530 UTM G 2 1 0 1 DESCRIPTION 4 1 1 POWER REQUIREMENTS 5 1 2 OPERATING TEMPERATURE 5 1 3 od ee tette ir REEF om 5 1 4 FRONT PANEL INDICATORS 1245 tr eite oen te Ee eet 5 1 5 SIGNAL SPECIFICATIONS ee rete cip tete ERE Ee ore 6 1 5 1 Inputs T S eet 6 1 5 2 Gate Input Gates 1 8 and Master 6 1 5 3 Fast Clear In putt eoe b tee eu tene 6 1 5 4 B sy Output iiec S RE GIU ERR NU ees 6 1 5 5 Data Reddy Outputs ies ovis eo m d ee 6 2 TECHNICAL NOTE FOR THE 2530 eeeeeeee reset 7 2 1 WHATIS THE 2530 dte pir ar ere ur Ord gre o gs 7 2 2 WHAT ARE THE PULSES THAT IT MEASURES 7 2 3 HOWS THE PULSE MEASURED 7 2 4 WHY IS GOOD I
14. Memory Data List Mode 12 4 3 2 Memory Data Histogram 14 4 3 3 Memory Data Histogram Mode sse eene nennen 14 44 PCBMEMORY AND 15 5 FIRMWARE REGISTERS eese esee ee eene essen ts so seta stesso t ens seta 16 5 1 MANUFACTURES DEVICE ID 16 5 2 DEVICE TYPE READ 16 5 3 CONTROL amp STATUS REGISTER 16 5 4 MEMORY OFFSET READ WRITE 17 5 5 MEMORY ADDRESS COUNTER LS 17 5 6 LIST MODE MEMORY ADDRESS COUNTER MS READ WRITE 17 5 7 INTERRUPT VECTOR READ WRITE AUTOMATICALLY READ BY AN IACK OPERATION 17 Page 2 of 27 Hytec Electronics Ltd 2530 UTM G 3 1 0 5 8 CALIBRATION AND TEST REGISTER READ WRITE 17 5 9 FULLNESS FLAG REGISTER 17 5 10 INTERRUPT MASK NUMBER EVENTS TO DATA READY FLAG REGISTER READ WRITE 18 5 11 LOWER LEVEL DISCRIMINATOR VALUE READ WRITE 18 5 12 UPPER LEVEL DISCRIMINATOR VALUE READ WhRITE 18 5 13 EVENT COUNTER LS READ WRITE 18 5 14 EVENT COUNTER MS 18 5 15 CONVERSION READ ADDRESS 18 5 16 SLIDING SCALE TEST REGISTER READ WRITE ADDRESS BASE 1E 19 5 17 USER ID REGISTER READ WRITE ADDRESS BA
15. NTEGRAL AND DIFFERENTIAL NON LINEARITY IMPORTANT 7 2 5 WHAT IS SLIDING SCALE CORRECTION 7 2 6 WHY USE A HISTOGRAM MODE Ta AEE E EE E T 8 2 WHATIS EIST MODE ore oer Ere docete ehe PER ek Ra aee od 8 3 OPERATING MODES 9 3 1 SEDET RIGGERING deca eee sav d ert te ede ud heen 9 3 2 LAST ZEROVENABEE 5 2 25 21 0o fn eis e das He ede e ERN 9 3 3 HISTOGRAM MEMORY obedire es 9 3 4 IB MEMOR T dM Cx 9 3 5 INTERRUPT SETTINGS e e tele e ute ie e e ed e e Rd s 9 3 5 1 Hist Mode Interruption cederent leis 9 3 5 2 List Mode Interrupts tired b e Eb UE 10 3 6 TIMESTAMP rte toe 2 tess vs or TREE Ee 10 4 USE OF THE VME DATA BUS AND MEMORY ACCESS eeeeeeeee esee eese eese en etta sen 10 4 1 BASE ADDRESS iem tit tet e et ofa 10 4 1 1 Short Addressing A16 AM29h and 11 ADDRESS MODIFIERS ccce erae ehe nackte ebat ec mna bete eek 11 4 1 2 Standard Addressing 424 AM39h and 3DR sss 11 ADDRESS MODIEIBRS 5 ance fce eee oet rait t ere i ne ode e rediere 11 4 1 3 Carrier board Configuration ROM A24 11 42 MEMORY ACCESS eot Sale ea Hien es 11 43 EXTENDED ADDRESSING ADDRESS MODIFIERS 11 4 3 1
16. ONVERSION CRITERIA STROBES DUAL PORT RAM CTRL CONTROL FPGA DATA VME BUS 2530 8 CHANNEL VME NUCLEAR ADC BLOCK DIAGRAM Page 20 of 27 Hytec Electronics Ltd APPENDIX A Configuration ROM 2530 UTM G 21 1 0 Address Offset Value Definition 0x03 Check Sum 0x07 00 Length of ID ROM MSB 0x0B 02 Length of ID ROM Ox0F 00 Length of ID ROM LSB Configuration ROM data access width 0x13 0x83 Use D16 or D8 CSR data access width 0 17 0 83 Use D16 D8 CSR space Specification ID 0 1 0 02 VME64x 1997 Identify a Valid CR Ox1F 0x43 0 23 0 52 R Manufacturer s ID 0x27 0x00 0x2B Ox1F Ox2F Ox7F Board ID 0x33 4 hex ANSI N Nuclear 0x37 0x41 hex ANSI A ADC m S 0 9 2 2530dec Revision ID 0x43 0x03 PCB issue 0x47 0x03 Xilinx version same as PCB issue 0x4B 0x00 Xilinx revision nos 0x4F 0x01 Xilinx revision nos ASCII string null terminated 0 000000 0x53 0x00 0x57 0x00 0x5B 0x00 Reserved for future use 0 5 to Ox7B Program ID code Ox7F 0x01 No program ID ROM only Interrupt capabilities OxF7 OxFE Denotes support for Int levels 7 1 Start of VME64X Defined CR 0x83 0x87 0x8B 0x001004 Offset to USER Ox8F 0x93 0x97 0x001103 Offset to END USER
17. SE 20 19 6 SYSTEM ccccccccscscscesssscscccescesscecsecsseccsccsecceacsacsecseccensenceecsecssecssecsecceacsncsecceneese 19 6 1 VME SYSTEM RESET WILL CLEAR THE FOLLOWING REGISTERS eerte 19 7 SLIDING SCALE CORRECT ION ceres eren thats 19 8 19 9 DATA e 19 10 NADC2530 BLOCK DIAGRAM eere eene en setas tosta stato seta seasons tastes 20 APPENDIX A CONFIGURATION ROM tns ta sons tn seta sessanta sensns etn ana 21 APPENDIXB PCB JUMPER AND LINK SETTINGS eeeeeeee 22 APPENDIX C JUMPER IDENTIFICATION eee eee eene e eene nsns tasso natns tests sento aen 25 APPENDIXD DIGITAL 1 eese tastes sone 26 APPENDIXE MODIFICATION TO ALLOW OPERATION ON NON VME64 27 Page 3 27 Hytec Electronics Ltd 2530 UTM G 4 1 0 1 Description The Hytec ADC2530 is a VME module that provides 8 channels of peak sensing voltage digitisation with the following characteristics 8 pulse inputs Single sampling ADC and 8 input multiplexer 13 bits resolution 8000 chann
18. achines and discrete logic Lower level detector LLD asserted on rising pulse the module waits for Peak Detect PKDET to go low If this does not go low within a defined time 125ns the system times out and a fast clear is invoked and the reading aborted If PKDET set Low then unit waits for PKDET High If at this point ARM 0 or if LLD 0 gate open on a glitch or if ULD 1 to small or to fast a pulse then again fast clear set and reading aborted 9 Data Format Data format 0 0000 0V 0x0001 ImV 8 191 Page 19 of 27 Hytec Electronics Ltd 2530 UTM G 20 1 0 10 NADC2530 BLOCK DIAGRAM P1 1 1 gt 1 PEAK DET1 gt GATE1 3 P2 v2 VP AMP 2 gt cc2 PEAKDET2 GATE2 ey pa gt 16 gt gt PEAKDET3 gt GATES F 8 P4 v4 E 4 gt CC4 PEAKDET4 gt E GATE4 di 64 81 8 WAY MUX P5 V5 uP AMP 5 gt 5 PEAKDET5 gt SATEE 8 BIT DAC lt 3 6 V6 uP AMP 6 gt cce PEAKDET6 gt a lt GATEG PET Q 5 lt 81 81 P7 V7 UPAMP7 gt gt PEAKDET7 gt a GATE zn 8 T P8 v8 8 gt ccs PEAKDET8 gt GATES ey 9 9 Q Q lt C
19. between 3V3 test pin and the pos of capacitor C9 The fuse F3 must be removed When the module is powered up the BLUE led on the front panel of the NADC2530 should come ON and then go OFF in under a couple of seconds to indicate that the power supplies and the FPGA are up and running PCB TOP EDGE A 0 0 D T 99 e 5c e PCB BOTTOM eee ees 7 ole 906 2 e eeoooo000000902029802029 9 99 eee 0 0 8 6 9 9 9 e eoo9soooo9000020292690 260606002666 e eeo906260628 389 e e e e e e e e e e e e e e e e e e e e e e e e e e e e 10 gaam D oS gg l ELITS gy Page 27 of 27
20. ccurs for input 4 0x6000 OxSFFF Spectrum 3 8K channels x 32 Counts the number of times a conversion value occurs for input 3 0x4000 0x3 FFF Spectrum 2 8K channels x 32 Counts the number of times a conversion value occurs for input 2 0x2000 Spectrum 1 8K channels x 32 Counts number of times conversion value occurs input 1 0x0000 Memory base Value in Memory Offset Register 4 3 3 Memory Data Histogram Mode DI5 D14 DI3 DI2 DIO Do7 Dos bos Do4 Do2 DOI DOO S0 31 denotes ADC conversion sampling frequency data An overflow will set Full Page 14 of 27 Hytec Electronics Ltd 2530 UTM G 15 1 0 4 4 PCB MEMORY and DATA PATH Total memory 512K x 32 bits 0 00000 0x7FFFF Total memory 256K x 64 bits 0x00000 0x3FFFF Mem Block 1 VME MA3 A0 BDO 1 4 256k 16615 20 17 5 256k 16615 ExtMEM Wr OE ExtMEM Wr WE 2 0 lt 0 gt CS Mem Block 2 VMEMA3 A0 BD32 18 256k 16615 20 17 19 256k 16615 ExtMEM Wr OE N ExtMEM Wr WE 2 1 CS lt 1 gt CS BD63 Mem Block 2 Mem Block 1 Address Chan 7 222 Hist FFF Chan 7 423 Hist FFE BFFFF Chan 7 777 Hist FFD Chan 7 555 Hist FFC BFFFC 0 000 Hist 3 0
21. els Sliding scale correction of differential non linearity 2 differential non linearity 0 025 linear non linearity OV 8 191V input range positive or negative going jumper selectable 1k input impedance jumper selectable On board dual port SRAM Code format straight binary List or histogram modes Event counter for list mode Self triggering or Gated modes 3us conversion and readout time per input Front panel Gate Fast clear Data ready Busy NIM ECL signals Two DAC settings for common Lower Level and Upper Level discrimination Front panel Lemo 00 co axial connectors Front panel LED status indication Page 4 of 27 Hytec Electronics Ltd 2530 UTM G 5 1 0 1 1 Power Requirements 5 300 12 200 quiescent 12V 200 quiescent 1 2 Operating Temperature Range 0 to 45 deg Celsius ambient 1 3 Mechanical 6U single width VME module with access to P1 and P2 connectors 1 4 Front Panel Indicators VME LED green illuminates for a minimum of 100msecs whenever the module 15 accessed the VME bus ARM LED red indicates that the module is Armed and is acquiring data BUSY LED red indicates that an input pulse has been accepted and is being converted GATE LED red illuminated when the module is in Gate mode INTR LED red indicates that the conditions for interrupt have occurred does not indicate a VME interrupt on to the backplane CONFIG L
22. ents of the configuration ROM Address modifiers 2 Configuration ROM Control amp Status Registers 4 2 Memory Access The unit s base address is stored as an offset in the Memory Offset register The module uses address lines A21 to A31 The unit also supports 32 bit VME block transfer mode BLT and 64 bit MBLT for memory access Memory data may be written and read using A32 D64 D32 D16 EO Words and bytes are accessed via 215 000 A1 addresses the low order word of a longword AO the high order word big endian thus 0 accesses the first conversion Al the second and so on 4 3 Extended Addressing Address Modifiers Memory AM 09 or 0D extended non privileged or supervisory BTL AM or extended non privileged or supervisory MBTL AM 08 or extended non privileged or supervisory Page 11 of 27 Hytec Electronics Ltd 2530 UTM G 12 1 0 4 3 1 Memory Data List Mode Memory top Base 512K x 32 bit words D31 D16 D15 D00 DO T e List mode data MS List mode data LS Memory base Value in Memory Offset Register 031 D30 D29 D27 D26 D25 D24 D23 D22 D21 D20 D19 D17 pog o 7 9106 9165 UsermD pois ois por T Tos oo os bos Ts sr vaid chans 1 LI l1 7 1 D31 D30 D29 D28
23. f valid channels in the event 0000 none and 1000 8 2 denote the channel number 000 chan1 and 111 chan8 PP3 denotes the number of pulses received by a channel for a single event ADxx denotes ADC conversion data bit ECO EC23 denote the event count Bits 24 26 in each 32 bit word denote header value end of block If ZE set number of valid channels will always be set to 8 and those channels which do not convert will have there channel numbers recorded and zero as there conversion data Page 12 of 27 Hytec Electronics Ltd 2530 UTM G 13 1 0 List Mode gate left open 0 GE 1 ZE 0 UserID 0xAA Input to channel I P3 In this case 3 pulses digitised and the largest recorded Vertical Timebase Trigger Display 0x02AA0100 0x05002444 0x065197D1 0x300212B7 0x04000001 Cursi ors Measure Math Analysis Utilities Help 300 mV offset 2 870 V ofst COT 005 5 _ n 971 mv Xi 50ns Ax 0018 t 176 971 2 50ns 1 LeCroy Bo for Trigger List Mode gate left open HE 0 GE 1 ZE 1 User ID Input to channel I P3 In this case 3 pulses digitised and the largest recorded List Mode Data 0x02AA0800 0x050026DD Ox0611F169 0x00000000 0x00010000 0x300212B5 0x00030000 0x00040000 0x00050000 0x00060000 0x00070000 0x04000001 1 00
24. input 1 5 5 Data Ready Output Connector type Lemo 00 socket Signal NIM ECL Asserted when any Half full or Full flag is set and can be cleared by writing to Full or Half Full flags in Fullness register Or it can be set by a number of events Page 6 of 27 Hytec Electronics Ltd 2530 UTM G 7 1 0 2 Technical Note for the ADC2530 2 1 What is the 2530 This is a VME64 module which accepts up to eight voltage pulsed signals It measures their peak heights and either counts the number of occurrences at certain peak heights for each input channel histogram mode or stores the conversions sequentially in its memory list mode 2 2 What are the pulses that it measures The input signals are rounded top or Gaussian shaped pulses These are derived from radiation detectors such as scintillation e g sodium iodide or solid state detectors e g Ge Li They are in the form of charge pulses which are normally amplified and converted to voltages by front end pre amplifiers and amplifiers The pulses are shaped to produce rise and fall times of different values Shaping produces a well defined pulse which is relatively free from noise Usually the rising edge is fast 50 200ns for solid state and 200ns 1us for scintillation with a slow falling edge which decays away exponentially and can be of the order of microseconds or tens of microseconds in the case of scintillation detectors 2 3 How is the pulse measured When the input
25. ith the same values 1 falling within the same bin are counted then the spectrum of the counts will be ideally Gaussian If the bins vary greatly in width then the spectral shape will be distorted 2 5 What is sliding scale correction Most ADCs have a figure for differential non linearity of 1 2LSB to 2LSBs This represents a figure of 50 200 In order to minimise the differential non linearity sliding scale correction may be applied This is done by adding a small varying waveform to the signal and then subtracting its digital value from the resultant conversion Therefore the input voltage 15 varied across several bins so that with time the variation in bin width is averaged out If the variation 1s 64 bins the differential non linearity will be reduced from 50 to 50 64 or less than 1 Other errors are involved the DAC producing the varying summing voltage will also be non linear This may be reduced by increasing the resolution of the ADC and dividing down both the analogue output and the digital subtracted value In practice 1 2 DNL 15 considered good Page 7 of 27 6 Hytec Electronics Ltd 2530 UTM G 8 1 0 Sliding scale over 64 bins 6bits 0 0x3F of ADC Volts bit of ADC 2 5 2 305 176uV Thus 6bits Ox3F x 305 176uV 19 226mV In the 8 191 V range the shaker will move by 19 226mV 8 191 2 5 62 992mV The shaker injects a negative voltage as this allows a peak pulse at max voltage of 8 191V to be digi
26. on the front panel to initiate conversions Any inputs that have a pulse present in coincidence with the gate s are converted The conversions are listed to memory with formatting words to provide header number of channels converted a 48bit time stamp highest conversion value pulse pileup and channel number end of block and event count Each gate pulse is counted in order to provide the event count When individual or master gate events coincide then the event counter will only be incremented once In the case of an event occurring in List mode with ZE set and where none of the inputs makes the LLT HLT Then the event counter is incremented and a header which includes the number channels held in the list with ZE set this is always 1000 8 chans a 48bit time stamp a trailer with event count and in between 8 longwords of channel data with a zero conversion value and a channel tag for each of the 8 channels will be logged in memory In the case of an event occurring in List mode with ZE not set and where none of the inputs makes the LLT HLT Then the event counter is incremented and a header which includes the number channels held in the list with ZE not set this will be 000 0 chan a 48bit time stamp and a trailer with event count will be logged in memory When the gate is open in List mode a record is made of the number of pulses per channel pulse pileup and the largest signal that occurred during the gate is logged The four bit pulse pile
27. ponding mask bit are set when the number of events is greater than the value set in the Number of Events to Data Ready Flag register when in List Mode The front panel INTR light is taken from the IS bit in the CSR and does not indicate that interrupt has been asserted It only shows only that the conditions for an interrupt to be generated have occurred A VME interrupt will only be generated when 15 1 1 and the interrupt priority bits IPO to IP2 in the CSR are set greater than zero 3 5 1 Hist Mode Interrupt Hist Mode STOP on FULL and Interrupt Half full flags channel 1 to 8 on bits 8 to 15 Full flag channel 1 to 8 on bits 0 to 7 The unit will stop i e ARM automatically cleared when full flag set for a channel and the corresponding Interrupt Mask Flag set If Interrupt mask not set then unit will set full flag for channel and wrap around on bin count Page 9 of 27 Hytec Electronics Ltd 2530 UTM G 10 1 0 3 5 2 List Mode Interrupts Interrupts in List Mode can be generated on the Full Half Full flags or when a set number of events has occurred as set in the Number of Events to Data Ready register In List Mode the half full flag 15 bit 8 and the Full flag is bit 0 in the Fullness register To generate an interrupt on half full need to set bit 8 in the Interrupt mask register and to generate an interrupt on full need to set bit 0 in interrupt mask reg For both these need to have IT bit12 CSR se
28. quisition will also be stopped i e ARM automatically cleared to prevent the memory wrapping round on its self Page 17 of 27 Hytec Electronics Ltd 2530 UTM G 18 1 0 5 10 Interrupt Mask Number Events to Data Ready Flag Register Read Write Address Base 12 015 D14 D12 DII DIO Dos Dos Dos Do4 DOO The interrupt mask bits mask on each respective flag and enable them to generate interrupt when iDR 0 When set to Number of Events to Data Ready flag by iDR 1 then in List Mode the Data Ready flag in the CSR and the front panel output DATA will be set when the number of events is greater than the value set in the Number of Events to Data Ready Flag register 5 11 Lower Level Discriminator Value Read Write Address Base 14 25 D14 DI2 DIO Do9 Dos Dos DO2 DO DOO 0 LD8 LD7 1106 LD5 LD4 LD3 LD2 LDI The value written to this register will set the common lower level discriminator value from 0 to 0 8191V full scale Pulses rising above this level will have their peak values held and converted Pulses below this level will be ignored or recorded as zero according to the control setting LLD DAC Value Vreq 3 2764 0 25 4095 2 amp Ox3ffc DAC 12 bits first 2 bit must be zero and la
29. set J15 to J19 to positions 2 and 3 as required all address lines pulled up use jumper to pull down Address Offset Range Assignment Size 0x0000 Base 0x0000 0x0001 Manufacturer s ID 2 Bytes 0x0002 0 0002 0x0003 Device Type 2 Bytes x 0x0004 Module specific TORS 0 001 configuration registers 0 0020 Not Mapped 0x003F Reserved for future use depen Base 0x0040 Rt Module serial number 2 Bytes 0 0041 0 0042 Data in Non volatile 0 0042 0x00BF 126 Bytes NADC2530 A16 and A24 address Map Page 10 of 27 Hytec Electronics Ltd 2530 UTM G 11 1 0 4 1 1 Short Addressing A16 AM29h and 2Dh The A16 base address is determined either by PCB jumper settings 15 11 to JI9 A15 or by geographical addressing lines GAO A11 to GA4 A15 Address modifiers Configuration Registers AM29 Short A16 non privilege AM2D Short A16 supervisory 4 1 2 Standard Addressing A24 AM39h and 3Dh The A24 base address is determined either by PCB jumper settings 15 19 to 19 23 or by geographical addressing lines GAO A19 to GA4 A23 Address modifiers Configuration Registers AM39 Standard A24 non privilege AM3D Standard A24 supervisory 4 1 3 Carrier board Configuration ROM A24 AM2Fh The module provides CR CSR Support as specified in VME64x specification See appendix B for the cont
30. st 2 bits must be zero these are control bits 5 12 Upper Level Discriminator Value Read Write Address Base 16 DI5 D14 D12 DII DIO Do9 Do7 Dos Do4 Do2 DOO UDII UDIO ups UD7 ube 005 UD4 UD3 UD2 The value written to this register will set the common upper level discriminator value as 8 191V full scale Pulses above the Lower Level and below this level will be converted Pulses rising above this level will be ignored or recorded as zero according to the control setting ULD DAC Value 3 2764 2 0 5 4095 lt lt 2 amp 0x3ffe DAC 12 bits first 2 bit must be zero and last 2 bits must be zero these are control bits 5 13 Event Counter LS Read Write Address Base 18 DI5 DI4 DI2 DIO Do9 Do7 Dos Dos Do4 Do2 DOO 5 14 Event Counter MS Read Write Address Base 1A DIS D14 D12 DIO Do9 Do7 Dos 204 D02 DOO po B23 EC 1 EC20 9 ECIS ECI7 ECI 5 15 Conversion Read Address Base DI5 D14 D12 DII DIO Do9 Do7 Dos Do4 Do2 DOO ADC 166 raw value this holds last channel conversion Used for calibration were one channel calibrated at a time OR
31. t to 0 The Full flag is set in List Mode when there is insufficient room in the memory for a full sized event to be stored The acquisition will also be stopped i e ARM automatically cleared to prevent the memory wrapping round on its self When bit12 CSR set to 1 an interrupt is generated when the number of events is greater than the value set in the Number of Events to Data Ready Flag register 3 6 Timestamp The Timestamp comprises of 48bit counter running at 32MHz onboard system clock this gives approx 2443 36hours The time stamp starts running as soon as the FPGA has configured It can be zeroed by writing to a bit in the CSR or it can be zeroed from the font panel Fast Clear input when the unit is not ARMed The contents of the Timestamp counter are latched when either the Master Gate or any of the individual channel gates are asserted in List mode The counter will be latched on the first gate to go if multiple gates are asserted 4 Use of the VME data bus and Memory Access 4 1 Base Address The module uses A16 D32 D16 A16D8 EO is read only Even and Odd byte or A24 D32 D16 A24D8 EO is read only for accesses to the module Configuration Registers The base address of the configuration registers 15 determined either by the geographical addressing lines GAO to 4 or by PCB jumpers J15 to 119 To use geographical addressing lines set J15 to J19 all to 1 and 2 to use PCB jumpers to select base address
32. ter Read Write Address Base 0E DIS D14 D12 DIO Do7 Dos 204 D02 Dol DOO X X X X X x X X X MEN M2 Select which channel to calibrate when SC set in CSR This opens the channel gate and sets the MUX switch on PCB to allow voltage at the channel input to be measured to M2 selects channel 000 chan 1 to 111 chan 8 and MEN enables MUX switch The ADC will convert and update the Conversion Register as fast as it can 1 as soon as one sample read a next is started When DISC Disable compensation 0 then compensation applied When Disable Auto Fast Clear DEAC set a fast clear pulse will not be issued this is for test only 5 9 Fullness Flag Register Read Write Address Base 10 DI5 DI4 D12 DIO Do9 Do7 Dos Dos Do4 002 DOO The Half full and Full flags for each channel 1 8 In spectrum mode Full denotes sample overflow Dis D14 D12 DIO Do9 Dos Do7 Dos Do4 D02 DOO NU NU NU NU NU NU NU HF NU NU NU NU NU NU NU The Half full and Full flags in LIST mode The Full flag is set in List Mode when there is insufficient room in the memory for a full sized event to be stored 1 number of free longwords in memory lt 10 The ac
33. tised with out the shaker causing over ranging However if a peak pulse of less that approx 63mV then the shaker will take the voltage negative which will cause errors 2 6 Why use a histogram mode When a radioisotope is detected it will produce pulses of different amplitudes depending on the escape energies of the detected particles The isotope may be identified by a spectrum of energies and its mass can be calculated by the rate of emissions Therefore it is necessary to count the pulses with similar amplitudes related to energy to form a spectrum of counts frequency vs bin number energy This provides an energy spectrum in which the radiation can be identified from the energy peaks and the activity by the integrated counts divided by the time to acquire them This time must be the actual count time and should take into account the dead time of the ADC live time real time dead time Therefore the time for which the ADC cannot accept a new pulse dead time must be indicated Busy The individual gates associated with each input are used for coincidence gating When the input pulse is in coincidence with its gate it is converted and the data recorded If it is not in coincidence the pulse is rejected and a fast clear initiated to discharge the hold capacitor and reset the linear gate In this case the event counter will not be incremented 2 7 What is List mode List or Gate Mode uses the Master Gate or individual gates inputs
34. up data per channel has been put in the top 4 bits of the same word as the channel number Page 8 of 27 Hytec Electronics Ltd 2530 UTM G 9 1 0 3 Operating Modes 3 1 Self Triggering A pulse received on any input if it is within the lower and upper level discriminator settings will cause the peak value detected to be digitised 3 2 List Zero Enable A pulse received on any input if it is within the LLD and ULD settings and coincident with the Gate pulse will cause the peak value detected to be digitised If the Zero Enable bit is set in the CSR those channels which do not convert will record a zero conversion 3 3 Histogram Memory Eight memory banks accumulate a spectrum of sample frequency vs channel number conversion value for each input The spectra are each 8Kx32 bits When any channel overflows acquisition on that input is halted until the Full flag is cleared 3 4 List Memory The conversions are listed to memory with formatting words to provide header number of channels converted conversion value and channel number end of block and event count 3 5 Interrupt Settings The VME interrupt level generated the unit 15 set using 3 bits in the CSR IP2 see table below VME Interrupt 2 1 1 Priority Level None 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 The interrupt is set if a Half Full or Full flag status bit and its corres
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