FleXDS-DSP-VC33 User Manual
Contents
1. After this bit has been set 1 under program control the external interrupts are enabled onto the VC33 interrupt pins The initial condition after a power up or Flying Reset is 0 interrupts disabled The state of this pin can be probed at TP3 on the VC33 module Page2 Register Read There is no data that can be read back from the Page2 Register Page3 Register Write DO Codec Control Serial Data Out This output of this bit is connected to the Codec Control Data Input pin when the Audio module is installed Codec data must be valid on the falling edge of the codec clock D1 Codec Control Serial Clock Out This bit is connected to the Codec Control Clock input of the codec when the Audio module is installed The control clock is generated by software Data will be clocked into the codec on the falling edge writing a 0 to this bit and clocked out of the codec on the rising edge writing a 1 to this bit The initial condition after a power up or Flying Reset is 0 D2 Codec Control Sync Out This bit is connected to the Codec Control Sync input of the codec when the Audio module is installed Setting this bit high one clock before the first data bit and low at the first data bit generates the control sync The control sync input is sampled every falling edge of the codec clock The initial condition after a power up or Flying Reset is 0 Page3 Register Read DO Codec Status Serial Data In This bit originates2. flash memory No external address bits are used to decode the peripherals Page2 and Page3 Registers The consequence is that the memory or registers will be aliased within their respective page decode spaces The term alias is defined as the same locations in a memory space can be accessed by two or more different address values The altased address space is not displayed on the following maps Each page decode space is 8M words in length External memory and page decode strobes are not active during TMS320VC33 internal accesses FLEXDS DSP VC33 2M APRIL 2003 MCBL MC 0 Page Decode Address Range Description 0 0x0000 0000 to 0x001F FFFF SRAM 10ns access zero wait state 1 0x0040 0000 to 0x0007 FFFF Flash memory 0x0080 0000 to 0x0080 9FFF TMS320VC33 internal access 2 2 Ox00BF FFFF Page 2 Peripheral Register 3 Ox00FF FFFF Page 3 Peripheral Register MCBL MC 1 2 0x0080 0000 to 0x0080 9FFF TMS320VC33 internal access 3 Ox00FF FFFF Page 3 Peripheral Register Configuration Boot Interrupt and DSPR Audio I O Module Support An additional pertpheral has been implemented with a programmable generic array logic chip GAL on the VC33 FleXDS module The GAL satisfies two requirements for the VC33 module The first is to control the activity on the interrupt pins at reset so that the boot mode may be entered into the VC33 After reset the external interrupts are then enabled under software control The second is to provid
3. 3 Contact and Service Information For further information or service contact DSP Research Inc 1095 E Duane Ave Ste 203 Sunnyvale CA 94085 Tel 408 773 1042 Fax 408 736 3451 http flexds com or http dspr com References DSP Research Publications www flexds com Schematic for the FleXDS VC33 2M DSP Module Schematic for the Peripheral GAL U2 Parts List for the FleXDS VC33 2M DSP Module Layout for the FleXDS VC33 2M DSP Module Texas Instruments Publications www ti com TMS320VC33 Data Sheet SPRS087 TMS320C3x User s Guide SPRU031 Important Notice DSP Research Inc DSPR reserves the right to make changes to their products or to discontinue any product or service without notice and advises customers to obtain the latest version of the relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability DSPR assumes no liability for applications assistance or customer product design Copyright 2000 DSP Research Inc
4. FleXDS Products FleXDS Module DSP VC33 2M FLEXDS DSP VC33 2M Block Diagram RESET CLKCMD 1 0 MC MP EDGEMODE TMS320VC33 APRIL 2003 JP4 VCORE Supply lt P4 J P1 JTAG Extension VCORE Adjus d L VIO Supply LL LL x x VIO Adjust JTAG_IN JTAG_OUT TCK 1 0 XF 1 0 Serial Port P2 INTD INTC INTB INTA FPGA PAGE3 F Simple Serial Port PAGE2 gt JTAG JP3 PAGE1 Flash Memory SRAM 512K X 32 15MHZ 1 l P1 P3 Specifications e 2 Megabytes of 10ns zero wait state SRAM organized as 512K words X 32 bits e Connector for serial port e Socket for flash memory AM29LV040 or equivalent e JTAG extension port to connect multiple DSP targets together e LEDs connected to XF0 and XF1 e Additional peripherals to support VC33 boot modes and DSP Research Audio I O Module Installation The module is installed onto the FleXDS host board connectors P6 P7 and P8 with JP2 and JP4 facing the top of the board Be sure to observe all ESD procedures while handling the FleXDS host VC33 module or any IO module installed on the FleXDS host External Memory Map The following tables detail the external memory map for the FleXDS DSP VC33 2M module The address bits A21 to A23 are not wired to the SRAM nor are A19 to A23 connected to the
5. ction with the JTAG expansion connector JP4 When this jumper is installed the VC33 board i is confieured as the last DSP in a multi board JTAG loop and JP4 is not functional When the jumper is not installed JP4 becomes active so that additional boards may be daisy chained on a JTAG loop External DSP Reset active LOW FLEXDS DSP VC33 2M APRIL 2003 Connectors P4 Serial Port 1 TMoteonnecied 3 Serial port CLKX0 sooo Tempo JP1 Miscellaneous I O so ha JP3 U2 ispGAL22LV10 Programming Pins Reed 1 5 Reserved STS 7 com soo ox FLEXDS DSP VC33 2M APRIL 2003 JP4 JTAG Expansion Connector 2 s eo o OR RE How to use the JTAG Expansion Port The JTAG expansion port is to be connected to another standard JTAG target connector such as P9 on a FleXDS Host board Two standard 14 pin connectors with ribbon cable may be used The cable must connect pin 1 of the expansion port to pin 1 of the target port and so on through all 14 pins The last DSP jumper is removed for all VC33 modules except the last target if another FleXDS module CAUTION This connector is NOT KEYED in order to avoid accidental connection of a JTAG pod OBSERVE PIN 1 POLARITY when connecting multiple boards DAMAGE WILL OCCUR if the cable is connected to another board s JTAG expansion port or is incorrectly installed to a target Keep cable length as short as possible FLEXDS DSP VC33 2M APRIL 200
6. e a second serial port to control a codec located on the FleXDS Audio module This port has been implemented as a simple bit banger type of serial port where all signals are under software control Inside the GAL are two registers One register is addressed when the TMS320VC33 PAGE2 address decode output is active the other when the PAGE3 address decode output is active These two registers are referred to as the Page2 and Page3 registers The Page2 register will be chosen when any address between 0x00 800000 and OxOOBFFFFF and the external memory strobe is active The Page3 register will be chosen when any address between 0x00C00000 and OxOOFRFFFFF and the external memory strobe is active FLEXDS DSP VC33 2M APRIL 2003 Page2 and Page3 Register Description Page2 Register Write DO Codec Reset active LOW This output of this bit is connected to the Codec reset pin when the Audio module is installed While this bit is 0 the codec is held in the RESET condition When this bit is set to 1 the codec will be ready to process data The initial condition after a power up or Flying Reset is 0 codec reset active D1 Interrupt Enable active HIGH This bit controls the access to the Interrupt pins on the VC33 While this bit is 0 external interrupts are blocked and the levels on all the VC33 interrupt pins are controlled by jumpers located on JP2 The levels on the VC33 interrupt pins after reset determine the boot mode
7. from the Codec Control Data Output pin when the Audio module is installed Because data is not latched the codec clock must be stable before reading this bit Data will be valid out of the codec after the rising edge of the codec clock The Audio Module uses Interrupt 0 The Interrupt Enable bit in the Page2 Register must be set to 1 to poll or use this interrupt For a detailed explanation of codec part used on the DSPR Audio I O Module see the Crystal Semiconductor CS4218 16 bit Stereo Audio Codec data sheet www citrus com FLEXDS DSP VC33 2M APRIL 2003 Jumpers JP1 13 14 15 16 INT2_L Pull Up When this jumper is installed Interrupt 2 is pulled up through a 10K resistor to 3 3V This position must be vacant if a jumper is installed from pin 3 to 4 INT2_L Pull Down When this jumper is installed Interrupt 2 is pulled down through a 10K resistor to ground This position must be vacant if a jumper is installed from pin 1 to 2 INTO_L Pull Up When this jumper is installed Interrupt 0 is pulled up through a 10K resistor to 3 3V This position must be vacant if a jumper is installed from pin 7 to 8 INTO_L Pull Down When this jumper is installed Interrupt 0 is pulled down through a 10K resistor to ground This position must be vacant if a jumper is installed from pin 5 to 6 INTI_L Pull Up When this jumper is installed Interrupt 1 is pulled up through a 10K resistor to 3 3V This position must be vacant if a jumper is
8. installed from pin 11to 12 INTI_L Pull Down When this jumper is installed Interrupt 1 is pulled down through a 10K resistor to ground This position must be vacant if a jumper is installed from pin 9 to 10 INT3_L Pull Up When this jumper is installed Interrupt 3 is pulled up through a 10K resistor to 3 3V This position must be vacant if a jumper is installed from pin 15 to 16 INT3_L Pull Down When this jumper is installed Interrupt 3 is pulled down through a 10K resistor to ground This position must be vacant if a jumper is installed from pin 13 to 14 17 18 CLKMDO Pull down used to configure CPU clock speed See data sheet for pin explanation If not installed CLKMDO is pulled up to 3 3V through a 10K resistor 19 20 CLKMD1 Pull down used to configure CPU clock speed See data sheet for pin explanation If not installed CLKMD1 is pulled up to 3 3V through a 10K resistor SHZ Pull down used to tri state the DSP See data sheet for pin explanation If not installed SHZ is pulled up to 3 3V through a 10K resistor MCB MP Pull down used to put the DSP in either the microcomputer or microprocessor mode See data sheet for pin explanation If not installed MCB MP is pulled up to 3 3V through a 10K resistor 25 26 EDGEMODE Pull down used to set the DSP interrupt mode See data sheet for pin explanation If not installed MCB MP is pulled up to 3 3V through a 10K resistor Last DSP On JTAG Loop Select This setting is used in conjun
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