UM10484 Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
Contents
1. Vbuf Vpld Vlpf Vvco EXT CLK input 5th harmonic Vbuf O PLD Frequency filter TFF11XXX Reference error signal E REF IN TFF1003 dividers and processing VCXO or VCO A TF1004 PFD loop filter I TFF1008 Vdv DC input Vbuf 4 Vpld SUPPLY Vlpf Vvco aaa 001261 Fig 2 Block diagram of integrated Clean Up PLL TFF11XXX TFF100X and buffer amplifier 2 2 Description of individual function blocks External reference input The external reference input provides the clock for the PLL The amplifier converts this reference clock to a clipped sine wave that is recognized by the CPLD logic device Clean Up PLL The Clean Up PLL for generating the required reference signal CW for the NXP LO generator family TFF1003HN for VSAT applications in the range 12 8 GHz to13 05 GHz TFF1007HN VSAT applications at 14 75 GHz TFF1008 HN VSAT application at 14 275 GHz TFF11XXX frequency range 7 GHz to 15 2 GHz The demo board has the following additional circuits to Clean Up PLL External PLL lock detector a simple voltage window detector logic circuit detects the tuning voltage at the loop filter output A voltage between 0 4 V and 2 2 V indicates a Clean Up PLL locked status and amber LED D1 turns on Phase noise performance and tuning range can be optimized using an optional active loop filter which allows the customer to select specific components to implement either a passive or an active loop filter2. VCC_3 3 V_TFF MIN VCC 5V LP5900SD 3 3 V I foe EN R39 H 24 3 5 4 T 16V 10 kO C84 Il 120 pF E C66 R60 ll VCC_3 3 V_TFF jane 200 TFF11XXX lock indicator Y T ON LOCK A R61 E OFF OUT OF LOCK SMESTIRTISS 5609 Gs n ll JH R70 res Res Re7 3 lo 470 pF d O 2700 00 JDNP Joo 9 N o z 2 Sd iri ad E o W D D D E a ra U13 Z z z gt O gt GND TAB a4 R69 LCKDET PMBTA45 mS GND3 BUF GND1 REF 1 BUF2_P C73 C69 IN REF P RF OUTPUT TO REF OUT TERIDO BuriP pi BUF amp 10 nF IN REF N Q5pF gt AE BUF2_N Re2 Re3 GNDARER BUF1_N m 510 240 1E FA VCC REF SE L13 GND2 BUF 95PF hac 510 BLM15AG100SN1D c T C76 C80 a a a a T i dR SSN RE F 4700 pF F 100 pF S 9 8 dL A od a gt L11 oO Z L12 VCC_3 3 V_TFF aan L L n Po BLM15AG100SN1D BLM15AG100SN1D l L C77 L C78 L C79 C75 T 4700 pF T 100 pF T 100 pF T 4700 pF aaa 001264 Fig 6 TFF100X TFF11XXX schematic UM10484 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 9 of 20 NXP Semiconductors UM10484 Integrated clean up PLL TFF1xxxx and buffer amplifier RF OUTPUT TO BUF AMP Fig 7 Buffer amplifier schematic 10 dBm version TP VCC 3 3 V_BUF_AMP Y VCC 3 8 V e 4 Lco 1 s
3. Buffer amplifier The buffer amplifier is the final stage which amplifies the TFF1XXX RF microwave output signal from 4 dBm typical to 7 dBm to 13 dBm depending on the amplifier used UM10484 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 5 of 20 UM10484 NXP Semiconductors 3 Application board Integrated clean up PLL TFF1xxxx and buffer amplifier 3 1 Application circuit Fig 3 VCC 3 3 V L1 C22 680 nH 1 22nF L0 R29 R30 100 nF 4 7 kQ 2200 CON F TYPE THROUGH s B 7 tH fret buf C27 10 nF RC Q2 27 uA T Il I K BFS17 s 100 nF d aL C28 R36 R37 C29 58 pF 2 7 KQ 820 T 10 nF zi S aaa 001262 10 MHz reference input and amplifier schematic All information provided in this document is subject to legal disclaim ers NXP B V 2012 All rights reserved 6 of 20 UM10484 User manual Rev 3 10 October 2012 NXP Semiconductors U M1 0484 Integrated clean up PLL TFF1xxxx and buffer amplifier VCC 3 3V En 220 VCC 3 3 V calle es te Me
4. 2 es d R78 R76 R77 390 m 12kQ 560 0a C97 C98 C99 I a j A 1 rA M2 DNP 12 pF DNP M1 Stub1 l R74 R73 o 39 kQ 39 kQ Y Q7 i ll t BFU730F 0 5 pF Q6 l RF OUT E E BFU730F aaa 001265 UM10484 3 2 Board layout In general a good PCB layout is an essential part of an RF circuit design The demo board of the integrated clean up PLL TFF100X TFF11XXX and buffer amplifier can serve as a guideline or reference for laying out a board using this complete solution Use controlled impedance lines for all high frequency inputs and outputs Bypass Vcc with decoupling capacitors preferably located as close as possible to the device For long bias lines decoupling capacitors may be required along the line farther away from the device Proper grounding of the GND pins is also essential for good RF performance either connecting the GND pins directly to the ground plane or through vias or both Due to the nature of microwave signals care is required to implement these circuits Refer to the respective documents for layout recommendations and suggestions The material for this integrated board depends on the TFF100X TFF11 XXX and buffer amplifier which operate at microwave frequencies Substrate low loss Rogers 4003 e Substrate critical thickness 20 mils 0 508 mm Dielectric constant 3 38 Dielectric Loss Tangent 0 0025 The second substrate layer is solely for rigidity purposes Figure 8 shows a deta
5. information included herein and shall have no liability for the consequences of use of such information 6 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specificati
6. 3 10 October 2012 19 of 20 NXP Semiconductors UM10484 Integrated clean up PLL TFF1xxxx and buffer amplifier 7 Contents 1 Introduction lessen 3 2 General description esses 4 2 1 High level function review 4 2 2 Description of individual function blocks 5 3 Application board ssleese 6 3 1 Application circuit 2 4 6 3 2 Board layout anaua auauua 10 3 3 Bill of materials nannan annaa 11 3 4 Evaluation equipment 15 3 5 Connections and setup 15 4 Demo board typical measurement result 16 4 1 Demo board typical test result 16 5 Abbreviations 00 cece eee eee 18 6 Legal information Less 19 6 1 Definitions 00 0200 00 19 6 2 Disclaimers 0 2000 eee eee 19 6 3 Trademarks ee ieie tuea cece eee 19 7 Contents e senna es oe eens 20 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information O NXP B V 2012 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 10 October 2012 Document identifier UM10484
7. based on the BFU7XX series of microwave transistors Circuit schematics a PCB layout design and test results are provided The demo board converts a reference signal typically 10 MHz to a frequency of 30 MHz to 50 MHz via a Xilinx CPLD and logic gate based Voltage Controlled eXternal Oscillator VCXO The fifth harmonic is filtered via a 7th order Cauer filter and used as the reference for the TFF11XXX TFF100X Microwave transistors BFU7XX amplify the output of the TFF11XXX TF100X to a level of 7 dBm 10 dBm or 13 dBm depending on the version of buffer used The NXP TFF11XXX TFF1003 TFF1007 TFF1008 are a family of low phase noise high frequency accurate microwave band Local Oscillator LO generators implemented in Silicon Germanium SiGe high Ft process These devices have a combined frequency range of 7 GHz to 15 GHz where TFF1003 TFF1007 TFF1008 cover the VSAT Ku band 12 GHz to 14 GHz e TFF11XXX series cover the remaining frequency band The LO generators require a reference input signal that minimizes the added phase noise to the LO generated signal The Clean Up PLL generates an ultra low phase noise reference signal based on a VCXO In practical applications customers often use the LO generator to drive a mixer which could be a passive or active type A high frequency buffer amplifier is required for applications requiring a higher LO drive level The demo board has a wideband buffer amplifier designed to deliver an output
8. 15 GHz 7 dBm BOM1 BOM2 BOM3 BOM4 10 dBm BOM5 BOM6 BOM7 BOM8 13 dBm BOM9 BOM10 BOM11 BOM12 UM10484 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 14 of 20 NXP Semiconductors U M1 0484 UM10484 Integrated clean up PLL TFF1xxxx and buffer amplifier 3 4 Evaluation equipment The following equipment is required for evaluation tests Low noise DC power supply output to at least 500 mA at 5 V Precision ammeter to measure the supply current RF power meter capable of measuring up to 20 GHz or above Spectrum analyzer or signal analyzer with phase noise measurement feature capable of measuring up to 20 GHz or above 10 MHz reference input for an input power level range of 15 dBm to 5 dBm with the following phase noise performance for divider N 64 135 dBc Hz at 1 kHz offset 140 dBc Hz at 10 kHz offset 150 dBc Hz at 100 kHz offset RF cables and connectors with minimum loss at 18 GHz or above 3 5 Connections and setup The demo board has a few variants so it is important to identify the frequency and RF power level of the demo board to be tested Typically the demo board is identified by suitable markings when it is fully assembled and tested A step by step guide for operating and testing the demo board is as follows 1 a RO m Connect the DC power supply to the Vcc and GND terminal a
9. 5 PSF S01 005 GigaLane GIGALANE 1 L1 LQW21HNR68J00L Murata 680 nH 1 L2 MLF1608A2R7K TDK 2 7 uH 1 L3 B82496C3221J EPCOS 220 nH 1 L4 LQW18AN39NJ00D Murata 39 nH 1 L5 LQW18ANR10J00D Murata 100 nH 1 L6 LQW18AN18NJO0D Murata 18 nH 1 L7 LQW18AN33NJ00D Murata 33 nH 2 L8 L9 LQW18AN6N8D00D Murata 6 8 nH 1 L10 LQW18AN4N7D00D Murata 4 7 nH 3 L11 L12 L13 BLM15AG100SN1D Murata BLM15AG100SN1D 2 M1 M2 PCB Copper B stub1 2 Q2 Q3 BFS17 NXP Semiconductors BFS17 1 Q4 PMBTA45 NXP Semiconductors PMBTA45 1 Q5 PBHV9050T NXP Semiconductors PBHV9050T 2 Q6 Q7 BFU730F NXP Semiconductors BFU730F 2 R1 R72 ERJ 3EKF22R0V Panasonic ECG 220 3 R2 R7 R23 ERJ 3EKF10ROV Panasonic ECG 100 11 R3 R4 R5 Re R9 ERJ 3EKF1002V Panasonic ECG 10 ko R10 R13 R16 R38 R39 R69 1 R15 ERJ 3EKF2702V Panasonic ECG 27 kQ 13 R17 R24 R27 lt tbd gt Panasonic ECG DNP R31 R33 R34 R35 R40 R41 R42 R50 R51 R68 2 R18 R28 ERJ 3EKF1212V Panasonic ECG 12 1 KQ 1 R19 ERJ 3EKF68ROV Panasonic ECG 68 Q UM10484 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 13 of 20 NXP Semiconductors UM10484 Integrated clean up PLL TFF1xxxx and buffer amplifier Table 1 Example BOM for a VSAT BUC with a 13 05 GHz LO continued Quantity Reference Type Manufacturer Value 1 R21 ERJ 3EKF9092V Panasonic ECG 90 9 kQ 3 R22 R30 R46 ERJ 2RKF2200X Panason
10. 5C1H221JA01D Murata 220 pF C50 C53 C60 C61 C62 2 C46 C47 GRM1885C1H151JA01D Murata 150 pF 2 C51 C52 GRM1885C1H120JA01D Murata 12 pF 1 C54 GRM1885C1H6R8DZ01D Murata 6 8 pF 1 C56 GRM1885C1H5R6DZ01D Murata 5 6 pF 2 C57 C58 GRM1885C1H180JA01D Murata 18 pF 1 C59 GRM1885C1H360JA01D Murata 36 pF 2 C63 C65 GRM1885C1H820JA01D Murata 82 pF 1 C66 GRM155R71C183KA01D Murata 18 nF 1 C67 08051 A330JAT2A AVX 33 pF 4 C69 C71 C95 GRM1555C1HR50CZ01 Murata 0 5 pF C96 2 C73 C74 GRM155R71C103KA01D Murata 10 nF 3 C75 C76 C77 GRM155R71E472KA01 Murata 4700 pF UM10484 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 12 of 20 NXP Semiconductors UM10484 Integrated clean up PLL TFF1xxxx and buffer amplifier Table 1 Example BOM for a VSAT BUC with a 13 05 GHz LO continued Quantity Reference Type Manufacturer Value 3 C78 C79 C80 GRM1555C1H101JZ01 Murata 100 pF 1 C83 GRM155R71H471KA01D Murata 470 pF 1 C84 GRM1555C1H121JA01D Murata 120 pF 5 C85 C86 C87 C3216X7R1C106M TDK 10 pF 16 V C88 C93 1 C98 GRM1555C1H120JZ01D Murata 12 pF 2 D1 D5 SML 211YTT86 ROHM Semiconductor SML 211YTT86 2 D3 D4 BB202 NXP Semiconductors BB202 1 D9 BZX84 A5V1 NXP Semiconductors BZX84 B5V 1 J1 90120 0762 Molex CON 2PIN 1 J2 90120 0766 Molex 6PIN 1 J3 531 40047 4 Amphenol CON F TYPE THROU GH 3 J4 J6 J7 903 415J 51P Amphenol SMB V 1 J
11. C FILTER aaa 001263 Fig 4 Clean up PLL schematic part 1 UM10484 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 7 of 20 NXP Semiconductors U M1 0484 Integrated clean up PLL TFF1xxxx and buffer amplifier VCC_3 3V VCC_5V L CON 2PIN 1 8V D9 VCC 1 8V 4 t 1 BZX84 B5V C8 35V VCC_3 3 V_VCXO 1 6 LP5900SD 3 3 V 27 3 5 4 POWER SUPPLY AR N E 7 VCC_3 3 V gt t R18 12 1 kQ UW 2 2 V i R21 i C18 90 9 kQ 1nF D1 T i Vw SML 211YTT86 ON LOCK OFF OUT OF LOCK R26 V TUNE gt C 1 MQ R22 R 220 Q LW 0 4 V 124 KQ Q5 T PBHV9050T R32 C26 22 1 T rad 74AUP1G86GW m R35 TU i DNE LOCK DETECTOR aaa 001371 Fig 5 Clean up PLL schematic part 2 UM10484 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 8 of 20 NXP Semiconductors UM10484 Integrated clean up PLL TFF1xxxx and buffer amplifier
12. CPLD PLL R5 R6 R7 o S e X x VCC 3 3 V s 10 ko ee u I Ig Q Q Ik 25 32 31 30 29 28 26 27 J2 VAUX 1 la 20 c 100 nF T 2 1 vot 21 PASSIVE L F 3 102 A 4 1 03 l I 3 XC2C32A 23 TP UP TP PASSIVE VT TP V TUNE Y 5 t ts 22 TP REF DIV Y 6 7 1 06 019 RIS RIS RAS 1 p I 6 pin PN m s Les ik C14 f 1 07 100 nF veo gt T 22nF T DNP 100 pF i 1 08 i R50 e ref buf 3 680 i Trvconv 7 1 J i R7 C2 R41 C 3 ll l VCC 3 3 V c34 PNP DNP c23 DNP JTAG 400 nF 100 Ii IH t E ee ee ee ee ee ee ee et E DNP lug DNP pNP VCC 3 3V VCXO l C25 ute v T 10008 4 5 g R33 R34 OPA376 ros 1_14 DNP e DNP C30 R40 I pNP DNP 4 M c92 Rn ACTIVELF Tp ACTIVE VT V TUNE ivco 100 pF 1000 R72 n c Y 220 GND V rum 5 Hee VCC 3 3 V VCXO VTUNE x1 x2 m I C40 um Y cso 4 10 nF 1nF 220 pF 1I 7atvciaxoacw 220 pF Ba s C43 L C44 Locas 10 nF T inF T220pF R48 1MQ I I 47kQ R46 V TUNE 220 kQ C46 x2 AT R49 ll 1 H I 150 pF 1 C51 40 78125 a 150 pF A D4 47kQ C53 Hs E Ter MHz T C52 BB202 T 220pF P 55 l 112 pF I L REF OUT BB202 C56 C57 C58 C59 c Il Il 1H H R47 C37 C101 5 6 pF 18 pF 18 pF 36 pF Cet I Il n ll 820 220pF 1nF L4 L5 L6 L7 c L 220pF jg 39 nH 100 nH 18 nH 33 nH ane R51 R42 DNP DNP L8 L ces L10 l cea L9 L i d 6 8nH T 82pF 47nH T 100 pF 6 8nH T 82 pF REFERENCE OUTPUT VCXO AND HARMONI
13. E k ee 120 je a TET 140 pe NEL l H a d 6134108 sPROFF i oaan mem 180 1 00 kHz 10 00 kHz 100 00 kHz 1 00 MHz 5 00 MHz Frequency Offset Measurement Aborted Date 4 MAY 2011 14 17 58 aaa 001268 Fig 10 Reference input phase noise of a Vectron 10 MHz OCXO module 4 1 Demo board typical test result fret input frequency 10 MHZ Pret in input power level 0 dBm UM10484 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 16 of 20 NXP Semiconductors U M1 0484 Integrated clean up PLL TFF1xxxx and buffer amplifier Table 3 Typical results measured on the demo board Test board example 13 05 GHz for VSAT BUC room temperature with 5 V power supply ID Parameter Conditions Min Typ Max Unit current consumption 195 2 mA 2 phase noise out see 1 kHz offset 96 dBc Hz Figure 11 10 kHz offset 102 dBc Hz 100 kHz offset 101 dBc Hz 1 MHz offset 108 dBc Hz spurious reference 70 dBc output power 13 05 GHz 7 dBm version 7 1 dBm 10 dBm version 9 8 dBm 13 dBm version 13 2 dBm LAN PHASE NOISE KS e e sexWoseWij Signal Freq 13 049987 GHz Evaluation from 1 kHz to 1MHz i kHz 96 20 dBc Hz Signal Level 9 79 dBm Residual PM 0 583 10 kHz 102 44 dBc Hz Signal Freq 2 27 Hz Residual FM 4 383 kHz 100 kHz 101 41 dBc Hz Signal Level A 0 28 dBm RMS Jitt
14. UM10484 Integrated clean up PLL TFF1xxxx and buffer amplifier Rev 3 10 October 2012 User manual Document information Info Content Keywords External reference clean up PLL VCXO LO generator buffer amplifier RF output power level phase noise Abstract This document describes an integrated demonstration demo board for Clean Up PLL CUP local oscillator generator TFF11XXX TFF100X The demo board includes an output buffer amplifier based on BFU7XX series microwave transistors NXP Semiconductors U M1 0484 Integrated clean up PLL TFF1xxxx and buffer amplifier Revision history Rev Date Description v 3 20121010 Correct mistake in fig 4 and components in table 1 v 2 20120202 Security status changed from company internal to company public v 1 20111221 Initial version Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10484 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 2 of 20 NXP Semiconductors U M1 0484 Integrated clean up PLL TFF1xxxx and buffer amplifier 1 Introduction UM10484 This user manual describes an integrated demonstration demo board for Clean Up PLL CUP local oscillator generator TFF11XXX TFF100X The demo board includes an output buffer amplifier
15. ber 2012 11 of 20 NXP Semiconductors UM10484 Integrated clean up PLL TFF1xxxx and buffer amplifier Buffer amplifier components are also both frequency and output power level dependent If the design requires an output power level of 7 dBm to 10 dBm at a frequency below 13 GHz the output level is achieved by a cascaded BFU730 solution If 10 dBm or more is required a balanced amplifier solution is required to combine the two cascaded buffer amplifiers to achieve a higher output RF power to drive the mixer Please contact NXP Semiconductors for reference design and evaluation board An example of a BOM for a VSAT BUC Block Up Converter application with a 13 05 GHz LO is given in Table 1 For other frequency applications please contact NXP Semiconductors for technical assistance Table 1 Example BOM for a VSAT BUC with a 13 05 GHz LO Quantity Reference Type Manufacturer Value 12 C1 C4 C6 C7 GRM188R71E104KA01D Murata 100 nF C13 C15 C16 C19 C20 C24 C25 C27 2 C2 C8 TAJE476K035RNJ AVX 47 uF 35 V 2 C3 C9 B45197A3107K509 EPCOS 100 uF 16 V 1 C11 GRM1885C1H222JA01D Murata 2 2 nF 8 C12 C21 C23 ibd Murata DNP C30 C31 C97 C99 C100 3 C14 C64 C92 GRM1885C1H101JA01D Murata 100 pF 6 C18 C26 C40 GRM1885C1H102JA01D Murata 1nF C44 C91 C101 1 C22 GRM188R71C223KA01D Murata 22 nF 1 C28 GRM1885C1H560JA01D Murata 56 pF 6 C29 C32 C39 GRM188R71H103KA01D Murata 10 nF C43 C89 C90 8 C37 C41 C45 GRM188
16. er 0 1242 ps 1MHz 107 72 dBc Hz PH Noise RF Atten 10 dB Top 80 dBc Hz TM AU 2 HI TOE A uu Frequency Ofset Meas urement Aborted Date 12 MAY 2011 09 28 16 aaa 001269 Fig 11 Phase noise and power output at 13 05 GHz 10 dBm version All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Rev 3 10 October 2012 17 of 20 NXP Semiconductors UM10484 5 Abbreviations Integrated clean up PLL TFF1xxxx and buffer amplifier UM10484 Table 4 Abbreviations Acronym Description BOM Bill Of Materials BUC Block Up Converter CPLD Complex Programmable Logic Device CW Continuous Wave PLL Phase Locked Loop OCXO Oven Controlled crystal Oscillator PCB Printed Circuit Board VCXO Voltage Controlled crystal Oscillator VSAT Very Small Aperture Terminal All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 18 of 20 NXP Semiconductors UM10484 Integrated clean up PLL TFF1xxxx and buffer amplifier 6 Legal information 6 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of
17. hts reserved User manual Rev 3 10 October 2012 15 of 20 NXP Semiconductors 4 Demo board typical measurement result To demonstrate the performance of the integrated board a representative board at 13 05 GHz for Ku band BUC is demonstrated in this document The following test result only refers to the final output performance of the demo board For detailed test results of each individual building block refer to the respective user manual application note or data sheet For accurate measurement use a Suitable 10 MHz reference source in accordance with the requirements previously mentioned In the following test result a Vectron OCXO module is used part number 718Y 4153 Its phase noise plot is shown in Figure 10 UM10484 Integrated clean up PLL TFF1xxxx and buffer amplifier R amp S FSUP 26 Signal Source Analyzer LOCKED Phase Detector 720 dB NE PHN 1 0 k 5 0 M 84 0 dBc Residual PM 5 116 m Residual FM 253 633 Hz ENS Jitter 1 4211 ps Signal Frequency 9 999985 MHz Signal Level 4 03 dBm PLL Mode E nternal Ref Tuned Phase Noise dBc Hz RF Atten 5 dB Top 90 dBc Hz Harmonic 1 Internal Phase Det i 03 00011 i 604 1340101 Spur Power dBc Loopdw 30 Hz ME MCI EA 100 M 100 1 dO LA t i jB LLL M0 ES i totter TE WEBSITE 2CLRWR i DEBEBMBEN
18. ic ECG 220 Q 4 R25 R29 R48 ERJ 3EKF4701V Panasonic ECG 4 7kQ R49 2 R26 R43 ERJ 3EKF1004V Panasonic ECG 1 MQ 1 R32 ERJ 3EKF2201V Panasonic ECG 2 2 kQ 2 R36 R58 ERJ 3EKF2701V Panasonic ECG 2 7 KQ 2 R37 R47 ERJ 3EKF82ROV Panasonic ECG 820 2 R44 R45 ERJ 3GEYOROOV Panasonic ECG 00 1 R53 ERJ 3EKF3301 V Panasonic ECG 3 3 KQ 1 R54 ERJ 3EKF6800V Panasonic ECG 680 Q 1 R59 ERJ 3EKF56ROV Panasonic ECG 560 2 R60 R70 ERJ 3EKF2700V Panasonic ECG 2709 1 R71 ERJ 3EKF1000V Panasonic ECG 100 Q 1 R61 ERJ 2GEJ561X Panasonic ECG 560 Q 2 R62 R64 ERJ 2GEJ510X Panasonic ECG 510 1 R63 ERJ 2GEJ240X Panasonic ECG 24 Q 3 R66 R67 R77 CRCW04020000Z0ED Vishay Dale 00 2 R73 R74 ERJ 2GEJ393X Panasonic ECG 39 kQ 1 R75 ERJ 2GEJ390X Panasonic ECG 39 0 1 R76 ERJ 2GEJ390X Panasonic ECG 560 1 R78 ERJ 3EKF123X Panasonic ECG 12 kQ 1 U1 LP3961EMP 3 3 National Semiconductors LP3961EMP 3 3 1 U2 XC2C32A 6QFG32C Xilinx XC2C32A 1 U3 LP3961EMP 1 8 National Semiconductors LP3961EMP 1 8 2 U4 U7 LMV7239M5 National Semiconductors LMV7239 1 U9 74LVC1GX04GW NXP Semiconductors 74LVC1GX04GW 1 U13 TFF1003 NXP Semiconductors TFF1003 2 U14 U15 LP5900SD 3 3V National Semiconductors LP5900SD 3 3V 1 U16 OPA376AIDBVT Texas Instruments OPA376 1 U17 74AUP1G86GW NXP Semiconductors 74AUP1G86GW 1 X2 lt tbd gt Tai Saw 40 78125 MHz Table 2 Example BOM matrix for different power and frequency applications Power Frequency examples 13 05 GHz 7 GHz 11 25 GHz
19. iled view of the layer stack up 0 5 oz copper on all layers 20 mils rogers4003 prepreg 20 mils rogers4003 4 layer stackup aaa 001266 Fig 8 PCB stack up of integrated clean up PLL TFF11XXX TFF100X and buffer amplifier All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 10 of 20 NXP Semiconductors U M1 0484 UM10484 Integrated clean up PLL TFF1xxxx and buffer amplifier UNH REF DUT MAP SEWICOKDUCTORS CUP TFF AWP EWB REVE Q502 COPPER DN ALL LAYER 2INIL RIGER J EE 20MILS RDGERS4 D LAYER STACKLP aaa 001 267 Fig 9 Board layout of integrated clean up PLL TFF11XXX TFF100X buffer amplifier 10 dBm version 3 3 Bill of materials The Bill Of Materials BOM is determined by the required generated frequency Because part of the PLL is a CPLD based solution it is possible to change the divider ratio N and R by software programming JTAG PLL filter flexible layout options allow different parts to be populated to make either a passive or an active loop filter A different crystal frequency may be required if the selected frequency is outside the pull range limits typically hundreds of ppm of the VCXO All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 Octo
20. ons and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification UM10484 All information provided in this document is subject to legal disclaimers Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the cu
21. power level of 7 dBm to 13 dBm All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 3 of 20 NXP Semiconductors U M1 0484 Integrated clean up PLL TFF1xxxx and buffer amplifier o c LJ o o o o o aaa 001260 Fig 1 PCB of integrated Clean Up PLL TFF11XXX TFF100X and buffer amplifier 2 General description UM10484 2 1 High level function review The demo board accommodates additional customer functional requirements with the following features Input typically a system may see a reference frequency of 10 MHz which can be internal or external however a different reference frequency can be used This demo board has a 10 MHz external reference input of 75 Q with F type connector for an input power level range of 15 dBm to 5 dBm Output the demo board can provide an output power of 7 dBm 10 dBm or 13 dBm to an output stage such as a mixer The on board buffer amplifier can be used avoiding the need to design a separate circuit saving engineering costs and time to market A high level block diagram is shown in Figure 2 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 3 10 October 2012 4 of 20 NXP Semiconductors U M1 0484 Integrated clean up PLL TFF1xxxx and buffer amplifier
22. se or performance of this product remains with customer In no event shall NXP Semiconductors its affiliates or their suppliers be liable to customer for any special indirect consequential punitive or incidental damages including without limitation damages for loss of business business interruption loss of use loss of data or information and the like arising out the use of or inability to use the product whether or not based on tort including negligence strict liability breach of contract breach of warranty or any other theory even if advised of the possibility of such damages Notwithstanding any damages that customer might incur for any reason whatsoever including without limitation all damages referenced above and all direct or general damages the entire liability of NXP Semiconductors its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars US 5 00 The foregoing limitations exclusions and disclaimers shall apply to the maximum extent permitted by applicable law even if any remedy fails of its essential purpose 6 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners NXP B V 2012 AII rights reserved User manual Rev
23. stomer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only NXP Semiconductors its affiliates and their suppliers expressly disclaim all warranties whether express implied or statutory including but not limited to the implied warranties of non infringement merchantability and fitness for a particular purpose The entire risk as to the quality or arising out of the u
24. t J1 which is a 2 pin terminal connector that can be clipped using a clip jacket Set the power supply to 5 V and current limiting to 400 mA Connect the RF output connector J5 to spectrum analyzer or power meter Turn on the power supply the total current drawn must not exceed 300 mA LED D3 illuminates first indicating that the TFF100X or TFF11XXX is in locked state Locked state is indicated without a 10 MHz reference input due to the wide range of the TFF s reference input frequency It is assumed that the free running VCXO output is at the correct frequency and at first lock If the divider ratio is 64 it locks to the frequency of 64 x ftee running vcxo but the Clean Up PLL is not locked until D1 illuminates Apply a 10 MHz reference input using a very low phase noise source such as the OCXO module with F type input connectors LED D1 illuminates indicating the Clean Up PLL is locked and can be considered as a secondary lock ensuring the whole system is locked onto the 10 MHz reference input Test the phase noise and power of the Clean Up PLL which is the reference input of TFF100X TFF11XXX at input J4 Test the tuning voltage of the Clean Up PLL at test point VTUNE PASSIVE if the loop filter is a passive type Test overall phase noise and power at output J5 with the spectrum analyzer and power meter All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rig
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