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Method for a correlating virtual memory systems by redirecting

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1. 39950 1S3A07 HLIA 3994 NIA t0 4 153135 23994 4IGOWNN 1 21 4305 39vd 3131 0 N JU ASOLSIH 29950 ele ble CS318V1 9 19 01 dVAS 01 30vVd 1534 123135 005 53994 31 31 NV 0313190 XDJ AMOLSTH 3995 15301 HLIM 3994 NI 4 9913 30950 13 34 31vddn 1591 3ONIS O4NI 39vsn HLIM 318V1 9 199 31vaan 31891 9 19 30 31vad LX3N 304 9913 100 3WIL 13 34 90 01 Sheet 9 of 10 5 063 499 Nov 5 1991 U S Patent e 0 6 Nant JY alt O14 OL 89 3915 WOSs 43151934 SOLVLS 35401 34 0353201 Advaa 19 1511 NI 53994 133201 ANLAVSOdWIL TS 20 Nn qvi 131530934 4524 v9E UNI 4934 34 OL 29074 33DNW 855 3993 31V I IVA 01 3NI1n03 17093 39vgd JSN 3994 5 304 9913 30941 ASIA 89312 5 LAMDW3W 30 39Vd N 3113A33AD A313 1dW09 53994 433201 dW3i 30 1517 DL 049 39vd 5201 SJA CLN3I IS 33 39vd SI ON 266 ON i TIVO O T LON 3113 AMIN 0935 DL N3LLIAM 38 49078 SIHLI 3994 INI 3 ASIA 043 0938 38 01 129078 151 14915 5 Dl HOLIAS 1192 W31SAS 09
2. 45 e y 4647425 i N4 Z NDT X 4 X Ca Qus NS7 0120 288 3900 0130 304 443F 0140 320 0602 0150 336 7500 0160 352 0000 0170 368 0000 0180 384 0000 0190 400 0000 01A0 416 0000 01B0 432 0000 01C0 448 0000 0100 464 0000 01 0 480 0000 01 0 496 0000 This is sector It is absolute Tags 0000 0000 000 0000 0010 016 0000 0020 032 0000 0030 048 0000 0040 064 0000 0050 080 0000 0060 096 0000 0070 112 0000 0080 128 0000 0090 144 0000 00A0 160 0000 0080 176 0000 00 0 192 0000 0000 208 0000 00E0 224 0000 00F0 240 0000 0100 256 0000 0110 272 0000 0120 288 0000 0130 304 0000 0140 320 0000 0150 336 0000 0160 352 0000 0170 368 0000 0180 384 0000 0190 400 0000 01A0 416 0000 01B0 432 0000 01C0 448 0000 01D0 464 0000 01 0 480 0000 01 0 496 9000 This is sector It is absolute Tags 0000 0000 000 0000 0010 016 0000 0020 032 0000 35 7F43 2 00 570 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 secto 0002 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000 secto 0002 0000 0000 0000 402F 4A48 FF42 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 13 r 37 0300 0000 0000 0000 0000 0000
3. aldana 211918 S3HIU JNOZ 3994 1 541891 NOILVISNVAL 3909 WW dVAS 3903 Vn LSITA S31qVl A XOLSIH aldana 911945 dOLW3W 3 1991 35 9 23 7 32915 AdNs qg 434404 ANNOS dU1NW3W Sheet 3 of 10 5 063 499 Nov 5 1991 U S Patent 99 0 3 GL HOLIAS 3344103 2915 SUSIAe3dhS 135 v9 3344104 2915 835 13 lec 31891 123 1d32X3 3N 01 INIDd 96 31891 3D133A NUILd32X3 MJN OL S30123 H3i1vd 75 WIW 1043 NI 31491 30123 NOId39X3 AJN 319352 25 STIVI 4941 3 12381134 05 37114 ASUW3W N3d 8 09 i LH 0 S3 8V1 1994 319342 1933 H NW MDH TIYLSNI 8e SSVdAH NDILVOD1 Q 3XI J 92 01 WY890dd AdD9 81045532305 193011 SJA amp 340 338 Q3 TIVISNI JM ASOW3H WALYIA 31920119 02 8l C13 TIVISNI AQV3a r 1v WVealOtlald UN S34 91 53 TIVLISNI SSVdAH CLN3WNDSITLAN3 43404 ON 01 9 1004 33 vv 1008 35 Welv 934 cb 5318491 3094 MJN JSN 01 AWWd 91440934 0v S3NI1RnUM 3D133A 40433 SNA 13S Be SALVLS 9 199 075 OL S3NDZ 911915 9 SAS 135
4. 28 REAL enor M BEGIN WARM RE BODT as N WARM 46 i CREATE ages 229 se POINT VBR TO NEW 22 VECTOR TABLE ALLOCATION SUCCESSFUL 58 USE STACK POINTER DU RM saka 60 SET SUPE VISOR STACK POINTE 2222 2 eee v 24 BYPASS 275 52 SeGw ICON USER sone EU RETURN 5 063 499 Sheet 1 of 10 zT 90443 sna Nant aa 82 11093 3994 91840 90143 31915 OL 32915 NV 543151935 3401534 THM 3NILROS 01 1133 OL 32915 5 9403 5449 53119 OT eJunsijJ 1 oUnsij 19 N IIRn23X3 3Wns3g 2991 043 AOSS3008d 30 31915 3401534 5 1991 U S Patent 171193 3994 42 19 3191 54315193 3501535 ANT LADS 4985 3994 31023X3 19 01 WNIOISD OL AJVE 42915 43 95 AdD3 4391 NO 505532059 40 31915 IN33303 JAYS 53999 q31dW3llV 123130 AAING NOLLVaOLS 3a LAW 4 314100 0 2 6 Sheet 2 of 10 5 063 499 Nov 5 1991 U S Patent 211915 0 W31SAS ONILV33dD qI t WALSAS 9 1 943 0 JNUZ 119211449 JNUZ NIILVOI IddVv 3 04 23915 JNUZ AOVLS AASA
5. 0000 S Ne ORIS EIN SII Seine Sg 0000 0000 0000 EE 0000 0000 0 00 0 00 c 19F9 Sel 59FD 53 BA10 tus 5950 us 990 5900 CAO1 5905 5909 Sa 590D xa 0A00 0A00 25 1900 S020 1900 0000 fud ae bois ERU 0000 0000 C 0000 HP MEET M tier abe 0000 HP EE 0000 0000 S apa ede ee a RU 0000 APT sector 4 0000 shana E i 0000 0000 E 0000 d ea cae hiya ga sunak 0000 Rite 0000 0000 0000 EE RUM 380C TD E E 8 8 044 i ey aes 002F I lt 88 0011 lt 00 0 Su Q 0230 5 2 FFBO 00E0 224 380C 00F0 240 1700 0100 256 004A 0110 272 6768 0120 288 6978 0130 304 001D 0140 320 6174 0150 336 0000 0160 352 0000 0170 368 0000 0180 384 0000 0190 400 0000 01A0 416 FFOO 01B0 432 0000 01C0 448 0000 01D0 464 0000 01E0 480 0000 01F0 496 0000 This is sector It is absolute Tags 0000 0000 000 0000 0010 016 0000 0020 032 0000 0030 048 2762 0040 064 6F00 0050 080 3ES8 0060 096 0100 0070 112 40ED 0080 128 B803 0090 144 0061 00A0 160 8 00B0 176 004 00C0 192 BC43 0000 208 00 00 0 224 4 5 00 0 240 1842 0100 256 4 52 0110 272 0430 0120 288 4 00
6. 5 063 499 17 managing such calls it is possible to ensure that no page faults will be generated from the I O request during the critical I O period The solution to this problem used in a preferred em bodiment of the present invention amounts to keeping a list of the pending I O operations and the locations to which those I O operations have been directed Those locations are temporarily marked with a Don t Swap flag and so can be regarded as temporarily locked in physical memory or RAM When the I O Operation has been completed the Don t Swap flag is removed for those temporarily locked locations and they are again free to be swapped if appropriate In rare instances it is possible that an I O Operation will request a single transfer which is larger than the number of available pages of physical memory For example a Macintosh computer having only one mega byte of RAM available for such an I O call may receive a request for a five megabyte transfer There is not enough memory available to handle the operation in one step In such event the process of the present inven tion can break the large read request into a number of smaller read operations each of which can be accom modated by the amount of available memory Thus for the example of a request for a five megabyte read the present invention can readjust the I O call into five one megabyte reads Following the last small read the call is readjusted back to
7. NUUS 135 38 01 03123dX3 10N 39 IN301S38 100 404049 4317093 19 1094 0317093 eec ON 9914 JIGUW 39Vd 49312 SIG 4043 39941 0939 ete oez 239981 03590950 asd 17094 39vd SIHI J YWI ASIQ Me N3HM LINYA 3994 30 4 19 1 9913 135 du mne SJA V 9 11935505 ASIC OL 39VWI JAYS 922 AQV33 1v SJA 8 amp 141 0 LINYA 022 S34 338 30vd 39vd 01 _ SVH 304 20543 3411103 NOILIVMDIS33 11093 902 gt na Vad 19 NUII0n23X3 3WnS3s 812 01 11193 3994 DIJO 30 5534009 Nan138 13 30333 504 40 35092 553 00 3NIW3313 80123 LdAAABINI 130v4 39vd OL 0154 912 ore SS3addv voz 31915 OL S331SID33 18 153 SED SALYLS AWWd NV dwar 543151934 JAYS 119907 IV S3INIDd 2915 IN332nO 202 3330330 LdASA3BLNI MJN J83H 2391 40 402 JAYS ONILI3S AWWd 0333 15413 1703 15513 HSINI 3 SH3ISIO3M4 33U1S32 002 sng vie Sheet 8 of 10 5 063 499 Nov 5 1991 U S Patent 53994 3I 4100WNN NV 3I JIGONW X04 39950 153801 HLIM 39Vd ANIJ 9973 39951 13534 31891 3094 JU 52094 ONIOV 1593 319040 531891 ONIOV 30 31904 1X3N 04 997134 34IL 1353 AgU1SIH 9 19 sv 30950 1103 JAVH 43123135 3994 2994 Gd JIQDW 123135 9 SIA 39Vd 031 4IGQWNN NV G3131G0W 304
8. PLE ASIA WOX 0935 38 01 0 X30 18 LX3N 3NIWVX3 4449 94941 ves 9150 OL dwn SAA PvE Sheet 10 of 10 5 063 499 Nov 5 1991 U S Patent elp 0934 303933 AVIS Olp SJA Woad 33181938 SNLYLS 3901534 02 q31SnvHx3 SSVd 3ND n sa 1 1118 4I Ee SV 3191 JWYS 01 1S03 90 9190 OL 25074 33L3AVelVd 32401534 ayay 5 ON 52018 330W 5 30 4 33201 1 JU 1811 de 40 53994 2 0 INn 9iv titr 393 05 1319411 W34 OL lX3N 40 3715 320434 03 1 1504 N ASIA WOJJ 9934 80 38 01 2019 1X3N 01 09 4934 LX3N X04 AGv34 38 39vd dVW3s 20 00 3994 LVHL 4 5 53994 433201 AllavaoOdWw31 40 1517 NI 1591 1 3 1 123135 865 96 2994 31901 9 OL JNILNDA 11193 3994 JSN 3993 5 903 9913 39VWI 510 39319 v6E 30 39 3114 4 A 1313 ldWU2 ON 39Vd 4332001 dW3l 30 1811 42 409 06E S3A CIN3OIS33 ON 885 985 DL N3llI 8A 38 VIA X90 1H SIHI 3994 ASIA WUSj 4939 38 OL N IIVWSUJNI 30 2018 1 3 19 1391 934 031530035 91840 40 ANJ 01 0934 90748 15971 40 WD34 0934 YSHLONY 135 286 dh 01934 3715 0320439 303
9. Written by Jonathan F Gar sber BE nhc 01D0 464 3800 01E0 480 0066 01F0 496 9067 This is sector It is absolute Tags 0000 0000 000 0000 0010 016 0000 0020 032 0000 0030 048 0000 0040 064 0000 0050 080 0000 0060 096 0000 0070 112 0000 0080 128 0808 0090 144 0828 00A0 160 0000 00B0 176 0000 00C0 192 0000 00D0 208 0000 00E0 224 0000 00F0 240 0000 0100 256 0000 0110 272 0000 0120 288 0000 0130 304 0000 0140 320 0808 0150 336 0828 0160 352 9000 0170 368 0000 0180 384 0000 0190 400 0000 01A0 416 0000 01B0 432 0000 01C0 448 0000 01D0 464 0000 01E0 480 0000 01F0 496 0000 This is sector It 1 absolute Tags 0000 0000 000 0000 0010 016 0000 0020 032 0000 0030 048 0000 0040 064 0000 0050 080 0000 0060 096 0000 0070 112 0000 0080 128 B23F 0090 144 492F 00A0 160 3 00 0080 176 COOC 00 0 192 0024 0000 208 1 02 23 5 063 499 0201 2F65 001E 030 3802 8 02 001 0441 00 9420 3900 7 40 0010 060 0017 8400 0000 0000 0003 3 of file Virtual sector 27 located at track 2 0002 0300 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0400 0810 0 00 0830 59 0000 59 0000 5920 0000 5960 0000 59 0 0000 59 0 0000 5902 0000 5906 0000 590 0000 590 0000 0 00 0810 0 00 0830 1900 000 1900 000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000
10. 0050 080 0060 096 0070 112 0080 128 0090 144 00 0 160 00B0 176 00C0 192 00D0 208 00E0 224 00F0 240 0100 256 0110 272 0000 0660 76 5 6AF3 224E 0600 0600 3781 0660 BC60 0 45 1 24 FFCS 5225 4FD4 0000 6 25 5 2 7F43 sector 35 0002 8066 0308 0815 0881 4166 FC60 9821 6 00 6123 FA4D 1A02 004 1700 2 00 0202 081 AFOO 024 E767 DF67 B434 424E 0000 0000 0000 0000 FAF2 2F00 4F24 004 0600 96 5 000C secto 0002 0000 8A32 SA4E 6254 0200 02C5 6200 14CS FE81 FAF1 5225 4FD4 6 00 FC00 0467 2F00 7800 1467 0300 OOFS 00 2200 5200 1222 00 7AF3 2C60 7E40 FAF2 8007 7504 0D67 0825 573F E100 7F00 772F 0000 0000 FC80 7A67 BAOC 9EOC C80C 002 5234 0400 524E 6254 0285 8A4E 12 r 36 0300 84 5 2F00 6254 AF00 0458 6F00 0600 8A3F 6100 6208 6 00 00 0800 104 0A24 0 25 2400 2848 5 063 499 of file Virtual located at track 2 000B 9FCC SA1D FC29 14 04 0 0024 0800 0266 1 4 4167 0400 0229 8A14 0460 022 8ABO 8953 2C00 0429 6 03 00 E64C DFSF FF61 OOFE 7600 2421 7AF3 7000 OOFE 564A 6800 186B E73F 3CFF FF2F 3AF3 E650 EEOO 7860 OOFD OOEF 8848 4006 8000 72700 0048 40 064E 081 E100 282F 2 00 044E 6224 SF2F FF4E 7324 SF4E 81 200C AF00 7 50 7 00 0000 0265 OA3F 700 OACS BA34 3781 6100 A20C 4200 7 67 0000 424 7366 0 5 8060 600C
11. 0130 304 8 2 0140 320 FC2D 0150 336 C12D 0160 352 004C 0170 368 6 00 0180 384 F23F 0190 400 7F43 01A0 416 574 0180 432 F228 010 448 20 0100 464 0002 01E0 480 FCEO 01F0 496 100 This is sector It is absolute Tags 0000 0000 000 7542 25 B266 0066 52 5 7420 2043 5772 6861 0000 0000 9000 0000 0000 0000 6900 0000 0000 0000 0000 0005 964 122 4 24 3139 6 72 6974 6 20 0000 0000 0000 7 04 O8FF 0000 7F3F 0000 0000 0000 0000 754 OA4E 524E 3838 706F 7465 462E 0000 0000 0000 0000 DF01 0000 7COF 0000 0000 0000 0000 F081 6A4A 7524 2043 7261 6E20 2047 0000 0000 0000 0000 8352 0000 00 0000 0000 0000 0000 5 063 499 100 6 08 436 6F6E 7469 6279 6172 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 7C40 004A 7079 6E65 6F6E 204A 6265 0000 0000 0000 0000 0104 0000 0000 7F81 0000 0000 0000 5 of file Virtual located at track 2 sector 29 0002 0000 0000 0000 0055 4C60 8860 0267 C000 1A0C 2860 1F60 OFSF FAFE 0700 2666 9100 6 00 4000 4CS2 8853 200 4900 DFSF 5020 2151 44DE 754A 4E61 1667 8200 4090 D200 0006 0300 0000 0000 0000 8F32 220C 0420 4655 0667 8000 0 08 004 FF4E BCS2 1466 0842 6A01 4A46 5452 6E00 8022 4420 5049 FFOO 2158 C8FF FCOO 9666 0000 DE22 0007 C166 8066 6 of file 0005 0000 0000 0000 2F00 6F
12. 430 1821 4467 0230 0011 0300 0302 0061 0500 8000 5 30 7801 F801 BC43 0021 A64D 0000 B940 0070 7 00 B64E 9020 B940 3E4E 800 20 4F22 FC67 4890 724E 800B 7802 04 821 FC4E C802 0A02 2 00 17 sector 41 0002 0031 42 5 20 EEOO SF6A 8011 0060 4AA9 BC20 2800 0300 7802 A800 2800 0A70 1041 70 0620 9736 1F67 0241 85D0 07FF 89B3 064 0022 O8EA C8FF B801 FCO2 FCOO 7CO0 1967 A935 E022 of file located at track 3 0010 FC3F 0026 0323 0821 3CA0 081 0043 F81E CEO1 FA00 BC21 8002 0120 021 B940 SF20 8004 B940 804E 004 7801 064E FC20 B940 B820 A621 004B 004E B940 21 0100 7 0 9 08 8804 800 00 5DA2 3801 F80C 004 0811 084 57 DE21 780D 004 8000 7 00 784 8004 B940 B940 oc2c B940 00A0 8266 7802 C801 EFO1 B940 8015 0001 cooc 6030 of file located at track 3 0011 1000 1242 SA4E 10A0 EEFC 004 4 21 1 0 4224 EEFE 9 16A0 6800 B940 2 55 0042 940 0002 43FF 40A0 024A 5 063 499 oc4c 40FF 083F 0000 1A08 8412 7 00 7 00 22 FC63 0008 0100 0060 0800 Virtual 5 10 900 8000 0800 7F42 4741 2 26 BO4E B940 C701 F940 4 53 FC00 BC4E B940 0A70 7F42 B940 644E 8002 8060 7801 802 2043 364 620 1821 9020 8002 1620 1412 0100 2E00 0500 7700 0843 000D 3800 94
13. 6974 6E20 030C 6431 007 0000 0000 0120 8 01 0000 4 68 2064 7561 2 20 206E 6F72 616C 6368 7461 2023 8601 6500 696 7920 7468 6169 7973 8850 3838 706F 7465 462 B166 FFFF 00 0 0000 6576 0202 0000 2120 6574 6C20 2050 6F74 206E 6C20 2053 6C20 225 5704 0 00 6720 2874 2061 6 74 7465 4824 2043 7261 6E20 2047 001 sector 2 F007 0000 0000 696E 0102 0800 2056 6563 6D65 6 65 6520 7560 436F 7570 4D65 3022 0544 9601 7769 686F 6273 7929 6020 436 6F6E 7469 6279 6172 EAOC a a lt v n n9 we a 9 e 9 9 9 9 5 3 gt e 9 5 m 9 n n o e t 6 4 q Uh Oh V irtual has detec ted a virtual me imory error Ple ase make a note sof the error num ber and call Co nnectix Tech Sup port Virtal mory Error 4 0 SContinuing wi 11 probably tho ugh not with abs olute certainty cause a system crash pyright 1988 Con nectix Corporati 0n
14. lt 1 M 01F0 496 A030 3 0 02 0 4730 3 0 03A1 4623 C800 0 lt 60 lt This is sector 0012 18 of file Virtual It is absolute sector 42 located at track 3 sector 6 Tags 0000 0002 0300 0012 9FCC SA1D 0000 000 7 43 8420 7 00 7F4F 3 0 03 0 472F 0 0 lt 0010 016 3 00 7F42 723F 3C00 083F 3C00 9520 lt lt lt 0020 032 7 00 7 0042 A042 6021 1 42 604E 672 11 B B B NG 0030 048 4891 C822 7 00 7 80 0022 D822 D822 3 00 t Une 0040 064 7 52 9230 3 00 3022 C151 C8FF FC20 3 00 0 lt 0 lt 0050 080 0001 0042 9951 C8FF 3CA9 FFA1 4623 2 0 0 lt 4 0060 096 800 7 43 8 23 00 7 43 000 7 80 0823 PES es uy A uy 0070 112 FCOO 7 50 7 00 7F80 2023 FCOO 7 52 1400 2 P 0080 128 7 80 2423 FCOO 7FSO 4600 7 80 2823 00 0090 144 7F42 6COO 7 80 7 22 7 00 7 80 004 7 98 1 171 00A0 160 0121 F900 7 43 8800 084E 733F 3CFO 203 C Ns2 lt 2 00B0 176 3CFF FF61 OE4E 753 3 303F 3CFF FF61 a Nu 0 a 00 0 192 024E 754E 600 002F 0B42 72 3 49 434E NuNV B ICN 0000 208 233F 2E00 OAA9 A020 1F67 2020 40A0 2926 g 8 6 00 0 224 482F 103F 2E00 084 BAOO 1420 4BAO 2A2F K 00F0 240 08A9 A326 SF4E SE2E 9F4E 7560 F64E S6FD 1 8 N NuC NV 0100 256 SC48 E73F 1 4 EEFD 5 48 6
15. o L o Bd gt vef 7 QFU W b H f ii atone Q 4 8 Iq T 2 L 5 iL Ness M 81 Ss ease f O 8F J LRn JF NuO n Tc Q TRn H HOPES B v 8 f a f ioc ds f B N uB Nu gv B 0010 016 1923 0020 032 0 61 0030 048 7F43 0040 064 0648 0050 080 DFO 0060 096 DFOO 0070 112 5C60 0080 128 6 00 0090 144 45 00A0 160 4A26 00B0 176 007 00 0 192 0300 0000 208 0830 00E0 224 FF38 00F0 240 4138 0100 256 0000 0110 272 44FF 0120 288 0000 0130 304 422C 0140 320 00 2 0150 336 4933 0160 352 0167 0170 368 8874 0180 384 FF66 0190 400 0000 01 0 416 AE32 0180 432 3162 01C0 448 0026 0100 464 0652 01E0 480 440C 01 0 496 4748 This is sector It 1s absolute Tags 0000 0000 000 E808 0010 016 BC80 0020 032 8261 0030 048 0866 0040 064 7 0050 080 0652 0060 096 440C 0070 112 4B00 0080 128 300C 0090 144 FA26 00A0 160 2C41 00B0 176 FC26 00C0 192 0007 00D0 208 104A 00E0 224 E760 00F0 240 064A 0100 256 7 43 0110 272 300 0120 288 00 0130 304 OOFD 0140 320 1 0150 336 0160 352 6800 27 200 000A 104A E760 064A 7F43 9E23 5 08 FAOC 3801 0042 3E66 0020 0053 0867 FF66 0067 0008 4908 8162 0001 0051 9A60 0866 3162 00 2 4836 4725 44FF 4192 0007 0002 0300 0062 00 242C 0026 4725
16. 0000 0000 0000 0000 004A 6800 186 Jh Xk 0020 032 064E FB81 61 5 D840 E742 672F 5 CE48 9 0030 048 FA4D 5 4642 6 00 7847 FAFB 0620 M FBn xG 0040 064 2800 24B0 AE00 7463 0420 4000 7426 2800 6 68 0050 080 20 6 B803 1A28 4300 8302 43 8 0022 4376 Po C C Cv 0060 096 0032 3 00 FFFO 1490 5705 FCOO 7700 0083 2 lt W w 0070 112 CC66 1602 FCO8 0080 8965 124A 6F00 3C66 uo ua s e Jo lt f 0080 128 0 02 6AFC FFOO 0260 0402 08 00 0 8B00 See o suq 44 n nn 0090 144 0 48 E700 0861 00 6 244C DF1B 0808 EAOO 1 00A0 160 0800 0266 OC4A 4366 0226 1352 8327 8A34 1 f J0Cf amp R 4 00B0 176 0028 4980 8 53 C9FF 52 4167 6626 834C 1 S RAgf amp L 00 0 192 DFSF FF66 0461 OE60 0461 0 61 2CSC 8 46 t _ f a a a F 0000 208 DF4A 404E 7550 F900 7F43 104E 781 6100 00 0 224 044A 4067 OCOC 4 567 FOOC 40FF EF67 J8g 8 9 8 g 00 0 240 EA42 3900 7F43 104E 7548 E710 1047 FAFB B9 C NuH G 0100 256 1426 1B66 0260 1453 4308 B300 0835 1200 u SC 0110 272 0257 CBFF F64A 436B 0260 EE42 A34C DF08 21 8 0Ck B L 0120 288 084 7526 8340 FAF4 420 6800 2400 6030 Nu amp M T h S 0130 304 6800 2 00 642D 6800 2E00 6890 8922 2800 kh d h h 0140 320 2492 8026 0102 41FE 0021 4100 2402 8300 amp 5 0150 336 0001 FFDO 8320 4000 6C93
17. 67 1831 0000 0031 4900 2800 024E 187A OSDA 024E 4000 2021 8 of file Virtual sector 32 located at track 2 0300 0008 2431 7 00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9FCC 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5 10 2C42 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 A800 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0009 9 of file Virtual sector 33 0002 0000 0000 0000 0000 0000 0000 0000 0000 0300 0009 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SFCC 0000 0000 0000 0000 0000 0000 0000 0000 5 10 0000 0900 0000 0000 0000 0000 0000 0000 located at track 2 0000 0000 0000 0000 0000 0000 0000 0000 780A 1270 1A11 71
18. 9 0000 0000 6240 6069 0000 4540 0000 0000 0139 0139 0000 0000 0000 0000 0000 0000 0000 5245 OOFF 0000 8 190 0 03 007 0000 0000 0000 FFFF FFFF FFFF Tags 0000 000 0010 016 0020 032 0030 048 0040 064 0050 080 0060 096 0070 112 0080 128 0090 144 00A0 160 00B0 176 00 0 192 0000 208 00E0 224 00F0 240 0100 256 0110 272 0120 288 0130 304 0140 320 0150 336 0160 352 0170 368 0180 384 0190 400 01A0 416 01B0 432 01C0 448 01D0 464 01 0 480 01F0 496 0000 0000 0000 0000 494E 0000 2300 0000 FOOF 001 31FC 0 03 FFFF 0750 0000 0000 F80F FFFF FFFF FFFF 0001 sector 25 This is sector It is absolute 0000 FFFF lFF8 0000 0001 0000 0000 0002 0007 0000 0000 0000 0000 0000 1004 0300 07EO 0000 0000 00 0 E398 0001 F001 0000 0000 0000 0000 0007 1004 SA1D 8000 0000 0000 0000 0000 F004 1024 9FCC E003 0000 0000 0000 01 0 FFFF 6198 Tags 0000 000 0010 016 0020 032 0030 048 0040 064 0050 080 0060 096 20 under the current version 6 0 2 of the Macintosh oper ating system From the foregoing teachings it can be appreciated by those skilled in the art that a new novel and unobvi ous virtual memory system for use on Apple Macintosh personal computers using the 680 0 microprocessors with appropriate memory management has been
19. Memory Draws Nearer MacWeek Jan 31 1989 p 1 First Look Virtual 2 0 Beats Mac s 8M Byte RAM Barrier PC Week Oct 23 1989 pp 15 18 Designing Cards and Drivers for Macintosh II and Macintosh SE Apple Computer Inc Addison Wesley INIT jio Publishing Company Inc 1987 ISBN 0 201 19256 X pp 1 4 to 1 6 Macintosh Family Hardware Reference Apple Com puter Inc Addison Wesley Publishing Company Inc 1988 ISBN 0 201 19255 1 pp 16 10 and 16 11 MC68020 32 Bit Microprocessor User s Manual Third Edition Motorola Inc Prentice Hall Inc 1984 1985 ISBN 0 13 566951 0 particularly Section 1 3 Eternal Ramdisk Program Dec 06 1986 Com puServe Information Service Byte Nov 1989 pp 341 360 Connectix s Virtual Memory Solution News Jun 5 1989 p 8 Mac the Knite No field test for 3 slot 030box2 MacWeek Nov 29 1988 p 70 MC68030 Enhanced 32 Bit Microprocessor User s Manual Second Ed Motorola Inc Prentice Hall Inc 1989 ISBN 0 13 566951 0 pp 1 1 to 1 12 MC68851 Paged Memory Management Unit User s Manual Motorola Inc Prentice Hall Inc 1986 ISBN 0 13 566902 2 particularly Chap 2 and Appendix C MC68851 Paged Memory Management Unit User s Manual Second Ed Motorola Inc Prentice Hall Inc 1989 ISBN 0 13 566993 6 as with the first edi tion particularly Chap 2 and Appendix C Operating Systems Design and Implementation An drew S Tanenba
20. address is saved in a static location all at step 25 45 55 60 65 10 84 This permits interrupts to be re enabled which im proves the apparent response of the system If no page fault was being processed at step 82 or following step 84 if a fault was being processed the process continues at step 86 by obtaining the exception vector number from the exception stack frame The current address pointed to by the exception vector num ber is then pushed on the stack in step 88 which permits execution to resume in step 90 at the original exception vector address In this manner the exception vectors set forth in Table above can be processed in essentially the same manner as for a non virtual memory system Privilege Violation Vector With reference now to FIG 4 a solution is shown for another type of problem with occur with a virtual mem ory system on the Macintosh system Since the proces sor is now normally running the operating system and programs in user mode while the operating system and programs expect to be running in supervisor mode there will be some occasions in which the CPU will be instructed to execute supervisor only or privileged instructions This causes a privilege violation which typically can be handled in either of two ways First the instruction can be emulated in software so that the user program does not know the instruction was not actually executed The second alternative is to permit the in
21. appear as if a single five megabyte read occurred so that the calling program is unaware that the read was not performed as one contiguous piece To understand the foregoing in greater detail refer ence is again made to FIGS 11a and 116 The read patch is entered at step 340 and inquires at step 342 whether the call which entered the read patch is a file system call rather than an I O call If it is a file system call the routine branches to step 344 where it jumps to the original read trap address However if the call which caused entry to the read patch is an I O call the routine branches from step 342 to step 346 where supervisor mode is enabled The system starts with the first block of information to be read from disk at step 348 and determines at step 350 to what memory page the block will be written It is then determined at step 352 whether th t page is resident If not a determination is made at step 354 whether the page of physical memory will be completely overwrit ten by the read from disk If the page is to be overwrit ten the disk image flag for the page is cleared at step 356 if not step 356 is bypassed Either way the page fault routine of FIG 8 beginning at step 222 is then used to validate the page If the page was not previously marked with a Don t Swap flag the page is then temporarily locked at step 360 by setting its Don t Swap flag and the page is added to a list of temporarily locked pages O
22. dis closed It is to be understood that numerous alternatives and equivalents will be apparent to those of ordinary skill in the art given the teachings herein such that the present invention is not to be limited by the foregoing description but only by the appended claims 0 of file Virtual It is absolute sector 24 located at track 2 sector 0 0000 0000 2049 0000 0000 0000 0000 2780 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 OFFO FFFF 61F8 1 6 1 00 781 0000 0000 OFFO FFFF FFFF FFFF FFFF 0008 0000 22 4949 494 0000 0040 is 0000 0000 E 0000 0000 0000 0000 0000 0000 0000 0000 1c56 00 0 0000 0000 005 lp 380C 380 1 8 1 8 7005 22 8 B8 0000 0000 0000 0000 F005 F80F F80F F005 4 6 o o s 4 c ee e qe ea 14 t t1 1 4 41 4 e 9 t t 24 4 9 dot 9 n t a 4 99 o o w lt a a 9 9 0 s on 1 of file Virtual loc
23. for example A UX and certain other manufacturers such as Sun Microsystems for example use different operating sys tems for example UNIX with the same classes of mi croprocessors and offer virtual memory in such differ ent environments The Motorola 680 0 series of microprocessors are designed to have two modes of operation usually re 50 55 60 65 2 ferred to as supervisor mode and user mode To imple ment virtual memory user programs generally are not permitted to operate with the 680 0 microprocessor in supervisor mode Instead only the operating system and operating system calls may run the processor in supervisor mode while user programs operate only in user mode A difficulty arises with the Apple Macintosh series of personal computers using 680 0 microprocessors be cause the Macintosh operating system permits user programs to operate the 680 0 processor in supervisor mode A key difficulty which results is that the user programs for the Macintosh computer operating with the 680X0 processor in supervisor mode may change the location of the supervisor stack FIG 16 is a simpli fied block diagram of the arrangement of physical mem ory in a conventional Apple Macintosh computer showing the operating system zone at the lowest ad dresses in memory followed by a zone of memory for application programs Above the zone for application programs is a stack zone which in conventional Apple Macintosh comput
24. g Rn 2 H 2 N a L a tg 0170 368 0180 384 0190 400 01A0 416 01 0 432 01C0 448 0100 464 01 0 480 01F0 496 2800 5 00 08 2 7 00 6800 003 4500 6900 6 00 This is sector It is absolute Tags 0000 000 0010 016 0020 032 0030 048 0040 064 0050 080 0060 096 0070 112 0080 128 0090 144 00A0 160 00B0 176 00C0 192 00D0 208 00E0 224 00F0 240 0100 256 0110 272 0120 288 0130 304 0140 320 0150 336 0160 352 0170 368 0180 384 0190 400 01A0 416 0180 432 01C0 448 01D0 464 01 0 480 01 0 496 0000 0008 7500 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 This is sector It 15 absolute Tags 0000 000 0010 016 0020 032 0030 048 0040 064 0050 080 0060 096 0070 112 0000 0000 0000 0000 0000 0000 0000 29 3078 1842 6067 0300 1800 2900 1 4 1430 1A00 0008 0002 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0038 2800 A800 1C43 024E 7142 1B42 A800 2E22 7803 263C 2900 0360 06 2900 483D 1821 7 00 38 8 09 800 1 0 4ED2 284C A900 4000 7EF8 5 063 499 FCO2 C821 0C42 006 E800 0350 0
25. in supervi sor mode under close scrutiny Additionally the process of the present invention intercepts other operations which might corrupt the state of the stack pointer and relocates to the appropri ate new location such as a user stack the information sought by or left from those operations In some situa tions user programs may attempt to alter the addresses used to perform such intercepts Such difficulties are avoided by forcing the routine to alter a different ad dress permitting the original vector exception table to be left intact The appropriate jump may then be made after the process evaluates the requested exception To permit the present invention to be implemented on an Apple Macintosh II computer using a Motorola 68020 microprocessor a memory management chip such as the Motorola 68851 PMMU must be added to the system A socket for such a chip s provided on the currently available Macintosh II Shown in FIG 1c isa simplified hardware schematic showing the interposing of a PMMU chip between the 68020 CPU and memory such as is found in the Apple Macintosh II computers In addition the process of the present invention oper ates Apple Macintosh computers using the Motorola 68030 microprocessor and running under the Macintosh operating system since the 68030 internally provides the memory management features necessary for opera tion of the present invention To implement the present invention on existing mod els of
26. known Most use a memory management unit of some sort which maps a memory address in the virtual address space either to physical RAM or to the peripheral stor age One such algorithm is referred to as paging in which the virtual address space is divided into pages and pages of information are swapped between the physical RAM and the peripheral storage Various al gorithms also exist for determining when best to make such a page swap One common approach is to swap pages on demand Shown in FIG 1a is a simplified prior art implemen tation of virtual memory As can be seen when the 25 30 35 40 system detects an attempted access to a location of 45 memory not resident in physical RAM it saves the state of the processor on the stack swaps in the page of vir tual memory containing the necessary information re trieves from the stack the state of the processor and proceeds to execute the instruction that accessed the virtual space Although such virtual memory techniques are well known such techniques generally have not been ap plied in the microcomputer based personal computer environment Thus for example virtual memory has not been used in the Apple Macintosh Macintosh SE Macintosh II environment with the Macintosh operat ing system These environments may in general be thought of as Motorola 68X XX based microcomputers using the Apple Macintosh operating system Other operating systems offered by Apple
27. non critical In this manner a non critical page can always be selected to be swapped out to disk The page selection routine described generally above can be appreciated in greater detail from the following The page selection routine is called at step 300 and begins at step 302 by inquiring whether it is time to update the aging tables The criterion for updating the aging tables can be varied over a fairly wide range and might include real time recent usage history of any one or more pages frequency of occurrence of page faults or number of page swaps since last update as just some examples Time and usage history have thus far been used in a preferred approach If the inquiry at step 302 determines that it is not time to update the modified and unmodified pagse with the lowest usage history are identified at step 304 20 25 30 35 45 50 55 65 16 However if an update is in order the time out flag is reset at step 306 The aging tables are then updated at step 308 with usage information since the last update and the usage flag is reset Next the modified and un modified pages with the lowest usage history as stored in the aging tables are identified at step 310 Regardless whether the aging tables were updated the appropriate branch supplies the usage history of the modified and unmodified pages to step 312 where the usage history of the unmodified page is compared to that of the modified page in acco
28. sau eus Oise 2 0170 368 9AFF FFOO 0003 5300 0000 0004 4061 696 Scena Main 0180 384 0000 0000 0000 0000 0000 0000 0000 0000 EI 4 0190 400 0000 0000 0000 0000 0000 0000 0000 0000 01 0 416 0000 0000 0000 0000 0000 0000 0000 0000 01 0 432 0000 0000 0000 0000 0000 0000 0000 0000 01C0 448 0000 0000 0000 0000 0000 0000 0000 0000 0100 464 0000 0000 0000 0000 0000 0000 0000 0000 01 0 480 0000 0000 0000 0000 0000 0000 0000 0000 01 0 496 0000 0000 0000 0000 0000 0000 0000 0000 I claim i reconfiguring the Apple Macintosh computer to con 1 A method of utilizing physical memory and periph eral storage in an Apple MacIntosh computer running under an Apple Macintosh operating system wherein the Apple Macintosh computer includes a suitable mi croprocessor capable of coacting with memory man agement logic either internal or external to the micro processor and an amount of physical memory and wherien the Apple Macintosh computer is capable of operating in both user and supervisor modes as virtual 55 memory comprising the steps of allocating a portion of the peripheral storage as a virtual memory file determining the amount of the physical memory resi dent in the Apple Macintosh computer 60 setting the memory management logic to address at tinue processing normally performed in superviso
29. that logical addresses need not map always to a physical address on a 1 1 basis Re Vectoring Patch With reference now to FIG 3 the flow diagram shown therein describes the redirection of the exception vectors not treated specifically hereinafter Basically the approach taken by the routine shown in FIG 3 is to receive the exception vector look up the value of the address currently stored in the original vector table and jump to the routine at that address This leaves the stack unaltered from what it would have been if handled direotly Thus programs can be fooled into not realiz ing the VBR has changed locations while still being permitted to alter vector addresses in the original zero vector table The programs can aiso affect where the exception will be processed while leaving the supervi sor stack protected Optionally to improve system per formance interrupts can be re enabled during the page fault caused by the exception vector after saving a copy of the registers and the stack pointer on the stack Sav ing such additional information will permit handling of secondary page faults as will be described in greater detail hereinafter In FIG 3 when an exception vector is received the routine is called up at step 80 and begins by determin ing at step 82 whether a page fault is currently being processed If it is a copy of the registers and the stack pointer is saved on the stack and a pointer to the cur rent stack
30. the Macintosh line which use a 68000 processor such as the Macintosh SE Macintosh Plus Macintosh 512E and others it is necessary to add a 680X0 proces sor other than a 68000 Numerous accelerator boards for these Macintosh computers offer just such capabil ity and use either a 68010 68012 68020 or 68030 pro cessor as well as providing a slot for a Motorola 68851 MMU As with the Macintosh II an MMU must also be added unless a 68030 processor is added to permit the Macintosh SE and Plus computers to run the present invention It is therefore one object of the present invention to provide a process for implementing a virtual memory algorithm on an Apple Macintosh computer having a 680X0 processor and operating under the Macintosh operating system It is another object of the present invention to pro vide a process by which an Apple Macintosh computer operating in user mode under the Apple Macintosh operating system emulates an Apple Macintosh com puter operating in supervisor mode under the Apple Macintosh operating system Still another object of the present invention is to provide a process by which instructions normally pro cessed by an Apple Macintosh computer in supervisor mode can be emulated by an Apple Macintosh com puter in user mode 10 15 20 25 30 35 45 50 55 60 65 4 It is a further object of the present invention to pro vide a virtual memory system which is substantially transp
31. up either regis ters or the stack with the calling parameters and then execute an instruction beginning 1010 The 1010 in struction in turn causes an exception to be generated to the un implemented instruction exception vector which effectively extends the instruction set of the pro cessor by causing the operating system to evaluate the instruction and generate the desired effects in software However such exceptions cause a transition from user mode to supervisor mode even though the user pro grams which made the call are operating in user mode with the user stack rather than the supervisor stack Thus when such a call is made it is necessary to substi tute the appropriate stack pointer to ensure that the pointer used by the system call is the same stack to which the parameters were originally passed This is accomplished by the routine described in FIG 6 where the line 1010 vector patch is called at step 160 The routine begins by inquiring at step 162 whether the system was in supervisor mode when the trap was called If so the routine jumps at step 164 to the original line 1010 vector address taken from the original zero base vector table If not however the routine branches to step 166 and copies the stack exception frame from the supervisor stack to the user stack Next at step 168 the return address of the current exception frame is replaced with the original line 1010 vector address so that when the return fro
32. 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 2F00 FAEB 6800 02 8 21 0C42 0066 E800 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 3500 E642 4400 0031 4900 2800 0006 184A 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 064E A800 1 26 780A 1270 1A11 D03D A900 15 of file located at track 3 sector 39 0002 0000 1CAO 284C A900 2900 7000 1A00 3C00 FC27 FAEB DA22 FC20 9951 70010 7500 F620 9951 0100 0022 0000 0122 9342 0258 E900 0300 24A2 12A0 0350 0865 483D 0100 1821 023F 004A 2091 7 00 3801 C8FF 0038 0800 0690 C8FF F678 004C 4020 0002 D342 9330 8951 0A00 000 1066 457 OSDA 0006 4000 2C21 7000 3 00 B801 9041 0840 084C FC2A 0006 0022 854 FC30 1F26 7 00 06 2 0006 9808 0422 C8FF 0258 9FCC 0006 007C 842D 802C 1831 7 00 0008 03A8 2067 FAEB 0030 7CO0 3801 4000 C106 7000 0422 7 00 0000 8804 8000 E900 7000 F622 8951 5 063 499 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 004E S6FF SE66 0007 OCA
33. 0 0003 0000 0000 0000 0000 0000 0000 0000 0000 0 00 0 00 S9FB 5950 5930 5970 59 0 59 0 5903 5907 5908 5902 OA00 0 00 1900 1900 0000 0000 0000 0000 0000 0000 0000 0000 9FCC 0000 0000 0000 0000 0000 0000 0000 0000 0818 0838 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0818 0838 8000 F000 0000 0000 0000 0000 0000 0000 0000 0000 SA1D 0000 0000 0000 0000 0000 0000 0000 0000 0A00 0A40 S9FC 5900 5940 5980 59 0 5900 5904 5908 590 5900 0 00 0A00 1900 1900 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 0820 0000 0000 0840 0000 0000 0000 0840 0000 0000 0000 0800 0820 8000 C000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0004 4 of file Virtual located at track 2 sector 28 0002 0300 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0102 8000 3 00 0840 0840 002F B2F0 1 4 004 7A00 4000 46 0004 0000 0000 0000 0000 0000 0000 0000 0000 0000 4060 3C7F 00 0 0208 DF4E 9FCC 0000 0000 0000 0000 0000 0000 0000 0000 FF67 0c22 FF02 0040 cooo 7502 SA1D 0000 0000 0000 0000 0000 0000 0000 0040 0 22 3680 0200 0029 034 8000 0000 0000 0000 0000 0000 0000 0000 E712 3C80 B849 7607 0140 7800 0000 40CO 8 0080 0000 Pagus sector 3 ec ceci t 0000 Jena
34. 0 8002 2 21 8020 430 7EF8 9020 8003 002F 5 30 800 940 CA4E 804E 080 BC4E F803 B940 5000 C802 7650 7 21 7802 2 00 066 7 0 Virtual SA1D 0 67 1 2 8012 4 42 800 8011 FF67 2920 6800 064 0766 7643 B80A 12A0 02 42 5042 522 046 0000 Lis 4008 Baca e e siiis 8 78 Xo 2 6 2 0053 227 bl S 0866 Find dies f 06 S entes SS 0008 Su Q sector 4 0320 Pu Sg uns Padus 0022 PI 8821 C BC20 tu t Bus 25 2E70 40 lt 1 0038 2 8 58 8 8002 8 8 202 CONS V SQL INST ot C30D Cb uius ieu FE 5021 FC42 N 0001 7CSO 004 8e cesbess NIR 0820 B 8 N X 2 m 3CA0 1 044 GN xN 800E 8 5N 8 d B940 N 8 N 8 B940 2F B857 iiw QUE B940 LSC g N 8 084E sucre 8000 rN f6N FC40 228222 Bori AA21 DW XV Eos F020 a aM eed Kees FCS7 tc Paes Bc t W A621 LSC N 8 060 044E 00 f N 6C41 0 2 1 sector 5 F940 ED Ma wees g N 8 0 28 7 08 Bh G F80A Z2N 8 vC F2A9 4 1 0066 6748 A742 7 6 9 2800 9 gB 8 R 0420 2 66 A Jh j 5 063 4
35. 0 CCFF 0748 182D 1308 BC80 C300 0300 4000 0652 81 5 66 0366 7 43 0908 0066 384 800 7130 5A1D 0324 6E00 0067 0086 ococ cc20 473E 7 00 0300 0062 0467 2E2F 6E00 61FB 0260 2230 1042 8300 0020 7541 1242 6800 5 2C60 2A08 4165 4701 7AFB 0424 0000 0 66 0052 7 02 7020 3900 SAAO 164 1823 4000 6 00 0428 4EOE FAF8 6800 4400 5 20 3900 B04C 1423 4000 3E42 FA10 0001 2 00 6E00 0A78 4490 0608 440C 2008 0A66 3162 00 2 4836 4725 44 4808 80EA AE32 OC7E 0064 0648 0753 0067 sector 7 AE33 0000 0000 1867 0064 5648 872D 0200 00 0 6 00 43FE 0861 7F43 0648 DFO DFOO 5 08 5 08 1467 2E4D 1642 1A26 58 21 SQ Ni e 5 Jr MS 18 9 C J C g Rn 2 H 2 lt N a L Jd g n f ES Or rd NU i yC sss gt B n N Nuz C SE sce n e Oi urs s j x 8 z B HD eis 225 21 I3 b Ae g amp H6 9 G d RGS 1 2 0 2 HD D Sef S S 42 gH eu C Bou gu wt a i EE 4642 1b I3 b Ae g amp 6 9 9 DQRGX t Q z H D D f JGg4 S gt an 06 f5 21b Ae g amp H6 g G d RG t Q z VH D D 8 HG gt ae lt 3 1 0 F 6 amp 3 1 amp gp t0 9 C J C
36. 0 0000 0000 0000 0000 0000 36 7743 29 C 9 CD C 2F00 D2 JHz V2 J2 044E W Bg Q0 N 0000 di PME 0000 0000 S e euim i y a IN PISTE D 0000 Sus S Seed wake awo 0000 tires era m 0000 a eae eve i 0000 S Puce e SUC a she que a 0000 Cen 0000 0000 0000 PCR Qo a sue 0030 048 0000 0040 064 0000 0050 080 0000 0060 096 0000 0070 112 0000 0080 128 0000 0090 144 0000 00A0 160 0000 00B0 176 0000 00C0 192 0000 0000 208 0000 00 0 224 0000 00 0 240 0000 0100 256 0000 0110 272 0000 0120 288 0000 0130 304 0000 0140 320 0000 0150 336 0000 0160 352 0000 0170 368 0000 0180 384 9 0190 400 9 01A0 416 0007 01B0 432 2800 01C0 448 1C43 01D0 464 E842 01E0 480 A800 01F0 496 7803 Th s is sector It is absolute Tags 0000 0000 000 8000 0010 016 0000 0020 032 2900 0030 048 06 0040 064 1430 0050 080 0 31 0060 096 6E00 0070 112 123F 0080 128 9546 0090 144 4041 00A0 160 FAE7 0080 176 CBFF 00C0 192 4942 00D0 208 0000 00E0 224 0122 00F0 240 CBFF 0100 256 8042 0110 272 0051 0120 288 8000 0130 304 0800 0140 320 7 00 0150 336 0420 0160 352 F220 0170 368 0800 0180 384 3F08 37 9000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 7608 EA4D 163D 38C8 FAFB 800 1CA0 4ED2 00
37. 0 0000 0000 0000 0000 0000 0000 0000 ETE PE RE 0000 208 0000 0000 0000 0000 0000 0000 0000 0000 00E0 224 0000 0000 0000 0000 0000 0000 0000 0000 00F0 240 0000 0000 0000 0000 0000 0000 0000 0000 Sad Sabie arse 0100 256 0000 0000 0000 9000 0000 0000 9000 0000 S abe ace 0110 272 0000 0000 0000 0000 0000 0000 9000 0000 0120 288 0000 0000 0000 0000 0000 0000 0000 0000 0130 304 0000 0000 0000 0000 0000 0000 0000 0000 0140 320 0000 0000 0000 0000 0000 0000 0000 0000 TUE 0150 336 0000 0000 0000 0000 0000 0000 0000 0000 HE TENERA 0160 352 0000 0000 0000 0000 0000 0000 0000 0000 0170 368 0000 0000 0000 0000 0000 0000 0000 0000 aer 0180 384 0000 0000 0000 0000 0000 0000 0000 0000 Da eret aia o s ain n 0190 400 0000 0000 0000 0000 0000 0000 0000 0000 IDEE 4 01 0 416 0000 0000 0000 0000 0000 0000 0000 0000 01B0 432 0000 0000 0000 0000 0000 0000 0000 0000 ERIT TEE 01C0 448 0000 0000 0000 0000 0000 0000 0000 0000 d Ux Ue Rs ears 0100 464 0000 0000 0000 0000 0000 0000 0000 0000 S a a aa s 01E0 480 0000 0000 0000 0000 0000 0000 0000 0000 ICE 01 0 496 0000 0000 0000 0000 0000 0000 0000 0000 This is sector OOQA 10 of file Virtual It is absolute sector 34 located at track 2 sector 10 Tags 0000 0002 0300 000A 9FCC 10 0000 000 0000 0000 0000 0000 0000 0000 0000 0000 E 0010 016 0000
38. 0 4 70 6572 tual Memory Oper 0020 032 6174 696E 6720 5379 7374 6560 2049 6E69 ating System Ini 0030 048 7469 616C 697A 6572 2066 6F72 2074 6865 tializer for the 0040 064 2040 6163 2049 492 2020 436F 7079 7269 Mac II Copyri 0050 080 6768 7420 3139 3838 2C20 436F 6E6E 6563 ght 1988 Connec 0060 096 7469 7820 436F 7270 6 72 6174 696F 6E2E tix Corporation 0070 112 2020 S772 6974 7465 6E20 6279 204A 6F6E Written by Jon 0080 128 6174 6861 6E20 462 2047 6172 6265 722E athan F Garber 0090 144 2041 6C6C 2072 6967 6874 7320 7265 7365 All rights rese 00A0 160 7276 6564 2E00 0001 0000 0026 500 0025 amp i 0080 176 500 0000 0800 6 1 9804 0 00 0000 100 1 00 0 192 0600 0756 4045 4000 0000 4246 5245 4600 2 0000 208 0000 4E42 4E44 4 00 0000 5A49 434E 2300 NBNDL 2ICN 00E0 224 0200 6649 4E49 5400 0000 8 53 4552 2300 fINIT SERE 00F0 240 0000 9641 4CS2 5400 0000 A244 4954 4C00 ALRT OITL 0100 256 0000 00 OOFF FFOO 0025 0300 0000 00 0 29 ores i 0110 272 20FF FFOO 0000 0000 0000 OOFO 20FF FFOO aues RR SEE evt 0120 288 0000 0800 0000 00 0 30FF FF20 0000 2800 CTI es 0 uti 0130 304 0000 OOFF 8 FF20 0001 2 00 0000 00 0 Tg 0140 320 20FF FF20 0002 3300 0000 0000 0 00 0000 2 d e ee ee ee i 0150 336 0004 7700 0000 0000 O8FF FFOO 0003 3700 du DC IUE 72 0160 352 6A8D 8802 9AFF 00 0003 4300 0000 0002 4
39. 0 system calls within the Macintosh operating system 5 063 499 5 FIG 7 is a flow diagram of the process of the present invention for permitting the Macintosh operating sys tem and programs executing under it to run with virtual memory in 32 bit mode as well as 24 bit mode FIG 8 is a flow diagram of the process of the present invention for handling page swaps between the physical RAM and the virtual address space FIG 9 is a flow diagram of the process of the present invention for permitting the system to handle double page faults which can occur when an interrupt gener ates a page fault while a page fault is already in progress FIG 10 is a flow diagram describing the process by which the present invention selects pages of physical RAM to be swapped out to disk FIGS 114 115 taken together are a flow diagram showing a read optimization routine in the present invention for transferring information from the virtual address space to physical RAM in anticipation of need DETAILED DESCRIPTION OF THE INVENTION The process of the present invention basically is com prised of several routines which cooperate to permit implementation of a virtual memory algorithm on a suitably configured Macintosh computer running under the Macintosh operating system As noted above a suitably configured Macintosh must include a 680X0 processor other than the 68000 MMU functions and a suitable storage media such as a hard disk or other co
40. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 14 r 38 0300 0000 0000 0000 3900 7AF2 672 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 7F43 563 B781 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 of file located at track 3 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9FCC 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 of file located at track 3 5 063 499 4423 2F00 144 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 croo 4A3F EFOO 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Virtual SA1D 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9000 0000 0000 0000 0000 0000 0000 0000 0000 Virtual 000 SFCC SAID 0000 0000 0000 0000 0000 0000 000
41. 1004 0 03 F000 00 0 0000 00 0 0000 0000 0000 0000 0000 00 0 F007 FFFF F27F FFFF 1F24 1004 0000 0000 0140 1005 0007 F027 FF7B F007 003 0820 0000 0000 0000 1004 1F7C 9004 0000 0000 0000 0000 0000 F007 FF7F 1 66 0000 0000 0000 03 0 FFFF FFFF FFFF FFFF 01CO 0000 0000 00 0 398 1 66 0000 0000 0000 00 0 FFFF FFFF 5 063 499 1204 1007 0000 0000 0220 A003 F007 F27B EF27 F007 coos 0440 0000 0000 0007 1004 1F24 1004 0000 0000 0000 0000 0007 F007 FF27 0C03 FFFF 01E0 0000 0000 01C0 FFFF FFFF FFFF FFFF 03E0 0000 0000 01 0 6198 1 66 0000 00 0 0000 0000 01 0 FFFF FFFF FFFF 0002 2 of file Virtual located at track 2 sector 26 0002 8300 F007 FFFF F000 00 0 0000 00 0 0000 0000 6 00 0000 5500 0001 5 01 7108 7475 616 6420 6120 7279 2065 6520 6061 2074 6865 722 2061 6563 7469 7274 3A0D 7279 2045 0000 0000 6E21 A100 5343 6F6E 2070 726 6820 6E6F 7574 6520 6175 7365 6173 683A 7269 6768 6374 6978 0000 001D 6F6E 6174 7200 000C 0002 F007 0000 0000 0000 2000 9955 2068 7669 7272 6865 2065 6E64 7820 0056 7272 7201 0000 7469 6261 7420 6365 2061 0000 7420 2043 5772 6851 3800 9FCC FFFF 0000 0000 6400 0200 6820 6173 7274 6F72 2061 7272 2063 5465 6972 6F72 1800 0000 6E75 626C 7769 7274 2073 0020 3139 6F72
42. 324 the aging tables for the fast aging pages can be updated new lowest usage unmodified and modified pages selected and the routine returned to step 312 for further processing Read Patch The read patch routine shown in FIGS 112 116 is essentially a pre fetch of pages of disk data to physical memory Such a pre fetch is particularly helpful in the virtual memory context to avoid a page fault during time critical operations in which occurrence of a page fault during the operation can cause an error exam ple of such a time critical operation is a read or write from disk in which a page fault during the read can cause the status of the disk interface to be lost More specifically during a disk reads or writes the spinning hard disk may not be able to wait and hold its place while a page fault is made good Thus it is helpful to avoid such situations by what is referred to herein as pre fetching Successful use of pre fetching relies in part on the good programming practice that I O operations are executed only through the operating system That is any program or peripheral that needs to perform I O operation posts that request to the operating system The request to the operating system includes where the information is to be placed in memory how much infor mation is to be transferred and where the information can be found The operating system then performs the operation and returns the result By intercepting and
43. 333 086 539 03X307 BLE JMVADTIV XVW OL 1530934 933 32n033 71504 04934 0130 9 6 30 371 34015 911 7914 5 063 499 1 METHOD FOR CREATING A VIRTUAL MEMORY SYSTEM BY REDIRECTING ACCESS FOR USER STACK INSTEAD OF SUPERVISOR STACK DURING NORMAL SUPERVISOR MODE PROCESSING FIELD OF THE INVENTION This invention relates to virtual memory systems for computers and more particularly relates to virtual memory systems for microprocessor based computers using the Motorola 680 0 series microprocessor and the Apple Macintosh operating system BACKGROUND OF THE INVENTION Virtual memory has long been known for use with mainframe computers and minicomputers Virtual memory basically refers to a technique for combining a quantity of physical memory typically provided by 5 10 semiconductor chips such as DRAM with a block of 20 peripheral storage which has in the past usually been magnetic media based storage such as a hard disk to give to the computer user the impression that the amount of physical RAM is actually larger than the available physical RAM The advantages of such techniques are well known in the art Certain of these advantages are particularly noteworthy at present including the substantial cost and relative unavailability of DRAM memory as com pared to hard disk memory as well as nominal space and power requirements and nonvolatility A variety of virtual memory algorithms are
44. 3D 007C 842D 7122 1631 7600 sector 8 OC4E 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 30 0x 8 8 1x 2 B C T p w i s ng e e 4 e n 4 eee on asoson 9 gt 9 c 9 a 9 a n ec 9 9 n 5 gt 4 gt 4 44 w o ee e es 4 14 0 9 9 n n9 n 1244 1244 14 14 4 5 063 499 31 32 0080 128 0000 0000 0000 0000 0000 0000 0000 0000 0090 144 0000 0000 0000 0000 0000 0000 0000 0000 P aleae gU UR ars ient q a 00A0 160 0000 0000 0000 0000 0000 0000 0000 0000 e e eie 00B0 176 0000 0000 0000 0000 0000 0000 0000 0000 eade ii d a dg 00C0 192 000
45. 4240 C067 480C 424E 7B67 420C 42F3 2767 0000 00 4246 FC67 0000 BEOC 420A 7C67 0000 D40C 42FF COOC 4246 C067 FC80 0024 8F4E 6A25 2A0 004A 6A00 324A 73 5 8A4E 6A35 2 00 AF00 0660 0000 AC34 6 00 04 5 BAS8 AFOO 6A3F 5 00 044 6254 of file Virtual located at track 3 000 SAID 8A30 2F00 0454 AF00 0454 AFOO 0660 6ACS AFOO 0660 SCCS 8A4E 0660 4ECS 8 7781 AFOO 0660 3C34 3781 04 5 8 58 AF00 0660 0285 6 00 04 5 8 58 7781 6200 0600 0200 0624 SFO8 9700 OD4E 9A00 0767 4208 9 00 0800 0424 AF00 0402 104E 6224 6AFF FO4E 0424 AFOO 0408 9200 6224 6AFF FO4E 7308 SF44 D74E F081 E100 2F00 0825 2F00 044 0202 573 FF4E 734A E7FF FAFO 2762 0055 sector 11 004C 1008 0 08 6A28 0429 7861 2831 064E 7248 9ECO 8000 8845 OA4E 7800 61 3 0264 0654 060 BOOC 8A45 0000 42F3 4240 4202 424E 9ECS 2F00 6AFE 0408 3781 0660 AFOO sector 0 0660 8A4E 6AF3 6200 6200 2834 AFOO 043F 732F 0766 525 7324 00 5 2 00 244 6224 3900 8F2F z n VJh K N ic c A Nu H8 N 0 9 N 3 NbS x 2 W NSS_N a 2 4 28 2 47 88 4 10 4 56 2 4 77 B g BNzgH BN gB B _g B g B 9 9 1g B 1q BN rg B BF g 4 1 20 24 0 5 5
46. 44FF 0824 46FF 132C FAF8 83F0 F4DO F900 E032 4067 1008 0060 0100 5820 0466 2 42 1 2 9200 F900 E032 4067 1008 DFOO 8200 02 6AB6 6 00 5842 422 7AFC 8448 1251 E2A9 4 08 8000 100 0086 0460 CCFF 0000 422C 00 2 4933 0167 8874 FF66 4726 CFO AEOO 7F43 3CA2 1CBO 2A00 7F43 044 120 AE00 2C2D 2500 0804 CE60 4420 CCFF FFS8 0000 0367 0 60 4165 ococ A820 E220 0008 4908 8162 0000 0051 A060 7214 0024 1 21 1067 024E 6E00 0000 1008 757 6E00 3065 4300 3E60 8100 OEE4 2008 F020 8876 0866 1020 OBEA 1A67 4701 7AFC 2008 8000 C100 00B6 A060 CCFF 7 4 0026 5 063 499 0041 4000 0652 81 5 66 0366 EEOO OB2F 0800 0001 3061 0000 7 00 8938 0000 7AFC FF4E 4808 80 AE32 0 7 0064 3A48 0000 0367 0 60 4165 ococ AE20 4767 1308 FAFB 2 2 6 00 61FD 0260 163D 0000 0A43 2C65 3ED6 100C BC20 806A 0148 0067 A848 7520 0000 AE32 3162 0026 0652 440C 0067 1020 OSEA 1A67 4701 7AFB 3422 0300 7 of file Virtual sector 31 located at track 2 0300 0866 002D AA20 OOEA 4836 8874 FF66 5 FF66 0828 0024 00 7F43 3CA2 20B0 2B00 8 23 3 08 1308 843 800 0767 0007 224 4 00 2008 32 0167 0051 38 036 0 26 8823 0008 1C21 1067 034 6 00 0000 DFOO C300 0000 FAFA 0C42 024E 9FCC 872C 0852 0000 3162 1E6
47. 53994 4350 47114300323 201 39995 449 18IA 30 401 OL 3102 W3W 4391 W31SAS 91044915 303 3 02 3d3dVN 319345 3994 dv WALYIA 01 SAHd dVW 3M Sheet 4 of 10 5 063 499 Nov 5 1991 U S Patent ss 1d4d39X3 339931 ADLY IAW 51234 3 3NII nD3 1d32x3 221 329841 OS 9914 135 149 Ald 32915 a3sn 021 OL Ald 32915 135 307 211918 NI 419 22915 8 405 40 0119907 1433905 JAYS 11915 5 405 403 ANWA 934 501915 3943 11432 3 135 CNOTLONALSNE 293 33139 dval gt 3 DW 32941 ej 83181934 501915 JWv 8i 11432 3 135 AIVLS 4350 NO 3WVa4 11432 3 JIITVIATad 319342 4 3991 43S GNn SV 3NDZ 843343408 51553229 333 31V33N39 340W dns GANT LNOD 33 M S NI N IIOQSISNI N WWOO 31V10W3 eNOILINALSNI NOWWOD 3403 WALYTA 1393 1IAI3d 043 71199 HILVd 393 1 AI3d yp n ni 06 0123 NOILd39X3 48 OL Q3INIOd SS3MOQv HSNd 88 98 H38WhN N0123A NOILd3OX3 139 5534009 16 Ol Y3LNIOd v8 JAYS M3lNIOd MOVIS SH31SIO3M JO ShiViS 3AvS 3SVd V SNISS3OOMUd ATLN38302 28 HOIVd Q330123 JY 08 Sheet 5 of 10 5 063 499 Nov 5 1991 U S Patent 11432 3 35941 WOd 4 ovi N31 33941 13 34 8
48. 6 whether the user program has independently updated the status register If not the trace bit is reset at step 138 and the routine returns from the exception at step 140 The routine then returns from the trace exception again at step 140 Thus the instruction is allowed to execute in supervisor mode under scrutiny the trace routine is then switched back out of supervisor mode and the processor is allowed to continue with other instructions in user mode However if no trace was expected at step 132 from the instruction emulation the routine branches to step 142 where the routine inquires whether the system is in supervisor mode If so the routine jumps to the original trace vector at step 144 If not the routine branches to step 146 where the trace exception frame is copied from the supervisor stack to the user stack The supervi sor stack exception frame is then changed in step 148 to the return address of the original trace vector followed in step 150 by clearing the supervisor and trace mode bits from the supervisor stack exception frame Once this is complete the routine returns from the exception to the original trace vector at step 152 20 25 30 35 40 45 55 65 12 Line 1010 Vector Patch Many operating systems for 68X X X based machines such as the Macintosh use line 1010 traps or traps to handle system calls Generally the application desir ing to execute such a system call will set
49. 99 41 42 00A0 160 5020 5048 6800 0648 6 00 044 B940 8012 P PHh Ho N 8 0080 176 984E B940 8018 A42F 0A48 6 00 04 8 F650 N Ho P 00 0 192 8F3F 03A9 9 51 C760 603F 03A9 9A43 ota Quo Sou 0000 208 4 76 014 B940 8012 0656 766 4 2 3 01 Jv N 8 V fL lt 00E0 224 5602 0042 A73F 3 00 4048 6 08 0045 EEFE lt 00F0 240 024A 6A00 046A 0424 5224 522 3 01 5602 1 7 SRSR V 0100 256 0042 A748 6A00 0648 6 00 044 B940 8012 B Hj Ho N 8 0110 272 9848 6F00 082F 0 48 6 00 1648 6 00 0 42 0120 288 6742 7 8 ECDE FCOO 164A 0767 064E B940 J g N 8 0130 304 8018 A470 284E 8940 8011 0804 B800 0004 jee P N eoe 0140 320 0001 0C43 EEOO 2A4E B940 8012 0467 0 06 EEEE I 0150 336 B800 0004 0001 0 60 204 9170 F64E B940 Sse ovate N p N 8 0160 352 8011 0843 00 3A4E B940 8012 0466 OA4E f 2 C N 8 N 0170 368 9170 F54E B940 8011 D843 F80A 0876 8 0180 384 940 8012 0666 164 9148 780 8020 7 00 1 0190 400 7 42 5E30 SDA2 474C DFO1 014E F940 B 0 GL N 8 01 0 416 8010 3822 7900 7F43 0822 1908 0100 0066 f 01B0 432 F859 8920 7 00 7F3F 7C22 1002 41FC 0022 01C0 448 8123 C900 7 43 0020 7600 7242 SE30 3 0 lt 010 464 SDA2 4720 7 00 7 48 DO4E 9061 0000 CE30 G 0 01E0 480 3CAO 02A1 4623 C800 7F43 8020 7 00 7F4D
50. BO 6F00 88 0 1EOC 8000 0100 DFSF 081 AEOO 0A2D 96 5 0100 DF4E 6 00 4 50 0022 5 54 00 5706 802 20 404E 104A D44A 1167 0084 BC61 OAFO 9FCC 0000 0000 0000 4608 0000 6008 109F 4000 0064 0767 FF4E E100 2840 4F00 D167 02F0 7530 4808 00 6 00 8822 1420 004 6141 4900 732F 9167 9166 DA26 8300 1E20 0024 5 10 0000 0000 0048 0100 4264 0100 57 0 0566 2005 10 0 7354 0824 700 4046 0660 0024 1 0 00 5620 5032 C822 8 54 7340 00 504 AFOO 062C 0628 4026 4200 1208 0042 0000 0000 EVEF 0867 0820 0 66 0062 2 20 00 1020 8FFO 1240 7CO6 DF60 0685 0020 6 00 0800 2 00 OFS1 2022 8FFO FAFE 1E23 7523 0481 9142 4961 1302 0976 0000 2 00 Virtual sector 30 located at track 2 0002 0300 0006 9FCC 5A1D 2 00 144E 7508 0200 0967 7600 E708 6AF8 7269 6314 0000 6F6E 7200 0000 0000 0000 0000 OOFF 0000 0000 0000 0000 0000 0000 sector 0000 0000 FAFO 0620 6F00 0808 0048 08 0 7700 0954 1 60 0008 0000 0166 4A00 5463 0220 4490 C8FF CF22 1F60 0E22 48FF DFOO 512E 9160 0000 43F8 000 0966 144 sector 6 4200 26 8 1 f N3J3 J3 1 JR OSRNuSCopyri ght 1988 Connect ix Corporation Written by Jon athan F Garber 0 e 9 9 9 a 9 o a n yes Rima 2 y vl Ha b U 2 F g
51. BR and the reset instruction are also defined as common even though they are infrequent cannot readily be traced or must provide different response in the emulated envi ronment For example emulation of the stop instruction involves executing a very tight loop to give the appear ance of a system halt and cannot readily be performed under the supervision of the TRACE mode In the event the call which led to the privilege viola tion is not a common instruction the process branches to step 110 where memory reference accesses are generated in a buffer zone around the user stack pointer The creation of such a buffer zone ensures that the memory around the user stack pointer is not cur 5 063 499 11 rently paged out by causing a page fault if the zone is swapped out If such a page fault occurs the page will be reloaded so that as long as the stack pointer points to any location in the buffer zone the corresponding page should be resident Following step 110 a dummy privilege exception frame is created on the user stack at step 112 followed further at step 114 by setting the exception frame status register value to trap after each instruction Such trap ping may also be referred to as trace and may be thought of as step by step supervision of the execution Next at step 116 the exception frame status register value is set for supervisor status This is followed by saving at step 118 the current location of the super
52. C32D 4900 704 irs 8 1 I pL 0160 352 DESF FF61 OOFF 7048 E7FF FA70 01 E803 D 8 pH p 0170 368 8200 2C4D FAF4 0649 FAFA 9A20 2800 24D1 Da M l1 29 0180 384 A800 2 20 3AF4 6221 4000 2426 3AF4 SE21 2 i b 8 96 0190 400 4300 2000 8306 8300 0001 FFO2 43F8 0022 C arua Canni 01A0 416 4322 1 57 812 14 0 1190 702 08 0005 01 0 432 FCOO 7700 0080 8965 OC4A 6 00 3C66 0602 w e Jo lt f 01C0 448 6AFC FFOO 02F0 8800 4C26 7414 0426 1348 L t amp H 0100 464 C041 1 A661 00 8 C824 1202 43F8 01 0 480 0002 8200 0007 0084 8300 4200 1961 OOF6 B a 01F0 496 1808 C200 0820 1208 0000 0066 OOF6 040 es eats f 33 This is sector 000 11 It is absolute Tags 0000 000 0010 016 0020 032 0030 048 0040 064 0050 080 0060 096 0070 112 0080 128 0090 144 00 0 160 00B0 176 00C0 192 0000 208 00 0 224 00F0 240 0100 256 0110 272 0120 288 0130 304 0140 320 0150 336 0160 352 0170 368 0180 384 0190 400 01 0 416 0180 432 01C0 448 01D0 464 01 0 480 01 0 496 0000 0200 DF03 B400 8700 9F52 4103 00 7AF3 81 803 7F00 7508 6A25 2800 1A4E 140C AF00 4240 4246 FAF2 B60C SF67 C167 7 67 7267 8 45 0825 00 5 0200 6200 0000 This is sector It is absolute Tags 0000 000 0010 016 0020 032 0030 048 0040 064
53. EFE FSA8 6E48 0110 272 6EFF 00A8 7448 6EFF 04A8 6F30 3809 2CE3 n tHn 008 0120 288 580 4010 21 0 7809 2 67 180C B850 6175 X 08 x g Pau 0130 304 6 7867 0831 FCOO 0809 2C60 0631 F80A il xg 1 i 0140 320 7 09 2C41 EEFF 0430 2800 0 04 4000 2848 0 H 0150 336 4030 3809 2C2D 40FF F82D 40FF FCO6 6E00 008 0160 352 20FF 06 6 00 20FF FC26 6 00 OA61 3630 22 amp n a60 0170 368 3809 2C32 2E00 086A 0432 3COO 2800 4131 8 2 3 2 Al 0180 384 C009 2CE3 580A 4010 2131 C009 2E48 6EFF X 8 1 Hn 0190 400 04A8 702 2EFF 00 8 734 DF38 FC4E SE20 SL 8 N 01 0 416 5 5 8F4E 0049 EEFF DC28 8 06 9400 0000 Tu 01B0 432 8039 7 00 0400 0442 00 0629 7 00 2000 91 01C0 448 2000 OA2F 0 45 EEFF 0448 6 00 0248 7 00 DO 2 E Hj Hz 0100 464 2C48 GEFF F83F 3 00 0342 7 8 ECO4 9400 Hn 2 B H 01 0 480 0000 802F 0C48 6 00 0248 7 00 1048 GEFF 2 1 2 01F0 496 F83F 3 00 0142 7 8 EC4E 7500 0000 0000 2 lt 5 063 499 43 0013 19 of file Virtual sector 43 located at track 3 sector 7 44 This is sector It is absolute Logical End Of File is after position 017F 383 in this sector Tags 0000 0002 8300 0013 SFCC 6431 0000 000 2000 2000 0000 9 302 3930 2056 6972 2 20 90 Vir 0010 016 7475 616C 2040 6560 6 72 792
54. I S3A 283151934 SNLYLS JHL GNA 03190411 19031SNI 032941 b SVH 13 NO 300W 82350 331N333 01 34943 2991 13539 SIA eNOTIVINWA ISNI WOS4 33941 5 ONII23dX3 cel 5194 32 1 JULIJA ONIGQV3 339231 2 9190 01 14d2X3 NIS JWVsd 1430 32915 5 WD33 5119 30 DN 399231 3 MgnS 493715 061 40193 39931 9190 30 449 Nia DL 4 1d39X3 2915 Y dNS 9 2 2918 33Sf OL 4 4 WOXI orl SWWS4 1d329X3 39931 AdOI YOLIBA 30val 918 dWnr G Sheet 6 of 10 5 063 499 Nov 5 1991 U S Patent 261 1 1439 3 0 1 wOd4 1 33 061 961 11 26 303 9913 135 300W 119 v2 55240449 3D0123A 9403 9913 135 891 0101 3NI 9ISO A JWV i 1432 3 1N332n2 JU 049 32v 1gd33 39995 55340449 qvn131A 03 31991 3994 3333 5119 26 119 5539044 40 3148 901 340934 AWWd 135 9 OL AWWd 135 4991 ASSN Ul ADVIS 881 vel 4 wOa4 1d32X3 3391S AdOI id 1S03 S3A ON 1 0 2 4049 30123 dval 981 0101 3NI1 9120 N3HM JNS NI 91 300W 30343 ON 031830033 NI Nan 32 SJA 19 9 I 281 9 ld id 4 ANSI spon AWW 32 081 Sheet 7 of 10 5 063 499 Nov 5 1991 U S Patent Nant aa SNLVLS AWWd 9 2 vt 543151935 3 401534
55. O 14A2 2800 3078 5 00 1842 08A2 6066 7 00 0300 6800 1800 0866 1 21 Virtual 10 AE21 7 00 00 2900 4500 1 4 2900 0822 4000 1642 TEF8 0000 0000 2448 953F 3 00 1420 3C00 1 4 8891 3 05 BF22 0000 0010 0820 054 2004 4400 8100 0008 0000 0008 C106 8100 0804 0020 0002 0006 8000 0100 0800 0020 O8FF FES1 0800 0008 7600 0800 C8FF F620 0000 0000 st 0000 0000 Sas ITE 0000 0000 woe NT d 0000 SG bist d aee 0000 C ecu ib ss 2 0000 0000 DE PEERS 0000 EP RERO E 0000 0000 E 0000 P A P CE S eee 0000 0000 S iva 0000 EHE 0000 E A s 0000 RIS 0000 OTT 02 NV 2A41 5 0766 f 0038 2 6 0 8 800 8 1x 2 B 0006 C qllopev f 1B42 SB He See 2 22 7000 sector 3 8000 263 Ez 1 amp 0360 D P E L 6900 FERIEN 800 0 H28 18 B 2031 28 7 00 2 Hz 02A8 2 2 lt 2 lt 2 lt 0001 2 2 g lt 5041 0851 5 262062750 0024 7000 IB Q 8 Ll 2272 HON 8 8 D r 0051 EA u S Q 0053 Pe
56. United States Patent Garber 5 063 499 Nov 5 1991 Patent Number Date of Patent 11 45 54 METHOD FOR CREATING VIRTUAL MEMORY SYSTEM BY REDIRECTING ACCESS FOR USER STACK INSTEAD OF SUPERVISOR STACK DURING NORMAL SUPERVISOR MODE PROCESSING 75 Inventor Jonathan F Garber Oakland Calif 73 Assignee Connectix Inc Menlo Park Calif 21 Appl No 294 831 22 Filed Jan 9 1989 511 Int CL T Ua n uu G06F 12 02 52 US Cl seen 395 500 364 244 3 364 246 11 364 254 8 364 261 364 DIG 1 58 Field of Search 364 200 MS File 900 MS File 56 References Cited U S PATENT DOCUMENTS 3 815 103 6 1974 Holtey et al 364 200 4 493 035 1 1985 MacGregor et al 364 200 4 519 032 5 1985 Mendell 364 200 4 528 624 7 1985 Kamionka et al 364 200 4 542 458 9 1985 Kitajima et al 364 200 4 592 011 5 1986 Mantellina et al 364 200 4 617 624 10 1986 Goodman 364 200 4 669 043 5 1987 Kaplinsky 364 200 4 714 993 12 1987 Livingston et al 364 200 4 825 358 4 1989 Letwin 364 200 4 849 878 7 1989 ROY 364 200 4 868 738 9 1989 Kish et al 364 200 OTHER PUBLICATIONS Editorial 89 Won t be Apple s Year of Multitask ing MacWeek Jan 3 1989 p 22 Virtual Memory Ends RAM Jam MacWeek Jan 10 1989 p 1 Latest Virtual
57. al memory space These and other objects of the present invention will be more apparent from the following Detailed Descrip tion of the Invention taken in conjunction with the FIGS described below THE FIGURES FIG 1 is a simplified view of a prior art approach to virtual memory FIG 16 is a prior art view in block diagram form of the memory arrangement of a Macintosh computer running the Macintosh operating system FIG Ic is a prior art view of a computer system such as the Apple Macintosh II having a 68020 microproces sor a 68851 MMU and memory FIG 2a is a flow diagram showing the installation of the process of the present invention upon initialization of a suitably configured Apple Macintosh computer system FIG 26 is a block diagram view of the memory rangement of a Macintosh computer running the pres ent invention with the Macintosh operating system FIG 3 is a flow diagram showing the process of the present invention by which exception vectors may be re routed FIG 4 is a flow diagram of the process of the present invention directed to emulating execution of privileged instructions FIG 5 is a flow diagram of the process of the present invention which permits certain privileged instructions to run in supervisor mode under close scutiny or super vision FIG 6 is a flow diagram of the process of the present invention directed to handling unimplemented instruc tion traps referred to as line 101
58. arent to the user of Apple Macintosh computers having 680X0 processors running under the Macintosh operating system It is a further object of the present invention to pro vide a virtual memory system capable of modifying the Apple Macintosh operating system to require user pro grams to operate with the 680X0 microprocessor in user mode as opposed to supervisor mode It is another object of the present invention to pro vide a process layered between the hardware and the operating system of the Macintosh computer which permits operation of a hard disk to provide virtual mem ory Another object of the present invention is to provide a method of warm booting a Macintosh computer run ning the Macintosh operating system which prevents resetting of a memory management unit and permits operation of a virtual memory algorithm It is yet another object of the present invention to provide a method for ensuring that no page fault occurs during time critical operations Still another object of the present invention is to provide a method partitioning I O operations into blocks small enough to be processed in the amount of available physical memory A still further object of the present invention is to provide a method for performing an initialization which permits a virtual memory system to be automatically installed in an Apple Macintosh computer which per mits slot devices and drivers to install in apparently normal fashion but within the virtu
59. ated at track 2 sector 1 601E 0000 0000 0000 00C0 0000 31DC 0000 RI ENTM 0000 0000 0000 0000 1004 qc OE 127C S aree ei es 0070 112 31DC 0080 128 0 03 0090 144 00 0 00 0 160 00 0 00 0 176 0000 00 0 192 0080 0000 208 01 0 00 0 224 FFFF 00 0 240 FFFF 0100 256 FFFF 0110 272 01 0 0120 288 0180 0130 304 0000 0140 320 0000 0150 336 00 0 0160 352 0000 0170 368 310 0180 384 0 03 0190 400 FFFF 01A0 416 01 0 01B0 432 0000 01C0 448 0000 01D0 464 00 0 01 0 480 FFFF 01F0 496 FFFF This is sector It is absolute Tags 0000 0000 000 FFFF 0010 016 FFFF 0020 032 01 0 0030 048 0000 0040 064 736 0050 080 9 55 0060 096 0800 0070 112 6972 0080 128 7465 0090 144 6D6F 00A0 160 6173 0080 176 6F66 00C0 192 6265 00D0 208 6E6E 00E0 224 706F 00F0 240 6D6F 0100 256 7400 0110 272 616D 0120 288 0308 0130 304 6C6C 0140 320 7567 0150 336 6F6C 0160 352 2063 0170 368 6372 0180 384 7079 0190 400 6E65 01 0 416 6F6E 0180 432 204A 01C0 448 6265 21 1 7 1A66 9004 0000 0000 00 0 0000 0000 0080 0000 0808 0180 E000 01 0 F007 FFFF FFFF FFFF F007 FFFF 0007 01 0 1010 0080 0100 0001 0000 0000 0000 00 0 1004 0000 127 310
60. boot The restart or re boot is limited and is prohib ited from incorrectly updating the values of the address at the top of memory the buffer pointer address or any part of the PMMU configuration registers Since the virtual memory space and the critical memory settings are already defined following the reboot the operating system runs in the virtual memory space set up by the first pass of the present invention and runs under the present invention The operating system then restarts the virtual memory process of the present invention which detects that it has already initialized once since power up and that the virtual memory space is avail able The remainder of the installation can then be com pleted as discussed below This stutter start technique starting once normally and then performing a con trolled restart of the operating system under the virtual memory process has been found to assist in providing a substantially transparent implementation of a virtual memory system on an Apple Macintosh II or similar computer Assuming the software implementing the present invention has not already been initialized the process inquires at step 18 whether the virtual memory software has ever not just on this pass been installed on this machine before If not a virtual address space is allo cated from the disk at step 20 In a preferred embodi ment the disk space allocated at step 20 is contiguous although it is not necessary
61. both the operating system and the process of the present invention it would be possible to identify in advance such critical pages and mark them as immune to page swaps The routine shown in FIG 10 has been optimized for aftermarket use in the Apple Macintosh environment in part because it does not need advance identification of the critical pages More specifically the page selection routine of FIG 10 relies primarily on three factors a history table which is based on usage in the preferred embodiment but may be based on any of a wide variety of criteria a don t swap this page flag and a page modified flag The history table see FIG 25 concept tracks for example how recently and frequently a page has been accessed The don t swap flag discussed further be low protects certain key pages of physical RAM from ever being swapped to disk and is designed to protect critical information such as the virtual memory code and some sections of the device manager disk driver system traps and trap patches The page modified flag determines whether a page has been modified since retrieved from disk One reason for determining whether a page has been modified since retrieved from disk relates to the reasons for allocating in the preferred embodiment a disk file which is larger than the total amount of memory re quired to supplement the existing physical memory to the total amount of virtual memory Thus for example for a
62. current Macintosh II which is capable of address ing a maximum of eight megabytes under the current 5 063 499 15 release of the Macintosh operating system the disk file may also eight megabytes although either larger or somewhat smaller sizes would also work This effec tively permits a disk image of each page to be main tained in physical memory It will be apparent to those skilled in the art given the foregoing discussion and the fact that a disk image can always be maintained for unmodified pages in physical memory that where possible an unmodified page might generally be se lected for swapping out since this eliminates the need for a disk write and correspondingly increases perfor mance By weighing these factors as discussed below in connection with FIG 10 a reasonably optimized candi date for replacement is identified In general the page selection routine shown in FIG 10 is a winnowing out process by which the system itself determines on a long term iterative basis what the critical page set is likely to be and errs generally on the side of including non critical pages to avoid swapping out critical pages The first basic assumption is that all pages critical to performing a page swap are used dur ing each complete page swap where a complete page swap includes both a read and a write By basing selec tion of a page to be swapped out initially on page usage history and not swapping out any page u
63. de 5 0008 0604 0 61 vi 8000 004C sg E ey uy uu s L 4020 S s eee acie C8FF mee Q E900 Sea zB Qu v 0070 taqe M o PE EEES 0604 X Q 0190 400 01A0 416 01B0 432 01C0 448 0100 464 01 0 480 01 0 496 8000 0002 900 0876 8022 0 08 935 This is sector It is absolute Tags 0000 000 0010 016 0020 032 0030 048 0040 064 0050 080 0060 096 0070 112 0080 128 0090 144 00A0 160 0080 176 00C0 192 0000 208 00E0 224 00F0 240 0100 2565 0110 272 0120 288 0130 304 0140 320 0150 336 0160 352 0170 368 01807384 0190 400 01A0 416 01B0 432 01 0 448 0100 464 01 0 480 01 0 496 0000 900 3 00 4008 00 7CO0 004E 380D 2041 7000 0031 FCOO B801 0 46 020 940 7800 50 2 940 224 BOOE 8007 4C53 8002 B940 9E4E 00A0 0001 0011 4 53 801 0100 00 This 4 sector It is absolute Tags 0000 000 0010 016 0020 032 0030 048 0040 064 0050 080 0060 096 0070 112 0080 128 0090 144 0000 EEFC B011 6800 D841 954A F940 047E 6E00 67A9 062F 39 0100 0006 0 00 FF78 7 00 0100 8312 0010 0090 8000 0258 2020 0800 0 66 0051 16 sector 40 0002 0500 7 80 900 7 43 7F42 902C A641 F80C 8000 C40D 7F42 204 27 0011 8004 BC4E 474 8002 B940 3246 E620 430 302 8060 940 5720 1440 7 00
64. eged mode 11 A method of utilizing physical memory and pe ripheral storage in a computer system running under an operating system wherein the computer system in cludes a suitable microprocessor capable of coacting with memory management logic either internal or ex ternal to the microprocessor and an amount of physical memory and wherein the computer system is capable of operating in both user and supervisor modes as virtual memory comprising the steps of allocating a portion of the peripheral storage as a virtual memory file determining the amount of the physical memory resi dent in the computer system setting the memory management logic to address at least part of the physical memory and at least part of the virtual memory file as virtual memory space whereby there is a first portion of the virtual mem ory space in the physical memory and a second portion of the virtual memory space in the periph eral storage establishing a supervisor stack in the physical mem reconfiguring the computer system to continue pro cessing normally performed in supervisor mode in the user mode including establishing at least one user stack in the virtual memory space in response to an attempt by the operating system to establish a stack and forcing the operating system or at least one currently executing application program to use the at least one user stack instead of the supervisor stack as if the operating system or the at leas
65. emented which breaks write operations from the virtual memory space to a conventional disk file into small enough operations to be processed with the amount of available physical memory The WRITE PATCH is essentially identical to the READ PATCH except that steps 354 356 392 and 394 may be deleted A similar technique can be used for any critical operation which cannot tolerate the occurrence of a page fault during the operation Attached hereto as Appendix A is a printout in ob ject code form of the code necessary to implement the present invention on an Apple Macintosh II operating This 15 sector 0000 0000 0000 096D 1081 0820 4954 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4D45 2049 0000 3FFC 000E 31F8 OFE6 B801 1FF8 0000 0000 3E3C FFFF FFFF FFFF 0002 0100 9C37 0801 5669 5640 494 0000 9 94 0004 0004 0000 0000 0000 0000 0000 0000 0007 4000 434 0000 0000 0007 380C 3806 D007 0000 0000 0000 0000 D007 FB80F F807 0300 0000 0000 0447 7274 4540 4954 0000 A9E6 E400 0000 26A5 0400 6172 7561 2000 5640 0000 0000 0000 0139 0000 0000 0000 0000 0000 0000 4954 0146 0000 0000 0001 7006 380C 3806 FOOL 0000 0000 0000 0001 F007 FOF F807 6432 25A5 1000 4143 0200 0040 2000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4600 8000 0000 8007 300E 380 B007 8000 0000 0000 0000 8007 FOOF F80F F007
66. erein critical information includes at least the location of the supervisor stack 4 The method of claim 3 further including the steps of switching to supervisor mode to perform the infor mation swapping step 5 The method of claim 1 further including the step of organizing the virtual memory space into pages and wherein the predetermined criteria includes consider ation of page usage history 6 The method of claim 2 further including the step of causing the macintosh operating system to recognize the entire virtual memory space as available physical memory by rebotting the Apple Macintosh computer after allocating the virtual memory file and setting the memory management logic without resetting the mem ory management logic or critical memory configuration values 7 The invention of claim 1 further including the step of retaining the supervisor stack in a known location in the physical memory 8 The invention of claim 6 wherein oen of the critical memory configuration values is the value of MEM TOP 9 The invention of claim 6 wherein one of the critical memory configuration values is the initial value of BUFPTR 10 A method of installing virtual memory compris ing a combination of physical memory and peripheral storage in an Apple Macintosh computer capable of operating in privileged and protected modes running under an Apple Macintosh operating system wherein the Apple Macintosh computer includes a suitable mi croprocess
67. ers is a supervisor mode stack zone Finally at the top of memory is a zone referred to as static memory where application programs can reserve a specific portion of memory to store needed informa tion and the information in those addresses generally cannot be moved by other programs until the system is rebooted Since most if not all virtual memory systems save the state of thprocessor to a stack permitting the user program to alter the location of the supervisor stack while at the same time trying to run virtual memory may mean that the supervisor stack is moved by the user program in supervisor mode to a location which the virtual memory system already has swapped out to disk When an attempt is later made to save the proces sor state on the stack the state of the processor is effec tively lost resulting in a fatal error Thus while the Macintosh operating system has many attractive features including a popular graphics capability and user friendly interface the limitations of the Apple Macintosh operating system have posed sig nificant problems for users desiring more memory and the associated performance improvements Thus there has been a significant need for a virtual memory system which is transparent to the normal user of the Apple Macintosh operating system with Apple Macintosh computers using the 680 0 processor SUMMARY OF THE INvENTION The present invention overcomes the limitations of the prior art by impleme
68. eturns at step 192 On the other hand if the inquiry at step 186 deter mines 32 bit mode is not requested the PMMU is set at step 194 to ignore the top byte or top 8 bits of the 32 bit address and the corresponding flag is set at step 196 Again the routine returns at step 192 5 063 499 13 Bus Error Vector When a memory location is called for but is not immediately available for referencing a bus error is generated In such an instance it is necessary to deter mine whether the location is unavailable because it has been paged out to disk this can be accomplished by the routine shown in FIG 8 The bus error vector is called at step 200 and begins at step 202 by saving the state of the registers and the PMMU followed by determining the address and the cause of the bus error at step 204 If as determined at step 206 the bus error is not due to a page fault the registers and PMMU setting are restored at step 208 and the routine jumps to the origi nal bus error address vector at step 210 However where the inquiry at step 206 determines that a page fault has occurred the routine inquires at step 212 whether a page fault was already being corrected that is the process of swapping information in from disk was already in progress when this page fault occurred If it was it will simplify operations to finish correcting the first page fault before dealing with the second This is accomplished in step 214 by saving at a d
69. he Operating system zone is the application zone followed by a user stack zone The user stack zone of FIG 25 corresponds gen erally to the stack zone shown in FIG 18 since user programs under the present invention are permitted only to modify the user stack zone Those of ordinary skill in the art will appreciate that some programs for the Apple Macintosh such as MultiFinder create a plurality of application zones and user stack Zones within what has been referred to here as a single user stack zone and application zone Above the user stack zone is static memory but static memory now includes a zone for conventional static memory together with specific portions of static memory assigned to perform particular virtual memory functions Those functions include a supervisor stack zone a vector base table pointed to by the vector base register or VBR history tables code for the virtual memory process of the pres ent invention and zones for the SWAP MMU process translation tables and transient page storage all as dis cussed hereinafter The installation of the supervisor stack zone into static memory permits the supervisor stack zone to always be in a known location The super visor stack zone which is typically a few thousand bytes for example 8K bytes but could range to on the order of 32K bytes located in physical memory al though its logical address is very near to the top of memory Those skilled in the art will appreciate
70. her the proper hardware a 68020 processor with a PMMU 68030 or other processor offering compara ble functionality and software the Macintosh operat ing system or comparable is present If the proper hardware software environment is not present or upon user request initialization is bypassed at step 14 typi 20 25 30 35 40 45 55 60 65 6 cally without halting the system The user may bypass installation by for example holding down the escape key during boot If the proper environment does exist the initialization continues at step 16 by determining whether the soft ware of the present invention has already been initial ized once since power was turned on This step is signif icant in the operation of the process of the present in vention Because the operating system loads into mem ory first at power up the virtual memory process of the present invention initially runs under the operating system By appropriate selection of the program name such as by using a space as the initial character in the name the process of the present invention will attempt to initialize or install immediately following boot by the operating system and prior to allowing other pro grams to initialize The software of the present invention installs itself by defining the virtual memory space and setting the PMMU and then as will be discussed in greater detail hereinafter restarts the operating system by a warm re
71. ifferent loca tion a copy of the stack from where the new page fault occurred to the current stack pointer Next at step 216 the registers are restored to their state prior to the oc currence of the second page fault that is their status during the handling of the first page fault which was saved at step 82 shown in FIG 3 Then at step 218 set the return address of the original page fault to resume execution at the double fault restoration routine shown in FIG 9 The routine then preferably switches to a very high level of priority so it will not again be inter rupted by the process which caused the second page fault and returns at step 220 to finish handling the first page fault If as should usually be the case there was no prior page fault being handled when the inquiry was made at step 212 the routine continues by selecting at step 222 a page not likely to be needed soon While various algo rithms exist for making this selection one acceptable algorithm is shown in FIG 10 which uses page usage history or aging tables That page is then mapped out as non resident still at step 222 At step 224 a determina tion is made as to whether the page has been modified since the last time it was written out to disk If it has the page is written to disk at step 226 and a flag is set that the page now has a disk image An inquiry is made at step 228 as to whether the faulted page has a disk image If it does the disk image of
72. in all instances that the disk space be contiguous In addition with the present re lease of the Macintosh operating system only eight megabytes of RAM can be recognized by the operating system and thus only eight megabytes are allocated at step 20 However it is anticipated that such limitations will be removed from the operating system in which case step 20 may be readily modified to include selec tion of the amount of virtual memory space desired which can then exceed eight megabytes In addition for performance reasons discussed below the amount of disk space allocated is presently more than just the amount required to supplement the physical memory to eight megabytes so that a copy of all data stored in physical RAM can also be maintained on disk This increases performance by among other things avoiding the need to write to disk when swapping out unused pages Whether the allocation of disk space was successful is determined at step 22 If the allocation was not success 5 063 499 7 ful installation is bypassed at step 24 However in most cases where sufficient free hard disk space exists the allocation will be successful At this point the disk space is allocated which was the purpose of the installa tion inquiry at step 18 and so the two paths converge Of course even if the virtual memory system of the present invention has been installed on this machine before if the previously allocated space has been cor
73. isk based or peripheral por tions of the virtual memory space The tables are then initialized to recognize the existing amount of physical RAM starting at address 0 followed by the allocated amount of disk based virtual memory starting with the next address following the physical RAM Such disk based virtual memory is alternatively referred to herein as non resident or paged out memory Following creation of the page translation tables a portion for example half or other suitable portion of physical memory is typically remapped at step 32 to the top of the virtual address space A logical zone for the Startup system stack is then created by remapping a suitable number of pages for example on the order of four 2K byte pages mapped at the very top of the virtual address space although the exact number of pages can be increased substantially to avoid any possible over flow to a zone at the halfway point between logical address and the top of virtual memory This complies with the manner in which the START MANAGER routine of the Macintosh OS operating system estab lishes the beginning location of the startup system stack Numerous alternative approaches can be implemented for mapping and locating a startup system stack as long as the logical address space which will hold the startup system stack is mapped to a location in physical mem ory even though that location may change and may be unknown The example described ab
74. located during the first pass initialization which pre vents the user from throwing the virtual memory file away during normal operation Then during step 50 the read and write trap calls are redirected to the custom routines described hereinafter At step 52 a new exception vector table is created in Static memory and marked as protected or immune from page swaps and then initialized with all vectors in the table pointing to Re Vectoring routine Next at step 54 the Bus Error Privilege Trace and Line 1010 vec tors are patched to the routines in the new exception vector table The Vector Base Register VBR is then pointed to the newly created vector table at step 56 and the user stack pointer is set to that stack s current value in step 58 In step 60 the supervisor stack pointer is set to a buffer protected from memory swaps to disk Fi nally at steps 62 and 64 the icon showing the loading of virtual memory is displayed and the processor is 5 063 499 9 switched to user mode from supervisor mode The Sys tem returns at step 66 ready to begin processing of user programs Once the code of the present invention has been in stalled the logical architecture of memory is substan tially as shown in FIG 25 The arrangement of FIG 2b which can be contrasted with the arrangement of con ventional Apple Macintosh memory in FIG 15 contin ues to show the operating system installed in memory beginning at address 0 Above t
75. locks to be read in this request In some cases there will be more blocks to read in which case the routine will branch to step 406 where a second inquiry is made as to whether the maxi mum number of temporarily lockable pages has already been locked In a good percentage of cases the answer will be no in which case the routine will loop back to step 386 through step 408 where the next block to be read from disk is examined In some cases however the maximum number of temporarily locked pages again will have been met so that a reduced size read is again required at step 410 In this case the size of the read is reduced to the amount of validated memory and then a read is performed at step 412 after which the routine loops back to step 382 Eventually the looping will return to step 404 and no more blocks will be requested At this point the routine branches to perform the final read at step 414 followed by unlocking the pages of the second list of temporarily locked pages at step 416 Next the parame ter block pointed to by the original read request is re stored to the same state as if it had been completed in one pass at step 418 and the status register is restored from the stack in step 420 The routine then returns control to the system at step 422 It can be appreciated that in this manner large size reads can be accom plished Although not shown in a similar fashion a 5 063 499 19 write patch routine may be impl
76. m parable device With all but the 68030 processor such MMU functions can be provided by adding a 68851 PMMU chip With the exception of the installation and page swap routines each of these routines may generally be re ferred to as a patch which fixes a problem the Macin tosh operating system trying to run a virtual memory algorithm would otherwise have The routines which comprise the process of the present invention can gen erally be referred to as the INITIALIZATION ROU TINE FIG 22 the RE VECTORING PATCH FIG 3 the PRIVILEGE VIOLATION PATCH FIG 4 the TRACE PATCH FIG 5 the LINE 1010 VECTOR PATCH FIG 6 the SWAP MMU MODE PATCH FIG 7 the BUS ERROR VEC TOR FIGS 8 and 9 the PAGE SELECTION ROU TINE FIG 10 the READ PATCH FIGS 11a 225 and the WRITE PATCH which is substantially identi cal to the READ PATCH INITIALIZATION ROUTINE The INITIALIZATION ROUTINE indicated gen erally at 10 is called at system startup by the Macintosh operating system More specifically the program by which the process of the present invention is imple mented is copied into the system folder or system di rectory of the suitably configured Apple Macintosh computer Then on the next boot of the system the program of the present invention is started by the sys tem in the normal course of booting as shown at step 10 The INITIALIZATION ROUTINE of the present invention thereupon checks at step 20 to determine whet
77. m the exception is made execution will con tinue with the appropriate information supplied to the appropriate stack at step 170 Sawp MMU Patch Under the current Maointosh operating system there are two common modes of addressing In twenty four bit mode only the least significant 24 bits are ordinarily recognized However in some cases with the current operating system all 32 bits are used presumably this trend will continue with future releases of the operating system such that eventually ail 32 bits will normally be used When all 32 bits are used it is necessary to alert the PMMU to fully decode the address but to still point to the page translation tables set up by the virtual mem ory routines of the present invention It is also necessary to be able to transfer back to 24 bit mode This toggling can be accomplished by the routine shown in FIG 7 which begins at step 180 by a call to the Set MMU Mode routine The routine begins at step 182 by deter mining whether the system is already in the requested mode If it is the routine returns at step 184 However if not the routine inquires at step 186 whether 32 bit mode has been requested If it has the PMMU shown in FIG 1c is set at step 188 to decode all 32 bits but still uses the page translation tables to decode the physical address for any location in the virtual address space A flag is then set at step 190 to indicate the current state is 32 bit mode and the routine r
78. nce the page has been temporarily locked a determination is made at step 362 as to whether additional blocks of data are to be read in If they are not the routine branches to step 364 where the requested read is performed follow ing by unlocking the temporarily locked pages at step 366 restoring the status register from the stack at step 368 and finally returning at step 370 In many such cases however additional blocks of data will be called for in which case the routine will branch from step 362 to step 372 At step 372 a determi nation is made whether the maximum number of tempo rarily lockable pages have already been locked In most 5 20 25 35 40 45 50 60 65 18 cases the answer will be no and the routine will loop by examining the next block to be read from disk at step 374 and then re entering the routine at step 350 In some oases however the maximum number of pages will have been locked as determined at step 372 In such event it is necessary to break the read into a plurality of smaller reads To accomplish this the rou tine will branch to step 376 where the size of the origi nal read request will be stored Then at step 378 the read request is reduced to match the maximum number of allowable locked pages followed at step by a read of that reduced size After completion of the reduced read another read is set up at step 382 extending from the end of the last block actually read to
79. nting a page swapping virtual memory algorithm for the Apple MacIntosh series of computers having add on or internal MMU functions and suitable disk space The disk space although typi cally a magnetic media hard disk also can be provided by a floppy disk tape drive optical disk or other suit able form of storage media Stated simplistically the present invention fools the Apple Macintosh operating system into believing that the system and all applications running under the sys tem are operating in supervisor mode In fact however the system and the applications are operating at most times in user mode In this manner the stack address can be carefully controlled and located where it will not be swapped out by the virtual memory algorithm In 5 063 499 3 this manner page swaps to the virtual address space can be readily performed for less critical information More specifically the present invention interposes a software layer of virtual memory code between hard ware and the operating system The present invention therefore runs above the operating system and user programs The process of the present invention then recognizes when the processor tries to execute an in struction not available in the unprivileged user mode and performs a software emulation of that instruction The emulation may either be a specially written emula tor such as might be desirable for certain common instructions or execution of the instruction
80. or capable of coacting with memory man agement logic either internal or external to the micro processor and an amount of physical memory compris ing the steps of allocating a portion of the peripheral storage as a block setting the memory management logic to address at least a portion of the physical memry and at least a portion of the block of the peripheral storage as virtual memory space reconfiguring the Macintosh operating system with out further resetting the memory management logic to cause the Macintosh operating system to recognize the virtual memory space as available physical memory nd to cause the Apple Macintosh computer to continue processing normally per formed in priviledged mode in the protected mode including establishing at least one user stack in the virtual memory space in response to an at tempt by the Macintosh operating system to estab 20 25 45 50 55 65 46 lish a stack and forcing the Macintosh operating system or at least one currently executing applica tion program to use the at least one user stack as if the macintosh operating system or the at least one currently executing application program was still operating in normal privileged mode by redirecting the microprocessor to use the at least one user stack when the Macintosh operating system or the at least one currently executing application program attempts to address any stack during processing normally performed in privil
81. ove is at present believed to provide good performance An alternative technique which would eliminate the requirement to map out a zone for the startup system stack which is effectively the supervisor stack is to perform the warm 20 25 30 35 40 45 50 60 65 8 re boot in user mode Such an approach involves other complications but does not require the stack integrity needed for operation in supervisor mode Following the re mapping of step 32 the page map is altered at step 34 to map the virtual memory code to the top of the virtual memory address space This can fill the space vacated by the memory taken to create a mapped zone for the startup system stack Once the page map is altered certain frequently used pages of the system and debugger if any are locked or prevented from being swapped out to disk by the virtual memory algorithm described below by setting an ap propriate flag at step 36 It is not necessary in all cases to lock such pages although such an approach is gener ally preferable to ensure critical pages are not swapped out to disk to maintain diagnostic integrity for debug ging if necessary to maintain a zone of 1 1 logical to physical memory mapping for alternate bus masters and to increase performance The zone of 1 1 logical to physical mapping referred to above is typically on the order of 64K bytes but could vary substantially Following the page locking of step 36 the por
82. r mode in the user mode including establishing at least one user stack in the virtual memory space in response to an attempt by the Apple Macintosh operating system to establish a stack and forcing the Apple Macintosh operating system or at least one currently executing application program to use the at least one user stack instead of the supervisor stack as if the Apple Macintosh operating system or the at least one currently executing application program was still operating in the normal supervi sor mode by redirecting the microprocessor to use the at least one user stack when the Apple Macin tosh operating system or the at least one currently executing application program attempts to address 7 least part of the physical memory and at least part of the virtual memory file as virtual memory space whereby there is a first portion of the virtual mem ory space in the physical memory and a second portion of the virtual memory space in the periph eral storage establishing a supervisor stack in the physical mem 65 any stack during processing normally performed in supervisor mode and swapping between the first and second portions of the virtual memory space in accordance with a prede termined criteria non critical information 2 The method of claim 1 further including the step of retaining critical information in the first portion of the virtual memory space 5 063 499 45 3 The method of claim 2 wh
83. rdance with any suit able weighting criteria and the least used page as deter mined by that criteria is then selected at either step 314 or step 316 and passed to the next step As noted above it is faster to mark an unmodified page as non resident and so in most cases it is preferable to use a weighting criteria that tends to select unmodified pages to be made non resident In some cases however it will not be desirable to swap out the selected page whether modified or un modified Most such pages are marked with a don t swap flag However it might occur that a page that is not so marked will still be selected by the page selection routine because all pages are being used regularly Such undesirable swap outs can be avoided by keeping track of usage history such as by the aging table discussed above and imposing a rule that any page which has always been used during the period between any two disk swaps is not to be swapped out This is shown at step 318 and if the selected least used page does not have a full usage history it is selected to be marked non resident swapped out at step 320 Alternatively if the page selected as least used does have a full usage history that page cannot be selected and the aging tables are again updated at step 322 so that another page can be selected Pages having a full usage history but which are not marked with a don t swap flag may be marked as slow aging pages Then as shown at step
84. return address for the stack is altered in step 246 to return to the routine to restore the registers and stack to the state they were in when the second page fault occurred The system then resumes processing If the page swap which solved the first page fault also solves the second page fault no error will be reported However if the solution to the first fault does not solve the second page fault the second page fault will recur However upon recurrence it will be the first fault and can be handled accordingly The routine then returns at step 248 from the bus error exception Page Selection Routine For any virtual memory system to work it is some times necessary to retrieve pages of memory from disk If physical RAM is full as it presumably is it is neces sary to mark to disk or page out pages in physical memory to make room for the pages retrieved from disk Various criteria can be implemented which will accomplish this task with reasonable results However at the same time certain critical pages should not be swapped out to disk This set of critical pages includes particularly the pages of memory nec essary to execute a page swap While these pages can in some virtual memory processes be readily identified such identification may not be done so readily in the Apple Macintosh environment where the code which implements virtual memory is added to an existing oper ating system Of course with sufficient knowledge of
85. rupted or discarded since that installation the present invention will simply proceed as though no prior instal lation had occurred Following successful allocation of the disk space the code which implements the present invention is copied at step 26 from the disk to a known location in physical memory In some embodiments it may be desirable to oopy the oode to a fixed location in physical memory although this is not always necessary At a later time the locations holding this code can be remapped to the top highest address of logical memory and locked made immune to page swapping described in greater detail hereinafter to ensure that no portion of the code is swapped out to disk The process then determines how much physical RAM exists and determines how much to emulate before reaching the current limit of eight megabytes noted above Although the present version of the Macintosh OS includes an eight mega byte limit step 28 may also include selection of the amount of memory to emulate Once the eight mega byte limit of the operating system is removed the user may then size the virtual memory in accordance with the available space on the hard disk Following the determination of how much virtual memory will be created page translation tables are created at step 30 a typical embodiment single table entry is made for each page of virtual memory The tables are used by the 68851 PMMU FIG Ic to address the physical and d
86. sed during each complete swap all the critical pages plus some additional non critical pages will be at least prelimi narily protected from being swapped out At this point a potential problem exists Depending on the size of physical memory it is possible that the entirety of physical memory will consist of pages that are used during the period of time between each page Swap even though sorne of those pages are non critical This necessitates a second level criteria for deciding which pages are non critical While many such criteria will work a presently preferred approach involves setting a flag bit for each page written in memory dur ing the initial installation of the virtual memory soft ware This marks all critical pages but also marks many non critical pages It will be apparent to those skilled in the art that the truly critical pages have both a heavy usage history ie satisfy the first criteria and also have the flag bit set the second criteria The combination of the two criteria then permits selection of a non critical page for swapping By using the page usage history criteria to make a determination of which page to swap out so long as not every page is heavily used non critical pages including those pages with the flag bit set can be swapped out to disk Then in the somewhat unlikely event that every page in mem ory has a heavy usage history those pages which do not have a flag bit set can still be selected as
87. struction to execute in supervisor mode oniy under careful supervision and to then switch the system back to user mode A combination of these approaches is shown in FIG 4 in which instructions predefined as common be emulated but other instructions are exe cuted under careful supervision typically through use of the TRACE instruction in the Macintosh operating system although other techniques are possible Thus when the privilege error occurs the privilege patch routine is called at step 100 If the privilege error results from a system call by specially authorized code segments including code of the present invention the process branches at step 102 to permit a return to the system at step 104 with the system continuing in super visor mode However if the call is not from the privileged virtual memory code of the present invention an inquiry is then made at step 106 to determine whether the call causing the privilege error is a common instruction Common instructions which are herein intended to mean those which are frequently used and easily emu lated are then emulated in software at step 108 and the system returns from the privilege exception at step 109 Typical instructions which may be viewed as common are the move status register to A7 instruction and its converse and the change priority instruction Other instructions such as the stop instruction any instruction which accesses or changes the address of the V
88. t one currently executing application program was still operating in the normal supervisor mode by redi recting the microprocessor to use the at least one user stack when the operating system or the at least one currently executing application program at tempts to address any stack during processing nor mally performed in supervisor mode and swapping between the first and second portions of the virtual memory space in accordance with a prede termined criteria non critical information
89. the end of the originally re quested read Following set up the next block of infor mation is read from disk at step 384 and as before the page to which that block is to be written is identified If the page is resident as determined at step 388 the page is added to a second list of temporarily locked pages As before if the page is not resident an inquiry is made at step 392 whether the page of physical memory will be completely overwritten by the read from disk If the page is to be completely overwritten the disk image flag for the page is cleared at step 394 If the page is not to be overwritten or after clearing the disk image flag if to be overwritten the routine continues with step 396 where the page fault routine shown beginning at step 222 of FIG 8 is used to validate the page Thereafter the successive next last in the list of tem porarily locked pages is selected at step 398 and that page is swapped out at step 400 This frees up a page for this block of the read operation previously no addi tional pages of physical memory were available since we had reached the maximum number of locked pages in performing the previous section of this 1 call and so this logical page is then remapped into RAM at step 402 to be ready for the next read at which time it will overwritten The results of either step 390 or step 402 then cause the routine to continue at step 404 where an inquiry is made as to whether there are more b
90. the faulted page is read from disk at step 230 into the physical memory of the selected page while the faulted page is temporarily mapped to an alternate location which may be regarded as a transient page zone FIG 2b and the page modified flag is cleared The transient holding zone is used to prevent processing of incorrect code or data in the event an interrupt occurs which requires the use of code or data on the page before the code or data in that page can be fully updated from its disk image If the answer to the inquiry at step 228 was no or following the reading of the disk image in step 230 the routine advances to step 232 and remaps the now restored faulted page to the address where the page fault was detected Thereafter in step 234 the registers and PMMU status are restored and the routine returns in step 236 If the inquiry at step 212 did not find a second page fault the return at step 236 will simply return to the 5 20 25 35 45 50 55 65 14 system However if a second page fault did exist the return address supplied at step 236 will jump to the routine shown in FIG 9 for double faults so that the secondary fault s can now be handled The routine is called at step 240 and begins at step 242 by copying the saved stack caused by the second page fault back to its original location The registers are then restored in step 244 to their state at the time of the second page fault Next the
91. tions of memory zoned for the system and static memory are assigned slow aging status at step 38 As will be dis cussed hereinafter assignment of such status simplifies determination of pages which cannot be swapped out to disk Next at step 40 the bus error vector is pointed to the bus error routine and the Swap MMU Mode rou tine FIG 7 is pointed to the new Swap MMU address tables set up by steps 30 38 by using a call to the Swap routine Finally after the reconfiguring of step 42 a warm re boot of the machine is performed at step 44 The warm boot uses the same boot code as the original code in the ROMs of the Macintosh computer but is tailored to avoid any call which initializes or otherwise affects critical memory locations such as the size and speed of memory including MEMTOP and the start of the static memory zone BUFPTR or the state of the PMMU so that the installed virtual memory code will not be disturbed The warm reboot allows slot drivers and device drivers to re install in the virtual address space rather than just in the physical address space causing the system to appear as it would if the same amount of physical memory as virtual memory existed During the course of the warm reboot process the INIT step lo will again be entered Since this is a second pass installation the decision at step 16 is yes causing the process to branch to step 48 At step 48 the process opens the virtual memory file al
92. um Prentice Hall Inc 1987 ISBN 0 13 637406 9 Chap 4 Primary Examiner Thomas C Lee Attorney Agent or Firm Harrison amp Eaken 57 ABSTRACT A method for causing suitably configured versions of the Apple Macintosh computer running the Apple Mac intosh operating system to operate in user mode while causing at least user programs to continue to perform as though operating in supervisor mode and in conjunc tion therewith a further method for implementing vir tual memory on such Apple Macintosh computer sys tems Macintosh 11 Claims 10 Drawing Sheets 12 9ROPER J RE MAP PHYS MEM ENV RONMENT gt OPEN VIRTUAL MEMORY FILE VIRTUAL ADD SPACE CREATE Se SS ee MAPPED ZONE FOR 32 ves i STARTUP SYSTEM STACK i6 i So REDIRECT R W TRAP CALLS PROGRAM 1 MAP VIRTUAL MEM CODE 3 ALREADY CREATE NEw EXCEPTION TOP OF VIRT ADD SPACE bi INSTALLED Se VECTOR TABLE IN BROT MEM LEE Pea SA SP LOCK FREQUENTLY USED PAGES 36 2o PATCH VECTORS TO NEw EVER ALLOCATE AR TUAL EXCEPTION VECTOR TABLE INSTALLED MEMORY ILE BEFORI x a SE SYS k STATIC MEM BE RES I ZONES TC SLOW AGING STATUS 38 A eT i ves d SET BUS ERROR VECTOR amp f SwopMMUmocde ROUTINES 40 CIPY PROGRAM 70 26 RECONFIG TO il FIxED LOCATION USE NEW PAGE TABLES __i bog HOW MUCH peal
93. vi sor stack pointer in a static location and setting the supervisor stack pointer to the user stack pointer ad dress at step 120 Finally a flat is set at step 122 so that the trace exception routine knows to expect a trace exception from the instruction emulator The process thus permits certain privileged instructions to execute in supervisor mode while at the same time protecting the pointers necessary for virtual memory Once the in struction completes processing the routine returns from the exception at step 109 Trace Patch As discussed above in the preferred embodiment of the present invention use of the TRACE instruction is helpful to emulate certain types of instructions which create a privilege violation Other instruction emulation techniques could readily be used In this preferred ap proach however it is necessary to trace or supervise on a step by step basis the execution of some of the system calls to avoid corruption of the stack The trace patch shown in FIG 5 will permit such supervision and used to allow execution of calls that cannot be easily emulated or are not yet known to exist In such event the trace patch is called at step 130 and begins at step 132 by inquiring whether the trace was expected from an instruction emulation If so the process branches to step 134 so the processor mode will be reset to user mode upon return from this exception Follow ing the reset the routine determines at step 13

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