Concurrent multi-threaded execution
Contents
1. The parameter thread does not hold the ID upon successful completion but is the thread control block that must be allocated in advance The thread startroutine never returns pthread_mutex_trylock pthread_mutex_t mutex pthread_mutex_unlock pthread_mutex_t mutex pthread_cond_wait pthread_cond_t cond pthread_mutex_t mutex pthread_cond_timedwait_np pthread_cond_t cond pthread_mutex_t mutex uint16_t reltime Non portable version of pthread_timewait The time to wait is specified by the reltime parameter as a relative system time The maximum number of conditions that can wait is defined by TW_SZ pthread_cond_broadcast pthread_cond_t cond pthread_cond_signal pthread_cond_t cond pthread_cond_timedwait_init_np void Non portable function that is not available in the POSIX standard The timer is required in case of timed wait on condition The initialization of the timer should be done in after thread creation pthread_schedrr_init_np void Non portable function that is not available in the POSIX standard The timer is required in case of round robin scheduling policy The initialization of the timer should be done after thread creation pthread_start_np void Non portable function that is not available in the POSIX standard This function should be called at the end of main and starts the thread exe cution It never returns Application N2. 16 for 77 1 17 counter ES printf Thread d counter d n int arg counter ig delay ms 200 20 o 200 22 23 void main void 24 pll init 25 7 26 pthread_create np thl NULL threadl void 1 2 pthread create np th2 NULL thread2 void 2 28 29 pthread schedrr init_np 30 pthread start _np 31 Application Note 10 V1 0 2010 03 e AP32152 Infi neon Concurrent multi threaded execution Threads Output Thread 1 counter 1 Thread 2 counter 1 Thread 1 counter 2 Thread 2 counter 2 Thread 1 counter 3 Thread 1 counter 4 Thread 2 counter 3 Thread 1 counter 5 Thread 1 counter 6 Thread 1 counter 7 Thread 2 counter 4 Thread 1 counter 8 Thread 2 counter 5 Thread 1 counter 9 Thread 1 counter 10 Listing 2 A first pthread example Example pthread_static_example_1 9 215 x _thl stack B3 _th2 stack 63 Figure 1 Snapshot of the debugger watch view 4 2 Creating Threads Each thread is associated with a thread control block The header file pthread h defines the following type 1 typedef struct pthread s 2 struct pthread_s next lt next thread pointer 3 struct pthread s prev lt previous thread pointer 4 uint32 t lex lt lower context pointer 5 uint32 t priority lt thread priority 0 to PTHREAD PRIO MAX 6 uint32 t policy lt policy is one of sched
3. a non preemptive system there is no guarantee as to when a running task will get around to checking for the notification or make a call that will allow the kernel to do so That means that if the overall system of co operating tasks and ISRs is not carefully designed non preemptive can easily become non responsive For that reason non preemptive kernels are rarely used in hard real time systems 2 2 Preemptive Scheduling Virtually all commercial real time operating systems on the market implement preemptive scheduling That means that an interrupt can cause a waiting task to become ready to execute and if the new task has higher priority than the task running when the interrupt was taken the new task will be dispatched when the ISR exits preempting the previously running task The simplest model for preemptive scheduling is 1 Application task is running at non interrupt background level All interrupts are enabled 2 Interrupt is taken ISR calls real time kernel function event notification that results in a change to the task ready queue 3 Real time kernel updates the appropriate queues but takes no further action before returning to the ISR 4 ISR completes but does not issue a direct return from interrupt Instead it branches to a kernel entry point or ISR termination 5 The kernel still operating at the interrupt level from which it was invoked examines the task ready queue If a task switch is called for it
4. check for a return context CIPN of zero This is the PCPN field Previous CPU Priority Number of the Previous Context Information PCXI register A limitation of this approach is that it still requires ISRs to exit through the kernel in order to perform the check However an alternative approach is available that avoids even that modest overhead Tasks and ISRs with an I O privilege level of 2 Supervisor mode can post interrupt requests by writing to the control registers of interrupt nodes If interrupt priority level 1 is left unused by any hardware device and there is an interrupt node available that is not used for any hardware interrupt then entry 1 in the interrupt vector can be used to invoke the task dispatch function If an ISR makes a kernel call that results in a change to the task ready queue then the kernel will post an interrupt request at priority level 1 The ISR for that IPN will be the task dispatch function Since priority level 1 is below any hardware interrupt priority but above the level for software managed tasks that interrupt will be taken after all hardware interrupts have been serviced but before returning to the original interrupted task Using a software posted interrupt to access the task dispatcher might initially seem to create unnecessary con text switching overhead However the TriCore s interrupt system is optimized to avoid unnecessary context switching If there is a pending interrupt at a level
5. values moving that value into the PCXI register issuing an RSLCX instruction to restore the new task s lower context and executing a Return From Exception RFE to complete the dispatch of the new task The restoration of the upper context of the newly dispatched task by the RFE instruction includes loading the task s saved Program Status Word PSW which re enables interrupts The total length of the critical dispatch sequence Listing 1 where interrupts are disabled is then just nine instructions including the DISABLE instruction itself 1 disable START CRITICAL SECTION 2 1d w d0 a0 soffset OSReadyQ Task Ready Queue 32 entries 3 c1z d0 d0 Index of highest priority ready task 32 if none 4 st w a0 Soffset OSCurrentTask d0 5 addsc a al5 a8 d0 2 Address of word containing context pointer 6 ld w d0 a15 Context pointer for this task 7 mtcr CR INDEX PCXI d0 Move context pointer to core register PCXI 8 rlex Restore lower context 9 rfe Complete the dispatch operation Listing 1 Dispatch sequence Note If a software posted interrupt is used to access the task dispatcher it is possible to avoid disabling interrupts in the dispatcher altogether If the sequence shown above is interrupted and as a result of the interrupt a higher priority task becomes ready to execute the final RFE will not cause the initial task to be dispatched The CIPN for its return context will be zero while a softwa
6. 68804 4465341 4548097 3023745 3023745 3023745 3023745 Listing 10 Synchronizing example using mutex 6 2 Conditions variables Example pthread_static_example_3 This example shows how to use a condition variable to wake up a thread All seven threads are created with priority 2 first in first out scheduling policy and the same thread function thread2 These threads are waiting on the condition variable conditionMet which is initialized with 0 to become 1 So all threads become blocked by the condition until thread thO with priority 1 and thread function thread1 are running and conditionMet is set to 1 A call of pthread_cond_broadcast signals all blocked threads to become runnable Example 3 define thread name priority policy stack size PTHREAD CONTROL BLOCK th0 1 SCHED FIFO PTHREAD DEFAULT STACK SIZI PTHREAD CONTROL BLOCK th1 2 SCHED FIFO PTHREAD DEFAULT STACK SIZI PTHREAD CONTROL BLOCK th2 2 SCHED FIFO PTHREAD DEFAULT STACK SIZI w ESTONIA Gl Gl El Application Note 20 V1 0 2010 03 Infineon AP32152 Concurrent multi threaded execution Synchronizing 5 PTHREAD CONTROL BLOCK th3 2 SCHED FIFO PTHREAD DEFAULT STACK
7. Core architecture and explains how particular features of the architecture can be used to expedite task management and scheduling 3 1 Task Dispatch Control For many architectures determining when to invoke the task dispatch logic is non trivial From an ISR there is no immediate way of knowing whether the current return context is for a software managed task or for another ISR that was executing when the current interrupt was taken One way to deal with this is to require every ISR to register itself with the kernel immediately upon entry while interrupts are disabled Registration may consist of as little as atomically incrementing an interrupt nesting counter The ISR is also required to exit through the kernel giving the kernel an opportunity to test and decre ment the nesting counter When the counter value prior to decrementing is 1 the kernel knows that it is about to return to the user level At that point it branches to the dispatcher to check whether it should return to the inter rupted task or switch to a new task The TriCore architecture provides a more direct method of determining the level of the current return context The user level at which software managed tasks are executed is priority level O At all times the CPU keeps track of both the current CPU Interrupt Priority Number CIPN and the CIPN of the return context Both values can be read by software so the test for being at the first interrupt level is simply to
8. D_RR and the default stack size The main function Lines 23 31 initializes the PLL creates the threads Lines 26 27 initializes the pthread scheduler Line 29 and starts the threads Line 30 The threads are created calling pthread_create_np with the thread control block the thread function and an argument that is passed to the thread function The thread functions thread1 Lines 5 12 thread2 Lines 14 21 once started run forever The endless loop contains a busy waiting delay_ms function thread1 is delayed by 100 ms thread2 by 200 ms Each thread function in this example increments a local counter variable These variables are allocated on the thread local stack With the busy waiting function the thread1 counter should increment twice as fast as the thread2 counter The counter variable is printed to the simulated I O terminal The counter values can be recognized on the stack with the debugger watch view Figure 1 Example 1 1 Define thread control block name priority policy stack size 2 PTHREAD CONTROL BLOCK th1 1 SCHED RR PTHREAD DEFAULT STACK SIZE 3 PTHREAD CONTROL BLOCK th2 1 SCHED RR PTHREAD DEFAULT STACK SIZE 4 5 void threadl void arg 6 uint32 t volatile counter 0 7 for 77 1 8 counter 9 printf Thread d counter d n int arg counter 10 delay ms 100 11 7 12 13 14 void thread2 void arg 15 uint32 t volatile counter 0
9. OSIX condition implements a unilateral synchronization A task waits for another task until is signals an event Bilateral synchronization often called a rendezvous is rarely supported by RTOSs A condition variable provides a way of naming an event in which threads have a general interest An event can be as simple as a counter s reaching a particular value or a flag being set or cleared Pthreads conditions are a perfect choice when a thread waits for a resource i e an interrupt to provide new data 6 1 Mutex variables Example pthread_static_example_2 This example shows the corruption that can result if no serialization is done and also shows the use of pthread_mutex_lock It can be called with no parameters to use pthread_mutex_lock to protect the critical section or called with one or more parameters to show data corruption that occurs without locking The example creates four threads with round robin scheduling policy with the same thread function The threads increment four global variables i j k Without using a mutex there is a chance that a thread switch will happen after loading a global variable The new thread increments the variable and when the first thread continues exe cuting the value that is already loaded to a register is outdated This results in different values of i j k and I as shown in the first output window The second output window shows the values when the critical section of incrementing the global var
10. SIZE 6 PTHREAD CONTROL BLOCK th4 2 SCHED FIFO PTHREAD DEFAULT STACK SIZE 7 PTHREAD CONTROL BLOCK th5 2 SCHED FIFO PTHREAD DEFAULT STACK SIZE 8 PTHREAD CONTROL BLOCK th6 2 SCHED FIFO PTHREAD DEFAULT STACK SIZE 9 PTHREAD CONTROL BLOCK th7 2 SCHED FIFO PTHREAD DEFAULT STACK SIZE 10 11 int32 t volatile conditionMet 0 12 pthread cond t cond PTHREAD COND INITIALIZER 13 pthread mutex t mutex PTHREAD MUTEX INITIALIZER 14 15 void threadl void arg 16 for 77 17 pthread mutex lock mutex 18 conditionMet 1 LY puts Wake up all waiters 20 delay ms 200 2 pthread cond broadcast amp cond 22 pthread mutex_unlock amp mutex 23 24 25 26 void thread2 void arg BY Lor z7 4 28 pthread mutex lock amp mutex 29 conditionMet 0 30 while conditionMet all printf Thread d blocked n int arg 32 delay ms 200 33 pthread cond wait amp cond amp mutex 34 35 pthread mutex unlock amp mutex 36 o E 37 38 39 void main void 40 pll_init 41 42 pthread create np th0 NULL threadl void 0 43 pthread create np thl NULL thread2 void 1 44 pthread create np th2 NULL thread2 void 2 45 pthread create np th3 NULL thread2 void 3 46 pthread create np th4 NULL thread2 void 4 47 pthread create np th5 NULL thread2 void 5 48 pthread create np th6 NULL thread2 void 6 49 pthread create np th7 NULL thread2 void 7 50 Bal
11. TCH_SIGNAL Line 43 Either the current running thread is swapped out or one or more blocked threads are appended to the runnable thread list In both cases the function pthread_start_np identifies the thread with the highest priority number in the runnable thread list Line 9 and swaps in this thread Application Note 15 V1 0 2010 03 Infineon Concurrent AP32152 multi threaded execution Threads 1 Start threads 2 inline void pthread start np void B extern uint32_t pthread runnable 4 extern pthread t pthread running 5 extern pthread t pthread_runnable threads PTHREAD PRIO MAX 6 pthread_t thread 7 8 get ready thread with highest priority ready 9 thread pthread_runnable threads 31l clz pthread_runnable 10 11 check if timer must be enabled if thread policy is SCHED RR 12 and there is another thread with the same priority 13 if thread gt next NULL amp amp thread gt policy SCHED RR 14 STM _SRCO B SRE 1 STOREBIT STM SRCO 12 1 LS else 16 STM_SRCO B SRE 0 STOREBIT STM SRCO 12 0 17 18 pthread_running thread 19 dsync 20 mtcr PCXI thread gt lcx 21 __rslex 22 asm mov d2 0 23 asm rfe 24 25 26 static void trapsystem pthread t blocked threads ptr pthread t last thread 2714 28 int tin i 29 pthread_t thread tmp 30 Sil asm mov 0 d15 n 32 _ svlcex n 33 d tin put d15 in C va
12. ample 5 1 define thread name priority policy stack size 2 PTHREAD CONTROL BLOCK th0 0 SCHED FIFO PTHREAD DEFAULT STACK SIZE 3 PTHREAD CONTROL BLOCK th1 2 SCHED FIFO PTHREAD DEFAULT STACK SIZE 4 PTHREAD CONTROL BLOCK th2 2 SCHED_FIFO PTHREAD DEFAULT STACK SIZE 5 6 pthread cond t condl PTHREAD COND INITIALIZER 7 pthread mutex t mutexl PTHREAD MUTEX INITIALIZER 8 pthread cond t cond2 PTHREAD COND INITIALIZER 9 pthread mutex t mutex2 PTHREAD MUTEX INITIALIZER 10 11 void _ interrupt 5 ascO rx void 12 puts Wake up all waiters 13 pthread cond broadcast amp cond1 14 pthread cond broadcast amp cond2 LS 16 17 void idle void arg 18 for LS 20 2al 22 void threadi void arg 23 for 75 24 pthread mutex lock mutexl 25 printf Thread d blocked n int arg 26 pthread_cond_wait amp condl mutexl 27 printf Thread d continued n int arg 28 pthread mutex unlock amp mutexl1 29 o 7 30 31 void thread2 void arg 32 f r 77 4 SS pthread mutex lock amp mutex2 34 printf Thread d blocked n int arg 35 pthread cond timedwait_np amp cond2 amp mutex2 100 36 printf Thread d continued n int arg Si pthread mutex unlock amp mutex2 38 o 39 40 41 void main void 42 pll_init 43 ascO_init 44 45 printf Example 5 Create 3 threads with first in first out policy 46 Shows how to block a thread unti
13. andler is directly placed in the interrupt vector table with the __interrupt_fast qualifier Every time the handler is called the next thread in the linked list is made the running thread Line 5 If this thread does not have a round robin scheduling policy the system timer service request node will be disabled Lines 8 11 1 void stm src0 void 2 pthread t thread 3 4 pthread running gt lcx mfcr PCXI 5 thread pthread _running gt next 6 pthread_runnable threads thread gt priority thread 7 8 if thread gt policy SCHED RR 9 STM_SRCO B SRE 1 7 10 else 11 STM SRCO B SRE 0 12 13 PTHREAD SWAP HANDLER thread pthread_ running callback hook optional 14 15 pthread_running thread 16 dsync required before PCXI manipulation 17 _ mtcr PCXI thread gt 1cx modify previous context 18 _ asm ji all 19 20 21 void interrupt fast 2 stm src0 fast void store upper context 22 STM ISRR B CMPOIRR 1 7 enable interrupts again 23 asm svlcx ka store lower context 24 Jla stm sreb An jump and link absolute to stm_src0 25 rslcx a restore lower context 26 RFE restores upper context Listing 7 stm_src0 interrupt function 4 5 Dispatching Threads The thread dispatcher is invoked by a system call SYSCALL which causes a system trap Listing 8 The trap identification number TIN defines two cases DISPATCH_WAIT Line 38 or DISPA
14. ative time parameter The relative time has to be given in 1 to 65536 ticks of the system timer of 728 us STM SRC1 U TIMEDWAIT INT set service request control l inline void pthread cond timedwait_init np 2 STM CMCON B MSIZE1 15 16 bits are used for compare operation 3 STM CMCON B MSTART1 16 STM 16 31 that is compared to CMP1 4 a Interrupt period 1 to 65535 ticks 728us 5 STM ICR B CMP1EN 1 Interrupt on compare match with CMP1 enabled 6 STM ICR B CMP10S 1 Interrupt output STMIR1 selected 7 8 Listing 9 pthread_schedrr_init_np function Application Note 17 V1 0 2010 03 Infineon AP32152 Concurrent multi threaded execution 5 API Reference API Reference The library implements a subset of the POSIX pthread standard 4 Non portable functions have a _np suffix These functions might have different parameter or different behaviour or they are not available in the standard In general the implementation does not set the error number For a complete description of the pthread func tions please read the Open Group Base Specifications Issue 6 IEEE Std 1003 1 see www opengroup org Table 1 Compatibility Matrix Name Notes pthread_create_np pthread_t thread const pthread_attr_t attr void start_routine void void arg Non portable version of pthread_create Function must be called from main The function does not start the thread
15. below the current CIPN but above the CIPN of the return context then the hardware executes a return from the current interrupt level as a branch to the ISR for the pending interrupt The return from the current ISR is folded with the taking of the pending interrupt bypassing the restore and immediate re save of the return context 3 2 Task Dispatching An issue that must be addressed by the task dispatcher is to ensure that a dispatch request cannot disappear between the time the highest priority ready task is identified and the time the dispatch is completed i e before the return from interrupt to the dispatched task is executed by the dispatcher The scenario for a lost request is 1 An interrupt is taken and results in a change in the task ready queue 2 The task dispatcher is entered and the highest priority ready task is identified 3 After the task is identified but before it is actually dispatched another interrupt is taken That interrupt results in further change to the task ready queue adding a task whose priority is higher than the task that was about to be dispatched The ISR could perform the check in line but it would have to know where to go depending on the outcome of the check It is cleaner and as efficient for it to branch to an exit function in the kernel Application Note 8 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Task Management on TriCore 4 The second ISR d
16. cture i e allocates memory on the heap The pthread_create_np function reserves two context areas Listing 4 Line 11 13 from a block allocated in cstart for the thread and sets up the PSW the stack pointer register A10 and Program Counter PC Finally it puts the threads control block in a linked list The library organizes the thread control blocks in an array of linked lists pthread t pthread_runnable threads PTHREAD PRIO MAX If the array element is not empty but holds one thread control block a corresponding bit in the 32 bit pthread_runnable variable is set Therefore the scheduler can quickly find the thread with the highest priority using the CLZ instruction 1l int pthread create np pthread t thread const pthread_attr_t attr 2 void start_routine void void arg El 4 const pthread attr t default attr PTHREAD DEFAULT ATTR 5 uint32 t fcx 7 7 7 7 6 context t cx 7 8 if attr NULL 9 attr amp default_attr 10 11 fex mfcr FCX At start up the context is a linear array 12 thread gt lcx fcx 1 so that a decrement of 2 reserves an 13 _ mtcr FCX fex 2 upper and lower context 14 15 cx cx _to_addr fcx Convert context pointer to address 16 cx gt u psw 0 lt lt 12 Protection Register Set PRS 0 17 attr gt mode lt lt 10 I O Privilege 18 IL lt lt 7 Call depth counting is enabled CDE 1 19 attr gt call dept
17. cular features of the architecture can be used to expedite task management and scheduling Processing is performed either at the interrupt service level with context switching driven entirely by the priority interrupt mechanisms of the hardware or at a non interrupt level by software managed tasks The interrupt system still operates of course but in addition to the context switching involved in taking and returning from an interrupt there is software managed context switching between application tasks driven by the task manage ment of a real time kernel Typical deeply embedded applications on the TriCore are driven mainly by interrupts The TriCore architecture supports these systems with multiple features resulting in extremely low interrupt latency e Hardware supported context switch The upper context sixteen 32bit registers 512bits are stored in 2 CPU cycles While application programmers are limited to 64 bit load store operations the core stores 128 bits in one cycle During a context load store a shadow bank inside the TriCore is used to temporarily store 256 bits so that although the complete store operation will take 4 cycles the core is ready to execute the interrupt routine within 2 cycles e 4 stage pipeline The TriCore has a 4 stage fetch decode execute writeback pipeline When an interrupt is taken the first instruction is executed after just 3 cycles e The Interrupt Control Unit ICU is running independently fro
18. document is aimed at developers who write or design real time applications on the TriCore and are considering splitting the application into multiple threads of execution This document looks specifically at those features of the TriCore architecture that make it such an attractive platform for real time embedded systems focusing par ticularly on fast context switching and the use of software posted interrupt requests for low overhead interfacing to the task dispatch function of the kernel This guide assumes that readers have access to the TriCore Architecture Manual 1 and have at least some general knowledge of the TriCore instruction set and architectural features Those chapters of the Architecture Manual covering Core Registers Context Management and function calling are particularly pertinent to potential readers of this document See References on Page 25 for more information on the TriCore Architecture manual and other relevant docu mentation It is assumed that most readers will be generally familiar with the features and functions of Real Time Operating Systems RTOSs However between this document and those listed in the references there is enough infor mation to enable embedded systems programmers with no prior RTOS experience to understand and add custom RTOS functionality to embedded applications that require it 2 Introduction This chapter explores specific real time issues for the TriCore architecture and explains how parti
19. ead void arg for 77 pthread_mutex_lock amp mutex printf Thread d blocked n int arg pthread _ cond wait amp cond amp mutex printf Thread d continued n int arg pthread_mutex_unlock amp mutex void main void pll_init ascO_init pthread_create np th0 NULL idle void 0 pthread create np thl NULL thread void 1 pthread create np th2 NULL thread void 2 pthread_ start _np Output Thread 1 blocked Thread 2 blocked Wake up all waiters Thread 1 continued Thread 1 blocked Thread 2 continued Thread 2 blocked Wake up all waiters Listing 12 Synchronizing example using condition with a wake up from an interrupt Application Note 22 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Synchronizing 6 4 Condition variables with timeout period Example pthread_static_example_5 This example shows how to use a condition variable to wake up a thread from an interrupt or after a timeout period has elapsed Thread th1 and th2 are waiting for a condition Lines 26 35 and become blocked The receive interrupt handler from an ASC interface broadcasts the conditions Lines 15 16 and make the threads runnable again Thread th2 is blocked with a timeout period of 100 timer ticks Line 35 Ex
20. ee cd Cinfineon Never stop thinking ose TriCore AP32152 Concurrent multi threaded execution Application Note V1 0 2010 03 Microcontrollers Edition 2010 03 Published by Infineon Technologies AG 81726 Munich Germany 2010 Infineon Technologies AG All Rights Reserved LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND INCLUDING WITHOUT LIMITATION WARRANTIES OF NON INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written approval o
21. eeeeaaeeeeeeaaeeeeeeaaeeeeeecaeeeesenaeeeeeeneeeseeaas 6 Task Management on TriC Ores csicnctccccrsisssanncacernennseananinedeansctiganssnnpacednciisaansnapacentatdsaansnapedsanenadnaannsie 8 Task Dispaten Control vimos dali svweduasuan liinda dai ads uananea cae dwsieldea seats n 8 Task DISPatChiNg sima aida villanas sida aaaea adas 8 Threads ici ara 10 Getting Started conocia cti cin dial edie ev ates 10 Creating Threads eeina lalala EATEN E a 10 Starting TASAS viii tii li datas vant en dente ante 14 Schequling TRES cai ita 14 Dispatching ThtSadS cuco ataai a aa Aaaa Aaaa 15 Condition scheduliNQreisiciaiian aid tdi 17 API References corona Ai 18 SYN CHOMIZING ico cional toediee diusnbeccueanettedees duedieess 19 Mutex variables Example pthread_static_example_2 cccccccceceeeeeecececeeeeeeesecnaeaeeeeeeeeeeeenseaeess 19 Conditions variables Example pthread_static_example_3 ccccccceceesecceceeeeeeeceeaeeeeeeeeeeeeesenanees 19 Condition variables from interrupt handler Example pthread_static_example_4 ceee 22 Condition variables with timeout period Example pthread_static_example_5 ceeeeee 23 VO a ata 25 DOUTCO CONO crisi AAA EA 25 Referenc s iia 25 Application Note 4 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Preface 1 Preface This application note describes a basic thread support implementation on the TriCore architecture 1 The
22. etermining that it interrupted another ISR rather than a user routine returns to the inter rupted ISR It does not re enter the task dispatcher but assumes incorrectly that the dispatcher will be entered after the ISR to which it is returning completes 5 On resumption following the second interrupt the task dispatcher completes the dispatch of the task it had previously found without noticing that a new higher priority task has been enabled A simple way to avoid this problem is for the task dispatcher to disable interrupts before locating and dispatch ing the highest priority task on the ready queue Interrupts remain disabled until the task dispatch is completed That is in fact how most RTOS implementations do address the problem Often the time required to find and dispatch the highest priority task on the ready queue is the longest period during which interrupts are disabled and it determines the worst case interrupt latency for the RTOS A popular way to implement the task ready queue is with a one or two level bit vector If a system has 32 or fewer software managed tasks each one can be assigned a unique bit in a single word bit vector The bits are assigned according to the priority order of the tasks The ready queue is a single word in memory A task is marked as ready to execute by setting its bit in the ready queue Finding the highest priority task ready to execute is a matter of identifying the leftmost 1 bit in the ready
23. f Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered AP32152 a n fi n eon Concurrent multi threaded execution TC1797 Revision History V1 0 2010 03 Previous Version none Page Subjects major changes since last revision We Listen to Your Comments Is there any information in this document that you feel is wrong unclear or missing Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to S lt mcdocu comments infineon com Application Note 3 V1 0 2010 03 AP32152 a n fi n eon Concurrent multi threaded execution Table of Contents Table of Contents 1 2 2 1 2 2 PROTA CC II q caxnsnaunnnacanxiexeds 5 INtrOdU CON ion ia E E 5 Non Preemptive Scheduling 0 0 00 cee eeeeeeeeeeeeeenee ee eeeaeeeeeeeaeeeseeaaeeeeeeaaeeeeeeaaeeeeeeaaeeeeseeaeeeeeeneeeeeeieeeeeeaas 6 Preemptive Scheduling 0 0 0 2 ee ec eeeeeeeeeenee ee eeente ee corn ae ee nono nn eee eeeaaee
24. h overflow Call Depth Overflow 20 cx gt u al0 thread gt stack thread gt stack stack grow down 2i cx gt u all 0 New task has no return address 22 cx gt u pcxi 0 No previous context 23 cx Decrement to get the lower context address 24 cx gt l pcxi OL lt lt 24 Previous CPU Priority Number PCPN 0 25 1L lt lt 23 Previous Interrupt Enable PIE 1 26 1L lt lt 22 Upper Context Tag 27 fex Previous Context Pointer 28 cx gt l pe start routine Init new task start address 29 ex gt 1 al arg Argument when thread started 30 thread gt arg arg Container that saves the argument uint32 t i thread gt priority 33 list append pthread_runnable threads i thread thread 34 pthread runnable threads i 35 _ putbit 1 int amp pthread_runnable i mark current thread as runnable ale return 0 Listing 4 pthread_create_np function The context save area set up in the LDRAM after the first 2 threads were created is shown in Figure 2 The thread occupies a lower and upper context The lower context PCXI is linked to the upper context The contexts program counter variable PC is initialized with the thread start address The contexts A4 variable holds the argument which is passed to the thread program when it is called the first time The upper context block holds the pointer to the upper limit of the stack On the TriCore the stack grows downward The contexts A11 the ret
25. iables is protected using a mutex Example 2 pragma align 8 define thread name priority policy stack size PTHREAD CONTROL BLOCK th1 1 SCHED RR PTHREAD DEFAULT STACK SIZI PTHREAD CONTROL th2 1 SCHED RR PTHREAD DEFAULT STACK SIZI PTHREAD CONTROL OCK th3 1 SCHED RR PTHREAD DEFAULT STACK SIZI PTHREAD CONTROL BLOCK th4 1 SCHED RR PTHREAD DEFAULT STACK SIZI pragma align restore w w w w PA Fl A A o tO OO lO OS LO NOS pthread mutex t mutex PTHREAD MUTEX INITIALIZER 10 int i j k 1 11 int volatile uselock 0 12 13 void thread void arg 14 for 77 TUS if uselock 16 pthread mutex lock amp mutex 117 t i k 1 5 18 if uselock Application Note 19 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Synchronizing Lg pthread mutex unlock amp mutex 20 gt E 211 22 23 void main void 24 pli init 25 7 26 printf Create 4 threads with round robin policy n 21 28 pthread create np thl NULL thread void 1 29 pthread create np th2 NULL thread void 2 30 pthread create np th3 NULL thread void 2 Sill pthread_create np th4 NULL thread void 2 32 33 pthread init timer np 34 pthread start np E E E Output without using mutex Variable unlock 0 I watch Yiew2 4506722 39
26. l the condition is signaled or 47 until a timeout period elapsed n 48 49 pthread create np th0 NULL idle void 0 50 pthread create np thl NULL threadl void 1 Bl pthread create np th2 NULL thread2 void 2 52 53 pthread cond timedwait_init_np timedwait condition requires a timer 54 pthread start np Application Note 23 V1 0 2010 03 Infineon AP32152 Concurrent multi threaded execution Synchronizing 55 Output Thread 1 blocked Thread 2 blocked Thread 2 con Thread 2 blocked tin Wake up all wai Thread Thread Thread Thread Thread 1 1 2 2 2 con blocked con blocked con tin tin tin ued ters ued ued ued Listing 13 Synchronizing example using condition with a timeout period Application Note 24 V1 0 2010 03 n_n AP32152 n fi n eon Concurrent multi threaded execution Tools 7 Tools The pthread library is built using Tasking 3 3r1 The example code includes project workspaces for the PLS UDE debugger V2 6 11 8 Source code The source code provided with this application consists of a library project pthread_static and five example pro grams that were generally described in the chapter 4 and 6 Documentation is extracted directly from the sources using eclox 5 Open the html index html in each project directory 9 References 1 TriCore Architecture V1 3 8 2007 11 2 htto Aww
27. m the core The core execution is broken only when an interrupt is pending which has a higher priority than the current priority of the core The ICU can handle up to 255 priorities By default interrupt routines should be short and non interruptable It s up to the application programmer to enable higher priority interrupts during interrupt execution Interrupts can be grouped e TriCore derivatives implement a second core on the same silicon The Peripheral Control Processor PCP is directly connected to the peripheral bus has its own ICU and can handle interrupts independently from the TriCore or can preprocess values before sending them to the TriCore This offloads simple tasks from the main CPU The TriCore interrupt system is very efficient fast and small Systems that are solely built on interrupts without using any software managed tasks are referred to as bare hardware systems However bare hardware sys tems are limited in the complexity of the applications they can handle as the different Interrupt Service Routines ISRs have little scope for interaction They may share global variables for communicating status but are con 1 128 bit load store will be available on TC1 6 Application Note 5 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Introduction strained to a strict priority based last in first out scheduling sequence An ISR can not be allowed to suspend its execution to wait for a me
28. modifies the return context for the interrupt such that a switch is made to the new context The kernel then executes the return from interrupt Application Note 6 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Introduction This model assumes that ISRs execute to completion without being interrupted in turn by higher priority events In practice keeping interrupts disabled for the duration of an ISR may be unacceptable in terms of impact on interrupt latency So the model must deal with two complications e Determining when to invoke the task dispatch function It must be invoked just prior to returning from inter rupt to user level but not when returning from one interrupt level to another e Guaranteeing that when the task dispatch function has selected the highest priority ready task it can com plete the dispatch of that task without another interrupt coming in and invalidating its selection Besides implementing the dispatch operation itself i e a task context switch handling these two complications is the most crucial function of any real time executive or operating system The code for handling them is liter ally the kernel around which the rest of the system is built Application Note 7 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Task Management on TriCore 3 Task Management on TriCore This chapter explores specific RTOS porting issues for the Tri
29. ote 18 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Synchronizing 6 Synchronizing The library implements mutex and conditions variables To protect a shared resource from a race condition a type of synchronization called mutual exclusion or mutex for short can be used Using mutexes a thread turns at having exclusive access to data When one thread has exclusive access to data other threads cannot simul taneously access the same data The mutex is similar to the principle of the binary semaphore with one signifi cant difference the principle of ownership Ownership is the simple concept that when a task locks acquires a mutex only the same task can unlock release it If a task tries to unlock a mutex it hasn t locked thus doesn t own then an error condition is encountered and most importantly the mutex is not unlocked If the mutual exclusion object doesn t have ownership then it is not a mutex no matter what it is called The concept of ownership enables mutex implementations to address the problems and inherent dangers asso ciated with using the semaphores accidental release recursive deadlock task death deadlock priority inver sion and using a semaphore as a signal Semaphores are rarely required in embedded systems software Whereas a mutex allows threads to synchronize by controlling their access to data a condition variable allows threads to synchronize on the value of data The P
30. policy e 7 uint32 t arg lt argument passed at thread start 8 uint32 t stack 1 1 lt stack 1 is only a dummy pthread_t Listing 3 Thread control block pthread_t type definition The blocks are organized as a double linked list The block holds a pointer to the current lower context Line 3 the threads priority Line 4 and policy Line 5 The priority is number ranged from 0 to PTHREAD_PRIO_MAX When multiple threads are runnable the scheduler determines the thread with the highest priority The library supports first in first out SCHED_FIFO and round robin SCHED_RR policy The last element of the pthread_s structure is the stack The type definition only defines a dummy value The actual definition of a thread control block uses more memory All threads are defined as static e for each thread function there must be a thread control block defined The macro PTHREAD_CONTROL_BLOCK is used to define a TCB It defines the name priority policy and stack size Example PTHREAD CONTROL BLOCK th1 2 SCHED_FIFO PTHREAD DEFAULT STACK SIZE Application Note 11 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Threads The thread control block named th1 is defined with thread priority 2 SCHED_FIFO policy and a default stack size This thread control block is passed to the pthread_create_np function where the POSIX version dynamically creates the stru
31. pthread start _ np 52 Output Thread 1 blocked Thread 2 blocked Thread 3 blocked Thread 4 blocked Thread 5 blocked Thread 6 blocked Thread 7 blocked Wake up all waiters Listing 11 Synchronizing example using conditions Application Note 21 V1 0 2010 03 AP32152 a n fi n eon Concurrent multi threaded execution 6 3 Synchronizing Condition variables from interrupt handler Example pthread_static_example_4 This example shows how to use a condition variable to wake up a thread from an interrupt Thread th1 and th2 are waiting for a condition Line 23 and become blocked The receive interrupt handler from an ASC interface broadcasts the condition Line 14 and make the threads runnable again The example also implements a thread on the lowest priority which is executed on idle I 6 OS 10 INS Example 4 define thread name priority policy stack size PTHREAD CONTROL BLOCK th0 0 SCHED FIFO PTHREAD DEFAULT STACK SIZE PTHREAD CONTROL BLOCK th1 2 SCHED FIFO PTHREAD DEFAULT STACK SIZE PTHREAD CONTROL BLOCK th2 2 SCHED FIFO PTHREAD DEFAULT STACK SIZE PTHREAD COND INITIALIZER PTHREAD MUTEX INITIALIZER pthread_cond_t cond pthread mutex t mutex void _ interrupt 5 asc0_rx void puts Wake up all waiters pthread_cond_ broadcast amp cond void idle void arg for 77 void thr
32. pthread_running thread De __dsync Required before mtcr 28 _ mtcr PCXI thread gt 1cx Set previous context to start thread 24 __rslcx Restore the lower context 25 _asm mov d2 0 26 _ asm rfe Return and restore upper context and enable 27 Listing 5 pthread_start_np function 4 4 Scheduling Threads The pthread timer in the example is setup to generate an interrupt every increment of STM_TIM4 With the reset value the STM module runs at 1 4 of the CPU frequency i e 45 MHz when the TC1797 3 runs at a maximum Application Note 14 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Threads speed of 180 MHZ The interrupt is generated every 728 us The interrupt uses the service request node 0 with priority SCHEDRR_INT Line 6 l inline void pthread schedrr init np void 2 3 STM CMPO U 1 load compare register 0 with constant 1 4 STM CMCON B MSIZEO 0 CMPO O used for compare operation 5 STM CMCON B MSTARTO 16 STM 16 is the lowest bit number STM TIM4 6 7 2 16 1 45MHz 728us gt 7 STM ICR B CMPOEN 1 Interrupt on compare match with CMPO enabled 8 STM ICR B CMPOOS 0 Interrupt output STMIRO selected 9 STM SRCO U 0x1000 SCHEDRR_INT set and enable service request 10 Listing 6 pthread_schedrr_init_np function The implementation of the interrupt handler is shown in Listing 7 The interrupt h
33. queue On the TriCore this can be done in one cycle using the CLZ Count Leading Zeros instruction It is common practice for the kernel routines that set entries in the task ready queue to check the priority of the entry being set against that of the currently running task This allows them to determine if a context switch will be needed If a switch is not required then there is no reason to go to the task dispatcher Therefore when the dispatcher is entered it inherently knows that it will be performing a context switch One of the first things it will do for a TriCore implementation is to save the current value of the PCXI register containing a pointer to the current task s saved context It saves it in an array of PCXI values indexed by the current task s priority ID num ber This can be thought of as a part of the Task Control Block TCB of the current task where the TCB data structure is distributed over multiple arrays indexed in parallel After saving the current context pointer it pro ceeds to examine the task ready queue After the dispatcher disables interrupts it uses the CLZ instruction to find the index number of the highest prior ity ready task If there are no entries in the ready queue the value returned by CLZ will be 32 which is the index for the always enabled system idle task It stores that index in a global variable for reference by other kernel routines then dispatches the task by indexing into the array of saved PCXI
34. re posted interrupt will now be pending at priority level 1 The RFE instruction will effectively operate as a branch to the ISR for priority level 1 which is the task dispatcher itself This second pass through the dispatcher will pick up the newly readied task and dispatch it correctly Application Note 9 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Threads 4 Threads POSIX Threads or Pthreads is a POSIX standard for threads 4 The standard defines an API for creating and manipulating threads Pthreads are most commonly used on Unix like POSIX systems Pthreads defines a set of C programming language types functions and constants It is implemented with a pthread h header and a thread library Programmers can use the library to create manipulate and manage threads as well as synchro nize between threads using mutexes and condition variables This application note implements the most impor tant functions of the pthread library for deeply embedded systems Functions that are not portable because either the parameters are different from the standard or the function does not exist in the standard are marked with the suffix _np 4 1 Getting Started Listing 2 shows a first pthread example running two threads concurrently Two thread control blocks th1 th2 are defined in Lines 2 3 using the macro PTHREAD_CONTROL_BLOCK The threads are set up with priority level 1 a round robin scheduling policy SCHE
35. return control to the task or service routine that was running when the associated interrupt was taken That makes a non preemptive task management kernel simpler and easier to write than a preemptive kernel More importantly it also simplifies certain aspects of the application tasks There is much less need to guard access to shared data through the use of semaphores because each task executes for as long as it needs without concern for preemption For the same reason tasks may call non reentrant functions that use statically allocated temporary variables A further potential advantage of non preemptive scheduling is that interrupt latency can be lower than with pre emptive scheduling Non preemption largely eliminates the need for interrupt lockouts within critical code sec tions In addition the de coupling of interrupts from task scheduling means that interrupt servicing does not go through the kernel and ISRs avoid a level of overhead that they would otherwise incur The overhead of en queuing a task request and exiting through the kernel to get the task dispatched is avoided On the other hand however while the ISR is executing lower priority interrupts are implicitly disabled The ISR is subject to the same non blocking considerations and consequent limitations on inter module messaging that it would have in a bare hardware system Therefore in practice most ISRs remain limited to data capture and posting of event notifications However in
36. riable tin 34 35 pthread running gt lcx mfcr PCXI 36 i pthread_running gt priority 37 switch tin 38 case DISPATCH WAIT _swap out _pthread running 39 list_delete_first amp pthread runnable threads i 40 list append blocked threads ptr pthread running pthread running NULL 41 _ putbit neza pthread_runnable threads i int amp pthread_runnable i 42 break 43 case DISPATCH SIGNAL append blocked threads 44 tmp NULL 45 assert blocked threads ptr 46 thread blocked threads ptr 47 while thread NULL 48 tmp thread gt next 49 i thread gt priority 50 list_append amp pthread_runnable threads i thread thread 51 pthread_runnable threads i 52 putbit 1 int amp pthread runnable 1 53 if thread last thread 54 break 55 thread tmp 56 57 blocked threads ptr tmp 58 break 59 default 60 break 61 62 pthread_start_np Listing 8 thread dispatcher function trapsystem Application Note 16 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Threads 4 6 Condition scheduling The pthread library implements the pthread_cond_timedwait_np function which blocks the thread until the condition is signaled or until a timeout period elapsed To use this function a timer must be initialized by calling pthread_cond_timedwait_init_np Listing 9 The pthread_cond_timedwait_np is a non portable POSIX imple mentation using a rel
37. s the previous context Line 22 to the thread with the highest priority Listing 5 Line 10 before restoring the lower context Line 23 and the upper context by calling Return From Event RFE RFE also enables the interrupt system i e the system timer interrupt used by the round robin scheduler The service request node is only enabled when there is more than 1 thread at the current running priority and the current thread has a round robin scheduling policy Lines 14 17 This avoids the overhead of interrupting the current thread by the system timer when there is no other thread The list handling functions see list_append list_delete_first in pthread c take care of setting the next member to NULL is there is only one list element l inline void pthread start np void 211 3 extern uint32 t pthread_runnable 4 extern pthread_t pthread_running 5 extern pthread t pthread runnable threads PTHREAD PRIO MAX 6 7 pthread t thread 8 9 get ready thread with highest priority ready 10 thread pthread_runnable threads 31 clz pthread_runnable 11 12 check if timer must be enabled if thread policy is SCHED RR 13 and there is another thread with the same priority 14 if thread gt next NULL amp amp thread gt policy SCHED RR 15 STM_SRCO B SRE 1 16 else 17 STM_SRC0 B SRE 0 18 19 PTHREAD_SWAP_HANDLER thread pthread_ running callback hook optional 20 2A
38. ssage from another ISR because it would be implicitly blocking execution of any lower priority ISR that it had interrupted In real time kernel based systems the routines that service hardware interrupts are typically small and fast Their main function is to capture or send data and to notify the task scheduling kernel of any further processing required The bulk of application processing is carried out by tasks running at the background level of the processor i e its normal state when it is not executing an ISR There are two general types of task scheduling in real time kernel based systems e Non preemptive scheduling e Preemptive systems scheduling 2 1 Non Preemptive Scheduling In non preemptive scheduling the kernel never preempts a running task in order to switch to another task Some explicit action is required by the running task for it to give up control of the CPU For example the task may request a resource that is not currently available with an implied request to suspend its execution until the resource becomes available The kernel would then remove the task from the ready queue and look for another task to which to pass control of the CPU Non preemptive scheduling is sometimes referred to as co operative multitasking because tasks co operate with one another to pass control of the CPU A running task can be interrupted but the interrupt will not cause it to lose control of the CPU to another task An ISR will always
39. urn address is initialized to NULL because the threads in this library run forever i e never return Application Note 12 V1 0 2010 03 _ o AP32152 n fi n eon Concurrent multi threaded execution Threads Qe down Thread 1 stack grows Qe Thread 2 stack A ES DIS neue ET A Thread 1 All RA NULL thread never returns Upper Context A10 SP Thread 1 stack address PCXI NULL D7 TN Thread 2 Thread 1 A4 Argument to thread program Lower Context TE code PO Thread 1 program counter PCXI DIS Thread 2 A11 RA NULL thread never returns Upper Context A10 SP Thread 2 stack address PCXI NULL lt x D7 Threaa AL Thread 2 A4 Argument to thread PESE Lower Context as code RE Thread 1 program counter PCXI A T CX PCXI CA a CX fa AAA 0xD0000000 0x80000000 a LDRAM PFLASH Figure 2 Context set up after first 2 threads were created Application Note 13 V1 0 2010 03 a AP32152 n fi n eon Concurrent multi threaded execution Threads 4 3 Starting Threads The function pthread_create_np does not start the thread This is done with the function pthread_start_np In Listing 4 the threads are started after the system timer initialization An initialization of the system timer by pthread_schedrr_init_np is required because of the round robin scheduling policy in the example The function pthread_create_np set
40. w infineon com tricore 3 TC1797 User s Manual V1 1 2009 05 4 The Open Group Base Specifications Issue 6 IEEE Std 1003 1 http www opengroup org 5 Eclox a Doxygen frontend plugin for Ecplise http home gna org eclox and http www doxygen org Application Note 25 V1 0 2010 03
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