Home

UM10147 P89LPC952/954 User manual

Contents

1. UM10147 P89LPC952 954 User manual Rev 02 28 April 2008 User manual Document information Info Content Keywords P89LPC952 P89LPC954 Abstract Technical information for the P89LPC952 954 devices founded by Philips NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Revision history Rev Date Description 02 20080428 Added LQFP48 package information 01 20070917 Initial version Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 2 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual 1 Introduction 1 1 Pin configuration esas oO OO SZ ZZ SZ era o e not a E lg 233835222 Z la III ge ot gc gc ol o rrr Nr OG o oO OO CO oOaeaqdqtereoaoadieaoaoadtreaa 19 oa HISIS P1 3 INTO SDA P0 4 CIN1A KBI4 AD03 P1 2 TO SCL PO 5 CMPREF KBI5 P1 1 RXDO P0 6 CMP1 KBI6 P1 0 TXDO Von P3 1 XTAL1 PO 7 T1 KBI7 P3 0 XTAL2 CLKOUT P89LPC952FA P2 2 MOSI Vpp P89LPC954FA P2 3 MISO P5 7 P2 4 SS P5 6 P2 5 SPICLK P5 5 P4 0 P5 4 P4 1 TRIG COL DIO ml A Oo st Lo Oly Nh oa kel mT OO sii tal o tal ta 002aab307 BN e Sa Sa a LO O O wo gt st E st D GO 0 kg D kg S N Z a o a a Fig 1 PLCC44 pin conf
2. MOSI input Ee S L B DORD 1 B MSB MISO output SS if SSIG bit 0 I I lt a dl Kiesch Gesi Sei 002aaa937 1 Not defined Fig 40 SPI master transfer format with CPHA 1 12 7 SPI clock prescaler select The SPI clock prescalar selection uses the SPR1 SPRO bits in the SPCTL register see Table 77 13 Analog comparators Two analog comparators are provided on the P89LPC952 954 Input and output options allow use of the comparators in a number of different configurations Comparator operation is such that the output is a logic 1 which may be read in a register and or routed to a pin when the positive input one of two selectable pins is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes 13 1 Comparator configuration Each comparator has a control register CMP1 for comparator 1 and CMP2 for comparator 2 The control registers are identical and are shown in Table 83 The overall connections to both comparators are shown in Figure 41 There are eight possible configurations for each comparator as determined by the control bits in the corresponding CMPn register CPn CNn and OEn These configurations are shown in Figure 42 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 93
3. auauua aunn 105 Debugger connections 106 Flash memory 107 General description 107 Features oe cce daad AEN dew de eee beds 107 Flash programming and erase 107 Using Flash as data storage IAP Lite 108 In circuit programming ICP 111 ISP and IAP capabilities of the P89LPC952 954 112 Boot ROM cece eee eee 112 Power on reset code execution 112 Hardware activation of Boot Loader 112 In system programming ISP 113 Using the In system programming ISP 113 In application programming IAP 117 IAP authorization key 117 Flash write enable 117 Configuration byte protection 118 IAP error status 118 User configuration bytes 122 User security bytes uauaanauanan 123 Boot Vector register 4 124 Boot status register 125 Instruction set 126 founded by 19 19 1 19 2 19 3 20 21 22 P89LPC952 954 User manual Legal information 00 0eeeeee 129 Definitions 129 Disclaimers 129 Trademarks 129 Table ee EIERE eae es ees oe ered ee 130 Figoures E ninaa 132 ET EE 133 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2008 All rights reserved For more information
4. Dual channel continuous conversion mode Single step mode NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 26 of 134 NXP Semiconductors UM1 01 47 UM10147_2 3 2 1 3 2 1 1 3 2 1 2 P89LPC952 954 User manual e Three conversion start modes Timer triggered start Start immediately Edge triggered e 10 bit conversion time of 4 us at an A D clock of 9 MHz e Interrupt or polled operation e High and low boundary limits interrupt e Clock divider e Power down mode p CONTROL __ LOGIC 002aab 103 Fig 8 ADC block diagram A D operating modes Fixed channel single conversion mode A single input channel can be selected for conversion A single conversion will be performed and the result placed in the result register pair which corresponds to the selected input channel see Table 7 An interrupt if enabled will be generated after the conversion completes The input channel is selected in the ADINS register This mode is selected by setting the SCANO bit in the ADMODA register Table 7 Input channels and result registers for fixed channel single auto scan single and auto scan continuous conversion modes Result register Input channel Result register Input channel ADODATOR L ADOO ADODAT4R L AD04 ADODAT1R L ADO1 ADODAT5R L ADO5 ADODAT2R L AD02 ADODAT6R L ADO6 ADODATS3R L ADO3 ADODAT7R L AD07 Fixed channel continuous conversion
5. In application programming IAP Several In Application Programming IAP calls are available for use by an application program to permit selective erasing and programming of Flash sectors pages security bits configuration bytes and device id All calls are made through a common interface PGM_MTP The programming functions are selected by setting up the microcontroller s registers before making a call to PGM_MTP at FFO3H The IAP calls are shown in Table 104 IAP authorization key IAP functions which write or erase code memory require an authorization key be set by the calling routine prior to performing the IAP function call This authorization key is set by writing 96H to RAM location FFH The following example was written using the Keil C compiler The methods used to access a specific physical address in memory may vary with other compilers include lt ABSACC H gt enable absolute memory access define key DBYTE OxFF force key to be at address 0xFF short pgm_mtp void OxFF00 set pointer to IAP entry point key 0x96 set the authorization key pgm_mtp execute the IAP function call After the function call is processed by the IAP routine the authorization key will be cleared Thus it is necessary for the authorization key to be set prior to EACH call to PGM_MTP that requires a key If an IAP routine that requires an authorization key is called without a valid authorization key prese
6. jenuew Jost 7S6 2S60d 168d ZVLOLINN SIOJONPUOSIWIS dXN jenuew sn 800z dv 8z ZO wen vELIOGL Z LyLOLWN pamasa Syu Ily 8002 A9 dXN Table 2 Special function registers continued indicates SFRs that are bit addressable Name P2 SCH P4 P5 POM1 POM2 P1M1 P1M2 P2M1 P2M2 P3M1 P3M2 PCON PCONA PSW PTOAD RSTSRC Description SFR addr Bit address Port 2 AOH Bit address Port 3 BOH Port 4 B3H Port 5 B4H Port 0 output 84H mode 1 Port 0 output 85H mode 2 Port 1 output 91H mode 1 Port 1 output 92H mode 2 Port 2 output A4H mode 1 Port 2 output A5H mode 2 Port 3 output B1H mode 1 Port 3 output B2H mode 2 Power control 87H register Power control B5H register A Bit address Program status DOH word Port 0 digital F6H input disable Reset source DFH register Bit functions and addresses Reset value MSB LSB Hex Binary 97 96 95 94 93 92 91 90 S g SPICLK SS MISO MOSI DI B7 B6 B5 B4 B3 B2 B1 BO XTAL1 XTAL2 DI TMS RXD1 TXD1 TRIG T3EX DI T3 DI POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 ERD 114111111 POM2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 00 0000 0000 P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D3U 11x1 xx11 P1M2 7 P1M2 6 d P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 00H 00x0 xx00 p A P2M1 5 P2M1 4
7. 0 87 Additional considerations fora slave 88 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 133 of 134 NXP Semiconductors UM10147 12 3 12 4 12 5 12 6 12 7 13 13 1 13 2 13 3 13 4 13 5 13 6 14 15 15 1 15 2 15 3 15 4 15 5 15 6 16 16 1 16 2 16 3 16 3 17 17 1 17 2 17 3 17 4 17 5 17 6 17 7 17 8 17 9 17 10 17 11 17 12 17 13 17 14 17 15 17 16 17 17 17 18 17 19 17 20 18 Additional considerations for a master 88 Mode change on Ge 88 Write collision 2 20 0005 89 Data mode 89 SPI clock prescaler select 93 Analog comparators 2 2200055 93 Comparator configuration 93 Internal reference voltage 95 Comparator input pins 95 Comparator interrupt s es aaaea 95 Comparators and power reduction modes 95 Comparators configuration example 96 Keypad interrupt KBI 5 97 Watchdog timer NDT 98 Watchdog function 98 Feed sequence eee 99 Watchdog clock source 102 Watchdog Timer in Timer mode 103 Power down operation 104 Periodic wake up from power down without an external oscillator n unnan aana 104 Additional features 104 Software reset 00000 eee eee 105 Dual Data Pointers 105 Debugger interface
8. 111 Reserved User must not configure to this mode 5 7 reserved 8 1 Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler Figure 15 shows Mode 0 operation In this mode the Timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TFn The count input is enabled to the Timer when TRn 1 and either TnGATE 0 or INTn 1 Setting TnGATE 1 allows the Timer to be controlled by external input INTn to facilitate pulse width measurements TRn is a control bit in the Special Function Register TCON Table 40 The TnGATE bit is in the TMOD register UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 49 of 134 NXP Semiconductors UM1 01 47 UM10147_2 8 2 8 3 8 4 8 5 P89LPC952 954 User manual The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear the registers Mode 0 operation is the same for Timer 0 and Timer 1 See Figure 15 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register THn and TLn are used See Figure 16 Mode 2 Mode 2 configures the Timer register as an
9. indicates SFRs that are bit addressable Name IENO IEN1 IEN2 IPO IPOH IP1 IP1H IP2 IP2H KBCON KBMASK KBPATN DO P1 Description SFR addr Interrupt A8H enable 0 Bit address Interrupt E8H enable 1 Interrupt D5H enable 2 Bit address Interrupt B8H priority 0 Interrupt B7H priority 0 high Bit address Interrupt F8H priority 1 Interrupt F7H priority 1 high Interrupt D6H priority 2 Interrupt D7H priority 2 high Keypad control 94H register Keypad 86H interrupt mask register Keypad pattern 93H register Bit address Port 0 80H Bit address Port 1 90H Bit functions and addresses Reset value MSB LSB Hex Binary EA EWDRT EBO ES ESR ET1 EX1 ETO EX0 00 0000 0000 EF EE ED EC EB EA E9 E8 EST ESPI EC EKBI El2C OO 00x0 0000 EST1 ES1 ESR1 EADC ool 00x0 0000 BF BE BD BC BB BA B9 B8 PWDRT PBO PS PSR PT1 PX1 PTO PXO OO x000 0000 PWDRTH PBOH PSH PT1H PX1H PTOH PX0OH ool x000 0000 PSRH FF FE FD FC FB FA F9 F8 PST PSPI PC PKBI PI2C ool 00x0 0000 PSTH PSPIH PCH PKBIH PI2CH ooi 00x0 0000 PEST1 PES1 PADC ool 00x0 0000 PESR1 PEST1H PES1H PADCH ool 00x0 0000 PESR1H z s e PATN KBIF ool XXXX XX00 _SEL 00 0000 0000 FF 1111 1111 87 86 85 84 83 82 81 80 T1 KB7 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B CMP2 Di KB6 KB5 KB4 KB3 KB2 KB1 KBO 97 96 95 94 93 92 91 90 RST INT1 INTO SDA TO SCL RXDO TXDO DI
10. ADCO SPI CC REAL TIME CLOCK SYSTEM TIMER Ge EC PORT 0 PO 0 To CONFIGURABLE I Os d gt KEYPAD eege INTERRUPT WATCHDOG TIMER CH AND OSCILLATOR PROGRAMMABLE CPU OSCILLATOR DIVIDER clock Gees CRYSTAL OR RESONATOR V 1 2 Fig 4 CONFIGURABLE OSCILLATOR 44 pin package 48 pin package Block diagram ON CHIP RC OSCILLATOR WITH CLOCK DOUBLER ANALOG COMPARATORS DEBUGGER INTERFACE POWER MONITOR POWER ON RESET BROWNOUT RESET 002aab305 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 10 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 1 3 Special function registers Remark SFR accesses are restricted in the following ways e User must not attempt to access any SFR locations not defined e Accesses to any defined SFR locations must be strictly for the functions for the SFRs e SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must be written with 0 and will return a 0 when read 1 must be written with 1 and will return a 1 when read UM10147_2 NXP B V 2008 All rights reserved User manu
11. 1F Security Byte 15 89LPC954 Return parameter s R7 status Carry set on error clear on no error UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 120 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 104 IAP function calls continued IAP function IAP call parameters Misc Read Input parameters ACC 03h R7 register address 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 to 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 OC Security Byte A OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 10 Manufacturer Id 11 Device Id 12 Derivative Id 18 Security Byte 8 89LPC954 19 Security Byte 9 89LPC954 1A Security Byte 10 89LPC954 1B Security Byte 11 89LPC954 1C Security Byte 12 89LPC954 1D Security Byte 13 89LPC954 1E Security Byte 14 89LPC954 1F Security Byte 15 89LPC954 Return parameter s R7 register data if no error else error status Carry set on error clear on no error Erase Sector Page Input parameters requires key ACC 04h R4 address MSB R5 address LSB R7 OOH erase page or 01H erase sector Return parameter s R7 data Carry set on error clear on no error UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 121 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table
12. 2 AINO2 When set enables the ADO2 pin for sampling and conversion 3 AINO3 When set enables the ADO3 pin for sampling and conversion 4 AINO4 When set enables the AD04 pin for sampling and conversion 5 AINO5 When set enables the ADO5 pin for sampling and conversion 6 AINO6 When set enables the ADO6 pin for sampling and conversion 7 AINO7 When set enables the ADO7 pin for sampling and conversion Table 19 Boundary status register 0 BNDSTAO address FFEDh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BST07 BST06 BST05 BST04 BST03 BST02 BST01 BSTOO Reset 0 0 0 0 0 0 0 0 Table 20 Boundary status register 0 BNDSTAO address FFEDh bit description Bit Symbol Description 0 BSTOO When set indicates that conversion result for the ADOO pin was inside outside the boundary limits This bit is cleared in software by writing a 1 to this bit 1 BSTO01 When set indicates that conversion result for the ADO1 pin was inside outside the boundary limits This bit is cleared in software by writing a 1 to this bit 2 BST02 When set indicates that conversion result for the ADO2 pin was inside outside the boundary limits This bit is cleared in software by writing a 1 to this bit 3 BST03 When set indicates that conversion result for the ADO3 pin was inside outside the boundary limits This bit is cleared in software by writing a 1 to this bit 4 BST04 When set indicates that conversion result for the AD04 pin was inside outside the bo
13. SIOJONPUODIWIS dXN Z LyLOLWN jenuew sn 800z dv 8z ZO wen pamasa SUD Iv 8002 A9 dXN vEL JOEL Table 2 Special function registers continued indicates SFRs that are bit addressable Name DPH DPL FMADRH FMADRL FMCON FMDATA I2ADR I2CON I2DAT I2SCLH I2SCLL I2STAT SFR addr Description Data pointer 83H high Data pointer 82H low Program flash E7H address high Program flash Een address low Program flash E4H control Read Program flash E4H control Write Program flash E5H data I2C bus slave DBH address register Bit address I2C bus control D8H register l2C bus data DAH register Serial clock DDH generator SCL duty cycle register high Serial clock DCH generator SCL duty cycle register low I2C bus status D9H register Bit address Bit functions and addresses Reset value MSB BUSY FMCMD 7 I2ADR 6 DF STA 4 AF FMCMD 6 I2ADR 5 DE I2EN STA 3 AE FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 70 0111 0000 00 0000 0000 00 0000 0000 00 x000 00x0 00 0000 0000 00 0000 0000 F8 1111 1000 SIOJONPUODIWIS dXN jenuew Jost 7S6 2S6Dd 168d ZVLOLINN jenuew sn 800z dv gz ZO wen vELIOVL Z ZvLOLWN pamasa SUD Ily 8002 A9 dXN Table 2 Special function registers continued
14. The WDRUN bit WDCON 2 can be set to start the WDT and cleared to stop the WDT Following reset this bit will be set and the WDT will be running All writes to WOCON need to be followed by a feed sequence see Section 15 2 Additional bits in WDCON allow the user to select the clock source for the WDT and the prescaler When the timer is not enabled to reset the device on underflow the WDT can be used in timer mode and be enabled to produce an interrupt IENO 6 if desired The Watchdog Safety Enable bit WOSE UCFG1 4 along with WDTE is designed to force certain operating conditions at power up Refer to Table 90 for details UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 98 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Figure 45 shows the watchdog timer in watchdog mode It consists of a programmable 13 bit prescaler and an 8 bit down counter The down counter is clocked decremented by a tap taken from the prescaler The clock source for the prescaler is either PCLK or the watchdog oscillator selected by the WDCLK bit in the WDCON register Note that switching of the clock sources will not take effect immediately see Section 15 3 The watchdog asserts the watchdog reset when the watchdog count underflows and the watchdog reset is enabled When the watchdog reset is enabled writing to WDL or WDCON must be followed by a feed sequence for the new values to take
15. pull up This pull up is used to speed up low to high transitions on a quasi bidirectional port pin when the port latch changes from a logic 0 to a logic 1 When this occurs the strong pull up turns on for two CPU clocks quickly pulling the port pin high The quasi bidirectional port configuration is shown in Figure 10 Although the P89LPC952 954 is a 3 V device most of the pins are 5 V tolerant If 5 V is applied to a pin configured in quasi bidirectional mode there will be a current flowing from the pin to Vpp Causing extra power consumption Therefore applying 5 V to pins configured in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC952 954 data sheet Dynamic characteristics for glitch filter specifications port latch data Fig 10 Quasi bidirectional output 2 CPU CLOCK DELAY P P trong fo ea weak port pin E input data glitch rejection 002aaa914 UM10147_2 5 3 Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port pin when the port latch contains a logic 0 To be used as a logic output a port configured in this manner must have an external pull up typically a resistor tied to Vpp The pull down for this mode is the same as for the quasi b
16. Note If SSIG 1 the operation is not defined 3 CPOL SPI Clock POLarity see Figure 37 to Figure 40 1 SPICLK is high when idle The leading edge of SPICLK is the falling edge and the trailing edge is the rising edge 0 SPICLK is low when idle The leading edge of SPICLK is the rising edge and the trailing edge is the falling edge MSTR Master Slave mode Select see Table 81 DORD SPI Data ORDer 1 The LSB of the data word is transmitted first 0 The MSB of the data word is transmitted first 6 SPEN SPI Enable 1 The SPI is enabled 0 The SPI is disabled and all SPI pins will be port pins 7 SSIG SS IGnore 1 MSTR bit 4 decides whether the device is a master or slave 0 The SS pin decides whether the device is master or slave The SS pin can be used as a port pin see Table 81 Table 78 SPI Status register SPSTAT address Eth bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SPIF WCOL e s Reset 0 0 x D D x x x Table 79 SPI Status register SPSTAT address Eth bit description Bit Symbol Description 0 5 reserved 6 WCOL SPI Write Collision Flag The WCOL bit is set if the SPI data register SPDAT is written during a data transfer see Section 12 5 Write collision The WCOL flag is cleared in software by writing a logic 1 to this bit 7 SPIF SPI Transfer Completion Flag When a serial transfer finishes the SPIF bit is set and an interrupt is gener
17. data is also shifted in the opposite direction simultaneously This means that during one shift cycle data in the master and the slave are interchanged Mode change on SS If SPEN 1 SSIG 0 and MSTR 1 the SPI is enabled in master mode The SS pin can be configured as an input P2M2 4 P2M1 4 00 or quasi bidirectional P2M2 4 P2M1 4 01 In this case another master can drive this pin low to select this device as an SPI NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 88 of 134 NXP Semiconductors UM1 01 47 UM10147_2 12 5 12 6 P89LPC952 954 User manual slave and start sending data to it To avoid bus contention the SPI becomes a slave As a result of the SPI becoming a slave the MOSI and SPICLK pins are forced to be an input and MISO becomes an output The SPIF flag in SPSTAT is set and if the SPI interrupt is enabled an SPI interrupt will occur User software should always check the MSTR bit If this bit is cleared by a slave select and the user wants to continue to use the SPI as a master the user must set the MSTR bit again otherwise it will stay in slave mode Write collision The SPI is single buffered in the transmit direction and double buffered in the receive direction New data for transmission can not be written to the shift register until the previous transaction is complete The WCOL SPSTAT 6 bit is set to indicate data collision when the data register is
18. the device see Section 15 3 Power down mode will also prevent PCLK from running and therefore the watchdog is effectively disabled 15 6 Periodic wake up from power down without an external oscillator Without using an external oscillator source the power consumption required in order to have a periodic wake up is determined by the power consumption of the internal oscillator source used to produce the wake up The Real time clock running from the internal RC oscillator can be used The power consumption of this oscillator is approximately 300 uA Instead if the WDT is used to generate interrupts the current is reduced to approximately 50 uA Whenever the WDT underflows the device will wake up 16 Additional features The AUXR1 register contains several special purpose control bits that relate to several chip features AUXR1 is described in Table 95 Table 94 AUXR1 register address A2h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKLP EBRR ENT1 ENTO SRST 0 DPS Reset 0 0 0 0 0 0 x 0 Table 95 AUXR1 register address A2h bit description Bit Symbol Description 0 DPS Data Pointer Select Chooses one of two Data Pointers 1 Not used Allowable to set to a logic 1 2 0 This bit contains a hard wired 0 Allows toggling of the DPS bit by incrementing AUXR1 without interfering with other bits in the register 3 SRST Software Reset When set by software resets the P89LPC952 954 as ifa hardware reset occurred 4 ENT
19. 1 0 0 0 1 CRSEL is not used for slave mode DEN must be set 1 to enable I2C function AA bit must be set 1 to acknowledge its own slave address or the general call address STA STO and SI are cleared to 0 After I2ADR and I2CON are initialized the interface waits until it is addressed by its own address or general address followed by the data direction bit which is 0 W If the direction bit is 1 R it will enter Slave Transmitter Mode After the address and the direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 75 for the status codes and actions UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 75 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual ne S logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW E from master to slave A not acknowledge SDA HIGH O from slave to master S START condition P STOP condition RS repeated START condition 002aaa932 Fig 30 Format of Slave Receiver mode 11 6 4 Slave Transmitter mode The first byte is received and handled as in the Slave Receiver Mode However in this mode the direction bit will indicate that the transfer direction is reversed Serial data is transmitted via P1 3 SDA while the serial clock is input through P1 2 SCL START and STOP con
20. 1 1 3 2 1 2 3 2 1 3 3 2 1 4 3 2 1 5 3 2 1 6 3 2 2 3 2 3 3 2 3 1 3 2 3 2 3 2 3 3 6 1 6 2 UM10147_2 Introduction 2 0 2 c eee eee eee eee 3 Pin configuration 0 eee eee 3 Pin description 5 Special function registers 11 Memory organization 20 CIOCKS 223 5 etre eee eevee edd EEN E 22 Enhanced CU 22 Clock definitions 0 0 00005 22 Oscillator Clock OSCCLK 22 Low speed oscillator option 22 Medium speed oscillator option 22 High speed oscillator option 22 Clock output 0c eee eee 23 On chip RC oscillator option 23 Watchdog oscillator option 24 External clock input option 24 Oscillator Clock OSCCLK wake up delay 25 CPU Clock CCLK modification DIVM register 26 Low power see 26 A D converter 26 General description 26 A D features 26 A D operating modes 27 Fixed channel single conversion mode 27 Fixed channel continuous conversion mode 27 Auto scan single conversion mode 28 Auto scan continuous conversion mode 28 Dual channel continuous conversion mode 28 Single step mode 29 Conversion mode selection bits 29 Conversion start modes 30 Timer triggered start 30 Start immediately 30 Edge triggered 00005 30 Stopping and restarting conv
21. 1 OE_0 Overrun Error 0 flag is set if a new character is received in the receiver buffer while it is still full before the software has read the previous character from the buffer i e when bit 8 of a new byte is received while RI_O in SOCON is still set Cleared by software 2 BRO Break Detect 0 flag A break is detected when any 11 consecutive bits are sensed low Cleared by software 3 FEO Framing error 0 flag is set when the receiver fails to see a valid STOP bit at the end of the frame Cleared by software 4 DBISEL Double buffering transmit interrupt select 0 Used only if double buffering is _0 enabled This bit controls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to SOBUF and there is also one more transmit interrupt generated at the beginning INTLO_0 0 or the end INTLO_0 1 of the STOP bit of the last character sent i e no more data in buffer This last interrupt can be used to indicate that all transmit operations are over When cleared 0 only one transmit interrupt is generated per character written to SOBUF Must be logic 0 when double buffering is disabled Note that except for the first character written when buffer is empty the location of the transmit interrupt is determined by INTLO 0 When the first character is written the transmit interrupt is generated immediately after SOBUF is written 5 CIDIS_
22. 104 IAP function calls continued IAP function IAP call parameters Read Sector CRC Input parameters ACC 05h R7 sector address Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read Global CRC Input parameters ACC 06h Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read User Code Input parameters ACC 07h R4 address MSB R5 address LSB Return parameter s R7 data 17 17 User configuration bytes A number of user configurable features of the P89LPC952 954 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of an Flash byte UCFG1 shown in Table 106 Table 105 Flash User Configuration Byte 1 UCFG1 bit allocation Bit 7 6 5 4 3 2 1 0 Symbol WDTE RPE BOE WDSE CLKDBL FOSC2 FOSC1 FOSCO Unprogrammed 0 1 0 0 0 0 1 1 value Table 106 Flash User Configuration Byte 1 UCFG1 bit description Bit Symbol Description 0 FOSCO CPU oscillator type select See Section 2 Clocks for additional information Combinations other than those FOSC1 shown in Table 107 are reserved for future use should not be used A 2 FOSC2 3 CLKDBL Clock doubler When set doubles
23. 125 of 134 NXP Semiconductors UM10147 18 Instruction set P89LPC952 954 User manual Table 117 Instruction set summary Mnemonic Description Bytes Cycles Hex code ARITHMETIC ADD A Rn Add register to A 1 1 28 to 2F ADD Adr Add direct byte to A 2 1 25 ADD A Ri Add indirect memory to A 1 1 26 to 27 ADD A data Add immediate to A 2 1 24 ADDC A Rn Add register to A with carry 1 1 38 to 3F ADDC A dir Add direct byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 to 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 to 9F SUBB A dir Subtract direct byte from A with borrow 2 1 95 SUBB A Ri Subtract indirect memory from A with 1 1 96 to 97 borrow SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 to OF INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 to 07 DECA Decrement A 1 1 14 DEC Rn Decrement register 1 1 18 to 1F DEC dir Decrement direct byte 2 1 15 DEC Ri Decrement indirect memory 1 1 16 to 17 INC DPTR Increment data pointer 1 2 A3 MUL AB Multiply A by B 1 4 A4 DIV AB Divide A by B 1 4 84 DAA Decimal Adjust A 1 1 D4 LOGICAL ANL A Rn AND register to A 1 1 58 to 5F ANL A dir AND direct byte to A 2 1 55 ANL A Ri AND indirect memory to A 1 1 56 to 57 ANL A data AND immediate to A 2 1 54 ANL dir A AND A to direct
24. 385 41 0 ms 2 73 ms 010 0 129 322 5 us 21 5 us 255 32 769 81 9 ms 5 46 ms 011 0 257 642 5 us 42 8 us 255 65 537 163 8 ms 10 9 ms 100 0 513 1 28 ms 85 5 us 255 131 073 327 7 ms 21 8 ms 101 0 1 025 2 56 ms 170 8 us 255 262 145 655 4 ms 43 7 ms UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 101 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 93 Watchdog timeout vales continued PRE2 to PREO 110 111 WDL in decimal Timeout Period Watchdog Clock Source in watchdog clock 400 KHz Watchdog 12 MHz CCLK 6 MHz cycles Oscillator Clock CCLK Watchdog Nominal Clock 0 2 049 5 12 ms 341 5 us 255 524 289 1 315 87 4 ms 0 4097 10 2 ms 682 8 us 255 1 048 577 2 62s 174 8 ms 15 3 UM10147_2 Watchdog clock source The watchdog timer system has an on chip 400 KHz oscillator The watchdog timer can be clocked from either the watchdog oscillator or from PCLK refer to Figure 43 by configuring the WDCLK bit in the Watchdog Control Register WDCON When the watchdog feature is enabled the timer must be fed regularly by software in order to prevent it from resetting the CPU After changing WDCLK WDCON 0 switching of the clock source will not immediately take effect As shown in Figure 45 the selection is loaded after a watchdog feed sequence In addition due to clock synchronization logic it can take two old clock cycles before the old clock source i
25. 8 bit Counter TLn with automatic reload as shown in Figure 17 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 Mode 3 When Timer 1 is in Mode 3 it is stopped The effect is the same as setting TR1 0 Timer 0 in Mode 3 establishes TLO and THO as two separate 8 bit counters The logic for Mode 3 on Timer 0 is shown in Figure 18 TLO uses the Timer 0 control bits TOC T TOGATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P89LPC952 954 device can look like it has three Timer Counters Note When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it into and out of its own Mode 3 It can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks see Figure 19 Its structure is similar to mode 2 except that e TFn n 0 and 1 for Timers 0 and 1 respectively is set and cleared in hardware e The low period of the TFn is in THn and should be between 1 and 254 and e The high peri
26. 96h bit allocation 23 address 8Fh bit allocation 49 Table 6 On chip RC oscillator trim register TRIM Table 38 Timer Counter Auxiliary Mode register TAMOD address 96h bit description 24 address 8Fh bit description 49 Table 7 Input channels and result registers for fixed Table 39 Timer Counter Control register TCON address channel single auto scan single and auto scan 88h bit allocation 51 continuous conversion modes 27 Table 40 Timer Counter Control register TCON address Table 8 Result registers and conversion results for fixed 88h bit description 51 channel continuous conversion mode 28 Table 41 Real time Clock System Timer clock sources 54 Table 9 Result registers and conversion results for dual Table 42 Real time Clock Control register RTCCON channel continuous conversion mode 29 address Dth bit allocation 55 Table 10 Conversion mode bit 29 Table 43 Real time Clock Control register RTCCON Table 11 A D Control register 0 ADCONO address 97h address Dth bit description 56 bit allocation 020002 eee ee 31 Table 44 UART SFR addresses n nananana 57 Table 12 A D Control register 0 ADCONO address 97h Table 45 UART baud rate generation 58 bit description 31 Table 46 Baud Rate Generator Control register Table 13 A D Mode register A ADMODA
27. C Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPLC Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C bit AND direct bit to carry 2 2 82 ANL C bit AND direct bit inverse to carry 2 2 BO ORL C bit OR direct bit to carry 2 2 72 ORL C bit OR direct bit inverse to carry 2 2 AO MOV C bit Move direct bit to carry 2 1 A2 MOV bit C Move carry to direct bit 2 2 92 BRANCHING ACALL addr 11 Absolute jump to subroutine 2 2 116F1 LCALL addr 16 Long jump to subroutine 3 2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LUMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump relative address 2 2 80 JC rel Jump on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 10 JMP A DPTR Jump indirect relative DPTR 1 2 73 JZ rel Jump on accumulator 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relative 3 2 B8 to BF CJNE Ri d rel Compare indirect immediate jne relative 3 2 B6 to B7 DJNZ Rn rel Decrement register jnz relative 2 2 D8 to DF DJNZ dir rel Decrement direct byte jnz relative 3 2 D5 MISCELLANEOUS NOP No operation 1 1 00 UM10147_2
28. CLKOUT pin when the crystal oscillator is not being used This condition occurs if a different clock source has been selected on chip RC oscillator watchdog oscillator external clock input on X1 and if the Real time Clock is not using the crystal oscillator as its clock source This allows external devices to synchronize to the P89LPC952 954 This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power Note on reset the TRIM SFR is initialized with a factory preprogrammed value Therefore when setting or clearing the ENCLK bit the user should retain the contents of other bits of the TRIM register This can be done by reading the contents of the TRIM register into the ACC for example modifying bit 6 and writing this result back into the TRIM register Alternatively the ANL direct or ORL direct instructions can be used to clear or set bit 6 of the TRIM register 2 4 On chip RC oscillator option The P89LPC952 has a 6 bit TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 at room temperature Note the initial value is better than 1 please refer to the P89LPC952 954 data sheet for behavior over temper
29. Dual channel continuous 1 0 0 Auto scan continuous UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 29 of 134 NXP Semiconductors UM1 01 47 UM10147_2 3 2 3 3 2 3 1 3 2 3 2 3 2 3 3 3 2 4 3 2 5 3 2 6 P89LPC952 954 User manual Conversion start modes Timer triggered start An A D conversion is started by the overflow of Timer 0 Once a conversion has started additional Timer 0 triggers are ignored until the conversion has completed The Timer triggered start mode is available in all A D operating modes This mode is selected by the TMMx bit and the ADCS01 and ADCS00 bits see Table 12 and Table 14 Start immediately Programming this mode immediately starts a conversion This start mode is available in all A D operating modes This mode is selected by setting the ADCS01 and ADCS00 bits in the ADCONDO register See Table 12 and Table 14 Edge triggered An A D conversion is started by rising or falling edge of P1 4 Once a conversion has started additional edge triggers are ignored until the conversion has completed The edge triggered start mode is available in all A D operating modes This mode is selected by setting the ADCS01 and ADCS00 bits in the ADCONO register See Table 12 and Table 14 Stopping and restarting conversions An A D conversion or set of conversions can be stopped by clearing the ADCS01 and ADCS00 bits in ADCONO and also the TMM0 b
30. FFFFH ADODATO 9 2 00 0000 0000 MSB ADODAT1R ADCO data register 1 right FFFCH ADODAT1 7 0 00 0000 0000 LSB ADODATIL ADCO data register 1 left FFFDH ADODAT1 9 2 00 0000 0000 MSB ADODAT2R ADCO data register 2 right FFFAH ADODAT2 7 0 00 0000 0000 LSB ADODAT2L ADCO data register 2 left FFFBH ADODAT2 9 2 00 0000 0000 MSB ADODAT3R ADCO data register 3 right FFF8H ADODATS3 7 0 00 0000 0000 LSB ADODAT3L ADCO data register 3 left FFF9H ADODAT3 9 2 00 0000 0000 MSB ADODAT4R ADCO data register 4 right FFF6H ADODAT4 7 0 00 0000 0000 LSB ADODAT4L ADCO data register 4 left FFF7H ADODAT4 9 2 00 0000 0000 MSB ADODAT5R ADCO data register 5 right FFF4H ADODATS 7 0 00 0000 0000 LSB ADODAT5L ADCO data register 5 left FFF5H ADODAT5 9 2 00 0000 0000 MSB ADODAT6R ADCO data register 6 right FFF2H ADODATE6 7 0 00 0000 0000 LSB ADODAT6L ADCO data register 6 left FFF3H ADODATE6 9 2 00 0000 0000 MSB ADODAT7R ADCO data register 7 right FFFOH ADODAT7 7 0 LSB Jenuew Joer 7S6 2S6Dd 168d ZVLOLINN SIOJONPUODIWIBS dXN jenuew sn 800z dv gz ZO wen vel JO GL Z ZyLOLWN pamasa SUD Iv 8002 A9 dXN Table 3 Extended special function registers continued Name ADODAT7L BNDSTAO BRGCON_1 BRGO_1 BRG1_1 FREEZE P4M1 P4M2 P5M1 P5M2 S1ADDR S1ADEN 1BUF Description ADCO data register 7 left MSB ADCO boundary status register Baud rate ge
31. Fig1 PLCC44pinconfiguration 3 Fig 47 Forcing ISP mode 0 005 113 Fig 2 LQFP44 pin configuration 4 Fig 3 LOQFP48 pin configuration 5 Fig 4 Block diagram 0 eee eee eee 10 Fig 5 P89LPC952 memory map P89LPC954 is similar 20 Fig 6 Using the crystal oscillator 25 Fig 7 Block diagram of oscillator control 25 Fig 8 ADC block diagram sss aasaua ananunua 27 Fig 9 Interrupt sources interrupt enables and power down wake up sources e 36 Fig 10 Quasi bidirectional out 38 Fig 11 Open drain output 0 39 Fig 12 Input only 39 Fig 13 Push pull output 00 00085 40 Fig 14 Block diagram of reset 47 Fig 15 Timer counter 0 or 1 in Mode 0 13 bit counter Di Fig 16 Timer counter 0 or 1 in mode 1 16 bit counter Di Fig 17 Timer counter 0 or 1 in Mode 2 8 bit auto reload 52 Fig 18 Timer counter 0 Mode 3 two 8 bit counters 52 Fig 19 Timer counter 0 or 1 in mode 6 PWM auto reload 52 Fig 20 Real time clock system timer block diagram 53 Fig 21 Baud rate generation for UARTs Modes 1 3 59 Fig 22 Serial Port Mode 0 double buffering must be disabled 0 0 0 cece 63 Fig 23 Serial Port Mode 1 only single transmit buffering case is Shown 64 Fig 24 Serial Port Mode 2 or 3 only single transmit buffering case is sbown 64 Fig 25
32. NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 128 of 134 NXP Semiconductors UM10147 19 Legal information P89LPC952 954 User manual 19 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 19 2 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof UM10147_2 Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malf
33. O pins available Clock source Reset option Number of UO pins On chip oscillator or watchdog No external reset except during power up 40 oscillator External RST pin supported 39 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 36 of 134 NXP Semiconductors UM1 01 47 UM10147_2 5 1 5 2 P89LPC952 954 User manual Table 23 Number of I O pins available continued Clock source Reset option Number of UO pins External clock input No external reset except during power up 39 External RST pin supported 38 Low medium high speed oscillator No external reset except during power up 38 external crystal or resonator External RST pin supported 37 1 Required for a clock frequency above 12 MHz Port configurations All but three I O port pins on the P89LPC952 954 may be configured by software to one of four types on a pin by pin basis as shown in Table 24 These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin P1 5 RST can only be an input and cannot be configured P1 2 SCL TO and P1 3 SDA INTO may only be configured to be either input only or open drain Table 24 Port output configuration settings PxM1 y PxM2 y Port output mode 0 0 Quasi bidirectional 0 1 Push pull 1 0 Input only high impedance 1 1 Open drain Quasi
34. Slave output input input Selected as slave 1 0 1 0 Slave Hi Z input input Not selected MISO is high impedance to avoid bus contention 1 0 0 1 gt Slave output input input P2 4 SS is configured as an input or 0 2 quasi bidirectional pin SSIG is 0 Selected externally as slave if SS is selected and is driven low The MSTR bit will be cleared to logic 0 when SS becomes low UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 87 of 134 NXP Semiconductors UM1 01 47 Table 81 P89LPC952 954 User manual SPI master and slave selection continued SPEN SSIG SSPin MSTR Master MISO MOSI _ SPICLK Remarks 1 1 1 1 P2 4l1 P2 40 or Slave Mode 1 Master input Hi Hi Z MOSI and SPICLK are at high impedance to idle avoid bus contention when the MAster is idle The application must pull up or pull down SPICLK depending on CPOL SPCTL 3 to avoid a floating SPICLK N Master output output MOSI and SPICLK are push pull when the active Master is active 0 Slave output input input 1 Master input output output 1 Selected as a port function 2 The MSTR bit changes to logic 0 automatically when SS becomes low in input mode and SSIG is logic 0 UM10147_2 12 2 12 3 12 4 Additional considerations for a slave When CPHA equals zero SSIG must be logic 0 and the SS pin must be negated and reasserted between each successive serial byte If the SPDAT register is writt
35. When the cycle is completed code execution resumes If an interrupt occurs during an erase programming or CRC cycle the erase programming or CRC cycle will be aborted so that the Flash memory can be used as the source of instructions to service the interrupt An IAP error condition will be flagged by setting the carry flag and status information returned The status information returned is shown in Table 103 If the application permits interrupts during erasing programming or CRC cycles the user code should check the carry flag after each erase programming or CRC operation to see if an error occurred If the operation was aborted the user s code will need to repeat the operation NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 118 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 103 IAP error status Bit Flag Description 0 Ol Operation Interrupted Indicates that an operation was aborted due to an interrupt occurring during a program or erase cycle 1 SV Security Violation Set if program or erase operation fails due to security settings Cycle is aborted Memory contents are unchanged CRC output is invalid 2 HVE High Voltage Error Set if error detected in high voltage generation circuits Cycle is aborted Memory contents may be corrupted 3 VE Verify error Set during IAP programming of user code if the contents of the programmed address does not agree with t
36. amp bits toggle TRO aa C To pin Gate P1 2 open drain INTO pin ENTO AUXR1 4 overflow Osc 2 om THO TF1 interrupt control _ 8 bits toggle Ba Get O T1 pin P0 7 ENT1 AUXR1 5 002aaa922 Fig 18 Timer counter 0 Mode 3 two 8 bit counters Si overflow PCLK _ A on TFn gt interrupt ES Control reload THn on falling transition and 256 THn on rising transition toggle TRn a C Tn pin Gate THn INTn pin 8 bits ENTn 002aaa923 Fig 19 Timer counter 0 or 1 in mode 6 PWM auto reload 8 6 Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs and PWM outputs are also used for the timer toggle outputs This function is enabled by UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 52 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual control bits ENTO and ENT1 in the AUXR1 register and apply to Timer 0 and Timer 1 respectively The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on In order for this mode to function the C T bit must be cleared selecting PCLK as the clock source for the timer 9 Real time clock system timer The P89LPC952 954 has a simple Real time Clock System Timer that allows a user to continue running an ac
37. and 2 CMF1 CMF2 0043h EC IEN1 2 IPOH 0 IP0 0 11 Yes interrupts SPI interrupt SPIF 004Bh ESPI IEN1 3 IP1H 3 IP1 3 14 No Serial port 0 Tx TIO 006Bh EST IEN1 6 IPOH 0 IP0 0 12 No Data EEPROM 0073h EAD IEN1 7 IP1H 7 IP1 7 15 No A D converter ADCIO BNDI1 0083h EADC IEN2 1 IP2H 1 IP2 1 16 lowest No Serial port 1 Tx and Rx TI and RI_1 008Bh ES1 ESR1 IP2H 2 IP2 2 17 No Serial port 1 Rx RL 1 IEN2 2 Serial port 1 Tx TL1 0093h EST1 IEN2 3 IP2H 3 IP2 3 18 No UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 35 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual IEO EX0 EX1 nl EBO k wake up RTCF gt KBIF if in power down ERTC EKBI RTCCON 1 AROYE EWDRT CMF2 CMF1 EC EA IEO 7 TFO ETO TET ET1 TI_O and RI_O RI_O ES ESR TLO j interrupt EST to CPU SI EC SPIF ESPI TI_1 and RI_1 RI_1 TWA EST iihi ENADCIO ADCIO ENBIO BNDIO EAR 002aab408 Fig 9 Interrupt sources interrupt enables and power down wake up sources 5 I O ports The P89LPC952 954 has four I O ports Port 0 Port 1 Port 2 Port 3 Port 4 and Port 5 Ports 0 1 4 and 5 are 8 bit ports Port 2 is a 6 bit port and Port 3 is a 2 bit port The exact number of I O pins available depends upon the clock and reset options chosen see Table 23 Table 23 Number of I
38. be generated if and only if the following conditions are met at the time the final shift pulse is generated Rl_n 0 and either SM2_n 0 or the received stop bit 1 If either of these two conditions is not met the received frame is lost If both conditions are met the stop bit goes into RB8_n the 8 data bits go into SOBUF and RI_n is activated UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 63 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual TX clock fl fl fl fl fl fl fl fl jl fl fl fl fl fl write to fl SBUF shift ji fl fl fl fl fl fl fl fl transmit tart TXB w Lo X XXX XXe X Y stop bi TI d KO INTLO 0 INTLO 1 clock sa RXD awai i Lo XXE X XEXE Xe XL Y stop RI receive 002aaa926 Fig 23 Serial Port Mode 1 only single transmit buffering case is shown 10 12 More about UART Modes 2 and 3 Reception is the same as in Mode 1 The signal to load SOBUF and RB8_n and to set RI_n will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI_n 0 and b Either SM2_n 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is lost and RI_n is not set If both conditions are met the received 9th data bit goes into RB_n and the first 8 data bits go into SnBUF write to fl SBUF shift j j I j tr
39. byte 2 1 52 ANL dir data AND immediate to direct byte 3 2 53 ORL A Rn OR register to A 1 1 48 to 4F ORL A dir OR direct byte to A 2 1 45 ORL A Ri OR indirect memory to A 1 1 46 to 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 126 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual Table 117 Instruction set summary continued Mnemonic Description Bytes Cycles Hex code XRL A Pn Exclusive OR register to A 1 1 68 to 6F XRL A dir Exclusive OR direct byte to A 2 1 65 XRL A Ri Exclusive OR indirect memory to A 1 1 66 to 67 XRL A data Exclusive OR immediate to A 2 1 64 XRL dir A Exclusive OR A to direct byte 2 1 62 XRL dir data Exclusive OR immediate to direct byte 3 2 63 CLRA Clear A 1 1 E4 CPLA Complement A 1 1 F4 SWAP A Swap Nibbles of A 1 1 C4 RLA Rotate A left 1 1 23 RLC A Rotate A left through carry 1 1 33 Rotate A right RRA 1 1 03 RRC A Rotate A right through carry 1 1 13 DATA TRANSFER MOV A Rn Move register to A 1 1 E8 to EF MOV A dir Move direct byte to A 2 1 E5 Move indirect memory to A MOV A Ri 1 1 E6 to E7 MOV A data Move immediate to A 2 1 74 MOV Rn A Move A to register 1 1 F8 to FF MOV Pn dir Move direct byte to register 2 2 A8 to AF MOV Rn data Move immediate to register 2 1 78 to 7F MOV dir A Move A
40. configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations All pins have Schmitt triggered inputs Port 3 also provides various special functions as described below P3 0 Port 3 bit 0 XTAL2 Output from the oscillator amplifier when a crystal oscillator option is selected via the flash configuration CLKOUT CPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 It can be used if the CPU clock is the internal RC oscillator watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the RTC system timer P3 1 Port 3 bit 1 XTAL1 Input to the oscillator circuit and internal clock generator circuits when selected via the flash configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source and if XTAL1 XTAL2 are not used to generate the clock for the RTC system timer Port 4 Port 4 is an 8 bit I O port with a user configurable output type During reset Port 4 latches are configured in the input only mode with the internal pull up disabled The operation of Port 4 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations All pins have Schmitt triggered inputs Port 4 also provides various special functions as described below NX
41. disabled i e SPEN SPCTL 6 0 reset value Ifthe SPI is configured as a master i e MSTR SPCTL 4 1 and P2 4 is configured as an output via the P2M1 4 and P2M2 4 SFR bits Ifthe SS pin is ignored i e SSIG SPCTL 7 bit 1 this pin is configured for port functions Note that even if the SPI is configured as a master MSTR 1 it can still be converted to a slave by driving the SS pin low if P2 4 is configured as input and SSIG 0 Should this happen the SPIF bit SPSTAT 7 will be set see Section 12 4 Mode change on SS Typical connections are shown in Figure 34 to Figure 36 Table 76 SPI Control register SPCTL address E2h bit allocation Bit 7 6 5 4 3 2 Symbol SSIG SPEN DORD MSTR CPOL CPHA Reset 0 0 0 0 0 1 1 0 SPR1 SPRO 0 0 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 84 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual Table 77 SPI Control register SPCTL address E2h bit description Bit Symbol Description 0 SPRO SPI Clock Rate Select 1 SPRI SPR1 SPRO 00 CCLKy 01 CCLKY 6 10 ba 11 CCLKy 28 2 CPHA SPI Clock PHAse select see Figure 37 to Figure 40 1 Data is driven on the leading edge of SPICLK and is sampled on the trailing edge 0 Data is driven when SS is low SSIG 0 and changes on the trailing edge of SPICLK and is sampled on the leading edge
42. effect If a watchdog reset occurs the internal reset is active for at least one watchdog clock cycle PCLK or the watchdog oscillator clock If CCLK is still running code execution will begin immediately after the reset cycle If the processor was in Power down mode the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable Table 90 Watchdog timer configuration WDTE WDSE FUNCTION 0 x The watchdog reset is disabled The timer can be used as an internal timer and can be used to generate an interrupt WDSE has no effect 1 0 The watchdog reset is enabled The user can set WDCLK to choose the clock source 1 1 The watchdog reset is enabled along with additional safety features 1 WDCLK is forced to 1 using watchdog oscillator 2 WDCON and WDL register can only be written once 3 WDRUN is forced to 1 Watchdog oscillator PCLK PRE2 PRE1 PREO WDCLK after a Watchdog feed DECODE Fig 43 Watchdog Prescaler TO WATCHDOG DOWN COUNTER after one prescaler count delay 002aaa938 UM10147_2 15 2 Feed sequence The watchdog timer control register and the 8 bit down counter See Figure 44 are not directly loaded by the user The user writes to the WDCON and the WDL SFRs At the end of a feed sequence the values in the WDCON and WDL SFRs are loaded to the control register and the 8 bit down counter Before the feed
43. high I2SCLL defines the number of PCLK cycles for SCL low The frequency is determined by the following formula Bit Frequency freck 2 IZSCLH I2SCLL Where fpcux is the frequency of PCLK NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 72 of 134 NXP Semiconductors UM1 01 47 UM10147_2 11 6 11 6 1 P89LPC952 954 User manual The values for l2SCLL and I2SCLH do not have to be the same the user can give different duty cycles for SCL by setting these two registers However the value of the register must ensure that the data rate is in the DC data rate range of 0 to 400 kHz Thus the values of I2SCLL and I2SCLH have some restrictions and values for both registers greater than three PCLKs are recommended Table 69 12C clock rates selection Bit data rate Kbit sec at fosc I2SCLL CRSEL 7 373 MHz 3 6865 MHz 1 8433 MHz 12 MHz 6 MHz I2SCLH 6 0 307 154 7 0 263 132 8 0 230 115 375 9 0 205 102 333 10 0 369 184 92 300 15 0 246 123 61 400 200 25 0 147 74 37 240 120 30 0 123 61 31 200 100 50 0 74 37 18 120 60 60 0 61 31 15 100 50 100 0 37 18 9 60 30 150 0 25 12 6 40 20 200 0 18 9 5 30 15 1 3 6 Kbps to 1 8Kbpsto 0 9Kbpsto 5 86Kbpsto 2 93 Kbps to 922 Kbps 461 Kbps 230 Kbps 1500 Kbps 750 Kbps Timer 1 in Timer 1 in Timer 1 in Timer 1 in Timer 1 in mode 2 mode 2 mode 2 mode 2 mode 2 I2C operation modes Master Transmit
44. high voltage generator FMCMD 2 W Command byte bit 2 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 109 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual Table 100 Flash Memory Control register FMCON address E4h bit description continued Bit Symbol Access Description 3 HVA R High voltage abort Set if either an interrupt or a brown out is detected during a program or erase cycle Also set if the brown out detector is disabled at the start of a program or erase cycle FMCMD 3 W Command byte bit 3 4 7 R reserved 4 7 FMCMD 4 W Command byte bit 4 4 7 FMCMD 5 W Command byte bit 5 4 7 FMCMD 6 W Command byte bit 6 4 7 FMCMD 7 W Command byte bit 7 An assembly language routine to load the page register and perform an erase program operation is shown below RERE SERRE EE ch pgm user code RE EELE EERE EK RRA ERRE ES ERE LEELA ER ES EERE RE ERR AK Inputs R3 number of bytes to program byte R4 page address MSB byte j R5 page address LSB byte R7 pointer to data buffer in RAM byte Outputs 5 R7 status byte S C clear on no error set on error KR P a a a a LOAD EQU 00H EP EQU 68H PGM_USER OV FMCON LOAD load command clears page register OV FMADRH R4 get high address DV FMADRL R5 get low address MOV A R7 i OV RI A get pointer into R0 LOAD_PAGE OV FMDAT R0 write data to page regi
45. interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are pending at the start of an instruction cycle an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used for pending requests of the same priority level Table 22 summarizes the interrupt sources flag bits vector addresses enable bits priority bits arbitration ranking and whether each interrupt may wake up the CPU from a Power down mode Interrupt priority structure Table 21 Interrupt priority level Priority bits IPXH IPx Interrupt priority level 0 0 Level 0 lowest priority 0 1 Level 1 1 0 Level 2 1 1 Level 3 There are four SFRs associated with the four interrupt levels IPO IPOH IP1 IP1H Every interrupt has two bits in IPx and IPXH x 0 1 and can therefore be assigned to one of four levels as shown in Table 22 The P89LPC952 954 has two external interrupt inputs in addition to the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers These external interrupts can be programmed to be level triggered or edge triggered by clearing or setting bit IT1 o
46. is done via the BOPD PCON 5 bit bit field PMOD1 PMODO PCON 1 0 and user configuration bit BOE UCFG1 5 If BOE is in an unprogrammed state brownout is disabled regardless of PMOD1 PMODO and BOPD If BOE is in a programmed state PMOD1 PMODO0O and BOPD will be used to determine whether Brownout Detect will be disabled or enabled PMOD1 PMODO0 is used to select the power reduction mode If PMOD1 PMODO0 11 the circuitry for the Brownout Detection is disabled for lowest power consumption BOPD defaults to logic 0 indicating brownout detection is enabled on power on if BOE is programmed H Brownout Detection is enabled the brownout condition occurs when Vpp falls below the Brownout trip voltage VBO see P89LPC952 954 data sheet Static characteristics and is negated when Von rises above VBO If the P89LPC952 954 device is to operate with a power supply that can be below 2 7 V BOE should be left in the unprogrammed state so that the device can operate at 2 4 V otherwise continuous brownout reset may prevent the device from operating If Brownout Detect is enabled BOE programmed PMOD1 PMOD0 11 BOPD 0 BOF RSTSRC 5 will be set when a brownout is detected regardless of whether a reset or an interrupt is enabled BOF will stay set until it is cleared in software by writing a logic 0 to the bit Note that if BOE is unprogrammed BOF is meaningless If BOE is programmed and a initial power on occurs BOF will be set in addi
47. ni will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SnADDR and the address mask SnADEN SnADEN is used to define which bits in the SnADDR are to be used and which bits are don t care The SnADEN mask can be logically ANDed with the SnADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Table 60 Slave 0 1 examples Example 1 Example 2 Slave 0 SnADDR 11000000 Slave 1 SnADDR 11000000 SnADEN 11111101 SnADEN 1111 1110 Given 1100 00X0 Given 1100 000X In the above example SnADDR is the same and the SnADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requi
48. of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service Table 82 Comparator Control register CMP1 address ACh CMP2 address ADh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CEn CPn CNn OEn COn CMFn Reset X D 0 0 0 0 0 0 Table 83 Comparator Control register CMP1 address ACh CMP2 address ADh bit description Bit Symbol Description 0 CMFn Comparator interrupt flag This bit is set by hardware whenever the comparator output COn changes state This bit will cause a hardware interrupt if enabled Cleared by software COn Comparator output synchronized to the CPU clock to allow reading by software 2 OEn Output enable When logic 1 the comparator output is connected to the CMPn pin if the comparator is enabled CEn 1 This output is asynchronous to the CPU clock 3 CNn Comparator negative input select When logic 0 the comparator reference pin CMPREF is selected as the negative comparator input When logic 1 the internal comparator reference Vref is selected as the negative comparator input 4 CPn
49. operation If the factory default setting for the Boot Vector is changed it will no longer point to the factory pre programmed ISP boot loader code If this happens the only way it is possible to change the contents of the Boot Vector is through the parallel or ICP programming method provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and Boot Status Bit After programming the Flash the status byte should be programmed to zero in order to allow execution of the user s application code beginning at address 0000H tvr RST t RESE 002aaa912 Fig 47 Forcing ISP mode In system programming ISP In System Programming is performed without removing the microcontroller from the system The In System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC952 954 through the serial port This firmware is provided by NXP and embedded within each P89LPC952 954 device The NXP In System Programming facility has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins Vpp Vss TXDO RXDO and RST Only a small connector needs to be available to interface your application to an external circuit in order to use this feature Using the In system p
50. program idle state is exited FMCON will contain status information for the cycle If an interrupt occurs during an erase programming cycle the erase programming cycle will be aborted and the Ol flag Operation Interrupted in FMCON will be set If the application permits interrupts during erasing programming the user code should check the NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 108 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Ol flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user s code will need to repeat the process starting with loading the page register The erase program cycle takes 4 ms 2 ms for erase 2 ms for programming to complete regardless of the number of bytes that were loaded into the page register Erasing programming of a single byte or multiple bytes in code memory is accomplished using the following steps e Write the LOAD command 00H to FMCON The LOAD command will clear all locations in the page register and their corresponding update flags Write the address within the page register to FMADRL Since the loading the page register uses FMADRL 5 0 and since the erase program command uses FMADRH and FMADRL 7 6 the user can write the byte location within the page register FMADRL 5 0 and the code memory page address FMADRH and FMADRL 7 6 at this time Write
51. register SPDAT address E3h bit allocation EE 86 Table 81 SPI master and slave selection 87 Table 82 Comparator Control register CMP1 address ACh CMP2 address ADh bit allocation 94 Table 83 Comparator Control register CMP1 address ACh CMP2 address ADh bit description 94 Table 84 Keypad Pattern register KBPATN address 93h bit allocation 2200022 0 eee 97 Table 85 Keypad Pattern register KBPATN address 93h bit description 97 Table 86 Keypad Control register KBCON address 94h bit allocation s n nananana 97 Table 87 Keypad Control register KBCON address 94h bit description 97 Table 88 Keypad Interrupt Mask register KBMASK address 86h bit allocation 98 Table 89 Keypad Interrupt Mask register KBMASK address 86h bit description 98 Table 90 Watchdog timer configuration 99 Table 91 Watchdog Timer Control register WDCON address A7h bit allocation 101 Table 92 Watchdog Timer Control register WDCON address A7h bit description 101 Table 93 Watchdog timeout vales 101 Table 94 AUXR1 register address A2h bit allocation 104 Table 95 AUXR1 register address A2h bit description P89LPC952 954 User manual Table 101 Boot loader address and default Boot vector 112 Table 102 In system Programming ISP hex record formats 115 Table 103 IAP err
52. sequence to load the WDL to the 8 bit down counter and the WDCON to the shadow register If writing to the WDCON register is not immediately followed by the feed sequence a watchdog reset will occur For example setting WDRUN 1 OV ACC WDCON get WDCON SETB ACC 2 eet WD_RUN 1 OV WDL 0FFh New count to be loaded to 8 bit down counter CLR EA disable interrupt OV WDCON ACC write back to WDCON after the watchdog is enabled a feed ust occur immediately OV WFEED1 0A5h do watchdog feed part 1 OV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt In timer mode WDTE 0 WDCON is loaded to the control register every CCLK cycle no feed sequence is required to load the control register but a feed sequence is required to load from the WDL SFR to the 8 bit down counter before a time out occurs The number of watchdog clocks before timing out is calculated by the following equations telks 20 PR WDL 1 1 1 where PRE is the value of prescaler PRE2 to PREO which can be the range 0 to 7 and WDL is the value of watchdog load register which can be the range of 0 to 255 The minimum number of tclks is telks 2 04 1 4 I 33 2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 100 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual The maximum number of tclks is tclks 2 255 1 1 1048577 3 Table 93 shows s
53. text Fig 7 Block diagram of oscillator control 2 7 Oscillator Clock OSCCLK wake up delay The P89LPC952 954 has an internal wake up timer that delays the clock until it stabilizes depending to the clock source used If the clock source is any of the three crystal selections the delay is 992 OSCCLK cycles plus 60 us to 100 us If the clock source is either the internal RC oscillator or the Watchdog oscillator the delay is 224 OSCCLK cycles plus 60 us to 100 us UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 25 of 134 NXP Semiconductors UM1 01 47 2 8 2 9 P89LPC952 954 User manual CPU Clock CCLK modification DIVM register The OSCCLK frequency can be divided down by an integer up to 510 times by configuring a dividing register DIVM to provide CCLK This produces the CCLK frequency using the following formula CCLK frequency fosc 2N Where fosc is the frequency of OSCCLK N is the value of DIVM Since N ranges from 0 to 255 the CCLK frequency can be in the range of fose tO fosc 510 for N 0 CCLK fosc This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events other than those that can cause interrupts i e events that allow exiting the Idle mode by executing its normal program at a lower rate This can often result in lower pow
54. the data to be programmed to FMDATA This will increment FMADRL pointing to the next byte in the page register Write the address of the next byte to be programmed to FMADRL if desired Not needed for contiguous bytes since FMADRL is auto incremented All bytes to be programmed must be within the same page e Write the data for the next byte to be programmed to FMDATA e Repeat writing of FMADRL and or FMDATA until all desired bytes have been loaded into the page register e Write the page address in user code memory to FMADRH and FMADRL 7 6 if not previously included when writing the page register address to FMADRLJ 5 0 e Write the erase program command 68H to FMCON starting the erase program cycle e Read FMCON to check status If aborted repeat starting with the LOAD command Table 99 Flash Memory Control register FMCON address E4h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol R z z s HVA HVE SV Ol Symbol W FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD 0 Reset 0 0 0 0 0 0 0 0 Table 100 Flash Memory Control register FMCON address E4h bit description Bit Symbol Access Description 0 Ol R Operation interrupted Set when cycle aborted due to an interrupt or reset FMCMD 0 W Command byte bit 0 1 SV R Security violation Set when an attempt is made to program erase or CRC a secured sector or page FMCMD 1 W Command byte bit 1 2 HVE R High voltage error Set when an error occurs in the
55. to 9 MHz to maintain accuracy A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose See Table 16 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 30 of 134 NXP Semiconductors UM1 01 47 3 2 7 3 2 8 P89LPC952 954 User manual UO pins used with ADC functions The analog input pins maybe be used as either digital I O or as inputs to A D and thus have a digital input and output function In order to give the best analog performance pins that are being used with the ADC should have their digital outputs and inputs disabled and have the 5V tolerance disconnected Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Table 24 Digital inputs will be disconnected automatically from these pins when the pin has been selected by setting its corresponding bit in the ADINS register and its corresponding A D has been enabled When used as digital I O these pins are 5 V tolerant If selected as input signals in ADINS these pins will be 3V tolerant if the corresponding A D is enabled and the device is not in power down Otherwise the pin will remain 5V tolerant Please refer to the P89LPC952 954 data sheet for specifications Power down and Idle mode In Idle mode the A D converter if enabled will continue to function and can cause the device to exit Idle mode when the conversion is complet
56. 0 Combined Interrupt Disable 0 When set 1 Rx and Tx interrupts are separate When cleared 0 the UART uses a combined Tx Rx interrupt like a conventional 80C51 UART This bit is reset to logic 0 to select combined interrupts 6 INTLO_ Transmit interrupt position 0 When cleared 0 the Tx interrupt is issued at the 0 beginning of the stop bit When set 1 the Tx interrupt is issued at end of the stop bit Must be logic 0 for mode 0 Note that in the case of single buffering if the Tx interrupt occurs at the end of a STOP bit a gap may exist before the next start bit 7 DBMOD Double buffering mode 0 When set 1 enables double buffering Must be logic 0 _0 for UART mode 0 In order to be compatible with existing 80C51 devices this bit is reset to logic 0 to disable double buffering NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 61 of 134 NXP Semiconductors UM1 01 47 UM10147_2 10 10 P89LPC952 954 User manual Table 57 Serial Port 1 Status register S1STAT address D4h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DBMOD INTLO_1 CIDIS_1 DBISEL_ FE_1 BR_1 OE_1 STINT_1 1 1 Reset D xX D xX D D 0 0 Table 58 Serial Port 1 Status register S1STAT address D4h bit description Bit Symbol Description 0 STINT_1 Status Interrupt Enable 1 When set 1 FE_1 BR_1 or OE_1 can cause an interrupt The interrupt used vector address 008Bh is shared with RI CIDIS_1 1 or t
57. 0 High frequency crystal High frequency crystal DIVM 01 10 11 High frequency crystal DIVM 1 00 High frequency crystal Internal RC oscillator 01 10 11 Internal RC oscillator 001 0 00 Medium frequency crystal Medium frequency crystal DIVM 01 10 11 Medium frequency crystal DIVM 1 00 Medium frequency crystal Internal RC oscillator 01 10 11 Internal RC oscillator NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 54 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual Table 41 Real time Clock System Timer clock sources continued FOSC2 0 RCCLK RTCS1 0 RTC clock source CPU clock source 010 0 00 Low frequency crystal Low frequency crystal 01 DIVM 10 11 Low frequency crystal DIV 1 00 Low frequency crystal Internal RC oscillator 01 10 11 Internal RC oscillator 011 0 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal DIVM 10 Low frequency crystal 11 Internal RC oscillator DIVM 1 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal 10 Low frequency crystal 11 Internal RC oscillator 100 0 00 High frequency crystal Watchdog oscillator 01 Medium frequency crystal DIVM 10 Low frequency crystal 11 Watchdog oscillator DIVM 1 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal 10 Low frequency crystal 11 Internal RC oscillator 101 x XX undefined undefined 110 x XX undef
58. 0 x STOP condition will be or transmitted STO flag will be reset no I2DAT action 1 1 0 Xx STOP condition followed by a START condition will be transmitted STO flag will be reset 28h Data byte in Load data byte or 0 0 0 x Data byte will be transmitted I2DAT sagoh ACK bit will be received transmitted S has been received I2DAT action 1 0 0 x Repeated START will be or transmitted no I2DAT action 0 1 0 x STOP condition will be or transmitted STO flag will be reset no I2DAT action 1 1 0 x STOP condition followed by a START condition will be transmitted STO flag will be reset UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 78 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual Table 72 Master Transmitter mode continued Siatus code Status of the I2C Application software response Next action taken by 12C I2STAT hardware to from I2DAT to I2CON hardware STA STO EI AA 30h Data byte in Load data byte or 0 0 0 Data byte will be transmitted DAT oo ee ACK bit will be received transmitted z ACK has been no I2DAT action 1 0 0 Repeated START will be received or transmitted no I2DAT action 0 1 0 STOP condition will be or transmitted STO flag will be reset no I2DAT action 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset 38H Arbitration lostin No I2DAT acti
59. 07 Oscillator type selection FOSC 2 0 Oscillator configuration 111 External clock input on XTAL1 100 Watchdog Oscillator 400 kHz 20 30 tolerance 011 Internal RC oscillator 7 373 MHz 2 5 010 Low frequency crystal 20 kHz to 100 kHz 001 Medium frequency crystal or resonator 100 kHz to 4 MHz 000 High frequency crystal or resonator 4 MHz to 18 MHz Table 108 Flash User Configuration Byte 2 UCFG2 bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DBG RPE1 Unprogrammed x x 0 x x x x x value Table 109 Flash User Configuration Byte 2 UCFG2 bit description Bit Symbol Description 0 RPE Reset pin enable 1 In combination with RPE UCFG1 6 determines the mode of the reset pin see Section 7 Reset on page 46 NOTE During a power up sequence the RPE and RPE1 selection is overridden and this pin will always functions as a reset input After power up the pin will function as defined by the RPE and RPE1 bits Only a power up reset will temporarily override the selection defined by RPE and RPE1 bits Other sources of reset will not override the RPE and RPE1 bits 1 4 Not used 5 DBG When set 1 enables the use of the debugger on the TCLK TDI and TRIG pins 6 7 Not used 17 18 User security bytes This device has three security bits associated with each of its eight sixteen sectors as shown in Table 110 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28
60. 0H 48H or 38H For slave mode the possible status codes are 68H 78H or BOH Refer to Table 74 for details UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 74 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual i EES a Li F logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW CT from master to slave A not acknowledge SDA HIGH EI from slave to master S START condition 002aaa930 Fig 28 Format of Master Receiver mode After a repeated START condition ZC bus may switch to the Master Transmitter Mode ee e tr logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW E from master to slave A not acknowledge SDA HIGH CT from slave to master S START condition P STOP condition SLA slave address RS repeat START condition 002aaa931 Fig 29 A Master Receiver switches to Master Transmitter after sending Repeated Start 11 6 3 Slave Receiver mode In the Slave Receiver Mode data bytes are received from a master transmitter To initialize the Slave Receiver Mode the user should write the slave address to the Slave Address Register I2ADR and the 12C Control Register I2CON should be configured as follows Table 71 1 C Control register I2CON address D8h Bit 7 6 5 4 3 2 1 0 I2EN STA STO SI AA CRSEL value
61. 28 April 2008 79 of 134 UM10147 P89LPC952 954 User manual NXP Semiconductors Table 73 Master Receiver mode continued Siatus code Status of the I2C Application software response Next action taken by I2C hardware I2STAT hardware to from I2DAT to I2CON STA STO EI STA 50h Data byte has Read data byte 0 0 0 0 Data byte will be received NOT ACK been received bit will be returned ACK has been read data byte 0 0 0 1 Data byte will be received ACK bit returned will be returned 58h Data byte has Read data byte or 1 0 x Repeated START will be transmitted been received read data byteor 0 x STOP condition will be transmitted NACK has been STO flag will be reset returned read data byte 1 1 0 D STOP condition followed by a START condition will be transmitted STO flag will be reset Table 74 Slave Receiver mode Status code Status of the EC Application software response Next action taken by PC I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA 60H Own SLA W has nol2DAT action x 0 0 0 Data byte will be received and NOT been received or ACK will be returned ACK has been no I2DAT action x 0 0 1 Data byte will be received and ACK received will be returned 68H Arbitration lostin No I2DAT action x 0 0 0 Data byte will be received and NOT SLA R Was or ACK will be returned master Own no I2DAT action x 0 0 1 Data byte will be received and ACK SLA W has been will be return
62. 4 0 write to i i f i i SBUF TX interrupt f f f f double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown with ending TX interrupt DBISEL SSTAT 4 1 002aaa928 Fig 25 Transmission with and without double buffering 10 18 The 9th bit bit 8 in double buffering Modes 1 2 and 3 If double buffering is disabled DBMOD_n i e SnSTAT 7 0 TB8_n can be written before or after SnBUF is written provided TB8_n is updated before that TB8_n is shifted out TB8_n must not be changed again until after TB8_n shifting has been completed as indicated by the Tx interrupt UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 66 of 134 NXP Semiconductors UM1 01 47 UM10147_2 10 19 P89LPC952 954 User manual If double buffering is enabled TB8_n MUST be updated before SnBUF is written as TB8_n will be double buffered together with SnBUF data The operation described in the Section 10 17 Transmit interrupts with double buffering enabled Modes 1 2 and 3 on page 65 becomes as follows The double buffer is empty initially The CPU writes to TB8_n The CPU writes to SnBUF The SnBUF TB8_n data is loaded to the shift register and a Tx interrupt is generated immediately S U N 5 If there is more data go to 7 else continue on 6 6 If there is no more data then If DBISEL_n is logic 0 no more interrupt
63. 5 CMPREF KBI5 P0 6 CMP1 KBI6 PO 7 T1 KBI7 P1 0 to P1 7 P1 0 TXDO P1 1 RXDO UM10147_2 Pin LQFP48 PLCC44 LQFP44 39 42 36 38 41 35 37 40 34 36 39 33 35 38 32 34 37 31 31 35 29 Type Description 1 0 I O DI 1 0 UO P0 1 Port 0 bit 1 CIN2B Comparator 2 positive input B KBI1 Keyboard input 1 ADO00 ADCO channel 0 analog input P0 2 Port 0 bit 2 CIN2A Comparator 2 positive input A KBI2 Keyboard input 2 AD01 ADCO channel 1 analog input P0 3 Port 0 bit 3 CIN1B Comparator 1 positive input B KBI3 Keyboard input 3 AD02 ADCO channel 2 analog input P0 4 Port 0 bit 4 CIN1A Comparator 1 positive input A KBI4 Keyboard input 4 AD03 ADCO channel 3 analog input P0 5 Port 0 bit 5 CMPREF Comparator reference negative input KBI5 Keyboard input 5 P0 6 Port 0 bit 6 CMP1 Comparator 1 output KBI6 Keyboard input 6 P0 7 Port 0 bit 7 T1 Timer counter 1 external count input or overflow output KBI7 Keyboard input 7 Port 1 Port 1 is an 8 bit I O port with a user configurable output type except for three pins as noted below During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configura
64. 7 2 Clocks P89LPC952 954 User manual UM10147_2 2 1 2 2 2 2 1 2 2 2 2 2 3 2 2 4 Enhanced CPU The P89LPC952 954 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles Clock definitions The P89LPC952 954 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency see Figure 6 and Section 2 8 CPU Clock CCLK modification DIVM register Note fosc is defined as the OSCCLK frequency CCLK CPU clock output of the DIVM clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output PCLK Clock for the various peripheral devices and is CCLK Oscillator Clock OSCCLK The P89LPC952 954 provides several user selectable oscillator options This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the FLASH is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source The crystal oscillator can be optimized for low me
65. 8 All rights reserved User manual Rev 02 28 April 2008 81 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual Table 74 Slave Receiver mode continued Status code Status of the I2C Application software response Next action taken by BC I2STAT hardware to from I2DAT to I2CON hardware STA STO sl AA AOH A STOP condition No I2DAT action 0 0 0 0 Switched to not addressed SLA or repeated mode no recognition of own SLA or START condition General call address hasbeenreceived vo I2DAT action 0 0 0 1 Switched to not addressed SLA while still mode Own slave address will be addressed as recognized General call address ee er will be recognized if I2ADR 0 1 SLA TRX no I2DAT action 1 0 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no I2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free Table 75 Slave Transmitter mode Siatus code Status of the EC Application software response Next action taken by PC WE Uw hardware to from I2DAT to I2CON hardware STA STO Si AA A8h Own SLA R has Load data byte or x 0 0 0 Last data byte will be transmitted been received and ACK bit will be received ACK has bee
66. April 2008 123 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 110 Sector Security Bytes SECx bit allocation Bit 7 6 5 4 3 2 1 0 Symbol EDISx SPEDISx MOVCDISx Unprogrammed 0 0 0 0 0 0 0 0 value Table 111 Sector Security Bytes SECx bit description Bit Symbol Description 0 MOVCDISx MOVC Disable Disables the MOVC command for sector x Any MOVC that attempts to read a byte ina MOVC protected sector will return invalid data This bit can only be erased when sector x is erased 1 SPEDISx Sector Program Erase Disable x Disables program or erase of all or part of sector x This bit and sector x are erased by either a sector erase command ISP IAP commercial programmer or a global erase command commercial programmer 2 EDISx Erase Disable ISP Disables the ability to perform an erase of sector x in ISP or IAP mode When programmed this bit and sector x can only be erased by a global erase command using a commercial programmer This bit and sector x CANNOT be erased in ISP or IAP modes 3 7 reserved Table 112 Effects of Security Bits EDISx SPEDISx MOVCDISx Effects on Programming 0 0 0 None 0 0 1 Security violation flag set for sector CRC calculation for the specific sector Security violation flag set for global CRC calculation if any MOVCDISx bit is set Cycle aborted Memory contents unchanged CRC invalid Program erase commands will not result in a securi
67. BMASK 1 When set enables P0 1 as a cause of a Keypad Interrupt 2 KBMASK 2 When set enables P0 2 as a cause of a Keypad Interrupt 3 KBMASK 3 When set enables P0 3 as a cause of a Keypad Interrupt 4 KBMASK 4 When set enables P0 4 as a cause of a Keypad Interrupt 5 KBMASK 5 When set enables P0 5 as a cause of a Keypad Interrupt 6 KBMASK 6 When set enables P0 6 as a cause of a Keypad Interrupt 7 KBMASK 7 When set enables PO 7 as a cause of a Keypad Interrupt 1 The Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective 15 Watchdog timer WDT The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count The watchdog timer can only be reset by a power on reset 15 1 Watchdog function The user has the ability using the WDCON and UCFG1 registers to control the run stop condition of the WDT the clock source for the WDT the prescaler value and whether the WDT is enabled to reset the device on underflow In addition there is a safety mechanism which forces the WDT to be enabled by values programmed into UCFG1 either through IAP or a commercial programmer The WDTE bit UCFG1 7 if set enables the WDT to reset the device on underflow Following reset the WDT will be running regardless of the state of the WDTE bit
68. BPATN O Reset 1 1 1 1 1 1 1 1 Table 85 Keypad Pattern register KBPATN address 93h bit description Bit Symbol Access Description 0 7 KBPATN 7 0 R W Pattern bit 0 bit 7 Table 86 Keypad Control register KBCON address 94h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PATN_SEL KBIF Reset x xX xX xX xX D 0 0 Table 87 Keypad Control register KBCON address 94h bit description Bit Symbol Access Description 0 KBIF R W Keypad Interrupt Flag Set when Port 0 matches user defined conditions specified in KBPATN KBMASK and PATN_SEL Needs to be cleared by software by writing logic 0 1 PATN_SEL R W Pattern Matching Polarity selection When set Port 0 has to be equal to the user defined Pattern in KBPATN to generate the interrupt When clear Port 0 has to be not equal to the value of KBPATN register to generate the interrupt 2 7 reserved UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 97 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 88 Keypad Interrupt Mask register KBMASK address 86h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol KBMASK 7 KBMASK 6 KBMASK 5 KBMASK 4 KBMASK 3 gt KBMASK 2 KBMASK 1 KBMASK 0 Reset 0 0 0 0 0 0 0 0 Table 89 Keypad Interrupt Mask register KBMASK address 86h bit description Bit Symbol Description 0 KBMASK 0 When set enables P0 0 as a cause of a Keypad Interrupt 1 K
69. C interface is already in master mode and some data is transmitted or received it transmits a repeated START condition STA may be set at any time it may also be set when the 12C interface is in an addressed slave mode STA 0 no START condition or repeated START condition will be generated 6 GEN 12C Interface Enable When set enables the 12C interface When clear the 12C function is disabled 7 reserved I2C Status register This is a read only register It contains the status code of the 12C interface The least three bits are always 0 There are 26 possible status codes When the code is F8H there is no relevant information available and SI bit is not set All other 25 status codes correspond to defined DC states When any of these states entered the SI bit will be set Refer to Table 72 to Table 75 for details Table 67 1 C Status register I2STAT address D9h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol STA 4 STA 3 STA 2 STA 1 STA O 0 0 0 Reset 0 0 0 0 0 0 0 0 Table 68 1 C Status register I2STAT address D9h bit description Bit Symbol Description 0 2 Reserved are always set to 0 3 7 STA 0 4 12C Status code 12C SCL duty cycle registers I2SCLH and I2SCLL When the internal SCL generator is selected for the 12C interface by setting CRSEL 0 in the I2CON register the user must set values for registers I2SCLL and I2SCLH to select the data rate I2SCLH defines the number of PCLK cycles for SCL
70. CMFn contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The two comparators use one common interrupt vector The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IENO register If both comparators enable interrupts after entering the interrupt service routine the user will need to read the flags to determine which comparator caused the interrupt When a comparator is disabled the comparator s output COx goes high If the comparator output was low and then is disabled the resulting transition of the comparator output from a low to high state will set the comparator flag CMFx This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparator flag CMFx after disabling the comparator 13 5 Comparators and power reduction modes Either or both comparators may remain enabled when Power down mode or Idle mode is activated but both comparators are disabled automatically in Total Power down mode If a comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor If the comparator outp
71. Comparator positive input select When logic 0 CINnA is selected as the positive comparator input When logic 1 CINnB is selected as the positive comparator input 5 CEn Comparator enable When set the corresponding comparator function is enabled Comparator output is stable 10 microseconds after CEn is set 6 7 reserved CP1 P0 4 CIN1A _ _ comparator 1 P0 3 CIN1B col i ca CMP1 P0 6 P0 5 CMPREF Vret bg change detect on interrupt change detect CP2 g EC CG P0 2 CIN2A comparator 2 P0 1 CIN2B Kb CMP2 P0 0 co2 i i OE2 CN2 002aaa904 Fig 41 Comparator input and output connections UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 94 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 13 2 Internal reference voltage An internal reference voltage Vref may supply a default reference when a single comparator input pin is used Please refer to the P89LPC952 954 data sheet for specifications 13 3 Comparator input pins Comparator input and reference pins maybe be used as either digital I O or as inputs to the comparator When used as digital I O these pins are 5 V tolerant However when selected as comparator input signals in CMPn lower voltage limits apply Please refer to the P89LPC952 954 data sheet for specifications 13 4 Comparator interrupt Each comparator has an interrupt flag
72. Cycle Register Low Byte I2C data register I2DAT register contains the data to be transmitted or the data received The CPU can read and write to this 8 bit register while it is not in the process of shifting a byte Thus this register should only be accessed when the SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data in l2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT Table 62 1 C data register I2DAT address DAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2DAT 7 1I2DAT 6 I2DAT 5 I2DAT 4 DDAT3 DDAT3 1I2DAT 1 DDAT 0 Reset 0 0 0 0 0 0 0 0 I2C slave address register I2ADR register is readable and writable and is only used when the 12C interface is set to slave mode In master mode this register has no effect The LSB of I2ZADR is general call bit When this bit is set the general call address 00h is recognized Table 63 1 C slave address register IZADR address DBh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC Reset 0 0 0 0 0 0 0 0 Table 64 1 C slave address register IZADR address DBh bit description Bit Symbol Description D Gc General call bit When set the general call address 00H is recognized otherwise it is ignored 1 7 I2ADR1 7 7 bit own slave address When in maste
73. D1 Watchdog C2H feed 1 WFEED2 Watchdog C3H feed 2 1 2 3 4 5 6 All ports are in input only high impedance state after power up BRGR1_0 and BRGR0_0 must only be written if BRGEN_0 in BRGCON_O SFR is logic 0 If any are written while BRGEN_O 1 the result is unpredictable The RSTSRC register reflects the cause of the UM10147 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is xx11 0000 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WORUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register The only reset source that affects these SFRs is power on reset Jenuew Jost 7S6 2S60d 168d ZVLOLINN SIOJONPUOSIWIBS dXN jenuew sn 800z dv gz ZO wen vel JO SL Z Asou pamasa SUD Iv 8002 A9 dXN Table 3 Extended special function registers Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary ADCOHBND ADCO high_boundary register FFEFH FF 1111 1111 left MSB ADCOLBND ADCO low_boundary register FFEEH 00 0000 0000 MSB ADODATOR ADCO data register 0 right FFFEH ADODATO 7 0 00 0000 0000 LSB ADODATOL ADCO data register 0 left
74. DD PO 7 T1 KBI7 P2 2 MOSI P2 3 MISO P2 4 SS P2 5 SPICLK P2 6 P4 0 P89LPC954FBD48 002aad095 P5 3 13 P5 2 14 Fig 3 LQFP48 pin configuration Vss 17 P5 1 15 P5 0 16 P4 7 TCLK 18 P4 6 19 P4 5 TDI 20 P4 4 21 P4 3 RXD1 22 P4 2 TXD1 23 P4 1 TRIG 24 1 2 Pin description Table 1 Pin description Symbol Pin LQFP48 PLA LQFP44 P0 0 to PO 7 P0 0 CMP2 40 43 37 KBIO AD05 UM10147_2 Type Description 1 0 gl Port 0 Port 0 is an 8 bit I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt triggered inputs Port 0 also provides various special functions as described below P0 0 Port 0 bit 0 CMP2 Comparator 2 output KBIO Keyboard input 0 AD05 ADCO channel 5 analog input NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 5 of 134 NXP Semiconductors UM10147 Table 1 Pin description continued P89LPC952 954 User manual Symbol PO 1 CIN2B KBI1 AD00 P0 2 CIN2A KBI2 AD01 P0 3 CIN1B KBI3 AD02 P0 4 CIN1A KBI4 AD03 P0
75. EN Baud Rate Generator 1Enable Enables the baud rate generator BRGR1_1 and 1 BRGRO_1 can only be written when BRGEN_1 0 1 SBRGS Select Baud Rate Generator 1as the source for baud rates to UART1 in modes 1 1 and 3 see Table 45 for details 2 7 reserved NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 58 of 134 NXP Semiconductors UM1 01 47 UM10147_2 10 8 10 9 P89LPC952 954 User manual timer 1 overflow SMOD1 lt 1 PCLK based gt SBRGS 0 0 baud rate modes 1 and 3 SMOD1 0 baud rate generator SBRGS 1 CCLK based 002aaa897 Fig 21 Baud rate generation for UARTs Modes 1 3 Framing error A Framing error occurs when the stop bit is sensed as a logic 0 A Framing error is reported in the status register SnSTAT In addition if SMODO PCON 6 is 1 framing errors can be made available in SnCON 7 If SMODO is 0 SOCON 7 is SMO_0 and S1CON is SM0_1 It is recommended that SMO_n and SM1_n SnCON 7 6 are programmed when SMODO is logic 0 Break detect A break detect is reported in the status register SnSTAT A break is detected when any 11 consecutive bits are sensed low Since a break condition also satisfies the requirements for a framing error a break condition will also result in reporting a framing error Once a break condition has been detected the UART will go into an idle state and remain in this idle state until a stop bit ha
76. Flash as data storage IAP Lite The Flash code memory array of this device supports IAP Lite in addition to standard IAP functions Any byte in a non secured sector of the code memory array may be read using the MOVC instruction and thus is suitable for use as non volatile data storage IAP Lite provides an erase program function that makes it easy for one or more bytes within a page to be erased and programmed in a single operation without the need to erase or program any other bytes in the page IAP Lite is performed in the application under the control of the microcontroller s firmware using four SFRs and an internal 64 byte page register to facilitate erasing and programing within unsecured sectors These SFRs are e FMCON Flash Control Register When read this is the status register When written this is a command register Note that the status bits are cleared to logic 0s when the command is written e FMADRL FMADRH Flash memory address low Flash memory address high Used to specify the byte address within the page register or specify the page within user code memory e FMDATA Flash Data Register Accepts data to be loaded into the page register The page register consists of 64 bytes and an update flag for each byte When a LOAD command is issued to FMCON the page register contents and all of the update flags will be cleared When FMDATA is written the value written to FMDATA will be stored in the page register at the loca
77. Generator is disabled the DROGEN Oo bit in the BRGCON_n register is logic 0 This avoids the loading of an interim value to the baud rate generator CAUTION If either BRGRO_n or BRGR1_n is written when BRGEN_n 1 the result is unpredictable Table 45 UART baud rate generation SnCON 7 SnCON 6 PCON 7 BRGCON_n Receive transmit baud rate for UART SMO SM1 SMOD1 1 SBRGS 0 0 x x CCLK 6 0 1 0 0 CELK 256 TH1 64 1 0 OCLK o56 TH1 32 X 1 CCLK BRGRI_n BRGRO_n 16 1 0 0 D CCLK 1 X CCLKy 6 1 1 0 0 CCL 556 THI 64 1 0 Flies TH1 32 X 1 CCLK BRGRI_n BRGRO_n 16 Table 46 Baud Rate Generator Control register BRGCON_O address BDh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SBRGS_0 BRGEN_O Reset xX D D D D xX 0 0 Table 47 Baud Rate Generator Control register BRGCON address BDh bit description Bit Symbol Description 0 DROGEN Baud Rate Generator 0 Enable Enables the baud rate generator BRGR1_0 and _0 BRGR0O_O can only be written when DROGEN Oo 0 1 SBRGS Select Baud Rate Generator 0 as the source for baud rates to UARTO in modes 1 0 and 3 see Table 45 for details 2 7 reserved Table 48 Baud Rate Generator Control register BRGCON_1 address FFB3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol z SBRGS_1 BRGEN_1 Reset x x x x x x 0 0 Table 49 Baud Rate Generator Conirol register BRGCON_1 address FFB3h bit description Bit Symbol Description 0 DROG
78. LH SCL DUTY CYCLE REGISTERS I2SCLL aist STATUS slats DUS DECODER I2STAT STATUS REGISTER i y 002aaa899 Fig 32 1 C serial interface block diagram UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 77 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 72 Master Transmitter mode Status code Status of the I2C Application software response Next action taken by 12C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA 08H A START Load SLA W x 0 0 x SLA W will be transmitted condition has ACK bit will be received been transmitted 10H A repeat START LoadSLA Wor x 0 0 x As above SLA W will be condition has Load SLA R transmitted I C bus switches been transmitted to Master Receiver Mode 18h SLA W has been Load data byte or 0 0 0 x Data byte will be transmitted transmitted ACK ACK bit will be received has been received ho DAT action 1 0 0 x Repeated START will be or transmitted no I2DAT action 0 1 0 x STOP condition will be or transmitted STO flag will be reset no I2DAT action 1 1 0 Xx STOP condition followed by a START condition will be transmitted STO flag will be reset 20h SLA W has been Load data byte or 0 0 0 x Data byte will be transmitted transmitted ACK bit will be received NOT ACK has ho I2DAT action 1 0 0 x Repeated START will be been received or transmitted no I2DAT action 0 1
79. M2 5 RST P1 6 P1M1 6 P1M2 6 OCB P1 7 P1M1 7 P1M2 7 OCC AD04 P2 0 P2M1 0 P2M2 0 ICB AD07 P2 1 P2M1 1 P2M2 1 OCD AD06 P2 2 P2M1 2 P2M2 2 MOSI P2 3 P2M1 3 P2M2 3 MISO P2 4 P2M1 4 P2M2 4 SS P2 5 P2M1 5 P2M2 5 SPICLK P3 0 P3M1 0 P3M2 0 CLKOUT XTAL2 P3 1 P3M1 1 P3M2 1 XTAL1 P4 0 P4M1 0 P4M2 0 P4 1 P4M1 1 P4M2 1 TRIG P4 2 P4M1 2 P4M2 2 TXD1 P4 3 P4M1 3 P4M2 3 RXD1 P4 4 P4M1 4 P4M2 4 P4 5 P4M1 5 P4M2 5 TDI P4 6 P4M1 6 P4M2 6 P4 7 P4M1 7 P4M2 7 TCLK P5 0 P5M1 0 P5M2 0 P5 1 P5M1 1 P5M2 1 P5 2 P5M1 2 P5M2 2 P5 3 P5M1 3 P5M2 3 P5 4 P5M1 4 P5M2 4 P5 5 P5M1 5 P5M2 5 P5 6 P5M1 6 P5M2 6 P5 7 P5M1 7 P5M2 7 NXP B V 2008 All rights reserved Rev 02 28 April 2008 41 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 6 Power monitoring functions 6 1 UM10147_2 The P89LPC952 954 incorporates power monitoring functions designed to prevent incorrect operation during initial power on and power loss or reduction during operation This is accomplished with two hardware functions Power on Detect and Brownout Detect Brownout detection The Brownout Detect function determines if the power supply voltage drops below a certain level The default operation for a Brownout Detection is to cause a processor reset However it may alternatively be configured to generate an interrupt by setting the BOI PCON 4 bit and the EBO IENO 5 bit Enabling and disabling of Brownout Detection
80. Manufacturer Id 11 Device Id 12 Derivative Id 18 Security Byte 8 89LPC954 19 Security Byte 9 89LPC954 1A Security Byte 10 89LPC954 1B Security Byte 11 89LPC954 1C Security Byte 12 89LPC954 1D Security Byte 13 89LPC954 1E Security Byte 14 89LPC954 1F Security Byte 15 89LPC954 Example 010000031 2cc Erase Sector Page 03xxxx04ssaaaacc Where xxxx required field but value is a don t care aaaa sector page address ss 01 erase sector ss 00 erase page cc checksum Example 03000004010000F8 Read Sector CRC 01xxxx05aacc Where xxxx required field but value is a don t care aa sector address high byte cc checksum Example 0100000504F6cc NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 116 of 134 NXP Semiconductors UM1 01 47 UM10147_2 17 12 17 13 17 14 P89LPC952 954 User manual Table 102 In system Programming ISP hex record formats continued Record type Command data function 06 Read Global CRC 00xxxx06cc Where xxxx required field but value is a don t care cc checksum Example 00000006FA 07 Direct Load of Baud Rate 02xxxx07HHLLcc Where xxxx required field but value is a don t care HH high byte of timer LL low byte of timer cc checksum Example 02000007FFFFcc 08 Reset MCU 00xxxx08cc Where xxxx required field but value is a don t care cc checksum Example 00000008F8
81. O When set the P1 2 pin is toggled whenever Timer 0 overflows The output frequency is therefore one half of the Timer 0 overflow rate Refer to Section 8 Timers 0 and 1 for details 5 ENTI When set the PO 7 pin is toggled whenever Timer 1 overflows The output frequency is therefore one half of the Timer 1 overflow rate Refer to Section 8 Timers 0 and 1 for details 6 EBRR UART Break Detect Reset Enable If logic 1 UART Break Detect will cause a chip reset and force the device into ISP mode 7 CLKLP Clock Low Power Select When set reduces power consumption in the clock circuits Can be used when the clock frequency is 8 MHz or less After reset this bit is cleared to support up to 12 MHz operation UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 104 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 16 1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred If a value is written to AUXR1 that contains a 1 at bit position 3 all SFRs will be initialized and execution will resume at program address 0000 Care should be taken when writing to AUXR1 to avoid accidental software resets 16 2 Dual Data Pointers The dual Data Pointers DPTR adds to the ways in which the processor can specify the address used with certain instructions The DPS bit in the AUXR1
82. O pins except P1 5 may be configured by software e Pin P1 5 is input only Pins P1 2 and P1 3 are configurable for either input only or open drain Every output on the P89LPC952 954 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to the P89LPC 952 954 data sheet for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 40 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual Table 25 Port output configuration Port pin Configuration SFR bits PxM1 y PxM2 y Alternate usage Notes P0 0 POM1 0 POM2 0 KBIO CMP2 AD05 PO 1 POM1 1 POM2 1 KBI1 CIN2B ADOO Refer to Section 5 6 Port 0 and P0 2 POM1 2 POM2 2 KBI2 CIN2A ADO1 Analog Comparator functions for usage as analog inputs P0 3 POM1 3 POM2 3 KBI3 CIN1B AD02 P0 4 POM1 4 POM2 4 KBI4 CIN1A ADO3 P0 5 POM1 5 POM2 5 KBI5 CMPREF P0 6 POM1 6 POM2 6 KBI6 CMP1 PO 7 POM1 7 POM2 7 KBI7 T1 P1 0 P1M1 0 P1M2 0 TXD P1 1 P1M1 1 P1M2 1 RXD P1 2 P1M1 2 P1M2 2 TO SCL Input only or open drain P1 3 P1M1 3 P1M2 3 INTO SDA input only or open drain P1 4 P1M1 4 P1iM2 4 INT1 P1 5 P1M1 5 P1
83. P B V 2008 All rights reserved User manual Rev 02 28 April 2008 8 of 134 NXP Semiconductors UM10147 Table 1 Pin description continued P89LPC952 954 User manual Symbol P4 0 P4 1 TRIG P4 2 TXD1 P4 3 RXD1 P4 4 P4 5 TDI P4 6 P4 7 TCLK P5 0 to P5 7 P5 0 P5 1 P5 2 P5 3 P5 4 P5 5 P5 6 P5 7 Vss VREFN Von VREFP Pin LQFP48 PLCC44 LQFP44 25 30 24 24 29 23 23 28 22 22 27 21 21 26 20 20 25 19 19 24 18 18 23 17 16 21 15 15 20 14 14 19 13 13 18 12 12 17 11 11 16 10 10 15 9 9 14 8 17 45 3 22 16 41 44 8 32 13 36 7 30 33 Type Description 1 0 UO O UO O 1 0 l UO 1 0 UO UO UO 1 0 UO 1 0 UO 1 0 gl UO 1 0 UO P4 0 Port 4 bit 0 P4 1 Port 4 bit 1 TRIG Debugger trigger output P4 2 Port 4 bit 2 TXD1 Transmitter output for serial port 1 P4 3 Port 4 bit 3 RXD1 Receiver input for serial port 1 P4 4 Port 4 bit 4 P4 5 Port 4 bit 5 TDI Serial data input output for debugger interface P4 6 Port 4 bit 6 P4 7 Port 4 bit 7 TCLK Serial clock input for debugger interface Port 5 Port 5 is an 8 bit I O port with a user configurable output type During reset Port 5 latches are configured in the input only mode with the internal pull up disabled The operation of Port 5 pins as inputs and outputs depends upon the port configuration selected Each port pin is
84. P2M1 3 P2M1 2 P2M1 1 P2M1 0 FEI 11111111 g P2M2 5 P2M2 4 P2M2 3 P2M2 2 P2M2 1 P2M2 0 0001 0000 0000 S i P3M1 1 P3M1 0 03 Xxxx Xx11 S S P3M2 1 P3M2 0 OO XXXX XX00 SMOD1 SMODO BOPD BOI GF1 GEO PMOD1 PMODO 00 0000 0000 RTCPD VCPD ADPD I2PD SPPD SPD ool 0000 0000 D7 D6 D5 D4 D3 D2 D1 DO CY AC FO RS1 RSO OV F1 P 00 0000 0000 PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00 000x BOF POF R_BK R_WD R_SF REX B Jenuew Jost 7S6 2S60d 168d ZVLOLINN SIOJONPUOSIWIS dXN jenuew sn 8002 dv gz ZO wen FCL JO OL Z ZvLOLWN pamasa Syu Ily 8002 A9 dXN Table 2 Special function registers continued indicates SFRs that are bit addressable Name RTCCON RTCH RTCL SOADDR SOADEN SOBUF SOCON SOSTAT SP SPCTL SPSTAT SPDAT S1CON S1STAT TAMOD Description SFR addr RTC control D1H RTC register D2H high RTC register D3H low Serial port A9H address register Serial port B9H address enable Serial Portdata 99H buffer register Bit address Serial port 98H control Serial port BAH extended status register Stack pointer 81H SPI control E2H register SPI status E1H register SPI data E3H register Serial port 1 B6H control Serial port 1 D4H extended status register Timer 0 and 1 8FH auxiliary mode Bit address Bit functions and addresses Reset value MSB LSB Hex Binary RTCF RTCS1 RTCSO ER
85. P89LPC 952 954 data sheet Dynamic characteristics for glitch filter specifications NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 39 of 134 NXP Semiconductors UM1 01 47 UM10147_2 5 6 5 7 P89LPC952 954 User manual VDD strong pin port latch N data input data Lea glitch rejection 002aaa917 Fig 13 Push pull output Port 0 and Analog Comparator functions The P89LPC952 954 incorporates two Analog Comparators In order to give the best analog performance and minimize power consumption pins that are being used for analog functions must have both the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Figure 12 Digital inputs on Port 0 may be disabled through the use of the PTOAD register Bits 1 through 5 in this register correspond to pins PO 1 through PO 5 of Port 0 respectively Setting the corresponding bit in PTOAD disables that pin s digital input Port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port On any reset PTOAD bits 1 through 5 default to logic Os to enable the digital functions Additional port features After power up all pins are in Input Only mode Please note that this is different from the LPC76x series of devices e After power up all I
86. TC RTCEN eol 011x xx00 oole 0000 0000 oole 0000 0000 00 0000 0000 00 0000 0000 XX XXXX XXXX 9F 9E 9D 9C 9B 9A 99 98 SM0_0 FE SM1_00 SM2_0 DEN 0 TB8_0 RB8_0 TLO HI O 00 0000 0000 0 DBMOD_0 INTLO_ O CIDIS_O DBISEL_O FE 0 BR_O OE_0 STINT_O 00 0000 0000 07 0000 0111 SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPRO 04 0000 0100 SPIF WCOL 00 OOxx Xxxx 00 0000 0000 SMO_1 FE SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TL1 HI 00 0000 0000 i DBMOD_1 INTLO_1 CIDIS_1 DBISEL 1 FE_1 BR_1 OE_1 STINT_1 00 0000 0000 T1iM2 TOM2 00 xXxx0 xt 8F 8E 8D 8C 8B 8A 89 88 Jenuew Joer 7S6 2S60d 168d ZVLOLINN SIOJONPUODIWIS dXN jenuew sn 800z dv gz ZO wen VEL IO LL Z ZvLOLWN pamasa SUD Ily 8002 A9 dXN Table 2 Special function registers continued indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary TCON Timer 0 and 1 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 0000 0000 control THO Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TLO Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TMOD Timer 0 and 1 89H TIGATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 0000 0000 mode TRIM Internal 96H RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O 5 6 oscillator trim register WDCON Watchdog A7H PRE2 PRE1 PREO WDRUN WDTOE WDCLK IIE control register WDL Watchdog load CH FF 1111 1111 WFEE
87. Transmission with and without double buffering G Fig 26 I C bus configuration 70 Fig 27 Format in the Master Transmitter mode 74 Fig 28 Format of Master Receiver mode 75 Fig 29 A Master Receiver switches to Master Transmitter after sending Repeated Start 75 Fig 30 Format of Slave Receiver mode 76 Fig 31 Format of Slave Transmitter mode 76 Fig 32 DC serial interface block diagram 77 Fig 33 SPI block dagram 00 0 ee 84 Fig 34 SPI single master single slave configuration 86 Fig 35 SPI dual device configuration where either canbe a master or a slave 86 Fig 36 SPI single master multiple slaves configuration 87 Fig 37 SPI slave transfer format with CPHA 0 90 Fig 38 SPI slave transfer format with CPHA 1 91 Fig 39 SPI master transfer format with CPHA 0 92 Fig 40 SPI master transfer format with CPHA 1 93 Fig 41 Comparator input and output connections 94 Fig 42 Comparator configurations 96 Fig 43 Watchdog Prescaler 000 99 Fig 44 Watchdog Timer in Watchdog Mode WDTE 1 103 Fig 45 Watchdog Timer in Timer Mode WDTE 0 103 Fig 46 Debugger connections top view 106 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 132 of 134 NXP Semiconductors UM10147 22 Contents P89LPC952 954 User manual 3 2
88. _2 10 1 10 2 10 3 The P89LPC952 954 has two enhanced UARTs that are compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC952 954 does include an independent Baud Rate Generator for each UART The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent Baud Rate Generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection break detect automatic address recognition selectable double buffering and several interrupt options The UART can be operated in 4 modes as described in the following sections Mode 0 Serial data enters and exits through RXDn TXDn outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at Le of the CPU clock frequency Mode 1 10 bits are transmitted through TXDn or received through RXDn a start bit logic 0 8 data bits LSB first and a stop bit logic 1 When data is received the stop bit is stored in RB8 in Special Function Register SnCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection on page 57 Mode 2 11 bits are transmitted through TXDn or received through RXDn start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit l
89. address 0COh BRGCON_0 address BDh bit allocation 58 bit allocation 00 cece eee 32 Table 47 Baud Rate Generator Control register BRGCON Table 14 A D Mode register A ADMODA address 0COh address BDh bit description 58 bit description 32 Table 48 Baud Rate Generator Control register Table 15 A D Mode register B ADMODB address A1h bit BRGCON_1 address FFB3h bit allocation 58 allocation 32 Table 49 Baud Rate Generator Control register Table 16 A D Mode register B ADMODB address A1h bit BRGCON_1 address FFB3h bit description 58 description 32 Table 50 Serial Port 0 Control register SOCON address Table 17 A D Input select ADINS address A3h bit 98h bit allocation 59 allocation AEN EEN E we de A 33 Table 51 Serial Port O Control register SOCON address Table 18 A D Input select ADINS address A3h bit 98h bit description 59 description 33 Table 52 Serial Port 1 Control register S1CON address Table 19 Boundary status register 0 BNDSTAO address B5h bit allocation 60 FFEDh bit allocation 33 Table 53 Serial Port 1 Control register S1CON address Table 20 Boundary status register 0 BNDSTAO address B5h bit description 60 FFEDh bit description 33 Table 54 Serial Port modes 04 61 Table 21 Interrupt priority level 34 Table 55 Serial Por
90. al Rev 02 28 April 2008 11 of 134 jenuew sn 800z dv gz ZO wen vELIOSL Z ZyLOLWN pamasa SUD Ily 8002 A9 dXN Table 2 Special function registers indicates SFRs that are bit addressable Name ACC ADOCON ADOINS ADOMODA ADOMODB AUXR1 B BRGRO_O BRGR1_0 BRGCON_0O CMP1 CMP2 DIVM DPTR Description SFR addr Bit address Accumulator EOH ADCO control 97H register ADCO input A3H select ADCO mode COH register A ADCO mode A1H register B Auxiliary A2H function register Bit address B register FOH Baud rate BEH generator 0 rate low Baud rate BFH generator 0 rate high Baud rate BDH generator 0 control Comparator 1 ACH control register Comparator2 ADH control register CPU clock 95H divide by M control Data pointer 2 bytes Bit functions and addresses Reset value MSB LSB Hex Binary E7 E6 E5 E4 E3 E2 E1 EO 00 0000 0000 ENBIO ENADCIO TMMO EDGEO ADCIO ENADCO ADCSO1 ADCS00 00 0000 0000 ADIO7 ADIO06 ADIO5 ADI04 ADIO3 ADI02 ADIO1 ADIOO 00 0000 0000 BNDIO BURSTO SCCO SCANO 00 0000 0000 CLK2 CLK1 CLKO 00 000x 0000 CLKLP EBRR ENT1 ENTO SRST 0 DPS 00 0000 00x0 F7 F6 F5 F4 F3 F2 F1 FO 00 0000 0000 00 0000 0000 00 0000 0000 SBRGS_0 BRGEN_O 00l xxxx xx00 CE1 CP1 CN1 OE1 CO1 CMF1 ool xx00 0000 CE2 CP2 CN2 OE2 CO2 CMF2 oo xx00 0000 00 0000 0000 Jenuew Joer Y96 2969d168d ZVLOLINN
91. al call address will be recognized if I2ADR 0 1 read data byte 1 0 0 0 Switched to not addressed SLA or mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free read data byte 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free 90H Previously Read data byte or x 0 0 0 Data byte will be received and NOT addressed with ACK will be returned General call Data fead data byte x 0 0 1 Data byte will be received and ACK has been will be returned received ACK has been returned 98H Previously Read data byte 0 0 0 0 Switched to not addressed SLA addressed with mode no recognition of own SLA or General call Data General call address has SEN K read data byte 0 0 0 1 Switched to not addressed SLA received NAC mode Own slave address will be has been returned recognized General call address will be recognized if IZADR 0 1 read data byte 1 0 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free read data byte 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free UM10147_2 NXP B V 200
92. ample P89LPC952 954 timeout values Table 91 Watchdog Timer Control register WDCON address A7h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PRE2 PRE1 PREO s WDRUN WDTOF WDCLK Reset 1 1 1 D D 1 1 0 1 Table 92 Watchdog Timer Control register WDCON address A7h bit description Bit Symbol Description 0 WDCLK Watchdog input clock select When set the watchdog oscillator is selected When cleared PCLK is selected If the CPU is powered down the watchdog is disabled if WDCLK 0 see Section 15 5 Note If both WDTE and WDSE are set to 1 this bit is forced to 1 Refer to Section 15 3 for details 1 WDTOF Watchdog Timer Time Out Flag This bit is set when the 8 bit down counter underflows In watchdog mode a feed sequence will clear this bit It can also be cleared by writing a logic 0 to this bit in software 2 WDRUN Watchdog Run Control The watchdog timer is started when WDRUN 1 and stopped when WDRUN 0 This bit is forced to 1 watchdog running and cannot be cleared to zero if both WDTE and WDSE are set to 1 3 4 reserved PREO 6 PRE1 Clock Prescaler Tap Select Refer to Table 93 for details 7 PRE2 Table 93 Watchdog timeout vales PRE2 to PREO WDL in decimal Timeout Period Watchdog Clock Source in watchdog clock 400 KHz Watchdog 12 MHz CCLK 6 MHz cycles Oscillator Clock CCLK Watchdog Nominal Clock 000 0 33 82 5 us 5 50 us 255 8 193 20 5 ms 1 37 ms 001 0 65 162 5 us 10 8 us 255 16
93. ansmit tart TxD Sat Xo Xt EX EXE XEXE Kb EY sop Bh ep E ae INTLO 0 INTLO I RX clock JL JL JJ IL JJJ JJJ JI IL start RXD D e e ER CECR E X e X CR stop a SMODO 0 SMODO 1 receive 002aaa927 Fig 24 Serial Port Mode 2 or 3 only single transmit buffering case is shown 10 13 Framing error and RI_n in Modes 2 and 3 with SM2_n 1 If SM2_n 1 in modes 2 and 3 RI_n and FE_n behaves as in the following table UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 64 of 134 NXP Semiconductors UM1 01 47 UM10147_2 10 14 10 15 10 16 10 17 P89LPC952 954 User manual Table 59 FE_n and RI_n when SM2_n 1 in Modes 2 and 3 Mode PCON 6 RB8 amp _n Ri_n FE_n SMODO 2 0 0 No RI_n when RB8 amp _n 0 Occurs during STOP bit 1 Similar to Figure 24 with SMODO 0 R_n Occurs during STOP bit 3 1 0 No RI_n when RB8 _n 0 Will NOT occur 1 Similar to 24 with SMODO 1 RI_n Occurs during STOP occurs during STOP bit bit Break detect A break is detected when 11 consecutive bits are sensed low and is reported in the status register SnSTAT For Mode 1 this consists of the start bit 8 data bits and two stop bit times For Modes 2 and 3 this consists of the start bit 9 data bits and one stop bit The break detect bit is cleared in software or by a reset The break detect of UARTO can be used to reset the device and force the device i
94. ated if both the ESPI IEN1 3 bit and the EA bit are set If SS is an input and is driven low when SPI is in master mode and SSIG 0 this bit will also be set see Section 12 4 Mode change on SS The SPIF flag is cleared in software by writing a logic 1 to this bit NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 85 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual Table 80 SPI Data register SPDAT address E3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol MSB LSB Reset 0 0 0 0 0 0 0 0 slave 4 8 BIT SHIFT __ REGISTER master MISO 8 BIT SHIFT 4 REGISTER _ MOSI I I I I SPICLK SPICLOCK f7 i GENERATOR PORT I I I 002aaa901 Fig 34 SPI single master single slave configuration In Figure 34 SSIG SPCTL 7 for the slave is logic 0 and SS is used to select the slave The SPI master can use any port pin including P2 4 SS to drive the SS pin master slave 8 BIT SHIFT REGISTER 8 1 8 BIT SHIFT REGISTER SPI CLOCK i GENERATOR gt F SPI CLOCK SS GENERATOR SPICLK T 002aaa902 Fig 35 SPI dual device configuration where either can be a master or a slave Figure 35 shows a case where two devices are conn
95. ature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies Increasing the TRIM value will decrease the oscillator frequency When the clock doubler option is enabled UCFG1 3 1 the output frequency is doubled If CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to logic 1 to reduce power consumption On reset CLKLP is logic 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8 MHz or slower The requirements in Section 2 2 4 High speed oscillator option for configuring P1 5 as an external reset input and using an external reset circuit when the clock frequency is greater than 12 MHz do not apply when using the internal RC oscillator s clock doubler option Table 5 On chip RC oscillator trim register TRIM address 96h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O Reset 0 0 Bits 5 0 loaded with factory stored value during reset UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 23 of 134 NXP Semiconductors UM1 01 47 Table 6 P89LPC952 954 User manual On chip RC oscillator trim register TRIM address 96h bit description Symbol Description TRIM O Trim value Determines the frequency of the internal RC oscillator During reset TRIM 1 these bits are loaded with a stored factory calibration valu
96. ay be required to hold the device in reset when Vpp falls below the minimum specified operating voltage These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 24 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual quartz crystal or ceramic resonator P89LPC952 954 1k Ff T XTAL1 eo a i UC l XTAL2 002aad364 Note The oscillator must be configured in one of the following modes Low frequency crystal medium frequency crystal or high frequency crystal 1 A series resistor may be required to limit crystal drive levels This is especially important for low frequency crystals see text Fig 6 Using the crystal oscillator XTAL1 gt HIGH FREQUENCY MEDIUM FREQUENCY 7 gt RTC XTAL2 lt LOW FREQUENCY rT f wo RCCLK gt LK RC OSCILLATOR RCCLK gt if WITH CLOCK DOUBLER 7 3728 MHz 14 7456 MHz 1 PCLK e WATCHDOG WDT OSCILLATOR 400 kHz 30 20 PCLK TIMER 0 AND 2 002aab409 Note The oscillator must be configured in one of the following modes Low frequency crystal medium frequency crystal or high frequency crystal 1 A series resistor may be required to limit crystal drive levels This is especially important for low frequency crystals see
97. bidirectional output configuration Quasi bidirectional outputs can be used both as an input and output without the need to reconfigure the port This is possible because when the port outputs a logic high it is weakly driven allowing an external device to pull the pin low When the pin is driven low it is driven strongly and able to sink a large current There are three pull up transistors in the quasi bidirectional output that serve different purposes One of these pull ups called the very weak pull up is turned on whenever the port latch for the pin contains a logic 1 This very weak pull up sources a very small current that will pull the pin high if it is left floating A second pull up called the weak pull up is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level This pull up provides the primary source current for a quasi bidirectional pin that is outputting a 1 If this pin is pulled low by an external device the weak pull up turns off and only the very weak pull up remains on In order to pull the pin low under these conditions the external device has to sink enough current to overpower the weak pull up and pull the port pin below its input threshold voltage NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 37 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual The third pull up is referred to as the strong
98. ble port pins are programmed independently Refer to Section 5 1 Port configurations P1 2 to P1 3 are open drain when used as outputs P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below P1 0 Port 1 bit 0 TXDO Transmitter output for serial port 0 P1 1 Port 1 bit 1 RXDO Receiver input for serial port 0 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 6 of 134 NXP Semiconductors UM10147 Table 1 Pin description continued P89LPC952 954 User manual Symbol Pin LQFP48 PLCC44 LQFP44 P1 2 T0 SCL 2 8 2 P1 3 INTO SDA 1 7 1 P1 4 INT1 48 6 44 P1 5 RST 47 5 43 P1 6 46 4 42 P1 7 AD04 43 2 40 P2 0 to P2 5 P2 0 AD07 42 1 39 P2 1 AD06 41 44 38 UM10147_2 Type Description 1 0 UO 1 0 UO 1 0 UO 1 0 UO UO UO UO P1 2 Port 1 bit 2 open drain when used as output TO Timer counter 0 external count input or overflow output open drain when used as output SCL C bus serial clock input output P1 3 Port 1 bit 3 open drain when used as output INTO External interrupt 0 input SDA 2C bus serial data input output P1 4 Port 1 bit 4 INT1 External interrupt 1 input P1 5 Port 1 bit 5 input only RST External Reset input during power on or maybe a reset input output if sele
99. call address Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IZADR 0 1 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free Switched to not addressed SLA mode no recognition of own SLA or General call address Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IZADR 0 1 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free 12 Serial Peripheral Interface SPI UM10147_2 The P89LPC952 954 provides another high speed serial communication interface the SPI interface SPI is a full duplex high speed synchronous communication bus with two operation modes Master mode and Slave mode Up to 3 Mbit s can be supported in either Master or Slave mode It has a Transfer Completion Flag and Write Collisi
100. cause an interrupt if the ADCIO flag is set and the A D interrupt is enabled 7 ENBIO Enable A D boundary interrupt 0 When set will cause an interrupt if the boundary interrupt 0 flag BNDIO is set and the A D interrupt is enabled UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 31 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual Table 13 A D Mode register A ADMODA address O0COh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BNDIO BURSTO SCCO SCANO Reset 0 0 0 0 0 0 0 0 Table 14 A D Mode register A ADMODA address 0COh bit description Bit Symbol Description 0 3 z Reserved 4 SCANO When 1 selects single conversion mode auto scan or fixed channel 5 SCCO When 1 selects fixed and dual channel continuous conversion modes 6 BURSTO When 1 selects auto scan continuous conversion mode 7 BNDIO ADCO boundary interrupt flag When set indicates that the converted result is inside outside of the range defined by the ADCO boundary registers Table 15 A D Mode register B ADMODB address Ath bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLK2 CLK1 CLKO INBNDO BSAO FCIIS Reset 0 0 0 0 0 0 0 0 Table 16 A D Mode register B ADMODB address Ath bit description Bit Symbol Description 0 FCIIS Four conversion intermediate interrupt select When 1 will generate an interrupt after four conversions in fixed channel or dual channe
101. cessible only via direct addressing XDATA External Data or Auxiliary RAM Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR RO or R1 All or part of this space could be implemented on chip The P89LPC952 954 has 256 bytes of on chip XDATA memory CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC952 954 has 8 kB 16 kB of on chip Code memory Table 4 Data RAM arrangement Type Data RAM Size bytes DATA Directly and indirectly addressable memory 128 IDATA Indirectly addressable memory 256 XDATA Indirectly addressable using MOVX MOVC DPTR RO R1 256 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 20 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual The P89LPC952 954 is a single chip microcontroller designed for applications demanding high integration low cost solutions over a wide range of performance requirements The P89LPC952 954 is based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC952 954 in order to reduce component count board space and system cost NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 21 of 134 NXP Semiconductors UM1 01 4
102. ck input configurations Some chip functions continue to operate and draw power during Power down mode increasing the total power used during power down These include e Brownout Detect e Watchdog Timer if WOCLK WDCON 0 is logic 1 e Comparators Note Comparators can be powered down separately with PCONA 5 set to logic 1 and comparators disabled e Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD Le PCONA 7 is logic 1 Total Power down mode This is the same as Power down mode except that the Brownout Detection circuitry and the voltage comparators are also disabled to conserve additional power Note that a brownout reset or interrupt will not occur Voltage comparator interrupts and Brownout interrupt cannot be used as a wake up source The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled The following are the wake up options supported e Watchdog Timer if WOCLK WDCON 0 is logic 1 Could generate Interrupt or Reset either one can wake up the device e External interrupts INTO INT1 when programmed to level triggered mode e Keyboard Interrupt e Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD Le PCONA 7 is logic 1 Note Using the internal RC oscillator to clock the RTC during power down may result in relatively high power consumption Lower power
103. configured independently Refer to Section 5 1 Port configurations All pins have Schmitt triggered inputs Port 5 also provides various special functions as described below P5 0 Port 5 bit 0 High current output P5 1 Port 5 bit 1 High current output P5 2 Port 5 bit 2 High current output P5 3 Port 5 bit 3 High current output P5 4 Port 5 bit 4 High current output P5 5 Port 5 bit 5 High current output P5 6 Port 5 bit 6 High current output P5 7 Port 5 bit 7 High current output Ground 0 V reference negative ADC reference voltage Power supply This is the power supply voltage for normal operation as well as Idle and Power down modes positive ADC reference voltage 1 Input output for P1 0 to P1 4 P1 6 P1 7 Input for P1 5 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 9 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual P89LPC952 954 8 kB 16 kB CODE FLASH internal zept n DATA RAM 256 BYTE i AUXILIARY RAM PORT 5 P5 7 0 p leani PTER 1 Os gt PORT 4 4 7 0 Se ee Ve C PORT 3 SS LEE CONFIGURABLE I Os So es Wo ee CONFIGURABLE I Os P2 5 0 1 P2 7 0 Deg GE ACCELERATED 2 CLOCK 80C51 CPU Be CH o CH um K I C BUS TXDO RXDO TXD1 RXD1 SCL SDA ADOO AD02 AD04 ADO6 ADO1 ADO3 ADO5 ADO7 SPICLK MOSI MISO SS
104. consumption can be achieved by using an external low frequency clock when the Real time Clock is running during power down UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 44 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual Table 28 Power Control register PCON address 87h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMOD1 SMODO BOPD BOI GF1 GEO PMOD1 PMODO Reset 0 0 0 0 0 0 0 0 Table 29 Power Control register PCON address 87h bit description Bit Symbol Description 0 PMODO Power Reduction Mode see Section 6 3 PMOD1 2 GFO General Purpose Flag 0 May be read or written by user software but has no effect on operation 3 GF1 General Purpose Flag 1 May be read or written by user software but has no effect on operation 4 BOI Brownout Detect Interrupt Enable When logic 1 Brownout Detection will generate a interrupt When logic 0 Brownout Detection will cause a reset 5 BOPD Brownout Detect power down When logic 1 Brownout Detect is powered down and therefore disabled When logic 0 Brownout Detect is enabled Note BOPD must be logic 0 before any programming or erasing commands can be issued Otherwise these commands will be aborted 6 SMODO Framing Error Location e When logic 0 bit 7 of SCON is accessed as SMO for the UART e When logic 1 bit 7 of SCON is accessed as the framing error status FE for the UART 7 SMOD1 Doub
105. cted via UCFG1 and UCFG2 When functioning as a reset input or input output a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 When functioning as a reset output or input output an internal reset source will drive this pin LOW Also used during a power on sequence to force ISP mode When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage P1 6 Port 1 bit 6 P1 7 Port 1 bit 7 AD04 ADCO channel 4 analog input Port 2 Port 2 is an 8 bit I O port with a user configurable output type During reset Port 2 latches are configured in the input only mode with the internal pull up disabled The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations All pins have Schmitt triggered inputs Port 2 also provides various special functions as describ
106. curate timer while the rest of the device is powered down The Real time Clock can be an interrupt or a wake up source see Figure 20 The Real time Clock is a 23 bit down counter The clock source for this counter can be either the CPU clock CCLK or the XTAL1 2 oscillator provided that the XTAL1 2 oscillator is not being used as the CPU clock If the XTAL1 2 oscillator is used as the CPU clock then the RTC will use CCLK as its clock source regardless of the state of the RTCS1 0 in the RTCCON register There are three SFRs used for the RTC RTCCON Real time Clock control RTCH Real time Clock counter reload high bits 22 to 15 RTCL Real time Clock counter reload low bits 14 to 7 The Real time clock system timer can be enabled by setting the RTCEN RTCCON 0 bit The Real time Clock is a 23 bit down counter initialized to all 0 s when RTCEN 0 that is comprised of a 7 bit prescaler and a 16 bit loadable down counter When RTCEN is written with logic 1 the counter is first loaded with RTCH RTCL 1111111 and will count down When it reaches all 0 s the counter will be reloaded again with RTCH RTCL 1111111 and a flag RTCF RTCCON 7 will be set Wake up from power down ky Power on reset XTAL2 XTAL1 RTC Reset LOW FREQ MED FREQ HIGH FREQ 7 bit prescaler CCLK internal oscillators 23 bit down counter Fig 20 Real time clock system timer bloc
107. d Bit 5 Symbol Description VCPD Analog Voltage Comparators power down When logic 1 the voltage comparators are powered down User must disable the voltage comparators prior to setting this bit DEEPD Data EEPROM power down When logic 1 the Data EEPROM is powered down Note that in either Power down mode or Total Power down mode the Data EEPROM will be powered down regardless of this bit RTCPD Real time Clock power down When logic 1 the internal clock to the Real time Clock is disabled 7 Reset UM10147_2 The P1 5 RST pin can function as either a digital input P1 5 an active LOW reset input with an internal pullup a bidirectional reset input output open drain output with an internal pullup or as push pull reset output These modes are selected by the RPE Reset Pin Enable bit in UCFG1 and the RPE1 Reset Pin Enable 1 bit in UCFG2 Table 32 Reset pin modes P1 5 RST mode RPE1 UCFG2 0 RPE UCFG1 6 General purpose input 0 0 Reset input with pullup 0 1 Bidirectional reset input output open drain with pullup 1 0 Reset ouput 1 1 Remark During a power up sequence The RPE and RPE1 selection is overridden and this pin always functions as a reset input An external circuit connected to this pin should not hold this pin LOW during a power on sequence as this will keep the device in reset After power up this pin will function as defined by the RPE and RPE1 bits Only a power up reset will tempora
108. d while the 12C interface is in the Master Receiver Mode 2 A data byte has been received while the 12C interface is in the addressed Slave Receiver Mode UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 71 of 134 NXP Semiconductors UM1 01 47 UM10147_2 11 5 P89LPC952 954 User manual Table 66 1 C Control register IZCON address D8h bit description continued Bit Symbol Description 3 SI 12C Interrupt Flag This bit is set when one of the 25 possible I2C states is entered When EA bit and El2C IEN1 0 bit are both set an interrupt is requested when SI is set Must be cleared by software by writing 0 to this bit 4 STO STOP Flag STO 1 In master mode a STOP condition is transmitted to the l2C bus When the bus detects the STOP condition it will clear STO bit automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed Slave Receiver Mode The STO flag is cleared by hardware automatically 5 STA Start Flag STA 1 I2C bus enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits fora STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator When the 12
109. dition in master mode or recovering from an error condition in slave mode If the STA and STO are both set then a STOP condition is transmitted to the I2C bus if it is in master mode and transmits a START condition afterwards If it is in slave mode an internal STOP condition will be generated but it is not transmitted to the bus Table 65 1 C Control register I2CON address D8h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA CRSEL Reset x 0 0 0 0 0 x 0 Table 66 12C Control register I2CON address D8h bit description Bit Symbol Description 0 CRSEL SCL clock selection When set 1 Timer 1 overflow generates SCL when cleared 0 the internal SCL generator is used base on values of I2SCLH and I2SCLL 1 reserved 2 AA The Assert Acknowledge Flag When set to 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 The own slave address has been received 2 The general call address has been received while the general call bit GC in IZADR is set 3 A data byte has been received while the 12C interface is in the Master Receiver Mode 4 A data byte has been received while the ZC interface is in the addressed Slave Receiver Mode When cleared to 0 an not acknowledge high level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been receive
110. ditions are recognized as the beginning and end of a serial transfer In a given application the I2 C bus may operate as a master and as a slave In the slave mode the 12C hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the I2C bus switches to the slave mode immediately and can detect its own slave address in the same serial transfer f A logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW E from master to slave A not acknowledge SDA HIGH O from slave to master S START condition P STOP condition 002aaa933 Fig 31 Format of Slave Transmitter mode NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 76 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual ti o X ADDRESS REGISTER INPUT FILTER P1 3 SDA OUTPUT STAGE BIT COUNTER ARBITRATION CCLK 2 INPUT AND SYNC LOGIC TIMING z FILTER AND S CONTROL 2 P1 2 SCL puts S OUTPUT SERIAL CLOCK interne 5 STAGE GENERATOR timer 1 Ge overflow P1 2 I2CON CONTROL REGISTERS AND I2SC
111. dium or high frequency crystals covering a range from 20 kHz to 18 MHz Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 100 kHz Ceramic resonators are also supported in this configuration Medium speed oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz Ceramic resonators are also supported in this configuration High speed oscillator option This option supports an external crystal in the range of 4 MHz to 18 MHz Ceramic resonators are also supported in this configuration When using a clock frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using a clock frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 22 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 2 3 Clock output The P89LPC952 954 supports a user selectable clock output function on the XTAL2
112. e When writing to either TRIM 2 bit 6 or bit 7 of this register care should be taken to preserve the current TRIM value by reading this register modifying bits 6 or 7 as required and writing the result to TRIM 3 this register TRIM 4 TRIM 5 ENCLK when 1 CCLK is output on the XTAL2 pin provided the crystal oscillator is not being used RCCLK when 1 selects the RC Oscillator output as the CPU clock CCLK This allows for fast switching between any clock source and the internal RC oscillator without needing to go through a reset cycle UM10147_2 2 5 2 6 Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz This oscillator can be used to save power when a high clock frequency is not needed External clock input option In this configuration the processor clock is derived from an external source driving the XTAL1 P3 1 pin The rate may be from 0 Hz up to 18 MHz The XTAL2 P3 0 pin may be used as a standard port pin or a clock output When using an external clock input frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an external clock input frequency above 12 MHz in some applications an external brownout detect circuit m
113. e to disable reception NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 59 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 51 Serial Port 0 Control register SOCON address 98h bit description continued Bit Symbol Description 5 SM2_0 Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is 0 In Mode 0 SM2 should be 0 In Mode 1 SM2 must be 0 6 SM1_0 With SMO defines the serial port mode see Table 54 7 GM0 0 The use of this bit is determined by SMODO in the PCON register If SMODO 0 FE_0 this bit is read and written as SMO which with SM1 defines the serial port mode If SMODO0 1 this bit is read and written as FE Framing Error FE is set by the receiver when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but is cleared by software Note UARTO mode bits SMO_0 and SM1_0 should be programmed when SMOD0 is logic 0 default mode on any reset Table 52 Serial Port 1 Control register S1CON address B5h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMO_0 F SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TL1 HI E 1 Reset xX xX D D xX xX 0 0 Table 53 Serial Port 1 Control register S1CON address B5h bit description Bit Symbol Description Oo Hi Receive interrupt flag 1 Set by hardware at the end of t
114. ebugger Any flash program operation in 2 ms 4 ms for erase program e Programmable security for the code in the Flash for each sector gt 400 000 typical erase program cycles for each byte e 20 year minimum data retention 17 3 Flash programming and erase The P89LPC952 954 program memory consists 1 kB sectors Each sector can be further divided into 64 byte pages In addition to sector erase and page erase a 64 byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time substantially reducing overall programming time Six methods of programming this device are available e Parallel programming with industry standard commercial programmers e In Circuit serial Programming ICP with industry standard commercial programmers e IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to AP Lite NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 107 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual e A factory provided default serial loader located in upper end of user program memory providing In System Programming ISP via the serial port e Two wire serial debugger 17 4 Using
115. ected to each other and either device can be a master or a slave When no SPI operation is occurring both can be configured as masters MSTR 1 with SSIG cleared to 0 and P2 4 SS configured in quasi bidirectional mode When a device initiates a transfer it can configure P2 4 as an output and drive it low forcing a mode change in the other device see Section 12 4 Mode change on SS to slave NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 86 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual I master slave I MISO 8 BIT SHIFT lt T T4 8 BIT SHIFT REGISTER MOSI i S REGISTER I SPICLK SPI CLOCK GENERATOR port I I I d slave I MISO 8 BIT SHIFT MOSI REGISTER SPICLK gt port SS gt 002aaa903 Fig 36 SPI single master multiple slaves configuration In Figure 36 SSIG SPCTL 7 bits for the slaves are logic 0 and the slaves are selected by the corresponding SS signals The SPI master can use any port pin including P2 4 SS to drive the SS pins 12 1 Configuring the SPI Table 81 shows configuration for the master slave modes as well as usages and directions for the modes Table 81 SPI master and slave selection SPEN SSIG SSPin MSTR Master MISO MOSI SPICLK Remarks or Slave Mode 0 D P2 40 x SPI P2 30 p2 altl P2 50 SPI disabled P2 2 P2 3 P2 4 P2 5 are used Disabled as port pins 1 0 0 0
116. ed below P2 0 Port 2 bit 0 AD07 ADCO channel 7 analog input P2 1 Port 2 bit 1 AD06 ADCO channel 6 analog input NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 7 of 134 NXP Semiconductors UM10147 Table 1 Pin description continued P89LPC952 954 User manual Symbol P2 2 MOSI P2 3 MISO P2 4 SS P2 5 SPICLK P2 6 P2 7 P3 0 to P3 1 P3 0 XTAL2 CLKOUT P3 1 XTAL1 P4 0 to P4 7 UM10147_2 Pin LQFP48 PLCC44 30 34 29 33 28 32 27 31 26 LQFP44 28 27 26 25 Type Description 1 0 UO UO 1 0 gl 1 0 UO 1 0 UO UO 1 0 1 0 UO 1 0 P2 2 Port 2 bit 2 MOSI SPI master out slave in When configured as master this pin is output when configured as slave this pin is input P2 3 Port 2 bit 3 MISO When configured as master this pin is input when configured as slave this pin is output P2 4 Port 2 bit 4 SS SPI Slave select P2 5 Port 2 bit 5 SPICLK SPI clock When configured as master this pin is output when configured as slave this pin is input P2 6 Port 2 bit 6 P2 7 Port 2 bit 7 Port 3 Port 3 is a 2 bit I O port with a user configurable output type During reset Port 3 latches are configured in the input only mode with the internal pull up disabled The operation of Port 3 pins as inputs and outputs depends upon the port
117. ed received ACK returned 70H General call No I2DAT action x 0 0 0 Data byte will be received and NOT address 00H has or ACK will be returned been received no I2DAT action x 0 0 1 Data byte will be received and ACK ACK has been will be returned returned 78H Arbitration lostin no I2DAT action x 0 0 0 Data byte will be received and NOT SLA R W as or ACK will be returned master General uo I2DAT action x 0 0 1 Data byte will be received and ACK call address has will be returned been received ACK bit has been returned 80H Previously Read data byte or x 0 0 0 Data byte will be received and NOT addressed with ACK will be returned own SLA address read data byte x 0 0 1 Data byte will be received ACK bit Data has been will be returned received ACK has been returned UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 80 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual Table 74 Slave Receiver mode continued Siatus code Status of the I2C Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA 88H Previously Read data byte or 0 0 0 0 Switched to not addressed SLA addressed with mode no recognition of own SLA or own SLA address general address Data nas ER read data byte 0 0 0 1 Switched to not addressed SLA received NACK or mode Own SLA will be recognized has been returned gener
118. ed if the A D interrupt is enabled In Power down mode or Total Power down mode the A D does not function If the A D is enabled it will consume power Power can be reduced by disabling the A D Table 11 A D Control register 0 ADCONO address 97h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ENBIO ENADCIO TMMO EDGEO ADCIO ENADCO ADCS01 ADCSO00 Reset 0 0 0 0 0 0 0 0 Table 12 A D Control register 0 ADCONO address 97h bit description Bit Symbol Description 1 0 ADCS01 ADCS00 A D start mode bits see below 00 Timer Trigger Mode when TMMO 1 Conversions starts on overflow of Timer 0 When TMMO 0 no start occurs stop mode 01 Immediate Start Mode Conversion starts immediately 10 Edge Trigger Mode Conversion starts when edge condition defined by bit EDGEO occurs 2 ENADCO Enable ADCO When set 1 enables ADCO when 0 the ADC is in power down 3 ADCIO A D Conversion complete Interrupt 0 Set when any conversion or set of multiple conversions has completed Cleared by software 4 EDGEO An edge conversion start is triggered by a falling edge on P1 4 when EDGEO 0 while in edge triggered mode An edge conversion start is triggered by a rising edge on P1 4 when EDGEO 1 while in edge triggered mode 5 TMMO Timer Trigger Mode 0 Selects either stop mode TMMO 0 or timer trigger mode TMM0 1 when the ADC GO and ADCS00 bits 00 6 ENADCIO Enable A D Conversion complete Interrupt 0 When set will
119. en while SS is active low a write collision error results The operation is undefined if CPHA is logic 0 and SSIG is logic 1 When CPHA equals one SSIG may be set to logic 1 If SSIG 0 the SS pin may remain active low between successive transfers can be tied low at all times This format is sometimes preferred in systems having a single fixed master and a single slave driving the MISO data line Additional considerations for a master In SPI transfers are always initiated by the master If the SPI is enabled SPEN 1 and selected as master writing to the SPI data register by the master starts the SPI clock generator and data transfer The data will start to appear on MOSI about one half SPI bit time to one SPI bit time after data is written to SPDAT Note that the master can select a slave by driving the SS pin of the corresponding device low Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave at the same time the data in SPDAT register in slave side is shifted out on MISO pin to the MISO pin of the master After shifting one byte the SPI clock generator stops setting the transfer completion flag SPIF and an interrupt will be created if the SPI interrupt is enabled ESPI or IEN1 3 1 The two shift registers in the master CPU and slave CPU can be considered as one distributed 16 bit circular shift register When data is shifted from the master to the slave
120. er consumption than in Idle mode This can allow bypassing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution Low power select The P89LPC952 954 is designed to run at 18 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to a logic 1 to lower the power consumption further On any reset CLKLP is logic 0 allowing highest performance This bit can then be set in software if CCLK is running at 8 MHz or slower 3 A D converter UM10147_2 3 1 General description The P89LPC952 954 has a 10 bit 8 channel multiplexed successive approximation analog to digital converter module A block diagram of the A D converter is shown in Figure 8 The A D consists of an 8 input multiplexer which feeds a sample and hold circuit providing an input signal to one of two comparator inputs The control logic in combination with the SAR drives a digital to analog converter which provides the other input to the comparator The output of the comparator is fed to the SAR 3 2 A D features e 10 bit 8 channel multiplexed input successive approximation A D converter e Eight result register pairs e Six operating modes Fixed channel single conversion mode Fixed channel continuous conversion mode Auto scan single conversion mode Auto scan continuous conversion mode
121. er Control 87H SOCON Serial Port UARTO Control 98H SOBUF Serial Port UARTO Data Buffer 99H SOADDR Serial Port UARTO Address A9H SOADEN Serial Port UARTO Address Enable Don SOSTAT Serial Port UARTO Status BAH BRGR1_0 Baud Rate Generator 0 High Byte BFH BRGRO_O Baud Rate Generator 0 Low Byte BEH BRGCON_0 Baud Rate Generator 0 Control BDH S1CON Serial Port UART1 Control B5H S1BUF Serial Port UART1 Data Buffer FFBOH S1ADDR Serial Port UART1 Address FFB2H S1ADEN Serial Port UART1 Address Enable FFB1H S1STAT Serial Port UART1 Status D4H BRGR1_1 Baud Rate Generator 1 Rate High Byte FFB5H BRGRO_1 Baud Rate GeneratoR 1 Rate Low FFB4H Byte BRGCON_1 Baud Rate Generator 1 Control FFB3H Baud Rate generator and selection The P89LPC952 954 enhanced UART has an independent Baud Rate Generator The baud rate is determined by a value programmed into the BRGR1_n and BRGRO_n SFRs Each UART can use either Timer 1 or the baud rate generator output as determined by BRGCON_n 2 1 see Figure 21 Note that Timer T1 is further divided by 2 if the SMOD1 bit PCON 7 is set and thus applies to both UARTs The independent Baud Rate Generator uses CCLK NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 57 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual 10 7 Updating the BRGR1 and BRGRO SFRs The baud rate SFRs BRGR1_n and BRGRO_n must only be loaded when the Baud Rate
122. ersions 30 Boundary limits interrupt 30 Clock divider 00 0000 c eee eee 30 I O pins used with ADC functions 31 Power down and Idle mode 31 Interrupts 33 Interrupt priority structure 34 External Interrupt pin glitch suppression 35 eh ln CEET 36 Port configurations 37 Quasi bidirectional output configuration 37 Open drain output configuration 38 Input only configuration 39 Push pull output configuration 39 Port 0 and Analog Comparator functions 40 Additional port features 40 Power monitoring functions 42 Brownout detection s a saaana 42 Power on detection s anaana nen 43 10 9 10 10 10 11 10 12 10 13 10 14 10 15 10 16 10 17 10 18 10 19 10 20 11 11 1 11 2 11 3 11 4 11 5 11 6 11 6 1 11 6 2 11 6 3 11 6 4 12 12 1 12 2 Power reduction modes 43 ReS t ee NEE REES e e 46 Reset vector nuanua annann nnr 48 Timers 0 and 48 Mode ANE de ud ia E SE e ere 49 Mode WEEN 50 Mode EE 50 MOG WEE 50 Mod 6 304 d tie ees A he ee ee 50 Timer overflow toggle output 52 Real time clock system timer 53 Real time clock source 54 Changing RTCS1 RTCSO 54 Real time clock interrupt wake up 54 Reset sources affecting the Real
123. ggered using the two wire debugger interface The following conditions are required to enter the debug mode e UCFG2 5 has been programmed e a 10K pullup resistor to Vpp is connected to SCLK e a 10K pullup resistor to Vpp is connected to SDAT e the debug pins are connected to a commercially available debugger e either a power on reset or external reset occurs UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 105 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual The Freeze register allows the user to selectively control clocking of peripheral device timers while in the debugger mode When a freeze bit is set the peripheral device will not be clocked while the debugger is performing monitor operations However when the debugger releases program control to the user s application program peripheral clocking will be resumed while executing user s code Table 96 FREEZE register address FFDOh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTC_F WDT E TE TO_F Reset x x x 0 0 0 0 0 Table 97 FREEZE register address FFDOh bit description Bit Symbol Description 0o TOF Timer 0 Freeze bit When set the clock to Timer 0 will be frozen while performing monitor operations in debugger mode 1 T1_F Timer 1Freeze bit When set the clock to Timer 1 will be frozen while performing monitor operations in debugger mode 2 WDI_F Watchdog timer Freeze bit When set
124. he 8th bit time in Mode 0 or approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO it is set near the middle of the 9th data bit bit 8 If SMODO 1 it is set near the middle of the stop bit see SM2_1 S1CON 5 for exceptions Must be cleared by software 1 TIA Transmit interrupt flag 1 Set by hardware at the end of the 8th bit time in Mode 0 or at the stop bit see description of INTLO_1 bit in S1STAT register in the other modes Must be cleared by software 2 RB8_1 The 9th data bit that was received in Modes 2 and 3 In Mode 1 SM2 must be 0 RB8_1 is the stop bit that was received In Mode 0 RB_1 is undefined 3 TB8_1 The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired 4 HEN 1 Enables serial reception Set by software to enable reception Clear by software to disable reception 5 SM2_1 Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then RI_1 will not be activated if the received 9th data bit RB8_1 is 0 In Mode 0 SM2_1 should be 0 In Mode 1 SM_1 must be 0 SM1_1 With SMO_1 defines the serial port mode see Table 54 MO 1 The use of this bit is determined by SMODO in the PCON register If SMODO 0 FE_1 this bit is read and written as SMO_1 which with SM1_1 defines the serial port mode If SMODO 1 this bit is read and written as FE_1 Framing Error FE_1 is set by the receiver
125. he Flash can be read and written as bytes The Sector and Page Erase functions can erase any Flash sector 1 kB or page 64 bytes The Chip Erase operation will erase the entire program memory Five Flash programming methods are available On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC952 954 Flash reliably stores memory contents even after 400 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms P89LPC952 954 uses Vpp as the supply voltage to perform the Program Erase algorithms 17 2 Features e Parallel programming with industry standard commercial programmers e In Circuit serial Programming ICP with industry standard commercial programmers e IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to AP Lite e Default serial loader providing In System Programming ISP via the serial port located in upper end of user program memory e Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space providing flexibility to the user e Programming and erase over the full operating voltage range Read Programming Erase using ISP IAP IAP Lite ICP and two wire serial d
126. he Power down mode stops the oscillator in order to minimize power consumption The P89LPC952 954 exits Power down mode via any reset or certain interrupts external pins INTO INT1 brownout Interrupt keyboard Real time Clock System Timer watchdog and comparator trips Waking up by reset is only enabled if the corresponding reset is enabled and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit IENO 7 is set External interrupts should be programmed to level triggered mode to be used to exit Power down mode In Power down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled In Power down mode the power supply voltage may be reduced to the RAM keep alive voltage VRAM This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vor has been lowered to VRAM therefore it is recommended to wake up the processor via Reset in this situation Vpp must be raised to within the operating range before the Power down mode is exited When the processor wakes up from Power down mode it will start the oscillator immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 1024 CPU clocks after start up when one of the crystal oscillator configurations is used or 256 clocks after start up for the internal RC or external clo
127. he combined TI RI CIDIS_1 0 When cleared 0 FE_1 BR_1 OE_1 cannot cause an interrupt Note FE_1 BR_1 or OE_1 is often accompanied by a RI which will generate an interrupt regardless of the state of STINT_1 1 OE_1 Overrun Error 1 flag is set if a new character is received in the receiver buffer while it is still full before the software has read the previous character from the buffer i e when bit 8 of a new byte is received while RI_1 in S1CON is still set Cleared by software 2 BR_1 Break Detect flag A break is detected when any 11 consecutive bits are sensed low Cleared by software 3 FEI Framing error flag is set when the receiver fails to see a valid STOP bit at the end of the frame Cleared by software 4 DBISEL Double buffering transmit interrupt select Used only if double buffering is enabled 1 This bit controls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to S1BUF and there is also one more transmit interrupt generated at the beginning INTLO_1 0 or the end INTLO_1 1 of the STOP bit of the last character sent i e no more data in buffer This last interrupt can be used to indicate that all transmit operations are over When cleared 0 only one transmit interrupt is generated per character written to S1BUF Must be logic 0 when double buffering is disabled Note that except for the first character w
128. he intended programmed value IAP uses the MOVC instruction to perform this verify Attempts to program user code that is MOVC protected can be programmed but will generate this error after the programming cycle has been completed 4to7 unused reads as a logic 0 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 119 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 104 IAP function calls IAP function IAP call parameters Program User Code Page Input parameters requires key ACC 00h R3 number of bytes to program R4 page address MSB R5 page address LSB R7 pointer to data buffer in RAM Fi 0h use IDATA Return parameter s R7 status Carry set on error clear on no error Read Version Id Input parameters ACC 01h Return parameter s R7 IAP version id Misc Write requires key Input parameters ACC 02h R5 data to write R7 register address 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 to 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 OC Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 10 Clear Configuration Protection 18 Security Byte 8 89LPC954 19 Security Byte 9 89LPC954 1A Security Byte 10 89LPC954 1B Security Byte 11 89LPC954 1C Security Byte 12 89LPC954 1D Security Byte 13 89LPC954 1E Security Byte 14 89LPC954
129. idirectional mode The open drain port configuration is shown in Figure 11 An open drain port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC952 954 data sheet Dynamic characteristics for glitch filter specifications NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 38 of 134 NXP Semiconductors UM1 01 47 5 4 5 5 UM10147_2 P89LPC952 954 User manual port TI pin port latch Ei data input data glitch rejection 002aaa915 Fig 11 Open drain output Input only configuration The input port configuration is shown in Figure 12 It is a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC 952 954 data sheet Dynamic characteristics for glitch filter specifications input port data pin glitch rejection 002aaa916 Fig 12 Input only Push pull output configuration The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output The push pull port configuration is shown in Figure 13 A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the
130. ight bits and BOOTVEC as the upper bits after a reset See Section 7 1 Reset vector on page 48 reserved Activate Write Protection bit When this bit is cleared the internal Write Enable flag is forced to the set state thus writes to the flash memory are always enabled When this bit is set the Write Enable internal flag can be set or cleared using the Set Write Enable SWE or Clear Write Enable CWE commands Configuration Write Protect bit Protects inadvertent writes to the user programmable configuration bytes UCFG1 BOOTVEC and BOOTSTAT If programmed to a logic 1 the writes to these registers are disabled If programmed to a logic 0 writes to these registers are enabled This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command to FMCON followed by writing 96H to FMDATA Disable Clear Configuration Protection command If Programmed to 1 the Clear Configuration Protection CCP command is disabled during ISP or IAP modes This command can still be used in ICP or parallel programmer modes If programmed to 0 the CCP command can be used in all programming modes This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command in either ICP or parallel programmer modes UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008
131. iguration UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 3 of 134 NXP Semiconductors UM10147 UM10147_2 P89LPC952 954 User manual P1 3 INTO SDA P1 2 TO SCL P1 1 RXDO P1 0 TXDO P3 1 XTAL1 P3 0 XTAL2 CLKOUT VDD P5 7 P5 6 P5 5 P5 4 Fig 2 44 P1 4 INT1 43 P1 5 RST 42 P1 6 41 Vss 37 P0 0 CMP2 KBI0 AD05 36 PO 1 CIN2B KBI1 AD00 35 P0 2 CIN2A KBI2 AD01 34 P0 3 CIN1B KBI3 AD02 40 P1 7 AD04 39 P2 0 AD07 38 P2 1 AD06 P89LPC952FBD P89LPC954FBD 19 P5 3 12 P5 2 13 LQFP44 pin configuration P5 1 14 Vss 16 P4 6 18 P5 0 15 P4 7 TCLK 17 P4 5 TDI P4 4 20 P4 3 RXD1 21 P4 2 TXD1 22 P0 4 CIN1A KBI4 AD03 P0 5 CMPREF KBI5 P0 6 CMP1 KBI6 Von P0 7 T1 KBI7 P2 2 MOSI P2 3 MISO P2 4 SS P2 5 SPICLK P4 0 P4 1 TRIG 002aab306 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 4 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual P1 3 INTO SDA P1 2 TO SCL P1 1 RXDO P1 0 TXDO P2 7 P3 1 XTAL1 P3 0 XTAL2 CLKOUT VDD P5 7 P5 6 P5 5 P5 4 48 P1 4 INT1 47 P1 5 RST 46 P1 6 45 Vss 40 P0 0 CMP2 KBI0 AD05 39 PO 1 CIN2B KBI1 AD00 38 P0 2 CIN2A KBI2 AD01 37 P0 3 CIN1B KBI3 AD02 43 P1 7 AD04 42 P2 0 AD07 41 P2 1 AD06 44 VREFN P0 4 CIN1A KBI4 AD03 P0 5 CMPREF KBI5 P0 6 CMP1 KBI6 VREFP V
132. ine where the user should load the slave address to I2DAT Data Register and data direction bit SLA W The SI bit must be cleared before the data transfer can continue When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status codes are 18h 20h or 38h for the master mode or 68h 78h or OBOh if the slave mode was enabled setting AA Logic 1 The appropriate action to be taken for each of these status codes is shown in Table 72 Bal logic 0 write data transferred logic 1 read n Bytes acknowledge E from master to slave Amiacknowiedgs SDA LOW A not acknowledge SDA HIGH CT from slave to master S START condition P STOP condition 002aaa929 Fig 27 Format in the Master Transmitter mode 11 6 2 Master Receiver mode In the Master Receiver Mode data is received from a slave transmitter The transfer started in the same manner as in the Master Transmitter Mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to 2C Data Register I2DAT The SI bit must be cleared before the data transfer can continue When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 4
133. ined undefined 111 0 00 External clock input External clock input 01 DIVM 10 11 External clock input DIVM 1 00 External clock input Internal RC oscillator 01 10 11 Internal RC oscillator Table 42 Real time Clock Control register RTCCON address D1h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCF RTCS1 RTCSO ERTC RTCEN Reset 0 1 1 x x x 0 0 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 55 of 134 NXP Semiconductors UM1 01 47 10 UARTs P89LPC952 954 User manual Table 43 Real time Clock Control register RTCCON address Dth bit description Bit Symbol Description 0 RTCEN Real time Clock enable The Real time Clock will be enabled if this bit is logic 1 Note that this bit will not power down the Real time Clock The RTCPD bit PCONA 7 if set will power down and disable this block regardless of RTCEN 1 ERTC Real time Clock interrupt enable The Real time Clock shares the same interrupt as the watchdog timer Note that if the user configuration bit WOTE UCFG1 7 is logic 0 the watchdog timer can be enabled to generate an interrupt Users can read the RTCF RTCCON 7 bit to determine whether the Real time Clock caused the interrupt reserved RTCSO Real time Clock source select see Table 41 RTCS1 RTCF Real time Clock Flag This bit is set to logic 1 when the 23 bit Real time Clock reaches a count of logic 0 It can be cleared in software UM10147
134. ister A single conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel see Table 7 The user may select whether an interrupt if enabled will be generated after either the first four conversions have occurred or all selected channels have been converted If the user selects to generate an interrupt after the first four input channels have been converted a second interrupt will be generated after the remaining input channels have been converted If only a single channel is selected this is equivalent to single channel single conversion mode The channels are converted from LSB to MSB order in ADINS This mode is selected by setting the SCANDO bit in the ADMODA register Auto scan continuous conversion mode Any combination of the eight input channels can be selected for conversion by setting a channel s respective bit in the ADINS register A conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel See Table 7 The user may select whether an interrupt if enabled will be generated after either the first four conversions have occurred or all selected channels have been converted If the user selects to generate an interrupt after the four input channels have been converted a second interrupt will be generated after the remaining input channels have been co
135. it 0 002aaa934 1 Not defined Fig 37 SPI slave transfer format with CPHA 0 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 90 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Clock cycle 1 SPICLK CPOL 0 SPICLK CPOL 1 MOSI input MISO output SS if SSIG bit 0 002aaa935 1 Not defined Fig 38 SPI slave transfer format with CPHA 1 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 91 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Clock cycle il i SPICLK CPOL 0 SPICLK CPOL 1 MOSI input DORD 0 MSB LSB DORD 1 LSB MSB l l l l l l MISO output SS if SSIG bit 0 l l t 002aaa936 1 Not defined Fig 39 SPI master transfer format with CPHA 0 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 92 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Clock cycle il SPICLK CPOL 0 SPICLK CPOL 1
136. it in ADCONO if the conversion was started in Timer triggered mode Prior to resuming conversions the user will need to reset the input multiplexer to the first user specified channel This can be accomplished by writing the ADINS register with the desired channels Boundary limits interrupt The A D converter has both a high and low boundary limit register The user may select whether an interrupt is generated when the conversion result is within or equal to the high and low boundary limits or when the conversion result is outside the boundary limits An interrupt will be generated if enabled if the result meets the selected interrupt criteria The boundary limit may be disabled by clearing the boundary limit interrupt enable An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits In this case after the four MSBs have been converted these four bits are compared with the four MSBs of the boundary high and low registers If the four MSBs of the conversion meet the interrupt criteria i e outside the boundary limits an interrupt will be generated if enabled If the four MSBs do not meet the interrupt criteria the boundary limits will again be compared after all 8 MSBs have been converted The boundary status register BNDSTAO flags the channels which caused a boundary interrupt Clock divider The A D converter requires that its internal clock source be in the range of 320 kHz
137. k diagram Interrupt if enabled H shared with WDT i RTC underflow flag RTC enable RTC clk select ERTC 002aaa924 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 53 of 134 NXP Semiconductors UM1 01 47 UM10147_2 9 1 9 2 9 3 9 4 P89LPC952 954 User manual Real time clock source RTCS1 RTCSO RTCCONJ 6 5 are used to select the clock source for the RTC if either the Internal RC oscillator or the internal WD oscillator is used as the CPU clock If the internal crystal oscillator or the external clock input on XTAL1 is used as the CPU clock then the RTC will use CCLK as its clock source Changing RTCS1 RTCSO RTCS1 RTCSO cannot be changed if the RTC is currently enabled RTCCON 0 1 Setting RTCEN and updating RTCS1 RTCSO may be done in a single write to RTCCON However if RTCEN 1 this bit must first be cleared before updating RTCS1 RTCSO Real time clock interrupt wake up If ERTC RTCCON 1 EWDRT IEN1 0 6 and EA IENO 7 are set to logic 1 RTCF can be used as an interrupt source This interrupt vector is shared with the watchdog timer It can also be a source to wake up the device Reset sources affecting the Real time clock Only power on reset will reset the Real time Clock and its associated SFRs to their default state Table 41 Real time Clock System Timer clock sources FOSC2 0 RCCLK RTCS1 0 RTC clock source CPU clock source 000 0 0
138. l continuous modes In any of the scan modes setting this bit will generate an interrupt after the fourth conversion if the number of channels selected is greater than four 1 BSAO ADCO Boundary Select All When 1 BNDIO will be set if any ADCO input exceeds the boundary limits When 0 BNDIO will be set only if the ADOO input exceeded the boundary limits 2 3 Reserved INBNDO When set 1 generates an interrupt if the conversion result is inside or equal to the boundary limits When cleared 0 generates an interrupt if the conversion result is outside the boundary limits 75 CLK2 CLK1 CLKO Clock divider to produce the ADC clock Divides CCLK by the value indicated below The resulting ADC clock should be 9 MHz or less A minimum of 320 kHz is required to maintain A D accuracy CLK2 0 Divisor 000 1 001 2 010 3 011 4 011 5 011 6 011 7 011 8 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 32 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 17 A D Input select ADINS address A3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol AINO7 AINO6 AINO5 AINO4 AINO3 AINO2 AINO1 AINOO Reset 0 0 0 0 0 0 0 0 Table 18 A D Input select ADINS address A3h bit description Bit Symbol Description 0 AINOO When set enables the ADOO pin for sampling and conversion 1 AINO1 When set enables the ADO1 pin for sampling and conversion
139. le Baud Rate bit for the serial port UART when Timer 1 is used as the baud rate source When logic 1 the Timer 1 overflow rate is supplied to the UART When logic 0 the Timer 1 overflow rate is divided by two before being supplied to the UART See Section 10 Table 30 Power Control register A PCONA address B5h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCPD DEEPD VCPD ADPD I2PD SPPD SPD Reset 0 0 0 0 0 0 0 0 Table 31 Power Control register A PCONA address B5h bit description Bit Symbol Description 0 Not used 1 SPD Serial Port UART power down When logic 1 the internal clock to the UART is disabled Note that in either Power down mode or Total Power down mode the UART clock will be disabled regardless of this bit 2 SPPD SPI power down When logic 1 the internal clock to the SPI is disabled Note that in either Power down mode or Total Power down mode the SPI clock will be disabled regardless of this bit 3 I2PD IC power down When logic 1 the internal clock to the I2C bus is disabled Note that in either Power down mode or Total Power down mode the 12C clock will be disabled regardless of this bit 4 ADPD A D converter power down When logic 1 the ADC is powered down UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 45 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 31 Power Control register A PCONA address B5h bit description continue
140. mer in Timer mode Figure 45 shows the Watchdog Timer in Timer Mode In this mode any changes to WDCON are written to the shadow register after one watchdog clock cycle A watchdog underflow will set the WDTOF bit If IENO 6 is set the watchdog underflow is enabled to cause an interrupt WDTOF is cleared by writing a logic 0 to this bit in software When an underflow occurs the contents of WDL is reloaded into the down counter and the watchdog timer immediately begins to count down again A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs Incorrect feeds are ignored in this mode MOV WFEED1 0A5H S A MOV WFEED2 05AH watchdog oscillator m PRESCALER Lo S BIT DOWN interrupt PCLK i PRESCALER O COUNTER nternup A A A k D WDCON A7H PRE2 PRE1 WDRUN WDTOF WDCLK pre2 pret preo f worun woror woe 002aaa939 Fig 45 Watchdog Timer in Timer Mode WDTE 0 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 103 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 15 5 Power down operation The WDT oscillator will continue to run in power down consuming approximately 50 pA as long as the WDT oscillator is selected as the clock source for the WDT Selecting PCLK as the WDT source will result in the WDT oscillator going into power down with the rest of
141. mmercial programmers to program and erase these devices without removing the microcontroller from the system The In Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC952 954 through a two wire serial interface NXP has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ICP function uses five pins Vpp Vss P0 5 P0 4 and RST Only a small connector needs to be available to interface your application to an external programmer in order to use this feature NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 111 of 134 NXP Semiconductors UM1 01 47 17 6 17 7 17 8 P89LPC952 954 User manual ISP and IAP capabilities of the P89LPC952 954 An In Application Programming IAP interface is provided to allow the end user s application to erase and reprogram the user code memory In addition erasing and reprogramming of user programmable bytes including UCFG1 the Boot Status Bit and the Boot Vector is supported As shipped from the factory the upper 512 bytes of user code space contains a serial In System Programming ISP loader allowing for the device to be programmed in circuit through the serial port This ISP boot loader will in turn call low level routines through the same common entry point that can be used by the end user applica
142. mode A single input channel can be selected for continuous conversion The results of the conversions will be sequentially placed in the eight result register pairs see Table 8 The user may select whether an interrupt can be generated after every four or every eight NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 27 of 134 NXP Semiconductors UM1 01 47 UM10147_2 3 2 1 3 3 2 1 4 3 2 1 5 P89LPC952 954 User manual conversions Additional conversion results will again cycle through the result register pairs overwriting the previous results Continuous conversions continue until terminated by the user This mode is selected by setting the SCCO bit in the ADMODA register Table 8 Result registers and conversion results for fixed channel continuous conversion mode Result register Contains ADODATOR L Selected channel first conversion result ADODAT1R L Selected channel second conversion result ADODAT2R L Selected channel third conversion result ADODAT3R L Selected channel fourth conversion result ADODAT4R L Selected channel fifth conversion result ADODATS5R L Selected channel sixth conversion result ADODATE6R L Selected channel seventh conversion result ADODAT7R L Selected channel eighth conversion result Auto scan single conversion mode Any combination of the eight input channels can be selected for conversion by setting a channel s respective bit in the ADINS reg
143. modes are described later in this section Table 35 Timer Counter Mode register TMOD address 89h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1GATE T1C T TiM1 T1MO TOGATE TOC T TOM1 TOMO Reset 0 0 0 0 0 0 0 0 Table 36 Timer Counter Mode register TMOD address 89h bit description Bit Symbol Description 0 TOMO Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the 1 TOM1 Timer 0 mode see Table 38 2 TOC T Timer or Counter selector for Timer 0 Cleared for Timer operation input from CCLK Set for Counter operation input from TO input pin 3 TOGATE Gating control for Timer 0 When set Timer Counter is enabled only while the INTO pin is high and the TRO control pin is set When cleared Timer 0 is enabled when the TRO control bit is set UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 48 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 36 Timer Counter Mode register TMOD address 89h bit description continued Bit Symbol Description T1MO Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the 5 TIM1 Timer 1 mode see Table 38 6 TiC _ Timer or Counter Selector for Timer 1 Cleared for Timer operation input from CCLK Set for Counter operation input from T1 input pin 7 T1IGATE Gating control for Timer 1 When set Timer Counter is e
144. n load data byte x 0 0 1 Data byte will be transmitted ACK returned will be received Boh Arbitration lostin Load data byte or x 0 0 0 Last data byte will be transmitted SLA R W as and ACK bit will be received master Own load data byte x 0 0 1 Data byte will be transmitted ACK SLA R has been bit will be received received ACK has been returned B8H Data byte in Load data byte or x 0 0 0 Last data byte will be transmitted I2DAT has been and ACK bit will be received transmitted ACK load data byte x 0 0 1 Data byte will be transmitted ACK has been received will be received UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 82 of 134 NXP Semiconductors UM10147 Table 75 Slave Transmitter mode continued P89LPC952 954 User manual Status code I2STAT COH C8H Status of the EC hardware Data byte in I2DAT has been transmitted NACK has been received Last data byte in I2DAT has been transmitted AA 0 ACK has been received Application software response to from I2DAT No I2DAT action or no I2DAT action or no I2DAT action or no I2DAT action No I2DAT action or no I2DAT action or no I2DAT action or no I2DAT action to I2CON STA STO sl AA 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 Next action taken by BC hardware Switched to not addressed SLA mode no recognition of own SLA or General
145. n results for dual channel continuous conversion mode Result register Contains ADODATOR L First channel first conversion result ADODAT1R L Second channel first conversion result ADODAT2R L First channel second conversion result ADODAT3R L Second channel second conversion result ADODAT4R L First channel third conversion result ADODAT5R L Second channel third conversion result ADODAT6R L First channel fourth conversion result ADODAT7R L Second channel fourth conversion result 3 2 1 6 Single step mode This special mode allows single stepping in an auto scan conversion mode Any combination of the eight input channels can be selected for conversion After each channel is converted an interrupt is generated if enabled and the A D waits for the next start condition The result of each channel is placed in the result register which corresponds to the selected input channel See Table 7 May be used with any of the start modes This mode is selected by clearing the BURSTO SCCO and SCANDO bits in the ADMODA register 3 2 2 Conversion mode selection bits The A D uses three bits in ADMODA to select the conversion mode These mode bits are summarized in Table 10 below Combinations of the three bits other than the combinations shown are undefined Table 10 Conversion mode bits Buren SCC Scan ADCO conversion mode 0 0 0 Single step 0 0 1 Fixed channel single Auto scan single 0 1 0 Fixed channel continuous
146. n the device Instead the page erase function can be used to erase the eight 64 byte pages located in this sector A custom boot loader can be written with the Boot Vector set to the custom boot loader if desired Table 101 Boot loader address and default Boot vector Product Flash size End Signature bytes Sector Page Pre programmed Default Boot address Mfg id Id 1 Id2 size size serial loader vector P89LPC952 8kB x 8 1FFFh 15h DDh 28h 1kBx8 64x8 1E00hto 1FFFh 1Fh P89LPC954 16kBx8 3FFFh 15h DDh Ah 1kBx8 64x8 3E00h to 3FFFh 3Fh 17 9 Hardware activation of Boot Loader The boot loader can also be executed by forcing the device into ISP mode during a power on sequence see Figure 47 This is accomplished by powering up the device with the reset pin initially held low and holding the pin low for a fixed time after Vpp rises to its UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 112 of 134 NXP Semiconductors UM1 01 47 UM10147_2 17 10 17 11 P89LPC952 954 User manual normal operating value This is followed by three and only three properly timed low going pulses Fewer or more than three pulses will result in the device not entering ISP mode Timing specifications may be found in the data sheet for this device This has the same effect as having a non zero status bit This allows an application to be built that will normally execute the user code but can be manually forced into ISP
147. nabled only while the INT1 pin is high and the TR1 control pin is set When cleared Timer 1 is enabled when the TR1 control bit is set Table 37 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1M2 TOM2 Reset D D D 0 D x x 0 Table 38 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit description Bit Symbol Description D TOM2 Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the Timer 0 mode see Table 38 1 3 reserved 4 T1iM2 Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the Timer 1 mode see Table 38 The following timer modes are selected by timer mode bits TnM 2 0 000 8048 Timer TLn serves as 5 bit prescaler Mode 0 001 16 bit Timer Counter THn and TLn are cascaded there is no prescaler Mode 1 010 8 bit auto reload Timer Counter THn holds a value which is loaded into TLn when it overflows Mode 2 011 Timer 0 is a dual 8 bit Timer Counter in this mode TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by the Timer 1 control bits see text Timer 1 in this mode is stopped Mode 3 100 Reserved User must not configure to this mode 101 Reserved User must not configure to this mode 110 PWM mode see Section 8 5
148. nerator 1 control Baud rate generator 1 rate low Baud rate generator 1 rate high Peripheral clock freeze Port 4 output mode 1 Port 4 output mode 2 Port 5 output mode 1 Port 5 output mode 3 Serial port 1 address register Serial port 1 address enable Serial port 1 data buffer register SFR addr FFF1H FFEDH FFB3H FFB4H FFB5H FFDOH FFB8H FFB9H FFBAH FFBBH FFB2H FFB1H FFBOH Bit functions and addresses Reset value MSB LSB Hex Binary ADODAT7 9 2 SBRGS_ BRGEN_ 00 2 xxxx xx00 1 1 RTC_F WDTE T1_F TO_F 00 vaxt 0000 P4M1 7 P4M1 6 P4M1 5 P4M1 4 P4M1 3 P4M1 2 P4M1 1 P4M1 0 IER 11111111 P4M2 7 P4M2 6 P4M2 5 P4M2 4 P4M2 3 P4M2 2 P4M2 1 P4M2 0 ool 0000 0000 P5M1 7 P5M1 6 P5M1 5 P5M1 4 P5M1 3 P5M1 2 P5M1 1 P5M1 0 IER 11111111 P5M2 7 P5M2 6 P5M2 5 P5M2 4 P5M2 3 P5M2 2 P5M2 1 P5M2 0 ool 0000 0000 00 00000000 00 00000000 XX XXXX XXXX 1 used to access these extended SFRs 2 BRGR1_1 and BRGRO_1 must only be written if BRGEN_1 in BRGCON_1 SFR is logic 0 If any are written while BRGEN_1 1 the result is unpredictable Extended SFRs are physically located on chip but logically located in external data memory address space XDATA The MOVX A DPTR and MOVX DPTR A instructions are Jenuew Joer 7S6 2S60d 168d ZVLOLINN SIOJONPUODIWIS dXN NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 1 4 Memor
149. nous serial transfer occurs and RI_n will be set again at the end of the transfer When RI_n is cleared the reception of the next character will begin Refer to Figure 22 E eeler ale ele sde sde sde 16 s1 sde eeler aler ale 16 s1 ad write to SBUF shift l l l l l l transmit RXD data out mpieb doch LILILITITITITILT TI WRITE to SCON j clear RI RI l RXD pe ge DIS p j p IL DL data in TXD shift clock LI LI LILILILILI UI receive 002aaa925 Fig 22 Serial Port Mode 0 double buffering must be disabled 10 11 More about UART Mode 1 Reception is initiated by detecting a 1 to 0 transition on RXDn RXDn is sampled at a rate 16 times the programmed baud rate When a transition is detected the divide by 16 counter is immediately reset Each bit time is thus divided into 16 counter states At the 7th 8th and 9th counter states the bit detector samples the value of RXDn The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection H the value accepted during the first bit time is not 0 the receive circuits are reset and the receiver goes back to looking for another 1 to 0 transition This provides rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SnBUF and RB8_n and to set RI_n will
150. nt the MCU will perform a reset Flash write enable This device has hardware write enable protection This protection applies to both ISP and IAP modes and applies to both the user code memory space and the user configuration bytes UCFG1 BOOTVEC and BOOTSTAT This protection does not apply to ICP or parallel programmer modes If the Activate Write Enable AWE bit in BOOTSTAT 7 is a logic 0 an internal Write Enable WE flag is forced set and writes to the flash memory and configuration bytes are enabled If the Active Write Enable AWE bit is a logic 1 then the state of the internal WE flag can be controlled by the user NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 117 of 134 NXP Semiconductors UM1 01 47 UM10147_2 17 15 17 16 P89LPC952 954 User manual The WE flag is SET by writing the Set Write Enable 08H command to FMCON followed by a key value 96H to FMDATA FMCON 0x08 FMDATA 0x96 The WE flag is CLEARED by writing the Clear Write Enable OBH command to FACON followed by a key value 96H to FMDATA or by a reset FMCON 0x0B FMDATA 0x96 The ISP function in this device sets the WE flag prior to calling the IAP routines The IAP function in this device executes a Clear Write Enable command following any write operation If the Write Enable function is active user code which calls IAP routines will need to set the Write Enable flag prior to each IAP write f
151. nter timers which are upward compatible with the 80C51 Timer 0 and Timer 1 Both can be configured to operate either as timers or event counters see Table 36 An option to automatically toggle the Tx pin upon timer overflow has been added In the Timer function the timer is incremented every PCLK In the Counter function the register is incremented in response to a 1 to 0 transition on its corresponding external input pin TO or T1 The external input is sampled once during every machine cycle When the pin is high during one cycle and low in the next cycle the count is incremented The new count value appears in the register during the cycle following the one in which the transition was detected Since it takes two machine cycles four CPU clocks to recognize a 1 to 0 transition the maximum count rate is 1 4 of the CPU clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle The Timer or Counter function is selected by control bits TnC T x 0 and 1 for Timers 0 and 1 respectively in the Special Function Register TMOD Timer 0 and Timer 1 have five operating modes modes 0 1 2 3 and 6 which are selected by bit pairs TnM1 TnMO in TMOD and TnM2 in TAMOD Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different The operating
152. nto ISP mode This occurs if UARTO is enabled and the the EBRR bit AUXR1 6 is set and a break occurs Double buffering The UARs have a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters provided the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD_n i e SNSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out Double buffering in different modes Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD_n 0 Transmit interrupts with double buffering enabled Modes 1 2 and 3 Unlike the conventional UART when double buffering is enabled the Tx interrupt is generated when the double buffer is ready to receive new data The following occurs during a transmission assuming eight data bits 1 The double buffer is empty initially 2 The CPU writes to SnBUF 3 The SnBUF data is loaded to the shift register and a Tx interrupt is generated immediately 4 If there is more data go to 6 else continue 5 If there is no more data then lf DBISEL_n is logic 0 no more in
153. nverted After all selected channels have been converted the process will repeat starting with the first selected channel Additional conversion results will again cycle through the eight result register pairs overwriting the previous results Continuous conversions continue until terminated by the user The channels are converted from LSB to MSB order in ADINS This mode is selected by setting the BURSTO bit in the ADMODA register Dual channel continuous conversion mode This is a variation of the auto scan continuous conversion mode where conversion occurs on two user selectable inputs Any combination of two of the eight input channels can be selected for conversion The result of the conversion of the first channel is placed in the result register pair ADODATOR and ADODATOL The result of the conversion of the NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 28 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual second channel is placed in result register pair ADODAT1R and ADODAT1L The first channel is again converted and its result stored in ADODAT2R and ADODAT2L The second channel is again converted and its result placed in ADODAT3R and ADODATS3L etc see Table 9 An interrupt is generated if enabled after every set of four or eight conversions user selectable This mode is selected by setting the SCCO bit in the ADMODA register Table 9 Result registers and conversio
154. ocessor vectors to the interrupt routine or by software except in mode 6 where it is cleared in hardware TR1 Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on off TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the interrupt is processed or by software except in mode 6 see above when it is cleared in hardware e C T 0 overflow PCLK TAB on Ten Ten TFn interrupt n pin Q CG i control 5 bits 8 bits toggle TRn Gate INTn pin ENTn 002aaa919 Fig 15 Timer counter 0 or 1 in Mode 0 13 bit counter C T 0 overflow FS TL TH eet on d TFn interrupt n pin Q CG control 8 bits 8 bits toggle TRn or C Tn pin Gate INTn pin ENTn 002aaa920 Fig 16 Timer counter 0 or 1 in mode 1 16 bit counter UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 51 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual PCLK ______ overflow mc n TFn interrupt npin C C T 1 Control toggle TRn Gate INTn pin ENTn 002aaa921 Fig 17 Timer counter 0 or 1 in Mode 2 8 bit auto reload PCLK ETER m overflow SCH x oo TFO interrupt Opin D C T 1 control
155. od of the TFn is always 256 THn e Loading THn with 00h will force the Tx pin high loading THn with FFh will force the Tx pin low Note that interrupt can still be enabled on the low to high transition of TFn and that TFn can still be cleared in software like in any other modes NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 50 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 39 Timer Counter Control register TCON address 88h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TF1 TR1 TFO TRO IE1 IT1 IEO ITO Reset 0 0 0 0 0 0 0 0 Table 40 Timer Counter Control register TCON address 88h bit description Bit Symbol Description 0 ITO Interrupt O Type control bit Set cleared by software to specify falling edge low level triggered external interrupts 1 IEO Interrupt 0 Edge flag Set by hardware when external interrupt 0 edge is detected Cleared by hardware when the interrupt is processed or by software 2 IT1 Interrupt 1 Type control bit Set cleared by software to specify falling edge low level triggered external interrupts 3 IE1 Interrupt 1 Edge flag Set by hardware when external interrupt 1 edge is detected Cleared by hardware when the interrupt is processed or by software TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off 5 TFO Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the pr
156. ogic 1 When data is transmitted the 9th data bit TB8 in SnCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 56 of 134 NXP Semiconductors UM1 01 47 UM10147_2 10 4 10 5 10 6 P89LPC952 954 User manual the 9th data bit goes into RB8_n in Special Function Register SnCON and the stop bit is not saved The baud rate is programmable to either Lie or Los of the CCLK frequency as determined by the SMOD1 bit in PCON The SMOD1 bit is used by both UARTs Mode 3 11 bits are transmitted through TXDn or received through RXDn a start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection on page 57 In all four modes transmission is initiated by any instruction that uses SnBUF as a destination register Reception is initiated in Mode 0 by the condition RI_n 0 and REN_n 1 Reception is initiated in the other modes by the incoming start bit if REN_n 1 SFR space The UART SFRs are at the following locations Table 44 UART SFR addresses Register Description SFR location PCON Pow
157. on 0 0 0 12C bus will be released not SLA R W or data or addressed slave will be bytes entered No l2DAT action 1 0 0 A START condition will be transmitted when the bus becomes free Table 73 Master Receiver mode Status code Status of the C Application software response Next action taken by I C hardware I2STAT hardware to from I2DAT to I2CON STA STO SI STA 08H A START Load SLA R x 0 0 x SLA R will be transmitted ACK bit condition has will be received been transmitted 10H A repeat START Load SLA R or x 0 0 x As above condition has Load SLA W SLA W will be transmitted 2C bus been transmitted will be switched to Master Transmitter Mode 38H Arbitration lostin no I2DAT action 0 0 0 x 12C bus will be released it will enter NOT ACK bit or a slave mode no I2DAT action 1 0 0 D A START condition will be transmitted when the bus becomes free 40h SLA R has been nol2DAT action 0 0 0 0 Data byte will be received NOT ACK transmitted ACK or bit will be returned has been received vo I2DAT action 0 0 0 1 Data byte will be received ACK bit or will be returned 48h SLA R has been No I2DAT action 1 0 0 x Repeated START will be transmitted transmitted NOT or ACK has been no I2DAT action 0 1 0 x STOP condition will be transmitted received or STO flag will be reset no I2DAT action 1 1 0 D STOP condition followed by a START or condition will be transmitted STO flag will be reset UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02
158. on Flag Protection NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 83 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual CPU clock DIVIDER BY 4 16 64 128 8 BIT SHIFT REGISTER READ DATA BUFFER CLOCK LOGIC ry A A SPI CONTROL SPI STATUS REGISTER Fig 33 SPI block diagram MSTR MISO P2 3 MOSI P2 2 SPICLK P2 5 SS P2 4 DEI e EIERE O M a alasa Q 2 0 0 n n SPI CONTROL REGISTER SPI internal interrupt data request bus 002aaa900 UM10147_2 The SPI interface has four pins SPICLK MOSI MISO and SS e SPICLK MOSI and MISO are typically tied together between two or more SPI devices Data flows from master to slave on the MOSI Master Out Slave In pin and flows from slave to master on the MISO Master In Slave Out pin The SPICLK signal is output in the master mode and is input in the slave mode If the SPI system is disabled i e SPEN SPCTL 6 0 reset value these pins are configured for port functions e SSis the optional slave select pin In a typical configuration an SPI master asserts one of its port pins to select one SPI device as the current slave An SPI slave device uses its SS pin to determine whether it is selected The SS is ignored if any of the following conditions are true Ifthe SPI system is
159. one flag bit may be set e During a power on reset both POF and BOF are set but the other flag bits are cleared e For any other reset previously set flag bits that have not been cleared will remain set RPE UCFG1 6 RST pin WDTE UCFG1 7 Watchdog timer reset el y Software reset SRST AUXR1 3 _ gt chip reset Power on detet W __ UART break detect EBAR AUXR1 6 _ _ Brownout detect reset BOPD PCON 5 Fig 14 Block diagram of reset 002aaa918 Table 33 Reset Sources register RSTSRC address DFh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOF POF R_BK R_WD R_SF R_EX Resetl x D 1 1 0 0 0 0 1 The value shown is for a power on reset Other reset sources will set their corresponding bits Table 34 Reset Sources register RSTSRC address DFh bit description Bit Symbol Description 0 HEN external reset Flag When this bit is logic 1 it indicates external pin reset Cleared by software by writing a logic 0 to the bit or a Power on reset If RST is still asserted after the Power on reset is over R_EX will be set 1 R_SF software reset Flag Cleared by software by writing a logic 0 to the bit or a Power on reset 2 RWD Watchdog Timer reset flag Cleared by software by writing a logic 0 to the bit or a Power on reset NOTE UCFG1 7 must be 1 3 R_BK break detect reset If a break detect occurs and EBRR AUXR1 6 is set to logic 1 a sy
160. or status 119 Table 104 IAP function calls 120 Table 105 Flash User Configuration Byte 1 UCFG1 bit allocation 0000000 eee eaee 122 Table 106 Flash User Configuration Byte 1 UCFG1 bit description 122 Table 107 Oscillator type selection 123 Table 108 Flash User Configuration Byte 2 UCFG2 bit allocation 000200c cee eae 123 Table 109 Flash User Configuration Byte 2 UCFG2 bit description 123 Table 110 Sector Security Bytes SECx bit allocation 124 Table 111 Sector Security Bytes SECx bit description 124 Table 112 Effects of Security Bis 124 Table 113 Boot Vector BOOTVEC bit allocation 124 Table 114 Boot Vector BOOTVEC bit description 124 Table 115 Boot Status BOOTSTAT bit allocation 125 Table 116 Boot Status BOOTSTAT bit description 125 Table 117 Instruction set summary 126 104 Table 96 FREEZE register address FFDOh bit allocation 106 Table 97 FREEZE register address FFDOh bit description 106 Table 98 Debugger interface connections 106 Table 99 Flash Memory Control register FMCON address E4h bit allocation 109 Table 100 Flash Memory Control register FMCON address E4h bit description 109 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 131 of 134 NXP Semiconductors UM10147 21 Figures P89LPC952 954 User manual
161. own below is an example of initializing one comparator Comparator 1 is configured to use the CIN1A and CMPREF inputs outputs the comparator result to the CMP1 pin and generates an interrupt when the comparator output changes CMPINIT MOV PTOAD 030h ANL POM2 0CFh ORL POM1 030h MOV CMP1 024h pin CALL delayldus before use ANL CMP1 0FEh SETB EC SETB EA RET 1 Disable digital INPUTS on CI 1A CMPREF Disable digital OUTPUTS on pins that are used for analog functions CIN1A CMPREF Turn on comparator 1 and set up for Positive input on CINIA Negative input from CMPREF Output to CMP1 pin The comparator needs at least 10 enabled icroseconds Clear comparator 1 interrupt flag Enable the comparator interrupt Enable the interrupt system if needed Return to caller The interrupt routine used for the comparator must clear the interrupt flag CMF1 in this case before returning NXP B V 2008 All rights reserved Rev 02 28 April 2008 96 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 14 Keypad interrupt KBI The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks There are three SFRs used for this f
162. please visit http Avww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 28 April 2008 Document identifier UM10147_2
163. quired field but value is a don t care ss subfunction code dd data cc checksum Subfunction codes 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 0C Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 10 Clear Configuration Protection 18 Security Byte 8 89LPC954 19 Security Byte 9 89LPC954 1A Security Byte 10 89LPC954 1B Security Byte 11 89LPC954 1C Security Byte 12 89LPC954 1D Security Byte 13 89LPC954 1E Security Byte 14 89LPC954 1F Security Byte 15 89LPC954 Example 020000020347cc NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 115 of 134 NXP Semiconductors UM10147 UM10147_2 P89LPC952 954 User manual Table 102 In system Programming ISP hex record formats continued Record type 03 04 05 Command data function Miscellaneous Read Functions 01xxxx03sscc Where xxxx required field but value is a don t care ss subfunction code cc checksum Subfunction codes 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 0C Security Byte A OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 10
164. r ITO in Register TCON If ITn 0 external interrupt n is triggered by a low level detected at the INTn pin If Tn 1 external interrupt n is edge triggered In this mode if consecutive samples of the INTn pin show a high level in one cycle and a low level in the next cycle interrupt request flag IEn in TCON is set causing an interrupt request Since the external interrupt pins are sampled once each machine cycle an input high or low level should be held for at least one machine cycle to ensure proper sampling If the external interrupt is edge triggered the external source has to hold the request pin high for at least one machine cycle and then hold it low for at least one machine cycle This is to ensure that the transition is detected and that interrupt request flag IEn is set IEn is automatically cleared by the CPU when the service routine is called NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 34 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual If the external interrupt is level triggered the external source must hold the request active until the requested interrupt is generated If the external interrupt is still asserted when the interrupt service routine is completed another interrupt will be generated It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive it simply tracks the input pin level If an external interrupt has been prog
165. r mode the contents of this register has no effect NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 70 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 11 3 I2C control register The CPU can read and write this register There are two bits are affected by hardware the SI bit and the STO bit The SI bit is set by hardware and the STO bit is cleared by hardware CRSEL determines the SCL source when the C bus is in master mode In slave mode this bit is ignored and the bus will automatically synchronize with any clock frequency up to 400 kHz from the master 12C device When CRSEL 1 the 12C interface uses the Timer 1 overflow rate divided by 2 for the 12C clock rate Timer 1 should be programmed by the user in 8 bit auto reload mode Mode 2 Data rate of I C bus Timer overflow rate 2 PCLK 2 256 reload value If fose 12 MHz reload value is 0 to 255 so DC data rate range is 11 72 Kbit sec to 3000 Kbit sec When CRSEL 0 the 12C interface uses the internal clock generator based on the value of I2SCLL and I2CSCLH register The duty cycle does not need to be 50 The STA bit is START flag Setting this bit causes the 12C interface to enter master mode and attempt transmitting a START condition or transmitting a repeated START condition when it is already in master mode The STO bit is STOP flag Setting this bit causes the 12C interface to transmit a STOP con
166. rammed as level triggered and is enabled when the P89LPC952 954 is put into Power down mode or Idle mode the interrupt occurrence will cause the processor to wake up and resume operation Refer to Section 6 3 Power reduction modes for details 4 2 External Interrupt pin glitch suppression Most of the P89LPC952 954 pins have glitch suppression circuits to reject short glitches please refer to the P89LPC952 954 data sheet Dynamic characteristics for glitch filter specifications However pins SDA INTO P1 3 and SCL T0 P1 2 do not have the glitch suppression circuits Therefore INT1 has glitch suppression while INTO does not Table 22 Summary of interrupts Description Interrupt flag Vector Interrupt enable Interrupt Arbitration Power bit s address bit s priority ranking down wake up External interrupt 0 IEO 0003h EX0 IENO 0 IPOH O0 IP0 0 1 highest Yes Timer 0 interrupt TFO 000Bh ETO IENO 1 IPOH 1 1P0 1 4 No External interrupt 1 IEI 0013h EX1 IENO 2 IPOH 2 IP0 2 7 Yes Timer 1 interrupt TF1 001Bh ET1 IENO 3 IPOH 3 IPO 3 10 No Serial port 0 Tx and Rx TlOandRI_O 0023h ES ESR IENO 4 IPOH 4 IP0 4 13 No Serial port 0 Rx RI_O Brownout detect BOF 002Bh EBO IENO 5 IPOH 5 IP0 5 2 Yes Watchdog timer Real time WDOVF RTCF 0053h EWDRT IENO 6 IPOH 6 1IP0 6 3 Yes clock 12C interrupt Sl 0033h El2C IEN1 0 IPOH 0 IP0 0 5 No KBI interrupt KBIF 003Bh EKBI IEN1 1 IPOH 0 IP0 0 8 Yes Comparators 1
167. register selects one of the two Data Pointers The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled Specific instructions affected by the Data Pointer selection are INC DPTR Increments the Data Pointer by 1 JMP A DPTR Jump indirect relative to DPTR value MOV DPTR data16 Load the Data Pointer with a 16 bit constant MOVC A A DPTR Move code byte relative to DPTR to the accumulator MOVX A DPTR Move accumulator to data memory relative to DPTR MOVX DPTR A Move from data memory relative to DPTR to the accumulator Also any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC952 954 since the part does not have an external data bus However they may be used to access Flash configuration information see Flash Configuration section or auxiliary data CDATA memory Bit 2 of AUXR1 is permanently wired as a logic 0 This is so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register 16 3 Debugger interface This device contains a two wire serial debugger interface designed to be used with commerically available debugging tools An additional trigger output is provided that maybe tri
168. res a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit O will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 Table 61 Slave 0 1 2 examples Example 1 Example 2 Example 3 SlaveO0 SnADDR 11000000 Slave1 SnADDR 11100000 Slave 2 SnADDR 11000000 SnADEN 1111 1001 SnADEN 1111 1010 SnADEN 1111 1100 Given 1100 0XX0 Given 1110 0X0X Given 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 68 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual SnADDR and SnADEN Zeros in this result are treated as don t cares In most cases interpreting the don t cares as ones the broadcast addre
169. rily override the selection defined by RPE and RPE1 bits Other sources of reset will not override the RPE and RPE1 bits Note During a power cycle Vpp must fall below Vpor see P89LPC952 954 data sheet Static characteristics before power is reapplied in order to ensure a power on reset Note When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage Reset can be triggered from the following sources e External reset pin during power up or if user configured via UCFG1 UCGF2 e Power on detect e Brownout detect e Watchdog timer e Software reset e UART break character detect reset NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 46 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a 0 to the corresponding bit More than
170. ritten when buffer is empty the location of the transmit interrupt is determined by INTLO_1 When the first character is written the transmit interrupt is generated immediately after S1BUF is written 5 CIDIS_1 Combined Interrupt Disable 1 When set 1 Rx and Tx interrupts are separate When cleared 0 the UART 1 uses a combined Tx Rx interrupt like a conventional 80C51 UART This bit is reset to logic 0 to select combined interrupts 6 INTLO_ Transmit interrupt position 1 When cleared 0 the Tx interrupt is issued at the 1 beginning of the stop bit When set 1 the Tx interrupt is issued at end of the stop bit Must be logic 0 for mode 0 Note that in the case of single buffering if the Tx interrupt occurs at the end of a STOP bit a gap may exist before the next start bit 7 DBMOD Double buffering mode 1 When set 1 enables double buffering Must be logic 0 1 for UART mode 0 In order to be compatible with existing 80C51 devices this bit is reset to logic 0 to disable double buffering More about UART Mode 0 In Mode 0 a write to SnBUF will initiate a transmission At the end of the transmission TI_n SnCON 1 is set which must be cleared in software Double buffering must be disabled in this mode NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 62 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Reception is initiated by clearing DU np SnCON 0 Synchro
171. rogramming ISP The ISP feature allows for a wide range of baud rates to be used in your application independent of the oscillator frequency It is also adaptable to a wide range of oscillator frequencies This is accomplished by measuring the bit time of a single bit in a received character This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency The ISP feature requires that an initial character an uppercase U be sent to the P89LPC952 954 to establish the baud rate The ISP firmware provides auto echo of received characters Once baud rate initialization has been performed the ISP firmware will only accept Intel Hex type records Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below NNAAAARRDD DDCC lt crif gt NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 113 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual In the Intel Hex record the NN represents the number of data bytes in the record The P89LPC952 954 will accept up to 64 40H data bytes The AAAA string represents the address of the first byte in the record If there are zero bytes in the record this field is often set to 0000 The RR string indicates the record type A record type of 00 is a data record A record type of 01 indicates the end of file mark In this applica
172. s 2 4 V to 3 6 V However BOF RSTSRC 5 will be set when Vpp falls to the Brownout Detection trip point BOF can be cleared by writing a logic 0 to the bit 1 Cannot be used with operation above 12 MHz as this requires Vpp of 3 0 V or above 6 2 Power on detection The Power On Detect has a function similar to the Brownout Detect but is designed to work as power initially comes up before the power supply voltage reaches a level where the Brownout Detect can function The POF flag RSTSRC 4 is set to indicate an initial power on condition The POF flag will remain set until cleared by software by writing a logic 0 to the bit Note that if BOE UCFG1 5 is programmed BOF RSTSRC 5 will be set when POF is set If BOE is unprogrammed BOF is meaningless 6 3 Power reduction modes The P89LPC952 954 supports three different power reduction modes as determined by SFR bits PCON 1 0 see Table 27 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 43 of 134 NXP Semiconductors UM1 01 47 Table 27 P89LPC952 954 User manual Power reduction modes PMOD1 PCON 1 0 0 PMODO PCON 0 0 1 Description Normal mode default no power reduction Idle mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode Power down mode T
173. s been received The break detect of VARTO can be used to reset the device and force the device into ISP mode by setting the EBRR bit AUXR1 6 The break detect of UART1 cannot reset the device but can be used to generate an interrupt Table 50 Serial Port 0 Control register SOCON address 98h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMO_0 F SM1_0 SM2_0 HEN Oo TB8_0 RB8_0 TLO HI 0 E 0 Reset x X D D xX xX 0 0 Table 51 Serial Port 0 Control register SOCON address 98h bit description Bit Symbol Description 0 RI_O Receive interrupt flag 0 Set by hardware at the end of the 8th bit time in Mode 0 or approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO it is set near the middle of the 9th data bit bit 8 If SMODO 1 itis set near the middle of the stop bit see SM2_0 SOCON 5 for exceptions Must be cleared by software 1 TI_O Transmit interrupt flag 0 Set by hardware at the end of the 8th bit time in Mode 0 or at the stop bit see description of INTLO_0 bit in SOSTAT register in the other modes Must be cleared by software 2 RB8_0 The 9th data bit that was received in Modes 2 and 3 In Mode 1 SM2 must be 0 RB8_0 is the stop bit that was received In Mode 0 RB_0O is undefined 3 TB8_0 The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired 4 HEN Oo Enables serial reception Set by software to enable reception Clear by softwar
174. s deselected and then an additional two new clock cycles before the new clock source is selected Since the prescaler starts counting immediately after a feed switching clocks can cause some inaccuracy in the prescaler count The inaccuracy could be as much as 2 old clock source counts plus 2 new clock cycles Note When switching clocks it is important that the old clock source is left enabled for two clock cycles after the feed completes Otherwise the watchdog may become disabled when the old clock source is disabled For example suppose PCLK WCLK 0 is the current clock source After WCLK is set to logic 1 the program should wait at least two PCLK cycles 4 CCLKs after the feed completes before going into Power down mode Otherwise the watchdog could become disabled when CCLK turns off The watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 102 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual MOV WFEED1 0A5H A MOV WFEED2 05AH watchdog oscillator Sen e PRESCALER Lo 8 BIT DOWN reset 1 PCLK 1 a PRESCALER ss COUNTER A A A LU T I SHADOW REGISTER A A A AAA pace eaer eeo J _ worun woror fwo 002aaa905 WDCON A7H Fig 44 Watchdog Timer in Watchdog Mode WDTE 1 15 4 Watchdog Ti
175. sequence any new values written to NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 99 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual these two SFRs will not take effect To avoid a watchdog reset the watchdog timer needs to be fed via a special sequence of software action called the feed sequence prior to reaching an underflow To feed the watchdog two write instructions must be sequentially executed successfully Between the two write instructions SFR reads are allowed but writes are not allowed The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register An incorrect feed sequence will cause an immediate watchdog reset The program sequence to feed the watchdog timer is as follows CLR EA disable interrupt MOV WFEED1 0A5h do watchdog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt This sequence assumes that the P89LPC952 954 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence If an interrupt was allowed to be serviced and the service routine contained any SFR writes it would trigger a watchdog reset If it is known that no interrupt could occur during the feed sequence the instructions to disable and re enable interrupts may be removed In watchdog mode WDTE 1 writing the WDCON register must be IMMEDIATELY followed by a feed
176. ss DFh Table 64 IC slave address register IZADR address DBh bitallocation ed NEE Gan duede ee 47 bit description 70 Table 34 Reset Sources register RSTSRC address DFh Table 65 12C Control register I2CON address D8h bit bit description 47 allocation vac uge Seek wee E 71 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 130 of 134 NXP Semiconductors UM10147 Table 66 12C Control register I2CON address D8h bit description ccie Hd Ee Eer ed dae te 71 Table 67 DC Status register I2STAT address D9h bit allocation ee erie ea EE ex 72 Table 68 DC Status register I2STAT address D9h bit descripti ON ci eas eiaa degen hha ade 72 Table 69 12C clock rates selection 73 Table 70 12C Control register I2CON address D8h 73 Table 71 12C Control register I2CON address D8h 75 Table 72 Master Transmitter mode 78 Table 73 Master Receiver mode 79 Table 74 Slave Receiver mode 80 Table 75 Slave Transmitter mode 82 Table 76 SPI Control register SPCTL address E2h bit allocation EE 84 Table 77 SPI Control register SPCTL address E2h bit CESCIIPION 2 A Hp ENER asa e bases 85 Table 78 SPI Status register SPSTAT address E1h bit allocation d ode ENEE dE e eee ey ee 85 Table 79 SPI Status register SPSTAT address E1h bit description 85 Table 80 SPI Data
177. ss will be FF hexadecimal Upon reset SnADDR and SnADEN are loaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature 11 12C interface The C bus uses two wires serial clock SCL and serial data SDA to transfer information between devices connected to the bus and has the following features Bidirectional data transfer between masters and slaves Multimaster bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The 2C bus may be used for test and diagnostic purposes A typical I2C bus configuration is shown in Figure 26 Depending on the state of the direction bit R W two types of data transfers are possible on the I C bus Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the sla
178. stem reset will occur This bit is set to indicate that the system reset is caused by a break detect Cleared by software by writing a logic 0 to the bit or on a Power on reset 4 POF Power on Detect Flag When Power on Detect is activated the POF flag is set to indicate an initial power up condition The POF flag will remain set until cleared by software by writing a logic 0 to the bit Note Ona Power on reset both BOF and this bit will be set while the other flag bits are cleared 5 BOF Brownout Detect Flag When Brownout Detect is activated this bit is set It will remain set until cleared by software by writing a logic 0 to the bit Note On a Power on reset both POF and this bit will be set while the other flag bits are cleared 6 7 reserved UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 47 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 7 1 Reset vector Following reset the P89LPC952 954 will fetch instructions from either address 0000h or the Boot address The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address 00h The Boot address will be used if a UART break reset occurs or the non volatile Boot Status bit BOOTSTAT 0 1 or the device has been forced into ISP mode Otherwise instructions will be fetched from address 0000H 8 Timers 0 and 1 The P89LPC952 954 has two general purpose cou
179. ster INC RO point to next byte DIN R3 LOAD_PAGE do until count is zero DV FMCON EP else erase amp program the page MOV R7 FMCON copy status for return MOV A Ri read status ANL A 0FH save only four lower bits INZ BAD CLR Cc clear error flag if good UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 110 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual RET and return BAD SETB C eet error flag RET and return A C language routine to load the page register and perform an erase program operation is shown below include lt REG952 H gt unsigned char idata dbytes 64 data buffer unsigned char Dm stat status result bit PGM_USER unsigned char unsigned char bit prog_fail void main prog_fail PGM_USER 0x1F 0xC0 bit PGM_USER unsigned char page bi unsigned char page_lo define LOAD0x00 clear page register enable loading define EP0x68 erase amp program page unsigned char i loop count FMCON LOAD load command clears page reg FMADRH page_hi FMADRL page_lo write my page address to addr regs for 1 0 1 lt 64 i i 1 FMDATA dbytes il FMCON EP erase amp prog page command Fm_stat FMCON read the result status if Fm_stat amp Ox0F 0 prog_fail 1 else prog_fail 0 return prog_fail 17 5 In circuit programming ICP In Circuit Programming is a method intended to allow co
180. t 0 Status register SOSTAT address Table 22 Summary of interrupts 35 BAh bit allocation 61 Table 23 Number of I O pins available 36 Table 56 Serial Port 0 Status register SOSTAT address Table 24 Port output configuration settings 37 BAh bit description 61 Table 25 Port output configuration 41 Table 57 Serial Port 1 Status register S1STAT address Table 26 Brownout option 43 D4h bit allocation 62 Table 27 Power reduction modes 44 Table 58 Serial Port 1 Status register S1STAT address Table 28 Power Control register PCON address 87h bit D4h bit description 62 alloCatlON ee eroice nate ee E EE ed EEN 45 Table 59 FE_n and RI_n when SM2_n 1 in Modes 2 and Table 29 Power Control register PCON address 87h bit ER 65 CESCIIPUON ZA one ae ees eae ia Er 45 Table 60 Slave 0 1 examples o nannnnu nunnana 68 Table 30 Power Control register A PCONA address B5h Table 61 Slave 0 1 2 examples 68 bit allocation 0 2 0 cee eee eee 45 Table 62 DC data register I2DAT address DAh bit Table 31 Power Control register A PCONA address B5h AMO CANON eenn sea x ache Me de ESAE 70 bit description 45 Table 63 DC slave address register I2ADR address DBh Table 32 Reset pin modes 2 005 46 bit allocation 70 Table 33 Reset Sources register RSTSRC addre
181. ter mode In this mode data is transmitted from master to slave Before the Master Transmitter mode can be entered I2CON must be initialized as follows Table 70 BC Control register I2CON address D8h Bit 7 6 5 4 3 2 1 0 I2EN STA STO SI AA CRSEL value 1 0 0 0 x bit rate CRSEL defines the bit rate I2EN must be set to 1 to enable the 12C function If the AA bit is 0 it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave mode STA STO and SI bits must be cleared to 0 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 73 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this case the data direction bit R W will be logic 0 indicating a write Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer The 2C bus will enter Master Transmitter Mode by setting the STA bit The 12C logic will send the START condition as soon as the bus is free After the START condition is transmitted the SI bit is set and the status code in I2STAT should be O8h This status code must be used to vector to an interrupt service rout
182. terrupts will occur NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 65 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual If DBISEL_n is logic 1 and INTLO_n is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL_nis logic 1 and INTLO_nis logic 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data Note that if DBISEL_n is logic 1 and the CPU is writing to SnBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following 6 If there is more data the CPU writes to SBUF again Then If INTLO_n is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO_n is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter Goto3 write to i i j SBUF 1 TX interrupt f f f single buffering DBMOD SSTAT 7 0 early interrupt INTLO SSTAT 6 0 is shown ee fi i 1 TX interrupt i f f f double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown no ending TX interrupt DBISEL SSTAT
183. the clock to the Watchdog timer will be frozen while performing monitor operations in debugger mode 3 Not used 4 RTC_F Realtime Clock Freeze bit When set the clock to the RTC will be frozen while performing monitor operations in debugger mode 5 7 Not used 16 3 1 Debugger connections The physical connection to the debugger requires the use of a 10 pin dual row male header on 0 100 inch centers as shown in Figure 46 9 O O O O o D 10 O O O O O E 002aac320 Fig 46 Debugger connections top view Table 98 Debugger interface connections Pin Signal UO Description 1 Von O Used by debugger to determine target s power on state draws minimal current 2 TRIG l Trigger output from the debugger active high 3 5 7 9 Vss l 0 V reference 4 TDI UO Serial data signal 6 RST UO Driven low by debugger to reset target system Sampled by debugger to detect target reset events 8 TCLK l Serial clock signal from the debugger 10 DBINST O Debugger installed signal Driven high by the debugger when debugger is active 1 UO direction is with respect to the P89LPC952 954 target system UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 106 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 17 Flash memory UM10147_2 17 1 General description The P89LPC952 954 Flash memory provides in circuit electrical erasure and programming T
184. the output frequency of the internal RC oscillator UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 122 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Table 106 Flash User Configuration Byte 1 UCFG1 bit description continued Bit Symbol Description WDSE Watchdog Safety Enable bit Refer to Table 90 Watchdog timer configuration for details BOE Brownout Detect Enable see Section 6 1 Brownout detection 6 RPE Reset pin enable In combination with RPE1 UCFG2 0 determines the mode of the reset pin see Section 7 Reset on page 46 NOTE During a power up sequence the RPE and RPE1 selection is overridden and this pin will always functions as a reset input After power up the pin will function as defined by the RPE and RPE1 bits Only a power up reset will temporarily override the selection defined by RPE and RPE1 bits Other sources of reset will not override the RPE and RPE1 bits The following reset pin modes are selected by and RPE1 UCFG2 00 and RPE UCFG1 6 bits 00 Normal input pin 01 Reset input pin 10 Bidirectional open drain reset 11 Reset output only 7 WDTE Watchdog timer reset enable When set 1 enables the watchdog timer reset When cleared 0 disables the watchdog timer reset The timer may still be used to generate an interrupt Refer to Table 90 Watchdog timer configuration for details Table 1
185. this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2_n 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2_n bit and prepare to receive the data bytes that follow The slaves that weren t being addressed leave their SM2_n bits set and go on about their business ignoring the subsequent data bytes NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 67 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Note that SM2_n has no effect in Mode 0 and must be logic 0 in Mode 1 10 20 Automatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2_n bit in SnCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag DI
186. time clock 54 UARTS ert ge saree hee eid ee Peas 56 Mode 0 a gk ches edie eee A vk 56 Mode 22 heir ice gar renati EE nin 56 Kloe ciiin n a E ae E Eer ger ae aa is 56 Mode 3 cecrriieis ved iiaia riai eae 57 SER tee sen iaeia aiak ST i 57 Baud Rate generator and selection 57 Updating the BRGR1 and BRGRO SFRs 58 Framing emor eee eeee 59 Break detect eee eee 59 More about UART Mode O 62 More about UART Mode 1 63 More about UART Modes 2and3 64 Framing error and RI_n in Modes 2 and 3 with SM2 MS ereere Bregen pad alee 64 Break detect eee eee 65 Double buffering o a uaaanuanana neua 65 Double buffering in different modes 65 Transmit interrupts with double buffering enabled Modes 1 2 and3 04 65 The 9th bit bit 8 in double buffering Modes 1 2 and EE 66 Multiprocessor communications 67 Automatic address recognition 68 EC Interface 69 GC data register n n nanan nunnana 70 IC slave address register 70 IC control register n nonna nanan 71 IC Status register 00 72 12C SCL duty cycle registers I2SCLH and I2SCLL 72 12C operation modes 05 73 Master Transmitter mode 73 Master Receiver mode 74 Slave Receiver mode 75 Slave Transmitter mode 76 Serial Peripheral Interface SPI 83 Configuring the SPI
187. tion Boot ROM When the microcontroller contains a a 256 byte Boot ROM that is separate from the user s Flash program memory This Boot ROM contains routines which handle all of the low level details needed to erase and program the user Flash memory A user program simply calls a common entry point in the Boot ROM with appropriate parameters to accomplish the desired operation Boot ROM operations include operations such as erase sector erase page program page CRC program security bit etc The Boot ROM occupies the program memory space at the top of the address space from FFOO to FFFFh thereby not conflicting with the user program memory space This function is in addition to the IAP Lite feature Power on reset code execution The P89LPC952 954 contains two special Flash elements the BOOT VECTOR and the Boot Status Bit Following reset the P89LPC952 954 examines the contents of the Boot Status Bit If the Boot Status Bit is set to zero power up execution starts at location 0000H which is the normal start address of the user s application code When the Boot Status Bit is set to a va one the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to OOH The factory default settings for this device is shown in Table 101 below The factory pre programmed boot loader can be erased by the user Users who wish to use this loader should take cautions to avoid erasing the last 1 kB sector o
188. tion additional record types will be added to indicate either commands or data for the ISP facility The maximum number of data bytes in a record is limited to 64 decimal ISP commands are summarized in Table 102 As a record is received by the P89LPC952 954 the information in the record is stored internally and a checksum calculation is performed The operation indicated by the record type is not performed until the entire record has been received Should an error occur in the checksum the P89LPC952 954 will send an X out the serial port indicating a checksum error If the checksum calculation is found to match the checksum in the record then the command will be executed In most cases successful reception of the record will be indicated by transmitting a character out the serial port NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 114 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual Table 102 In system Programming ISP hex record formats Record type Command data function 00 Program User Code Memory Page nnaaaa00dd ddcc Where nn number of bytes to program aaaa page address dd dd data bytes cc checksum Example 100000000102030405006070809cc 01 Read Version Id 00xxxx01cc Where xxxx required field but value is a don t care cc checksum Example 00000001cc 02 Miscellaneous Write Functions 02xxxx02ssddcc Where xxxx re
189. tion specified by the lower 6 bits of FMADRL In addition the update flag for that location will be set FMADRL will auto increment to the next location Auto increment after writing to the last byte in the page register will wrap around to the first byte in the page register but will not affect FMADRL 7 6 Bytes loaded into the page register do not have to be continuous Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writing to FMDATA However each location in the page register can only be written once following each LOAD command Attempts to write to a page register location more than once should be avoided FMADRH and FMADRL 7 6 are used to select a page of code memory for the erase program function When the erase program command is written to FMCON the locations within the code memory page that correspond to updated locations in the page register will have their contents erased and programmed with the contents of their corresponding locations in the page register Only the bytes that were loaded into the page register will be erased and programmed in the user code array Other bytes within the user code memory will not be affected Writing the erase program command 68H to FMCON will start the erase program process and place the CPU in a program idle state The CPU will remain in this idle state until the erase program cycle is either completed or terminated by an interrupt When the
190. tion to the power on flag POF RSTSRC 4 For correct activation of Brownout Detect certain Vpp rise and fall times must be observed Please see the data sheet for specifications NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 42 of 134 NXP Semiconductors UM10147 Table 26 Brownout options P89LPC952 954 User manual BOE PMOD1 UCFG1 5 PMODO PCON 1 0 0 erased XX X 1 program 11 total X med power down 11 any mode 1 brownout other than total detect power down power down 0 brownout detect active BOPD PCON 5 BOI PCON 4 X X X 0 brownout detect generates reset 1 brownout detect generates an interrupt EBO IENO 5 X X 1 enable brownout interrupt EA IENO 7 1 global interrupt enable Description Brownout disabled Vor operating range is 2 4 V to 3 6 V Brownout disabled Vpp operating range is 2 4 V to 3 6 V However BOPD is default to logic 0 upon power up Brownout reset enabled Von operating range is 2 7 V to 3 6 V Upon a brownout reset BOF RSTSRC 5 will be set to indicate the reset source BOF can be cleared by writing a logic 0 to the bit Brownout interrupt enabled Vpp operating range is 2 7 V to 3 6 V Upon a brownout interrupt BOF RSTSRC 5 will be set BOF can be cleared by writing a logic 0 to the bit Both brownout reset and interrupt disabled Vpp operating range i
191. to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 to 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir Ri Move indirect memory to direct byte 2 2 86 to 87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 to F7 MOV Ri dir Move direct byte to indirect memory 2 2 A6 to A7 MOV Ri data Move immediate to indirect memory 2 1 76 to 77 MOV DPTR data Move immediate to data pointer 3 2 90 MOVC A A DPTR Move code byte relative DPTR to A 1 2 93 MOVC A A PC Move code byte relative PC to A 1 2 94 MOVX A Ri Move external data A8 to A 1 2 E2 to E3 MOVX A DPTR Move external data A16 to A 1 2 EO MOVX Ri A Move A to external data A8 1 2 F2 to F3 MOVX DPTR A Move A to external data A16 1 2 FO PUSH dir Push direct byte onto stack 2 2 co POP dir Pop direct byte from stack 2 2 DO XCH A Rn Exchange A and register 1 1 C8 to CF XCH A dir Exchange A and direct byte 2 1 C5 XCH A Ri Exchange A and indirect memory 1 1 C6 to C7 UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 127 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual Table 117 Instruction set summary continued Mnemonic Description Bytes Cycles Hex code XCHD A Ri Exchange A and indirect memory nibble 1 1 D6 to D7 BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 C2 SETB
192. ty violation 0 1 D Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Sector erase and global erase are allowed 1 x x Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Global erase is allowed 17 19 Boot Vector register Table 113 Boot Vector BOOTVEC bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOOTV4 BOOTV3 BOOTV2 BOOTV1 BOOTVO Factory default 0 0 0 1 1 1 1 1 value Table 114 Boot Vector BOOTVEC bit description Bit Symbol Description 0 4 BOOTV 0 4 Boot vector If the Boot Vector is selected as the reset address the P89LPC952 954 will start execution at an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a reset 57 reserved UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 124 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual 17 20 Boot status register Table 115 Boot Status BOOTSTAT bit allocation Bit Symbol Factory default value 7 6 5 4 3 2 1 0 DCCP CWP AWP S BSB 0 0 0 0 0 0 0 1 Table 116 Boot Status BOOTSTAT bit description Bit Symbol 0 BSB 5 AWP 6 CWP 7 DCCP Description Boot Status Bit If programmed to logic 1 the P89LPC952 954 will always start execution at an address comprised of OOH in the lower e
193. unction The Keypad Interrupt Mask Register KBMASK is used to define which input pins connected to Port 0 are enabled to trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated if it has been enabled by setting the EKBI bit in IEN1 register and EA 1 The PATN_SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in the 87LPC76x series the user needs to set KBPATN OFFH and PATN_SEL 0 not equal then any key connected to Port which is enabled by KBMASK register is will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than 6 CCLKs Table 84 Keypad Pattern register KBPATN address 93h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol KBPATN 7 KBPATN 6 KBPATN 5 KBPATN 4 KBPATN 3 KBPATN 2 KBPATN 1 K
194. unction call Configuration byte protection In addition to the hardware write enable protection described above the configuration bytes may be separately write protected These configuration bytes include UCFG1 BOOTVEG and BOOTSTAT This protection applies to both ISP and IAP modes and does not apply to ICP or parallel programmer modes If the Configuration Write Protect bit CWP in BOOTSTAT 6 is a logic 1 writes to the configuration bytes are disabled If the Configuration Write Protect bit CWP is a logic 0 writes to the configuration bytes are enabled The CWP bit is set by programming the BOOTSTAT register This bit is cleared by using the Clear Configuration Protection CCP command in IAP or ISP The Clear Configuration Protection command can be disabled in ISP or IAP mode by programming the Disable Clear Configuration Protection bit DCCP in BOOTSTAT 7 toa logic 1 When DCOP is set the CCP command may still be used in ICP or parallel programming modes This bit is cleared by writing the Clear Configuration Protection CCP command in either ICP or parallel programming modes IAP error status It is not possible to use the Flash memory as the source of program instructions while programming or erasing this same Flash memory During an IAP erase program or CRC the CPU enters a program idle state The CPU will remain in this program idle state until the erase program or CRC cycle is completed These cycles are self timed
195. unction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification 19 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners 2C bus logo is a trademark of NXP B V NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 129 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual 20 Tables Table 1 Pin description 5 Table 35 Timer Counter Mode register TMOD address Table 2 Special function registers 12 89h bit allocation 48 Table 3 Extended special function registers 18 Table 36 Timer Counter Mode register TMOD address Table 4 Data RAM arrangement 20 89h bit description 48 Table 5 On chip RC oscillator trim register TRIM Table 37 Timer Counter Auxiliary Mode register TAMOD address
196. undary limits This bit is cleared in software by writing a 1 to this bit 5 BST05 When set indicates that conversion result for the ADO5 pin was inside outside the boundary limits This bit is cleared in software by writing a 1 to this bit 6 BST06 When set indicates that conversion result for the ADO6 pin was inside outside the boundary limits This bit is cleared in software by writing a 1 to this bit 7 BST07 When set indicates that conversion result for the ADO7 pin was inside outside the boundary limits This bit is cleared in software by writing a 1 to this bit 4 Interrupts The P89LPC952 954 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the P89LPC952 954 s 15 interrupt sources UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 33 of 134 NXP Semiconductors UM1 01 47 UM10147_2 4 1 P89LPC952 954 User manual Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global enable bit EA which enables all interrupts Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 and IP1H An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another
197. ut to a pin is enabled the pin should be configured in the push pull mode in order to obtain fast switching times while in Power down mode The reason is that with the oscillator stopped the temporary strong pull up that normally occurs during switching on a quasi bidirectional port pin does not take place Comparators consume power in Power down mode and Idle mode as well as in the normal operating mode This should be taken into consideration when system power consumption is an issue To minimize power consumption the user can power down the comparators by disabling the comparators and setting PCONA 5 to logic 1 or simply putting the device in Total Power down mode UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 95 of 134 NXP Semiconductors UM10147 P89LPC952 954 User manual CINnA CMPREF m con 002aaa618 a CPn CNn OEn 000 CINNA Vper 1 23 V COn 002aaa621 c CPn CNn OEn 010 CINnB P gt com CMPREF 002aaa623 e CPn CNn OEn 100 CINnB Var 1 23 V con 002aaa625 g CPn CNn OEn 110 Fig 42 Comparator configurations CINnA COn CMPREF SE b CPn CNn OEn CINnA COn Vper 1 23 V m OMen d CPn CNn OEn CINnB CMPREF f CPn CNn OEn COn CINnB n VREF 1 23 V h CPn CNn OEn 111 COn CMPn 002aaa620 001 002aaa622 011 002aaa624 101 002aaa626 13 6 Comparators configuration example The code sh
198. ve address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the 12C bus will not be released The P89LPC952 954 device provides a byte oriented ZC interface It has four operation modes Master Transmitter Mode Master Receiver Mode Slave Transmitter Mode and Slave Receiver Mode UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 69 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual SDA SCL P1 3 SDA P1 2 SCL OTHER DEVICE OTHER DEVICE GC MCU WITH I2C BUS WITH I2C BUS INTERFACE INTERFACE 002aac130 Fig 26 I C bus configuration The P89LPC952 954 CPU interfaces with the I C bus through six Special Function Registers SFRs I2CON SC Control Register DDAT GC Data Register I2STAT 12C Status Register IZADR 12C Slave Address Register I2SCLH SCL Duty Cycle Register High Byte and I2SCLL SCL Duty
199. when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but is cleared by software Note UART1 mode bits SMO0_1 and SM1_1 should be programmed when SMODO is logic 0 default mode on any reset UM10147_2 NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 60 of 134 NXP Semiconductors UM1 01 47 UM10147_2 P89LPC952 954 User manual Table 54 Serial Port modes SM0O_n SM1_n UART mode UART baud rate 00 Mode 0 shift register CCLK 6 default mode on any reset 01 Mode 1 8 bit UART Variable see Table 45 10 Mode 2 9 bit UART CELK or CCLKY 6 11 Mode 3 9 bit UART Variable see Table 45 Table 55 Serial Port 0 Status register SOSTAT address BAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DBMOD INTLO_O CIDIS_0 DBISEL_ FE_0O BR_O OE_0 STINT_O 0 0 Reset D xX D D xX X 0 0 Table 56 Serial Port 0 Status register SOSTAT address BAh bit description Bit Symbol Description 0 STINT_O Status Interrupt Enable 0 When set 1 FE_0 BR_O or OE_0 can cause an interrupt The interrupt used vector address 0023h is shared with RI CIDIS 1 or the combined TI RI CIDIS 0 When cleared 0 FE_0 BR_0 OE_0 cannot cause an interrupt Note FE_0 BR_0 or OE_0 is often accompanied by a RI_0 which will generate an interrupt regardless of the state of STINT_0 Note that BR_0O can cause a break detect reset if EBRR AUXR1 6 is set to logic 1
200. will occur If DBISEL_n is logic 1 and INTLO_n is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL_nis logic 1 and INTLO_nis logic 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data 7 If there is more data the CPU writes to TB8_n again 8 The CPU writes to SnBUF again Then If INTLO_n is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO_n is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter 9 Go to 4 10 Note that if DBISEL_n is logic 1 and the CPU is writing to SnBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following Multiprocessor communications UART modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received or transmitted When data is received the 9th bit is stored in RB8_n The UART can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8_n 1 This feature is enabled by setting bit SM2_n in SnCON One way to use
201. written during transmission In this case the data currently being transmitted will continue to be transmitted but the new data i e the one causing the collision will be lost While write collision is detected for both a master or a slave it is uncommon for a master because the master has full control of the transfer in progress The slave however has no control over when the master will initiate a transfer and therefore collision can occur For receiving data received data is transferred into a parallel read data buffer so that the shift register is free to accept a second character However the received character must be read from the Data Register before the next character has been completely shifted in Otherwise the previous data is lost WCOL can be cleared in software by writing a logic 1 to the bit Data mode Clock Phase Bit CPHA allows the user to set the edges for sampling and changing data The Clock Polarity bit CPOL allows the user to set the clock polarity Figure 37 to Figure 40 show the different settings of Clock Phase bit CPHA NXP B V 2008 All rights reserved User manual Rev 02 28 April 2008 89 of 134 NXP Semiconductors UM1 01 47 P89LPC952 954 User manual Clock cycle il i SPICLK CPOL 0 SPICLK CPOL 1 MOSI input DORD 0 MSB V LSB l SS if SSIG b
202. y organization FFOOh FFEFh 1FFFh 1E00h 1C00h 1BFFh 1800h 17FFh 1400h 13FFh 1000h OFFFh oCoOoh OBFFh 0800h O7FFh 0400h O3FFh 0000h Fig 5 P89LPC952 memory map P89LPC954 is similar Read protected SSeS DW IAP calls only 1 IAP entry 1 FFEFh beata eer SPECIALFUNCTION ag gelen F FEIER 128 BYTES ON CHIP 51 ASM code san REGISTERS DATA MEMORY STACK Lao FFOOh DIRECTLY ADDRESSABLE AND INDIR ADDR ATA 128 BYTES ON CHIP 1FFFh ISP serial loader DATA MEMORY STACK entry points for DIRECT AND INDIR ADDR Cd Beer 4 REG BANKS R 7 0 l2C etc SECTOR 6 EE data memory Flexible choices DATA IDATA SECTOR 5 as supplied UART Philips libraries SECTOR 4 user defined SECTOR 3 SECTOR 2 SECTOR 1 SECTOR 0 002aaa948 UM10147_2 The various P89LPC952 954 memory spaces are as follows DATA 128 bytes of internal data memory space 00h 7Fh accessed via direct or indirect addressing using instruction other than MOVX and MOVC All or part of the Stack may be in this area IDATA Indirect Data 256 bytes of internal data memory space OOh FFh accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it SFR Special Function Registers Selected CPU registers and peripheral control and status registers ac

Download Pdf Manuals

Related Search

Related Contents

Ariazone 601HD - User`s Manual  Manual XP 2.indd - MALVICA  Instrucciones de operación  pets Steam Mop User Guide IMPORTANT: RETAIN FOR FUTURE  Association des locataires du 19 rue Censier 75005 PARIS NOTE D  

Copyright © All rights reserved. Failed to retrieve file