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XC886/888CLM

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1. 1 Includes 1 Kbyte monitor ROM 2 The 24 32 Kbyte ROM has an additional 4 Kbyte Flash Figure 1 2 XC886 888 Block Diagram User s Manual 1 5 V1 1 2007 05 Introduction V 1 1 Cinfin eon XC886 888CLM Introduction 1 2 Pin Configuration The pin configuration of the XC886 which is based on the PG TQFP 48 package is shown in Figure 1 3 while that of the XC888 which is based on the PG TQFP 64 package is shown in Figure 1 4 Figure 1 3 XC886 Pin Configuration PG TQFP 48 Package top view User s Manual 1 6 V1 1 2007 05 Introduction V 1 1 infin eon XC886 888CLM Introduction 48 47 46 45 5 6 7 8 gre Aa RR O 8 y Ny Note The pins shaded in blue are not available in the PG TQFP 48 package
2. 0 0 00 ccc ees 2 5 2 2 7 Power Control PCON 0 0 ccc eee eee 2 6 2 3 Instruction MING 2 ce eee eee 2 6 3 Memory Organization 0 0 0 ccc eens 3 1 3 1 Compatibility between Flash and ROM devices 005 3 3 3 2 Program Memory 0 00 cc ee eee ets 3 4 3 3 Data Memory 0 ce eee eee etnies 3 4 3 3 1 Internal Data Memory 0 ce eens 3 4 3 3 2 External Data Memory 0 0 0 ce ees 3 5 3 4 Memory Protection Strategy 0 0 0c eee 3 6 3 4 1 Flash Memory Protection 0 0000 3 6 3 4 2 Miscellaneous Control Register 0 0 00 cee eee 3 9 3 5 Special Function Registers 2 0 cece ee 3 10 3 5 1 Address Extension by Mapping 2 00 eee ees 3 10 3 5 1 1 System Control Register O oana aana aaaea 3 12 3 5 2 Address Extension by Paging 000 cece eee ee eee 3 13 3 5 2 1 Page Register 0 ccc cee eee eens 3 15 3 5 3 Bit Addressing saecueacens eee saeesudens eeedeteuedende sense 3 16 3 5 4 System Control Registers 0 cc es 3 17 3 5 4 1 Bit Protection Scheme 2 0 ees 3 19 3 5 5 XC886 888 Register Overview 0 cee ee ees 3 21 3 5 5 1 CPU Registers nnna anana bore daee dean ebewnees 3 21 3 5 9 2 MDU REOISTETS sieaed eto seo doce tae enh Ghee an annie 3 22 3 0 0 0 CORDIC Registers 0 cee eee es 3 23 3 5 5 4 System Control Registers 0c cee ee es 3 24 User
3. Figure 1 4 XC888 Pin Configuration PG TQFP 64 Package top view User s Manual 1 7 V1 1 2007 05 Introduction V 1 1 Cinfin eon XC886 888CLM Introduction 1 3 Pin Definitions and Functions After reset all pins are configured as input with one of the following e Pull up device enabled only PU e Pull down device enabled only PD e High impedance with both pull up and pull down devices disabled Hi Z The functions and default states of the XC886 888 external pins are provided in Table 1 3 Table 1 3 Pin Definitions and Functions Symbol Pin Number Type Reset Function TQFP 48 64 State PO I O Port 0 Port 0 is an 8 bit bidirectional general purpose P0 0 11 17 I O port It can be used as alternate functions PO 1 13 21 for the JTAG CCU6 UART UART1 Timer 2 Timer 21 MultiCAN and SSC i Z i Z TDIO JTAG Serial Data Input T13HR_1 CCU6 Timer 13 Hardware Run Input RXD_1 UART Receive Data Input RXDC1_0 MultiCAN Node 1 Receiver Input COUT61_1 Output of Capture Compare EXF2 1 Timer 2 External Flag Output P0 2 12 18 PU CTRAP_2 CCU6 Trap Input TDO_O JTAG Serial Data Output TXD 1 UART Transmit Data Output Clock Output TXDC1_0 MultiCAN Node 1 Transmitter Output User s Manual 1 8 V1 1 2007 05 H TCK_0O JTAG Clock Input T12HR_1 CCU6 Timer 12 Hardware Run Input CC61_1 Input Output of Capture Compare channel 1 CLKOUT_O Clock Output RXDO 1 UART Transmit Data Output H channel 1 Introduction V 1 1
4. User s Manual MultiCAN V1 0 XC886 888CLM Controller Area Network MultiCAN Controller Description LEC Indicated Error Interrupt Enable LECIE enables the last error code interrupt of CAN node x This interrupt is generated with each update of bit field NSRx LEC with LEC gt 0 CAN protocol error 0 Last error code interrupt is disabled 1 Last error code interrupt is enabled Bit field NIPRx LECINP selects the interrupt output line which becomes activated at this type of interrupt Alert Interrupt Enable ALIE enables the alert interrupt of CAN node x This interrupt is generated by any one of the following events e A change of bit NSRx BOFF e A change of bit NSRx EWRN e A List Length Error which also sets bit NSRx LLE e A List Object Error which also sets bit NSRx LOE e A Bit INIT is set by hardware 0 Alert interrupt is disabled 1 Alert interrupt is enabled Bit field NIPRx ALINP selects the interrupt output line which becomes activated at this type of interrupt CAN Disable Setting this bit disables the CAN node The CAN node first waits until it is bus idle or bus off Then bit INIT is automatically set and an alert interrupt is generated if bit ALIE is set Configuration Change Enable 0 The Bit Timing Register the Port Control Register and the Error Counter Register may only be read All attempts to modify them are ignored The Bit Timing Register the Port Control Register and the Error Cou
5. l l i i 1D0 Global Module Control MultiCAN_RegsOv Figure 15 15 MultiCAN Kernel Register Address Map User s Manual 15 47 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 2 1 Global Module Registers All list operations such as allocation de allocation and relocation of message objects within the list structure are performed via the Command Panel It is not possible to modify the list structure directly by software by writing to the message objects and the LIST registers The Panel Control Register PANCTR is used to start a new command by writing the command arguments and the command code into its bit fields PANCTR Panel Control Register Reset Value 0000 0301 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RBU BUS r rh rh rwh Field Bits Type Description PANCMD 7 0 rwh Panel Command This bit field is used to start a new command by writing a panel command code into it At the end of a panel command the NOP no operation command code is automatically written into PANCMD The coding of PANCMD is defined in Table 15 7 BUSY Panel Busy Flag 0 Panel has finished command and is ready to accept a new command 1 Panel operation is in progress RBUSY Result Busy Flag 0 No update of PANAR1 and PANAR2 is scheduled by the list controller 1 A list command is running BUSY 1 that
6. RMAP 0 PAGE 6 ADC_CRCR1 Reset 004 Bit Field CH7 ae Conversion Request Control ADC_CRPR1 Reset 00y Bit Field CHP7 CHP6 CHP5 CHP4 Conversion Request Pending Te Cy ADC_CRMRI1 Reset 00 Bit Field LDEV CLRP SCAN ENSI ENTR ENGT Conversion Request Mode ND Register 1 j a Ee Dy ADC_QMRO Reset 00 Bit Field CEV TREV ins CLRV ENTR ENGT Queue Mode Register 0 fim e Pw ww pow Evy ADC_QSRO Reset 20 Bit Field 2 FILL Queue Status Register 0 Type r ne re ADC_QORO Reset 00 REQCHNR Queue 0 Register 0 ele mm CaF REQCHNR H ADC_QBURO Reset 00 Queue Backup Register 0 p type m m Bit Fiela EE REQCHNR we wo ww ADC_QINRO Reset 00 4 Queue Input Register 0 User s Manual 3 32 Memory Organization V 1 2 lt o_o o_o nN Pi 5 O J infin eon XC886 888CLM Memory Organization 3 5 5 8 Timer 2 Registers The Timer 2 SFRs can be accessed in the standard memory area RMAP 0 Table 3 10 T2 Register Overview Addr RegisterName Bt 7 6 5 4 3 2 4 O RMAP 0 T2_T2CON Reset 00y Bit Field EXF2 aa C T2 CP Timer 2 Control Register EF Type T2_T2MOD Reset 00y Bit Field EN EON a PREN ee Timer 2 Mode Register GS EN SEL Type CIES E SEAS Timer 2 Reload Capture Timer 2 Reload Capture T2_T2L Reset 001 Bit Field THL2 Timer 2 Register Low Type rwh T2_T2H Reset 001 Bit Field THL
7. 05 18 2 2 CAN Message Object definition 18 2 3 User Defined Parameter for MultiCAN BSL 19 IndeX 0 ees 19 1 Keyword Index 2 0 0 0 eee 19 2 Register Index 0 ee User s Manual I 10 XC886 888CLM V1 1 2007 05 Cinfine on XC886 888CLM Introduction 1 Introduction The XC886 888 is a member of the high performance XC800 family of 8 bit microcontrollers It is based on the XC800 Core that is compatible with the industry standard 8051 processor Furthermore the XC886 888 is a superset of the Infineon XC866 8 bit microcontroller thus offering an easy upgrade path for XC866 users The XC886 888 features both a CAN controller and LIN support integrated on a single chip to provide advance networking capabilities The on chip CAN module reduces the CPU load by performing most of the functions required by the networking protocol masking filtering and buffering of CAN frames The XC886 888 is equipped with either embedded Flash memory to offer high flexibility in development and ramp up or compatible ROM versions to provide cost saving potential in high volume production The XC886 888 memory protection strategy features read out protection of user intellectual property IP along with Flash program and erase protection to prevent data corruption The multi bank Flash architecture supports In Application Programming IAP allowing user program to modify Flash contents during program execu
8. Note The error interrupt handler must clear the associated enabled error flag s to prevent repeated interrupt requests Bits in Register CON Transmit gt Error 7 Receive Error Error Interrup EIR F Phase e Error Baud rate J Error Figure 12 17 SSC Error Interrupt Control A Receive Error master or slave mode is detected when a new data frame is completely received but the previous data was not read out of the register RB This condition sets the error flag CON RE and the EIR when enabled via CON REN The old data in the receive buffer RB will be overwritten with the new value and this lost data is irretrievable User s Manual 12 41 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces A Phase Error master or slave mode is detected when the incoming data at pin MRST master mode or MTSR slave mode sampled with the same frequency as the module clock changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK This condition sets the error flag CON PE and when enabled via CON PEN sets the EIR Note When receiving and transmitting data in parallel phase error occurs if the baud rate is configured to fiw o 2 A Baud Rate Error slave mode is detected when the incoming clock signal deviates from the programmed baud rate by more than 100 i e it is either more than double or less than half the expecte
9. 4 RXD Master Transmit Buffer Receive Buffer Register TB Register RB Internal Bus Figure 12 11 Synchronous Serial Channel SSC Block Diagram User s Manual 12 31 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 3 1 General Operation 12 3 1 1 Operating Mode Selection The operating mode of the serial channel SSC is controlled by its control register CON This register has a double function e During programming SSC disabled by CON EN 0 it provides access to a set of control bits e During operation SSC enabled by CON EN 1 it provides access to a set of status flags The shift register of the SSC is connected to both the transmit lines and the receive lines via the pin control logic Transmission and reception of serial data are synchronized and take place at the same time i e the same number of transmitted bits is also received Transmit data is written into the Transmitter Buffer register TB and is moved to the shift register as soon as this is empty An SSC master CON MS 1 immediately begins transmitting while an SSC slave CON MS 0 will wait for an active shift clock When the transfer starts the busy flag CON BSY is set and the Transmit Interrupt Request line TIR will be activated to indicate that register TB may be reloaded again When the programmed number of bits 2 8 have been transferred the contents of the shift register are moved to the Rec
10. 7 6 5 4 3 2 1 0 pa emes omes ome i rw rw rw rw r rw rw Field Bits Type Description EVINPx rw Interrupt Node Pointer for Event x x 0 1 4 7 This bit defines which SR lines becomes activated if the event x interrupt is generated Os The line SRO becomes activated 1 The line SR1 becomes activated 0 3 2 r Reserved Returns 0 if read should be written with 0 User s Manual 16 62 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter The bit fields in register LCBR define the four MSB of the compare values boundaries used by the limit checking unit The values defined in bit fields BOUNDO and BOUND1 are concatenated with either four 8 bit conversion or six 10 bit conversion Os at the end to form the final value used for comparison with the converted result For example the reset value of BOUND1 Bp will translate into BO for an 8 bit comparison and 2C0 for a 10 bit comparison LCBR Limit Check Boundary Register CD Reset Value B7 7 6 5 4 3 2 1 0 rw rw Field Bits Type Description BOUNDx Boundary for Limit Checking x 0 1 This bit field defines the four MSB of the compare value used by the limit checking unit The result of the limit check is used for interrupt generation User s Manual 16 63 V1 1 2007 05 ADC V 1 0 Cinfine on XC886 888CLM On Chip Debug Support 17 On Chip Debug Support The On Chip Debug Support OCDS provides the basic
11. Cinfineon XC886 888CLM Introduction Table 1 3 Pin Definitions and Functions contd Symbol Pin Number Type Reset TQFP 48 64 State k Bi i i i ail pos e Pu o7 ae Pu User s Manual Introduction V 1 1 Function SCK 1 COUT63_1 RXDO1_0 MTSR_1 CC62_1 TXD1_0 MRST_1 EXINTO_0O T2EX1_1 RXD1_0 COUT62_1 GPIO CLKOUT_1 SSC Clock Input Output Output of Capture Compare channel 3 UART1 Transmit Data Output SSC Master Transmit Output Slave Receive Input Input Output of Capture Compare channel 2 UART1 Transmit Data Output Clock Output SSC Master Receive Input Slave Transmit Output External Interrupt Input 0 Timer 21 External Trigger Input UART1 Receive Data Input Output of Capture Compare channel 2 Clock Output V1 1 2007 05 Cinfineon Table 1 3 Symbol Pin Number Type Reset Function TQFP 48 64 State P1 0 P1 2 P1 3 P1 4 PiS EEn k Big T 28 36 29 37 30 38 31 39 User s Manual Introduction V 1 1 Port 1 XC886 888CLM Introduction Pin Definitions and Functions contd Port 1 is an 8 bit bidirectional general purpose I O port It can be used as alternate functions for the JTAG CCU6 UART Timer 0 Timer 1 Timer 2 Timer 21 MultiCAN and SSC RXD_0O T2EX RXDCO_0 EXINTS TO_1 TDO_1 TXD_0 TXDCO_0 PU SCK_0 Pr Bi MTSR_O TXDC1_3 MRST_O EXINTO_1 RXDC1_3 CCPOSO_1 EXINTS T1_1 EXF2_0 RXDO_0
12. Field Description Pn Up Pull Down Select Port x Bit n n 0 7 Pull down device is selected Pull up device is selected Px PUDEN Port x Pull Up Pull Down Enable Register 7 6 5 4 3 2 1 0 IeIeI T TeTe T rw rw rw rw rw rw rw rw Field Description Pn _ Up Pull Down Enable at Port x Bit n n 0 7 Pull up or Pull down device is disabled Pull up or Pull down device is enabled User s Manual 6 9 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 1 1 5 Alternate Input and Output Functions The number of alternate functions that uses a pin for input is not limited Each port control logic of an I O pin provides several input paths of digital input value via register or direct digital input value Alternate functions are selected via an output multiplexer which can select up to four output lines This multiplexer can be controlled by the following registers e Register Px_ALTSELO e Register Px _ALTSEL1 Selection of alternate functions is defined in registers Px_ALTSELO and Px_ALTSEL41 Px ALTSELn n 0 1 Port x Alternate Select Register 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn Pin Output Functions n 0 7 Configuration of Px_ALTSELO Pn and Px_ALTSEL1 Pn for GPIO or alternate settings 00 Normal GPIO 10 Alternate Select 1 01 Alternate Select 2 11 Alternate Select 3 Note Set Px_ALTSELO Pn and Px_ALTSEL1 Pn to select only implemented alternate output func
13. IDEE ae eee ee 1DC2 1DC1 1DCO oone all cae senece nance le Ateeae ress 00C2 00C1 00CO OOB Rial a che 0082 0081 0080 OOT Ga ote ceteree cere nore 0042 0041 0040 QOS i llaeeees eee er eee 0002 0001 0000 WL Address P Flash Wordline Addresses 4 6 V1 1 2007 05 infin eon XC886 888CLM Flash Memory Byte 31 Byte 2 Byte 1 ByteO Byte 31 Byte2 Byte1 ByteO age ee ee 7FE2 7FE1 7FEQ ON g BFFR scsssescsces sianvesivdenctseectace 6FE2 6FEt 6FEO A Brg l 54 Dog on 4 Ms Na TFOF ceseseseceseseesesteeseeeeess 7F82 7F81 7F80 GFOF essseseccsseccseseeeseeteseeven 6F82 6F81 6F80 hei E AETA 7F62 7F61 7F60 2 Gi Le a eee eee ee 6F62 6F61 6F60 Q or Q or 5 POE Sy a 09 Lo 3 BY 2 B28 Mj DM _j Tie E MSEE EA i mai 7F02 7F01 7F00 GEE O eattestiae 6F02 6F01 6F00 JEFF censeceuteerctaniitissoteannce 7EE2 7EE1 7EEO 2 GEPF sipasnintin 6EE2 6EE1 6EE0 2 Nog mog Sos S of og oa Mj Mr JE9F a aenaran nan T ii 7E82 7E81 7E80 BE9F aissis 6E82 6E81 6E80 TEE A ere eee eae 7E62 7E61 7E60 egal eee tara oe
14. UART Receive Data Input Timer 2 External Trigger Input MultiCAN Node 0 Receiver Input External Interrupt Input 3 Timer O Input JTAG Serial Data Output UART Transmit Data Output Clock Output MultiCAN Node 0 Transmitter Output SSC Clock Input Output SSC Master Transmit Output Slave Receive Input MultiCAN Node 1 Transmitter Output SSC Master Receive Input Slave Transmit Output External Interrupt Input 0 MultiCAN Node 1 Receiver Input CCU6 Hall Input 0 External Interrupt Input 5 Timer 1 Input Timer 2 External Flag Output UART Transmit Data Output V1 1 2007 05 Cinfin eon XC886 888CLM Introduction Table 1 3 Pin Definitions and Functions contd Symbol Pin Number Type Reset Function TQFP 48 64 State 8 10 PU CCPOS1_1 CCU6 Hall Input 1 T12HR_O CCU6 Timer 12 Hardware Run Input EXINT6_0 External Interrupt Input 6 RXDCO 2 MultiCAN Node 0 Receiver Input T21_1 Timer 21 Input 9 11 PU CCPOS2_1 CCU6 Hall Input 2 T13HR_0O CCU6 Timer 13 Hardware Run Input T2_1 Timer 2 Input TXDCO 2 MultiCAN Node 0 Transmitter Output P1 5 and P1 6 can be used as a software chip select output for the SSC User s Manual 1 11 V1 1 2007 05 Introduction V 1 1 Cinfineon Table 1 3 Symbol Pin Number Type Reset Function TQFP 48 64 State Port 2 Port 2 is an 8 bit general purpose input only port It can be used as alternate functions for the digital inputs of the JTAG and CCU6 It is also used as the
15. e Ol Enter Fast LIN BSL e Other values Ignored Fast LIN BSL is not entered Note The Block Length used in UART BSL is not implemented here as a Diagnostic LIN frame has a standard 8 data bytes structure followed by the checksum When this Command LIN frame Header Block is used for entering Fast LIN BSL no other Master Request Header and Command LIN frames for Data Block or EOT Block should be received Instead the microcontroller will receive a Slave Response Header LIN frame and send a Response LIN frame to acknowledge receiving correct header block to enter Fast LIN BSL where UART BSL protocol is used See Section 18 1 3 9 On successfully receipt of the Header Block the microcontroller enters Mode 0 2 8 whereby the program code is transmitted from the host to the microcontroller by Data Block and EOT Block which are described below The Data Block NAD Data Block Program Code Checksum 1 byte 01 6 bytes 1 byte Description Program Code The program code has a fixed length of 6 bytes per Data Block Note No empty Data Block is allowed The EOT Block NAD EOT Block Last_Codelength Program Code Checksum 1 byte 02 1 byte 1 byte Description Last_Codelength This byte indicates the length of the program code in this EOT Block Program Code The last program code valid data to be sent to the microcontroller Not used The length is LIN_Block_Length 4 Last_Codelength These bytes are not used and
16. e UART BSL e LIN BSL e MultiCAN BSL If a device is programmed as LIN LIN BSL is always entered If a device is programmed as UART MultiCAN then the entry to the respective BSL UART or MultiCAN is decided based on their initial header frames Note UART BSL is supported only via UART module and not UART1 Note For BSL modes only the default set of receive transmit pins of UART and MultiCAN node 0 P1 0 P1 1 can be used Note For the Flash devices BSL mode is entered automatically via user mode pin configuration if no valid password is installed and the data at memory address 0000 equals zero Table 18 1 Pin Configuration to Enter BSL Mode MBC MODE Comment 0 BSL Mode via UART LIN OSC PLL non bypassed normal or MultiCAN OSC bypassed PLL non bypassed Latched pin values Section 18 1 describes the UART and LIN BSL modes while Section 18 2 describes the MultiCAN BSL mode User s Manual 18 1 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM 18 1 UART and LIN BSL Modes The UART and LIN BSL Modes have three functional parts represented by the three phases described below Bootstrap Loader e Phase I Establish a serial connection and automatically synchronize to the transfer speed baud rate of the serial communication partner host e Phase Il Perform serial communication with the host The host controls and sends a special header information which selects one of the modes describ
17. refers to the input clock frequency PCON Power Control Register Reset Value 00 7 6 5 4 3 2 1 0 a ie rw r rw rw r rw User s Manual 12 10 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces Field Bits Type Description SMOD 7 rw Double Baud Rate Enable 0 Do not double the baud rate of serial interface in modes 1 2 and 3 1 Double the baud rate of serial interface in mode 2 and in modes 1 and 3 only if Timer 1 is used as variable baud rate source 0 1 6 4 r Reserved Returns 0 if read should be written with 0 Baud rate in Mode 2 For UART module the baud rate in mode 2 is dependent on the value of bit SMOD in the PCON register If SMOD 0 value after reset the baud rate is 1 64 of the input clock frequency fpc If SMOD 1 the baud rate is 1 32 of foc 12 1 SMOD Mode 2 baud rate Ta x fPCLK For UART1 module the baud rate in mode 2 does not depend on the bit SMOD and is always 1 64 of the input clock frequency fpc k 12 1 4 2 Dedicated Baud rate Generator Each of the UART modules has a dedicated baud rate generator that is based on a programmable 8 bit reload value and includes divider stages i e prescaler and fractional divider for generating a wide range of baud rates based on its input clock fog x The baud rate timer is a count down timer and is clocked by either the output of the fractional divider f yop if the fractional divider is enabled
18. 1 30 2859 1 37 1965 ND for X lt 1 2 0 3980 ND for Y lt 2 Input conditions Useful Domain Y lt X X gt 0 Jatanh Y X lt 1 11rad 34 5399 34 5438 17 9254 0 58 3062 1 41 6938 ND for Z lt 1 11 6747 1 3162 DforX lt 4 11 10 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfin eon XC886 888CLM CORDIC Coprocessor Table 11 3 Normalized Deviation of a Calculation cont d Mode X Normalized Deviation Y or Z Normalized Deviation Hyperbolic Input conditions Useful Domain Z lt 1 11rad Y 0 Rotation 14 9401 40 4787 31 6474 40 6711 23 7692 11 9209 14 8353 4 6940 7 4881 1 7290 4 3398 0 4453 2 4387 0 0607 0 5267 0 0003 0 0146 D for Y lt 7 D forX lt 8 Note The accuracy deviation as stated above for each mode is not guaranteed for the final result of multi step calculations e g if an operation involves two CORDIC calculations the second calculation uses the result data from the first calculation enabled with corresponding KEEP bit set This is due to accumulated approximations and errors 11 2 7 Performance of CORDIC Coprocessor The CORDIC calculation time increases linearly with increased precision Increased precision is achieved with greater number of iterations which requires increased width of the data parameters The CORDIC Coprocessor uses barrel shifters for data shifting For a fixed number of 16
19. 32 bytes 1 WL XC886 888CLM Flash Memory 16 bytes 16 bytes 0000 0000 4 0000 0000 rogram 1 0000 0000 1111 1111y 0000 0000 1111 1111 4 Program 2 1111 0000 4 0000 0000 1111 0000 y Flash memory cells Figure 4 7 D Flash Program User s Manual 4 10 Flash Memory V 1 0 Note A Flash memory cell can be programmed from 0 to 1 but not from 1 to O 32 byte write buffers V1 1 2007 05 Cinfin eon XC886 888CLM Flash Memory 4 5 Operating Modes The Flash operating modes for each bank are shown in Figure 4 8 Sector s Erase Ready to Read Program Call of Call of FLASH ERASE routine FLASH PROG routine or by BSL or by BSL Power Down System Power Down Figure 4 8 Flash Operating Modes In general the Flash operating modes are controlled by the BSL and Flash program erase subroutines see Section 4 8 Each Flash bank must be in ready to read mode before the program mode or sector s erase mode is entered In the ready to read mode the 32 byte write buffers for each Flash bank can be written and the memory cell contents read via CPU access In the program mode data in the 32 byte write buffers is programmed into the Flash memory cells of the targeted wordline The operating modes for each Flash bank are enforced by its ded
20. ADC is disabled SSC DIS an Disable Request Active high SSC is in normal operation default SSC is disabled User s Manual 8 7 V1 1 2007 05 Power Saving Modes V 1 0 Cinfine on XC886 888CLM Power Saving Modes Field ai Description CCU DIS r Disable Request Active high CCU is in normal operation default CCU is disabled T2_DIS Timer 2 Disable Request Active high 0 Timer2 is in normal operation default 1 Timer2 is disabled MDU_DIS 4 rw MDU Disable Request Active high 0 MDU is in normal operation default 1 MDU is disabled CAN_DIS 5 CAN Disable Request Active high 0 CAN is in normal operation default 1 CAN is disabled CDC_DIS m Disable Request Active high CORDIC is in normal operation default CORDIC is disabled 0 Reserved Returns 0 if read should be written with O PMCON2 Power Mode Control Register 2 Reset Value 00 7 6 5 4 3 2 1 0 UART1_ ee ee ee r rw rw Field Description T21_DIS mer 21 Disable Request Active high Timer 21 is in normal operation default Timer 21 is disabled UART1_DIS rah Disable Request Active high UART1 is in normal operation default UART1 is disabled 0 7 2 Reserved Returns 0 if read should be written with 0 User s Manual 8 8 V1 1 2007 05 Power Saving Modes V 1 0 Cinfine on XC886 888CLM Power Saving Modes ADC_GLOBCTR Global Control Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw r Field Description ANON Analog Part Switc
21. ALT3 P1 5 Input P1_DATA P5 ALT1 CCPOSO_1 CCU6 ALT2 EXINTS External interrupt 5 Output GPO P DATA P5 ALT1 EXF2_0 Timer 2 ALT2 RXDO_0 UART ATS eaa External interrupt 6 at ae po o H am User s Manual 6 22 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Table 6 6 Port 1 Input Output Functions Port Pin ees e ee From to Module P1 7 Input GPI P1_DATA P7 ameo me y L 0 P1 5 can be used as a software Chip Select function for the SSC 2 P1 6 can be used as a software Chip Select function for the SSC User s Manual 6 23 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 4 2 Register Description P1 DATA Port 1 Data Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field ee Description Pn 1 Pin n Data Value n 0 7 Port 1 pin n data value 0 default Port 1 pin n data value 1 P1_DIR Port 1 Direction Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn 1 Pin n Direction Control n 0 7 Direction is set to input default Direction is set to output User s Manual 6 24 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports P1_OD Port 1 Open Drain Control Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn ron 1 Pin n Open Drain Mode n 0 7 Normal mode output is actively driven for 0 and 1 states
22. An overflow has occurred since last flag reset eres must be reset by software 0 21 Reserved 31 24 Read as 0 should be written with 0 Bit Timing Analysis Modes Table 15 9 Bit Timing Analysis Modes CFMOD 10 CFSEL Measurement 000p Whenever a dominant edge transition from 1 to 0 is monitored on the receive input the time measured in clock cycles between this edge and the most recent dominant edge is stored in CFC 001 Whenever a recessive edge transition from 0 to 1 is monitored on the receive input the time measured in clock cycles between this edge and the most recent dominant edge is stored in CFC 010 Whenever a dominant edge is received as a result of a transmitted dominant edge the time clock cycles between both edges is stored in CFC 011 Whenever a recessive edge is received as a result of a transmitted recessive edge the time clock cycles between both edges is stored in CFC 100 Whenever a dominant edge that qualifies for synchronization is monitored on the receive input the time measured in clock cycles between this edge and the most recent sample point is stored in CFC 101 With each sample point the time measured in clock cycles between the Start of the new bit time and the start of the previous bit time is stored in CFC 1 1 0 Additional information is written to CFC 15 12 at each sample point CFC 15 Transmit value of actual bit time CFC 14 Receive sample value of actual bit ti
23. Cinfine on XC886 888CLM Parallel Ports 6 7 Port 4 Port P4 is an 8 bit general purpose bidirectional port The registers of P4 are Summarized in Table 6 11 Table 6 11 Port 4 Registers Register Short Name Register Full Name P4 DATA Port 4 Data Register P4 DIR Port 4 Direction Register P4 OD Port 4 Open Drain Control Register P4 PUDSEL Port 4 Pull Up Pull Down Select Register P4 PUDEN Port 4 Pull Up Pull Down Enable Register P4 ALTSELO Port 4 Alternate Select Register 0 P4 ALTSEL1 Port 4 Alternate Select Register 1 6 7 1 Functions Port 4 input and output functions are shown in Table 6 12 Table 6 12 Port 4 Input Output Functions Port Pin P4 0 Input GPI ALT1 ALT2 ALT3 Output GPO ALT1 ALT2 ALT 3 Connected Signal s From to Module P4 DATA PO RXDCO_3 MultiCAN P4 DATA PO CC60_1 CCU6 User s Manual 6 39 V1 1 2007 05 Parallel Ports V 1 0 Infineon XC886 888CLM i Parallel Ports Table 6 12 Port 4 Input Output Functions cont d Port Pin Input Output P4 1 Input Connected Signal s From to Module GP P4 DATA P1 gt gt gt Tm e 4 4 44 P Output GPO P4 DATA P1 COUT60 _1 CCU6 TXDCO 3 MultiCAN Input GPI P4 DATA P2 T121 0 Timer 21 EXINT6_1 External Interrupt 6 gt gt gt Tm P e H OINI Output GPO P4 DATA P2 EN DA gt gt gt gt gt gt Tm e Tm e 4 4 44 H OINI OINI zi OD Input GPI P4 DATA P3 gt
24. RF 5 rh Refill This bit is updated by bit QORO RF when the conversion requested by QORDO is started ENSI rh Enable Source Interrupt This bit is updated by bit QORO ENSI when the conversion requested by QORDO is started EXTR 7 rh External Trigger This bit is updated by bit QORO EXTR when the conversion requested by QORDO is started 0 3 r Reserved Returns 0 if read should be written with 0 User s Manual 16 47 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Register QINRO is the entry register for sequential requests QINRO Queue Input Register 0 D2 Reset Value 00 7 6 5 4 3 2 1 0 jem em fe e enn W W W r W Field Description REQCHNR 2 CO Request Channel Number This bit field defines the requested channel number RF Refill This bit defines the refill functionality ENSI W Enable Source Interrupt This bit defines the source interrupt functionality EXTR T W External Trigger This bit defines the external trigger functionality 0 4 3 r Reserved Returns 0 if read should be written with 0 User s Manual 16 48 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 7 7 Parallel Source Registers These registers contain the control and status bits of parallel request source 1 Register CRCR1 contains the bits that are copied to the pending register CRPR1 when the load event occurs This register can be accessed at two different addresses one
25. SCHE ee a Ea KE Capture Compare Interrupt Status PM CM Set Register High Tee w w PSL63 CCU6_PSLR Reset 00y Bit Field PSL63 Passive State Level Register Type rwh CCU6_MCMCTR Reset 00 Bit Field ee SWSYN T SWSEL i ep m Multi Channel Mode Control Register Bit Field T13TED TISTEC T13 T12 SSC SSC User s Manual 3 36 V1 1 2007 05 Memory Organization V 1 2 CCU6_TCTR2L Reset 00y Timer Control Register 2 Low el Cinfine on XC886 888CLM Memory Organization Table 3 12 CCU6 Register Overview i Register Name FBuy CCU6_TCTR2H Reset 00 Bit Field Timer Control Register 2 High cont d e Nr T13RSEL T12RSEL T12MODEN Type CCU6_MODCTRL Reset 004 Bit Field Modulation Control Register Low MCM Type Bit Field r ECT1 r T13MODEN CCU6_MODCTRH Reset 00H Modulation Control Register High r Go m O Z rw TRPM TRPM TRPM 2 1 0 TRPP TRPE TRPEN EN N13 Type CCU6_TRPCTRL Reset 004 Bit Field Trap Control Register Low Type CCU6_TRPCTRH Reset 004 Bit Field Trap Control Register High Type rw gt i CCU6_MCMOUTL Reset 004 Bit Field Me MCMP Multi Channel Mode Output Register Low By CCU6 MCMOUTH Reset 00y BitFiea 0 CURH EXPH Multi Channel Mode Output Register Cy CCU6_ISL Reset 00h Bit Field T12 T12 ICC62 ICC62 ICC61 ICC61 ICC60 ICC60 F R oh T h Capture Compa
26. Sector O WLO 119 3 75KByte x2 128 byte Sector 2 x2 x2 128 byte Sector 1 WL 120 123 WL 124 127 P Flash Pair O Sector 0 WL 0 119 3 75 KByte x2 Byte 63 Byte 2 Byte1 ByteO 2 leat ce ae enn nee SFC2 5FC1 SFCO 5 gat Sal EE er aaa ae ema eee SFO2 SFO1 SFOO SERIES S E SEC2 5EC1 5ECO SEF y airesin uniits Eeer rinitni 5E02 5E01 5EOO SDF Susteren rae saree 5DC2 5DC1 5DCO 10E perenne ee te eet e 40C2 40C1 40C0 40BF INE e a cca 4082 4081 4080 AO earl esetececeecrmec ae wer emas veneer 4042 4041 4040 BOS a M PADE a cree cea R o ae 4002 4001 4000 OIE E ceria tae oes sce 3FC2 3FC1 3FCO ro aS eval eee Aare eee ae earner 3F02 3F01 3F00 SEPE aera E E A EE 3EC2 3EC1 3ECO lol gl eE a E 3E02 3E01 3E00 SDRE ell caeccereere acces eeactoee 3DC2 3DC1 3DCO0 20E nee ann ones tas ner 20C2 20C1 20C0 PAS torte Mee rerinee aneer ime nara raat 2082 2081 2080 207 Fae suas sven tenconcatawoem ues 2042 2041 2040 AOS ar al e rrer cee re ree ree 2002 2001 2000 se pe roan E oneee eee een 1FC2 1FC1 1FCO IESE dll ee a canteen conees once Wire Meets Weeks TEP Rigi ae a ae 1EC2 1EC1 1ECO IESE a e E 1E02 1E01 1E00
27. Without hardware With hardware protection protection D Flash Read instructions in Read instructions in Read instructions in contents can be any program memory any program memory the P Flash or D read by Flash External access Not possible Not possible Not possible to D Flash D Flash Possible Possible Not possible program D Flash erase Possible Possible on Not possible condition that bit DFLASHEN in register MISC_CON is set to 1 prior to each erase operation In Flash hardware protection mode 0 an erase operation on either of the D Flash banks can proceed only if bit DFLASHEN in register MISC_CON is set to 1 At the end of each erase operation DFLASHEN is cleared automatically by hardware Hence it is necessary to set DFLASHEN before each D Flash erase operation While the setting of DFLASHEN is taken care by the Bootstrap Loader BSL routine during D Flash in system erasing DFLASHEN must be set by the user application code before starting each D Flash in application erasing The extra step serves to prevent inadvertent destruction of the D Flash contents Parallel erase of the D Flash banks is disallowed in Flash protection mode 0 Two D Flash erase operations are needed to erase D Flash banks 0 and 1 The user programmable password must be of the format shown in Table 3 2 User s Manual 3 7 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization Table 3 2 User
28. s Manual Interrupt System V 1 0 Interrupt Flag SFR TFO TCON TF1 TCON TF2 T2_T2CON EXF2 T2_T2CON T21_T2CON EXF2 T21_T2CON EOFSYN FDCON ERRSYN FDCON SCON SCON NDOV FDCON UART1_SCON UART1_SCON NDOV UART1_FDCON IEO TCON E TCON EXINT2 IRCONO EXINTS IRCONO EXINT4 IRCONO EXINT5 IRCONO EXINT6 IRCONO EOC STATC IRDY MDUSTAT IERR MDUSTAT ADCSRO IRCON1 ADCSR1 IRCON1 7 NO ok 5 3 V1 1 2007 05 Cinfineon Table 5 4 Interrupt Source SSC Error SSC Transmit SSC Receive MultiCAN Interrupt 0 MultiCAN Interrupt 1 MultiCAN Interrupt 2 MultiCAN Interrupt 3 MultiCAN Interrupt 4 MultiCAN Interrupt 5 MultiCAN Interrupt 6 MultiCAN Interrupt 7 CCU6 Node 0 Interrupt CCU6 Node 1 Interrupt CCU6 Node 2 Interrupt CCU6 Node 3 Interrupt Watchdog Timer NMI PLL NMI Flash NMI VDD Prewarning NMI VDDP Prewarning NMI Flash ECC NMI Locations of the Interrupt Request Flags contd XC886 888CLM Interrupt System Interrupt Flag SFR R IRCON1 IRCONT IRCON1 IRCON2 IRCON1 IRCON1 IRCON2 IRCON3 IRCON3 IRCON4 IRCON4 IRCON3 IRCON3 IRCON4 IRCON4 NMISR NMISR NMISR NMISR NMISR NMISR m T T CANSRCO CANSRC1 CANSRC2 CANSRC3 CANSRC4 CANSRC5 CANSRC6 CANSRC7 CCU6SRO CCU6SR1 CCU6SR2 CCU6SR3 FNMIWDT FNMIPLL FNMIFLASH FNMIVDD FNMIVDDP FNMIECC 0 Different MultiCAN interrupt can be assigned to different MultiCAN interrupt output lines 7 0 via MultiCAN r
29. 0 ce ee 13 2 13 1 1 Basic Timer Operations 0 0 0 0 cc eee ee ees 13 2 13 1 2 Timer Modes 0 cc ee eee ees 13 3 13 1 2 1 MOOG CO gina oh eek wt Canaan eh oe eee eh eee ees 13 4 13 1 2 2 MOG T ea reana oven suneudeaoers ae andeneee arene eae 13 5 13 1 2 3 MOO 4h eater heeeneudeete ERTER 13 6 13 1 2 4 Aa e e op acaeseneews ee dd aeons eo eee TE 13 7 13 1 3 FOR CODIO 24 cunndv0hsd ad eaeerae eben ESAERAN awed 13 8 13 1 4 Register Map 0 ce ete eens 13 9 13 1 5 Register Description 0 ccc ees 13 10 13 2 Timer 2 and Timer 21 2 es 13 14 13 2 1 Basic Timer Operations 0 2 0 0 0 eee eee 13 14 13 2 2 Auto Reload Mode 0 cc ee eee 13 14 13 2 2 1 Up Down Count Disabled 0 0 cc ee 13 14 13 2 2 2 Up Down Count Enabled 0 0 cc es 13 15 13 2 3 Capture Mode 0 cc eee eens 13 18 13 2 4 COUNGCIOCK 44 ditbeetaroene tanh ane she ee eae ea eh bed an eee 13 19 13 2 5 External Interrupt Function 0 000 ees 13 20 13 2 6 POM COMMO 42400050604 0ueeeaeoypas eben be odueassbeanes 13 20 1 24 Low Power Mode 2 0c ccc ee ee eens 13 21 13 2 8 Module Suspend Control 0 0 00 ee ee 13 22 13 2 9 Register Map 0 0 ccc eee eens 13 23 13 2 10 Register Description 0 aaan aa ee es 13 24 14 Capture Compare Unit6 0 0 ce ee 14 1 14 1 Functional Description 1 0 0 0 00 cc eee 14 3 14 1 1 UME VA gins tenba
30. 0 7 for an LEC interrupt of CAN Node x 0000 Interrupt output line CANSRCO is selected 0001 Interrupt output line CANSRC1 is selected 0111 Interrupt output line CANSRC7 is selected 1000 1111 IReserved User s Manual 15 66 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Field md Description TRINP 11 8 Transfer OK Interrupt Node Pointer TRINP selects the interrupt output line CANSRCm m 0 7 for a transfer OK interrupt of CAN Node x si Interrupt output line CANSRCO is selected 0001 Interrupt output line CANSRC1 is selected 01 11 Interrupt output line CANSRC7 is selected 1000 1111 lReserved CFCINP 15 12 rw Frame Counter Interrupt Node Pointer CFCINP selects the interrupt output line CANSRCm m 0 7 for a frame counter overflow interrupt of ao Node x 0000 Interrupt output line CANSRCO is selected 0001 Interrupt output line CANSRC1 is selected 01 11 Interrupt output line CANSRC7 is selected 1000 1111 Reserved 0 31 16 r Reserved Read as 0 should be written with O User s Manual 15 67 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller The Node Port Control Register NPCRx configures the CAN bus transmit receive ports NPCRx can be written only if bit NCRx CCE is set NPCRx x 0 1 Node x Port Control Register Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
31. 0 The on chip oscillator is not powered down 1 The on chip oscillator is powered down Note The on chip oscillator must not be powered down even when external oscillator is used 7 5 Ir Reserved Returns 0 if read should be written with O x Note The reset value of register OSC_CON is 0000 1000 One clock cycle after reset bit OSCR will be set to 1 if the oscillator is running then the value 0000 1001 will be observed User s Manual 7 17 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management PLL_CON PLL Control Register Reset Value 1001 0000 7 6 5 4 3 2 1 0 rw rw rw rwh rh Field LOCK Type Description PLL Lock Status Flag 0 PLL is not locked PLL is locked RESLD rwh Restart Lock Detection 8 Setting this bit will reset the PLL lock status flag and restart the lock detection This bit will automatically be reset to 0 and thus always be read back as 0 0 No effect 1 Reset lock flag and restart lock detection OSCDISC 2 rw Oscillator Disconnect 0 Oscillator is connected to the PLL 1 Oscillator is disconnected from the PLL VCOBYP 3 rw PLL VCO Bypass Mode Select 0 Normal operation default 1 VCO bypass mode PLL output clock is derived from input clock divided by P and K dividers User s Manual 7 18 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management Field B
32. 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Table 6 4 Port 0 Input Output Functions Scie Port Pin Leaner _soemeentd 1 From to Module i ae eooo amooo h User s Manual 6 14 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Table 6 4 Port 0 Input Output Functions Scie Port Pin Cea seaman 1 From to Module Ae ALT3 CC62 1 CCU6 Output GPO PO_DATA P4 PODATAPS External interrupt 0 a H i i am mobo wmo awe eo ooo y o aws eooo y o User s Manual 6 15 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Table 6 4 Port 0 Input Output Functions Scie Port Pin InpuvOwtput Sect Connected Sigrate From to Module An pooo l ame eooo h a gt ALT3 Output GPO PO_DATA P7 pomar Ae am Pin PO 6 is only available in XC888 User s Manual 6 16 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 3 1 1 Register Description Note For the XC886 bit P6 is not available for use as its corresponding pad is not bonded PO DATA Port 0 Data Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn _ 0 Pin n Data Value n 0 7 Port O pin n data value O default Port 0 pin n data value 1 PO_DIR Port 0 Direction Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn _ 0 Pin n Direction Control n 0 7 Direction
33. 4 tapcp 16 3 Refer to Section 16 7 2 for register description of priority and arbitration control User s Manual 16 9 V1 1 2007 05 ADC V 1 0 Cinfine on XC886 888CLM Analog to Digital Converter 16 4 2 Conversion Start Modes At the end of each arbitration round the arbiter would have found the request source with the highest priority and a pending conversion request It stores the arbitration result namely the channel number the sample time and the targeted result register for further actions If the analog part is idle a conversion can be started immediately If a conversion is currently running the arbitration result is compared to the priority of the currently running conversion If the current conversion has the same or a higher priority it will continue to completion Immediately after its completion the next conversion can begin As soon as the analog part is idle and the arbiter has output a conversion request the conversion will start In case the new conversion request has a higher priority than the current conversion two conversion start modes exist selectable by bit CSMx x 0 1 e Wait for Start In this mode the current conversion is completed normally The pending conversion request will be treated immediately after the conversion is completed The conversion start takes place as soon as possible e Cancel Inject Repeat In this mode the current conversion is aborted immediately if a new request
34. Bit field RESULT in register FDRES represents the timer value while bit field STEP in register FDSTEP defines the reload value At each timer overflow an overflow flag FDCON NDOV will be set and an interrupt request generated This gives an output clock fyop that is 1 n of the input clock fp y where n is defined by 256 STEP The output frequency in normal divider mode is derived as follows 12 5 1 f f ORE pee aad 256 STEP Figure 12 5 shows the operation in normal divider mode with a reload value of STEP FD In order to get fon Jow STEP must be programmed with FF User s Manual 12 15 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces Figure 12 5 Normal Mode Timing Baud Rate Generator Registers Both UART and UART1 module baud rate generators contain the five SFRs BG BCON FDCON FDSTEP and FDRES The functionality of these registers are described in the following pages Register BCON contains the control bits for the baud rate generator and the prescaling factor BCON Baud Rate Control Register Reset Value 00 7 6 5 4 3 2 1 0 poset pros mre rw r rw rw rw Field ee Description R Baud rate Generator Run Control 0 Baud rate generator is disabled 1 Baud rate generator is enabled Note BR_VALUE should only be written if R 0 BRPRE 3 1 Irw Prescaler Select 000 fow fpoLk 001 Jow fpoLK 2 010 Jow fecik 4 011 fow fecik 8 100 tow fecoik 16 10
35. CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Bits Type Description HSYNC 6 4 rw Hall Synchronization Bit field HSYNC defines the source for the sampling of the Hall inout pattern and the comparison to the current and the expected Hall pattern bit fields In all modes a trigger by software by writing a 1 to bit SWHC is possible 000 Any edge at one of the inputs CCPOSx x 0 1 2 triggers the sampling 001 A T13 compare match triggers the sampling 010 A T13 period match triggers the sampling 011 The Hall sampling triggered by hardware sources is switched off 100 A112 period match while counting up triggers the sampling 101 A112 o0ne match while counting down triggers the sampling 110 A112 compare match of channel 0 while counting up triggers the sampling 111 A 112 compare match of channel 0 while counting down triggers the sampling W DBYP 7 r Delay Bypass Bit DBYP defines if the source signal for the sampling of the Hall input pattern selected by HSYNC uses the dead time counter DTCO of timer T12 as additional delay or if the delay is bypassed 0 The delay bypass is not active The dead time counter DTCO is generating a delay after the source signal becomes active 1 The delay bypass is active The dead time counter DTCO is not used by the sampling of the Hall pattern Note In the capture modes all edges at the CC6x inputs lead to the setting of the correspondi
36. Controller 15 1 10 Access Mediator The MultiCAN needs to cover a maximum of 16 Kbytes SFR kernel address range which is much greater than the XC886 888 can provide To meet this demand an address extension decoding mechanism is built in the unit called Access Mediator to decode the SFRs in the MultiCAN kernel The address lines are not directly controlled by the CPU instruction itself but they are derived from register bits that have to be programmed before accessing the MultiCAN kernel To decode the address of the MultiCAN kernel registers at least 14 bit address line is needed As the MultiCAN registers are 32 bit wide 4 Bytes then the address lines A 1 0 are not needed for decoding and are tied to 00 The address lines A 13 2 are implemented and they are programmed from the register bits CA2 to CA9 in the register CAN_ADL and CA10 to CA13 in the register CAN_ADH The address registers need to be programmed before accessing the MultiCAN registers The data bus are 32 bit D 31 0 between the Access Mediator and MultiCAN kernel Four data registers CAN DATAn n 3 0 are implemented in the Access Mediator Each register in the MultiCAN kernel is read and written via these 4 data registers When writing to MultiCAN kernel the data in the registers CAN_DATAn n 3 0 are set valid or not valid by configuring the register bits Vn n 3 0 in the register CAN _ADCON Only the valid data bytes are sent during the write proc
37. Controller 15 1 7 2 Pending Messages With a message interrupt request generation a message pending bit is set in one of the Message Pending Registers There are two Message Pending Registers MSPNDk k 1 0 with 32 pending bits available to each resulting in 64 pending bits Figure 15 10 shows the allocation of the message pending bits Message Object n Interrupt Pointer Register MOIPRn 15 0 TXINP RXINP MPN EAC CEE Ee Ou 0 transmit event 1 receive event Message Pending Registers p 63 MSPND1 5 MSPNDO bo b DA E E a MPSEL a gt O xczZmuUo Modul Control Register MCR 31 0 MultiCAN_msgpnd Figure 15 10 Message Pending Bit Allocation User s Manual 15 25 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller The location of a pending bit is defined by two demultiplexers selecting the number k of the MSPNDk registers 1 bit demux and the bit location within the corresponding MSPNDKk register 5 bit demux Allocation Case 1 In this allocation case bit field MCR MPSEL 0000 Here the location selection consists of two parts e The bit 5 of MOIPRn MPN MPN 5 select the number k k 1 0 of a Message Pending Register MSPNDk in which the pending bit will be set e The lower five bits of MOIPRn MPN MPN 4 0 select the bit position 31 0 in MSPNDk for the pending bit to be set Allocation Case 2 In this allocation case bi
38. DATAS3 15 100 DPH 2 3 DPL 2 3 19 8 V1 1 2007 05 Cinfineon E EO 2 5 ETRCR 16 38 EVINCR 16 61 EVINFR 16 61 EVINPR 16 62 EVINSR 16 62 EXICONO 5 21 EXICON1 5 22 F FDCON 12 19 FDRES 12 21 FDSTEP 12 20 FEAH 4 13 FEAL 4 13 G GLOBCTR 8 9 16 33 GLOBSTR 16 35 IENO 5 17 13 13 IEN1 5 18 IENH 14 89 IENL 14 87 INPCRO 16 40 INPH 14 92 INPL 14 90 IRCONO 5 25 IRCON1 5 25 IRCON2 5 27 IRCONS 5 27 IRCON4 5 28 ISH 14 80 ISL 14 79 ISRH 14 86 ISRL 14 85 ISSH 14 84 ISSL 14 83 User s Manual XC886 888CLM L LCBR 16 63 M MCMCTR 14 78 MCMOUTH 14 77 MCMOUTL 14 75 MCMOUTSH 14 74 MCMOUTSL 14 73 MD4 10 9 MDUCON 10 11 MDUSTAT 10 13 MDx x 0 5 10 9 MISC_CON 3 9 MODCTRH 14 68 MODCTRL 14 67 MODPISEL 5 23 8 7 12 23 17 11 MODPISEL1 5 23 12 23 17 11 MODPISEL2 13 8 13 20 MODSUSP 9 4 13 22 14 27 MR4 10 10 MRx x 0 5 10 9 N NMICON 5 19 NMISR 5 30 O OSC_CON 7 17 8 9 P PO_ALTSELO 6 19 PO_ALTSEL1 6 19 PO_DATA 6 17 PO_DIR 6 17 PO_OD 6 18 PO_PUDEN 6 19 PO_PUDSEL 6 18 P1_ALTSELO 6 26 P1_ALTSEL1 6 26 P1_DATA 6 24 P1_DIR 6 24 19 9 V1 1 2007 05 XC886 888CLM Cinfineon P1_ OD 6 25 P1_PUDEN 6 26 P1 PUDSEL 6 25 P2 DATA 6 30 P2 DIR 6 30 P2 PUDEN 6 31 P2 PUDSEL 6 31 P3_ ALTSELO 6 38 P3_ ALTSEL1 6 38 P3_ DATA 6 36 P3 DIR 6 36 P3 OD 6 37 P3_ PUDEN 6 38 P3_ PUDSEL 6 37 P4 ALTSELO 6 45 P4 ALTSEL1 6 45 P4 DATA 6 43 P4 DIR 6 43 P4 OD 6 44 P4 P
39. FDCON FDEN 1 or the output of the prescaler f if the fractional divider is disabled FDEN 0 For baud rate generation the fractional divider must be configured to fractional divider mode FDCON FDM 0 This allows the baud rate control run bit BCON R to be used to start or stop the baud rate timer At each timer underflow the timer is reloaded with the 8 bit reload value in register BG and one clock pulse is generated for the serial channel Enabling the fractional divider in normal divider mode FDEN 1 and FDM 1 stops the baud rate timer and nullifies the effect of bit BCON R Register BG is a dual function Baud rate Generator Reload register Reading from BG returns the timer s contents while writing to BG causes an auto reload of its contents into the baud rate timer if BCON R 1 If BCON R 0 at the time a write operation to BG User s Manual 12 11 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces occurs the auto reload action will be delayed until the first instruction cycle after setting BCON R Fractional Divider 3 Bit Reload Value Xt 0 7 FDEN amp FDM V Adder f N 0 o 0 FDRES MOD overflo FDEN f Figure 12 3 Baud rate Generator Circuitry The baud rate fer value is dependent on the following parameters e Input clock foo x Prescaling factor 22 defined by bit field BRPRE in register
40. Object Transfer Transmit Receive CAN Error LECINP List Length Error List Object Error ALERT NSRx NSRx Frame Counter Overflow Event CFCINP MultiC AN _Can_interrupts Figure 15 5 CAN Node Interrupts User s Manual 15 12 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 4 Message Object List Structure This section describes the structure of the message object lists in the MultiCAN module 15 1 4 1 Basics The message objects of the MultiCAN module are organized in double chained lists where each message object has a pointer to the previous message object in the list as well as a pointer to the next message object in the list The MultiCAN module provides eight lists Each message object is allocated to one of these lists In the example in Figure 15 6 the three message objects 3 5 and 16 are allocated to the list with index 2 List Register LIST2 PPREV 5 PPREV 5 PPREV 16 PNEXT 16 PNEXT 3 PNEXT 3 Message Message Message Object 5 Object 16 Object 3 Register LIST2 MultiC AN_list_basics Figure 15 6 Example Allocation of Message Objects to a List Bit field LIST BEGIN points to the first element in the list object 5 in the example and bit field LIST END points to the last element in the list object 3 in the example The number of elements in the list is indicated by bit field LIST SIZE SIZE number of list e
41. PAGE Page Register Type we o w Pw Pw Popara __ Reset OOy BitField P7 Pe Ps P4 Ps P2 Pi Po AA Po DIR n pden OO Et Fea N A O O PI_DATA Reset 00H BitFied P7 Pe Ps Pa Pa Pe P Po a PLDIR eat pore pr re ee Type ow ow ow ow ow Sow rw rw P5_DATA Reset 004 BitField P7 Pe Ps Pa Pa Po Pi Po eee ESE aE eee AAS P5 DIR Reset BitFied P7 Pe PS P4 P P5 Direction Register type rw ow w ow P2 DATA Reset fi ae P2 Data Register ow w es P2 DIR Reset 7 pe P5 P P2 Direction Register wel ow w P3_DATA Reset fo ps e P3 Data Register we wlw P3_DIR _ Reset 7 Pe 5 P wel wwr v ce mS wy ow ow e AEE w iw we P3 Direction Register rom Type P4 DATA Reset Bit Field P4 Data Register rm Type P4 DIR Reset 00 Bit Field P4 Direction Register User s Manual 3 27 V1 1 2007 05 Memory Organization V 1 2 TEREN TEREN Infineon Table 3 8 XC886 888CLM Memory Organization Port Register Overview cont d Addr RegisterName Bt 7 6 5 4 3 2 1 oO ae eae tet metre Jaroa e e R e a e RMAP 0 PAGE 1 PO_PUDSEL PO Pull Up Pull Down Select Register PO_PUDEN PO Pull Up Pull Down Enable Register P1_PUDSEL P1 Pull Up Pull Down Select Register P1_PUDEN P1 Pull Up Pull Down Enable Register P5 PUDSEL P5 Pull Up Pull Down Select Register P5 PUDEN P5
42. Receive Enable 0 Message object n is not enabled for frame reception 1 Message object n is enabled for frame reception RXEN is only evaluated for receive acceptance filtering 15 81 V1 1 2007 05 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Field Description TXRQ Transmit Request 0 No transmission of message object n is requested 1 Transmission of message object n on the CAN bus is requested The transmit request becomes valid only if TXRQ TXENO TXEN1 and MSGVAL are set TXRQ is set by hardware if a matching remote frame has been received correctly TXRQ is reset by hardware if message object n has been transmitted successfully and NEWDAT is not set again by software TXENO Transmit Enable 0 0 Message object n is not enabled for frame transmission 1 Message object n is enabled for frame transmission Message object n can be transmitted only if both bits TXENO and TXEN1 are set The user may clear TXENO in order to inhibit the transmission of a message that is currently updated or to disable automatic response of remote frames TXEN1 10 rh Transmit Enable 1 0 Message object n is not enabled for frame transmission 1 Message object n is enabled for frame transmission Message object n can be transmitted only if both bits TXENO and TXEN1 are set TXEN1 is used by the MultiCAN module for selecting the active message object in the transmit FIFOs User s Manual 15 82 V1 1 2007 05 M
43. T12 in edge aligned mode Bit CTM 0 The count direction is set to counting up CDIR 0 The counter is reset to zero if a period match is detected and the T12 shadow register transfer takes place if STE12 1 T12 in center aligned mode Bit CTM 1 e The count direction is set to counting up CDIR 0 if a one match is detected while counting down e The count direction is set to counting down CDIR 1 if a period match is detected while counting up e If STE12 1 shadow transfer takes place when aperiod match is detected while counting up aone match is detected while counting down The timer T12 prescaler is reset when T12 is not running to ensure reproducible timings and delays User s Manual 14 4 V1 1 2007 05 CCU6B V 1 0 Cinfine on XC886 888CLM Capture Compare Unit 6 14 1 1 3 Switching Rules Compare actions take place in parallel for the three compare channels Depending on the count direction the compare matches have different meanings In order to get the PWM information independent of the output levels two different states have been introduced for the compare actions the active state and the passive state Both these states are used to generate the desired PWM as a combination of the control by T13 the trap control unit and the multi channel control unit If the active state is interpreted as a 1 and the passive state as a 0 the state information is combined with a logical AND function e acti
44. Type Description BM 3 0 rw Data Width Selection 0000 Reserved Do not use this combination 0001 0111 Transfer Data Width is 2 8 bits lt BM gt 1 Note BM 3 is fixed to 0 HB 4 rw Heading Control 0 Transmit Receive LSB First 1 Transmit Receive MSB First PH 5 rw Clock Phase Control 0 Shift transmit data on the leading clock edge latch on trailing edge 1 Latch receive data on leading clock edge shift on trailing edge PO rw Clock Polarity Control 0 Idle clock line is low leading clock edge is low to high transition 1 Idle clock line is high leading clock edge is high to low transition LB 7 rw Loop Back Control 0 Normal output 1 Receive input is connected with transmit output half duplex mode User s Manual 12 46 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces CONH Control Register High Reset Value 00 7 6 5 4 3 2 1 0 rw rw r rw rw rw rw rw Field CELT Description TEN k Error Interrupt Enable Transmit error interrupt is disabled Transmit error interrupt is enabled REN Receive Error Enable 0 Receive error interrupt is disabled Receive error interrupt is enabled h PEN Phase Error Enable 0 Phase error interrupt is disabled 1 Phase error interrupt is enabled x BEN Baud Rate Error Enable 0 Baud rate error interrupt is disabled 1 Baud rate error interrupt is enabled x AREN Automatic Reset Enable 0 No additional action upon a baud rate error 1 The
45. bit TRPS 0 as soon as bit TRPF is reset by software after the input CTRAP becomes inactive TRPF is not cleared by Field Bits Type Description hardware Bit TRPS is automatically cleared by hardware if bit TRPF 0 and if the TRPMO 1 0 rw Trap Mode Control Bits 1 0 TRPM1 These two bits define the behavior of the selected outputs when leaving the trap state after the trap condition has become inactive again A synchronization to the timer driving the PWM pattern permits to avoid unintended short pulses when leaving the trap state The combination TRPM1 TRPMO leads to 00 The trap state is left return to normal operation according to TRPM2 when a zero match of T12 while counting up is detected synchronization to 112 01 The trap state is left return to normal operation according to TRPM2 when a zero match of T13 is detected synchronization to T13 10 reserved 11 The trap state is left return to normal operation according to TRPM2 immediately without any TRPM2 2 rw synchronization condition according to TRPMO 1 is detected synchronization to 112 or T13 Trap Mode Control Bit 2 0 The trap state can be left return to normal 0 7 3 r Reserved Returns 0 if read should be written with O User s Manual 14 70 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 TRPCTRH Trap Control Register High Reset Value 00 7 6 5 4 3 2 1 0 TRP bhii EN TRPEN PEN 13 rw rw rw Field Bit
46. by the bit field NSRx LEC The data consistency of an incoming frame is verified by checking the associated CRC field When an error has been detected the Last Error interrupt request is generated and the error code is indicated by the bit field NSRx LEC Furthermore an error frame is generated and transmitted on the CAN bus After decomposing a faultless frame into identifier and data portion the received information is transferred to the message buffer executing remote and data frame handling interrupt generation and status processing 15 1 3 3 Error Handling Unit The Error Handling Unit of a CAN node x is responsible for the fault confinement of the CAN device Its two counters the Receive Error Counter NECNTx REC and the Transmit Error Counter NECNTx TEC are incremented and decremented by commands from the Bit Stream Processor If the Bit Stream Processor itself detects an error while a transmit operation is running the Transmit Error Counter is incremented by 8 An increment of 1 is used when the error condition was reported by an external CAN node via an error frame generation For error analysis the transfer direction of the disturbed message and the node recognizing the transfer error are indicated for the respective CAN node x in register NECNTx According to the values of the error counters the CAN node is set into the states error active error passive and bus off The CAN node is in error active sta
47. clearing TXRQ time stamp update message interrupt etc within the old context of the object can occur after the message object becomes valid again but within a new context NEWDAT When the content of a message object has been transferred to the internal transmit buffer of the CAN node bit MOSTATn NEWDAT New Data is cleared by hardware to indicate that the transmit message object data is no longer new When the transmission of the frame is successful and NEWDAT is still cleared if no new data has been copied into the message object meanwhile TXRQ Transmit Request Is cleared automatically by hardware If however the NEWDAT bit has been set again by the software because a new frame is to be transmitted TXRQ is not cleared to enable the transmission of the new data User s Manual 15 31 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Obj wins transmit acc filtering RTSEL 1 D SGVAL amp TXRQ amp TXENO amp TXEN1 1 continously during message Request Transmission of internal buffer on CAN bus no Transmission Successful Done yes no MSGVAL amp RTSEL 1 yes no TXRQ 0 lt lt Newoat 1 O 1 G time milestones Issue Interrupt Done Figure 15 12 Transmission of a Message Object msgobj_transmit User s Manual 15 32 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network Mult
48. default Open drain mode output is actively driven only for O state P1_PUDSEL Port 1 Pull Up Pull Down Select Register Reset Value FF 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn Up Pull Down Select Port 1 Bit n n 0 7 Pull down device is selected Pull up device is selected default User s Manual 6 25 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports P1 PUDEN Port 1 Pull Up Pull Down Enable Register Reset Value FF 7 6 5 4 3 2 1 0 EARLIER aa a rw rw rw rw rw rw rw rw Field Description Pn oa Up Pull Down Enable at Port 1 Bit n n 0 7 Pull up or Pull down device is disabled Pull up or Pull down device is enabled default P1 _ALTSELn n 0 1 Port 1 Alternate Select Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn Pin Output Functions n 0 7 Configuration of Px_ALTSELO Pn and Px ALTSEL1 Pn for GPIO or alternate settings 00 Normal GPIO 10 Alternate Select 1 01 Alternate Select 2 11 Alternate Select 3 User s Manual 6 26 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 5 Port 2 Port P2 is an 8 bit general purpose input only port The registers of P2 are summarized in Table 6 7 Table 6 7 Port 2 Registers Register Short Name Register Full Name P2 DATA Port 2 Data Register P2 DIR Port 2 Direction Register P2 PUDSEL Port 2 Pull Up Pull Down Select Register P2 PUDEN
49. detect PLL core N 1 OSCDISC NDIV VCOBYP Figure 7 6 CGU Block Diagram User s Manual 7 11 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management 7 3 1 1 Functional Description When the XC886 888 is powered up the PLL is disconnected from the oscillator and will run at its VCO base frequency After the EVR Is stable provided the oscillator is running the PLL will be connected and the continuous lock detection will ensure that the PLL Starts functioning Once reset has been released bit OSCR will be set to 1 if the oscillator is running and bit LOCK will be set to 1 if the PLL is locked Loss of Lock Operation lf the PLL is not the system s clock source VCOBYP 1 when the loss of lock is detected only the lock flag is reset PLL_CON LOCK 0 and no further action is taken This allows the PLL parameters to be switched dynamically lf PLL loses its lock to the oscillator the PLL Loss of Lock NMI flag NMISR FNMIPLL is set and an NMI request to the CPU is activated if PLL NMI is enabled NMICON NMIPLL In addition the LOCK flag in PLL_CON is reset The oscillator must be disconnected immediately via the NMI routine upon PLL Loss of Lock to force PLL to run in VCO base frequency Emergency routines can be executed with the XC886 888 clocked with this base frequency The XC8
50. e Data Area Fixed size of 6 bytes which represent the data of the block For Header Block one byte will indicate the Mode selected and 5 bytes for Mode data For Data and EOT Blocks data area consists of the program code e Checksum The Programming Checksum or LIN Checksum contains the non inverted or inverted eight bit sum with carry over NAD Block Type and Data Area Eight bit sum with carry equivalent to sum all values and subtract 255 every time the sum is greater or equal to 256 which is not the same as modulo 255 or modulo 256 Diagnostic LIN frame always uses classic checksum where checksum calculation is over the data bytes only It is used for communication with LIN 1 3 slaves The Classic Checksum contains the inverted eight bit sum with carry over all data bytes A non LIN standard checksum also Known as Programming Checksum is implemented to differentiate an XC886 888 Programming LIN frame from a normal LIN frame and to allow other slaves non Programming which are on the LIN bus to ignore this Programming frame XC886 888 supports both the LIN Classic Checksum and Programming Checksum where Programming Checksum contains the eight bit sum with carry over all 8 data bytes User s Manual 18 4 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader An illustration on the Programming Checksum and LIN Checksum calculation is provided in Table 18 3 for data of 4A 55 93 and E5
51. e Multiprocessor communication e Interrupt generation on the completion of a data transmission or reception LIN Features e Master and slave mode operation SSC Features e Master and slave mode operation Full duplex or half duplex operation e Transmit and receive buffered e Flexible data format Programmable number of data bits 2 to 8 bits Programmable shift direction LSB or MSB shift first Programmable clock polarity idle low or high state for the shift clock Programmable clock data phase data shift with leading or trailing edge of the shift clock e Variable baud rate e Compatible with Serial Peripheral Interface SPI e Interrupt generation On a transmitter empty condition On a receiver full condition On an error condition receive phase baud rate transmit error User s Manual 12 1 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 1 UART The UART provides a full duplex asynchronous receiver transmitter i e it can transmit and receive simultaneously It is also receive buffered i e it can commence reception of a second byte before a previously received byte has been read from the receive register However if the first byte still has not been read by the time reception of the second byte is complete one of the bytes will be lost Note The term UART is used to represent the serial port in general and is applicable to both UART and UART1 m
52. gt gt Tm i 0 N Output GPO P4 DATA P3 EXF21 1 Timer 21 COUT63 2 CCU6 gt gt gt Tm F 4 4 44 P User s Manual 6 40 V1 1 2007 05 Parallel Ports V 1 0 Infineon XC886 888CLM i Parallel Ports Table 6 12 Port 4 Input Output Functions cont d Port Pin Input Output P4 4 Input Connected Signal s From to Module P4 DATA P4 CCPOSO_3 CCU6 TO O Timer 0 GP gt gt gt Tm e 4 4 44 P EN at gt gt gt Tm e 4 4 OINI Output GPO P4 DATA P4 CC61 4 CCU6 gt gt gt Tm P e H OINI Input GPI P4 DATA P5 CCPOS1_3 CCU6 T1_0 Timer 1 Output GPO P4 DATA P5 COUT61_ 2 CCU6 gt gt gt Tm e 4 4 44 P P4 6 Input GPI P4 DATA P6 CCPOS2 3 CCU6 T2_0 Timer 2 gt gt gt Tm i 0 N Output GPO P4 DATA P6 CC62 2 CCU6 gt gt gt Tm F 4 4 44 P User s Manual 6 41 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Table 6 12 Port 4 Input Output Functions cont d Port Pin haan gt P4 7 Input ALT1 ALT2 ALT3 Output ALT1 ALT2 ALT3 1 Pins P4 2 P4 4 to P4 7 are only available only in XC888 Connected Signal s From to Module P4 DATA P7 CTRAP 3 CCU6 P4 DATA P7 COUT62_2 CCU6 User s Manual 6 42 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 7 2 Register Descripti
53. gt Tm e 4 4 44 P gt gt gt Tm P e H OINI Input GPI P3_DATA P5 Output GPO P3_ DATA P5 COUT62_0 CCU6 EXF21_ 0 Timer 21 TXDCO_1 MultiCAN Input GPI P3_DATA P6 CTRAP_O CCU6 gt gt gt Tm e 4 4 44 P a O gt gt gt Tm i 0 N Output GPO P3 DATA P6 Se O1 wil wil Tm F Tm e 4 4 44 H P 0 N BE User s Manual 6 34 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Table 6 10 Port 3 Input Output Functions cont d Port Pin Input Output P3 7 Input GPI ALT1 ALT2 ALT3 Output GPO P3 _DATA P7 ALT1 COUT63_0 CCU6 ALT2 ALT3 Connected Signal s From to Module P3 _DATA P7 EXINT4 External interrupt 4 User s Manual 6 35 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 6 2 Register Description P3_ DATA Port 3 Data Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field mS Description Pn Ad 3 Pin n Data Value n 0 7 Port 3 pin n data value O default Port 3 pin n data value 1 P3_DIR Port 3 Direction Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn 3 Pin n Direction Control n 0 7 Direction is set to input default Direction is set to output User s Manual 6 36 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports P3 OD P
54. opcode executes the MOVC instruction When TRAP_EN is 1 the A5H opcode executes the software break instruction TRAP which switches the CPU to debug mode for breakpoint processing EO Extended Operation Register Reset Value 00 7 6 5 4 3 2 1 0 8 tare orto r rw r rw Field Bits Type Description DPSELO rw Data Pointer Select 0 DPTRO is selected 1 DPTR1 is selected TRAP_EN 4 rw TRAP Enable 0 Select MOVC DPTR A 1 Select software TRAP instruction 0 3 1 Ir Reserved 7 5 Returns 0 if read should be written with O User s Manual 2 5 V1 1 2007 05 Processor Architecture V 1 0 Cinfine on XC886 888CLM Processor Architecture 2 2 7 Power Control PCON The CPU has two power saving modes idle mode and power down mode The idle mode can be entered via the PCON register In idle mode the clock to the CPU is Stopped while the timers serial port and interrupt controller continue to run using a half speed clock In power down mode the clock to the entire CPU is stopped PCON Power Control Register Reset Value 00 7 6 5 4 3 2 1 0 r rw rw r rw rw Field Bits Type Description IDLE rw Idle Mode Enable 0 Do not enter idle mode 1 Enter idle mode GFO General Purpose Flag Bit 0 GF1 General Purpose Flag Bit 1 0 1 r Reserved 6 4 Returns 0 if read should be written with 0 2 3 Instruction Timing For memory access without wait state a CPU machine cycle comprises two input clock periods referred t
55. ow we ow IEN1 Reset 00y Bit Field Pee ats oe Te ESSC EADC Interrupt Enable Register 1 o w tw fw we we IP1 Reset 00 Bit Field ae oe Bed fe PSSC 2 Interrupt Priority 1 Register Fie ow IPH1 Reset 00y Bit Field PCCIP PCCIP E En a ae Interrupt Priority 1 High Register EN EN EE a Type 3 5 5 2 MDU Registers The MDU SFRs can be accessed in the mapped memory area RMAP 1 Table 3 4 MDU Register Overview Addr RegisterName Bit 7 6 5 4 3 2 1 0 BiH MDUCON Reset 00y Bit Field RSEL a OPCODE MDU Control Register a aoo B24 MDO Reset 00 Bit Field DATA Vo operand eoster type mw O B2y MRO Reset 00y Bit Field DATA MDU Result Register 0 h B34 MD1 Reset 004 Bit Field DATA MDU Operand Register 1 i User s Manual 3 22 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization Table 3 4 MDU Register Overview cont d i Register Name 3H MR1 Reset 00y Bit Field MDU Result Register 1 Type MD2 Reset 00 Bit Field MDU O d Register 2 perand Register Type 4y MR2 Reset 00 Bit Field MDU Result Register 2 Type SH MD3 Reset 00y Bit Field MDU Operand Register 3 Type SH MR3 Reset 004 Bit Field MDU Result Register 3 Type MD4 Reset 00 Bit Field MDU O d Register 4 perand Register Type U L 6y MR4 Reset 00y Bit Field MDU Result Register 4 Type 74H MD5 Reset 004 Bit Field MDU
56. read view two write views The first address for read and write access is the address given for CRCR1 The second address for write actions is given for CRPR1 A write operation to CRPR1 leads to a data write to the bits in CRCR1 with an automatic load event one clock cycle later CRCR1 Conversion Request Control Register 1 CA Reset Value 00 7 6 9 4 3 2 1 0 Se te om om rwh rwh rwh rwh r Field Description CHx C Channel Bit x x 4 7 Each bit corresponds to one analog channel the channel number x is defined by the bit position in the register The corresponding bit x in the conversion request pending register will be overwritten by this bit when the load event occurs Os The analog channel x will not be requested for conversion by the parallel request source 1 The analog channel x will be requested for conversion by the parallel request source 0 3 0 Reserved Returns 0 if read should be written with 0 User s Manual 16 49 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Register CRPR1 contains bits that request a conversion of the corresponding analog channel The bits in this register have only a read view A write operation to this address leads to a data write to CRCR1 with an automatic load event one clock cycle later anon Request Pending Register 1 CB Reset Value 00 7 6 5 4 3 2 1 0 voor om om ome O wh rwh rwh rwh r r Field Bits Type Description CHPx X rwh Channel
57. target of the operation defined by bit OP If OP 10 the contents of PAGE are saved in STx before being Field Bits Type Description rw Ww overwritten with the new value If OP 11 the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STO is selected 01 ST1 is selected 10 ST2 is selected 11 STS is selected User s Manual 16 31 V1 1 2007 05 ADC V 1 0 Cinfineon ee Description Operation Field OP 7 6 OX 0 User s Manual ADC V 1 0 XC886 888CLM Analog to Digital Converter Manual page mode The value of STNR is ignored and PAGE is directly written New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the former contents of PAGE are saved in the storage bit field STx indicated by STNR Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR eee riem 0 if read should be written with 0 16 32 V1 1 2007 05 Cinfin eon XC886 888CLM Analog to Digital Converter 16 7 Register Description This section describes all the registers which are associated with the functionalities of the ADC module 16 7 1 General Function Registers Register GLOBCTR contains bits that control the analog converter and the conversi
58. the ROM is protected at all times and BSL mode 6 is used only to block external access to the device However unlike the Flash device it is not possible to disable the memory protection of the ROM device Here entering BSL mode 6 will result in a protection error Note If ROM read out protection is enabled only read instructions in the ROM memory can target the ROM contents User s Manual 3 8 V1 1 2007 05 Memory Organization V 1 2 Cinfin eon XC886 888CLM Memory Organization Although no protection scheme can be considered infallible the XC886 888 memory protection strategy provides a very high level of protection for a general purpose microcontroller 3 4 2 Miscellaneous Control Register The MISC_CON register contains the DFLASHEN bit to enable the erase of a D Flash bank This bit has no effect if the Flash hardware protection is not enabled or protection mode 1 is enabled MISC CON Miscellaneous Control Register Reset Value 00 7 6 5 4 3 2 1 0 DFLASH EN r rwh Field Description DFLASHEN Bie m D Flash Bank Enable 0 D Flash bank cannot be erased 1 D Flash bank can be erased This bit is reset by hardware after each D Flash erase operation Note Superfluous setting of this bit has no adverse effect on the XC886 888 system operation 0 7 1 Reserved Returns 0 if read should be written with 0 User s Manual 3 9 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization 3 5 Sp
59. the device is put into the hardware reset state When the wake up source and wake up type have been selected prior to entering power down mode the power down mode can be exited via EXINTO pin RXD pin Bits MODPISEL URRIS and MODPISEL URRISH are used to select one of the three RXD inputs and bit MODPISEL EXINTOIS is used to select one of the two EXINTO inputs If bit WKSEL was set to 1 before entering power down mode the system will execute a reset sequence similar to the power on reset sequence Therefore all port pins are put into their reset state and will remain in this state until they are affected by program execution If bit WKSEL was cleared to 0 before entering power down mode a fast wake up sequence is used The port pins continue to hold their state which was valid during power down mode until they are affected by program execution The wake up from power down without reset undergoes the following procedure 1 In power down mode EXINTO pin RXD pin must be held at high level 2 Power down mode is exited when EXINTO pin RXD pin goes low for at least 100 ns 3 The main voltage regulator is switched on and takes approximately 150 us to become stable 4 The on chip oscillator and the PLL are started Typically the on chip oscillator takes approximately 500 ns to stabilize The PLL will be locked within 200 us after the on chip oscillator clock is detected for stable nominal frequency 5 Subsequently the FLASH will enter
60. the selected edge has been detected These bits are set and reset according to the 112 and T13 switching rules CCPOSx Sampled Hall Pattern Bits x 0 1 2 Bits CCPOSx indicate the value of the input Hall pattern that has been compared to the current and expected value The value is sampled when the event amd Hall compare ready occurs The input CCPOSx has been sampled as 0 The input CCPOSx has been sampled as 1 0 leone lo O if read should be written with 0 User s Manual 14 55 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 CMPSTATH Compare State Register High Reset Value 00 7 6 5 4 3 2 1 0 T13 C C CC C CC C CC IM OUT63PS OUT62PS 62PS OUT61PS 61PS OUT60PS 60PS rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description CC6xPS Passive State Select for Compare Outputs x 0 1 2 Bits CC6xPS COUT6xPS select the state of the corresponding compare channel which is considered COUT6xPS to be the passive state During the passive state the x 0 1 2 3 passive level defined in register PSLR is driven by the output pin Bits CC6xPS COUT6xPS x 0 1 2 are related to T12 bit COUT63PS is related to T13 0 The corresponding compare output drives passive level while CC6xST is 0 1 The corresponding compare output drives passive level while CC6xST is 1 These bits have shadow bits and are updated in parallel to the capture compare registers of 112 and T13 respec
61. x 1 0 Table 15 4 shows how bits and bit fields must be programmed for the required I O functionality of the CAN I O lines Table 15 4 CAN I O Control Selection Port Lines PISEL Register Bit Input Output Control I O Register Bits P1_DIR PO 0p Input P1_DIR P1 1 Output P1_ALTSELO P1 1B P1_ALTSEL1 P1 1B P3_DIR P4 0 Input P3_DIR P5 1 Output P3 ALTSELO P5 1 P3 ALTSEL1 P5 1 P1 DIR P6 0 Input P1_DIR P7 1 Output P1_ALTSELO P7 1 P1_ALTSEL1 P7 1 P4_DIR PO 0p Input P4_DIR P1 1 Output P4 ALTSELO P1 1B P4 ALTSEL1 P1 1B PO_DIR P1 Op Input PO_DIR P2 1 Output PO ALTSELO P2 1B PO_ALTSEL1 P2 1B P3_DIR P2 0k Input P1 0 RXDCO_0 NPCRO RXSEL 000 P1 1 TXDCO_0 P3 4 RXDCO_1 NPCRO RXSEL 001 P3 5 TXDCO_1 P1 6 RXDCO_ 2 NPCRO RXSEL 010 P1 7 TXDCO_ 2 P4 0 RXDCO_3 NPCRO RXSEL 011 P4 1 TXDCO_3 PO 1 RXDC1_0 NPCR1 RXSEL 000 PO 2 TXDC1_0 P3 2 RXDC1_ 1 NPCR1 RXSEL 001 User s Manual 15 43 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Table 15 4 CAN I O Control Selection cont d cont d Port Lines PISEL Register Bit Input Output Control I O Register Bits P3 3 TXDC1_1 P3_DIR P3 1 Output P3_ALTSELO P3 1B P3_ALTSEL1 P3 1B P1 4 RXDC1_3 NPCR1 RXSEL 001 P1_DIR P4 0 Input P1 3 TXDC1_ 3 P1_DIR P3 1 Output P1 ALTSELO P3 1B P1 ALTSEL1 P3 1B 15 1 12 Low Power Mode If the MultiCAN fun
62. 0 WDT NMI is disabled 1 WDT NMI is enabled NMIPLL PLL Loss of Lock NMI Enable 0 PLL Loss of Lock NMI is disabled 1 PLL Loss of Lock NMI is enabled NMIFLASH 2 rw Flash NMI Enable 0 Flash NMI is disabled 1 Flash NMI is enabled NMIOCDS 3 rw OCDS NMI Enable 0 OCDS NMI is disabled 1 Reserved NMIVDD 4 rw VDD Prewarning NMI Enable 0 VDD NMI is disabled 1 VDD NMI is enabled User s Manual 5 19 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System Field Bits Type Description NMIVDDP 5 rw VDDP Prewarning NMI Enable 0 VDDP NMI is disabled 1 VDDP NMI is enabled Note When the external power supply is 3 3 V the user must disable NMIVDDP NMIECC rw ECC NMI Enable 0 ECC NMI is disabled 1 ECC NMI is enabled Reserved Returns 0 if read should be written with 0 User s Manual 5 20 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System 5 6 2 External Interrupt Control Registers The seven external interrupts EXT _INT 6 0 are driven into the XC886 888 from the ports External interrupts can be positive negative or double edge triggered Registers EXICONO and EXICON1 specify the active edge for the external interrupt Among the external interrupts external interrupt O and external interrupt 1 can be selected to bypass edge detection for direct feed through to the core This signal to the core can be further programmed to either low level or negative transition activ
63. 1 e sinh v cosh v sart w sart w 0 25 w 0 25 wt ef nw acosh w In w sart 1 w2 asinh w In w sart 1 w Usage Notes For solving the respective functions user must initialize the CORDIC data X Y and Z with meaningful initial values within domain of convergence to ensure result convergence The useful domain listed in Table 11 2 covers the supported domain of convergence for the CORDIC algorithm and excludes the not meaningful range s for the function For details regarding the supported domain of convergence refer to Chapter 11 2 4 1 For result data accuracy refer to Chapter 11 2 6 Function limitations must be considered e g setting initial X 0 for atan Y X is not meaningful Violations of such function limitations may yield incoherent CORDIC result data All data inputs are processed and handled as twos complement Only exception is user option for X result data only to be read as unsigned value The only case where the result data is always positive and larger than the initial data is X result data only in circular vectoring mode therefore the user may want to use the MSB bit as data bit instead of sign bit By setting X_USIGN 1 X result data will be processed as unsigned data For circular and hyperbolic functions and due to the corresponding fixed LUT the Z data is always handled as signed integer S19 accessible as S15 The LUTs contain scaled integer values S19 of atan 2
64. 1 Cinfin eon XC886 888CLM CORDIC Coprocessor 11 2 Functional Description The following sections describe the function of the CORDIC Coprocessor 11 2 1 Operation of the CORDIC Coprocessor The CORDIC Coprocessor can be used for the circular trigonometric linear multiply add divide add or hyperbolic function in either rotation or vectoring mode The modes are selectable by software via the CD_CON control register Initialization of the kernel data register is enabled by clearing respective KEEP bits of the CD_STATC If ST_MODE 1 writing 1 to bit ST starts a new calculation Otherwise by default where ST_MODE 0 a new calculation starts after a write access to register CD CORDXL Each calculation involves a fixed number of 16 iterations Bit BSY is set while a calculation is in progress to indicate busy status It is cleared by hardware at the end of a calculation As the first step on starting a CORDIC calculation provided the corresponding KEEP bits are not set the initial data is loaded from the data registers CD_CORDxL and CD_CORDxH to the internal kernel data registers During the calculation the kernel data registers always hold the latest intermediate data On completion of the calculation they hold the result data The data registers CD_CORDxL and CD_CORDxH function as shadow registers which can be written to without affecting an ongoing calculation Values are transferred to the kernel data registers only on va
65. 1 2007 05 Cinfin eon XC886 888CLM Table of Contents Page 15 1 4 1 ceee 2estanexeeeeses oyee eee eases oe eee ae E 15 13 15 1 4 2 List of Unallocated Elements 0 0 0 000 eee eee 15 14 15 1 4 3 Connection to the CAN Nodes 0 000 e eee eee 15 14 15 1 4 4 List Command Panel 0 002 e eee ee eee 15 15 15 1 5 CAN Node Analysis Features 0 0 00 cee ees 15 18 15 1 5 1 Analyze Mode ccc eee eee 15 18 15 1 5 2 Loop Back Mode 0 15 18 15 1 5 3 Bit Timing Analysis 0 0 0c eee 15 19 15 1 6 Message Acceptance Filtering 2 00 eee 15 21 15 1 6 1 Receive Acceptance Filtering 2 0 00 cece eee ees 15 21 15 1 6 2 Transmit Acceptance Filtering 0 0 00 cee eee eee 15 22 15 1 7 Message Postprocessing 0 00 ce ee eee 15 23 15 1 7 1 Message InterruptS 0 cc ees 15 23 15 1 7 2 Pending Messages 00 c cece eee tees 15 25 15 1 8 Message Object Data Handling 2c eee eee ees 15 27 15 1 8 1 Frame Reception 0 0 0 cc eee 15 27 15 1 8 2 Frame Tra nsMmisSSiON 2 0000 ce eee 15 30 15 1 9 Message Object Functionality 0 0 00 cee eee eee 15 33 15 1 9 1 Standard Message Object 0 00 0 c eee ee eee 15 33 15 1 9 2 Single Data Transfer Mode 0 00 cece eee eens 15 33 15 1 9 3 Single Transmit Trial 0 0 0 0 ees 15 33 15 1 9 4 Message Object FIFO Structure
66. 12 16 The maximum baud rate that can be achieved when using a module clock of 24 MHZ is 12 MBaud in master mode with lt BR gt 0000 or 6 MBaud in slave mode with lt BR gt 0001 Table 12 6 lists some possible baud rates together with the required reload values and the resulting deviation errors assuming a module clock frequency of 24 MHZ User s Manual 12 39 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces Table 12 6 Typical Baud Rates of the SSC faw cik 24 MHz FFFF 183 11 Baud 0 0 Reload Value Deviation 183 11 Baud User s Manual 12 40 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 3 1 7 Error Detection Mechanisms The SSC is able to detect four different error conditions Receive Error and Phase Error are detected in all modes Transmit Error and Baud Rate Error apply only to slave mode When an error is detected the respective error flag is can be set and an error interrupt request will be generated by activating the Error Interrupt Request line EIR see Figure 12 17 The error interrupt handler may then check the error flags to determine the cause of the error interrupt The error flags are not reset automatically but rather must be cleared by software after servicing This allows servicing of error conditions to be done via interrupt if their enable bits are set or via polling by software if their enable bits are not set
67. 13 UART1 Register Overview Addr Register Name Bt 7 6 5 4 3 2 41 0 Baud Rate Timer Reload FDEN Fractional Divider Control cae FDSTEP Reset 001 Bit Field STEP Fractional Divider Reload FDRES Reset 00y Bit Field RESULT Fractional Divider Result User s Manual 3 38 V1 1 2007 05 Memory Organization V 1 2 infine on XC886 888CLM Memory Organization 3 5 5 12 SSC Registers The SSC SFRs can be accessed in the standard memory area RMAP 0 Table 3 14 SSC Register Overview Addr Register Name Bt 7 6 5 4 3 2 4 0 RMAP 0 Port Input Select Register Da Type TT om Control Register Low ar ais fee ee SSC_CONL Reset 00 Bit Field Control Register Low Control Register High Control Register High SSC_TBL Reset 00y Bit Field TB VALUE eee tye fw ADH SSC_RBL Reset 00y Bit Field RB_VALUE eee ype SSC_BRL Reset 00 Bit Field BR VALUE Baud Rate Timer Reload Register Low SSC_BRH Reset 00 Bit Field Baud Rate Timer Reload Register High 3 5 5 13 MultiCAN Registers The MultiCAN SFRs can be accessed in the standard memory area RMAP 0 Table 3 15 CAN Register Overview me Control JEEE CAN Address Register Low Pe een n m Reset 00 E h omn wn wh rw ane af a fa User s Manual 3 39 V1 1 2007 05 Memory Organization V 1 2 infine on XC886 888CLM Memory Organization Table 3 15 CAN Register Overview daii Register Name
68. 14 26 14 1 9 Module Suspend Control 0 0 00 ce ee eee 14 27 14 1 10 POM COMMCCHON 6 2244 c bnu eh cana ee adiunds eeeenneanen es heas 14 28 14 2 MeGISIC MAD u4 2 eeiebudebudcdees td ivdeenseebubdisiaua ds 14 32 14 3 Register Description 0 cc ees 14 35 14 3 1 System Registers 0 ee eee ene 14 37 14 3 2 Timer 12 Related Registers 0 0 00 eee ee eee 14 40 14 3 3 Timer 13 Related Registers 0 0 0 cece eee 14 51 14 3 4 Capture Compare Control Registers 00 cee 14 55 14 3 5 Global Modulation Control Registers 0 000 14 67 14 3 6 Multi Channel Modulation Control Registers 14 73 14 3 7 Interrupt Control Registers 0 0 0 0c ees 14 79 15 Controller Area Network MultiCAN Controller 15 1 15 1 MultiCAN Kernel Functional Description 0 20085 15 4 15 1 1 Module Structure 1 naana naa aaa 15 4 15 1 2 ClOCK CONUO s 222 lt c5cctaceehubadsdewsdveg ese eee eds ewe Hee 15 7 15 1 3 CAN Node Control 0 0 ccc eee eee 15 8 15 1 3 1 Bit Timing Unit 0 0 0 eee 15 8 1921 3 2 Bitstream Processor 00 cee eee ee ete eee 15 9 15 1 3 3 Error Handling Unit 0 ee es 15 10 15 1 3 4 CAN Frame Counter 0 0 00 ccc ee ees 15 11 15 1 3 5 CAN Node Interrupts 0 0 0 00 ee ees 15 11 15 1 4 Message Object List Structure 1 0 20 00 eee 15 13 User s Manual 7 V1
69. 16 r Field nm Description 2 0 Receive Select l 0 7 3 31 9 RXSEL selects one out of 8 possible receive inputs The CAN receive signal is performed only through the selected input Note In XC886 888 only specific combinations of RXSEL are available see also Page 15 43 Loop Back Mode 0 Loop Back Mode is disabled 1 Loop Back Mode is enabled This node is connected to an internal virtual loop back CAN bus All CAN nodes which are in Loop Back Mode are connected to this virtual CAN bus so that they can communicate with each other internally The external transmit line is forced recessive in Loop Back Mode Reserved Read as 0 should be written with O User s Manual 15 68 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller The Node Bit Timing Register NBTRx contains all parameters to set up the bit timing for the CAN transfer NBTRx can be written only if bit NCRx CCE is set NBTRx x 0 1 Node x Bit Timing Register Reset Value 0000 0000 31 30 29 28 2 26 25 24 23 22 21 20 19 18 17 16 DGGSGSGT Seeeeeee r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIV8 TSEG2 TSEG1 SJW BRP rw rw rw rw rw Field BRP Type Description gi i W Baud Rate Prescaler The duration of one time quantum is given by BRP 1 clock cycles if DIV8 0 The duration of one time quantum is given by 8 x BRP 1 clock cycles if DIV8 1 rw Re Syn
70. 16 bit timer counter 2 8 bit timer counter with auto reload The timer register TLx is reloaded with a user defined 8 bit value in THx upon overflow 3 Timer 0 operates as two 8 bit timers counters The timer registers TLO and THO operate as two separate 8 bit counters Timer 1 is halted and retains its count even if enabled User s Manual 13 3 V1 1 2007 05 Timers V 1 0 Cinfine on XC886 888CLM Timers 13 1 2 1 Mode 0 Putting either Timer 0 or Timer 1 into mode O configures it as an 8 bit timer counter with a divide by 32 prescaler Figure 13 1 shows the mode 0 operation In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the timer overflow flag TFx The overflow flag TFx can then be used to request an interrupt The counted input is enabled for the timer when TRx 1 and either GATEx 0 or EXINTx 1 setting GATEx 1 allows the timer to be controlled by external input EXINTx to facilitate pulse width measurements TRx is a control bit in the register TCON bit GATEx is in register TMOD The 13 bit register consists of all the 8 bits of THx and the lower 5 bits of TLx The upper 3 bits of TLx are indeterminate and should be ignored Setting the run flag TRx does not clear the registers Mode 0 operation is the same for Timer 0 and Timer 1 TLO THO 5 Bits 8 Bits Interrupt TOS 1 TO Control k i 1 GATEO Y N EXINTO DOA
71. 2 1 The CORDIC Coprocessor expects Z data to be interpreted with this scaling 32768 Inout Z Initial Data Real Z Initial Value in radians x a JI Z Real Z Result Value in radians Result Data x 30768 The CORDIC calculated data includes an inherent gain factor K resulting from the rotation or vectoring The value K is different for each CORDIC function as shown in Table 11 1 Table 11 1 CORDIC Function Inherent Gain Factor for Result Data Function Approximated Gain K Circular 1 64676 Hyperbolic 0 828 Linear 1 User s Manual 11 4 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfine on XC886 888CLM CORDIC Coprocessor 11 2 4 CORDIC Coprocessor Operating Modes Table 11 2 gives an overview of the CORDIC Coprocessor operating modes In this table X Y and Z represent the initial data while X 1 Yina and Zina represent the final result data when all processing is complete and BSY is no longer active The CORDIC equations are Xie H m dy 2 11 4 Var V tx 2 11 5 onan Ge 11 6 Table 11 2 CORDIC Coprocessor Operating Modes and Corresponding Result Data Function Rotation Mode Vectoring Mode di sign zi z 0 di sign yi y0 Circular Xina KIX cos Z Y sin Z MPS Xina K saqrt X Y MPS m 1 Yina KIY cos Z X sin 2 MPS Yina 0 i atan 2 Liina 0 Liina Z atan Y X where K 1 64676 where K 1 64676 For solving cos Z and sin Z set X For solving magn
72. 2 LIN Header Transmission LIN header transmission is only applicable in master mode In the LIN communication a master task decides when and which frame is to be transferred on the bus It also identifies a slave task to provide the data transported by each frame The information needed for the handshaking between the master and slave tasks is provided by the master task through the header portion of the frame The header consists of a break and synch pattern followed by an identifier Among these three fields only the break pattern cannot be transmitted as a normal 8 bit UART data The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes In the LIN communication a slave task is required to be synchronized at the beginning of the protected identifier field of frame For this purpose every frame starts with a sequence consisting of a break field followed by a synch byte field This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field 12 2 2 1 Automatic Synchronization to the Host Upon entering LIN communication a connection is established and the transfer speed baud rate of the serial communication partner host is automatically synchronized in the following steps that are to be included in user software STEP 1 Initialize interface for reception and timer for baud rate measur
73. 4 3 2 1 0 T12PVL rwh Field Bits Type Description T12PVL 7 0 rwh T12 Period Value Low Byte The value T12PV defines the counter value for T12 which leads to a period match On reaching this value the timer T12 is set to zero edge aligned mode or changes its count direction to down counting center aligned mode T12PRH Timer T12 Period Register High Reset Value 00 7 6 5 4 3 2 1 0 T12PVH rwh Field Description T12PVH pis in T12 Period Value High Byte The value T12PV defines the counter value for T12 which leads to a period match On reaching this value the timer T12 is set to zero edge aligned mode or changes its count direction to down counting center aligned mode User s Manual 14 47 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 CC6xRL x 0 1 2 Capture Compare Register for Channel CC6x Low Reset Value 00 7 6 5 4 3 2 1 0 CC6XVL x 0 1 2 rh Field Bits Type Description CC6xVL 7 0 rh Channel x Capture Compare Value Low Byte x 0 1 2 In compare mode the bit fields CC6xV contain the values that are compared to the T12 counter value In capture mode the captured value of T12 can be read from these registers CC6xRH x 0 1 2 Capture Compare Register for Channel CC6x High Reset Value 00 7 6 5 4 3 2 1 0 rh Field Bits Type Description CC6xVH 7 0 rh Channel x Capture Compare Value High Byte x 0 1 2 In compare mode th
74. 5 0 V e Output voltage Vppc 2 5 V 7 5 e Low power voltage regulator provided in power down mode Vopc and Vopp prewarning detection Vppc brownout detection The EVR consists of a main voltage regulator and a low power voltage regulator In active mode both voltage regulators are enabled In power down mode the main voltage regulator is switched off while the low power voltage regulator continues to function and provide power supply to the system with low power consumption The EVR has the Vbpc and Vppp detectors There are two threshold voltage levels for Vbpc detection prewarning 2 3 V and brownout 2 1 V When Vpp Is below 2 3 V the Vopc NMI flag NMISR FNMIVDD is set and an NMI request to the CPU is activated provided Vbpc NMI is enabled NMICON NMIVDD If Vbpc is below 2 1 V the brownout reset is activated putting the microcontroller into a reset state For Vppp there is only one prewarning threshold of 4 0 V if the external power supply is 5 0 V When Vppp is below 4 0 V the Vbpp NMI flag NMISR FNMIVDDP is set and an NMI request to the CPU is activated provided Vppp NMI is enabled NMICON NMIVDDP lf an external power supply of 3 3 V is used the user must disable Vppp detector by clearing bit NUICON NMIVDDP In power down mode the Vpbpc detector is switched off while Vppp detector continues to function The EVR also has a power on reset POR detector for Vppc to ensure correct power up The voltage level detec
75. 5 1 Monitor Work Register 2 Only one register MMWR2 can be used for general purposes when no debug session is possible if the XC886 888 is not started in OCDS mode and no external device is connected to the JTAG interface MMWR2 Monitor Work Register 2 mapped SFR EC Reset value 00 7 6 5 4 3 2 1 0 Field Bits Type Description MMWR2 7 0 rw Work Register 2 Work location 2 for the Monitor Program User s Manual 17 10 V1 1 2007 05 OCDS V 1 0 Cinfin eon XC886 888CLM On Chip Debug Support 17 5 2 Input Select Registers Bits MODPISEL JTAGTCKS and MODPISEL1 JTAGTCKS1 are used to select one of the three TCK inputs while bits MODPISEL JTAGTDIS and MODPISEL1 JTAGTDIS1 are used to select one of the three TDI inputs MODPISEL Peripheral Input Select Register Reset Value 00 7 6 5 4 3 2 1 0 fe sracrors ASTOR mantais XNTHIS EXT URRIS r rw rw rw rw rw rw rw Field Bits Type Description JTAGTCKS 4 rw JTAG TCK Input Select 0 JTAG TCK Input TCK_0 is selected 1 JTAG TCK Input TCK_1 is selected JTAGTDIS 5 rw JTAG TDI Input Select 0 JTAG TDI Input TDI_O is selected 1 JTAG TDI Input TDI_1 is selected 0 7 r Reserved Returns 0 if read should be written with O MODPISEL1 Peripheral Input Select Register 1 Reset Value 00 7 6 5 4 3 2 1 0 pms o ums ravens ASTI TASK S1 S1 rw r rw rw rw rw Field Bits Type Description JTAGTCKS1 rw JTAG TCK Input Select 1 0 JTAG TCK Input TCK_2 is not selected 1 JTAG TCK
76. 5 6 2 External Interrupt Control Registers 000 eee eee 5 21 9 6 3 Interrupt Flag Registers 0 0 0 eee 9 25 5 6 4 Interrupt Priority Registers anaana aa aaa 5 32 5 7 Interrupt Flag Overview 0 0 eee 5 35 6 Parallel Ports 0 0 0 0 0 cc eee eee 6 1 6 1 General Port Operation 0 0 cc ee nee 6 2 6 1 1 General Register Description 2 0 ee ee 6 5 6 1 1 1 Pala REISE cadecad siani senarren et ban oo ot beens es 6 6 6 1 1 2 Direction Register 0 0 ce ees 6 6 1 1 3 Open Drain Control Register 0 0 0 0 eee 6 8 6 1 1 4 Pull Up Pull Down Device Register 00 00 eee eee 6 8 6 1 1 5 Alternate Inout and Output Functions 005 6 10 6 2 MCOISICUIMAD a206 soho ae be deacee En RSS oe yee eeeena bo ee SETER 6 11 6 3 POU O gages eee eeeree bones teehee ae heneeteaeerueer oe ee eaee 6 13 6 3 1 FUNCIONS c2 2h4 4en5550n0seeeus SEsteueresueaesatoeeeees 6 13 6 3 1 1 Register Description 0 0 eee 6 17 6 4 POM 222554 eeneeee eee oe ee ne ee eaeee eee SERER e Senet 6 20 6 4 1 PUMNCIONS 62cceeeeeueesentee pennies eeeeeeenereneestareeeas 6 20 6 4 2 Register Description 0 ce eee 6 24 6 5 POR 2 2heaenh peeearga cases deeeues ste a ease sees ase sedan eees 6 27 6 5 1 FUNGHONS 22 eutecocsedgess ese euesseGeesegeesisueseeeeages 6 27 6 5 2 Register Description 0 a eee 6 30 6 6 FONTO sensoren eyre E EE eee ees es be ewaeee 6 32
77. 5 Register Map cc eee 11 15 11 6 Register Description 0 cece ees 11 16 11 6 1 Control Register 0 0 0 0 cee eee 11 16 11 6 2 Status and Data Control Register 0 0 0 e eee 11 18 11 6 3 Data Registers 0 ce eee tenes 11 19 12 Serial Interfaces 0 0 0 0 0 000 ee eens 12 1 12 1 WART eee omenen see oh ee ee eee eee eee ewes pone 12 2 12 1 1 UART Modes 64 achaca Sead born peeee eed beunadeteepeseaenas 12 2 12 1 1 1 Mode 0 8 Bit Shift Register Fixed Baud Rate 12 2 12 1 1 2 Mode 1 8 Bit UART Variable Baud Rate 0 12 3 12 1 1 3 Mode 2 9 Bit UART Fixed Baud Rate 0 12 5 12 1 1 4 Mode 3 9 Bit UART Variable Baud Rate 0 12 5 12 1 2 Multiprocessor Communication 0 0 00 cee eee 12 7 12 1 3 UART Register Description 0 0 ees 12 8 12 1 4 Baud Rate Generation 0000 ee eee 12 10 12 1 4 1 FIMGCO CIOCK geagdeucueeeaneeereeahosawaadseneeus seannee 12 10 12 1 4 2 Dedicated Baud rate Generator 0 0 00 cee eee 12 11 12 1 4 3 TS cite eevee ye eare sy be eee ead toh Sue Be ep eas 12 22 12 1 5 POM COMUO ace0henesdaceaetunean sda eeateeen ees baee an 12 23 12 1 6 Low Power Mode 0 0 00 cece eee eee eee eee 12 24 12 1 7 Register Map 0 0c eee nas 12 25 12 2 GUN ao en dus bee eocbueerw see be cebuee E E ute see neha 12 26 12 2 1 EIN ProtOCOl s oaeacepeecccaegenegencadeearene
78. 6 6 1 FUNCTIONS anana anaana aa eee ees 6 32 6 6 2 Register Description 0 0 00 ees 6 36 6 POW og eseheaseareouge cht ne see wees dbs eraren 6 39 6 7 1 FUNCIONO 222 e eee54uo duu EENE ee ee does Erne peed bee eee 6 39 6 7 2 Register Description 0 0 eee 6 43 6 8 POM O 2245 staseceneuandene pee uedeend cag Ane neeeaee sda eeaets 6 46 6 8 1 FUNCIONS cas 4 tema ena s ee See seen eee ewe ees bee ene sex 6 46 6 8 2 Register Description 0 0 eee 6 50 7 Power Supply Reset and Clock Management 7 1 7 1 Power Supply System with Embedded Voltage Regulator 7 1 7 2 Reset COMO lt lt a ween weed be eee ee hes Beh eeu e eee eee es Sauneee 7 3 7 2 1 Types of Resets 0 00 0 eee eee ees 7 3 7 2 1 1 Power On Reset 0 00 ce eee ees 7 3 7 2 1 2 Hardware Reset 2 0 0 ccc ee eens 7 5 721 3 Watchdog Timer Reset 0 0 cee 7 5 7 2 1 4 Power Down Wake Up Reset 0 000 c eee eee eee 7 6 7 2 1 5 Brownout Reset 2 ce eee eens 7 6 User s Manual l 3 V1 1 2007 05 Cinfineon Table of Contents 8 1 4 Peripheral Clock Management 7 2 2 Module Reset Behavior 7 2 3 Booting Scheme 7 2 4 Register Description 7 3 Clock System 7 3 1 Clock Generation Unit 7 3 1 1 Functional Description 7 3 2 Clock Source Control 7 3 3 Clock Management 7 3 4 Register Description 8 Power Saving Modes 8 1 Functional Description 8 1 1 Idle Mode 8 1 2 Slow
79. 7 Parallel Request Source Control The load event for a parallel load can be e External trigger at the input line REQTR See Section 16 4 5 3 e Write operation to a specific address of the conversion request control register see Section 16 4 5 4 e Write operation with LDEV 1 to the request source mode register see Section 16 4 5 4 e Source internal action conversion completed and PND 0 for autoscan mode see Section 16 4 5 5 Each bit bit x x 4 7 in the conversion request control pending registers corresponds to one analog input channel The bit position directly defines the channel number The bits in the conversion request pending register can be set or reset bitwisely by the arbiter e The corresponding bit in the conversion request pending register is automatically reset when the arbiter indicates the start of conversion for this channel e The bit is automatically set when the arbiter indicates that the conversion has been aborted A source interrupt can be generated if enabled when a conversion requested by this source is completed while PND 0 These rules apply only if the request source has triggered the conversion User s Manual 16 15 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 5 3 External Trigger The conversion request for the parallel source and also the sequential source can be synchronized to an external trigger event For the parallel source this
80. 8 Flash Memory V 1 0 V1 1 2007 05 Cinfin eon XC886 888CLM Flash Memory A WL address can be calculated as follow 0000 40 x n with O lt n lt 127 for P Flash Pair 0 4 1 2000 40 x n with O lt n lt 127 for P Flash Pair 1 4 2 4000 40 x n with O lt n lt 127 for P Flash Pair 2 4 3 7000 A000 20 x n with O lt n lt 127 for D Flash 0 4 4 6000 B000 20 x n with O lt n lt 127 for D Flash 1 4 5 Only one out of all the wordlines in the Flash banks can be programmed each time The minimum program width of each WL is 64 bytes for P Flash and 32 bytes for D Flash Before programming can be done the user must first write the number of bytes of data that is equivalent to the program width into the IRAM using MOV instructions Then the Bootstrap Loader BSL routine see Section 4 7 or Flash program subroutine see Section 4 8 1 will transfer this IRAM data to the corresponding write buffers of the targeted Flash bank Once the data are assembled in the write buffers the charge pump voltages are ramped up by a built in program and erase state machine Once the voltage ramping is completed the volatile data content in the write buffers would have been stored into the non volatile Flash cells along the selected WL The WL is selected via the WL addresses shown in Figure 4 4 Figure 4 5 and Figure 4 6 It is necessary to fill the IRAM with the number of bytes of data as defined by the pro
81. 8 bit timers 13 7 Port control 13 8 Register description 13 10 Register map 13 9 Timer operations 13 2 Timer overflow 13 2 Timer 2 and Timer 21 13 14 13 28 Auto Reload mode 13 14 Up Down Count Disabled 13 14 Up Down Count Enabled 13 15 Capture mode 13 18 Counter 13 14 External interrupt function 13 20 Low power mode 13 21 Module suspend control 13 22 Port control 13 20 Register description 13 24 Register map 13 23 Timer operations 13 14 Timer T12 14 3 Capture mode 14 9 Center aligned mode 14 4 Compare mode 14 6 Dead time 14 8 User s Manual 19 6 XC886 888CLM Index Duty cycle 14 8 Edge aligned mode 14 4 Hysteresis like control mode 14 10 Shadow transfer 14 3 Single shot mode 14 10 Three phase PWM 14 1 Timer T13 14 12 Compare mode 14 13 Shadow transfer 14 12 Single shot mode 14 13 Total conversion time 16 6 Trap handling 14 17 Tristate 6 8 U UART BSL 18 8 UART UART1 module 12 2 12 25 Baud rate generation 12 10 Interrupt requests 12 5 Mode 1 8 bit UART 12 3 Mode 2 9 bit UART 12 5 Mode 3 9 bit UART 12 5 Modes 12 2 Port control 12 23 Receive buffered 12 2 Register map 12 25 UART1 module Low power mode 12 24 User programmable password 3 7 V VCO bypass 7 14 W Wait for read mode 16 17 Wait for Start 16 10 Watchdog timer 9 1 Input frequency 9 3 Module suspend control 9 4 Register description 9 5 Servicing 9 2 Time period 9 3 Watchdog timer reset 7 5 V1 1 2007 05 Cinfineon Window bou
82. BCON e Fractional divider STEP 256 defined by register FDSTEP to be considered only if fractional divider is enabled and operating in fractional divider mode e 8 bit reload value BR_VALUE for the baud rate timer defined by register BG User s Manual 12 12 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces The following formulas calculate the final baud rate without see Equation 12 2 and with the fractional divider see Equation 12 3 respectively 12 2 baud rate PCLK PRE where 2 BR VALUE 1 gt 1 iera RAE BR VALUE 1 x BR _ 12 3 f STEP baud rate PCLK SE OPAK _ 16x 2PRPRE BR VALUE 1 256 The maximum baud rate that can be generated is limited to fp 32 Hence for a module clock of 24 MHz the maximum achievable baud rate is 0 75 MBaud Standard LIN protocol can support a maximum baud rate of 20kHz the baud rate accuracy is not critical and the fractional divider can be disabled Only the prescaler is used for auto baud rate calculation For LIN fast mode which supports the baud rate of 20kHz to 115 2kHz the higher baud rates require the use of the fractional divider for greater accuracy Table 12 2 lists the various commonly used baud rates with their corresponding parameter settings and deviation errors The fractional divider is disabled and a module clock of 24 MHz is used Table 12 2 Typical Baud rates for UART with Fractional Divid
83. Byte 5 of Message Object n DB6 23 16 Data Byte 6 of Message Object n DB7 31 24 Data Byte 7 of Message Object n User s Manual 15 96 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller 15 2 4 MultiCAN Access Mediator Register CAN ADCON CAN Address Data Control Register Reset Value 0000 0000 7 6 9 4 3 2 1 0 rw rw rw rw rw rh rw Field Description RWEN Read Write Enable 0 Read is enabled 1 Write is enabled BSY Data Transmission Busy 0 Data Transimission is finished 1 Data Transimission is in progress AUAD 3 2 rw Auto Increment Decrement the Address 00 No increment decrement the address 01 Auto increment the current address 1 10 Auto decrement the current address 1 11 Auto increment the current address 8 VO r CAN Data 0 Valid 0 Data in CAN_DATAO register is not valid for transmission 1 Data in CAN_DATAO register is valid for transmission V1 5 r CAN Data 1 Valid 0 Data in CAN_DATA1 register is not valid for transmission 1 Data in CAN_DATA1 register is valid for transmission V2 r CAN Data 2 Valid 0 Data in CAN_DATA2 register is not valid for transmission 1 Data in CAN_DATA2 register is valid for transmission User s Manual 15 97 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Field Bits Type Description V3 7 rw CAN Data 3 Valid 0 Data in CAN_DATAS register is not valid for transm
84. Capture Compare Unit 6 Table 14 7 Multi Input Capture Modes Description 1100 The timer value of T12 is stored in CC6nR after a rising edge at the input pin CC6n The timer value of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx 1101 The timer value of T12 is stored in CC6nR after a falling edge at the input pin CC6n The timer value of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx 1110 The timer value of T12 is stored in CC6nR after any edge at the input pin CC6n The timer value of T12 is stored in CC6nSR after any edge at the input pin CCPOSx 1111 reserved no capture or compare action T12MSELL T12 Capture Compare Mode Select Register Low Reset Value 00 7 6 5 4 3 2 1 0 rw rw User s Manual 14 42 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field oe Description MSEL60 Capture Compare Mode Selection MSEL61 These bit fields select the operating mode of the three timer T12 capture compare channels Each channel n 0 1 2 can be programmed individually either for compare or capture operation according to 0000 Compare outputs disabled pins CC6n and COUTE6n can be used for I O No capture action 0001 Compare output on pin CC6n pin COUTE6n can be used for I O No capture action 0010 Compare output on pin COUTEn pin CC6n can be used for I O No capture action 0011 Compare output on pins COUT6n and CC6n 01XX Double Register Capture modes
85. Compare Unit 6 Table 14 4 Registers Overview cont d Register Register Long Name Description Short Name see T12MSELH T12 Mode Select Register High Page 14 44 Interrupt Control Registers ISL Capture Compare Interrupt Status Register Low Page 14 79 ISH Capture Compare Interrupt Status Register High Page 14 80 ISSL Capture Compare Interrupt Status Set Register Page 14 83 Low ISSH Capture Compare Interrupt Status Set Register Page 14 84 High ISRL Capture Compare Interrupt Status Reset Page 14 85 Register Low ISRH Capture Compare Interrupt Status Reset Page 14 86 Register High IENL Capture Compare Interrupt Enable Register Low Page 14 87 IENH Capture Compare Interrupt Enable Register High Page 14 89 INPL Capture Compare Interrupt Node Pointer Page 14 90 Register Low INPH Capture Compare Interrupt Node Pointer Page 14 92 Register High 14 3 1 System Registers Registers PISELO and PISEL2 contain bit fields that select the actual input port for the module inputs This permits the adaptation of the pin functionality of the device to the application s requirements The output pins are chosen according to the registers in the ports PISELOL Port Input Select Register 0 Low Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw User s Manual 14 37 V1 1 2007 05 CCU6 V 1 0 Cinfine on XC886 888CLM Capture Compare Unit 6 Field Description ISCC60 Input Select for CC60 This bit field defines the port pin that is used
86. Connect oscillator to PLL OSCDISC 0 Wait till the LOCK bit has been set Disable VCO bypass mode as Sy a Select the External Oscillator To select the external oscillator the following sequence must be performed Select the VCO bypass mode VCOBYP 1 Disconnect the oscillator from the PLL OSCDISC 1 External OSC is powered up by resetting bit XPD The source of external oscillator is selected by setting bit OSCSS Wait until the external oscillator is stable the delay time should be adjusted according to different external oscillators 6 Restart the Oscillator Run Detection by setting bit OSC_CON ORDRES 7 Wait for 2048 cycles based on VCO frequency If bit OSC_CON OSCR is set then 1 Reprogram the NDIV factor to the required value 2 Reconnect oscillator to the PLL OSCDISC 0 3 The RESLD bit must be set and the LOCK flag checked Only if the LOCK flag is set again can the VCO bypass mode be deselected and normal operation resumed ae SY In order to minimize power consumption while the on chip oscillator is used XTAL is powered down by setting bit XPD When the external oscillator is used the on chip oscillator can be powered down by setting bit OSCPD 7 3 2 Clock Source Control The clock system provides three ways to generate the system clock PLL Base Mode When the oscillator is disconnected from the PLL the system clock is derived from the VCO base free running frequency clock
87. Down Mode 8 1 3 Power down Mode 8 2 Register Description 9 Watchdog Timer 9 1 Functional Description 9 1 1 Module Suspend Control 9 2 Register Map 9 3 Register Description 10 Multiplication Division Unit 10 1 Functional Description 10 1 1 Division Operation 10 1 2 Normalize 10 1 3 Shift 10 1 4 Busy Flag 10 1 5 Error Detection 10 2 Interrupt Generation 10 3 Low Power Mode 10 4 Register Map 10 5 Register Description 10 5 1 Operand and Result Registers 11 2 1 Operation of the CORDIC Coprocessor 10 5 2 Control Register 10 5 3 Status Register 11 CORDIC Coprocessor 11 1 Features 11 2 Functional Description 11 2 2 Interrupt User s Manual XC886 888CLM V1 1 2007 05 Cinfin eon XC886 888CLM Table of Contents Page 11 2 3 Normalized Result Data 1 2 0 0 ee 11 4 11 2 4 CORDIC Coprocessor Operating Modes 00005 11 5 11 2 4 1 Domains of Convergence 0 0 cee ees 11 7 11 2 4 2 Overflow Considerations 0 00 cee ee es 11 8 11 2 5 CORDIC Coprocessor Data Format 00 000 eee ees 11 8 11 2 6 Accuracy of CORDIC Coprocessor 0000s 11 9 11 2 7 Performance of CORDIC Coprocessor 0000 ees 11 11 11 3 The CORDIC Coprocessor Kernel 0 000 eee eee 11 12 11 3 1 Arctangent and Hyperbolic Arctangent Look Up Tables 11 12 11 3 2 Linear Function Emulated Look Up Table 11 13 11 4 Low Power Mode 0000s 11 14 11
88. Error Counter Register Reset Value 0060 0000 31 30 29 28 2 26 25 24 23 22 21 20 19 18 17 16 LEIN LET r rh rh rw TEC REC rwh rwh Field Bits Type Description REC 7 0 rwh Receive Error Counter Bit field REC contains the value of the receive error counter of CAN node x TEC 15 8 rwh Transmit Error Counter Bit field TEC contains the value of the transmit error counter of CAN node x EWRNLVL 23 16 rw Error Warning Level Bit field EWRNLVL defines the threshold value warning level default 96 to be reached in order to set the corresponding error warning bit NSRx EWRN LETD 24 rh Last Error Transfer Direction 0 The last error occurred while the CAN node x was receiver REC has been incremented 1 The last error occurred while the CAN node x was transmitter TEC has been incremented LEINC 25 h Last Error Increment 0 The last error led to an error counter increment of 1 1 The last error led to an error counter increment of 8 User s Manual 15 71 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Field Description 0 26 Reserved Read as 0 should be written with O The Node Frame Counter Register NFCRx contains the actual value of the frame counter as well as control and status bits of the frame counter NFCRx x 0 1 Node x Frame Counter Register Reset Value 0000 0000 31 380 29 28 2 7 26 25 24 23 22 21 20 19 18 17 16 CFC CFCI o
89. Figure 16 6 Sequential Request Source Control If the requested conversion is sensitive to an external trigger event EXTR 1 the signal REQTR can be taken into account with ENTR 1 or the software can write TREV 1 Both actions set the event flag EV The event flag EV 1 indicates that an external event has taken place and a conversion can be requested EV can be set only if a conversion request is valid with V 1 In this case the signal REQCHNRV is derived from bit EV In the queue backup register bit EXTR is always considered as 0 If a queue controlled conversion has been started and aborted due to a higher priority conversion the aborted conversion will be restarted without waiting for a new trigger event User s Manual 16 13 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 5 Parallel Request Source A parallel request source generates one or more channel conversion requests in parallel The requests are always treated one after the other in a pre defined sequence higher channel numbers before lower channel numbers The parallel source register description can be found in Section 16 7 7 16 4 5 1 Overview The parallel request source at arbitration slot 1 generates one or more conversion requests for channel numbers between 4 and 7 in parallel The requests are always treated one after the other in separate arbitration rounds in a predefined sequence higher channel numbers befo
90. Flash bank pair 0 occupies the address range 0000 1FFF User s Manual 4 2 V1 1 2007 05 Flash Memory V 1 0 Cinfin eon XC886 888CLM Flash Memory e P Flash pair bank 1 occupies 2000 3FFF e P Flash pair bank 2 occupies 4000 5FFF for 32 Kbyte device or 4000 4FFF for 24 Kbyte device The D Flash bank s in the XC886 888 Flash devices are mapped to two program memory address spaces e D Flash Bank 0 is mapped to 7000 7FFF and A000 AFFF e D Flash Bank 1 which is only available in the 32 Kbyte Flash device is mapped to 6000 6FFF and BOOO BFFF In general the lower address spaces 6000 6FFF and 7000 7FFF should be used for D Flash bank s contents that are intended to be used as program code Alternatively the higher address spaces A000 AFFF and B000 BFFF should be used for D Flash bank s contents that are intended to be used as data All ROM devices in the XC886 888 product family offer a 4 Kbyte D Flash bank mapped to the address space A000 AFFF 4 2 Flash Bank Sectorization The XC886 888 Flash devices consist of two types of 4 Kbyte banks namely Program Flash P Flash bank and Data Flash D Flash bank with different sectorization as shown in Figure 4 2 Both types can be used for code and data storage The label Data neither implies that the D Flash is mapped to the data memory region nor that it can only be used for data
91. Input TCK_2 is selected Note If this bit is set JTAG TCK input TCK 2 is selected regardless of the bit JTAGTCKS in register MODPISEL User s Manual 17 11 V1 1 2007 05 OCDS V 1 0 Cinfin eon XC886 888CLM On Chip Debug Support Field Bits Type Description JTAGTDIS1 1 rw JTAG TDI Input Select 1 0 JTAG TDI Input TDI 2 is not selected 1 JTAG TDI Input TDI_2 is selected Note If this bit is set JTAG TDI input TDI 2 is selected regardless of the bit JTAGTDIS in register MODPISEL 0 6 5 r Reserved Returns 0 if read should be written with 0 17 6 JTAG ID This is a read only register located inside the JTAG module and is used to recognize the device s connected to the JTAG interface Its content is shifted out when INSTRUCTION register contains the IDCODE command opcode 04 and the same is also true immediately after reset The JTAG ID for the XC886 888 devices is given in Table 17 3 Table 17 3 JTAG ID Summary Device Type JTAG ID Flash 1012 0083 ROM 1013 C083 XC886 888 6RF 1013 D083 User s Manual 17 12 V1 1 2007 05 OCDS V 1 0 Cinfine on XC886 888CLM Bootstrap Loader 18 Bootstrap Loader The XC886 888 includes a Bootstrap Loader BSL Mode that can be entered with the pin configuration shown in Table 18 1 during hardware reset The main purpose of BSL Mode is to allow easy and quick programming erasing of the Flash and XRAM via serial interface The XC886 888 supports three device BSL modes
92. Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System 5 2 Interrupt Source and Vector Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to This vector is accessed to service the corresponding interrupt node request The interrupt service of each interrupt node can be individually enabled or disabled via an enable bit The assignment of the XC886 888 interrupt sources to the interrupt vector address and the corresponding interrupt node enable bits are Summarized in Table 5 1 Table 5 1 Interrupt Vector Addresses Interrupt Vector Assignment for Enable Bit SFR Node Address XC886 888 NMI 00734 Watchdog Timer NMI PLL NMI Flash NMI VDDC Prewarning NMI VDDP Prewarning NMI NMIVDDP Flash ECC NMI NMIECC XINTRO 00034 External Interrupt 0 EX0 IENO T UART Fractional Divider Normal Divider Overflow MultiCAN Node 0 NMIWDT NMICON NMIPLL NMIFLASH NMIVDD User s Manual 5 11 V1 1 2007 05 Interrupt System V 1 0 Cinfine on XC886 888CLM Table 5 1 Interrupt Node XINTR6 XINTR7 XINTR8 XINTRQ XINTR10 XINTR11 XINTR12 XINTR13 User s Manual Interrupt System Interrupt Vector Addresses contd Vector Assignment for Enable Bit Address XC886 888 00334 aa N Nodes 1 and 2 EADC IEN1 we ea 0 _ External Interrupt2 a 2 EX2 oa eooo ane Divider Overflow MDU 1 0 0 004B External Interrupt3 External Interrupt3 3 EXM Ext
93. Manual 14 19 V1 1 2007 05 CCU6 V 1 0 Cinfine on XC886 888CLM Capture Compare Unit 6 synchronization event which leads to the transfer from MCMPS to MCMP Due to this structure an update takes place with a new PWM period The update can also be requested by software by writing to bit field MCMPS with the shadow transfer request bit STRMCM set If this bit is set during the write action to the register the flag R is automatically set By using this the update takes place completely under software control A shadow transfer interrupt can be generated when the shadow transfer takes place The possible hardware request events are e a112 period match while counting up T12pm e a112 one match while counting down T120m e a113 period match 113pm e a112compare match of channel 1 T12c1cm e acorrect Hall event The possible hardware synchronization events are e a 112 zero match while counting up T12zm e a113zero match 113zm User s Manual 14 20 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 1 6 Hall Sensor Mode In Brushless DC motors the next multi channel state values depend on the pattern of the Hall inputs There is a strong correlation between the Hall pattern CURH and the modulation pattern MCMP Because of different machine types the modulation pattern for driving the motor can vary Therefore it is beneficial to have wide flexibility in defining the correlation between
94. Manual 6 19 V1 1 2007 05 Parallel Ports V 1 0 Cinfine on XC886 888CLM Parallel Ports 6 4 Port 1 Port P1 is a 8 bit general purpose bidirectional port The registers of P1 are summarized in Table 6 5 Table 6 5 Port 1 Registers Register Short Name Register Full Name P1 DATA Port 1 Data Register P1_ DIR Port 1 Direction Register P1_ OD Port 1 Open Drain Control Register P1_ PUDSEL Port 1 Pull Up Pull Down Select Register P1 PUDEN Port 1 Pull Up Pull Down Enable Register P1 ALTSELO Port 1 Alternate Select Register 0 P1 ALTSEL1 Port 1 Alternate Select Register 1 6 4 1 Functions Port 1 input and output functions are shown in Table 6 6 Table 6 6 Port 1 Input Output Functions Port Pin Input Output Select _ Connected Signals F From to Module P1 0 Input P1 DATA PO an am i am i ooo User s Manual 6 20 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Table 6 6 Port 1 Input Output Functions a Output GPO PT DATA P1 ALT1 TDO _1 JTAG ALT2 TXD_0O UART ALT3 TXDCO_0 MultiCAN P1 2 Input P1_DATA P2 PLOATAPE a es f ALT3 Output GPO P1_DATA P2 PLOATAPE ae me ALT2 ALT3 TXDC1_3 MultiCAN User s Manual 6 21 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Table 6 6 Port 1 Input Output Functions Port Pin pna a e i From to Module External interrupt 0 ALT3 RXDC1_3 MultiCAN Output GPO P1_DATA P4 PIDATAPE Ae t
95. Match Rising Edge Interrupt Enable for Channel 1 0 No interrupt will be generated if the set condition for bit CC61R in register IS occurs 1 An interrupt will be generated if the set condition for bit ICC61R in register IS occurs The interrupt line that will be activated is selected by bit field INPCC61 User s Manual 14 87 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field ENCC61F Description Capture Compare Match Falling Edge Interrupt are for Channel 1 No interrupt will be generated if the set condition for bit ICC61F in register IS occurs An interrupt will be generated if the set condition for bit CC61F in register IS occurs The interrupt line that will be activated is selected by bit field INPCC61 i ENCC62R Capture Compare Match Rising Edge Interrupt Enable for Channel 2 0 No interrupt will be generated if the set condition for bit ICC62R in register IS occurs 1 An interrupt will be generated if the set condition for bit ICC62R in register IS occurs The interrupt line that will be activated is selected by bit field INPCC62 ENCC62F Capture Compare Match Falling Edge Interrupt Enable for Channel 2 0 No interrupt will be generated if the set condition for bit ICC62F in register IS occurs 1 An interrupt will be generated if the set condition for bit ICC62F in register IS occurs The interrupt line that will be activated is selected by bit field INPCC62 Enable Inte
96. Memory Organization V 1 2 Infineon SYSCONO RMAP rw SFR Data _ to from CPU XC886 888CLM Memory Organization Standard Area RMAP 0 Module 1 SFRs Module 2 SFRs Module n SFRs Module n 1 SFRs Module n 2 SFRs Module m SFRs 80 Direct Internal Data Memory Address Figure 3 4 Address Extension by Mapping User s Manual Memory Organization V 1 2 V1 1 2007 05 Cinfin eon XC886 888CLM Memory Organization 3 5 1 1 System Control Register 0 The SYSCONO register contains bits to select the SFR mapping and interrupt structure 2 mode SYSCONO System Control Register 0 Reset Value 04 7 6 5 4 3 2 1 0 r rw r r r rw Field Description RMAP n Function Register Map Control The access to the standard SFR area is enabled The access to the mapped SFR area is enabled 1 A i a 1 if read should be written with 1 0 3 Reserved 7 5 Returns 0 if read should be written with 0 Note The RMAP bit should be cleared set using ANL or ORL instructions User s Manual 3 12 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization 3 5 2 Address Extension by Paging Address extension is further performed at the module level by paging With the address extension by mapping the XC886 888 has a 256 SFR address range However this is still less than the total number of SFRs needed by the on chip peripherals To meet this requirement some peripherals have a bui
97. Mode Data 00 02 StartAddr StartAddr Not Used Checksum 2 bytes Mode 0 2 High Low 1 byte 1 byte Mode Data Description Start Addr High Low 16 bit Start Address which determines where to copy the received program code in the XRAM Flash Block_Length The whole length block type data area and checksum of the following Data or EOT Blocks Flash address must be aligned to the wordline address where DPL is 00 40 80 CO for P Flash and 00 20 40 60 80 A0 CO0 E0 for D Flash If the data starts in a non wordline address PC Host needs to fill up the beginning vacancies with OOH and provide the start address of that wordline address For example if data starts in OF82 the PC Host will fill up the addresses OF80 and OF81 with OOH and provide the Start Address OF80 to uC And if data is only 8 bytes the PC Host will also fill up the remaining addresses with OOH and transfer 64 bytes as 2 When the Block_Length is defined in Header Block the subsequent Data or EOT Block must be of this length To redefine the Block _Length it must be accompanied by a new Header Block User s Manual 18 10 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader Not used 2 bytes these bytes are not used and will be ignored in Mode 0 2 After the header block is successfully received the microcontroller enters Mode 0 2 during which the program code is transmitted fr
98. OSC value which specifies the oscillator frequency connected to the device Is programmed into the uppermost P Flash bank pair This parameter is specified by the user Table 18 9 shows the address supported values and default value of the user defined parameter for unprotected Flash To ensure the validity of the parameter the inverted values are required to be programmed together with the actual values A check is done to verify whether the addition of the inverted value actual value and 01 will give 00 Table 18 9 User Defined Parameter for MultiCAN BSL 00 4 MHz 8 MHz 014 6 MHz 024 8 MHz 034 12 MHz Others 8 MHz default 5FF9 OFFA FFL 4 MHz FE 6 MHz FD 8 MHz FC 12 MHz Others 8 MHz default The address shown in the table assumes a device with 24 Kbytes of P Flash For variants with smaller P Flash sizes the address used will be the address of the uppermost P Flash bank plus the offset For example a 20 Kbytes Flash variant will have the OSC address at 4FF9 User s Manual 18 31 V1 1 2007 05 Bootstrap Loader V1 0 Cinfineon 19 Index 19 1 Keyword Index XC886 888CLM Index This section lists a number of keywords which refer to specific details of the XC886 888 in terms of its architecture its functional units or functions A Accumulator 2 3 Alternate functions 6 10 Input 6 10 Output 6 10 Analog input clock 16 3 Analog to Digital Converter 16 1 Interrupt 16 23 Chan
99. Pending Bit x x 4 7 Write view A write to this address targets the bits in register CRCR1 Read view Each bit corresponds to one analog channel the channel number x is defined by the bit position in the register The arbiter automatically resets at start of conversion or sets it again at abort of conversion for the corresponding analog channel Os The analog channel x is not requested for conversion by the parallel request source 1 The analog channel x is requested for conversion by the parallel request source 0 3 0 r Reserved Returns 0 if read should be written with 0 Note The bits that can be read from this register location are generally rh They cannot be modified directly by a write operation A write operation modifies the bits in CRCR1 that is why they are marked rwh and leads to a load event one clock cycle later User s Manual 16 50 V1 1 2007 05 ADC V 1 0 Cinfine on XC886 888CLM Analog to Digital Converter Register CRMR1 contains bits that are used to set the request source in the desired mode CRMR1 Conversion Request Mode Register 1 CC Reset Value 00 7 6 5 4 3 2 1 0 Rev DEV cuRpNO SCAN ENSI ENTR 0 enot r W W rw rw rw r rw Field Description ENGT Enable Gate This bit enables the gating functionality for the request source Os The gating line is permanently 0 The source is switched off 1g The gating line is permanently 1 The source is Switched on ENTR Ena
100. Port 2 Pull Up Pull Down Enable Register 6 5 1 Functions Port 2 input functions are shown in Table 6 8 Table 6 8 Port 2 Input Functions Port Pin Input Output Select Connected Signal s _ Fromito Module External interrupt 1 ALT 3 T12HR_2 CCU6 ALT 4 TCK_1 JTAG P2 1 Input P2 DATA P1 External interrupt 2 T13HR 2 CCU6 User s Manual 6 27 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Table 6 8 Port 2 Input Functions cont d Port Pin Input Output CC60_3 CCU6 P2 2 Input GPI ALT 1 ALT 2 ALT 3 ALT 4 ALT 5 ANALOG AN2 ADC P2 3 Input P2 DATA P3 m ALT 2 ALT 3 B as ooo h AN3 ADC P2 4 Input P2 DATA P4 7 ATS o ANALOG AN4 ADC P2 5 Input P2 DATA P5 as ooo h AN5 ADC User s Manual 6 28 V1 1 2007 05 Parallel Ports V 1 0 Connected Signal s From to Module P2 DATA P2 CCPOS2_0 CCU6 CTRAP_1 CCU6 Cinfin eon XC886 888CLM Parallel Ports Table 6 8 Port 2 Input Functions cont d Port Pin aan gt Connected Signal s From to Module P2 DATA P6 P2 6 Input are 5 a eo ADC User s Manual 6 29 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 5 2 Register Description P2 DATA Port 2 Data Register Reset Value 00 7 6 5 4 3 2 1 0 r r r r r r r r Field Description Pn _ 2 Pin n Data Value n 0 7 Port 2 pin n data value O default Port 2 pin n data value 1 P2 DIR Port 2 Direction Regi
101. Power Mode Control Register 1 Reset Value 00 7 6 9 4 3 2 1 0 UART1_ ee U r rw rw Field oe Description UART1 DIS ee Module Disable Request Active high UART1 module is in normal operation default Request to disable the UART1 module 0 7 2 Reserved Returns 0 if read should be written with O Note The Low Power Mode option is not available in VART module User s Manual 12 24 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 1 7 Register Map All UART1 module register names described in the previous sections are referenced in other chapters of this document with the module name prefix UART1_ e g UART1_SCON However all UART module registers are not referenced by any prefix Besides the SCON and SBUF registers which can be accessed from both the standard non mapped and mapped SFR area the rest of the UART module s SFRs are located in SCU page O0 of the standard area The UART1 module SFRs are all located in the mapped SFR area Table 12 5 lists the addresses of these SFRs Table 12 5 UART Module SFR Address List UART Module UART1 Module EA FDSTEP FDSTEP User s Manual 12 25 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces 12 2 LIN The UART module can be used to support the Local Interconnect Network LIN protocol for both master and slave operations The LIN baud rate detection feature provides the capabilit
102. Programmable Password Bit Fields 7 1 bit Flash hardware Flash hardware protection mode 0 is protection mode selected selection bit Flash hardware protection mode 1 is selected 6 5 2 bit Select field for Flash Only P Flash banks are erased during banks to be erased unprotection during unprotection P Flash banks and D Flash bank 0 are erased during unprotection P Flash banks and D Flash bank 1 are erased during unprotection All Flash banks P Flash and D Flash are erased during unprotection If bit 7 of password is set all Flash banks will be erased during unprotection regardless of the value of bits 4 to 6 4 1 bit Flash hardware Flash hardware protection will not be protection enable bit activated Flash hardware protection will be activated 3 0 4 bit User defined password This password field must be a non zero field value Note For ROM devices bits 5 to 7 are not applicable and should be written with zeros Setting bit 4 enables the protection of D Flash from accidental erase i e DFLASHEN bit must be set prior to each erase operation BSL mode 6 which is used for enabling Flash protection can also be used for disabling Flash protection Here the programmed password must be provided by the user A password match triggers an automatic erase of the protected P Flash and D Flash contents including the programmed password The Flash protection is then disabled upon the next reset For the ROM device
103. Pull Up Pull Down Enable Register P2 PUDSEL P2 Pull Up Pull Down Select Register P2 PUDEN Reset 00 P2 Pull Up Pull Down Enable Register P3_PUDSEL P3 Pull Up Pull Down Select Register P3 PUDEN Reset 404 P3 Pull Up Pull Down Enable Register P4 PUDSEL P4 Pull Up Pull Down Select Register P4_PUDEN Reset 04 P4 Pull Up Pull Down Enable Register RMAP 0 PAGE 2 a PO_ALTSELO Reset 00 PO Alternate Select 0 Register PO ALTSEL1 Reset 00 PO Alternate Select 1 Register P1 ALTSELO Reset 00y P1 Alternate Select 0 Register P1_ALTSEL1 Reset 00 4 P1 Alternate Select 1 Register P5_ALTSELO Reset 00 4 P5 Alternate Select 0 Register User s Manual Memory Organization V 1 2 Reset C44 Reset FFH Reset FFy Reset FFy Reset FFy Reset FFy Reset BF Reset FFH Reset FFy Bit Field Field fee ee Bit Field Field cc cs jetried 7 pe ps pe po pe pr Po er Bit Field Field fee ee Bit Field Field fee ee Bit Field Field ee e eee Bit Field Field fee ee Bit Field Field oc errea Pz Pe ps pe po pe pr Po CREAKAKACAKAKSEAES Bit Field Field fee ee Bit Field Field fee ee ee Bit Field Field Siete lelele iets ete ae Type pow iw ow ew ow w urea er ee rs me ro me mr Type w w w w rw w ow BtFea P7 Pe ps pa po P2 Pt Tee w w ow w rw w
104. Reset Set Receive Updating SETRXUPD 18 W These bits control the set reset condition for RXUPD see Table 15 11 3 W 19 W RESNEWDAT Reset Set New Data SETNEWDAT These bits control the set reset condition for NEWDAT see Table 15 11 User s Manual 15 76 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Field Bits Type Description 4 W RESMSGLST Reset Set Message Lost SETMSGLST 20 W These bits control the set reset condition for MSGLST see Table 15 11 RESMSGVAL 5 W Reset Set Message Valid SETMSGVAL 21 W These bits control the set reset condition for MSGVAL see Table 15 11 RESRTSEL 6 W Reset Set Receive Transmit Selected SETRTSEL 22 W These bits control the set reset condition for RTSEL see Table 15 11 RESRXEN 7 W Reset Set Receive Enable SETRXEN 23 W These bits control the set reset condition for RXEN see Table 15 11 RESTXRQ 8 W Reset Set Transmit Request SETTXRQ 24 W These bits control the set reset condition for TXRQ see Table 15 11 RESTXENO 9 W Reset Set Transmit Enable 0 SETTXENO 25 W These bits control the set reset condition for TXENO see Table 15 11 RESTXEN1 10 W Reset Set Transmit Enable 1 SETTXENT1 26 W These bits control the set reset condition for TXEN1 see Table 15 11 RESDIR 11 W Reset Set Message Direction SETDIR 27 W These bits control the set reset condition for DIR see Table 15 11 0 15 12 w Reserved 31 28 Shou
105. SBUF with the 8 data bits loads RB8 SCON 2 with the 9th data bit and sets the RI bit provided RI 0 and either SM2 0 see Section 12 1 2 or the 9th bit 1 If none of these conditions is met the received byte is lost The baud rate for the transfer is either foc 64 Or foo x 32 for UART module depending on the setting of the top bit SMOD of the PCON Power Control register which acts as a Double Baud Rate selector For UART1 module the baud rate is fixed at foc 64 12 1 1 4 Mode 3 9 Bit UART Variable Baud Rate Mode 3 is the same as mode 2 in all respects except that the baud rate is variable In all modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in the modes by the incoming start bit if REN 1 The serial interface also provides interrupt requests when transmission or reception of the frames has been completed The corresponding interrupt request flags are TI or RI respectively If the serial interrupt is not used i e serial interrupt not enabled Tl and RI can also be used for polling the serial interface The associated timings for transmit receive in modes 2 and 3 are illustrated in Figure 12 2 User s Manual 12 5 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces Transmit reset B o E BE D o x oa xS 2 25 _ ro X mw op X FO O D F l Receive Figure 12 2 Serial Interface Modes 2 a
106. Select Registers 0005 17 6 JTAG ID 1 eee 18 Bootstrap Loader 18 1 UART and LIN BSL Modes 18 1 1 Communication Protocol 18 1 1 1 UART Transfer Block Structure 18 1 1 2 LIN Transfer Block Structure 18 1 1 3 Response Code to the Host 18 1 2 Bootstrap Loader via UART 18 1 2 1 Communication Structure 18 1 2 2 The Selection of Modes 18 1 2 3 The Activation of Modes 0 and2 18 1 2 4 The Activation of Modes 1 3 andF 18 1 2 5 The Activation of Mode 4 18 1 2 6 The Activation of Mode6 18 1 2 7 The Activation of Mode A 18 1 3 Bootstrap Loader viaLIN 18 1 3 1 Communication Structure 18 1 3 2 The Selection of Modes 18 1 3 3 The Activation of Modes 0 2and8 18 1 3 4 The Activation of Modes 1 3 and9 18 1 3 5 The Activation of Mode 4 18 1 3 6 The Activation of Mode 6 18 1 3 7 The Activation of Mode A 18 1 3 8 LIN Response Protocol to the Host 18 1 3 9 Fast LIN BSL 18 1 3 10 After Reset Conditions 18 1 3 11 User Defined Parameter for LIN BSL 18 2 MultiCAN BSL Mode 0 18 2 1 Communication protocol
107. T12CLK In order to support higher clock frequencies an additional prescaler factor of 1 256 can be enabled for the prescaler of 112 if bit T12PRE 1 The timer period compare values passive state selects bits and passive levels bits are written to shadow registers and not directly to the actual registers while the read access targets the registers actually used except for the three compare channels where both the actual and the shadow registers can be read The transfer from the shadow registers to the actual registers is enabled by setting the shadow transfer enable bit STE12 lf this transfer is enabled the shadow registers are copied to the respective registers as soon as the associated timer reaches the value zero the next time being cleared in edge aligned mode or counting down to 1 in center aligned mode When timer T12 is operating in center aligned mode it will also copy the registers if enabled by STE12 if it reaches the currently programmed period value counting up When timer T12 is stopped the shadow transfer takes place immediately if the corresponding bit STE12 is set Once the transfer is complete the respective bit STE12 is cleared automatically Figure 14 2 shows an overview of Timer T12 1 one match zero match period match Ue T12PR lt T12PS period shadow transfer compare match compare shadow transfer CC6xR lt H CC6xSR capture events A according to Al bitfield MSEL6x counter regist
108. Table 18 3 LIN Frame Programming Checksum Addition of data Addition with CARRY 4Ay 554 01324 oT oO 9F 93 0132 33 ES The Programming Checksum is 19 An inversion of the Programming Checksum yields the standard LIN Checksum Classic Checksum i e E6 Both Programming and LIN Checksum are supported and indicated in respective modes 4A OF 33 19 User s Manual 18 5 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader 18 1 1 3 Response Code to the Host The microcontroller would let the host Know whether a block has been successfully received by sending out a response code Table 18 4 tabulates the possible responses from the microcontroller upon reception of a Header Data or EOT block for each working mode Table 18 4 Possible Responses for Various Block Types Mode Header Block Data Block EOT Block 0 8 Acknowledge Block Error Acknowledge Block Acknowledge Block Checksum Error Protection Error Checksum Error Error Checksum Error Error 1 9 Acknowledge Block Error Checksum Error 2 Acknowledge Block Error Acknowledge Block Acknowledge Block Checksum Error Protection Error Checksum Error Error Checksum Error Error 3 Acknowledge Block Error Checksum Error 4 Acknowledge Block Error Checksum Error Protection Error 6 Acknowledge Block Error Checksum Error Protection Error A Acknowledge Block Er
109. Watchdog Timer V1 0 Cinfin eon XC886 888CLM Watchdog Timer WDTL Watchdog Timer Low Byte Reset Value 00 7 6 5 4 3 2 1 0 WDTI 7 0 rh Field Bits Type Description WDT 7 0 Watchdog Timer Current Value WDTH Watchdog Timer High Byte Reset Value 00 7 6 5 4 3 2 1 0 WDT 15 8 rh Field Bits Type Description WDT 15 8 Watchdog Timer Current Value User s Manual 9 7 V1 1 2007 05 Watchdog Timer V1 0 Cinfin eon XC886 888CLM Watchdog Timer WDTWINB Watchdog Window Boundary Count Reset Value 00 7 6 9 4 3 2 1 0 WDTWINB rw Field Bits Type Description WDTWINB 7 0 rw Watchdog Window Boundary Count Value This value is programmble Within this Window Boundary range from OOOOH to WDTWINB OOH the WDT cannot do a Refresh else it will cause a WDTRST to be asserted WDTWINB is matched to WDTH PMCONO Power Mode Control Register 0 Reset Value See 00 7 6 5 4 3 2 1 0 r wh rwh rw rw wh rw 0 The reset value for watchdog timer reset is 40 and the reset value for power down wake up reset is 20 Field Description WDTRST LL ka Timer Reset Indication Bit No WDT reset has occurred WDT reset has occurred 0 N 0 if read should be written with 0 User s Manual 9 8 V1 1 2007 05 Watchdog Timer V1 0 Cinfin eon XC886 888CLM Multiplication Division Unit 10 Multiplication Division Unit The Multiplication Division Unit MDU provides fast 16 bit multiplication 16 b
110. an on chip Monitor program factory stored into the non volatile Monitor ROM see Figure 17 1 Activating this program is the primary and basic OCDS reaction to recognized debug events The OCDS hardware ensures that the Monitor is always safely started and fully independent of the current system status at the moment when the debug action is taken Also interrupt requests optionally raised during Monitor entry will not disturb the firmware functioning User s Manual 17 6 V1 1 2007 05 OCDS V 1 0 Cinfin eon XC886 888CLM On Chip Debug Support Once started the Monitor runs with own stack and data memory see Monitor RAM in Figure 17 1 which guarantees that all of the core and memory resources will be found untouched when returning control back to the user program Therefore the OCDS debugging in XC886 888 is fully non destructive The functions of the XC886 888 Monitor include e Communication with an external Debugger via the JTAG interface e Read write access to arbitrary memory locations and Special Function Registers SFRs including the Instruction Pointer and password protected bits e Configuring OCDS and setting removing breakpoints e Executing a single instruction step mode Note Detailed descriptions of the Monitor program functionality and the JTAG communication protocol are not provided in this document 17 3 2 2 Activate the MBC pin The MBC pin can be driven actively low in reaction to debug events if re
111. analog inputs for the ADC P2 0 114 22 Hi Z CCPOSO 0 EXINT1_0 T12HR 2 TCK 1 CC61 3 ANO P2 1 15 23 Hi Z CCPOS1 0 EXINT2 0 T13HR 2 TDI 1 CC62 3 AN1 p22 16 24 CCPOS2 0 CTRAP 1 CC60 3 AN2 P2 3 49 27 HZ AN3 P24 20 28 fee tea AN4 P25 21 29 Hi Z AN5 P2 6 122 30 HIZ AN6 P2 7 25 33 HIZ AN7 Users Manual 1 12 Introduction V 1 1 XC886 888CLM Introduction Pin Definitions and Functions contd CCU6 Hall Input 0 External Interrupt Input 1 CCU6 Timer 12 Hardware Run Input JTAG Clock Input Input of Capture Compare channel 1 Analog Input 0 CCU6 Hall Input 1 External Interrupt Input 2 CCU6 Timer 13 Hardware Run Input JTAG Serial Data Input Input of Capture Compare channel 2 Analog Input 1 CCU6 Hall Input 2 CCU6 Trap Input Input of Capture Compare channel 0 Analog Input 2 Analog Input 3 Analog Input 4 Analog Input 5 Analog Input 6 Analog Input 7 V1 1 2007 05 Cinfin eon XC886 888CLM Introduction Table 1 3 Pin Definitions and Functions contd Symbol Pin Number Type Reset Function TQFP 48 64 State I O Port 3 Port 3 is an 8 bit bidirectional general purpose I O port It can be used as alternate functions for CCU6 UART1 Timer 21 and MultiCAN P3 0 35 43 CCPOS1_2 CCU6 Hall Input 1 CC60_0 Input Output of Capture Compare channel 0 RXDO1_1 UART1 Transmit Data Output P3 1 36 44 Hi Z CCPOSO 2 CCU6 Hall Input 0 CC61_ 2 Input Output of Capture Compare channe
112. any FIFO slave object When tagging the message objects of the FIFO as valid to start the operation of the FIFO then the base object must be tagged valid MSGVAL 1 first Before a Transmit FIFO becomes de installed during operation its slave objects must be tagged invalid MSGVAL 0 The Transmit FIFO uses the bit MOCTRn TXEN1 of all FIFO elements to select the actual message for transmission Transmit acceptance filtering evaluates TXEN1 for each message object and a message object can win transmit acceptance filtering only if its TXEN1 bit is set When a FIFO object has transmitted a message the hardware clears its TXEN1 bit in addition to standard transmit postprocessing clear TXRQ transmit interrupt etc and moves the CUR pointer to the next message object to be transmitted TXEN1 is set automatically by hardware in the next message object Thus TXEN1 moves along the Transmit FIFO structure like a token that selects the active element If bit field MOFCRn OVIE Overflow Interrupt Enable of the FIFO base object is set and the current pointer CUR becomes equal to MOFGPRn SEL a FIFO overflow interrupt request is generated The interrupt request is generated on interrupt node RXINP of the base object after postprocessing of the received frame Receive interrupts are still generated for the Transmit FIFO base object if bit RXIE is set User s Manual 15 37 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controlle
113. bit When the Protection Scheme is activated this bit cannot be written directly WKSEL 4 rw Wake up Reset Select Bit 0 Wake up without reset 1 Wake up with reset WKRS 5 rwh Wake up Indication Bit This bit can only be set by hardware and reset by software 0 No wake up occurred 1 Wake up has occurred 0 7 r Reserved Returns 0 if read should be written with 0 PCON Power Control Register Reset Value 00 7 6 9 4 3 2 1 0 rw r rw rw r rw Field Description IDLE ad Mode Enable Do not enter idle mode Enter idle mode 0 1 6 4 Reserved Returns 0 if read should be written with 0 User s Manual 8 6 V1 1 2007 05 Power Saving Modes V 1 0 Cinfin eon XC886 888CLM Power Saving Modes MODPISEL Peripheral Input Select Register Reset Value 00 7 6 5 4 3 2 1 0 o ee SRST r rw rw rw rw rw r rw Field Description URRISH ried Receive Input Select URRIS UART Receiver Input RXD_0 is selected UART Receiver Input RXD_1 is selected UART Receiver Input RXD_2 is selected Reserved EXINTOIS ee Interrupt 0 Input Select External Interrupt Inout EXINTO_O is selected External Interrupt Inout EXINTO_1 is selected 0 ee i 0 if read should be written with 0 PMCONT Power Mode Control Register 1 Reset Value 00 7 6 5 4 3 2 1 0 oe CDC DIS CAN DIS mounis T2 DIS CCU DIS SSC_DIS ADC _DIS r rw rw rw rw rw rw rw Field eid Description ADC _DIS a Disable Request Active high ADC is in normal operation default
114. by bits 0 to 1 For example a value of 01 in the DFlash_Bank1_H byte selects sector 8 of D Flash Bank 1 for erase Thus the sectors of different D Flash Banks can be erased at one time When Option C04 this mode is used to do a mass erase of all the sectors in the P Flash and the D Flash The header block has the following structure 1 When the bit contains a 1 the corresponding sector is selected 2 Bits 2 to 7 must be cleared to 0 User s Manual 18 13 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader The Header Block o Mode Data 5 bytes Crack ecksum Mode 4 Not Used Option 4 bytes CO Mode Data Description Not used The four bytes are not used and will be ignored Note Un wanted un selected bits should be cleared to 0 Note Itis not possible to erase select specified sectors for P Flash and D Flash with this mode 4 Two separate mode 4 commands have to be send Note When Flash is protected it cannot be erased Erase operation will fail if user tries to erase a protected and an unprotected sectors together 18 1 2 6 The Activation of Mode 6 Mode 6 is used to enable or disable Flash protection via the given user password The header block for this mode has the following structure The Header Block Mode Data 5 bytes heck ecksum Mod 6 User Password Not Used 1 byte 4 bytes Mode Data Description User Password This byte is given by user to enable or di
115. correct Hall event and the bit CHE is set which causes an interrupt lf it is required that the multi channel mode and the Hall pattern comparison work independently of timer T12 the delay generation by DTCO can be bypassed In this case timer T12 can be used for other purposes Bit field HSYNC defines the source for the sampling of the Hall input pattern and the comparison to the current and the expected Hall pattern bit fields The hall compare action can also be triggered by software by writing a 1 to bit SWHC The triggering sources for the sampling by hardware include e Any edge at one of the inputs CCPOSx x 0 2 e A113 compare match e A113 period match e A112 period match while counting up e A112 one match while counting down e A 112 compare match of channel 0 while counting up e A 112 compare match of channel O while counting down User s Manual 14 21 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 This correct Hall event can be used as a transfer request event for register MCMOUTS The transfer from MCMOUTS to MCMOUT transfers the new CURH pattern as well as the next EXPH pattern In case the sampled Hall inouts were neither the current nor the expected Hall pattern the bit WHE wrong Hall event is set which can also cause an interrupt and set the IDLE mode to clear MCMP modulation outputs are inactive To restart from IDLE the transfer request of MCMOUTS must be initiated
116. dominant to dominant and NFCRx CFSEL 100 recessive to recessive These delays indicate the time needed to represent a new bit value on the physical implementation of the CAN bus User s Manual 15 20 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 6 Message Acceptance Filtering This section describes the Message Acceptance Filtering capabilities of the MultiCAN module 15 1 6 1 Receive Acceptance Filtering When a CAN frame is received by a CAN node a unique message object is determined in which the received frame Is stored after successful frame reception A message object is qualified for reception of a frame if the following six conditions are fulfilled e The message object is allocated to the message object list of the CAN node by which the frame is received e Bit MOSTATn MSGVAL is set e Bit MOSTATn RXEN is set e Bit MOSTATn DIR is equal to bit RTR of the received frame lf bit MOSTATn DIR 1 transmit object the message object accepts only remote frames If bit MOSTATn DIR 0 receive object the message object accepts only data frames e If bit MOAMRn MIDE 1 the IDE bit of the received frame is evaluated in the following way If MOARn IDE 1 the IDE bit of the received frame must be set indicates extended identifier If MOARn IDE 0 the IDE bit of the received frame must be cleared indicates standard identifier If bit MOAMRn MIDE 0 the I
117. e On chip debug support 1 Kbyte of monitor ROM part of the 12 Kbyte Boot ROM User s Manual 1 4 V1 1 2007 05 Introduction V 1 1 Cinfin eon XC886 888CLM Introduction 64 bytes of monitor RAM e PG TQFP 48 or PG TQFP 64 pin packages e Temperature range 7 SAF 40 to 85 C SAK 40 to 125 C The block diagram of the XC886 888 is shown in Figure 1 2 XC886 888 Internal Bus 12 Kbyte Boot ROM P0 0 P0 7 XC800 Core 256 byte RAM 64 byte monitor oe SARI P1 0 P1 7 RAM CORDIC UART 1 1 5 Kbyte XRAM P2 0 P2 7 MDU SSC 24 32 Kbyte Flash or ROM2 WDT Timer 2 V AREF Clock Generator Ly 9 6 MHz On chip OSC i CCUG P3 0 P3 7 OCDS Timer 21 PLL MultiCAN P4 0 P4 7 P5 0 P5 7
118. e WDT prewarning has occurred e The PLL has lost the lock to the external crystal e Flash operation has completed program erase or aborted erase e VDD is below the prewarning voltage level 2 3 V e VDDP is below the prewarning voltage level 4 0 V if the external power supply is 5 0 V e Flash ECC error has occurred Figure 5 1 to Figure 5 5 give a general overview of the interrupt sources and nodes and their corresponding control and status flags Figure 5 6 gives the corresponding overview for the NMI sources User s Manual 5 1 V1 1 2007 05 Interrupt System V 1 0 Cinfineon Timer 0 Overflow TCON 5 ETO IENO 1 Timer 1 ED Overflow TCON 7 ay RY Receive rA UART Transmit SCON 1 IENO 4 oD nis mS HH TCON 1 ITO IENO 0 TCON O EXICONO 0 1 QU Ls tee ee TOONS Ey IT1 O IENO 2 TCON 2 EXINT1 EXICONO 2 3 Bit addressable J Request flag is cleared by hardware Figure 5 1 Interrupt Request Sources Part 1 User s Manual 5 2 Interrupt System V 1 0 XC886 888CLM Interrupt System ik a P riority Level 2ODdOCQH AOaHM eaxars 7 o Fv V1 1 2007 05 infin eon XC886 888CLM Interrupt System Timer 2 Overflow TF2 T2_T2CON 7 S EXEN2 T2_T2CON 6 T2_T2CON 3 EDGES ES EL Normal Divider T2_T2MOD 5 Overflow EOFSYN Synch Byte EOFSYN FDCON 4 gt Synch Byte Eror ERRSYN FDCON 5 Priority Level MultiCAN_O CANSRCO IRCON2 0 ADC_0 AD
119. ees bos noo bees ou ohh eeehn anes pene ees 14 3 14 1 1 1 Timer Configuration 0 naaa aaa ce ees 14 4 14 1 1 2 COUnUNG RUIES sx usca0ccnentuereekad eenabacub es on eeun es 14 4 User s Manual l 6 V1 1 2007 05 Cinfin eon XC886 888CLM Table of Contents Page 14 1 1 3 SWINGING RUGS 2 2242544 2442e e44d2e8 SEENE Ri eiee ERRA 14 5 14 1 1 4 Compare Mode of 112 1 ee 14 6 14 1 1 5 Duty Cycle of 0 and 100 ce es 14 8 14 1 1 6 Dead time Generation 0 0 0 ce ees 14 8 14 1 1 7 Capture Mode aanne eens 14 9 14 1 1 8 Single Shot Mode 0 ccc eee ees 14 10 14 1 1 9 Hysteresis Like Control Mode 0000 c cece eee eee 14 10 14 1 2 TMr WIS Scag Gua acne ue Hye ee Gee eed RO Hao ee HO OE 14 12 14 1 2 1 Timer Configuration n aa aaa 0c eee 14 12 14 1 2 2 Compare Mode 2 c ccc eee eens 14 13 14 1 2 3 Single Shot Mode 0 ccc eee ees 14 13 14 1 2 4 synchronization of T13 to 112 1 ee 14 13 14 1 3 Modulation Control 0 0 0 0 0 cee eee 14 15 14 1 4 Hap Hand sh2necee 22 oe unease udwst en neeeoe cane oa eee 14 17 14 1 5 Multi Channel Mode 0 0 0 cc eee 14 19 14 1 6 Hall Sensor Mode 0 ccc eee 14 21 14 1 6 1 Sampling of the Hall Pattern 0 0 0 00 cece 14 21 14 1 6 2 Brushless DC Control 0 0 0 0 ccc eens 14 22 14 1 7 Interrupt Generation 0 0 0 0 ce ees 14 25 14 1 8 Low Power Mode 0 000 cece eee eee eee eens
120. entered if no valid password is installed and data at memory address 0000 equals Zero 2 OSC is bypassed in MultiCAN BSL mode 3 Normal user mode with standard JTAG TCK TDI TDO pins for hot attach purpose h O Note The boot options are valid only with the default set of UART and JTAG pins User s Manual 7 8 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management 7 2 4 Register Description Table 7 3 Reset Values of Register PMCONO Reset Source Reset Value Power on Reset Hardware Reset Brownout Reset 0000 0000 Watchdog Timer Reset 0100 0000 Power down Wake up Reset 0010 0000 PMCONO Power Mode Control Register 0 Reset Value See Table 7 3 7 6 5 4 3 2 1 0 r rwh rwh rw rw rwh rw Field Description WS COR 0 Wake Up Source Select 00 No wake up is selected 01 Wake up source RXD falling edge trigger is selected 10 Wake up source EXINTO falling edge trigger is selected 11 Wake up source RXD falling edge trigger or EXINTO falling edge trigger is selected WKSEL Wake Up Reset Select Bit 0 Wake up without reset 1 Wake up with reset WKRS 5 rwh Wake Up Indication Bit 0 No wake up occurred 1 Wake up has occurred This bit can only be set by hardware and reset by software User s Manual 7 9 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management Field Bits Type Descri
121. event which is a reference to the actual soeed CC61 can be used for a phase delay function between hall event and output switching CC62 can act as a time out trigger if the expected hall event comes too late The value 1000 must be programmed to MSELO MSEL1 and MSEL2 if the hall signals are used In this mode the contents of timer T12 are captured in CC60 and T12 is reset after the detection of a valid hall event In order to avoid noise effects the dead time counter channel 0 is started after an edge has been detected at the hall inputs On reaching the value of 000001 the hall inputs are sampled and the pattern comparison is done 1001 Hysteresis like control mode with dead time generation The negative edge of the CCPOSx input signal is used to reset bit CC6nST As a result the output signals can be switched to passive state immediately and switch back to active state with dead time if the CCPOSx is high and the bit CC6nST is set by a compare event Table 14 7 Multi Input Capture Modes Description 1010 The timer value of T12 is stored in CC6nR after a rising edge at the input pin CC6n The timer value of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx 1011 The timer value of T12 is stored in CC6nR after a falling edge at the input pin CC6n The timer value of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx User s Manual 14 41 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM
122. field Whenever NFCRx CFC is updated in bit timing analysis mode the bit NFCRx CFCOV is set to indicate the CFC update event If NFCRx CFCIE is set an interrupt request can be generated see Figure 15 5 Automatic Baud Rate Detection For automatic baud rate detection the time between the observation of subsequent dominant edges on the CAN bus must be measured This measurement is automatically performed if bit field NFCRx CFSEL 000 With each dominant edge monitored on the CAN receive input line the time measured in fean clock cycles between this edge and the most recent dominant edge Is stored in the NFCRx CFC bit field User s Manual 15 19 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Synchronization Analysis The bit time synchronization is monitored if NFCRx CFSEL 010 The time between the first dominant edge and the sample point is measured and stored in the NFCRx CFC bit field The bit timing synchronization offset may be derived from this time as the first edge after the sample point triggers synchronization and there is only one synchronization between consecutive sample points Synchronization analysis can be used for example for fine tuning of the baud rate during reception of the first CAN frame with the measured baud rate Driver Delay Measurement The delay between a transmitted edge and the corresponding received edge is measured when NFCRx CFSEL 011
123. field MCMP are used to select the outputs that may become active If the multi channel mode is enabled bit MCMEN 1 only those outputs that have a 1 at the corresponding bit positions in bit field MCMP may become active This bit field has its own shadow bit field MCMPS which can be written by software The transfer of the new value in MCMPS to the bit field MCMP can be triggered by and synchronized to T12 or T13 events This structure permits the software to write the new value which is then taken into account by the hardware at a well defined moment and synchronized to a PWM period This avoids unintended pulses due to unsynchronized modulation sources 112 T13 SW SW write by software SEL 6 Correct MCMPS Hall Event Tom T13pm se 7 i T12pm RHR iihi KA T120m ai z T12c1cm no action 6 T12zm to modulation selection JL write to T13zm bitfield direct shadow transfer MCMPS interrupt with W STRMCM T D E CCU6_mod_sync_int Figure 14 15 Modulation Selection and Synchronization Figure 14 15 shows the modulation selection for the multi channel mode The event that triggers the update of bit field MCMP is chosen by SWSEL If the selected switching event occurs the reminder flag R is set This flag monitors the update request and it is automatically reset when the update takes place In order to synchronize the update of MCMP to a PWM generated by T12 or T13 bit field SWSYN allows the selection of the User s
124. for i 0 1 2 15 and atanh 2 for User s Manual 11 6 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfine on XC886 888CLM CORDIC Coprocessor i 1 2 15 such that angles in the range 2 2 9 1 2 are represented by integer values ranging 2 2 1 Therefore Z data is limited not considering domain of convergence to represent angles 2 2 1 2 z for these CORDIC functions Any calculated value of Z outside of this range will result in overflow error e For linear function the Z data is always handled as signed fraction S4 15 accessible as 4 11 in the form signed 4Q16 The emulated LUT is actually a shift register that holds data in the form 1 15 which gives the real value of 2 Therefore regardless of the domain of convergence Z data is logically only useful for values whose magnitude is smaller than 16 Overflow error is indicated by the CD_STATC ERROR bit e The MPS setting has no effect on Z data User must ensure proper initialization of Z initial data to prevent overflow and incorrect result data e The CORDIC Coprocessor is designed such that with correct user setting of MPS gt 1 there is no internal overflow of the X and Y data and the read result data is complete However note that in these cases the higher the MPS setting the lower the resolution of the result data due to loss of LSB bit s e The hyperbolic rotation mode is limited in terms of result accuracy in that initial Y da
125. for the analog components fapcp IS input clock for the digital part This clock is used for the arbiter defines the duration of an arbitration round and other digital control structures e g registers and the interrupt generation The internal clock for the analog part fapc is limited to a maximum frequency of 10 MHz Therefore the ADC clock prescaler must be programmed to a value that ensures fang does not exceed 10 MHz The prescaler ratio is selected by bit field CTC in register GLOBCTR A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required Condition f apc lt 10 MHz where t ang _ f Figure 16 2 Clocking Scheme User s Manual 16 3 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter For module clock fapc 24 MHz the analog clock fapc frequency can be selected as shown in Table 16 1 Table 16 1 fapnc rreueney Selection AS fapc cannot exceed 10 MHz bit field CTC should not be set to 00 when fang is 24 MHz During slow down mode where fang may be reduced to 12 MHz 6 MHz etc CTC can be set to 00 as long as the divided analog clock fapc does not exceed 10 MHz However it is important to note that the conversion error could increase due to loss of charges on the capacitors if fanc becomes too low during slow down mode 16 2 1 Conversion Timing The analog to digital conversion procedure consists of the following phases e Sy
126. functionality required for software development and debugging of XC800 based systems The OCDS design is based on these principles e Use the built in debug functionality of the XC800 Core e Add a minimum of hardware overhead e Provide support for most of the operations by a Monitor Program e Use standard interface to communicate with the Host a Debugger 17 1 Features The main debug features supported are e Set breakpoints on instruction address and on address range within the Program Memory e Set breakpoints on Internal RAM address range e Support unlimited software breakpoints in Flash RAM code region e Process external breaks via JTAG and upon activating a dedicated pin e Step through the program code User s Manual 17 1 V1 1 2007 05 OCDS V 1 0 Cinfin eon XC886 888CLM On Chip Debug Support 17 2 Functional Description The OCDS functional blocks are shown in Figure 17 1 The Monitor Mode Control MMC block at the center of OCDS system brings together control signals and supports the overall functionality The MMC communicates with the XC800 Core primarily via the Debug Interface and also receives reset and clock signals After processing memory address and control signals from the core the MMC provides proper access to the dedicated extra memories a Monitor ROM holding the firmware code and a Monitor RAM for work data and Monitor stack The OCDS system is accessed through the JTAG which is an interfa
127. inject repeat mode is selected PRIO1 2 rw Priority of Request Source 1 This bit defines the priority of the parallel request source 1 Oz Low priority 1 High priority CSM1 3 rw Conversion Start Mode of Request Source 1 This bit defines the conversion start mode of the parallel request source 1 Os The wait for start mode is selected 1 The cancel inject repeat mode is selected ARBM 4 rw Arbitration Mode This bit defines which arbitration mode is selected On Permanent arbitration default 1 Arbitration started by pending conversion request User s Manual 16 36 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Field Description ASENx a 6 Arbitration Slot x Enable x 0 1 Each bit enables an arbitration slot of the arbiter round ASENO enables arbitration slot 0 ASEN1 enables slot 1 lf an arbitration slot is disabled a pending conversion request of a request source connected to this slot is not taken into account for arbitration Os The corresponding arbitration slot is disabled 1g The corresponding arbitration slot is enabled 0 HN ee T O if read should be written with 0 User s Manual 16 37 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 7 3 External Trigger Control Register Register ETRCR contains bits that select the external trigger input signal source and enable synchronization of the external trigger input ETRCR External Trigger Co
128. instructions to six e g 1 byte 4 cycle instructions Table 2 1 CPU Instruction Timing Mnemonic Hex Code Bytes Number of feck Cycles XC886 888 8051 1 ws with parallel read ARITHMETIC ADD A dir 25 2 2 J6 4 12 ADDC A dir 35 2 2 6 J4 12 Users Manual Processor Architecture V 1 0 Pe O V1 1 2007 05 Cinfineon Table 2 1 Mnemonic DEC Rn DEC dir DEC Ri INC DPTR MUL AB DIV AB DAA LOGICAL ANL A Rn ANL A dir ANL A Ri ANL A data ANL dir A ANL dir data ORL A Rn ORL A dir ORL A Ri ORL A data ORL dir A ORL dir data XRL A Rn XRL A dir XRL A Ri XRL A data XRL dir A XRL dir data CLRA CPLA User s Manual CPU Instruction Timing cont d Hex Code 15 O1 O1 On On ri 7 On On N T i i p i NO O D el NO O1 O1 Q Ol h O XC886 888 4 Bytes Number of foc Cycles 1 T T XC886 888CLM Processor Architecture 1 ws with parallel read NO O D as NO D as NO O O oe NO AIN i NO A gt n o iN TI T r T NO O x EN a NO i ae KN N p NO O iN h NO 4 il Processor Architecture V 1 0 i i NO 0 0 T T oe as l NO V1 1 2007 05 Cinfin eon XC886 888CLM Processor Architecture Table 2 1 CPU Instruction Timing cont d Mnemonic Hex Code Bytes Number of foc Cycles ro
129. interrupt is vectored to this delay guarantees that changes of the interrupt status can be observed by the CPU The polling cycle is repeated with each machine cycle and the values polled are the values that were present at phase 2 of the previous machine cycle Note that if any interrupt flag is active but was not responded to for one of the conditions already mentioned or if the flag is no longer active at a later time when servicing the interrupt node the corresponding interrupt source will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate service routine In some cases hardware also clears the flag that generated the interrupt while in other cases the flag must be cleared by the user s software The hardware generated LCALL pushes the contents of the Program Counter PC onto the stack but it does not save the PSW and reloads the PC with an address that depends on the source of the interrupt being vectored to as shown in the Table 5 1 Program execution returns to the next instruction after calling the interrupt when the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and rel
130. interrupt source is connected to the same interrupt node pointer in the interrupt node pointer register the requests are combined to one common line Interrupt TL Interrupt Event Interrupt Enable to CANSRCO to CANSRC1 Other Interrupt Sources on the same INP to CANSRC7 MutiCAN_int_struct Figure 15 3 General Interrupt Structure User s Manual 15 6 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller 15 1 2 Clock Control Table 15 1 indicates the minimum operating frequencies in MHz for fean that are required for a baud rate of 1 Mbit s for the active CAN nodes If less baud rate is desired the values can be scaled linearly e g for a maximum of 500 kbit s 50 of the indicated value are required The values imply that the CPU executes maximum access to the MultiCAN module The values may contain rounding effects Table 15 1 Minimum Operating Frequencies MHz Number of Allocated Message with 1 CAN Node with 2 CAN Nodes Objects Active Active 32 Message Objects 15 23 1 Only those message objects that are allocated to a CAN node must be taken into account The unallocated message objects have no influence on the minimum operating frequency User s Manual 15 7 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 3 CAN Node Control Each CAN node ma
131. is automatically performed with each reset of the MultiCAN module but with the exception that all message object registers are reset User s Manual 15 49 V1 1 2007 05 MultiCAN V1 0 Cinfineon XC886 888CLM Controller Area Network MultiCAN Controller Table 15 7 Panel Commands cont d PANCMD PANAR2 PANAR1 Command Description 024 Argument List Index Message Object Number Result Message Object Number 03h Argument List Index Result Bit 7 ERR Bit 6 0 undefined 04 Argument Destination Object Number User s Manual MultiCAN V1 0 Argument Argument Source Object Number 15 50 Static Allocate Allocate message object to a list The message object is removed from the list that it currently belongs to and appended to the end of the list given by PANAR2 This command is also used to deallocate a message object In this case the target list is the list of unallocated elements PANAR2 0 Dynamic Allocate Allocate the first message object of the list of unallocated objects to the selected list The message object is appended to the end of the list The message number of the message object is returned in PANAR1 An ERR bit bit 7 of PANAR2 reports the success of the operation 0 SUCCESS 1 The operation has not been performed because the list of unallocated elements was empty Static Insert Before Remove a message object source object from the list that it
132. mapping 3 3 4 3 Data memory 3 4 Data pointer 2 3 Data reduction 16 19 Counter 16 20 Debug 17 3 Events 17 3 Debug suspend control 17 7 D Flash 4 2 4 3 DFLASHEN 3 9 Digital input clock 16 3 Direct feed through 6 4 Division operation 10 3 Document Acronyms 1 19 Terminology 1 19 Textual convention 1 8 Textual conventions 1 18 Dynamic error detection 4 12 E EEPROM emulation 4 5 Embedded voltage regulator 7 1 Features 7 2 Low power voltage regulator 7 2 Main voltage regulator 7 2 Threshold voltage levels 7 2 Enter BSL mode 18 1 Error Correction Code 4 12 Extended operation 2 5 External breaks 17 6 Break now 17 6 External data memory 3 5 External oscillator 7 11 7 13 F Fast LIN BSL 18 24 Flash 4 1 Endurance 4 5 Erase mode 4 11 User s Manual XC886 888CLM Index Non volatile 4 1 Operating modes 4 11 Power down mode 4 11 Program mode 4 11 Ready to read mode 4 11 Sector 4 4 Flash devices 3 1 Flash memory protection 3 6 Flash program memory 3 1 Flash Timer NMI 4 16 4 17 G Gate disturb 4 9 GPIO 6 1 6 6 H Hall sensor mode Actual hall pattern 14 21 Block commutation 14 23 Brushless DC 14 21 14 22 Correct hall event 14 21 Expected Hall pattern 14 21 Hall pattern 14 21 Modulation pattern 14 21 Noise filter 14 21 Hamming code 4 12 Hardware breakpoints 17 4 Hardware reset 7 5 High impedance 6 2 Idle mode 7 16 8 2 In Application Programming 4 15 Aborting Flash erase 4 18 Flash bank read
133. may be disabled by resetting the ANON bit This causes the generation of fapc to be stopped and results in a reduction in power consumption Conversions are possible only by enabling the analog part ANON 1 again The wake up time is approximately 100 ns Refer to Section 16 7 1 for register description of disabling the ADC analog part lf the ADC functionality is not required at all it can be completely disabled by gating off its clock input fanc for maximal power reduction This is done by setting bit ADC_DIS in register PMCON1 Refer to Chapter 8 1 4 for details on peripheral clock management PMCON1 Power Mode Control Register 1 B5 Reset Value 00 7 6 J 4 3 2 1 0 cbcp can pis mup Te DIS CCU DIS 86 015 ADC pis r rw rw rw rw rw rw rw Field Description ADC _DIS Disable Request Active high ADC is in normal operation default Request to disable the ADC 0 Reserve ieee O if read should be written with 0 User s Manual 16 7 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 Functional Description The ADC module functionality includes e Two different conversion request sources Sequential and parallel with independent registers The request sources are used to trigger conversions due to external events synchronization to PWM signals sequencing schemes etc e An arbiter that regularly scans the request sources to find the channel with the highest priority for the
134. n has been successfully transmitted the CAN frame counter value NFCRx CFC is then copied to CFCVAL User s Manual 15 85 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller The Message Object Function Control Register MOFCRhn contains bits that select and configure the function of the message object It also holds the CAN data length code MOFCRnhn n 0 31 Message Object n Function Control Register Reset Value 0000 0000 31 30 29 28 2 26 25 24 23 22 21 20 19 18 17 16 Ce aren oo rw rwh rw srw w w w mw w rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Description MMC 3 0 rw Message Mode Control MMC controls the message mode of message object n 0000 Standard Message Object 0001 Receive FIFO Base Object 0010 Transmit FIFO Base Object W 0011 Transmit FIFO Slave Object 0100 Gateway Source Object Others Reserved GDFS r Gateway data frame Send 0 TXRQ is unchanged in the destination object 1 TXRQ is set in the gateway destination object after the transfer of a data frame from the gateway source to the gateway destination object Applicable only to a gateway source object ignored in other nodes User s Manual 15 86 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Description rw Identifier Copy 0 The identifier of the gateway source object is not copied 1 The identifier of the gateway source
135. nodes A powerful command driven list controller manages the organization of the list structure and ensures consistency of the list Message FIFOs are based on the list structure and can easily be scaled in size during CAN operation Static allocation commands offer compatibility with TwinCAN applications that are not list based e Advanced interrupt handling User s Manual 15 2 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Up to 8 interrupt output lines are available Interrupt requests can be individually routed to one of the 8 interrupt output lines Message post processing notifications can be combined flexibly into a dedicated register field of 64 notification bits User s Manual 15 3 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 MultiCAN Kernel Functional Description This section describes the functionality of the MultiCAN module 15 1 1 Module Structure Figure 15 2 shows the general structure of the MultiCAN module CAN Bus 0 CAN Bus 1 CAN CAN Node 0 Message Controller Interrupt Control o Logic Address Decoder N7 interrupt control bus interface MultiCAN_Blockdiag_x2 Figure 15 2 MultiCAN Block Diagram CAN Nodes Each CAN node consists of several sub units e Bitstream Processor The Bitstream Processor performs data remote error and overload frame p
136. number and some additional control information As a result the order in which the channels are to be converted is freely programmable without restrictions in the sequence The additional control information is used to enable the request source interrupt when the requested channel conversion is completed and to enable the automatic refill process A sequential source consists of 4 queue stages one backup stage QBURO and a mode control register QMRO The backup stage stores the information about the latest conversion requested after it has been aborted If the backup register contains an aborted request V 1 it is treated before the entries in the queue stage This implies that only the bit V in the backup register is cleared when the requested conversion is Started If the bit V in the backup register is not set the bit V in the queue stage 0 is reset when the requested conversion is started The request source can take part in the source arbitration if the backup stage or queue stage contains a valid request V 1 Note Of the 4 queue stages only the register queue 0 can be read the register of the other stages are internal User s Manual 16 11 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter ey CPU W queue stage q 1 intermediate queue stages queue stage 1 V Queue stage 0 CHNR RF ENSI RF ENSI start of abort of conversion conversion backup stage CHNR RF
137. number of elements in the list m SIZE number of list elements 1 EMPTY 24 rh List Empty Indication 0 At least one message object is allocated to list m 1 No message object is allocated to the list m List m is empty User s Manual 15 54 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Field Bits Type Description 0 31 25 r Reserved ead as 0 should be written with O User s Manual 15 55 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Message Notifications When a message object n generates an interrupt request upon the transmission or reception of a message then the request is routed to the interrupt output line selected by the bit field MOIPRn TXIPND or MOIPRn RXIPND of the message object n As there are more message objects than interrupt output lines an interrupt routine typically processes requests from more than one message object Therefore a priority selection mechanism is implemented in the MultiCAN module to select the highest priority object within a collection of message objects The Message Pending Register MSPNDk contains the pending interrupt notification of list m MSPNDk k 0 1 Message Pending Register k Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rwh PND rwh Field Bits Type Description PND 31 0 irwh Message Pending When a message interru
138. on XC886 888CLM Memory Organization 3 3 2 External Data Memory The 1 5 Kbyte XRAM is mapped to both the external data memory area and the program memory area It can be accessed using both MOVX and MOVC instructions The MOVX instructions for XRAM access use either 8 bit or 16 bit indirect addresses While the DPTR register is used for 16 bit addressing either register RO or R1 is used to form the 8 bit address The upper byte of the XRAM address during execution of the 8 bit accesses is defined by the value stored in register XADDRH Hence the write instruction for setting the higher order XRAM address in register XADDRH must precede the MOV instruction XADDRH On Chip XRAM Address Higher Order Reset Value FO 7 6 5 4 3 2 1 0 rw Field Bits Type Description ADDRH 7 0 rw Higher Order of On chip XRAM Address This value is from FO to F5 for the XC886 888 User s Manual 3 5 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization 3 4 Memory Protection Strategy The XC886 888 memory protection strategy includes e Read out protection The user is able to protect the contents in the Flash for Flash devices and ROM for ROM devices memory from being read Flash protection is enabled by programming a valid password 8 bit non zero value via BSL mode 6 ROM protection is fixed with the ROM mask and is always enabled e Flash program and erase protection This
139. opcode without wait state next instruction __ Read next opcode one wait state next instruction c 1 byte 2 cycle instruction e g MOVX Figure 2 2 CPU Instruction Timing Instructions are 1 2 or 3 bytes long as indicated in the Bytes column of Table 2 1 For the XC886 888 the time taken for each instruction includes e decoding executing the fetched opcode e fetching the operand s for instructions gt 1 byte e fetching the first byte opcode of the next instruction due to XC886 888 CPU pipeline User s Manual 2 8 V1 1 2007 05 Processor Architecture V 1 0 Cinfine on XC886 888CLM Processor Architecture Note The XC886 888 CPU fetches the opcode of the next instruction while executing the current instruction Table 2 1 provides a reference for the number of clock cycles required by each instruction The first value applies to fetching operand s and opcode from fast program memory e g Boot ROM and XRAM without wait state The second value applies to fetching operand s and opcode from slow program memory e g Flash with one wait State inserted The instruction time for the standard 8051 processor is provided in the last column for performance comparison with the XC886 888 CPU Even with one wait state inserted for each byte of operand opcode fetched the XC886 888 CPU executes instructions faster than the standard 8051 processor by a factor of between two e g 2 byte 1 cycle
140. or data Figure 3 3 Flash to ROM Compatibility The lower address spaces 60004 6FFF and 7000 7FFF is to be used as program code while the higher address spaces A000 AFFF and BOOO BFFF is to be used as data However if a Flash to ROM device migration is considered user should not use the four bytes address space from 7FFC to 7FFF in the Flash device For example if the Flash device is used as a prototype to develop the 32 Kbyte less four bytes program code later stored in 32 Kbyte ROM memory for the ROM device the two User s Manual 3 3 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization D Flash banks need to be used for program code based on address spaces 6000 6FFF and 7000 7FFB This allows program code developed using the Flash device to be migrated to the ROM device without any changes In the case that only 28 Kbytes of program code later stored in 32 Kbyte ROM memory is required for the ROM device with the available D Flash bank in the ROM device used for data then D Flash Bank 1 in the Flash device should be used for program code development based on address space 6000 6FFF while D Flash Bank 0 is used for data based on address space AO00 AFFF This way migration of program code from the Flash to ROM device can be performed without any changes 3 2 Program Memory The performance of the CPU is optimized with a dedic
141. request request polled sampled last cycle of current instruction 1 instruction at interrupt vector toma ee EW a Interrupt response time 6 x machine cycle Figure 5 10 Interrupt Response Time for Condition 2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 A Interrupt request sampled active 2 cycle currgnt instruction to k 4 cycle next instruction Interrupt Interrupt reques MUL or DIV request polled sampled RETI or write ple gt ple k interrupt requesd Interrupt polled ccess to interru D ane 1 instruction at request last cycle of interrupt vector sampled current instruction l l pl Interrupt response time 8 x machine cycle Figure 5 11 Interrupt Response Time for Condition 3 Thus in a single interrupt system the response time is between three machine cycles and less than nine machine cycles if wait states are not considered When considering wait states the interrupt response time will be extended depending on the user instructions except the hardware generated LCALL being executed during the interrupt response time shaded region in Figure 5 10 and Figure 5 11 User s Manual 5
142. reset to indicate the sample phase is over while the BUSY flag continues to be asserted The BUSY flag is deasserted only at the end of the conversion phase with the corresponding source interrupt of the source that started the conversion asserted Write Result Phase typ At the end of the conversion phase the corresponding channel interrupt of the converted channel is asserted three fapc periods later after the limit checking has been performed The result interrupt is asserted once the conversion result has been written into the target result register User s Manual 16 5 V1 1 2007 05 ADC V 1 0 Cinfine on XC886 888CLM Analog to Digital Converter Total Conversion Time fcony The total conversion time synchronizing sampling charge redistribution toony Is given by tconv tanc x 1 r x 3 n STC 16 2 where r CTC 2 for CTC 00p 01 or 103 r 32 for CTC 11g CTC Conversion Time Control STC Sample Time Control n 8 or 10 for 8 bit and 10 bit conversion respectively tanc 1 fapc Example STC 00 CTC 01g fade 26 7 MHZ n 10 tconv tapcX 1 3 x 3 10 0 1 5 us User s Manual 16 6 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 3 Low Power Mode The ADC module may be disabled either partially or completely when no conversion is required in order to reduce power consumption The analog part of the ADC module
143. routine is entered When Timer 0 operates in mode 3 the Timer 1 control bits TR1 TF1 and ET1 are reserved for THO see Section 13 1 2 4 External Control In addition to pure software control the timers can also be enabled or disabled through external port control When external port control is used SFR EXICONO must first be configured to bypass the edge detection circuitry for EXINTx to allow direct feed through When the timer is enabled TCON TRx 1 and TMOD GATEx is set the respective timer will only run if the core external interrupt EXINTx 1 This facilitates pulse width measurements However this is not applicable for Timer 1 in mode 3 lf TMOD GATEx is cleared the timer reverts to pure software control User s Manual 13 2 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 1 2 Timer Modes Timers 0 and 1 are fully compatible and can be configured in four different operating modes as shown in Table 13 1 The bit field TxM in register TMOD selects the operating mode to be used for each timer In modes 0 1 and 2 the two timers operate independently but in mode 3 their functions are specialized Table 13 1 Timer 0 and Timer 1 Modes Mode Operation 0 13 bit timer counter The timer is essentially an 8 bit counter with a divide by 32 prescaler This mode is included solely for compatibility with Intel 8048 devices 1 16 bit timer counter The timer registers TLx and THx are concatenated to form a
144. routing Figure 16 14 Channel Interrupt Overview The limit checking unit uses two boundaries BOUNDO and BOUND1 to compare with the conversion result With these two boundaries the conversion result space is split into three areas e Area The conversion result is below both boundaries e Area Il The conversion result is between the two boundaries or is equal to one of the boundaries e Area Ill The conversion result is above both boundaries After a conversion has been completed a channel interrupt can be triggered according to the following conditions selected by the limit check control bit field LCC e LCC 000 No trigger the channel interrupt is disabled e LCC 001 A channel interrupt is generated if the conversion result is not in area l e LCC 010 A channel interrupt is generated if the conversion result is not in area Il e LCC 011 Achannel interrupt is generated if the conversion result is not in area Ill e LCC 100 A channel interrupt is always generated regardless of the boundaries e LCC 101 A channel interrupt is generated if the conversion result is in area l e LCC 110 A channel interrupt is generated if the conversion result is in area Il e LCC 111 A channel interrupt is generated if the conversion result is in area Ill The channel specific interrupt node pointer CHINPx x 0 7 selects the service request output SR 1 0 that will be activated upon a channel interrupt trigger See Fi
145. s Manual l 1 V1 1 2007 05 Cinfineon Table of Contents 3 5 5 5 3 5 5 6 3 9 9 3 9 9 8 3 9 9 9 3 9 5 10 3 5 5 11 3 9 9 12 3 9 9 13 3 9 9 14 3 6 3 6 1 3 6 2 3 6 3 3 6 4 4 4 1 4 2 4 3 4 4 4 5 4 6 4 6 1 4 4 8 4 8 1 4 8 2 4 8 3 4 8 4 4 8 5 4 8 6 5 5 1 5 1 1 5 1 2 5 1 2 1 5 2 5 3 5 4 9 9 5 6 WDT Registers Port Registers ADC Registers Timer 2 Registers Timer 21 Registers CCU6 Registers UART1 Registers SSC Registers MultiCAN Registers OCDS Registers Boot ROM Operating Mode User Mode 005 Bootstrap Loader Mode OCDS Mode User JTAG Mode Flash Memory Flash Memory Map Flash Bank Sectorization Parallel Read Access of P Flash Wordline Address Operating Modes Error Detection and Correction Flash Error Address Register In System Programming In Application Programming Flash Programming Flash Erasing Aborting Flash Erase Flash Bank Read Status P Flash Parallel Read Enable Disable Get Chip Information Interrupt System Interrupt Structure Interrupt Structure 1 Interrupt Structure 2 System Control Register 0 Interrupt Source and Vector Interrupt Priority Interrupt Handling Interrupt Response Time Interrupt Registers User s Manual XC886 888CLM V1 1 2007 05 Cinfin eon XC886 888CLM Table of Contents Page 5 6 1 Interrupt Node Enable Registers 0 000 5 17
146. same number of bits for decimal place The Z data is always handled as integer based on the normalization factor for circular or hyperbolic function In case of linear function accessible Z data is a real number with User s Manual 11 8 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfin eon XC886 888CLM CORDIC Coprocessor fixed input and result data form of 4 11 signed 4Q16 which is a fraction with 11 decimal places Refer to Chapter 11 2 3 for details on data normalization 11 2 6 Accuracy of CORDIC Coprocessor Each CORDIC calculation involves a fixed number of 16 CORDIC iterations starting from iteration 0 The hyperbolic function is special in this respect in that it starts from iteration 1 with repeat iterations at defined steps The addressable data registers are 16 bits wide while the internal kernel X and Y data registers used for calculation are each 26 bits wide 24 data bits plus 2 overflow bits and internal kernel Z data register is 21 bits wide 20 data bits plus 1 overflow bit For more details on the data form of the LUTs refer to Chapter 11 3 1 and Chapter 11 3 2 For input data values within the specified useful domain see Table 11 2 the result of each calculation of the CORDIC Coprocessor is guaranteed to converge although the accuracy is not fixed per data form in each operating mode The accuracy is a measure of the magnitude of the difference between the result data and the expected data from a high ac
147. see Table 14 5 1000 Hall Sensor mode see Table 14 6 In order to enable the hall edge detection all three MSEL6x must be programmed to Hall Sensor mode 1001 Hysteresis like mode see Table 14 6 101X Multi Inout Capture modes see Table 14 7 11XX Multi Inpout Capture modes see Table 14 7 User s Manual 14 43 V1 1 2007 05 CCU6B V 1 0 Cinfine on XC886 888CLM Capture Compare Unit 6 T12MSELH T12 Capture Compare Mode Select Register High Reset Value 00 7 6 5 4 3 2 1 0 D rw rw rw Field Description 101X Multi Inout Capture modes see Table 14 7 MSEL62 pe 0 Capture Compare Mode Selection These bit fields select the operating mode of the three timer T12 capture compare channels Each channel n 0 1 2 can be programmed individually either for compare or capture operation according to 0000 Compare outputs disabled pins CC6n and COUTE6n can be used for I O No capture action 0001 Compare output on pin CC6n pin COUTE6n can be used for I O No capture action 0010 Compare output on pin COUTEn pin CC6n can be used for I O No capture action 0011 Compare output on pins COUT6n and CC6n 01XX Double Register Capture modes see Table 14 5 1000 Hall Sensor mode see Table 14 6 In order to enable the hall edge detection all three MSEL6x must be programmed to Hall Sensor mode 1001 Hysteresis like mode see Table 14 6 11XX Multi Inout Capture modes see Table 14 7 User s Manual 14 44 V1 1 2007 05
148. shown in Table 7 6 divided by the K factor 7 1 1 f 1 SYS VCObase K User s Manual 7 13 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfine on XC886 888CLM Power Supply Reset and Clock Management Prescaler Mode VCO Bypass Operation In VCO bypass operation the system clock is derived from the oscillator clock divided by the P and K factors 7 2 foye fosc Xx TT SYS OSC Dy K PLL Mode The system clock is derived from the oscillator clock divided by the P factor multiplied by the N factor and divided by the K factor 7 3 f f x SYS OSC PxK Table 7 4 shows the settings of bits OSCDISC and VCOBYP for different clock mode selection Table 7 4 Clock Mode Selection OSCDISC VCOBYP Clock Working Modes 0 PLL Mode 0 Prescaler Mode 1 C 1 PLL Base Mode PLL Base Mode Note When oscillator clock is disconnected from PLL the clock mode is PLL Base mode regardless of the setting of VCOBYP bit In normal running mode the system works in the PLL mode User s Manual 7 14 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfine on XC886 888CLM Power Supply Reset and Clock Management For different source oscillator the selection of output frequency fsys 96 MHz is shown in Table 7 5 Table 7 5 System frequency f 96 MHz For the XC886 888 the value of P is fixed to 1 In order to obtain the required fsys the value of N and K can be selected by bits NDIV and KDIV r
149. source and destination of data transfers and control the arithmetic logic unit ALU processing User s Manual 2 1 V1 1 2007 05 Processor Architecture V 1 0 Cinfin eon XC886 888CLM Processor Architecture Internal Data Memory Core SFRs Register Interface External Data Memory External SFRs 16 bit Registers amp Memory Interface ALU Program Memory Opcode amp Immediate __ Multiplier Divider Registers Opcode Decoder Timer 0 Timer 1 fo Memory a State Machine amp Power Saving Reset Legacy External Interrupts IENO IEN1 External Interrupts Interrupt Controller Non Maskable Interrupt Figure 2 1 CPU Block Diagram The arithmetic section of the processor performs extensive data manipulation and consists of the ALU ACC register B register and PSW register The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU performs both arithmetic and logic operations Arithmetic operations include add subtract multiply divide increment de
150. status 4 20 Flash erasing 4 17 Flash programming 4 16 Get chip information 4 21 P Flash parallel read enable disable 4 20 Input class 16 8 Instruction decoder 2 1 Instruction timing 2 6 2 9 19 3 V1 1 2007 05 Cinfineon CPU state 2 6 Mnemonic 2 9 Wait state 2 6 In System Programming 4 14 Internal analog clock 16 3 Maximum frequency 16 3 Internal data memory 3 4 Internal RAM 3 1 Interrupt handling 5 14 Interrupt request flags 5 35 Interrupt response time 5 15 Interrupt source and vector 5 11 Interrupt structure 5 8 Interrupt system 5 1 Register description 5 17 J JTAG ID 17 12 L Limit checking 16 19 LIN 12 26 12 30 Break field 12 27 Header transmission 12 28 LIN frame 12 26 LIN protocol 12 26 synch byte 12 27 LIN BSL 18 16 Maskable interrupt 5 1 Memory organization 3 1 Special Function Registers 3 10 Address extension by mapping 3 10 Mapped 3 10 Standard 3 10 Address extension by paging 3 13 Local address extension 3 13 Save and restore 3 14 Memory protection 3 6 Minimum erase width 4 4 User s Manual XC886 888CLM Index Minimum program width 4 9 Modulation 14 15 Monitor mode control 17 2 Monitor RAM 17 2 Data 17 7 Stack 17 7 Monitor ROM 17 2 MultiCAN BSL 18 28 Multi Channel Mode 14 19 Multifold replications 4 5 Multiplication Division Unit 10 1 Error detection 10 4 Interrupt generation 10 4 Low power mode 10 5 Register description 10 7 Register map 10 6 N Non maskable interrupt
151. stop bit In a mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received User s Manual 12 7 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 1 3 UART Register Description Both UART modules contain the two Special Function Registers SFRs SCON and SBUF SCON is the control register and SBUF is the data register On reset both SCON and SBUF return 00 The serial port control and status register is the SFR SCON This register contains not only the mode selection bits but also the 9th data bit for transmit and receive 1B8 and RB8 and the serial port interrupt bits Tl and RI SBUF is the receive and transmit buffer of the serial interface Writing to SBUF loads the transmit register and initiates transmission This register is used for both transmit and receive data Transmit data is written to this location and receive data is read from this location but the two paths are independent Reading out SBUF accesses a physically separate receive register SBUF Serial Data Buffer Reset Value 00 7 6 5 4 3 2 1 0 VAL rwh Field Bits Type Description VAL 7 0 Serial Interface Buffer Register SCON Serial Channel Control Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rwh rwh rwh Field Description RI Ci Receive Interrupt Flag This is set by hardware at the end of the 8th bit on mode 0 or at the half point of the stop bit in mode
152. the Output position it has a 1 and a sequence of zeros to its left The control block then executes one last shift before setting the TI bit User s Manual 12 2 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces Reception is started by the condition REN 1 and RI 0 At the start of the reception cycle 11111110 is written to the receive shift register In each machine cycle that follows the contents of the shift register are shifted left one position and the value sampled on the RXD line in the same machine cycle is shifted in from the right When the O of the initial byte reaches the leftmost position the control block executes one last shift loads SBUF and sets the RI bit The baud rate for the transfer is fixed at fpo 2 where fpc x is the input clock frequency i e one bit per machine cycle 12 1 1 2 Mode 1 8 Bit UART Variable Baud Rate In mode 1 the UART behaves as an 8 bit serial port A start bit 0 8 data bits anda Stop bit 1 are transmitted on TXD or received on RXD at a variable baud rate The transmission cycle is activated by a write to SBUF The data is transferred to the transmit register and a 1 is loaded to the 9th bit position as in mode 0 At phase 1 of the machine cycle after the next rollover in the divide by 16 counter the start bit is copied to TXD and data is activated one bit time later One bit time after the data is activated the data starts getting shifte
153. the Hall pattern and the corresponding modulation pattern The CCU6 offers this by having a register which contains the actual Hall pattern CURHS the next expected Hall pattern EXPHS and its output pattern MCMPS At every correct Hall event a new Hall pattern with its corresponding output pattern can be loaded from a predefined table by software into the register MCMOUTS This shadow register can also be loaded by a write action on MCMOUTS with bit STRHP 1 In case of a phase delay generated by T12 channel 1 a new pattern can be loaded when the multi channel mode shadow transfer indicated by bit STR occurs 14 1 6 1 Sampling of the Hall Pattern The Hall pattern on CCPOSx is sampled with the module clock fecus By using the dead time counter DTCO mode MSEL6x 1000 a hardware noise filter can be implemented to suppress spikes on the Hall inputs In case of a Hall event the DTCO is reloaded and it starts counting and generates a delay between the detected event and the sampling point After the counter value of 1 is reached the CCPOSx inputs are sampled without noise and spikes and are compared to the current Hall pattern CURH and to the expected Hall pattern EXPH If the sampled pattern equals to the current pattern it means that the edge on CCPOSx was due to a noise spike and no action will be triggered implicit noise filter by delay If the sampled pattern equals to the next expected pattern the edge on CCPOSx was a
154. the device is in power down mode i e wake up reset While the contents of the static RAM are undefined after a power on reset they are well defined after a wake up reset from power down mode A brownout reset Is triggered if the Vbpc supply voltage dips below 2 1 V 7 2 1 Types of Resets 7 2 1 1 Power On Reset The supply voltage Vppp is used to power up the chip The EVR is the first module in the chip to be reset which includes 1 Startup of the main voltage regulator and the low power voltage regulator 2 When Vppp and Vppc reach the threshold of the Vbpp and Vppc detectors the reset of EVR becomes inactive In order to power up the system properly the external reset pin RESET must be asserted until Vopc reaches 0 9 Vbpc The delay of external reset can be realized by an external capacitor at RESET pin This capacitor value must be selected so that Vkeser reaches 0 4 V but not before Vppc reaches 0 9 Vpope A typical application example is shown in Figure 7 2 The Vppp capacitor value is 100 nF while the Vbpc capacitor value is 220 nF The capacitor connected to RESET pin is 100 nF Typically the time taken for Vbpc to reach 0 9 Vbpc is less than 50 us once Vppp reaches 2 3V based on the condition that 10 to 90 Vppp slew rate is less than 500 us See Figure 7 3 User s Manual 7 3 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management SOOSSS
155. the following MultiCAN Access Mediator SFRs Table 15 6 MultiCAN Register Mapping Register Name Description See CAN DATA3 DE non mapped Page 15 100 CAN DATA2 Page 15 99 CAN DATAT1 DC non mapped Page 15 99 CAN DATAO DB non mapped Page 15 99 CAN_ ADH DA non mapped Page 15 98 CAN ADL D9 non mapped Page 15 98 CAN _ADCON Page 15 97 User s Manual 15 46 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Figure 15 15 shows the MultiCAN kernel register address map MO Message Object n 31 0 MOpage 1000 n 20 MO nControl Status Reg MOgage 10 MO n Arbitration Reg MOa 18 MO n Data Register High MO 14 MO n Data Register Low MO 10 MO n Accept Mask Reg MOgage OC MO n Interrupt Ptr Reg MOgace 08 MO n FIFO Gtw Ptr Reg MOgase 04 MO n Function Control Reg MOgase OO 1400 Message Object 31 Message Object 30 Message Object Registers 1040 1020 1000 Message Object 1 Message Object 0 NO Node x 1 0 Node x Frame Counter Reg NObase 184 Node x Error Counter Reg NObase 144 H Node x Port Control Reg NO 0C Node x Interrupt Ptr Reg NObase 08 Node x Status Register NOgase 04 Node x Control Register NObase 00 m 7 0 k 1 0 Module Interrupt Trg Reg CG 08 Chy 60 List Registers m 00 i l 280
156. the port pin that is used for the CCPOS2 input signal 00 The input pin for CCPOS2_0 01 The input pin for CCPOS2_1 10 The input pin for CCPOS2_ 2 11 The input pin for CCPOS2_3 Input Select for T12HR This bit field defines the port pin that is used for the T12HR input signal 00 The input pin for T12HR_O 01 The input pin for T12HR_1 10 The input pin for T12HR_2 11 Reserved IST12HR PISEL2 Port Input Select Register 2 Reset Value 00 7 6 5 4 3 2 1 0 ee r rw User s Manual 14 39 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Description IST13HR Bs 0 Input Select for T13HR This bit field defines the port pin that is used for the lt 4 input signal The input pin for T13HR_O The input pin for T13HR_1 The input pin for T13HR_2 Reserved 0 Pees i O if read should be written with 0 14 3 2 Timer 12 Related Registers The generation of the patterns for a 3 channel PWM is based on timer T12 The registers related to timer T12 can be concurrently updated with well defined conditions in order to ensure consistency of the three PWM channels Timer T12 supports capture and compare modes which can be independently selected for the three channels CC60 CC61 and CC6 2 Register T12MSEL contains control bits to select the capture compare functionality of the three channels of timer T12 Table 14 5 Table 14 6 and Table 14 7 define and elaborate some of the capture compare mod
157. to the value obtained from the concatenation of WOTWINB and 00 This feature can be enabled by WINBEN After being serviced the WDT continues counting up from the value lt WDTREL gt 2 The time period for an overflow of the WDT is programmable in two ways e The input frequency to the WDT can be selected via bit WDTIN in register WOTCON to be either foo 2 Or fog 128 e The reload value WDTREL for the high byte of WDT can be programmed in register WDTREL The period Pwpr between servicing the WDT and the next overflow can be determined by the following formula Ee ste 2 _ WDTREL x 2 9 1 WDT PCLK If the Window Boundary Refresh feature of the WDT is enabled the period Pwpr between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL See also Figure 9 2 This period can be calculated by the same formula by replacing WDTREL with WDTWINB In order for this feature to be useful WOTWINB cannot be smaller than WDTREL FFFF WDTWINB WDTREL No refresh Refresh allowed allowed Figure 9 2 WDT Timing Diagram User s Manual 9 3 V1 1 2007 05 Watchdog Timer V1 0 Cinfin eon XC886 888CLM Watchdog Timer Table 9 1 lists the possible ranges for the watchdog time which can be achieved using a certain module clock Some numbers are rounded to 3 significant digits Table 9 1 Watchdog Time Ranges Reload value in Prescaler for fwor WDTREL 2 WDTIN 0 128 WDTI
158. transmit interrupt of message object n This interrupt is generated after the transmission of a CAN message 0 Message transmit interrupt is disabled 1 Message transmit interrupt is enabled Bit field MOIPRn TXINP selects the interrupt output line which becomes activated at this type of interrupt Overflow Interrupt Enable OVIE enables the FIFO full interrupt of message object n This interrupt is generated when the pointer to the current message object CUR reaches the value of SEL in the FIFO Gateway Pointer Register 0 FIFO full interrupt is disabled 1 FIFO full interrupt is enabled lf message object n is a Receive FIFO base object bit field MOIPRn TXINP selects the interrupt output line which becomes activated at this type of interrupt lf message object n is a Transmit FIFO base object bit field MOIPRn RXINP selects the interrupt output line which becomes activated at this type of interrupt For all other message object modes bit OVIE has no effect Foreign Remote Request Enable Specifies whether the TXRQ bit is set in message object n or in a foreign message object referenced by the pointer CUR 0 TXRQ of message object n is set on reception of a matching remote frame 1 TXRQ of the message object referenced by the pointer CUR is set on reception of a matching remote frame 15 88 V1 1 2007 05 Cinfineon SDT 29 DLC 27 24 rwh User s Manual MultiCAN V1 0 XC886 888CLM Controller Area
159. value which specifies the address of the active Slave node for the LIN modes is programmed into the uppermost P Flash bank pair This parameter is specified by the user There are two cases to consider when reading the programmed value one when the Flash is unprotected and the other when the Flash is protected When Flash is not protected user needs to program the NAD in the format shown in Table 18 7 To ensure the validity of the parameter the inverted NAD value is required to be programmed together with the actual value If an invalid NAD is programmed the default NAD value is assumed Table 18 7 User Defined Parameters in relation with Unprotected Flash 5FFE NAD 01 OFF 00 is reserved TF 10 The address shown in the table assumes a device with 24 Kbytes of P Flash For variants with smaller P Flash sizes the address used will be the address of the uppermost P Flash bank plus the offset For example a 20 Kbytes Flash variant will have the NAD address at 4FFE When Flash is protected the least significant bit LSB of the user password determines the NAD value used by the device When LSB of the password is 0 the default broadcast NAD is used When LSB of the user password is 1 user needs to program the NAD in the format shown in Table 18 8 Table 18 8 User Defined Parameters in relation with Flash Protection Mode LSB of User Parameter Value Requirement Password Instruction Criteria Range 0 NAD ar Default Not
160. while the slave devices receive it Due to the fact that all transmit and receive pins are connected to one data exchange line serial data may be moved between arbitrary stations As in full duplex mode there are two ways to avoid collisions on the data exchange line e only the transmitting device may enable its transmit pin driver e the non transmitting devices use open drain output and send only ones Since the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for a slave By this method any corruptions on the common data exchange line are detected if the received data is not equal to the transmitted data Device 2 Master Device 1 Shift Register Transmit Common Trans mit Line Figure 12 14 SSC Half Duplex Configuration User s Manual 12 36 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 3 1 4 Continuous Transfers When the transmit interrupt request flag is set it indicates that the transmit buffer TB is empty and ready to be loaded with the next transmit data If TB has been reloaded by the time the current transmission is finished the data is immediately transferred to the shift register and the next transmission will start without any additional delay On the data line there is no gap between the two successive frames For example two byte transfers would look the same
161. width plus 2 overflow bits for X and Y each 20 bit kernel data width plus 1 overflow bit for Z With KEEP bit to retain the last value in the kernel register for a new calculation e 16 iterations per calculation Approximately 41 clock cycles or less from set of start ST bit to set of end of calculation flag excluding time taken for write and read access of data bytes e Twos complement data processing Only exception X result data with user selectable option for unsigned result e Xand Y data generally accepted as integer or rational number X and Y must be of the same data form e Entries of LUTs are 20 bit signed integers Entries of atan and atanh LUTs are integer representations S19 of angles with the scaling such that 2 2 1 represents the range 7 2 1 2 z Accessible Z result data for circular and hyperbolic functions is integer in data form of S15 e Emulated LUT for linear function Data form is 1 integer bit and 15 bit fractional part 1 15 Accessible Z result data for linear function is rational number with fixed data form of S4 11 signed 4Q16 e Truncation Error The result of aCORDIC calculation may return an approximation due to truncation of LSBs Good accuracy of the CORDIC calculated result data especially in circular mode e Interrupt On completion of a calculation Interrupt enabling and corresponding flag User s Manual 11 2 V1 1 2007 05 CORDIC Coprocessor V 1 2
162. will write results to PANAR1 and PANAR2 but the results are not yet available User s Manual 15 48 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Field Bits Type Description PANAR1 23 16 rwh Panel Argument 1 See Table 15 7 PANAR2 31 24 rwh_ Panel Argument 2 see Table 15 7 0 15 10 r Reserved Read as 0 should be written with O Panel Commands A panel operation consists of a command code PANCMD and up to two panel arguments PANAR1 PANAR2 Commands that have a return value deliver it to the PANAR1 bit field Commands that return an error flag deliver it to bit 31 of the Panel Control Register this means bit 7 of PANAR2 Table 15 7 Panel Commands PANCMD PANAR2 PANAR1 Command Description 00 No Operation Writing 00 to PANCMD has no effect No new command is started Oly Result Initialize Lists Bit 7 ERR Run the initialization sequence to reset Bit 6 0 undefined the CTRL and LIST fields of all message objects List registers LIST 7 0 are setto their reset values This results in the de allocation of all message objects The initialization command requires that bits NCRx INIT and NCRx CCE are set for all CAN nodes x 0 1 Bit 7 of PANAR2 ERR reports the success of the operation 0 Initialization was successful 1 Not all NCRx INIT and NCRx CCE bits are set Therefore no initialization is performed The initialized list command
163. will be set ST120M W Set Timer T12 One Match Flag 0 No action 1 Bit T120M in register IS will be set ST12PM 7 W Set Timer T12 Period Match Flag 0 No action 1 Bit T12PM in register IS will be set Note If the setting by hardware of the corresponding flags leads to an interrupt the setting by software has the same effect User s Manual 14 83 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 ISSH Capture Compare Interrupt Status Set Register High Reset Value 00 6 5 4 3 2 1 S S S S S E IDLE WHE CHE WHC TRPF PM W W W W W W Field Bits Type Description ST13CM Ww Set Timer T13 Compare Match Flag 0 No action 1 Bit T13CM in register IS will be set 1 W ST13PM Set Timer T13 Period Match Flag 0 No action 1 Bit T13PM in register IS will be set 7 STRPF 2 W Set Trap Flag 0 No action 1 Bits TRPF and TRPS in register IS will be set SWHC 3 W Software Hall Compare 0 No action 1 The Hall compare action is triggered SCHE 4 W Set Correct Hall Event Flag 0 No action 1 Bit CHE in register IS will be set SWHE 5 W Set Wrong Hall Event Flag 0 No action 1 Bit WHE in register IS will be set SIDLE W Set IDLE Flag 0 No action 1 Bit IDLE in register IS will be set SSTR 7 Ww Set STR Flag 0 No action 1 Bit STR in register IS will be set Register ISR contains the individual interrupt request reset bits to reset the corresponding flags by software User s Manual 14 84 V1 1 200
164. 0 Field CANS CCU6 CANS CCU6 Interrupt Request Register 3 RC5 ES Ea 2 we r m IRCON4 Reset 00y Bit Field CANS E3 eza Ea Interrupt Request Register 4 cx EA EN Ea Type MODPISEL1 Reset 00y Bit Field a AT E a ECA Kca Peripheral Input Select Register 6IS DIS1 EN et et ow oe se MODPISEL2 Reset 00 4 Bit Field 2 Tas Tais THs a Peripheral Input Select Register ee Se ee PMCON2 Reset 00 Bit Field UART Lote _D Power Mode Control Register 2 1 x Type MODSUSP Reset 01 Bit Field a aaa T13SU E ne Module Suspend Control EE EE lt a EE Register g Type 3 5 5 5 WDT Registers The WDT SFRs can be accessed in the mapped memory area RMAP 1 Table 3 7 WDT Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 oO PMA RMAP 1 WDTCON Reset 001 Bit Field WINB ae Me ae i Watchdog Timer Control EN Register g ca WDTREL Reset 00 4 Bit Field Field ENER Watchdog Timer Reload WDTWINB Reset 00 Bit Field WDTWINB Watchdog Window Boundary User s Manual 3 26 V1 1 2007 05 Memory Organization V 1 2 infin eon XC886 888CLM Memory Organization Table 3 7 WDT Register Overview cont d Saal Register Name joe 7 je js 4 js 2 jt jo WDTL Reset 001 Bit Field Di ee fm ype rh es 3 5 5 6 Port Registers The Port SFRs can be accessed in the standard memory area RMAP 0 Table 3 8 Port Register Overview PORT_PAGE Reset 004 BitFicd OP STNR O
165. 0 7 6 5 4 3 2 1 0 T12 T12 DT T12 T12 T12 STD STR RES RES RS RR W W r W W W W Field Description T12RR Timer T12 Run Reset Setting this bit resets the T12R bit 0 T12R is not influenced 1 T12R is cleared T12 stops counting T12RS 1 W Timer T12 Run Set Setting this bit sets the T12R bit 0 T12R is not influenced 1 T12R is set 112 counts T12RES 2 Ww Timer T12 Reset 0 No effect on 112 1 The 112 counter register is reset to zero The switching of the output signals is according to the switching rules Setting of T12RES has no impact on bit T12R DTRES 3 W Dead Time Counter Reset 0 No effect on the dead time counters 1 The three dead time counter channels are reset to zero T12STR W Timer T12 Shadow Transfer Request 0 No action 1 STE12 is set enabling the shadow transfer T12STD 7 Ww Timer T12 Shadow Transfer Disable 0 No action 1 STE12 is reset without triggering the shadow transfer User s Manual 14 65 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field ee e Description 0 5 4 Reserved Returns 0 if read should be written with O TCTR4H Timer Control Register 4 High Reset Value 00 7 6 9 4 3 2 1 0 T13 T13 T13 T13 T13 STD STR RES RS RR W W r WwW W W Field Se Description T13RR Timer T13 Run Reset Setting this bit resets the T13R bit 0 T13R is not influenced 1 T13R is cleared T13 stops counting T13RS 1 W Timer T13 Run Set Setting this bit sets the T13R bit
166. 0 04 D Flash Bank 1 Others Invalid Output PSW CY 0 Flash bank is not in ready to read mode 1 Flash bank is in ready to read mode Stack size required 3 bytes Resource ACC PSW used destroyed For invalid ACC input PSW CY will be 0 4 8 5 P Flash Parallel Read Enable Disable User can opt to disable the P Flash parallel read feature by calling the parallel read disable subroutine A subroutine to enable the parallel read feature is also provided Table 4 5 P Flash Parallel Read Enable Disable Subroutine Subroutine DFFC PARALLEL _READ_DISABLE DFFF PARALLEL READ ENABLE Input Output Stack size required 3 bytes Resource He used destroyed User s Manual 4 20 V1 1 2007 05 Flash Memory V 1 0 Cinfine on XC886 888CLM Flash Memory 4 8 6 Get Chip Information This subroutine reads out a 4 byte data that contains chip related information In the XC886 888 it reads out the 4 byte chip identification number which is used to identify the particular device variant Table 4 6 Get Chip Information Subroutine Subroutine DFE1 GET_CHIP_INFO Input ACC 00 Chip Identification Number Others Reserved R1 of Current Register Bank IRAM start address for 4 byte return data Output 4 byte of return data in IRAM only if input ACC 00 Byte 1 in R1 MSB Byte 2 in R1 1 Byte 3 in R1 2 Byte 4 in R1 3 LSB PSW CY 0 Fetch is successful 1 Fetch is unsuccessful Stack size re
167. 0 0 0 2 eee 15 34 15 1 9 5 Receive FIFO cacuvaG hieue enue Ee eek oe Reed eee dee beeen 15 36 15 1 9 6 Transmit FIFO 3 4 40 2 0 athe 6a oho ee ao he ee ee oe ee ead 15 37 15 1 9 7 Gateway M606 24 24 4442 nedeew ease dade re dede cous dare 15 38 15 1 9 8 Foreign Remote Requests 00 cece eee ee ees 15 40 15 1 10 Access Mediator p4sa4bodvdxeaedans bobs bor dennit bets ae ees 15 41 15 1 11 POR COMUO accercarenceneatebsede anadeaRebewa dangers ia 15 43 15 1 12 Low Power Mode 0 0 ccc ee ee eens 15 44 15 2 Registers Description 1 0 ee ees 15 45 15 2 1 Global Module Registers 0 0 ccc ees 15 48 15 2 2 CAN Node Registers 0 00 cee eens 15 59 15 2 3 Message Object Registers 0 cee ee eee 15 76 15 2 4 MultiCAN Access Mediator Register 000 0 eee 15 97 16 Analog to Digital Converter 0 0 0 0 c eee ee 16 1 16 1 Structure Overview 0 0 ee ee ee ees 16 2 16 2 Clocking Scheme 00 ccc eee ees 16 3 16 2 1 Conversion Timing naana 0c ee eee ee ees 16 4 16 3 Low Power Mode 0 ccc ee eee ees 16 7 16 4 Functional Description 0 2 0 000 16 8 16 4 1 Request Source Arbiter 0 0 0 eee 16 9 16 4 2 Conversion Start Modes 0 0 ccc ee ees 16 10 User s Manual l 8 V1 1 2007 05 Cinfin eon XC886 888CLM Table of Contents Page 16 4 3 Channel Control s0ateas sate atawn cals dooce been eaaceeend 16 10 16 4 4 Sequential R
168. 0 T13R is not influenced 1 T13R is set 113 counts T13RES 2 Ww Timer T13 Reset 0 No effect on T13 1 The 113 counter register is reset to zero The switching of the output signals is according to the switching rules Setting of T13RES has no impact on bit T13R T13STR Ww Timer T13 Shadow Transfer Request 0 No action 1 STE13 is set enabling the shadow transfer T13STD 7 W Timer T13 Shadow Transfer Disable 0 No action 1 STE13 is reset without triggering the shadow transfer 0 5 3 r Reserved Returns 0 if read should be written with O User s Manual 14 66 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Note A simultaneous write of a 1 to bits which set and reset the same bit will trigger no action The corresponaing bit will remain unchanged 14 3 5 Global Modulation Control Registers Register MODCTR contains control bits enabling the modulation of the corresponding output signal by PWM pattern generated by the timers 112 and 113 Furthermore the multi channel mode can be enabled as additional modulation source for the output signals MODCTRL Modulation Control Register Low Reset Value 00 7 6 9 4 3 2 1 0 rw r rw Field Description T12MODEN Be 0 T12 Modulation Enable Setting these bits enables the modulation of the corresponding compare channel by a PWM pattern generated by timer T12 The bit positions are corresponding to the following output signals Bit 0 modulation of CC60 Bit 1
169. 007 05 Interrupt System V 1 0 infin eon XC886 888CLM Interrupt System CCU6 interrupt node 0 CCU6SRO IRCONS 0 MultiCAN_4 CANSRC4 IRCONS 1 CCU6 interrupt node 1 CCU6SR1 IRCON3 4 MultiCAN_5 CANSRC5 IRCON3 5 CCU6 interrupt node 2 CCU6SR2 IRCON4 0 P O n g S e q u e n C e MutliCAN_6 CANSRC6 IRCON4 1 CCU6 interrupt node 3 CCU6SRC3 IRCON4 4 MultiCAN_7 CANSRC7 IRCON4 5 Bit addressable J Request flag is cleared by hardware Figure 5 5 Interrupt Request Sources Part 5 User s Manual 5 6 V1 1 2007 05 Interrupt System V 1 0 Infineon WDT Overflow PLL Loss of Lock Flash NMI VDD Pre Warning VDDP Pre Warning Flash ECC Error A Bit addressable NMIWDT NMIISR O NMIP LL NMIISR 1 NMIFLASH NMIISR 2 NMIVDD NMIISR 4 NMIVDDP NMIISR 5 NMIECC NMIISR 6 NMIWDT NMICON O NMIPLL NMICON 1 NMIFLASH NMICON 2 NMIVDD NMICON 4 NMIVDDP NMICON 5 NMIECC NMICON 6 XC886 888CLM Interrupt System Non H Maskable Interrupt d Request flag is cleared by hardware Figure 5 6 Non Maskable Interrupt Request Sources User s Manual 5 7 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System 5 1 Interrupt Structure An interrupt event source may be generated from the on chip peripherals or from external Detection of interrupt events is controlled by the respective on chip peripherals Interrupt
170. 007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Table 15 2 gives an overview on the available panel commands while Table 15 7 describes the panel commands in more detail Table 15 2 Panel Commands Overview Command Name Description No Operation No new command is started Initialize Lists Run the initialization sequence to reset the CTRL and LIST field of all message objects Static Allocate Allocate message object to a list Dynamic Allocate Allocate the first message object of the list of unallocated objects to the selected list Static Insert Before Remove a message object source object from the list that it currently belongs to and insert it before a given destination object into the list structure of the destination object Dynamic Insert Before Insert a new message object before a given destination object Static Insert Behind Remove a message object Source object from the list that it currently belongs to and insert it behind a given destination object into the list structure of the destination object Dynamic Insert Behind Insert a new message object behind a given destination object A panel command is started by writing the respective command code to the bit field PANCTR PANCMD The corresponding command arguments must be written to bit fields PANCTR PANAR1 and PANCTR PANAR2 before writing the command code or together with the command code in a single 32 bit writ
171. 1 LSB represents sector 8 bit 1 represents sector 9 R5 Select sector s to be erased for P Flash Bank Pair 0 LSB represents sector 0 bit 2 represents sector 2 User s Manual 4 17 V1 1 2007 05 Flash Memory V 1 0 Cinfin eon XC886 888CLM Flash Memory Table 4 2 Flash Erase Subroutine cont d R6 Select sector s to be erased for P Flash Bank Pair 1 LSB represents sector 0 bit 2 represents sector 2 R7 Select sector s to be erased for P Flash Bank Pair 2 LSB represents sector 0 bit 2 represents sector 2 Flash NMI NMICON NMIFLASH is enabled 1 or disabled 0 MISC_CON DFLASHEN bit 1 Output PSW CY 0 Flash erasing is in progress 1 Flash erasing is not started Stack size required 9 bytes Resource ACC B SCU PAGE PSW used destroyed RO R7 of Current Register Bank 8 bytes The time taken by the subroutine from the calling of the subroutine to the setting of the NMI flag can be split into two components One is the time from the calling of the subroutine to the return to the calling function which is lt 30 us the other is the time needed by the Flash State Machine which is given by the formula 9807360 foys The inputs should be clear to 0 if the sector s of the bank s is are not to be selected for erasing 3 When Flash Protection Mode 0 is enabled the DFLASHEN bit needs to be set before each erase of the D Flash banks In addition parallel erase of the D Flash Banks 0 and 1 is not a
172. 1 O inactive inactive active inactive active inactive doni active active Idle inactive inactive 10 In case the sampled Hall inputs were neither the current nor the expected Hall pattern the bit WHE Wrong Hall Event is set which can also cause an interrupt and set the IDLE mode to clear MCMP modulation outputs are inactive User s Manual 14 23 V1 1 2007 05 CCU6B V 1 0 XC886 888CLM ineon Inf Capture Compare Unit 6 CCPOSO CCPOS1 CCPOS2 COUT60 COUT61 COUT62 Figure 14 17 Block Commutation in Rotate Left Mode CCPOSO CCPOS1 CCPOS2 CC 60 CC61 COUT60 al O O N O H D O O Figure 14 18 Block Commutation in Rotate Right Mode 14 24 V1 1 2007 05 User s Manual CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 1 7 Interrupt Generation The interrupt generation can be triggered by the interrupt event or the setting of the corresponding interrupt bit in register IS by software The interrupt is generated independently of the interrupt flag in register IS Register IS can only be read write actions have no impact on the contents of this register The software can set or reset the bits individually by writing to register ISS or register ISR respectively lf enabled by the related interrupt enable bit in register IEN an interrupt will be generated The interrupt sources of the CCU6 module can be mapped to four interrupt
173. 1 0 Cinfine on XC886 888CLM On Chip Debug Support Also suspending the other timer modules makes sense for debugging once the application is not running stopping counters helps for a more complete freeze of the device status during a break It must be noted in XC886 888 all of the debug suspend control bits global enable in OCDS and individual selections in SCU have values 0 after reset i e by default no module will be suspended upon a break But normally for debugging the device will be started in OCDS mode and then the monitor will be invoked before to start any user code Then it is possible using a debugger to configure suspend controls as desired and only afterwards start the debug session Note For more information on debug suspend refer to the individual modules section on Module Suspend Control User s Manual 17 8 V1 1 2007 05 OCDS V 1 0 Cinfin eon XC886 888CLM On Chip Debug Support 17 5 Register Description From a programmer s point of view OCDS is represented in XC886 888 by a total of 10 register addresses see Table 17 1 all located within the mapped SFR area Table 17 1 OCDS Directly Addressable Registers Register Register Full Name Short Name mapped MMCR Monitor Mode Control Register MMCR2 Monitor Mode Control Register 2 MMSR Monitor Mode Status Register MMBPCR F3 Monitor Mode Breakpoints Control Register MMICR F4 Monitor Mode Interrupt Control Register MMDR FS Monitor Mode
174. 1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 7 3 Data Reduction Filter Each result register can be controlled to enable or disable the data reduction filter The data reduction block allows the accumulation of conversion results for anti aliasing filtering or for averaging conversion f k s p 7 i ready olla elles La La Le Lo Le version ones EEE tz tonct DRC a T T o T content of result register x oc O OC O valid flag for result register x VFX DRC 0 content of result register x DRCTR VFx Figure 16 10 Data Reduction Flow lf DRC is 0 and a new conversion result comes in DRC is reloaded with its reload value defined by bit DRCTR in the result control register and the value of O is added to the conversion result instead of the previous result register content Then the complete result is stored in the selected result register If the reload value is O data reduction filter disabled accumulation is done over one conversion Hence a result event is generated and the valid bit VF for the result register becomes set If the reload value is 1 data reduction filter enabled accumulation is done over two conversions In this case neither a result event is generated nor the valid bit is set lf DRC is 1 and a new conversion result comes in the data reduction filter adds the incoming result to the value already stored in the result register a
175. 1 tow fecoik 32 Others reserved User s Manual 12 16 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces Field Bits Type Description BRDIS 4 rw Break Synch Detection Disable 0 Break Synch detection is enabled 1 Break Synch detection is disabled BGSEL rw Baud Rate Select for Detection For different values of BGSEL the baud rate range for detection is defined by the following formula feci 2184 2 BGSEL lt baud rate range lt fecik 72 2 BGSEL where BGSEL 00g 015 10 11 See Table 12 4 for bit field BGSEL definition for different input frequencies Reserved Returns 0 if read should be written with 0 y Ke O 7 Note Bits BRDIS and BGSEL are used only in UART module and not in UART1 module Therefore they should always be written with O in the BCON register in UART1 module Setting them to 1 in the UART1 register has no effect Table 12 4 BGSEL Bit Field Definition for Different Input Frequencies I eeik BGSEL Baud Rate Select for Detection Secik 2184 24BGSEL to fp 72 2 BGSEL 24 MHz 00 11 kHz to 333 3 KHz 5 5 KHz to 166 6 KHz 2 8 kHz to 83 3 kHz 1 4 KHz to 41 6 kHz 12 MHz 00 5 5 KHz to 166 6 KHz 2 8 kHz to 83 3 kHz 1 4 kHz to 41 6 kHz 0 7 kHz to 20 8 kHz B 0 92 KHz to 27 7 KHz 0 46 KHz to 13 8 kHz 0 23 kHz to 6 9 kHz 0 12 kHz to 3 4 kHz 2 MHz 0 o o o a o a o a o WO JJ JJ JJ JJ JJ JJ JJ JJ User s Manua
176. 10 R7 R2 R1 RO VF IDRO CHNR rh rh 10 bit conversion accumulated 11 bit Figure 16 11 Result Register View User s Manual 16 22 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 8 Interrupts The ADC module provides 2 service request outputs SR 1 0 that can be activated by different interrupt sources The interrupt structure of the ADC supports two different types of interrupt sources e Event Interrupts Activated by events of the request sources source interrupts or result registers result interrupts e Channel Interrupts Activated by the completion of any input channel conversion They are enabled according to the control bits for the limit checking The settings are defined individually for each input channel The interrupt compressor is an OR combination of all incoming interrupt pulses for each of the SR lines unit request sources 7 event interrupt interrupt com pressor channel interrupt routing Figure 16 12 Interrupt Overview Refer to Section 16 7 9 for description of the interrupt registers User s Manual 16 23 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 8 1 Event Interrupts Event interrupts can be generated by the request sources and the result registers The event interrupt enable bits are located in the request sources ENSI
177. 12 DT T12 ee ee Timer Control Register 4 Low EN Ea cH EE Type CCU6_TCTR4H Reset 00y Bit Field E EZ K2 zm co Timer Control Register 4 High EN a EN Type 9E CCU6_MCMOUTSL Reset 004 Bit Field KAKS a Multi Channel Mode Output Shadow CM Register Low tye w fer wo O O CCU6_MCMOUTSH Reset 00 Bit Field ae CURHS EXPHS Multi Channel Mode Output Shadow Register High g g Type CCU6_ISRL Reset 00y Bit Field lt ae E RCC6 RCC6 EE RCC6 RCC6 Capture Compare Interrupt Status EN EI EN EI EN F EJ R EN EI Reset Register Low g Type CCU6_ISRH Reset 00y Bit Field lt lt ae cane aE ES Ea Capture Compare Interrupt Status PM CM Reset Register High Type CEKESEAESEAEAKTENKI CCU6_CMPMODIFL Reset 00 Bit Field MCC6 MCC6 MCC6 MCC6 Compare State Modification Register EN 2S EJ OS Low Type CCU6_CMPMODIFH Reset 00 Bit ef CEE S eee Compare State Modification Register 3R 1R mirtiel ste User s Manual 3 34 V1 1 2007 05 Memory Organization V 1 2 infine on XC886 888CLM Memory Organization Table 3 12 CCU6 Register Overview cont d Addr Register Name Bit 7 6 5 4 3 2 1 0 FAR o CCU6_CC60SRL Reset 00 Bit Field CC60SL Capture Compare Shadow Register CCU6_CC60SRH Reset 00 4 Bit Field Field BOSH Capture Compare Shadow Register for Channel CC60 High CCU6_CC61SRL Reset 00 Bit Bit Field tS SL Capture Compare Shadow Register for Chann
178. 16 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System 5 6 Interrupt Registers Interrupt registers are used for interrupt node enable external interrupt control interrupt flags and interrupt priority setting 5 6 1 Interrupt Node Enable Registers Each interrupt node can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IENO or IEN1 Register IENO also contains the global interrupt masking bit EA which can be cleared to block all pending interrupt requests at once The NMI interrupt vector is shared by a number of sources each of which can be enabled or disabled individually via register NMICON After reset the enable bits in IENO IEN1 and NMICON are cleared to 0 This implies that all interrupt sources are disabled by default IENO Interrupt Enable Register 0 Reset Value 00 7 6 5 4 3 2 1 0 rw r rw rw rw rw rw rw Field mid Description EX0 Interrupt Node XINTRO Enable 0 XINTRO is disabled 1 XINTRO is enabled ETO 1 rw Interrupt Node XINTR1 Enable 0 XINTR1 is disabled 1 XINTR1 is enabled EX1 2 rw Interrupt Node XINTR2 Enable 0 XINTR2 is disabled 1 XINTR2 is enabled ET1 3 rw Interrupt Node XINTR3 Enable 0 XINTR3 is disabled 1 XINTR3 is enabled User s Manual 5 17 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System Field eee Description ES Interrupt Node XINTR4 Enable 0 XINTR4 is disab
179. 2 Timer 2 Register High Type rwh 3 5 5 9 Timer 21 Registers The Timer 21 SFRs can be accessed in the mapped memory area RMAP 1 Table 3 11 121 Register Overview ual Register Name 76 5 4st ziti o T21_T2CON Reset 00 Bit Field EXF2 C T2 CP Timer 2 Control Register RL2 Type ate ote T21_T2MOD Reset 00 Bit Field T2RE T2RH EDGE PREN T2PRE DCEN Timer 2 Mode Register GS EN SEL rw rw lt O D Timer 2 Reload Capture Register Low Type rwh T21_RC2H Reset 00y Bit Field RC2 Timer 2 Reload Capture Type rwh Register High 4y T21_T2L Reset 004 Bit Field THL2 Timer 2 Register Low Type rwh User s Manual 3 33 V1 1 2007 05 Memory Organization V 1 2 infine on XC886 888CLM Memory Organization Table 3 11 121 Register Overview cont d Addr RegisterName Bt 7 6 5 4 3 2 4 0 Sy T21_T2H Reset 00 Bit Field THL2 Timer 2 Register High 3 5 5 10 CCU6 Registers The CCU6 SFRs can be accessed in the standard memory area RMAP 0 Table 3 12 CCU6 Register Overview Addr Register Name Bt 77 6 5s 4 3 2i1 oo RMAP 0 CCU6_PAGE Reset 004 BitFied OP STNR o PAGE Page Register Type we w w r r m m RMAP 0 PAGE 0 CCU6_CC63SRL Reset 00 Bit Field CC63SL Capture Compare Shadow Register CCU6_CC63SRH Reset 00 Bit Field CC63SH Capture Compare Shadow Register for Channel CC63 High Type CCU6_TCTR4L Reset 00y Le T12 T
180. 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 5 ADC Module Initialization Sequence The following steps is meant to provide a general guideline on how to initialize the ADC module Some steps may be varied or omitted depending on the application requirements Configure global control functions Select conversion width GLOBCTR DW Select analog clock fanc divider ratio GLOBCTR CTC Configure arbitration control functions Select priority level for request source x PRAR PRIOx Select conversion start mode for request source x PRAR CSMx Enable arbitration slot x PRAR ASENx Select arbitration mode PRAR ARBM Configure channel control information Select limit check control for channel x CHC TRx LCC Select target result register for channel x CHCTRx RESRSEL Select sample time for all channels INPCRO STC Configure result control information Enable disable data reduction for result register x RCRx DRCTR Enable disable event interrupt for result register x RCRx IEN Enable disable wait for read mode for result register x RCRx WFR Enable disable valid flag reset by read access for result register x RCRx VFCTR Configure interrupt control functions Select channel x interrupt node pointer CHINPR CHINPx Select event x interrupt node pointer EVINPR EVINPx Configure limit check boundaries Select limit check bounda
181. 2007 05 CORDIC Coprocessor V 1 2 1 Cinfine on XC886 888CLM CORDIC Coprocessor Field Description KEEPX Last X Result as Initial Data for New Calculation If set a new calculation will use as initial data the value of the result from the previous calculation In other words the respective kernel data register will not be overwritten by the contents of the shadow data register at the beginning of new calculation This bit should always be cleared for the very first calculation to load the initial X data Note Independent of the KEEP bit the shadow data registers will continue to hold the last written initial data value until the next software write Note If KEEPx bit is set for a multi step calculation the accuracy of the corresponding final x result data may be reduced and is not guaranteed as shown in Section 11 2 6 KEEPY i Y Result as Initial Data for New Calculation description for KEEPX gt KEEPZ Last Z Result as Initial Data for New Calculation lt See description for KEEPX gt 11 6 3 Data Registers The Data registers are used to initialize the X Y and Z parameters The result data from CORDIC calculation can also be read DMAP 0 Reading of the shadow registers for initial data are also possible DMAP 1 Regardless of the DMAP setting for reading these data registers always hold the last written initial value until the next user software write or reset CD_CORDXxL x X Y or Z CORDIC x Data Lo
182. 2CLK ste 0 Timer T12 Input Clock Select Selects the input clock for timer T12 which is derived from the peripheral clock according to the equation frie foou 2S 000 ft12 focu 001 ft12 Jccu 2 010 ft12 JSocu 4 011 fri2 fecu 8 100 ft12 fecy 16 101 fti2 focu 32 110 ft12 focy 64 111 fty2 Secu 128 T12PRE Timer T12 Prescaler Bit In order to support higher clock frequencies an additional prescaler factor of 1 256 can be enabled for the prescaler for T12 0 The additional prescaler for T12 is disabled 1 The additional prescaler for T12 is enabled T12R 4 rh Timer T12 Run Bit T12R starts and stops timer T12 It is set reset by software by setting bits T12RS or T12RR or it is reset by hardware according to the function defined by bit field T12SSC 0 Timer T12 is stopped 1 Timer T12 is running A concurrent set reset action on T12R from T12SSC T12RR or T12RS will have no effect The bit T12R will remain unchanged User s Manual 14 59 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Description STE12 5 rh Timer T12 Shadow Transfer Enable Bit STE12 enables or disables the shadow transfer of the T12 period value the compare values and passive state select bits and levels from their shadow registers to the actual registers if a T12 shadow transfer event is detected Bit STE12 is cleared by hardware after the shadow transfer A 112 shadow transfer event is a period match while counting up or a on
183. 3 MOAMRnhn 15 91 MOARn 15 92 MOCTRn 15 76 MODATAHn 15 96 MODATALn 15 95 MOFCRnhn 15 86 MOFGPRnhn 15 90 MOIPRn 15 84 MOSTATn 15 79 MSIDk 15 57 MSIMASK 15 58 MSPNDk 15 56 NBTRx 15 69 NCRx 15 59 NECNTx 15 71 NFCRx 15 72 NIPRx 15 66 NPCRx 15 68 NSRx 15 63 PANCTR 15 48 Cancel Inject Repeat 16 10 Capture Compare Unit 6 14 1 Low Power Mode 14 26 Module Suspend Control 14 27 Register description 14 35 Register map 14 32 Central Processing Unit 2 1 Chip identification number 1 17 Circular stack memory 4 5 User s Manual Index Clock management 7 15 Clock source 7 13 Clock system 7 11 Register description 7 17 Conversion error 16 4 Conversion phase 16 5 CORDIC 11 1 Accuracy 11 9 Normalized Deviation 11 10 Calculated Data 11 1 CORDIC equations 11 1 Data Format 11 8 Data Overflow 11 8 Domains of Convergence 11 7 Features 11 2 Functional Description 11 3 Gain Factor 11 4 Initial Data 11 1 Interrupt 11 4 Look Up Tables atan 11 12 atanh 11 12 linear 11 13 Low power mode 11 14 Normalized Result Data 11 4 Operating Modes 11 5 Circular Function 11 5 Hyperbolic Function 11 6 Linear Function 11 5 Rotation Mode 11 5 Usage Notes 11 6 Vectoring Mode 11 5 Performance 11 11 Register description 11 16 Register map 11 15 Result Data 11 1 Correction algorithm 4 12 Count Clock 13 19 Counter 13 2 13 14 CPU 2 1 CPU Registers Extended Operation 2 5 Power Control 2 6 V1 1 2007 05 Cinfineon D Data Flash 4 2 4 3 Address
184. 420 643F y ee re 6422 6421 6420 TAIF lt rosiucateedcasutoniueatuaisansetse 7402 74014 7400 CAM sess aesaidecet hcuenseseadensdse 6402 6401 6400 Alger Meee N ee Ziq Wlelile ce eee eee ee 63E2 63E1 63E0 Sie D O D B68 B68 Aes al Cee ee ee re yee 7042 70414 7040 822 cll eee 6042 6041 6040 S22 TOs ey eee en eee re 7022 7021 7020 S E A A 6022 6021 6020 AO ll E r teresa eee 7002 7001 7000 Ug a eee cetacean 6002 6001 6000 WL WL Address Address Figure 4 5 D Flash Wordline Addresses Program User s Manual Flash Memory V 1 0 4 7 V1 1 2007 05 infin eon XC886 888CLM Flash Memory Byte 31 Byte 2 Byte 1 ByteO Byte 31 Byte 2 Byte1 Byte 0 BEF reris aie BFE2 BFE1 BFEO aes A
185. 5 8 These bits indicate the current timer value User s Manual 13 28 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 Capture Compare Unit 6 The Capture Compare Unit 6 CCU6 provides two independent timers 112 T13 which can be used for Pulse Width Modulation PWM generation especially for AC motor control The CCU6 also supports special control modes for block commutation and multi phase machines The block diagram of the CCU6 module is shown in Figure 14 1 The timer T12 can function in capture and or compare mode for its three channels The timer T13 can work in compare mode only The multi channel control unit generates output patterns which can be modulated by T12 and or T13 The modulation sources can be selected and combined for the signal modulation Timer T12 Features e Three capture compare channels each channel can be used either as a capture or as a compare channel e Supports generation of a three phase PWM six outputs individual signals for highside and lowside switches e 16 bit resolution maximum count frequency peripheral clock frequency e Dead time control for each channel to avoid short circuits in the power stage e Concurrent update of the required 112 13 registers e Generation of center aligned and edge aligned PWM e Supports single shot mode e Supports many interrupt request sources e Hysteresis like control mode Timer T13 Features e One independent com
186. 6 PSSCH Priority Level High Bit for Interrupt Node XINTR7 PX2H _ Priority Level High Bit for Interrupt Node XINTR8 PXMH Priority Level High Bit for Interrupt Node XINTR9 PCCIPOH Priority Level High Bit for Interrupt Node XINTR10 PCCIP1H Priority Level High Bit for Interrupt Node XINTR11 PCCIP2H rw Priority Level High Bit for Interrupt Node XINTR12 PCCIP3H 7 rw Priority Level High Bit for Interrupt Node XINTR13 User s Manual 5 34 V1 1 2007 05 Interrupt System V 1 0 Cinfineon 5 7 Interrupt Flag Overview XC886 888CLM Interrupt System The interrupt events have interrupt flags that are located in different SFRs Table 5 4 provides the corresponding SFR to which each interrupt flag belongs Detailed information on the interrupt flags is provided in the respective peripheral chapters Table 5 4 Locations of the Interrupt Request Flags Interrupt Source Timer 0 Overflow Timer 1 Overflow Timer 2 Overflow Timer 2 External Event Timer 21 Overflow Timer 21 External Event LIN End of Syn Byte LIN Syn Byte Error UART Receive UART Transmit UART Normal Divider Overflow UART1 Receive UART1 Transmit UART1 Normal Divider Overflow External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 CORDIC End of Calculation MDU Result Ready MDU Error A D Converter Service Request 0 A D Converter Service Request 1 User
187. 7 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 ISRL Capture Compare Interrupt Status Reset Register Low Reset Value 00 Field a Description RCC60R Reset Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC60R in register IS will be reset RCC60F Reset Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC60F in register IS will be reset RCC61R 2 Ww Reset Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC61R in register IS will be reset RCC61F 3 W Reset Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC61F in register IS will be reset RCC62R 4 Ww Reset Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC62R in register IS will be reset RCC62F 5 W Reset Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC62F in register IS will be reset RT120M Ww Reset Timer T12 One Match Flag 0 No action 1 Bit T12OM in register IS will be reset RT12PM 7 Ww Reset Timer T12 Period Match Flag 0 No action 1 Bit T12PM in register IS will be reset User s Manual 14 85 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 ISRH Capture Compare Interrupt Status Reset Register High Reset Value 00 Field a Description RT13CM Reset Timer T13 Compare Match Flag 0 No action 1 Bit T13CM in register IS will be reset RT13PM Reset Timer T13 Period Match Flag 0 No action 1 Bit T13PM in register IS will be reset RTRPF 2 W Reset Tr
188. 7 6 5 4 3 2 1 0 Sse os W W r rw Field Description PAGE 0 Page Bits When written the value indicates the new page When read the value indicates the currently active page STNR 5 4 Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP If OP 10p the contents of PAGE are saved in STx before being overwritten with the new value If OP 11p the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STO is selected 01 ST1 is selected 10 ST2 is selected 11 STS is selected User s Manual 3 15 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization Field Bits Type Description OP 7 6 w Operation OX Manual page mode The value of STNR is ignored and PAGE is directly written 10 New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR 11 Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR Reserved Returns 0 if read should be written with 0 3 5 3 Bit Addressing SFRs that have addresses in the form of 1XXXX000 z e g 80 88 90 FO F8p are bitaddressable
189. 8 bit Central Processing Unit CPU that is compatible with the standard 8051 processor While the standard 8051 processor is designed around a 12 clock machine cycle the XC886 888 CPU uses a 2 clock machine cycle This allows fast access to ROM or RAM memories without wait state Access to the Flash memory however requires one wait state one machine cycle See Section 2 3 The instruction set consists of 45 one byte 41 two byte and 14 three byte instructions The XC886 888 CPU provides a range of debugging features including basic stop start single step execution breakpoint support and read write access to the data memory program memory and Special Function Registers SFRs Features e Two clocks per machine cycle architecture for memory access without wait state e Wait state support for Flash memory e Program memory download option e 15 source 4 level interrupt controller e Two data pointers e Power saving modes e Dedicated debug mode and debug signals e Two 16 bit timers Timer 0 and Timer 1 e Full duplex serial port UART 2 1 Functional Description Figure 2 1 shows the CPU functional blocks The CPU consists of the instruction decoder the arithmetic section and the program control section Each program instruction is decoded by the instruction decoder This instruction decoder generates internal signals that control the functions of the individual units within the CPU The internal signals have an effect on the
190. 8 bit reload value OM3 THO holds the 8 bit timer value TH1 is not used TCON Timer 0 1 Control Registers Reset Value 00 7 6 5 4 3 2 1 0 coe om owo oo f om e ro rwh rw rwh rw rwh rw rwh rw Field i Description TRO 4 Timer 0 Run Control 0 Timer is halted 1 Timer runs TFO 5 rwh_ Timer 0 Overflow Flag Set by hardware when Timer 0 overflows Cleared by hardware when the processor calls the interrupt service routine TR1 rw Timer 1 Run Control 0 Timer is halted 1 Timer runs Note Timer 1 Run Control affects THO also if Timer 0 operates in Mode 3 TF1 7 rwh_ Timer 1 Overflow Flag Set by hardware when Timer 1 overflows Cleared by hardware when the processor calls the interrupt service routine 10 TF1 is set by THO instead if Timer 0 operates in Mode 3 User s Manual 13 11 V1 1 2007 05 Timers V 1 0 Cinfine on XC886 888CLM Timers TMOD Timer Mode Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw Field Bits Type Description TOM 1 0 rw Mode select bits 00 13 bit timer M8048 compatible mode 01 16 bit timer 10 8 bit auto reload timer 11 Timer 0 is split into two halves TLO is an 8 bit timer controlled by the standard Timer 0 control bits and THO is the other 8 bit timer controlled by the standard Timer 1 control bits TH1 and TL1 of Timer 1 are held Timer 1 is stopped T1M 5 4 W Mode select bits 00 13 bit timer M8048 compatible mode 01 16 bit timer 10 8 bit auto relo
191. 86 888 remains in this loss of lock state until the next power on reset hardware reset or after a successful lock recovery has been performed Note While PLL is running in VCO base frequency i e fsys Veopase K Read from Flash is possible at low frequency However Flash program or erase operation is not allowed Loss of Lock Recovery lf PLL has lost its lock to the oscillator the PLL can be re locked by software The following sequence must be performed 1 Disconnect the oscillator from the PLL OSCDISC 1 2 Wait until the oscillator is stable 3 Restart the Oscillator Run Detection by setting bit OSC_CON ORDRES 4 Wait for 2048 cycles based on VCO frequency If bit OSC_CON OSCR is set then 1 Select the VCO bypass mode VCOBYP 1 2 Reconnect oscillator to the PLL OSCDISC 0 3 The RESLD bit must be set and the LOCK flag checked Only if the LOCK flag is set again can the VCO bypass mode be deselected and normal operation resumed If neither OSCR nor LOCK is set emergency measures must be executed Emergency measures such as a system shut down can be carried out by the user User s Manual 7 12 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfine on XC886 888CLM Power Supply Reset and Clock Management Changing PLL Parameters To change the PLL parameters first check if the oscillator is running OSC_CON OSCR 1 In this case Select VCO bypass mode VCOBYP 1 Program desired NDIV value
192. 9 18 17 16 Field Description 0 Interrupt Trigger Writing a 1 to IT n n 0 7 generates an interrupt request on interrupt output line CANSRC n Writing a 0 to IT n has no effect Bit field IT is always read as 0 Multiple interrupt requests can be generated with a single write operation to MITR by writing a 1 to several bit positions of IT 0 31 8 Reserved Read as 0 should be written with O User s Manual 15 53 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller List Pointer and List Register Each of the two CAN nodes has a list which defines the allocated message objects Additionally a list of all unallocated objects is available Further general purpose lists are available which are not associated to a CAN node The List Registers are assigned in the following way e LISTO defines the list of all unallocated objects e LIST1 defines the list for CAN node 0 e LIST2 defines the list for CAN node 1 e LIST 7 3 are not associated to a CAN node free lists LISTO List Register 0 Reset Value 001F 1F00 LISTm m 1 7 List Register m Reset Value 0100 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rh rh Field Description BEGIN 7 C rh List Begin BEGIN indicates the number of the first message object in list m END 15 8 rh List End END indicates the number of the last message object in list m SIZE 23 16 rh List Size SIZE indicates the
193. ART Fixed Baud Rate In mode 2 the UART behaves as a 9 bit serial port A start bit 0 8 data bits plus a programmable 9th bit and a stop bit 1 are transmitted on TXD or received on RXD The 9th bit for transmission is taken from TB8 SCON 3 while for reception the 9th bit received is placed in RB8 SCON 2 The transmission cycle is activated by a write to SBUF The data is transferred to the transmit register and TB8 is copied into the 9th bit position At phase 1 of the machine cycle following the next rollover in the divide by 16 counter the start bit is copied to TXD and data is activated one bit time later One bit time after the data is activated the data starts shifting right For the first shift a stop bit 1 is shifted in from the left and for subsequent shifts zeros are shifted in When the TB8 bit gets to the output position the control block executes one last shift and sets the TI bit Reception is started by a high to low transition on RXD sampled at 16 times the baud rate The divide by 16 counter is then reset and 1111 1111 is written to the receive register If a valid start bit 0 is then detected based on two out of three samples it is shifted into the register followed by 8 data bits If the transition is not followed by a valid Start bit the controller goes back to looking for a high to low transition on RXD When the Start bit reaches the leftmost position the control block executes one last shift then loads
194. Applicable 1 Mov R7 XX 5SFFB 01 OFF 00 is reserved NAD OFF 5SFFC 01 OFF 00 is reserved 1 The address shown in the table assumes a E with 24 Kbytes of P Flash For variants with smaller P Flash sizes the address used will be the address of the uppermost P Flash bank plus the offset For example a 20 Kbytes Flash variant will have the NAD address at 4FFC User s Manual 18 26 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader The default NAD value is assumed in the following two cases for protected Flash 1 LSB of user password is 0 2 LSB of user password is 1 and user programmed NAD is invalid Note For a variant device with LIN BSL support it must be ensured that a valid NAD is programmed before protecting the device Device access is not granted without the correct NAD in place User s Manual 18 27 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader 18 2 MultiCAN BSL Mode MultiCAN BSL can be entered only when Flash is not protected else user mode is entered instead and code from memory address location 0000 will be executed The MultiCAN BSL protocol is divided into two sections hardware initialisation and software communication In the hardware initialisation section XC886 888 is configured to use an external oscillator and CAN node 0 for communication The use of external oscillator is to ensure an optimal performance
195. By DATAO Reset 00 Bit Field CAN Data Register 0 Type CAN Data Register 1 CAN Data Register 2 g a CAN Data Register 3 Type 3 5 5 14 OCDS Registers The OCDS SFRs can be accessed in the mapped memory area RMAP 1 Table 3 16 OCDS Register Overview Addr RegisterName Bt 7 6 5 4 3 2 1 oO RMAP 1 MMCR2 Reset 1U Bit Field eee EXBC ae sea ALTDI MMEP Cee JENA Monitor Mode Control 2 Register Type MMCR Reset 00 Bit Field a EEES Co Ea ane Monitor Mode Control Register lt a P COMNEN F24 MMSR Reset 00y Bit Field IA MBCIN Co HE co cI Monitor Mode Status Register Type F34 MMBPCR Reset 00y Bit Field E ESEN ca a ca Breakpoints Control Register Type F44 MMICR Reset 00y Bit Field EA E COMR s MMUI me a RRIE Monitor Mode Interrupt Control ST EL EP Register 5 NESEAETEN MMDR Reset 00y Bit Field MMRR Monitor Mode Data Transfer Register Type rh Receive HWBPSR Reset 00y Bit Field A BPSEL Hardware Breakpoints Select Register Tye Type E a a HWBPDR Reset 004 Bit Field HWBPxx Hardware Breakpoints Data MMWR1 Reset 00y Bit Field MMWR1 Monitor Work Register 1 W User s Manual 3 40 Memory Organization V 1 2 lt o_o o_o M Pi oS on J Cinfine on XC886 888CLM Memory Organization Table 3 16 OCDS Register Overview cont d Addr RegisterName Bt 7 6 5 4 3 2 1 oO MMWR2 Reset 004 Bit Field MMWR2 Monitor Work R
196. C in register NMISR is set and if enabled via NMICON NMIECC an NMI to the CPU is triggered The 16 bit Flash address at which the ECC error occurs is stored in the system control SFRs FEAL and FEAH and can be accessed by the interrupt service routine to determine the Flash bank sector in which the error occurred User s Manual 4 12 V1 1 2007 05 Flash Memory V 1 0 Cinfin eon XC886 888CLM Flash Memory 4 6 1 Flash Error Address Register The FEAL and FEAH registers together store the 16 bit Flash address at which the ECC error occurs FEAL Flash Error Address Register Low Reset Value 00 7 6 5 4 3 2 1 0 ECCERRADDR rh Field Bits Type Description ECCERRADDR _ 7 0 ECC Error Address Value 7 0 FEAH Flash Error Address Register High Reset Value 00 7 6 5 4 3 2 1 0 ECCERRADDR rh Field Bits Type Description ECCERRADDR _ 7 0 ECC Error Address Value 15 8 User s Manual 4 13 V1 1 2007 05 Flash Memory V 1 0 Cinfin eon XC886 888CLM Flash Memory 4 7 In System Programming In System Programming ISP of the Flash memory is supported via the Boot ROM based Bootstrap Loader BSL allowing a blank microcontroller device mounted onto an application board to be programmed with the user code and also a previously programmed device to be erased then reprogrammed without removal from the board This feature offers ease of use and versatility for the embedded design ISP is supported through the
197. C886 888 e High performance XC800 Core compatible with standard 8051 processor two clocks per machine cycle architecture for memory access without wait state two data pointers e On chip memory 12 Kbytes of Boot ROM 256 bytes of RAM 1 5 Kbytes of XRAM 24 32 Kbytes of Flash or 24 32 Kbytes of ROM with additional 4 Kbytes of Flash includes memory protection strategy e O port supply at 3 3 or 5 0 V and core logic supply at 2 5 V generated by embedded voltage regulator e Power on reset generation e Brownout detection for core logic supply e On chip OSC and PLL for clock generation PLL loss of lock detection e Power saving modes slow down mode idle mode power down mode with wake up capability via RXD or EXINTO clock gating control to each peripheral e Programmable 16 bit Watchdog Timer WDT e Six ports Up to 48 pins as digital I O 8 pins as digital analog input e 8 channel 10 bit ADC e Four 16 bit timers Timer 0 and Timer 1 TO and T1 Timer 2 and Timer 21 T2 and T21 e Multiplication Division Unit for arithmetic calculation MDU e Software libraries to support floating point and MDU calculations e CORDIC Coprocessor for computation of trigonometric hyperbolic and linear functions e MultiCAN with 2 nodes 32 message objects e Capture compare unit for PWM signal generation CCU6 e Two full duplex serial interfaces UART and UART1 e Synchronous serial channel SSC
198. CSRO IRCON1 3 ADC_1 ADCSRI1 IRCON1 4 MultiCAN_ 1 CANSRC1 IRCON1 5 MultiCAN 2 CANSRG2 IRCON1 6 y Bit addressable 4 Request flag is cleared by hardware PDOs 0CQO0OHMW a5 o 7 Figure 5 2 Interrupt Request Sources Part 2 User s Manual 5 3 V1 1 2007 05 Interrupt System V 1 0 infin eon XC886 888CLM Interrupt System Priority Level SSC_EIR EIR IRCON1 0 SSC_TIR TIR gt o IRCON1 1 ESSO ESSC IRCON1 2 P ee 5 EXINT2 l IRCONO 2 i EXICONO 4 5 g Eb z UARTI UART1_SCON 0 gt 1 o q UART1_SCON 1 Timer 21 A n Overflow TF2 S c T21_T2CON 7 EX2 e gt 1 IEN1 2 T21EX o TA 9 EXEN2 T21_T2CON 6 T21_T2CON 3 EDGES mp EL Normal Divider NDOV T21_T2MOD 5 Overflow UART1_FDCON 2 Cordic EOC CDSTATC 2 IRDY MDUSTAT O UO Cc IERR MDUSTAT 1 A Bit addressable d Request flag is cleared by hardware Eq J C Figure 5 3 Interrupt Request Sources Part 3 User s Manual 5 4 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System EINT3 IRCONO 3 EXICONO 6 7 EINT4 z IRCONO 4 o EXICON1 0 1 X n O X gt 1 O O g EINT5 O ve O IRCONO 5 EXM S IEN1 3 EXICON1 2 3 u e TE n TA c ii IRCONO 6 EXICON1 4 5 MultiCAN_ 3 CANSRG3 IENO 7 Bit addressable 4 Request flag is cleared by hardware EXINT6 HN Dlje Figure 5 4 Interrupt Request Sources Part 4 User s Manual 5 5 V1 1 2
199. CTRhn LIST gt 0 After reset all message objects are unallocated This means that they are assigned to the list of unallocated elements with MOCTRn LIST 0 After this initial allocation of the message objects caused by reset the list of all unallocated message objects is ordered by message number predecessor of message object n is object n 1 successor of object n is object n 1 15 1 4 3 Connection to the CAN Nodes Each CAN node is linked to one unique list of message objects A CAN node performs message transfer only with the message objects that are allocated to the list of the CAN node This is illustrated in Figure 15 7 Frames that are received on a CAN node may only be stored in one of the message objects that belongs to the CAN node frames to be transmitted on a CAN node are selected only from the message objects that are allocated to that node as indicated by the vertical arrows There are more lists eight than CAN nodes two This means that some lists are not linked to one of the CAN nodes A message object that is allocated to one of these unlinked lists cannot receive messages directly from a CAN node and it may not transmit messages FIFO and gateway mechanisms refer to message object numbers and not directly to a specific list The user must take care that the message objects targeted by FIFO gateway belong to the desired list The mechanisms allow working with lists that do not belong to this CAN node User s Man
200. Channel CC63 Low Reset Value 00 7 6 5 4 3 2 1 0 rw Field Description CC63SL Shadow Register for Channel CC63 Compare Value Low Byte The contents of bit field CC63S are transferred to the bit field CC63V during a shadow transfer CC63SRH Capture Compare Shadow Register for Channel CC63 High Reset Value 00 7 6 5 4 3 2 1 0 rw Field Description CC63SH Shadow Register for Channel CC63 Compare Value High Byte The contents of bit field CC63S are transferred to the bit field CC63V during a shadow transfer User s Manual 14 54 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 3 4 Capture Compare Control Registers The Compare State Register CMPSTAT contains status bits monitoring the current capture and compare state and control bits defining the active passive state of the compare channels CMPSTATL Compare State Register Low Reset Value 00 4 3 2 1 0 baa Po CC lt oC 3 0 62ST 61ST 60ST rh rh rh rh rh Field Bits Type Description CC6xST 0 1 rh Capture Compare State Bits x 0 1 2 3 2 6 Bits CC6xST monitor the state of the capture compare channels Bits CC6xST are related to T12 bit CC63ST i related to T13 In compare mode the timer count is less than the compare value In capture mode the selected edge has not yet been detected since the bit has been reset by software the last time In compare mode the counter value is greater than or equal to the compare value In capture mode
201. D orL Control Table 10 4 MRx Registers Register Roles of registers in ee Division Division Shift Abbreviations e D end Dividend 1st operand of division User s Manual 10 7 V1 1 2007 05 MDU V2 1 Cinfin eon XC886 888CLM Multiplication Division Unit e Dror Divisor 2nd operand of division e Mand Multiplicand 1st operand of multiplication e Mor Multiplicator 2nd operand of multiplication e Pr Product result of multiplication e Rem Remainder e Quo Quotient result of division e L means that this byte is the least significant of the 16 bit or 32 bit operand e H means that this byte is the most significant of the 16 bit or 32 bit operand The MDx registers are built with shadow registers which are latched with data from the actual registers at the start of a calculation This frees up the MDx registers to be written with the next set of operands while the current calculation is ongoing MDx and MRx registers not used in an operation are undefined to the user For normalize and shift operations the registers MD4 and MR4 are used as shift input and output control registers to specify the shift direction and store the number of shifts performed User s Manual 10 8 V1 1 2007 05 MDU V2 1 mfin eon XC886 888CLM i Multiplication Division Unit 10 5 1 Operand and Result Registers The MDx and MRx registers are used to store the operands and results of a calculation MD4 and MR4 are also u
202. DE bit of the received frame is don t care In this case message objects with standard and extended frames are accepted e The identifier of the received frame matches the identifier stored in the register MOARn as qualified by the acceptance mask in the MOAMRnh register This means that each bit of the received message object identifier is equal to the bit field MOARnhn ID except those bits for which the corresponding acceptance mask bits in bit field MOAMRn AM are cleared These identifier bits are don t care for reception Among all messages that fulfill all six qualifying criteria the message object with the highest receive priority wins receive acceptance filtering and becomes selected to store the received frame All other message objects lose receive acceptance filtering The following priority scheme is defined for the message objects A message object a MOa has higher receive priority than a message object b MOb if the following two conditions are fulfilled see Page 15 93 1 MOa has a higher priority class than MOb This means the 2 bit priority bit field MOARa PRI must be equal or less than bit field MOARb PRI 2 If both message objects have the same priority class MOARa PRI MOARb PRI MOb is a list successor of MOa This means that MOb can be reached by means of successively stepping forward in the list starting from a User s Manual 15 21 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Con
203. Data Register HWBPSR Hardware Breakpoints Select Register HWBPDR Hardware Breakpoints Data Register MMWR1 EB Monitor Work Register 1 MMWR2 EC Monitor Work Register 2 Additionally there are 8 indirectly accessible OCDS registers e 8 Hardware Breakpoint registers accessible via HWBPSR Register Select and HWBPDR Data Table 17 2 Hardware Breakpoint Registers 8 16 bit Addresses Register Register Full Name Short Name HWBPOL Hardware Breakpoint 0 Low Register HWBPOH Hardware Breakpoint 0 High Register HWBP1L Hardware Breakpoint 1 Low Register HWBP1H Hardware Breakpoint 1 High Register HWBP2L Hardware Breakpoint 2 Low Register HWBP2H Hardware Breakpoint 2 High Register HWBP3L Hardware Breakpoint 3 Low Register HWBP3H Hardware Breakpoint 3 High Register User s Manual 17 9 V1 1 2007 05 OCDS V 1 0 Cinfin eon XC886 888CLM On Chip Debug Support The OCDS registers are exclusively dedicated to the on chip Monitor program and the user should not write into them Anyway a big part of these registers or separate bits fields are protected and can not be written by user software but only by the firmware in two modes of XC886 888 e Startup mode while the Bootcode is executed after reset the user code is still not started e Monitor mode while the Monitor program is running the user code is in break Therefore an unintentional access to OCDS registers by the user software can not disturb the normal debug functionality 17
204. ENSI OR ADC seq _reosrc flow Figure 16 5 Multi Stage Queue The automatic refill feature can be activated RF 1 to allow automatic re insertion of the pending request into the queue stage after a successful execution conversion start Otherwise the pending request will be discarded once it is executed While the automatic refill feature is enabled software should not write data to the queue input register The write address in which to enter a conversion request is given by the write only queue input register QINRO If there is still an empty stage V 0 in the queue the written value will be stored there bit V becomes set or else the write action is ignored In the event that a requested conversion is aborted after its start its setting is stored in the backup register bit V becomes set Refer to Section 16 7 6 for description of the sequential request source registers User s Manual 16 12 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 4 2 Request Source Control lf the conversion requested by the source is not related to an external trigger event EXTR 0 the valid bit V 1 directly requests the conversion by setting signals REQPND and REQCHNRYV to 1 In this case no conversion will be requested if V 0 A gating mechanism allows the user to enable disable conversion requests according to bit ENGT conversion started REQPND REQCHNRV ADC seq _regsrc_corird
205. ESULT DRC CHNR gt 4 Bit Field ADC_RESR1H_ Reset 00y Result Register 1 High RESULT lt gt i F gt k gt 4 E ADC_RESR2L Reset 00y Bit Field DRC CHNR Result Register 2 Low F ADC_RESR2H Reset 00y Bit Field RESULT Result Register 2 High O gt L I I I L L Type Bit Field U RESULT lt DRC CHNR rh 2 ADC_RESR3L_ Reset 00 Result Register 3 Low 4 4 4 gt 4 lt lt lt lt lt O O O O O iq iq a i Dg als gt User s Manual 3 30 Memory Organization V 1 2 lt s as nN Pi oO on J infine on XC886 888CLM Memory Organization Table 3 9 ADC Register Overview cont d Addr Register Name Bit 7 6 5 4 3 274 oO D3 ADC_RESR3H Reset 00 Bit Field RESULT iS RMAP 0 PAGE 3 ADC_RESRAOL Reset 00 Bit Field RESULT CHNR Result Register 0 View A Low Type ADC_RESRAOH Reset 00y Bit Field RESULT Result Register 0 View A High a ee sr ADC_RESRA1L Reset 00y Result Register 1 View A Low ADC_RESRA1H Reset 00y DH Pen Result Register 1 View A High Bit Field RESULT Type Bit Field RESULT CHNR ADC_RESRA2L Reset 00 Result Register 2 View A Low ADC_RESRA2H Reset 00y Bit Field RESULT Result Register 2 View A High Type rh ADC_RESRASL Reset 00 Bit Field RESULT CHNR Result Register 3 View A Low Type ADC_RESRA3H Reset 00y Bi
206. Enable Interrupt for Trap Flag 0 No interrupt will be generated if the set condition for bit TRPF in register IS occurs 1 An interrupt will be generated if the set condition for bit TRPF in register IS occurs The interrupt line that will be activated is selected by bit field INPERR r Enable Interrupt for Correct Hall Event 0 No interrupt will be generated if the set condition for bit CHE in register IS occurs 1 An interrupt will be generated if the set condition for bit CHE in register IS occurs The interrupt line that will be activated is selected by bit field INPCHE ENTRPF ENCHE a a User s Manual 14 89 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field amr Description ENWHE 5 nana Interrupt for Wrong Hall Event No interrupt will be generated if the set condition for bit WHE in register IS occurs An interrupt will be generated if the set condition for bit WHE in register IS occurs The interrupt line that will be activated is selected by bit field INPERR Enable Idle This bit enables the automatic entering of the idle state bit IDLE will be set after a wrong hall event has been detected bit WHE is set During the idle state the bit field MCMP is automatically cleared 0 The bit IDLE is not automatically set when a wrong hall event is detected g a ENIDLE 1 The bit IDLE is automatically set when a wrong hall event is detected Enable Multi Channel Mode Shadow
207. Events 5 1 Normalize operation 10 3 O On Chip Debug Support 17 1 Register description 17 9 Register map 17 9 On chip oscillator 7 11 P PO register description 6 17 P1 register description 6 24 P2 register description 6 30 P3 register description 6 36 P4 register description 6 43 P5 register description 6 50 Parallel ports 6 1 Bidirectional port structure 6 3 Driver 6 2 6 8 General port structure 6 3 General register description 6 5 Input port structure 6 4 Kernel registers 6 5 Direction control register 6 7 V1 1 2007 05 Cinfineon Offset addresses 6 11 Open drain control register 6 8 Normal mode 6 2 6 8 Open drain mode 6 2 6 8 Parallel Read 4 5 Parallel request source 16 14 Password 3 Peripheral clock management 8 5 Permanent arbitration 16 9 Personal computer host 4 14 P Flash 4 2 4 3 P Flash bank pair 4 2 Phase Locked Loop 7 11 Changing PLL parameters 7 13 Loss of Lock operation 7 12 Loss of Lock recovery 7 12 Pin Configuration 1 6 PLL Loss of lock 7 12 Startup 7 12 PLL base mode 7 13 PLL mode 7 14 Power control 2 6 Power saving modes 8 1 Power supply system 7 1 Power down mode 7 16 8 3 Entering power down mode 8 3 Exiting power down mode 8 4 Power down wake up reset 7 6 Power on reset 7 2 7 3 Prescaler mode 7 14 Prewarning period 9 2 Processor architecture 2 1 Instruction timing Machine cycle 2 6 Register description 2 3 Program control 2 1 Program counter 2 3 Program Flash 4 2 4 3 Para
208. FF hassei BBE2 BBE1 BBEO Q ABFF ossis ABE2 ABE1 ABEO LO LO mo g mog 568 568 OO gq O Og ae Oye BAG aR BA22 BA21 BA20 WOR cosine encanta AA22 AA21 AA20 Z BAARI pae BA02 BA01 BA0O A eee AA02 AAO1 AA00 BOFF BeNOR Tee ee OE AT B9E2 BOE B9EO A9FF E ie EL aL E A9E2 A9E1 a AQE0 op o an g ang a 548 Bou 3S B83F Sire heer Hen ae IRA en aR Ne B822 B821 B820 AS A83F AOD aR A Ea URE RE Caer ier A822 A821 A820 we B81F OSCR Ore Pere ee B802 B801 B800 A81 Fy E EC Te A A802 A801 A800 B7FF cssscssssssssesseseseseseeseseseens B7E2 B7E1 B7EO ATER sueaidealsidacassstisashisormnecis A7E2 A7E1 A7EO mn fee lt 2 oe Sag Sag o 41 1 B45F seuaGd ec ouachieee cess a B442 B441 B440 OS A45F E E A EAT S A442 A441 A440 ns B43F E P EEEE E ct B4224 B421 B420 A43F P AE EE A422 A421 A420 B41F PA EEE B402 B401 B400 A41 Fj SEEE TER T A402 A401 A400 ok el a late Mee erg iee a ered nee B3E2 B3E1 B3E0 AFE E eee ee A3E2 A3E1 A3E0 D 5 o zog Bog BOSF Pe Ur ene STN E E B042 B041 B040 DE AOSF RNG PASE Ea AE TA AT E A042 A041 A040 0z BO3F Sa ten aR Pope A aE oh ena tar Tee em B022 B021 B020 A03F E tea aera Sp UR TEE TENG TC A022 A021 A020 BO1F SRP Rae EO E a acre ne B002 B001 B000 A01 Fu R A aA eM nr A002 A001 A000 WL WL Address Address Figure 4 6 D Flash Wordline Addresses Data User s Manual 4
209. Field CC60VH Capture Compare Register for Channel CC60 High CCU6 CC61RL Reset 00 Capture Compare Register for Channel CC61 Low FDy CCU6_CC61RH Reset 00y Capture Compare Register for Type Bit Field CC 61VL Type Bit Field CC61VH Channel CC61 High Type CCU6_CC62RL Reset 00y Bit Field CC62VL Capture Compare Register for CCU6_CC62RH Reset 00 4 Bit Field Field CC62VH Capture Compare Register for RMAP 0 PAGE 2 CCU6_T12MSELL Reset 00 Bit Field MSEL61 MSEL60 T12 Capture Compare Mode Select CCU6_T12MSELH Reset 00 Bit Field DBYP HSYNC MSEL62 T12 Capture Compare Mode Select Register High Type CCU6_IENL Reset 00 Capture Compare Interrupt Enable Register Low Bit Field ae 2y ENCC ENCC ENCC ENCC ENCC ENCC 62F 62R 61F 61R 60F 60R etal ele le aac IDLE CHE TRPF 3PM 3CM me ie e ee ie CCU6_INPL Reset 404 BitField INPCHE INPCC62 INPCC6 EER Type CCU6_IENH Reset 00y Bit Field Capture Compare Interrupt Enable Capture Compare Interrupt Node Pointer Register Low a a a a CCU6_INPH Reset 394 Bit Field mama INPT13 INPT12 INPERR Capture Compare Interrupt Node Pointer Register High Type CCU6_ISSL Reset 00 Ce Field am ST12 SCC6 SCC6 SCC6 SCC6 SCCE6 SCCE Capture Compare Interrupt Status PM OM 2F 2R 1F 1R EN EE Set Register Low we ow iw fw iw fw ow CCU6_ISSH Reset 00y Bit Field SSTR SIDLE SWHE
210. Figure 13 1 Timer 0 Mode 0 13 Bit Timer Counter User s Manual 13 4 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 1 2 2 Mode 1 Mode 1 operation is similar to that of mode 0 except that the timer register runs with all 16 bits Mode 1 operation for Timer 0 is shown in Figure 13 2 TOS 0 T To _ 8 Bits 8 Bits Interrupt TOS 1 oo Control 1 Z N EXINTO T A Figure 13 2 Timer 0 Mode 1 16 Bit Timer Counter User s Manual 13 5 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 1 2 3 Mode 2 In Mode 2 operation the timer is configured as an 8 bit counter TLx with automatic reload as shown in Figure 13 3 for Timer 0 An overflow from TLx not only sets TFx but also reloads TLx with the contents of THx that has been preset by software The reload leaves THx unchanged i TLO 8 Bits Interrupt TOS 1 TO Control Reload TRO GATEO Y N EXINTO INA Figure 13 3 Timer 0 Mode 2 8 Bit Timer Counter with Auto Reload User s Manual 13 6 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 1 2 4 Mode 3 In mode 3 Timer O and Timer 1 behave differently Timer O in mode 3 establishes TLO and THO as two separate counters Timer 1 in mode 3 simply holds its count The effect is the same as setting TR1 0 The logic for mode 3 operation for Timer 0 is shown in Figure 13 4 TLO uses the Timer 0 control bits GATEO TRO and TFO while T
211. Flash_Bank_Pair1 byte selects sectors 0 and 2 of P Flash Banks 2 and 3 for erase PFlash_Bank_Pair2 The sectors 0 to 2 of P Flash Bank Pair 2 Banks 4 and 5 are represented by bits 0 to 2 For example a value of 07 in the PFlash_Bank_PairO byte selects sectors 0 1 and 2 of P Flash Banks 4 and 5 for erase Not used The byte is not used and will be ignored Hence the sectors of different P Flash Banks can be erased at one time When Option 40 this mode is used to erase the D Flash sector s The header block has the following structure The Header Block Mode Data 5 bytes 4 Checksum sion 4 DFlash_ DFlash_ DFlash_ DFlash_ Option j Bank0_L Bank0_H Bank1_L Bank1_H 40 Mode Data Description DFlash_Bank0_L The sectors 0 to 7 of D Flash BankO are represented are represented by bits 0 to 7 For example a value of 12 in the DFlash_BankO_L byte selects sectors 1 and 4 of D Flash Bank 0 for erase DFlash_Bank0O_H The sectors 8 and 9 of D Flash Bank 0 are represented are represented by bits 0 to 1 For example a value of 01 in the DFlash_BankO_H byte selects sector 8 of D Flash Bank 0 for erase DFlash_Bank1_L The sectors 0 to 7 of D Flash Bank1 are represented are represented by bits 0 to 7 For example a value of 12 in the DFlash_Bank1_L byte selects sectors 1 and 4 of D Flash Bank 1 for erase DFlash_Bank1_H The sectors 8 and 9 of D Flash Bank 1 are represented are represented
212. For each Flash bank the user can select one sector or a combination of several sectors for erase Before calling this subroutine the Flash NMI can be enabled via bit NMIFLASH in register NMICON so that the Flash NMI service routine is entered once the erase operation on the Flash bank s is completed Before calling this subroutine the user must ensure that RO R1 and R3 to R7 of the Current Register Bank are set accordingly see Table 4 2 Also protected Flash banks should not be targeted for erase If valid inputs are available before calling the subroutine the microcontroller will continue with the initialization sequence exit the Subroutine and then return to the user program code User program code will continue execution from where it last stopped until the Flash NMI event is generated bit FNMIFLASH in register NMISR is set and if enabled via NMIFLASH an NMI to the CPU is triggered to enter the Flash NMI service routine see Figure 4 9 At this point all Flash banks are in ready to read mode Table 4 2 Flash Erase Subroutine Subroutine DFF9 FLASH ERASE Input RO Select sector s to be erased for D Flash bank 0 LSB represents sector 0 MSB represents sector 7 R1 Select sector s to be erased for D Flash bank 0 LSB represents sector 8 bit 1 represents sector 9 R3 Select sector s to be erased for D Flash bank 1 LSB represents sector 0 MSB represents sector 7 R4 Select sector s to be erased for D Flash bank
213. HO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now sets TF1 upon overflow and generates an interrupt if ET1 is set Mode 3 Is provided for applications requiring an extra 8 bit timer When Timer 0 is in mode 3 and TR1 is set Timer 1 can be turned on by switching it to any of the other modes and turned off by switching it into mode 3 Timer Clock Interrupt TOS 1 TO Control Interrupt Figure 13 4 Timer 0 Mode 3 Two 8 Bit Timers Counters User s Manual 13 7 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 1 3 Port Control When functioning as an event counter Timer O and 1 count 1 to 0 transitions at their external input pins TO and T1 which can be selected from two different sources TO_0 and T0_1 for Timer 0 and T1_0 and T1_1 for Timer 1 This selection is performed by the SFR bits MODPISEL2 TOIS and MODPISEL2 T1IS MODPISEL2 Peripheral Input Select Register 2 Reset Value 00 7 6 5 4 3 2 1 0 r rw rw rw rw Field Bits Type Description TOIS rw TO Input Select 0 Timer O Input TO_O is selected 1 Timer O Input TO_1 is selected T11S 1 rw T1 Input Selectt 0 Timer 1 Input T1_0 is selected 1 Timer 1 Input T1_1 is selected 0 7 4 r Reserved Returns 0 if read should be written with O User s Manual 13 8 V1 1 2007 05 Timers V 1 0 Cinfine on XC886 888CLM Timers 13 1 4 Register Map Seven SFRs control
214. Hence routine service of the WDT confirms that the system is functioning properly This ensures that an accidental malfunction of the XC886 888 will be aborted in a user specified time period The WDT is by default disabled In debug mode the WDT is default suspended and stops counting its debug suspend bit is default set i e MODSUSP WDTSUSP 1 Therefore during debugging there is no need to refresh the WDT Features e 16 bit Watchdog Timer e Programmable reload value for upper 8 bits of timer e Programmable window boundary e Selectable input frequency of foo 2 or foc 128 User s Manual 9 1 V1 1 2007 05 Watchdog Timer V1 0 Cinfin eon XC886 888CLM Watchdog Timer 9 1 Functional Description The Watchdog Timer is a 16 bit timer which is incremented by a count rate of fp 2 or feci 128 This 16 bit timer is realized as two concatenated 8 bit timers The upper 8 bits of the Watchdog Timer can be preset to a user programmable value via a watchdog service access in order to vary the watchdog expire time The lower 8 bits are reset on each service access Figure 9 1 shows the block diagram of the watchdog timer unit WDT WDTREL Control Clear WDT Low Byte g WDT High Byte Overflow Time out Control amp ENMIWDT Window boundary control Figure 9 1 WDT Block Diagram If the WDT is enabled by setting WDTEN to 1 the timer is set to a user defined start value and begins counting up It must be serviced bef
215. Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit ICC62R if enabled by bit ENCC62R or for bit ICC62F if enabled by bit ENCC62F 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected INPCHE rw Interrupt Node Pointer for the CHE Interrupt This bit field defines the interrupt output line which is activated due to a set condition for bit CHE if enabled by bit ENCHE or for bit STR if enabled by bit ENSTR 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected User s Manual 14 91 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 INPH Capture Compare Interrupt Node Pointer Register High Reset Value 39 7 6 5 4 3 2 1 0 0 INP INP INP T13 T12 ERR r rw rw rw Field Description INPERR Interrupt Node Pointer for Error Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit TRPF if enabled by bit ENTRPF or for bit WHE if enabled by bit ENWHE 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected T INPT12 2 Interrupt Node Pointer for Timer T12 Int
216. JTAGT JTAGT EXINT EXINT EXINT URRIS Peripheral Input Select Register EN EN EN EN EN Type IRCONO Reset 00 Bit Field ae ae an a EE a Interrupt Request Register 0 a coc IRCON1 Reset 00 Bit Field CANS CANS ADCS ADCS Interrupt Request Register 1 RC2 RC1 R1 RO IRCON2 Reset 001 Bit Field CANS CANS Interrupt Request Register 2 RC3 RCO EXICONO Reset FO Bit Field EXINT3 EXINT2 EXINT1 EXINTO External Interrupt Control EXICON1 Reset 3Fy Bit Field EXINT6 EXINT5 External Interrupt Control NMICON Reset 00y Bit Field a NMI NMI NMI NMI NMI NMI NMI Control Register ECC VDDP VDD OCDS FLASH a E me r w w w User s Manual 3 24 V1 1 2007 05 Memory Organization V 1 2 infin eon XC886 888CLM Memory Organization Table 3 6 SCU Register Overview cont d Addr Register Name Bt 7 6 5 4 3 2 4 0 NMISR Reset 00 Bit Field FNMI FNMI FNMI FNMI FNMI FNMI FNMI NMI Status Register ECC VDDP VDD OCDS FLASH PLL WDT we r om on wm own rom om on BCON Reset 00 Bit Field BGSEL 0 BRDIS BRPRE Baud Rate Control Register Type BG Reset 004 Bit Field BR_VALUE Baud Rate Timer Reload D Bee EOFS EI Register FDCON Reset 004 ale y BDE Type Bit Field NDOV DM FDEN Fractional Divider Control Register 9 Type Bit Field rw FDSTEP Reset 00 Fractional Divider Reload Register cae Type FDRES Reset 00 4 Fractional Divider
217. LM Interrupt System MODPISEL Peripheral Input Select Register Reset Value 00 7 6 5 4 3 2 1 0 0 URRISH JTAGTDIS tad EXINT2IS EXINT1IS EXINTOIS URRIS r rw rw rw rw rw rw rw Field Com Description EXINTOIS Interrupt 0 Input Select External Interrupt Inout EXINTO_O is selected External Interrupt Inout EXINTO_1 is selected EXINT11S onan Interrupt 1 Input Select External Interrupt Inout EXINT1_0 is selected External Interrupt Inout EXINT1_1 is selected EXINT2IS ee Interrupt 2 Input Select External Interrupt Inout EXINT2_0 is selected External Interrupt Input EXINT2_1 is selected 0 ieee a O if read should be written with 0 MODPISEL1 Peripheral Input Select Register 1 Reset Value 00 7 6 9 4 3 2 1 0 emo o umim ates HTAGTONS TASTA r r rw rw rw rw Field Description EXINT6IS ae Interrupt 6 Input Select External Interrupt Input EXINT6_0 is selected External Interrupt Inout EXINT6_1 is selected 0 6 5 Reserved Returns 0 if read should be written with 0 User s Manual 5 23 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System TCON Timer and Counter Control Status Register Reset Value 00 7 6 5 4 3 2 0 rwh rw rwh rw rwh rw rwh rw Field Description ITO External Interrupt 0 Level Edge Trigger Control Flag 0 Low level triggered external interrupt 0 is selected 1 Falling edge triggered external interrupt 0 is selected IT1 External Interrupt 1 Level Edge Tri
218. M On Chip Debug Support 17 3 1 1 Hardware Breakpoints Hardware breakpoints are generated by observing certain address buses within the XC886 888 system The bus relevant to the hardware breakpoint type is continuously compared against certain registers where addresses for the breakpoints have been programmed The hardware breakpoints can be classified into different types e Depending on the address bus supervised Breakpoints on Instruction Address Program Memory Address PROGA is observed Breakpoints on IRAM Address Internal Data Memory Addresses for read write GOURCE_A DESTIN_A are observed e Depending on the way comparison is done Equal breakpoints Comparison is done only against one value the break event is raised when just this value is matched Range breakpoints Comparison is done against two values the break event is raised when a value observed is found belonging to the range between two programmed values inclusively Breakpoints on Instruction Address These Instruction Pointer IP breakpoints are generated when a break address is matched for the first byte of an instruction that is going to be executed i e for the address within Program Memory where an instruction opcode is fetched from Note In case of 2 and 3 byte instructions the break will not be generated for addresses of the second and third instruction bytes The IP breakpoints are of Break Before Make type therefore the instruction at t
219. Master Request Command Frame else wait for next frame Dont Invalid Don t Save LIN message to XRAM and care jump to Flash 0000 Yes Cy LIN Don t Valid Invalid Save LIN message to XRAM and care al jump to Flash 0000 lt V Qo Yes i LIN Valid Valid Valid Execute command Yes 7 a Invalid Valid Message is ignored Wait for next frame Yes 3C Prog Invalid Dont Don t Message is ignored Wait for next care care frame Yes 3C Prog Valid Invalid Error flag is triggered Wait for Response frame to reflect error Yes 3C Prog vate tc Error flag is triggered Wait for oz Response frame to reflect error Yes 3C Prog Valid Invalid Valid Error flag is triggered Wait for Response frame to reflect error Yes 3C Valid Valid Valid Execute command Yes 3C Invalid Don t Don t Don t Save LIN message to XRAM and care care care jump to Flash 0000 D If Flash content at 0000 is 00 it will stay in BootROM Otherwise it will jump to Flash 00004 If Flash is protected then it will jump to 0000 Valid modes for LIN Checksum are Mode 8 and Mode 9 Other modes are considered invalid Valid modes for Programming Checksum are Mode 0 6 Other modes are considered invalid User s Manual 18 25 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader 18 1 3 11 User Defined Parameter for LIN BSL The NAD Node Address for Diagnostic
220. Mode 3 Two 8 bit timers counters Timer 2 and Timer 21 Features e Selectable up down counting e 16 bit auto reload mode e 1 channel 16 bit capture mode User s Manual 13 1 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 1 Timer 0 and Timer 1 Timer O and Timer 1 can function as both timers or counters When functioning as a timer Timer O and Timer 1 are incremented every machine cycle i e every 2 input clocks or 2 PCLKs When functioning as a counter TimerO and Timer1 are incremented in response to a 1 to 0 transition falling edge at their respective external input pins TO or T1 13 1 1 Basic Timer Operations The operations of the two timers are controlled using the Special Function Registers SFRs TCON and TMOD To enable a timer i e allow the timer to run its control bit TCON TRx is set To select the timer input to be either from internal system clock or external pin the input selector bit TMOD is used Note The x e g TCON TRx in this chapter denotes either 0 or 1 Each timer consists of two 8 bit registers TLx low byte and THx high byte which defaults to 00 on reset Setting or clearing TCON TRx does not affect the timer registers Timer Overflow When a timer overflow occurs the timer overflow flag TCON TFx is set and an interrupt may be raised if the interrupt enable control bit IENO ETx is set The overflow flag is automatically cleared when the interrupt service
221. N 1 Note For safety reasons the user is advised to rewrite WDTCON each time before the WDT is serviced 9 1 1 Module Suspend Control The WDT is by default suspended on entering debug mode The WDT can be allowed to run in debug mode by clearing the bit WOTSUSP in SFR MODSUSP to 0 MODSUSP Module Suspend Control Register Reset Value 01 7 6 5 4 3 2 1 0 r rw rw rw TW rw Field Description WDTSUSP anid Debug Suspend Bit WDT will not be suspended WDT will be suspended 0 7 5 Reserved Returns 0 if read should be written with O User s Manual 9 4 V1 1 2007 05 Watchdog Timer V1 0 Cinfin eon XC886 888CLM Watchdog Timer 9 2 Register Map Five SFRs control the operations of the WDT They can be accessed from the mapped SFR area Table 9 2 lists the addresses of these SFRs Table 9 2 SFR Address List Address Register BB WDTCON BC WDTREL BD WDTWINB BE WDTL BF WDTH 9 3 Register Description The Watchdog Timer Current Count Value is contained in the Watchdog Timer Register WDTH and WDTL which are non bitaddressable read only register The operation of the WDT is controlled by its bitaddressable WDT Control Register WDTCON This register also selects the input clock prescaling factor The register WDTREL specifies the reload value for the high byte of the timer WDTREL Watchdog Timer Reload Register Reset Value 00 7 6 5 4 3 2 1 0 WDTREL rw Field Bits Type Description WDTREL 7 0 rw Watchdo
222. Network MultiCAN Controller Description Transmit Object Remote Monitoring 0 Remote monitoring is disabled Identifier IDE bit and DLC of message object n remain unchanged upon the reception of a matching remote frame 1 Remote monitoring is enabled Identifier IDE bit and DLC of a matching remote frame are copied to transmit object n in order to monitor incoming remote frames Bit RMM applies only to transmit objects and has no effect on receive objects Single Data Transfer lf SDT 1 and message object n is not a FIFO base object then MSGVAL is reset when this object has taken part in a successful data transfer receive or transmit lf SDT 1 and message object n is a FIFO base object then MSGVAL is reset when the pointer to the current object CUR reaches the value of SEL in the FIFO Gateway Pointer Register With SDT 0 bit MSGVAL is not affected Single Transmit Trial If this bit is set then TXRQ is cleared on transmission start of message object n Thus no transmission retry is performed in case of transmission failure Data Length Code Bit field determines the number of data bytes for message object n Valid values for DLC are 0 to 8 A value of DLC gt 8 results in a data length of 8 data bytes but the DLC code is not truncated upon reception or transmission of CAN frames Reserved Read as 0 after reset value last written is read back Should be written with 0 15 89 V1 1 2007 05 Cinfin eo
223. OFSYN bit is set starts upon negative transition set T2RHEN bit T2 is stopped SYN BREAK SYN CHAR 55 tart Wz Bit Check the break field flag bit BRK is set or not k Captured Value 8 bits gt Figure 12 10 LIN Auto Baud Rate Detection With the first falling edge e The Timer 2 External Start Enable bit T2MOD T2RHEN is set The falling edge at pin T2EX is selected by default for Timer 2 External Start bit T2MOD T2REGS is 0 With the second falling edge e Start Timer 2 by the hardware With the third falling edge e Timer 2 captures the timing of 2 bits of SYN byte e Check the Break Field Flag bit FDCON BRK lf the Break Field Flag FDCON BRK is set software may continue to capture 4 6 8 bits of SYN byte Finally the End of SYN Byte Flag FDCON EOFSYN is set Timer 2 is User s Manual 12 29 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces stopped T2 Reload Capture register RC2H L is the time taken for 2 4 6 8 bits according to the implementation Then the LIN routine calculates the actual baud rate sets the PRE and BG values if the UART module uses the baud rate generator for baud rate generation After the third falling edge the software may discard the current operation and continue to detect the next header LIN frame if the following conditions were detected e The Break Field Flag FOCON BRK is not set or e The SYN Byte Err
224. OT fi Base Object PPREV f1 PNEXT f3 Slave Object f2 PPREV C PNEXT f2 Slave Object f1 MultiCAN_msgobj_fifo Figure 15 13 FIFO Structure with FIFO Base Object and n FIFO Slave Objects User s Manual 15 35 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 9 5 Receive FIFO The Receive FIFO structure is used to buffer incoming received remote or data frames A Receive FIFO is selected by setting MOFCRn MMC 0001 in the FIFO base object This MMC code automatically designates a message object as FIFO base object The message modes of the FIFO slave objects are not relevant for the operation of the Receive FIFO When the FIFO base object receives a frame from the CAN node it belongs to the frame is not stored in the base object itself but in the message object that is selected by the base objects MOFGPRn CUR pointer This message object receives the CAN message as if it is the direct receiver of the message However MOFCRn MMC 0000 is implicitly assumed for the FIFO slave object and a standard message delivery is performed The actual message mode MMC setting of the FIFO slave object is ignored For the slave object no acceptance filtering takes place that checks the received frame for a match with the identifier IDE bit and DIR bit With the reception of a CAN frame the current pointer CUR of the base object is set to the number of the next me
225. Operand Register 5 Type 74H MR5 Reset 00 Bit Field MDU Result Register 5 Type 3 5 5 3 CORDIC Registers The CORDIC SFRs can be accessed in the mapped memory area RMAP 1 Table 3 5 CORDIC Register Overview CD_CORDXL Reset 00 Bit Field CORDIC X Data Low Byte Type CD_CORDXH Reset 00y Bit Field CORDIC X Data High Byte Type Cu CD_CORDYL Reset 00y Bit Field CORDIC Y Data Low Byte Type Dy CD CORDYH Reset 00 Bit Field CORDIC Y Data High Byte Type Ev CD CORDZL Reset 001 Bit Field CORDIC Z Data Low Byte Type Fu CD CORDZH Reset 00 Bit Field CORDIC Z Data High Byte Type User s Manual 3 23 V1 1 2007 05 Memory Organization V 1 2 infine on XC886 888CLM Memory Organization Table 3 5 CORDIC Register Overview cont d po eer Naine LES c ae SE ESE SERED CD _STATC Reset 00 Bit Field sca Se sna DMAP ie E nie CORDIC Status and Data Control Register fim e w vow pow ow CD_CON Reset 00 Bit Field X_USI ST_M ROTV BEE CORDIC Control Register EJ EE EJ Type 3 5 5 4 System Control Registers The system control SFRs can be accessed in the mapped memory area RMAP 0 Table 3 6 SCU Register Overview Addr Register Name Bt 7 6 5 4 3 2 1 oO ee RMAP 0 or 1 SYSCONO Reset 04 Bit Field ree RMAP System Control Register 0 Type RMAP 0 SCUPAGE Reset 00y BitFid OP STNR o PAGE A Tyee MODPISEL Reset 00 Bit Field aay
226. P 2 rw Timer 13 Debug Suspend Bit 0 Timer 13 will not be suspended 1 Timer 13 will be suspended 0 7 5 r Reserved Returns 0 if read should be written with O User s Manual 14 27 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 1 10 Port Connection Table 14 2 shows how bits and bit fields must be programmed for the required I O functionality of the CCU6 I O lines This table also shows the values of the peripheral input select registers Table 14 2 CCU6 I O Control Selection Register Bits P4 0 CC60_1 Output User s Manual 14 28 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Table 14 2 CCU6 I O Control Selection cont d Register Bits P3 1 COUT60_0 Output P3 P3_ALTSELOP1 1 Pi 1 P3 a P3_ALTSEL1 P1 O0 8 P4 1 COUT60_ 1 Output P4 P4_ALTSELO P1 1 P1 1 P4 R P4_ALTSEL1 P1 0 P3 DIR P2 1 Output P3 P3_ALTSEL0O P2 1 P2 P3_ALTSEL0O P2 1 1 P3 P3_ALTSEL1 P2 0 8 P2 0 P3 P3_ALTSELOP1 0 P3_ALTSELO P1 O0 P3_ALTSEL1 P1 1 P4 4 CC61 4 Output P4 P4_ALTSELOP4 1 P4_ALTSELO P4 1 P4_ALTSEL1 P4 0 8 P3 3 COUT61_0 a P3 P3_ALTSELOP3 1 P3_ALTSELO P3 1 P3_ALTSEL1 P3 O0 PO 1 COUT61_ 1 ee PO PO_ALTSELOP1 0 PO_LALTSELO P1 O0 8 PO_LALTSEL1 P1 1 User s Manual 14 29 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Table 14 2 CCU6 I O Control Selection cont d Port Lines PISEL Register Bit Input Output Cont
227. Paak CFMOD CFSEL r rw rw rwh rw r 15 14 13 12 11 10 9 8 7 6 o 4 3 2 1 0 CFC rwh Field Description C 0 rwh_ CAN Frame Counter In Frame Count Mode CFMOD 00 this bit field contains the frame count value In Time Stamp Mode CFMOD 01 this bit field contains the captured bit time count value captured with the start of a new frame In all Bit Timing Analysis Modes CFMOD 10 CFC always displays the number of fean clock cycles measurement result minus 1 Example a CFC value of 34 in measurement mode CFSEL 000 means that 35 fean clock cycles have been elapsed between the most recent two dominant edges on the receive input User s Manual 15 72 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Field Description CFSEL aa 16 CAN Frame Count Selection This bit field selects the function of the frame counter for the chosen frame count mode Frame Count Mode BitO If BitO of CFSEL is set then CFC is incremented each time a foreign frame i e a frame not matching to a message object has been received on the CAN bus Bit 1 If Bit 1 of CFSEL is set then CFC is incremented each time a frame matching to a message object has been received on the CAN bus Bit 2 If Bit 2 of CFSEL is set then CFC is incremented each time a frame has been transmitted successfully by the node Time Stamp Mode 000 The frame counter is incremented internally at the beginning
228. RMAP 0 PAGE 0 ADC_GLOBCTR Reset 304 BitFietd ANON DW ete 0 Global Control Register we ow w w o e O ADC_GLOBSTR Reset 00y Bit Field CHNR SAMP BUSY Global Status Register EN Type ADC_PRAR Reset 00 Bit Field ee ae ae CSM1 lt EJ Priority and Arbitration Register User s Manual 3 29 V1 1 2007 05 Memory Organization V 1 2 Infineon lt 00 00 D 00 00 00 O rr Table 3 9 ADC Register Overview cont d RegisierName en 7 6 5 4 3 2 1 0 Oy ADC CER Reset Bry erre BOUND BOUNDD O a en ADCINPCRO Reseno errea STO i External Trigger Control N1 NO jiii T ay ADC_CHCTAO Reset 004 errea o wo f o f msa we a ADC_CHCTRI Reset o0y Btr 0 iee o asa aa Oy ADCLOHCTRA nesevooy trea o e o ms O S e r ee oe a r E EH ry T L T I H BH 2 F Channel Control Register 3 j ADC_CHCTRA Reset 00y etree o io o mesme Channel Control Register 4 Type Type Fy aDc oneTRs Reset 00 etre o o o mesa Channel Control Register 5 Type Type Pe a E E E D34 E Channel Control Register 6 Type we e mwm e m Jee E E Channel Control Register 7 Type Type RMAP 0 PAGE 2 ADC_RESROL Reset 00y BitFieid RESULT o VF DRC CHNR Result Register 0 Low Tye we mr B ADC_RESROH Reset 00y Bit Field RESULT Result Register 0 High n C ADC_RESRIL Reset 00y Bit Field RESULT Result Register 1 Low VF rh R
229. RPE Ih e e saGateinesas AFE2 AFE1 AFEO ahs A o o gt gt 2x Q 2 4Q 5 T Q D ql Mo YM pa an BFOF ssesescecesseceseceeseseeeestee BF82 BF81 BF80 AGE al chenatenae nese irenerauancers AF82 AF81 AF80 2 aia eee eee BF62 BF61 BF60 g Api ee ee eee ee AF62 AF61 AF60 g Cm KE cor g Te E E a2 a2 M_ji Mj BEG E A E an BF02 BFO01 BFOO Niles a amor hcemsccmrc AF02 AFO1 AFOO BEFF ssssssssssssessssessseeesseessnens BEE2 BEE1 BEEO 2 AEFF cscossesssssaseressonesernsessusons AEE2 AEE1 AEEO nr mro Sof Sos ce SEN 00 ae e Na a BEE E BE82 BE81 BE80 AE9F li seecanneectmnctemmenatartis AE82 AE81 AE80 DEVE Ah cette eaters BE62 BE61 BE60 2 Rem E ae eet eee AE62 AE61 AE60 or o Corie Sak Sat 5 g z E x i 3 2 are pe cl E eens BE02 BEO1 BE00 Aer M ereemanamna AE02 AE01 AE00 BDFF essssesessesesssessessseeeeseses BDE2 BDE1 BDEO ADI ec Goetercnrncitannremternonnn ADE2 ADE1 ADEO lo QD LO a 548 bya CO wo O Owo Da D a8 BOIR ener eee eee eee re BD02 BD01 BDOO ADAG coreceeeeneovactepntite ADO2 ADO1 ADOO Solar eee ee BCE2 BCE1 BCEQ ACRE Wee ear a ee ACE2 ACE1 ACEO e t S 2 Da on g O o g E 28 S z L BCIF FRED HEAR HAR OH ROLE Ona Dn aaa BCO02 BCO1 BC00 LL AC1F EEE E E EO E S AC02 ACO1 AC00 Q BB
230. Registers The result registers deliver the conversion results and optionally the channel number that has lead to the latest update of the result register The result registers are available as different read views at different addresses The following bit fields can be read from the result registers depending on the selected read address For details on the conversion result alignment and width see Section 16 4 7 4 Normal Read View RESRx This view delivers the 8 bit or 10 bit conversion result and a 3 bit channel number The corresponding valid flag is cleared when the high byte of the register is accessed by a read command provided that bit RCRx VFCTR is set RESRXL x 0 3 Result Register x Low CA X 2 Reset Value 00 7 6 3 4 3 2 1 0 rh r rh rh rh Field Description CHNR 2 rh Channel Number This bit field contains the channel number of the latest register update DRC Data Reduction Counter This bit field indicates how many conversion results have still to be accumulated to generate the final result for data reduction Os The final result is available in the result register The valid flag is automatically set when this bit field is set to 0 1 1 more conversion result must be added to obtain the final result in the result register The valid flag is automatically reset when this bit field is set to 1 User s Manual 16 53 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converte
231. Result Register Bit Field RESULT Type RMAP 0 PAGE 1 Reset UU Bit Field coal Register y heg Type PMCONO Reset 00 Bit Field Power Mode Control Register 0 PRODID WDT WKRS RST A CDC_ CAN_ MDU_ DIS DIS DIS VERID j Lp ep Type PMCON1 Reset 00 Bit Field Power Mode Control Register 1 CCU_ SSC_ ADC_ DIS DIS DIS DIS ose ORD OSCR RES VCO OSC a LOCK BYP DISC Type vt wm Bit Field KDIV ate FCCF CLKREL SEL Type ow ow Bit Field Type OSC _CON Reset 084 Bit Field OSC Control Register PLL_CON Reset 904 PLL Control Register OSC Type Bit Field 3 J NDIV CMCON Reset 104 Clock Control Register PASSWD Reset 074 Password Register PASS PROT lt S MODE Type FEAL Reset 00y Bit Field Flash Error Address Register Low ECCERRADDR Type FEAH Reset 00H Flash Error Address Register High Bit Field ECCERRADDR Type User s Manual 3 25 V1 1 2007 05 Memory Organization V 1 2 infin eon XC886 888CLM Memory Organization Table 3 6 SCU Register Overview cont d Addr Register Name Bt 7 6 5 4 3 2 4 0 Reset 00 Bit Field TLEN COUT COREL Clock Output Control Register gt MISC_CON Reset 00y Bit Field DFLAS Miscellaneous Control Register HEN We fi XADDRH Reset FO Bit Field ADDRH On chip XRAM Address Higher Order Type IRCON3 Reset 0
232. S and MODPISEL2 T21IS MODPISEL2 Peripheral Input Select Register Reset Value 00 7 6 9 4 3 2 1 0 tris ras fis rs r rw rw rw rw Field Bits Type Description T2IS 2 rw T2 Input Select 0 Timer 2 Input T2_0 is selected 1 Timer 2 Input T2_1 is selected T211S 3 rw T21 Input Select 0 Timer 21 Input T21_0 is selected 1 Timer 21 Input T21_1 is selected 0 7 4 r Reserved Returns 0 if read should be written with O User s Manual 13 20 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 2 7 Low Power Mode lf the Timer 2 and Timer 21 functionalities are not required at all they can be completely disabled by gating off their clock inputs for maximal power reduction This is done by setting bits T2_ DIS in register PMCON1 and T21_ DIS in register PMCON2 as described below Refer to Chapter 8 1 4 for details on peripheral clock management PMCON1 Power Mode Control Register 1 Reset Value 00 7 6 5 4 3 2 1 0 oe CDC_DIS CAN_DIS movos T2_DIS CCU_DIS SSC_DIS ADC_DIS r rw rw rw rw rw rw rw Field oe Description T2_DIS ii 2 Disable Request Active high Timer 2 is in normal operation default Request to disable the Timer 2 0 ee len O if read should be written with 0 PMCON2 Power Mode Control Register 1 Reset Value 00 7 6 9 4 3 2 1 0 UART1_ 0 E T21 DIS r rw rw Field Description T21_DIS Mii 21 Disable Request Active high Timer 21 is in normal operation default Request to di
233. SSC is automatically reset upon a baud rate error MS Master Select 0 Slave mode Operate on shift clock received via SCLK Master mode Generate shift clock and output it via SCLK Enable Bit 0 Transmission and reception disabled Access to control bits x h EN Reserved Returns 0 if read should be written with 0 x User s Manual 12 47 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces CON EN 1 Operating Mode CONL Control Register Low Reset Value 00 7 6 5 4 3 2 1 0 0 BC r rh Field Description BC 3 COR rh Bit Count Field 0001 1111 Shift counter is updated with every shifted bit 0 7 4 Reserved Returns 0 if read should be written with 0 CONH Control Register High Reset Value 00 7 6 5 4 3 2 1 0 rw rw r rh rwh rwh rwh rwh Field Bits Type Description TE rwh_ Transmit Error Flag 0 No error 1 Transfer starts with the slave s transmit buffer not being updated RE 1 rwh Receive Error Flag 0 No error 1 Reception completed before the receive buffer was read PE 2 rwh Phase Error Flag 0 No error 1 Received data changes around sampling clock edge User s Manual 12 48 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces Field Description BE m rate Error Flag No error More than factor 2 or 0 5 between slave s actual and expected baud rate BSY ee Flag an while a transfer is in progr
234. SSSOSOOSSSSSSSSOSOSOOCOSOS X C 8 8 6 8 8 8 Figure 7 2 Reset Circuitry Voltage Time RESET witt capacitor typ lt 50us Figure 7 3 Vopp Vooc and Vgeser during Power on Reset When the system starts up the PLL is disconnected from the oscillator and will run at its base frequency Once the EVR is stable provided the oscillator is running the PLL is connected and the continuous lock detection ensures that PLL starts functioning Following this as soon as the system clock is stable each 4 Kbyte Flash bank will enter the ready to read mode User s Manual 7 4 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management The status of pins MBC TMS and P0 0 is latched by the reset The latched values are used to select the boot options see Section 7 2 3 A correctly executed reset leaves the system in a defined state The program execution starts from location 0000 Figure 7 4 shows the power on reset sequence FLASH go to Reset Is EVR is stable PLLis locked Ready to Read _ leased and Start of program Mode Typ 300 us Max 200 us Typ 160 us Figure 7 4 Power on Reset Note When V ppp is not powered on the current over any GPIO pin must not source Vopp higher than 0 3 0 5 V 7 2 1 2 Hardware Reset An external hardware reset sequence is started when the reset input pin RESET is asserted low To ensure the recognition of the hardware rese
235. Set by hardware when external interrupt 0 event is detected Cleared by hardware when processor vectors to interrupt routine Can also be cleared by software IE1 3 rwh External Interrupt 1 Flag Set by hardware when external interrupt 1 event is detected Cleared by hardware when processor vectors to interrupt routine Can also be cleared by software TFO 5 rwh_ Timer 0 Overflow Flag Set by hardware on Timer 0 overflow Cleared by hardware when processor vectors to interrupt routine Can also be cleared by software User s Manual 5 29 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System Field Description TF1 Ca Timer 1 Overflow Flag Set by hardware on Timer 1 overflow Cleared by hardware when processor vectors to interrupt routine Can also be cleared by software SCON Serial Channel Control Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rwh rwh rwh Field Bits Type Description RI rwh Serial Interface Receiver Interrupt Flag Set by hardware if a serial data byte has been received Must be cleared by software TI 1 rwh Serial Interface Transmitter Interrupt Flag Set by hardware at the end of a serial data transmission Must be cleared by software NMISR NMI Status Register Reset Value 00 7 6 5 4 3 2 1 0 FNMI FNMI FNMI FNMIFLAS r rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description FNMIWDT rwh aaa Timer NMI Flag No Watchdog Timer NMI has occurred Watchdog Timer
236. TEP in register FDSTEP and can take any value from 0 to 255 In fractional divider mode the output clock pulse fyop is dependent on the result of the addition FDRES RESULT FDSTEP STEP if the addition leads to an overflow over FF 4 a pulse is generated for fmon The average output frequency in fractional divider mode is derived as follows 12 4 STEP fMop prv where STEP 0 255 256 User s Manual 12 14 V1 1 2007 05 Serial Interfaces V 1 0 infin eon XC886 888CLM Serial Interfaces Figure 12 4 shows the operation in fractional divider mode with a reload value of STEP 8D factor of 141 256 0 55 STEP 8D fron 055X Spy Jor RESULT _ 70 D eA 17 a4 31 BE 4 Fz 7F oc a i 2 2 2 2 2 el 2 i Figure 12 4 Fractional Divider Mode Timing Note In fractional divider mode fyop will have a maximum jitter of one fp clock period In general the fractional divider mode can be used to generate an average output clock frequency with higher accuracy than the normal divider mode Normal Divider Mode Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider mode while at the same time disables baud rate generation see Figure 12 3 Once the fractional divider is enabled FDEN 1 it functions as an 8 bit auto reload timer with no relation to baud rate generation and counts up from the reload value with each input clock pulse
237. The Structure of Byte Field The break is used to signal the beginning of a new frame It is the only field that does not comply with Figure 12 7 A break is always generated by the master task in the master mode and it must be at least 13 bits of dominant value including the start bit followed by a break delimiter as shown in Figure 12 8 The break delimiter will be at least one nominal bit time long A slave node will use a break detection threshold of 11 nominal bit times Break delimit Figure 12 8 The Break Field synch Byte is a specific pattern for determination of time base The byte field is with the data value 55 as shown in Figure 12 9 A slave task is always able to detect the Break Synch sequence even if it expects a byte field assuming the byte fields are separated from each other If this happens detection of the Break Synch sequence will abort the transfer in progress and processing of the new frame will commence Figure 12 9 The Synch Byte Field User s Manual 12 27 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces The slave task will receive and transmit data when an appropriate ID is sent by the master Slave waits for Synch Break Slave synchronizes on Synch Byte Slave snoops for ID According to ID slave determines whether to receive or transmit data or do nothing When transmitting the slave sends 2 4 or 8 data bytes followed by check byte ee 12 2
238. The register CC6xR can only be read by software and the modification of the value is done by a shadow register transfer from register CC6xSR Register T12PR contains the period value for timer T12 The period value is compared to the actual counter value of 112 and the resulting counter actions depend on the defined counting rules Figure 14 4 shows an example in the center aligned mode without dead time The bit CC6xST indicates the occurrence of a capture or compare event of the corresponding channel It can be set if it is 0 by the following events e asoftware set MCC6xS e acompare set event 112 counter value above the compare value if the T12 runs and if the T12 set event is enabled e upon a capture set event The bit CC6xST can be reset if it is 1 by the following events e a software reset MCC6xR e acompare reset event T12 counter value below the compare value if the T12 runs and if the T12 reset event is enabled including in single shot mode at the end of the T12 period e areset event in the hysteresis like control mode The bit CC6xPS represents passive state select bit The timer T12 s two output lines CC6x COUT6x can be selected to be in the passive state while CC6xST is O with CC6xPS 0 or while CC6xST is 1 with CC6xPS 1 The output level that is driven while the output is in the passive state is defined by the corresponding bit in bit field PSL Figure 14 5 shows the settings of CC6xPS COUT6xPS a
239. Transfer Interrupt 0 No interrupt will be generated if the set condition for bit STR in register IS occurs 1 An interrupt will be generated if the set condition for bit STR in register IS occurs The interrupt line that will be activated is selected by bit field INPCHE Reserved Returns 0 if read should be written with 0 INPL Capture Compare Interrupt Node Pointer Register Low Reset Value 40 7 6 3 4 3 2 1 0 INP INP INP INP CHE CC62 CC61 CC60 rw rw rw rw User s Manual 14 90 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field ahd Description INPCC60 Interrupt Node Pointer for Channel 0 Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit ICC6OR if enabled by bit ENCC60R or for bit ICC60F if enabled by bit ENCC60F 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected INPCC61 rw Interrupt Node Pointer for Channel 1 Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit ICC61R if enabled by bit ENCC61R or for bit CC61F if enabled by bit ENCC61F 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected INPCC62 rw Interrupt Node Pointer for Channel 2
240. Type Description SYNEN rw End of SYN Byte and SYN Byte Error Interrupts Enable 0 End of SYN Byte and SYN Byte Error Interrupts are not enabled 1 End of SYN Byte and SYN Byte Error Interrupts are enabled BGS 7 rw Baud rate Generator Select 0 Baud rate generator is selected 1 Timer 1 is selected Note Bits 3 to 7 are used only in UART module and not in UART1 module Therefore they should always be written with 0 in the FDCON register in UART1 module Setting them to 1 in the UART1 register has no effect Register FDSTEP contains the 8 bit STEP value for the fractional divider FDSTEP Fractional Divider Reload Register Reset Value 00 7 6 9 4 3 2 1 0 STEP rw Field Bits Type Description STEP 7 0 rw STEP Value In normal divider mode STEP contains the reload value for RESULT In fractional divider mode this bit field defines the 8 bit value that is added to the RESULT with each input clock cycle User s Manual 12 20 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces Register FDRES contains the 8 bit RESULT value for the fractional divider FDRES Fractional Divider Result Register Reset Value 00 7 6 5 4 3 2 1 0 RESULT rh Field Description RESULT COR O rh RESULT Value In normal divider mode RESULT acts as reload counter addition 1 In fractional divider mode this bit field contains the result of the addition RESULT STEP lf FDEN bit is changed from 0
241. U Status Register MDO MRO B2 mapped MDU Data Result Register 0 MD1 MR1 B3 mapped MDU Data Result Register 1 MD2 MR2 B4 mapped MDU Data Result Register 2 MD3 MR3 MDU Data Result Register 3 MD4 MR4 MDU Data Result Register 4 MD5 MR5 B7 mapped MDU Data Result Register 5 The MDx and MRx registers share the same address However since MRx registers should never be written to any write operation to one of these addresses will be interpreted as a write to an MDx register In the event of a read operation an additional bit MDUCON RSEL is needed to select which set of registers MDx or MRx the read operation must be directed to By default the MRx registers are read User s Manual 10 6 V1 1 2007 05 MDU V2 1 Cinfin eon XC886 888CLM Multiplication Division Unit 10 5 Register Description The 14 SFRs of the MDU consist of a control register MDUCON a status register MDUSTAT and 2 sets of data registers MDO to MD5 which contain the operands and MRO to MR5 which contain the results Depending on the type of operation the individual MDx and MRx registers assume Specific roles as summarized in Table 10 3 and Table 10 4 For example in a multiplication operation the low byte of the 16 bit multiplicator must be written to register MD4 and the high byte to MD5 Table 10 3 MDx Registers Register Roles of registers in operations Multiplication Division Division Shift MD3 a D endH OperandH MD4
242. UDEN 6 45 P4 PUDSEL 6 44 P5 ALTSELO 6 52 P5 ALTSEL1 6 52 P5 DATA 6 50 P5 DIR 6 50 P5 OD 6 51 P5 PUDEN 6 52 P5 PUDSEL 6 51 PASSWD 3 19 PCON 2 6 8 6 12 10 PISEL 12 45 PISELOH 14 38 PISELOL 14 37 PISEL2 14 39 PLL_CON 7 18 PMCONO 7 9 8 5 9 8 PMCON1 8 7 10 5 11 14 12 44 13 21 14 26 15 44 16 7 PMCON2 8 8 12 24 13 21 PORT PAGE 6 11 PRAR 16 36 PSLR 14 72 PSW 2 4 User s Manual 19 10 Px ALTSELn 6 10 Px_ DATA 6 6 Px_DIR 6 7 Px_OD 6 8 Px _PUDEN 6 9 Px PUDSEL 6 9 Q QORO 16 45 QBURO 16 47 QINRO 16 48 QMRO 16 41 QSRO 16 43 R RBL 12 51 RC2H 13 27 RC2L 13 27 RCRx x 0 3 16 57 RESRAXH x 0 3 16 56 RESRAXL x 0 3 16 55 RESRxH x 0 3 16 54 RESRxL x 0 3 16 53 S SBUF 12 8 SCON 5 30 12 8 SCU_PAGE 3 17 SP 2 3 SYSCONO 3 12 5 10 T T12DTCH 14 50 T12DTCL 14 50 T12H 14 46 T12L 14 46 T12MSELH 14 44 T12MSELL 14 42 T12PRH 14 47 T12PRL 14 47 T13H 14 52 T13L 14 51 T13PRH 14 53 V1 1 2007 05 Cinfineon TI3PRL 14 52 T2CON 13 25 T2H 13 28 T2L 13 28 T2MOD 13 24 TBL 12 51 TCON 5 24 5 29 13 11 TCTR2H 14 64 TCTR2L 14 62 TCTR4H 14 66 TCTR4L 14 65 TCTROH 14 60 TCTROL 14 59 THx x 0 1 18 10 TLx x 0 1 13 10 TMOD 13 12 TRPCTRH 14 71 TRPCTRL 14 69 V VFCR 16 57 W WDTCON 9 6 WDTH 9 7 WDTL 9 7 WDTREL 9 5 WDTWINB 9 8 X XADDRH 3 5 User s Manual 19 11 XC886 888CLM V1 1 2007 05
243. User s Manual 18 2 Bootstrap Loader V1 0 V1 1 2007 05 Cinfin eon XC886 888CLM Bootstrap Loader 18 1 1 Communication Protocol Once baud rate is established the host sends a block of information to the microcontroller to select the desired mode All blocks follow the specified block structure as shown in Section 18 1 1 1 for UART and Section 18 1 1 2 for LIN The microcontroller respond to host by sending specific response code as shown in Section 18 1 1 3 18 1 1 1 UART Transfer Block Structure A UART transfer block consists of three parts Block Type Data Area Checksum 1 byte XX bytes 1 byte e Block Type the type of block which determines how the data area is interpreted Implemented block types are 00 type HEADER Header Block has a fixed length of 8 bytes Special information is contained in the data area of the Header Block which is used to select different modes 01 type DATA Data Block is used in Mode 0 and Mode 2 to transfer a portion of program code The program code is in the data area of the Data Block 02 type END OF TRANSMISSION EOT EOT Block is the last block in data transmission in Mode 0 and Mode 2 The last program code to be transferred is in the data area of the EOT Block e Data Area Data size is 6 bytes for Header Block and cannot exceed 96 bytes for both Data and EOT Blocks e Checksum the XOR checksum of the block type and data area sent by the
244. User s Manual 3 16 V1 1 2007 05 Memory Organization V 1 2 Cinfin eon XC886 888CLM Memory Organization 3 5 4 System Control Registers The system control SFRs are used to control the overall system functionalities such as interrupts variable baud rate generation clock management bit protection scheme oscillator and PLL control The SFRs are located in the standard memory area RMAP 0 and are organized into 2 pages The SCU_PAGE register is located at BF It contains the page value and page control information SCU_PAGE Page Register for System Control Reset Value 00 7 6 5 4 3 2 1 0 i e e W W r rw Field Description PAGE COR 0 Page Bits When written the value indicates the new page When read the value indicates the currently active page STNR 5 4 Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP If OP 10p the contents of PAGE are saved in STx before being overwritten with the new value If OP 11p the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STO is selected 01 ST1 is selected 10 ST2 is selected 11 STS is selected User s Manual 3 17 V1 1 2007 05 Memory Organization V 1 2 Cinfineon XC886 888CLM Memory Organization Field Bits Type Description Operation User s Manual Memory Organization V 1 2 OX 10 11 Manual page mode The va
245. Users Manual V1 1 May 2007 XC886 888CLM 8 Bit Single Chip Microcontroller Microcontrollers N ee Never stop thinking Edition 2007 05 Published by Infineon Technologies AG 81726 Munchen Germany Infineon Technologies AG 2007 All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics Beschaffenheitsgarantie With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that de
246. V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 6 Walit for Read Mode The wait for read mode can be used for all request sources to allow the CPU to treat each conversion result independently without the risk of data loss Data loss can occur if the CPU does not read a conversion result in a result register before a new result overwrites the previous one In wait for read mode the conversion request generated by a request source for a specific channel will be disabled and conversion not possible if the targeted result register contains valid data indicated by its valid flag being set Conversion of the requested channel will not start unless the valid flag of the targeted result register is cleared data is invalid The wait for read mode for a result register can be enabled by setting bit WFR see Section 16 7 8 16 4 7 Result Generation The result generation part handles the storage of the conversion result data decimation limit checking and interrupt generation 16 4 7 1 Overview The result generation of the ADC module consists of several parts e A limit checking unit comparing the conversion result to two selected boundary values BOUNDO and BOUND1 A channel interrupt can be generated according to the limit check result e A data reduction filter accumulating the conversion results The accumulation is done by adding the new conversion result to the value stored in the selected resu
247. X is selected The rising edge at Pin T2EX is selected Register T2CON controls the operating modes of Timer 2 In addition it contains the status flags for interrupt generation T2CON Timer 2 Control Register Reset Value 00 0 C T2 CP RL2 rw rw Field mi Description CP RL2 ga ecnem Select Reload upon overflow or upon negative positive transition at pin T2EX when EXEN2 1 Capture Timer 2 data register contents on the negative positive transition at pin T2EX provided EXEN2 1 The negative or positive transition at pin T2EX is selected by bit EDGESEL C T2 Timer or Counter Select 0 Timer function selected 1 Count upon negative edge at pin T2 TR2 2 rwh Timer 2 Start Stop Control 0 Stop Timer 2 1 Start Timer 2 EXEN2 3 rw Timer 2 External Enable Control 0 External events are disabled 1 External events are enabled in capture reload mode User s Manual 13 25 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers Field Bits Type Description EXF2 rwh_ Timer 2 External Flag In capture reload mode this bit is set by hardware when a negative positive transition occurs at pin T2EX if bit EXEN2 1 This bit must be cleared by software Note When bit DCEN 1 in auto reload mode no interrupt request to the core is generated TF2 7 rwh_ Timer 2 Overflow Underflow Flag Set by a Timer 2 overflow underflow Must be cleared by software 0 5 4 r Reserved Returns 0 if read should be writ
248. a bit When the serial interfaces are enabled the master device can initiate the first data transfer by writing the transmit data into register TB This value is copied into the shift register assumed to be empty at this time and the selected first bit of the transmit data will be placed onto the TXD line on the next clock from the baud rate generator transmission starts only if CON EN 1 Depending on the selected clock phase a clock pulse will also be generated on the MS _CLK line At the same time with the opposite clock edge the master latches and shifts in the data detected at its input line RXD This exchanges the transmit data with the receive data Because the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line With the start of the transfer the busy flag CON BSY is set and the TIR will be activated to indicate that register TB may be reloaded again After the preprogrammed number of clock pulses via the data width selection the data transmitted by the master is contained in all the slaves shift registers while the master s shift register holds the data of the selected slave In the master and all slaves the contents of the shift register are copied into the receive buffer RB and the RIR is activated If no further transfer is to take place TB i
249. a is transferred to the data bus when addressed From user s point the angles 2 2 1 2 x are therefore represented by the range 2 2 1 11 3 2 Linear Function Emulated Look Up Table The emulated LUT for linear function is actually a shift register The emulated LUT has 1 integer bit MSB followed by 15 bit fractional part of the form 1Q16 In linear function where Z is a real number the internal Z data is of the form signed 4Q20 The externally read data has the last 4 bits of the fractional part truncated resulting in a sign bit followed by 4 bit integer part and finally 11 bit fractional part User s Manual 11 13 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfine on XC886 888CLM CORDIC Coprocessor 11 4 Low Power Mode lf the CORDIC Coprocessor functionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit CDC_DIS in register PMCON1 as described below Refer to Chapter 8 1 4 for details on peripheral clock management PMCON1 Power Mode Control Register 1 Reset Value 00 7 6 5 4 3 2 1 0 OBC DIS GANDIS MDULDIS T2 DIS GGULDIS 86 16 ADC_DIS r rw rw rw rw rw rw rw Field Description CDC_DIS ale Disable Request Active high CORDIC is in normal operation default Request to disable the CORDIC 0 ae ir io O if read should be written with 0 User s Manual 11 14 V1 1 2007 05 CORDIC Coprocess
250. a number of 8 bit registers Bits with the same meaning and function are assembled together in the same register The registers configure and use the port as general purpose I O or alternate function input output For port P2 not all the registers in Table 6 1 are implemented The availability and definition of registers specific to each port is defined in Section 6 3 to Section 6 8 This section provides only an overview of the different port registers Table 6 1 Port Registers Register Short Name Register Full Name Description Px DATA Port x Data Register Page 6 6 Px DIR Port x Direction Register Page 6 7 Px OD Port x Open Drain Control Register Page 6 8 Px PUDSEL Port x Pull Up Pull Down Select Register Page 6 8 Px PUDEN Port x Pull Up Pull Down Enable Register Page 6 8 Px ALTSELO Port x Alternate Select Register 0 Page 6 10 Px ALTSEL1 Port x Alternate Select Register 1 Page 6 10 User s Manual 6 5 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 1 1 1 Data Register lf a port pin is used as general purpose output output data is written into the data register Px_DATA If a port pin is used as general purpose input the latched value of the port pin can be read through register Px_ DATA Note A port pin that has been assigned as input will latch in the active internal pull up pull down setting if it is not driven by an external source This results in register Px_DATA being updated with the acti
251. able 13 3 SFR Address List Address Register CO T2CON Cin T2MOD C2 RC2L C3 RC2H C4 T2L CS T2H User s Manual 13 23 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 2 10 Register Description Register T2MOD is used to configure Timer 2 for the various modes of operation T2MOD Timer 2 Mode Register Reset Value 00 7 6 9 4 3 2 1 0 TRREGS TARMEN EDGESEL PREN TAPRE DOEN rw rw rw rw rw rw Field Description DCEN Up Down Counter Enable 0 Up Down Counter function is disabled 1 Up Down Counter function is enabled and controlled by pin T2EX Up 1 Down 0 T2PRE 3 1 rw Timer 2 Prescaler Bit Selects the input clock for Timer 2 which is derived from the peripheral clock 000 ft2 Spcik 001 fro fpcik 2 010 ft2 fpcik 4 011 fre fecik 8 100 fre SpciK 16 101 fre Spcik 32 110 fre fecik 64 111 frz fpcik 128 PREN 4 rw Prescaler Enable 0 Prescaler is disabled and the divider 12 takes effect 1 Prescaler is enabled see T2PRE bit and the divider 12 is bypassed EDGESEL 5 rw Edge Select in Capture Mode Reload Mode 0 The falling edge at pin T2EX is selected 1 The rising edge at pin T2EX is selected T2RHEN rw Timer 2 External Start Enable 0 Timer 2 External Start is disabled 1 Timer 2 External Start is enabled User s Manual 13 24 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers Field Description T2REGS a Select for Timer 2 External Start The falling edge at Pin T2E
252. according to their functional units The contents bits of the SFRs are summarized in Chapter 3 5 5 1 to Chapter 3 5 5 14 Note The addresses of the bitaddressable SFRs appear in bold typeface 3 5 5 1 CPU Registers The CPU SFRs can be accessed in both the standard and mapped memory areas RMAP 0 or 1 Table 3 3 CPU Register Overview Addr Register Name Bt 7 6 5 4 3 2 1 0 Oo Type iliac Type ow rw ow por Sow Gii i 94 TMOD Reset 00 Bit Field GATE T1S TiM GATE TOS TOM Timer Mode Register 1 0 fi Ay TLO Reset 00 Bit Field VA Timer 0 Register Low 81H 82H OO OO Serial Data Buffer Register 8Buy TL1 Reset 00y Bit Field VAL Timer 1 Register Low Type Type rwh THO Reset 00 Bit Field VAL Timer 0 Register High Type Type Timer 1 Register High Type Type rwh g SCON Reset 004 BitField SMO SM1 SM2 REN TB8 RB8 m R ial Ch Regist 9914 SBUF Reset 00y Bit Field VAL Type A2 EO Reset 00y Bit Field TRAP_ DPSE Extended Operation Register EN LO w User s Manual 3 21 V1 1 2007 05 Memory Organization V 1 2 Cinfin eon XC886 888CLM Memory Organization Table 3 3 CPU Register Overview cont d Register Name Bit 7 IENO Reset 00 Bit Field ee ET2 ETI Interrupt Enable Register 0 ot pror pet OOH a o oee os er f ee e e a E a a SS a T fre orm pm fafa fof ef ACC Reset 00H Accumulator Register i me om om wm
253. action Bit VFCx is reset 0 7 4 seared Returns 0 if read should be written with O The result control registers RCRx contain bits that control the behavior of the result registers and monitor their status RCRx x 0 3 Result Control Register x CA X 1 Reset Value 00 7 6 5 4 3 2 1 0 elmeje e a rw rw r rw r rw User s Manual 16 57 V1 1 2007 05 ADC V 1 0 Cinfineon Field DRCTR IEN WFR VFCTR User s Manual ADC V 1 0 a XC886 888CLM Analog to Digital Converter Description Data Reduction Control This bit defines how many conversion results are accumulated for data reduction It defines the reload value for bit DRC Os The data reduction filter is disabled The reload value for DRC is 0 so the accumulation is done over 1 conversion 1 The data reduction filter is enabled The reload value for DRC is 1 so the accumulation is done over 2 conversions Interrupt Enable This bit enables the event interrupt related to the result register x An event interrupt can be generated when DRC is set to 0 after decrementing or by reload Os The event interrupt is disabled 1 The event interrupt is enabled Wait for Read Mode This bit enables the wait for read mode for result register x Os The wait for read mode is disabled 1 The wait for read mode is enabled Valid Flag Control This bit enables the reset of valid flag by read access to high byte for result register x 0
254. ad timer 11 Timer 0 is split into two halves TLO is an 8 bit timer controlled by the standard Timer 0 control bits and THO is the other 8 bit timer controlled by the standard Timer 1 control bits TH1 and TL1 of Timer 1 are held Timer 1 is stopped TOS r Timer 0 Selector 0 Input is from internal system clock 1 Input is from TO pin GATEO r Timer 0 Gate Flag 0 Timer O will only run if TCON TRO 1 software control 1 Timer O will only run if NINTO pin 1 hardware control and TCON TRO is set User s Manual 13 12 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers Field Description T1S s 1 Selector Input is from internal system clock Input is from T1 pin GATE1 Gate Flag Timer 1 will only run if TCON TR1 1 software control Timer 1 will only run if NINT1 pin 1 hardware control and TCON TR1 is set IENO Interrupt Enable Register Reset Value 00 7 6 5 4 3 2 1 0 rw r rw rw rw rw rw rw Field Bits Type Description ETO 1 rw Timer 0 Overflow Interrupt Enable 0 Timer O interrupt is disabled 1 Timer 0 interrupt is enabled ET1 3 rw Timer 1 Overflow Interrupt Enable 0 Timer 1 interrupt is disabled 1 Timer 1 interrupt is enabled Note When Timer 0 operates in Mode 3 this interrupt indicates an overflow in the Timer 0 register THO User s Manual 13 13 V1 1 2007 05 Timers V 1 0 Cinfine on XC886 888CLM Timers 13 2 Timer 2 and Timer 21 Timer 2 and Timer 21 are 16 bit general pu
255. ader block is the only transfer block to be sent by the host no further serial communication is necessary The microcontroller will exit the LIN BSL and jump to the XRAM address at OFO000 Mode 1 and Mode 9 and or jump to Flash address at 0000 Mode 3 18 1 3 5 The Activation of Mode 4 Mode 4 is used to erase sector s of P Flash bank s or D Flash bank s or mass erase of all sectors in P Flash and D Flash banks The selection of the type of erase is controlled through the Option byte in the header block When Option 00 this mode is used to erase the P Flash sector s The header block has the following structure The Header Block Mode Data 5 bytes PFlash PFlash PFlash Checksum 1 byte User s Manual 18 21 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader Mode data description can be referred at Section 18 1 2 5 When Option 40 this mode is used to erase the D Flash sector s The header block has the following structure The Header Block Mode Data 5 bytes 04 DFlash DFlash DFlash DFlash Checksum Mode 4 _Bank0 _Bank0 _Bank1 _Bank1 1 byte _L H L H Mode data description can be referred at Section 18 1 2 5 When Option CO this mode is used to do a mass erase of all the sectors in the P Flash and the D Flash The header block has the following structure The Header Block bi Mode Data 5 bytes Crock ecksum Mode 4 Not Used Opti
256. al 14 9 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 CC6xSR registers In order to work in capture mode the capture pins must be configured as inputs There are several ways to store the captured values in the registers For example in double register capture mode the timer value is stored in the channel shadow register CC6xSR The value previously stored in this register is simultaneously copied to the channel register CC6xR The software can then check the newly captured value while still preserving the possibility of reading the value captured earlier Note In capture mode a shadow transfer can be requested according to the shadow transfer rules except for the capture compare registers that are left unchanged 14 1 1 8 Single Shot Mode The single shot mode of timer T12 is selected when bit T12SSC is set to 1 In single shot mode the timer T12 stops automatically at the end of its counting period Figure 14 7 shows the functionality at the end of the timer period in edge aligned and center aligned modes If the end of period event is detected while bit T12SSC is set the bit T12R and all CC6xST bits are reset edge aligned mode center aligned mode _ period match T12P l while counting up one match while if T12SSC 1 counting down T12 if T12SSC 1 T12 T12R T12R a Lo CC6xST CCU6_T12_singleshot Figure 14 7 End of Single Shot Mode of T12 14 1 1 9 Hysteresis Like Contro
257. allow for updates without undesired pulses on the output lines The bits are updated with the 112 shadow transfer A read action targets the actually used values whereas a write action targets the shadow bits Note Bit field PSL63 has a shadow register to allow for updates without undesired pulses on the output line The bit is updated with the 113 shadow transfer A read action targets the actually used values whereas a write action targets the shadow bits 14 3 6 Multi Channel Modulation Control Registers Register MCMOUTS contains bits controlling the output states for multi channel mode Furthermore the appropriate signals for the block commutation by Hall sensors can be selected This register is a shadow register that can be written for register MCMOUT which indicates the currently active signals MCMOUTSL Multi Channel Mode Output Shadow Register Low Reset Value 00 7 6 5 4 3 2 1 0 STR aw cc W r rw Field Description MCMPS ECE 0 Multi Channel PWM Pattern Shadow Bit field MCMPS is the shadow bit field for bit field MCMP The multi channel shadow transfer is triggered according to the transfer conditions defined by register MCMCTR User s Manual 14 73 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Bits Type Description STRMCM 7 W Shadow Transfer Request for MCMPS Setting this bit during a write action leads to an immediate update of bit field MCMP by the value written to bit fie
258. ance the P Flash banks are configured for parallel read to allow two bytes of linear code to be read in 4 x CCLK cycles compared to 6 x CCLK cycles if serial read is performed This is achieved by reading two bytes in parallel from a P Flash bank pair within the 3 x CCLK cycles access time and storing them in a cache Subsequent read from the cache by the CPU does not require a wait state and can be completed within 1 x CCLK cycle The result is the average instruction fetch time from the P Flash banks is reduced and thus the MIPS Mega Instruction Per Second of the system Is increased However if the parallel read feature is not desired due to certain timing constraints it can be disabled by calling the parallel read disable subroutine see Section 4 8 5 User s Manual 4 5 V1 1 2007 05 Flash Memory V 1 0 Infineon 4 4 Wordline Address XC886 888CLM Flash Memory The wordline WL addresses of the P Flash and D Flash banks used as program code and as data are given in Figure 4 4 Figure 4 5 and Figure 4 6 respectively Figure 4 4 User s Manual Flash Memory V 1 0 Sector 2 Sector 1 128 byte x2 WL 120 123 WL124 127 P Flash Pair 2 Sector 0 WLO 119 3 75 KByte x2 x2 Sector 2 128 byte x2 128 byte Sector 1 WL 120 123 WL124 127 P Flash Pair 1
259. and result register control IEN An interrupt node pointer EVINP for each event allows the selection of the targeted service output line A request source event is generated when the requested channel conversion is completed e Event 0 Request source event of sequential request source 0 arbitration slot 0 e Event 1 Request source event of parallel request source 1 arbitration slot 1 A result event is generated according to the data reduction control see Section 16 4 7 3 e Event 4 Result register event of result register 0 e Event 5 Result register event of result register 1 e Event 6 Result register event of result register 2 e Event 7 Result register event of result register 3 event 7 event 6 event 5 event 4 interrupt trigger O event 1 AA event O interrupt trigger O Figure 16 13 Event Interrupt Structure User s Manual 16 24 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 8 2 Channel Interrupts The channel interrupts occur when a conversion is completed and the selected limit checking condition is met As a result only one channel interrupt can be activated at a time An interrupt can be triggered according to the limit checking result by comparing the conversion result with two selectable boundaries for each channel request bounda sources conversion finished arbiter channel interrupt channel rem channel number
260. anual 14 12 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 e Bit T13R is set reset by software by setting bit T13RS or T13RR e In single shot mode if bit T13SSC 1 the bit T13R is reset by hardware when 113 reaches its period value e Bit fields T13TEC and T13TED select the trigger event that will set bit T13R for synchronization of different T12 compare events The T13 counter register can be reset to zero by setting bit T13RES Setting of T13RES has no impact on bit T13R 14 1 2 2 Compare Mode Register CC63R is the actual compare register for T13 The value stored in CC63R is compared to the counter value of 113 The register CC63R can only be read by software and the modification of the value is done by a shadow register transfer from register CC63SR The corresponding shadow register CC63SR can be read and written by software Register T13PR contains the period value for timer T13 The period value is compared to the actual counter value of T13 and the resulting counter actions depend on the defined counting rules The bit CC63ST indicates the occurrence of a compare event of the corresponding channel It can be set if it is 0 by the following events e a software set MCC63S e a compare set event T13 counter value above the compare value if the T13 runs and if the T13 set event is enabled The bit CC63ST can be reset if it is 1 by the following events e asoftware reset MCC63R e aco
261. any data length from 2 bit characters up to 8 bit characters Starting with the LSB CON HB 0 allows communication with SSC devices in synchronous mode or with serial interfaces such as the one in 8051 Starting with the MSB CON HB 1 allows operation compatible with the SPI interface Regardless of the data width selected and whether the MSB or the LSB is transmitted first the transfer data is always right aligned in registers TB and RB with the LSB of the transfer data in bit O of these registers The data bits are rearranged for transfer by the internal shift register logic The unselected bits of TB are ignored the unselected bits of RB will not be valid and should be ignored by the receiver service routine The Clock Control allows the transmit and receive behavior of the SSC to be adapted to a variety of serial interfaces A specific shift clock edge rising or falling is used to shitt out transmit data while the other shift clock edge is used to latch in receive data Bit CON PH selects the leading edge or the trailing edge for each function Bit CON PO selects the level of the shift clock line in the idle state Thus for an idle high clock the leading edge is a falling one a 1 to O transition see Figure 12 12 PO PH Shift Clock MS_CLK SS_CLK MTSR MRST First Transmit Data st f l Latch Data Shift Data Figure 12 12 Serial Clock Phase and Polarity Options When initializing the d
262. ap Flag 0 No action 1 Bit TRPF in register IS will be reset not taken into account while input CTRAP 0 and TRPPEN 1 RCHE 4 W Reset Correct Hall Event Flag 0 No action 1 Bit CHE in register IS will be reset RWHE 5 Ww Reset Wrong Hall Event Flag 0 No action 1 Bit WHE in register IS will be reset RIDLE W Reset IDLE Flag 0 No action 1 Bit IDLE in register IS will be reset RSTR 7 Ww Reset STR Flag 0 No action 1 Bit STR in register IS will be reset 0 3 r Reserved Returns 0 if read should be written with 0 User s Manual 14 86 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 IENL Capture Compare Interrupt Enable Register Low Reset Value 00 7 6 5 4 3 2 1 0 Field ae Description ENCC60R Capture Compare Match Rising Edge Interrupt Enable for Channel 0 0 No interrupt will be generated if the set condition for bit ICC6OR in register IS occurs 1 An interrupt will be generated if the set condition for bit ICC60R in register IS occurs The interrupt line that will be activated is selected by bit field INPCC60 ENCC60F 1 rw Capture Compare Match Falling Edge Interrupt Enable for Channel 0 0 No interrupt will be generated if the set condition for bit ICC60F in register IS occurs 1 An interrupt will be generated if the set condition for bit ICC60F in register IS occurs The interrupt line that will be activated is selected by bit field INPCC6O ENCC61R 2 rw Capture Compare
263. ared by hardware after each instruction to indicate an odd even number of one bits in the accumulator i e even parity F1 1 wo General Purpose Flag OV 2 rwh_ Overflow Flag Used by arithmetic instructions RS1 4 3 Register Bank Select RSO These bits are used to select one of the four register banks 00 Bank 0 selected data address 00 07 01 Bank 1 selected data address 08 OF 10 Bank 2 selected data address 10 17 11 Bank 3 selected data address 18 1F FO tw General Purpose Flag AC Auxiliary Carry Flag Used by instructions that execute BCD operations CY 7 rwh_ Carry Flag Used by arithmetic instructions User s Manual 2 4 V1 1 2007 05 Processor Architecture V 1 0 Cinfin eon XC886 888CLM Processor Architecture 2 2 6 Extended Operation EO The instruction set includes an additional instruction MOVC DPTR A which allows program memory to be written This instruction may be used to download code into the program memory when the CPU is initialized and subsequently also to provide software updates The instruction copies the contents of the accumulator to the code memory at the location pointed to by the current data pointer and then increments the data pointer The instruction uses the opcode A5 which is the same as the software break instruction TRAP see Table 2 1 Register bit EO TRAP_EN is used to select the instruction executed by the opcode A5H When TRAP_EN is 0 default the A5
264. art describes the Debug Actions that are taken when a debug event is generated e Debug events Hardware Breakpoints Software Breakpoints External Breaks e Debug event actions Call the Monitor Program Activate the MBC pin The XC886 888 debug operation is based on close interaction between the OCDS hardware and a specialized software called the Monitor program 17 3 1 Debug Events The OCDS system recognizes a number of different debug events which are also called breakpoints or simply breaks Depending on how the events are processed in time they can be classified into three types of breaks e Break Before Make The break happens just before the break instruction i e the instruction causing the break is executed Therefore the break instruction itself will be the next instruction from the user program flow but executed only after the relevant debug action has been taken e Break After Make The break happens immediately after the instruction causing it has been executed Therefore the break instruction itself has already been executed when the relevant debug action is taken e Break Now The events of this type are asynchronous to the code execution inside the XC886 888 and there is no instruction causing the debug event in this case The debug action is performed by OCDS as soon as possible once the debug event is raised User s Manual 17 3 V1 1 2007 05 OCDS V 1 0 Cinfin eon XC886 888CL
265. as one word transfer This feature can be used to interface with devices that can operate with or require more than 8 data bits per transfer It is just a matter of software specifying the total data frame length This option can also be used to interface with byte wide and word wide devices Note This feature allows only multiples of the selected basic data width because it would require disabling enabling of the SSC to reprogram the basic data width on the fly User s Manual 12 37 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces 12 3 1 5 Port Control The SSC uses three lines to communicate with the external world as shown in Figure 12 15 Pin SCLK serves as the clock line while pins MRST and MTSR serve as the serial data input output lines Interrupt System PO 3 SCK 1 _ PO 4 MTSR_1 SSC ne on a gt Posmrst_t Slave Kernel Control e P1 2 SCK_0 gt P1 3 MTSR_0 gt P1 4 MRST_0 Master Slave Figure 12 15 SSC Module I O Interface Operation of the SSC I O lines depends on the selected operating mode master or Slave The direction of the port lines depends on the operating mode The SSC will automatically use the correct kernel output or kernel input line of the ports when Switching modes Since the SSC I O lines are connected with the bidirectional lines of the general purpose I O ports software I O control is used to control the port pins assigned to these li
266. ated by the bits ITO and IT1 in the TCON register In addition to the corresponding interrupt node enable each external interrupt 2 to 6 may be disabled individually lf the external interrupt is positive negative edge triggered the external source must hold the request pin low high for at least one CCLK cycle and then hold it high low for at least one CCLK cycle to ensure that the transition is recognized If edge detection is bypassed for external interrupt 0 and external interrupt 1 the external source must hold the request pin high or low for at least two CCLK cycles External interrupts 0 1 2 and 6 support alternative input pin selected via EXINTXxIS bits in SFRs MODPISEL and MODPISEL1 When switching inputs the active edge level trigger select and the level on the associated pins should be considered to prevent unintentional interrupt generation EXICONO External Interrupt Control Register 0 Reset Value FO 7 6 5 4 3 2 1 0 rw rw rw rw Field Description EXINTO CON 0 External Interrupt 0 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edges 11 Bypass the edge detection The interrupt request signal directly feeds to the core EXINT1 3 2 External Interrupt 1 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edges 11 Bypass the edge detection The interrupt request signal directly fee
267. ated interface for direct interfacing with the program memory without using any port pin This means that a code fetch can occur on every rising edge of the clock Hence there is no concept of internal or external program memory as all code is fetched from a single program memory interface 3 3 Data Memory The data memory space consists of an internal and external memory space The labels internal and external for data memory are used to distinguish between the register memory and the 64 Kbyte data space accessed using MOVX instructions They do not imply that the external data memory is located off chip 3 3 1 Internal Data Memory The internal data memory is divided into two physically separate and distinct blocks the 256 byte RAM and the 128 byte Special Function Register SFR area While the upper 128 bytes of RAM and the SFR area share the same address locations they are accessed through different addressing modes The lower 128 bytes of RAM can be accessed through either direct or register indirect addressing while the upper 128 bytes of RAM can be accessed through register indirect addressing only The SFRs are accessible through direct addressing The 16 bytes of RAM that occupy addresses from 20 to 2F are bitaddressable RAM occupying direct addresses from 30 to 7F can be used as scratch pad registers or used for the stack User s Manual 3 4 V1 1 2007 05 Memory Organization V 1 2 Cinfine
268. ay be independently switched off to reduce power consumption for the different power saving modes At the center of the XC886 888 clock system is the Clock Generation Unit CGU which generates a master clock frequency using the Phase Locked Loop PLL and oscillator units In ohase synchronized clock signals are derived from the master clock and distributed throughout the system A programmable clock divider is available for scaling the master clock into lower frequencies for power savings 7 1 Power Supply System with Embedded Voltage Regulator The XC886 888 microcontroller requires two different levels of power supply e 3 3 Vor 5 0 V for the Embedded Voltage Regulator EVR and Ports e 2 5 V for the core memory on chip oscillator and peripherals Figure 7 1 shows the XC886 888 power supply system A power supply of 3 3 V or 5 0 V must be provided from the external power supply pin The 2 5 V power supply for the logic is generated by the EVR The EVR helps reduce the power consumption of the whole chip and the complexity of the application board design CPU amp On chip Peripheral Memory OSC logic ADC V p00 29 a FLASH a p PLL a p XTAL1 amp a GPIO Ports EVR XTAL2 PO P5 Vo 3 3V 5 0V V Figure 7 1 XC886 888 Power Supply System User s Manual 7 1 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management EVR Features e Input voltage Vppp 3 3 V
269. ble External Trigger This bit enables the external trigger possibility If enabled the load event takes place if a rising edge is detected at the external trigger inout REQTR Os The external trigger is disabled 1 The external trigger is disabled ENSI 3 rw Enable Source Interrupt This bit enables the request source interrupt This interrupt can be generated when the last pending conversion is completed for this source while PND 0 Os The source interrupt is disabled 1 The source interrupt is enabled SCAN 4 rw Autoscan Enable This bit enables the autoscan functionality If enabled the load event is automatically generated when a conversion requested by this source is completed and PND 0 Os The autoscan functionality is disabled 1 The autoscan functionality is enabled User s Manual 16 51 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Field Description CLRPND Clear Pending Bits 0s No action 1 The bits in register CRPR1 are reset LDEV Generate Load Event On No action 1 The load event is generated Rsv 7 r Reserved Returns 1 if read should be written with O Note This bit is initialized to 0 immediately after reset but is updated by hardware to 1 and remains as 1 shortly after 0 1 r Reserved Returns 0 if read should be written with 0 User s Manual 16 52 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 7 8 Result
270. by software bit STRHP and bit fields SWSEL SWSYN 14 1 6 2 Brushless DC Control For Brushless DC motors there is a special mode MSEL6x 1000 which is triggered by a change of the Hall inputs CCPOSx In this case T12 s channel 0 acts in capture function channel 1 and 2 act in compare function without output modulation and the multi channel block is used to trigger the output switching together with a possible modulation of T13 After the detection of a valid Hall edge the T12 count value is captured to channel 0 representing the actual motor speed and the T12 is reset When the timer reaches the compare value in channel 1 the next multi channel state is switched by triggering the shadow transfer of bit field MCMP This trigger event can be combined with several conditions which are necessary to implement noise filtering correct Hall event and to synchronize the next multi channel state to the modulation sources avoiding spikes on the output lines This compare function of channel 1 can be used as a phase delay for the position input to the output switching which is necessary if a sensorless back EMF technique is used instead of Hall sensors The compare value in channel 2 can be used as a time out trigger interrupt indicating that the motor s destination speed Is far below the desired value which can be caused by an abnormal load change In this mode the modulation of T12 must be disabled T12MODENx 0 capture ev
271. cal dead time generation in center aligned and in edge aligned PWM mode A duty cycle of 50 leads to CC6x COUT6x switched on for 0 5 period dead time Note The dead time counters are not reset by bit T12RES but by bit DTRES 14 3 3 Timer 13 Related Registers The generation of the patterns for a single channel PWM is based on timer T13 The registers related to timer T13 can be concurrently updated with well defined conditions in order to ensure consistency of the PWM signal T13 can be synchronized to several timer 112 events Timer T13 supports only compare mode on its compare channel CC63 Register T13 represents the counting value of timer T13 It can only be written while the timer T13 is stopped Write actions while T13 is running are not taken into account Register T13 can always be read by software Timer T13 supports only edge aligned mode counting up T13L Timer T13 Counter Register Low Reset Value 00 7 6 5 4 3 2 1 0 T13CVL rwh User s Manual 14 51 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Bits Type Description T13CVL 7 0 rwh Timer T13 Counter Value Low Byte This register represents the lower 8 bit counter value of timer T13 T13H Timer T13 Counter Register High Reset Value 00 7 6 5 4 3 2 1 0 rwh Field Description T13CVH me y Timer T13 Counter Value High Byte This register represents the upper 8 bit counter value of timer T13 Note While
272. ce dedicated exclusively for testing and debugging activities and is not normally used in an application The dedicated MBC pin is used for external configuration and debugging control JTAG Module Memory call Control Debu Unit g 5 Interface JTAG User Boot Program Monitor Memory ROM Monitor Mode Control Monitor amp __ MBC Bootstrap loader Control line Monitor RAM System Control Unit Reset Clock Reset Clock Debug PROG PROG Memory parts of Interface amp IRAM Data Control OCDS Addresses XC800 Core OCDS_XC886C Block_Diagram UM v0 2 Figure 17 1 XC886 888 OCDS Block Diagram 1 The pins of the JTAG port can be assigned to either Port 0 primary or Ports 1 and 2 Secondary set one or Port 5 secondary set two User must set the JTAG pins TCK and TDI as input during connection with the OCDS system User s Manual 17 2 V1 1 2007 05 OCDS V 1 0 Cinfine on XC886 888CLM On Chip Debug Support Note All the debug functionality described here can normally be used only after XC886 888 has been started in OCDS mode For more information on boot configuration options see Chapter 7 2 3 Attention As long as the OCDS is actively used the application software should not change the TRAP_EN bit within Extended Operation EO register 17 3 Debugging The on chip debug system functionality can be described in two parts The first part covers the generation of Debug Events and the second p
273. ce step information Two methods are provided to read a device variant s chip identification number e In application subroutine see Chapter 4 8 6 e Bootstrap loader BSL mode A see Chapter 18 1 2 7 or Chapter 18 1 3 7 User s Manual 1 17 V1 1 2007 05 Introduction V 1 1 Cinfin eon XC886 888CLM 1 5 Introduction Text Conventions This document uses the following text conventions for named components of the XC886 888 Functional units of the XC886 888 are shown in upper case For example The SSC can be used to communicate with shift registers Pins using negative logic are indicated by an overbar For example A reset input pin RESET is provided for the hardware reset Bit fields and bits in registers are generally referenced as Register name Bit field or Register name Bit Most of the register names contain a module name prefix separated by an underscore character _ from the actual register name In the example of SSC CON SSC is the module name prefix and CON is the actual register name Variables that are used to represent sets of processing units or registers appear in mixed case type For example the register name CC6xR refers to multiple CC6xR registers with the variable x x 0 1 2 The bounds of the variables are always specified where the register expression is first used e g x 0 2 and Is repeated as needed The defaul
274. cessive 2 During bus off recovery this code is set each time a sequence of 11 recessive bits has been monitored The CPU may use this code as indication that the bus is not continuously disturbed 110 CRC Error The CRC checksum of the received message was incorrect 111 CPU write to LEC Whenever the CPU writes the value 111 to LEC it takes the value 111 Whenever the CPU writes another value to LEC the written LEC value Is ignored User s Manual 15 65 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller The four interrupt pointers in the NIPR register select one out of the eight interrupt outputs individually for each type of CAN node interrupt See also Page 15 11 for more CAN node interrupt details NIPRx x 0 1 Node x Interrupt Pointer Register Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BEGGS RSE SEESEEen r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFCINP TRINP LECINP ALINP rw rw rw rw Field Bits Type Description ALINP 3 0 rw Alert Interrupt Node Pointer ALINP selects the interrupt output line CANSRCm m 0 7 for an alert interrupt of CAN Node x 0000 Interrupt output line CANSRCO is selected 0001 Interrupt output line CANSRC1 is selected 0111 Interrupt output line CANSRC7 is selected 10005 1111 Reserved LECINP 7 4 Last Error Code Interrupt Node Pointer LECINP selects the interrupt output line CANSRCm m
275. chronization Jump Width SJW 1 time quanta are allowed for re synchronization SJW 7 6 eC eC h h 00 TSEG1 W Time Segment Before Sample Point TSEG1 1 time quanta is the user defined nominal time between the end of the synchronization segment and the sample point It includes the propagation segment which takes into account signal propagation delays The time segment may be lengthened due to re synchronization Valid values for TSEG1 are 2 to 15 rw Time Segment After Sample Point TSEG2 1 time quanta is the user defined nominal time between the sample point and the start of the next synchronization segment It may be shortened due to re synchronization Valid values for TSEG2 are 1 to 7 TSEG2 14 12 User s Manual 15 69 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Field Bits Type Description DIV8 15 rw Divide Prescaler Clock by 8 0 A time quantum lasts BRP 1 clock cycles 1 A time quantum lasts 8 x BRP 1 clock cycles 0 31 16 r Reserved Read as 0 should be written with O User s Manual 15 70 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller The Node Error Counter Register NECNTx contains the CAN receive and transmit error counter as well as some additional bits to ease error analysis NECNTx can be written only if bit NCRx CCE is set NECNTx x 0 1 Node x
276. cial Function Register area e 24 32 Kbytes of Flash program memory Flash devices or 24 32 Kbytes of ROM program memory with additional 4 Kbytes of Flash ROM devices Figure 3 1 illustrates the memory address spaces of the 32 Kbyte Flash devices For the 24 Kbyte Flash devices the shaded banks are not available 1 In 24 Kbyte Flash devices the upper 2 Kbyte of Banks 4 and 5 are not available XRAM XRAM 1 5 Kbytes 1 5 Kbytes Boot ROM 12 Kbytes D Flash Bank 1 4 Kbytes D Flash Bank 0 4 Kbytes D Flash Bank 0 4 Kbytes D Flash Bank 1 4 Kbytes Indirect Direct P Flash Banks 4 and 5 Address Address 2 x 4 Kbytes Special Function P Flash Banks 2 and 3 MEEN NAM Registers 2 x 4 Kbytes P Flash Banks 0 and 1 2 x 4 Kbytes Internal RAM v v v Program Space External Data Space Internal Data Space Figure 3 1 Memory Map of XC886 888 Flash Device User s Manual 3 1 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization Figure 3 2 illustrates the memory address spaces of the 32 Kbyte ROM devices For the 24 Kbyte ROM devices the shaded address regions are not available For both 24 Kbyte and 32 Kbyte ROM devices the last four bytes of the ROM from 7FFC to 7FFF are reserved for the ROM signature and cannot be used to store user code or data Therefore even though the ROM
277. combined with rw or r bits to rwh and rh bits respectively 1 7 Acronyms Table 1 5 lists the acronyms used in this document Table 1 5 Acronyms Acronym Description ADC Analog to Digital Converter ALU Arithmetic Logic Unit BSL BootStrap Loader User s Manual 1 19 V1 1 2007 05 Introduction V 1 1 Cinfineon Table 1 5 Acronym CAN CCU6 CGU CORDIC CPU ECC EVR FDR GPIO IAP I O ISP JTAG LIN MDU NMI OCDS PC POR PLL PSW PWM RAM ROM SFR SPI SSC UART WDT User s Manual Introduction V 1 1 XC886 888CLM Introduction Acronyms cont d Description Controller Area Network Capture Compare Unit 6 Clock Generation Unit Cordinate Rotation Digital Computer Central Processing Unit Error Correction Code Embedded Voltage Regulator Fractional Divider General Purpose O In Application Programming Input Output In System Programming Joint Test Action Group Local Interconnect Network Multiplication Division Unit Non Maskable Interrupt On Chip Debug Support Program Counter Power On Reset Phase Locked Loop Program Status Word Pulse Width Modulation Random Access Memory Read Only Memory Special Function Register Serial Peripheral Interface Synchronous Serial Channel Universal Asynchronous Receiver Transmitter Watchdog Timer 1 20 V1 1 2007 05 Cinfin eon XC886 888CLM Processor Architecture 2 Processor Architecture The XC886 888 is based on a high performance
278. crement BCD decimal add adjust and compare Logic operations include AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations such as set clear complement jump if set jump if not set jump if set and clear and move to from carry The ALU can perform the bit operations of logical AND or logical OR between any addressable bit or its complement and the carry flag and place the new result in the carry flag User s Manual 2 2 V1 1 2007 05 Processor Architecture V 1 0 Cinfin eon XC886 888CLM Processor Architecture The program control section controls the sequence in which the instructions stored in program memory are executed The 16 bit Program Counter PC holds the address of the next instruction to be executed The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence 2 2 CPU Register Description The CPU registers occupy direct Internal Data Memory space locations in the range 80 to FFy 2 2 1 Stack Pointer SP The SP register contains the Stack Pointer SP The SP is used to load the Program Counter PC into Internal Data Memory during LCALL and ACALL instructions and to retrieve the PC from memory during RET and RETI instructions Data may also be saved on or retrieved from the stack using PUSH and POP instructions respectively Instructions t
279. cted Signal s From to Module P5 DATA PO EXINT1_1 External Interrupt 1 P5_DATA PO User s Manual 6 46 V1 1 2007 05 Parallel Ports V 1 0 Infineon XC886 888CLM i Parallel Ports Table 6 14 Port 5 Input Output Functions cont d Port Pin Input Output P5 1 Input Connected Signal s From to Module GP P5_DATA P1 gt gt gt Tm e 4 4 44 P EXINT2 1 External Interrupt 2 Output GPO P5 DATA P1 gt gt gt Tm P e H OINI Input GPI P5 DATA P2 RXD 2 UART Output GPO P5 DATA P2 gt gt gt Tm e 4 4 44 P sa OD Input GPI P5 DATA P3 gt gt gt Tm i 0 N Output GPO P5 DATA P3 z TXD_2 UART O1 NO wil wil Tm F Tm e 4 4 44 H P 0 N User s Manual 6 47 V1 1 2007 05 Parallel Ports V 1 0 Infineon XC886 888CLM i Parallel Ports Table 6 14 Port 5 Input Output Functions cont d Port Pin Input Output P5 4 Input Connected Signal s From to Module GP P5 DATA P4 gt gt gt Tm e 4 4 44 P Output GPO P5 DATA P4 RXDO 2 UART gt gt gt Tm P e H OINI Input GPI P5 DATA P5 a Output GPO P5 DATA P5 TDO 2 JTAG TXD1_2 UART1 gt gt gt Tm e 4 4 44 P ih op Input GPI P5 DATA P6 TCK 2 JTAG O1 O1 wil wil Tm Tm e i H 0 N 0 N BE Output GPO P5 DATA P6 z RXDO1_2 UART 1
280. cted wordline WL of the P Flash and D Flash bank respectively Before calling this subroutine the Flash NMI can be enabled via bit NMIFLASH in register NMICON so that the Flash NMI service routine is entered once programming of the selected WL is completed Before calling this subroutine the user must ensure that the 64 byte or 32 byte WL contents are stored incrementally in the IRAM starting from the address specified in RO of current general register bank In addition the input DPTR must contain a valid Flash WL address WL addresses of a protected Flash bank are considered invalid Otherwise PSW CY bit will be set and no programming will occur If valid inputs are available before calling the subroutine the microcontroller will continue with the initialization sequence includes transferring the 64 byte or 32 byte IRAM data to the selected Flash bank write buffers exit the subroutine and then return to the user program code see Table 4 1 User program code will continue execution from where it last stopped until the Flash NMI event is generated the NMISR FNMIFLASH bit is set and if enabled via NMIFLASH an NMI to the CPU is triggered to enter the Flash NMI service routine see Figure 4 9 At this point all Flash banks are in ready to read mode Table 4 1 Flash Program Subroutine Subroutine DFF6 FLASH PROG Input DPTR DPH DPL Flash WL address RO IRAM start address for 64 32 byte Flash data 64 32 byte Flash data fo
281. ctionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit CAN_DIS in register PMCON1 as described below Refer to Chapter 8 1 4 for details on peripheral clock management PMCONT Power Mode Control Register 1 Reset Value 00 7 6 5 4 3 2 1 0 mounis T2_DIS CCU_DIS SSC_DIS ADC_DIS Field Bits Type Description CAN_DIS 5 rw CAN Disable Request Active high 0 CAN is in normal operation default 1 CAN is disabled Reserved Returns 0 if read should be written with 0 User s Manual 15 44 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 2 Registers Description This section describes the registers of the MultiCAN module All MultiCAN register names described in this section are also referenced in other parts of the User s Manual by the module name prefix CAN_ MultiCAN Kernel Register Overview The MultiCAN Kernel include three blocks of registers e Global Module Registers e Node Registers for each CAN node x e Message Object Registers for each message object n Table 15 5 Registers Overview MultiCAN Kernel Registers Offset Address Description see Register Register Long Name Short Name Global Module Registers LISTm 0100 mx 4 Page 15 54 MSPNDk 01204 k x 4 Page 15 56 MSIDk 01404 k x 4 Page 15 57 MSIMASK 01C0 Page 15 58 PANCTR 01C4 Pag
282. curacy calculator Normalized Deviation ND is a generic term used to refer to the magnitude of deviation of the result data from the expected result The deviation is calculated as if the input result data is integer In case the data is a rational number the magnitude of deviation has to be interpreted For example Z for linear vectoring mode of the data form 4 11 ND 1 01 means the difference from expected real data has magnitude of no more than 21 2 ND 2 10 means the difference is no more than 2 2 ND 3 113 means the difference is no more than 2 2 942 ND 4 100 means the difference is no more than 2 2 and so on The value of 2 is always added to account for possible truncation error Table 11 3 lists the probability of Normalized Deviation in a single calculation obtained from simulation with approximately one million different input sets for each respective CORDIC Coprocessor operating mode based on the input conditions specified always within useful domain possibly with additional conditions The accuracy of each mode can be easily increased by working with rational numbers fraction instead of integers This refers to X and Y data only X and Y must always be of same data form while the data form of Z is fixed per the respective LUT s definition It is obvious to expect that for a given input of X and Y and Z the calculated result will always return a constant value re
283. curred CANSRC1 CANSRC2 Reserved Returns 0 if read should be written with 0 E User s Manual 5 26 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System IRCON2 Interrupt Request Register 2 Reset Value 00 7 6 5 4 3 2 1 0 r rwh r rwh Field Bits Type Description CANSRCO rwh Interrupt Flag 0 for MultiCAN This bit is set by hardware and can only be cleared software Interrupt event has not occurred Interrupt event has occurred CANSRC3 re Flag 3 for MultiCAN This bit is set by hardware and can only be cleared 4 software Interrupt event has not occurred Interrupt event has occurred 0 7 5 Reserved 3 1 Returns 0 if read should be written with O IRCONS Interrupt Request Register 3 Reset Value 00 7 6 5 4 3 2 1 0 r rwh rwh r rwh rwh Field Description CCU6SRO prs fw Interrupt Flag 0 for CCU6 This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred User s Manual 5 27 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System Field Description CANSRC4 os Interrupt Flag 4 for MultiCAN This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred CCU6SR1 Interrupt Flag 1 for CCU6 This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event
284. currently belongs to and insert it before a given destination object into the list structure of the destination object The source object thus becomes the predecessor of the destination object V1 1 2007 05 Cinfineon XC886 888CLM Controller Area Network MultiCAN Controller Table 15 7 Panel Commands cont d PANCMD PANAR2 PANAR1 Command Description 05y Argument Result Destination Object Object Number of inserted object Number Result Bit 7 ERR Bit 6 0 undefined 06 Argument Destination Object Source Number Object Number 07y Argument Result Destination Object Object Number Result Bit 7 ERR Bit 6 0 undefined inserted object Argument Number of Dynamic Insert Before Insert a new message object before a given destination object The new object is taken from the list of unallocated elements the first element is chosen The number of the new object is delivered as a result to PANAR1 An ERR bit bit 7 of PANAR2 reports the success of the operation 0 SUCCESS 1 The operation has not been performed because the list of unallocated elements was empty Static Insert Behind Remove a message object source object from the list that it currently belongs to and insert it behind a given destination object into the list structure of the destination object The source object thus becomes the successor of the destination object Dynamic Insert Behind Ins
285. d Bits Type Description RXPND rh Receive Pending 0 No CAN message has been received 1 A CAN message has been received by the message object n either directly or via gateway copy action RXPND is not reset by hardware but must be reset by software TXPND 1 rh Transmit Pending 0 No CAN message has been transmitted 1 A CAN message from message object n has been transmitted successfully over the CAN bus TXPND is not reset by hardware but must be reset by software User s Manual 15 79 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Field Bits Type Description RXUPD 2 rh Receive Updating 0 No receive update ongoing 1 Message identifier DLC and data of the message object are currently updated NEWDAT 3 rh New Data 0 No update of the message object n since last flag reset 1 Message object n has been updated NEWDAT is set by hardware after a received CAN frame has been stored in message object n NEWDAT is cleared by hardware when a CAN transmission of message object n has been started NEWDAT should be set by software after the new transmit data has been stored in message object n to prevent the automatic reset of TXRQ at the end of an ongoing transmission MSGLST 4 rh Message Lost 0 No CAN message is lost 1 A CAN message is lost because NEWDAT has become set again when it has been already set MSGVAL 5 rh Message Valid 0 Message object n is not
286. d CAN_ADH registers User s Manual 15 41 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Write the data to the CAN DATAO0 CAN DATA1 CAN_DATA2 CAN_DATAS registers Write the register CAN ADCON including setting the valid bit of the data registers and setting register bit RWEN to 1 The valid data will be written to the MultiCAN kernel only once Register bit BSY will become 1 When Register bit BSY becomes 0 the transmission is finished Read Process to the MultiCAN Kernel Write the address of the MultiCAN kernel register to the CAN ADL and CAN_ADH registers Write the register CAN ADCON setting register bit RWEN to 0 The 32 bit data will be read from the MultiCAN kernel only once Register bit BSY will become 1 When register bit BSY becomes 0 the transmission is finished Read the data from the CAN DATA0 CAN_DATA1 CAN_DATA2 CAN_DATA3 registers Note The address registers and data registers should be only written read when register bit BSY is 0 User s Manual 15 42 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 11 Port Control The interconnections between the MultiCAN module and the port I O lines are controlled in the port logics In addition to the I O control selection the selection of a CAN node s receive input line is configured by a bit field RXSEL in its node port control register NPCRx
287. d NAD stored in uppermost P Flash Bank Pair Default Broadcast NAD used if value not present or valid e Save LIN frame into XRAM and jump to User Mode if first frame received is an invalid LIN Frame e Programming and LIN Checksum supported e Fast LIN BSL using BSL Mode protocol on single wire UART LIN Re synchronization and setup of baud rate Phase are always performed prior to the entry of Phase II and IIl Thus different baud rates can be supported Phase II is entered when its Master Request Header is received otherwise Phase Ill is entered Slave Response Header The Master Request Header has a Protected ID of 3C while the Slave Response Header has a Protected ID of 7D The microcontroller responds to the host only after a Slave Response Header is received The Command and Response LIN frames are identified as Diagnostic LIN frame which has a standard 8 data byte structure instead of 2 or 4 Upon entering LIN BSL a connection is established and the transfer speed baud rate of the serial communication partner host is automatically synchronized in the following steps e STEP 1 Initialize interface for reception and timer for baud rate measurement e STEP 2 Wait for an incoming LIN frame from the host e STEP 3 Synchronize the baud rate to the host e STEP 4 Enter Phase II for Master Request Frame or e Phase Ill for Slave Response Frame Note Re synchronization and setup of baud rate are always done for every Mast
288. d baud rate This condition sets the error flag CON BE and when enabled via CON BEN sets the EIR Using this error detection capability requires that the slave s baud rate generator be programmed to the same baud rate as the master device This feature detects false additional or missing pulses on the clock line within a certain frame Note If this error condition occurs and bit CON REN 1 an automatic reset of the SSC will be performed This is done to re initialize the SSC if too few or too many clock pulses have been detected Note This error can occur after any transfer if the communication is stopped This is the case due to the fact that the SSC module supports back to back transfers for multiple transfers In order to handle this the baud rate detector expects immediately after a finished transfer the next clock cycle for a new transfer A Transmit Error slave mode is detected when a transfer was initiated by the master SS_CLK gets active but the transmit buffer TB of the slave had not been updated since the last transfer This condition sets the error flag CON TE and the EIR when enabled via CON TEN If a transfer starts without the transmit buffer having been updated the Slave will shift out the old contents of the shift register which normally is the data received during the last transfer This may lead to corruption of the data on the transmit receive line in half duplex mode open drain configuration if this slav
289. d by resetting the GLOBCTR ANON bit This feature causes the generation of franc to be stopped and allows a reduction in power consumption when no conversion is needed In order to Save power consumption when the on chip oscillator is used XTAL should be powered down by setting bit OSC_CON XPD When the external oscillator is used the on chip oscillator can be powered down by setting bit OSC_CON OSCPD 8 2 Register Description PMCONO Power Mode Control Register 0 Reset Value 00 7 6 5 4 3 2 1 0 ES Jee r rwh rwh rw rw rwh rw 0 The reset value for watchdog timer reset is 40 and the reset value for power down wake up reset is 20 Field Description WS 0 Wake up Source Select 00 No wake up is selected 01 Wake up source RXD falling edge trigger is selected 10 Wake up source EXINTO falling edge trigger is selected 11 Wake up source RXD falling edge trigger or EXINTO falling edge trigger is selected User s Manual 8 5 V1 1 2007 05 Power Saving Modes V 1 0 Cinfine on XC886 888CLM Power Saving Modes Field Description PD Power down Enable Bit Setting this bit will cause the chip to enter power down mode It is reset by wake up circuit The PD bit is a protected bit When the Protection Scheme see Chapter 3 5 4 1 is activated this bit cannot be written directly SD Slow down Enable Bit Setting this bit will cause the chip to enter slow down mode It is reset by the user The SD bit is a protected
290. d in every PCLK cycle When a sampled input shows a low high level in one PCLK cycle and a high low in the next PCLK cycle a transition is recognized If the capture signal is detected while the counter is being incremented the counter is first incremented before the capture operation is performed This ensures that the latest value of the timer register is always captured lf bit T2RHEN is set Timer 2 is started by first falling edge rising edge at pin T2EX which is defined by bit T2REGS If bit EXEN2 is set bit EXF2 is also set at the same point when Timer 2 is started with the same falling edge rising edge at pin T2EX which is defined by bit EDGESEL The capture will happen with the following negative positive transitions at pin T2EX which is defined by bit EDGESEL When the capture operation is completed bit EXF2 is set and can be used to generate an interrupt request Figure 13 7 describes the capture function of Timer 2 User s Manual 13 18 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers PREN C T2 10 Overflow O THL2 T2 Timer 2 Interrupt EXEN2 T2EX Figure 13 7 Capture Mode 13 2 4 Count Clock The count clock for the auto reload mode is chosen by the bit C T2 in register T2CON lf C T2 0 a count clock of PCLK 12 if prescaler is disabled is used for the count operation If C T2 1 Timer 2 behaves as a counter that counts 1 to 0 transitions of input pin T2 The counter sampl
291. d right with zeros shifted in from the left When the MSB gets to the output position the control block executes one last shift and sets the TI bit Reception is started by a high to low transition on RXD sampled at 16 times the baud rate The divide by 16 counter is then reset and 1111 1111 is written to the receive register If a valid start bit 0 is then detected based on two out of three samples it is shifted into the register followed by 8 data bits If the transition is not followed by a valid Start bit the controller goes back to looking for a high to low transition on RXD When the Start bit reaches the leftmost position the control block executes one last shift then loads SBUF with the 8 data bits loads RB8 SCON 2 with the stop bit and sets the RI bit provided RI 0 and either SM2 0 see Section 12 1 2 or the received stop bit 1 If none of these conditions is met the received byte is lost The associated timings for transmit receive in mode 1 are illustrated in Figure 12 1 User s Manual 12 3 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces Transmit reset 7p a o OF D o v Q AF x x lt oO ka ro am mw 09 am TX Clock Data Shift TXD TI Receive Figure 12 1 Serial Interface Mode 1 Timing Diagram User s Manual 12 4 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces 12 1 1 3 Mode 2 9 Bit U
292. de 2 while the other is adopted by the rest of the modes Data and EOT Blocks are transferred only in Mode 0 and 2 Microcontroller Header Block Mode 0 2 Response Code Acknowledge 59 gt E HOST Microcontroller Data Block Response Code Header Block Mode 1 3 4 6 A F Response Code Data Block Response Code EOT Block Response Code Mode 0 amp 2 Mode 1 3 4 6 A amp Figure 18 1 Communication Structure of the UART BSL Modes User s Manual 18 9 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader 18 1 2 2 The Selection of Modes When UART BSL routine enters Phase Il it first awaits for an 8 byte Header Block from the host which contains the information for the selection of the modes as shown below Block Type 00 Checksum Mode Mode Data 1 byte H Header Block 1 byte 5 bytes Description e 00 The block type which marks the block as a Header Block e Mode The mode to be selected Mode 0 6 are supported See Table 18 2 e Mode Data Five bytes of special information to activate corresponding mode e Checksum The checksum of the header block XOR of all 7 bytes 18 1 2 3 The Activation of Modes 0 and 2 Mode 0 and Mode 2 are used to transfer a user program from the host to the XRAM and Flash of the microcontroller respectively The header block has the following structure The Header Block
293. defined hardware action The write access to bit fields CURHS and EXPHS does not modify the bit fields CURH and EXPH 1 The bit fields CURH and EXPH are updated by the value written to the bit fields CURHS and e EXPHS Reserved Returns 0 if read should be written with 0 O Register MCMOUT shows the multi channel control bits that are currently used Register MCMOUT is defined as follows MCMOUTL Multi Channel Mode Output Register Low Reset Value 00 7 6 5 4 3 2 1 0 sie l r rh rh User s Manual 14 75 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Description MCMP pe 0 rh Multi Channel PWM Pattern Bit field MCMP is written by a shadow transfer from bit field MCMPS It contains the output pattern for the multi channel mode If this mode is enabled by bit MCMEN in register MODCTR the output state of the following output signal can be modified Bit 0 multi channel state for output CC60 Bit 1 multi channel state for output COUT60 Bit 2 multi channel state for output CC61 Bit 3 multi channel state for output COUT61 Bit 4 multi channel state for output CC62 Bit 5 multi channel state for output COUT62 The multi channel patterns can set the related output to the passive state 0 The output is set to the passive state The PWM generated by T12 or T13 is not taken into account 1 The output can deliver the PWM generated by T12 or T13 according to register MODCTR Whil
294. detected since this bit has been reset for the last time A timer T13 compare match has been detected User s Manual 14 80 V1 1 2007 05 CCU6 V 1 0 Cinfineon Bits Type Description alae T13 Period Match Flag Field T13PM TRPF TRPS CH User s Manual CCU6B V 1 0 XC886 888CLM Capture Compare Unit 6 A timer T13 period match has not yet been detected since this bit has been reset for the last time A timer T13 period match has been detected E Flag The trap flag TRPF will be set by hardware if TRPPEN 1 and CTRAP 0 or by software If TRPM2 0 bit TRPF is reset by hardware if the input CTRAP becomes inactive TRPPEN 1 If TRPM2 1 bit TRPF must be reset by software in order to leave the trap state 0 The trap condition has not been detected 1 The trap condition has been detected input CTRAP has been 0 or by software Trap State 0 The trap state is not active The trap state is active Bit TRPS is set while bit TRPF 1 It is reset according to the mode selected in register TRPCTR During the trap state the selected outputs are set to the passive state The logic level driven during the passive state is defined by the corresponding bit in register PSLR Bit TRPS 1 and TRPF 0 can occur if the trap condition is no longer active but the selected synchronization has not yet taken place Correct Hall Event On every valid hall edge the contents of EXPH are compared with
295. device contains either a 24 Kbyte or 32 Kbyte ROM the maximum size of code that can be placed in the ROM is the given size less four bytes XRAM XRAM 1 5 Kbytes 1 5 Kbytes Boot ROM 12 Kbytes D Flash Bank 4 Kbytes Indirect Direct Address Address ROM 32 Kbytes Internal RAM Special Function Registers Internal RAM v vy Program Space External Data Space Internal Data Space Figure 3 2 Memory Map of XC886 888 ROM Device User s Manual 3 2 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization 3 1 Compatibility between Flash and ROM devices Each Flash device consists of P Flash and D Flash banks As shown in Figure 3 3 each physical D Flash bank is mapped to two program memory address spaces e D Flash Bank 0 is mapped to 7000 7FFF and A000 AFFF e D Flash Bank 1 is mapped to 6000 6FFF and B000 BFFF XRAM XRAM 1 5 Kbytes 1 5 Kbytes Boot ROM Boot ROM 12 Kbytes 12 Kbytes P Flash Banks 4 and 5 2 x 4 Kbytes M 32 Kbytes 4 bytes P Flash Banks 2 and 3 2 x 4 Kbytes P Flash Banks 0 and 1 2 x 4 Kbytes 24K P Flash 8K D Flash 32K ROM Device Device a The last four bytes of the ROM in the ROM device from 7FFC to 7FFF are reserved for the ROM signature and cannot be used for user code
296. ds to the core User s Manual 5 21 V1 1 2007 05 Interrupt System V 1 0 Cinfineon Field XC886 888CLM Interrupt System Bits Type Description Interrupt on falling edge Interrupt on rising edge Interrupt on both rising and falling edges EXINT2 5 4 rw External Interrupt 2 Trigger Select 00 01 10 11 External interrupt 2 is disabled Interrupt on falling edge Interrupt on rising edge Interrupt on both rising and falling edges External interrupt 3 is disabled EXINT3 7 6 rw External Interrupt 3 Trigger Select 00 01 10 11 EXICON1 External Interrupt Control Register 1 7 6 5 4 Reset Value 3F 3 2 1 0 ee EXINTS EXINTS EXINTA r rw rw rw Field Bits Type Description EXINT4 1 0 rw External Interrupt 4 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edges 11 External interrupt 4 is disabled EXINT5 3 2 rw External Interrupt 5 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on both rising and falling edges 11 External interrupt 5 is disabled EXINT6 Interrupt on falling edge Interrupt on rising edge Interrupt on both rising and falling edges External interrupt 6 is disabled 5 4 rw External Interrupt 6 Trigger Select 00 01 10 11 0 7 6 r Reserved Returns 0 if read should be written with 0 Users Manual 5 22 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888C
297. dware at the beginning of calculation MODE Operating Mode 00 Linear Mode 01 Circular Mode default 10 Reserved 11 Hyperbolic Mode ROTVEC Rotation Vectoring Selection 0 Vectoring Mode default 1 Rotation Mode ST MODE Start Method 0 Auto start of calculation after write access to X low byte CD_CORDXL default 1 Start calculation only after bit ST is set User s Manual 11 16 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfin eon XC886 888CLM CORDIC Coprocessor Field Description X_USIGN Result Data Format for X in Circular Vectoring Mode When reading the X result data with DMAP 0 X data has a data format of 0 Signed twos complement 1 Unsigned default With this bit set the MSB bit of the X result data is processed as a data bit instead of a sign bit Note This bit is only effective when operating in circular vectoring mode In all other modes X is always processed as twos complement data Note X_USIGN 1 is meaningful in circular vectoring mode because the result data is always positive and always larger than the initial data MP 6 X and Y Magnitude Prescaler After the last iteration of a calculation the calculated value of X and Y are each divided by this factor to yield the result Proper setting of these bits is important to avoid an overflow of the result in the respective kernel data registers 00 Divide by 1 01 Divide by 2 default 10 Divide by 4 11 Reserved retain the last MPS settin
298. e 15 48 MCR 01C8 Page 15 52 MITR 01CC Page 15 53 Node Registers NCRx 0200 x x100 Page 15 59 NSRx 0204 xx 100 Page 15 63 NIPRx 0208 xx100 Page 15 66 NPCRx 020C xx100 Page 15 68 NBTRx 02104 xx 100 Page 15 69 NECNTx 0214 xx100 Page 15 71 NFCRx 0218 xx 100 Page 15 72 Message Object Registers MOFCRn Message Object n Function Control Register 1000 N x 20 Page 15 86 MOFGPRn Message Object n FIFO Gateway Pointer Register 1004 N x 20 Page 15 90 User s Manual 15 45 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Table 15 5 Registers Overview MultiCAN Kernel Registers cont d Register Register Long Name Offset Address Description Short Name see MOIPRn Message Object n 1008 n x 20 Page 15 84 Interrupt Pointer Register MOAMRn Message Object n 100C n x 20 Page 15 91 Acceptance Mask Register MODATALn Message Object n 1010 nx 20 Page 15 95 Data Register Low MODATAHhn Message Object n 10144 N xX 20 Page 15 96 Data Register High MOARn Message Object n 10184 N x 204 Page 15 92 Arbitration Register MOCTRn Message Object n Control Reg 101C n x 20 Page 15 76 MOSTATn Message Object n Status Reg Page 15 79 1 The following ranges for parameters m k x and n are valid m 7 0 k 1 0 x 1 0 n 31 0 MultiCAN Access Mediator Register Overview Table 15 6 shows the addresses non mapped of
299. e IDLE 1 bit field MCMP is cleared Reminder Flag This reminder flag indicates that the shadow transfer from bit field MCMPS to MCMP has been requested by the selected trigger source This bit is cleared when the shadow transfer takes place and while MCMEN 0 0 Currently no shadow transfer from MCMPS to MCMP is requested 1 A shadow transfer from MCMPS to MCMP has been requested by the selected trigger source but it has not yet been executed because the selected synchronization condition has not yet occurred Reserved Returns 0 if read should be written with 0 User s Manual 14 76 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 MCMOUTH Multi Channel Mode Output Register High Reset Value 00 7 6 5 4 3 2 1 0 r rh rh Field Description hall event is set and an interrupt request is generated if enabled by bit ENWHE CURH 3 Current Hall Pattern Bit field CURH is written by a shadow transfer from bit field CURHS The contents are compared after every detected edge at the hall input pins with the pattern at the hall input pins in order to detect the occurrence of the next desired expected hall pattern or a wrong pattern If the current hall input pattern is equal to bit field CURH the detected edge at the hall input pins has been an invalid transition e g a spike EXPH pe 0 rh Expected Hall Pattern Bit field EXPH is written by a shadow transfer from bit field EXPHS The con
300. e Message Index Mask Register MSIMASK selects individual bits for the calculation of the Message Pending Index The Message Index Mask Register is used commonly for all Message Pending registers and their associated Message Index registers MSIMASK Message Index Mask Register Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Description IM CN 0 Message Index Mask Only those bits in MSPNDk for which the corresponding Index Mask bits are set contribute to the calculation of the Message Index User s Manual 15 58 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 2 2 CAN Node Registers The CAN node registers are built in for each CAN node of the MultiCAN module They contain information that is directly related to the operation of the CAN nodes and are shared among the nodes The Node Control Register NCRx contains basic settings that define the operation of the CAN node NCRx x 0 1 Node x Control Register Reset Value 0000 0001 31 380 29 28 2 26 25 24 2 2 21 20 19 18 17 16 BOGGS Seeeeeee r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAL CAN LECI r rw rw r rw rw rw rwh rw User s Manual 15 59 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Field Bits Type Description INIT rwh Node Initialization 0 Resetting bit INIT enables the participation of the node i
301. e MultiCAN module and a bus select switch for each CAN node With the switch each CAN node can be connected either to the internal CAN bus loop back mode activated or the external CAN bus respectively to its transmit or receive pin normal operation The CAN bus which is currently not selected is driven recessive this means the transmit pin is held at 1 and the receive pin is ignored by the CAN nodes that are in loop back mode The loop back mode is selected by setting bit NPCRx LBM All CAN nodes that are in loop back mode may communicate together via the internal CAN bus without affecting the normal operation of the other CAN nodes that are not in loop back mode User s Manual 15 18 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller NPCRO LBM internal CAN bus 0 CAN node 0 Z 1 NPCR1 LBM 0 CAN node 1 Z 1 MultiCAN_loop_back_x2 Figure 15 8 Loop Back Mode 15 1 5 3 Bit Timing Analysis Detailed analysis of the bit timing can be performed for each CAN node using the analysis modes of the CAN frame counter The bit timing analysis functionality of the frame counter may be used for automatic detection of the CAN baud rate as well as for the analysis of the timing of the CAN network Bit timing analysis is selected by NFCRx CFMOD 10 Bit timing analysis does not affect the operation of the CAN node The bit timing measurement results are written into the NFCRx CFC bit
302. e access to the PANCTR Register With the write operation of a valid command code the PANCTR BUSY flag is set and further write accesses to the Panel Control Register are ignored The BUSY flag remains active and the control panel remains locked until the execution of the requested command has been completed After a reset the list controller builds up list 0 During this operation BUSY is set and other accesses to the CAN RAM are forbidden The CAN RAM can be accessed again when BUSY becomes inactive Note The CAN RAM is automatically initialized after reset by the list controller in order to ensure correct list pointers in each message object The end of this CAN RAM initialization is indicated by bit PANCTR BUSY becoming inactive In case of a dynamic allocation command that takes an element from the list of unallocated objects the PANCTR RBUSY bit becomes set together with the BUSY bit RBUSY BUSY 1 This indicates that bit fields PANCTR PANAR1 and PANCTR PANAR2 are going to be updated by the list controller in the following way User s Manual 15 16 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller 1 The message number of the message object taken from the list of unallocated elements is written to PANAR1 2 If ERR bit 7 of PANAR2 is set to 1 the list of unallocated elements was empty and the command is aborted If ERR is 0 the list was not empty and the command will be
303. e bit fields CC6xV contain the values that are compared to the T12 counter value In capture mode the captured value of T12 can be read from these registers CC6xSRL x 0 1 2 Capture Compare Shadow Register for Channel CC6x Low Reset Value 00 7 6 5 4 3 2 1 0 CC6xSL x 0 1 2 rwh User s Manual 14 48 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Description CC6xSL ets p Shadow Register for Channel x x 0 1 2 Capture Compare Value Low Byte In compare mode the contents of bit field CC6xS are transferred to the bit field CC6xV during a shadow transfer In capture mode the captured value of T12 can be read from these registers CC6xSRH x 0 1 2 Capture Compare Shadow Register for Channel CC6x High Reset Value 00 7 6 5 4 3 2 1 0 CC6xSH x 0 1 2 rwh Field Description CC6xSH Bis f Shadow Register for Channel x x 0 1 2 Capture Compare Value High Byte In compare mode the contents of bit field CC6xS are transferred to the bit field CC6xV during a shadow transfer In capture mode the captured value of T12 can be read from these registers User s Manual 14 49 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 T12DTCL Dead Time Control Register for Timer T12 Low Reset Value 00 7 6 9 4 3 2 1 0 DTM rw Field Bits Type Description DTM 7 0 rw Dead Time Bit field DIM determines the programmable delay between switchin
304. e bytes are not used and will be ignored in Mode 1 3 F For Modes 1 3 and F the header block is the only transfer block to be sent by the host no further serial communication is necessary The microcontroller will then exit the BSL Mode and jump to the XRAM address at OFOOO Mode 1 jump to Flash address at 0000 Mode 3 and or start to communicate with the OCDS UART debugger Mode F 18 1 2 5 The Activation of Mode 4 Mode 4 is used to erase sector s of P Flash bank s or D Flash bank s or mass erase of all sectors in P Flash and D Flash banks The selection of the type of erase is controlled through the Option byte in the header block When Option 00 this mode is used to erase the P Flash sector s The header block has the following structure The Header Block Mode Data 5 bytes Checksum Option 00 Mode Data Description PFlash_Bank_Pair0 The sectors 0 to 2 of P Flash Bank Pair 0 Banks 0 and 1 are represented by bits 0 to 2 For example a value of 03 in the PFlash_Bank_Pair0 byte selects sectors 0 and 1 of P Flash Banks 0 and 1 for erase 1 Bits 3 to 7 must be cleared to 0 2 When the bit contains a 1 the corresponding sector is selected User s Manual 18 12 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader PFlash_Bank_Pair1 The sectors 0 to 2 of P Flash Bank Pair 1 Banks 2 and 3 are represented by bits 0 to 2 For example a value of 05 in the P
305. e current operation to be aborted and triggers an interrupt see Section 10 2 below A division by zero error does not set the error flag immediately but rather at the end of calculation phase for a division operation An opcode error is detected upon setting MDUCON START to 1 Errors due to division by zero lead to the loading of a saturated value into the MRx registers Note The accuracy of any result obtained when the error flag is set is not guaranteed by MDU and hence the result should not be used 10 2 Interrupt Generation The interrupt structure of the MDU is shown in Figure 10 2 There are two possible interrupt events in the MDU and each event sets one of the two interrupt flags The interrupt flags is reset by software by writing O to it At the end of phase two the interrupt flag MDUSTAT IRDY is set by hardware to indicate the successful completion of a calculation The results can then be obtained from the MRx registers The interrupt line INT _O0 is mapped directly to this interrupt source An interrupt can also be triggered when an error occurs during calculation This is indicated by the setting of the interrupt flag MDUSTAT IERR In the event of a division by zero error MDUSTAT IERR is set only at the end of the calculation phase Once the MDUSTAT IERR is set any ongoing calculation will be aborted For a division by zero error a saturated value is then loaded into the MRx registers The bit MDUCON IR determines the interru
306. e is not selected for transmission This mode requires that slaves not selected for transmission only shift out ones that is their transmit buffers must be loaded with FFFF prior to any transfer Note A slave with push pull outout drivers not selected for transmission will normally have its output drivers switched off However in order to avoid possible conflicts or misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer The cause of an error interrupt request receive phase baud rate or transmit error can be identified by the error status flags in control register CON Note The error status flags CON TE CON RE CON PE and CON BE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software User s Manual 12 42 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 3 2 Interrupts An overview of the various interrupts in SSC is provided in Table 12 7 Table 12 7 SSC Interrupt Sources Interrupt Signal Description Transmission TIR Indicates that the transmit buffer can be reloaded with new Starts data Transmission The configured number of bits have been transmitted and ends shifted to the receive buffer Receive EIR This interrupt occurs if a new data frame is completely Error received and the last data in the receive buffer was not read Phase Error EIR This interrupt is genera
307. e level driven by the output pins of the module The passive state level is the value that is driven by the port pin during the passive state of the output During the active state the corresponding output pin drives the active state level which is the inverted passive state level The passive state level permits the adaptation of the driven output levels to the driver polarity inverted not inverted of the connected power stage PSLR Passive State Level Register Reset Value 00 7 6 5 4 3 2 1 0 PSL rwh r rwh Field Bits Type Description PSL 5 0 rwh Compare Outputs Passive State Level The bits of this bit field define the passive level driven by the module outputs during the passive state The bit positions are Bit O passive level for output CC60 Bit 1 passive level for output COUT60 Bit 2 passive level for output CC61 Bit 3 passive level for output COUT61 Bit 4 passive level for output CC62 Bit 5 passive level for output COUT62 The value of each bit position is defined as 0 The passive level is 0 1 The passive level is 1 User s Manual 14 72 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Bits Type Description PSL63 7 rwh_ Passive State Level of Output COUT63 This bit field defines the passive level of the output pin COUT6S3 A The passive level is 0 The passive level is 1 0 Reserved Returns 0 if read should be written with 0 Note Bit field PSL has a shadow register to
308. e match while counting down 0 The shadow register transfer is disabled 1 The shadow register transfer is enabled CDIR rh Count Direction of Timer T12 This bit is set reset according to the counting rules of T12 0 T12 counts up 1 T12 counts down CTM 7 rw T12 Operating Mode 0 Edge aligned Mode T12 always counts up and continues counting from zero after reaching the period value 1 Center aligned Mode T12 counts down after detecting a period match and counts up after detecting a one match TCTROH Timer Control Register 0 High Reset Value 00 7 6 5 4 3 2 1 0 STE T13 Ooo alela e r rh rh rw rw User s Manual 14 60 V1 1 2007 05 CCU6 V 1 0 Cinfineon Bits Type Description Timer T13 Input Clock Select Selects the input clock for timer T13 which is derived from the peripheral clock according to the equation tr o gt fooy 2s cian Field T13CLK T13PRE T13R STE13 User s Manual CCU6B V 1 0 2 0 rw 000 001 010 011 100 101 110 111 fris focu fris focu 2 fris focu 4 fris focy 8 fris focy 16 fris focy 32 ftis focu 64 ftis foc 28 Timer T13 Prescaler Bit In order to support higher clock frequencies an additional prescaler factor of 1 256 can be enabled for the prescaler for T13 The additional prescaler for T13 is disabled The additional prescaler for T13 is enabled Timer T13 Run Bit T13R starts and stops timer T13 It is set reset by software by setting bits T13RS
309. e object involved in the transfer e Time Stamp Mode The frame counter is incremented with the beginning of a new bit time When the transmission reception of a frame starts the value of the frame counter is captured and stored to the bit field NFCRx CFC After the successful transfer of the frame the captured value is copied to the bit field MOIPRn CFCVAL of the message object involved in the transfer e Bit Timing Mode Used for baud rate detection and analysis of the bit timing Chapter 15 1 5 3 15 1 3 5 CAN Node Interrupts Each CAN node is equipped with four interrupt sources to generate an interrupt request upon e the successful transmission reception of a frame e a CAN protocol error with a last error code e an alert condition occurs transmit receive error counters reach the warning limit bus off state changes a list length error occurs or a list object error occurs e an overflow of the frame counter Besides the hardware generated interrupts software initiated interrupts can be generated using the register MITR Writing a 1 to bit n of bit field MITR IT generates an interrupt request signal on the corresponding interrupt output line CANSRCm When writing MITR IT more than one bit can be set resulting in the activation of multiple CANSRCm interrupt output lines at the same time User s Manual 15 11 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Correct Message
310. e requests If the data within the message object has not been updated in the time between the transmissions the same data can be sent more than once on the CAN bus In single data transfer mode SDT 1 this is avoided because MSGVAL is automatically cleared after the successful transmission of a data frame After the transmission of a remote frame bit MSGVAL is not automatically cleared 15 1 9 3 Single Transmit Trial If bit MOFCRn STT is set then the transmission request is cleared TXRQ 0 when the frame content of the message object has been copied to the internal transmit buffer of the CAN node Thus the transmission of the message object is not tried again when it fails due to CAN bus errors User s Manual 15 33 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller 15 1 9 4 Message Object FIFO Structure In case of high CPU load it may be difficult to process a series of CAN frames in time This may happen if multiple messages are received or must be transmitted in short time Therefore a FIFO buffer structure is available to avoid loss of incoming messages and to minimize the setup time for outgoing messages The FIFO structure can also be used to automate the reception or transmission of a series of CAN messages and to generate a single message interrupt when the whole CAN frame series is done There can be several FIFOs in parallel The number of FIFOs and their size a
311. ecial Function Registers The Special Function Registers SFRs occupy direct internal data memory space in the range 80 to FF All registers except the program counter reside in the SFR area The SFRs include pointers and registers that provide an interface between the CPU and the on chip peripherals As the 128 SFR range is less than the total number of registers required address extension mechanisms are required to increase the number of addressable SFRs The address extension mechanisms include e Mapping e Paging 3 5 1 Address Extension by Mapping Address extension is performed at the system level by mapping The SFR area is extended into two portions the standard non mapped SFR area and the mapped SFR area Each portion supports the same address range 80 to FF bringing the number of addressable SFRs to 256 The extended address range is not directly controlled by the CPU instruction itself but is derived from bit RMAP in the system control register SYSCONO at address 8F To access SFRs in the mapped area bit RMAP in SFR SYSCONO must be set However the SFRs in the standard area can be accessed by clearing bit RMAP Figure 3 4 shows how the SFR area can be selected As long as bit RMAP is set the mapped SFR area can be accessed This bit is not cleared automatically by hardware Thus before standard mapped registers are accessed bit RMAP must be cleared set respectively by software User s Manual 3 10 V1 1 2007 05
312. eck that both NEWDAT and RXUPD are cleared If this is not the case go back to step 1 4 As step 3 was successful the message object content is consistent i e has not been updated by the MultiCAN module while reading Bits RXUPD NEWDAT and MSGLST have the same behavior for the reception of data as well as remote frames User s Manual 15 28 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Start receiving et Data from CAN frame gateway fifo source no Done AN rec successfu yes yes yes RXUPD 1 RXUPD 1 2 Copy Frame to Copy Frame to Message Obj Message Obj 3 TXRQ 1 inthis YCS or in foreign obj No yes MSGLST 1 lt lt NEWDAT 7 No NEWDAT 1 RXUPD 0 RXPND 1 4 time milestones msgobj_receive Figure 15 11 Reception of a Message Object User s Manual 15 29 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 8 2 Frame Transmission The process of a message object transmission is shown in Figure 15 12 With the copy of the message object content to be transmitted identifier IDE bit RTR DIR bit DLC and for data frames also the data field into the internal transmit buffer of the assigned CAN node also several status flags are served and monitored to control consistent data handling The transmission process of a message object starting after the tran
313. ed and are set to 00 Checksum The LIN Checksum contains the eight bit sum with carry over NAD Response and Not Used All responses will adopt LIN Checksum regardless of modes User s Manual 18 23 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader 18 1 3 9 Fast LIN BSL Fast LIN BSL is an enhanced feature in XC886 888 device supporting higher baud rate up to 115 2KHz This is higher than Standard LIN which supports only a baud rate of up to 20 kHz This mode is especially useful during back end programming where faster programming time is desirable Fast LIN BSL is entered when the last byte of the Mode Data of Command LIN frame is 01 header block for LIN Modes 0 2 and 8 See Section 18 1 3 3 When Fast LIN BSL Master Request Header and Command LIN frames are received the microcontroller will wait for the Slave Response Header LIN frame before sending back the Response LIN frame The host will then send the header block using BSL UART protocol at the calculated high baud rate See Figure 18 5 Microcontroller will stay at Fast LIN BSL and the communication structure and selection of modes will be like BSL Mode via UART as shown in Section 18 1 2 1 and Section 18 1 2 2 LIN BSL a Master Request Header e Command SYN 8 Data bytes for Command Break SYN Protected NAD Header Mode Fast_Prog At least Char ID xx 00 00 08 XX4 XX XX XX Ofu 13 bits 55 3C or low X
314. ed as a special coprocessor for multiplication division normalization and shift Its operation can be divided into three phases see Figure 10 1 Phase one Load MDx registers In this phase the operands are loaded into the MDU Operand MDx registers by the CPU The type of calculation the MDU must perform is selected by writing a 4 bit opcode that represents the required operation into the bit field MDUCON OPCODE Phase two Execute calculation This phase commences only when the start bit MDUCON START is set which in turn sets the busy flag The start bit is automatically cleared in the next cycle During this phase the MDU works on its own in parallel with the CPU The result of the calculation is made available in the MDU Result MRx registers at the end of this phase Phase three Read result from the MRx registers In this final phase the result is fetched from the MRx registers by the CPU The MRx registers will be overwritten at the start of the next calculation phase Start bit is First Write set First Read Last Read Phase 1 Phase 2 Phase 3 Load Registers Calculate Read Registers Figure 10 1 Operating phases of the MDU User s Manual 10 2 V1 1 2007 05 MDU V2 1 Cinfin eon XC886 888CLM Multiplication Division Unit 10 1 1 Division Operation The MDU supports the truncated division operation which is also the ISO C99 standard and the popular choice among modern processo
315. ed bits is added to the description of NewBit in Table 15 10 We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com p lt Cinfin eon XC886 888CLM Table of Contents Page 1 INIFOOUCTION 2 42 euceceusny eee e ewes sey eehe eee esses oheeees 1 1 1 1 Feature Summary 0 eee ee eee 1 4 1 2 Pili CGOMMGUIAlOn s i nc20debenes basse be see Seers ee edasecse es 1 6 1 3 Pin Definitions and Functions 0 0 ccc eee 1 8 1 4 Chip Identification Number 0 0 0 c eee eee 1 17 1 5 Text Conventions 0 0 0 0 ee eee ee ees 1 18 1 6 Reserved Undefined and Unimplemented Terminology 1 19 Tee AOON a esa a iu eeeaee Goud eyeeee see eee eee sen Ge eee eet 1 19 2 Processor Architecture 0 0 0 0 ccc ees 2 1 2 1 Functional Description 1 0 2 0 0 0 eens 2 1 2 2 CPU Register Description 0 0 cc ees 2 3 2 2 1 stack Pointer SP 22 4 02 00220600444 000 44506 ESR Cae teen eee 2 3 2 2 2 Data Pointer DPTR 0 0 ccc eens 2 3 2 2 3 Accumulator ACC 1 0 0 0 eee eee 2 3 2 2 4 B Register s encgeeuconcetceeeuree nose ede aeenaees 46e enue os 2 3 2 2 5 Program Status Word 0 ccc eee eee 2 4 2 2 6 Extended Operation EO
316. ed frames with 29 bit identifier O User s Manual 15 92 V1 1 2007 05 MultiCAN V1 0 Cinfineon Field PR 30 User s Manual MultiCAN V1 0 XC886 888CLM Controller Area Network MultiCAN Controller Description Priority Class PRI assigns one of the four priority classes 0 1 2 3 to message object n A lower PRI number defines a higher priority Message objects with lower PRI value always win acceptance filtering for frame reception and transmission over message objects with higher PRI value Acceptance filtering based on identifier mask and list position is performed only between message objects of the same priority class PRI also determines the acceptance filtering method for transmission 00 Reserved 01 Transmit acceptance filtering is based on the list order This means that message object n is considered for transmission only if there is no other message object with valid transmit request MSGVAL amp TXENO amp TXEN1 1 somewhere before this object in the list 10 Transmit acceptance filtering is based on the CAN identifier This means message object n is considered for transmission only if there is no other message object with higher priority identifier IDE DIR with respect to CAN arbitration rules somewhere in the list see Table 15 13 11 Transmit acceptance filtering is based on the list order as PRI 01 15 93 V1 1 2007 05 Cinfin eon XC886 888CLM Controller A
317. ed in Table 18 2 e Phase lll Response to host to indicate successful failure transfer See Section 18 1 1 3 Table 18 2 Serial Communication Modes of the UART and LIN BSL Modes Mode Description 0 00 Transfer a user program from the host to XRAM F000 to F5FF 1 01 Execute a user program in the XRAM at start address FO00 2 02 Transfer a user program from the host to Flash 0000 to 2FFF A000 to AFFF 3 03 Execute a user program in the Flash at start address 0000 4 04 Erase Flash sector s 6 06 Flash Protection Mode enabling disabling scheme 8 08 Transfer a user program from the host to XRAM F000 to F5FF 9 09 Execute a user program in the XRAM at start address FO00 7 A 0A Get 4 byte chip information F OF Enter OCDS UART Mode The microcontroller would return to the beginning of Phase I II and wait for the next command from the host BSL Mode is exited and the serial communication is not established N x y ye Mode 8 and Mode 9 are supported in BSL Mode via LIN only It is the similar to Mode 0 and Mode 1 Basic serial communication protocol such as transfer block structure and the various response code to host for both BSL Mode via UART and LIN are described in Section 18 1 1 while implementation details of BSL Mode via both UART and LIN protocols will be covered in Section 18 1 2 and Section 18 1 3 respectively
318. ee options are available to awaken it e through RXD e through EXINTO e through RXD or EXINTO selection of these options is made via the control bit PMCONO WS The wake up from power down can be with reset or without reset this is chosen by the PMCONO WKSEL bit The wake up status with or without reset is indicated by the PMCONO WKRS bit Figure 7 5 shows the power down wake up reset sequence The EVR takes approximately 150 us to become stable which is a shorter time period compared to the power on reset FLASH go to Reset Is EVR is stable PLL is locked Ready to Read released and Mode Start of program Max 200 us Typ 160 us Figure 7 5 Power down Wake up Reset In addition to the above mentioned three options the power down mode can also be exited by the hardware reset through RESET pin 7 2 1 5 Brownout Reset In active mode the Vppc detector in EVR detects brownout when the core supply voltage Vopc dips below the threshold voltage Vbpe ty 2 1 V The brownout will cause the device to be reset In power down mode the Vppc is monitored by the POR in EVR and a reset is generated when Vbpc drops below 1 5 V Once the brownout reset takes place the reset sequence is the same as the power on reset sequence as shown in Figure 7 4 User s Manual 7 6 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management 7 2 2 Module Reset Behavior Table 7 1 lists
319. eee eee 16 33 16 7 2 Priority and Arbitration Register 0 0 00 cee eee 16 36 16 7 3 External Trigger Control Register 20 000 c eee eee 16 38 16 7 4 Channel Control Registers 0 0 eee 16 39 16 7 5 Input Class Register 0 0 eee ees 16 40 16 7 6 Sequential Source Registers naana aaea 16 41 16 7 7 Parallel Source Registers 0 0 00 ee eee 16 49 16 7 8 Result Registers 2 0 0 eens 16 53 16 7 9 Interrupt Registers 0 0 ce eee 16 59 17 On Chip Debug Support 0 0 0 cc eee 17 1 17 1 FOAMS 2 onease een Gesee nese Gaeed eh eos E464 44 Fodeds EERE 17 1 17 2 Functional Description 0 0 0 eee 17 2 17 3 DCDUGGING 2 44 dene nc E eae oe b ace eee 6 ee been dee hee oe eee Oe 17 3 17 3 1 Debug Events 0c eee ees 17 3 17 3 1 1 Hardware BreakpointS 0 0 0 cee eee eee 17 4 17 3 1 2 Software BreakpointS n naaa anaana ee eee 17 5 17 3 1 3 External BreakS 0 ccc tees 17 6 17 3 1 4 NMlI mode priority over Debug mode 00000 ee 17 6 17 3 2 Debug Actions 0 aaa eee eens 17 6 User s Manual l 9 V1 1 2007 05 Cinfineon Table of Contents 17 3 2 1 Call the Monitor Program 17 3 2 2 Activate the MBC pin 0 17 4 Debug Suspend Control 0006 17 5 Register Description 00000 17 5 1 Monitor Work Register 2 005 17 5 2 Input
320. eeeenge eared 12 26 122 2 LIN Header Transmission 0 000 eee ee eee 12 28 12 2 2 1 Automatic Synchronization to the Host 005 12 28 12 2 2 2 Baud Rate Detection of LIN 0 0 cee eee 12 29 12 3 High Speed Synchronous Serial Interface 00000 12 31 12 3 1 General Operation 0 0 0 0 ee eee 12 32 12 3 1 1 Operating Mode Selection 0 0 00 eee 12 32 12 3 1 2 Full Duplex Operation 0 0 00 eee 12 33 12 3 1 3 Half Duplex Operation 0 0 0 00 eee 12 36 User s Manual l 5 V1 1 2007 05 Cinfin eon XC886 888CLM Table of Contents Page 12 3 1 4 Continuous Transfers 0 0 00 a ee ee es 12 37 12 3 1 5 POM COMMO saccadeae eb hee Geeee owod hae aeead wows wbewnae 12 38 12 3 1 6 Baud Rate Generation 0 00 ccc ee ees 12 39 12 3 1 7 Error Detection Mechanisms 0 0000 c eee eee eee 12 41 12 3 2 Interrupts a6 6and wen oo Peek RE eee Pee eee bee eek ee we 12 43 12 3 3 Low Power Mode 00 cee a 12 44 12 3 4 Register Map 0 0 cc eee eas 12 44 12 3 5 Register Description 0 ce eee eee 12 45 12 3 5 1 Port Input Select Register 0 00 eee 12 45 12 3 5 2 Configuration Register 0 ccc eens 12 46 12 3 5 3 Baud Rate Timer Reload Register 000008 12 50 12 3 5 4 Transmit and Receive Buffer Register 005 12 51 13 Timers 2 0 ee ee eee eee 13 1 13 1 TimerQ and Timer 1 0
321. egister CB Reset Value 00 7 6 5 4 3 2 1 0 rh r rh rh r Field Bits Type Description BUSY rh Analog Part Busy This bit indicates that a conversion is currently active O The analog part is idle 1g A conversion is currently active SAMPLE 1 rh Sample Phase This bit indicates that an analog input signal is currently sampled O The analog part is not in the sampling phase 1 The analog part is in the sampling phase CHNR 5 3 rh Channel Number This bit field indicates which analog input channel is currently converted This information is updated when a new conversion is started 0 2 7 6 r Reserved Returns 0 if read should be written with 0 User s Manual 16 35 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 7 2 Priority and Arbitration Register Register PRAR contains bits that define the request source priority and the conversion start mode It also contains bits that enable disable the conversion request treatment in the arbitration slots PRAR Priority and Arbitration Register CC Reset Value 00 7 6 5 4 3 2 1 0 rw rw r rw rw rw rw rw Field Description PRIOO Priority of Request Source 0 This bit defines the priority of the sequential request source 0 Os Low priority 1 High priority CSMO Conversion Start Mode of Request Source 0 This bit defines the conversion start mode of the sequential request source 0 Os The wait for start mode is selected 1 The cancel
322. egister 2 3 6 Boot ROM Operating Mode After a reset the CPU will always start by executing the Boot ROM code in active memory map 0 In active memory map 0 the Boot ROM occupies the program memory address space 0000 2FFF and C000 EFFF with the remaining program memory address space disabled The Boot ROM start up procedure will first jump to COOX before switching to active memory map 1 as shown in Figure 3 7 As a result the Boot ROM memory formerly occupying the address range 0000 2FFF and C000 EFFF will be mapped to only C000 EFFF Also the remaining program memory blocks XRAM P Flash and D Flash are enabled After the active memory map switch the remaining Boot ROM start up procedure will be executed from CO0X This includes checking the latched values of pins MBC TMS and P0 0 to enter the selected Boot ROM operating modes Refer to Chapter 7 2 3 for the selection of different Boot ROM operating modes The memory organization of the XC886 888 shown in this document is after the active memory map switch i e active memory map 1 where the different operating modes are executed User s Manual 3 41 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization D Flash Banks as data D Flash Banks as program 3000 P Flash Banks CPU starts execution 0000 Active Memory Map 0 Active Memory Map 1 Af
323. egister 2 is selected 11 The result register 3 is selected LCC 6 4 Limit Check Control This bit field defines the behavior of the limit checking mechanism See coding in Section 16 4 8 2 0 3 2 7 r Reserved Returns 0 if read should be written with 0 User s Manual 16 39 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 7 5 Input Class Register Register INPCRO contains bits that control the sample time for the input channels INPCRO Input Class 0 Register CE Reset Value 00 7 6 5 4 3 2 1 0 STC rw Field Description STC C 0 Sample Time Control This bit field defines the additional length of the sample time given in terms of fapc clock cycles A sample time of 2 analog clock cycles is extended by the programmed value User s Manual 16 40 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 7 6 Sequential Source Registers These registers contain the control and status bits of sequential request source 0 Register QMRO contains bits that are used to set the sequential request source in the desired mode QMRO Queue Mode Register CD Reset Value 00 7 6 5 4 3 2 1 0 W W W W r rw r rw Field Description ENGT Enable Gate This bit enables the gating functionality for the request source Os The gating line is permanently 0 The source is switched off 1 The gating line is permanently 1 The source is Switched on ENTR Enable Exte
324. egisters NIPRx MOIPRn User s Manual Interrupt System V 1 0 5 3 O V1 1 2007 05 Cinfin eon XC886 888CLM Parallel Ports 6 Parallel Ports The XC886 has 34 port pins organized into five parallel ports Port O PO to Port 4 P4 while the XC888 has 48 port pins organized into six parallel ports Port O PO to Port 5 P5 Each pin has a pair of internal pull up and pull down devices that can be individually enabled or disabled Ports PO P1 P3 P4 and P5 are bidirectional and can be used as general purpose input output GPIO or to perform alternate input output functions for the on chip peripherals When configured as an output the open drain mode can be selected Port P2 is an input only port providing general purpose input functions alternate input functions for the on chip peripherals and also analog inputs for the Analog to Digital Converter ADC Bidirectional Port Features e Configurable pin direction e Configurable pull up pull down devices e Configurable open drain mode e Transfer data through digital inputs and outputs general purpose I O e Alternate input output for on chip peripherals Input Port Features e Configurable input driver e Configurable pull up pull down devices e Receive data through digital input general purpose input e Alternate input for on chip peripherals e Analog input for ADC module User s Manual 6 1 V1 1 2007 05 Parallel Ports V 1 0 Cinfine on XC886 888CLM Pa
325. eive interrupt occurs also after a frame storage event has been induced by a FIFO or a gateway action The status bits MOSTATn TXPND and MOSTATn RXPND are always set after a successful transmission reception regardless if the respective message interrupt is enabled or not A FIFO full interrupt condition of a message object is provided If bit field MOFCRn OVIE is set the FIFO full interrupt will become activated depending on the actual message object type In case of a Receive FIFO Base Object MOFCRn MMC 0001 the FIFO full interrupt is routed to the interrupt output line CANSRCm as defined by the transmit interrupt node pointer MOIPRn TXINP In case of a Transmit FIFO Base Object MOFCRn MMC 0010 the FIFO full interrupt is routed to the interrupt output line CANSRCm as defined by the receive interrupt node pointer MOIPRn RXINP User s Manual 15 23 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller MOSTATn MOFCRn TXPND RXPND OVIE TXIE RXIE Message n 00015 a transmitted mel TXINP X NP Message n FIFO full Message n Heo 1 S T Rxine gt RXINP received MMC 0001 Message object nis a Receive FIFO Base Object MultiCAN l MMC 0010 Message object n is a Transmit FIFO Base Object UG Ms 9 ES Figure 15 9 Message Interrupt Request Routing User s Manual 15 24 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN
326. eiver Buffer register RB and the Receive Interrupt Request line RIR will be activated If no further transfer is to take place TB is empty CON BSY will be cleared at the same time Software should not modify CON BSY as this flag is hardware controlled Note The SSC starts transmission and sets CON BSY minimum two clock cycles after transmit data is written into TB Therefore it is not recommended to poll CON BSY to indicate the start and end of a single transmission Instead interrupt service routine should be used if interrupts are enabled or the interrupt flags IRCON1 TIR and IRCON1 RIR should be polled if interrupts are disabled Note Only one SSC can be the master at a given time The transfer of serial data bits can be programmed in a number of ways e The data width can be specified from 2 to 8 bits e A transfer may start with either the LSB or the MSB e The shift clock may be idle low or idle high e The data bits may be shifted with the leading edge or the trailing edge of the shift clock signal e The baud rate may be set within a certain range depending on the module clock e The shift clock can be generated MS_CLK or can be received SS_CLK These features allow the SSC to be adapted to a wide range of applications requiring serial data transfer User s Manual 12 32 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces The Data Width Selection supports the transfer of frames of
327. el CC61 Low CCU6_CC61SRH Reset 00y BitFied CC6 amp SH i Capture Compare Shadow Register for Channel CC61 High S CCU6_CC62SRL Reset 00y Bit Field Field a eee Capture Compare Shadow Register for Channel CC62 Low CCU6_CC62SRH Reset 00 4 Bit Field Field 2H Capture Compare Shadow Register RMAP 0 PAGE 1 CCU6_CC63RL Reset 00y Bit Field CC63VL Capture Compare Register for CCU6_CC63RH Reset 00y Bit Field CC63VH Capture Compare Register for CCU6_T12PRL Reset 00y Bit Field T12PVL ee ype wh CCU6_T12PRH Reset 00y Bit Field T12PVH ee SIS tye wm CCU6_T13PRL Reset 00 Bit Field T13PVL ee IOS type tw CCU6_T13PRH Reset 00 Bit Field T13PVH an gt hi Timer T13 Period Register High Type we J o o S Dead Time Control Register for Timer T12 Low CCU6_T12DTCH Reset 00 Dead Time Control Register for Timer T12 High CCU6_TCTROL Reset 00y Timer Control Register 0 Low Bit JER PRE STE Em T13CLK Type EHE n w Bit Field CC60VL Type CCU6_TCTROH Reset 00 4 Timer Control Register 0 High Bit Field y JJ m CCU6_CC60RL Reset 00 Capture Compare Register for Channel CC60 Low Type rh 4 4 lt lt O O iq User s Manual 3 35 Memory Organization V 1 2 lt o_o o_o nN Pi oS on J infine on XC886 888CLM Memory Organization Table 3 12 CCU6 Register Overview cont d ps7 i e s 4 3 2iiajo CCU6_CC60RH Reset 00 Bit
328. eld ens vee Description Pn Up Pull Down Enable at Port 4 Bit n n 0 7 Pull up or Pull down device is disabled Pull up or Pull down device is enabled Note The reset value of P4 PUDEN is package dependent For TQFP 48 the reset value is F4 while for TQFP 64 it is 04 P4 ALTSELn n 0 1 Port 4 Alternate Select Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn Pin Output Functions n 0 7 Configuration of Px_ALTSELO Pn and Px ALTSEL1 Pn for GPIO or alternate settings 00 Normal GPIO 10 Alternate Select 1 01 Alternate Select 2 11 Alternate Select 3 User s Manual 6 45 V1 1 2007 05 Parallel Ports V 1 0 Cinfine on XC886 888CLM Parallel Ports 6 8 Port 5 Port P5 is an 8 bit general purpose bidirectional port The registers of P5 are Summarized in Table 6 13 Note Port 5 is only available in XC 888 Table 6 13 Port 5 Registers Register Short Name Register Full Name P5 DATA Port 5 Data Register P5 DIR Port 5 Direction Register P5 OD Port 5 Open Drain Control Register P5 PUDSEL Port 5 Pull Up Pull Down Select Register P5 PUDEN Port 5 Pull Up Pull Down Enable Register P5 ALTSELO Port 5 Alternate Select Register 0 P5 ALTSEL1 Port 5 Alternate Select Register 1 6 8 1 Functions Port 5 input and output functions are shown in Table 6 14 Table 6 14 Port 5 Input Output Functions Port Pin P5 0 Input GPI ALT1 ALT2 ALT3 Output GPO ALT1 ALT2 ALT 3 Conne
329. election the clock output frequency can further be divided by 2 using toggle latch bit TLEN is set to 1 so that the resulting output frequency has 50 duty cycle In idle mode only the CPU clock CCLK is disabled In power down mode CCLK SCLK FCLK CCLK2 and PCLK are all disabled If slow down mode is enabled the clock to the core and peripherals will be divided by a programmable factor that is selected by the bit field CMCON CLKREL FCCFG FCLK cee MultiCAN Gen Peripherals SCLK i CCLK CORE TLEN Toggle Latch CLKOUT Figure 7 7 Clock Generation from User s Manual 7 16 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management 7 3 4 Register Description OSC_CON OSC Control Register Reset Value 0000 1000 7 6 5 4 3 2 1 0 Tose To oros ee rw rw rw rwh rh r Field OSCR Description Oscillator Run Status Bit This bit shows the state of the oscillator run detection 0 The oscillator is not running 1 The oscillator is running a ORDRES rwh_ Oscillator Run Detection Reset 0 No operation 1 The oscillator run detection logic is reset and restarted This bit will automatically be reset to 0 OSCSS w__ Oscillator Source Select 0 On chip oscillator is selected 1 External oscillator is selected XPD W XTAL Power down Control 0 XTAL is not powered down 1 XTAL is powered down OSCPD W On chip OSC Power down Control
330. ement STEP 2 Wait for an incoming LIN frame from host STEP 3 Synchronize the baud rate to the host STEP 4 Enter for Master Request Frame or for Slave Response Frame The next section Section 12 2 2 2 provides some hints on setting up the microcontroller for baud rate detection of LIN Note Re synchronization and setup of baud rate are always done for every Master Request Header or Slave Response Header LIN frame User s Manual 12 28 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 2 2 2 Baud Rate Detection of LIN The LIN baud rate detection feature provides the capability to detect the baud rate within the LIN protocol using Timer 2 Initialization consists of e Serial port of the microcontroller set to Mode 1 8 bit UART variable baud rate for communication e Provide the baud rate range via bit field BOON BGSEL e Timer 2 is set to capture mode with falling edge trigger at pin T2EX Bit T2MOD EDGESEL is set to 0 by default and bit T2CON CP RL2 is set to 1 e Timer 2 external events are enabled T2CON EXEN 2 is set to 1 EXF2 flag is set when a negative transition occurs at pin T2EX e ft can be configured by bit field T2MOD T2PRE The baud rate detection for LIN is shown in Figure 12 10 the Header LIN frame consists of the e SYN Break 13 bit times low e SYN byte 55 e Protected ID field 1st negative transition T2 automatically Last captured value of T2 E
331. emory Map The XC886 888 product family offers Flash devices with either 24 Kbytes or 32 Kbytes of embedded Flash memory Each Flash device consists of Program Flash P Flash and Data Flash D Flash bank s The 32 Kbyte Flash device consists of 6 P Flash and 2 D Flash banks while the 24 Kbyte Flash device consists of also of 6 P Flash banks but with the upper 2 banks only 2 Kbytes each and only 1 D Flash bank The program memory map for the two Flash sizes is shown in Figure 4 1 D Flash Bank 1 data 4 Kbytes D Flash Bank 0 data D Flash Bank 0 data 4 Kbytes 4 Kbytes D Flash Bank 0 D Flash Bank 0 program 4 Kbytes program 4 Kbytes D Flash Bank 1 program 4 Kbytes P Flash Banks 4 and 5 P Flash Banks 4 and 5 2x 4 Kbytes 2x 2 Kbytes P Flash Banks 2 and 3 P Flash Banks 2 and 3 2x 4 Kbytes 2x 4 Kbytes P Flash Banks 0 and 1 P Flash Banks 0 and 1 2x 4 Kbytes 2x 4 Kbytes 24 Kbytes 32 Kbytes Figure 4 1 Flash Memory Map The P Flash banks in the XC886 888 Flash devices are always grouped in pairs As such the P Flash banks are also sometimes referred to as P Flash bank pair P Flash banks 0 and 1 constitute P Flash bank pair 0 P Flash banks 2 and 3 constitute P Flash bank pair 1 and P Flash banks 4 and 5 constitute P Flash bank pair 2 P Flash occupies program memory address starting from 0000 where the reset and interrupt vectors are located The address range of the P Flash bank pairs are as follows e P
332. ent resets CCPOSO CCPOS 1 CCPOS2 CC6x COUT6y Figure 14 16 Timer T12 Brushless DC Mode all MSEL6x 1000 User s Manual 14 22 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Table 14 1 lists an example of block commutation in BLDC motor control If the input signal combination CCPOSO CCPOS2 changes its state the outputs CC6x and COUT6x are set to their new states Figure 14 17 shows the block commutation in rotate left mode and Figure 14 18 shows the block commutation in rotate right mode These figures are derived directly from Table 14 1 Table 14 1 Block Commutation Control Table CCPOS2 Inputs Outputs Outputs OSO OS1 OS2 60 61 62 Rotate left 1 fo f1 inactive inactive active inactive active inactive 9 phaseshitl4 jo O inactive inactive active active inactive inactive 1 1 0 inactive active inactive active inactive inactive o 1 o inactive active inactive inactive inactive active o 1 1 active inactive inactive inactive inactive active o o 1 _factve inactive inactive inactive active inactive Rotate right 1 f1 f0 active inactive inactive inactive active _ inactive 1 0 o active inactive inactive inactive inactive active 1 o 1 _ inactive active inactive inactive inactive active o o i _ inactive active inactive active inactive inactive o 1 f1 inactive inactive active active inactive inactive o
333. equest Source 20 0 eee 16 11 16 4 4 1 OVON OW 265 eter hee peas BEES as Poe ee Cada ey Bob Ree oe 16 11 16 4 4 2 Request Source Control 0 0 0 es 16 13 16 4 5 Parallel Request Source 0 ee ee es 16 14 16 4 5 1 OVCINICOW a2cieacead ers hacen cider sghuewsa eds er cane ne 16 14 16 4 5 2 Request Source Control 2 0 ce es 16 15 16 4 5 3 External IMIGOC s ases she ee caweds bode oos ceeueatdet anes oe 16 16 16 4 5 4 Software Control 0 0 cc ee eens 16 16 16 4 5 5 AUIOSCAN 4a245545426eesed en an beeee eset errebes taerae 16 16 16 4 6 Wait for Read Mode 0 0 ccc ee eee 16 17 16 4 7 Result Generation n n aana aaaea eee ee eee 16 17 16 4 7 1 OVEIVIEW 22 4ece rand bones eee ses oan beeen heen se bane ees 16 17 16 4 7 2 Limit Checking 0 0 0 ccc eee eens 16 19 16 4 7 3 Data Reduction Filter 0 0 0 00 ccc ees 16 20 16 4 7 4 Result Register View 0 00 eee eee 16 21 16 4 8 Interrupts oice8dduseascnn phedtucesaces pereeunesauns eenes 16 23 16 4 8 1 Event Interrupts 2 0 ccc ees 16 24 16 4 8 2 Channel Interrupts 20 0 0 0c ee eee 16 25 16 4 9 External Trigger Inputs 0 0 ce ees 16 27 16 5 ADC Module Initialization Sequence 0 0 eee ees 16 28 16 6 Register MOD 2 4 eecedegud decd eae eteedand otade eee dans niaaa 16 30 16 7 Register Description 0 eee nee 16 33 16 7 1 General Function Registers 0 00 cece
334. er he valid flag is automatically set when this bit field is set to 0 1 1 more conversion result must be added to obtain the final result in the result register The valid flag is automatically reset when this bit field is set to 1 VF 4 Valid Flag for Result Register x This bit indicates that the contents of the result register x are valid Os The result register x does not contain valid data 1 The result register x contains valid data RESULT 2 0 7 5 Conversion Result This bit field contains the conversion result or the result of the data reduction filter User s Manual 16 55 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter RESRAXH x 0 3 Result Register x View A High CB X 2 Reset Value 00H 7 6 5 4 3 2 1 0 rh Field Description RESULT 10 3 7 rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter User s Manual 16 56 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Writing a 1 to a bit position in register VFCR clears the corresponding valid flag in registers RESRx RESRAx If a hardware event triggers the setting of a bit VFx and VFCx 1 the bit VFx is cleared software overrules hardware VFCR Valid Flag Clear Register CE Reset Value 00 7 6 5 4 3 2 1 0 rea vec wren VED r W W W W Field Description VFCx x 0 ma a Valid Flag for Result Register x No
335. er Request Header or Slave Response Header LIN frame A Header LIN frame consists of the e Synch SYN Break 13 bit times low e Synch SYN byte 55 User s Manual 18 16 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader e Protected Identifier ID field 8C or 7D The Break is used to indicate the beginning of a new frame and it must be at least 13 bits of dominant value When a negative transition is detected at pin T2EX at the beginning of Break the Timer 2 External Start Enable bit T2MOD T2RHEN is set This will then automatically start Timer 2 at the next negative transition of pin T2EX Finally the End of SYN Byte Flag FDCON EOFSYN is polled When this flag is set Timer 2 is stopped The time taken for the transfer 8 bits is captured in the T2 Reload Capture register RC2H L Then the LIN BSL routine calculates the actual baud rate sets the PRE and BG values and activates the Baud Rate Generator The baud rate detection for LIN is shown in Figure 18 2 1st negative transition T2 automatically Last captured value of T2 EOFSYN bit is set set T2RHEN bit Starts upon negative transition T2 is stopped SYN BREAK SYN CHAR 55 01 02 03 Captured Value 8 bits p gt Figure 18 2 LIN Auto Baud Rate Detection for Header LIN Frame 18 1 3 1 Communication Structure The transfer between the PC host and the microcontroller for the 3 phases is shown i
336. er 0 MultiCAN Interrupt CCU6 Interrupt Node Pointer 1 MultiCAN Interrupt CCU6 Interrupt Node Pointer 2 MultiCAN Interrupt CCU6 Interrupt Node Pointer 3 MultiCAN Interrupt User s Manual Interrupt System V 1 0 Level highest 2 3 4 3 6 10 11 12 13 14 9 13 V1 1 2007 05 Cinfin eon XC886 888CLM Interrupt System 5 4 Interrupt Handling The interrupt request signals are sampled at phase 2 in each machine cycle The Sampled requests are then polled during the following machine cycle If one interrupt node request was active at phase 2 of the preceding cycle the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority is already in progress 2 The current polling cycle is not in the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write access to registers IENO IEN1 or IP IPH IP1 IP1H Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IENO IEN1 or IP IPH IP1 IP1H then at least one more instruction will be executed before any
337. er Reset Value 00 7 6 2 4 3 2 1 0 elage ee rw rw rw rwh rw Field Description OPCODE Operation Code 0000 Unsigned 16 bit Multiplication 0001 Unsigned 16 bit 16 bit Division 0010 Unsigned 32 bit 16 bit Division 0011 32 bit Logical Shift L R 0100 Signed 16 bit Multiplication 0101 Signed 16 bit 16 bit Division 0110 Signed 32 bit 16 bit Division 0111 32 bit Arithmetic Shift L R 1000 32 bit Normalize Others Reserved START Start Bit The bit START is set by software and reset by hardware 0 Operation is not started 1 Operation is started RSEL 5 rw Read Select 0 Read the MRx registers 1 Read the MDx registers IR rw Interrupt Routing 0 The two interrupt sources have their own dedicated interrupt lines 1 The two interrupt sources share one interrupt line INT_OO User s Manual 10 11 V1 1 2007 05 MDU V2 1 Cinfin eon XC886 888CLM Multiplication Division Unit Field Bits Type Description IE 7 rw Interrupt Enable 0 The interrupt is disabled 1 The interrupt is enabled Note Write access to MDUCON is not allowed when the busy flag MDUSTAT BSY is set during the calculation phase Note Writing reserved opcode values to MDUCON results in an error condition when MDUCON START bit is set to 1 User s Manual 10 12 V1 1 2007 05 MDU V2 1 Cinfin eon XC886 888CLM Multiplication Division Unit 10 5 3 Status Register Register MDUSTAT contains the status flags of the MDU MDUSTAT MDU Status Register Rese
338. er T12 TAR CCU6_T12_overv Figure 14 2 T12 Overview User s Manual 14 3 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 1 1 1 Timer Configuration Register T12 represents the counting value of timer T12 It can be written only while timer T12 is stopped Write actions while 112 is running are not taken into account Register T12 can always be read by software In edge aligned mode 112 only counts up whereas in center aligned mode 112 can count up and down Timer T12 can be started and stopped by using bit T12R by hardware or software e Bit field T12RSEL defines the event on pin T12HR rising edge falling edge or either of these two edges that can set the run bit T12R by hardware e If bit field T12RSEL 00 the external setting of T12R is disabled and the timer run bit can only be controlled by software Bit T12R is set reset by software by setting bit T12RS or T12RR e In single shot mode bit T12R is reset by hardware according to the function defined by bit T12SSC If bit T12SSC 1 the bit T12R is reset by hardware when 112 reaches its period value in edge aligned mode 112 reaches the value 1 while counting down in center aligned mode Register T12 can be reset to zero by setting bit T12RES Setting of T12RES has no impact on run bit T12R 14 1 1 2 Counting Rules With reference to the T12 input clock the counting sequence is defined by the following counting rules
339. er disabled Baud rate Deviation Error QBRPRE BR_VALUE 1 19 2 kBaud 1 BRPRE 000 0 17 4800 Baud 2 BRPRE 001 0 17 The fractional divider allows baud rates of higher accuracy lower deviation error to be generated Table 12 3 lists the resulting deviation errors from generating a baud rate of 115 2 kHz using different module clock frequencies The fractional divider is enabled fractional divider mode and the corresponding parameter settings are shown User s Manual 12 13 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces Table 12 3 Deviation Error for UART with Fractional Divider enabled QBRPRE BR_VALUE 1 Error 26 67 MHz 10 An 0 03 24 MHz 10 An 0 20 16 MHz 8 8 0 03 13 33 MHz 7 12 MHz 0 03 O W N I EN CO TI CO L La a O o 8 MHz 6 67 MHz 6 MHz Fractional Divider The input clock fp to the 8 bit fractional divider is scaled either by a factor of 1 n or n 256 to generate an output clock fuon for the baud rate timer The fractional divider has two operating modes e Fractional divider mode e Normal divider mode Fractional Divider Mode The fractional divider mode Is selected by clearing bit FDM in register FDCON to 0 Once the fractional divider is enabled FDEN 1 the output clock fyop of the fractional divider is derived from scaling its input clock f 5 by a factor of n 256 where n is defined by bit field S
340. er to indicate that a programmed time interval has elapsed The set is only generated when bit CC6xST is reset a reset can only take place when the bit is set Thus the events triggering the set and reset actions of the CC6xST bit must be combined This OR combination of the resulting set and reset permits the reload of the dead time counter to be triggered see Figure 14 6 This is triggered only if bit CC6xST is changed permitting a correct PWM generation with dead time and the complete duty cycle range of 0 to 100 in edge aligned and center aligned modes 14 1 1 5 Duty Cycle of 0 and 100 These counting and switching rules ensure a PWM functionality in the full range between 0 and 100 duty cycle duty cycle active time total PWM period In order to obtain a duty cycle of 0 compare state never active a compare value of T12P 1 must be programmed for both compare modes A compare value of 0 will lead to a duty cycle of 100 compare state always active 14 1 1 6 Dead time Generation In most cases the switching behavior of the connected power switches is not symmetrical with respect to the times needed to switch on and to switch off A general problem arises if the time taken to switch on is less than the time to switch off the power device This leads to a short circuit in the inverter bridge leg which may damage the entire system In order to solve this problem by hardware the CCU6 contains a programmable dead time counter
341. ermine the 4 bytes data to be sent to the host Only option 00 is available to return the chip identification number which is used to identify the particular device variant 00 Chip Identification Number MSB byte 1 LSB byte 4 In Mode A the header block is the only transfer block to be sent by the host The microcontroller will return an acknowledgement followed by 4 bytes of data to the host if the header block is received successfully If an invalid option is received the microcontroller will return 4 bytes of 00 User s Manual 18 15 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader 18 1 3 Bootstrap Loader via LIN Standard LIN protocol can support a maximum baud rate of 20 KHz However the XC886 888L device has an enhanced feature which supports a baud rate of up to 115 2 kHz LIN BSL is implemented to support the baud rate of 20 KHz and below using standard LIN protocol while Fast LIN BSL is introduced to support the baud rate of 20kHz to 115 2kHz via a single wire UART using UART protocol See Section 18 1 3 9 LIN BSL supports Fast Programming through Mode 0 Mode 2 or Mode 8 with the selection of Fast Programming Option Refer to Section 18 1 3 3 for more details Features of LIN BSL are e Re synchronization of the transfer speed baud rate of the communication partner upon receiving every LIN frame e Use of Diagnostic Frame Master Request and Slave Response e User preloade
342. ernal Interrupt 4 External Interrupt5 External Interrupt5 5 External Interrupt6 External Interrupt6 6 MultiCAN Node3 Node 3 was alan MultiCAN Node 4 MultiCAN Node 6 OO6B CCU6 INP3 ECCIP3 MultiCAN Node7 Node 7 9 12 V1 1 2007 05 Interrupt System V 1 0 Cinfineon 5 3 Interrupt Priority XC886 888CLM Interrupt System An interrupt that is currently being serviced can only be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority Hence an interrupt of the highest priority cannot be interrupted by any other interrupt request lf two or more requests of different priority levels are received simultaneously the request with the highest priority is serviced first If requests of the same priority are received simultaneously an internal polling sequence determines which request is serviced first Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 5 2 Table 5 2 Priority Structure within Interrupt Level Source Non Maskable Interrupt NMI External Interrupt 0 Timer O Interrupt External Interrupt 1 Timer 1 Interrupt UART Interrupt Timer 2 UVART Normal Divider Overflow LIN MultiCAN Interrupt ADC MultiCAN Interrupt SSC Interrupt External Interrupt 2 Timer 21 UART1 UART1 Normal Divider Overflow CORDIC MDU Interrupt External Interrupt 6 3 MultiCAN CCU6 Interrupt Node Point
343. errupts This bit field defines the interrupt output line which is activated due to a set condition for bit T12OM if enabled by bit ENT12OM or for bit T12PM if enabled by bit ENT12PM 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected INPT13 Interrupt Node Pointer for Timer T13 Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit T13CM if enabled by bit ENT13CM or for bit T13PM if enabled by bit ENT13PM 00 Interrupt output line SRO is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected 0 7 6 r Reserved Returns 0 if read should be written with 0 User s Manual 14 92 V1 1 2007 05 CCU6B V 1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller 15 Controller Area Network MultiCAN Controller The MultiCAN module contains 2 Full CAN nodes operating independently or exchanging data and remote frames via a gateway function Transmission and reception of CAN frames is handled in accordance to CAN specification V2 0 B active Each CAN node can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers Two CAN nodes share a common set of message objects Each message object can be individually a
344. ert a new message object behind a given destination object The new object is taken from the list of unallocated elements the first element is chosen The number of the new object is delivered as result to PANAR1 An ERR bit bit 7 of PANAR2 reports the success of the operation 0 SUCCESS 1 The operation has not been performed because the list of unallocated elements was empty User s Manual MultiCAN V1 0 V1 1 2007 05 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller The Module Control Register MCR contains basic settings that define the operation of the MultiCAN module MCR Module Control Register Reset Value 0000 0000 31 30 29 28 2 26 25 24 23 22 21 20 19 18 17 16 Field Description MPSEL La 5 12 Message Pending Selector Bit field MPSEL allows the bit position of the message pending bit to be selected after a message reception transmission by a mixture of the MOIPRn register bit fields RXINP TXINP and MPN Selection details are given in Figure 15 10 on Page 15 25 0 31 16 Reserved 11 0 Read as 0 should be written with 0 User s Manual 15 52 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller The Interrupt Trigger Register ITR allows interrupt requests to be triggered on each interrupt output line by software MITR Module Interrupt Trigger Register Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 1
345. es pin T2 over 2 PCLK cycles If a 1 was detected during the first clock and a O was detected in the following clock then the counter increments by one Therefore the input levels should be stable for at least 1 clock If bit T2RHEN is set Timer 2 can be started by the falling edge rising edge on pin T2EX which is defined by bit T2REGS Note The C501 compatible feature requires a count resolution of at least 24 clocks User s Manual 13 19 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 2 5 External Interrupt Function While the timer counter function is disabled TR2 0 it is still possible to generate a Timer 2 interrupt to the core via an external event at T2EX as long as Timer 2 remains enabled PMCON1 T2_DIS 0 To achieve this bit EXEN2 in register T2CON must be set As a result any transition on T2EX will cause either a dummy reload or a dummy capture depending on the CP RL2 bit selection By disabling the timer counter function T2EX can be alternatively used to provide an edge triggered rising or falling external interrupt function with bit EXF2 serving as the external interrupt flag 13 2 6 Port Control When functioning as an event counter Timer 2 and Timer 21 count 1 to 0 transitions at their external input pins T2 and T21 which can be selected from two different sources T2_0 and T2_1 for Timer 2 and T21_0 and 1721_1 for Timer 21 This selection is performed by the SFR bits MODPISEL2 T2I
346. es selectable Refer to the following register description for the selection Table 14 5 Double Register Capture Modes Description 0100 The contents of T12 are stored in CC6nR after a rising edge and in CC6nSR after a falling edge on the input pin CC6n 0101 The value stored in CC6nSR is copied to CC6nR after a rising edge on the input pin CC6n The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR This feature is useful for time measurements between consecutive rising edges on pins CC6n COUTEn is I O User s Manual 14 40 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Table 14 5 Double Register Capture Modes cont d Description 0110 The value stored in CC6nSR is copied to CC6nR after a falling edge on the input pin CC6n The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR This feature is useful for time measurements between consecutive falling edges on pins CC6n COUTEn is I O 0111 The value stored in CC6nSR is copied to CC6nR after any edge on the input pin CC6n The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR This feature is useful for time measurements between consecutive edges on pins CC6n COUTEn is I O Table 14 6 Combined T12 Modes Description 1000 Hall Sensor mode Capture mode for channel 0 compare mode for channels 1 and 2 The contents of T12 are captured into CC60 at a valid hall
347. espectively for different oscillator inputs The output frequency must always be configured for 96 MHz Table 7 6 shows the VCO ranges in the XC886 888 ee d Table 7 6 VCO Ranges VCOSEL Unit mo soft M The VCO range can be selected by bit VCOSEL For fsys 96 MHz and K 2 fig Ssys 2 192 MHz VCOSEL must be selected to be 0 7 3 3 Clock Management The Clock Management sub module generates all clock signals required within the microcontroller from the basic clock It consists of e Basic clock slow down circuitry e Centralized enable disable circuit for clock control Figure 7 7 shows the clock generation from the system frequency f mode the typical frequencies of different modules are as follows e CPU clock CCLK SCLK 24 MHz e Fast clock FOLK 24 or 48 MHz e Peripheral clock PCLK 24 MHz e Flash Interface clock CCLK2 48 MHz and CCLK 24 MHz For the XC886 888 FCLK is used to clock the MultiCAN at 24 MHz or 48 MHz clock The selection of the clock frequency is done via bit CMCON FCCFG sys IN normal running User s Manual 7 15 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management Furthermore a clock output CLKOUT is available on pin P 0 0 or 0 7 as an alternate output If bit COUTS 0 the output clock is from oscillator output frequency if bit COUTS 1 the clock output frequency is chosen by the bit field COREL Under this s
348. ess The register bits Vn n 3 0 has no effect on the read process During the read process 32 bit data will be read from the MultiCAN kernel The register bit CAN ADCON BSY is used to indicate if the transmission is complete or not When the BSY register bit is set the data registers and address registers will not accept any read write access The write read action to the MultiCAN kernel only takes place when writing the CAN _ADCON register The write read action to the MultiCAN kernel is defined by the bit CAN ADCON RWEN Reading the CAN _ADCON register has no effect on write read data to from the MultiCAN kernel Each write read action to the MultiCAN kernel only writes reads data once Furthermore there is an additional functionality for auto increment decrement the address by configuring the bit field CAN ADCON AUAD The address can be auto incremented decremented by 1 or auto incremented by 8 which is useful when programming the message objects If this function is enabled after a read write process is finished the address pointer will automatically point to the next register address The address registers CAN ADL and CAN_ADH also reflect the address that the address pointer pointed to The next read write action to the next register can be taken immediately without writing the address to the registers CAN_ADL and CAN_ADH again Write Process to the MultiCAN Kernel e Write the address of the MultiCAN kernel register to the CAN ADL an
349. ess ji eee Select Bit Slave mode Operate on shift clock received via SCLK Master mode Generate shift clock and output it via SCLK EN Enable Bit 1 Transmission and reception enabled Access to status flags and Master Slave control Reserved Returns 0 if read should be written with 0 Note The target of an access to CON control bits or flags is determined by the state of CON EN prior to the access that is writing CO57 to CON in programming mode CON EN 0 will initialize the SSC CON EN was 0 and then turn it on CON EN 1 When writing to CON ensure that reserved locations receive zeros User s Manual 12 49 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 3 5 3 Baud Rate Timer Reload Register The SSC baud rate timer reload register BR contains the 16 bit reload value for the baud rate timer BRL Baud Rate Timer Reload Register Low Reset Value 00 7 6 5 4 3 2 1 0 BR VALUE rw Field Description BR_VALUE C 0 Baud Rate Timer Reload Register Value 7 0 Reading BR returns the 16 bit contents of the baud rate timer Writing to BR loads the baud rate timer reload register with BR_VALUE BRH Baud Rate Timer Reload Register High Reset Value 00 7 6 3 4 3 2 1 0 rw Field Description BR_VALUE CC 0 Baud Rate Timer Reload Register Value 15 8 Reading BR returns the 16 bit contents of the baud rate timer Writing to BR loads the baud rate timer reload register wi
350. essage object for frame reception A message object can receive CAN messages from the CAN bus only if RXEN 1 The MultiCAN module evaluates RXEN only during receive acceptance filtering After receive acceptance filtering RXEN is ignored and has no further influence on the actual storage of a received message in a message object Bit RXEN enables the soft phase out of a message object after clearing RXEN a currently received CAN message for which the message object has won acceptance filtering is still stored in the message object but for subsequent messages the message object no longer wins receive acceptance filtering RXUPD NEWDAT and MSGLST An ongoing frame storage process is indicated by the bit MOSTATn RXUPD Receive Updating RXUPD is set with the start and cleared with the end of a message object update which consists of frame storage as well as flag updates After storing the received frame identifier IDE bit DLC and the data field for data frames as well the bit MOSTATn NEWDAT New Data is set If NEWDAT was already set before it becomes set again bit MOSTATn MSGLST Message Lost is set to indicate a data loss condition The RXUPD and NEWDAT flags can help to read consistent frame data from the message object during an ongoing CAN operation The following steps are recommended to be executed 1 Clear NEWDAT bit 2 Read message content identifier data etc from the message object 3 Ch
351. essor operating mode and the application data The MPS setting has no effect on the Z data For circular and hyperbolic functions any value of Z outside of the range 7 2 1 2 x cannot be represented and will result in Z data overflow error Note that kernel data Z has values in the range 2 2 9 1 2 z scaled to the range 2 2 1 so the written and read values of Z data are always normalized as such For linear function where Z is a real value magnitude of Z must not exceed 4 integer bits 11 2 5 CORDIC Coprocessor Data Format The CORDIC Coprocessor accepts initial data X Y and Z inputs in twos complement format The result data is also in twos complement format The only exception is for the X result data in circular vectoring mode The X result data has a default data format of twos complement but the user can select via bit CD_CON X_USIGN 1 for the X result data to be read as unsigned value This option prevents a potential overflow of the X result data taken together with the MPS setting as the MSB bit is now a data bit Note that setting bit X_USIGN 1 is only effective when operating in the circular vectoring mode which always yields result data that is positive and larger than the initial data Generally the input data for X and Y can be integer or rational number fraction However in any calculation the data form must be the same for both X and Y Also in case of fraction X and Y must have the
352. evices for serial communication one device must be selected for master operation while all other devices must be programmed for slave operation 12 3 1 2 Full Duplex Operation The various devices are connected through three lines The definition of these lines is always determined by the master the line connected to the master s data output line User s Manual 12 33 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces TXD is the transmit line the receive line is connected to its data input line RXD the shift clock line is either MS_CLK or SS_CLK Only the device selected for master operation generates and outputs the shift clock on line MS_CLK Since all slaves receive this clock their pin SCLK must be switched to input mode The external connections are hard wired and the function and direction of these pins are determined by the master or Slave operation of the individual device Master Device 1 Device 2 Shift Register Shift Register Figure 12 13 SSC Full Duplex Configuration The data output pins MRST of all slave devices are connected together onto the single receive line in the configuration shown in Figure 12 13 During a transfer each slave shifts out data from its shift register There are two ways to avoid collisions on the receive line due to different slave data e Only one slave drives the line i e enables the driver of its MRST pin All the other slaves must have their MRST pi
353. f Capture Compare channel 0 P4 1 46 60 Hi Z TXDCO 3 MultiCAN Node 0 Transmitter Output COUT60_1 Output of Capture Compare channel 0 P4 2 61 PU EXINT6_1 External Interrupt Input 6 T21_0 Timer 21 Input P4 3 32 40 Hi Z EXF21_1 Timer 21 External Flag Output COUT63_ 2 Output of Capture Compare channel 3 P4 4 45 CCPOSO 3 CCU6 Hall Input 0 TO O Timer O Input CC61_ 4 Output of Capture Compare channel 1 P4 5 46 Hi Z CCPOS1_3 CCU6 Hall Input 1 T1_0 Timer 1 Input COUT61_2 Output of Capture Compare channel 1 P4 6 47 Hi Z CCPOS2_3 CCU6 Hall Input 2 T2_0 Timer 2 Input CC62 2 Output of Capture Compare channel 2 P4 7 48 Hi Z CTRAP_3 CCU6 Trap Input COUT62 2 Output of Capture Compare channel 2 User s Manual 1 15 V1 1 2007 05 Introduction V 1 1 Cinfineon Table 1 3 Symbol Pin Number Type Reset Function TQFP 48 64 State P5 0 P5 1 P5 2 P5 3 P5 4 P5 5 P5 6 Pow fe wo 3 a mo fo er Pu aa i wef Pe ae e User s Manual Introduction V 1 1 Port 5 XC886 888CLM Introduction Pin Definitions and Functions contd Port 5 is an 8 bit bidirectional general purpose I O port It can be used as alternate functions for UART UART1 and JTAG PU EXINT1 1 EXINT2 1 RXD_2 TXD_2 RXDO_2 TDO 2 TXD1_2 TCK_2 RXDO1_ 2 TDL 2 RXD1_ 2 External Interrupt Input 1 External Interrupt Input 2 UART Receive Data Input UART Transmit Data Output Clock Output UART Trans
354. feature is available only for Flash devices 3 4 1 Flash Memory Protection As long as a valid password is available all external access to the device including the Flash will be blocked For additional security the Flash hardware protection can be enabled to implement a second layer of read out protection as well as to enable program and erase protection Flash hardware protection is available only for Flash devices and comes in two modes e Mode 0 Only the P Flash is protected the D Flash is unprotected e Mode 1 Both the P Flash and D Flash are protected The selection of each protection mode and the restrictions imposed are summarized in Table 3 1 Table 3 1 Flash Protection Modes Flash Protection Without hardware With hardware protection protection Hardware 1 Protection Mode Activation Program a valid password via BSL mode 6 Selection Bit 4 of password 0 Bit 4 of password 1 Bit 4 of password 1 MSB of password 0 MSB of password 1 P Flash Read instructions in Read instructions in Read instructions in contents can be any program memory the P Flash the P Flash or D read by Flash External access Not possible Not possible Not possible to P Flash P Flash program Possible Not possible Not possible and erase User s Manual 3 6 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization Table 3 1 Flash Protection Modes cont d Flash Protection
355. for the CC60 capture input signal 00 The input pin for CC60_0 01 Reserved 10 Reserved 11 Reserved ISCC61 Input Select for CC61 This bit field defines the port pin that is used for the CC61 capture input signal 00 The input pin for CC61_0 01 Reserved 10 Reserved 11 Reserved ISCC62 Input Select for CC62 This bit field defines the port pin that is used for the CC62 capture input signal 00 The input pin for CC62_0 01 Reserved 10 Reserved 11 Reserved ISTRP Input Select for CTRAP This bit field defines the port pin that is used for the CTRAP input signal 00 The input pin for CTRAP_O 01 The input pin for CTRAP_1 10 The input pin for CTRAP 2 11 The input pin for CTRAP_3 PISELOH Port Input Select Register 0 High Reset Value 00 7 6 5 4 3 2 1 0 Oom re eee rw rw rw rw User s Manual 14 38 V1 1 2007 05 CCU6 V 1 0 Cinfine on XC886 888CLM Capture Compare Unit 6 Field Description ISPOSO Input Select for CCPOSO This bit field defines the port pin that is used for the CCPOS0O input signal 00 The input pin for CCPOSO_O 01 The input pin for CCPOSO 1 10 The input pin for CCPOSO 2 11 The input pin for CCPOSO_ 3 T ISPOS1 2 Input Select for CCPOS1 This bit field defines the port pin that is used for the CCPOS1 input signal 00 The input pin for CCPOS1_0 01 The input pin for CCPOS1_1 10 The input pin for CCPOS1_2 11 The input pin for CCPOS1_3 ISPOS2 Input Select for CCPOS2 This bit field defines
356. g User s Manual 11 17 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfin eon XC886 888CLM CORDIC Coprocessor 11 6 2 Status and Data Control Register The CD_STATC register is bit addressable and generally reflects the status of the CORDIC Coprocessor The register also contain bits for data control as well as for interrupt control CD_STATC CORDIC Status and Data Control Register Reset Value 00 7 6 5 4 3 2 1 0 ee tr Je omne Tomt ee T omon T oor rw rw rw rw rw rwh rh rh Field Bits Type Description BSY rh Busy Indication Indicates a running calculation when set The flag is asserted one clock cycle after bit ST was set It is deasserted at the end of a calculation ERROR 1 rh Error Indication In case of overflow error in the calculated result for X Y or Z this bit is set at the end of CORDIC calculation Cleared after any read access on this register or when a new CORDIC calculation is started EOC 2 rwh_ End of Calculation Flag Set at the end of a complete CORDIC calculation when BSY goes inactive Unless cleared by software bit remains set until a read access is performed to the low byte of Z result data DMAP 0 where the bit is automatically cleared by hardware INT EN 3 rw Interrupt Enable Set to enable CORDIC Coprocessor interrupt DMAP 4 rw Data Map 0 Read result data from kernel data registers default 1 Read initial data from the shadow data registers User s Manual 11 18 V1 1
357. g Timer Reload Value for the high byte of WDT A new reload value can be written to WOTREL and this value is loaded to the upper 8 bits of the WDT upon the enabling of the timer or the next service for refresh User s Manual 9 5 V1 1 2007 05 Watchdog Timer V1 0 Cinfine on XC886 888CLM Watchdog Timer WDTCON Watchdog Timer Register Reset Value 00 7 6 5 4 3 2 1 0 8 winsen wore o woten worRS worn r rw rh r rw rwh rw Field Description WDTIN Watchdog Timer Input Frequency Selection 0 Input frequency is foo 2 1 Input frequency Is foo 128 WDTRS WDT Refresh Start Active high Set to start refresh operation on the watchdog timer Cleared by hardware automatically WDT Enable WDTEN is a protected bit If the Protection Scheme see Chapter 3 5 4 1 is activated then this bit cannot be written directly 0 WDT is disabled 1 WDT is enabled Watchdog Prewarning Mode Flag This bit is set to 1 when a Watchdog error is detected The Watchdog Timer has issued an NMI trap and is in Prewarning Mode A reset of the chip WDTEN WDTPR occurs after the prewarning period has expired 0 Normal mode default after reset 1 The Watchdog is operating in Prewarning Mode Watchdog Window Boundary Enable 0 Watchdog Window Boundary feature is disabled default 1 Watchdog Window Boundary feature is enabled WINBEN Reserved Returns 0 if read should be written with 0 User s Manual 9 6 V1 1 2007 05
358. g from the passive state to the active state of the selected outputs The switching from the active state to the passive state is not delayed T12DTCH Dead Time Control Register for Timer T12 High Reset Value 00 7 6 5 4 3 2 1 0 Er DTR2 DTR1 DTRO Er DTE2 DTE1 DTEO r rh rh rh r rw rw rw Field Bits Type Description DTEx 2 0 rw Dead Time Enable Bits x 0 1 2 Bits DTEO DTE2 enable and disable the dead time generation for each compare channel 0 1 2 of timer T12 0 Dead time generation is disabled The corresponding outputs switch from the passive State to the active state according to the actual compare status without any delay Dead time generation is enabled The corresponding outputs switch from the passive State to the active state according to the compare status with the delay programmed in bit field DTM User s Manual 14 50 V1 1 2007 05 CCU6B V 1 0 h Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Bits Type Description DTRx 6 4 rh Dead Time Run Indication Bits x 0 1 2 Bits DIRO DTR2 indicate the status of the dead time generation for each compare channel 0 1 2 of timer T12 0 The value of the corresponding dead time counter channel is 0 1 The value of the corresponding dead time counter channel is not 0 0 3 7 Ir Reserved Returns 0 if read should be written with 0 Note The dead time counters are clocked with the same frequency as T12 This structure allows symmetri
359. gardless of whether X and Y are integers or rational numbers The only difference is with regards to interpreting the input and result data i e with no decimal place or how many decimal places The deviation of the CORDIC result from the expected data is never smaller if X and Y are integers instead of rational numbers Therefore wherever possible assign X and Y as rational numbers with carefully selected decimal place point which could be based on the maximum ND of that mode User s Manual 11 9 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfineon Table 11 3 Mode Circular Vectoring Circular Rotation Linear Vectoring Linear Rotation Hyperbolic Vectoring User s Manual XC886 888CLM CORDIC Coprocessor Normalized Deviation of a Calculation X Normalized Deviation Y or Z Normalized Deviation Input conditions Useful Domain and 1 64676 2 sqrt X Y7 gt 600 0 50 8317 1 49 1683 0 55 8702 1 44 1298 ND for X lt 1 ND for Z lt 1 Input conditions Useful Domain Full range of X Y and Z 50 7715 0 51 2011 48 8579 1 48 4944 0 3681 2 0 3024 0 0023 3 0 0020 4 0 0002 4 0 0001 ND for X lt 4 ND for Y lt 4 Input conditions Useful Domain Y X lt 2 X gt 0 O 66 9170 0 88 56 7 6 1 33 0830 1 11 4322 ND for X lt 1 2 0 0002 ND for Z lt 2 Input conditions Useful Domain Z lt 2 0 69 7141 0 62 4055
360. ge Flag x 0 1 2 4 In compare mode a compare match has been detected while T12 was counting up In capture mode a rising edge has been detected at the input CC6x 0 The event has not yet occurred since this bit has been reset for the last time 1 The event described above has been detected User s Manual 14 79 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Description ICC6xF ie rh Capture Compare Match Falling Edge Flag x 0 1 2 In compare mode a compare match has been detected while 112 was counting down In capture mode a falling edge has been detected at the input CC6x 0 The event has not yet occurred since this bit has been reset for the last time 1 The event described above has been detected T120M Timer T12 One Match Flag 0 A timer 112 one match while counting down has not yet been detected since this bit has been reset for the last time A timer 112 one match while counting down has been detected T12PM 7 rh Timer T12 Period Match Flag 0 A timer T12 period match while counting up has not yet been detected since this bit has been reset for the last time A timer T12 period match while counting up has been detected h as ISH Capture Compare Interrupt Status Register High Reset Value 00 7 6 9 4 3 2 1 0 TRP TRP T13 T13 rh rh rh rh rh rh rh rh Field Description T13CM pis tr aaa T13 Compare Match Flag A timer T13 compare match has not yet been
361. gger Control Flag 0 Low level triggered external interrupt 1 is selected 1 Falling edge triggered external interrupt 1 is selected User s Manual 5 24 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System 5 6 3 Interrupt Flag Registers The interrupt flags for the different interrupt sources are located in several Special Function Registers SFRs In case of software and hardware access to a flag bit at the same time hardware will have higher priority IRCONO Interrupt Request Register 0 Reset Value 00 7 6 5 4 3 2 1 0 Er EXINT6 EXINT5 EXINT4 EXINT3 EXINT2 EXINT1 EXINTO r rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description EXINTx 1 0 rwh_ Interrupt Flag for External Interrupt 0 1 x 0 1 This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred These bits are set by corresponding active edge event i e falling rising both These flags are dummy and has no effect on the respective interrupt signal to core Instead the corresponding TCON flag is the interrupt request to the core it is sufficient to poll and clear the TCON flag EXINTy 6 2 rwh Interrupt Flag for External Interrupt y y 2 6 This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred Reserved Returns 0 if read should be written with 0 IRCON1 Interrup
362. gh Bit for Interrupt Node XINTRO PTOH 1 rw___ Priority Level High Bit for Interrupt Node XINTR1 PX1H 2 rw__ Priority Level High Bit for Interrupt Node XINTR2 PT1H Priority Level High Bit for Interrupt Node XINTR3 PSH 4 irw Priority Level High Bit for Interrupt Node XINTR4 O1 PT2H a_i Priority Level High Bit for Interrupt Node XINTR5 6 Reserved Returns 0 if read should be written with 0 N IP1 Interrupt Priority 1 Register Reset Value 00 7 6 5 4 3 2 1 0 PCCIP3 PCCIP2 PCCIPI PCCIPO PSSC PADC rw rw rw rw rw rw rw rw Field Bits Type Description PADC O rw___ Priority Level Low Bit for Interrupt Node XINTR6 Priority Level Low Bit for Interrupt Node XINTR7 rw Priority Level Low Bit for Interrupt Node XINTR8 PXM 3 jw Priority Level Low Bit for Interrupt Node XINTR9 rw Priority Level Low Bit for Interrupt Node XINTR10 Priority Level Low Bit for Interrupt Node XINTR11 Priority Level Low Bit for Interrupt Node XINTR12 v gt L N T Q O O a User s Manual 5 33 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System Field Bits Type Description PCCIP3 Priority Level Low Bit for Interrupt Node XINTR13 IPH1 Interrupt Priority 1 High Register Reset Value 00 7 6 5 4 3 2 1 0 PCCIP3H PCCIP2H PCCIP1H PCCIPOH PXMH PX2H PSSCH PADCH rw rw rw rw rw rw rw rw Field Bits Type Description PADCH o rw___ Priority Level High Bit for Interrupt Node XINTR
363. gram width otherwise the previous values stored in the write buffers will remain and be programmed into the WL For the P Flash banks a programmed WL must be erased before it can be reprogrammed again as the Flash cells can only withstand one gate disturb This means that the entire sector containing the WL must be erased since it is impossible to erase a single WL For the D Flash bank the same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs This means if the number of data bytes that need to be written is smaller than the 32 bytes minimum programming width the user can opt to program this number of data bytes x where x can be any integer from 1 to 31 first and program the remaining bytes 32 x later However since the minimum programming width of D Flash is always 32 bytes the bytes that are unused in each programming cycle must be written with all zeros Figure 4 7 shows an example of programming the same wordline twice with 16 bytes of data In the first program cycle the lower 16 bytes are written with valid data while the upper 16 bytes that do not contain meaningful data are written with all zeros In the second program cycle it will be opposite as now only the upper 16 bytes can be written with valid data and the lower 16 bytes which already contain meaningful data must be written with all zeros User s Manual 4 9 V1 1 2007 05 Flash Memory V 1 0 Infineon
364. gt gt gt Tm F 4 4 44 P User s Manual 6 48 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Table 6 14 Port 5 Input Output Functions cont d Port Pin Input Output P5 7 Input GPI ALT1 ALT2 ALT3 Output GPO P5_DATA P7 ALT1 ALT2 ALT3 Connected Signal s From to Module P5 DATA P7 TDI 2 JTAG RXD1_2 UART1 User s Manual 6 49 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 8 2 Register Description P5 DATA Port 5 Data Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field mS Description Pn Ad 5 Pin n Data Value n 0 7 Port 5 pin n data value O default Port 5 pin n data value 1 P5 DIR Port 5 Direction Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn 5 Pin n Direction Control n 0 7 Direction is set to input default Direction is set to output User s Manual 6 50 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports P5 OD Port 5 Open Drain Control Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn H 5 Pin n Open Drain Mode n 0 7 Normal mode output is actively driven for 0 and 1 states default Open drain mode output is actively driven only for O state P5_PUDSEL Port 5 Pull Up Pull Down Select Register Reset Value FF 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw
365. gure 16 15 User s Manual 16 25 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter rh rw 2 w rh rw channel number Figure 16 15 Channel Interrupt Routing User s Manual 16 26 V1 1 2007 05 ADC V 1 0 Cinfine on XC886 888CLM Analog to Digital Converter 16 4 9 External Trigger Inputs The sequential and parallel request sources has one request trigger input REQTRx x 0 1 each through which a conversion request can be started The input to REQTRx is selected from eight external trigger inputs ETRx0 to ETRx7 via a multiplexer depending on bit field ETRSELx It is possible to bypass the synchronization stages for external trigger requests that come synchronous to ADC This selection is done via bit SYNENx Refer to Section 16 7 9 for description of the external trigger control registers rising edge REQTRx detect syn stages SYNENx Figure 16 16 External Trigger Input The external trigger inputs to the ADC module are driven by events occuring in the CCU6 module See Table 16 2 Table 16 2 External Trigger Input Source External Trigger Input CCU6 Event ETRx0 T13 period match ETRx1 T13 compare match ETRx2 T12 period match ETRx3 T12 compare match for channel 0 ETRx4 T12 compare match for channel 1 ETRx5 T12 compare match for channel 2 ETRx6 Shadow transfer event for multi channel mode ETRx7 Correct hall event for multi channel mode User s Manual 16 27 V1 1
366. h or ROM ees 24K 32K x 8 On Chip Debug Support UART 8 bit Digital I O Boot ROM Capture Compare Unit TPR XC800 Core XRAM Compare Unit Port 2 8 bit Digital 1 5K x 8 16 bit Analog Input ADC RAM Timer O Timer 1 Timer 2 Watchdog l TEE 10 bit Port 3 8 bit Digital I O 256 x 8 16 bit 16 bit 16 bit Timer A co CORDIC MultiCAN ieee UARTI Port 5 Port 4 8 bit Digital I O Improved functionality in comparison to the XC866 bit Digital 1 All ROM devices come with an additional 4K x 8 Flash 8 bit Digital VO Figure 1 1 XC886 888 Functional Units The XC886 888 product family features devices with different configurations program memory sizes package options temperature and quality profiles Automotive or Industrial to offer cost effective solutions for different application requirements The list of XC886 888 device configurations are summarized in Table 1 1 For each configuration 2 types of packages are available e TQFP 48 which is denoted by XC886 and e TQFP 64 which is denoted by XC888 Table 1 1 Device Configuration Module Support Module XC886 888CLM Yes Yes User s Manual 1 2 V1 1 2007 05 Introduction V 1 1 Cinfine on XC886 888CLM Introduction From these 10 different combinations of configuration and package type each are further made available in many sales types which are grouped according to device type pr
367. has occurred CANSRC5 Interrupt Flag 5 for MultiCAN This bit is set by hardware and can only be cleared by software Interrupt event has not occurred Interrupt event has occurred 0 7 6 Reserved 3 2 Returns 0 if read should be written with 0 IRCON4 Interrupt Request Register 4 Reset Value 00 7 6 5 4 3 2 1 0 r rwh rwh r rwh rwh Field Bits Type Description CCU6SR2 rwh_ Interrupt Flag 2 for CCU6 This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred CANSRC6 1 rwh Interrupt Flag 6 for MultiCAN This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred Users Manual 5 28 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System Field Description CCU6SR3 Interrupt Flag 3 for CCU6 This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred CANSRC7 Interrupt Flag 7 for MultiCAN This bit is set by hardware and can only be cleared by software A Interrupt event has not occurred Interrupt event has occurred 0 7 6 Reserved 3 2 Returns 0 if read should be written with 0 TCON Timer Control Register Reset Value 00 7 6 5 4 3 2 1 0 mom mwm e om eo rwh rw rwh rw rwh rw rwh rw Field Bits Type Description IEO 1 rwh External Interrupt 0 Flag
368. hat use the stack automatically pre increment or post decrement the stack pointer so that the stack pointer always points to the last byte written to the stack i e the top of the stack On reset the SP is reset to 07 This causes the stack to begin at a location 08 above register bank zero The SP can be read or written under software control 2 2 2 Data Pointer DPTR The Data Pointer DPTR is stored in registers DPL Data Pointer Low byte and DPH Data Pointer High byte to form 16 bit addresses for External Data Memory accesses MOVX AY DPTR and MOVX DPITR A for program byte moves MOVC A A DPTR and for indirect program jumps JMP A DPTR Two true 16 bit operations are allowed on the Data Pointer load immediate MOV DPTR data and increment INC DPTR 2 2 3 Accumulator ACC This register provides one of the operands for most ALU operations 2 2 4 B Register The B register is used during multiply and divide operations to provide the second operand For other instructions it can be treated as another scratch pad register User s Manual 2 3 V1 1 2007 05 Processor Architecture V 1 0 Cinfin eon XC886 888CLM Processor Architecture 2 2 5 Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU PSW Program Status Word Register Reset Value 00 7 6 5 4 3 2 1 0 rwh rwh rw rw rw rwh rw rh Field Description P i Parity Flag Set cle
369. hdog timer reset User s Manual 7 22 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfine on XC886 888CLM Power Saving Modes 8 Power Saving Modes The power saving modes in the XC886 888 provide flexible power consumption through a combination of techniques including e Stopping the CPU clock e Stopping the clocks of individual system components e Reducing clock speed of some peripheral components e Power down of the entire system with fast restart capability After a reset the active mode normal operating mode is selected by default see Figure 8 1 and the system runs in the main system clock frequency From active mode different power saving modes can be selected by software They are e Idle mode e Slow down mode e Power down mode ACTIVE any interrupt EXINTO RXD pin amp clear SD bit POWER DOWN set IDLE bit any interrupt amp SD 1 SLOW DOWN Figure 8 1 Transition between Power Saving Modes User s Manual 8 1 V1 1 2007 05 Power Saving Modes V 1 0 Cinfine on XC886 888CLM Power Saving Modes 8 1 Functional Description This section describes the various power saving modes their operations and how they are entered and exited 8 1 1 Idle Mode The idle mode is used to reduce power consumption by stopping the core s clock In idle mode the oscillator continues to run but the core is stopped with its clock disabled Peripherals whose input clocks are not disabled are still functi
370. he breakpoint is executed only after the proper debug action is taken The OCDS in XC886 888 supports both equal breakpoints and range breakpoints on Instruction address see Configurations of Hardware Breakpoints on Page 17 5 Breakpoints on IRAM Address These breakpoints are generated when an instruction performs read or write access to a location within a defined address range from the Internal Data Memory IRAM The IRAM breakpoints are of Break After Make type therefore the proper debug action is taken immediately after the operation to the breakpoint address is performed The OCDS in XC886 888 supports only range breakpoints on IRAM address User s Manual 17 4 V1 1 2007 05 OCDS V 1 0 Cinfine on XC886 888CLM On Chip Debug Support The OCDS differentiates between a breakpoint on read and a breakpoint on write operation to the IRAM Configurations of Hardware Breakpoints The OCDS allows setting of up to 4 hardware breakpoints In XC886 888 the Program Memory address is 16 bit wide while the Internal Data Memory address both for Read and Write is 8 bit wide For setting of breakpoint on instruction address HWBPx defines the 16 bit address For setting of breakpoint on IRAM address HWBP2 3L and HWBP2 3H define the 8 bit IRAM address range The configurations supported are e Breakpoint 0 e Breakpoint 1 Two equal breakpoints on Instruction Address HWBPO and Instruction Address HWBP1 or One ra
371. hecks and an initialization sequence before starting the program or erase operation Following this the user program can continue execution while background programming or erasing is taking place until the occurrence of a Flash NMI event to indicate the completion of the program or erase operation A manual check on the Flash data is necessary to determine if the programming or erasing was successful via using the MOVC instruction to read out the Flash contents Other special subroutines include aborting the Flash erase operation and checking the Flash bank ready to read status Note The Flash bank where the Flash user program is executing from cannot be targeted for any erase and program operation For example user program in P Flash Bank Pair 0 Sector 0 cannot program or erase other sectors of P Flash Bank Pair 0 Boot ROM special Flash program erase subroutines user program Flash NMI service routine RETI instruction Flash NMI Figure 4 9 Flash Program Erase Flow Note While programming or erasing P Flash Bank Pair O where interrupt vectors are located the Flash NMI should be disabled and polling used instead User s Manual 4 15 V1 1 2007 05 Flash Memory V 1 0 Cinfin eon XC886 888CLM Flash Memory 4 8 1 Flash Programming Each call of the Flash program subroutine allows the programming of 64 and 32 bytes of data into the sele
372. hed On This bit enables the analog part of the ADC module and defines its operation mode 0 The analog part is switched off and conversions are not possible To achieve minimal power consumption the internal analog circuitry is in its power down state and the generation of fADCI is stopped 1 The analog part of the ADC module is switched on and conversions are possible The automatic power down capability of the analog part is disabled 0 I eat A eai 0 if read should be written with 0 OSC_CON OSC Control Register Reset Value 08 7 6 5 4 3 2 1 0 rw rw rw rwh rh r Field Description XPD a Power down Control XTAL is not powered down XTAL is powered down User s Manual 8 9 V1 1 2007 05 Power Saving Modes V 1 0 Cinfine on XC886 888CLM Power Saving Modes Field Bits Type Description OSCPD 4 rw On chip OSC Power down Control 0 The on chip oscillator is not powered down 1 The on chip oscillator is powered down 0 7 5 r Reserved Returns 0 if read should be written with 0 User s Manual 8 10 V1 1 2007 05 Power Saving Modes V 1 0 Cinfin eon XC886 888CLM Watchdog Timer 9 Watchdog Timer The Watchdog Timer WDT provides a highly reliable and secure way to detect and recover from software or hardware failures The WDT is reset at a regular interval that is predefined by the user The CPU must service the WDT within this interval to prevent the WDT from causing an XC886 888 system reset
373. hooses the multi channel patterns e TRPENx enables the trap functionality e PSLx defines the output level that is driven while the output is in the passive state User s Manual 14 15 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 As shown in Figure 14 12 the modulation control part for the 113 related output COUT63 combines the T13 output signal COUT63_1T13_0 is the output signal that is configured by COUT63PS and the enable bit ECT130 with the trap functionality The output level of the passive state is selected by bit PSL63 O passive state ECT130 1 active state COUT63_1T13_0 to Output TRPEN13 pin COUT63 TRPS CCU6 T13 mod ctr Figure 14 12 Modulation Control of the T13 related Output COUT63 User s Manual 14 16 V1 1 2007 05 CCU6B V 1 0 infin eon XC886 888CLM Capture Compare Unit 6 Figure 14 13 shows a modulation control example for CC60 and COUT60 T13 CC60 MCMPO no modulation COUT60 MCMP1 no modulation CC60 T12 no modulation COUT60 T12 no modulation CC60 MCMPO modulated with T12 COUT60 MCMP1 modulated with T12 CC60 MCMPO modulated with T12 and T13 COUT60 MCMP1 modulated with T12 and T13 Figure 14 13 Modulation Control Example for CC60 and COUT60 14 1 4 Trap Handling The trap functionality permits the PWM outputs to react to the state of the input pin CTRAP This functionality can be used to switch off the power device
374. host BSL routine calculates the checksum of the received bytes block type and data area and compares it with received checksum The length of Data and EOT Blocks is defined as Block_Length in the Header Block The length of data area is always 64 bytes for Mode 2 when targeting P Flash since the P Flash is written by a wordline of 64 bytes each time For D Flash the length of data area can range from 32 to 96 bytes but always in multiples of 32 since D Flash is written by a wordline of 32 bytes each time If there is less than one wordline to be programmed to Flash the host needs to fill up vacancies with 00 and transfer Flash data in length of 32 64 and 96 bytes depending on the Flash type User s Manual 18 3 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader 18 1 1 2 LIN Transfer Block Structure A LIN transfer block 9 bytes long fixed consists of four parts NAD Block Type Data Area Checksum 1 byte 1 byte 6 bytes 1 byte e NAD Node Address for Diagnostic which specifies the address of the active slave node 01 to 7E Valid Slave Address 80 to FF Valid Slave Address 7Fy Broadcast Address For Master nodes to all Slave nodes 00 Invalid Slave Address Reserved for go to sleep command e Block Type The type of block which determines how the data area is interpreted See Section 18 1 1 1 00 HEADEP type 01 DATA type 02 END OF TRANSMISSION EOT type
375. iCAN Controller 15 1 9 Message Object Functionality This section describes the functionality of the Message Objects in the MultiCAN module 15 1 9 1 Standard Message Object A message object is selected as Standard Message Object when bit field MOFCRn MMC 0000 The Standard Message Object can transmit and receive CAN frames according to the basic rules as described in the previous sections Additional services such as Single Data Transfer Mode or Single Transmit Trial see following sections are available and can be individually selected 15 1 9 2 Single Data Transfer Mode Single data transfer mode is a useful feature in order to broadcast data over the CAN bus without unintended doubling of information Single data transfer mode is selected via bit MOFCRn SDT Message Reception When a received message stored in a message object is overwritten by a new received message the content of the first message gets lost and is replaced with the content of the new received message indicated by MSGLST 1 In single data transfer mode SDT 1 bit MSGVAL of the message object is automatically cleared by hardware after the storage of a received data frame This prevents the reception of further messages After the reception of a remote frame bit MSGVAL is not automatically cleared Message Transmission When a message object receives a series of multiple remote requests then it transmits several data frames in response to the remot
376. iCAN Controller 15 2 3 Message Object Registers The Message Object Control Register MOCTRn and the Message Object Status Register MOSTATn are located at the same address offset within a message object address block offset address 1C The MOCTRnh is a write only register that makes it possible to set reset CAN transfer related control bits through software MOCTRO Message Object 0 Control Register Reset Value 0100 0000 MOCTR31 Message Object 31 Control Register Reset Value 1F1E 0000 MOCTRnhn n 1 30 Message Object n Control Register Reset Value n 1 01000000 n 1 00010000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SET SET SET SET SET SET SET SET SET SET SET SET DIR TXE TXE TXR RXE RTS MSG MSG NEW RXU TXP RXP N1 NO Q N EL VAL LST DAT PD ND ND W W W W W W W W W W W W W 10 9 8 7 6 5 4 3 2 1 0 RES RES RES RES RES RES RES RES RES RES RES TXE TXE TXR RXE RTS MSG MSG NEW RXU TXP RXP N1 NO Q N EL VAL LST DAT PD ND ND W W W W W W W W W W W 15 14 13 12 11 W W Field Bits Type Description W RESRXPND Reset Set Receive Pending SETRXPND 16 W These bits control the set reset condition for RXPND see Table 15 11 RESTXPND SETTXPND W Reset Set Transmit Pending W These bits control the set reset condition for TXPND see Table 15 11 i 17 RESRXUPD 2 W
377. iS no pending conversion request e Arbitration started by pending conversion request In this mode the arbiter will start polling the request sources only if there is at least one conversion pending request Once started the arbiter polls the two request sources source x at slot x x 0 1 to find the analog channel with the highest priority that must be converted For each arbitration slot the arbiter polls the request pending signal REQPND and the channel number valid signal REQCHNRV of one request source The sum of all arbitration slots is called an arbitration round An arbitration slot must be enabled ASENx 1 before it can take part in the arbitration Each request source has a source priority that can be programmed via bit PRIOx Starting with request source 0 arbitration slot 0 the arbiter checks if a request source has a pending request REQPND 1 for a conversion If more than one request source is found with the same programmed priority level and a pending conversion request the channel specified by the request source that was found first is selected The REQCHNRYV signal is also checked by the arbiter and a conversion can only be started if REQCHNRV 1 and REQPND 1 If both request sources are programmed with the same priority the channel number specified by request source 0 will be converted first since it is connected to arbitration slot 0 The period tagg of a complete arbitration round is fixed at tarp
378. ialized The bootstrap loader then terminates its sequence and transfers program execution to the user code by jumping to location FOOO i e the first loaded instruction The program that was loaded into the XRAM from the host will now be executed Note The bootstrap loader assumes all message data is valid The host should send its code data sequentially in multiples of 8 code data bytes The user is limited to sending a maximum of 192 messages 18 2 2 CAN Message Object definition Host Command Message Object In the Autobaud phase the Host Command message is sent by the host and used for automatic baud rate detection Since there are no other nodes Point to Point on the bus the host will continually send the message The host will transmit this message and wait for the microcontroller to acknowledge it The Host Command message data field contains 8 bytes of information for enabling the BSL mode The first 2 data bytes Byte 0 and 1 contain the value 0x5555 The next 2 data bytes Bytes 2 and 3 contain the identifier for an acknowledge message that the microcontroller sends back to the host Bytes 4 and 5 contain the 16 bit value for the number of messages to be received The final 2 data bytes bytes 6 and 7 contain the identifier for the data messages that the host will send to the XC886 888 device User s Manual 18 29 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader The message identif
379. icated state machine to ensure the correct sequence of Flash mode transition This avoids inadvertent destruction of the Flash contents with a reasonably low software overhead The state machine also ensures that a Flash bank is blocked no read access possible while it is being programmed or erased At any time a Flash bank can only be in ready to read program or sector s erase mode However it is possible to program erase one Flash bank while reading from another When the user sets bit PMCONO PD 1 to enter the system power down mode the Flash banks are automatically brought to its power down state by hardware Upon wake up from system power down the Flash banks are brought to ready to read mode to allow access by the CPU User s Manual 4 11 V1 1 2007 05 Flash Memory V 1 0 Cinfine on XC886 888CLM Flash Memory 4 6 Error Detection and Correction The 8 bit data from the CPU is encoded with an Error Correction Code ECC before being stored in the Flash memory During a read access data is retrieved from the Flash memory and decoded for dynamic error detection and correction The correction algorithm hamming code has the capability to e Detect and correct all 1 bit errors e Detect all 2 bit errors but cannot correct No distinction is made between a corrected 1 bit error result is valid and an uncorrected 2 bit error result is invalid In both cases an ECC non maskable interrupt NMI event is generated bit FNMIEC
380. ied into two categories depending upon the DCEN control bit in register T2MOD 13 2 2 1 Up Down Count Disabled lf DCEN 0 the up down count selection is disabled The timer therefore functions as a pure up counting timer only The operational block diagram is shown in Figure 13 5 lf the T2CON register bit EXEN2 0 the timer starts to count up to a maximum of FFFF once the timer is started by setting the bit TR2 in register T2CON to 1 Upon overflow bit TF2 is set and the timer register is reloaded with the 16 bit reload value of the RC2 register This reload value is chosen by software prior to the occurrence of an overflow condition A fresh count sequence is started and the timer counts up from this reload value as in the previous count sequence lf EXEN2 1 the timer counts up to a maximum of FFFF once TR2 is set A 16 bit reload of the timer registers from register RC2 Is triggered either by an overflow condition or by a negative positive edge chosen by the bit EDGESEL in register T2MOD at input pin T2EX If an overflow caused the reload the overflow flag TF2 is set If a User s Manual 13 14 V1 1 2007 05 Timers V 1 0 Cinfine on XC886 888CLM Timers negative positive transition at pin T2EX caused the reload bit EXF2 in register T2CON is set In either case an interrupt is generated to the core and the timer proceeds to its next count sequence The EXF2 flag similar to the TF2 must be cleared by software If b
381. ier is 555 and the data length code is set to 8 ae Control s Ack Arbitration Field Data field CRC Field End of Frame Data 7 DATA Identifier High Byte Data 6 DATA Identifier Low Byte Data 5 Number of Messages to receive High Byte Data 4 Number of Messages to receive Low Byte Data 3 ACK Identifier High Byte Data 2 ACK Identifier Low Byte Data 1 0x55 Data 0 0x55 Figure 18 7 Host Command Message Format Acknowledgement Message Object In the Acknowledgement phase this message is sent by the microcontroller after successfully determining the CAN network baud rate The message identifier used is specified by the host and determined from the Host message Data bytes 2 and 3 received The data length code is set to 4 Control Ack Arbitration Field Data field CRC Field Field End of Frame Data 3 ACK Identifier High Byte Data 2 ACK Identifier Low Byte Data 1 0x55 Data 0 0x55 Figure 18 8 Acknowledgement Message Format Data Message Object In the Data Reception phase this message is sent by the host with a host specified Data Identifier which is defined in data bytes 6 and 7 of the Host Command message The data field contains user code data that is required for the BSL Mode The data received is then loaded to the XRAM User s Manual 18 30 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader 18 2 3 User Defined Parameter for MultiCAN BSL The
382. ility The minimum erase width is always a complete sector and sectors can be erased separately or in parallel Contrary to standard EEPROMs erased Flash memory cells contain Os The D Flash bank is divided into more physical sectors for extended erasing and reprogramming capability even numbers for each sector size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements User s Manual 4 4 V1 1 2007 05 Flash Memory V 1 0 Cinfin eon XC886 888CLM Flash Memory For example the user s program can implement a buffer mechanism for each sector Double copies of each data set can be stored in separate sectors of similar size to ensure that a backup copy of the data set is available in the event the actual data set is corrupted or erased Alternatively the user can implement an algorithm for EEPROM emulation which uses the D Flash bank like a circular stack memory the latest data updates are always programmed on top of the actual region When the top of the sector is reached all actual data representing the EEPROM data is copied to the bottom area of the next sector and the last sector is then erased This round robin procedure using multifold replications of the emulated EEPROM size significantly increases the Flash endurance To speed up data search the RAM can be used to contain the pointer to the valid data set 4 3 Parallel Read Access of P Flash To enhance system perform
383. ing conditions is fulfilled e PRI 10 and CAN message MOa has higher or equal priority than CAN message MOb with respect to CAN arbitration rules see Table 15 13 e PRI 01 or PRI 11 priority by list order The message object that is qualified for transmission and has highest transmit priority wins the transmit acceptance filtering and will be transmitted first All other message objects lose the current transmit acceptance filtering round They get a new chance in Subsequent acceptance filtering rounds The priority rules are valid for normal CAN operation User s Manual 15 22 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 7 Message Postprocessing After a message object has successfully received or transmitted a frame the CPU can be notified to perform a message postprocessing on the message object The postprocessing of the MultiCAN module consists of two elements 1 Message interrupts to trigger postprocessing 2 Message pending registers to collect pending message interrupts into a common structure for postprocessing 15 1 7 1 Message interrupts When the storage of a received frame into a message object or the successful transmission of a frame is completed a message interrupt can be issued For each message object a transmit and a receive interrupt can be generated and routed to one of the eight CAN interrupt output lines see Figure 15 9 A rec
384. ing the operating mode during a running calculation as indicated by BSY has no effect User s Manual 11 3 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfin eon XC886 888CLM CORDIC Coprocessor 11 2 2 Interrupt The End of Calculation EOC is the only interrupt source of the CORDIC Coprocessor If interrupt is enabled by CD_STATC INT_EN 1 an interrupt request signal is activated at the end of CORDIC calculation and also indicated by the CD_STATC EOC flag If not cleared by software the EOC flag remains set until cleared by hardware when a read access is performed to the low byte of Z result data DMAP 0 During EOC data processing a check must be made to ensure that the ERROR flag is not set indicates data overflow has occurred 11 2 3 Normalized Result Data In all operating modes the CORDIC Coprocessor returns a normalized result data for X and Y as shown in the following equation CORDIC Calculated Data MPS Xor Y Result Data On the other hand the interpretation for Z result data differs which is also dependent on the CORDIC function used For linear function there is no additional processing of the CORDIC calculated Z data as such it is taken directly as the result data The accessible Z result data is a real number expressed as signed 4Q16 For circular and hyperbolic functions the accessible Z result data is a normalized integer value angles in the range 7 2 1 2 z are represented by 2
385. ion Mode The full range of Z input 2 2 1 representing angles 2 1 2 z is supported No limitations on initial X and Y inputs except for overflow considerations which can be overcome with MPS setting User s Manual 11 7 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfine on XC886 888CLM CORDIC Coprocessor Circular Vectoring Mode The full range of X and Y inputs 2 2 1 are supported while Z initial value should satisfy Z lt 2 2 to prevent possible Z result data overflow Note Considerations should also be given to function limitations such as the meaning of the result data e g divide by zero is not meaningful The useful domain included within Table 11 2 for each of the main functions attempts to cover both for CORDIC convergence and useful range of the function Note Input values may be within the domain of convergence however this does not guarantee a fixed level of accuracy of the CORDIC result data Refer to Chapter 11 2 6 for details on accuracy of the CORDIC Coprocessor 11 2 4 2 Overflow Considerations Besides considerations for domain of convergence the limitations on the magnitude of input data must also be considered to prevent result data overflow Data overflow is handled by the CORDIC Coprocessor in the same way in all operating modes Overflow for X and Y data can be prevented by correct setting by the user of the MPS bit whose value is partly based on the CORDIC Coproc
386. ion of data frames source object is receive object i e DIR 0 as well as for the reception of remote frames source object is transmit object Source CAN Bus Destination CAN Bus Pointer to Destination Message Object Copy if IDC Copy if DLCC Source Copy if DATC Source set if GDFS Source Message Object MMC 0100 Destination Message Object MultiC AN _Msgobj_ gateway Figure 15 14 Gateway Transfer from Source to Destination User s Manual 15 39 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 9 8 Foreign Remote Requests When a remote frame has been received on a CAN node and is stored in a message object a transmit request is set to trigger the answer transmission of a data frame to the request or to automatically issue a secondary request If the Foreign Remote Request Enable bit MOFCRn FRREN is cleared in the message object in which the remote request is stored MOSTATn TXRQ is set in the same message object lf bit FRREN is set TXRQ is set in the message object that is referenced by pointer MOFGPRhn CUR The value of CUR is however not changed by this feature Although the foreign remote request feature works independently of the selected message mode it is especially useful for gateways to issue a remote request on the source bus of a gateway after the reception of a remote request on the gateway destinati
387. ion request is sensitive to an external trigger event The event flag bit EV indicates if an external event ae taken place and a conversion can be requested Bit EV is not used to start conversion request Bit EV is used to start conversion request 0 Reserve ie 0 if read should be written with 0 User s Manual 16 46 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter The registers QBURO and QINRO share the same register address A read operation at this register address will deliver the rh bits of the QBURO register while a write operation to the same address will target the w bits of the QINRO register Register QBURO contains bits that monitor the status of an aborted sequential request QBURO Queue Backup Register 0 D2 Reset Value 00 1 0 7 6 5 4 3 2 rh rh rh rh r h r Field Bits Type Description REQCHNR 2 0 rh Request Channel Number This bit field is updated by bit field QORO REQCHNR when the conversion requested by QORO is started V Request Channel Number Valid This bit indicates if the data in REQCHNR RF ENSI and EXTR is valid Bit V is set if a running conversion is aborted It is reset when the conversion is started Os The backup register does not contain valid data because the conversion described by this data has not been aborted 1 The data is valid The aborted conversion is requested before taking into account what is requested by QORO
388. ioned above is actually a shift register that generates data by shifting This shift register is reloaded whenever the Finite State Machine FSM switches to the setup mode on starting a new calculation The CORDIC Coprocessor FSM controls the flow of the calculation 11 3 1 Arctangent and Hyperbolic Arctangent Look Up Tables The LUTs are 20bits and 21bits wide respectively for the arctangent table atan LUT and hyperbolic arctangent table atanh LUT Each entry of the atan LUT is divided into 1 sign bit MSB followed by 19 bit integer part For the atanh LUT each entry has 1 repeater bit MSB followed by 1 sign bit then 19 bit integer part The contents of the LUTs are e atan LUT with data form of S19 see Table 11 4 Table 11 4 Precomputed Scaled Values for atan 2 Iteration No Scaled atan 2 in hex Iteration No Scaled atan 2 in hex i 5 14 i 6 A2F A e atanh LUT with data form of S19 see Table 11 5 User s Manual 11 12 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfin eon XC886 888CLM CORDIC Coprocessor Table 11 5 Precomputed Scaled Values for atanh 2 Iteration No Scaled atanh 2 in hex Iteration No Scaled atanh 2 in hex i 1 16618 i 9 146 518 i 15 5 5 wet nB 14 i 6 A30 i 14 JA 7 mso The Z data is a normalized representation of the actual angle The internal scaling is such that n 219 1 2 n is equivalent to 2 9 2 9 1 The last 4 LSB bits are truncated as 16 bit dat
389. ions of PAGE is ignored 00 STO is selected 01 ST1 is selected 10 ST2 is selected 11 STS is selected OP 7 6 w Operation OX Manual page mode The value of STNR is ignored and PAGE is directly written 10 New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR 11 Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR Reserved Returns 0 if read should be written with 0 User s Manual 6 12 V1 1 2007 05 Parallel Ports V 1 0 Cinfine on XC886 888CLM Parallel Ports 6 3 Port 0 Port PO is a 8 bit general purpose bidirectional port The registers of PO are summarized in Table 6 3 Table 6 3 Port 0 Registers Register Short Name Register Full Name PO DATA Port 0 Data Register PO DIR Port 0 Direction Register PO OD Port 0 Open Drain Control Register PO PUDSEL Port 0 Pull Up Pull Down Select Register PO PUDEN Port 0 Pull Up Pull Down Enable Register PO ALTSELO Port 0 Alternate Select Register 0 PO_ALTSEL1 Port 0 Alternate Select Register 1 6 3 1 Functions Port 0 input and output functions are shown in Table 6 4 Table 6 4 Port 0 Input Output Functions Port Pin en e From to Module P0 0 Input PO _DATA PO User s Manual 6 13 V1 1
390. is done by coupling the reload event to a request trigger input REQTR 16 4 5 4 Software Control The load event for the parallel source can also be generated under software control in two ways e The conversion request control register can be written at two different addresses CRCR1 and CRPR1 Accessed at CRCR1 the write action changes only the bits in this register Accessed at CRPR1 a load event will take place one clock cycle after the write access This automatic load event can be used to start conversions with a single move operation In this case the information about the channels to be converted is given as an argument in the move instruction e Bit LDEV can be written with 1 by software to trigger the load event In this case the load event does not contain any information about the channels to be converted but always takes the contents of the conversion request control register This allows the conversion request control register to be written at a second address without triggering the load event 16 4 5 5 Autoscan The autoscan is a functionality of the parallel source If autoscan mode is enabled the load event takes place when the conversion is completed while PND O provided the parallel request source has triggered the conversion This automatic reload feature allows channels 4 to 7 to be constantly scanned for pending conversion requests without the need for external trigger or software action User s Manual 16 16
391. is set to input default Direction is set to output User s Manual 6 17 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports PO OD Port 0 Open Drain Control Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn 0 Pin n Open Drain Mode n 0 7 Normal mode output is actively driven for 0 and 1 states default Open drain mode output is actively driven only for O state PO PUDSEL Port 0 Pull Up Pull Down Select Register Reset Value FF 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field ens vee Description Pn A Up Pull Down Select Port 0 Bit n n 0 7 Pull down device is selected Pull up device is selected default User s Manual 6 18 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports PO_PUDEN Port 0 Pull Up Pull Down Enable Register Reset Value C4 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Enable at Port 0 Bit n n 0 7 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled default PO_ALTSELn n 0 1 Port 0 Alternate Select Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pin Output Functions n 0 7 Configuration of Px_ALTSELO Pn and Px ALTSEL1 Pn for GPIO or alternate settings 00 Normal GPIO 10 Alternate Select 1 01 Alternate Select 2 11 Alternate Select 3 User s
392. ission 1 Data in CAN_DATA3 register is valid for transmission CAN_ADL Can Address Register Low Reset Value 0000 0000 7 6 5 4 3 2 1 0 rwh Field Bits Type Description CAn n 2 to 9 rwh_ CAN Address Bit n CAN_ADH CAN Address Register High Reset Value 0000 0000 7 6 5 4 3 2 1 0 r rwh rwh rwh rwh Field Bits Type Description CA10 o rwh CAN Address Bit 10 CA11 CAN Address Bit 11 CA12 rwh_ CAN Address Bit 12 CA13 rwh_ CAN Address Bit 13 0 7 4 Reserved read as 0 should be written with 0 User s Manual 15 98 V1 1 2007 05 MultiCAN V1 0 mfin eon XC886 888CLM i Controller Area Network MultiCAN Controller CAN_DATAO CAN Data Register 0 Reset Value 0000 0000 7 6 5 4 3 2 1 0 CD 7 0 rwh Field Bits Type Description CD 7 0 CAN Data Byte 0 CAN_DATA1 CAN Data Register 1 Reset Value 0000 0000 7 6 5 4 3 2 1 0 CD 15 8 rwh Field Bits Type Description CD 7 0 CAN Data Byte 1 CAN_DATA2 CAN Data Register 2 Reset Value 0000 0000 7 6 5 4 3 2 1 0 CD 23 16 rwh Field Bits Type Description CD 7 0 CAN Data Byte 2 User s Manual 15 99 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller CAN_DATA3 CAN Data Register 3 Reset Value 0000 0000 7 6 9 4 3 2 1 0 rwh Field Bits Type Description CD 7 0 CAN Data Byte 3 User s Manual 15 100 V1 1 2007 05 MultiCAN V1 0 Cinfin eo
393. ister Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Cm Description RXINP 3 0 Receive Interrupt Node Pointer RXINP selects the interrupt output line CANSRCm m 0 7 for a receive interrupt event of message object n RXINP can also be taken for message pending bit selection see Page 15 25 0000 Interrupt output line CANSRCO is selected 0001 Interrupt output line ICANSRC1 is selected 01 10 Interrupt output line CANSRCS6 is selected 0111 Interrupt output line CANSRC7 is selected 1000 1111 Reserved TXINP 7 4 rw Transmit Interrupt Node Pointer TXINP selects the interrupt output line CANSRCm m 0 7 for a transmit interrupt event of message object n TXINP can also be taken for message pending bit selection see Page 15 25 0000 Interrupt output line CANSRCO is selected 0001 Interrupt output line CANSRC1 is selected 01 10 Interrupt output line CANSRCE6 is selected 0111 Interrupt output line CANSRC7 is selected 1000 1111 Reserved User s Manual 15 84 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Field Bits Type Description MPN 15 8 rw Message Pending Number This bit field selects the bit position of the bit in the Message Pending Register that is set upon a message object n receive transmit interrupt CFCVAL 31 16 rwh CAN Frame Counter Value When a message is stored in message object n or message object
394. it T2RHEN is set Timer 2 is started by first falling edge rising edge at pin T2EX which is defined by bit T2REGS If bit EXEN2 is set bit EXF2 is also set at the same point when Timer 2 is started with the same falling edge rising edge at pin T2EX which is defined by bit EDGESEL The reload will happen with the following negative positive transitions at pin T2EX which is defined by bit EDGESEL P Overflow Figure 13 5 Auto Reload Mode DCEN 0 13 2 2 2 Up Down Count Enabled lf DCEN 1 the up down count selection is enabled The direction of count is determined by the level at input pin T2EX The operational block diagram is shown in Figure 13 6 User s Manual 13 15 V1 1 2007 05 Timers V 1 0 Cinfine on XC886 888CLM Timers A logic 1 at pin T2EX sets the Timer 2 to up counting mode The timer therefore counts up to a maximum of FFFF Upon overflow bit TF2 is set and the timer register is reloaded with a 16 bit reload value of the RC2 register A fresh count sequence is started and the timer counts up from this reload value as in the previous count sequence This reload value is chosen by software prior to the occurrence of an overflow condition A logic 0 at pin T2EX sets the Timer 2 to down counting mode The timer counts down and underflows when the THL2 value reaches the value stored at register RC2 The underflow condition sets the TF2 flag and causes FFFF to be reloaded into the THL2 register A fresh d
395. it and 32 bit division as well as shift and normalize features It has been integrated to support the XC886 888 Core in real time control applications which require fast mathematical computations The MDU uses a total of 14 registers 12 registers for data manipulation one register to control the operation of MDU and one register for storing the status flags These registers are memory mapped as special function registers like any other registers for peripheral control The MDU operates concurrently with and independent of the CPU Features e Fast signed unsigned 16 bit multiplication e Fast signed unsigned 32 bit divide by 16 bit and 16 bit divide by 16 bit operations e 32 bit unsigned normalize operation e 32 bit arithmetic logical shift operations Table 10 1 specifies the number of clock cycles used for calculation in various operations Table 10 1 MDU Operation Characteristics Operation Remainder No of Clock Cycles used for calculation Signed 32 bit 16 bit 32 bit 16 bit 33 Signed 16 bit 16bit 16 bit 16 bit 17 oak O Signed 16 bit x 16 bit 32 bit Unsigned 32 bit 16 bit 32 bit Unsigned 16 bit 16 bit 16 bit Unsigned 16 bit x 16 bit 32 bit 32 bit normalize 32 bit shift L R 16 bit 32 16 bit 16 a O No of shifts 1 Max 32 No of shifts 1 Max 32 Users Manual 10 1 V1 1 2007 05 MDU V2 1 Cinfine on XC886 888CLM Multiplication Division Unit 10 1 Functional Description The MDU can be regard
396. iterations per calculation the total time from the start of calculation to the instant the EOC flag is set is approximately 41 clock cycles or less It should be noted that the ERROR flag is valid only after one cycle This timing for one complete calculation is applicable also to those modes which involve additional data processing and also to the hyperbolic modes which involve repeat iterations and an extra cycle for mode setup Note The above timing exclude time taken for software loading of initial data and reading of the final result data to and from the six data registers User s Manual 11 11 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfin eon XC886 888CLM CORDIC Coprocessor 11 3 The CORDIC Coprocessor Kernel The CORDIC Coprocessor consists of data registers for holding the X Y and Z values in twos complement format Three shift registers are used to shift the values in the X and Y registers by the number of iterations and to generate the emulated LUT data for the linear function Additionally two look up tables LUT are implemented as combinatorial logic to support the circular and hyperbolic function each The LUT data for the selected operating mode is multiplexed and then added to the data in the Z register with the correct sign The atan LUT contains precalculated atan 2 values while the atanh LUT contains precalculated atanh 2 values both in twos complement format for i iteration count The emulated LUT as ment
397. its Type Description NDIV 7 4 rw PLL N Divider 0000 N 10 0001 N 12 0010 N 13 0011 N 14 0100 N 15 0101 N 16 0110 N 17 0111 N 18 1000 N 19 1001 N 20 1010 N 24 1011 N 30 1100 N 32 1101 N 36 1110 N 40 1111 N 48 The NDIV bit is a protected bit When the Protection Scheme see Chapter 3 5 4 1 is activated this bit cannot be written directly Note The reset value of register PLL_CON is 1001 0000 One clock cycle after reset bit LOCK will be set to 1 if the PLL is locked then the value 1001 0001 will be observed CMCON Clock Control Register Reset Value 10 3 2 1 0 7 6 5 4 VCOSEL KDIV Er FCCFG CLKREL rw rw r rw rw User s Manual 7 19 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management Field e Description CLKREL 3 0 Clock Divider 0000 fsyg 4 0001 foyc 6 0010 fsys 8 0011 fsys 12 0100 fsys 16 0101 foys 24 0110 fsys 32 0111 fsys 48 1000 fsys 64 1001 fsys 96 1010 fsys 128 1011 fsys 192 1100 foys 256 1101 fsys 384 1110 fsys 512 1111 fsys 768 Note The clock division factors listed above is inclusive of the fixed divider factor of 2 See Figure 7 7 FCCFG 4 Fast Clock Configuration 0 FCLK runs at the same frequency as PCLK 1 FCLK runs at 2 times the frequency of PCLK KDIV PLL K Divider 0 K 2 1 K 1 The KDIV bit is a protected bit When the Protection Scheme see Chapter 3 5 4 1 is activated this bit cannot be writ
398. itude of vector 1 K Y 0 sart x y set X x K Y y K Useful domain Full range of X Y Useful domain Full range of X and and Z supported due to pre Y supported due to pre and post processing logic processing logic For solving atan Y X set Z 0 Useful domain Full range of X and Y except X 0 Relationships Relationships tan v sin v cos v acos w atan sart 1 w w asin w atan w sart 1 w m 0 Yina Y X Z MPS Vinal 0 ej 2 Liinal 0 Liinal Z Y X For solving X Z set Y 0 For solving ratio Y X set Z 0 Useful domain Z lt 2 Useful domain Y X lt 2 X gt 0 User s Manual 11 5 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfine on XC886 888CLM CORDIC Coprocessor Table 11 2 CORDIC Coprocessor Operating Modes and Corresponding Result Data contd Function Rotation Mode Vectoring Mode Hyperbolic X K X cosh Z Y sinh Z Xina k sqrt X Y MPS m 1 MPS Yiinal 0 e atanh 2 Yana KIY cosh Z X sinh Z Zina Z atanh Y X MPS where k 0 828 Liinal 0 where k 0 828 For solving cosh Z and sinh Z and For solving sart x y set X x k ef set X 1 k Y 0 Y y k Useful domain Z lt 1 11rad Y 0 Useful domain y lt x X gt 0 For solving atanh Y X set Z 0 Useful domain atanh Y X lt 1 11rad X gt 0 Relationships Relationships tanh v sinh v cosh v In w 2 atanh w 1 w
399. l 1 COUT60_0 Output of Capture Compare channel 0 TXD1 1 UART1 Transmit Data Output Clock Output P3 2 37 49 Hi Z CCPOS2_2 CCU6 Hall Input 2 RXDC1_1 MultiCAN Node 0 Receiver Input RXD1_1 UART1 Receive Data Input CC61_0 Input Output of Capture Compare channel 1 P3 3 38 50 Hi Z COUT61_0 Output of Capture Compare channel 1 TXDC1 1 MultiCAN Node 1 Transmitter Output P3 4 39 51 Hi Z CC62_0 Input Output of Capture Compare channel 2 RXDCO_1 MultiCAN Node 0 Receiver Input T2EX1_0 Timer 21 External Trigger Input P3 5 40 52 Hi Z COUT62_0 Output of Capture Compare channel 2 EXF21_0 Timer 21 External Flag Output TXDCO 1 MultiCAN Node 0 Transmitter Output P3 6 33 41 PD_ CTRAP_O CCU6 Trap Input User s Manual 1 13 V1 1 2007 05 Introduction V 1 1 Cinfine on XC886 888CLM Introduction Table 1 3 Pin Definitions and Functions cont d Symbol Pin Number Type Reset Function TQFP 48 64 State 34 42 Hi Z EXINT4 External Interrupt Input 4 COUT63_0 Output of Capture Compare channel 3 User s Manual 1 14 V1 1 2007 05 Introduction V 1 1 Cinfin eon XC886 888CLM Introduction Table 1 3 Pin Definitions and Functions contd Symbol Pin Number Type Reset Function TQFP 48 64 State I O Port 4 Port 4 is an 8 bit bidirectional general purpose I O port It can be used as alternate functions for CCU6 Timer 0 Timer 1 Timer 21 and MultiCAN P4 0 45 59 Hi Z RXDCO_3 MultiCAN Node 0 Receiver Input CC60_1 Output o
400. l 12 17 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces When foc x 24 MHz the baud rate range between 1 4 kHz to 333 3 kHz can be detected In order to increase the detection accuracy of the baud rate the following examples serve as a guide to select BGSEL value e lf the baud rate falls in the range of 1 4 kHz to 2 8 kHz selected BGSEL value is 11g e Ifthe baud rate falls in the range of 2 8 kHz to 5 5 kHz selected BGSEL value is 10 e Ifthe baud rate falls in the range of 5 5 kHz to 11 kHz selected BGSEL value is 01 e lf the baud rate falls in the range of 11 kHz to 333 3 kHz selected BGSEL value is 00 If the baud rate is 20kHz the possible values of BGSEL that can be selected are 00 012 10 and 11 However it is advisable to select 00 for better detection accuracy The baud rate can also be detected when the system is in the slow down mode For detection of the standard LIN baud rate the required minimum fp is 2 MHz for which the baud rate range that can be detected is between 0 12 kHz to 27 7 KHz Register BG contains the 8 bit reload value for the baud rate timer BG Baud Rate Timer Reload Register Reset Value 00 7 6 5 4 3 2 1 0 rwh Field Description BR_VALUE COR O irwh Baud rate Timer Reload Value Reading returns the 8 bit content of the baud rate timer writing loads the baud rate timer reload value Note BG should only be writte
401. l Mode The hysteresis like control mode MSEL6x 1001 offers the possibility of switching off the PWM output if the input CCPOSx becomes 0 by resetting bit CC6xST This can be used as a simple motor control feature by using a comparator to indicate for example over current While CCPOSx 0 the PWM outputs of the corresponding channel are driving their passive levels The setting of bit CC6xST is only possible while CCPOSx 1 Figure 14 8 shows an example of hysteresis like control mode User s Manual 14 10 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 This mode can be used to introduce a timing related behavior to a hysteresis controller A standard hysteresis controller detects if a value exceeds a limit and switches its output according to the compare result Depending on the operating conditions the switching frequency and the duty cycle may change constantly mee L V A AVAVA value Period value Compare value 0 Pin CC6x CC6xPS 0 PSL 0 Pin COUT6x COUT6xPS 1 PSL 0 I Pin CCPOSx I l l i Figure 14 8 Hysteresis Like Control Mode User s Manual 14 11 V1 1 2007 05 CCU6B V 1 0 Cinfine on XC886 888CLM Capture Compare Unit 6 14 1 2 Timer T13 The timer 113 is similar to timer 112 except that it has only one channel in compare mode The counter can only count up similar to the edge aligned mode of 112 The input clock for timer T13 can be from fecus t
402. l up pull down or putting the port to output In power down mode the clock is turned off Hence it cannot be awakened by an interrupt or by the WDT It is awakened only when it receives an external wake up signal or reset signal Entering Power down Mode Software requests power down mode by setting the bit PMCONO PD to 1 Two NOP instructions must be inserted after the bit PMCONO PD is set to 1 This ensures the first instruction after two NOP instructions is executed correctly after wake up from power down mode lf the external wake up from power down is used software must prepare the external environment of the XC886 888 to trigger one of these signals under the appropriate conditions before entering power down mode A wake up circuit is used to detect a wake up signal and activate the power up During power down this circuit remains active It does not depend on any clocks Exit from power down mode can be achieved by applying a falling edge trigger to the e EXINTO pin e RXD pin e RXD pin or EXINTO pin The wake up source can be selected by the bit WS of the PMCONO register The wake up with reset or without reset is selected by bit PMCONO WKSEL The wake up source and wake up type must be selected before the system enters the power down mode User s Manual 8 3 V1 1 2007 05 Power Saving Modes V 1 0 Cinfine on XC886 888CLM Power Saving Modes Exiting Power down Mode lf power down mode is exited via a hardware reset
403. ld MCMPS This functionality permits an update triggered by software When read this bit always delivers 0 0 Bit field MCMP is updated according to the defined hardware action The write access to bit field MCMPS does not modify bit field MCMP Bit field MCMP is updated by the value written to bit field MCMPS 0 Reserved Returns 0 if read should be written with 0 h MCMOUTSH Multi Channel Mode Output Shadow Register High Reset Value 00 7 6 5 4 3 2 1 0 STR cc W r rw rw Field Bits Type Description EXPHS 2 0 rw Expected Hall Pattern Shadow Bit field EXPHS is the shadow bit field for bit field EXPH The bit field is transferred to bit field EXPH if an edge on the hall input pins CCPOSx x 0 1 2 is detected CURHS 53 rw Current Hall Pattern Shadow Bit field CURHS is the shadow bit field for bit field CURH The bit field is transferred to bit field CURH if an edge on the hall input pins CCPOSx x 0 1 2 is detected User s Manual 14 74 V1 1 2007 05 CCU6B V 1 0 Cinfine on XC886 888CLM Capture Compare Unit 6 Field Bits Type Description STRHP 7 Ww Shadow Transfer Request for the Hall Pattern Setting these bits during a write action leads to an immediate update of bit fields CURH and EXPH by the value written to bit fields CURHS and EXPHS This functionality permits an update triggered by software When read this bit always delivers 0 0 The bit fields CURH and EXPH are updated according to the
404. ld be written with 0 Table 15 11 Reset Set Conditions for Bits in Register MOCTRn RESy Bit Action on Write Write O Leave element unchanged Write User s Manual 15 77 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Table 15 11 Reset Set Conditions for Bits in Register MOCTRn cont d RESy Bit SETy Bit Action on Write Write 1 Reset element Write 0 Write 1 Set element No write 1 The parameter y stands for the second part of the bit name RXPND TXPND up to DIR User s Manual 15 78 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller The MOSTATn is a read only register that indicates message object list status information such as the number of the current message object predecessor and successor message object as well as the list number to which the message object is assigned MOSTATO Message Object 0 Status Register Reset Value 0100 0000 MOSTAT31 Message Object 31Status Register Reset Value 1F1E 0000 MOSTATn n 1 30 Message Object n Status Register Rest Value n 1 01000000 n 1 00010000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PNEXT PPREV rh rh 15 14 13 12 1 0 11 10 9 8 7 6 5 4 3 2 LIST TX TX TX RX RTS MSG MSG NEW RX TX RX EN1 ENO RQ EN EL VAL LST DAT UPD PND PND rh rh rh rh rh rh rh rh rh rh rh rh rh Fiel
405. led 1 XINTR4 is enabled ET2 5 rw Interrupt Node XINTR5 Enable 0 XINTRS5 is disabled 1 XINTR5 is enabled EA 7 rw Global Interrupt Mask 0 All pending interrupt requests except NMI are blocked from the core Pending interrupt requests are not blocked from the core 0 r Reserved Returns 0 if read should be written with 0 IEN1 Interrupt Enable Register 1 Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Bits Type Description EADC rw Interrupt Node XINTR6 Enable 0 XINTR6 is disabled 1 XINTR6 is enabled ESSC 1 rw Interrupt Node XINTR7 Enable 0 XINTR7 is disabled 1 XINTR7 is enabled EX2 2 rw Interrupt Node XINTR8 Enable 0 XINTR8 is disabled 1 XINTR8 is enabled EXM 3 rw Interrupt Node XINTR9 Enable 0 XINTR is disabled 1 XINTR is enabled User s Manual 5 18 V1 1 2007 05 Interrupt System V 1 0 h Cinfin eon XC886 888CLM Interrupt System Field Bits Type Description ECCIPO 4 rw Interrupt Node XINTR10 Enable 0 XINTR10 is disabled 1 XINTR10 is enabled ECCIP1 5 rw Interrupt Node XINTR11 Enable 0 XINTR11 is disabled 1 XINTR11 is enabled ECCIP2 rw Interrupt Node XINTR12 Enable 0 XINTR12 is disabled 1 XINTR12 is enabled ECCIP3 i rw Interrupt Node XINTR13 Enable 0 XINTR13 is disabled 1 XINTR13 is enabled NMICON NMI Control Register Reset Value 00 7 6 5 4 3 2 1 0 mecc ymavoor nmvop nanocos MEAS aut NWOT r rw rw rw rw rw rw rw Field Description NMIWDT Watchdog Timer NMI Enable
406. lements 1 thus SIZE 2 for the 3 elements in the example The bit LIST EMPTY indicates whether a list is empty or not EMPTY 0 in the example because list 2 is not empty Each message object n has a pointer MOCTRn PNEXT that points to the next message object in the list and a pointer MOCTRn PPREV that points to the previous message object in the list PPREV of the first message object points to the message object itself because the first message object has no predecessor in the example message object 5 is the first message object in the list indicated by PPREV 5 PNEXT of the last message object also points to the message object itself because the last message object User s Manual 15 13 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller has no successor in the example object 3 is the last message object in the list indicated by PNEXT 3 Bit field MOCTRn LIST indicates the list index number to which the message object is currently allocated The message object of the example are allocated to list 2 Therefore all LIST bit fields for the message objects assigned to list 2 are set to LIST 2 15 1 4 2 List of Unallocated Elements The list with list index 0 has a special meaning it is the list of all unallocated elements An element is called unallocated if it belongs to list 0 MOCTRn LIST 0 It is called allocated if it belongs to a list with an index not equal to O MO
407. lid setting of bit ST or if ST MODE 0 after write access to X low byte CD_CORDXL provided KEEP bit of corresponding data is not set The result data must be read at the end of calculation BSY no longer active before starting a new calculation The result data is read directly from the kernel data registers with bit CD_STATC DMAP 0 The kernel data is placed directly on the bus so the data registers which function as shadow registers are not overwritten during this operation Alternatively the shadow data registers are read DMAP 1 although this would be merely reading back the user initialized initial data At the end of each calculation CD STATC BSY returns to 0 the End of Calculation EOC flag is set and the interrupt request signal will be activated if interrupt is enabled by INT_EN 1 The result data in X Y and Z are internally checked and in case of data overflow the ERROR bit is set This bit is automatically cleared on the start of a new calculation or when read On starting a new calculation the kernel data registers can no longer be expected to hold the result of the previous calculation The kernel data registers always hold either the initial value or the intermediate result of the last CORDIC iteration Setting the bit ST during an ongoing calculation while BSY is set has no effect In order to start a new calculation bit ST must be set again at a later time when BSY is no longer active In the same manner chang
408. llel Read 4 5 Program memory 3 4 Program status word 2 4 User s Manual XC886 888CLM Index Pull down device 6 8 Pull up device 6 8 Pulse width modulation 14 1 R Read access time 4 1 Read out protection 3 6 Request gating 16 13 Request trigger 16 13 16 15 16 16 16 27 CCU6 Event 16 27 Reset control 7 3 Module behavior 7 7 Result read view 16 21 Accumulated 16 21 Normal 16 21 ROM devices 3 1 3 2 ROM program memory 3 1 RS 232 4 14 S Sample phase 16 5 Schmitt Trigger 6 2 6 3 Sectorization 4 3 Sequential request source 16 11 Serial interfaces 12 1 12 30 Shift operation 10 3 Slow down mode 7 16 8 2 Software breakpoints 17 5 Break before make 17 5 Source priority 16 9 Special Function Register area 3 1 Stack pointer 2 3 Synchronization phase 16 5 Synchronous serial interface 12 31 Baud rate generation 12 39 Continuous transfer operation 12 37 Data width 12 33 Error detection 12 41 Baud rate error 12 42 Phase error 12 42 Receive error 12 41 Transmit error 12 42 Full duplex operation 12 33 19 5 V1 1 2007 05 Cinfineon Half duplex operation 12 36 Interrupts 12 41 Low power mode 12 44 Master mode 12 31 Operating mode 12 32 Port control 12 38 Register description 12 45 Register map 12 44 Right aligned 12 33 Slave mode 12 31 T Timer 0 and Timer 1 13 1 Counter 13 2 External control 13 2 Mode 0 13 bit timer 13 4 Mode 1 16 bit timer 13 5 Mode 2 8 bit automatic reload timer 13 6 Mode 3 two
409. llocated to one of the CAN nodes Besides serving as a storage container for incoming and outgoing frames message objects can be combined to build gateways between the CAN nodes or to setup a FIFO buffer The message objects are organized in double chained lists where each CAN node has its own list of message objects A CAN node stores frames only into message objects that are allocated to the message object list of the CAN node and it only transmits messages belonging to this message object list A powerful command driven list controller performs all message object list operations The bit timings for the CAN nodes are derived from the module clock fcan and are programmable up to a data rate of 1 Mbit s External bus transceivers are connected with a CAN node via a pair of receive and transmit pins Multi CAN Module Kernel Interrupt CANSRC 7 0 Controller TXDC1 a RXDC1 Port TXDCO Control a RXDCO control Access Mediator CAN Control MultiCAN_XC8 overview Figure 15 1 Overview of the MultiCAN Module User s Manual 15 1 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Features e Compliant with ISO 11898 e CAN functionality according to CAN specification V2 0 B active e Dedicated control registers for each CAN node e Data transfer rates up to 1 Mbit s e Flexible and powerful message transfer control and error handling capabilities e Advanced CAN bus bit
410. llowed in the Flash Protection Mode 0 4 8 3 Aborting Flash Erase Each complete erase operation on a Flash bank requires approximately 100 ms during which read and program operations on the Flash bank cannot be performed For the XC886 888 provision has been made to allow an on going erase operation to be interrupted so that higher priority tasks such as reading programming of critical data from to the Flash bank can be performed Hence erase operations on selected Flash bank sector s may be aborted to allow data in other sectors to be read or programmed To minimize the effect of aborted erase on the Flash data retention cycling and to guarantee data reliability the following points must be noted for each Flash bank e An erase operation cannot be aborted earlier than 5 ms after it starts e Maximum of two consecutive aborted erase without complete erase in between are allowed on each sector e Complete erase operation approximately 100 ms is required and initiated by user program after a single or two consecutive aborted erase as data in relevant sector s is corrupted User s Manual 4 18 V1 1 2007 05 Flash Memory V 1 0 Cinfin eon XC886 888CLM Flash Memory e For the specified cycling time each aborted erase constitutes one program erase cycling e Maximum allowable number of aborted erase for each D Flash sector during lifetime is 2500 The Flash erase abort subroutine call see Table 4 3 cannot be performed any
411. lt register e Four result registers storing the conversion results The software can read the conversion result from the result registers The result register used to store the conversion result is selected individually for each input channel User s Manual 16 17 V1 1 2007 05 ADC V 1 0 Cinfine on XC886 888CLM Analog to Digital Converter analog part conversion from channel result control result buffer boundary values result register O result register 1 result register 3 resp conta resp conta control limit check control channel interrupt data reduction control event interrupt Figure 16 8 Result Path Refer to Section 16 7 8 for description of the result generation registers User s Manual 16 18 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 7 2 Limit Checking The limit checking and the data reduction filter are based on a common add subtract structure The incoming result is compared with BOUNDO then with BOUND1 Depending on the result flags lower than compare the limit checking unit can generate a channel interrupt It can become active when the valid result of the data reduction filter is stored in the selected result register G compare result with result in BOUNDO BOUNDO buffer e compare result with BOUNDI BOUND1 BOUND rw data reduction filter limit checking channel Interrupt Figure 16 9 Limit Checking Flow User s Manual 16 19 V
412. lt in local address extension mechanism for increasing the number of addressable SFRs The extended address range is not directly controlled by the CPU instruction itself but is derived from bit field PAGE in the module page register MOD_PAGE Hence the bit field PAGE must be programmed before accessing the SFRs of the target module Each module may contain a different number of pages and a different number of SFRs per page depending on the specific requirement Besides setting the correct RMAP bit value to select the SFR area the user must also ensure that a valid PAGE is selected to target the desired SFRs Figure 3 5 shows how a page inside the extended address range can be selected SFR Address from CPU i MOD_PAGE PAGE rw SFR Data to from CPU Module Figure 3 5 Address Extension by Paging User s Manual 3 13 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization In order to access a register located in a page other than the current one the current page must be exited This is done by reprogramming the bit field PAGE in the page register Only then can the desired access be performed lf an interrupt routine is initiated between the page register access and the module register access and the interrupt needs to access a register located in another page the current page setting can be saved the new one programmed and the old page setting restored This is possible with the st
413. lue of STNR is ignored and PAGE is directly written New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR Reserved Returns 0 if read should be written with 0 3 18 V1 1 2007 05 Cinfin eon XC886 888CLM Memory Organization 3 5 4 1 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits i e protected bits using the PASSWD register When the bit field MODE is 11 writing 10011 to the bit field PASS opens access to writing of all protected bits and writing 10101 to the bit field PASS closes access to writing of all protected bits In both cases the value of the bit field MODE is not changed even if PASSWD register is written with 98 or A8 It can only be changed when bit field PASS is written with 11000 for example writing DO to PASSWD register disables the bit protection scheme Note that access is opened for maximum 32 CCLKs if the close access password is not written If open access password is written again before the end of 32 CCLK cycles there will be a recount of 32 CCLK cycles The protected bits include the N and K Divide
414. m the memory location Before a message object that is allocated to the list of an active CAN node is moved to another list or to another position within the same list bit MOCTRn MSGVAL Message Valid of message object n must be cleared User s Manual 15 17 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 5 CAN Node Analysis Features This section describes the CAN node analysis capabilities of the MultiCAN module 15 1 5 1 Analyze Mode The CAN analyze mode allows the CAN traffic to be monitored without affecting the logical state of the CAN bus The CAN analyze mode is selected by setting bit NCRx CALM In CAN analyze mode the transmit pin of a CAN node is held on recessive level permanently The CAN node may receive frames data remote and error frames but is not allowed to transmit Received data remote frames are not acknowledged i e acknowledge slot is sent recessive but will be received and stored in matching message objects as long as there is any other node that acknowledges the frame The complete message object functionality is available but no transmit request will be executed 15 1 5 2 Loop Back Mode The MultiCAN module provides a loop back mode to enable an in system test of the MultiCAN module as well as the development of CAN driver software without access to an external CAN bus The loop back feature consists of an internal CAN bus inside th
415. m the value of the bits in register IS e g the interrupt will be generated if enabled even if the corresponding bit is already set The trigger for an interrupt generation is the detection of a set condition by hardware or software for the corresponding bit in register IS Note In compare mode and hall mode the timer related interrupts are only generated while the timer is running TXR 1 In capture mode the capture interrupts are also generated while the timer T12 is stopped Register ISS contains the individual interrupt request set bits required to generate a CCU6 interrupt request by software User s Manual 14 82 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 ISSL Capture Compare Interrupt Status Set Register Low Reset Value 00 Field a Description SCC60R Set Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC60R in register IS will be set SCC60F Set Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC60F in register IS will be set SCC61R 2 W Set Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC61R in register IS will be set SCC61F 3 W Set Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC61F in register IS will be set SCC62R 4 W Set Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC62R in register IS will be set SCC62F 5 W Set Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC62F in register IS
416. marks the block as a Header Block e Mode The mode to be selected Mode 0 1 2 3 4 6 8 and 9 are supported See Table 18 2 e Mode Data Five bytes of special information to activate corresponding mode e Checksum The Programming Checksum or LIN Checksum of the header block Note Mode 8 and Mode 9 support LIN Checksum while Mode O 6 support Programming Checksum 18 1 3 3 The Activation of Modes 0 2 and 8 Mode 0 as well as Mode 8 and Mode 2 are used to transfer a user program from the host to the XRAM and Flash of the microcontroller respectively The header block has the following structure The Header Block Mode Data 00 02 08 StartAddr StartAddr Checksum Mode 0 2 8 High Low Not Used 1 byte 1 byte Z Pytes Mode Data Description Start Addr High Low 16 bit Start Address which determines where to copy the received program code in the XRAM Flash Not used 2 bytes these bytes are not used and will be ignored in Mode 0 2 8 Fast_Prog Indication byte to enter Fast LIN BSL 1 Flash address must be aligned to the wordline address where DPL is 00 40 80 C0 for P Flash and 00 20 40 60 80 A0 CO0 E0 for D Flash If the data starts in a non wordline address PC Host needs to fill up the beginning vacancies with 00 and provide the start address of that wordline address User s Manual 18 19 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader
417. me CFC 13 12 CAN bus information see Table 15 10 111 Reserved do not use this combination User s Manual 15 74 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Table 15 10 CAN Bus State Information CFC 13 12 CAN Bus State 00 Olg 10 11 User s Manual MultiCAN V1 0 NoBit The CAN bus is idle performs bit de stuffing or is in one of the following frame segments SOF SRR CRC delimiters first 6 EOF bits IFS NewBit This code represents the first bit of a new frame segment The current bit is the first bit in one of the following frame segments Bit 10 MSB of standard ID transmit only RTR reserved bits IDE DLC MSB bit 7 MSB in each data byte and the first bit of the ID extension Bit This code represents a bit inside a frame segment with a length of more than one bit not the first bit of those frame segments that is indicated by NewBit The current bit is processed within one of the following frame segments ID bits except first bit of standard ID for transmission and first bit of ID extension DLC 3 LSB and bits 6 0 in each data byte Done The current bit is in one of the following frame segments Acknowledge slot last bit of EOF active passive error frame overload frame Two or more directly consecutive Done codes signal an Error Frame 15 75 V1 1 2007 05 Cinfine on XC886 888CLM Controller Area Network Mult
418. me 1 parane eao parallel read SWAP A DATA TRANSFER MOV A data 74 2 2 6 J4 12 MOV Ri data 76 77 2 2 6 4 12 A A DPTR h h Users Manual Processor Architecture V 1 0 V1 1 2007 05 Cinfin eon XC886 888CLM Processor Architecture Table 2 1 CPU Instruction Timing cont d Mnemonic Hex Code Bytes Number of foc i XC886 888 8051 a ae parallel ag D NINNIN BOOLEAN BRANCHING e Jors ohe CO D RET 22 RETI 32 e h Users Manual 2 12 V1 1 2007 05 Processor Architecture V 1 0 Cinfine on XC886 888CLM Processor Architecture Table 2 1 CPU Instruction Timing cont d Mnemonic Hex Code Bytes Number of foc i XC886 888 8051 1 ws a w ee S9 N MISCELLANEOUS ADDITIONAL INSTRUCTIONS MOVC DPTR A TRAP 1 With parallel read the number of clock cycles for each instruction may vary depending on whether the access is made to the cache or to the Flash See Chapter 4 3 CO PM Ws WW WI WM NM OJO A HR HR HA AIAJ HY HR HAY A User s Manual 2 13 V1 1 2007 05 Processor Architecture V 1 0 Cinfin eon XC886 888CLM Memory Organization 3 Memory Organization The XC886 888 CPU operates in the following five address spaces e 12 Kbytes of Boot ROM program memory e 256 bytes of internal RAM data memory e 1 5 Kbytes of XRAM memory XRAM can be read written as program memory or external data memory e a128 byte Spe
419. metic right shifts signed bits are shifted in from the left end of register MD3 For example if the data 0101 and 1010 are to undergo an arithmetic shift right the results obtained will be 0010 and 1101p respectively For any shift operation register bit MD4 SLR specifies the shift direction and MD4 SCTR the shift count Note The MDU does not detect overflows due to an arithmetic shift left operation User must always ensure that the result of an arithmetic shift left is within the boundaries of MDU Users Manual 10 3 V1 1 2007 05 MDU V2 1 Cinfin eon XC886 888CLM Multiplication Division Unit 10 1 4 Busy Flag A busy flag is provided to indicate the MDU is still performing a calculation The flag MDUSTAT BSY is set at the start of a calculation and cleared after the calculation is completed at the end of phase two It is also cleared when the error flag is set lf a second operation needs to be executed the status of the busy flag will be polled first and only when it is not set can the start bit be written and the second operation begin Any unauthorized write to the start bit while the busy flag is still set will be ignored 10 1 5 Error Detection The error flag MDUSTAT IERR is provided to indicate that an error has occurred while performing a calculation The flag is set by hardware when one of these occurs e Division by zero e Writing of reserved opcodes to MDUCON register The setting of the error flag causes th
420. microcontrollers serial interface UART which is connected to the personal computer host via the commonly available RS 232 serial cable The BSL mode is selected if the latched values of the MBC and TMS pins are 0 after power on or hardware reset The BSL routine will first perform an automatic synchronization with the transfer speed baud rate of the serial communication partner personal computer host Communication between the BSL routine and the host is done via a transfer protocol information is sent from the host to the microcontroller in blocks with specified block structure and the BSL routine acknowledges the received data by returning a single acknowledge or error byte User can program erase or execute the P Flash and D Flash banks The available working modes include e Transfer user program from host to Flash e Execute user program in Flash e Erase Flash sector s from the same or different bank s for P Flash or D Flash e Mass Erase of all the sectors of P Flash and D Flash User s Manual 4 14 V1 1 2007 05 Flash Memory V 1 0 Cinfin eon XC886 888CLM Flash Memory 4 8 In Application Programming In some applications the Flash contents may need to be modified during program execution In Application Programming IAP is supported so that users can program or erase the Flash memory from their Flash user program by calling some subroutines in the Boot ROM see Figure 4 9 The Flash subroutines will first perform some c
421. mit Data Output JTAG Serial Data Output UART1 Transmit Data Output Clock Output JTAG Clock Input UART1 Transmit Data Output JTAG Serial Data Input UART1 Receive Data Input V1 1 2007 05 Cinfine on XC886 888CLM Introduction Table 1 3 Pin Definitions and Functions cont d Symbol Pin Number Type Reset Function TQFP 48 64 State I O Port Supply 3 3 or 5 0 V Also used by EVR and analog modules All pins must be connected Vssp 18 42 26 54 I O Ground All pins must be connected Vopc eB o e e Core Supply Monitor 2 5 V Vssc CS e e Core Supply Ground V AREF 2432 f ADC Reference Voltage VaGnp 2331 0 ADC Reference Ground XTAL1 4 4 Hi Z External Oscillator Input backup for on chip OSC normally NC XTAL2 3 3 Hi Z External Oscillator Output backup for on chip OSC normally NC TMS 10 16 1 PD Test Mode Select RESET 41 53 1 PU_ Reset Input MBC 44 58 1 PU Monitor amp BootStrap Loader Control NC 56 57 i No Connection 1 An external pull up device in the range of 4 7 kQ to 100 kQ is required to enter user mode Alternatively MBC can be tied to high if alternate functions for debugging of the pin are not utilized Vopp 1 4 Chip Identification Number Each device variant of XC886 888 is assigned an unique chip identification number to allow easy identification of one device variant from the others The differentiation is based on the product variant type and devi
422. modulation of COUT60 Bit 2 modulation of CC61 Bit 3 modulation of COUT61 Bit 4 modulation of CC62 Bit 5 modulation of COUT62 The enable feature of the modulation is defined as follows 0 The modulation of the corresponding output signal by a T12 PWM pattern is disabled 1 The modulation of the corresponding output signal by a T12 PWM pattern is enabled User s Manual 14 67 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Bits Type Description MCMEN 7 rw Multi Channel Mode Enable 0 The modulation of the corresponding output signal by a multi channel pattern according to bit field MCMPis disabled 1 The modulation of the corresponding output signal by a multi channel pattern according to bit field MCMP is enabled a Reserved Returns 0 if read should be written with 0 MODCTRH Modulation Control Register High Reset Value 00 7 6 5 4 3 2 1 0 ECT 8 Townes rw r rw Field Description T13MODEN 5 0 rw T13 Modulation Enable Setting these bits enables the modulation of the corresponding compare channel by a PWM pattern generated by timer 113 The bit positions are corresponding to the following output signals Bit 0 modulation of CC60 Bit 1 modulation of COUT60 Bit 2 modulation of CC61 Bit 3 modulation of COUT61 Bit 4 modulation of CC62 Bit 5 modulation of COUT62 The enable feature of the modulation is defined as follows 0 The modulation of the corresponding output sig
423. mpare reset event 113 counter value below the compare value if the T13 runs and if the T13 reset event is enabled including in single shot mode at the end of the T13 period Timer T13 is used to modulate the other output signals with a 113 PWM In order to decouple COUT63 from the internal modulation the compare state can be selected independently by bits T13IM and COUT63PS 14 1 2 3 Single Shot Mode The single shot mode of timer T13 is selected when bit T13SSC is set to 1 In single shot mode the timer T13 stops automatically at the end of its counting period If the end of period event is detected while bit T13SSC is set the bit T13R and the bit CC63ST are reset 14 1 2 4 Synchronization of T13 to T12 The timer T13 can be synchronized on a 112 event The events include User s Manual 14 13 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 e a112 compare event on channel 0 e a112 compare event on channel 1 e a112 compare event on channel 2 e any 112 compare event on channel 0 1 or 2 e aperiod match of T12 e azero match of T12 while counting up e any edge of inputs CCPOSx The bit fields T13TEC and T13TED select the event that is used to start timer T13 This event sets bit T13R by hardware and T13 starts counting Combined with the single shot mode this can be used to generate a programmable delay after a T12 event compare match while counting up Ny 3 2 CCU6_1T13_ sync Fig
424. n Figure 18 3 while Figure 18 4 shows the Master Request Header Slave Response Header Command and Response LIN frames User s Manual 18 17 V1 1 2007 05 Bootstrap Loader V1 0 infin eon XC886 888CLM Bootstrap Loader Microcontroller Master Request Header Phase l Synchronize P and Set up Baud rate Command x Phase lIl Selection of Working Mode for valid command Slave Response Header Phase l Synchronize D gt and Set up Baud rate Response Phase III Report its status to the host Figure 18 3 LIN BSL Phases Il and Ill LIN BSL Master Request Header Command SYN Break Protected ID Checksum At least 13 3C 8 Data bytes for Command 1 byte bits low Slave Response Header lt SYN Break At least 13 bits low Protected ID 7D Response Checksum 1 byte 8 Data bytes for Response Figure 18 4 LIN BSL Frames User s Manual 18 18 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader 18 1 3 2 The Selection of Modes When the LIN BSL routine enters Phase Il it first awaits for a 9 byte Header Block from the host which contains the information for the selection of the modes as shown below Block Type Check 00 Mode Mode Data ep Header Block 1 byte 5 bytes Description e NAD Node Address for Diagnostic e 00 The block type which
425. n XC886 888CLM Analog to Digital Converter 16 Analog to Digital Converter The XC886 888 includes a high performance 10 bit Analog to Digital Converter ADC with eight multiplexed analog input channels The ADC uses a Successive approximation technique to convert the analog voltage levels from up to eight different sources Features e Successive approximation e 8 bit or 10 bit resolution TUE of 1 LSB and 2 LSB respectively e Eight analog channels e Four independent result registers e Result data protection for slow CPU access wait for read mode Single conversion mode e Autoscan functionality e Limit checking for conversion results e Data reduction filter accumulation of up to 2 conversion results e Two independent conversion request sources with programmable priority e Selectable conversion request trigger e Flexible interrupt generation with configurable service nodes e Programmable sample time e Programmable clock divider e Cancel restart feature for running conversions e Integrated sample and hold circuitry e Compensation of offset errors e Low power modes User s Manual 16 1 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 1 Structure Overview The ADC module consists of two main parts i e analog and digital with each containing independent building blocks The analog part includes e Analog input multiplexer for selecting the channel to be converted e Analog c
426. n XC886 888CLM Controller Area Network MultiCAN Controller The Message Object FIFO Gateway Pointer register MOFGPRn contains a set of message object link pointers that are used for FIFO and gateway operations MOFGPRnh n 0 31 Message Object n FIFO Gateway Pointer Register Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SEL CUR rw rwh Field Bits Type Description T rw Bottom Pointer Bit field BOT points to the first element in a FIFO structure TOP 15 8 rw Top Pointer Bit field TOP points to the last element in a FIFO structure Type CUR 23 16 irwh Current Object Pointer Bit field CUR points to the actual target object within a FIFO Gateway structure After a FIFO gateway operation CUR is updated with the message number of the next message object in the list structure given by PNEXT of the message control register until it reaches the FIFO top element given by TOP when itis reset to the bottom element given by BOT SEL 31 24 rw Object Select Pointer Bit field SEL is the second software pointer to complement the hardware pointer CUR in the FIFO structure SEL is used for monitoring purposes FIFO interrupt generation User s Manual 15 90 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Message Object n Acceptance Mask Register MOAMRnh contains the mask bits for the acceptance filtering of the message objec
427. n bit field SWSYN 000 no trigger request will be generated 001 correct hall pattern on CCPOSx detected 010 113 period match detected while counting up 011 T12 one match while counting down 100 112 channel 1 compare match detected phase delay function 101 T12 period match detected while counting up else reserved no trigger request will be generated User s Manual 14 78 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Bits Type Description SWSYN 5 4 rw Switching Synchronization Bit field SWSYN triggers the shadow transfer between MCMPS and MCMP if it has been requested before flag R set by an event selected by SWSEL This feature permits the synchronization of the outputs to the PWM source that is used for modulation T12 or T13 00 direct the trigger event directly causes the shadow transfer 01 T13 zero match triggers the shadow transfer 10 a T12 zero match while counting up triggers the shadow transfer 11 reserved no action 0 3 6 r Reserved 7 Returns 0 if read should be written with 0 Note The generation of the shadow transfer request by hardware is only enabled if bit MCMEN 1 14 3 7 Interrupt Control Registers ISL Capture Compare Interrupt Status Register Low Reset Value 00 7 6 5 4 3 2 1 0 T12 T12 ICC ICC ICC ICC ICC ICC PM OM 62F 62R 61F 61R 60F 60R rh rh rh rh rh rh rh rh Field Bits Type Description ICC6xR 0 2 rh Capture Compare Match Rising Ed
428. n drain mode If driven with 1 no driver will be activated and the pin output state depends on the internal pull up pull down device setting If driven with 0 the driver s pull down transistor will be activated The open drain mode is controlled by the register Px_OD Px OD Port x Open Drain Control Register 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn x Pin n Open Drain Mode n 0 7 Normal mode output is actively driven for 0 and 1 states Open drain mode output is actively driven only for O state 6 1 1 4 Pull Up Pull Down Device Register Internal pull up pull down devices can be optionally applied to a port pin This offers the possibility of configuring the following input characteristics e tristate e high impedance with a weak pull up device e high impedance with a weak pull down device and the following output characteristics e push pull optional pull up pull down e open drain with internal pull up e open drain with external pull up The pull up pull down device can be fixed or controlled via the registers Px_ PUDSEL and Px _PUDEN Register Px _PUDSEL selects the type of pull up pull down device while register Px _ PUDEN enables or disables it The pull up pull down device can be selected pinwise User s Manual 6 8 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Px PUDSEL Port x Pull Up Pull Down Select Register 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw
429. n if R 0 User s Manual 12 18 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces Register FDCON contains the control and status bits for the fractional divider and also the status flags used in LIN protocol support see Section 12 2 1 FDCON Fractional Divider Control Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rwh rwh rwh rwh rw rw Field Description FDEN Fractional Divider Enable Bit 0 Fractional Divider is disabled only prescaler is considered 1 Fractional Divider is enabled FDM Fractional Divider Mode Select 0 Fractional Divider Mode is selected 1 Normal Divider Mode is selected NDOV rwh_ Overflow Flag in Normal Divider Mode This bit is set by hardware and can only be cleared by software 0 Interrupt request is not active 1 Interrupt request is active rwh_ Break Field Flag This bit is set by hardware and can only be cleared by software 0 Break Field is not detected 1 Break Field is detected rwh End of SYN Byte Flag This bit is set by hardware and can only be cleared by software 0 End of SYN Byte is not detected 1 End of SYN Byte is detected rwh SYN Byte Error Flag This bit is set by hardware and can only be cleared by software 0 Error is not detected in SYN Byte 1 Error is detected in SYN Byte BRK EOFSYN ERRSYN User s Manual 12 19 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces Field Bits
430. n segment The maximum number of time quanta allowed for re synchronization is defined by bit field NBTRx SJW The Propagation Time Segment and the Phase Buffer Segment 1 are combined to parameter T gt which is defined by the value NBTRx TSEG1 A minimum of 3 time quanta is requested by the ISO standard Parameter Tseg2 which is defined by the value of NBTRx TSEG2 covers the Phase Buffer Segment 2 A minimum of 2 time User s Manual 15 8 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller quanta is requested by the ISO standard According to ISO standard a CAN bit time calculated as the sum Of Toyncs Tseg1 AND Tego Must not fall below 8 time quanta Calculation of the bit time bo BRP 1 foan if DIV8 0 8 x BRP 1 foan if DIV8 1 T syne xf Toggi TSEG1 1 x tg min 3 ta Tseg2 TSEG2 1 x tg min 2 ta bit time I syno Tgeg1 Tseg2 min 8 ta To compensate phase shifts between clocks of different CAN controllers the CAN controller must synchronize on any edge from the recessive to the dominant bus level If the hard synchronization is enabled at the start of frame the bit time is restarted at the synchronization segment Otherwise the re synchronization jump width Tsw defines the maximum number of time quanta a bit time may be shortened or lengthened by one re synchronization The value of SJW is defined by bit field NBTRx SJW T seg 2 T
431. n the CAN traffic If the CAN node is in the bus off state then the ongoing bus off recovery which does not depend on the INIT bit is continued With the end of the bus off recovery sequence the CAN node is allowed to take part in the CAN traffic If the CAN node is not in the bus off state a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic 1 Setting this bit terminates the participation of this node in the CAN traffic Any ongoing frame transfer is cancelled and the transmit line goes recessive If the CAN node is in the bus off state then the running bus off recovery sequence is continued If the INIT bit is still set after the successful completion of the bus off recovery sequence i e after detecting 128 sequences of 11 consecutive recessive bits 11 x 1 then the CAN node leaves the bus off state but remains inactive as long as INIT remains set Bit INIT is automatically set when the CAN node enters the bus off state TRIE 1 rw Transfer Interrupt Enable TRIE enables the transfer interrupt of CAN node x This interrupt is generated after the successful reception or transmission of a CAN frame in node x 0 Transfer interrupt is disabled 1 Transfer interrupt is enabled Bit field NIPRx TRINP selects the interrupt output line which becomes activated at this type of interrupt User s Manual 15 60 V1 1 2007 05 MultiCAN V1 0 Cinfineon i l a
432. nal by a T13 PWM pattern is disabled 1 The modulation of the corresponding output signal by a T13 PWM pattern is enabled User s Manual 14 68 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Bits Type Description ECT130 7 rw Enable Compare Timer T13 Output 0 The alternate output function COUT63 is disabled 1 The alternate output function COUT63 is enabled for the PWM signal generated by T13 i a The register TRPCTR controls the trap functionality It contains independent enable bits for each output signal and control bits to select the behavior in case of a trap condition The trap condition is a low level on the CTRAP input pin which is monitored inverted level by bit TRPF in register IS While TRPF 1 trap input active the trap state bit TRPS in register IS is set to 1 Reserved Returns 0 if read should be written with 0 TRPCTRL Trap Control Register Low Reset Value 00 7 6 5 4 3 2 1 0 TRP TRP TRP M2 M1 Mo r rw rw rw User s Manual 14 69 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 operation bit TRPS 0 as soon as the input CTRAP becomes inactive Bit TRPF is automatically cleared by hardware if the input pin CTRAP becomes 1 Bit TRPS is automatically cleared by hardware if bit TRPF is 0 and if the synchronization condition according to TRPMO 1 is detected 1 The trap state can be left return to normal operation
433. nation object 3 If bit MOFCRs DATC is set the data bytes stored in the two data registers MODATALs and MODATAHS are copied from the gateway source object to the gateway destination object All 8 data bytes are copied even if MOFCRs DLC indicates less than 8 data bytes 4 If bit MOFCRs GDFS is set the transmit request flag MOSTATd TXRQ is set in the gateway destination object 5 The receive pending bit MOSTATd RXPND and the new data bit MOSTATd NEWDAT are set in the gateway destination object 6 A message interrupt request is generated for the gateway destination object if its MOSTATd RXIE is set 7 The current object pointer MOFGPRs CUR of the gateway source object is moved to the next destination object according to the FIFO rules as described on Page 15 34 A gateway with a single static destination object is obtained by setting MOFGPRs TOP MOFGPRs BOT MOFGPRs CUR destination object The link from the gateway source object to the gateway destination object works in the same way as the link from a FIFO base to a FIFO slave This means that a gateway with an integrated destination FIFO may be created in Figure 15 13 where the object on the left is the gateway source object and the message object on the right side is the gateway destination objects User s Manual 15 38 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller The gateway operates in the same way for the recept
434. nchronization phase tsyy e Sample phase ts e Conversion phase e Write result phase twp conversion start Source Channel Result trigger interrupt interrupt interrupt Sample Phase Conversion Phase fapci BUSY Bit SAMPLE Bit Write Result Phase t gt WR Figure 16 3 Conversion Timing User s Manual 16 4 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Synchronization Phase tsyyn One franc period is required for synchronization between the conversion start trigger from the digital part and the beginning of the sample phase in the analog part The BUSY and SAMPLE bits will be set with the conversion start trigger Sample Phase ts During this period the analog input voltage is sampled The internal capacitor array is connected to the selected analog input channel and is loaded with the analog voltage to be converted The analog voltage is internally fed to a voltage comparator With the beginning of the sampling phase the SAMPLE and BUSY flags in register GLOBSTR are set The duration of this phase is common to all analog input channels and is controlled by bit field STC in register INPCRO Conversion Phase During the conversion phase the analog voltage is converted into an 8 bit or 10 bit digital value using the successive approximation technique with a binary weighted capacitor network At the beginning of the conversion phase the SAMPLE flag is
435. nd 3 Timing Diagram User s Manual 12 6 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 1 2 Multiprocessor Communication Modes 2 and 3 have a special provision for multiprocessor communication using a system of address bytes with bit 9 1 and data bytes with bit 9 0 In these modes 9 data bits are received The 9th data bit goes into RB8 The communication always ends with one stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON One of the ways to use this feature in multiprocessor systems is described in the following paragraph When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte that identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that were not being addressed retain their SM2s as set and ignore the incoming data bytes Bit SM2 has no effect in mode 0 SM2 can be used in mode 1 to check the validity of the
436. nd PSL for different applications The examples are in the center aligned mode with dead time Hardware modifications of the compare state bits are only possible while timer 112 is running Therefore the bit T12R can be used to enable disable the modification by hardware User s Manual 14 6 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 period value compare value CC6xST CC6xPS 0 passive gt active passive PSL 0 Pin COUT6x e e e COUT6xPS 1 active passive active PSL 0 CCU6 T12_comp_ states Figure 14 4 Compare States of Timer T12 Driving Stage gt high active gt high active CC60PS 0 PSLO 0 CC6xPS 0 PSLO 1 COUT60PS 1 PSL1 0 COUT6xPS 1 PSL1 0 Driving Driving Stage low active high active COUT60 X gt o low active low active CC6xPS 0 PSLO 1 CC6xPS 0 PSLO 0 COUT6xPS 1 PSL1 1 COUT6xPS 1 PSL1 1 Figure 14 5 Different settings of CC6xPS COUT6xPS and PSL User s Manual 14 7 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 For the hysteresis like compare mode MSEL6x 1001 see Section 14 1 1 9 the setting of the compare state bit is possible only while the corresponding input CCPOSx 1 inactive lf the hall sensor mode MSEL6x 1000 is selected see Section 14 1 6 the compare state bits of the compare channels 1 and 2 are modified by the timer T12 in ord
437. nd decrements DRC User s Manual 16 20 V1 1 2007 05 ADC V 1 0 Cinfine on XC886 888CLM Analog to Digital Converter After this addition the complete result is stored in the selected result register The result event is generated and the valid bit becomes set It is possible to have an identical cycle behavior of the path to the result register with the data reduction filter being enabled or disabled Furthermore an overflow of the result register is avoided because a maximum of 2 conversion results are added a 10 bit result added twice delivers a maximum of 11 bits 16 4 7 4 Result Register View In order to cover a wide range of applications the content of result register x x 0 3 is available as different read views at different addresses see Figure 16 11 e Normal read view RESRxL H This view delivers the 8 bit or 10 bit conversion result e Accumulated read view RESRAXL H This view delivers the accumulated 9 bit or 11 bit conversion result All conversion results with or without accumulation are stored in the result registers but can be viewed at either RESRxL H or RESRAXL H which shows different data alignment and width When the data reduction filter is enabled DRCTR 1 read access should be performed on RESRAxL H as it shows the full 9 bit R8 RO or 11 bit R10 RO accumulated conversion result Reading from RESRxL H gives the appended MSB unavailable accumulated result When the data reduction fil
438. ndary 9 2 Wordline address 4 6 Write buffers 4 9 Write result phase 16 5 X XC886 888 Device configuration 1 2 Device profile 1 3 Feature summary 1 4 Functional units 1 2 XRAM 3 1 User s Manual XC886 888CLM Index V1 1 2007 05 Cinfineon 19 2 Register Index XC886 888CLM This section lists the references to the Special Function Registers of the XC886 888 A ACC 2 3 ADC_PAGE 16 31 ADCON 15 97 ADH 15 98 ADL 15 98 B B 2 3 BCON 12 16 BG 12 18 BRH 12 50 BRL 12 50 C CAN LISTi 15 54 CAN MCR 15 52 CAN_MITR 15 53 CAN _MOAMRnh 15 91 CAN MOARn 15 92 CAN MOCTRnhn 15 76 CAN _MODATAHn 15 96 CAN _MODATALn 15 95 CAN_MOFCRnhn 15 86 CAN _MOFGPRnhn 15 90 CAN_MOIPRn 15 84 CAN MOSTATn 15 79 CAN_MSIDk 15 57 CAN_MSIMASK 15 58 CAN _MSPNDk 15 56 CAN_NBTRx 15 69 CAN _NCRx 15 59 CAN _NECNTx 15 71 CAN _NFCRx 15 72 CAN_NIPRx 15 66 CAN_NPCRx 15 68 CAN _NSRx 15 63 User s Manual CAN_PANCTR 15 48 CC63RH 14 53 CC63RL 14 53 CC63SRH 14 54 CC63SRL 14 54 CC6xRH 14 48 CC6xRL 14 48 CC6xSRH 14 49 CC6xSRL 14 48 CCU6_PAGE 14 33 CD_CON 11 16 CD_CORDXH x X Y or Z 11 20 CD_CORDxL x X Y or Z 11 19 CD_STATC 11 18 CHCTRx x 0 7 16 39 CHINCR 16 59 CHINFR 16 59 CHINPR 16 60 CHINSR 16 60 CMCON 7 19 CMPMODIFH 14 58 CMPMODIFL 14 57 CMPSTATH 14 56 CMPSTATL 14 55 COCON 7 21 CONH 12 47 12 48 CONL 12 46 12 48 CRCR1 16 49 CRMR1 16 51 CRPR1 16 50 D DATAO 15 99 DATA1 15 99 DATA2 15 99
439. nding Register k is changed User s Manual 15 26 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 8 Message Object Data Handling This section describes the handling capabilities for the Message Object Data of the MultiCAN module 15 1 8 1 Frame Reception After the reception of a message it is stored in a message object according to the scheme shown in Figure 15 11 The MultiCAN module not only copies the received data into the message object but it provides advanced features to enable consistent data exchange between MultiCAN and CPU MSGVAL During the frame reception information is stored only in the message object when MOSTATn MSGVAL 1 If bit MSGVAL is reset by the CPU the MultiCAN module Stops all ongoing write accesses to the message object so that the message object can be reconfigured by the CPU with subsequent write accesses to it without being disturbed by the MultiCAN RTSEL When the CPU re configures a message object during CAN operation for example clears MSGVAL modifies the message object and sets MSGVAL again the following scenario can occur 1 The message object wins receive acceptance filtering 2 The CPU clears MSGVAL to re configure the message object 3 The CPU sets MSGVAL again after re configuration 4 The end of the received frame is reached As MSGVAL is set the received data is stored in the message object a message interrup
440. nel 16 25 Event 16 24 Node pointer 16 25 Low power mode 16 7 Module clock 16 3 Register description 16 33 Register map 16 30 Arbitration round 16 9 Arbitration slot 16 9 Arithmetic 2 1 Automatic refill 16 12 Autoscan 16 16 B B Register 2 3 Baud rate generator 12 11 Fractional divider Fractional divider mode 12 14 Normal divider mode 12 15 Bit protection scheme 3 19 Bitaddressable 3 16 Boot options 7 8 BSL mode 7 8 OCDS mode 7 8 User mode 7 8 User s Manual Boot ROM 3 1 Boot ROM operating mode 3 41 BootStrap Loader Mode 3 42 OCDS mode 3 43 User JTAG mode 3 43 User mode 3 42 Booting scheme 7 8 Bootstrap loader 3 42 4 9 4 14 18 1 Fast LIN BSL 18 24 LIN BSL 18 16 Communication structure 18 17 Mode selection 18 19 MultiCAN BSL 18 28 Communication protocol 18 28 Message object 18 29 Response code 18 6 UART BSL 18 8 Communication structure 18 9 Mode selection 18 10 Brownout reset 7 6 Buffer mechanism 4 5 C CAN Block diagram 15 1 MultiCAN Bit timing 15 8 Block diagram 15 4 Interrupt structure 15 6 Low Power Mode 15 44 Message acceptance filtering 15 21 Message object data handling 19 1 V1 1 2007 05 XC886 888CLM Cinfineon 15 27 Message object FIFO 15 34 Message object functionality 15 33 Message object interrupts 15 23 Message object lists 15 13 Node control 15 8 Node interrupts 15 11 Register map 15 46 Registers Offset addresses 15 45 MultiCAN registers LISTI 15 54 MCR 15 52 MITR 15 5
441. nes The port registers must be programmed for alternate output and input selection When switching between master and slave modes port registers must be reprogrammed User s Manual 12 38 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 3 1 6 Baud Rate Generation The serial channel SSC has its own dedicated 16 bit baud rate generator with 16 bit reload capability allowing baud rate generation independent of the timers Figure 12 16 shows the baud rate generator 16 Bit Reload Register MS_CLK SS_CLK in Master Modeg f 2 MS_ CLK max PCLK fss CLK max IN Slave Mode lt fpok 4 Figure 12 16 SSC Baud rate Generator The baud rate generator is clocked with the module clock fpc The timer counts downwards Register BR is the dual function Baud rate Generator Reload register Reading BR while the SSC is enabled returns the contents of the timer Reading BR while the SSC is disabled returns the programmed reload value In this mode the desired reload value can be written to BR Note Never write to BR while the SSC is enabled The formulas below calculate either the resulting baud rate for a given reload value or the required reload value for a given baud rate Baud rat i BR 1 ea lal 2 x lt BR gt 1 2 x Baud rate lt BR gt represents the contents of the reload register taken as an unsigned 16 bit integer while baud rate is equal to fus cLKss clk aS Shown in Figure
442. next conversion The priority of each source can be programmed individually to obtain the required flexibility to cover the desired range of applications e Control registers for each of the eight channels that define the behavior of each analog input such as the interrupt behavior a pointer to a result register a pointer to a channel class etc e An input class register that delivers general channel control information Sample time from a centralized location e Four result registers instead of one result register per analog input channel for Storing the conversion results and controlling the data reduction e A decimation stage for conversion results adding the incoming result to the value already stored in the targeted result register This stage allows fast consecutive conversions without the risk of data loss for slow CPU clock frequency parallel request source 1 _ channel contol 7 me arbitration slot 1 arbiter channel controlO control 0 H me request source 0 me slot 0 E analog input 7 analog input 0 result register 3 result register 0 data reduction Figure 16 4 ADC Block Diagram User s Manual 16 8 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 1 Request Source Arbiter The arbiter can operate in two modes that are selectable by bit ARBM e Permanent arbitration In this mode the arbiter will continuously poll the request sources even when there
443. ng interrupt status flags in register IS In order to monitor the selected capture events at the CCPOSx inputs in the multi inout capture modes the CC6xST bits of the corresponding channel are set when detecting the selected event The interrupt status bits and the CC6xST bits must be reset by software Register T12 represents the counting value of timer T12 It can only be written while the timer 112 is stopped Write actions while 112 is running are not taken into account Register T12 can always be read by software User s Manual 14 45 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 In edge aligned mode 112 only counts up whereas in center aligned mode 112 can count up and down T12L Timer T12 Counter Register Low Reset Value 00 7 6 5 4 3 2 1 0 rwh Field Bits Type Description T12CVL 7 0 rwh_ Timer T12 Counter Value Low Byte This register represents the lower 8 bit counter value of timer T12 T12H Timer T12 Counter Register High Reset Value 00 7 6 5 4 3 2 1 0 rwh Field Description T12CVH ee M Timer T12 Counter Value High Byte This register represents the upper 8 bit counter value of timer T12 Note While timer T12 is stopped the internal clock divider is reset in order to ensure reproducible timings and delays User s Manual 14 46 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 T12PRL Timer T12 Period Register Low Reset Value 00 7 6 9
444. nge breakpoint on HWBPO lt Instruction Address lt HWBP1 e Breakpoint 2 One equal breakpoint on Instruction Address HWBP2 or One range breakpoint on HWBP2L lt IRAM Read Address lt HWBP2H e Breakpoint 3 One equal breakpoint on Instruction Address HWBP3 or One range breakpoint on HWBP3L lt IRAM Write Address lt HWBP3H Setting both values for a range breakpoint to the same address leads to generation of an equal breakpoint 17 3 1 2 Software Breakpoints These breakpoints use the XC800 specific not 8051 standard TRAP instruction decoded by the core while at the same time the TRAP_EN bit within the Extended Operation EO register is setto 1 Upon fetching a TRAP instruction a Break Before Make breakpoint is generated and the relevant Break Action is taken The software breakpoints are in fact similar in behavior to the equal breakpoints on Instruction address except that they are raised by a program code instead of specialized compare logic An unlimited number of software breakpoints can be set by replacing the original instruction opcodes in the user program However this is possible only at addresses where a writable memory RAM Flash is implemented User s Manual 17 5 V1 1 2007 05 OCDS V 1 0 Cinfin eon XC886 888CLM On Chip Debug Support Note In order to continue user program execution after the debug event an external Debugger must restore the original opcode at the address of
445. ns programmed as input so only one slave can put its data onto the master s receive line Only the receiving of data from the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected Slave then switches its MRST line to output until it gets a de selection signal or command User s Manual 12 34 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces e The slaves use open drain output on MRST This forms a wired AND connection The receive line needs an external pull up in this case Corruption of the data on the receive line sent by the selected slave is avoided when all slaves not selected for transmission to the master send ones only Because this high level is not actively driven onto the line but only held through the pull up device the selected slave can pull this line actively to a low level when transmitting a zero bit The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave After performing the necessary initialization of the SSC the serial interfaces can be enabled For a master device the clock line will now go to its programmed polarity The data line will go to either O or 1 until the first transfer starts After a transfer the data line will always remain at the logic level of the last transmitted dat
446. nter Register may be read and written CAN Analyze Mode If this bit is set then the CAN node operates in Analyze Mode This means that messages may be received but not transmitted No acknowledge is sent on the CAN bus upon frame reception Active error flags are sent recessive instead of dominant The transmit line is continuously held at recessive 1 level Bit CALM can be written only while bit INIT is set h 15 61 V1 1 2007 05 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Field Bits Type Description 0 31 8 r Reserved 5 Read as 0 should be written with O User s Manual 15 62 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller The Node Status Register NSRx reports errors as well as successfully transferred CAN frames NSRx x 0 1 Node x Status Register Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 a r 15 14 13 LOE LLE i ALE jo T RT r rh rwh rwh rwh Field Bits Type Description LEC 2 0 rwh Last Error Code This bit field indicates the type of the last most recent CAN error The encoding of this bit field is described in Table 15 8 TXOK Message Transmitted Successfully 0 No successful transmission since last most recent flag reset 1 A message has been transmitted successfully error free and acknowledged by at least another node TXOK must be reset by software write 0 W
447. ntrol Register CF Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw Field Bits Type Description ETRSELx External Trigger Selection for Request Source x x 0 1 This bit field defines which external trigger input signal is selected 000 The trigger input ETRXxO is selected 001 The trigger input ETRx1 is selected 010 The trigger input ETRx2 is selected 011 The trigger input ETRx3 is selected 100 The trigger input ETRx4 is selected 101 The trigger input ETRXx5 is selected 110 The trigger input ETRXx6 is selected 111 The trigger input ETRx7 is selected SYNENx 7 6 rw Synchronization Enable x 0 1 0s Synchronizing stage is not in external trigger input REQTRx path 1g Synchronizing stage is in external trigger input REQTRx path User s Manual 16 38 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 7 4 Channel Control Registers The channel control registers contain bits that select the targeted result register and control the limit check mechanism Register CHCTRx defines the settings for the input channel x CHCTRx x 0 7 Channel Control Register x CA X 1 Reset Value 00 7 6 5 4 3 2 1 0 r rw r rw Field Description RESRSEL 0 Result Register Selection This bit field defines which result register will be the target of a conversion of this channel 00 The result register O is selected O01 The result register 1 is selected 10 The result r
448. o a maximum of fecug 128 and is configured by bit field T13CLK In order to support higher clock frequencies an additional prescaler factor of 1 256 can be enabled for the prescaler of 113 if bit T13PRE 1 The T13 shadow transfer in case of a period match is enabled by bit STE13 During the T13 shadow transfer the contents of register CC63SR are transferred to register CC63R Both registers can be read by software while only the shadow register can be written by software The bits CC63PS T13IM and PSL63 have shadow bits The contents of these shadow bits are transferred to the actually used bits during the 113 shadow transfer Write actions target the shadow bits while read actions deliver the value of the actually used bits zero match period match T13PR compare match T13 shadow transfer CC63R H lt H CC 3SR counter register 113 Taca Figure 14 9 T13 Overview CCU6_t13_overv Timer T13 counts according to the same counting and switching rules as timer T12 in edge aligned mode Figure 14 9 shows an overview of Timer T13 14 1 2 1 Timer Configuration Register T13 represents the counting value of timer T13 It can be written only while the timer T13 is stopped Write actions are not taken into account while T13 is running Register T13 can always be read by software Timer T13 supports only edge aligned mode counting up Timer T13 can be started and stopped by using bit T13R by hardware or software User s M
449. o as Phase 1 P1 and Phase 2 P2 that correspond to two different CPU states A CPU state within an instruction is denoted by reference to the machine cycle and state number e g C2P1 is the first clock period within machine cycle 2 Memory accesses take place during one or both phases of the machine cycle SFR writes only occur at the end of P2 An instruction takes one two or four machine cycles to execute Registers are generally updated and the next opcode read at the end of P2 of the last machine cycle for the instruction With each access to the Flash memory instruction execution times are extended by one machine cycle one wait state starting from either P1 or P2 Figure 2 2 shows the fetch execute timing related to the internal states and phases Execution of an instruction occurs at C1P1 For a 2 byte instruction the second reading starts at C1P1 Users Manual 2 6 V1 1 2007 05 Processor Architecture V 1 0 Cinfin eon XC886 888CLM Processor Architecture Figure 2 2 a shows two timing diagrams for a 1 byte 1 cycle 1 x machine cycle instruction The first diagram shows the instruction being executed within one machine cycle since the opcode C1P2 is fetched from a memory without wait state The second diagram shows the corresponding states of the same instruction being executed over two machine cycles instruction time extended with one wait state inserted for opcode fetching from the Flash memory Figure 2 2 b show
450. oads the PC Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is important because it informs the processor that the program has left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system on the assumption that an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged User s Manual 5 14 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System 5 5 Interrupt Response Time Due to an interrupt event of the various sources of an interrupt node its corresponding request signal will be sampled active at phase 2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be the next instruction to be executed The call itself takes two machine cycles Thus a minimum of three complete machine cycles will elapse from activation of the interrupt request to the beginning of execution of the first instruction of the service routine as shown in Figure 5 9 i D 1 instruction at Interrupt vector nterrupt reques request las
451. object after storing the received frame in the source is copied to the gateway destination object Applicable only to a gateway source object ignored in other nodes Field IDC DLCC 0 Data Length Code Copy 0 Data length code is not copied 1 Data length code of the gateway source object after storing the received frame in the source is copied to the gateway destination object Applicable only to a gateway source object ignored in other nodes DATC Data Copy 0 Data fields are not copied 1 Data fields in registers MODATALn and MODATAHn of the gateway source object after storing the received frame in the source are copied to the gateway destination Applicable only to a gateway source object ignored in other nodes RXIE 6 Receive Interrupt Enable RXIE enables the message receive interrupt of message object n This interrupt is generated after reception of a CAN message independent of whether the CAN message is received directly or indirectly via a gateway action 0 Message receive interrupt is disabled 1 Message receive interrupt is enabled Bit field MOIPRn RXINP selects the interrupt output line which becomes activated at this type of interrupt User s Manual 15 87 V1 1 2007 05 MultiCAN V1 0 Cinfineon Field TXIE j FRREN User s Manual MultiCAN V1 0 XC886 888CLM Controller Area Network MultiCAN Controller Description Transmit Interrupt Enable TXIE enables the message
452. odules If it is followed by the word module as in UART module it is used to represent the first UART module 12 1 1 UART Modes The UART can be used in four different modes In mode O it operates as an 8 bit shift register In mode 1 it operates as an 8 bit serial port In modes 2 and 3 it operates as a 9 bit serial port The only difference between mode 2 and mode 3 is the baud rate which is fixed in mode 2 but variable in mode 3 The variable baud rate is set by either the underflow rate on the dedicated baud rate generator or by the overflow rate on Timer 1 The different modes are selected by setting bits SMO and SM1 to their corresponding values as shown in Table 12 1 Table 12 1 UART Modes 0 Mode0 eit sit register fra 0 For UART1 module the baud rate is fixed at foc x 64 12 1 1 1 Mode 0 8 Bit Shift Register Fixed Baud Rate In mode 0 the serial port behaves as an 8 bit shift register Data is shifted in through RXD and out through RXDO while the TXD line is used to provide a shift clock which can be used by external devices to clock data in and out The transmission cycle is activated by a write to SBUF One machine cycle later the data has been written to the transmit shift register with a 1 at the 9th bit position For the next seven machine cycles the contents of the transmit shift register are shifted right one position and a zero shifted in from the left so that when the MSB of the data byte is at
453. of a new bit time The value is sampled during the SOF bit of a new frame The sampled value is visible in the CFC field Bit Timing Mode The available bit timing measurement modes are shown in Table 15 9 If CFCIE is set then an interrupt on request node x where x is the CAN node number is generated with a CFC update CFMOD 20 19 CAN Frame Counter Mode This bit field determines the operation mode of the frame counter 00 Frame Count Mode The frame counter is incremented upon the reception and transmission of frames 01 Time Stamp Mode The frame counter is used to count bit times 10 Bit Timing Mode The frame counter is used for analysis of the bit timing 11 Reserved CFCIE 22 rw CAN Frame Count Interrupt Enable CFCIE enables the CAN frame counter overflow interrupt of CAN node x 0 CAN frame counter overflow interrupt is disabled 1 CAN frame counter overflow interrupt is enabled Bit field NIPRx CFCINP selects the interrupt output line that is activated at this type of interrupt User s Manual 15 73 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Field Description CFCOV rwh_ CAN Frame Counter Overflow Flag Flag CFCOV is set upon a frame counter overflow transition from FFFF to 0000 In bit timing analysis mode CFCOV is set upon an update of CFC An interrupt request is rr if CFCIE 1 No overflow has occurred since last flag reset
454. ogram memory sizes power supply voltage temperature and quality profiles Automotive or Industrial as shown in Table 1 2 Table 1 2 Device Profile Sales Type Device Program Power Temp Type Memory Supply erature Kbytes V Profile C SAK XC886 888 8FFA 5V Flash 32 5 0 40to125 _ Automotive SAK XC886 888 6FFA 5V Flash 24 5 0 40to125 Automotive SAF XC886 888 8FFA 5V Flash 32 5 0 40to85 Automotive SAF XC886 888 6FFA 5V Flash 24 5 0 40to85 Automotive SAF XC886 888 8FFI 5V Flash 32 5 0 40to85 Industrial SAF XC886 888 6FFI 5V Flash 24 5 0 40to85 Industrial SAK XC886 888 8FFA 3V3 Flash 32 3 3 40to125 Automotive SAK XC886 888 6FFA 3V3 Flash 24 3 3 40to125 Automotive SAF XC886 888 8FFA 3V3 Flash 32 3 3 40to85 Automotive SAF XC886 888 6FFA 3V3 ee Automotive SAF XC886 888 8FFI 3V3 Flash 32 33 40 to 85 Industrial SAF XC886 888 6FFI 3V3 tee a 40 to 85 Industrial Note The asterisk above denotes the device configuration letters from Table 1 1 Corresponding ROM derivatives will be available on request The term XC886 888 in this document refers to all devices of the XC886 888 family unless stated otherwise Quality Profile User s Manual 1 3 V1 1 2007 05 Introduction V 1 1 Cinfin eon XC886 888CLM Introduction 1 1 Feature Summary The following list summarizes the main features of the X
455. om the host to the microcontroller by Data Block and EOT Block which are described below The Data Block 01 Data Block Program Code Checksum 1 byte Block_Length 2 bytes 1 byte Description Program Code The program code has a length of Block_Length 2 byte where the Block _Length is provided in the previous Header Block Note No empty Data Block is allowed The EOT Block 02 EOT Block Last_Codelength Program Code Checksum 1 byte 1 byte 1 byte Description Last_Codelength This byte indicates the length of the program code in this EOT Block Program Code The last program code to be sent to the microcontroller Not used The length is Block_Length 3 Last_Codelength These bytes are not used and they can be set to any value 3 The minimum and maximum Block _Length for is 34 bytes and 98 bytes respectively for Mode 2 if D Flash is targeted For P Flash the Block_Length is always 66 bytes User s Manual 18 11 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader 18 1 2 4 The Activation of Modes 1 3 and F Modes 1 and 3 are used to execute a user program in the XRAM Flash of the microcontroller at OFOOO and 0000 respectively while Mode F is used to enter OCDS UART Mode The header block has the following structure The Header Block 00 01 03 0F Checksum H Header Block Mode 1 3 F Not Used 5 Bytes 1 byte Mode Data Description Not used The fiv
456. on Note For the XC886 bits P2 P4 P5 P6 and P7 are not available for use as their corresponding pads are not bonded P4 DATA Port 4 Data Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn _ 4 Pin n Data Value n 0 7 Port 4 pin n data value O default Port 4 pin n data value 1 P4 DIR Port 4 Direction Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn _ 4 Pin n Direction Control n 0 7 Direction is set to input default Direction is set to output User s Manual 6 43 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports P4 OD Port 4 Open Drain Control Register Reset Value 00 7 6 5 A 3 2 1 0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Port 4 Pin n Open Drain Mode n 0 7 0 Normal mode output is actively driven for 0 and 1 states default 1 Open drain mode output is actively driven only for O state P4 PUDSEL Port 4 Pull Up Pull Down Select Register Reset Value FF 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Select Port 4 Bit n n 0 7 0 Pull down device is selected 1 Pull up device is selected User s Manual 6 44 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports P4 PUDEN Port 4 Pull Up Pull Down Enable Register Reset Value See note below 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Fi
457. on 1 ites 4 bytes C0 Mode data description can be referred at Section 18 1 2 5 18 1 3 6 The Activation of Mode 6 Mode 6 is used to enable or disable Flash protection via the given user password The header block for this mode has the following structure The Header Block 00 ne Mode Data 5 bytes Checka un Header Mode 6 User Password Not Used 1 byte Block 1 byte 4 bytes Mode data description can be referred at Section 18 1 2 6 User s Manual 18 22 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader 18 1 3 7 The Activation of Mode A Mode A is used to get 4 bytes data determined by the Option byte in the header block The header block for this mode has the following structure The Header Block Mode Data 5 bytes 00 Checksum 0A l Sie Mode A Not Used Option 1 byte ock 4 bytes 1 byte Mode data description can be referred at Section 18 1 2 7 18 1 3 8 LIN Response Protocol to the Host The microcontroller replies with a Response Block indicating its status when the host sends a Slave Response Header LIN frame A Response transfer block 9 bytes long fixed consists of four parts NAD Response Not Used Checksum 1 byte 1 byte 6 bytes 1 byte NAD Node Address for Diagnostic which specifies the address of the active slave node Response Acknowledgement or Error Status indication byte See Section 18 1 1 3 Not Used These 6 bytes are ignor
458. on delay GLOBCTR Global Control Register CA Reset Value 30 7 6 5 4 3 2 1 0 mala rw rw rw r Field Description CTC CoE 4 Conversion Time Control This bit field defines the divider ratio for the divider stage of the internal analog clock fang This clock provides the internal time base for the conversion and sample time calculations 00s Sano 1 2 x fapca Ols fapci 1 3 x faneca 108 fapnci 1 4 x fapca 11s fapc 1 82 x fapca default DW Data Width This bit defines the conversion resolution Os The result is 10 bits wide default 1 The result is 8 bits wide User s Manual 16 33 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Field Description ANON Analog Part Switched On This bit enables the analog part of the ADC module and defines its operation mode Os The analog part is switched off and conversions are not possible To achieve minimal power consumption the internal analog circuitry is in its power down state and the generation of fapc is stopped 1 The analog part of the ADC module is switched on and conversions are possible The automatic power down capability of the analog part is disabled 0 3 0 Reserved Returns 0 if read should be written with O User s Manual 16 34 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Register GLOBSTR contains bits that indicate the current status of a conversion GLOBSTR Global Status R
459. on CAN applications which requires the oscillator to have a frequency deviation of less than 1 5 XC886 888 supports four oscillator frequency values which the user can enter at the top address of the P Flash banks The usage for user defined parameter is described in Section 18 2 3 In the software communication section three main phases have been identified namely the Autobaud Acknowledgement and Data Reception phases All three phases involves the transmission and reception of CAN Message Objects The Autobaud phase is started on entry to MultiCAN BSL where the host sends a Host Command Message to the microcontroller The microcontroller will determine the current CAN network baud rate and configure the baud rate of the CAN node accordingly to enable the communication channel In the Acknowledgement Phase the microcontroller sends an Acknowledge Message to the host to establish the communication channel With the communication channel established the Data Reception Phase can now be started The host sends Data Message Objects to download the code into XRAM and execute the code from there In the XC886 888 there are 1 5 Kbytes of XRAM available for program execution The following assumptions are introduced to keep the MultiCAN BSL implementation simple e Host and the XC886 888 are the only CAN node in the CAN network Point to Point Connection e CAN Node 0 P1 0 P1 1 on the XC886 888 is used for this mode e XC886 888 ex
460. on XC886 888CLM Serial Interfaces 12 3 5 Register Description All SSC register names described in this section are referenced in other chapters of this document with the module name prefix SSC_ e g SSC_PISEL 12 3 5 1 Port Input Select Register The PISEL register controls the receiver input selection of the SSC module PISEL Port Input Select Register Reset Value 00 7 6 5 4 3 2 1 0 tl rw rw rw r Field Bits Type Description MIS rw Master Mode Receiver Input Select 0 Receiver input P1 4 MRST_0 is selected 1 Receiver input P0 5 MRST_1 is selected SIS 1 rw Slave Mode Receiver Input Select 0 Receiver input P1 8 MTSR_0 is selected 1 Receiver input P0 4 MTSR_1 is selected CIS 2 rw Slave Mode Clock Input Select 0 Clock input P1 2 SCK_0 is selected 1 Clock input P0 3 SCK_1 is selected 0 7 3 r Reserved Returns 0 if read should be written with O User s Manual 12 45 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 3 5 2 Configuration Register The operating mode of the serial channel SSC is controlled by the control register CON This register contains control bits for mode and error check selection and status flags for error identification Depending on bit EN either control functions or status flags and master slave control are enabled CON EN 0 Programming Mode CONL Control Register Low Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw Field Bits
461. on bus According to the setting of FRREN in the gateway destination object there are two capabilities to handle remote requests that appear on the destination side assuming that the source object is a receive object and the destination is a transmit object i e DlReource O and Dl Rogestination 1 FRREN 0 in the Gateway Destination Object 1 Aremote frame is received by gateway destination object 2 TXRQ is set automatically in the gateway destination object 3 A data frame with the current data stored in the destination object is transmitted on the destination bus FRREN 1 in the Gateway Destination Object 1 Aremote frame is received by gateway destination object 2 TXRQ is set automatically in the gateway source object must be referenced by CUR pointer of the destination object 3 A remote request is transmitted by the source object which is a receive object on the source CAN bus 4 The receiver of the remote request responds with a data frame on the source bus 5 The data frame is stored in the source object 6 The data frame is copied to the destination object gateway action 7 TXRQ is set in the destination object assuming GDFS ource 1 8 The new data stored in the destination object is transmitted on the destination bus as response to the initial remote request on the destination bus User s Manual 15 40 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN
462. onal The user should disable the Watchdog Timer WDT before the system enters the idle mode otherwise it will generate an internal reset when an overflow occurs and thus will disrupt the idle mode The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The port pins hold the logical state they had at the time the idle mode was activated Software requests idle mode by setting the bit PCON IDLE to 1 The system will return to active mode on occurrence of any of the following conditions e The idle mode can be terminated by activating any enabled interrupt The CPU operation is resumed and the interrupt will be serviced Upon RETI instruction the core will return to execute the next instruction after the instruction that sets the IDLE bit to 1 e An external hard reset signal RESET is asserted 8 1 2 Slow Down Mode The slow down mode is used to reduce power consumption by decreasing the internal clock in the device The slow down mode is activated by setting the bit SD in SFR PMCONO The bit field CMCON CLKREL is used to select a different slow down frequency The CPU and peripherals are clocked at this lower frequency The slow down mode is terminated by clearing bit SD The slow down mode can be combined with the idle mode by performing the following sequence 1 The slow down mode is activated by setting the bi
463. onverter stage e g capacitor network and comparator as part of the ADC e Digital control part of the analog converter stage for controlling the analog to digital conversion process and generating the conversion result The digital part defines and controls the overall functionality of the ADC module and includes e Digital data and conversion request handling for controlling the conversion trigger mechanisms and handling the conversion results e Bus interface to the device internal data bus for controlling the interrupts and register accesses The block diagram of the ADC module is shown in Figure 16 1 The analog input channel x x 0 7 is available at port pin P2 x ANx analog part digital part analog input 0 data result AD converter handling analog input 7 conversion request control y control analog clock fron digital clock f 5 Figure 16 1 Overview of ADC Building Blocks User s Manual 16 2 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 2 Clocking Scheme A common module clock fpc generates the various clock signals used by the analog and digital parts of the ADC module franca S input clock for the analog part franc IS internal clock for the analog part defines the time base for conversion length and the sample time This clock is generated internally in the analog part based on the input clock fapca to generate a correct duty cycle
464. or V 1 2 1 Cinfine on XC886 888CLM CORDIC Coprocessor 11 5 Register Map The CORDIC Coprocessor registers are located in the mapped Special Function Register SFR area Table 11 6 lists the addresses of these registers Note All CORDIC Coprocessor register names described in this section shall be referenced fully with the module name prefix CD_ Table 11 6 Register Summary for CORDIC Coprocessor Name Description HEX HEX CD_CORDXL 9A 00 CORDIC X Data Low Byte CD_CORDXH 9B 00 CORDIC X Data High Byte CD_CORDYL 9C 00 CORDIC Y Data Low Byte CD_CORDYH 9D 00 CORDIC Y Data High Byte CD_CORDZL 9E 00 CORDIC Z Data Low Byte CD_CORDZH 9F J00 CORDIC Z Data High Byte CD_STATC Ao 00 CORDIC Status and Data Control Register CD_CON CORDIC Control Register User s Manual 11 15 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfin eon XC886 888CLM CORDIC Coprocessor 11 6 Register Description 11 6 1 Control Register The CD_CON register allows for the general control of the CORDIC Coprocessor Write action to this register while CD_STATC BSY is set has no effect CD_CON CORDIC Control Register Reset Value 62 7 6 5 4 3 2 1 0 ase em a rw rw rw rw rw rwh Field Bits Type Description ST rwh_ Start Calculation lf ST MODE 1 set ST to start a CORDIC calculation Is effective only while BSY is not set This bit may be set with the other bits of this register in one write access Cleared by har
465. or Flag FDCON ERRSYN is set or e The Break Field Flag FDCON BRK is set but the End of SYN Byte Flag FDCON EOFSYN and the SYN Byte Error Flag FDCON ERRSYN are not set User s Manual 12 30 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 3 High Speed Synchronous Serial Interface The SSC supports full duplex and half duplex synchronous communication The serial clock signal can be generated by the SSC internally master mode using its own 16 bit baud rate generator or can be received from an external master slave mode Data width shift direction clock polarity and phase are programmable This allows communication with SPl compatible devices or devices using other synchronous serial interfaces Data is transmitted or received on lines TXD and RXD which are normally connected to the pins MTSR Master Transmit Slave Receive and MRST Master Receive Slave Transmit The clock signal is output via line MS_CLK Master Serial Shift Clock or input via line SS_CLK Slave Serial Shift Clock Both lines are normally connected to the pin SCLK Transmission and reception of data are double buffered Figure 12 11 shows the block diagram of the SSC Baud rate Clock Generator Control RIR eee Ok mw Receive Int Request ontrol Bloc Register CON an Transmit Int Request p Error Int Request Status Control _ TXD Master RXD Slave Toman Pin 8 Bit Shift Register Control TXD Slave
466. or T13RR or it is set reset by hardware according to the function defined by bit fields T13SSC T13TEC and T13TED 0 j 0 j Timer T13 is stopped Timer T13 is running XC886 888CLM Capture Compare Unit 6 A concurrent set reset action on T13R from T13SSC TI3TEC T13RR or T13RS will have no effect The bit T13R will remain unchanged Timer T13 Shadow Transfer Enable Bit STE13 enables or disables the shadow transfer of the T13 period value the compare value and passive State select bit and level from their shadow registers to the actual registers if a T13 shadow transfer event is detected Bit STE13 is cleared by hardware after the shadow transfer A 113 shadow transfer event is a period match The shadow register transfer is disabled The shadow register transfer is enabled 0 j 14 61 V1 1 2007 05 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Description 0 LJ 6 Reserved Returns 0 if read should be written with 0 Note A write action to the bit fields T12CLK or T12PRE is only taken into account when the timer T12 is not running T12R 0 A write action to the bit fields T13CLK or T13PRE is only taken into account when the timer T13 is not running T13R 0 Register TCTR2 controls the single shot and the synchronization functionality of both timers T12 and T13 Both timers can run in single shot mode In this mode they stop their counting sequence automatically after one counting period wi
467. orage fields STx x 0 3 for the save and restore action of the current page setting By indicating which storage bit field should be used in parallel with the new page value a single write operation can e Save the contents of PAGE in STx before overwriting with the new value this is done at the beginning of the interrupt routine to save the current page setting and program the new page number or e Overwrite the contents of PAGE with the contents of STx ignoring the value written to the bit positions of PAGE this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred STNR value update from CPU Figure 3 6 Storage Elements for Paging With this mechanism a certain number of interrupt routines or other routines can perform page changes without reading and storing the previously used page information The use of only write operations makes the system simpler and faster Consequently this mechanism significantly improves the performance of short interrupt routines The XC886 888 supports local address extension for e Parallel Ports e Analog to Digital Converter ADC e Capture Compare Unit 6 CCU6 e System Control Registers User s Manual 3 14 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization 3 5 2 1 Page Register The page register has the following definition MOD_ PAGE Page Register for module MOD Reset Value 00
468. ore the counter overflows Servicing is performed through refresh operation setting bit WDTRS to 1 This reloads the timer with the start value and normal operation continues WDTRST lf the WDT is not serviced before the timer overflows a system malfunction is assumed and normal mode is terminated A WDT NMI request FNMIWDT is then asserted and prewarning is entered The prewarning lasts for 30 count During the prewarning period refreshing of the WDT is ignored and the WDT cannot be disabled A reset WDTRST of the XC886 888 is imminent and can no longer be avoided The occurrence of a WDT reset is indicated by the bit WDTRST which is set to 1 once hardware detects the assertion of the signal WDTRST If refresh happens at the same time an overflow occurs WDT will not go into prewarning period The WDT must be serviced periodically so that its count value will not overflow Servicing the WDT clears the low byte and reloads the high byte with the preset value in bit field WDTREL Servicing the WDT also clears the bit WOTRS The WDT has a programmable window boundary which disallows any refresh during the WDT s count up A refresh during this window boundary constitutes an invalid User s Manual 9 2 V1 1 2007 05 Watchdog Timer V1 0 Cinfin eon XC886 888CLM Watchdog Timer access to the WDT and causes the WDT to activate WDTRST although no NMI request is generated in this instance The window boundary is from 0000
469. ort 3 Open Drain Control Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn H 3 Pin n Open Drain Mode n 0 7 Normal mode output is actively driven for 0 and 1 states default Open drain mode output is actively driven only for O state P3_PUDSEL Port 3 Pull Up Pull Down Select Register Reset Value BF 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn Up Pull Down Select Port 3 Bit n n 0 7 Pull down device is selected Pull up device is selected Note Pull down device is activated for Pin P3 6 when reset is active In the BootROM Start up procedure the pull down device is deactivated so that Pin P3 6 becomes tristate User s Manual 6 37 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports P3 PUDEN Port 3 Pull Up Pull Down Enable Register Reset Value 40 7 6 5 4 3 2 1 0 EARS EISELE rw rw rw rw rw rw rw rw Field Description Pn iaa Up Pull Down Enable at Port 3 Bit n n 0 7 Pull up or Pull down device is disabled Pull up or Pull down device is enabled P3 _ALTSELn n 0 1 Port 3 Alternate Select Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn Pin Output Functions n 0 7 Configuration of Px_ALTSELO Pn and Px ALTSEL1 Pn for GPIO or alternate settings 00 Normal GPIO 10 Alternate Select 1 01 Alternate Select 2 11 Alternate Select 3 User s Manual 6 38 V1 1 2007 05 Parallel Ports V 1 0
470. ort 3 input and output functions are shown in Table 6 10 Table 6 10 Port 3 Input Output Functions Port Pin P3 0 Input GPI ALT1 ALT2 ALT3 Output GPO ALT1 ALT2 ALT 3 Connected Signal s From to Module P3_DATA PO CC60_0 CCU6 CCPOS1_2 CCU6 P3_DATA PO CC60_0 CCU6 RXDO1_ 1 UART 1 User s Manual 6 32 V1 1 2007 05 Parallel Ports V 1 0 Infineon XC886 888CLM i Parallel Ports Table 6 10 Port 3 Input Output Functions cont d Port Pin Input Output P3 1 Input Connected Signal s From to Module GP P3_DATA P1 gt gt gt Tm e 4 4 44 P CCPOSO0 2 CCU6 CC61 2 CCU6 Output GPO P3 DATA P1 COUT60_0 CCU6 CC61 2 CCU6 TXD1 1 UART Input GPI P3 DATA P2 CC61_0 CCU6 CCPOS2 2 CCU6 RXDC1 1 MultiCAN RXD1_1 UART P3 DATA P2 CC61_0 CCU6 gt gt gt Tm P e H OINI Q Output PO Sau OO a M gt gt gt mT P e 4 4 44 PM Q D gt IDP D gt i Lr D ri P YS 4 4 4 sai 4 4 4a olin oO PM WINI A oO PO P Input P3 DATA P3 Output GPO P3_ DATA P3 COUT61_0 CCU6 TXDC1_1 MultiCAN User s Manual 6 33 V1 1 2007 05 Parallel Ports V 1 0 Infineon XC886 888CLM i Parallel Ports Table 6 10 Port 3 Input Output Functions cont d Port Pin Input Output P3 4 Input Connected Signal s From to Module P3_DATA P4 CC62_0 CCU6 T2EX1_0 Timer 21 RXDCO_1 MultiCAN Output GPO P3_DATA P4 CC62_0 CCU6 GP gt gt
471. output lines by programming the interrupt node pointer register INP User s Manual 14 25 V1 1 2007 05 CCU6B V 1 0 Cinfine on XC886 888CLM Capture Compare Unit 6 14 1 8 Low Power Mode If the CCU6 functionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit CCU_DIS in register PMCON1 as described below Refer to Chapter 8 1 4 for details on peripheral clock management PMCON1 Power Mode Control Register 1 Reset Value 00 7 6 5 4 3 2 1 0 oe CDC DIS CAN_DIS MDU_DIS T2_DIS SSC _DIS ADC_DIS r rw rw rw rw rw rw rw Field Description CCU DIS Disable Request Active high CCU6 is in normal operation default Request to disable the CCU6 0 oe len 0 if read should be written with O User s Manual 14 26 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 1 9 Module Suspend Control The timers of CCU6 Timer 12 and Timer 13 can be configured to stop their counting when the OCDS enters monitor mode see Chapter 17 3 by setting their respective module suspend bits T12SUSP and T13SUSP in SFR MODSUSP MODSUSP Module Suspend Control Register Reset Value 01 7 6 5 4 3 2 1 0 0 asus T2SUSP T13SUSP T12SUSP WOTSUSP rw rw rw rw rw r Field Bits Typ Description T12SUSP 1 rw Timer 12 Debug Suspend Bit 0 Timer 12 will not be suspended 1 Timer 12 will be suspended T13SUS
472. ow BtFea P7 Pe Ps Pa po P2 Pt pow rw ow ce pow ow ow i ole perea er re rs re V1 1 2007 05 infine on XC886 888CLM Memory Organization Table 3 8 Port Register Overview cont d Adar Register Name et 7 6 6 4 3 2 4 oo 3 PS_ALTSEL1 Reset 00 ree es P5 Alt te Select 1 R t P3_ALTSELO Reset 004 pra fe bee ee To e P3 Alt te S egister P3_ALTSELI Reset OOH pre e Fe fe e e e e P3 Al Select 1 R t P4_ALTSELO Reset OOH preoa or ee es e f ee f ee f r o P4 Alt te Select 0 R t Pcie eee peres a pete Pee e fe To oe ernate Selec egister we tye w ow ow ow ow ow ow w RMAP 0 PAGE 3 POOD onoo ceo OO St Feld A a i NEIEAEEENES P1OD Reset ony BtFied P7 Pe Ps Pa Ps pe Pi Po en Drain Control Register i e e ae i eee P5 OD Reset 00 BitFied P7 Pe Ps Pa Ps Pe Pi Po en Drain Control Register i WU e aie e eee P3 OD Reset 004 BitField P7 Pe Ps Pa Ps Pe Pi Po en Drain Control Register P a ea a ae aE ae PAOD Reset OOy BtFiea P7 Pe Ps Pa ps P2 Pi Po en Drain Control Register i type w ow Tow ow ow Tow ow ow 3 5 5 7 ADC Registers The ADC SFRs can be accessed in the standard memory area RMAP 0 Table 3 9 ADC Register Overview Addr Register Name Bt 7 6 5 4 3 2 1 oO RMAP 0 Di ADC_PAGE Reset 004 BitFild OP STNR o PAGE Page Register Type Type
473. own counting sequence is started and the timer counts down as in the previous counting sequence lf bit TZRHEN is set Timer 2 can only be started either by rising edge T2REGS 1 at pin T2EX and then proceed with the up counting or be started by falling edge T2ZREGS 0 at pin T2EX and then proceed with the down counting In this mode bit EXF2 toggles whenever an overflow or an underflow condition is detected This flag however does not generate an interrupt request User s Manual 13 16 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers FFFF 4 EXF2 Down count reload PREN iL PCLK re Te mer 2 Interrupt LZ cot Bitar Overflow C T2 0 THL2 M I rE g i Figure 13 6 Auto Reload Mode DCEN 1 User s Manual 13 17 V1 1 2007 05 Timers V 1 0 Cinfine on XC886 888CLM Timers 13 2 3 Capture Mode In order to enter the 16 bit capture mode bits CP RL2 and EXEN2 in register T2CON must be set In this mode the down count function must remain disabled The timer functions as a 16 bit timer and always counts up to FFFF after which an overflow condition occurs Upon overflow bit TF2 is set and the timer reloads its registers with 0000 The setting of TF2 generates an interrupt request to the core Additionally with a falling rising edge chosen by T2MOD EDGESEL on pin T2EX the contents of the timer register THL2 are captured into the RC2 register The external input is sample
474. pare channel with one output e 16 bit resolution maximum count frequency peripheral clock frequency e Can be synchronized to T12 e Interrupt generation at period match and compare match e Supports single shot mode Additional Features e Implements block commutation for Brushless DC drives e Position detection via Hall sensor pattern e Automatic rotational soeed measurement for block commutation e Integrated error handling e Fast emergency stop without CPU load via external signal CT RAP e Control modes for multi channel AC drives e Output levels can be selected and adapted to the power stage User s Manual 14 1 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 module kemel compare decoder dead multi channel 1 z time channel control control channel 2 clock control outpu select Hall input outpu select compare interrupt 1 3 24242 control p input foutputcontrol p input foutputcontrol output control 3 3 8 3 8 S18 18 5 a portcontroh a portcontroh Ly aes Ala AA AMAA LA LLA AA AA N44 AA AA N_Z CCU6_block diagram Figure 14 1 CCU6 Block Diagram User s Manual 14 2 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 1 Functional Description 14 1 1 Timer T12 The timer T12 is built with three channels in capture compare mode The input clock for timer T12 can be from fecus to a maximum of fecus 128 and is configured by bit field
475. pects to receive a standard CAN frame with message identifier of 0550p 18 2 1 Communication protocol Data is exchanged using Message Objects implemented with the standard CAN data frame 11 bit identifier as shown in Figure 18 6 Message Objects with other message identifiers are ignored by XC886 888 The data field in a standard CAN message is used to implement the communication protocol 1 CAN Message Object refers to a standard CAN data frame as defined in BOSCH CAN Specification 2 0B User s Manual 18 28 V1 1 2007 05 Bootstrap Loader V1 0 Cinfin eon XC886 888CLM Bootstrap Loader Control To ee Hi is a of Identifier Field RTR Bit IDE Bit Reserved 22 enath CRC Sequence ov Ries 11 bits 1 bit 1 Bit 1 Bit 15 Bits ct er i n A Bi Figure 18 6 Standard CAN frame format Communication is initiated by the host which continuously sends a Host Command Message Object until it receives an Acknowledgement Message Object from the microcontroller After the baud rate is determined and the acknowledgement is received by the host the host can activate the MultiCAN BSL operational mode by sending the Data Message Object All messages received from this point on will have their data bytes sequentially written into the XRAM starting at location FO00 The size of the internal XRAM is 1 5 kbytes which results in a maximum of 1535 8 bit instructions Once all messages have been received the CAN module will be reinit
476. performed successfully The results of a dynamic allocation command are written before the list controller starts the actual allocation process As soon as the results are available RBUSY becomes Inactive RBUSY 0 again while BUSY still remains active until completion of the command This allows the user to set up the new message object while it is still in the process of list allocation The access to message objects is not limited during ongoing list operations However any access to a register resource located inside the RAM delays the ongoing allocation process by one access cycle As soon as the command is finished the BUSY flag becomes inactive BUSY 0 and write accesses to the Panel Control Register are enabled again Additionally the No Operation command code is automatically written to the bit field PANCTR PANCMD A new command may be started any time when BUSY 0 All fields of the register PANCTR except BUSY and RBUSY may be written by the user This allows the register PANCTR to be saved and restored if the Command Panel is used within independent mutually interruptible interrupt routines If this is the case then any task that uses the Command Panel and that may interrupt another task also using the Command Panel should poll the BUSY flag until it becomes inactive and save the whole PANCTR register to a memory location before issuing a command At the end of the interrupt service routine it should restore PANCTR fro
477. prewarning has occurred User s Manual 5 30 V1 1 2007 05 Interrupt System V 1 0 Cinfine on XC886 888CLM Interrupt System Field Bits Type Description FNMIPLL 1 rwh PLL NMI Flag 0 No PLL NMI has occurred 1 PLL loss of lock to the external crystal has occurred FNMIFLASH 2 rwh Flash NMI Flag 0 No Flash NMI has occurred 1 Flash NMI has occurred FNMIOCDS 3 rwh OCDS NMI Flag 0 No OCDS NMI has occurred 1 Reserved FNMIVDD 4 rwh VDD Prewarning NMI Flag 0 No Vpp NMI has occurred 1 Vbp prewarning drop to 2 3 V has occurred FNMIVDDP 5 rwh VDDP Prewarning NMI Flag 0 No Vbpp NMI occurred 1 Vbpp prewarning drop to 4 0 V for external power supply of 5 0 V has occurred FNMIECC rwh ECC NMI Flag 0 No ECC error has occurred 1 ECC error has occurred 0 7 r Reserved Returns 0 if read should be written with O Register NMISR can only be cleared by software or reset to the default value after the power on reset hardware reset brownout reset The register value is retained on any other reset such as watchdog timer reset or power down wake up reset This allows the system to detect what caused the previous NMI User s Manual 5 31 V1 1 2007 05 Interrupt System V 1 0 Cinfine on XC886 888CLM Interrupt System 5 6 4 Interrupt Priority Registers Each interrupt source can be individually programmed to one of the four available priority levels Two pairs of interrupt priority registers are available to program the priorit
478. pt line to be mapped to this interrupt source An interrupt is only generated when interrupt enable bit MDUCON IE is 1 and the corresponding interrupt event occurs An interrupt request signal is always asserted positively for 2 clocks User s Manual 10 4 V1 1 2007 05 MDU V2 1 Cinfin eon XC886 888CLM Multiplication Division Unit int reset swt IRDY Completion of J1 Calculation to INT OO to INT _O1 Occurrence TL of Error int reset SW JL reset Figure 10 2 Interrupt Generation 10 3 Low Power Mode lf the MDU functionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit MDU_DIS in register PMCON1 as described below Refer to Chapter 8 1 4 for details on peripheral clock management PMCON1 Power Mode Control Register 1 Reset Value 00 7 6 9 4 3 2 1 0 oe CDC _ DIS CAN_DIS vouos T2_DIS CCU_DIS SSC DIS ADC_DIS r rw rw rw rw rw rw rw Field Bits Type Description MDU_DIS 4 rw MDU Disable Request Active high 0 MDU is in normal operation default 1 Request to disable the MDU Reserved Returns 0 if read should be written with 0 Users Manual 10 5 V1 1 2007 05 MDU V2 1 Cinfin eon XC886 888CLM Multiplication Division Unit 10 4 Register Map Table 10 2 lists the MDU registers with their addresses Table 10 2 MDU Registers SFR Address Name MDUCON B1 mapped MDU Control Register MDUSTAT MD
479. pt occurs the message object sets a bit in one of the MSPND register where the bit position is given by the MPN 4 0 field of the IPR register of the message object The register selection k is given by the bit 5 of MPN The register bits can be cleared by software write 0 Writing a 1 has no effect User s Manual 15 56 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Each Message Pending Register has a Message Index Register MSIDk associated with it The Message Index Register shows the active set pending bit with lowest bit position within groups of pending bits MSIDk k 0 1 Message Index Register k Reset Value 0000 0020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 INDEX r rh Field Bits Type Description INDEX 5 0 rh Message Pending Index The value of INDEX is given by the bit position i of the pending bit of MSPNDk with the following properties 1 MSPNDKk i amp IM i 1 2 i 0 or MSPNDK i 1 0 amp IM i 1 0 0 If no bit of MSPNDk satisfies these conditions then INDEX reads 100000z Thus INDEX shows the position of the first pending bit of MSPNDKk in which only those bits of MSPNDk that are selected in the Message Index Mask Register are taken into account 0 31 6 r Reserved Read as 0 should be written with O User s Manual 15 57 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Th
480. ption WDTRST rwh_ Watchdog Timer Reset Indication Bit 0 No watchdog timer reset occurred 1 Watchdog timer reset has occurred This bit can only be set by hardware and reset by software Reserved Returns 0 if read should be written with 0 User s Manual 7 10 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management 7 3 Clock System The XC886 888 clock system performs the following functions e Acquires and buffers incoming clock signals to create a master clock frequency e Distributes in phase synchronized clock signals throughout the system e Divides a system master clock frequency into lower frequencies for power saving mode 7 3 1 Clock Generation Unit The Clock Generation Unit CGU in the XC886 888 consists of an oscillator circuit and a Phase Locked Loop PLL In the XC886 888 the oscillator can be from either of these two sources the on chip oscillator 9 6 MHz or the external oscillator 4 MHz to 12 MHz The term oscillator is used to refer to both on chip oscillator and external oscillator unless otherwise stated After the reset the on chip oscillator will be used by default The external oscillator can be selected via software The PLL can convert a low frequency external clock signal from the oscillator circuit to a high speed internal clock for maximum performance Figure 7 6 shows the block diagram of CGU osc fall detect lock
481. quired 4 bytes Resource ACC R1 DPL DPH used destroyed User s Manual 4 21 V1 1 2007 05 Flash Memory V 1 0 Cinfin eon XC886 888CLM Interrupt System 5 Interrupt System The XC800 Core supports one non maskable interrupt NMI and 14 maskable interrupt requests In addition to the standard interrupt functions supported by the core e g configurable interrupt priority and interrupt masking the XC886 888 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources Supported and additional status registers for detecting and identifying the interrupt source The XC886 888 supports 14 interrupt vectors with four priority levels Twelve of these interrupt vectors are assigned to the on chip peripherals Timer 0 Timer 1 UART and SSC are each assigned one dedicated interrupt vector Timer 2 Timer 21 CORDIC MDU UART1 MultiCAN ADC CCU6 the Fractional Dividers and LIN share the other eight interrupt vectors Two of these interrupt vectors are also shared with External Interrupts 2 to 6 External interrupts O to 1 are each assigned one dedicated interrupt vector The Non Maskable Interrupt NMI is similar to regular interrupts except it has the highest priority over other regular interrupts when addressing important system events In the XC886 888 any one of the following six events can generate an NMI
482. r Field Description VF Valid Flag for Result Register x This bit indicates that the contents of the result _ x are valid The result register x does not contain valid data The result register x contains valid data RESULT 1 0 7 6 n Result This bit field contains the conversion result or the result of the data reduction filter 0 ir eee O if read should be written with 0 RESRxH x 0 3 Result Register x High CB x 2 Reset Value 00 7 6 5 4 3 2 1 0 rh Field Description RESULT 9 2 7 CONN rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter User s Manual 16 54 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Accumulated Read View RESRAx This view delivers the accumulated 9 bit or 11 bit conversion result and a 3 bit channel number The corresponding valid flag is cleared when the high byte of the register is accessed by a read command provided that bit RCRx VFCTR is set RESRAXL x 0 3 Result Register x View A Low CA X 2 Reset Value 00 7 6 3 4 3 2 1 0 r h Field a Description CHNR Channel Number This bit field contains the channel number of the latest register update DRC Data Reduction Counter This bit field indicates how many conversion results have still to be accumulated to generate the final result for data reduction Os The final result is available in the result regist
483. r Area Network MultiCAN Controller 15 1 9 7 Gateway Mode The gateway mode allows an automatic information transfer to be established between two independent CAN buses without CPU interaction The gateway mode operates on message object level In gateway mode information is transferred between two message objects resulting in an information transfer between the two CAN nodes to which the message objects are allocated A gateway may be established with any pair of CAN nodes and there can be as many gateways as there are message objects available to build the gateway structure Gateway mode is selected by setting MOFCRs MMC 0100 of the gateway source object s The gateway destination object d is selected by the MOFGPRd CUR pointer of the source object The gateway destination object only needs to be valid its MSGVAL 1 All other settings are not relevant for the information transfer from the source object to the destination object A gateway source object s behaves like a standard message object except some additional actions are performed by the MultiCAN module when a CAN frame has been received and stored in the source object see Figure 15 14 1 If bit MOFCRs DLCC is set the data length code MOFCRs DLC is copied from the gateway source object to the gateway destination object 2 If bit MOFCRs IDC is set the identifier MOARs ID and the identifier extension MOARs IDE are copied from the gateway source object to the gateway desti
484. r P D Flash respectively Flash NMI NMICON NMIFLASH is enabled 1 or disabled 0 Output PSW CY 0 Flash programming is in progress 1 Flash programming is not started DPTR is incremented by 20 or 404 Stack size required 7 bytes Resource ACC B SCU PAGE PSW used destroyed RO R7 of Current Register Bank 8 bytes The time taken by the subroutine from the calling of the subroutine to the setting of the NMI flag can be split into two components One is the time from the calling of the subroutine to the return to the calling function which is lt 100 us for D Flash and lt 150 us for P Flash the other is the time needed by the Flash State Machine which is given by the formula 248256 foyc User s Manual 4 16 V1 1 2007 05 Flash Memory V 1 0 Cinfine on XC886 888CLM Flash Memory 2 For P Flash programming the last 6 LSB of the DPL is 0 for aligned WL address for e g 40 80 C0 and 100 As for the D Flash programming the last 5 LSB of the DPL is 0 for an aligned WL address for e g 00 20 40 60h 804 AOp CO and E0 3 DPTR is only incremented by 40 and 20 when PSW CY is 0 for the P Flash and D flash programming 4 8 2 Flash Erasing Each call of the Flash erase subroutine only allows either the P Flash bank s or the D Flash bank to be erased Hence while it is possible to erase the P Flash banks in parallel it is not possible to erase both the P Flash and D Flash banks simultaneously
485. r ae 6E62 6E61 6E60 9 Sigs Sas 5 5 F amp me z 3 X ZRS gt TEIE V eect 7E02 7E01 7E00 eE a anata ee 6E02 6E01 6E00 DP ee ee eee 7DE2 7DE1 7DEO GDF srs 6DE2 6DE1 6DEO LO z QD LO a B48 Soa OOo O Oo Da Ba oh rane eee eee errr 7D02 7D01 7D00 Deel a 6D02 6DO1 6D00 TORE eee eee O22 C CES AC cad See a 6CE2 6CE1 6CEO S xf S Soe Sot pe B28 x B28 T oe CIE ee eee ears ee 7O02 760i 7600 o CG eee 6C02 6C01 6C00 O TBFFy sisirin 7BE2 7BE1 7BEO O GBFF cceeescccssescssesceeseeseseeseees 6BE2 6BE1 6BEO LO LO Om g mog Soa Soa OO gq OO O r O gt TAIF ES 7A22 7A21 7A20 GAGE ccascpnciens deoeseanctetereceseee 6A22 6A21 6A20 S TN ill sacareeeansceeceateteceopectoeeneee 7A02 7A01 7A00 GAME aap 6A02 6A01 6A00 ORE E ep E E EL TERN 79E0 69FF Coote ior elute E E E 69E2 69E1 69E0 oO oO an g au isot S 2 9 OQ OONN O O N j Ase etl tenn eee tet 7822 7821 7820 e a ee eee 6822 6821 6820 et ee eee ree 7802 7801 7800 A E 6802 6801 6800 TIPE ccscsescsesescsssssesescseeceneees 77E2 77E1 77EO OTE E sesesesscscutesddencosescitecetde 67E2 67E1 67E0 fee fee Ar Tog Sad Sag O lt 4 DOOR a ENEN 74424 7441 7440 Bo aF a sanepan 64424 6441 6440 Bo TA I aeee 7422 74214 7
486. r bits NDIV and KDIV the Watchdog Timer enable bit WDTEN and the power down and slow down enable bits PD and SD PASSWD Password Register Reset Value 07 7 6 5 4 3 2 1 0 PROTECT a ee el aa wh rh rw Field Description MODE 0 Bit Protection Scheme Control bits 00 Scheme disabled direct access to the protected bits is allowed 11 Scheme enabled the bit field PASS has to be written with the passwords to open and close the access to protected bits default Others Scheme enabled These two bits cannot be written directly To change the value between 11 and 00 the bit field PASS must be written with 11000 only then will the MODE 1 0 be registered PROTECT S Bit Protection Signal Status bit This bit shows the status of the protection 0 Software is able to write to all protected bits 1 Software is unable to write to any protected bits User s Manual 3 19 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization Field Bits Type Description PASS 7 3 wh Password bits The Bit Protection Scheme only recognizes three patterns 11000 Enables writing of the bit field MODE 10011 O0Opens access to writing of all protected bits 10101 Closes access to writing of all protected bits User s Manual 3 20 V1 1 2007 05 Memory Organization V 1 2 infine on XC886 888CLM Memory Organization 3 5 5 XC886 888 Register Overview The SFRs of the XC886 888 are organized into groups
487. rallel Ports 6 1 General Port Operation Figure 6 1 shows the block diagram of an XC886 888 bidirectional port pin Each port pin is equipped with a number of control and data bits thus enabling very flexible usage of the pin By defining the contents of the control register each individual pin can be configured as an input or an output The user can also configure each pin as an open drain pin with or without internal pull up pull down device Each bidirectional port pin can be configured for input or output operation Switching between input and output mode is accomplished through the register Px_DIR x 0 1 3 4 or 5 which enables or disables the output and input drivers A port pin can only be configured as either input or output mode at any one time In input mode default after reset the output driver is switched off high impedance The actual voltage level present at the port pin is translated into a logic O or 1 via a Schmitt Trigger device and can be read via the register Px_DATA In output mode the output driver is activated and drives the value supplied through the multiplexer to the port pin In the output driver each port line can be switched to open drain mode or normal mode push pull mode via the register Px_OD The output multiplexer in front of the output driver enables the port output function to be used for different purposes If the pin is used for general purpose output the multiplexer is switched by software
488. re Interrupt Status PM OM F R F R nosier ow rh h Capture Compare Interrupt Status PM CM Evy CCU6_PISELOL Reset 00y Bit Field ISTRP ISCC62 ISCC61 ISCC60 Port Input Select Register 0 Low Type Ww Ww Ww w oF H CCU6_PISELOH Reset 00y Bit Field IST12HR ISPOS2 ISPOS1 ISPOSO Port Input Select Register 0 High Type w A4 CCU6_PISEL2 Reset 00 Bit Field IST13HR Port Input Select Register 2 Type gt 4 lt lt lt O O iq FAY CCU6_T12L Reset 00y Bit Field T12CVL Timer T12 Counter Register Low Type rwh FBu CCU6_T12H Reset 00 Bit Field T12CVH Timer T12 Counter Register High rwh FCH CCU6_T13L Reset 00 Bit Field T13CVL Timer T13 Counter Register Low Type rwh FDy CCU6_T13H Reset 00y Bit Field T13CVH Timer T13 Counter Register High rwh User s Manual 3 37 V1 1 2007 05 Memory Organization V 1 2 infin eon XC886 888CLM Memory Organization Table 3 12 CCU6 Register Overview cont d Register Name Bit 7 6 5 4 3 2 1 07 CCU6_CMPSTATL Reset 00 Bit Field CC63 CC CC CC CC62 CC61 CC60 Compare State Register Low ST POS2 POS1 POSO ST ST ST we for oh om fom om fom oh om CCU6_CMPSTATH Reset 00y Bit Field T13IM COUT COUT CC62 COUT CC61 COUT CC60 Compare State Register High 63PS 62PS PS 61PS PS 60PS BS Type wn wn wh wn wn wh wn on 3 5 5 11 UART1 Registers The UART1 SFRs can be accessed in the mapped memory area RMAP 1 Table 3
489. re lower channel numbers The parallel request source consists of a conversion request control register CRCR1 a conversion request pending register CRPR1 and a conversion request mode register CRMR1 The contents of the conversion request control register are copied overwrite to the conversion request pending register when a selected load event LDE occurs The type of the event defines the behavior and the trigger of the request source The activation of a conversion request to the arbiter may be started if the content of the conversion pending register is not 0 The highest bit position number among the pending bits with values equal to 1 specifies the channel number for conversion To take part in the source arbitration both the REQCHNRV and REQPND signals must be 1 Refer to Section 16 7 7 for description of the parallel request source registers User s Manual 16 14 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 5 2 Request Source Control All conversion pending bits are ORed together to deliver an intermediate signal PND for generating REQCHNRV and REQPND The signal PND is gated with bit ENGT allowing the user to enable disable conversion requests See Figure 16 7 data written conversion request control register by CPU mwh LDE 7 parallel load bitwise conversion request pending register set reset wm by arbiter ee i bitwise OR ae REQPND REQCHNRV Figure 16
490. re only limited by the number of available message objects A FIFO can be installed resized and de installed at any time even during CAN operation The basic structure of a FIFO is shown in Figure 15 13 A FIFO consists of one base object and n slave objects The slave objects are chained together in a list structure similar as in message object lists The base object may be allocated to any list Although Figure 15 13 shows the base object as a separate part beside the slave objects it is also possible to integrate the base object at any place into the chain of slave objects This means that the base object is slave object too not possible for gateways The absolute object numbers of the message objects have no impact on the operation of the FIFO The base object need not to be allocated to the same list as the slave objects Only the Slave object must be allocated to a common list as they are chained together Several pointers BOT CUR and TOP that are located in the Register MOFGPRnh link the base object to the slave objects regardless whether the base object is allocated to the same or to another list than the slave objects The smallest FIFO would be a single message object which is both FIFO base and FIFO Slave not very useful The biggest possible FIFO structure would include all message objects of the MultiCAN module Any FIFO sizes between these limits are possible In the FIFO base object the FIFO boundaries are defined Bi
491. re several ways to generate the baud rate clock for the serial ports depending on the mode in which they are operating The baud rates in modes 0 and 2 are fixed so they use the e Fixed clock see Section 12 1 4 1 In modes 1 and 3 the variable baud rate is generated using the e Dedicated baud rate generator see Section 12 1 4 2 Additionally for UART module the variable baud can also be generated using e Timer 1 see Section 12 1 4 3 This selection between the different variable baud rate sources is performed by bit BGS in UART module s FDCON register 12 1 4 1 Fixed Clock The baud rates in modes 0 and 2 are fixed However for the case of UART module while the baud rate in mode 0 can only be fp 2 the baud rate in mode 2 can be selected as either foo x 64 Or foc 32 depending on bit SMOD Bit SMOD in the PCON register acts as a double baud rate selector in modes 1 2 and 3 In modes 1 and 3 only the variable baud rate supplied by Timer 1 is dependent on SMOD The baud rate supplied by the dedicated baud rate generator is independent of SMOD Baud rate clock and baud rate must be distinguished from each other The serial interface requires a clock rate that is 16 times the baud rate for internal synchronization Therefore the dedicated baud rate generator and Timer 1 must provide a baud rate clock to the serial interface where it is divided by 16 to obtain the actual baud rate The abbreviation foc
492. rea Network MultiCAN Controller Transmit Priority of Msg Objects based on CAN Arbitration Rules Table 15 13 Transmit Priority of Msg Objects Based on CAN Arbitration Rules Settings of Arbitrarily Chosen Message Comment Objects A and B A has higher transmit priority than B A MOAR 28 18 lt B MOAR 28 18 Messages with lower standard identifier 11 bit standard identifier of A less than have higher priority than messages with 11 bit standard identifier of B higher standard identifier MOAR 28 is the most significant bit MSB of the standard identifier MOAR 18 is the least significant bit of the standard identifier A MOAR 28 18 B MOAR 28 18 Standard Frames have higher transmit A MOAR IDE 0 send Standard Frame priority than Extended Frames with equal B MOAR IDE 1 send Extended Frame standard identifier A MOAR 28 18 B MOAR 28 18 Standard data frames have higher transmit A MOAR IDE B MOAR IDE 0 priority than standard remote frames with A MOCTR DIR 1 send data frame equal identifier B MOCTR DIR 0 send Remote Fame A MOAR 28 0 B MOAR 28 0 Extended data frames have higher transmit A MOAR IDE B MOAR IDE 1 priority than Extended remote frames with A MOCTR DIR 1 send data frame equal identifier B MOCTR DIR 0 send remote frame A MOAR 28 0 lt B MOAR 28 0 Extended Frames with lower identifier have A MOAR IDE B MOAR IDE 1 higher transmit priority than Extended 29 bit iden
493. ready to read mode This does not require the typical 160 us as is the case for the normal reset The timing for this part can be ignored 6 The CPU operation is resumed If wake up source is EXINTO pin the interrupt will be serviced if EXINTO is enabled before entering power down mode Upon RETI instruction the core will return to execute the next instruction after the instruction that sets the PD bit If wake up source is RXD pin the core will return to execute the next instruction after the instruction which sets the PD bit User s Manual 8 4 V1 1 2007 05 Power Saving Modes V 1 0 Cinfin eon XC886 888CLM Power Saving Modes 8 1 4 Peripheral Clock Management The amount of reduction in power consumption that can be achieved by this feature depends on the number of peripherals running Peripherals that are not required for a particular functionality can be disabled by gating off the clock inputs For example in idle mode if all timers are stopped and ADC CCU6 CORDIC MDU MultiCAN and the serial interfaces are not running maximum power reduction can be achieved However the user must take care when determining which peripherals should continue running and which must be stopped during active and idle modes The ADC SSC CCU6 CORDIC MDU MultiCAN UART1 Timer 2 and Timer 21 can be disabled clock is gated off by setting the corresponding bit in the PMCON1 register Furthermore the analog part of the ADC module may be disable
494. rect message object for storing of a received CAN frame e Transmit acceptance filtering to determine the message object to be transmitted first individually for each CAN node e Transfer contents between message objects and the CAN nodes taking into account the status control bits of the message objects e Handling of the FIFO buffering and gateway functionality e Aggregation of message pending notification bits List Controller The List Controller performs all operations that lead to a modification of the double chained message object lists Only the list controller is allowed to modify the list structure The allocation deallocation or reallocation of a message object can be requested via a user command interface command panel The list controller state machine then performs the requested command autonomously Interrupt Control The general interrupt structure is shown in Figure 15 3 The interrupt event can trigger the interrupt generation The interrupt pulse is generated independently from the interrupt flag in the interrupt status register The interrupt flag can be reset by software by writing a 0 to it lf enabled by the related interrupt enable bit in the interrupt enable register an interrupt pulse can be generated at one of the 8 interrupt output lines CANSRCm of the MultiCAN User s Manual 15 5 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller module If more than one
495. remented each time a requested conversion has been finished A new entry is ignored if the filling level has reached its maximum value If EMPTY bit 1 there are no valid entries in the queue 00 If EMPTY bit 0 there is 1 valid entry in the queue O01 IfEMPTY bit 0 there are 2 valid entries in the queue 10 If EMPTY bit 0 there is 3 valid entry in the queue 11 IfEMPTY bit 0 there are 4 valid entries in the queue EV 4 rh Event Detected This bit indicates that an event has been detected while V 1 Once set this bit is reset automatically when the requested conversion is started Os An event has not been detected 1 An event has been detected EMPTY 5 rh Queue Empty This bit indicates if the sequential source contains valid entries A new entry is ignored if the queue is filled EMPTY 0 Os The queue is filled with FILL 1 valid entries in the queue 1 The queue is empty no valid entries are present in the queue User s Manual 16 43 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Field Bits Type Description Rsv T r Reserved Returns 1 if read should be written with O Note This bit is initialized to O immediately after reset but is updated by hardware to 1 and remains as 1 shortly after 0 3 0 6 r Reserved Returns 0 if read should be written with 0 User s Manual 16 44 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Con
496. result if T12 is running in edge aligned mode counting up only T13 can only be started automatically if bit field T13TED 01 or 11g TCTR2H Timer Control Register 2 High Reset Value 00 vi 6 s 4 3 2 1 0 0 T13 T12 RSEL RSEL r rw rw Field Description T12RSEL Bis 0 Timer T12 External Run Selection Bit field T12RSEL defines the event of signal T12HR that can set the run bit T12R by hardware 00 The external setting of T12R is disabled 01 Bit T12R is set if a rising edge of signal T12HR is detected 10 BitT12R is set if a falling edge of signal T12HR is detected 11 BitT12R is set if an edge of signal T12HR is detected T13RSEL 2 Timer T13 External Run Selection Bit field T13RSEL defines the event of signal T13HR that can set the run bit T13R by hardware 00 The external setting of T13R is disabled 01 Bit T13R is set if a rising edge of signal T13HR is detected 10 BitT13R is set if a falling edge of signal T13HR is detected 11 Bit T13R is set if an edge of signal T13HR is detected 0 7 4 r Reserved Returns 0 if read should be written with 0 User s Manual 14 64 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Register TCTR4 allows the software control of the run bits T12R and T13R by independent set and reset conditions Furthermore the timers can be reset while running and the bits STE12 and STE13 can be controlled by software TCTR4L Timer Control Register 4 Low Reset Value 0
497. ries for all channels LCBR BOUNDO LCBR BOUND1 Configure external trigger control functions Select source x external trigger inout ETRCR ETRSELx Enable disable source x external trigger input synchronization ETRCR SYNENx Setup sequential source Enable conversion request QMRO ENGT Enable disable external trigger QMRO ENTR Setup parallel source Enable conversion request CRMR1 ENGT Enable disable external trigger CRMR1 ENTR Enable disable source interrupt CRMR1 ENSI Enable disable autoscan CRMR1 SCAN Turn on analog part Set GLOBCTR ANON wait for 100 ns Start sequential request Write to QINRO with information such as REQCHNR RF ENSI and EXTR User s Manual 16 28 V1 1 2007 05 ADC V V1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Generate a pending conversion request using any method described in Section 16 4 4 2 e Start parallel request Write to CRCR1 no load event or CRPR1 automatic load event the channels to be converted Generate a load event if not already available to trigger a pending conversion request using any method described in Section 16 4 5 2 e Wait for ADC conversion to be completed The source interrupt indicates that the conversion requested by the source is completed The channel interrupt indicates that the corresponding channel conversion is completed with limit check performed The result in
498. rigger AltDataln lt Figure 6 1 General Structure of Bidirectional Port Figure 6 2 shows the structure of an input only port pin Each P2 pin can only function in input mode Register P2_DIR is provided to enable or disable the input driver When the input driver is enabled the actual voltage level present at the port pin is translated into a logic 0 or 1 via a Schmitt Trigger device and can be read via the register P2 _ DATA Each pin can also be programmed to activate an internal weak pull up or pull down device Register P2 PUDSEL selects whether a pull up or the pull down device is User s Manual Parallel Ports V 1 0 V1 1 2007 05 Cinfin eon XC886 888CLM Parallel Ports activated while register P2_ PUDEN enables or disables the pull device The analog input Analogin bypasses the digital circuitry and Schmitt Trigger device for direct feed through to the ADC input channel aS Internal Bus Px_PUDSEL Pull up Pull down Select Register Px Pull up Pull down Enable Register Px DIR Direction Register Input Y Driver Data Register Schmitt Trigger AltDataln lt Analogln lt Figure 6 2 General Structure of Input Port User s Manual 6 4 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 1 1 General Register Description The individual control and data bits of each parallel port are implemented in
499. riting 1 has no effect RXOK Message Received Successfully 0 No successful reception since last most recent flag reset 1 A message has been received successfully RXOK must be reset by software write 0 Writing 1 has no effect User s Manual 15 63 V1 1 2007 05 MultiCAN V1 0 Cinfineon i 7 a i LLE i rwh LOE i rwh User s Manual MultiCAN V1 0 XC886 888CLM Controller Area Network MultiCAN Controller Description Alert Warning The ALERT bit is set upon the occurrence of one of the following events the same events which also trigger an alert interrupt if NCRx ALIE is set e Achange of bit NSRx BOFF e Achange of bit NSRx EWRN e A List Length Error which also sets bit NSRx LLE e A List Object Error which also sets bit NSRx LOE e Bit INIT has been set by hardware ALERT must be reset by software write 0 Writing 1 has no effect Error Warning Status 0 No warning limit exceeded 1 One of the error counters NECNTx REC or NECNTx TEC reached the warning limit NECNTx EWRNLVL Bus off Status 0 CAN controller is not in the bus off state 1 CAN controller is in the bus off state List Length Error 0 No List Length Error since last most recent flag reset 1 A List Length Error has been detected during message acceptance filtering The number of elements in the list that belongs to this CAN node differs from the list SIZE given in the list termination pointer LLE must be reset by software
500. rnal Trigger This bit enables the external trigger possibility If enabled bit EV is set if a rising edge is detected at the external trigger inout REQTR when at least one V bit is set in register QORO or QBURO Os The external trigger is disabled 1 The external trigger is enabled CLRV 4 W Clear V Bits On No action l The bit Vin register QORO or QBURDO is reset lf QBURO V 1 then QBURO V is reset If QBURO V 0 then QORO V is reset FLUSH 5 W Flush Queue 0s No action 1 All bits V in the queue registers and bit EV are reset The queue contains no more valid entry User s Manual 16 41 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Field Description TREV Naat Event No action A trigger event is generated by software If the source waits for a trigger event a conversion request is started CEV ae Event Bit No action Bit EV is cleared 0 Reserve ee O if read should be written with 0 User s Manual 16 42 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Register QSRO contains bits that indicate the status of the sequential source QSRO Queue Status Register CE Reset Value 20 3 2 1 0 7 6 5 4 r r rh rh rh r Field Bits Type Description FILL 1 0 rh Filling Level This bit field indicates how many entries are valid in the sequential sourced queue It is incremented each time a new entry is written to QINRO dec
501. rocessing according to the ISO 11898 standard This includes conversion between the serial data stream and the input output registers e Bit Timing Unit The Bit Timing Unit defines the length of a bit time and the location of the sample point according to the user settings taking into account propagation delays and phase shift errors The Bit Timing Unit also performs re synchronization User s Manual 15 4 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller e Error Handling Unit The Error Handling Unit manages the receive and transmit error counter According to the contents of both counters the CAN node is set into an error active error passive or bus off state e Node Control Unit The Node Control Unit coordinates the operation of the CAN node Enable disable CAN transfer of the node Enable disable and generate node specific events that lead to an interrupt request CAN bus errors successful frame transfers etc Administration of the Frame Counter e Interrupt Control Unit The Interrupt Control Unit in the CAN node controls the interrupt generation for the different conditions that can occur in the CAN node Message Controller The Message Controller handles the exchange of CAN frames between the CAN nodes and the message objects that are stored in the Message RAM The Message Controller performs several functions e Receive acceptance filtering to determine the cor
502. rol Register Bits P4 5 COUT61_ 2 P4 DIR P5 1 Output P4 P4_ALTSELO P5 1 0 0 P5 P4_ALTSELO P5 1 0 0 1 P4 P4_ALTSEL1 P5 0 P5 0 P3 4 CC62_0 ISCC62 00 ISCC62 00 feomeeg DIR P4 0 P3_DIR P4 0 input P3 P3_ALTSELOP4 1 P4 P3_ALTSELO P4 1 1 P3 P3_ALTSEL1 P4 0 8 P4 0 P0 4 CC62 1 ISCC62 01g ISCC62 01g A DIR P4 0 PO_DIR P4 0 input P4 6 CC62_2 Output P3 5 COUT62 0 Output P3 P3_ALTSELOPS 1 P3_ALTSELO P5 1 P3_ALTSEL1 P5 O0 8 P0 5 COUT62_1 ee PO PO_ALTSELOPS 0 P5 0 PO A P5 1 P4 7 COUT62_2 ao R P4 P4_ALTSELO P7 1 P4_ALTSEL0 P7 1 P4_ALTSEL1 P7 0 P3 7 COUT63_0 2a ae P3 P3_ALTSELOP7 1 P3_ALTSELO P7 1 P3_ALTSEL1 P7 O0 P0 3 COUT63 _ 1 a PO PO_ALTSELOP3 0 P3 0 PO rene P3 1 User s Manual 14 30 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Table 14 2 CCU6 I O Control Selection cont d Port Lines PISEL Register Bit Input Output Control Register Bits P4 3 COUT63 2 P4 DIR P3 1 Output P4_ALTSELO P3 0 8 8 P4 ae P3 1 P1 6 T12HR_O ISTI2HR 00 0 ISTI2HR 00 0 PAATSECLPS 1 _DIR P6 0 Input User s Manual 14 31 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 2 Register Map The CCU6 SFRs are located in the standard memory area RMAP 0 and are organized into 4 pages The CCU6_PAGE register is located at address A3 It contains the page value and the page control information All CCU6 register names described in the follo
503. ror Checksum Error F Acknowledge Block Error Checksum Error lf a block is received correctly an Acknowledge Code 55 is sent In case of failure it may be a wrong block type error or checksum error Block type error is caused by two conditions i The microcontroller receives a block type other than the implemented ones il The microcontroller receives the transfer blocks in wrong sequence In both error cases the BSL routine awaits the actual block from the host again When program and erase operations of Flash are restricted due to Flash Protection Mode 0 or 1 being enabled protection error code will be sent to the host This will indicate that Flash is protected and hence it cannot be programmed or erased In this error case the BSL routine will wait for the next header block from the host again User s Manual 18 6 V1 1 2007 05 Bootstrap Loader V1 0 Infineon XC886 888CLM i Bootstrap Loader Table 18 5 lists the responses with the possible reasons and or implcations for error and suggests the possible corrective actions that the host can take upon notification of the error Table 18 5 Definition of Responses Response Value Description Block BSL _ Reasons Implications Corrective Action Type Mode Acknow 554 Header 1 3 The requested operation ledge 9 F iwill be performed once the response is sent The requested operation EOT 0 2 has been performed and is 4 8 Successful All others Recep
504. rpose timers that are functionally identical Both have two modes of operation a 16 bit auto reload mode and a 16 bit one channel capture mode and can function as a timer or counter in each of its modes As a timer the timers count with an input clock of PCLK 12 if prescaler is disabled As a counter they count 1 to 0 transitions on pin T2 In the counter mode the maximum resolution for the count is PCLK 24 if prescaler is disabled Note Subsequent sections describe the functionalities of Timer 2 which is valid also for Timer 21 unless otherwise stated 13 2 1 Basic Timer Operations Timer 2 can be started by using TR2 bit by hardware or software Timer 2 can be started by setting TR2 bit by software If bit T2RHEN is set Timer 2 can be started by hardware Bit TZ2REGS defines the event on pin T2EX falling edge or rising edge that can set the run bit TR2 by hardware Timer 2 can only be stopped by resetting TR2 bit by software 13 2 2 Auto Reload Mode The auto reload mode is selected when the bit CP RL2 in register T2CON is zero In this mode Timer 2 counts to an overflow value and then reloads its register contents with a 16 bit start value for a fresh counting sequence The overflow condition is indicated by setting bit TF2 in the T2CON register At the same time an interrupt request to the core will be generated if interrupt is enabled The overflow flag TF2 must be cleared by software The auto reload mode is further classif
505. rrupt for T12 One Match 0 No interrupt will be generated if the set condition for bit T12OM in register IS occurs 1 An interrupt will be generated if the set condition for bit T120M in register IS occurs The interrupt line that will be activated is selected by bit field INPT12 Enable Interrupt for T12 Period Match 0 No interrupt will be generated if the set condition for bit T12PM in register IS occurs 1 An interrupt will be generated if the set condition for bit T12PM in register IS occurs The interrupt line that will be activated is selected by bit field INPT12 ENT120M ENT12PM User s Manual 14 88 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 IENH Capture Compare Interrupt Enable Register High Reset Value 00 7 6 5 4 3 2 1 0 EN EN EN EN IDLE WHE CHE TRPF rw rw rw r Field Description ENT13CM ar Interrupt for T13 Compare Match No interrupt will be generated if the set condition for bit T13CM in register IS occurs An interrupt will be generated if the set condition for bit T13CM in register IS occurs The interrupt line that will be activated is selected by bit field INPT13 ENT13PM Enable Interrupt for T13 Period Match 0 No interrupt will be generated if the set condition for bit T13PM in register IS occurs 1 An interrupt will be generated if the set condition for bit T13PM in register IS occurs The interrupt line that will be activated is selected by bit field INPT13 r
506. rrupt pulse CHINSR Channel Interrupt Set Register CC Reset Value 00 7 6 5 4 3 2 1 0 CHINS7 CHINS6 CHINSS CHINS4 CHINS3 CHINS2 CHINS1 CHINSO W W W W W W W W Field Bits Type Description CHINSx X W Set Interrupt Flag for Channel x x 0 7 On No action 1 Bit CHINFR x is set and an interrupt pulse is generated The bits in register CHINPR define the service request output line SRx x 0 or 1 that is activated if a channel interrupt is generated CHINPR Channel Interrupt Node Pointer Register CD Reset Value 00 7 6 5 4 3 2 1 0 CHINP7 CHINP6 CHINPS CHINP4 CHINP3 CHINP2 CHINP1 CHINPO rw rw rw rw rw rw rw rw Field Bits Type Description CHINPx X rw Interrupt Node Pointer for Channel x x 0 7 This bit defines which SR lines becomes activated if the channel x interrupt is generated Os The line SRO becomes activated 1 The line SR1 becomes activated User s Manual 16 60 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Register EVINFR monitors the activated event interrupt flags EVINFR Event Interrupt Flag Register CE Reset Value 00 3 2 1 0 7 6 5 4 EVINF7 EVINF6 EVINF5 EVINF4 oO EVINF1 EVINFO rh rh rh rh rh rh r Field Bits Type Description EVINFx Interrupt Flag for Event x x 0 1 4 7 This bit monitors the status of the event interrupt x Os An event interrupt for event x has not occurred 1 An event interrupt for e
507. rs The division and modulus functions of the truncated division are related in the following way If q D div d and r D mod d then D q d r and r lt d where D is the dividend d is the divisor g is the quotient and r is the remainder The truncated division rounds the quotient towards zero and the sign of its remainder is always the same as that of its dividend i e sign r sign D 10 1 2 Normalize The MDU supports up to 32 bit unsigned normalize Normalizing is done on an unsigned integer variable stored in MDO least significant byte to MD3 most significant byte This feature is mainly meant to support applications where floating point arithmetic is used During normalization all leading zeros of an unsigned integer variable in registers MDO to MD3 are removed by shift left operations The whole operation is completed when the MSB most significant bit contains a 1 After normalizing bit field MR4 SCTR contains the number of shift left operations that were done This number may be used later as an exponent The maximum number of shifts in a normalize operation is 31 2 1 10 1 3 Shift The MDU implements both logical and arithmetic shifts to support up to 32 bit unsigned and signed shift operations During logical shift zeros are shifted in from the left end of register MD3 or right end of register MDO An arithmetic left shift is identical to a logical left shift but during arith
508. ructure 1 User s Manual 5 9 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System where the pending interrupt request is cleared directly by resetting the node s interrupt status flags If IMODE 0 only on clearing the interrupt node enable bit will indirectly clear its pending interrupt request Hence when IMODE 0 the interrupt node enable bit additionally serves a dual function to enable disable the generation of pending interrupt request and to clear an already generated pending interrupt request by resetting enable bit to 0 Note Interrupt structure 2 applies to the NMI with the exclusion of EA bit and interrupt node enable bit is replaced by OR of all NMICON bits Therefore NMI node is non maskable when IMODE 1 whereas NMI pending interrupt request may be cleared by clearing all NMICON bits when IMODE 0 5 1 2 1 System Control Register 0 The SYSCONO register contains bits to select the SFR mapping and interrupt structure 2 mode SYSCONO System Control Register 0 Reset Value 04 7 6 5 4 3 2 1 0 r rw r r r rw Field Description IMODE asi Structure 2 Mode Select Interrupt structure 2 mode 0 is selected Interrupt structure 2 mode 1 is selected 1 Y eeet fees 1 if read should be written with 0 0 E 3 Reserved 7 5 Returns 0 if read should be written with O Note The IMODE bit should be cleared set using ANL or ORL instructions User s Manual 5 10 V1 1 2007 05
509. rw Field Description Pn Up Pull Down Select Port 5 Bit n n 0 7 Pull down device is selected Pull up device is selected User s Manual 6 51 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports P5 PUDEN Port 5 Pull Up Pull Down Enable Register Reset Value FF 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Enable at Port 5 Bit n n 0 7 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled P5_ALTSELn n 0 1 Port 5 Alternate Select Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pin Output Functions n 0 7 Configuration of Px_ALTSELO Pn and Px ALTSEL1 Pn for GPIO or alternate settings 00 Normal GPIO 10 Alternate Select 1 01 Alternate Select 2 11 Alternate Select 3 User s Manual 6 52 V1 1 2007 05 Parallel Ports V 1 0 Cinfine on XC886 888CLM Power Supply Reset and Clock Management 7 Power Supply Reset and Clock Management The XC886 888 provides a range of utility features for secure system performance under critical conditions e g brownout The power supply to the core memories and the peripherals is regulated by the Embedded Voltage Regulator EVR that comes with detection circuitries to ensure that the supplied voltages are within the specified operating range The main voltage and low power voltage regulators in the EVR m
510. s Type Description TRPEN 5 0 rw Trap Enable Control Setting these bits enables the trap functionality for the following corresponding output signals Bit O trap functionality of CC60 Bit 1 trap functionality of COUT60 Bit 2 trap functionality of CC61 Bit 3 trap functionality of COUT61 Bit 4 trap functionality of CC62 Bit 5 trap functionality of COUT62 The enable feature of the trap functionality is defined as follows 0 The trap functionality of the corresponding output signal is disabled The output state is independent from bit TRPS 1 The trap functionality of the corresponding output signal is enabled The output is set to the passive state while TRPS 1 TRPEN13 rw Trap Enable Control for Timer T13 0 The trap functionality for T13 is disabled Timer T13 if selected and enabled provides PWM functionality even while TRPS 1 1 The trap functionality for T13 is enabled The timer 113 PWM output signal is set to the passive state while TRPS 1 User s Manual 14 71 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Bits Type Description TRPPEN rw Trap Pin Enable 0 The trap functionality based on the input pin CTRAP is disabled A trap can only be generated by software by setting bit TRPF j The trap functionality based on the input pin CTRAP is enabled A trap can be generated by software by setting bit TRPF or by CTRAP 0 Register PSLR defines the passive stat
511. s 1 2 and 3 Must be cleared by software Users Manual 12 8 V1 1 2007 05 Serial Interfaces V 1 0 Cinfineon Cid Description Field Tl RB8 TB8 REN SM2 SM1 SMO User s Manual Serial Interfaces V 1 0 XC886 888CLM Serial Interfaces Transmit Interrupt Flag This is set by hardware at the end of the 8th bit in mode 0 or at the beginning of the stop bit in modes 1 2 and 3 Must be cleared by software Serial Port Receiver Bit 9 In modes 2 and 3 this is the 9th data bit received In mode 1 this is the stop bit received In mode 0 this bit is not used Serial Port Transmitter Bit 9 In modes 2 and 3 this is the 9th data bit sent Enable Receiver of Serial Port 0 Serial reception is disabled Serial reception is enabled Enable Serial Port Multiprocessor Communication in Modes 2 and 3 In mode 2 or 3 if SM2 is set to 1 RI will not be activated if the received 9th data bit RB8 is 0 In mode 1 if SM2 is set to 1 RI will not be activated if a valid stop bit RB8 was not received In mode 0 SM2 should be 0 Serial Port Operating Mode Selection 00 01 10 11 Mode 0 8 bit shift register fixed baud rate Vecik 2 Mode 1 8 bit UART variable baud rate Mode 2 9 bit UART fixed baud rate fp 64 OF feciK 32 Mode 3 9 bit UART variable baud rate 12 9 V1 1 2007 05 Cinfin eon XC886 888CLM Serial Interfaces 12 1 4 Baud Rate Generation There a
512. s VF unchanged by read access to RESRxH RESRAxH default 1 VF reset by read access to RESRxH RESRAXH Reserved Returns 0 if read should be written with 0 16 58 V1 1 2007 05 Cinfin eon XC886 888CLM Analog to Digital Converter 16 7 9 Interrupt Registers Register CHINFR monitors the activated channel interrupt flags CHINFR Channel Interrupt Flag Register CA Reset Value 00 7 6 5 4 3 2 1 0 CHINF7 CHINF6 CHINF5 CHINF4 CHINF3 CHINF2 CHINF1 CHINFO rh rh rh rh rh rh rh rh Field Commu Description CHINFx rh Interrupt Flag for Channel x x 0 7 ie bit monitors the status of the channel interrupt x A channel interrupt for channel x has not occurred A channel interrupt for channel x has occurred Writing a 1 to a bit position in register CHINCR clears the corresponding channel interrupt flag in register CHINFR If a hardware event triggers the setting of a bit CHINFx and CHINCx 1 the bit CHINFx is cleared software overrules hardware CHINCR Channel Interrupt Clear Register CB Reset Value 00 7 6 5 4 3 2 1 0 meron me ome ome ome ome omor W W W W W W W W Field Description CHINCx Interrupt Flag for Channel x x 0 7 No action Bit CHINFR x is reset User s Manual 16 59 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Writing a 1 to a bit position in register CHINSR sets the corresponding channel interrupt flag in register CHINFR and generates an inte
513. s empty CON BSY will be cleared at the same time Software should not modify CON BSY as this flag is hardware controlled When configured as a slave device the SSC will immediately output the selected first bit MSB or LSB of the transfer data at the output pin once the contents of the transmit buffer are copied into the slave s shift register Bit CON BSY is not set until the first clock edge at SS_CLK appears Note On the SSC a transmission and a reception take place at the same time regardless of whether valid data has been transmitted or received Note The initialization of the CLK pin on the master requires some attention in order to avoid undesired clock transitions which may disturb the other devices Before the clock pin is switched to output via the related direction control register the clock output level will be selected in the control register CON and the alternate output User s Manual 12 35 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces be prepared via the related ALTSEL register or the outout latch must be loaded with the clock idle level 12 3 1 3 Half Duplex Operation In a half duplex mode only one data line is necessary for both receiving and transmitting of data The data exchange line is connected to both the MTSR and MRST pins of each device the shift clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock
514. s if the trap input becomes active e g as emergency stop During the trap state the selected outputs are forced into the passive state and no active modulation is possible The trap state is entered immediately by hardware if the CTRAP input signal becomes active and the trap function is enabled by bit TRPPEN It can also be entered by software by setting bit TRPF trap input flag thus leading to TRPS 1 trap state indication flag The trap state can be left when the input is inactive by software control and synchronized to the following events e TRPF is automatically reset after CTRAP becomes inactive if TRPM2 0 e TRPF must be reset by software after CTRAP becomes inactive if TRPM2 1 e synchronized to T12 PWM after TRPF is reset T12 period match in edge aligned mode or one match while counting down in center aligned mode User s Manual 14 17 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 e synchronized to T13 PWM after TRPF is reset 113 period match e no synchronization to 112 or 113 CTRAP active sync to 113 TRPS sync to 112 TRPS no sync CCU6_trap_ sync Figure 14 14 Trap State Synchronization with TRPM2 0 User s Manual 14 18 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 1 5 Multi Channel Mode The multi channel mode offers the possibility of modulating all six T12 related outputs The bits in bit
515. s two timing diagrams for a 2 byte 1 cycle 1 x machine cycle instruction The first diagram shows the instruction being executed within one machine cycle since the second byte C1P1 and the opcode C1P2 are fetched from a memory without wait state The second diagram shows the corresponding states of the same instruction being executed over three machine cycles instruction time extended with one wait state inserted for each access to the Flash memory two wait states inserted in total Figure 2 2 c shows two timing diagrams of a 1 byte 2 cycle 2 x machine cycle instruction The first diagram shows the instruction being executed over two machine cycles with the opcode C2P2 fetched from a memory without wait state The second diagram shows the corresponding states of the same instruction being executed over three machine cycles instruction time extended with one wait state inserted for opcode fetching from the Flash memory User s Manual 2 7 V1 1 2007 05 Processor Architecture V 1 0 infin eon XC886 888CLM Processor Architecture look Read next opcode without wait state __ Read next opcode one wait state next instruction a 1 byte 1 cycle instruction e g INC A Read 2 byte Read next opcode without wait state without wait state next instruction Read 2 byte __ Read next opcode one wait state one wait state next instruction Read next
516. sable Flash protection and it is a non zero value For a description of the user password see Chapter 3 4 1 Not used The four bytes are not used and will be ignored in Mode 6 In Mode 6 the header block is the only transfer block to be sent by the host This mode is used when user wants to i enable Flash protection ii disable Flash protection When Flash is not protected yet the microcontroller will enable the Flash protection based on the MSB and bit 4 of the user password The selected Flash protection mode will be activated at the next power up or hardware reset and microcontroller identifies this user password as the program password for future operations When Flash is already protected the microcontroller will deactivate all Flash Protection if the user password byte matches the program password Protected Flash Banks will be erased and the program password is reset At the next power up or hardware reset the Flash protection will not be activated User s Manual 18 14 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader 18 1 2 7 The Activation of Mode A Mode A is used to obtain a 4 byte data The contents of the 4 byte data is determined by the Option byte in the header block The header block for this mode has the following structure The Header Block 0 Mode Data 5 bytes caus Mode A Not Used Option ecksum 4 bytes 1 byte Mode Data Description Option This byte will det
517. sable the Timer 21 0 ra 2 fees i 0 if read should be written with O User s Manual 13 21 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 2 8 Module Suspend Control Timer 2 and Timer 21 can be configured to stop their counting when the OCDS enters monitor mode see Chapter 17 3 by setting their respective module suspend bits T2SUSP and T21SUSP in SFR MODSUSP MODSUSP Module Suspend Control Register Reset Value 01 7 6 5 4 3 2 1 0 8 suse T2SUSP T13SUSP T12SUSP WOTSUSP rw rw rw rw rw r Field CEL Description T2SUSP m 2 Debug Suspend Bit Timer 2 will not be suspended Timer 2 will be suspended T21SUSP A 21 Debug Suspend Bit Timer 21 will not be suspended Timer 21 will be suspended 0 7 5 Reserved Returns 0 if read should be written with O User s Manual 13 22 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 2 9 Register Map Timer 2 and Timer 21 contain an identical set of SFRs All Timer 2 register names described in the following sections are referenced in other chapters of this document with the module name prefix T2_ e g T2_T2CON while those of Timer 21 are referenced with T21_ e g T21_ T2CON The Timer2 SFRs are located in the standard non mapped SFR area The corresponding set of SFRs for Timer 21 are assigned the same address as the Timer 2 SFRs except that they are located instead in the mapped area Table 13 3 lists these addresses T
518. sed as input and output control registers for shift and normalize operations MDx x 0 5 MDU Operand Register Reset Value 00 7 6 5 4 3 2 1 0 DATA rw Field Bits Type Description DATA 7 0 rw Operand Value See Table 10 3 MRx x 0 5 MDU Result Register Reset Value 00 7 6 5 4 3 2 1 0 DATA rw Field Bits Type Description DATA 7 0 rh Result Value See Table 10 4 MD4 Shift Input Control Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw User s Manual 10 9 V1 1 2007 05 MDU V2 1 Cinfin eon XC886 888CLM Multiplication Division Unit Field Bits Type Description SCTR 4 0 rw Shift Counter The count written to SCTR determines the number of shifts to be performed during a shift operation SLR 5 rw Shift Direction 0 Selects shift left operation 1 Selects shift right operation 0 7 6 rw Reserved Should be written with 0 Returns undefined data if read MR4 Shift Output Control Register Reset Value 00 7 6 3 4 3 2 1 0 em Field Bits Type Description SCTR 4 0 rh Shift Counter After a normalize operation SCTR contains the number of normalizing shifts performed 7 5 rh Reserved Returns undefined data if read User s Manual 10 10 V1 1 2007 05 MDU V2 1 Cinfin eon XC886 888CLM Multiplication Division Unit 10 5 2 Control Register Register MDUCON contains control bits that select and start the type of operation to be performed MDUCON MDU Control Regist
519. sion of the data frame is suspended until transmission is re enabled by software setting TXENO User s Manual 15 30 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Table 15 3 Message Transmission Bit Definitions cont d Bit Description TXEN1 Transmit Enable 1 This bit is used in transmit FIFOs to select the message object that is transmit active within the FIFO structure For message objects that are not transmit FIFO elements TXEN1 can either be set permanently to 1 or can be used as a second independent transmission enable bit RTSEL When a message object has been identified after transmission acceptance filtering to be transmitted next bit MOCTRn RTSEL Receive Transmit Selected becomes set When the message object is copied into the internal transmit buffer bit RTSEL is checked and the message is only transmitted if RTSEL 1 After the successful transmission of the message bit RISEL is checked again and the message postprocessing is only executed if RTSEL 1 For a complete re configuration of a valid message object the following steps should be executed 1 Clear MSGVAL bit 2 Re configure the message object while MSGVAL 0 3 Clear RTSEL and set MSGVAL Clearing of RISEL ensures that the message object is disconnected from an ongoing scheduled transmission and no message object processing copying message to transmit buffer including clearing NEWDAT
520. smit acceptance filtering is identical for remote and data frames MSGVAL TXRQ TXENO TXEN1 A message can only be transmitted if all four bits in MOSTATn Register MSGVAL Message Valid TXRQ Transmit Request TXENO Transmit Enable 0 TXEN1 Transmit Enable 1 are set Although these bits are equivalent with respect to the transmission process they have different semantics Table 15 3 Message Transmission Bit Definitions Bit Description MSGVAL Message Valid This is the main switch bit of the message object TXRQ Transmit Request This is the standard transmit request bit This bit must be set whenever a message object is to be transmitted TXRQ is cleared by hardware at the end of a successful transmission except when there is new data indicated by NEWDAT 1 to be transmitted When bit MOFCRn STT Single Transmit Trial is set TXRQ is already cleared when the content of the message object is copied into the transmit frame buffer of the CAN node A received remote request after a remote frame reception sets bit TXRQ to request the transmission of the requested data frame TXENO Transmit Enable 0 This bit can be temporarily cleared by software to suppress the transmission of this message object when it writes new content to the data field This avoids transmission of inconsistent frames that consist of a mixture of old and new data Remote requests are still accepted when T XENO 0 but transmis
521. sources RXD_0 RXD_1 and RXD_2 This selection is performed by the SFR bits MODPISEL URRIS and MODPISEL URRISH in UART module and MODPISEL1 UR1RIS in UART1 module MODPISEL Peripheral Input Select Register Reset Value 00 7 6 5 4 3 2 1 0 0 URIS sTAGTON STAGTCK EXINT2IS EXINTHIS EXINTOIS uRRIS r rw rw rw rw rw rw rw Field Description URRISH gia Receive Input Select 6 0 UART Receiver Input RXD_0 is selected UART Receiver Input RXD_1 is selected UART Receiver Input RXD_2 is selected Reserved 0 ae a O if read should be written with 0 MODPISEL1 Peripheral Input Select Register 1 Reset Value 00 7 6 5 4 3 2 1 0 EXINTG6IS To1EXIg JTAGTDI JTAGTCK S1 S1 r rw rw rw rw rw Field Description UR1RIS LI 3 UART1 Receive Input Select 00 UART1 Receiver Input RXD_0 is selected 01 UART1 Receiver Input RXD_1 is selected 10 UART1 Receiver Input RXD_2 is selected 11 Reserved User s Manual 12 23 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces Field Bits Type Description 0 6 5 r Reserved Returns 0 if read should be written with 0 12 1 6 Low Power Mode lf the UART1 module functionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit UART1_DIS in register PMCONZ2 as described below Refer to Chapter 8 1 4 for details on peripheral clock management PMCON2
522. spective settings have been done in OCDS This functionality allows two alternative configurations e As an action additional to the Monitor program start in such a case MBC pin is activated for up to 77 system clock SCLK cycles e As the only OCDS action while temporarily suspending the core activity MBC pin is driven low for 4 SCLK cycles only as a fastest reaction to the program flow breakpoint match 17 4 Debug Suspend Control Next to the basic debug functionality setting breakpoints and halting the execution of user software XC886 888 OCDS supports also an additional feature module suspend during debugging As long as the device is in monitor mode i e while the user software is not running but in break and if debug suspend functionality is generally enabled by on chip software Monitor or Bootcode OCDS activates a signal to a number of counter modules namely e Watchdog Timer WDT e Timer 2 and Timer 21 e Timer 12 and Timer 13 in Capture Compare Unit 6 CCU6 The Module Suspend Control Register MODSUSP holds control bits for these timers When some control bit is set the respective timer will be stopped while the monitor mode is active This feature could be quite useful especially regarding the Watchdog Timer it allows to prevent XC886 888 from unintentional WDT resets while the user software is not executed and respectively not able to service the Watchdog User s Manual 17 7 V1 1 2007 05 OCDS V
523. ssage object in the FIFO structure This message object will then be used to store the next incoming message If bit field MOFCRn OVIE Overflow Interrupt Enable of the FIFO base object is set and the current pointer MOFGPRn CUR becomes equal to MOFGPRn SEL a FIFO overflow interrupt request is generated This interrupt request is generated on interrupt node TXINP of the base object immediately after the storage of the received frame in the slave object Transmit interrupts are still generated if TXIE is set A CAN message is stored in FIFO base and slave object only if MSGVAL 1 User s Manual 15 36 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 9 6 Transmit FIFO The Transmit FIFO structure is used to buffer a series of data or remote frames that must be transmitted A Transmit FIFO is selected by setting MOFCRn MMC 0010 in the FIFO base object Unlike the Receive FIFO slave objects assigned to the Transmit FIFO are required to set explicitly their bit fields MOFCRn MMC 0011 The CUR pointer in all slave objects must point back to the Transmit FIFO Base Object to be initialized by software The MOSTATn TXEN1 bits Transmit Enable 1 of all message objects except the one which is selected by the CUR pointer of the base object must be cleared by software TXEN1 of the message slave object selected by CUR must be set CUR of the base object may be initialized to
524. st event flag interrupt source enable bit to core Figure 5 7 Interrupt Structure 1 For the XC886 888 interrupt sources Timer 0 Timer 1 external interrupt 0 and external interrupt 1 each have a dedicated interrupt node will have their respective interrupt status flags TFO TF1 IEO and IE1 in register TCON cleared by the core once their corresponding pending interrupt request is serviced In the case that an interrupt node is User s Manual 5 8 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System disabled e g software polling is used its interrupt status flag must be cleared by software since the core will not be interrupted and therefore the interrupt acknowledge is not generated For the UART module interrupt status flags RI and TI in register SCON will not be cleared by the core even when its pending interrupt request is serviced The UART module s interrupt status flags and hence the pending interrupt request can only be cleared by software 5 1 2 Interrupt Structure 2 Interrupt structure 2 in Figure 5 8 applies to Timer 2 Timer 21 UART1 LIN external interrupts 2 to 6 ADC SSC CCU6 Flash MDU CORDIC and MultiCAN interrupt sources For this structure the interrupt status flag does not directly drive the pending interrupt request which is latched due to an interrupt event Further an additional control bit IMODE in SYSCONO register is used to select one of t
525. status flags are available for determining which interrupt event has occurred especially useful for an interrupt node which is shared by several event sources Each interrupt node has a global enable disable bit In most cases additional enable bits are provided for enabling disabling particular interrupt events In general the XC886 888 has two interrupt structures distinguished mainly by the manner in which the pending interrupt request one per interrupt vector source going directly to the core is generated due to the events and cleared Common among these two interrupt structures is the interrupt masking bit EA which is used to globally enable or disable all interrupt requests except NMI to the core Resetting bit EA to 0 only masks the pending interrupt requests from the core but does not block the capture of incoming interrupt requests 5 1 1 Interrupt Structure 1 For interrupt structure 1 in Figure 5 7 the interrupt event will set the interrupt status flag which doubles as a pending interrupt request to the core An active pending interrupt request will interrupt the core only if its corresponding interrupt node is enabled Once an interrupt node is serviced interrupt acknowledged its pending interrupt request represented by the interrupt status flag may be automatically cleared by hardware the core software interrupt acknowledge 1 cea clear pending from core interrupt interrupt set interrupt status reque
526. ster Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn 2 Pin n Driver Control n 0 7 Input driver is enabled default Input driver is disabled User s Manual 6 30 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports P2 PUDSEL Port 2 Pull Up Pull Down Select Register Reset Value FF 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Select Port 2 Bit n n 0 7 0 Pull down device is selected 1 Pull up device is selected P2 _ PUDEN Port 2 Pull Up Pull Down Enable Register Reset Value 00 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Pull Up Pull Down Enable at Port 2 Bit n n 0 7 0 Pull up or Pull down device is disabled default 1 Pull up or Pull down device is enabled User s Manual 6 31 V1 1 2007 05 Parallel Ports V 1 0 Cinfine on XC886 888CLM Parallel Ports 6 6 Port 3 Port P3 is an 8 bit general purpose bidirectional port The registers of P3 are Summarized in Table 6 9 Table 6 9 Port 3 Registers Register Short Name Register Full Name P3 DATA Port 3 Data Register P3 DIR Port 3 Direction Register P3 OD Port 3 Open Drain Control Register P3 PUDSEL Port 3 Pull Up Pull Down Select Register P3 PUDEN Port 3 Pull Up Pull Down Enable Register P3 ALTSELO Port 3 Alternate Select Register 0 P3_ ALTSEL1 Port 3 Alternate Select Register 1 6 6 1 Functions P
527. storage but rather it is used to distinguish the different Flash bank sectorizations Sector 2 128 byte Sector 9 128 byte Sector 1 128 byte Sector 8 128 byte Sector 7 128 byte Sector 6 128 byte Sector 5 256 byte Sector 4 256 byte Sector 3 512 byte Sector 0 3 75 Kbyte Sector 2 512 byte Sector 1 1 Kbyte Sector 0 1 Kbyte P Flash D Flash Figure 4 2 Flash Bank Sectorization User s Manual 4 3 V1 1 2007 05 Flash Memory V 1 0 Cinfine on XC886 888CLM Flash Memory Sector Partitioning in P Flash e One 3 75 Kbyte sector e Two 128 byte sectors Note In 24 Kbyte Flash variants P Flash banks 4 and 5 have only a single 2 Kbyte sector Sector 0 available Each sector in a P Flash bank is grouped with the corresponding sector from the other bank within a bank pair to form a P Flash bank pair sector For example sector 0 of P Flash bank pair 0 consists of the two sector Os from P Flash banks 0 and 1 Figure 4 3 shows the sectorization of a P Flash bank pair Sector 2 2 x 128 byte Sector 1 2 x 128 byte Sector 0 2 x 3 75 Kbyte P Flash Bank Pair Figure 4 3 P Flash Bank Pair Sectorization Sector Partitioning in D Flash e Two 1 Kbyte sectors e Two 512 byte sectors e Two 256 byte sectors e Four 128 byte sectors The internal structure of each Flash bank represents a sector architecture for flexible erase capab
528. syw T prop Tgego2 Z suw The maximum relative tolerance for fon depends on the Phase Buffer Segments and the re synchronization jump width dfeay lt MIN Ty Tyo 2 x 13 x bit time T 5 AND A valid CAN bit timing must be written to the register NBTR before resetting the bit NCRx INIT i e before enabling the operation of the CAN node The register NBTRx may be written only if bit NCRx CCE Configuration Change Enable is set 15 1 3 2 Bitstream Processor Based on the message objects in the message buffer the Bit Stream Processor generates the remote and data frames to be transmitted via the CAN bus It controls the CRC generator and adds the checksum information to the new remote or data frame After including the Start of Frame Bit and the End of Frame Field the Bit Stream User s Manual 15 9 V1 1 2007 05 MultiCAN V1 0 Cinfine on XC886 888CLM Controller Area Network MultiCAN Controller Processor starts the CAN bus arbitration procedure and continues with the frame transmission when the bus was found in idle state While the data transmission is running the Bit Stream Processor monitors continuously the I O line If outside the CAN bus arbitration phase or the acknowledge slot a mismatch is detected between the voltage level on the I O line and the logic state of the bit currently sent out by the transmit shift register a Last Error interrupt request is generated and the error code is indicated
529. t pin RESET must be held low for at least 100 ns After the RESET pin is deasserted the reset sequence is the same as the power on reset sequence as shown in Figure 7 4 A hardware reset through RESET pin will terminate the idle mode or the power down mode The status of pins MBC TMS and P0 0 is latched by the reset The latched value is used to select the boot options see Section 7 2 3 7 2 1 3 Watchdog Timer Reset The watchdog timer reset is an internal reset The Watchdog Timer WDT maintains a counter that must be refreshed or cleared periodically If the WDT is not serviced correctly and in time it will generate an NMI request to the CPU and then reset the device after a predefined time out period Bit PMCON0O WDTRST is used to indicate the watchdog timer reset status For watchdog timer reset as the EVR is already stable and PLL lock detection is not needed the timing for watchdog timer reset is approximately 200 us which is shorter compared to the other types of resets User s Manual 7 5 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfine on XC886 888CLM Power Supply Reset and Clock Management 7 2 1 4 Power Down Wake Up Reset Power is still applied to the XC886 888 during power down mode as the low power voltage regulator is still operating If power down mode is entered appropriately all important system states will have been preserved in the Flash by software If the XC886 888 is in power down mode thr
530. t Field RESULT Result Register 3 View A High i RMAP 0 PAGE 4 Ay ADC_RCRO Reset 00 Bit Field ae WFR aa Result Control Register 0 Type ee Cu ADC_RCR2 Reset Bit Field VFCT WFR DRCT Result Control Register 2 R R ADC_RCRI1 Reset Result Control Register 1 a el el Tae Result Control Register 3 R R ADG AOR nat 00 e roa OE aeaee IV VOD pe fl RMAP 0 PAGE 5 ADC_CHINFR Reset 00 Bit Field cays ops A Sor ci Pea cae E Channel Interrupt Flag Register m m n el ITNE By ADC_CHINCR Reset 00 Bit Field SUNE E A E Pra a e gu Channel Interrupt Clear Register Type EIES Le Ls User s Manual 3 31 V1 1 2007 05 Memory Organization V 1 2 a II infin eon XC886 888CLM Memory Organization Table 3 9 ADC Register Overview cont d saad Register Name Bit 7 6 5 4 3s 2 1 oO ADC_CHINSR Reset 00y Bit Field ie Se ee ca Cia Se S a rane Channel Interrupt Set Register Type ADC_CHINPR Reset 00 Bit Field a moa oo oo a aa a ae Channel Interrupt Node Pointer Register Type ADC_EVINFR Reset 00 Bit Field Co co oo eee Co ae Event Interrupt Flag Register Type ADC_EVINCR Reset 00y Bit Field oa or a oe oa oy Event Interrupt Clear Flag Register Type Type es ADC_EVINSR Reset 00 Bit Field ae See ay ek ae 4 Event Interrupt Set Flag Register Type ADC_EVINPR Reset 00 Bit Field ar oo oo ee co oa Event Interrupt Node Pointer Register Type
531. t PMCONO SD 2 The idle mode is activated by setting the bit PCON IDLE There are two ways to terminate the combined idle and slow down modes e The idle mode can be terminated by activation of any enabled interrupt CPU operation is resumed and the interrupt will be serviced The next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bit IDLE Nevertheless the slow down mode stays enabled and if required termination must be done by clearing the bit SD in the corresponding interrupt service User s Manual 8 2 V1 1 2007 05 Power Saving Modes V 1 0 Cinfine on XC886 888CLM Power Saving Modes routine or at any point in the program where the user no longer requires the slow down mode e The other way of terminating the combined idle and slow down mode is through a hardware reset 8 1 3 Power down Mode In power down mode the oscillator and the PLL are turned off The FLASH is put into the power down mode The main voltage regulator is switched off but the low power voltage regulator continues to operate Therefore all functions of the microcontroller are stopped and only the contents of the FLASH on chip RAM XRAM and the SFRs are maintained The port pins hold the logical state they had when the power down mode was activated For the digital ports the user must take care that the ports are not floating in power down mode This can be done with internal or external pul
532. t Request Register 1 Reset Value 00 7 6 5 4 3 2 1 0 eae wm ae om r rwh rwh rwh rwh rwh rwh rwh User s Manual 5 25 V1 1 2007 05 Interrupt System V 1 0 Cinfin eon XC886 888CLM Interrupt System Field EIR Description Error Interrupt Flag for SSC This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred 8 TIR rwh_ Transmit Interrupt Flag for SSC This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred RIR rwh Receive Interrupt Flag for SSC This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred rwh Interrupt Flag 0 for ADC This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred ADCSRO ADCSR1 rwh interrupt Flag 1 for ADC This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred rwh Interrupt Flag 1 for MultiCAN This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred rwh Interrupt Flag 2 for MultiCAN This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has oc
533. t Value 00 7 6 5 4 3 2 1 0 r rh rwh rwh Field Bits Type Description IRDY rwh_ interrupt on Result Ready The bit IRDY is set by hardware and reset by aaah No interrupt is triggered at the end of a successful operation An interrupt is triggered at the end of a successful operation IERR Interrupt on Error The bit IERR is set by hardware and reset by a No interrupt is triggered with the occurrence of an error An interrupt is triggered with the occurrence of an error BSY H Bit The MDU is not running any calculation The MDU is still running a calculation 0 A er a 0 if read should be written with 0 User s Manual 10 13 V1 1 2007 05 MDU V2 1 Cinfin eon XC886 888CLM CORDIC Coprocessor 11 CORDIC Coprocessor The CORDIC algorithm is a useful convergence method for computing trigonometric linear hyperbolic and related functions It allows performance of vector rotation not only in the Euclidian plane but also in the Linear and Hyperbolic planes The CORDIC algorithm is an iterative process where truncation errors are inherent Higher accuracy is achieved in the CORDIC Coprocessor with 16 iterations per calculation and kernel data width of at least 20 bits The main advantage of using this algorithm is the low hardware costs involved compared to other complex algorithms The generalized CORDIC algorithm has the following CORDIC equations The factor m controls the vector rotation and selects the set of angles for
534. t cycle of active sampled current I instruction gt l Interrupt response time 3 x machine cycle Figure 5 9 Minimum Interrupt Response Time A longer response time would be obtained if the request is blocked by one of the three previously listed conditions 1 Ifan interrupt of equal or higher priority is already in progress the additional wait time will depend on the nature of the other interrupt s service routine 2 Ifthe instruction in progress is not in its final cycle the additional wait time cannot be more than three machine cycles since the longest instructions MUL and DIV are only four machine cycles long See Figure 5 10 3 If the instruction in progress is RETI or a write access to registers IENO IEN1 or IP H IP1 H the additional wait time cannot be more than five cycles a maximum of one more machine cycle to complete the instruction in progress plus four machine cycles to complete the next instruction if the instruction is MUL or DIV See Figure 5 11 User s Manual 5 15 V1 1 2007 05 Interrupt System V 1 0 infin eon XC886 888CLM Interrupt System U P2 P1 U A D Interrupt 4 cycle current instruction request MUL or DIV sampled active 4 ri j Interrupt Interrupt
535. t field MCR MPSEL is taken into account for pending bit allocation Bit field MCR MPSEL allows the inclusion of the interrupt request node pointer for reception MOIPRn RXINP or transmission MOIPRn TXINP for pending bit allocation in a way that different target locations for the pending bits are used in receive and transmit cases If MPSEL 1111 the location selection operates in the following way Ata transmit event the bit 1 of TXINP define the number k of a Pending Register MSPNDk in which the pending bit will be set At a receive event the bit 1 of RXINP define the number k e The bit position 31 0 in MSPNDk for the pending bit to be set is selected by the lowest bit of TXINP or RXINP and the four least significant bits of MPN General Hints The Message Pending Registers MSPNDk can be written by software Bits that are written with 1 are left unchanged and bits which are written with O are cleared This allows individual MSPNDk bits to be cleared with a single register write access Therefore access conflicts are avoided when the MultiCAN module hardware sets another pending bit at the same time when software writes to the register Each Message Pending Register MSPNDKk is associated with a Message Index Register MSIDk which indicates the lowest bit position of all set 1 bits in Message Pending Register k The MSIDk register is a read only register which is updated immediately when a value in the corresponding Message Pe
536. t field MOFGPRn BOT of the base object points to includes the number of the bottom slave object in the FIFO structure The MOFGPRnhn TOP bit field points to includes the number of the top slave object in the FIFO structure The MOFGPRn CUR bit field points to includes the number of the slave object that is actually selected by the MultiCAN module for message transfer When a message transfer occurs with this object CUR is set to the next message object in the list structure of the slave objects CUR PNEXT of current object If CUR was equal to TOP top of the FIFO reached the next update of CUR will result in CUR BOT wrapped around from the top to the bottom of the FIFO This scheme represents a circular FIFO structure where the bit fields BOT and TOP establish the link from the last to the first element Bit field MOFGPRn SEL of the base object can be used for monitoring purposes It allows a slave object to be defined within the list at which a message interrupt is generated whenever the CUR pointer reaches the value of the SEL pointer Thus SEL User s Manual 15 34 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller allows the end of a predefined message transfer series to be detected or to issue a warning interrupt when the FIFO becomes full PPREV f n 1 PNEXT Slave Object fn PPREV PPREV li 1 Aad PNEXT fli 1 TOP fn Slave Object fi CUR fi B
537. t n MOAMRn n 0 31 Message Object n Acceptance Mask Register Reset Value 3FFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field a Description 28 0 Acceptance Mask for Message Identifier i Bit field AM is the 29 bit mask for filtering incoming messages with standard identifiers AM 28 18 or extended identifiers AM 28 0 For standard identifiers bits AM 17 0 are don t care Acceptance Mask Bit for Message IDE Bit 0 Message object n accepts the reception of both standard and extended frames 1 Message object n receives frames only with matching IDE bit 0 31 30 rw Reserved Read as 0 after reset value last written is read back should be written with O Users Manual 15 91 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Message Object n Arbitration Register MOARn contains the CAN identifier of the message object MOARnhn n 0 31 Message Object n Arbitration Register Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Bits Type Description 28 0 rwh_ CAN Identifier of Message Object n Identifier of a standard message ID 28 18 or an extended message ID 28 0 For standard identifiers bits ID 17 0 are don t care IDE 29 rwh__ Identifier Extension Bit of Message Object n 0 Message object n handles standard frames with 11 bit identifier 1 Message object n handles extend
538. t radix is decimal Hexadecimal constants have a suffix with the subscript letter H e g CO Binary constants have a suffix with the subscript letter B e g 115 When the extents of register fields groups of signals or groups of pins are collectively named in the body of the document they are represented as NAME A B which defines a range from B to A for the named group Individual bits signals or pins are represented as NAME C with the range of the variable C provided in the text e g CFG 2 0 and TOS 0 Units are abbreviated as follows MHz Megahertz us Microseconds kBaud kbit 1000 characters bits per second MBaud Mbit 1 000 000 characters bits per second Kbyte 1024 bytes of memory Mbyte 1 048 576 bytes of memory In general the k prefix scales a unit by 1000 whereas the K prefix scales a unit by 1024 Hence the Kbyte unit scales the expression preceding it by 1024 The kBaud unit scales the expression preceding it by 1000 The M prefix scales by 1 000 000 or 1048576 and u scales by 0 000001 For example 1 Kbyte is 1024 bytes 1 Mbyte is 1024 x 1024 bytes 1 kKBaud kbit are 1000 characters bits per second 1 MBaud Mbit are 1 000 000 characters bits per second and 1 MHz is 1 000 000 Hz Data format quantities are defined as follows Byte 8 bit quantity User s Manual 1 18 V1 1 2007 05 Introduction V 1 1 Cinfin eon XC886 888CLM In
539. t request is generated gateway and FIFO actions are processed etc After the re configuration of the message object after step 3 above the storage of further received data may be undesirable This can be achieved through bit MOCTRn RTSEL Receive Transmit Selected that allows a message object to be disconnected from an ongoing frame reception When a message object wins the receive acceptance filtering its RTSEL bit is set by the MultiCAN module to indicate an upcoming frame delivery The MultiCAN module checks RTSEL whether it is set on successful frame reception to verify that the object is still ready for receiving the frame The received frame is then stored in the message object along with all subsequent actions such as message interrupts FIFO amp gateway actions flag updates only if RTSEL 1 When a message object is invalidated during CAN operation resetting bit MSGVAL RTSEL should be cleared before setting MSGVAL again latest with the same write access that sets MSGVAL to prevent the storage of a frame that belongs to the old User s Manual 15 27 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller context of the message object Therefore a message object re configuration should consist of the following steps 1 Clear MSGVAL bit 2 Re configure the message object while MSGVAL 0 3 Clear RTSEL bit and set MSGVAL again RXEN Bit MOSTATn RXEN enables a m
540. ta must be set to zero In other words the CORDIC Coprocessor is not able to return accurate result for cosh Z sinh Z in a single calculation 11 2 4 1 Domains of Convergence For convergence of result data there are limitations to the magnitude or value of initial data and corresponding useful data form depending on the operating mode used The following are generally applicable regarding convergence of CORDIC result data Rotation Mode Z data must converge towards 0 Initial Z data must be equal or smaller than dd e where e is always decreasing for iteration i In other words Z lt Sum of LUT In circular function this means Z lt integer value representing 1 74 radians For linear function Z lt 2 In hyperbolic function Z lt integer value representing 1 11 radians Vectoring Mode Y data must converge towards 0 The values of initial X and Y are limited by the Z function which is dependent on the corresponding LUT For circular function this means atan Y X lt 1 74 radians For linear function Y X lt 2 For hyperbolic function jatanh Y X lt 1 11 radians In vectoring mode the additional requirement is that X gt 0 While the operating modes of the CORDIC Coprocessor are generally bounded by these convergence limits there are exceptions to the circular rotation and circular vectoring modes which use additional pre and post processing logic to support wider range of inputs Circular Rotat
541. te if both error counters are below the error passive limit of 128 The CAN node is in error passive state if at least one of the error counters is equal or greater than 128 The bus off state is activated if the Transmit Error Counter is equal or greater than the ous off limit of 256 This state is reported by flag NSRx BOFF The device remains in this state until the bus off recovery sequence is finished Additionally bit NSRx EWRN is set when at least one of the error counters is equal or greater than the error warning limit defined by bit field NECNTx EWRNLVL Bit NSRx EWRN is reset if both error counters fall below the error warning limit again User s Manual 15 10 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller 15 1 3 4 CAN Frame Counter Each CAN node is equipped with a frame counter which enables the counting of transmitted received CAN frames or helps obtain information on the time instant when a frame has started to transmit or received by the CAN node CAN frame counting bit time counting is performed by a 16 bit counter which is controlled by register NFCRx Bit field NFCRx CFSEL defines the operation mode of the frame counter e Frame Count Mode The frame counter is incremented after the successful transmission and or reception of a CAN frame The incremented value is stored to the bit field NFCRx CFC and copied to the bit field MOIPRn CFCVAL of the messag
542. ted if the incoming data changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK Baud Rate EIR This interrupt is generated when the incoming clock signal Error Slave deviates from the programmed baud rate by more than mode only 100 Transmit EIR This interrupt is generated when TB was not updated since Error Slave the last transfer if a transfer is initiated by a master mode only User s Manual 12 43 V1 1 2007 05 Serial Interfaces V 1 0 Cinfine on XC886 888CLM Serial Interfaces 12 3 3 Low Power Mode If the SSC functionality is not required at all it can be completely disabled by gating off its clock input for maximal power reduction This is done by setting bit SSC_DIS in register PMCON1 as described below Refer to Chapter 8 1 4 for details on peripheral clock management PMCON1 Power Mode Control Register 1 Reset Value 00 7 6 5 4 3 2 1 0 CBCD CAN DIS MDULDIS T2 DIS GGULDIS ssc pis ADE_DIS r rw rw rw rw rw rw rw Field Description SSC DIS Disable Request Active high SSC is in normal operation default Request to disable the SSC 0 U e Fie O if read should be written with 0 12 3 4 Register Map The addresses of the kernel SFRs are listed in Table 12 8 Table 12 8 SFR Address List Address Register AQ PISEL AA CONL AB CONH AC TBL AD RBL AE BRL AF BRH User s Manual 12 44 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin e
543. ten directly VCOSEL 7 PLL VCO Range Select 0 PLL VCO Range is within 150 MHz 200MHz 1 PLL VCO Range is within 100 MHz 150MHz 0 Reserved Returns 0 if read should be written with O User s Manual 7 20 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfine on XC886 888CLM Power Supply Reset and Clock Management COCON Clock Output Control Register Reset Value 00 7 6 5 4 3 2 1 0 r rw rw rw Field Bits Type Description COREL 3 0 riw Clock Output Divider 0000 fsys 2 0001 fsys 3 0010 fsys 4 0011 fsys 5 0100 foyc 6 0101 fsys 8 0110 fsys 9 0111 fsys 10 1000 fsys 12 1001 fsys 16 1010 fsys 18 1011 fsys 20 1100 fsys 24 1101 fsys 32 1110 fsys 36 1111 fsys 40 rw rw COUTS 4 Clock Out Source Select 0 Oscillator output frequency is selected 1 Clock output frequency is chosen by the bit field COREL and the bit TLEN TLEN 5 Toggle Latch Enable This bit is only applicable when COUTS is set to 1 0 Toggle Latch is disabled Clock output frequency is chosen by the bit field COREL 1 Toggle Latch is enabled Clock output frequency is half of the frequency that is chosen by the bit field COREL The clock output frequency has 50 duty cycle 0 7 6 Reserved Returns 0 if read should be written with 0 User s Manual 7 21 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfin eon XC886 888CLM Power Supply Reset and Clock Management Note Registers OSC_CON PLL_CON CMCON and COCON are not reset during the watc
544. ten with 0 User s Manual 13 26 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers Register RC2 is used for a 16 bit reload of the timer count upon overflow or a capture of current timer count depending on the mode selected RC2L Timer 2 Reload Capture Register Low Reset Value 00 r 6 9 4 3 2 1 0 RC2 rwh Field Description RC2 LE 0 rwh Reload Capture Value 7 0 If CP RL2 0 these contents are loaded into the timer register upon an overflow condition If CP RL2 1 this register is loaded with the current timer count upon a negative positive transition at pin T2EX when EXEN2 1 RC2H Timer 2 Reload Capture Register High Reset Value 00 7 6 5 4 3 2 1 0 RC2 rwh Field Bits Type Description RC2 7 0 rwh Reload Capture Value 15 8 lf CP RL2 0 these contents are loaded into the timer register upon an overflow condition lf CP RL2 1 this register is loaded with the current timer count upon a negative positive transition at pin T2EX when EXEN2 1 User s Manual 13 27 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers Register T2 holds the current 16 bit value of the Timer 2 count T2L Timer 2 Register Low Reset Value 00 7 6 5 4 3 2 1 0 THL2 rwh Field Description THL2 7 CN rwh Timer 2 Value 7 0 These bits indicate the current timer value T2H Timer 2 Register High Reset Value 00 7 6 5 4 3 2 1 0 THL2 rwh Field Description THL2 7 CONN rwh Timer 2 Value 1
545. tents are compared after every detected edge at the hall input pins with the pattern at the hall input pins in order to detect the occurrence of the next desired expected hall pattern or a wrong pattern lf the current hall pattern at the hall input pins is equal to the bit field EXPH bit CHE correct hall event is set and an interrupt request is generated if enabled by bit ENCHE If the current hall pattern at the hall input pins is not equal to the bit fields CURH or EXPH bit WHE wrong 0 7 6 r Reserved Returns 0 if read should be written with 0 Note The bits in the bit fields EXPH and CURH correspond to the hall patterns at the input pins CCPOSx x 0 1 2 in the following order EXPH 2 EXPH 1 EXPH 0 CURH 2 CURH 1 CURH 0 CCPOS2 CCPOS 1 CCPOSO User s Manual 14 77 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Register MCMCTR contains control bits for the multi channel functionality MCMCTR Multi Channel Mode Control Register Reset Value 00 7 6 5 4 3 2 1 0 r rw r rw Field Description SWSEL Bre 0 Switching Selection Bit field SWSEL selects one of the following trigger request sources next multi channel event for the shadow transfer from MCMPS to MCMP The trigger request is stored in the reminder flag R until the shadow transfer is done and flag R is cleared automatically with the shadow transfer The shadow transfer takes place synchronously with an event selected i
546. ter is disabled DRCTR 0 the user can read the 8 bit or 10 bit conversion result from either RESRxL H or RESRAXL H In particular for 8 bit conversion without accumulation the result can be read from RESRXH with a single instruction Hence depending on the application requirement the user can choose to read from the different views User s Manual 16 21 V1 1 2007 05 ADC V 1 0 infin eon XC886 888CLM Analog to Digital Converter Result Register x High Result Register x Low 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 R10 R9 R8 R7 R6 R5 R3 R2 R1 RO VF DRO CHNR RESRxH RESRxL RESRAxH RESRAxL 7 6 5432 10 7 6 543210 59 43210 7 6 543210 R7 R6 R5 R4 R3 R2 R1 RO 0 0 0 VF DRC CHNR R6 R5 R4 R3 R2 R1 RO 0 0 VFIDRO CHNR rh rh rh rh 8 bit conversion with without accumulation 8 bit conversion without accumulation 7 6 543210 R5 R1 RO 0 VF DRC CHNR R5 VF rh rh rh rh 10 bit conversion with without accumulation 8 bit conversion accumulated 9 bit 7 6 543210 R7 R2 R1 RO VF IDRO CHNR rh rh 10 bit conversion without accumulation 7 6 5432
547. ter reset Figure 3 7 Active Memory Map Select 3 6 1 User Mode If MBC TMS P0 0 1 0 x the Boot ROM will jump to program memory address 0000 to execute the user code in the Flash or ROM memory This is the normal operating mode of the XC886 888 However for Flash devices if program memory address 0000 contains 00 indicating the Flash memory is not yet programmed with user code BootStrap Loader BSL mode will be entered instead to facilitate Flash programming Note User should always program a non zero value to program memory address 0000 to avoid entering BSL mode unintentionally 3 6 2 Bootstrap Loader Mode lf MBC TMS P0 0 0 0 x the software routines of the BootStrap Loader BSL located in the Boot ROM will be executed allowing the XRAM and Flash memory if available to be programmed erased and executed Refer to Chapter 4 7 for the different BSL working modes User s Manual 3 42 V1 1 2007 05 Memory Organization V 1 2 Cinfine on XC886 888CLM Memory Organization 3 6 3 OCDS Mode If MBC TMS P0 0 0 1 0 the OCDS mode will be entered for debugging program code The OCDS hardware is initialized and a jump to program memory address 0000 is performed next The user code in the Flash or ROM memory is executed and the debugging process may be started During the OCDS mode the lowest 64 bytes 00 3F in the internal data memory address range may be alternatively mapped to
548. terrupt indicates that the result with without accumulation in the corresponding result register is ready and can be read e Read ADC result User s Manual 16 29 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 6 Register Map All ADC register names described in the following sections are referenced in other chapters of this document with the module name prefix ADC_ e g ADC_GLOBCTR The addresses of the ADC SFRs are listed in Table 16 3 and Table 16 4 Table 16 3 SFR Address List for Pages 0 3 Address Page 0 Page 2 Page 3 CA GLOBCTR RESROL RESRAOL CB GLOBSTR RESROH RESRAOH Tor PRAR RESR1L RESRA1L CD LCBR RESR1H RESRA1H CE INPCRO RESR2L RESRA2L CF ETRCR RESR2H RESRA2H D2 CHCTR6 RESR3L RESRASL D3 CHCTR7 RESR3H RESRASH Table 16 4 SFR Address List for Pages 4 7 User s Manual 16 30 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter The ADC SFRs are located in the standard memory area RMAP 0 and are organized into 7 pages The ADC_PAGE register is located at address D1 It contains the page value and page control information ADC_PAGE Page Register for ADC D1 Reset Value 00 7 6 5 4 3 2 1 0 sees W W r rw PAGE 2 0 Page Bits When written the value indicates the new page address When read the value indicates the currently active page STNR 5 4 Storage Number This number indicates which storage bit field is the
549. th BR_VALUE User s Manual 12 50 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 3 5 4 Transmit and Receive Buffer Register The SSC transmitter buffer register TB contains the transmit data value TBL Transmitter Buffer Register Low Reset Value 00 7 6 5 4 3 2 1 0 rw Field Description TB_VALUE 0 Transmit Data Register Value TB VALUE is the data value to be transmitted Unselected bits of TB are ignored during transmission The SSC receiver buffer register RB contains the receive data value RBL Receiver Buffer Register Low Reset Value 00 7 6 4 3 2 1 0 RB VALUE rh Field Bits Type Description RB VALUE 7 0 rh Receive Data Register Value RB contains the received data value RB_ VALUE Unselected bits of RB will not be valid and should be ignored User s Manual 12 51 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Timers 13 Timers The XC886 888 provides four 16 bit timers Timer 0 Timer 1 Timer 2 and Timer 21 They are useful in many timing applications such as measuring the time interval between events counting events and generating signals at regular intervals In particular Timer 1 can be used as the baud rate generator for the on chip serial port Timer 0 and Timer 1 Features e Four operational modes Mode 0 13 bit timer counter Mode 1 16 bit timer counter Mode 2 8 bit timer counter with auto reload
550. th a count value of zero The single shot mode and the synchronization feature of T13 to T12 allow the generation of events with a programmable delay after well defined PWM actions of T12 For example this feature can be used to trigger AD conversions after a specified delay to avoid problems due to switching noise synchronously to a PWM event TCTR2L Timer Control Register 2 Low Reset Value 00 7 6 5 4 3 2 1 0 T13 T13 T13 T12 TED TEC SSC SSC r rw rw rw rw Field oe Description T12SSC Timer T12 Single Shot Control o bit controls the single shot mode of T12 The single shot mode is disabled no hardware action on T12R The single shot mode is enabled the bit 112R is reset by hardware if 12 reaches its period value in edge aligned mode T12 reaches the value 1 while down counting in center aligned mode In parallel to the reset action of bit T12R the bits CC6xST x 0 1 2 are reset User s Manual 14 62 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field T13SSC 4 6 T13TEC 2 7 Description Timer T13 Single Shot Control This bit controls the single shot mode of T13 0 No hardware action on T13R 1 The single shot mode is enabled the bit T13R is reset by hardware if T13 reaches its period value In parallel to the reset action of bit T13R the bit CC63ST is reset rw T13 Trigger Event Control Bit field T13TEC selects the trigger event to start T13 automa
551. the 64 byte monitor RAM or the internal data RAM 3 6 4 User JTAG Mode If MBC TMS P0 0 1 1 0 the Boot ROM will jump to program memory address 0000 to execute the user code in the Flash or ROM memory This is similar to the normal user mode described in Section 3 6 1 with the addition that the primary JTAG port is automatically configured to allow hot attach User s Manual 3 43 V1 1 2007 05 Memory Organization V 1 2 Cinfin eon XC886 888CLM Flash Memory 4 Flash Memory The XC886 888 has an embedded user programmable non volatile Flash memory that allows for fast and reliable storage of user code and data It is operated with a single 2 5 V supply from the Embedded Voltage Regulator EVR and does not require additional programming or erasing voltage The sectorization of the Flash memory allows each sector to be erased independently Features e In System Programming ISP via UART e In Application Programming IAP e Error Correction Code ECC for dynamic correction of single bit errors e Background program and erase operations for CPU load minimization e Support for aborting erase operation e 32 or 64 byte minimum program width e 1 sector minimum erase width e 1 byte read access e 3 x CCLK period read access time inclusive of one wait state e Flash is delivered in erased state read all zeros User s Manual 4 1 V1 1 2007 05 Flash Memory V 1 0 Cinfin eon XC886 888CLM Flash Memory 4 1 Flash M
552. the circular linear and hyperbolic function Xie m dy 2 11 1 Vier Mt x12 11 2 Lig Sar Ge 11 3 where m 1 Circular function basic CORDIC with e atan 2 m 0 Linear function with e 2 m 1 Hyperbolic function with e atanh 2 For clarity the document uses the following terms for referencing CORDIC data e Result Data Final result data at the end of CORDIC calculation Bit BSY no longer active e Calculated Data Intermediate or last data resulting from CORDIC iterations e Initial Data Data used for the very first CORDIC iteration is usually user initialized data User s Manual 11 1 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfin eon XC886 888CLM CORDIC Coprocessor 11 1 Features e Modes of operation Supports all CORDIC operating modes for solving circular trigonometric linear multiply add divide add and hyperbolic functions Integrated look up tables LUTs for all operating modes e Circular vectoring mode Extended support for values of initial X and Y data up to full range of 2 2 1 for solving angle and magnitude e Circular rotation mode Extended support for values of initial Z data up to full range of 2 2 1 representing angles in the range z 2 1 2 x for solving trigonometry e Implementation dependent operational frequency of up to 80 MHz e Gated clock input to support disabling of module e 16 bit accessible data width 24 bit kernel data
553. the current software breakpoint 17 3 1 3 External Breaks These debug events are of Break Now type and can be raised in two ways e By a request via the JTAG interface using a special sequence an external device connected to the JTAG can break the user program running on XC886 888 and start a debug session e By asserting low the dedicated Monitor and BootStrap loader Control line MBC while the XC886 888 is running and this type of break is enabled used for reaction to asynchronous events from the external world 17 3 1 4 NMI mode priority over Debug mode While the core is in NMI mode after an NMI request has been accepted and before the RETI instruction is executed i e the time during a NMI servicing routine certain debug functions are blocked restricted 1 No external break is possible while the core is servicing an NMI External break requested inside a NMl servicing routine will be taken only after RETI is executed 2 A breakpoint into NMlI servicing routine is taken but single step is not possible afterwards lf a step is requested the servicing routine will run as coded and monitor mode will be invoked again only after a RETI is executed Hardware breakpoints and software breakpoints proceed as normal while CPU is in NMI mode 17 3 2 Debug Actions In case of a debug event the OCDS system can respond in two ways depending on the current configuration 17 3 2 1 Call the Monitor Program XC886 888 comes with
554. the functions of the XC886 888 and the various reset types that affect these functions The symbol W signifies that the particular function is reset to its default state Table 7 1 Effect of Reset on Device Functions Module Wake Up Watchdog Hardware Power On Brownout Function Reset Reset Reset Reset Reset Peripherals On Chip Not Ea Not a Not a R un Affected un Static RAM Reliable Reliable Reliable reliable reliable Oscillator Not affected PLL EVR The voltage Not affected regulator is oo on FLASH NMI C ORN Disabled A S User s Manual 7 7 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfine on XC886 888CLM Power Supply Reset and Clock Management 7 2 3 Booting Scheme When the XC886 888 is reset it must identify the type of configuration with which to start the different modes once the reset sequence is complete Thus boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins After power on reset or hardware reset the pins MBC TMS and P0 0 collectively select the different boot options Table 7 2 shows the available boot options in the XC886 888 Table 7 2 XC886 888 Boot Selections 0x User Mode on chip OSCIPLL non bypassed 0000 0x BSL Mode OSCIPLL non bypassed normal 0000 1 User JTAG Mode on chip OSC PLL non 0000 bypassed normal 0 For the Flash devices BSL mode is automatically
555. the operations of Timer 0 and Timer 1 They can be accessed from both the standard non mapped and mapped SFR area Table 13 2 lists the addresses of these SFRs Table 13 2 Register Map Address Register 88y TCON 89 TMOD 8A TLO 8B TL1 8C THO 8D TH1 A8 IENO User s Manual 13 9 V1 1 2007 05 Timers V 1 0 Cinfin eon XC886 888CLM Timers 13 1 5 Register Description The low bytes TLO TL1 and high bytes THO TH1 of both Timer O and Timer 1 can be combined to a one timer configuration depending on the mode used Register TCON controls the operations of Timer 0 and Timer 1 The operating modes of both timers are selected using register TMOD Register IENO contains bits that enable interrupt operations in Timer 0 and Timer 1 TLx x 0 1 Timer x Low Byte Reset Value 00 7 6 9 4 3 2 1 0 VAL rwh Field Description TLx VAL x 0 1 a 0 rwh_ Timer 0 1 Low Register OMO TLx holds the 5 bit prescaler value OM1 TLx holds the lower 8 bit part of the 16 bit timer value OM2 TLx holds the 8 bit timer value OM3 TLO holds the 8 bit timer value TL1 is not used THx x 0 1 Timer x High Byte Reset Value 00 7 6 5 4 3 2 1 0 VAL rwh User s Manual 13 10 V1 1 2007 05 Timers V 1 0 Cinfine on XC886 888CLM Timers Field Description THx VAL x 0 1 0 rwh_ Timer 0 1 High Register OMO THx holds the 8 bit timer value OM1 THx holds the higher 8 bit part of the 16 bit timer value OM2 THx holds the
556. the pattern on pin CCPOSx and if equal bit CHE is set 0 A transition to a correct expected hall event has not yet been detected since this bit has been reset for the last time A transition to a correct expected hall event has been detected 14 81 V1 1 2007 05 Cinfin eon XC886 888CLM Capture Compare Unit 6 Field Bits Type Description WHE 5 Wrong Hall Event On every valid hall edge the contents of EXPH are compared with the pattern on pin CCPOSx If both comparisons CURH and EXPH with CCPOSx are not true bit WHE wrong hall event is set 0 A transition to a wrong hall event not the expected one has not yet been detected since this bit has been reset for the last time 1 A transition to a wrong hall event not the expected one has been detected rh IDLE rh IDLE State This bit is set together with bit WHE wrong hall event and it must be reset by software 0 No action 1 Bit field MCMP is cleared and held to 0 the selected outputs are set to passive state h STR 7 r Multi Channel Mode Shadow Transfer Request This bit is set when a shadow transfer from MCMOUTS to MCMOUT takes places in multi channel mode 0 The shadow transfer has not yet taken place 1 The shadow transfer has taken place Note Not all bits in register IS can generate an interrupt Other status bits have been added which have a similar structure for their set and reset actions Note The interrupt generation is independent fro
557. they can be set to any value Internally the microcontroller will transfer the valid data 6 bytes of the Data Block into a buffer and count the number of data bytes received Microcontroller will program the data once the maximum buffer size is reached If an EOT Block is received before maximum bytes are reached then the remaining data bytes are programmed PC host 1 LIN_Block_Length is always 9 bytes inclusive of a NAD and a checksum User s Manual 18 20 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader has to transfer data in multiples of 32 for D Flash or 64 P Flash to ensure correct programming Note In XC886 888 flash programming needs to be performed in multiples of wordline For P Flash and D Flash 1 wordline is 64 bytes and 32 bytes respectively The maximum buffer size defined is 64 bytes for P Flash and 96 bytes for D flash Note In P Flash programming PC host needs to insert 2 bytes of blank data after every 64 bytes of data sent i e every 65th and 66th data byte equals zero 18 1 3 4 The Activation of Modes 1 3 and 9 Mode 1 as well as Mode9 and Mode 3 are used to execute a user program in the XRAM Flash of the microcontroller at OFOOOH and OOOOH respectively The header block for this mode has the following structure The Header Block Mode Data Description Not used The five bytes are not used and will be ignored in Mode 1 3 9 For Modes 1 3 and 9 the he
558. tic set of T13R for synchronization to T12 compare signals according to following combinations 000 no action 001 set 113R ona 112 compare event on channel 0 010 set 113R ona 112 compare event on channel 1 011 set 113R ona 112 compare event on channel 2 100 set T13R on any 112 compare event on the channels O 1 or 2 101 set 113R upon a period match of T12 110 set T13R upon a zero match of T12 while counting up 111 set T13R on any edge of inputs CCPOSx Timer T13 Trigger Event Direction Bit field T13TED delivers additional information to control the automatic set of bit T13R in the case that the trigger action defined by T13TEC is detected 00 no action 01 while T12 is counting up 10 while T12 is counting down 11 independent on the count direction of T12 T13TED 0 Reserved Returns 0 if read should be written with 0 Example lf the timer T13 is intended to start at any compare event on T12 T13TEC 100 the trigger event direction can be programmed to counting up gt gt a 112 channel 0 1 2 compare match triggers T13R only while 112 is User s Manual 14 63 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 counting up counting down gt gt a T12 channel 0 1 2 compare match triggers 113R only while 112 is counting down independent from bit CDIR gt gt each T12 channel 0 1 2 compare match triggers T13R The timer count direction is taken from the value of bit CDIR As a
559. tifier Frames with higher identifier MOAR 28 is the most significant bit MSB of the overall identifier standard identifier MOAR 28 18 and identifier extension MOAR 17 0 MOARJ 0 is the least significant bit LSB of the overall identifier User s Manual 15 94 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Message Object n Data Register Low MODATALn contains the lowest four data bytes of message object n Unused data bytes are set to zero upon reception and ignored for transmission MODATALNh n 0 31 Message Object n Data Register Low Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rwh rwh Field Bits Type Description DBO 7 0 Data Byte 0 of Message Object n DB1 15 8 Data Byte 1 of Message Object n DB2 23 16 Data Byte 2 of Message Object n DB3 31 24 Data Byte 3 of Message Object n User s Manual 15 95 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Message Object n Data Register High MODATAH contains the highest four data bytes of message object n Unused data bytes are set to zero upon reception and ignored for transmission MODATAHnh n 0 31 Message Object n Data Register High Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB5 DB4 rwh rwh Field Bits Type Description DB4 7 0 Data Byte 4 of Message Object n DB5 15 8 Data
560. time within 5 ms after the erase operation has started This is a strict requirement that must be ensured by the user Otherwise the erase operation cannot be aborted A successful abort action is indicated by a Flash NMI event bit FNMIFLASH in register NMISR is set and if enabled via NMICON NMIFLASH an NMI to the CPU is triggered to enter the Flash NMI service routine See Figure 4 9 At this point all Flash banks are in ready to read mode Table 4 3 Flash Erase Abort Subroutine Subroutine DFF3 FLASH ERASE ABORT Input P Flash bank s or D Flash bank is are in erase mode Flash NMI NMICON NMIFLASH is enabled 1 or disabled 0 Output PSW CY 0 Flash erase abort is in progress 1 Flash erase abort is not started Stack size required 3 bytes Resource ACC PSW used destroyed 1 Refer to XC886 888 Data Sheet for Flash data profile User s Manual 4 19 V1 1 2007 05 Flash Memory V 1 0 Cinfin eon XC886 888CLM Flash Memory 4 8 4 Flash Bank Read Status Each call of the Flash bank read status subroutine allows the checking of ready to read Status of the Flash bank Before calling this subroutine the user must ensure that the ACC SFR is set accordingly see Table 4 4 Table 4 4 Flash Bank Read Status Subroutine Subroutine DFFO FLASH _READ_STATUS Input ACC Select desired Flash bank for ready to read status 00 P Flash Bank Pair 0 01 P Flash Bank Pair 1 02 P Flash Bank Pair 2 03 D Flash Bank
561. timer T13 is stopped the internal clock divider is reset in order to ensure reproducible timings and delays T13PRL Timer T13 Period Register Low Reset Value 00 7 6 9 4 3 2 1 0 rwh Field Bits Type Description T13PVL 7 0 rwh T13 Period Value Low Byte The value T13PV defines the counter value for T13 which leads to a period match On reaching this value the timer T13 is set to zero User s Manual 14 52 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 T13PRH Timer T13 Period Register High Reset Value 00 7 6 5 4 3 2 1 0 T13PVH rwh Field Description T13PVH Bis w T13 Period Value High Byte The value T13PV defines the counter value for T13 which leads to a period match On reaching this value the timer T13 Is set to zero CC63RL Capture Compare Register for Channel CC63 Low Reset Value 00 7 6 9 4 3 2 1 0 CC63VL rh Field Bits Type Description CC63VL 7 0 rh Channel CC63 Compare Value Low Byte The bit field CC63V contains the value that is compared to the T13 counter value CC63RH Capture Compare Register for Channel CC63 High Reset Value 00 7 6 5 4 3 2 1 0 CC63VH rh User s Manual 14 53 V1 1 2007 05 CCU6B V 1 0 Cinfine on XC886 888CLM Capture Compare Unit 6 Field Description CC63VH ete Channel CC63 Compare Value High Byte The bit field CC63V contains the value that is compared to the T13 counter value CC63SRL Capture Compare Shadow Register for
562. timing analysis and baud rate detection for each CAN node via a frame counter e Full CAN functionality A set of 32 message objects can be individually Allocated assigned to any CAN node Configured as transmit or receive object Set up to handle frames with 11 bit or 29 bit identifier Identified by a timestamp via a frame counter Configured to remote monitoring mode e Advanced acceptance filtering Each message object provides an individual acceptance mask to filter incoming frames A message object can be configured to accept standard or extended frames or to accept both standard and extended frames Message objects can be grouped into four priority classes for transmission and reception The selection of the message to be transmitted first can be based on frame identifier IDE bit and RTR bit according to CAN arbitration rules or according to its order in the list e Advanced message object functionality Message objects can be combined to build FIFO message buffers of arbitrary size limited only by the total number of message objects Message objects can be linked to form a gateway that automatically transfers frames between two different CAN buses A single gateway can link any two CAN nodes An arbitrary number of gateways can be defined e Advanced data management The message objects are organized in double chained lists List reorganizations can be performed at any time even during full operation of the CAN
563. tion In System Programming ISP is available through the Boot ROM based BootStrap Loader BSL enabling convenient programming and erasing of the embedded Flash via an external host e g personal computer Other key features include a Capture Compare Unit 6 CCU6 for the generation of pulse width modulated signal with special modes for motor control a 10 bit Analog to Digital Converter ADC with extended functionalities such as autoscan and result accumulation for anti aliasing filtering or for averaging a Multiplication Division Unit MDU to support the XC800 Core in math intensive real time control applications a CORDIC COrdinate Rotation Digital Computer Coprocessor for high speed computation of trigonometric linear or hyperbolic functions and an On Chip Debug Support OCDS unit for software development and debugging of XC800 based systems The XC886 888 also features an on chip oscillator and an integrated voltage regulator to allow a single voltage supply of 3 3 or 5 0 V For low power applications various power saving modes are available for selection by the user Control of the numerous on chip peripheral functionalities is achieved by extending the Special Function Register SFR address range with an intelligent paging mechanism optimized for interrupt handling User s Manual 1 1 V1 1 2007 05 Introduction V 1 1 Cinfine on XC886 888CLM Introduction Figure 1 1 shows the functional units of the XC886 888 A Flas
564. tion of POR is 1 5 V The monitoring function is used in both active mode and power down mode During power up after Vijo exceeds 1 5 V the reset of EVR is extended by a delay that is typically 300 us In active mode Vppc S monitored mainly by the Vppc detector and a reset is generated when Vppc drops below 2 1 V In power down mode the Vppc is monitored by the POR and a reset is generated when Vppc drops below 1 5 V User s Manual 7 2 V1 1 2007 05 Power Reset and Clock V 1 0 Cinfine on XC886 888CLM Power Supply Reset and Clock Management 7 2 Reset Control The XC886 888 has five types of resets power on reset hardware reset watchdog timer reset power down wake up reset and brownout reset When the XC886 888 is first powered up the status of certain pins see Table 7 2 must be defined to ensure proper start operation of the device At the end of a reset sequence the sampled values are latched to select the desired boot option which cannot be modified until the next power on reset or hardware reset This guarantees stable conditions during the normal operation of the device The hardware reset function can be used during normal operation or when the chip is in power down mode A reset input pin RESET is provided for the hardware reset The Watchdog Timer WDT module is also capable of resetting the device if it detects a malfunction in the system Another type of reset that needs to be detected is the reset while
565. tion of the block is successful Transmission of 4 byte data follows in Mode A Ready to receive the next block Block Error FF Data Flash start address is out of Retransmit a valid range Header block All others Either the block type is Retransmit a valid undefined or block the communication structure is invalid Checksum FE All Mismatch exists between Retransmit the Error the calculated and block received Checksum 2 Protection FD Header 0 2 Protection against external Error 4 8 access is enabled i e FPASSWD is valid User s Manual 18 7 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader 18 1 2 Bootstrap Loader via UART Upon entering UART BSL a serial connection is established and the transfer speed baud rate of the serial communication partner host is automatically synchronized in the following steps e STEP 1 Initialize serial interface for reception and timer for baud rate measurement e STEP 2 Wait for test byte 80 from host e STEP 3 Synchronize the baud rate to the host e STEP 4 Send Acknowledge byte 55 to the host e STEP 5 Enter Phase Il Baud rate is established once in the beginning of UART BSL Until next hardware reset Subsequent communication between host and the microcontroller will follow this baud rate The serial port of the microcontroller is set to Mode 1 8 bit UART variable baud rate while Timer 2 is configured to a
566. tions User s Manual 6 10 V1 1 2007 05 Parallel Ports V 1 0 Cinfine on XC886 888CLM Parallel Ports 6 2 Register Map The Port SFRs are located in the standard memory area RMAP 0 and are organized into 4 pages The PORT_PAGE register is located at address B2 It contains the page value and page control information The addresses of the Port SFRs are listed in Table 6 2 Table 6 2 SFR Address List for Pages 0 3 Address Page 0 Page 2 Page 3 80 PO DATA PO ALTSELO PO OD 86 PO DIR PO_ALTSEL1 90 P1 DATA Pi ALTSELO P1_OD 91 P1_DIR P1_ALTSELI 92 P5 DATA P5 ALTSELO P5 OD 93 P5 DIR P5 ALTSEL1 AO P2 DATA A1 P2 DIR BO P3 DATA P3 ALTSELO P3 OD B1 P3_DIR P3_ALTSEL1 C8 P4 DATA P4 ALTSELO P4 OD C9 P4 DIR P4 ALTSELI PORT_PAGE Page Register for PORT Reset Value 00 7 6 5 4 3 1 0 W W r rw User s Manual 6 11 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports Field Bits Type Description PAGE 2 0 rw Page Bits When written the value indicates the new page When read the value indicates the currently active page STNR 5 4 w Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP If OP 10 the contents of PAGE are saved in STx before being overwritten with the new value If OP 11 the contents of PAGE are overwritten by the contents of STx The value written to the bit posit
567. tively A read action targets the actually used values whereas a write action targets the shadow bits In capture mode these bits are not used T13IM T rwh T13 Inverted Modulation Bit T13IM inverts the T13 signal for the modulation of the CC6x and COUT6x x 0 1 2 signals 0 T13 output is not inverted 1 T13 output is inverted for further modulation This bit has a shadow bit and is updated in parallel to the compare and period registers of T13 A read action targets the actually used values whereas a write action targets the shadow bit The Compare Status Modification Register contains control bits allowing for modification by software of the Capture Compare state bits User s Manual 14 56 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 CMPMODIFL Compare State Modification Register Low Reset Value 00 7 6 5 4 3 2 1 0 0 MCC MCC MCC MCC 63S 62S 61S 60S r W r W W W Field Bits Type Description MCC6xS 0 1 iw Capture Compare Status Modification Bits Set x 0 1 2 3 2 6 These bits are used to set the corresponding CC6xST bits by software This feature allows the user to individually change the Status of the output lines by software e g when the corresponding compare timer is stopped This allows a bit manipulation of CC6xST bits by a single data write action The following functionality of a write access to bits concerning the same capture compare state bit is provided MCC 6
568. to 1 RESULT is loaded with FF User s Manual 12 21 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 1 4 3 Timer 1 In modes 1 and 3 of UART module Timer 1 can be used for generating the variable baud rates In theory this timer could be used in any of its modes But in practice it should be set into auto reload mode Timer 1 mode 2 with its high byte set to the appropriate value for the required baud rate The baud rate is determined by the Timer 1 overflow rate and the value of SMOD as follows 12 6 SMOD 2 X PCLK 32 x 2x 256 TH1 Mode 1 3 baud rate Alternatively for a given baud rate the value of Timer 1 high byte can be derived 12 7 SMOD 2 X PCLK TH1 256 gt 32 x 2x Model 3 baud rate Note Timer 1 can neither indicate an overflow nor generate an interrupt if Timer 0 is in mode 3 Timer 1 is halted while Timer 0 takes over the use of its control bits and overflow flag Hence the baud rate supplied to the UART module is defined by Timer 0 and not Timer 1 User should avoid using Timer 0 and Timer 1 in mode 3 for baud rate generation Note Timer 1 cannot be used to generate the variable baud rate in UVART1 User s Manual 12 22 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces 12 1 5 Port Control The UART modules shift in data through RXD which can be selected from three different
569. to the data register Px_DATA Software can set or clear the bit in Px_DATA and therefore directly influence the state of the port pin If an on chip peripheral uses the pin for output signals alternate output lines AltDataOut can be switched via the multiplexer to the output driver circuitry Selection of the alternate function is defined in registers Px_ALTSELO and Px_ALTSEL1 When a port pin is used as an alternate function its direction must be set accordingly in the register Px_DIR Each pin can also be programmed to activate an internal weak pull up or pull down device Register Px _PUDSEL selects whether a pull up or the pull down device is activated while register Px_PUDEN enables or disables the pull device User s Manual 6 2 V1 1 2007 05 Parallel Ports V 1 0 Infineon Internal Bus Px PUDSEL Pull up Pull down Select Register aN Px_PUDEN lt gt Pull up Pull down Enable Register Px OD t Open Drain Control Register Px DIR Direction Register Px ALTSELO Alternate Select Register 0 amp _ _ _ Px ALTSEL1 Alternate Select Register 1 4 XC886 888CLM Parallel Ports ir Pull Down Device y AltDataOut 3 B 11 enable Output AltDataOut 2 Bl 40 Driver AltDataOut1 gt 01 P 00 enable Px Data Input Data Register gin Pues VY Schmitt T
570. troduction 1 6 Reserved Undefined and Unimplemented Terminology In tables where register bit fields are defined the following conventions are used to indicate undefined and unimplemented function Further types of bits and bit fields are defined using the abbreviations shown in Table 1 4 Table 1 4 Bit Function Terminology Function of Bits Description Unimplemented Register bit fields named 0 indicate unimplemented functions with the following behavior Reading these bit fields returns 0 Writing to these bit fields has no effect These bit fields are reserved When writing software should always set such bit fields to 0 in order to preserve compatibility with future products Setting the bit fields to 1 may lead to unpredictable results Undefined Certain bit combinations in a bit field can be labeled Reserved indicating that the behavior of the XC886 888 is undefined for that combination of bits Setting the register to undefined bit combinations may lead to unpredictable results Such bit combinations are reserved When writing software must always set such bit fields to legal values as provided in the bit field description tables rw The bit or bit field can be read and written r The bit or bit field can only be read read only W The bit or bit field can only be written write only Reading always return 0 h The bit or bit field can also be modified by hardware such as a Status bit This attribute can be
571. troller Area Network MultiCAN Controller 15 1 6 2 Transmit Acceptance Filtering A message is requested for transmission by setting a transmit request in the message object that holds the message If more than one message object have a valid transmit request for the same CAN node one of these message objects is chosen for transmission because only a single message object can be transmitted at one time on a CAN bus A message object is qualified for transmission on a CAN node if the following four conditions are are fulfilled 1 The message object is allocated to the message object list of the CAN node 2 Bit MOSTATn MSGVAL is set 3 Bit MOSTATn TXRQ is set 4 Bit MOSTATn TXENO and MOSTATn TXEN1 are set A priority scheme determines which of all qualifying message objects is transmitted first The following assumption is made message object a MOa and message object b MOb are two message objects qualified for transmission MOb is a list successor of MOa This means MOb can be reached by means of successively stepping forward in the list starting from a If both message objects belong to a different priority class different value of bit field MOARn PRI then the message object with lower MOAR PRI value has higher transmit priority and will be transmitted first If both message objects belong to the same priority class identical PRI bit field in register MOARn MOa has a higher transmit priority than MOb if one of the follow
572. ual 15 14 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller CAN Bus 0 CAN Bus 1 2 T A CAN CAN Fienenie Node 0 Node 1 1 Object 1 Object 1 Object in List O in List 1 in List 2 2 Object 2 Object 2 Object in List O in List 1 in List 2 Last Object Last Object Last Object in List O in List 1 in List 2 MultiCAN_list_to_can Figure 15 7 Message Objects Linked to CAN Nodes 15 1 4 4 List Command Panel The list structure cannot be modified directly by means of write accesses to the LIST registers and the PPREV PNEXT and LIST bit fields in the register MOSTATn as they are read only The management of the list structure is performed by and limited to the list controller inside the MultiCAN module The list controller is controlled via a command panel allowing the user to issue list allocation commands to the list controller The list controller basically serves two purposes 1 Ensure that all operations that modify the list structure result in a consistent list structure 2 Present flexibility to the user The list controller and the associated command panel allows the programmer to concentrate on the final properties of the list which are characterized by the allocation of message objects to a CAN node and the ordering relation between objects that are allocated to the same list The process of list re building is done in the list controller User s Manual 15 15 V1 1 2
573. ultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Field Bits Type Description DIR 11 rh Message Direction 0 Receive Object selected With TXRQ 1 a remote frame with the identifier of message object n is scheduled for transmission On reception of a data frame with matching identifier the message is stored in message object n 1 Transmit Object selected lf TXRQ 1 message object n is scheduled for transmission of a data frame On reception of a remote frame with matching identifier bit TXRQ is set LIST 15 12 rh List Allocation LIST indicates the number of the message list to which message object n is allocated LIST is updated by hardware when the list allocation of the object is modified by a panel command PPREV Pointer to Previous Message Object PPREV holds the message object number of the previous message object in a message list structure PNEXT Pointer to Next Message Object PNEXT holds the message object number of the next message object in a message list structure Table 15 12 MOSTATn Reset Values Message Object Reset Value User s Manual 15 83 V1 1 2007 05 MultiCAN V1 0 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller The Message Object Interrupt Pointer Register MOIPRn holds the message interrupt pointers the message pending number and the frame counter value of message object n MOIPRn n 0 31 Message Object n Interrupt Pointer Reg
574. ure 14 10 Synchronization of T13 to T12 Figure 14 10 shows the synchronization of T13 to a 112 event The selected event in this example is a compare match compare value 2 while counting up The clocks of T12 and T13 can be different use other prescaler factor but in this example T12CLK is shown as equal to T13CLK for the sake of simplicity User s Manual 14 14 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 1 3 Modulation Control The modulation control part combines the different modulation sources CC6x_T12_0 and COUT6x T12 oare the output signals that are configured with CC6xPS COUT6xPS MOD_1T13_0 is the output signal after T13 Inverted Modulation T13IM Each modulation source can be individually enabled per output line Furthermore the trap functionality is taken into account to disable the modulation of the corresponding output line during the trap state if enabled T12MODENx tt CC6x T12 o COUT6x T12 o O passive state T13MODENx 1 active state MOD_1T13_0 to output MCMEN pin CC6x COUT6x MCMPx TRPENx TRPS 1 x for each T12 related output CCU6_mod_ctr Figure 14 11 Modulation Control of T12 related Outputs For each of the six T12 related output lines represented by x in the Figure 14 11 e T12MODENx enables the modulation by a PWM pattern generated by timer T12 e T13MODENx enables the modulation by a PWM pattern generated by timer T13 e MCMPx c
575. uto reload mode 16 bit timer for baud rate measurement The PC host sends test byte 80 to start the synchronization flow The timer is started on reception of the start bit 0 and stopped on reception of the last bit of the test byte 1 Then the UART BSL routine calculates the actual baud rate sets the PRE and BG values and activates Baud Rate Generator When the synchronization is done the microcontroller sends back the Acknowledge byte 55 to the host The baud rate supported ranges from 1200 Baud to 19200 Baud If the synchronization fails the Acknowledge code from the microcontroller cannot be received correctly by the host In this case on the host side the host software may display a message to the user e g requesting the user to repeat the synchronization procedure see Section 18 1 1 3 for Response code On the microcontroller side the UART BSL routine cannot determine whether the synchronization is correct or not It always enters Phase II after sending the acknowledge byte Therefore if synchronization fails a reset of the microcontroller has to be invoked to restart the microcontroller for a new synchronization attempt User s Manual 18 8 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader 18 1 2 1 Communication Structure There are two types of transfer flow of the Header Block Data Block EOT Block and the Response Code as shown in Figure 18 1 One is adopted by Mode 0 and Mo
576. valid 1 Message object n is valid Only a valid message object takes part in CAN transfers User s Manual 15 80 V1 1 2007 05 MultiCAN V1 0 Cinfineon Field l T User s Manual MultiCAN V1 0 XC886 888CLM Controller Area Network MultiCAN Controller Description Receive Transmit Selected 0 Message object n is not selected for receive or transmit operation 1 Message object n is selected for receive or transmit operation Frame Reception RTSEL is set by hardware when message object n has been identified for storage of a CAN frame that is currently received Before a received frame becomes finally stored in message object n a check is performed to determine if RTSEL is set Thus the CPU can suppress a scheduled frame delivery to this message object n by clearing RTSEL by software Frame Transmission RTSEL is set by hardware when message object n has been identified to be transmitted next It is checked that RTSEL is still set before message object n is actually set up for transmission and bit NEWDAT is cleared Itis also checked that RTSEL is still set before its message object n is verified due to the successful transmission of a frame RTSEL needs to be checked only when the context of message object n changes and interference with an ongoing frame transfer will be avoided In all other cases RTSEL can be ignored RTSEL has no impact on message acceptance filtering RTSEL is not cleared by hardware
577. ve AND active active e active AND passive passive e passive AND passive passive The compare states change with the detected compare matches and are indicated by the CC6xST bits The compare states of T12 are defined as follows e passive if the counter value is below the compare value e active if the counter value is above the compare value This leads to the following switching rules for the compare states e set to the active state when the counter value reaches the compare value while counting up e reset to the passive state when the counter value reaches the compare value while counting down e reset to the passive state in case of a zero match without compare match while counting up e set to the active state in case of a zero match with a parallel compare match while counting up T12cIk compare match EEN compare active passive State CCU6_1T12_center_cm2 Figure 14 3 Compared States for Compare Value 2 User s Manual 14 5 V1 1 2007 05 CCU6B V 1 0 Cinfine on XC886 888CLM Capture Compare Unit 6 The switching rules are considered only while the timer is running As a result write actions to the timer registers while the timer is stopped do not lead to compare actions 14 1 1 4 Compare Mode of T12 In compare mode the registers CC6xR x 0 2 are the actual compare registers for T12 The values stored in CC6xR are compared all three channels in parallel to the counter value of T12
578. ve pull value Px DATA Port x Data Register 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n rw Port x Pin n Data Value n 0 7 0 Port x Pin n data value 0 1 Port x Pin n data value 1 Bit Px_DATA n can only be written if the corresponding pin is set to output Px_DIR n 1 and cannot be written if the corresponding pin is set to input Px_DIR n 0 The content of Px_DATA n is output on the assigned pin if the pin is assigned as GPIO pin and the direction is switched set to output A read operation of Px_DATA returns the register value and not the state of the corresponding Px_DATA pin User s Manual 6 6 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 1 1 2 Direction Register The direction of bidirectional port pins is controlled by the respective direction register Px_DIR For input only port pins register Px_ DIR is used to enable or disable the input drivers Px DIR Port x Direction Register 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Field Description Pn Bidirectional Port x Pin n Direction Control n 0 7 0 Direction is set to input 1 Direction is set to output or Input only Port x Pin n Driver Control 0 Input driver is enabled 1 Input driver is disabled User s Manual 6 7 V1 1 2007 05 Parallel Ports V 1 0 Cinfin eon XC886 888CLM Parallel Ports 6 1 1 3 Open Drain Control Register Each pin in output mode can be switched to ope
579. vent x has occurred 0 3 2 r Reserved Returns 0 if read should be written with 0 Writing a 1 to a bit position in register EVINCR clears the corresponding event interrupt flag in register EVINFR If a hardware event triggers the setting of a bit EVINFx and EVINCx 1 the bit EVINFx is cleared software overrules hardware EVINCR Event Interrupt Clear Flag Register CF Reset Value 00 7 6 5 4 3 2 1 0 mer me ems es 6 me eee W W W W r W W Field Bits Type Description EVINCx W Clear Interrupt Flag for Event x x 0 1 4 7 0s No action 1g Bit EVINFR x is reset 0 3 2 r Reserved Returns 0 if read should be written with 0 User s Manual 16 61 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Writing a 1 to a bit position in register EVINSR sets the corresponding event interrupt flag in register EVINFR and generates an interrupt pulse if the interrupt is enabled EVINSR Event Interrupt Set Flag Register D2 Reset Value 00 7 6 5 4 3 2 1 0 mes emes 6 on W W W W r W W Field Bits Type Description EVINSx W Set Interrupt Flag for Event x x 0 1 4 7 On No action 1 Bit EVINFR x is set 0 3 2 r Reserved Returns 0 if read should be written with 0 The bits in register EVINPR define the service request output line SRx x O or 1 that is activated if an event interrupt is generated EVINPR Event Interrupt Node Pointer Register D3 Reset Value 00
580. verter Register QORO contains bits that monitor the status of the current sequential request QORO Queue 0 Register 0 CF Reset Value 00 7 6 5 4 3 2 1 0 rh rh rh rh r rh Field Bits Type Description REQCHNR 2 0 rh Request Channel Number This bit field indicates the channel number that will 4 rh be or is currently requested Request Channel Number Valid This bit indicates if the data in REQCHNR RF ENSI and EXTR is valid Bit V is set when a valid entry is written to the queue input register QINRO or by an update by intermediate queue registers O The data is not valid 1 The data is valid RF 5 rh Refill This bit indicates if the pending request is discarded after being executed conversion start or if it is automatically refilled in the top position of the request queue Os The request is discarded after conversion start 1p The request is refilled in the queue after conversion start ENSI rh Enable Source Interrupt This bit indicates if a source interrupt will be generated when the conversion is completed The interrupt trigger becomes activated if the conversion requested by the source has been completed and ENSI 1 O The source interrupt generation is disabled 1 The source interrupt generation is enabled User s Manual 16 45 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter Field Description EXTR Ci External Trigger This bit defines if the convers
581. vice or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered XC886 888CLM 8 Bit Single Chip Microcontroller Cinfineon Never stop thinking XC886 888 Revision History 2007 05 V1 1 Previous Version V0 1 V0 2 V0 3 V1 0 Page Subjects major changes since last revision Changes from V1 0 2006 12 to V1 1 2007 04 1 17 3 19 2 5 3 21 4 1 4 4 4 16 4 21 7 12 8 3 8 4 12 28 12 40 14 85 14 87 15 75 Footnote is added for MBC pin NC pin numbers and description of Vbpp Vssp pins are updated Section on bit protection scheme is updated Bit DPSEL in EO register is renamed DPSELO New bullet point on Flash delivery state is added to the feature list Section on sector partitioning is expanded to include more details Stack size required by the user subroutines are updated Sections on loss of lock operation loss of lock recovery and select external oscillator are updated Descriptions on the use of Internal pulls to bring ports into a defined state in power down mode is added Wording on the number of RXD inputs is corrected Section on automatic synchronization to host is updated Reload values in Table 12 6 are corrected References made to bits of IS register are corrected The wording reserv
582. w Byte Reset Value 00 User s Manual 11 19 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfin eon XC886 888CLM CORDIC Coprocessor Field Bits Type Description DATAL 7 0 rw Low Byte Data Write to this byte always writes to the low byte of the corresponding shadow data register New data may be written during an ongoing CORDIC calculation For read DMAP 0 Result data from kernel data byte DMAP 1 Initial data from the shadow data byte CD_CORDxH x X Y or Z CORDIC x Data High Byte Reset Value 00 Field Bits Type Description DATAH 7 0 rw High Byte Data Write to this byte always writes to the high byte of the corresponding shadow data register New data may be written during an ongoing CORDIC calculation For read DMAP 0 Result data from kernel data byte DMAP 1 Initial data from the shadow data byte User s Manual 11 20 V1 1 2007 05 CORDIC Coprocessor V 1 2 1 Cinfin eon XC886 888CLM Serial Interfaces 12 Serial Interfaces The XC886 888 contains three serial interfaces which consists of two Universal Asynchronous Receivers Transmitters UART and UART1 and a High Speed synchronous Serial Interface SSC for serial communication with external devices Additionally the UART module can be used to support the Local Interconnect Network LIN protocol UART and UART1 Features e Full duplex asynchronous modes 8 bit or 9 bit data frames LSB first fixed or variable baud rate e Receive buffered
583. which delays the passive to active edge of the switching signals the active to passive edge is not delayed User s Manual 14 8 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 Center aligned Edge aligned CC6xST CC6xST DTCx_o Pin CC6x CC6xST AND DTCx o CC6xPS 0 PSL 0 Pin COUT6x COUT6xPS 1 CC6xST AND DTCx_o PSL 0 Figure 14 6 PWM signals with Dead time Generation Register T12DTC controls the dead time generation for the timer T12 compare channels Each channel can be independently enabled disabled for dead time generation by bit DTEx If enabled the transition from passive state to active state is delayed by the value defined by bit field DTM 8 bit down counter clocked with T12CLKk The dead time counter can only be reloaded when it is zero Each of the three channels works independenily with its own dead time counter trigger and enable signals The value of bit field DIM is valid for all three channels 14 1 1 7 Capture Mode In capture mode the bits CC6xST indicate the occurrence of the selected capture event according to the bit fields MSEL6x e MSEL6x 01XXg double register capture mode see Table 14 5 e MSEL6x 101X or 11XX multi input capture modes see Table 14 7 A rising and or a falling edge on the pins CC6x or CCPOSx can be selected as the capture event that is used to transfer the contents of timer T12 to the CC6xR and User s Manu
584. wing sections are referenced in other chapters of this document with the module name prefix CCU6_ e g CCU6_ CC63SRL The addresses non mapped of the kernel SFRs are listed in Table 14 3 Table 14 3 SFR Address List for Pages 0 3 FE CC62SRL FF CC62SRH CC62RL CC62RH TRPCTRL CMPSTATL TRPCTRH CMPSTATH cossa coser TRPOTRL cosesRH co62RH_ TRPOTRH_ User s Manual 14 32 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 CCU6_ PAGE Page Register for CCU6 Reset Value 00 7 6 5 4 3 2 1 0 a e e W W r rw Field Description PAGE Lm 0 Page Bits When written the value indicates the new page address When read the value indicates the currently active page addr y x 1 STNR 5 4 Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP If OP 10 the contents of PAGE are saved in STx before being overwritten with the new value If OP 11 the contents of PAGE are overwritten by the contents of STx The value written to the bit positions of PAGE is ignored 00 STO is selected 01 ST1 is selected 10 ST2 is selected 11 ST3 is selected User s Manual 14 33 V1 1 2007 05 CCU6B V 1 0 Cinfineon Field OP User s Manual CCU6B V 1 0 XC886 888CLM Capture Compare Unit 6 Bits Type Description Operation 0X 10 11 Manual page mode The value of STNR is ignored and PAGE is directl
585. with a higher priority has been found The new conversion is started as soon as possible after the abort action The aborted conversion request is restored in the request source that has requested the aborted conversion As a result it takes part in the next arbitration round The priority of an active request source including pending or active conversion must not be changed by software The abort will not be accepted during the last 3 clock cycles of a running conversion Refer to Section 16 7 2 for register description relating to conversion start control 16 4 3 Channel Control Each channel has its own control information that defines the target result register for the conversion result see Section 16 7 4 The only control information that is common to all channels is the sampling time defined by the input class register See Section 16 7 5 User s Manual 16 10 V1 1 2007 05 ADC V 1 0 Cinfin eon XC886 888CLM Analog to Digital Converter 16 4 4 Sequential Request Source A sequential request source requests one conversion after the other The amount of channels requested for conversion depends on the length of the sequential buffer queue number of queue stages The sequential source register description can be found in Section 16 7 6 16 4 4 1 Overview The sequential request source at arbitration slot O requests one conversion after another for channel numbers between 0 and 7 The queue stage stores the requested channel
586. wo defined modes of handling incoming interrupt events All qualified flags of the 7 interrupt node Corresponding Jf interrupt event status cine flag gt from core Event interrupt request pending interrupt request IL Ricans set clear Event MODE occurrence ll a Corresponding event interrupt interrupt node L gt tocore enable bit enable bit Implemented as latch cannot set by software Figure 5 8 Interrupt Structure 2 If IMODE 1 an event generated by its corresponding interrupt source will set the status flag and in parallel if the event is enabled for interrupt generate a pending interrupt request to the core If IMODE 0 an event will set the status flag but the pending interrupt request is generated only if the event is enabled for interrupt and the interrupt node is enabled An active pending interrupt request interrupts the core and is automatically cleared by hardware the core once the interrupt node is serviced interrupt acknowledged the status flag remains set and must be cleared by software A pending interrupt request can also be cleared by software the method differs depending on the IMODE bit setting If IMODE 1 only on clearing all interrupt enabled status flags of the node will indirectly clear its pending interrupt request Note that this is not exactly like interrupt st
587. write 0 Writing 1 has no effect List Object Error 0 No List Object Error since last most recent flag reset 1 A List Object Error has been detected during message acceptance filtering A message object with wrong LIST index entry in the Message Object Control Register has been detected LOE must be reset by software write 0 Writing 1 has no effect 15 64 V1 1 2007 05 Cinfin eon XC886 888CLM Controller Area Network MultiCAN Controller Field Description 0 10 Reserved Read as 0 should be written with 0 Encoding of the LEC Bit Field Table 15 8 Encoding of the LEC Bit Field LEC Value Signification 000 No Error No error was detected for the last most recent message on the CAN bus 001 Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed 010 Form Error A fixed format part of a received frame has the wrong format O11 Ack Error The transmitted message was not acknowledged by another node 100 Biti Error During a message transmission the CAN node tried to send a recessive level 1 outside the arbitration field and the acknowledge slot but the monitored bus value was dominant 101 BitO Error Two different conditions are signaled by this code 1 During transmission of a message or acknowledge bit active error flag overload flag the CAN node tried to send a dominant level 0 but the monitored bus value was re
588. xR MCC6xS 0 0 Bit CC6xST is not changed 0 1 Bit CC6xST is set 1 0 Bit CC6xST is reset 1 1 Reserved toggle 0 Sor IT Reserved Returns 0 if read should be written with 0 User s Manual 14 57 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 CMPMODIFH Compare State Modification Register High Reset Value 00 7 6 5 4 3 2 1 0 0 MCC MCC MCC MCC 63R 62R 61R 60R r W r W W W Field Bits Type Description MCC6xR 0 1 iw Capture Compare Status Modification Bits Reset x 0 1 2 3 2 6 These bits are used to reset the corresponding CC6xST bits by software This feature allows the user to individually change the Status of the output lines by software e g when the corresponding compare timer is stopped This allows a bit manipulation of CC6xST bits by a single data write action The following functionality of a write access to bits concerning the same capture compare state bit is provided MCC 6xR MCC6xS 0 0 Bit CC6xST is not changed 0 1 Bit CC6xST is set 1 0 Bit CC6xST is reset 1 1 Reserved toggle 0 Sor I1 Reserved Returns 0 if read should be written with 0 Register TCTRO controls the basic functionality of both timers T12 and 113 User s Manual 14 58 V1 1 2007 05 CCU6B V 1 0 Cinfin eon XC886 888CLM Capture Compare Unit 6 TCTROL Timer Control Register 0 Low Reset Value 00 7 6 5 4 3 2 1 0 om om oes vn pe PRE rw rh rh rh rw rw Field Description T1
589. xX OO O2 XX XX XX XX O1 Checksum 1 byte Slave Response Header gt SYN Break SYN Protected At least Char ID 13 bits 554 7D low eee Cn eee Response lt gt 8 Data bytes for Command NAD Response ACK not used Checksum 1 byte XX 55 00 00 00 00 00 OO Xs Fast LIN BSL lt lt lt lt lt lt lt lt lt lt lt lt lt lt BSL UART protocol Phase II gt gt gt gt gt gt gt gt gt gt gt gt Figure 18 5 Fast LIN BSL Frames 18 1 3 10 After Reset Conditions When one or more parameters of the transfer block are invalid different procedures are carried out This also depends on whether the invalid frame is a first frame to be received Table 18 6 list the different scenarios in relation to the first frame Protected ID Checksum LIN or Programming block type and modes User s Manual 18 24 V1 1 2007 05 Bootstrap Loader V1 0 Cinfine on XC886 888CLM Bootstrap Loader Table 18 6 LIN BSL After Reset Conditions First Check Block Action Frame sum Type Header only Yes Invalid Dont Don t Don t Dont Save LIN message to XRAM and care care care care jump to Flash 0000 No Invalid Dont Dont Don t Dont Message is ignored Wait for next care care care care frame Yes N A N A N A N A Save LIN message to XRAM and jump to Flash 0000 No N A N A Reply if there is a previous valid
590. y be configured and run independently from the other CAN nodes Each CAN node is equipped with an individual set of SFR registers to control and to monitor the CAN node Note In the following descriptions index x stands for the node number and index n represents the message object number 15 1 3 1 Bit Timing Unit According to the ISO 11898 standard a CAN bit time is subdivided into different segments Figure 15 4 Each segment consists of multiples of a time quantum The magnitude of f is adjusted by bit fields NBTRx BRP and NBTRx DIV8 both controlling the baud rate prescaler The baud rate prescaler is driven by the module clock fean 1 Bit Time 1 Time Quantum f Sample Point Transmit Point MCT04518 Figure 15 4 CAN Bus Bit Timing Standard The synchronization Segment Tsync allows a phase synchronization between transmitter and receiver time base The Synchronization Segment length is always one t The Propagation Time Segment Tp takes into account the physical propagation delay in the transmitter output driver on the CAN bus line and in the transceiver circuit For a working collision detection mechanism T prop Must be two times the sum of all propagation delay quantities rounded up to a multiple of t The phase buffer segments 1 and 2 T Tp2 before and after the signal sample point are used to compensate for a mismatch between transmitter and receiver clock phases detected in the synchronizatio
591. y level of each interrupt vector The first pair of Interrupt Priority Registers are SFRs IP and IPH The second pair of Interrupt Priority Registers are SFRs IP1 and IPH1 The corresponding bits in each pair of Interrupt Priority Registers select one of the four priority levels shown in Table 5 3 Table 5 3 Interrupt Priority Level Selection IPH x IPH1 x IP x IP1 x Priority Level 0 Level O lowest Level 1 0 Ao 1 A Level 3 highest Note NMI always has the highest priority above Level 3 it does not use the level selection shown in Table 5 3 IP Interrupt Priority Register Reset Value 00 7 6 5 4 3 2 1 0 a a aa a a A a A r rw rw rw rw rw rw Field Bits Type Description PXO o rw___ Priority Level Low Bit for Interrupt Node XINTRO PTO Priority Level Low Bit for Interrupt Node XINTR1 PX1 2 rw___ Priority Level Low Bit for Interrupt Node XINTR2 Q PT1 3 Jw Priority Level Low Bit for Interrupt Node XINTR3 PS wo Priority Level Low Bit for Interrupt Node XINTR4 PT2 C Priority Level Low Bit for Interrupt Node XINTR5 0 6 Reserved Returns 0 if read should be written with 0 User s Manual 5 32 V1 1 2007 05 Interrupt System V 1 0 TTT T Cinfin eon XC886 888CLM Interrupt System IPH Interrupt Priority High Register Reset Value 00 7 6 5 4 3 2 1 0 0 PT2H oH PT1H PX1H PTOH PX0OH r rw rw rw rw rw rw Field Bits Type Description PXOH o rw___ Priority Level Hi
592. y to detect the baud rate within LIN protocol using Timer 2 This allows the UART module to be synchronized to the LIN baud rate for data transmission and reception 12 2 1 LIN Protocol LIN is a holistic communication concept for local interconnected networks in vehicles The communication is based on the SCI UART data format a single master multiple Slave concept a clock synchronization for nodes without stabilized time base An attractive feature of LIN is self synchronization of the slave nodes without a crystal or ceramic resonator which significantly reduces the cost of hardware platform Hence the baud rate must be calculated and returned with every message frame The structure of a LIN frame is shown in Figure 12 6 The frame consists of the e header which comprises a Break 13 bit time low Synch Byte 55 and ID field e response time e data bytes according to UART protocol e checksum Frame slot Response Space Response Synch Protected Data 1 Data2 DataN Checksum identifier Figure 12 6 The Structure of LIN Frame Each byte field is transmitted as a serial byte as shown in Figure 12 7 The LSB of the data is sent first and the MSB is sent last The start bit is encoded as a bit with value zero dominant and the stop bit is encoded as a bit with value one recessive User s Manual 12 26 V1 1 2007 05 Serial Interfaces V 1 0 Cinfin eon XC886 888CLM Serial Interfaces Byte field Figure 12 7
593. y written New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR Automatic restore page action The value written to the bit positions PAGE is ignored and instead PAGE is overwritten by the contents of the storage bit field STx indicated by STNR Reserved Returns 0 if read should be written with 0 14 34 V1 1 2007 05 Cinfin eon XC886 888CLM Capture Compare Unit 6 14 3 Register Description Table 14 4 shows all registers associated with the CCU6 module For all CCU6 registers the write only bit positions indicated by w always deliver the value of 0 when they are read out If a hardware and a software request to modify a bit occur simultaneously the software wins Table 14 4 Registers Overview Short Name see System Registers Timer T12 Registers Low High CC6x Low CC6x High Timer T13 Registers Low User s Manual 14 35 V1 1 2007 05 CCU6 V 1 0 Cinfineon XC886 888CLM Capture Compare Unit 6 Table 14 4 Registers Overview cont d Short Name see High CC63 Low CC63 High CCU6 Control Registers Modulation Control Registers MCMOUTSL Multi_ Channel Mode Output Shadow Register Page 14 73 Low MCMOUTSH Multi_Channel Mode Output Shadow Register Page 14 74 High User s Manual 14 36 V1 1 2007 05 CCU6 V 1 0 Cinfin eon XC886 888CLM Capture

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